From baldrick at free.fr  Mon Sep  5 01:52:49 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 05 Sep 2011 06:52:49 -0000
Subject: [llvm-commits] [llvm] r139113 - in /llvm/trunk:
 include/llvm/Analysis/ConstantFolding.h
 include/llvm/Analysis/InstructionSimplify.h
 lib/Analysis/InstructionSimplify.cpp
 test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
Message-ID: <20110905065249.103B72A6C12C@llvm.org>

Author: baldrick
Date: Mon Sep  5 01:52:48 2011
New Revision: 139113

URL: http://llvm.org/viewvc/llvm-project?rev=139113&view=rev
Log:
Add some simple insertvalue simplifications, for the purpose of cleaning
up do-nothing exception handling code produced by dragonegg.

Added:
    llvm/trunk/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
Modified:
    llvm/trunk/include/llvm/Analysis/ConstantFolding.h
    llvm/trunk/include/llvm/Analysis/InstructionSimplify.h
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp

Modified: llvm/trunk/include/llvm/Analysis/ConstantFolding.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ConstantFolding.h?rev=139113&r1=139112&r2=139113&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/ConstantFolding.h (original)
+++ llvm/trunk/include/llvm/Analysis/ConstantFolding.h Mon Sep  5 01:52:48 2011
@@ -61,6 +61,12 @@
                                           Constant *LHS, Constant *RHS,
                                           const TargetData *TD = 0);
 
+/// ConstantFoldInsertValueInstruction - Attempt to constant fold an insertvalue
+/// instruction with the specified operands and indices.  The constant result is
+/// returned if successful; if not, null is returned.
+Constant *ConstantFoldInsertValueInstruction(Constant *Agg, Constant *Val,
+                                             ArrayRef<unsigned> Idxs);
+
 /// ConstantFoldLoadFromConstPtr - Return the value that a load from C would
 /// produce if it is constant and determinable.  If this is not determinable,
 /// return null.

Modified: llvm/trunk/include/llvm/Analysis/InstructionSimplify.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/InstructionSimplify.h?rev=139113&r1=139112&r2=139113&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/InstructionSimplify.h (original)
+++ llvm/trunk/include/llvm/Analysis/InstructionSimplify.h Mon Sep  5 01:52:48 2011
@@ -126,6 +126,13 @@
   Value *SimplifyGEPInst(ArrayRef<Value *> Ops,
                          const TargetData *TD = 0, const DominatorTree *DT = 0);
 
+  /// SimplifyInsertValueInst - Given operands for an InsertValueInst, see if we
+  /// can fold the result.  If not, this returns null.
+  Value *SimplifyInsertValueInst(Value *Agg, Value *Val,
+                                 ArrayRef<unsigned> Idxs,
+                                 const TargetData *TD = 0,
+                                 const DominatorTree *DT = 0);
+
   //=== Helper functions for higher up the class hierarchy.
 
 

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=139113&r1=139112&r2=139113&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Mon Sep  5 01:52:48 2011
@@ -2270,6 +2270,35 @@
   return ConstantExpr::getGetElementPtr(cast<Constant>(Ops[0]), Ops.slice(1));
 }
 
+/// SimplifyInsertValueInst - Given operands for an InsertValueInst, see if we
+/// can fold the result.  If not, this returns null.
+Value *llvm::SimplifyInsertValueInst(Value *Agg, Value *Val,
+                                     ArrayRef<unsigned> Idxs,
+                                     const TargetData *,
+                                     const DominatorTree *) {
+  if (Constant *CAgg = dyn_cast<Constant>(Agg))
+    if (Constant *CVal = dyn_cast<Constant>(Val))
+      return ConstantFoldInsertValueInstruction(CAgg, CVal, Idxs);
+
+  // insertvalue x, undef, n -> x
+  if (match(Val, m_Undef()))
+    return Agg;
+
+  // insertvalue x, (extractvalue y, n), n
+  if (ExtractValueInst *EV = dyn_cast<ExtractValueInst>(Val))
+    if (EV->getIndices() == Idxs) {
+      // insertvalue undef, (extractvalue y, n), n -> y
+      if (match(Agg, m_Undef()))
+        return EV->getAggregateOperand();
+
+      // insertvalue y, (extractvalue y, n), n -> y
+      if (Agg == EV->getAggregateOperand())
+        return Agg;
+    }
+
+  return 0;
+}
+
 /// SimplifyPHINode - See if we can fold the given phi.  If not, returns null.
 static Value *SimplifyPHINode(PHINode *PN, const DominatorTree *DT) {
   // If all of the PHI's incoming values are the same then replace the PHI node
@@ -2471,6 +2500,13 @@
     Result = SimplifyGEPInst(Ops, TD, DT);
     break;
   }
+  case Instruction::InsertValue: {
+    InsertValueInst *IV = cast<InsertValueInst>(I);
+    Result = SimplifyInsertValueInst(IV->getAggregateOperand(),
+                                     IV->getInsertedValueOperand(),
+                                     IV->getIndices(), TD, DT);
+    break;
+  }
   case Instruction::PHI:
     Result = SimplifyPHINode(cast<PHINode>(I), DT);
     break;

Added: llvm/trunk/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll?rev=139113&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll (added)
+++ llvm/trunk/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll Mon Sep  5 01:52:48 2011
@@ -0,0 +1,22 @@
+; RUN: opt < %s -instsimplify -S | FileCheck %s
+
+; CHECK-NOT: extractvalue
+; CHECK-NOT: insertvalue
+
+declare void @bar()
+
+define void @foo() {
+entry:
+  invoke void @bar() to label %cont unwind label %lpad
+cont:
+  ret void
+lpad:
+  %ex = landingpad { i8*, i32 } personality i32 (i32, i64, i8*, i8*)* @__gxx_personality_v0 cleanup
+  %exc_ptr = extractvalue { i8*, i32 } %ex, 0
+  %filter = extractvalue { i8*, i32 } %ex, 1
+  %exc_ptr2 = insertvalue { i8*, i32 } undef, i8* %exc_ptr, 0
+  %filter2 = insertvalue { i8*, i32 } %exc_ptr2, i32 %filter, 1
+  resume { i8*, i32 } %filter2
+}
+
+declare i32 @__gxx_personality_v0(i32, i64, i8*, i8*)



From baldrick at free.fr  Mon Sep  5 07:57:58 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 05 Sep 2011 12:57:58 -0000
Subject: [llvm-commits] [llvm] r139117 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll
Message-ID: <20110905125758.26B812A6C12C@llvm.org>

Author: baldrick
Date: Mon Sep  5 07:57:57 2011
New Revision: 139117

URL: http://llvm.org/viewvc/llvm-project?rev=139117&view=rev
Log:
Delete trivial landing pads that just continue unwinding the caught
exception.

Added:
    llvm/trunk/test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll
Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=139117&r1=139116&r2=139117&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Sep  5 07:57:57 2011
@@ -63,6 +63,7 @@
   bool FoldValueComparisonIntoPredecessors(TerminatorInst *TI,
                                            IRBuilder<> &Builder);
 
+  bool SimplifyResume(ResumeInst *RI, IRBuilder<> &Builder);
   bool SimplifyReturn(ReturnInst *RI, IRBuilder<> &Builder);
   bool SimplifyUnwind(UnwindInst *UI, IRBuilder<> &Builder);
   bool SimplifyUnreachable(UnreachableInst *UI);
@@ -2138,6 +2139,52 @@
   return true;
 }
 
+bool SimplifyCFGOpt::SimplifyResume(ResumeInst *RI, IRBuilder<> &Builder) {
+  // If this is a trivial landing pad that just continues unwinding the caught
+  // exception then zap the landing pad, turning its invokes into calls.
+  BasicBlock *BB = RI->getParent();
+  LandingPadInst *LPInst = dyn_cast<LandingPadInst>(BB->getFirstNonPHI());
+  if (RI->getValue() != LPInst)
+    // Not a landing pad, or the resume is not unwinding the exception that
+    // caused control to branch here.
+    return false;
+
+  // Check that there are no other instructions except for debug intrinsics.
+  BasicBlock::iterator I = LPInst, E = RI;
+  while (++I != E)
+    if (!isa<DbgInfoIntrinsic>(I))
+      return false;
+
+  // Turn all invokes that unwind here into calls and delete the basic block.
+  for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE;) {
+    InvokeInst *II = cast<InvokeInst>((*PI++)->getTerminator());
+    SmallVector<Value*, 8> Args(II->op_begin(), II->op_end() - 3);
+    // Insert a call instruction before the invoke.
+    CallInst *Call = CallInst::Create(II->getCalledValue(), Args, "", II);
+    Call->takeName(II);
+    Call->setCallingConv(II->getCallingConv());
+    Call->setAttributes(II->getAttributes());
+    Call->setDebugLoc(II->getDebugLoc());
+
+    // Anything that used the value produced by the invoke instruction now uses
+    // the value produced by the call instruction.  Note that we do this even
+    // for void functions and calls with no uses so that the callgraph edge is
+    // updated.
+    II->replaceAllUsesWith(Call);
+    BB->removePredecessor(II->getParent());
+
+    // Insert a branch to the normal destination right before the invoke.
+    BranchInst::Create(II->getNormalDest(), II);
+
+    // Finally, delete the invoke instruction!
+    II->eraseFromParent();
+  }
+
+  // The landingpad is now unreachable.  Zap it.
+  BB->eraseFromParent();
+  return true;
+}
+
 bool SimplifyCFGOpt::SimplifyReturn(ReturnInst *RI, IRBuilder<> &Builder) {
   BasicBlock *BB = RI->getParent();
   if (!BB->getFirstNonPHIOrDbg()->isTerminator()) return false;
@@ -2836,6 +2883,8 @@
     } else {
       if (SimplifyCondBranch(BI, Builder)) return true;
     }
+  } else if (ResumeInst *RI = dyn_cast<ResumeInst>(BB->getTerminator())) {
+    if (SimplifyResume(RI, Builder)) return true;
   } else if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator())) {
     if (SimplifyReturn(RI, Builder)) return true;
   } else if (SwitchInst *SI = dyn_cast<SwitchInst>(BB->getTerminator())) {

Added: llvm/trunk/test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll?rev=139117&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll (added)
+++ llvm/trunk/test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll Mon Sep  5 07:57:57 2011
@@ -0,0 +1,22 @@
+; RUN: opt < %s -simplifycfg -S | FileCheck %s
+
+; CHECK-NOT: invoke
+; CHECK-NOT: landingpad
+
+declare void @bar()
+
+define i32 @foo() {
+entry:
+  invoke void @bar()
+          to label %return unwind label %lpad
+
+return:
+  ret i32 0
+
+lpad:
+  %lp = landingpad { i8*, i32 } personality i32 (i32, i64, i8*, i8*)* @__gxx_personality_v0
+          cleanup
+  resume { i8*, i32 } %lp
+}
+
+declare i32 @__gxx_personality_v0(i32, i64, i8*, i8*)



From renato.golin at arm.com  Mon Sep  5 10:38:34 2011
From: renato.golin at arm.com (Renato Golin)
Date: Mon, 05 Sep 2011 15:38:34 -0000
Subject: [llvm-commits] [www] r139118 -
	/www/trunk/devmtg/2011-09-16/index.html
Message-ID: <20110905153834.A1A072A6C12C@llvm.org>

Author: rengolin
Date: Mon Sep  5 10:38:34 2011
New Revision: 139118

URL: http://llvm.org/viewvc/llvm-project?rev=139118&view=rev
Log:
euro-llvm closed for registration

Modified:
    www/trunk/devmtg/2011-09-16/index.html

Modified: www/trunk/devmtg/2011-09-16/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-09-16/index.html?rev=139118&r1=139117&r2=139118&view=diff
==============================================================================
--- www/trunk/devmtg/2011-09-16/index.html (original)
+++ www/trunk/devmtg/2011-09-16/index.html Mon Sep  5 10:38:34 2011
@@ -42,9 +42,7 @@
 
 <div class="www_sectiontitle" id="registration">Registration:</div>
 
-<p>We're still accepting registration via email (Euro-LLVM at arm.com), free of charge. 
-Please, send your details (name, email, company/institution).
-Attendance will be limited to 60 people.</p>
+<p>We're already full, and won't be accepting registrations any more. Please let us know of your interests to join the European Meeting next year.</p>
 
 <p>If you need funding to attend the meeting, please tell us in your
 registration email (to Euro-LLVM at arm.com).</p>



From James.Molloy at arm.com  Mon Sep  5 13:00:32 2011
From: James.Molloy at arm.com (James Molloy)
Date: Mon, 5 Sep 2011 19:00:32 +0100
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and
	resolve	(safe) ambiguous instruction encodings
In-Reply-To: <005a01cc6986$58d21980$0a764c80$@molloy@arm.com>
References: <005a01cc6986$58d21980$0a764c80$@molloy@arm.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA473757133DD@GEORGE.Emea.Arm.com>

Ping?
________________________________________
From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of James Molloy [james.molloy at arm.com]
Sent: 02 September 2011 16:38
To: llvm-commits at cs.uiuc.edu
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve  (safe) ambiguous instruction encodings

Hi,

The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M series
not allowing the correct mask names.

The patch becomes difficult because:
  * There is no way to determine in the InstPrinter any subtarget specific
features (such as "operating on an m-class core?").
  * There is currently no subtarget feature for "M-class core?"; the nearest is
IsThumb2 && !HasARM.
  * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
a way that makes them deterministically separable. This causes non-conflicting
ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
both code paths are emitted but only one will ever be hit.

The solution is:
  * Add subtarget info to InstPrinter so it can determine what to do with the
mask immediate.
  * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
IsARClass == !IsMClass. This feature only has semantic sense on v6+
architectures.
  * The conflicts occur because the FixedLenDecoderEmitter does not honour the
Predicates field of instructions in the tablegen description. If the island
checking also checked the AssemblerPredicates field (if defined), ambiguous
instruction encodings that are disambiguated by predicates would (do) work fine.

The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and MCDisassembler.
They can use this (in patch #2) to determine what mask names to accept (primask?
or cpsr_zxvf?)

The second enhances FixedLenPredicateEncoder to emit predicate checks for
instructions before it accepts an encoding - this allows ambiguous instructions
to be disambiguated by the Predicates field in TableGen. This required changing
llvm-mc to accept -mattr, and tests to set the correct features they rely upon.

**As part of this, a bug in the MC was found in that ARM-mode STC2's were being
generated in Thumb2 mode (not the T2 encoding) and the test was checking for
this. The test has been disabled for the moment until a patch to add T2 STC/STC2
is created.**

The third patch adds a new predicate "IsMClass" along with its counterpart
"IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
encodings respectively. It also fixes mask printing for MRS/MSR in the
ARMMCInstPrinter and ARMMCAsmParser.

Testcases added with the final patch.

Comments? Is it OK?

Cheers,

James

[N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout myself
after review]

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.



From nicholas at mxc.ca  Mon Sep  5 13:14:00 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 05 Sep 2011 11:14:00 -0700
Subject: [llvm-commits] [llvm] r139009
	-	/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp
In-Reply-To: <20110902172628.D88A92A6C12C@llvm.org>
References: <20110902172628.D88A92A6C12C@llvm.org>
Message-ID: <4E651168.9090404@mxc.ca>

Andrew Trick wrote:
> Author: atrick
> Date: Fri Sep  2 12:26:28 2011
> New Revision: 139009
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139009&view=rev
> Log:
> Enable SCEV-based unrolling by default.
>
> This changes loop unrolling to use the same mechanism for trip count
> computation as indvars. This is a stronger check that tends to unroll
> more loops. A very common side-effect is that many single iteration
> loops will be removed sooner. The real goal was simply to remove
> dependence on canonical IVs.

Great!

> x86 is break even.
> ARM performance changes to expect (+ is good):
> External/SPEC/CFP2000/183.equake/183.equake +13%
> SingleSource/Benchmarks/Dhrystone/fldry     +21%
> MultiSource/Applications/spiff/spiff         +3%
> SingleSource/Benchmarks/Stanford/Puzzle     -14%
>
> The Puzzle regression is actually an improvement in loop optimization
> that defeats GVN: rdar://problem/10065079.

PR, please?

Nick

From benny.kra at googlemail.com  Mon Sep  5 13:16:19 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 05 Sep 2011 18:16:19 -0000
Subject: [llvm-commits] [llvm] r139120 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp
 test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
Message-ID: <20110905181619.7762C2A6C12C@llvm.org>

Author: d0k
Date: Mon Sep  5 13:16:19 2011
New Revision: 139120

URL: http://llvm.org/viewvc/llvm-project?rev=139120&view=rev
Log:
InstSimplify: Don't try to replace an extractvalue/insertvalue pair with the original value if types don't match.

Fixes clang selfhost.

Modified:
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp
    llvm/trunk/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=139120&r1=139119&r2=139120&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Mon Sep  5 13:16:19 2011
@@ -2286,7 +2286,8 @@
 
   // insertvalue x, (extractvalue y, n), n
   if (ExtractValueInst *EV = dyn_cast<ExtractValueInst>(Val))
-    if (EV->getIndices() == Idxs) {
+    if (EV->getAggregateOperand()->getType() == Agg->getType() &&
+        EV->getIndices() == Idxs) {
       // insertvalue undef, (extractvalue y, n), n -> y
       if (match(Agg, m_Undef()))
         return EV->getAggregateOperand();

Modified: llvm/trunk/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll?rev=139120&r1=139119&r2=139120&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll Mon Sep  5 13:16:19 2011
@@ -1,11 +1,8 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
-; CHECK-NOT: extractvalue
-; CHECK-NOT: insertvalue
-
 declare void @bar()
 
-define void @foo() {
+define void @test1() {
 entry:
   invoke void @bar() to label %cont unwind label %lpad
 cont:
@@ -17,6 +14,16 @@
   %exc_ptr2 = insertvalue { i8*, i32 } undef, i8* %exc_ptr, 0
   %filter2 = insertvalue { i8*, i32 } %exc_ptr2, i32 %filter, 1
   resume { i8*, i32 } %filter2
+; CHECK: @test1
+; CHECK-NOT: extractvalue
+; CHECK-NOT: insertvalue
 }
 
 declare i32 @__gxx_personality_v0(i32, i64, i8*, i8*)
+
+define { i8, i32 } @test2({ i8*, i32 } %x) {
+  %ex = extractvalue { i8*, i32 } %x, 1
+  %ins = insertvalue { i8, i32 } undef, i32 %ex, 1
+  ret { i8, i32 } %ins
+; CHECK: @test2
+}



From resistor at mac.com  Mon Sep  5 13:29:42 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 05 Sep 2011 11:29:42 -0700
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and	resolve
 (safe) ambiguous instruction encodings
In-Reply-To: <F01D8B85CFF58440B2A13965FBA90CA473757133DD@GEORGE.Emea.Arm.com>
References: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>
	<F01D8B85CFF58440B2A13965FBA90CA473757133DD@GEORGE.Emea.Arm.com>
Message-ID: <AF10579E-4931-410D-9B6E-F35C1248240F@mac.com>

I'm planning to look at this, but haven't had a chance yet.

--Owen

On Sep 5, 2011, at 11:00 AM, James Molloy wrote:

> Ping?
> ________________________________________
> From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of James Molloy [james.molloy at arm.com]
> Sent: 02 September 2011 16:38
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve  (safe) ambiguous instruction encodings
> 
> Hi,
> 
> The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M series
> not allowing the correct mask names.
> 
> The patch becomes difficult because:
>  * There is no way to determine in the InstPrinter any subtarget specific
> features (such as "operating on an m-class core?").
>  * There is currently no subtarget feature for "M-class core?"; the nearest is
> IsThumb2 && !HasARM.
>  * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
> a way that makes them deterministically separable. This causes non-conflicting
> ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
> both code paths are emitted but only one will ever be hit.
> 
> The solution is:
>  * Add subtarget info to InstPrinter so it can determine what to do with the
> mask immediate.
>  * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
> IsARClass == !IsMClass. This feature only has semantic sense on v6+
> architectures.
>  * The conflicts occur because the FixedLenDecoderEmitter does not honour the
> Predicates field of instructions in the tablegen description. If the island
> checking also checked the AssemblerPredicates field (if defined), ambiguous
> instruction encodings that are disambiguated by predicates would (do) work fine.
> 
> The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and MCDisassembler.
> They can use this (in patch #2) to determine what mask names to accept (primask?
> or cpsr_zxvf?)
> 
> The second enhances FixedLenPredicateEncoder to emit predicate checks for
> instructions before it accepts an encoding - this allows ambiguous instructions
> to be disambiguated by the Predicates field in TableGen. This required changing
> llvm-mc to accept -mattr, and tests to set the correct features they rely upon.
> 
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
> is created.**
> 
> The third patch adds a new predicate "IsMClass" along with its counterpart
> "IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
> Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
> encodings respectively. It also fixes mask printing for MRS/MSR in the
> ARMMCInstPrinter and ARMMCAsmParser.
> 
> Testcases added with the final patch.
> 
> Comments? Is it OK?
> 
> Cheers,
> 
> James
> 
> [N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout myself
> after review]
> 
> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From nicholas at mxc.ca  Mon Sep  5 13:35:03 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 05 Sep 2011 18:35:03 -0000
Subject: [llvm-commits] [llvm] r139122 -
	/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
Message-ID: <20110905183503.5BDE12A6C12C@llvm.org>

Author: nicholas
Date: Mon Sep  5 13:35:03 2011
New Revision: 139122

URL: http://llvm.org/viewvc/llvm-project?rev=139122&view=rev
Log:
Fix typo in comment.

Modified:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=139122&r1=139121&r2=139122&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Sep  5 13:35:03 2011
@@ -41,7 +41,7 @@
   unsigned Len = TT.size();
   unsigned Idx = 0;
 
-  // FIXME: Enahnce Triple helper class to extract ARM version.
+  // FIXME: Enhance Triple helper class to extract ARM version.
   bool isThumb = false;
   if (Len >= 5 && TT.substr(0, 4) == "armv")
     Idx = 4;



From nicholas at mxc.ca  Mon Sep  5 13:42:45 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 05 Sep 2011 11:42:45 -0700
Subject: [llvm-commits] [PATCH] Add Native Client Flags/Modes
In-Reply-To: <CAAU48JKe8gyLMD9sQu+=i-OCsc80v3GL39PEmSQ+JtNjLvwLLQ@mail.gmail.com>
References: <CAAU48JKe8gyLMD9sQu+=i-OCsc80v3GL39PEmSQ+JtNjLvwLLQ@mail.gmail.com>
Message-ID: <4E651825.3030702@mxc.ca>

David Meyer wrote:
> This patch adds the basic scaffolding needed to control code
> generation for the Native Client target, for X86 and ARM backends.

Very nice -- though I'd still like someone familiar with MC to look at 
it, I think this is straight-forward enough to commit now and wait for 
post-commit review.

One thing: I'd prefer '+nacl' over '+nacl-mode'. I see that the '-mode' 
suffix is used for thumb-mode and 64bit-mode but I don't like those 
either. :) Optional.

Nick

From nicholas at mxc.ca  Mon Sep  5 13:50:59 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 05 Sep 2011 18:50:59 -0000
Subject: [llvm-commits] [llvm] r139124 -
	/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
Message-ID: <20110905185059.958B42A6C12C@llvm.org>

Author: nicholas
Date: Mon Sep  5 13:50:59 2011
New Revision: 139124

URL: http://llvm.org/viewvc/llvm-project?rev=139124&view=rev
Log:
Update the C++ backend to use the new ArrayRef'ified APIs. Patch by arrowdodger!

Modified:
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=139124&r1=139123&r2=139124&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Sep  5 13:50:59 2011
@@ -1086,8 +1086,7 @@
         << getOpName(inv->getCalledFunction()) << ", "
         << getOpName(inv->getNormalDest()) << ", "
         << getOpName(inv->getUnwindDest()) << ", "
-        << iName << "_params.begin(), "
-        << iName << "_params.end(), \"";
+        << iName << "_params, \"";
     printEscapedString(inv->getName());
     Out << "\", " << bbname << ");";
     nl(Out) << iName << "->setCallingConv(";
@@ -1409,7 +1408,7 @@
     Out << "ExtractValueInst* " << getCppName(evi)
         << " = ExtractValueInst::Create(" << opNames[0]
         << ", "
-        << iName << "_indices.begin(), " << iName << "_indices.end(), \"";
+        << iName << "_indices, \"";
     printEscapedString(evi->getName());
     Out << "\", " << bbname << ");";
     break;
@@ -1426,7 +1425,7 @@
     Out << "InsertValueInst* " << getCppName(ivi)
         << " = InsertValueInst::Create(" << opNames[0]
         << ", " << opNames[1] << ", "
-        << iName << "_indices.begin(), " << iName << "_indices.end(), \"";
+        << iName << "_indices, \"";
     printEscapedString(ivi->getName());
     Out << "\", " << bbname << ");";
     break;



From nicholas at mxc.ca  Mon Sep  5 13:52:23 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 05 Sep 2011 11:52:23 -0700
Subject: [llvm-commits] [PATCH][CppBackend] Chase some LLVM API changes.
In-Reply-To: <CALH631naeXsq5MTciiDn5KdHNhekP=pGsAxXW_zgVOHWPOjjRg@mail.gmail.com>
References: <CALH631naeXsq5MTciiDn5KdHNhekP=pGsAxXW_zgVOHWPOjjRg@mail.gmail.com>
Message-ID: <4E651A67.2090702@mxc.ca>

arrowdodger wrote:
> Hello. This patch changes how std::vector's are passed to some
> *Inst::Create methods - now they are passed as ArrayRef's. I've tested
> it on code from demo page to make sure that generated bc's are equal.

Committed in r139124. Thanks for the patch!

Nick

From vadve at illinois.edu  Mon Sep  5 13:33:09 2011
From: vadve at illinois.edu (Vikram Adve)
Date: Mon, 05 Sep 2011 18:33:09 -0000
Subject: [llvm-commits] [www] r139121 - /www/trunk/Users.html
Message-ID: <20110905183309.BD3D52A6C12C@llvm.org>

Author: vadve
Date: Mon Sep  5 13:33:09 2011
New Revision: 139121

URL: http://llvm.org/viewvc/llvm-project?rev=139121&view=rev
Log:
Add two teaching users.

Modified:
    www/trunk/Users.html

Modified: www/trunk/Users.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/Users.html?rev=139121&r1=139120&r2=139121&view=diff
==============================================================================
--- www/trunk/Users.html (original)
+++ www/trunk/Users.html Mon Sep  5 13:33:09 2011
@@ -562,13 +562,13 @@
 
   <tr>
     <td>
-      <a href="http://www.cmu.edu/">Carnegie Mellon University</a>
+      <a href="http://www.ucla.edu/">University of California, Los Angeles</a>
     </td>
   </tr>
 
   <tr>
     <td>
-      <a href="http://www.ucla.edu/">University of California, Los Angeles</a>
+      <a href="http://www.cmu.edu/">Carnegie Mellon University</a>
     </td>
   </tr>
 
@@ -580,6 +580,18 @@
 
   <tr>
     <td>
+      <a href="http://www.cse.iitm.ac.in/">Indian Institute of Technology, Bombay</a>
+    </td>
+  </tr>
+
+  <tr>
+    <td>
+      <a href="http://www.cse.iitm.ac.in/">Indian Institute of Technology, Madras</a>
+    </td>
+  </tr>
+
+  <tr>
+    <td>
     <a href="http://www.unsw.edu.au/">University of New South Wales, Australia</a>
     </td>
   </tr>



From evan.cheng at apple.com  Mon Sep  5 16:52:31 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 05 Sep 2011 14:52:31 -0700
Subject: [llvm-commits] [llvm] r139028 - in /llvm/trunk:
 lib/Target/X86/Disassembler/X86Disassembler.cpp
 lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
 test/MC/Disassembler/X86/simple-tests.txt
In-Reply-To: <CAJdarcH2oP9GTszS2QxWGTmw9D7v4Ze8wj8MRsHU3fyn6QBLwQ@mail.gmail.com>
References: <20110902200123.B05252A6C12C@llvm.org>
	<CAJdarcH2oP9GTszS2QxWGTmw9D7v4Ze8wj8MRsHU3fyn6QBLwQ@mail.gmail.com>
Message-ID: <C43A6901-80B0-4EA9-B0D4-4E196E7CA7E0@apple.com>



On Sep 4, 2011, at 1:09 PM, Eli Friedman <eli.friedman at gmail.com> wrote:

> On Fri, Sep 2, 2011 at 1:01 PM, Kevin Enderby <enderby at apple.com> wrote:
>> Author: enderby
>> Date: Fri Sep  2 15:01:23 2011
>> New Revision: 139028
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=139028&view=rev
>> Log:
>> Change X86 disassembly to print immediates values as signed by default.  Special
>> case those instructions that the immediate is not sign-extend.  radr://8795217
>> 
>> Modified:
>>    llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
>>    llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
>>    llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
>> 
>> Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=139028&r1=139027&r2=139028&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Fri Sep  2 15:01:23 2011
>> @@ -28,6 +28,8 @@
>> 
>>  #define GET_REGINFO_ENUM
>>  #include "X86GenRegisterInfo.inc"
>> +#define GET_INSTRINFO_ENUM
>> +#include "X86GenInstrInfo.inc"
>>  #include "X86GenEDInfo.inc"
>> 
>>  using namespace llvm;
>> @@ -184,6 +186,38 @@
>>       break;
>>     }
>>   }
>> +  // By default sign-extend all X86 immediates based on their encoding.
>> +  else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
>> +           type == TYPE_IMM64) {
>> +    uint32_t Opcode = mcInst.getOpcode();
>> +    switch (operand.encoding) {
>> +    default:
>> +      break;
>> +    case ENCODING_IB:
>> +      // Special case those X86 instructions that use the imm8 as a set of
>> +      // bits, bit count, etc. and are not sign-extend.
>> +      if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
>> +         Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
>> +         Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
>> +         Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
>> +         Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
>> +         Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
>> +         Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
>> +         Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
>> +         Opcode != X86::VINSERTPSrr)
> 
> This can't possibly be the complete list of instructions with a
> non-extended immediate.  PCMPESTRI and friends, SHUFPS and friends,
> all shift instructions, and IN/OUT (plus possibly others I've missed)
> all take an imm8 which is clearly not signed.

It's also the wrong way to fix the bug. Kevin, can you add a new type to distinguish between extending and non-extending immediates?

Evan

> 
> -Eli
> 
>> +       type = TYPE_MOFFS8;
>> +      break;
>> +    case ENCODING_IW:
>> +      type = TYPE_MOFFS16;
>> +      break;
>> +    case ENCODING_ID:
>> +      type = TYPE_MOFFS32;
>> +      break;
>> +    case ENCODING_IO:
>> +      type = TYPE_MOFFS64;
>> +      break;
>> +    }
>> +  }
>> 
>>   switch (type) {
>>   case TYPE_MOFFS8:
>> 
>> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=139028&r1=139027&r2=139028&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Fri Sep  2 15:01:23 2011
>> @@ -90,7 +90,8 @@
>>   if (Op.isReg()) {
>>     O << '%' << getRegisterName(Op.getReg());
>>   } else if (Op.isImm()) {
>> -    O << '$' << Op.getImm();
>> +    // Print X86 immediates as signed values.
>> +    O << '$' << (int64_t)Op.getImm();
>> 
>>     if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
>>       *CommentStream << format("imm = 0x%llX\n", (long long)Op.getImm());
>> 
>> Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=139028&r1=139027&r2=139028&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
>> +++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Fri Sep  2 15:01:23 2011
>> @@ -102,3 +102,59 @@
>> 
>>  # CHECK: vmovapd %xmm0, %xmm2
>>  0xc5 0xf9 0x28 0xd0
>> +
>> +# Check X86 immediates print as signed values by default.  radr://8795217
>> +# CHECK: andq $-16, %rsp
>> +0x48 0x83 0xe4 0xf0
>> +
>> +# Check these special case instructions that the immediate is not sign-extend.
>> +# CHECK: blendps $129, %xmm2, %xmm1
>> +0x66 0x0f 0x3a 0x0c 0xca 0x81
>> +
>> +# CHECK: blendpd $129, %xmm2, %xmm1
>> +0x66 0x0f 0x3a 0x0d 0xca 0x81
>> +
>> +# CHECK: pblendw $129, %xmm2, %xmm1
>> +0x66 0x0f 0x3a 0x0e 0xca 0x81
>> +
>> +# CHECK: mpsadbw $129, %xmm2, %xmm1
>> +0x66 0x0f 0x3a 0x42 0xca 0x81
>> +
>> +# CHECK: dpps $129, %xmm2, %xmm1
>> +0x66 0x0f 0x3a 0x40 0xca 0x81
>> +
>> +# CHECK: dppd $129, %xmm2, %xmm1
>> +0x66 0x0f 0x3a 0x41 0xca 0x81
>> +
>> +# CHECK: insertps $129, %xmm2, %xmm1
>> +0x66 0x0f 0x3a 0x21 0xca 0x81
>> +
>> +# CHECK: vblendps $129, %ymm2, %ymm5, %ymm1
>> +0xc4 0xe3 0x55 0x0c 0xca 0x81
>> +
>> +# CHECK: vblendps $129, (%rax), %ymm5, %ymm1
>> +0xc4 0xe3 0x55 0x0c 0x08 0x81
>> +
>> +# CHECK: vblendpd $129, %ymm2, %ymm5, %ymm1
>> +0xc4 0xe3 0x55 0x0d 0xca 0x81
>> +
>> +# CHECK: vblendpd $129, (%rax), %ymm5, %ymm1
>> +0xc4 0xe3 0x55 0x0d 0x08 0x81
>> +
>> +# CHECK: vpblendw $129, %xmm2, %xmm5, %xmm1
>> +0xc4 0xe3 0x51 0x0e 0xca 0x81
>> +
>> +# CHECK: vmpsadbw $129, %xmm2, %xmm5, %xmm1
>> +0xc4 0xe3 0x51 0x42 0xca 0x81
>> +
>> +# CHECK: vdpps $129, %ymm2, %ymm5, %ymm1
>> +0xc4 0xe3 0x55 0x40 0xca 0x81
>> +
>> +# CHECK: vdpps $129, (%rax), %ymm5, %ymm1
>> +0xc4 0xe3 0x55 0x40 0x08 0x81
>> +
>> +# CHECK: vdppd $129, %xmm2, %xmm5, %xmm1
>> +0xc4 0xe3 0x51 0x41 0xca 0x81
>> +
>> +# CHECK: vinsertps $129, %xmm3, %xmm2, %xmm1
>> +0xc4 0xe3 0x69 0x21 0xcb 0x81
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

From nicholas at mxc.ca  Mon Sep  5 16:51:43 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 05 Sep 2011 21:51:43 -0000
Subject: [llvm-commits] [llvm] r139125 - in /llvm/trunk/lib/Target:
 ARM/ARM.td ARM/ARMInstrInfo.td ARM/ARMSubtarget.cpp ARM/ARMSubtarget.h
 ARM/MCTargetDesc/ARMMCTargetDesc.cpp X86/MCTargetDesc/X86MCTargetDesc.cpp
 X86/X86.td X86/X86InstrInfo.td X86/X86Subtarget.cpp X86/X86Subtarget.h
Message-ID: <20110905215143.A17032A6C12C@llvm.org>

Author: nicholas
Date: Mon Sep  5 16:51:43 2011
New Revision: 139125

URL: http://llvm.org/viewvc/llvm-project?rev=139125&view=rev
Log:
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!

Modified:
    llvm/trunk/lib/Target/ARM/ARM.td
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
    llvm/trunk/lib/Target/ARM/ARMSubtarget.h
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
    llvm/trunk/lib/Target/X86/X86.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
    llvm/trunk/lib/Target/X86/X86Subtarget.h

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=139125&r1=139124&r2=139125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Mon Sep  5 16:51:43 2011
@@ -23,6 +23,9 @@
 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
                                   "Thumb mode">;
 
+def ModeNaCl   : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
+                                  "Native client mode">;
+
 //===----------------------------------------------------------------------===//
 // ARM Subtarget features.
 //

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep  5 16:51:43 2011
@@ -209,6 +209,8 @@
                                  AssemblerPredicate<"!ModeThumb">;
 def IsDarwin         : Predicate<"Subtarget->isTargetDarwin()">;
 def IsNotDarwin      : Predicate<"!Subtarget->isTargetDarwin()">;
+def IsNaCl           : Predicate<"Subtarget->isTargetNaCl()">,
+                                 AssemblerPredicate<"ModeNaCl">;
 
 // FIXME: Eventually this will be just "hasV6T2Ops".
 def UseMovt          : Predicate<"Subtarget->useMovt()">;

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Sep  5 16:51:43 2011
@@ -53,6 +53,7 @@
   , HasVMLxForwarding(false)
   , SlowFPBrcc(false)
   , InThumbMode(false)
+  , InNaClMode(false)
   , HasThumb2(false)
   , NoARM(false)
   , PostRAScheduler(false)

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=139125&r1=139124&r2=139125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Sep  5 16:51:43 2011
@@ -70,6 +70,9 @@
   /// InThumbMode - True if compiling for Thumb, false for ARM.
   bool InThumbMode;
 
+  /// InNaClMode - True if targeting Native Client
+  bool InNaClMode;
+
   /// HasThumb2 - True if Thumb2 instructions are supported.
   bool HasThumb2;
 
@@ -209,6 +212,9 @@
   const Triple &getTargetTriple() const { return TargetTriple; }
 
   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
+  bool isTargetNaCl() const {
+    return TargetTriple.getOS() == Triple::NativeClient;
+  }
   bool isTargetELF() const { return !isTargetDarwin(); }
 
   bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Sep  5 16:51:43 2011
@@ -86,6 +86,14 @@
       ARMArchFeature += ",+thumb-mode";
   }
 
+  Triple TheTriple(TT);
+  if (TheTriple.getOS() == Triple::NativeClient) {
+    if (ARMArchFeature.empty())
+      ARMArchFeature = "+nacl-mode";
+    else
+      ARMArchFeature += ",+nacl-mode";
+  }
+
   return ARMArchFeature;
 }
 

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Sep  5 16:51:43 2011
@@ -40,9 +40,16 @@
 
 std::string X86_MC::ParseX86Triple(StringRef TT) {
   Triple TheTriple(TT);
+  std::string FS;
   if (TheTriple.getArch() == Triple::x86_64)
-    return "+64bit-mode";
-  return "-64bit-mode";
+    FS = "+64bit-mode";
+  else
+    FS = "-64bit-mode";
+  if (TheTriple.getOS() == Triple::NativeClient)
+    FS += ",+nacl-mode";
+  else
+    FS += ",-nacl-mode";
+  return FS;
 }
 
 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the

Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=139125&r1=139124&r2=139125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Mon Sep  5 16:51:43 2011
@@ -23,6 +23,9 @@
 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
                                   "64-bit mode (x86_64)">;
 
+def ModeNaCl  : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
+                                 "Native Client mode">;
+
 //===----------------------------------------------------------------------===//
 // X86 Subtarget features.
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep  5 16:51:43 2011
@@ -482,6 +482,14 @@
                              AssemblerPredicate<"Mode64Bit">;
 def IsWin64      : Predicate<"Subtarget->isTargetWin64()">;
 def NotWin64     : Predicate<"!Subtarget->isTargetWin64()">;
+def IsNaCl       : Predicate<"Subtarget->isTargetNaCl()">,
+                             AssemblerPredicate<"ModeNaCl">;
+def IsNaCl32     : Predicate<"Subtarget->isTargetNaCl32()">,
+                             AssemblerPredicate<"ModeNaCl,!Mode64Bit">;
+def IsNaCl64     : Predicate<"Subtarget->isTargetNaCl64()">,
+                             AssemblerPredicate<"ModeNaCl,Mode64Bit">;
+def NotNaCl      : Predicate<"!Subtarget->isTargetNaCl()">,
+                             AssemblerPredicate<"!ModeNaCl">;
 def SmallCode    : Predicate<"TM.getCodeModel() == CodeModel::Small">;
 def KernelCode   : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
 def FarData      : Predicate<"TM.getCodeModel() != CodeModel::Small &&"

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Sep  5 16:51:43 2011
@@ -260,7 +260,8 @@
   // FIXME: this is a known good value for Yonah. How about others?
   , MaxInlineSizeThreshold(128)
   , TargetTriple(TT)
-  , In64BitMode(is64Bit) {
+  , In64BitMode(is64Bit)
+  , InNaClMode(false) {
   // Determine default and user specified characteristics
   if (!FS.empty() || !CPU.empty()) {
     std::string CPUName = CPU;
@@ -306,6 +307,11 @@
   if (In64BitMode)
     ToggleFeature(X86::Mode64Bit);
 
+  if (isTargetNaCl()) {
+    InNaClMode = true;
+    ToggleFeature(X86::ModeNaCl);
+  }
+
   if (HasAVX)
     X86SSELevel = NoMMXSSE;
     

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=139125&r1=139124&r2=139125&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Sep  5 16:51:43 2011
@@ -119,6 +119,9 @@
   /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
   bool In64BitMode;
 
+  /// InNaClMode - True if compiling for Native Client target.
+  bool InNaClMode;
+
 public:
 
   /// This constructor initializes the data members to match that
@@ -190,6 +193,11 @@
     return !isTargetDarwin() && !isTargetWindows() && !isTargetCygMing();
   }
   bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
+  bool isTargetNaCl() const {
+    return TargetTriple.getOS() == Triple::NativeClient;
+  }
+  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
+  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
 
   bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
   bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }



From nicholas at mxc.ca  Mon Sep  5 18:25:16 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 05 Sep 2011 23:25:16 -0000
Subject: [llvm-commits] [llvm] r139126 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp
 test/Analysis/ScalarEvolution/max-trip-count.ll
Message-ID: <20110905232517.1991E2A6C12C@llvm.org>

Author: nicholas
Date: Mon Sep  5 18:25:16 2011
New Revision: 139126

URL: http://llvm.org/viewvc/llvm-project?rev=139126&view=rev
Log:
Teach SCEV to report a max backedge count in one interesting case in
HowFarToZero; the case for a canonical loop.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139126&r1=139125&r2=139126&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Sep  5 18:25:16 2011
@@ -5184,8 +5184,12 @@
   // Handle unitary steps, which cannot wraparound.
   // 1*N = -Start; -1*N = Start (mod 2^BW), so:
   //   N = Distance (as unsigned)
-  if (StepC->getValue()->equalsInt(1) || StepC->getValue()->isAllOnesValue())
-    return Distance;
+  if (StepC->getValue()->equalsInt(1) || StepC->getValue()->isAllOnesValue()) {
+    ConstantRange CR = getUnsignedRange(Start);
+    const SCEV *MaxBECount = getConstant(CountDown ? CR.getUnsignedMax()
+                                                   : ~CR.getUnsignedMin());
+    return ExitLimit(Distance, MaxBECount);
+  }
 
   // If the recurrence is known not to wraparound, unsigned divide computes the
   // back edge count. We know that the value will either become zero (and thus

Modified: llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll?rev=139126&r1=139125&r2=139126&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll Mon Sep  5 18:25:16 2011
@@ -70,3 +70,34 @@
 }
 
 declare i32 @printf(i8*, ...)
+
+; Before -indvars ran on this loop, SCEV solved a max loop trip count of
+; 2^31-2.  Afterwards, we can only solve 2^32-1.
+
+define void @test(i8* %a, i32 %n) nounwind {
+entry:
+  %cmp1 = icmp sgt i32 %n, 0
+  br i1 %cmp1, label %for.body.lr.ph, label %for.end
+
+for.body.lr.ph:                                   ; preds = %entry
+  %tmp = zext i32 %n to i64
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %for.body.lr.ph
+  %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %for.body.lr.ph ]
+  %arrayidx = getelementptr i8* %a, i64 %indvar
+  store i8 0, i8* %arrayidx, align 1
+  %indvar.next = add i64 %indvar, 1
+  %exitcond = icmp ne i64 %indvar.next, %tmp
+  br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
+
+for.cond.for.end_crit_edge:                       ; preds = %for.body
+  br label %for.end
+
+for.end:                                          ; preds = %for.cond.for.end_crit_edge, %entry
+  ret void
+}
+
+; CHECK: Determining loop execution counts for: @test
+; CHECK-NEXT: backedge-taken count is
+; CHECK-NEXT: max backedge-taken count is -1



From nicholas at mxc.ca  Mon Sep  5 21:43:13 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 06 Sep 2011 02:43:13 -0000
Subject: [llvm-commits] [llvm] r139130 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp
 test/Analysis/ScalarEvolution/max-trip-count.ll
Message-ID: <20110906024313.A00D32A6C12C@llvm.org>

Author: nicholas
Date: Mon Sep  5 21:43:13 2011
New Revision: 139130

URL: http://llvm.org/viewvc/llvm-project?rev=139130&view=rev
Log:
Revert r139126 due to selfhost failures reported by buildbots.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139130&r1=139129&r2=139130&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Sep  5 21:43:13 2011
@@ -5184,12 +5184,8 @@
   // Handle unitary steps, which cannot wraparound.
   // 1*N = -Start; -1*N = Start (mod 2^BW), so:
   //   N = Distance (as unsigned)
-  if (StepC->getValue()->equalsInt(1) || StepC->getValue()->isAllOnesValue()) {
-    ConstantRange CR = getUnsignedRange(Start);
-    const SCEV *MaxBECount = getConstant(CountDown ? CR.getUnsignedMax()
-                                                   : ~CR.getUnsignedMin());
-    return ExitLimit(Distance, MaxBECount);
-  }
+  if (StepC->getValue()->equalsInt(1) || StepC->getValue()->isAllOnesValue())
+    return Distance;
 
   // If the recurrence is known not to wraparound, unsigned divide computes the
   // back edge count. We know that the value will either become zero (and thus

Modified: llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll?rev=139130&r1=139129&r2=139130&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll Mon Sep  5 21:43:13 2011
@@ -70,34 +70,3 @@
 }
 
 declare i32 @printf(i8*, ...)
-
-; Before -indvars ran on this loop, SCEV solved a max loop trip count of
-; 2^31-2.  Afterwards, we can only solve 2^32-1.
-
-define void @test(i8* %a, i32 %n) nounwind {
-entry:
-  %cmp1 = icmp sgt i32 %n, 0
-  br i1 %cmp1, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  %tmp = zext i32 %n to i64
-  br label %for.body
-
-for.body:                                         ; preds = %for.body, %for.body.lr.ph
-  %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %for.body.lr.ph ]
-  %arrayidx = getelementptr i8* %a, i64 %indvar
-  store i8 0, i8* %arrayidx, align 1
-  %indvar.next = add i64 %indvar, 1
-  %exitcond = icmp ne i64 %indvar.next, %tmp
-  br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
-
-for.cond.for.end_crit_edge:                       ; preds = %for.body
-  br label %for.end
-
-for.end:                                          ; preds = %for.cond.for.end_crit_edge, %entry
-  ret void
-}
-
-; CHECK: Determining loop execution counts for: @test
-; CHECK-NEXT: backedge-taken count is
-; CHECK-NEXT: max backedge-taken count is -1



From pdox at google.com  Mon Sep  5 23:40:17 2011
From: pdox at google.com (David Meyer)
Date: Mon, 5 Sep 2011 21:40:17 -0700
Subject: [llvm-commits] [PATCH] Clean up RegOp2MemOp tables in
	X86InstrInfo.cpp
Message-ID: <CAAU48JKT3LE1gCzvWtv5Me4AsQLTbGa+boxFyZsjuKOP+8BanQ@mail.gmail.com>

Hello!

This patch:

* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.

* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }

* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.

* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.

* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).

Unfortunately, this patch looks like a lot bigger than it is, because
the spacing adjustments confuse diff. Here is a visual diff which are
slightly easier to follow:

http://codereview.chromium.org/7834034  (click View)

(Reminder: I do not have commit access; if you approve, please commit!)

- pdox
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From nicholas at mxc.ca  Tue Sep  6 00:05:14 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 06 Sep 2011 05:05:14 -0000
Subject: [llvm-commits] [llvm] r139133 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp
 test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
Message-ID: <20110906050514.BD5592A6C12C@llvm.org>

Author: nicholas
Date: Tue Sep  6 00:05:14 2011
New Revision: 139133

URL: http://llvm.org/viewvc/llvm-project?rev=139133&view=rev
Log:
The logic inside getMulExpr to simplify {a,+,b}*{c,+,d} was wrong, which was
visible given a=b=c=d=1, on iteration #1 (the second iteration). Replace it with
correct math. Fixes PR10383!

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139133&r1=139132&r2=139133&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep  6 00:05:14 2011
@@ -1735,7 +1735,7 @@
       // If all of the other operands were loop invariant, we are done.
       if (Ops.size() == 1) return NewRec;
 
-      // Otherwise, add the folded AddRec by the non-liv parts.
+      // Otherwise, add the folded AddRec by the non-live parts.
       for (unsigned i = 0;; ++i)
         if (Ops[i] == AddRec) {
           Ops[i] = NewRec;
@@ -1960,7 +1960,7 @@
       // If all of the other operands were loop invariant, we are done.
       if (Ops.size() == 1) return NewRec;
 
-      // Otherwise, multiply the folded AddRec by the non-liv parts.
+      // Otherwise, multiply the folded AddRec by the non-live parts.
       for (unsigned i = 0;; ++i)
         if (Ops[i] == AddRec) {
           Ops[i] = NewRec;
@@ -1976,22 +1976,29 @@
          OtherIdx < Ops.size() && isa<SCEVAddRecExpr>(Ops[OtherIdx]);
          ++OtherIdx)
       if (AddRecLoop == cast<SCEVAddRecExpr>(Ops[OtherIdx])->getLoop()) {
-        // F * G, where F = {A,+,B}<L> and G = {C,+,D}<L>  -->
-        // {A*C,+,F*D + G*B + B*D}<L>
+        // {A,+,B}<L> * {C,+,D}<L>  -->  {A*C,+,A*D + B*C + B*D,+,2*B*D}<L>
         for (; OtherIdx != Ops.size() && isa<SCEVAddRecExpr>(Ops[OtherIdx]);
              ++OtherIdx)
           if (const SCEVAddRecExpr *OtherAddRec =
                 dyn_cast<SCEVAddRecExpr>(Ops[OtherIdx]))
             if (OtherAddRec->getLoop() == AddRecLoop) {
-              const SCEVAddRecExpr *F = AddRec, *G = OtherAddRec;
-              const SCEV *NewStart = getMulExpr(F->getStart(), G->getStart());
-              const SCEV *B = F->getStepRecurrence(*this);
-              const SCEV *D = G->getStepRecurrence(*this);
-              const SCEV *NewStep = getAddExpr(getMulExpr(F, D),
-                                               getMulExpr(G, B),
-                                               getMulExpr(B, D));
-              const SCEV *NewAddRec = getAddRecExpr(NewStart, NewStep,
-                                                    F->getLoop(),
+              const SCEV *A = AddRec->getStart();
+              const SCEV *B = AddRec->getStepRecurrence(*this);
+              const SCEV *C = OtherAddRec->getStart();
+              const SCEV *D = OtherAddRec->getStepRecurrence(*this);
+              const SCEV *NewStart = getMulExpr(A, C);
+              const SCEV *BD = getMulExpr(B, D);
+              const SCEV *NewStep = getAddExpr(getMulExpr(A, D),
+                                               getMulExpr(B, C), BD);
+              const SCEV *NewSecondOrderStep =
+                  getMulExpr(BD, getConstant(BD->getType(), 2));
+
+              SmallVector<const SCEV *, 3> AddRecOps;
+              AddRecOps.push_back(NewStart);
+              AddRecOps.push_back(NewStep);
+              AddRecOps.push_back(NewSecondOrderStep);
+              const SCEV *NewAddRec = getAddRecExpr(AddRecOps,
+                                                    AddRec->getLoop(),
                                                     SCEV::FlagAnyWrap);
               if (Ops.size() == 2) return NewAddRec;
               Ops[Idx] = AddRec = cast<SCEVAddRecExpr>(NewAddRec);

Modified: llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll?rev=139133&r1=139132&r2=139133&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll Tue Sep  6 00:05:14 2011
@@ -1,11 +1,11 @@
 ; RUN: opt < %s -analyze -scalar-evolution \
-; RUN:   -scalar-evolution-max-iterations=0 | grep {backedge-taken count is 100}
+; RUN:   -scalar-evolution-max-iterations=0 | FileCheck %s
+
 ; PR1101
 
 @A = weak global [1000 x i32] zeroinitializer, align 32         
 
-
-define void @test(i32 %N) {
+define void @test1(i32 %N) {
 entry:
         %"alloca point" = bitcast i32 0 to i32           ; <i32> [#uses=0]
         br label %bb3
@@ -30,3 +30,34 @@
 return:         ; preds = %bb5
         ret void
 }
+; CHECK: Determining loop execution counts for: @test1
+; CHECK-NEXT: backedge-taken count is 100
+
+
+; PR10383
+; This used to crash.
+
+define void @test2(i1 %cmp, i64 %n) {
+entry:
+  br label %for.body1
+
+for.body1:
+  %a0.08 = phi i64 [ 0, %entry ], [ %inc512, %for.body1 ]
+  %inc512 = add i64 %a0.08, 1
+  br i1 %cmp, label %preheader, label %for.body1
+
+preheader:
+  br label %for.body2
+
+for.body2:
+  %indvar = phi i64 [ 0, %preheader ], [ %indvar.next, %for.body2 ]
+  %tmp111 = add i64 %n, %indvar
+  %tmp114 = mul i64 %a0.08, %indvar
+  %mul542 = mul i64 %tmp114, %tmp111
+  %indvar.next = add i64 %indvar, 1
+  br i1 undef, label %end, label %for.body2
+
+end:
+  ret void
+}
+; CHECK: Determining loop execution counts for: @test2



From nicholas at mxc.ca  Tue Sep  6 00:08:09 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 06 Sep 2011 05:08:09 -0000
Subject: [llvm-commits] [llvm] r139134 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20110906050809.6E7F12A6C12C@llvm.org>

Author: nicholas
Date: Tue Sep  6 00:08:09 2011
New Revision: 139134

URL: http://llvm.org/viewvc/llvm-project?rev=139134&view=rev
Log:
No no no, fix typo properly!

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139134&r1=139133&r2=139134&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep  6 00:08:09 2011
@@ -1735,7 +1735,7 @@
       // If all of the other operands were loop invariant, we are done.
       if (Ops.size() == 1) return NewRec;
 
-      // Otherwise, add the folded AddRec by the non-live parts.
+      // Otherwise, add the folded AddRec by the non-invariant parts.
       for (unsigned i = 0;; ++i)
         if (Ops[i] == AddRec) {
           Ops[i] = NewRec;
@@ -1960,7 +1960,7 @@
       // If all of the other operands were loop invariant, we are done.
       if (Ops.size() == 1) return NewRec;
 
-      // Otherwise, multiply the folded AddRec by the non-live parts.
+      // Otherwise, multiply the folded AddRec by the non-invariant parts.
       for (unsigned i = 0;; ++i)
         if (Ops[i] == AddRec) {
           Ops[i] = NewRec;



From nicholas at mxc.ca  Tue Sep  6 00:33:18 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 06 Sep 2011 05:33:18 -0000
Subject: [llvm-commits] [llvm] r139135 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20110906053318.B886E2A6C12C@llvm.org>

Author: nicholas
Date: Tue Sep  6 00:33:18 2011
New Revision: 139135

URL: http://llvm.org/viewvc/llvm-project?rev=139135&view=rev
Log:
Fix flipped sign. While there, show my math.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139135&r1=139134&r2=139135&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep  6 00:33:18 2011
@@ -1976,7 +1976,13 @@
          OtherIdx < Ops.size() && isa<SCEVAddRecExpr>(Ops[OtherIdx]);
          ++OtherIdx)
       if (AddRecLoop == cast<SCEVAddRecExpr>(Ops[OtherIdx])->getLoop()) {
-        // {A,+,B}<L> * {C,+,D}<L>  -->  {A*C,+,A*D + B*C + B*D,+,2*B*D}<L>
+        // {A,+,B}<L> * {C,+,D}<L>  -->  {A*C,+,A*D + B*C - B*D,+,2*B*D}<L>
+        //
+        // For reference, given that {X,+,Y,+,Z} = x + y*It + z*It^2 then
+        // X = x, Y = y-z, Z = 2z.
+        //
+        // x = A*C, y = (A*D + B*C), z = B*D
+        // Therefore X = A*C, Y = (A*D + B*C) - B*D and Z = 2*B*D.
         for (; OtherIdx != Ops.size() && isa<SCEVAddRecExpr>(Ops[OtherIdx]);
              ++OtherIdx)
           if (const SCEVAddRecExpr *OtherAddRec =
@@ -1989,7 +1995,8 @@
               const SCEV *NewStart = getMulExpr(A, C);
               const SCEV *BD = getMulExpr(B, D);
               const SCEV *NewStep = getAddExpr(getMulExpr(A, D),
-                                               getMulExpr(B, C), BD);
+                                               getMulExpr(B, C),
+                                               getNegativeSCEV(BD));
               const SCEV *NewSecondOrderStep =
                   getMulExpr(BD, getConstant(BD->getType(), 2));
 



From nicholas at mxc.ca  Tue Sep  6 01:39:54 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 06 Sep 2011 06:39:54 -0000
Subject: [llvm-commits] [llvm] r139136 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20110906063954.46BAF2A6C12C@llvm.org>

Author: nicholas
Date: Tue Sep  6 01:39:54 2011
New Revision: 139136

URL: http://llvm.org/viewvc/llvm-project?rev=139136&view=rev
Log:
Nope! I had it right the first time. Revert the operative part of r139135 and
add more showing of my work.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139136&r1=139135&r2=139136&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep  6 01:39:54 2011
@@ -652,7 +652,7 @@
 /// Assume, K > 0.
 static const SCEV *BinomialCoefficient(const SCEV *It, unsigned K,
                                        ScalarEvolution &SE,
-                                       Type* ResultTy) {
+                                       Type *ResultTy) {
   // Handle the simplest case efficiently.
   if (K == 1)
     return SE.getTruncateOrZeroExtend(It, ResultTy);
@@ -1976,12 +1976,15 @@
          OtherIdx < Ops.size() && isa<SCEVAddRecExpr>(Ops[OtherIdx]);
          ++OtherIdx)
       if (AddRecLoop == cast<SCEVAddRecExpr>(Ops[OtherIdx])->getLoop()) {
-        // {A,+,B}<L> * {C,+,D}<L>  -->  {A*C,+,A*D + B*C - B*D,+,2*B*D}<L>
+        // {A,+,B}<L> * {C,+,D}<L>  -->  {A*C,+,A*D + B*C + B*D,+,2*B*D}<L>
         //
-        // For reference, given that {X,+,Y,+,Z} = x + y*It + z*It^2 then
-        // X = x, Y = y-z, Z = 2z.
+        // {A,+,B} * {C,+,D} = A+It*B * C+It*D = A*C + (A*D + B*C)*It + B*D*It^2
+        // Given an equation of the form x + y*It + z*It^2 (above), we want to
+        // express it in terms of {X,+,Y,+,Z}.
+        // {X,+,Y,+,Z} = X + Y*It + Z*(It^2 - It)/2.
+        // Rearranging, X = x, Y = x+y, Z = 2z.
         //
-        // x = A*C, y = (A*D + B*C), z = B*D
+        // x = A*C, y = (A*D + B*C), z = B*D.
         // Therefore X = A*C, Y = (A*D + B*C) - B*D and Z = 2*B*D.
         for (; OtherIdx != Ops.size() && isa<SCEVAddRecExpr>(Ops[OtherIdx]);
              ++OtherIdx)



From nicholas at mxc.ca  Tue Sep  6 01:46:01 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 06 Sep 2011 06:46:01 -0000
Subject: [llvm-commits] [llvm] r139137 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20110906064601.E9DA22A6C12C@llvm.org>

Author: nicholas
Date: Tue Sep  6 01:46:01 2011
New Revision: 139137

URL: http://llvm.org/viewvc/llvm-project?rev=139137&view=rev
Log:
Fix typo in comment.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139137&r1=139136&r2=139137&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep  6 01:46:01 2011
@@ -1982,7 +1982,7 @@
         // Given an equation of the form x + y*It + z*It^2 (above), we want to
         // express it in terms of {X,+,Y,+,Z}.
         // {X,+,Y,+,Z} = X + Y*It + Z*(It^2 - It)/2.
-        // Rearranging, X = x, Y = x+y, Z = 2z.
+        // Rearranging, X = x, Y = y+z, Z = 2z.
         //
         // x = A*C, y = (A*D + B*C), z = B*D.
         // Therefore X = A*C, Y = (A*D + B*C) - B*D and Z = 2*B*D.



From eli.friedman at gmail.com  Tue Sep  6 01:55:54 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 5 Sep 2011 23:55:54 -0700
Subject: [llvm-commits] [llvm] r139136 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
In-Reply-To: <20110906063954.46BAF2A6C12C@llvm.org>
References: <20110906063954.46BAF2A6C12C@llvm.org>
Message-ID: <CAJdarcEy-5wGMtaBd99ueLqmjFTcr6VK6cQQ_2izZgze40rxCg@mail.gmail.com>

On Mon, Sep 5, 2011 at 11:39 PM, Nick Lewycky <nicholas at mxc.ca> wrote:
> Author: nicholas
> Date: Tue Sep ?6 01:39:54 2011
> New Revision: 139136
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139136&view=rev
> Log:
> Nope! I had it right the first time. Revert the operative part of r139135 and
> add more showing of my work.

Commit message not consistent with the commit.

-Eli

> Modified:
> ? ?llvm/trunk/lib/Analysis/ScalarEvolution.cpp
>
> Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139136&r1=139135&r2=139136&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
> +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep ?6 01:39:54 2011
> @@ -652,7 +652,7 @@
> ?/// Assume, K > 0.
> ?static const SCEV *BinomialCoefficient(const SCEV *It, unsigned K,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ScalarEvolution &SE,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Type* ResultTy) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Type *ResultTy) {
> ? // Handle the simplest case efficiently.
> ? if (K == 1)
> ? ? return SE.getTruncateOrZeroExtend(It, ResultTy);
> @@ -1976,12 +1976,15 @@
> ? ? ? ? ?OtherIdx < Ops.size() && isa<SCEVAddRecExpr>(Ops[OtherIdx]);
> ? ? ? ? ?++OtherIdx)
> ? ? ? if (AddRecLoop == cast<SCEVAddRecExpr>(Ops[OtherIdx])->getLoop()) {
> - ? ? ? ?// {A,+,B}<L> * {C,+,D}<L> ?--> ?{A*C,+,A*D + B*C - B*D,+,2*B*D}<L>
> + ? ? ? ?// {A,+,B}<L> * {C,+,D}<L> ?--> ?{A*C,+,A*D + B*C + B*D,+,2*B*D}<L>
> ? ? ? ? //
> - ? ? ? ?// For reference, given that {X,+,Y,+,Z} = x + y*It + z*It^2 then
> - ? ? ? ?// X = x, Y = y-z, Z = 2z.
> + ? ? ? ?// {A,+,B} * {C,+,D} = A+It*B * C+It*D = A*C + (A*D + B*C)*It + B*D*It^2
> + ? ? ? ?// Given an equation of the form x + y*It + z*It^2 (above), we want to
> + ? ? ? ?// express it in terms of {X,+,Y,+,Z}.
> + ? ? ? ?// {X,+,Y,+,Z} = X + Y*It + Z*(It^2 - It)/2.
> + ? ? ? ?// Rearranging, X = x, Y = x+y, Z = 2z.
> ? ? ? ? //
> - ? ? ? ?// x = A*C, y = (A*D + B*C), z = B*D
> + ? ? ? ?// x = A*C, y = (A*D + B*C), z = B*D.
> ? ? ? ? // Therefore X = A*C, Y = (A*D + B*C) - B*D and Z = 2*B*D.
> ? ? ? ? for (; OtherIdx != Ops.size() && isa<SCEVAddRecExpr>(Ops[OtherIdx]);
> ? ? ? ? ? ? ?++OtherIdx)
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From nicholas at mxc.ca  Tue Sep  6 01:56:00 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 06 Sep 2011 06:56:00 -0000
Subject: [llvm-commits] [llvm] r139138 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20110906065600.5230D2A6C12C@llvm.org>

Author: nicholas
Date: Tue Sep  6 01:56:00 2011
New Revision: 139138

URL: http://llvm.org/viewvc/llvm-project?rev=139138&view=rev
Log:
Apparently we compile the code, not the comments. Thanks Eli!

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139138&r1=139137&r2=139138&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep  6 01:56:00 2011
@@ -1998,8 +1998,7 @@
               const SCEV *NewStart = getMulExpr(A, C);
               const SCEV *BD = getMulExpr(B, D);
               const SCEV *NewStep = getAddExpr(getMulExpr(A, D),
-                                               getMulExpr(B, C),
-                                               getNegativeSCEV(BD));
+                                               getMulExpr(B, C), BD);
               const SCEV *NewSecondOrderStep =
                   getMulExpr(BD, getConstant(BD->getType(), 2));
 



From nicholas at mxc.ca  Tue Sep  6 01:57:54 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 05 Sep 2011 23:57:54 -0700
Subject: [llvm-commits] [llvm] r139136 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
In-Reply-To: <CAJdarcEy-5wGMtaBd99ueLqmjFTcr6VK6cQQ_2izZgze40rxCg@mail.gmail.com>
References: <20110906063954.46BAF2A6C12C@llvm.org>
	<CAJdarcEy-5wGMtaBd99ueLqmjFTcr6VK6cQQ_2izZgze40rxCg@mail.gmail.com>
Message-ID: <4E65C472.1080107@mxc.ca>

Eli Friedman wrote:
> On Mon, Sep 5, 2011 at 11:39 PM, Nick Lewycky<nicholas at mxc.ca>  wrote:
>> Author: nicholas
>> Date: Tue Sep  6 01:39:54 2011
>> New Revision: 139136
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=139136&view=rev
>> Log:
>> Nope! I had it right the first time. Revert the operative part of r139135 and
>> add more showing of my work.
>
> Commit message not consistent with the commit.

Thanks Eli!

Nick

>
> -Eli
>
>> Modified:
>>     llvm/trunk/lib/Analysis/ScalarEvolution.cpp
>>
>> Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139136&r1=139135&r2=139136&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
>> +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep  6 01:39:54 2011
>> @@ -652,7 +652,7 @@
>>   /// Assume, K>  0.
>>   static const SCEV *BinomialCoefficient(const SCEV *It, unsigned K,
>>                                         ScalarEvolution&SE,
>> -                                       Type* ResultTy) {
>> +                                       Type *ResultTy) {
>>    // Handle the simplest case efficiently.
>>    if (K == 1)
>>      return SE.getTruncateOrZeroExtend(It, ResultTy);
>> @@ -1976,12 +1976,15 @@
>>           OtherIdx<  Ops.size()&&  isa<SCEVAddRecExpr>(Ops[OtherIdx]);
>>           ++OtherIdx)
>>        if (AddRecLoop == cast<SCEVAddRecExpr>(Ops[OtherIdx])->getLoop()) {
>> -        // {A,+,B}<L>  * {C,+,D}<L>    -->    {A*C,+,A*D + B*C - B*D,+,2*B*D}<L>
>> +        // {A,+,B}<L>  * {C,+,D}<L>    -->    {A*C,+,A*D + B*C + B*D,+,2*B*D}<L>
>>          //
>> -        // For reference, given that {X,+,Y,+,Z} = x + y*It + z*It^2 then
>> -        // X = x, Y = y-z, Z = 2z.
>> +        // {A,+,B} * {C,+,D} = A+It*B * C+It*D = A*C + (A*D + B*C)*It + B*D*It^2
>> +        // Given an equation of the form x + y*It + z*It^2 (above), we want to
>> +        // express it in terms of {X,+,Y,+,Z}.
>> +        // {X,+,Y,+,Z} = X + Y*It + Z*(It^2 - It)/2.
>> +        // Rearranging, X = x, Y = x+y, Z = 2z.
>>          //
>> -        // x = A*C, y = (A*D + B*C), z = B*D
>> +        // x = A*C, y = (A*D + B*C), z = B*D.
>>          // Therefore X = A*C, Y = (A*D + B*C) - B*D and Z = 2*B*D.
>>          for (; OtherIdx != Ops.size()&&  isa<SCEVAddRecExpr>(Ops[OtherIdx]);
>>               ++OtherIdx)
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>


From nicholas at mxc.ca  Tue Sep  6 02:02:40 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 06 Sep 2011 07:02:40 -0000
Subject: [llvm-commits] [llvm] r139139 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20110906070240.C21F32A6C12C@llvm.org>

Author: nicholas
Date: Tue Sep  6 02:02:40 2011
New Revision: 139139

URL: http://llvm.org/viewvc/llvm-project?rev=139139&view=rev
Log:
Fix typo in comment again.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139139&r1=139138&r2=139139&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep  6 02:02:40 2011
@@ -1985,7 +1985,7 @@
         // Rearranging, X = x, Y = y+z, Z = 2z.
         //
         // x = A*C, y = (A*D + B*C), z = B*D.
-        // Therefore X = A*C, Y = (A*D + B*C) - B*D and Z = 2*B*D.
+        // Therefore X = A*C, Y = (A*D + B*C) + B*D and Z = 2*B*D.
         for (; OtherIdx != Ops.size() && isa<SCEVAddRecExpr>(Ops[OtherIdx]);
              ++OtherIdx)
           if (const SCEVAddRecExpr *OtherAddRec =



From baldrick at free.fr  Tue Sep  6 08:37:06 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 06 Sep 2011 13:37:06 -0000
Subject: [llvm-commits] [llvm] r139140 - in /llvm/trunk: docs/ include/llvm/
 include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/PowerPC/
 lib/Target/X86/ lib/Target/XCore/ lib/Transforms/InstCombine/ lib/VMCore/
 test/Assembler/ test/CodeGen/PowerPC/ test/CodeGen/XCore/
 test/Transforms/InstCombine/
Message-ID: <20110906133707.645662A6C12C@llvm.org>

Author: baldrick
Date: Tue Sep  6 08:37:06 2011
New Revision: 139140

URL: http://llvm.org/viewvc/llvm-project?rev=139140&view=rev
Log:
Split the init.trampoline intrinsic, which currently combines GCC's
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC.  While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function.  To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function.  Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!).  Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC.  Patch mostly by Sanjoy Das.

Modified:
    llvm/trunk/docs/LangRef.html
    llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h
    llvm/trunk/include/llvm/Intrinsics.td
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
    llvm/trunk/lib/Transforms/InstCombine/InstCombine.h
    llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
    llvm/trunk/lib/VMCore/AutoUpgrade.cpp
    llvm/trunk/test/Assembler/AutoUpgradeIntrinsics.ll
    llvm/trunk/test/CodeGen/PowerPC/trampoline.ll
    llvm/trunk/test/CodeGen/XCore/trampoline.ll
    llvm/trunk/test/Transforms/InstCombine/2008-01-14-VarArgTrampoline.ll

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Tue Sep  6 08:37:06 2011
@@ -275,9 +275,10 @@
       </li>
       <li><a href="#int_debugger">Debugger intrinsics</a></li>
       <li><a href="#int_eh">Exception Handling intrinsics</a></li>
-      <li><a href="#int_trampoline">Trampoline Intrinsic</a>
+      <li><a href="#int_trampoline">Trampoline Intrinsics</a>
         <ol>
           <li><a href="#int_it">'<tt>llvm.init.trampoline</tt>' Intrinsic</a></li>
+          <li><a href="#int_at">'<tt>llvm.adjust.trampoline</tt>' Intrinsic</a></li>
         </ol>
       </li>
       <li><a href="#int_atomics">Atomic intrinsics</a>
@@ -7680,12 +7681,12 @@
 
 <!-- ======================================================================= -->
 <h3>
-  <a name="int_trampoline">Trampoline Intrinsic</a>
+  <a name="int_trampoline">Trampoline Intrinsics</a>
 </h3>
 
 <div>
 
-<p>This intrinsic makes it possible to excise one parameter, marked with
+<p>These intrinsics make it possible to excise one parameter, marked with
    the <a href="#nest"><tt>nest</tt></a> attribute, from a function.
    The result is a callable
    function pointer lacking the nest parameter - the caller does not need to
@@ -7702,7 +7703,8 @@
 <pre class="doc_code">
   %tramp = alloca [10 x i8], align 4 ; size and alignment only correct for X86
   %tramp1 = getelementptr [10 x i8]* %tramp, i32 0, i32 0
-  %p = call i8* @llvm.init.trampoline(i8* %tramp1, i8* bitcast (i32 (i8*, i32, i32)* @f to i8*), i8* %nval)
+  call i8* @llvm.init.trampoline(i8* %tramp1, i8* bitcast (i32 (i8*, i32, i32)* @f to i8*), i8* %nval)
+  %p = call i8* @llvm.adjust.trampoline(i8* %tramp1)
   %fp = bitcast i8* %p to i32 (i32, i32)*
 </pre>
 
@@ -7720,12 +7722,12 @@
 
 <h5>Syntax:</h5>
 <pre>
-  declare i8* @llvm.init.trampoline(i8* &lt;tramp&gt;, i8* &lt;func&gt;, i8* &lt;nval&gt;)
+  declare void @llvm.init.trampoline(i8* &lt;tramp&gt;, i8* &lt;func&gt;, i8* &lt;nval&gt;)
 </pre>
 
 <h5>Overview:</h5>
-<p>This fills the memory pointed to by <tt>tramp</tt> with code and returns a
-   function pointer suitable for executing it.</p>
+<p>This fills the memory pointed to by <tt>tramp</tt> with executable code,
+   turning it into a trampoline.</p>
 
 <h5>Arguments:</h5>
 <p>The <tt>llvm.init.trampoline</tt> intrinsic takes three arguments, all
@@ -7739,17 +7741,50 @@
 
 <h5>Semantics:</h5>
 <p>The block of memory pointed to by <tt>tramp</tt> is filled with target
-   dependent code, turning it into a function.  A pointer to this function is
-   returned, but needs to be bitcast to an <a href="#int_trampoline">appropriate
-   function pointer type</a> before being called.  The new function's signature
-   is the same as that of <tt>func</tt> with any arguments marked with
-   the <tt>nest</tt> attribute removed.  At most one such <tt>nest</tt> argument
-   is allowed, and it must be of pointer type.  Calling the new function is
-   equivalent to calling <tt>func</tt> with the same argument list, but
-   with <tt>nval</tt> used for the missing <tt>nest</tt> argument.  If, after
-   calling <tt>llvm.init.trampoline</tt>, the memory pointed to
-   by <tt>tramp</tt> is modified, then the effect of any later call to the
-   returned function pointer is undefined.</p>
+   dependent code, turning it into a function.  Then <tt>tramp</tt> needs to be
+   passed to <a href="#int_at">llvm.adjust.trampoline</a> to get a pointer
+   which can be <a href="#int_trampoline">bitcast (to a new function) and
+   called</a>.  The new function's signature is the same as that of
+   <tt>func</tt> with any arguments marked with the <tt>nest</tt> attribute
+   removed.  At most one such <tt>nest</tt> argument is allowed, and it must be of
+   pointer type.  Calling the new function is equivalent to calling <tt>func</tt>
+   with the same argument list, but with <tt>nval</tt> used for the missing
+   <tt>nest</tt> argument.  If, after calling <tt>llvm.init.trampoline</tt>, the
+   memory pointed to by <tt>tramp</tt> is modified, then the effect of any later call
+   to the returned function pointer is undefined.</p>
+</div>
+
+<!-- _______________________________________________________________________ -->
+<h4>
+  <a name="int_at">
+    '<tt>llvm.adjust.trampoline</tt>' Intrinsic
+  </a>
+</h4>
+
+<div>
+
+<h5>Syntax:</h5>
+<pre>
+  declare i8* @llvm.adjust.trampoline(i8* &lt;tramp&gt;)
+</pre>
+
+<h5>Overview:</h5>
+<p>This performs any required machine-specific adjustment to the address of a
+   trampoline (passed as <tt>tramp</tt>).</p>
+
+<h5>Arguments:</h5>
+<p><tt>tramp</tt> must point to a block of memory which already has trampoline code
+   filled in by a previous call to <a href="#int_it"><tt>llvm.init.trampoline</tt>
+   </a>.</p>
+
+<h5>Semantics:</h5>
+<p>On some architectures the address of the code to be executed needs to be
+   different to the address where the trampoline is actually stored.  This
+   intrinsic returns the executable address corresponding to <tt>tramp</tt>
+   after performing the required machine specific adjustments.
+   The pointer returned can then be <a href="#int_trampoline"> bitcast and
+   executed</a>.
+</p>
 
 </div>
 

Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Tue Sep  6 08:37:06 2011
@@ -566,14 +566,19 @@
     // HANDLENODE node - Used as a handle for various purposes.
     HANDLENODE,
 
-    // TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
-    // It takes as input a token chain, the pointer to the trampoline,
-    // the pointer to the nested function, the pointer to pass for the
-    // 'nest' parameter, a SRCVALUE for the trampoline and another for
-    // the nested function (allowing targets to access the original
-    // Function*).  It produces the result of the intrinsic and a token
-    // chain as output.
-    TRAMPOLINE,
+    // INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.  It
+    // takes as input a token chain, the pointer to the trampoline, the pointer
+    // to the nested function, the pointer to pass for the 'nest' parameter, a
+    // SRCVALUE for the trampoline and another for the nested function (allowing
+    // targets to access the original Function*).  It produces a token chain as
+    // output.
+    INIT_TRAMPOLINE,
+
+    // ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
+    // It takes a pointer to the trampoline and produces a (possibly) new
+    // pointer to the same trampoline with platform-specific adjustments
+    // applied.  The pointer it returns points to an executable block of code.
+    ADJUST_TRAMPOLINE,
 
     // TRAP - Trapping instruction
     TRAP,

Modified: llvm/trunk/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Tue Sep  6 08:37:06 2011
@@ -344,10 +344,14 @@
 
 //===------------------------ Trampoline Intrinsics -----------------------===//
 //
-def int_init_trampoline : Intrinsic<[llvm_ptr_ty],
+def int_init_trampoline : Intrinsic<[],
                                     [llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty],
-                                    [IntrReadWriteArgMem]>,
-                          GCCBuiltin<"__builtin_init_trampoline">;
+                                    [IntrReadWriteArgMem, NoCapture<0>]>,
+                                   GCCBuiltin<"__builtin_init_trampoline">;
+
+def int_adjust_trampoline : Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty],
+                                      [IntrReadArgMem]>,
+                                     GCCBuiltin<"__builtin_adjust_trampoline">;
 
 //===------------------------ Overflow Intrinsics -------------------------===//
 //

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Sep  6 08:37:06 2011
@@ -872,7 +872,8 @@
     if (Action == TargetLowering::Legal)
       Action = TargetLowering::Expand;
     break;
-  case ISD::TRAMPOLINE:
+  case ISD::INIT_TRAMPOLINE:
+  case ISD::ADJUST_TRAMPOLINE:
   case ISD::FRAMEADDR:
   case ISD::RETURNADDR:
     // These operations lie about being legal: when they claim to be legal,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep  6 08:37:06 2011
@@ -6054,7 +6054,8 @@
   case ISD::CTLZ:    return "ctlz";
 
   // Trampolines
-  case ISD::TRAMPOLINE: return "trampoline";
+  case ISD::INIT_TRAMPOLINE: return "init_trampoline";
+  case ISD::ADJUST_TRAMPOLINE: return "adjust_trampoline";
 
   case ISD::CONDCODE:
     switch (cast<CondCodeSDNode>(this)->get()) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Sep  6 08:37:06 2011
@@ -5016,12 +5016,15 @@
     Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
     Ops[5] = DAG.getSrcValue(F);
 
-    Res = DAG.getNode(ISD::TRAMPOLINE, dl,
-                      DAG.getVTList(TLI.getPointerTy(), MVT::Other),
-                      Ops, 6);
+    Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
 
-    setValue(&I, Res);
-    DAG.setRoot(Res.getValue(1));
+    DAG.setRoot(Res);
+    return 0;
+  }
+  case Intrinsic::adjust_trampoline: {
+    setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
+                             TLI.getPointerTy(),
+                             getValue(I.getArgOperand(0))));
     return 0;
   }
   case Intrinsic::gcroot:

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Sep  6 08:37:06 2011
@@ -211,7 +211,8 @@
   setOperationAction(ISD::TRAP, MVT::Other, Legal);
 
   // TRAMPOLINE is custom lowered.
-  setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
+  setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
+  setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
 
   // VASTART needs to be custom lowered to use the VarArgsFrameIndex
   setOperationAction(ISD::VASTART           , MVT::Other, Custom);
@@ -1373,8 +1374,13 @@
   return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), false, false, 0);
 }
 
-SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op,
-                                           SelectionDAG &DAG) const {
+SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  return Op.getOperand(0);
+}
+
+SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
+                                                SelectionDAG &DAG) const {
   SDValue Chain = Op.getOperand(0);
   SDValue Trmp = Op.getOperand(1); // trampoline
   SDValue FPtr = Op.getOperand(2); // nested function
@@ -1403,16 +1409,13 @@
 
   // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
   std::pair<SDValue, SDValue> CallResult =
-    LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
+    LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
                 false, false, false, false, 0, CallingConv::C, false,
                 /*isReturnValueUsed=*/true,
                 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
                 Args, DAG, dl);
 
-  SDValue Ops[] =
-    { CallResult.first, CallResult.second };
-
-  return DAG.getMergeValues(Ops, 2, dl);
+  return CallResult.second;
 }
 
 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
@@ -4499,7 +4502,8 @@
   case ISD::GlobalTLSAddress:   llvm_unreachable("TLS not implemented for PPC");
   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
   case ISD::SETCC:              return LowerSETCC(Op, DAG);
-  case ISD::TRAMPOLINE:         return LowerTRAMPOLINE(Op, DAG);
+  case ISD::INIT_TRAMPOLINE:    return LowerINIT_TRAMPOLINE(Op, DAG);
+  case ISD::ADJUST_TRAMPOLINE:  return LowerADJUST_TRAMPOLINE(Op, DAG);
   case ISD::VASTART:
     return LowerVASTART(Op, DAG, PPCSubTarget);
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Tue Sep  6 08:37:06 2011
@@ -390,7 +390,8 @@
     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
                          const PPCSubtarget &Subtarget) const;
     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep  6 08:37:06 2011
@@ -504,7 +504,8 @@
   setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
   setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
 
-  setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
+  setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
+  setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
 
   setOperationAction(ISD::TRAP, MVT::Other, Legal);
 
@@ -9406,8 +9407,13 @@
                      Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
 }
 
-SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
-                                             SelectionDAG &DAG) const {
+SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  return Op.getOperand(0);
+}
+
+SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
+                                                SelectionDAG &DAG) const {
   SDValue Root = Op.getOperand(0);
   SDValue Trmp = Op.getOperand(1); // trampoline
   SDValue FPtr = Op.getOperand(2); // nested function
@@ -9471,9 +9477,7 @@
                                 MachinePointerInfo(TrmpAddr, 22),
                                 false, false, 0);
 
-    SDValue Ops[] =
-      { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
-    return DAG.getMergeValues(Ops, 2, dl);
+    return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
   } else {
     const Function *Func =
       cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
@@ -9553,9 +9557,7 @@
                                 MachinePointerInfo(TrmpAddr, 6),
                                 false, false, 1);
 
-    SDValue Ops[] =
-      { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
-    return DAG.getMergeValues(Ops, 2, dl);
+    return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
   }
 }
 
@@ -10356,7 +10358,8 @@
                                 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
   case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
   case ISD::EH_RETURN:          return LowerEH_RETURN(Op, DAG);
-  case ISD::TRAMPOLINE:         return LowerTRAMPOLINE(Op, DAG);
+  case ISD::INIT_TRAMPOLINE:    return LowerINIT_TRAMPOLINE(Op, DAG);
+  case ISD::ADJUST_TRAMPOLINE:  return LowerADJUST_TRAMPOLINE(Op, DAG);
   case ISD::FLT_ROUNDS_:        return LowerFLT_ROUNDS_(Op, DAG);
   case ISD::CTLZ:               return LowerCTLZ(Op, DAG);
   case ISD::CTTZ:               return LowerCTTZ(Op, DAG);

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Sep  6 08:37:06 2011
@@ -821,7 +821,8 @@
     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Sep  6 08:37:06 2011
@@ -147,7 +147,8 @@
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
 
   // TRAMPOLINE is custom lowered.
-  setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
+  setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
+  setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
 
   maxStoresPerMemset = maxStoresPerMemsetOptSize = 4;
   maxStoresPerMemmove = maxStoresPerMemmoveOptSize
@@ -180,7 +181,8 @@
   case ISD::ADD:
   case ISD::SUB:              return ExpandADDSUB(Op.getNode(), DAG);
   case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
-  case ISD::TRAMPOLINE:       return LowerTRAMPOLINE(Op, DAG);
+  case ISD::INIT_TRAMPOLINE:  return LowerINIT_TRAMPOLINE(Op, DAG);
+  case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
   default:
     llvm_unreachable("unimplemented operand");
     return SDValue();
@@ -789,7 +791,12 @@
 }
 
 SDValue XCoreTargetLowering::
-LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
+LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
+  return Op.getOperand(0);
+}
+
+SDValue XCoreTargetLowering::
+LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
   SDValue Chain = Op.getOperand(0);
   SDValue Trmp = Op.getOperand(1); // trampoline
   SDValue FPtr = Op.getOperand(2); // nested function
@@ -841,9 +848,7 @@
                               MachinePointerInfo(TrmpAddr, 16), false, false,
                               0);
 
-  SDValue Ops[] =
-    { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5) };
-  return DAG.getMergeValues(Ops, 2, dl);
+  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.h?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Tue Sep  6 08:37:06 2011
@@ -145,7 +145,8 @@
     SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
 
     // Inline asm support
     std::pair<unsigned, const TargetRegisterClass*>

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombine.h?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombine.h (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombine.h Tue Sep  6 08:37:06 2011
@@ -11,6 +11,7 @@
 #define INSTCOMBINE_INSTCOMBINE_H
 
 #include "InstCombineWorklist.h"
+#include "llvm/IntrinsicInst.h"
 #include "llvm/Operator.h"
 #include "llvm/Pass.h"
 #include "llvm/Analysis/ValueTracking.h"
@@ -214,7 +215,8 @@
   Instruction *visitCallSite(CallSite CS);
   Instruction *tryOptimizeCall(CallInst *CI, const TargetData *TD);
   bool transformConstExprCastCall(CallSite CS);
-  Instruction *transformCallThroughTrampoline(CallSite CS);
+  Instruction *transformCallThroughTrampoline(CallSite CS,
+                                              IntrinsicInst *Tramp);
   Instruction *transformZExtICmp(ICmpInst *ICI, Instruction &CI,
                                  bool DoXform = true);
   Instruction *transformSExtICmp(ICmpInst *ICI, Instruction &CI);

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Tue Sep  6 08:37:06 2011
@@ -12,7 +12,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "InstCombine.h"
-#include "llvm/IntrinsicInst.h"
 #include "llvm/Support/CallSite.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Analysis/MemoryBuiltins.h"
@@ -821,6 +820,83 @@
   return Simplifier.NewInstruction;
 }
 
+static IntrinsicInst *FindInitTrampolineFromAlloca(Value *TrampMem) {
+  // Strip off at most one level of pointer casts, looking for an alloca.  This
+  // is good enough in practice and simpler than handling any number of casts.
+  Value *Underlying = TrampMem->stripPointerCasts();
+  if (Underlying != TrampMem &&
+      (!Underlying->hasOneUse() || *Underlying->use_begin() != TrampMem))
+    return 0;
+  if (!isa<AllocaInst>(Underlying))
+    return 0;
+
+  IntrinsicInst *InitTrampoline = 0;
+  for (Value::use_iterator I = TrampMem->use_begin(), E = TrampMem->use_end();
+       I != E; I++) {
+    IntrinsicInst *II = dyn_cast<IntrinsicInst>(*I);
+    if (!II)
+      return 0;
+    if (II->getIntrinsicID() == Intrinsic::init_trampoline) {
+      if (InitTrampoline)
+        // More than one init_trampoline writes to this value.  Give up.
+        return 0;
+      InitTrampoline = II;
+      continue;
+    }
+    if (II->getIntrinsicID() == Intrinsic::adjust_trampoline)
+      // Allow any number of calls to adjust.trampoline.
+      continue;
+    return 0;
+  }
+
+  // No call to init.trampoline found.
+  if (!InitTrampoline)
+    return 0;
+
+  // Check that the alloca is being used in the expected way.
+  if (InitTrampoline->getOperand(0) != TrampMem)
+    return 0;
+
+  return InitTrampoline;
+}
+
+static IntrinsicInst *FindInitTrampolineFromBB(IntrinsicInst *AdjustTramp,
+                                               Value *TrampMem) {
+  // Visit all the previous instructions in the basic block, and try to find a
+  // init.trampoline which has a direct path to the adjust.trampoline.
+  for (BasicBlock::iterator I = AdjustTramp,
+       E = AdjustTramp->getParent()->begin(); I != E; ) {
+    Instruction *Inst = --I;
+    if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
+      if (II->getIntrinsicID() == Intrinsic::init_trampoline &&
+          II->getOperand(0) == TrampMem)
+        return II;
+    if (Inst->mayWriteToMemory())
+      return 0;
+  }
+  return 0;
+}
+
+// Given a call to llvm.adjust.trampoline, find and return the corresponding
+// call to llvm.init.trampoline if the call to the trampoline can be optimized
+// to a direct call to a function.  Otherwise return NULL.
+//
+static IntrinsicInst *FindInitTrampoline(Value *Callee) {
+  Callee = Callee->stripPointerCasts();
+  IntrinsicInst *AdjustTramp = dyn_cast<IntrinsicInst>(Callee);
+  if (!AdjustTramp ||
+      AdjustTramp->getIntrinsicID() != Intrinsic::adjust_trampoline)
+    return 0;
+
+  Value *TrampMem = AdjustTramp->getOperand(0);
+
+  if (IntrinsicInst *IT = FindInitTrampolineFromAlloca(TrampMem))
+    return IT;
+  if (IntrinsicInst *IT = FindInitTrampolineFromBB(AdjustTramp, TrampMem))
+    return IT;
+  return 0;
+}
+
 // visitCallSite - Improvements for call and invoke instructions.
 //
 Instruction *InstCombiner::visitCallSite(CallSite CS) {
@@ -880,10 +956,8 @@
     return EraseInstFromFunction(*CS.getInstruction());
   }
 
-  if (BitCastInst *BC = dyn_cast<BitCastInst>(Callee))
-    if (IntrinsicInst *In = dyn_cast<IntrinsicInst>(BC->getOperand(0)))
-      if (In->getIntrinsicID() == Intrinsic::init_trampoline)
-        return transformCallThroughTrampoline(CS);
+  if (IntrinsicInst *II = FindInitTrampoline(Callee))
+    return transformCallThroughTrampoline(CS, II);
 
   PointerType *PTy = cast<PointerType>(Callee->getType());
   FunctionType *FTy = cast<FunctionType>(PTy->getElementType());
@@ -1164,10 +1238,13 @@
   return true;
 }
 
-// transformCallThroughTrampoline - Turn a call to a function created by the
-// init_trampoline intrinsic into a direct call to the underlying function.
+// transformCallThroughTrampoline - Turn a call to a function created by
+// init_trampoline / adjust_trampoline intrinsic pair into a direct call to the
+// underlying function.
 //
-Instruction *InstCombiner::transformCallThroughTrampoline(CallSite CS) {
+Instruction *
+InstCombiner::transformCallThroughTrampoline(CallSite CS,
+                                             IntrinsicInst *Tramp) {
   Value *Callee = CS.getCalledValue();
   PointerType *PTy = cast<PointerType>(Callee->getType());
   FunctionType *FTy = cast<FunctionType>(PTy->getElementType());
@@ -1178,8 +1255,8 @@
   if (Attrs.hasAttrSomewhere(Attribute::Nest))
     return 0;
 
-  IntrinsicInst *Tramp =
-    cast<IntrinsicInst>(cast<BitCastInst>(Callee)->getOperand(0));
+  assert(Tramp &&
+         "transformCallThroughTrampoline called with incorrect CallSite.");
 
   Function *NestF =cast<Function>(Tramp->getArgOperand(1)->stripPointerCasts());
   PointerType *NestFPTy = cast<PointerType>(NestF->getType());

Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original)
+++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Tue Sep  6 08:37:06 2011
@@ -43,6 +43,26 @@
   
   switch (Name[0]) {
   default: break;
+  case 'i':
+    //  This upgrades the old llvm.init.trampoline to the new
+    //  llvm.init.trampoline and llvm.adjust.trampoline pair.
+    if (Name == "init.trampoline") {
+      // The new llvm.init.trampoline returns nothing.
+      if (FTy->getReturnType()->isVoidTy())
+        break;
+
+      assert(FTy->getNumParams() == 3 && "old init.trampoline takes 3 args!");
+
+      // Change the name of the old intrinsic so that we can play with its type.
+      std::string NameTmp = F->getName();
+      F->setName("");
+      NewFn = cast<Function>(M->getOrInsertFunction(
+                               NameTmp,
+                               Type::getVoidTy(M->getContext()),
+                               FTy->getParamType(0), FTy->getParamType(1),
+                               FTy->getParamType(2), (Type *)0));
+      return true;
+    }
   case 'p':
     //  This upgrades the llvm.prefetch intrinsic to accept one more parameter,
     //  which is a instruction / data cache identifier. The old version only
@@ -216,6 +236,32 @@
     CI->eraseFromParent();
     break;
   }
+  case Intrinsic::init_trampoline: {
+
+    //  Transform
+    //    %tramp = call i8* llvm.init.trampoline (i8* x, i8* y, i8* z)
+    //  to
+    //    call void llvm.init.trampoline (i8* %x, i8* %y, i8* %z)
+    //    %tramp = call i8* llvm.adjust.trampoline (i8* %x)
+
+    Function *AdjustTrampolineFn =
+      cast<Function>(Intrinsic::getDeclaration(F->getParent(),
+                                               Intrinsic::adjust_trampoline));
+
+    IRBuilder<> Builder(C);
+    Builder.SetInsertPoint(CI);
+
+    Builder.CreateCall3(NewFn, CI->getArgOperand(0), CI->getArgOperand(1),
+                        CI->getArgOperand(2));
+
+    CallInst *AdjustCall = Builder.CreateCall(AdjustTrampolineFn,
+                                              CI->getArgOperand(0),
+                                              CI->getName());
+    if (!CI->use_empty())
+      CI->replaceAllUsesWith(AdjustCall);
+    CI->eraseFromParent();
+    break;
+  }
   }
 }
 

Modified: llvm/trunk/test/Assembler/AutoUpgradeIntrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/AutoUpgradeIntrinsics.ll?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/test/Assembler/AutoUpgradeIntrinsics.ll (original)
+++ llvm/trunk/test/Assembler/AutoUpgradeIntrinsics.ll Tue Sep  6 08:37:06 2011
@@ -40,3 +40,16 @@
   tail call void @llvm.prefetch(i8* %ptr, i32 0, i32 1)
   ret void
 }
+
+declare i32 @nest_f(i8* nest, i32)
+declare i8* @llvm.init.trampoline(i8*, i8*, i8*)
+
+define void @test_trampolines() {
+; CHECK: call void @llvm.init.trampoline(i8* null, i8* bitcast (i32 (i8*, i32)* @nest_f to i8*), i8* null)
+; CHECK: call i8* @llvm.adjust.trampoline(i8* null)
+
+  call i8* @llvm.init.trampoline(i8* null,
+                                 i8* bitcast (i32 (i8*, i32)* @nest_f to i8*),
+                                 i8* null)
+  ret void
+}

Modified: llvm/trunk/test/CodeGen/PowerPC/trampoline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/trampoline.ll?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/trampoline.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/trampoline.ll Tue Sep  6 08:37:06 2011
@@ -67,7 +67,8 @@
 	store %struct.NSBitmapImageRep* %4, %struct.NSBitmapImageRep** %3, align 4
 	%TRAMP.91 = bitcast %struct.__builtin_trampoline* %TRAMP.9 to i8*		; <i8*> [#uses=1]
 	%FRAME.72 = bitcast %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7 to i8*		; <i8*> [#uses=1]
-	%tramp = call i8* @llvm.init.trampoline(i8* %TRAMP.91, i8* bitcast (void (%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*, %struct.__block_1*, %struct.CGImage*)* @__helper_1.1632 to i8*), i8* %FRAME.72)		; <i8*> [#uses=1]
+	call void @llvm.init.trampoline(i8* %TRAMP.91, i8* bitcast (void (%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*, %struct.__block_1*, %struct.CGImage*)* @__helper_1.1632 to i8*), i8* %FRAME.72)		; <i8*> [#uses=1]
+        %tramp = call i8* @llvm.adjust.trampoline(i8* %TRAMP.91)
 	store i8* %tramp, i8** %0, align 4
 	%5 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 1		; <void (%struct.__block_1*, %struct.CGImage*)**> [#uses=1]
 	%6 = load i8** %0, align 4		; <i8*> [#uses=1]
@@ -113,7 +114,8 @@
 	ret %struct.objc_object* %retval5
 }
 
-declare i8* @llvm.init.trampoline(i8*, i8*, i8*) nounwind
+declare void @llvm.init.trampoline(i8*, i8*, i8*) nounwind
+declare i8* @llvm.adjust.trampoline(i8*) nounwind
 
 define internal void @__helper_1.1632(%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* nest %CHAIN.8, %struct.__block_1* %_self, %struct.CGImage* %cgImage) nounwind {
 entry:

Modified: llvm/trunk/test/CodeGen/XCore/trampoline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/trampoline.ll?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/trampoline.ll (original)
+++ llvm/trunk/test/CodeGen/XCore/trampoline.ll Tue Sep  6 08:37:06 2011
@@ -11,7 +11,8 @@
   %FRAME.0 = alloca %struct.FRAME.f, align 4
   %TRAMP.23.sub = getelementptr inbounds [20 x i8]* %TRAMP.23, i32 0, i32 0
   %FRAME.02 = bitcast %struct.FRAME.f* %FRAME.0 to i8*
-  %tramp = call i8* @llvm.init.trampoline(i8* %TRAMP.23.sub, i8* bitcast (i32 (%struct.FRAME.f*)* @g.1101 to i8*), i8* %FRAME.02)
+  call void @llvm.init.trampoline(i8* %TRAMP.23.sub, i8* bitcast (i32 (%struct.FRAME.f*)* @g.1101 to i8*), i8* %FRAME.02)
+  %tramp = call i8* @llvm.adjust.trampoline(i8* %TRAMP.23.sub)
   %0 = getelementptr inbounds %struct.FRAME.f* %FRAME.0, i32 0, i32 1
   %1 = bitcast i8* %tramp to i32 ()*
   store i32 ()* %1, i32 ()** %0, align 4
@@ -32,6 +33,7 @@
   ret i32 %1
 }
 
-declare i8* @llvm.init.trampoline(i8*, i8*, i8*) nounwind
+declare void @llvm.init.trampoline(i8*, i8*, i8*) nounwind
+declare i8* @llvm.adjust.trampoline(i8*) nounwind
 
 declare void @h(i32 ()*)

Modified: llvm/trunk/test/Transforms/InstCombine/2008-01-14-VarArgTrampoline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2008-01-14-VarArgTrampoline.ll?rev=139140&r1=139139&r2=139140&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/2008-01-14-VarArgTrampoline.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/2008-01-14-VarArgTrampoline.ll Tue Sep  6 08:37:06 2011
@@ -3,7 +3,8 @@
 	%struct.FRAME.nest = type { i32, i32 (...)* }
 	%struct.__builtin_trampoline = type { [10 x i8] }
 
-declare i8* @llvm.init.trampoline(i8*, i8*, i8*) nounwind 
+declare void @llvm.init.trampoline(i8*, i8*, i8*) nounwind 
+declare i8* @llvm.adjust.trampoline(i8*) nounwind
 
 declare i32 @f(%struct.FRAME.nest* nest , ...)
 
@@ -15,7 +16,8 @@
 	%tmp3 = getelementptr %struct.FRAME.nest* %FRAME.0, i32 0, i32 0		; <i32*> [#uses=1]
 	store i32 %n, i32* %tmp3, align 8
 	%FRAME.06 = bitcast %struct.FRAME.nest* %FRAME.0 to i8*		; <i8*> [#uses=1]
-	%tramp = call i8* @llvm.init.trampoline( i8* %TRAMP.216.sub, i8* bitcast (i32 (%struct.FRAME.nest*, ...)* @f to i8*), i8* %FRAME.06 )		; <i8*> [#uses=1]
+	call void @llvm.init.trampoline( i8* %TRAMP.216.sub, i8* bitcast (i32 (%struct.FRAME.nest*, ...)* @f to i8*), i8* %FRAME.06 )		; <i8*> [#uses=1]
+        %tramp = call i8* @llvm.adjust.trampoline( i8* %TRAMP.216.sub)
 	%tmp7 = getelementptr %struct.FRAME.nest* %FRAME.0, i32 0, i32 1		; <i32 (...)**> [#uses=1]
 	%tmp89 = bitcast i8* %tramp to i32 (...)*		; <i32 (...)*> [#uses=2]
 	store i32 (...)* %tmp89, i32 (...)** %tmp7, align 8



From baldrick at free.fr  Tue Sep  6 08:37:38 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 06 Sep 2011 13:37:38 -0000
Subject: [llvm-commits] [dragonegg] r139141 -
	/dragonegg/trunk/src/Convert.cpp
Message-ID: <20110906133739.009962A6C12C@llvm.org>

Author: baldrick
Date: Tue Sep  6 08:37:38 2011
New Revision: 139141

URL: http://llvm.org/viewvc/llvm-project?rev=139141&view=rev
Log:
Use the new trampoline intrinsics.  Since they correspond exactly
to the GCC intrinsics this basically just means deleting a bunch
of hacks.  Patch mostly by Sanjoy Das.

Modified:
    dragonegg/trunk/src/Convert.cpp

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=139141&r1=139140&r2=139141&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Tue Sep  6 08:37:38 2011
@@ -5309,20 +5309,11 @@
   if (!validate_gimple_arglist(stmt, POINTER_TYPE, VOID_TYPE))
     return false;
 
-  Type *ResultTy = ConvertType(gimple_call_return_type(stmt));
-
-  // The adjusted value is stored as a pointer at the start of the storage GCC
-  // allocated for the trampoline - load it out and return it.
-  assert(TD.getPointerSize() <= TRAMPOLINE_SIZE &&
-         "Trampoline smaller than a pointer!");
-  Value *Tramp = EmitMemory(gimple_call_arg(stmt, 0));
-  Tramp = Builder.CreateBitCast(Tramp, ResultTy->getPointerTo());
-  Result = Builder.CreateLoad(Tramp, "adjusted");
-
-  // The load has the alignment of the trampoline storage.
-  unsigned Align = TYPE_ALIGN(TREE_TYPE(TREE_TYPE(gimple_call_arg(stmt, 0))))/8;
-  cast<LoadInst>(Result)->setAlignment(Align);
-
+  Function *Intr = Intrinsic::getDeclaration(TheModule,
+                                             Intrinsic::adjust_trampoline);
+  Value *Arg = Builder.CreateBitCast(EmitRegister(gimple_call_arg(stmt, 0)),
+                                     Builder.getInt8PtrTy());
+  Result = Builder.CreateCall(Intr, Arg);
   return true;
 }
 
@@ -5331,57 +5322,20 @@
                          VOID_TYPE))
     return false;
 
-  // LLVM's trampoline intrinsic, llvm.init.trampoline, combines the effect of
-  // GCC's init_trampoline and adjust_trampoline.  Calls to adjust_trampoline
-  // should return the result of the llvm.init.trampoline call.  This is tricky
-  // because the adjust_trampoline and init_trampoline calls need not occur in
-  // the same function.  To overcome this, we don't store the trampoline machine
-  // code in the storage GCC created for it, we store the result of the call to
-  // llvm.init.trampoline there instead.  Since this storage is the argument to
-  // adjust_trampoline, we turn adjust_trampoline into a load from its argument.
-  // The trampoline machine code itself is stored in a stack temporary that we
-  // create (one for each init_trampoline) in the function where init_trampoline
-  // is called.
-  static Type *VPTy = Type::getInt8PtrTy(Context);
-
-  // Create a stack temporary to hold the trampoline machine code.
-  Type *TrampType = ArrayType::get(Type::getInt8Ty(Context),
-                                         TRAMPOLINE_SIZE);
-  AllocaInst *TrampTmp = CreateTemporary(TrampType);
-  TrampTmp->setAlignment(TRAMPOLINE_ALIGNMENT);
-  TrampTmp->setName("TRAMP");
-
-  Value *Func = EmitMemory(gimple_call_arg(stmt, 1));
-  Value *Chain = EmitMemory(gimple_call_arg(stmt, 2));
+  Value *Tramp = EmitRegister(gimple_call_arg(stmt, 0));
+  Value *Func = EmitRegister(gimple_call_arg(stmt, 1));
+  Value *Chain = EmitRegister(gimple_call_arg(stmt, 2));
 
+  Type *VPTy = Builder.getInt8PtrTy();
   Value *Ops[3] = {
-    Builder.CreateBitCast(TrampTmp, VPTy),
+    Builder.CreateBitCast(Tramp, VPTy),
     Builder.CreateBitCast(Func, VPTy),
     Builder.CreateBitCast(Chain, VPTy)
   };
 
   Function *Intr = Intrinsic::getDeclaration(TheModule,
                                              Intrinsic::init_trampoline);
-  Value *Adjusted = Builder.CreateCall(Intr, Ops, "adjusted");
-
-  // Store the llvm.init.trampoline result to the GCC trampoline storage.
-  assert(TD.getPointerSize() <= TRAMPOLINE_SIZE &&
-         "Trampoline smaller than a pointer!");
-  Value *Tramp = EmitMemory(gimple_call_arg(stmt, 0));
-  Tramp = Builder.CreateBitCast(Tramp, Adjusted->getType()->getPointerTo());
-  StoreInst *Store = Builder.CreateStore(Adjusted, Tramp);
-
-  // The store has the alignment of the trampoline storage.
-  unsigned Align = TYPE_ALIGN(TREE_TYPE(TREE_TYPE(gimple_call_arg(stmt, 0))))/8;
-  Store->setAlignment(Align);
-
-  // The GCC trampoline storage is constant from this point on.   Tell this to
-  // the optimizers.
-  Intr = Intrinsic::getDeclaration(TheModule, Intrinsic::invariant_start);
-  Ops[0] = Builder.getInt64(TRAMPOLINE_SIZE);
-  Ops[1] = Builder.CreateBitCast(Tramp, VPTy);
-  Builder.CreateCall(Intr, ArrayRef<Value *>(Ops, 2));
-
+  Builder.CreateCall(Intr, Ops);
   return true;
 }
 



From baldrick at free.fr  Tue Sep  6 10:05:17 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 06 Sep 2011 15:05:17 -0000
Subject: [llvm-commits] [dragonegg] r139142 -
	/dragonegg/trunk/src/Backend.cpp
Message-ID: <20110906150517.766C22A6C12C@llvm.org>

Author: baldrick
Date: Tue Sep  6 10:05:17 2011
New Revision: 139142

URL: http://llvm.org/viewvc/llvm-project?rev=139142&view=rev
Log:
Enable segmented stacks when compiling Go.

Modified:
    dragonegg/trunk/src/Backend.cpp

Modified: dragonegg/trunk/src/Backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=139142&r1=139141&r2=139142&view=diff
==============================================================================
--- dragonegg/trunk/src/Backend.cpp (original)
+++ dragonegg/trunk/src/Backend.cpp Tue Sep  6 10:05:17 2011
@@ -322,6 +322,10 @@
     Args.push_back("--ffunction-sections");
   if (flag_data_sections)
     Args.push_back("--fdata-sections");
+#if (GCC_MINOR > 5)
+  if (flag_split_stack)
+    Args.push_back("--segmented-stacks");
+#endif
 
   // If there are options that should be passed through to the LLVM backend
   // directly from the command line, do so now.  This is mainly for debugging



From echristo at apple.com  Tue Sep  6 11:11:30 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 06 Sep 2011 09:11:30 -0700
Subject: [llvm-commits] [llvm] r139067 -
 /llvm/trunk/lib/Target/X86/X86InstrSSE.td
In-Reply-To: <20110903004654.3B03F2A6C12F@llvm.org>
References: <20110903004654.3B03F2A6C12F@llvm.org>
Message-ID: <B59D7CE9-F02B-4200-A8F2-E59C5B99ED15@apple.com>


On Sep 2, 2011, at 5:46 PM, Bruno Cardoso Lopes wrote:

> Author: bruno
> Date: Fri Sep  2 19:46:54 2011
> New Revision: 139067
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=139067&view=rev
> Log:
> Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}

Testcases for all of these? :)

-eric

From echristo at apple.com  Tue Sep  6 11:27:16 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 06 Sep 2011 09:27:16 -0700
Subject: [llvm-commits] [llvm] r138831 -
 /llvm/trunk/test/CodeGen/X86/segmented-stacks.ll
In-Reply-To: <4E62F011.9040408@gmail.com>
References: <20110830211937.5D7532A6C12C@llvm.org>
	<117CD29F-7FA4-4729-B7BC-A45FBC78B0C0@apple.com>
	<4E5D6B9D.7040101@gmail.com>
	<BD4849D3-1A34-4B88-A791-C79621364362@apple.com>
	<4E62F011.9040408@gmail.com>
Message-ID: <33AD5E1A-57ED-45DB-92D4-D266E9E30813@apple.com>


On Sep 3, 2011, at 8:27 PM, Rafael ?vila de Esp?ndola wrote:

>> The first darwin failure after r138821 was:
>> Assertion failed: (!Subtarget->isTargetEnvMacho()), function LowerDYNAMIC_STACKALLOC, file .../llvm/lib/Target/X86/X86ISelLowering.cpp, line 8853.
> 
> Sorry for taking so long to reply.
> 
> The attached patch turns the assert into a fatal error. Is it OK?

Sure. Can you also add a check in X86Subtarget similar to the 64-bit problem to verify that no one has asked for it as well on targets that aren't supported?

-eric

From eli.friedman at gmail.com  Tue Sep  6 11:48:59 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 6 Sep 2011 09:48:59 -0700
Subject: [llvm-commits] [llvm] r139138 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
In-Reply-To: <20110906065600.5230D2A6C12C@llvm.org>
References: <20110906065600.5230D2A6C12C@llvm.org>
Message-ID: <CAJdarcEyWMZw7Lr2JF6KW3SHtoqd3tzT+7ajoYgB=yZNrEhpWg@mail.gmail.com>

On Mon, Sep 5, 2011 at 11:56 PM, Nick Lewycky <nicholas at mxc.ca> wrote:
> Author: nicholas
> Date: Tue Sep ?6 01:56:00 2011
> New Revision: 139138
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139138&view=rev
> Log:
> Apparently we compile the code, not the comments. Thanks Eli!

Sure. :)

BTW, please commit a test for this...

-Eli

> Modified:
> ? ?llvm/trunk/lib/Analysis/ScalarEvolution.cpp
>
> Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139138&r1=139137&r2=139138&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
> +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep ?6 01:56:00 2011
> @@ -1998,8 +1998,7 @@
> ? ? ? ? ? ? ? const SCEV *NewStart = getMulExpr(A, C);
> ? ? ? ? ? ? ? const SCEV *BD = getMulExpr(B, D);
> ? ? ? ? ? ? ? const SCEV *NewStep = getAddExpr(getMulExpr(A, D),
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? getMulExpr(B, C),
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? getNegativeSCEV(BD));
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? getMulExpr(B, C), BD);
> ? ? ? ? ? ? ? const SCEV *NewSecondOrderStep =
> ? ? ? ? ? ? ? ? ? getMulExpr(BD, getConstant(BD->getType(), 2));
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From grosbach at apple.com  Tue Sep  6 11:50:54 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 09:50:54 -0700
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and	resolve
 (safe) ambiguous instruction encodings
In-Reply-To: <AF10579E-4931-410D-9B6E-F35C1248240F@mac.com>
References: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>
	<F01D8B85CFF58440B2A13965FBA90CA473757133DD@GEORGE.Emea.Arm.com>
	<AF10579E-4931-410D-9B6E-F35C1248240F@mac.com>
Message-ID: <CC29118F-81C7-4345-909C-CB4B535DE4B0@apple.com>

Ditto. It was a holiday weekend over here, so folks have been offline for the most part.

-j
On Sep 5, 2011, at 11:29 AM, Owen Anderson wrote:

> I'm planning to look at this, but haven't had a chance yet.
> 
> --Owen
> 
> On Sep 5, 2011, at 11:00 AM, James Molloy wrote:
> 
>> Ping?
>> ________________________________________
>> From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of James Molloy [james.molloy at arm.com]
>> Sent: 02 September 2011 16:38
>> To: llvm-commits at cs.uiuc.edu
>> Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve  (safe) ambiguous instruction encodings
>> 
>> Hi,
>> 
>> The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M series
>> not allowing the correct mask names.
>> 
>> The patch becomes difficult because:
>> * There is no way to determine in the InstPrinter any subtarget specific
>> features (such as "operating on an m-class core?").
>> * There is currently no subtarget feature for "M-class core?"; the nearest is
>> IsThumb2 && !HasARM.
>> * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
>> a way that makes them deterministically separable. This causes non-conflicting
>> ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
>> both code paths are emitted but only one will ever be hit.
>> 
>> The solution is:
>> * Add subtarget info to InstPrinter so it can determine what to do with the
>> mask immediate.
>> * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
>> IsARClass == !IsMClass. This feature only has semantic sense on v6+
>> architectures.
>> * The conflicts occur because the FixedLenDecoderEmitter does not honour the
>> Predicates field of instructions in the tablegen description. If the island
>> checking also checked the AssemblerPredicates field (if defined), ambiguous
>> instruction encodings that are disambiguated by predicates would (do) work fine.
>> 
>> The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and MCDisassembler.
>> They can use this (in patch #2) to determine what mask names to accept (primask?
>> or cpsr_zxvf?)
>> 
>> The second enhances FixedLenPredicateEncoder to emit predicate checks for
>> instructions before it accepts an encoding - this allows ambiguous instructions
>> to be disambiguated by the Predicates field in TableGen. This required changing
>> llvm-mc to accept -mattr, and tests to set the correct features they rely upon.
>> 
>> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
>> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
>> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
>> is created.**
>> 
>> The third patch adds a new predicate "IsMClass" along with its counterpart
>> "IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
>> Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
>> encodings respectively. It also fixes mask printing for MRS/MSR in the
>> ARMMCInstPrinter and ARMMCAsmParser.
>> 
>> Testcases added with the final patch.
>> 
>> Comments? Is it OK?
>> 
>> Cheers,
>> 
>> James
>> 
>> [N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout myself
>> after review]
>> 
>> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> _______________________________________________
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> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From grosbach at apple.com  Tue Sep  6 12:05:38 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 10:05:38 -0700
Subject: [llvm-commits] [llvm] r139125 - in /llvm/trunk/lib/Target:
 ARM/ARM.td ARM/ARMInstrInfo.td ARM/ARMSubtarget.cpp ARM/ARMSubtarget.h
 ARM/MCTargetDesc/ARMMCTargetDesc.cpp X86/MCTargetDesc/X86MCTargetDesc.cpp
 X86/X86.td X86/X86InstrInfo.td X86/X86Subtarget.cpp X86/X86Subtarget.h
In-Reply-To: <20110905215143.A17032A6C12C@llvm.org>
References: <20110905215143.A17032A6C12C@llvm.org>
Message-ID: <79B5A5D3-E8C4-4768-8C9B-58C526765027@apple.com>

Hi Nick,

I have a few concerns about this that hopefully won't be too hard to alleviate. On the more trite side, we generally try to keep the nomenclature descriptive of purpose rather than of use. This patch names the sub-target feature according to purpose (native client) and doesn't give any indication of what it actually does. Is this really a sub-target feature at all? Honestly, my general impression is that this is more accurately a target platform in the triple akin to Linux or Darwin. For example, thumbv7-unknown-nacl. Assuming so (and it looks like that is indeed how it's specified?), why isn't querying the triple directly a-la ARMSubtarget->isTargetDarwin(), sufficient? Lastly, speculating here as this patch doesn't go into these details, but be very careful with alignment changes in code sections, as the ARM backend is very sensitive to small changes. Specifically, the constant island pass tracks instruction alignment and relative distances as exactly as it can, and will need to be taught how to deal with these changes.

-Jim

On Sep 5, 2011, at 2:51 PM, Nick Lewycky wrote:

> Author: nicholas
> Date: Mon Sep  5 16:51:43 2011
> New Revision: 139125
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=139125&view=rev
> Log:
> Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
> instructions are more aligned than the CPU requires, and adds some additional
> directives, to follow in future patches. Patch by David Meyer!
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARM.td
>    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>    llvm/trunk/lib/Target/ARM/ARMSubtarget.h
>    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
>    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
>    llvm/trunk/lib/Target/X86/X86.td
>    llvm/trunk/lib/Target/X86/X86InstrInfo.td
>    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
>    llvm/trunk/lib/Target/X86/X86Subtarget.h
> 
> Modified: llvm/trunk/lib/Target/ARM/ARM.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=139125&r1=139124&r2=139125&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARM.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARM.td Mon Sep  5 16:51:43 2011
> @@ -23,6 +23,9 @@
> def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
>                                   "Thumb mode">;
> 
> +def ModeNaCl   : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
> +                                  "Native client mode">;
> +
> //===----------------------------------------------------------------------===//
> // ARM Subtarget features.
> //
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep  5 16:51:43 2011
> @@ -209,6 +209,8 @@
>                                  AssemblerPredicate<"!ModeThumb">;
> def IsDarwin         : Predicate<"Subtarget->isTargetDarwin()">;
> def IsNotDarwin      : Predicate<"!Subtarget->isTargetDarwin()">;
> +def IsNaCl           : Predicate<"Subtarget->isTargetNaCl()">,
> +                                 AssemblerPredicate<"ModeNaCl">;
> 
> // FIXME: Eventually this will be just "hasV6T2Ops".
> def UseMovt          : Predicate<"Subtarget->useMovt()">;
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Sep  5 16:51:43 2011
> @@ -53,6 +53,7 @@
>   , HasVMLxForwarding(false)
>   , SlowFPBrcc(false)
>   , InThumbMode(false)
> +  , InNaClMode(false)
>   , HasThumb2(false)
>   , NoARM(false)
>   , PostRAScheduler(false)
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=139125&r1=139124&r2=139125&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Sep  5 16:51:43 2011
> @@ -70,6 +70,9 @@
>   /// InThumbMode - True if compiling for Thumb, false for ARM.
>   bool InThumbMode;
> 
> +  /// InNaClMode - True if targeting Native Client
> +  bool InNaClMode;
> +
>   /// HasThumb2 - True if Thumb2 instructions are supported.
>   bool HasThumb2;
> 
> @@ -209,6 +212,9 @@
>   const Triple &getTargetTriple() const { return TargetTriple; }
> 
>   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
> +  bool isTargetNaCl() const {
> +    return TargetTriple.getOS() == Triple::NativeClient;
> +  }
>   bool isTargetELF() const { return !isTargetDarwin(); }
> 
>   bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
> 
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Sep  5 16:51:43 2011
> @@ -86,6 +86,14 @@
>       ARMArchFeature += ",+thumb-mode";
>   }
> 
> +  Triple TheTriple(TT);
> +  if (TheTriple.getOS() == Triple::NativeClient) {
> +    if (ARMArchFeature.empty())
> +      ARMArchFeature = "+nacl-mode";
> +    else
> +      ARMArchFeature += ",+nacl-mode";
> +  }
> +
>   return ARMArchFeature;
> }
> 
> 
> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Sep  5 16:51:43 2011
> @@ -40,9 +40,16 @@
> 
> std::string X86_MC::ParseX86Triple(StringRef TT) {
>   Triple TheTriple(TT);
> +  std::string FS;
>   if (TheTriple.getArch() == Triple::x86_64)
> -    return "+64bit-mode";
> -  return "-64bit-mode";
> +    FS = "+64bit-mode";
> +  else
> +    FS = "-64bit-mode";
> +  if (TheTriple.getOS() == Triple::NativeClient)
> +    FS += ",+nacl-mode";
> +  else
> +    FS += ",-nacl-mode";
> +  return FS;
> }
> 
> /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
> 
> Modified: llvm/trunk/lib/Target/X86/X86.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=139125&r1=139124&r2=139125&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86.td (original)
> +++ llvm/trunk/lib/Target/X86/X86.td Mon Sep  5 16:51:43 2011
> @@ -23,6 +23,9 @@
> def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
>                                   "64-bit mode (x86_64)">;
> 
> +def ModeNaCl  : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
> +                                 "Native Client mode">;
> +
> //===----------------------------------------------------------------------===//
> // X86 Subtarget features.
> //===----------------------------------------------------------------------===//
> 
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep  5 16:51:43 2011
> @@ -482,6 +482,14 @@
>                              AssemblerPredicate<"Mode64Bit">;
> def IsWin64      : Predicate<"Subtarget->isTargetWin64()">;
> def NotWin64     : Predicate<"!Subtarget->isTargetWin64()">;
> +def IsNaCl       : Predicate<"Subtarget->isTargetNaCl()">,
> +                             AssemblerPredicate<"ModeNaCl">;
> +def IsNaCl32     : Predicate<"Subtarget->isTargetNaCl32()">,
> +                             AssemblerPredicate<"ModeNaCl,!Mode64Bit">;
> +def IsNaCl64     : Predicate<"Subtarget->isTargetNaCl64()">,
> +                             AssemblerPredicate<"ModeNaCl,Mode64Bit">;
> +def NotNaCl      : Predicate<"!Subtarget->isTargetNaCl()">,
> +                             AssemblerPredicate<"!ModeNaCl">;
> def SmallCode    : Predicate<"TM.getCodeModel() == CodeModel::Small">;
> def KernelCode   : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
> def FarData      : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
> 
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Sep  5 16:51:43 2011
> @@ -260,7 +260,8 @@
>   // FIXME: this is a known good value for Yonah. How about others?
>   , MaxInlineSizeThreshold(128)
>   , TargetTriple(TT)
> -  , In64BitMode(is64Bit) {
> +  , In64BitMode(is64Bit)
> +  , InNaClMode(false) {
>   // Determine default and user specified characteristics
>   if (!FS.empty() || !CPU.empty()) {
>     std::string CPUName = CPU;
> @@ -306,6 +307,11 @@
>   if (In64BitMode)
>     ToggleFeature(X86::Mode64Bit);
> 
> +  if (isTargetNaCl()) {
> +    InNaClMode = true;
> +    ToggleFeature(X86::ModeNaCl);
> +  }
> +
>   if (HasAVX)
>     X86SSELevel = NoMMXSSE;
> 
> 
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=139125&r1=139124&r2=139125&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Sep  5 16:51:43 2011
> @@ -119,6 +119,9 @@
>   /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
>   bool In64BitMode;
> 
> +  /// InNaClMode - True if compiling for Native Client target.
> +  bool InNaClMode;
> +
> public:
> 
>   /// This constructor initializes the data members to match that
> @@ -190,6 +193,11 @@
>     return !isTargetDarwin() && !isTargetWindows() && !isTargetCygMing();
>   }
>   bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
> +  bool isTargetNaCl() const {
> +    return TargetTriple.getOS() == Triple::NativeClient;
> +  }
> +  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
> +  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
> 
>   bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
>   bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From stoklund at 2pi.dk  Tue Sep  6 12:06:58 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 06 Sep 2011 10:06:58 -0700
Subject: [llvm-commits] [PATCH] Clean up RegOp2MemOp tables in
 X86InstrInfo.cpp
In-Reply-To: <CAAU48JKT3LE1gCzvWtv5Me4AsQLTbGa+boxFyZsjuKOP+8BanQ@mail.gmail.com>
References: <CAAU48JKT3LE1gCzvWtv5Me4AsQLTbGa+boxFyZsjuKOP+8BanQ@mail.gmail.com>
Message-ID: <6CF9FE3C-ABC0-4BB8-89A8-A27A45803A7A@2pi.dk>


On Sep 5, 2011, at 9:40 PM, David Meyer wrote:

> Hello!
> 
> This patch:
> 
> * Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
> single field (Flags), which is a bitwise OR of items from the TB_*
> enum. This makes it easier to add new information in the future.
> 
> * Gives every static array an equivalent layout: { RegOp, MemOp, Flags }
> 
> * Adds a helper function, AddTableEntry, to avoid duplication of the
> insertion code.
> 
> * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.
> 
> * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
> it prevents addition of the Reg->Mem entry. (This is going to be used
> by Native Client, in the next CL).

Looks good, but please add an explanation of the TB_INDEX* and TB_ALIGN* enums.

/jakob


From atrick at apple.com  Tue Sep  6 12:36:45 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 06 Sep 2011 10:36:45 -0700
Subject: [llvm-commits] [llvm] r139009 -
 /llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp
In-Reply-To: <4E651168.9090404@mxc.ca>
References: <20110902172628.D88A92A6C12C@llvm.org> <4E651168.9090404@mxc.ca>
Message-ID: <8C8F6004-18E6-45F9-9C10-6AFCA4FBC707@apple.com>


On Sep 5, 2011, at 11:14 AM, Nick Lewycky wrote:
>> x86 is break even.
>> ARM performance changes to expect (+ is good):
>> External/SPEC/CFP2000/183.equake/183.equake +13%
>> SingleSource/Benchmarks/Dhrystone/fldry     +21%
>> MultiSource/Applications/spiff/spiff         +3%
>> SingleSource/Benchmarks/Stanford/Puzzle     -14%
>> 
>> The Puzzle regression is actually an improvement in loop optimization
>> that defeats GVN: rdar://problem/10065079.
> 
> PR, please?

See PR10872.

-Andy

From dpatel at apple.com  Tue Sep  6 12:40:08 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 06 Sep 2011 17:40:08 -0000
Subject: [llvm-commits] [llvm] r139147 -
	/llvm/trunk/lib/Analysis/DebugInfo.cpp
Message-ID: <20110906174008.EC6112A6C12C@llvm.org>

Author: dpatel
Date: Tue Sep  6 12:40:08 2011
New Revision: 139147

URL: http://llvm.org/viewvc/llvm-project?rev=139147&view=rev
Log:
Now, named mdnode llvm.dbg.cu keeps track of all compile units in a module. Update DebugInfoFinder to collect compile units from llvm.dbg.cu.

Modified:
    llvm/trunk/lib/Analysis/DebugInfo.cpp

Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=139147&r1=139146&r2=139147&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DebugInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Sep  6 12:40:08 2011
@@ -905,6 +905,10 @@
 
 /// processModule - Process entire module and collect debug info.
 void DebugInfoFinder::processModule(Module &M) {
+  if (NamedMDNode *CU_Nodes = M.getNamedMetadata("llvm.dbg.cu"))
+    for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i)
+      addCompileUnit(DICompileUnit(CU_Nodes->getOperand(i)));
+
   for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
     for (Function::iterator FI = (*I).begin(), FE = (*I).end(); FI != FE; ++FI)
       for (BasicBlock::iterator BI = (*FI).begin(), BE = (*FI).end(); BI != BE;
@@ -934,7 +938,8 @@
     for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
       DIGlobalVariable DIG(cast<MDNode>(NMD->getOperand(i)));
       if (addGlobalVariable(DIG)) {
-        addCompileUnit(DIG.getCompileUnit());
+        if (DIG.getVersion() <= LLVMDebugVersion10)
+          addCompileUnit(DIG.getCompileUnit());
         processType(DIG.getType());
       }
     }
@@ -962,8 +967,8 @@
 void DebugInfoFinder::processType(DIType DT) {
   if (!addType(DT))
     return;
-
-  addCompileUnit(DT.getCompileUnit());
+  if (DT.getVersion() <= LLVMDebugVersion10)
+    addCompileUnit(DT.getCompileUnit());
   if (DT.isCompositeType()) {
     DICompositeType DCT(DT);
     processType(DCT.getTypeDerivedFrom());
@@ -994,7 +999,8 @@
 void DebugInfoFinder::processSubprogram(DISubprogram SP) {
   if (!addSubprogram(SP))
     return;
-  addCompileUnit(SP.getCompileUnit());
+  if (SP.getVersion() <= LLVMDebugVersion10)
+    addCompileUnit(SP.getCompileUnit());
   processType(SP.getType());
 }
 
@@ -1009,8 +1015,8 @@
 
   if (!NodesSeen.insert(DV))
     return;
-
-  addCompileUnit(DIVariable(N).getCompileUnit());
+  if (DIVariable(N).getVersion() <= LLVMDebugVersion10)
+    addCompileUnit(DIVariable(N).getCompileUnit());
   processType(DIVariable(N).getType());
 }
 



From stoklund at 2pi.dk  Tue Sep  6 12:40:35 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 06 Sep 2011 17:40:35 -0000
Subject: [llvm-commits] [llvm] r139148 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/atomic-cmp.ll
 test/CodeGen/ARM/atomic-op.ll
Message-ID: <20110906174036.05CD42A6C12C@llvm.org>

Author: stoklund
Date: Tue Sep  6 12:40:35 2011
New Revision: 139148

URL: http://llvm.org/viewvc/llvm-project?rev=139148&view=rev
Log:
Atomic pseudos don't use (as in read) CPSR. They clobber it.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll
    llvm/trunk/test/CodeGen/ARM/atomic-op.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139148&r1=139147&r2=139148&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Sep  6 12:40:35 2011
@@ -1613,7 +1613,7 @@
 
 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
 // (These psuedos use a hand-written selection code).
-let usesCustomInserter = 1, Uses = [CPSR] in {
+let usesCustomInserter = 1, Defs = [CPSR] in {
 def ATOMOR6432   : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
                               (ins GPR:$addr, GPR:$src1, GPR:$src2),
                               NoItinerary, []>;
@@ -4104,7 +4104,7 @@
 }
 
 let usesCustomInserter = 1 in {
-  let Uses = [CPSR] in {
+  let Defs = [CPSR] in {
     def ATOMIC_LOAD_ADD_I8 : PseudoInst<
       (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
       [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;

Modified: llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll?rev=139148&r1=139147&r2=139148&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll Tue Sep  6 12:40:35 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=armv7-apple-darwin   | FileCheck %s -check-prefix=ARM
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=T2
+; RUN: llc < %s -mtriple=armv7-apple-darwin -verify-machineinstrs   | FileCheck %s -check-prefix=ARM
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -verify-machineinstrs | FileCheck %s -check-prefix=T2
 ; rdar://8964854
 
 define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {

Modified: llvm/trunk/test/CodeGen/ARM/atomic-op.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=139148&r1=139147&r2=139148&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/atomic-op.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/atomic-op.ll Tue Sep  6 12:40:35 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=armv7-apple-darwin10 | FileCheck %s
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -mtriple=armv7-apple-darwin10 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -verify-machineinstrs | FileCheck %s
 
 define void @func(i32 %argc, i8** %argv) nounwind {
 entry:



From dpatel at apple.com  Tue Sep  6 12:52:49 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 06 Sep 2011 10:52:49 -0700
Subject: [llvm-commits] [llvm] r139117 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyCFG.cpp
 test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll
In-Reply-To: <20110905125758.26B812A6C12C@llvm.org>
References: <20110905125758.26B812A6C12C@llvm.org>
Message-ID: <445CE0ED-BD2B-4A80-9A86-BC0C17A6CED9@apple.com>


On Sep 5, 2011, at 5:57 AM, Duncan Sands wrote:

> Author: baldrick
> Date: Mon Sep  5 07:57:57 2011
> New Revision: 139117
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=139117&view=rev
> Log:
> Delete trivial landing pads that just continue unwinding the caught
> exception.
> 
> Added:
>    llvm/trunk/test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll
> Modified:
>    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
> 
> Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=139117&r1=139116&r2=139117&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
> +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Sep  5 07:57:57 2011
> @@ -63,6 +63,7 @@
>   bool FoldValueComparisonIntoPredecessors(TerminatorInst *TI,
>                                            IRBuilder<> &Builder);
> 
> +  bool SimplifyResume(ResumeInst *RI, IRBuilder<> &Builder);
>   bool SimplifyReturn(ReturnInst *RI, IRBuilder<> &Builder);
>   bool SimplifyUnwind(UnwindInst *UI, IRBuilder<> &Builder);
>   bool SimplifyUnreachable(UnreachableInst *UI);
> @@ -2138,6 +2139,52 @@
>   return true;
> }
> 
> +bool SimplifyCFGOpt::SimplifyResume(ResumeInst *RI, IRBuilder<> &Builder) {
> +  // If this is a trivial landing pad that just continues unwinding the caught
> +  // exception then zap the landing pad, turning its invokes into calls.
> +  BasicBlock *BB = RI->getParent();
> +  LandingPadInst *LPInst = dyn_cast<LandingPadInst>(BB->getFirstNonPHI());
> +  if (RI->getValue() != LPInst)
> +    // Not a landing pad, or the resume is not unwinding the exception that
> +    // caused control to branch here.
> +    return false;
> +
> +  // Check that there are no other instructions except for debug intrinsics.
> +  BasicBlock::iterator I = LPInst, E = RI;
> +  while (++I != E)
> +    if (!isa<DbgInfoIntrinsic>(I))
> +      return false;
> +
> +  // Turn all invokes that unwind here into calls and delete the basic block.
> +  for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE;) {
> +    InvokeInst *II = cast<InvokeInst>((*PI++)->getTerminator());
> +    SmallVector<Value*, 8> Args(II->op_begin(), II->op_end() - 3);
> +    // Insert a call instruction before the invoke.
> +    CallInst *Call = CallInst::Create(II->getCalledValue(), Args, "", II);

Any reason to not use Builder to create call inst ?
-
Devang

> +    Call->takeName(II);
> +    Call->setCallingConv(II->getCallingConv());
> +    Call->setAttributes(II->getAttributes());
> +    Call->setDebugLoc(II->getDebugLoc());
> +
> +    // Anything that used the value produced by the invoke instruction now uses
> +    // the value produced by the call instruction.  Note that we do this even
> +    // for void functions and calls with no uses so that the callgraph edge is
> +    // updated.
> +    II->replaceAllUsesWith(Call);
> +    BB->removePredecessor(II->getParent());
> +
> +    // Insert a branch to the normal destination right before the invoke.
> +    BranchInst::Create(II->getNormalDest(), II);
> +
> +    // Finally, delete the invoke instruction!
> +    II->eraseFromParent();
> +  }
> +
> +  // The landingpad is now unreachable.  Zap it.
> +  BB->eraseFromParent();
> +  return true;
> +}
> +
> bool SimplifyCFGOpt::SimplifyReturn(ReturnInst *RI, IRBuilder<> &Builder) {
>   BasicBlock *BB = RI->getParent();
>   if (!BB->getFirstNonPHIOrDbg()->isTerminator()) return false;
> @@ -2836,6 +2883,8 @@
>     } else {
>       if (SimplifyCondBranch(BI, Builder)) return true;
>     }
> +  } else if (ResumeInst *RI = dyn_cast<ResumeInst>(BB->getTerminator())) {
> +    if (SimplifyResume(RI, Builder)) return true;
>   } else if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator())) {
>     if (SimplifyReturn(RI, Builder)) return true;
>   } else if (SwitchInst *SI = dyn_cast<SwitchInst>(BB->getTerminator())) {
> 
> Added: llvm/trunk/test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll?rev=139117&view=auto
> ==============================================================================
> --- llvm/trunk/test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll (added)
> +++ llvm/trunk/test/Transforms/SimplifyCFG/2011-09-05-TrivialLPad.ll Mon Sep  5 07:57:57 2011
> @@ -0,0 +1,22 @@
> +; RUN: opt < %s -simplifycfg -S | FileCheck %s
> +
> +; CHECK-NOT: invoke
> +; CHECK-NOT: landingpad
> +
> +declare void @bar()
> +
> +define i32 @foo() {
> +entry:
> +  invoke void @bar()
> +          to label %return unwind label %lpad
> +
> +return:
> +  ret i32 0
> +
> +lpad:
> +  %lp = landingpad { i8*, i32 } personality i32 (i32, i64, i8*, i8*)* @__gxx_personality_v0
> +          cleanup
> +  resume { i8*, i32 } %lp
> +}
> +
> +declare i32 @__gxx_personality_v0(i32, i64, i8*, i8*)
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From nlewycky at google.com  Tue Sep  6 12:56:09 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Tue, 6 Sep 2011 10:56:09 -0700
Subject: [llvm-commits] [llvm] r139138 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
In-Reply-To: <CAJdarcEyWMZw7Lr2JF6KW3SHtoqd3tzT+7ajoYgB=yZNrEhpWg@mail.gmail.com>
References: <20110906065600.5230D2A6C12C@llvm.org>
	<CAJdarcEyWMZw7Lr2JF6KW3SHtoqd3tzT+7ajoYgB=yZNrEhpWg@mail.gmail.com>
Message-ID: <CADbEz-gOxRMJC6E1vKiwB_n_edxMQzJ8gx7ddZWxwxUTWgNmFA@mail.gmail.com>

On 6 September 2011 09:48, Eli Friedman <eli.friedman at gmail.com> wrote:

> On Mon, Sep 5, 2011 at 11:56 PM, Nick Lewycky <nicholas at mxc.ca> wrote:
> > Author: nicholas
> > Date: Tue Sep  6 01:56:00 2011
> > New Revision: 139138
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=139138&view=rev
> > Log:
> > Apparently we compile the code, not the comments. Thanks Eli!
>
> Sure. :)
>
> BTW, please commit a test for this...
>

Actually, Transforms/IndVarSimplify/test_compute.ll's @quadratic_setlt will
suffice.

Nick


>
> -Eli
>
> > Modified:
> >    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
> >
> > Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139138&r1=139137&r2=139138&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
> > +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep  6 01:56:00 2011
> > @@ -1998,8 +1998,7 @@
> >               const SCEV *NewStart = getMulExpr(A, C);
> >               const SCEV *BD = getMulExpr(B, D);
> >               const SCEV *NewStep = getAddExpr(getMulExpr(A, D),
> > -                                               getMulExpr(B, C),
> > -                                               getNegativeSCEV(BD));
> > +                                               getMulExpr(B, C), BD);
> >               const SCEV *NewSecondOrderStep =
> >                   getMulExpr(BD, getConstant(BD->getType(), 2));
> >
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From bruno.cardoso at gmail.com  Tue Sep  6 12:59:14 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 6 Sep 2011 10:59:14 -0700
Subject: [llvm-commits] [llvm] r139067 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
In-Reply-To: <B59D7CE9-F02B-4200-A8F2-E59C5B99ED15@apple.com>
References: <20110903004654.3B03F2A6C12F@llvm.org>
	<B59D7CE9-F02B-4200-A8F2-E59C5B99ED15@apple.com>
Message-ID: <CACk9FxZfTTZd6w1FAKvk1CCLpTpvWQgXVYRZXfBbNnmJ_kOtEw@mail.gmail.com>

This are all duplications of SSE patterns already in the .td file.
None of the commits has added a new pattern for SSE instructions nor
modified the behavior. I don't have testcases, this duplication is
something I've done in mass since last year and I'm just fulfilling
the holes, as to trying to compile and execute the llvm testsuite with
AVX turned on (and make sure we don't have code size and performance
regressions). If you feel this is not the way to go, I can revert all
last 30 commits I've done, but I won't add testcases for all those
right now. My future plan though is organize all sse tests in
test/CodeGen/X86 (which are quite messy) and then duplicate all
relevant ones to check for AVX versions instead.

On Tue, Sep 6, 2011 at 9:11 AM, Eric Christopher <echristo at apple.com> wrote:
>
> On Sep 2, 2011, at 5:46 PM, Bruno Cardoso Lopes wrote:
>
>> Author: bruno
>> Date: Fri Sep ?2 19:46:54 2011
>> New Revision: 139067
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=139067&view=rev
>> Log:
>> Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}
>
> Testcases for all of these? :)
>
> -eric
>



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From echristo at apple.com  Tue Sep  6 13:00:16 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 06 Sep 2011 11:00:16 -0700
Subject: [llvm-commits] [llvm] r139067 -
 /llvm/trunk/lib/Target/X86/X86InstrSSE.td
In-Reply-To: <CACk9FxZfTTZd6w1FAKvk1CCLpTpvWQgXVYRZXfBbNnmJ_kOtEw@mail.gmail.com>
References: <20110903004654.3B03F2A6C12F@llvm.org>
	<B59D7CE9-F02B-4200-A8F2-E59C5B99ED15@apple.com>
	<CACk9FxZfTTZd6w1FAKvk1CCLpTpvWQgXVYRZXfBbNnmJ_kOtEw@mail.gmail.com>
Message-ID: <68BCC341-D212-406A-9467-A22A82B9113D@apple.com>


On Sep 6, 2011, at 10:59 AM, Bruno Cardoso Lopes wrote:

> This are all duplications of SSE patterns already in the .td file.
> None of the commits has added a new pattern for SSE instructions nor
> modified the behavior. I don't have testcases, this duplication is
> something I've done in mass since last year and I'm just fulfilling
> the holes, as to trying to compile and execute the llvm testsuite with
> AVX turned on (and make sure we don't have code size and performance
> regressions). If you feel this is not the way to go, I can revert all
> last 30 commits I've done, but I won't add testcases for all those
> right now. My future plan though is organize all sse tests in
> test/CodeGen/X86 (which are quite messy) and then duplicate all
> relevant ones to check for AVX versions instead.

Nah, sounds good to me. Should probably have more tests is what I'm saying.

-eric

From eli.friedman at gmail.com  Tue Sep  6 13:01:34 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 6 Sep 2011 11:01:34 -0700
Subject: [llvm-commits] [llvm] r139148 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/atomic-cmp.ll
 test/CodeGen/ARM/atomic-op.ll
In-Reply-To: <20110906174036.05CD42A6C12C@llvm.org>
References: <20110906174036.05CD42A6C12C@llvm.org>
Message-ID: <CAJdarcH+2kUEXtQ617tyXJ+uj1cqokmyOB+EVDswHkis_aG+Rw@mail.gmail.com>

On Tue, Sep 6, 2011 at 10:40 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
> Author: stoklund
> Date: Tue Sep ?6 12:40:35 2011
> New Revision: 139148
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139148&view=rev
> Log:
> Atomic pseudos don't use (as in read) CPSR. They clobber it.

Thanks for spotting that. :)

-Eli

> Modified:
> ? ?llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> ? ?llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll
> ? ?llvm/trunk/test/CodeGen/ARM/atomic-op.ll
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139148&r1=139147&r2=139148&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Sep ?6 12:40:35 2011
> @@ -1613,7 +1613,7 @@
>
> ?// Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
> ?// (These psuedos use a hand-written selection code).
> -let usesCustomInserter = 1, Uses = [CPSR] in {
> +let usesCustomInserter = 1, Defs = [CPSR] in {
> ?def ATOMOR6432 ? : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (ins GPR:$addr, GPR:$src1, GPR:$src2),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? NoItinerary, []>;
> @@ -4104,7 +4104,7 @@
> ?}
>
> ?let usesCustomInserter = 1 in {
> - ?let Uses = [CPSR] in {
> + ?let Defs = [CPSR] in {
> ? ? def ATOMIC_LOAD_ADD_I8 : PseudoInst<
> ? ? ? (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
> ? ? ? [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
>
> Modified: llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll?rev=139148&r1=139147&r2=139148&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll Tue Sep ?6 12:40:35 2011
> @@ -1,5 +1,5 @@
> -; RUN: llc < %s -mtriple=armv7-apple-darwin ? | FileCheck %s -check-prefix=ARM
> -; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=T2
> +; RUN: llc < %s -mtriple=armv7-apple-darwin -verify-machineinstrs ? | FileCheck %s -check-prefix=ARM
> +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -verify-machineinstrs | FileCheck %s -check-prefix=T2
> ?; rdar://8964854
>
> ?define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {
>
> Modified: llvm/trunk/test/CodeGen/ARM/atomic-op.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=139148&r1=139147&r2=139148&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/atomic-op.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/atomic-op.ll Tue Sep ?6 12:40:35 2011
> @@ -1,5 +1,5 @@
> -; RUN: llc < %s -mtriple=armv7-apple-darwin10 | FileCheck %s
> -; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
> +; RUN: llc < %s -mtriple=armv7-apple-darwin10 -verify-machineinstrs | FileCheck %s
> +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -verify-machineinstrs | FileCheck %s
>
> ?define void @func(i32 %argc, i8** %argv) nounwind {
> ?entry:
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From stoklund at 2pi.dk  Tue Sep  6 13:11:23 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 06 Sep 2011 11:11:23 -0700
Subject: [llvm-commits] [llvm] r139148 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/atomic-cmp.ll
 test/CodeGen/ARM/atomic-op.ll
In-Reply-To: <CAJdarcH+2kUEXtQ617tyXJ+uj1cqokmyOB+EVDswHkis_aG+Rw@mail.gmail.com>
References: <20110906174036.05CD42A6C12C@llvm.org>
	<CAJdarcH+2kUEXtQ617tyXJ+uj1cqokmyOB+EVDswHkis_aG+Rw@mail.gmail.com>
Message-ID: <D6F2CE3E-85F1-40E3-A144-23A54EE77203@2pi.dk>


On Sep 6, 2011, at 11:01 AM, Eli Friedman wrote:

> On Tue, Sep 6, 2011 at 10:40 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>> Author: stoklund
>> Date: Tue Sep  6 12:40:35 2011
>> New Revision: 139148
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=139148&view=rev
>> Log:
>> Atomic pseudos don't use (as in read) CPSR. They clobber it.
> 
> Thanks for spotting that. :)

No problem. I blame English :-)

It is actually a good idea to add -verify-machineinstrs to this kind of test case. These days, the ARM backend is good enough that there isn't a ton of false positives. It's quite common for usesCustomInserter instructions to do something silly, and usually the verifier catches it.

/jakob


From James.Molloy at arm.com  Tue Sep  6 13:10:31 2011
From: James.Molloy at arm.com (James Molloy)
Date: Tue, 6 Sep 2011 19:10:31 +0100
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and	resolve
 (safe) ambiguous instruction encodings
In-Reply-To: <CC29118F-81C7-4345-909C-CB4B535DE4B0@apple.com>
References: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>
	<F01D8B85CFF58440B2A13965FBA90CA473757133DD@GEORGE.Emea.Arm.com>
	<AF10579E-4931-410D-9B6E-F35C1248240F@mac.com>,
	<CC29118F-81C7-4345-909C-CB4B535DE4B0@apple.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA473757133DE@GEORGE.Emea.Arm.com>

Hi Jim,

Ah, thanks for letting me know. To be honest I wasn't pinging out of impatience, more to ensure that it didn't get off everyone's radar after they came back for the weekend :)

Cheers,

James
________________________________________
From: Jim Grosbach [grosbach at apple.com]
Sent: 06 September 2011 17:50
To: Owen Anderson
Cc: James Molloy; llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and      resolve (safe) ambiguous instruction encodings

Ditto. It was a holiday weekend over here, so folks have been offline for the most part.

-j
On Sep 5, 2011, at 11:29 AM, Owen Anderson wrote:

> I'm planning to look at this, but haven't had a chance yet.
>
> --Owen
>
> On Sep 5, 2011, at 11:00 AM, James Molloy wrote:
>
>> Ping?
>> ________________________________________
>> From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of James Molloy [james.molloy at arm.com]
>> Sent: 02 September 2011 16:38
>> To: llvm-commits at cs.uiuc.edu
>> Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve  (safe) ambiguous instruction encodings
>>
>> Hi,
>>
>> The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M series
>> not allowing the correct mask names.
>>
>> The patch becomes difficult because:
>> * There is no way to determine in the InstPrinter any subtarget specific
>> features (such as "operating on an m-class core?").
>> * There is currently no subtarget feature for "M-class core?"; the nearest is
>> IsThumb2 && !HasARM.
>> * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
>> a way that makes them deterministically separable. This causes non-conflicting
>> ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
>> both code paths are emitted but only one will ever be hit.
>>
>> The solution is:
>> * Add subtarget info to InstPrinter so it can determine what to do with the
>> mask immediate.
>> * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
>> IsARClass == !IsMClass. This feature only has semantic sense on v6+
>> architectures.
>> * The conflicts occur because the FixedLenDecoderEmitter does not honour the
>> Predicates field of instructions in the tablegen description. If the island
>> checking also checked the AssemblerPredicates field (if defined), ambiguous
>> instruction encodings that are disambiguated by predicates would (do) work fine.
>>
>> The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and MCDisassembler.
>> They can use this (in patch #2) to determine what mask names to accept (primask?
>> or cpsr_zxvf?)
>>
>> The second enhances FixedLenPredicateEncoder to emit predicate checks for
>> instructions before it accepts an encoding - this allows ambiguous instructions
>> to be disambiguated by the Predicates field in TableGen. This required changing
>> llvm-mc to accept -mattr, and tests to set the correct features they rely upon.
>>
>> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
>> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
>> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
>> is created.**
>>
>> The third patch adds a new predicate "IsMClass" along with its counterpart
>> "IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
>> Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
>> encodings respectively. It also fixes mask printing for MRS/MSR in the
>> ARMMCInstPrinter and ARMMCAsmParser.
>>
>> Testcases added with the final patch.
>>
>> Comments? Is it OK?
>>
>> Cheers,
>>
>> James
>>
>> [N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout myself
>> after review]
>>
>> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.



From resistor at mac.com  Tue Sep  6 13:14:10 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 06 Sep 2011 18:14:10 -0000
Subject: [llvm-commits] [llvm] r139150 - in /llvm/trunk:
 lib/Transforms/Scalar/DeadStoreElimination.cpp
 test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll
 test/Transforms/DeadStoreElimination/2011-09-06-MemCpy.ll
Message-ID: <20110906181410.0DA702A6C12C@llvm.org>

Author: resistor
Date: Tue Sep  6 13:14:09 2011
New Revision: 139150

URL: http://llvm.org/viewvc/llvm-project?rev=139150&view=rev
Log:
Try again at r138809 (make DSE more aggressive in removing dead stores at the end of a function), now with less deleting stores before memcpy's.

Added:
    llvm/trunk/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll
    llvm/trunk/test/Transforms/DeadStoreElimination/2011-09-06-MemCpy.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=139150&r1=139149&r2=139150&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Tue Sep  6 13:14:09 2011
@@ -52,18 +52,18 @@
       AA = &getAnalysis<AliasAnalysis>();
       MD = &getAnalysis<MemoryDependenceAnalysis>();
       DominatorTree &DT = getAnalysis<DominatorTree>();
-      
+
       bool Changed = false;
       for (Function::iterator I = F.begin(), E = F.end(); I != E; ++I)
         // Only check non-dead blocks.  Dead blocks may have strange pointer
         // cycles that will confuse alias analysis.
         if (DT.isReachableFromEntry(I))
           Changed |= runOnBasicBlock(*I);
-      
+
       AA = 0; MD = 0;
       return Changed;
     }
-    
+
     bool runOnBasicBlock(BasicBlock &BB);
     bool HandleFree(CallInst *F);
     bool handleEndBlock(BasicBlock &BB);
@@ -105,34 +105,34 @@
                                   MemoryDependenceAnalysis &MD,
                                   SmallPtrSet<Value*, 16> *ValueSet = 0) {
   SmallVector<Instruction*, 32> NowDeadInsts;
-  
+
   NowDeadInsts.push_back(I);
   --NumFastOther;
-  
+
   // Before we touch this instruction, remove it from memdep!
   do {
     Instruction *DeadInst = NowDeadInsts.pop_back_val();
     ++NumFastOther;
-    
+
     // This instruction is dead, zap it, in stages.  Start by removing it from
     // MemDep, which needs to know the operands and needs it to be in the
     // function.
     MD.removeInstruction(DeadInst);
-    
+
     for (unsigned op = 0, e = DeadInst->getNumOperands(); op != e; ++op) {
       Value *Op = DeadInst->getOperand(op);
       DeadInst->setOperand(op, 0);
-      
+
       // If this operand just became dead, add it to the NowDeadInsts list.
       if (!Op->use_empty()) continue;
-      
+
       if (Instruction *OpI = dyn_cast<Instruction>(Op))
         if (isInstructionTriviallyDead(OpI))
           NowDeadInsts.push_back(OpI);
     }
-    
+
     DeadInst->eraseFromParent();
-    
+
     if (ValueSet) ValueSet->erase(DeadInst);
   } while (!NowDeadInsts.empty());
 }
@@ -163,7 +163,7 @@
 getLocForWrite(Instruction *Inst, AliasAnalysis &AA) {
   if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
     return AA.getLocation(SI);
-  
+
   if (MemIntrinsic *MI = dyn_cast<MemIntrinsic>(Inst)) {
     // memcpy/memmove/memset.
     AliasAnalysis::Location Loc = AA.getLocationForDest(MI);
@@ -174,10 +174,10 @@
       return AliasAnalysis::Location();
     return Loc;
   }
-  
+
   IntrinsicInst *II = dyn_cast<IntrinsicInst>(Inst);
   if (II == 0) return AliasAnalysis::Location();
-  
+
   switch (II->getIntrinsicID()) {
   default: return AliasAnalysis::Location(); // Unhandled intrinsic.
   case Intrinsic::init_trampoline:
@@ -185,7 +185,7 @@
     // that we should use the size of the pointee type.  This isn't valid for
     // init.trampoline, which writes more than an i8.
     if (AA.getTargetData() == 0) return AliasAnalysis::Location();
-      
+
     // FIXME: We don't know the size of the trampoline, so we can't really
     // handle it here.
     return AliasAnalysis::Location(II->getArgOperand(0));
@@ -198,10 +198,10 @@
 
 /// getLocForRead - Return the location read by the specified "hasMemoryWrite"
 /// instruction if any.
-static AliasAnalysis::Location 
+static AliasAnalysis::Location
 getLocForRead(Instruction *Inst, AliasAnalysis &AA) {
   assert(hasMemoryWrite(Inst) && "Unknown instruction case");
-  
+
   // The only instructions that both read and write are the mem transfer
   // instructions (memcpy/memmove).
   if (MemTransferInst *MTI = dyn_cast<MemTransferInst>(Inst))
@@ -216,7 +216,7 @@
   // Don't remove volatile/atomic stores.
   if (StoreInst *SI = dyn_cast<StoreInst>(I))
     return SI->isUnordered();
-  
+
   IntrinsicInst *II = cast<IntrinsicInst>(I);
   switch (II->getIntrinsicID()) {
   default: assert(0 && "doesn't pass 'hasMemoryWrite' predicate");
@@ -227,7 +227,7 @@
   case Intrinsic::init_trampoline:
     // Always safe to remove init_trampoline.
     return true;
-    
+
   case Intrinsic::memset:
   case Intrinsic::memmove:
   case Intrinsic::memcpy:
@@ -255,14 +255,14 @@
   const TargetData *TD = AA.getTargetData();
   if (TD == 0)
     return AliasAnalysis::UnknownSize;
-  
+
   if (AllocaInst *A = dyn_cast<AllocaInst>(V)) {
     // Get size information for the alloca
     if (ConstantInt *C = dyn_cast<ConstantInt>(A->getArraySize()))
       return C->getZExtValue() * TD->getTypeAllocSize(A->getAllocatedType());
     return AliasAnalysis::UnknownSize;
   }
-  
+
   assert(isa<Argument>(V) && "Expected AllocaInst or Argument!");
   PointerType *PT = cast<PointerType>(V->getType());
   return TD->getTypeAllocSize(PT->getElementType());
@@ -287,7 +287,7 @@
                                 AliasAnalysis &AA) {
   const Value *P1 = Earlier.Ptr->stripPointerCasts();
   const Value *P2 = Later.Ptr->stripPointerCasts();
-  
+
   // If the start pointers are the same, we just have to compare sizes to see if
   // the later store was larger than the earlier store.
   if (P1 == P2) {
@@ -302,33 +302,33 @@
         return Later.Ptr->getType() == Earlier.Ptr->getType();
       return false;
     }
-    
+
     // Make sure that the Later size is >= the Earlier size.
     if (Later.Size < Earlier.Size)
       return false;
     return true;
   }
-  
+
   // Otherwise, we have to have size information, and the later store has to be
   // larger than the earlier one.
   if (Later.Size == AliasAnalysis::UnknownSize ||
       Earlier.Size == AliasAnalysis::UnknownSize ||
       Later.Size <= Earlier.Size || AA.getTargetData() == 0)
     return false;
-  
+
   // Check to see if the later store is to the entire object (either a global,
   // an alloca, or a byval argument).  If so, then it clearly overwrites any
   // other store to the same object.
   const TargetData &TD = *AA.getTargetData();
-  
+
   const Value *UO1 = GetUnderlyingObject(P1, &TD),
               *UO2 = GetUnderlyingObject(P2, &TD);
-  
+
   // If we can't resolve the same pointers to the same object, then we can't
   // analyze them at all.
   if (UO1 != UO2)
     return false;
-  
+
   // If the "Later" store is to a recognizable object, get its size.
   if (isObjectPointerWithTrustworthySize(UO2)) {
     uint64_t ObjectSize =
@@ -336,26 +336,26 @@
     if (ObjectSize == Later.Size)
       return true;
   }
-  
+
   // Okay, we have stores to two completely different pointers.  Try to
   // decompose the pointer into a "base + constant_offset" form.  If the base
   // pointers are equal, then we can reason about the two stores.
   int64_t EarlierOff = 0, LaterOff = 0;
   const Value *BP1 = GetPointerBaseWithConstantOffset(P1, EarlierOff, TD);
   const Value *BP2 = GetPointerBaseWithConstantOffset(P2, LaterOff, TD);
-  
+
   // If the base pointers still differ, we have two completely different stores.
   if (BP1 != BP2)
     return false;
 
   // The later store completely overlaps the earlier store if:
-  // 
+  //
   // 1. Both start at the same offset and the later one's size is greater than
   //    or equal to the earlier one's, or
   //
   //      |--earlier--|
   //      |--   later   --|
-  //      
+  //
   // 2. The earlier store has an offset greater than the later offset, but which
   //    still lies completely within the later store.
   //
@@ -373,7 +373,7 @@
 
 /// isPossibleSelfRead - If 'Inst' might be a self read (i.e. a noop copy of a
 /// memory region into an identical pointer) then it doesn't actually make its
-/// input dead in the traditional sense.  Consider this case: 
+/// input dead in the traditional sense.  Consider this case:
 ///
 ///   memcpy(A <- B)
 ///   memcpy(A <- A)
@@ -391,10 +391,10 @@
   // location read.
   AliasAnalysis::Location InstReadLoc = getLocForRead(Inst, AA);
   if (InstReadLoc.Ptr == 0) return false;  // Not a reading instruction.
-  
+
   // If the read and written loc obviously don't alias, it isn't a read.
   if (AA.isNoAlias(InstReadLoc, InstStoreLoc)) return false;
-  
+
   // Okay, 'Inst' may copy over itself.  However, we can still remove a the
   // DepWrite instruction if we can prove that it reads from the same location
   // as Inst.  This handles useful cases like:
@@ -404,10 +404,10 @@
   // aliases, so removing the first memcpy is safe (assuming it writes <= #
   // bytes as the second one.
   AliasAnalysis::Location DepReadLoc = getLocForRead(DepWrite, AA);
-  
+
   if (DepReadLoc.Ptr && AA.isMustAlias(InstReadLoc.Ptr, DepReadLoc.Ptr))
     return false;
-  
+
   // If DepWrite doesn't read memory or if we can't prove it is a must alias,
   // then it can't be considered dead.
   return true;
@@ -420,28 +420,28 @@
 
 bool DSE::runOnBasicBlock(BasicBlock &BB) {
   bool MadeChange = false;
-  
+
   // Do a top-down walk on the BB.
   for (BasicBlock::iterator BBI = BB.begin(), BBE = BB.end(); BBI != BBE; ) {
     Instruction *Inst = BBI++;
-    
+
     // Handle 'free' calls specially.
     if (CallInst *F = isFreeCall(Inst)) {
       MadeChange |= HandleFree(F);
       continue;
     }
-    
+
     // If we find something that writes memory, get its memory dependence.
     if (!hasMemoryWrite(Inst))
       continue;
 
     MemDepResult InstDep = MD->getDependency(Inst);
-    
+
     // Ignore any store where we can't find a local dependence.
     // FIXME: cross-block DSE would be fun. :)
     if (InstDep.isNonLocal() || InstDep.isUnknown())
       continue;
-     
+
     // If we're storing the same value back to a pointer that we just
     // loaded from, then the store can be removed.
     if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
@@ -450,13 +450,13 @@
             SI->getOperand(0) == DepLoad && isRemovable(SI)) {
           DEBUG(dbgs() << "DSE: Remove Store Of Load from same pointer:\n  "
                        << "LOAD: " << *DepLoad << "\n  STORE: " << *SI << '\n');
-          
+
           // DeleteDeadInstruction can delete the current instruction.  Save BBI
           // in case we need it.
           WeakVH NextInst(BBI);
-          
+
           DeleteDeadInstruction(SI, *MD);
-          
+
           if (NextInst == 0)  // Next instruction deleted.
             BBI = BB.begin();
           else if (BBI != BB.begin())  // Revisit this instruction if possible.
@@ -467,14 +467,14 @@
         }
       }
     }
-    
+
     // Figure out what location is being stored to.
     AliasAnalysis::Location Loc = getLocForWrite(Inst, *AA);
 
     // If we didn't get a useful location, fail.
     if (Loc.Ptr == 0)
       continue;
-    
+
     while (!InstDep.isNonLocal() && !InstDep.isUnknown()) {
       // Get the memory clobbered by the instruction we depend on.  MemDep will
       // skip any instructions that 'Loc' clearly doesn't interact with.  If we
@@ -496,12 +496,12 @@
           !isPossibleSelfRead(Inst, Loc, DepWrite, *AA)) {
         DEBUG(dbgs() << "DSE: Remove Dead Store:\n  DEAD: "
               << *DepWrite << "\n  KILLER: " << *Inst << '\n');
-        
+
         // Delete the store and now-dead instructions that feed it.
         DeleteDeadInstruction(DepWrite, *MD);
         ++NumFastStores;
         MadeChange = true;
-        
+
         // DeleteDeadInstruction can delete the current instruction in loop
         // cases, reset BBI.
         BBI = Inst;
@@ -509,7 +509,7 @@
           --BBI;
         break;
       }
-      
+
       // If this is a may-aliased store that is clobbering the store value, we
       // can keep searching past it for another must-aliased pointer that stores
       // to the same location.  For example, in:
@@ -519,20 +519,20 @@
       // we can remove the first store to P even though we don't know if P and Q
       // alias.
       if (DepWrite == &BB.front()) break;
-      
+
       // Can't look past this instruction if it might read 'Loc'.
       if (AA->getModRefInfo(DepWrite, Loc) & AliasAnalysis::Ref)
         break;
-        
+
       InstDep = MD->getPointerDependencyFrom(Loc, false, DepWrite, &BB);
     }
   }
-  
+
   // If this block ends in a return, unwind, or unreachable, all allocas are
   // dead at its end, which means stores to them are also dead.
   if (BB.getTerminator()->getNumSuccessors() == 0)
     MadeChange |= handleEndBlock(BB);
-  
+
   return MadeChange;
 }
 
@@ -547,14 +547,14 @@
     Instruction *Dependency = Dep.getInst();
     if (!hasMemoryWrite(Dependency) || !isRemovable(Dependency))
       return MadeChange;
-  
+
     Value *DepPointer =
       GetUnderlyingObject(getStoredPointerOperand(Dependency));
 
     // Check for aliasing.
     if (!AA->isMustAlias(F->getArgOperand(0), DepPointer))
       return MadeChange;
-  
+
     // DCE instructions only used to calculate that store
     DeleteDeadInstruction(Dependency, *MD);
     ++NumFastStores;
@@ -567,7 +567,7 @@
     //    free(s);
     Dep = MD->getDependency(F);
   };
-  
+
   return MadeChange;
 }
 
@@ -579,28 +579,28 @@
 /// ret void
 bool DSE::handleEndBlock(BasicBlock &BB) {
   bool MadeChange = false;
-  
+
   // Keep track of all of the stack objects that are dead at the end of the
   // function.
   SmallPtrSet<Value*, 16> DeadStackObjects;
-  
+
   // Find all of the alloca'd pointers in the entry block.
   BasicBlock *Entry = BB.getParent()->begin();
   for (BasicBlock::iterator I = Entry->begin(), E = Entry->end(); I != E; ++I)
     if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
       DeadStackObjects.insert(AI);
-  
+
   // Treat byval arguments the same, stores to them are dead at the end of the
   // function.
   for (Function::arg_iterator AI = BB.getParent()->arg_begin(),
        AE = BB.getParent()->arg_end(); AI != AE; ++AI)
     if (AI->hasByValAttr())
       DeadStackObjects.insert(AI);
-  
+
   // Scan the basic block backwards
   for (BasicBlock::iterator BBI = BB.end(); BBI != BB.begin(); ){
     --BBI;
-    
+
     // If we find a store, check to see if it points into a dead stack value.
     if (hasMemoryWrite(BBI) && isRemovable(BBI)) {
       // See through pointer-to-pointer bitcasts
@@ -609,10 +609,10 @@
       // Stores to stack values are valid candidates for removal.
       if (DeadStackObjects.count(Pointer)) {
         Instruction *Dead = BBI++;
-        
+
         DEBUG(dbgs() << "DSE: Dead Store at End of Block:\n  DEAD: "
                      << *Dead << "\n  Object: " << *Pointer << '\n');
-        
+
         // DCE instructions only used to calculate that store.
         DeleteDeadInstruction(Dead, *MD, &DeadStackObjects);
         ++NumFastStores;
@@ -620,7 +620,7 @@
         continue;
       }
     }
-    
+
     // Remove any dead non-memory-mutating instructions.
     if (isInstructionTriviallyDead(BBI)) {
       Instruction *Inst = BBI++;
@@ -629,45 +629,45 @@
       MadeChange = true;
       continue;
     }
-    
+
     if (AllocaInst *A = dyn_cast<AllocaInst>(BBI)) {
       DeadStackObjects.erase(A);
       continue;
     }
-    
+
     if (CallSite CS = cast<Value>(BBI)) {
       // If this call does not access memory, it can't be loading any of our
       // pointers.
       if (AA->doesNotAccessMemory(CS))
         continue;
-      
+
       // If the call might load from any of our allocas, then any store above
       // the call is live.
       SmallVector<Value*, 8> LiveAllocas;
       for (SmallPtrSet<Value*, 16>::iterator I = DeadStackObjects.begin(),
            E = DeadStackObjects.end(); I != E; ++I) {
         // See if the call site touches it.
-        AliasAnalysis::ModRefResult A = 
+        AliasAnalysis::ModRefResult A =
           AA->getModRefInfo(CS, *I, getPointerSize(*I, *AA));
-        
+
         if (A == AliasAnalysis::ModRef || A == AliasAnalysis::Ref)
           LiveAllocas.push_back(*I);
       }
-      
+
       for (SmallVector<Value*, 8>::iterator I = LiveAllocas.begin(),
            E = LiveAllocas.end(); I != E; ++I)
         DeadStackObjects.erase(*I);
-      
+
       // If all of the allocas were clobbered by the call then we're not going
       // to find anything else to process.
       if (DeadStackObjects.empty())
         return MadeChange;
-      
+
       continue;
     }
 
     AliasAnalysis::Location LoadedLoc;
-    
+
     // If we encounter a use of the pointer, it is no longer considered dead
     if (LoadInst *L = dyn_cast<LoadInst>(BBI)) {
       if (!L->isUnordered()) // Be conservative with atomic/volatile load
@@ -677,8 +677,9 @@
       LoadedLoc = AA->getLocation(V);
     } else if (MemTransferInst *MTI = dyn_cast<MemTransferInst>(BBI)) {
       LoadedLoc = AA->getLocationForSource(MTI);
-    } else if (!BBI->mayReadOrWriteMemory()) {
-      // Instruction doesn't touch memory.
+    } else if (!BBI->mayReadFromMemory()) {
+      // Instruction doesn't read memory.  Note that stores that weren't removed
+      // above will hit this case.
       continue;
     } else {
       // Unknown inst; assume it clobbers everything.
@@ -694,7 +695,7 @@
     if (DeadStackObjects.empty())
       break;
   }
-  
+
   return MadeChange;
 }
 
@@ -708,14 +709,14 @@
   // A constant can't be in the dead pointer set.
   if (isa<Constant>(UnderlyingPointer))
     return;
-  
+
   // If the kill pointer can be easily reduced to an alloca, don't bother doing
   // extraneous AA queries.
   if (isa<AllocaInst>(UnderlyingPointer) || isa<Argument>(UnderlyingPointer)) {
     DeadStackObjects.erase(const_cast<Value*>(UnderlyingPointer));
     return;
   }
-  
+
   SmallVector<Value*, 16> NowLive;
   for (SmallPtrSet<Value*, 16>::iterator I = DeadStackObjects.begin(),
        E = DeadStackObjects.end(); I != E; ++I) {

Added: llvm/trunk/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll?rev=139150&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll (added)
+++ llvm/trunk/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll Tue Sep  6 13:14:09 2011
@@ -0,0 +1,27 @@
+; RUN: opt -dse -S < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin"
+
+%"class.std::auto_ptr" = type { i32* }
+
+; CHECK: @_Z3foov
+define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret %agg.result) uwtable ssp {
+_ZNSt8auto_ptrIiED1Ev.exit:
+  %temp.lvalue = alloca %"class.std::auto_ptr", align 8
+  call void @_Z3barv(%"class.std::auto_ptr"* sret %temp.lvalue)
+  %_M_ptr.i.i = getelementptr inbounds %"class.std::auto_ptr"* %temp.lvalue, i64 0, i32 0
+  %tmp.i.i = load i32** %_M_ptr.i.i, align 8, !tbaa !0
+; CHECK-NOT: store i32* null
+  store i32* null, i32** %_M_ptr.i.i, align 8, !tbaa !0
+  %_M_ptr.i.i4 = getelementptr inbounds %"class.std::auto_ptr"* %agg.result, i64 0, i32 0
+  store i32* %tmp.i.i, i32** %_M_ptr.i.i4, align 8, !tbaa !0
+; CHECK: ret void
+  ret void
+}
+
+declare void @_Z3barv(%"class.std::auto_ptr"* sret)
+
+!0 = metadata !{metadata !"any pointer", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}

Added: llvm/trunk/test/Transforms/DeadStoreElimination/2011-09-06-MemCpy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/DeadStoreElimination/2011-09-06-MemCpy.ll?rev=139150&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/DeadStoreElimination/2011-09-06-MemCpy.ll (added)
+++ llvm/trunk/test/Transforms/DeadStoreElimination/2011-09-06-MemCpy.ll Tue Sep  6 13:14:09 2011
@@ -0,0 +1,85 @@
+; RUN: opt -dse -S < %s | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.pair.162 = type { %struct.BasicBlock*, i32, [4 x i8] }
+%struct.BasicBlock = type { %struct.Value, %struct.ilist_node.24, %struct.iplist.22, %struct.Function* }
+%struct.Value = type { i32 (...)**, i8, i8, i16, %struct.Type*, %struct.Use*, %struct.StringMapEntry* }
+%struct.Type = type { %struct.LLVMContext*, i8, [3 x i8], i32, {}* }
+%struct.LLVMContext = type { %struct.LLVMContextImpl* }
+%struct.LLVMContextImpl = type opaque
+%struct.Use = type { %struct.Value*, %struct.Use*, %struct.PointerIntPair }
+%struct.PointerIntPair = type { i64 }
+%struct.StringMapEntry = type opaque
+%struct.ilist_node.24 = type { %struct.ilist_half_node.23, %struct.BasicBlock* }
+%struct.ilist_half_node.23 = type { %struct.BasicBlock* }
+%struct.iplist.22 = type { %struct.ilist_traits.21, %struct.Instruction* }
+%struct.ilist_traits.21 = type { %struct.ilist_half_node.25 }
+%struct.ilist_half_node.25 = type { %struct.Instruction* }
+%struct.Instruction = type { [52 x i8], %struct.ilist_node.26, %struct.BasicBlock*, %struct.DebugLoc }
+%struct.ilist_node.26 = type { %struct.ilist_half_node.25, %struct.Instruction* }
+%struct.DebugLoc = type { i32, i32 }
+%struct.Function = type { %struct.GlobalValue, %struct.ilist_node.14, %struct.iplist.4, %struct.iplist, %struct.ValueSymbolTable*, %struct.AttrListPtr }
+%struct.GlobalValue = type <{ [52 x i8], [4 x i8], %struct.Module*, i8, i16, [5 x i8], %struct.basic_string }>
+%struct.Module = type { %struct.LLVMContext*, %struct.iplist.20, %struct.iplist.16, %struct.iplist.12, %struct.vector.2, %struct.ilist, %struct.basic_string, %struct.ValueSymbolTable*, %struct.OwningPtr, %struct.basic_string, %struct.basic_string, %struct.basic_string, i8* }
+%struct.iplist.20 = type { %struct.ilist_traits.19, %struct.GlobalVariable* }
+%struct.ilist_traits.19 = type { %struct.ilist_node.18 }
+%struct.ilist_node.18 = type { %struct.ilist_half_node.17, %struct.GlobalVariable* }
+%struct.ilist_half_node.17 = type { %struct.GlobalVariable* }
+%struct.GlobalVariable = type { %struct.GlobalValue, %struct.ilist_node.18, i8, [7 x i8] }
+%struct.iplist.16 = type { %struct.ilist_traits.15, %struct.Function* }
+%struct.ilist_traits.15 = type { %struct.ilist_node.14 }
+%struct.ilist_node.14 = type { %struct.ilist_half_node.13, %struct.Function* }
+%struct.ilist_half_node.13 = type { %struct.Function* }
+%struct.iplist.12 = type { %struct.ilist_traits.11, %struct.GlobalAlias* }
+%struct.ilist_traits.11 = type { %struct.ilist_node.10 }
+%struct.ilist_node.10 = type { %struct.ilist_half_node.9, %struct.GlobalAlias* }
+%struct.ilist_half_node.9 = type { %struct.GlobalAlias* }
+%struct.GlobalAlias = type { %struct.GlobalValue, %struct.ilist_node.10 }
+%struct.vector.2 = type { %struct._Vector_base.1 }
+%struct._Vector_base.1 = type { %struct._Vector_impl.0 }
+%struct._Vector_impl.0 = type { %struct.basic_string*, %struct.basic_string*, %struct.basic_string* }
+%struct.basic_string = type { %struct._Alloc_hider }
+%struct._Alloc_hider = type { i8* }
+%struct.ilist = type { %struct.iplist.8 }
+%struct.iplist.8 = type { %struct.ilist_traits.7, %struct.NamedMDNode* }
+%struct.ilist_traits.7 = type { %struct.ilist_node.6 }
+%struct.ilist_node.6 = type { %struct.ilist_half_node.5, %struct.NamedMDNode* }
+%struct.ilist_half_node.5 = type { %struct.NamedMDNode* }
+%struct.NamedMDNode = type { %struct.ilist_node.6, %struct.basic_string, %struct.Module*, i8* }
+%struct.ValueSymbolTable = type opaque
+%struct.OwningPtr = type { %struct.GVMaterializer* }
+%struct.GVMaterializer = type opaque
+%struct.iplist.4 = type { %struct.ilist_traits.3, %struct.BasicBlock* }
+%struct.ilist_traits.3 = type { %struct.ilist_half_node.23 }
+%struct.iplist = type { %struct.ilist_traits, %struct.Argument* }
+%struct.ilist_traits = type { %struct.ilist_half_node }
+%struct.ilist_half_node = type { %struct.Argument* }
+%struct.Argument = type { %struct.Value, %struct.ilist_node, %struct.Function* }
+%struct.ilist_node = type { %struct.ilist_half_node, %struct.Argument* }
+%struct.AttrListPtr = type { %struct.AttributeListImpl* }
+%struct.AttributeListImpl = type opaque
+
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
+
+; CHECK: _ZSt9iter_swapIPSt4pairIPN4llvm10BasicBlockEjES5_EvT_T0_
+; CHECK: store
+; CHECK: ret void
+define void @_ZSt9iter_swapIPSt4pairIPN4llvm10BasicBlockEjES5_EvT_T0_(%struct.pair.162* %__a, %struct.pair.162* %__b) nounwind uwtable inlinehint {
+entry:
+  %memtmp = alloca %struct.pair.162, align 8
+  %0 = getelementptr inbounds %struct.pair.162* %memtmp, i64 0, i32 0
+  %1 = getelementptr inbounds %struct.pair.162* %__a, i64 0, i32 0
+  %2 = load %struct.BasicBlock** %1, align 8
+  store %struct.BasicBlock* %2, %struct.BasicBlock** %0, align 8
+  %3 = getelementptr inbounds %struct.pair.162* %memtmp, i64 0, i32 1
+  %4 = getelementptr inbounds %struct.pair.162* %__a, i64 0, i32 1
+  %5 = load i32* %4, align 4
+  store i32 %5, i32* %3, align 8
+  %6 = bitcast %struct.pair.162* %__a to i8*
+  %7 = bitcast %struct.pair.162* %__b to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %6, i8* %7, i64 12, i32 1, i1 false)
+  %8 = bitcast %struct.pair.162* %memtmp to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %7, i8* %8, i64 12, i32 1, i1 false)
+  ret void
+}



From isanbard at gmail.com  Tue Sep  6 13:37:11 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 06 Sep 2011 18:37:11 -0000
Subject: [llvm-commits] [llvm] r139152 - /llvm/trunk/lib/MC/MCDwarf.cpp
Message-ID: <20110906183711.E2B182A6C12C@llvm.org>

Author: void
Date: Tue Sep  6 13:37:11 2011
New Revision: 139152

URL: http://llvm.org/viewvc/llvm-project?rev=139152&view=rev
Log:
As a first step, emit both the compact unwind and CIE/FDEs for a function.

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=139152&r1=139151&r2=139152&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Tue Sep  6 13:37:11 2011
@@ -1013,24 +1013,18 @@
   MCObjectFileInfo *MOFI =
     const_cast<MCObjectFileInfo*>(Context.getObjectFileInfo());
   FrameEmitterImpl Emitter(UsingCFI, IsEH);
-  SmallVector<MCDwarfFrameInfo, 8> RequiresFDE;
-  ArrayRef<MCDwarfFrameInfo> FrameArray;
+  ArrayRef<MCDwarfFrameInfo> FrameArray = Streamer.getFrameInfos();
 
-  if (IsEH && MOFI->getCompactUnwindSection()) {
+  // Emit the compact unwind info if available.
+  // FIXME: This emits both the compact unwind and the old CIE/FDE
+  //        information. Only one of those is needed.
+  if (IsEH && MOFI->getCompactUnwindSection())
     for (unsigned i = 0, n = Streamer.getNumFrameInfos(); i < n; ++i) {
       const MCDwarfFrameInfo &Frame = Streamer.getFrameInfo(i);
-      if (!Frame.CompactUnwindEncoding ||
-          !Emitter.EmitCompactUnwind(Streamer, Frame))
-        RequiresFDE.push_back(Streamer.getFrameInfo(i));
+      if (!Frame.CompactUnwindEncoding)
+        Emitter.EmitCompactUnwind(Streamer, Frame);
     }
 
-    // Early exit if we don't need to emit FDEs.
-    if (RequiresFDE.empty()) return;
-    FrameArray = RequiresFDE;
-  } else {
-    FrameArray = Streamer.getFrameInfos();
-  }
-
   const MCSection &Section = IsEH ? *MOFI->getEHFrameSection() :
                                     *MOFI->getDwarfFrameSection();
   Streamer.SwitchSection(&Section);



From resistor at me.com  Tue Sep  6 13:43:41 2011
From: resistor at me.com (Owen Anderson)
Date: Tue, 06 Sep 2011 11:43:41 -0700
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and
	resolve	(safe) ambiguous instruction encodings
In-Reply-To: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>
References: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>
Message-ID: <718C7FA3-810A-486A-80BD-F3476C59DBFF@me.com>

James,

Patch 0 seems to be missing some necessary changes to non-ARM targets to make LLVM build with it applied.  I see a lot of errors of the form:

MipsMCTargetDesc.cpp:109:41: error: cannot initialize a parameter of type 'Target::MCInstPrinterCtorTy' (aka 'llvm::MCInstPrinter *(*)(const llvm::Target
      &, unsigned int, const llvm::MCAsmInfo &, const llvm::MCSubtargetInfo &)') with an lvalue of type 'llvm::MCInstPrinter *(const llvm::Target &,
      unsigned int, const llvm::MCAsmInfo &)'
                                        createMipsMCInstPrinter);
                                        ^~~~~~~~~~~~~~~~~~~~~~~

--Owen

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:

> Hi,
> 
> The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M series
> not allowing the correct mask names.
> 
> The patch becomes difficult because:
>  * There is no way to determine in the InstPrinter any subtarget specific
> features (such as "operating on an m-class core?").
>  * There is currently no subtarget feature for "M-class core?"; the nearest is
> IsThumb2 && !HasARM.
>  * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
> a way that makes them deterministically separable. This causes non-conflicting
> ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
> both code paths are emitted but only one will ever be hit.
> 
> The solution is:
>  * Add subtarget info to InstPrinter so it can determine what to do with the
> mask immediate.
>  * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
> IsARClass == !IsMClass. This feature only has semantic sense on v6+
> architectures.
>  * The conflicts occur because the FixedLenDecoderEmitter does not honour the
> Predicates field of instructions in the tablegen description. If the island
> checking also checked the AssemblerPredicates field (if defined), ambiguous
> instruction encodings that are disambiguated by predicates would (do) work fine.
> 
> The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and MCDisassembler.
> They can use this (in patch #2) to determine what mask names to accept (primask?
> or cpsr_zxvf?)
> 
> The second enhances FixedLenPredicateEncoder to emit predicate checks for
> instructions before it accepts an encoding - this allows ambiguous instructions
> to be disambiguated by the Predicates field in TableGen. This required changing
> llvm-mc to accept -mattr, and tests to set the correct features they rely upon.
> 
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
> is created.**
> 
> The third patch adds a new predicate "IsMClass" along with its counterpart
> "IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
> Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
> encodings respectively. It also fixes mask printing for MRS/MSR in the
> ARMMCInstPrinter and ARMMCAsmParser.
> 
> Testcases added with the final patch.
> 
> Comments? Is it OK?
> 
> Cheers,
> 
> James
> 
> [N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout myself
> after review]
> <patch0-add-sti-to-instprinter.patch><patch1-modify-fixedlendecoderemitter.patch><patch2-fix-msr-mrs.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From rafael.espindola at gmail.com  Tue Sep  6 13:43:09 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 06 Sep 2011 18:43:09 -0000
Subject: [llvm-commits] [llvm] r139154 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20110906184309.25EBC2A6C12C@llvm.org>

Author: rafael
Date: Tue Sep  6 13:43:08 2011
New Revision: 139154

URL: http://llvm.org/viewvc/llvm-project?rev=139154&view=rev
Log:
Fix style issues and typos found by Duncan.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139154&r1=139153&r2=139154&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep  6 13:43:08 2011
@@ -8861,8 +8861,8 @@
   assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
           EnableSegmentedStacks) &&
          "This should be used only on Windows targets or when segmented stacks "
-         "are being used.");
-  assert(!Subtarget->isTargetEnvMacho());
+         "are being used");
+  assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
   DebugLoc dl = Op.getDebugLoc();
 
   // Get the inputs.
@@ -8879,7 +8879,7 @@
 
     if (Is64Bit) {
       // The 64 bit implementation of segmented stacks needs to clobber both r10
-      // r11. This makes it impossible to use it along with nested paramenters.
+      // r11. This makes it impossible to use it along with nested parameters.
       const Function *F = MF.getFunction();
 
       for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();



From grosbach at apple.com  Tue Sep  6 13:46:23 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 18:46:23 -0000
Subject: [llvm-commits] [llvm] r139155 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20110906184623.6CF312A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep  6 13:46:23 2011
New Revision: 139155

URL: http://llvm.org/viewvc/llvm-project?rev=139155&view=rev
Log:
ARM .code directive should always go to the streamer.

Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139155&r1=139154&r2=139155&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Sep  6 13:46:23 2011
@@ -3797,15 +3797,13 @@
   Parser.Lex();
 
   if (Val == 16) {
-    if (!isThumb()) {
+    if (!isThumb())
       SwitchMode();
-      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
-    }
+    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
   } else {
-    if (isThumb()) {
+    if (isThumb())
       SwitchMode();
-      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
-    }
+    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
   }
 
   return false;



From rafael.espindola at gmail.com  Tue Sep  6 13:48:07 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Tue, 06 Sep 2011 14:48:07 -0400
Subject: [llvm-commits] [llvm] r138818 - in /llvm/trunk/lib/Target/X86:
 X86ISelLowering.cpp X86ISelLowering.h
In-Reply-To: <4E5DDB45.3000000@free.fr>
References: <20110830194704.AA1372A6C12C@llvm.org> <4E5DDB45.3000000@free.fr>
Message-ID: <4E666AE7.1060105@gmail.com>

> What are the restrictions on using segmented stacks with nested functions
> exactly?  Hopefully the implementation can fully support Go.  Does GCC have
> the same restrictions?

If I understand it correctly, it is an ABI issue (they want to use r10 
for different purposes), so yes. Sanjoy, is that the case?

Cheers,
Rafael

From dpatel at apple.com  Tue Sep  6 13:49:53 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 06 Sep 2011 18:49:53 -0000
Subject: [llvm-commits] [llvm] r139156 -
	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
Message-ID: <20110906184953.E714A2A6C12C@llvm.org>

Author: dpatel
Date: Tue Sep  6 13:49:53 2011
New Revision: 139156

URL: http://llvm.org/viewvc/llvm-project?rev=139156&view=rev
Log:
Use IRBuilder.

Modified:
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=139156&r1=139155&r2=139156&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Tue Sep  6 13:49:53 2011
@@ -811,7 +811,7 @@
   // Insert this computation right after this user.  Since our caller is
   // scanning from the top of the BB to the bottom, reuse of the expr are
   // guaranteed to happen later.
-  BasicBlock::iterator InsertPt = MemoryInst;
+  IRBuilder<> Builder(MemoryInst);
 
   // Now that we determined the addressing expression we want to use and know
   // that we have to sink it into this block.  Check to see if we have already
@@ -822,7 +822,7 @@
     DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrMode << " for "
                  << *MemoryInst);
     if (SunkAddr->getType() != Addr->getType())
-      SunkAddr = new BitCastInst(SunkAddr, Addr->getType(), "tmp", InsertPt);
+      SunkAddr = Builder.CreateBitCast(SunkAddr, Addr->getType(), "tmp");
   } else {
     DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for "
                  << *MemoryInst);
@@ -839,10 +839,9 @@
     if (AddrMode.BaseReg) {
       Value *V = AddrMode.BaseReg;
       if (V->getType()->isPointerTy())
-        V = new PtrToIntInst(V, IntPtrTy, "sunkaddr", InsertPt);
+        V = Builder.CreatePtrToInt(V, IntPtrTy, "sunkaddr");
       if (V->getType() != IntPtrTy)
-        V = CastInst::CreateIntegerCast(V, IntPtrTy, /*isSigned=*/true,
-                                        "sunkaddr", InsertPt);
+        V = Builder.CreateIntCast(V, IntPtrTy, /*isSigned=*/true, "sunkaddr");
       Result = V;
     }
 
@@ -852,29 +851,27 @@
       if (V->getType() == IntPtrTy) {
         // done.
       } else if (V->getType()->isPointerTy()) {
-        V = new PtrToIntInst(V, IntPtrTy, "sunkaddr", InsertPt);
+        V = Builder.CreatePtrToInt(V, IntPtrTy, "sunkaddr");
       } else if (cast<IntegerType>(IntPtrTy)->getBitWidth() <
                  cast<IntegerType>(V->getType())->getBitWidth()) {
-        V = new TruncInst(V, IntPtrTy, "sunkaddr", InsertPt);
+        V = Builder.CreateTrunc(V, IntPtrTy, "sunkaddr");
       } else {
-        V = new SExtInst(V, IntPtrTy, "sunkaddr", InsertPt);
+        V = Builder.CreateSExt(V, IntPtrTy, "sunkaddr");
       }
       if (AddrMode.Scale != 1)
-        V = BinaryOperator::CreateMul(V, ConstantInt::get(IntPtrTy,
-                                                                AddrMode.Scale),
-                                      "sunkaddr", InsertPt);
+        V = Builder.CreateMul(V, ConstantInt::get(IntPtrTy, AddrMode.Scale),
+                              "sunkaddr");
       if (Result)
-        Result = BinaryOperator::CreateAdd(Result, V, "sunkaddr", InsertPt);
+        Result = Builder.CreateAdd(Result, V, "sunkaddr");
       else
         Result = V;
     }
 
     // Add in the BaseGV if present.
     if (AddrMode.BaseGV) {
-      Value *V = new PtrToIntInst(AddrMode.BaseGV, IntPtrTy, "sunkaddr",
-                                  InsertPt);
+      Value *V = Builder.CreatePtrToInt(AddrMode.BaseGV, IntPtrTy, "sunkaddr");
       if (Result)
-        Result = BinaryOperator::CreateAdd(Result, V, "sunkaddr", InsertPt);
+        Result = Builder.CreateAdd(Result, V, "sunkaddr");
       else
         Result = V;
     }
@@ -883,7 +880,7 @@
     if (AddrMode.BaseOffs) {
       Value *V = ConstantInt::get(IntPtrTy, AddrMode.BaseOffs);
       if (Result)
-        Result = BinaryOperator::CreateAdd(Result, V, "sunkaddr", InsertPt);
+        Result = Builder.CreateAdd(Result, V, "sunkaddr");
       else
         Result = V;
     }
@@ -891,7 +888,7 @@
     if (Result == 0)
       SunkAddr = Constant::getNullValue(Addr->getType());
     else
-      SunkAddr = new IntToPtrInst(Result, Addr->getType(), "sunkaddr",InsertPt);
+      SunkAddr = Builder.CreateIntToPtr(Result, Addr->getType(), "sunkaddr");
   }
 
   MemoryInst->replaceUsesOfWith(Repl, SunkAddr);



From evan.cheng at apple.com  Tue Sep  6 13:52:21 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 06 Sep 2011 18:52:21 -0000
Subject: [llvm-commits] [llvm] r139157 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td
 lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/carry.ll
Message-ID: <20110906185221.2FCBE2A6C12C@llvm.org>

Author: evancheng
Date: Tue Sep  6 13:52:20 2011
New Revision: 139157

URL: http://llvm.org/viewvc/llvm-project?rev=139157&view=rev
Log:
Fix fall outs from my recent change on how carry bit is modeled during isel.
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/CodeGen/ARM/carry.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=139157&r1=139156&r2=139157&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Sep  6 13:52:20 2011
@@ -5708,7 +5708,7 @@
   // the optional operand to CPSR. Otherwise, remove the CPSR implicit def.
   const MCInstrDesc &MCID = MI->getDesc();
   if (Node->hasAnyUseOfValue(1)) {
-    MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 2);
+    MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 1);
     MO.setReg(ARM::CPSR);
     MO.setIsDef(true);
   } else {

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139157&r1=139156&r2=139157&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Sep  6 13:52:20 2011
@@ -1037,8 +1037,8 @@
 
 }
 
-/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except sets 's' bit.
-let isCodeGenOnly = 1, Defs = [CPSR] in {
+/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except it sets 's' bit by default.
+let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
 multiclass AsI1_rbin_s_is<bits<4> opcod, string opc,
                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
                         PatFrag opnode, bit Commutable = 0> {
@@ -1101,25 +1101,25 @@
 }
 }
 
-/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
-/// instruction modifies the CPSR register.
-let isCodeGenOnly = 1, Defs = [CPSR] in {
-multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
+/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
+let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
+multiclass AsI1_bin_s_irs<bits<4> opcod, string opc,
                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
                          PatFrag opnode, bit Commutable = 0> {
-  def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
+  let isReMaterializable = 1 in {
+  def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
                iii, opc, "\t$Rd, $Rn, $imm",
                [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]> {
     bits<4> Rd;
     bits<4> Rn;
     bits<12> imm;
     let Inst{25} = 1;
-    let Inst{20} = 1;
     let Inst{19-16} = Rn;
     let Inst{15-12} = Rd;
     let Inst{11-0} = imm;
   }
-  def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
+  }
+  def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
                iir, opc, "\t$Rd, $Rn, $Rm",
                [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
     bits<4> Rd;
@@ -1127,13 +1127,12 @@
     bits<4> Rm;
     let isCommutable = Commutable;
     let Inst{25} = 0;
-    let Inst{20} = 1;
     let Inst{19-16} = Rn;
     let Inst{15-12} = Rd;
     let Inst{11-4} = 0b00000000;
     let Inst{3-0} = Rm;
   }
-  def rsi : AI1<opcod, (outs GPR:$Rd),
+  def rsi : AsI1<opcod, (outs GPR:$Rd),
                (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
                iis, opc, "\t$Rd, $Rn, $shift",
                [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
@@ -1141,7 +1140,6 @@
     bits<4> Rn;
     bits<12> shift;
     let Inst{25} = 0;
-    let Inst{20} = 1;
     let Inst{19-16} = Rn;
     let Inst{15-12} = Rd;
     let Inst{11-5} = shift{11-5};
@@ -1149,7 +1147,7 @@
     let Inst{3-0} = shift{3-0};
   }
 
-  def rsr : AI1<opcod, (outs GPR:$Rd),
+  def rsr : AsI1<opcod, (outs GPR:$Rd),
                (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
                iis, opc, "\t$Rd, $Rn, $shift",
                [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
@@ -3136,10 +3134,12 @@
                          BinOpFrag<(sub  node:$LHS, node:$RHS)>, "SUB">;
 
 // ADD and SUB with 's' bit set.
-defm ADDS : AI1_bin_s_irs<0b0100, "adds",
+// FIXME: Eliminate them if we can write def : Pat patterns which defines
+// CPSR and the implicit def of CPSR is not needed.
+defm ADDS : AsI1_bin_s_irs<0b0100, "add",
                           IIC_iALUi, IIC_iALUr, IIC_iALUsr,
                           BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
-defm SUBS : AI1_bin_s_irs<0b0010, "subs",
+defm SUBS : AsI1_bin_s_irs<0b0010, "sub",
                           IIC_iALUi, IIC_iALUr, IIC_iALUsr,
                           BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
 
@@ -3153,6 +3153,9 @@
 defm RSB  : AsI1_rbin_irs <0b0011, "rsb",
                          IIC_iALUi, IIC_iALUr, IIC_iALUsr,
                          BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
+
+// FIXME: Eliminate them if we can write def : Pat patterns which defines
+// CPSR and the implicit def of CPSR is not needed.
 defm RSBS : AsI1_rbin_s_is<0b0011, "rsb",
                          IIC_iALUi, IIC_iALUr, IIC_iALUsr,
                          BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139157&r1=139156&r2=139157&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep  6 13:52:20 2011
@@ -588,44 +588,41 @@
 
 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
 /// instruction modifies the CPSR register.
-let isCodeGenOnly = 1, Defs = [CPSR] in {
+let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
                          PatFrag opnode, bit Commutable = 0> {
    // shifted imm
-   def ri : T2TwoRegImm<
+   def ri : T2sTwoRegImm<
                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
-                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
+                opc, ".w\t$Rd, $Rn, $imm",
                 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
      let Inst{31-27} = 0b11110;
      let Inst{25} = 0;
      let Inst{24-21} = opcod;
-     let Inst{20} = 1; // The S bit.
      let Inst{15} = 0;
    }
    // register
-   def rr : T2ThreeReg<
+   def rr : T2sThreeReg<
                 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
-                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
+                opc, ".w\t$Rd, $Rn, $Rm",
                 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
      let isCommutable = Commutable;
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
-     let Inst{20} = 1; // The S bit.
      let Inst{14-12} = 0b000; // imm3
      let Inst{7-6} = 0b00; // imm2
      let Inst{5-4} = 0b00; // type
    }
    // shifted register
-   def rs : T2TwoRegShiftedReg<
+   def rs : T2sTwoRegShiftedReg<
                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
-                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
+                opc, ".w\t$Rd, $Rn, $ShiftedRm",
                [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
-     let Inst{20} = 1; // The S bit.
    }
 }
 }
@@ -737,28 +734,26 @@
 
 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
 /// version is not needed since this is only for codegen.
-let isCodeGenOnly = 1, Defs = [CPSR] in {
+let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
    // shifted imm
-   def ri : T2TwoRegImm<
+   def ri : T2sTwoRegImm<
                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
-                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
+                opc, ".w\t$Rd, $Rn, $imm",
                 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
      let Inst{31-27} = 0b11110;
      let Inst{25} = 0;
      let Inst{24-21} = opcod;
-     let Inst{20} = 1; // The S bit.
      let Inst{15} = 0;
    }
    // shifted register
-   def rs : T2TwoRegShiftedReg<
+   def rs : T2sTwoRegShiftedReg<
                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
-                IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
+                IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
               [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
-     let Inst{20} = 1; // The S bit.
    }
 }
 }
@@ -1699,6 +1694,8 @@
                              BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
 
 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
+// FIXME: Eliminate them if we can write def : Pat patterns which defines
+// CPSR and the implicit def of CPSR is not needed.
 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
                              IIC_iALUi, IIC_iALUr, IIC_iALUsi,
                              BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
@@ -1716,6 +1713,9 @@
 // RSB
 defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb",
                              BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
+
+// FIXME: Eliminate them if we can write def : Pat patterns which defines
+// CPSR and the implicit def of CPSR is not needed.
 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
                              BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
 

Modified: llvm/trunk/test/CodeGen/ARM/carry.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/carry.ll?rev=139157&r1=139156&r2=139157&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/carry.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/carry.ll Tue Sep  6 13:52:20 2011
@@ -35,3 +35,13 @@
 	%dw = add i64 %ch, %bw
 	ret i64 %dw
 }
+
+; rdar://10073745
+define i64 @f4(i64 %x) nounwind readnone {
+entry:
+; CHECK: f4:
+; CHECK: rsbs r
+; CHECK: rsc r
+  %0 = sub nsw i64 0, %x
+  ret i64 %0
+}



From baldrick at free.fr  Tue Sep  6 14:07:46 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 06 Sep 2011 19:07:46 -0000
Subject: [llvm-commits] [llvm] r139159 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/
 lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/
 lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/
 lib/Target/PowerPC/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/
 lib/VMCore/
Message-ID: <20110906190747.A0DD02A6C12C@llvm.org>

Author: baldrick
Date: Tue Sep  6 14:07:46 2011
New Revision: 139159

URL: http://llvm.org/viewvc/llvm-project?rev=139159&view=rev
Log:
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

Modified:
    llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/include/llvm/CodeGen/ValueTypes.h
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.h
    llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
    llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h
    llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
    llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
    llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h
    llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.h
    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
    llvm/trunk/lib/Target/PTX/PTXISelLowering.h
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
    llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
    llvm/trunk/lib/VMCore/ValueTypes.cpp

Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Tue Sep  6 14:07:46 2011
@@ -323,6 +323,12 @@
     // i1 then the high bits must conform to getBooleanContents.
     SELECT,
 
+    // Select with a vector condition (op #0) and two vector operands (ops #1
+    // and #2), returning a vector result.  All vectors have the same length.
+    // Much like the scalar select and setcc, each bit in the condition selects
+    // whether the corresponding result element is taken from op #1 or op #2.
+    VSELECT,
+
     // Select with condition operator - This selects between a true value and
     // a false value (ops #2 and #3) based on the boolean result of comparing
     // the lhs and rhs (ops #0 and #1) of a conditional expression with the
@@ -333,16 +339,10 @@
     // true.  If the result value type is not i1 then the high bits conform
     // to getBooleanContents.  The operands to this are the left and right
     // operands to compare (ops #0, and #1) and the condition code to compare
-    // them with (op #2) as a CondCodeSDNode.
+    // them with (op #2) as a CondCodeSDNode. If the operands are vector types
+    // then the result type must also be a vector type.
     SETCC,
 
-    // RESULT = VSETCC(LHS, RHS, COND) operator - This evaluates to a vector of
-    // integer elements with all bits of the result elements set to true if the
-    // comparison is true or all cleared if the comparison is false.  The
-    // operands to this are the left and right operands to compare (LHS/RHS) and
-    // the condition code to compare them with (COND) as a CondCodeSDNode.
-    VSETCC,
-
     // SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
     // integer shift operations, just like ADD/SUB_PARTS.  The operation
     // ordering is:

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Sep  6 14:07:46 2011
@@ -560,17 +560,13 @@
   ///
   SDValue getSetCC(DebugLoc DL, EVT VT, SDValue LHS, SDValue RHS,
                    ISD::CondCode Cond) {
+    assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() &&
+      "Cannot compare scalars to vectors");
+    assert(LHS.getValueType().isVector() == VT.isVector() &&
+      "Cannot compare scalars to vectors");
     return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
   }
 
-  /// getVSetCC - Helper function to make it easier to build VSetCC's nodes
-  /// if you just have an ISD::CondCode instead of an SDValue.
-  ///
-  SDValue getVSetCC(DebugLoc DL, EVT VT, SDValue LHS, SDValue RHS,
-                    ISD::CondCode Cond) {
-    return getNode(ISD::VSETCC, DL, VT, LHS, RHS, getCondCode(Cond));
-  }
-
   /// getSelectCC - Helper function to make it easier to build SelectCC's if you
   /// just have an ISD::CondCode instead of an SDValue.
   ///

Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Tue Sep  6 14:07:46 2011
@@ -438,6 +438,21 @@
       return MVT::INVALID_SIMPLE_VALUE_TYPE;
     }
 
+    /// changeVectorElementTypeToInteger - Return a vector with the same number
+    /// of elements as this vector, but with the element type converted to an
+    /// integer type with the same bitwidth.
+    EVT changeVectorElementTypeToInteger() const {
+      if (!isSimple())
+        return changeExtendedVectorElementTypeToInteger();
+      MVT EltTy = getSimpleVT().getVectorElementType();
+      unsigned BitWidth = EltTy.getSizeInBits();
+      MVT IntTy = MVT::getIntegerVT(BitWidth);
+      MVT VecTy = MVT::getVectorVT(IntTy, getVectorNumElements());
+      assert(VecTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
+             "Simple vector VT not representable by simple integer vector VT!");
+      return VecTy;
+    }
+
     /// isSimple - Test if the given EVT is simple (as opposed to being
     /// extended).
     bool isSimple() const {
@@ -674,6 +689,7 @@
     // Methods for handling the Extended-type case in functions above.
     // These are all out-of-line to prevent users of this header file
     // from having a dependency on Type.h.
+    EVT changeExtendedVectorElementTypeToInteger() const;
     static EVT getExtendedIntegerVT(LLVMContext &C, unsigned BitWidth);
     static EVT getExtendedVectorVT(LLVMContext &C, EVT VT,
                                    unsigned NumElements);

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Tue Sep  6 14:07:46 2011
@@ -113,6 +113,22 @@
     ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
   };
 
+  static ISD::NodeType getExtendForContent(BooleanContent Content) {
+    switch (Content) {
+    default:
+      assert(false && "Unknown BooleanContent!");
+    case UndefinedBooleanContent:
+      // Extend by adding rubbish bits.
+      return ISD::ANY_EXTEND;
+    case ZeroOrOneBooleanContent:
+      // Extend by adding zero bits.
+      return ISD::ZERO_EXTEND;
+    case ZeroOrNegativeOneBooleanContent:
+      // Extend by copying the sign bit.
+      return ISD::SIGN_EXTEND;
+    }
+  }
+
   /// NOTE: The constructor takes ownership of TLOF.
   explicit TargetLowering(const TargetMachine &TM,
                           const TargetLoweringObjectFile *TLOF);
@@ -148,8 +164,7 @@
   /// the condition operand of SELECT and BRCOND nodes.  In the case of
   /// BRCOND the argument passed is MVT::Other since there are no other
   /// operands to get a type hint from.
-  virtual
-  MVT::SimpleValueType getSetCCResultType(EVT VT) const;
+  virtual EVT getSetCCResultType(EVT VT) const;
 
   /// getCmpLibcallReturnType - Return the ValueType for comparison
   /// libcalls. Comparions libcalls include floating point comparion calls,
@@ -162,7 +177,13 @@
   /// "Boolean values" are special true/false values produced by nodes like
   /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
   /// Not to be confused with general values promoted from i1.
-  BooleanContent getBooleanContents() const { return BooleanContents;}
+  /// Some cpus distinguish between vectors of boolean and scalars; the isVec
+  /// parameter selects between the two kinds.  For example on X86 a scalar
+  /// boolean should be zero extended from i1, while the elements of a vector
+  /// of booleans should be sign extended from i1.
+  BooleanContent getBooleanContents(bool isVec) const {
+    return isVec ? BooleanVectorContents : BooleanContents;
+  }
 
   /// getSchedulingPreference - Return target scheduling preference.
   Sched::Preference getSchedulingPreference() const {
@@ -938,6 +959,12 @@
   /// setBooleanContents - Specify how the target extends the result of a
   /// boolean value from i1 to a wider type.  See getBooleanContents.
   void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
+  /// setBooleanVectorContents - Specify how the target extends the result
+  /// of a vector boolean value from a vector of i1 to a wider type.  See
+  /// getBooleanContents.
+  void setBooleanVectorContents(BooleanContent Ty) {
+    BooleanVectorContents = Ty;
+  }
 
   /// setSchedulingPreference - Specify the target scheduling preference.
   void setSchedulingPreference(Sched::Preference Pref) {
@@ -1657,6 +1684,10 @@
   /// BooleanContents - Information about the contents of the high-bits in
   /// boolean values held in a type wider than i1.  See getBooleanContents.
   BooleanContent BooleanContents;
+  /// BooleanVectorContents - Information about the contents of the high-bits
+  /// in boolean vector values when the element type is wider than i1.  See
+  /// getBooleanContents.
+  BooleanContent BooleanVectorContents;
 
   /// SchedPreferenceInfo - The target scheduling preference: shortest possible
   /// total cycles or lowest register usage.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Sep  6 14:07:46 2011
@@ -3757,7 +3757,7 @@
   if (VT.isInteger() &&
       (VT0 == MVT::i1 ||
        (VT0.isInteger() &&
-        TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
+        TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) &&
       N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
     SDValue XORNode;
     if (VT == VT0)
@@ -4112,7 +4112,7 @@
         // we know that the element size of the sext'd result matches the
         // element size of the compare operands.
       if (VT.getSizeInBits() == N0VT.getSizeInBits())
-        return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
+        return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
                              N0.getOperand(1),
                              cast<CondCodeSDNode>(N0.getOperand(2))->get());
       // If the desired elements are smaller or larger than the source
@@ -4126,7 +4126,7 @@
           EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
                            N0VT.getVectorNumElements());
         SDValue VsetCC =
-          DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
+          DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
                         N0.getOperand(1),
                         cast<CondCodeSDNode>(N0.getOperand(2))->get());
         return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
@@ -4342,7 +4342,7 @@
         // we know that the element size of the sext'd result matches the
         // element size of the compare operands.
         return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
-                           DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
+                           DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
                                          N0.getOperand(1),
                                  cast<CondCodeSDNode>(N0.getOperand(2))->get()),
                            DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
@@ -4358,7 +4358,7 @@
         EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
                          N0VT.getVectorNumElements());
       SDValue VsetCC =
-        DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
+        DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
                       N0.getOperand(1),
                       cast<CondCodeSDNode>(N0.getOperand(2))->get());
       return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
@@ -4526,7 +4526,7 @@
         // we know that the element size of the sext'd result matches the
         // element size of the compare operands.
       if (VT.getSizeInBits() == N0VT.getSizeInBits())
-        return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
+        return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
                              N0.getOperand(1),
                              cast<CondCodeSDNode>(N0.getOperand(2))->get());
       // If the desired elements are smaller or larger than the source
@@ -4540,7 +4540,7 @@
           EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
                            N0VT.getVectorNumElements());
         SDValue VsetCC =
-          DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
+          DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
                         N0.getOperand(1),
                         cast<CondCodeSDNode>(N0.getOperand(2))->get());
         return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
@@ -7547,7 +7547,8 @@
 
   // fold select C, 16, 0 -> shl C, 4
   if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
-      TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
+    TLI.getBooleanContents(N0.getValueType().isVector()) ==
+      TargetLowering::ZeroOrOneBooleanContent) {
 
     // If the caller doesn't want us to simplify this into a zext of a compare,
     // don't do it.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Sep  6 14:07:46 2011
@@ -475,11 +475,13 @@
 
 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
   EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
-  assert(isTypeLegal(SVT) && "Illegal SetCC type!");
+
   DebugLoc dl = N->getDebugLoc();
+  assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
+         "Vector compare must return a vector result!");
 
   // Get the SETCC result using the canonical SETCC type.
-  SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
+  SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
                               N->getOperand(1), N->getOperand(2));
 
   // Convert to the expected type.
@@ -729,6 +731,7 @@
   case ISD::MEMBARRIER:   Res = PromoteIntOp_MEMBARRIER(N); break;
   case ISD::SCALAR_TO_VECTOR:
                           Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
+  case ISD::VSELECT:
   case ISD::SELECT:       Res = PromoteIntOp_SELECT(N, OpNo); break;
   case ISD::SELECT_CC:    Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
   case ISD::SETCC:        Res = PromoteIntOp_SETCC(N, OpNo); break;
@@ -921,14 +924,17 @@
 }
 
 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
-  assert(OpNo == 0 && "Only know how to promote condition");
+  assert(OpNo == 0 && "Only know how to promote the condition!");
+  SDValue Cond = N->getOperand(0);
+  EVT OpTy = N->getOperand(1).getValueType();
 
   // Promote all the way up to the canonical SetCC type.
-  EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
-  SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
+  EVT SVT = TLI.getSetCCResultType(N->getOpcode() == ISD::SELECT ?
+                                   OpTy.getScalarType() : OpTy);
+  Cond = PromoteTargetBoolean(Cond, SVT);
 
-  return SDValue(DAG.UpdateNodeOperands(N, Cond,
-                                N->getOperand(1), N->getOperand(2)), 0);
+  return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
+                                        N->getOperand(2)), 0);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Tue Sep  6 14:07:46 2011
@@ -1113,24 +1113,8 @@
 /// type i1, the bits of which conform to getBooleanContents.
 SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, EVT VT) {
   DebugLoc dl = Bool.getDebugLoc();
-  ISD::NodeType ExtendCode;
-  switch (TLI.getBooleanContents()) {
-  default:
-    assert(false && "Unknown BooleanContent!");
-  case TargetLowering::UndefinedBooleanContent:
-    // Extend to VT by adding rubbish bits.
-    ExtendCode = ISD::ANY_EXTEND;
-    break;
-  case TargetLowering::ZeroOrOneBooleanContent:
-    // Extend to VT by adding zero bits.
-    ExtendCode = ISD::ZERO_EXTEND;
-    break;
-  case TargetLowering::ZeroOrNegativeOneBooleanContent: {
-    // Extend to VT by copying the sign bit.
-    ExtendCode = ISD::SIGN_EXTEND;
-    break;
-  }
-  }
+  ISD::NodeType ExtendCode =
+    TargetLowering::getExtendForContent(TLI.getBooleanContents(VT.isVector()));
   return DAG.getNode(ExtendCode, dl, VT, Bool);
 }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Tue Sep  6 14:07:46 2011
@@ -272,6 +272,7 @@
   SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
+  SDValue PromoteIntOp_VSETCC(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_Shift(SDNode *N);
   SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
   SDValue PromoteIntOp_SINT_TO_FP(SDNode *N);
@@ -573,6 +574,7 @@
   SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
   SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
   SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N);
+  SDValue SplitVecOp_VSETCC(SDNode *N);
   SDValue SplitVecOp_FP_ROUND(SDNode *N);
 
   //===--------------------------------------------------------------------===//

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Tue Sep  6 14:07:46 2011
@@ -439,14 +439,26 @@
 
 void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo,
                                        SDValue &Hi) {
-  SDValue LL, LH, RL, RH;
+  SDValue LL, LH, RL, RH, CL, CH;
   DebugLoc dl = N->getDebugLoc();
   GetSplitOp(N->getOperand(1), LL, LH);
   GetSplitOp(N->getOperand(2), RL, RH);
 
   SDValue Cond = N->getOperand(0);
-  Lo = DAG.getNode(ISD::SELECT, dl, LL.getValueType(), Cond, LL, RL);
-  Hi = DAG.getNode(ISD::SELECT, dl, LH.getValueType(), Cond, LH, RH);
+  CL = CH = Cond;
+  if (Cond.getValueType().isVector()) {
+    assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&
+           "Condition legalized before result?");
+    unsigned NumElements = Cond.getValueType().getVectorNumElements();
+    EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2);
+    CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
+                     DAG.getIntPtrConstant(0));
+    CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
+                     DAG.getIntPtrConstant(NumElements / 2));
+  }
+
+  Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL);
+  Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH);
 }
 
 void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDValue &Lo,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Tue Sep  6 14:07:46 2011
@@ -158,7 +158,7 @@
   case ISD::CTPOP:
   case ISD::SELECT:
   case ISD::SELECT_CC:
-  case ISD::VSETCC:
+  case ISD::SETCC:
   case ISD::ZERO_EXTEND:
   case ISD::ANY_EXTEND:
   case ISD::TRUNCATE:
@@ -214,7 +214,7 @@
       Result = ExpandUINT_TO_FLOAT(Op);
     else if (Node->getOpcode() == ISD::FNEG)
       Result = ExpandFNEG(Op);
-    else if (Node->getOpcode() == ISD::VSETCC)
+    else if (Node->getOpcode() == ISD::SETCC)
       Result = UnrollVSETCC(Op);
     else
       Result = DAG.UnrollVectorOp(Op.getNode());

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Sep  6 14:07:46 2011
@@ -64,8 +64,6 @@
   case ISD::SETCC:             R = ScalarizeVecRes_SETCC(N); break;
   case ISD::UNDEF:             R = ScalarizeVecRes_UNDEF(N); break;
   case ISD::VECTOR_SHUFFLE:    R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
-  case ISD::VSETCC:            R = ScalarizeVecRes_VSETCC(N); break;
-
   case ISD::ANY_EXTEND:
   case ISD::CTLZ:
   case ISD::CTPOP:
@@ -244,6 +242,12 @@
 }
 
 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
+  assert(N->getValueType(0).isVector() ==
+         N->getOperand(0).getValueType().isVector() &&
+         "Scalar/Vector type mismatch");
+
+  if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
+
   SDValue LHS = GetScalarizedVector(N->getOperand(0));
   SDValue RHS = GetScalarizedVector(N->getOperand(1));
   DebugLoc DL = N->getDebugLoc();
@@ -266,35 +270,23 @@
 }
 
 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
+  assert(N->getValueType(0).isVector() &&
+         N->getOperand(0).getValueType().isVector() &&
+         "Operand types must be vectors");
+
   SDValue LHS = GetScalarizedVector(N->getOperand(0));
   SDValue RHS = GetScalarizedVector(N->getOperand(1));
   EVT NVT = N->getValueType(0).getVectorElementType();
-  EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
   DebugLoc DL = N->getDebugLoc();
 
   // Turn it into a scalar SETCC.
-  SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
-
-  // VSETCC always returns a sign-extended value, while SETCC may not.  The
-  // SETCC result type may not match the vector element type.  Correct these.
-  if (NVT.bitsLE(SVT)) {
-    // The SETCC result type is bigger than the vector element type.
-    // Ensure the SETCC result is sign-extended.
-    if (TLI.getBooleanContents() !=
-        TargetLowering::ZeroOrNegativeOneBooleanContent)
-      Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
-                        DAG.getValueType(MVT::i1));
-    // Truncate to the final type.
-    return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
-  }
-
-  // The SETCC result type is smaller than the vector element type.
-  // If the SetCC result is not sign-extended, chop it down to MVT::i1.
-  if (TLI.getBooleanContents() !=
-        TargetLowering::ZeroOrNegativeOneBooleanContent)
-    Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
-  // Sign extend to the final type.
-  return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
+  SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
+                            N->getOperand(2));
+  // Vectors may have a different boolean contents to scalars.  Promote the
+  // value appropriately.
+  ISD::NodeType ExtendCode =
+    TargetLowering::getExtendForContent(TLI.getBooleanContents(true));
+  return DAG.getNode(ExtendCode, DL, NVT, Res);
 }
 
 
@@ -423,6 +415,7 @@
     llvm_unreachable("Do not know how to split the result of this operator!");
 
   case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
+  case ISD::VSELECT:
   case ISD::SELECT:       SplitRes_SELECT(N, Lo, Hi); break;
   case ISD::SELECT_CC:    SplitRes_SELECT_CC(N, Lo, Hi); break;
   case ISD::UNDEF:        SplitRes_UNDEF(N, Lo, Hi); break;
@@ -439,7 +432,6 @@
     SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
     break;
   case ISD::SETCC:
-  case ISD::VSETCC:
     SplitVecRes_SETCC(N, Lo, Hi);
     break;
   case ISD::VECTOR_SHUFFLE:
@@ -746,6 +738,10 @@
 }
 
 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
+  assert(N->getValueType(0).isVector() &&
+         N->getOperand(0).getValueType().isVector() &&
+         "Operand types must be vectors");
+
   EVT LoVT, HiVT;
   DebugLoc DL = N->getDebugLoc();
   GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
@@ -971,7 +967,7 @@
       dbgs() << "\n";
 #endif
       llvm_unreachable("Do not know how to split this operator's operand!");
-
+    case ISD::SETCC:             Res = SplitVecOp_VSETCC(N); break;
     case ISD::BITCAST:           Res = SplitVecOp_BITCAST(N); break;
     case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
     case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
@@ -1169,6 +1165,26 @@
                      &Elts[0], Elts.size());
 }
 
+SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
+  assert(N->getValueType(0).isVector() &&
+         N->getOperand(0).getValueType().isVector() &&
+         "Operand types must be vectors");
+  // The result has a legal vector type, but the input needs splitting.
+  SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
+  DebugLoc DL = N->getDebugLoc();
+  GetSplitVector(N->getOperand(0), Lo0, Hi0);
+  GetSplitVector(N->getOperand(1), Lo1, Hi1);
+  unsigned PartElements = Lo0.getValueType().getVectorNumElements();
+  EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
+  EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
+
+  LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
+  HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
+  SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
+  return PromoteTargetBoolean(Con, N->getValueType(0));
+}
+
+
 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
   // The result has a legal vector type, but the input needs splitting.
   EVT ResVT = N->getValueType(0);
@@ -1229,10 +1245,6 @@
   case ISD::VECTOR_SHUFFLE:
     Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
     break;
-  case ISD::VSETCC:
-    Res = WidenVecRes_VSETCC(N);
-    break;
-
   case ISD::ADD:
   case ISD::AND:
   case ISD::BSWAP:
@@ -1929,6 +1941,11 @@
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
+  assert(N->getValueType(0).isVector() ==
+         N->getOperand(0).getValueType().isVector() &&
+         "Scalar/Vector type mismatch");
+  if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
+
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDValue InOp1 = GetWidenedVector(N->getOperand(0));
   SDValue InOp2 = GetWidenedVector(N->getOperand(1));
@@ -1967,6 +1984,9 @@
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
+  assert(N->getValueType(0).isVector() &&
+         N->getOperand(0).getValueType().isVector() &&
+         "Operands must be vectors");
   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   unsigned WidenNumElts = WidenVT.getVectorNumElements();
 
@@ -1984,7 +2004,7 @@
          InOp2.getValueType() == WidenInVT &&
          "Input not widened to expected type!");
   (void)WidenInVT;
-  return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
+  return DAG.getNode(ISD::SETCC, N->getDebugLoc(),
                      WidenVT, InOp1, InOp2, N->getOperand(2));
 }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep  6 14:07:46 2011
@@ -927,13 +927,25 @@
   assert(VT.isInteger() && "Cannot create FP integer constant!");
 
   EVT EltVT = VT.getScalarType();
-  assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
-         "APInt size does not match type size!");
+  const ConstantInt *Elt = &Val;
+
+  // In some cases the vector type is legal but the element type is illegal and
+  // needs to be promoted, for example v8i8 on ARM.  In this case, promote the
+  // inserted value (the type does not need to match the vector element type).
+  // Any extra bits introduced will be truncated away.
+  if (VT.isVector() && TLI.getTypeAction(*getContext(), EltVT) ==
+      TargetLowering::TypePromoteInteger) {
+   EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT);
+   APInt NewVal = Elt->getValue().zext(EltVT.getSizeInBits());
+   Elt = ConstantInt::get(*getContext(), NewVal);
+  }
 
+  assert(Elt->getBitWidth() == EltVT.getSizeInBits() &&
+         "APInt size does not match type size!");
   unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
   FoldingSetNodeID ID;
   AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
-  ID.AddPointer(&Val);
+  ID.AddPointer(Elt);
   void *IP = 0;
   SDNode *N = NULL;
   if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
@@ -941,7 +953,7 @@
       return SDValue(N, 0);
 
   if (!N) {
-    N = new (NodeAllocator) ConstantSDNode(isT, &Val, EltVT);
+    N = new (NodeAllocator) ConstantSDNode(isT, Elt, EltVT);
     CSEMap.InsertNode(N, IP);
     AllNodes.push_back(N);
   }
@@ -1720,8 +1732,8 @@
     // The boolean result conforms to getBooleanContents.  Fall through.
   case ISD::SETCC:
     // If we know the result of a setcc has the top bits zero, use this info.
-    if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent &&
-        BitWidth > 1)
+    if (TLI.getBooleanContents(Op.getValueType().isVector()) ==
+        TargetLowering::ZeroOrOneBooleanContent && BitWidth > 1)
       KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
     return;
   case ISD::SHL:
@@ -2155,7 +2167,7 @@
     // The boolean result conforms to getBooleanContents.  Fall through.
   case ISD::SETCC:
     // If setcc returns 0/-1, all bits are sign bits.
-    if (TLI.getBooleanContents() ==
+    if (TLI.getBooleanContents(Op.getValueType().isVector()) ==
         TargetLowering::ZeroOrNegativeOneBooleanContent)
       return VTBits;
     break;
@@ -5965,8 +5977,8 @@
 
   case ISD::FPOWI:  return "fpowi";
   case ISD::SETCC:       return "setcc";
-  case ISD::VSETCC:      return "vsetcc";
   case ISD::SELECT:      return "select";
+  case ISD::VSELECT:     return "vselect";
   case ISD::SELECT_CC:   return "select_cc";
   case ISD::INSERT_VECTOR_ELT:   return "insert_vector_elt";
   case ISD::EXTRACT_VECTOR_ELT:  return "extract_vector_elt";

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Sep  6 14:07:46 2011
@@ -2626,10 +2626,12 @@
   SDValue Cond     = getValue(I.getOperand(0));
   SDValue TrueVal  = getValue(I.getOperand(1));
   SDValue FalseVal = getValue(I.getOperand(2));
+  ISD::NodeType OpCode = Cond.getValueType().isVector() ?
+    ISD::VSELECT : ISD::SELECT;
 
   for (unsigned i = 0; i != NumValues; ++i)
-    Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
-                          TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
+    Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
+                            TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
                             Cond,
                             SDValue(TrueVal.getNode(),
                                     TrueVal.getResNo() + i),

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Sep  6 14:07:46 2011
@@ -609,6 +609,7 @@
   ExceptionPointerRegister = 0;
   ExceptionSelectorRegister = 0;
   BooleanContents = UndefinedBooleanContent;
+  BooleanVectorContents = UndefinedBooleanContent;
   SchedPreferenceInfo = Sched::Latency;
   JumpBufSize = 0;
   JumpBufAlignment = 0;
@@ -915,7 +916,8 @@
 }
 
 
-MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
+EVT TargetLowering::getSetCCResultType(EVT VT) const {
+  assert(!VT.isVector() && "No default SetCC type for vectors!");
   return PointerTy.SimpleTy;
 }
 
@@ -2191,7 +2193,7 @@
         }
       } else if (N1C->getAPIntValue() == 1 &&
                  (VT == MVT::i1 ||
-                  getBooleanContents() == ZeroOrOneBooleanContent)) {
+                  getBooleanContents(false) == ZeroOrOneBooleanContent)) {
         SDValue Op0 = N0;
         if (Op0.getOpcode() == ISD::TRUNCATE)
           Op0 = Op0.getOperand(0);

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -106,7 +106,7 @@
 
   EVT ElemTy = VT.getVectorElementType();
   if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
-    setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
+    setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
   setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
   if (ElemTy != MVT::i32) {
     setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
@@ -178,6 +178,8 @@
   RegInfo = TM.getRegisterInfo();
   Itins = TM.getInstrItineraryData();
 
+  setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
+
   if (Subtarget->isTargetDarwin()) {
     // Uses VFP for Thumb libfuncs if available.
     if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
@@ -453,7 +455,7 @@
     setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
     setOperationAction(ISD::FREM, MVT::v2f64, Expand);
     setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
-    setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
+    setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
     setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
     setOperationAction(ISD::FABS, MVT::v2f64, Expand);
     setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
@@ -485,8 +487,8 @@
     setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
     setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
     setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
-    setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
-    setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
+    setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
+    setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
     // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
     // a destination type that is wider than the source.
     setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
@@ -930,6 +932,11 @@
   }
 }
 
+EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
+  if (!VT.isVector()) return getPointerTy();
+  return VT.changeVectorElementTypeToInteger();
+}
+
 /// getRegClassFor - Return the register class that should be used for the
 /// specified value type.
 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
@@ -4925,7 +4932,7 @@
   case ISD::SRL_PARTS:
   case ISD::SRA_PARTS:     return LowerShiftRightParts(Op, DAG);
   case ISD::CTTZ:          return LowerCTTZ(Op.getNode(), DAG, Subtarget);
-  case ISD::VSETCC:        return LowerVSETCC(Op, DAG);
+  case ISD::SETCC:         return LowerVSETCC(Op, DAG);
   case ISD::BUILD_VECTOR:  return LowerBUILD_VECTOR(Op, DAG, Subtarget);
   case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
   case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Sep  6 14:07:46 2011
@@ -255,6 +255,9 @@
 
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
+    /// getSetCCResultType - Return the value type to use for ISD::SETCC.
+    virtual EVT getSetCCResultType(EVT VT) const;
+
     virtual MachineBasicBlock *
       EmitInstrWithCustomInserter(MachineInstr *MI,
                                   MachineBasicBlock *MBB) const;

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -49,6 +49,7 @@
   // Set up the TargetLowering object.
   //I am having problems with shr n i8 1
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
 
   addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
   addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
@@ -168,7 +169,7 @@
   computeRegisterProperties();
 }
 
-MVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(EVT VT) const {
+EVT AlphaTargetLowering::getSetCCResultType(EVT VT) const {
   return MVT::i64;
 }
 

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h Tue Sep  6 14:07:46 2011
@@ -66,7 +66,7 @@
     virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i64; }
 
     /// getSetCCResultType - Get the SETCC result ValueType
-    virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
+    virtual EVT getSetCCResultType(EVT VT) const;
 
     /// LowerOperation - Provide custom lowering hooks for some operations.
     ///

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -42,6 +42,7 @@
 BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
   setStackPointerRegisterToSaveRestore(BF::SP);
   setIntDivIsCheap(false);
 
@@ -135,7 +136,7 @@
   }
 }
 
-MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
+EVT BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
   // SETCC always sets the CC register. Technically that is an i1 register, but
   // that type is not legal, so we treat it as an i32 register.
   return MVT::i32;

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h Tue Sep  6 14:07:46 2011
@@ -33,7 +33,7 @@
   public:
     BlackfinTargetLowering(TargetMachine &TM);
     virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i16; }
-    virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
+    virtual EVT getSetCCResultType(EVT VT) const;
     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
     virtual void ReplaceNodeResults(SDNode *N,
                                     SmallVectorImpl<SDValue> &Results,

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -439,6 +439,7 @@
   setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
 
   setBooleanContents(ZeroOrNegativeOneBooleanContent);
+  setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); // FIXME: Is this correct?
 
   setStackPointerRegisterToSaveRestore(SPU::R1);
 
@@ -498,7 +499,7 @@
 // Return the Cell SPU's SETCC result type
 //===----------------------------------------------------------------------===//
 
-MVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const {
+EVT SPUTargetLowering::getSetCCResultType(EVT VT) const {
   // i8, i16 and i32 are valid SETCC result types
   MVT::SimpleValueType retval;
 

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Tue Sep  6 14:07:46 2011
@@ -107,7 +107,7 @@
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
     /// getSetCCResultType - Return the ValueType for ISD::SETCC
-    virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
+    virtual EVT getSetCCResultType(EVT VT) const;
 
     virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
 

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -59,6 +59,7 @@
   // MBlaze does not have i1 type, so use i32 for
   // setcc operations results (slt, sgt, ...).
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
 
   // Set up the register classes
   addRegisterClass(MVT::i32, MBlaze::GPRRegisterClass);
@@ -187,7 +188,7 @@
   computeRegisterProperties();
 }
 
-MVT::SimpleValueType MBlazeTargetLowering::getSetCCResultType(EVT VT) const {
+EVT MBlazeTargetLowering::getSetCCResultType(EVT VT) const {
   return MVT::i32;
 }
 

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h Tue Sep  6 14:07:46 2011
@@ -102,7 +102,7 @@
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
     /// getSetCCResultType - get the ISD::SETCC result ValueType
-    MVT::SimpleValueType getSetCCResultType(EVT VT) const;
+    EVT getSetCCResultType(EVT VT) const;
 
   private:
     // Subtarget Info

Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -79,6 +79,7 @@
 
   setStackPointerRegisterToSaveRestore(MSP430::SPW);
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
   setSchedulingPreference(Sched::Latency);
 
   // We have post-incremented loads / stores.

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -88,6 +88,7 @@
   // Mips does not have i1 type, so use i32 for
   // setcc operations results (slt, sgt, ...).
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
 
   // Set up the register classes
   addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
@@ -219,7 +220,7 @@
   return SVT == MVT::i32 || SVT == MVT::i16; 
 }
 
-MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
+EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
   return MVT::i32;
 }
 

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Tue Sep  6 14:07:46 2011
@@ -108,7 +108,7 @@
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
     /// getSetCCResultType - get the ISD::SETCC result ValueType
-    MVT::SimpleValueType getSetCCResultType(EVT VT) const;
+    EVT getSetCCResultType(EVT VT) const;
 
     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
   private:

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -48,6 +48,7 @@
   addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
 
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
   setMinFunctionAlignment(2);
   
   ////////////////////////////////////
@@ -106,7 +107,7 @@
   computeRegisterProperties();
 }
 
-MVT::SimpleValueType PTXTargetLowering::getSetCCResultType(EVT VT) const {
+EVT PTXTargetLowering::getSetCCResultType(EVT VT) const {
   return MVT::i1;
 }
 

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.h Tue Sep  6 14:07:46 2011
@@ -71,7 +71,7 @@
                 DebugLoc dl, SelectionDAG &DAG,
                 SmallVectorImpl<SDValue> &InVals) const;
 
-    virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
+    virtual EVT getSetCCResultType(EVT VT) const;
 
   private:
     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -370,6 +370,7 @@
   setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
 
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
 
   if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
     setStackPointerRegisterToSaveRestore(PPC::X1);
@@ -469,7 +470,7 @@
   }
 }
 
-MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
+EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
   return MVT::i32;
 }
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Tue Sep  6 14:07:46 2011
@@ -246,7 +246,7 @@
     virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
 
     /// getSetCCResultType - Return the ISD::SETCC ValueType
-    virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
+    virtual EVT getSetCCResultType(EVT VT) const;
 
     /// getPreIndexedAddressParts - returns true by value, base pointer and
     /// offset pointer and addressing mode by reference if the node's address

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -81,6 +81,7 @@
   setSchedulingPreference(Sched::RegPressure);
 
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
 
   setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
   setOperationAction(ISD::BRCOND,           MVT::Other, Expand);

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -181,6 +181,8 @@
 
   // X86 is weird, it always uses i8 for shift amounts and setcc results.
   setBooleanContents(ZeroOrOneBooleanContent);
+  // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
+  setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
 
   // For 64-bit since we have so many registers use the ILP scheduler, for
   // 32-bit code use the register pressure specific scheduling.
@@ -710,7 +712,7 @@
     setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
     setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
     setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
-    setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
+    setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
     setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
     setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
     setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
@@ -787,7 +789,7 @@
     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v4f32, Custom);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
     setOperationAction(ISD::SELECT,             MVT::v4f32, Custom);
-    setOperationAction(ISD::VSETCC,             MVT::v4f32, Custom);
+    setOperationAction(ISD::SETCC,              MVT::v4f32, Custom);
   }
 
   if (!UseSoftFloat && Subtarget->hasXMMInt()) {
@@ -817,10 +819,10 @@
     setOperationAction(ISD::FSQRT,              MVT::v2f64, Legal);
     setOperationAction(ISD::FNEG,               MVT::v2f64, Custom);
 
-    setOperationAction(ISD::VSETCC,             MVT::v2f64, Custom);
-    setOperationAction(ISD::VSETCC,             MVT::v16i8, Custom);
-    setOperationAction(ISD::VSETCC,             MVT::v8i16, Custom);
-    setOperationAction(ISD::VSETCC,             MVT::v4i32, Custom);
+    setOperationAction(ISD::SETCC,              MVT::v2f64, Custom);
+    setOperationAction(ISD::SETCC,              MVT::v16i8, Custom);
+    setOperationAction(ISD::SETCC,              MVT::v8i16, Custom);
+    setOperationAction(ISD::SETCC,              MVT::v4i32, Custom);
 
     setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v16i8, Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v8i16, Custom);
@@ -950,7 +952,7 @@
   }
 
   if (Subtarget->hasSSE42() || Subtarget->hasAVX())
-    setOperationAction(ISD::VSETCC,             MVT::v2i64, Custom);
+    setOperationAction(ISD::SETCC,             MVT::v2i64, Custom);
 
   if (!UseSoftFloat && Subtarget->hasAVX()) {
     addRegisterClass(MVT::v32i8,  X86::VR256RegisterClass);
@@ -1002,10 +1004,10 @@
     setOperationAction(ISD::SRA,               MVT::v8i32, Custom);
     setOperationAction(ISD::SRA,               MVT::v16i16, Custom);
 
-    setOperationAction(ISD::VSETCC,            MVT::v32i8, Custom);
-    setOperationAction(ISD::VSETCC,            MVT::v16i16, Custom);
-    setOperationAction(ISD::VSETCC,            MVT::v8i32, Custom);
-    setOperationAction(ISD::VSETCC,            MVT::v4i64, Custom);
+    setOperationAction(ISD::SETCC,             MVT::v32i8, Custom);
+    setOperationAction(ISD::SETCC,             MVT::v16i16, Custom);
+    setOperationAction(ISD::SETCC,             MVT::v8i32, Custom);
+    setOperationAction(ISD::SETCC,             MVT::v4i64, Custom);
 
     setOperationAction(ISD::SELECT,            MVT::v4f64, Custom);
     setOperationAction(ISD::SELECT,            MVT::v4i64, Custom);
@@ -1145,8 +1147,9 @@
 }
 
 
-MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
-  return MVT::i8;
+EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
+  if (!VT.isVector()) return MVT::i8;
+  return VT.changeVectorElementTypeToInteger();
 }
 
 
@@ -8319,6 +8322,9 @@
 }
 
 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
+
+  if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
+
   assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
   SDValue Op0 = Op.getOperand(0);
   SDValue Op1 = Op.getOperand(1);
@@ -8374,7 +8380,7 @@
 static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) {
   EVT VT = Op.getValueType();
 
-  assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::VSETCC &&
+  assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
          "Unsupported value type for operation");
 
   int NumElems = VT.getVectorNumElements();
@@ -10038,7 +10044,6 @@
   SDNode* Node = Op.getNode();
   EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
   EVT VT = Node->getValueType(0);
-
   if (Subtarget->hasSSE2() && VT.isVector()) {
     unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
                         ExtraVT.getScalarType().getSizeInBits();
@@ -10344,7 +10349,6 @@
   case ISD::FCOPYSIGN:          return LowerFCOPYSIGN(Op, DAG);
   case ISD::FGETSIGN:           return LowerFGETSIGN(Op, DAG);
   case ISD::SETCC:              return LowerSETCC(Op, DAG);
-  case ISD::VSETCC:             return LowerVSETCC(Op, DAG);
   case ISD::SELECT:             return LowerSELECT(Op, DAG);
   case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Sep  6 14:07:46 2011
@@ -572,8 +572,8 @@
     /// DAG node.
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
-    /// getSetCCResultType - Return the ISD::SETCC ValueType
-    virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
+    /// getSetCCResultType - Return the value type to use for ISD::SETCC.
+    virtual EVT getSetCCResultType(EVT VT) const;
 
     /// computeMaskedBitsForTargetNode - Determine which of the bits specified
     /// in Mask are known to be either zero or one and return them in the

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Sep  6 14:07:46 2011
@@ -81,6 +81,7 @@
 
   // Use i32 for setcc operations results (slt, sgt, ...).
   setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
 
   // XCore does not have the NodeTypes below.
   setOperationAction(ISD::BR_CC,     MVT::Other, Expand);

Modified: llvm/trunk/lib/VMCore/ValueTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ValueTypes.cpp?rev=139159&r1=139158&r2=139159&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ValueTypes.cpp (original)
+++ llvm/trunk/lib/VMCore/ValueTypes.cpp Tue Sep  6 14:07:46 2011
@@ -19,6 +19,12 @@
 #include "llvm/Support/ErrorHandling.h"
 using namespace llvm;
 
+EVT EVT::changeExtendedVectorElementTypeToInteger() const {
+  LLVMContext &Context = LLVMTy->getContext();
+  EVT IntTy = getIntegerVT(Context, getVectorElementType().getSizeInBits());
+  return getVectorVT(Context, IntTy, getVectorNumElements());
+}
+
 EVT EVT::getExtendedIntegerVT(LLVMContext &Context, unsigned BitWidth) {
   EVT VT;
   VT.LLVMTy = IntegerType::get(Context, BitWidth);



From rafael.espindola at gmail.com  Tue Sep  6 14:29:31 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 06 Sep 2011 19:29:31 -0000
Subject: [llvm-commits] [llvm] r139161 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.h
Message-ID: <20110906192932.027162A6C12C@llvm.org>

Author: rafael
Date: Tue Sep  6 14:29:31 2011
New Revision: 139161

URL: http://llvm.org/viewvc/llvm-project?rev=139161&view=rev
Log:
Fix comment. Noticed by Duncan.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.h

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=139161&r1=139160&r2=139161&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Sep  6 14:29:31 2011
@@ -288,7 +288,7 @@
 
       // SEG_ALLOCA - For allocating variable amounts of stack space when using
       // segmented stacks. Check if the current stacklet has enough space, and
-      // defects to heap allocation if not.
+      // falls back to heap allocation if not.
       SEG_ALLOCA,
 
       // Memory barrier



From James.Molloy at arm.com  Tue Sep  6 15:05:19 2011
From: James.Molloy at arm.com (James Molloy)
Date: Tue, 6 Sep 2011 21:05:19 +0100
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and
	resolve	(safe) ambiguous instruction encodings
In-Reply-To: <718C7FA3-810A-486A-80BD-F3476C59DBFF@me.com>
References: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>,
	<718C7FA3-810A-486A-80BD-F3476C59DBFF@me.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA473757133DF@GEORGE.Emea.Arm.com>

Hi Owen,

Alas, my selective-target-syndrome strikes again :(  (fixed up ARM, X86 and MBlaze; forgot about the rest of the MC targets)

I'll obviously get that fixed and resent in the morning.

Cheers,

James
________________________________________
From: Owen Anderson [resistor at me.com]
Sent: 06 September 2011 19:43
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve      (safe) ambiguous instruction encodings

James,

Patch 0 seems to be missing some necessary changes to non-ARM targets to make LLVM build with it applied.  I see a lot of errors of the form:

MipsMCTargetDesc.cpp:109:41: error: cannot initialize a parameter of type 'Target::MCInstPrinterCtorTy' (aka 'llvm::MCInstPrinter *(*)(const llvm::Target
      &, unsigned int, const llvm::MCAsmInfo &, const llvm::MCSubtargetInfo &)') with an lvalue of type 'llvm::MCInstPrinter *(const llvm::Target &,
      unsigned int, const llvm::MCAsmInfo &)'
                                        createMipsMCInstPrinter);
                                        ^~~~~~~~~~~~~~~~~~~~~~~

--Owen

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:

> Hi,
>
> The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M series
> not allowing the correct mask names.
>
> The patch becomes difficult because:
>  * There is no way to determine in the InstPrinter any subtarget specific
> features (such as "operating on an m-class core?").
>  * There is currently no subtarget feature for "M-class core?"; the nearest is
> IsThumb2 && !HasARM.
>  * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
> a way that makes them deterministically separable. This causes non-conflicting
> ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
> both code paths are emitted but only one will ever be hit.
>
> The solution is:
>  * Add subtarget info to InstPrinter so it can determine what to do with the
> mask immediate.
>  * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
> IsARClass == !IsMClass. This feature only has semantic sense on v6+
> architectures.
>  * The conflicts occur because the FixedLenDecoderEmitter does not honour the
> Predicates field of instructions in the tablegen description. If the island
> checking also checked the AssemblerPredicates field (if defined), ambiguous
> instruction encodings that are disambiguated by predicates would (do) work fine.
>
> The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and MCDisassembler.
> They can use this (in patch #2) to determine what mask names to accept (primask?
> or cpsr_zxvf?)
>
> The second enhances FixedLenPredicateEncoder to emit predicate checks for
> instructions before it accepts an encoding - this allows ambiguous instructions
> to be disambiguated by the Predicates field in TableGen. This required changing
> llvm-mc to accept -mattr, and tests to set the correct features they rely upon.
>
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
> is created.**
>
> The third patch adds a new predicate "IsMClass" along with its counterpart
> "IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
> Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
> encodings respectively. It also fixes mask printing for MRS/MSR in the
> ARMMCInstPrinter and ARMMCAsmParser.
>
> Testcases added with the final patch.
>
> Comments? Is it OK?
>
> Cheers,
>
> James
>
> [N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout myself
> after review]
> <patch0-add-sti-to-instprinter.patch><patch1-modify-fixedlendecoderemitter.patch><patch2-fix-msr-mrs.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




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From enderby at apple.com  Tue Sep  6 15:11:23 2011
From: enderby at apple.com (Kevin Enderby)
Date: Tue, 06 Sep 2011 13:11:23 -0700
Subject: [llvm-commits] [llvm] r139028 - in /llvm/trunk:
 lib/Target/X86/Disassembler/X86Disassembler.cpp
 lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
 test/MC/Disassembler/X86/simple-tests.txt
In-Reply-To: <C43A6901-80B0-4EA9-B0D4-4E196E7CA7E0@apple.com>
References: <20110902200123.B05252A6C12C@llvm.org>
	<CAJdarcH2oP9GTszS2QxWGTmw9D7v4Ze8wj8MRsHU3fyn6QBLwQ@mail.gmail.com>
	<C43A6901-80B0-4EA9-B0D4-4E196E7CA7E0@apple.com>
Message-ID: <ACADEEC8-024E-47F3-A933-CC18413B5F55@apple.com>

Hi Evan & Eli,

I'd be happy to back this out and change it to the much better way using a type to distinguish between extending and non-extending immediates. My fear is breaking a bunch of "bad assembly code" that might exist and assembles today but is technically wrong.

As Eli pointed out their are many other instructions that really use an non-extended immediate.  The problem is that bad assembly code like this:

	pcmpestri $0x181, %xmm2, %xmm1
	pcmpestri $-127, %xmm2, %xmm1

currently assembles in many cases.  As I found out when I spent a lot of time auditing ALL the x86 instructions with immediates and seeing what the Mac OS X gas(1) assembler and the llvm-mc assembler will accept.

For the two line example above llvm-mc will assembly both of these lines and gas(1) will give a hard error only on the first.  And there is also a class of instructions like in/out where the handling of this:

	out %al, $0x181

produces only a warning with gas(1) but assembles and assembles with no warning with llvm-mc.  Then you get to the class of instructions that are special cased in the patch like:

	blendps $0x81, %xmm2, %xmm1
	blendps $-127, %xmm2, %xmm1

Where gas will assemble both but llvm-mc will (I feel correctly) refuse to assemble the second.  So the patch is a bit if a tight rope act and a workaround trying to only change the disassembler to match what the llvm-mc assembler currently allows.

I would love to tighten up all this in llvm-mc but with all the technically wrong intel assembly code out there being accepted by various assemblers I choose to only change the disassembler to address the specific problem with the lack of sign extension in disassembly the bug rdar://8795217 was asking for.

I welcome any suggestions and guidance in this area,
Kev

On Sep 5, 2011, at 2:52 PM, Evan Cheng wrote:

> 
> 
> On Sep 4, 2011, at 1:09 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> 
>> On Fri, Sep 2, 2011 at 1:01 PM, Kevin Enderby <enderby at apple.com> wrote:
>>> Author: enderby
>>> Date: Fri Sep  2 15:01:23 2011
>>> New Revision: 139028
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=139028&view=rev
>>> Log:
>>> Change X86 disassembly to print immediates values as signed by default.  Special
>>> case those instructions that the immediate is not sign-extend.  radr://8795217
>>> 
>>> Modified:
>>>   llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
>>>   llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
>>>   llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
>>> 
>>> Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=139028&r1=139027&r2=139028&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
>>> +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Fri Sep  2 15:01:23 2011
>>> @@ -28,6 +28,8 @@
>>> 
>>> #define GET_REGINFO_ENUM
>>> #include "X86GenRegisterInfo.inc"
>>> +#define GET_INSTRINFO_ENUM
>>> +#include "X86GenInstrInfo.inc"
>>> #include "X86GenEDInfo.inc"
>>> 
>>> using namespace llvm;
>>> @@ -184,6 +186,38 @@
>>>      break;
>>>    }
>>>  }
>>> +  // By default sign-extend all X86 immediates based on their encoding.
>>> +  else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
>>> +           type == TYPE_IMM64) {
>>> +    uint32_t Opcode = mcInst.getOpcode();
>>> +    switch (operand.encoding) {
>>> +    default:
>>> +      break;
>>> +    case ENCODING_IB:
>>> +      // Special case those X86 instructions that use the imm8 as a set of
>>> +      // bits, bit count, etc. and are not sign-extend.
>>> +      if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
>>> +         Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
>>> +         Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
>>> +         Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
>>> +         Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
>>> +         Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
>>> +         Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
>>> +         Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
>>> +         Opcode != X86::VINSERTPSrr)
>> 
>> This can't possibly be the complete list of instructions with a
>> non-extended immediate.  PCMPESTRI and friends, SHUFPS and friends,
>> all shift instructions, and IN/OUT (plus possibly others I've missed)
>> all take an imm8 which is clearly not signed.
> 
> It's also the wrong way to fix the bug. Kevin, can you add a new type to distinguish between extending and non-extending immediates?
> 
> Evan
> 
>> 
>> -Eli
>> 
>>> +       type = TYPE_MOFFS8;
>>> +      break;
>>> +    case ENCODING_IW:
>>> +      type = TYPE_MOFFS16;
>>> +      break;
>>> +    case ENCODING_ID:
>>> +      type = TYPE_MOFFS32;
>>> +      break;
>>> +    case ENCODING_IO:
>>> +      type = TYPE_MOFFS64;
>>> +      break;
>>> +    }
>>> +  }
>>> 
>>>  switch (type) {
>>>  case TYPE_MOFFS8:
>>> 
>>> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=139028&r1=139027&r2=139028&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original)
>>> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Fri Sep  2 15:01:23 2011
>>> @@ -90,7 +90,8 @@
>>>  if (Op.isReg()) {
>>>    O << '%' << getRegisterName(Op.getReg());
>>>  } else if (Op.isImm()) {
>>> -    O << '$' << Op.getImm();
>>> +    // Print X86 immediates as signed values.
>>> +    O << '$' << (int64_t)Op.getImm();
>>> 
>>>    if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
>>>      *CommentStream << format("imm = 0x%llX\n", (long long)Op.getImm());
>>> 
>>> Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=139028&r1=139027&r2=139028&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
>>> +++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Fri Sep  2 15:01:23 2011
>>> @@ -102,3 +102,59 @@
>>> 
>>> # CHECK: vmovapd %xmm0, %xmm2
>>> 0xc5 0xf9 0x28 0xd0
>>> +
>>> +# Check X86 immediates print as signed values by default.  radr://8795217
>>> +# CHECK: andq $-16, %rsp
>>> +0x48 0x83 0xe4 0xf0
>>> +
>>> +# Check these special case instructions that the immediate is not sign-extend.
>>> +# CHECK: blendps $129, %xmm2, %xmm1
>>> +0x66 0x0f 0x3a 0x0c 0xca 0x81
>>> +
>>> +# CHECK: blendpd $129, %xmm2, %xmm1
>>> +0x66 0x0f 0x3a 0x0d 0xca 0x81
>>> +
>>> +# CHECK: pblendw $129, %xmm2, %xmm1
>>> +0x66 0x0f 0x3a 0x0e 0xca 0x81
>>> +
>>> +# CHECK: mpsadbw $129, %xmm2, %xmm1
>>> +0x66 0x0f 0x3a 0x42 0xca 0x81
>>> +
>>> +# CHECK: dpps $129, %xmm2, %xmm1
>>> +0x66 0x0f 0x3a 0x40 0xca 0x81
>>> +
>>> +# CHECK: dppd $129, %xmm2, %xmm1
>>> +0x66 0x0f 0x3a 0x41 0xca 0x81
>>> +
>>> +# CHECK: insertps $129, %xmm2, %xmm1
>>> +0x66 0x0f 0x3a 0x21 0xca 0x81
>>> +
>>> +# CHECK: vblendps $129, %ymm2, %ymm5, %ymm1
>>> +0xc4 0xe3 0x55 0x0c 0xca 0x81
>>> +
>>> +# CHECK: vblendps $129, (%rax), %ymm5, %ymm1
>>> +0xc4 0xe3 0x55 0x0c 0x08 0x81
>>> +
>>> +# CHECK: vblendpd $129, %ymm2, %ymm5, %ymm1
>>> +0xc4 0xe3 0x55 0x0d 0xca 0x81
>>> +
>>> +# CHECK: vblendpd $129, (%rax), %ymm5, %ymm1
>>> +0xc4 0xe3 0x55 0x0d 0x08 0x81
>>> +
>>> +# CHECK: vpblendw $129, %xmm2, %xmm5, %xmm1
>>> +0xc4 0xe3 0x51 0x0e 0xca 0x81
>>> +
>>> +# CHECK: vmpsadbw $129, %xmm2, %xmm5, %xmm1
>>> +0xc4 0xe3 0x51 0x42 0xca 0x81
>>> +
>>> +# CHECK: vdpps $129, %ymm2, %ymm5, %ymm1
>>> +0xc4 0xe3 0x55 0x40 0xca 0x81
>>> +
>>> +# CHECK: vdpps $129, (%rax), %ymm5, %ymm1
>>> +0xc4 0xe3 0x55 0x40 0x08 0x81
>>> +
>>> +# CHECK: vdppd $129, %xmm2, %xmm5, %xmm1
>>> +0xc4 0xe3 0x51 0x41 0xca 0x81
>>> +
>>> +# CHECK: vinsertps $129, %xmm3, %xmm2, %xmm1
>>> +0xc4 0xe3 0x69 0x21 0xcb 0x81
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From grosbach at apple.com  Tue Sep  6 15:12:23 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 20:12:23 -0000
Subject: [llvm-commits] [llvm] r139168 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110906201223.37AF62A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep  6 15:12:23 2011
New Revision: 139168

URL: http://llvm.org/viewvc/llvm-project?rev=139168&view=rev
Log:
Thumb2 parsing and encoding for CDP/CDP2.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139168&r1=139167&r2=139168&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep  6 15:12:23 2011
@@ -283,6 +283,16 @@
 
 
 @------------------------------------------------------------------------------
+@ CDP/CDP2
+ at ------------------------------------------------------------------------------
+  cdp  p7, #1, c1, c1, c1, #4
+  cdp2  p7, #1, c1, c1, c1, #4
+
+@ CHECK: cdp	p7, #1, c1, c1, c1, #4  @ encoding: [0x11,0xee,0x81,0x17]
+@ CHECK: cdp2	p7, #1, c1, c1, c1, #4  @ encoding: [0x11,0xfe,0x81,0x17]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From atrick at apple.com  Tue Sep  6 15:20:38 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 06 Sep 2011 20:20:38 -0000
Subject: [llvm-commits] [llvm] r139169 -
	/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
Message-ID: <20110906202039.014722A6C12C@llvm.org>

Author: atrick
Date: Tue Sep  6 15:20:38 2011
New Revision: 139169

URL: http://llvm.org/viewvc/llvm-project?rev=139169&view=rev
Log:
Add -verify-indvars for imperfect SCEV trip count verification after indvars.

Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=139169&r1=139168&r2=139169&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Sep  6 15:20:38 2011
@@ -76,6 +76,13 @@
   cl::opt<bool> DisableIVRewrite(
     "disable-iv-rewrite", cl::Hidden,
     cl::desc("Disable canonical induction variable rewriting"));
+
+  // Trip count verification can be enabled by default under NDEBUG if we
+  // implement a strong expression equivalence checker in SCEV. Until then, we
+  // use the verify-indvars flag, which may assert in some cases.
+  cl::opt<bool> VerifyIndvars(
+    "verify-indvars", cl::Hidden,
+    cl::desc("Verify the ScalarEvolution result after running indvars"));
 }
 
 // Temporary flag for use with -disable-iv-rewrite to force a canonical IV for
@@ -1968,7 +1975,8 @@
   // Verify that LFTR, and any other change have not interfered with SCEV's
   // ability to compute trip count.
 #ifndef NDEBUG
-  if (DisableIVRewrite && !isa<SCEVCouldNotCompute>(BackedgeTakenCount)) {
+  if (DisableIVRewrite && VerifyIndvars &&
+      !isa<SCEVCouldNotCompute>(BackedgeTakenCount)) {
     SE->forgetLoop(L);
     const SCEV *NewBECount = SE->getBackedgeTakenCount(L);
     if (SE->getTypeSizeInBits(BackedgeTakenCount->getType()) <



From grosbach at apple.com  Tue Sep  6 15:23:44 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 13:23:44 -0700
Subject: [llvm-commits] [llvm] r139157 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td
 lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/carry.ll
In-Reply-To: <20110906185221.2FCBE2A6C12C@llvm.org>
References: <20110906185221.2FCBE2A6C12C@llvm.org>
Message-ID: <FF1F6AE9-14EB-464F-BD2B-C719715395B5@apple.com>

Hi Evan,

In that case, can we get rid of the distinct ADDS definitions entirely and just use the ADD instructions w/ the cc_out operand set appropriately?

-Jim

On Sep 6, 2011, at 11:52 AM, Evan Cheng wrote:

> Author: evancheng
> Date: Tue Sep  6 13:52:20 2011
> New Revision: 139157
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=139157&view=rev
> Log:
> Fix fall outs from my recent change on how carry bit is modeled during isel.
> Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
> Also fix isel hook to correctly set the optional operand.
> rdar://10073745
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>    llvm/trunk/test/CodeGen/ARM/carry.ll
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=139157&r1=139156&r2=139157&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Sep  6 13:52:20 2011
> @@ -5708,7 +5708,7 @@
>   // the optional operand to CPSR. Otherwise, remove the CPSR implicit def.
>   const MCInstrDesc &MCID = MI->getDesc();
>   if (Node->hasAnyUseOfValue(1)) {
> -    MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 2);
> +    MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 1);
>     MO.setReg(ARM::CPSR);
>     MO.setIsDef(true);
>   } else {
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139157&r1=139156&r2=139157&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Sep  6 13:52:20 2011
> @@ -1037,8 +1037,8 @@
> 
> }
> 
> -/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except sets 's' bit.
> -let isCodeGenOnly = 1, Defs = [CPSR] in {
> +/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except it sets 's' bit by default.
> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
> multiclass AsI1_rbin_s_is<bits<4> opcod, string opc,
>                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
>                         PatFrag opnode, bit Commutable = 0> {
> @@ -1101,25 +1101,25 @@
> }
> }
> 
> -/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
> -/// instruction modifies the CPSR register.
> -let isCodeGenOnly = 1, Defs = [CPSR] in {
> -multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
> +/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
> +multiclass AsI1_bin_s_irs<bits<4> opcod, string opc,
>                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
>                          PatFrag opnode, bit Commutable = 0> {
> -  def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
> +  let isReMaterializable = 1 in {
> +  def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
>                iii, opc, "\t$Rd, $Rn, $imm",
>                [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]> {
>     bits<4> Rd;
>     bits<4> Rn;
>     bits<12> imm;
>     let Inst{25} = 1;
> -    let Inst{20} = 1;
>     let Inst{19-16} = Rn;
>     let Inst{15-12} = Rd;
>     let Inst{11-0} = imm;
>   }
> -  def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
> +  }
> +  def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
>                iir, opc, "\t$Rd, $Rn, $Rm",
>                [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
>     bits<4> Rd;
> @@ -1127,13 +1127,12 @@
>     bits<4> Rm;
>     let isCommutable = Commutable;
>     let Inst{25} = 0;
> -    let Inst{20} = 1;
>     let Inst{19-16} = Rn;
>     let Inst{15-12} = Rd;
>     let Inst{11-4} = 0b00000000;
>     let Inst{3-0} = Rm;
>   }
> -  def rsi : AI1<opcod, (outs GPR:$Rd),
> +  def rsi : AsI1<opcod, (outs GPR:$Rd),
>                (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
>                iis, opc, "\t$Rd, $Rn, $shift",
>                [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
> @@ -1141,7 +1140,6 @@
>     bits<4> Rn;
>     bits<12> shift;
>     let Inst{25} = 0;
> -    let Inst{20} = 1;
>     let Inst{19-16} = Rn;
>     let Inst{15-12} = Rd;
>     let Inst{11-5} = shift{11-5};
> @@ -1149,7 +1147,7 @@
>     let Inst{3-0} = shift{3-0};
>   }
> 
> -  def rsr : AI1<opcod, (outs GPR:$Rd),
> +  def rsr : AsI1<opcod, (outs GPR:$Rd),
>                (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
>                iis, opc, "\t$Rd, $Rn, $shift",
>                [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
> @@ -3136,10 +3134,12 @@
>                          BinOpFrag<(sub  node:$LHS, node:$RHS)>, "SUB">;
> 
> // ADD and SUB with 's' bit set.
> -defm ADDS : AI1_bin_s_irs<0b0100, "adds",
> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
> +// CPSR and the implicit def of CPSR is not needed.
> +defm ADDS : AsI1_bin_s_irs<0b0100, "add",
>                           IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>                           BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
> -defm SUBS : AI1_bin_s_irs<0b0010, "subs",
> +defm SUBS : AsI1_bin_s_irs<0b0010, "sub",
>                           IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>                           BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
> 
> @@ -3153,6 +3153,9 @@
> defm RSB  : AsI1_rbin_irs <0b0011, "rsb",
>                          IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>                          BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
> +
> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
> +// CPSR and the implicit def of CPSR is not needed.
> defm RSBS : AsI1_rbin_s_is<0b0011, "rsb",
>                          IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>                          BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139157&r1=139156&r2=139157&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep  6 13:52:20 2011
> @@ -588,44 +588,41 @@
> 
> /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
> /// instruction modifies the CPSR register.
> -let isCodeGenOnly = 1, Defs = [CPSR] in {
> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
> multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
>                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
>                          PatFrag opnode, bit Commutable = 0> {
>    // shifted imm
> -   def ri : T2TwoRegImm<
> +   def ri : T2sTwoRegImm<
>                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
> +                opc, ".w\t$Rd, $Rn, $imm",
>                 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
>      let Inst{31-27} = 0b11110;
>      let Inst{25} = 0;
>      let Inst{24-21} = opcod;
> -     let Inst{20} = 1; // The S bit.
>      let Inst{15} = 0;
>    }
>    // register
> -   def rr : T2ThreeReg<
> +   def rr : T2sThreeReg<
>                 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
> +                opc, ".w\t$Rd, $Rn, $Rm",
>                 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
>      let isCommutable = Commutable;
>      let Inst{31-27} = 0b11101;
>      let Inst{26-25} = 0b01;
>      let Inst{24-21} = opcod;
> -     let Inst{20} = 1; // The S bit.
>      let Inst{14-12} = 0b000; // imm3
>      let Inst{7-6} = 0b00; // imm2
>      let Inst{5-4} = 0b00; // type
>    }
>    // shifted register
> -   def rs : T2TwoRegShiftedReg<
> +   def rs : T2sTwoRegShiftedReg<
>                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
> +                opc, ".w\t$Rd, $Rn, $ShiftedRm",
>                [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
>      let Inst{31-27} = 0b11101;
>      let Inst{26-25} = 0b01;
>      let Inst{24-21} = opcod;
> -     let Inst{20} = 1; // The S bit.
>    }
> }
> }
> @@ -737,28 +734,26 @@
> 
> /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
> /// version is not needed since this is only for codegen.
> -let isCodeGenOnly = 1, Defs = [CPSR] in {
> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
> multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
>    // shifted imm
> -   def ri : T2TwoRegImm<
> +   def ri : T2sTwoRegImm<
>                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
> +                opc, ".w\t$Rd, $Rn, $imm",
>                 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
>      let Inst{31-27} = 0b11110;
>      let Inst{25} = 0;
>      let Inst{24-21} = opcod;
> -     let Inst{20} = 1; // The S bit.
>      let Inst{15} = 0;
>    }
>    // shifted register
> -   def rs : T2TwoRegShiftedReg<
> +   def rs : T2sTwoRegShiftedReg<
>                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
> -                IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
> +                IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
>               [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
>      let Inst{31-27} = 0b11101;
>      let Inst{26-25} = 0b01;
>      let Inst{24-21} = opcod;
> -     let Inst{20} = 1; // The S bit.
>    }
> }
> }
> @@ -1699,6 +1694,8 @@
>                              BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
> 
> // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
> +// CPSR and the implicit def of CPSR is not needed.
> defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
>                              IIC_iALUi, IIC_iALUr, IIC_iALUsi,
>                              BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
> @@ -1716,6 +1713,9 @@
> // RSB
> defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb",
>                              BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
> +
> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
> +// CPSR and the implicit def of CPSR is not needed.
> defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
>                              BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
> 
> 
> Modified: llvm/trunk/test/CodeGen/ARM/carry.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/carry.ll?rev=139157&r1=139156&r2=139157&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/carry.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/carry.ll Tue Sep  6 13:52:20 2011
> @@ -35,3 +35,13 @@
> 	%dw = add i64 %ch, %bw
> 	ret i64 %dw
> }
> +
> +; rdar://10073745
> +define i64 @f4(i64 %x) nounwind readnone {
> +entry:
> +; CHECK: f4:
> +; CHECK: rsbs r
> +; CHECK: rsc r
> +  %0 = sub nsw i64 0, %x
> +  ret i64 %0
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From resistor at mac.com  Tue Sep  6 15:26:34 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 06 Sep 2011 20:26:34 -0000
Subject: [llvm-commits] [llvm] r139171 -
	/llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt
Message-ID: <20110906202634.EBA642A6C12C@llvm.org>

Author: resistor
Date: Tue Sep  6 15:26:34 2011
New Revision: 139171

URL: http://llvm.org/viewvc/llvm-project?rev=139171&view=rev
Log:
Port more encoding tests over to Thumb2 decoding tests.

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt?rev=139171&r1=139170&r2=139171&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt Tue Sep  6 15:26:34 2011
@@ -24,6 +24,228 @@
 0x42 0xf5 0xd0 0x64
 
 #------------------------------------------------------------------------------
+# ADC (register)
+#------------------------------------------------------------------------------
+# CHECK: adc.w r4, r5, r6
+# CHECK: adcs.w r4, r5, r6
+# CHECK: adc.w r9, r1, r3
+# CHECK: adcs.w r9, r1, r3
+# CHECK: adc.w r0, r1, r3, ror #4
+# CHECK: adcs.w  r0, r1, r3, lsl #7
+# CHECK: adc.w r0, r1, r3, lsr #31
+# CHECK: adcs.w  r0, r1, r3, asr #32
+
+0x45 0xeb 0x06 0x04
+0x55 0xeb 0x06 0x04
+0x41 0xeb 0x03 0x09
+0x51 0xeb 0x03 0x09
+0x41 0xeb 0x33 0x10
+0x51 0xeb 0xc3 0x10
+0x41 0xeb 0xd3 0x70
+0x51 0xeb 0x23 0x00
+
+
+#------------------------------------------------------------------------------
+# ADD (immediate)
+#------------------------------------------------------------------------------
+# CHECK: itet eq
+# CHECK: addeq r1, r2, #4
+# CHECK: addwne r5, r3, #1023
+# CHECK: addweq r4, r5, #293
+# CHECK: add.w r2, sp, #1024
+# CHECK: add.w r2, r8, #65280
+# CHECK: addw r2, r3, #257
+# CHECK: add.w r12, r6, #256
+# CHECK: addw r12, r6, #256
+# CHECK: adds.w r1, r2, #496
+
+0x0a 0xbf
+0x11 0x1d
+0x03 0xf2 0xff 0x35
+0x05 0xf2 0x25 0x14
+0x0d 0xf5 0x80 0x62
+0x08 0xf5 0x7f 0x42
+0x03 0xf2 0x01 0x12
+0x06 0xf5 0x80 0x7c
+0x06 0xf2 0x00 0x1c
+0x12 0xf5 0xf8 0x71
+
+
+#------------------------------------------------------------------------------
+# ADD (register)
+#------------------------------------------------------------------------------
+# CHECK: add.w r1, r2, r8
+# CHECK: add.w r5, r9, r2, asr #32
+# CHECK: adds.w r7, r3, r1, lsl #31
+# CHECK: adds.w r0, r3, r6, lsr #25
+# CHECK: add.w r4, r8, r1, ror #12
+
+0x02 0xeb 0x08 0x01
+0x09 0xeb 0x22 0x05
+0x13 0xeb 0xc1 0x77
+0x13 0xeb 0x56 0x60
+0x08 0xeb 0x31 0x34
+
+
+#------------------------------------------------------------------------------
+# FIXME: ADR
+#------------------------------------------------------------------------------
+
+#------------------------------------------------------------------------------
+# AND (immediate)
+#------------------------------------------------------------------------------
+# CHECK: and r2, r5, #1044480
+# CHECK: ands r3, r12, #15
+# CHECK: and r1, r1, #255
+
+0x05 0xf4 0x7f 0x22
+0x1c 0xf0 0x0f 0x03
+0x01 0xf0 0xff 0x01
+
+
+#------------------------------------------------------------------------------
+# AND (register)
+#------------------------------------------------------------------------------
+# CHECK: and.w r4, r9, r8
+# CHECK: and.w r1, r4, r8, asr #3
+# CHECK: ands.w r2, r1, r7, lsl #1
+# CHECK: ands.w r4, r5, r2, lsr #20
+# CHECK: and.w r9, r12, r1, ror #17
+
+0x09 0xea 0x08 0x04
+0x04 0xea 0xe8 0x01
+0x11 0xea 0x47 0x02
+0x15 0xea 0x12 0x54
+0x0c 0xea 0x71 0x49
+
+#------------------------------------------------------------------------------
+# ASR (immediate)
+#------------------------------------------------------------------------------
+# CHECK: asr.w r2, r3, #12
+# CHECK: asrs.w r8, r3, #32
+# CHECK: asrs.w r2, r3, #1
+# CHECK: asr.w r2, r3, #4
+# CHECK: asrs.w r2, r12, #15
+
+# CHECK: asr.w r3, r3, #19
+# CHECK: asrs.w r8, r8, #2
+# CHECK: asrs.w r7, r7, #5
+# CHECK: asr.w r12, r12, #21
+
+0x4f 0xea 0x23 0x32
+0x5f 0xea 0x23 0x08
+0x5f 0xea 0x63 0x02
+0x4f 0xea 0x23 0x12
+0x5f 0xea 0xec 0x32
+
+0x4f 0xea 0xe3 0x43
+0x5f 0xea 0xa8 0x08
+0x5f 0xea 0x67 0x17
+0x4f 0xea 0x6c 0x5c
+
+
+#------------------------------------------------------------------------------
+# ASR (register)
+#------------------------------------------------------------------------------
+# CHECK: asr.w r3, r4, r2
+# CHECK: asr.w r1, r1, r2
+# CHECK: asrs.w r3, r4, r8
+
+0x44 0xfa 0x02 0xf3
+0x41 0xfa 0x02 0xf1
+0x54 0xfa 0x08 0xf3
+
+#------------------------------------------------------------------------------
+# B
+#------------------------------------------------------------------------------
+# CHECK: bmi.w   #-183396
+
+0x13 0xf5 0xce 0xa9
+
+
+#------------------------------------------------------------------------------
+# BFC
+#------------------------------------------------------------------------------
+# CHECK: bfc r5, #3, #17
+# CHECK: it lo
+# CHECK: bfclo r5, #3, #17
+
+0x6f 0xf3 0xd3 0x05
+0x38 0xbf
+0x6f 0xf3 0xd3 0x05
+
+
+#------------------------------------------------------------------------------
+# BFI
+#------------------------------------------------------------------------------
+# CHECK: bfi r5, r2, #3, #17
+# CHECK: it ne
+# CHECK: bfine r5, r2, #3, #17
+
+0x62 0xf3 0xd3 0x05
+0x18 0xbf
+0x62 0xf3 0xd3 0x05
+
+
+#------------------------------------------------------------------------------
+# BIC
+#------------------------------------------------------------------------------
+# CHECK: bic r10, r1, #15
+# CHECK: bic.w r12, r3, r6
+# CHECK: bic.w r11, r2, r6, lsl #12
+# CHECK: bic.w r8, r4, r1, lsr #11
+# CHECK: bic.w r7, r5, r7, lsr #15
+# CHECK: bic.w r6, r7, r9, asr #32
+# CHECK: bic.w r5, r6, r8, ror #1
+
+# CHECK: bic r1, r1, #15
+# CHECK: bic.w r1, r1, r1
+# CHECK: bic.w r4, r4, r2, lsl #31
+# CHECK: bic.w r6, r6, r3, lsr #12
+# CHECK: bic.w r7, r7, r4, lsr #7
+# CHECK: bic.w r8, r8, r5, asr #15
+# CHECK: bic.w r12, r12, r6, ror #29
+
+0x21 0xf0 0x0f 0x0a
+0x23 0xea 0x06 0x0c
+0x22 0xea 0x06 0x3b
+0x24 0xea 0xd1 0x28
+0x25 0xea 0xd7 0x37
+0x27 0xea 0x29 0x06
+0x26 0xea 0x78 0x05
+
+0x21 0xf0 0x0f 0x01
+0x21 0xea 0x01 0x01
+0x24 0xea 0xc2 0x74
+0x26 0xea 0x13 0x36
+0x27 0xea 0xd4 0x17
+0x28 0xea 0xe5 0x38
+0x2c 0xea 0x76 0x7c
+
+
+#------------------------------------------------------------------------------
+# BXJ
+#------------------------------------------------------------------------------
+# CHECK: bxj r5
+# CHECK: it ne
+# CHECK: bxjne r7
+
+0xc5 0xf3 0x00 0x8f
+0x18 0xbf
+0xc7 0xf3 0x00 0x8f
+
+
+#------------------------------------------------------------------------------
+# CBZ/CBNZ
+#------------------------------------------------------------------------------
+# CHECK: cbnz    r7, #6
+# CHECK: cbnz    r7, #12
+
+0x1f 0xb9
+0x37 0xb9
+
+
+#------------------------------------------------------------------------------
 # IT
 #------------------------------------------------------------------------------
 # Test encodings of a few full IT blocks, not just the IT instruction



From grosbach at apple.com  Tue Sep  6 15:27:04 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 20:27:04 -0000
Subject: [llvm-commits] [llvm] r139172 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110906202704.6BB902A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep  6 15:27:04 2011
New Revision: 139172

URL: http://llvm.org/viewvc/llvm-project?rev=139172&view=rev
Log:
Thumb2 parsing and encoding for CLREX.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139172&r1=139171&r2=139172&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep  6 15:27:04 2011
@@ -2897,9 +2897,7 @@
   let Inst{11-8} = Rt2;
 }
 
-// Clear-Exclusive is for disassembly only.
-def t2CLREX : T2XI<(outs), (ins), NoItinerary, "clrex",
-                   [/* For disassembly only; pattern left blank */]>,
+def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
             Requires<[IsThumb2, HasV7]>  {
   let Inst{31-16} = 0xf3bf;
   let Inst{15-14} = 0b10;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139172&r1=139171&r2=139172&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Sep  6 15:27:04 2011
@@ -3022,8 +3022,8 @@
       Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
       Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
       Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
-      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
-      Mnemonic == "setend" ||
+      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
+      (Mnemonic == "clrex" && !isThumb()) ||
       (Mnemonic == "nop" && isThumbOne()) ||
       ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
        !isThumb()) ||

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139172&r1=139171&r2=139172&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep  6 15:27:04 2011
@@ -293,6 +293,18 @@
 
 
 @------------------------------------------------------------------------------
+@ CLREX
+ at ------------------------------------------------------------------------------
+        clrex
+        it ne
+        clrexne
+
+@ CHECK: clrex                           @ encoding: [0xbf,0xf3,0x2f,0x8f]
+@ CHECK: it	ne                       @ encoding: [0x18,0xbf]
+@ CHECK: clrexne                         @ encoding: [0xbf,0xf3,0x2f,0x8f]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From jasonwkim at google.com  Tue Sep  6 15:32:34 2011
From: jasonwkim at google.com (Jason Kim)
Date: Tue, 6 Sep 2011 13:32:34 -0700
Subject: [llvm-commits] [llvm] r139125 - in /llvm/trunk/lib/Target:
 ARM/ARM.td ARM/ARMInstrInfo.td ARM/ARMSubtarget.cpp ARM/ARMSubtarget.h
 ARM/MCTargetDesc/ARMMCTargetDesc.cpp X86/MCTargetDesc/X86MCTargetDesc.cpp
 X86/X86.td X86/X86InstrInfo.td X86/X86Subt
Message-ID: <CABR3mn7-dFnQW7g8-Oxd1U76kBeQQz2+uZJEhizb6nYnfVmUxA@mail.gmail.com>

Hi Jim!

On Tue, Sep 6, 2011 at 10:05 AM, Jim Grosbach <grosbach at apple.com> wrote:

> Hi Nick,
>
> I have a few concerns about this that hopefully won't be too hard to
> alleviate. On the more trite side, we generally try to keep the nomenclature
> descriptive of purpose rather than of use. This patch names the sub-target
> feature according to purpose (native client) and doesn't give any indication
> of what it actually does. Is this really a sub-target feature at all?
> Honestly, my general impression is that this is more accurately a target
> platform in the triple akin to Linux or Darwin. For example,
> thumbv7-unknown-nacl.


That is exactly right - Native Client mode acts like a new "ostype" - which
entails changes to the backends - Specifically, instruction sequences deemed
"unsafe" are either disallowed or is transformed into their safe
equivalents.


> Assuming so (and it looks like that is indeed how it's specified?), why
> isn't querying the triple directly a-la ARMSubtarget->isTargetDarwin(),
> sufficient?


In order to enable this for multiple OS's and architectures (linux AND
darwin, ARM AND x86) we need a switch to turn on NaCl mode as a feature
across the supported matrix.


> Lastly, speculating here as this patch doesn't go into these details, but
> be very careful with alignment

changes in code sections, as the ARM backend is very sensitive to small
> changes. Specifically, the constant island pass tracks instruction alignment
> and relative distances as exactly as it can, and will n!
>  eed to be taught how to deal with these changes.
>

Yep - we are in the middle of refactoring our local work in constant islands
for eventual upstreaming.

Hope this clarifies things!

-jason

>
> -Jim
>
> On Sep 5, 2011, at 2:51 PM, Nick Lewycky wrote:
>
> > Author: nicholas
> > Date: Mon Sep  5 16:51:43 2011
> > New Revision: 139125
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=139125&view=rev
> > Log:
> > Add a new MC bit for NaCl (Native Client) mode. NaCl requires that
> certain
> > instructions are more aligned than the CPU requires, and adds some
> additional
> > directives, to follow in future patches. Patch by David Meyer!
> >
> > Modified:
> >    llvm/trunk/lib/Target/ARM/ARM.td
> >    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> >    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> >    llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> >    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> >    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> >    llvm/trunk/lib/Target/X86/X86.td
> >    llvm/trunk/lib/Target/X86/X86InstrInfo.td
> >    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> >    llvm/trunk/lib/Target/X86/X86Subtarget.h
> >
> > Modified: llvm/trunk/lib/Target/ARM/ARM.td
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=139125&r1=139124&r2=139125&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/ARM.td (original)
> > +++ llvm/trunk/lib/Target/ARM/ARM.td Mon Sep  5 16:51:43 2011
> > @@ -23,6 +23,9 @@
> > def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
> >                                   "Thumb mode">;
> >
> > +def ModeNaCl   : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
> > +                                  "Native client mode">;
> > +
> >
> //===----------------------------------------------------------------------===//
> > // ARM Subtarget features.
> > //
> >
> > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep  5 16:51:43 2011
> > @@ -209,6 +209,8 @@
> >                                  AssemblerPredicate<"!ModeThumb">;
> > def IsDarwin         : Predicate<"Subtarget->isTargetDarwin()">;
> > def IsNotDarwin      : Predicate<"!Subtarget->isTargetDarwin()">;
> > +def IsNaCl           : Predicate<"Subtarget->isTargetNaCl()">,
> > +                                 AssemblerPredicate<"ModeNaCl">;
> >
> > // FIXME: Eventually this will be just "hasV6T2Ops".
> > def UseMovt          : Predicate<"Subtarget->useMovt()">;
> >
> > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
> > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Sep  5 16:51:43 2011
> > @@ -53,6 +53,7 @@
> >   , HasVMLxForwarding(false)
> >   , SlowFPBrcc(false)
> >   , InThumbMode(false)
> > +  , InNaClMode(false)
> >   , HasThumb2(false)
> >   , NoARM(false)
> >   , PostRAScheduler(false)
> >
> > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=139125&r1=139124&r2=139125&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
> > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Sep  5 16:51:43 2011
> > @@ -70,6 +70,9 @@
> >   /// InThumbMode - True if compiling for Thumb, false for ARM.
> >   bool InThumbMode;
> >
> > +  /// InNaClMode - True if targeting Native Client
> > +  bool InNaClMode;
> > +
> >   /// HasThumb2 - True if Thumb2 instructions are supported.
> >   bool HasThumb2;
> >
> > @@ -209,6 +212,9 @@
> >   const Triple &getTargetTriple() const { return TargetTriple; }
> >
> >   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
> > +  bool isTargetNaCl() const {
> > +    return TargetTriple.getOS() == Triple::NativeClient;
> > +  }
> >   bool isTargetELF() const { return !isTargetDarwin(); }
> >
> >   bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
> >
> > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
> > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Sep  5
> 16:51:43 2011
> > @@ -86,6 +86,14 @@
> >       ARMArchFeature += ",+thumb-mode";
> >   }
> >
> > +  Triple TheTriple(TT);
> > +  if (TheTriple.getOS() == Triple::NativeClient) {
> > +    if (ARMArchFeature.empty())
> > +      ARMArchFeature = "+nacl-mode";
> > +    else
> > +      ARMArchFeature += ",+nacl-mode";
> > +  }
> > +
> >   return ARMArchFeature;
> > }
> >
> >
> > Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
> > +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Sep  5
> 16:51:43 2011
> > @@ -40,9 +40,16 @@
> >
> > std::string X86_MC::ParseX86Triple(StringRef TT) {
> >   Triple TheTriple(TT);
> > +  std::string FS;
> >   if (TheTriple.getArch() == Triple::x86_64)
> > -    return "+64bit-mode";
> > -  return "-64bit-mode";
> > +    FS = "+64bit-mode";
> > +  else
> > +    FS = "-64bit-mode";
> > +  if (TheTriple.getOS() == Triple::NativeClient)
> > +    FS += ",+nacl-mode";
> > +  else
> > +    FS += ",-nacl-mode";
> > +  return FS;
> > }
> >
> > /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values
> in the
> >
> > Modified: llvm/trunk/lib/Target/X86/X86.td
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=139125&r1=139124&r2=139125&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86.td (original)
> > +++ llvm/trunk/lib/Target/X86/X86.td Mon Sep  5 16:51:43 2011
> > @@ -23,6 +23,9 @@
> > def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
> >                                   "64-bit mode (x86_64)">;
> >
> > +def ModeNaCl  : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
> > +                                 "Native Client mode">;
> > +
> >
> //===----------------------------------------------------------------------===//
> > // X86 Subtarget features.
> >
> //===----------------------------------------------------------------------===//
> >
> > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep  5 16:51:43 2011
> > @@ -482,6 +482,14 @@
> >                              AssemblerPredicate<"Mode64Bit">;
> > def IsWin64      : Predicate<"Subtarget->isTargetWin64()">;
> > def NotWin64     : Predicate<"!Subtarget->isTargetWin64()">;
> > +def IsNaCl       : Predicate<"Subtarget->isTargetNaCl()">,
> > +                             AssemblerPredicate<"ModeNaCl">;
> > +def IsNaCl32     : Predicate<"Subtarget->isTargetNaCl32()">,
> > +                             AssemblerPredicate<"ModeNaCl,!Mode64Bit">;
> > +def IsNaCl64     : Predicate<"Subtarget->isTargetNaCl64()">,
> > +                             AssemblerPredicate<"ModeNaCl,Mode64Bit">;
> > +def NotNaCl      : Predicate<"!Subtarget->isTargetNaCl()">,
> > +                             AssemblerPredicate<"!ModeNaCl">;
> > def SmallCode    : Predicate<"TM.getCodeModel() == CodeModel::Small">;
> > def KernelCode   : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
> > def FarData      : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
> >
> > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
> > +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Sep  5 16:51:43 2011
> > @@ -260,7 +260,8 @@
> >   // FIXME: this is a known good value for Yonah. How about others?
> >   , MaxInlineSizeThreshold(128)
> >   , TargetTriple(TT)
> > -  , In64BitMode(is64Bit) {
> > +  , In64BitMode(is64Bit)
> > +  , InNaClMode(false) {
> >   // Determine default and user specified characteristics
> >   if (!FS.empty() || !CPU.empty()) {
> >     std::string CPUName = CPU;
> > @@ -306,6 +307,11 @@
> >   if (In64BitMode)
> >     ToggleFeature(X86::Mode64Bit);
> >
> > +  if (isTargetNaCl()) {
> > +    InNaClMode = true;
> > +    ToggleFeature(X86::ModeNaCl);
> > +  }
> > +
> >   if (HasAVX)
> >     X86SSELevel = NoMMXSSE;
> >
> >
> > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=139125&r1=139124&r2=139125&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
> > +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Sep  5 16:51:43 2011
> > @@ -119,6 +119,9 @@
> >   /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
> >   bool In64BitMode;
> >
> > +  /// InNaClMode - True if compiling for Native Client target.
> > +  bool InNaClMode;
> > +
> > public:
> >
> >   /// This constructor initializes the data members to match that
> > @@ -190,6 +193,11 @@
> >     return !isTargetDarwin() && !isTargetWindows() && !isTargetCygMing();
> >   }
> >   bool isTargetLinux() const { return TargetTriple.getOS() ==
> Triple::Linux; }
> > +  bool isTargetNaCl() const {
> > +    return TargetTriple.getOS() == Triple::NativeClient;
> > +  }
> > +  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
> > +  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
> >
> >   bool isTargetWindows() const { return TargetTriple.getOS() ==
> Triple::Win32; }
> >   bool isTargetMingw() const { return TargetTriple.getOS() ==
> Triple::MinGW32; }
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From grosbach at apple.com  Tue Sep  6 15:37:45 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 13:37:45 -0700
Subject: [llvm-commits] [llvm] r139125 - in /llvm/trunk/lib/Target:
 ARM/ARM.td ARM/ARMInstrInfo.td ARM/ARMSubtarget.cpp ARM/ARMSubtarget.h
 ARM/MCTargetDesc/ARMMCTargetDesc.cpp X86/MCTargetDesc/X86MCTargetDesc.cpp
 X86/X86.td X86/X86InstrInfo.td X86/X86Subt
In-Reply-To: <CABR3mn7-dFnQW7g8-Oxd1U76kBeQQz2+uZJEhizb6nYnfVmUxA@mail.gmail.com>
References: <CABR3mn7-dFnQW7g8-Oxd1U76kBeQQz2+uZJEhizb6nYnfVmUxA@mail.gmail.com>
Message-ID: <29E9E482-304C-4BBC-9C15-2B182432F263@apple.com>

Side note. Quotes don't seem to be nesting correctly. Don't know why.
On Sep 6, 2011, at 1:32 PM, Jason Kim wrote:

> Hi Jim!
> 
> On Tue, Sep 6, 2011 at 10:05 AM, Jim Grosbach <grosbach at apple.com> wrote:
> Hi Nick,
> 
> I have a few concerns about this that hopefully won't be too hard to alleviate. On the more trite side, we generally try to keep the nomenclature descriptive of purpose rather than of use. This patch names the sub-target feature according to purpose (native client) and doesn't give any indication of what it actually does. Is this really a sub-target feature at all? Honestly, my general impression is that this is more accurately a target platform in the triple akin to Linux or Darwin. For example, thumbv7-unknown-nacl.
> 
> That is exactly right - Native Client mode acts like a new "ostype" - which entails changes to the backends - Specifically, instruction sequences deemed "unsafe" are either disallowed or is transformed into their safe equivalents.  
>  
> Assuming so (and it looks like that is indeed how it's specified?), why isn't querying the triple directly a-la ARMSubtarget->isTargetDarwin(), sufficient?
> 
> In order to enable this for multiple OS's and architectures (linux AND darwin, ARM AND x86) we need a switch to turn on NaCl mode as a feature across the supported matrix.
>  

Why isn't the target triple sufficient in and of itself? If NaCl is the target OS in the triple, then it should be orthogonal to the actual host OS. That is, the code doesn't specify both Linux and NaCl; it's just NaCl as the target OS in the triple, right?

> Lastly, speculating here as this patch doesn't go into these details, but be very careful with alignment 
> changes in code sections, as the ARM backend is very sensitive to small changes. Specifically, the constant island pass tracks instruction alignment and relative distances as exactly as it can, and will n!
>  eed to be taught how to deal with these changes.
> 
> Yep - we are in the middle of refactoring our local work in constant islands for eventual upstreaming.
> 
> Hope this clarifies things!
> 
> -jason
> 
> -Jim
> 
> On Sep 5, 2011, at 2:51 PM, Nick Lewycky wrote:
> 
> > Author: nicholas
> > Date: Mon Sep  5 16:51:43 2011
> > New Revision: 139125
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=139125&view=rev
> > Log:
> > Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
> > instructions are more aligned than the CPU requires, and adds some additional
> > directives, to follow in future patches. Patch by David Meyer!
> >
> > Modified:
> >    llvm/trunk/lib/Target/ARM/ARM.td
> >    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> >    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> >    llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> >    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> >    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> >    llvm/trunk/lib/Target/X86/X86.td
> >    llvm/trunk/lib/Target/X86/X86InstrInfo.td
> >    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> >    llvm/trunk/lib/Target/X86/X86Subtarget.h
> >
> > Modified: llvm/trunk/lib/Target/ARM/ARM.td
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=139125&r1=139124&r2=139125&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/ARM.td (original)
> > +++ llvm/trunk/lib/Target/ARM/ARM.td Mon Sep  5 16:51:43 2011
> > @@ -23,6 +23,9 @@
> > def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
> >                                   "Thumb mode">;
> >
> > +def ModeNaCl   : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
> > +                                  "Native client mode">;
> > +
> > //===----------------------------------------------------------------------===//
> > // ARM Subtarget features.
> > //
> >
> > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep  5 16:51:43 2011
> > @@ -209,6 +209,8 @@
> >                                  AssemblerPredicate<"!ModeThumb">;
> > def IsDarwin         : Predicate<"Subtarget->isTargetDarwin()">;
> > def IsNotDarwin      : Predicate<"!Subtarget->isTargetDarwin()">;
> > +def IsNaCl           : Predicate<"Subtarget->isTargetNaCl()">,
> > +                                 AssemblerPredicate<"ModeNaCl">;
> >
> > // FIXME: Eventually this will be just "hasV6T2Ops".
> > def UseMovt          : Predicate<"Subtarget->useMovt()">;
> >
> > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
> > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Sep  5 16:51:43 2011
> > @@ -53,6 +53,7 @@
> >   , HasVMLxForwarding(false)
> >   , SlowFPBrcc(false)
> >   , InThumbMode(false)
> > +  , InNaClMode(false)
> >   , HasThumb2(false)
> >   , NoARM(false)
> >   , PostRAScheduler(false)
> >
> > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=139125&r1=139124&r2=139125&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
> > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Sep  5 16:51:43 2011
> > @@ -70,6 +70,9 @@
> >   /// InThumbMode - True if compiling for Thumb, false for ARM.
> >   bool InThumbMode;
> >
> > +  /// InNaClMode - True if targeting Native Client
> > +  bool InNaClMode;
> > +
> >   /// HasThumb2 - True if Thumb2 instructions are supported.
> >   bool HasThumb2;
> >
> > @@ -209,6 +212,9 @@
> >   const Triple &getTargetTriple() const { return TargetTriple; }
> >
> >   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
> > +  bool isTargetNaCl() const {
> > +    return TargetTriple.getOS() == Triple::NativeClient;
> > +  }
> >   bool isTargetELF() const { return !isTargetDarwin(); }
> >
> >   bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
> >
> > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
> > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Sep  5 16:51:43 2011
> > @@ -86,6 +86,14 @@
> >       ARMArchFeature += ",+thumb-mode";
> >   }
> >
> > +  Triple TheTriple(TT);
> > +  if (TheTriple.getOS() == Triple::NativeClient) {
> > +    if (ARMArchFeature.empty())
> > +      ARMArchFeature = "+nacl-mode";
> > +    else
> > +      ARMArchFeature += ",+nacl-mode";
> > +  }
> > +
> >   return ARMArchFeature;
> > }
> >
> >
> > Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
> > +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Sep  5 16:51:43 2011
> > @@ -40,9 +40,16 @@
> >
> > std::string X86_MC::ParseX86Triple(StringRef TT) {
> >   Triple TheTriple(TT);
> > +  std::string FS;
> >   if (TheTriple.getArch() == Triple::x86_64)
> > -    return "+64bit-mode";
> > -  return "-64bit-mode";
> > +    FS = "+64bit-mode";
> > +  else
> > +    FS = "-64bit-mode";
> > +  if (TheTriple.getOS() == Triple::NativeClient)
> > +    FS += ",+nacl-mode";
> > +  else
> > +    FS += ",-nacl-mode";
> > +  return FS;
> > }
> >
> > /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
> >
> > Modified: llvm/trunk/lib/Target/X86/X86.td
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=139125&r1=139124&r2=139125&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86.td (original)
> > +++ llvm/trunk/lib/Target/X86/X86.td Mon Sep  5 16:51:43 2011
> > @@ -23,6 +23,9 @@
> > def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
> >                                   "64-bit mode (x86_64)">;
> >
> > +def ModeNaCl  : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
> > +                                 "Native Client mode">;
> > +
> > //===----------------------------------------------------------------------===//
> > // X86 Subtarget features.
> > //===----------------------------------------------------------------------===//
> >
> > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep  5 16:51:43 2011
> > @@ -482,6 +482,14 @@
> >                              AssemblerPredicate<"Mode64Bit">;
> > def IsWin64      : Predicate<"Subtarget->isTargetWin64()">;
> > def NotWin64     : Predicate<"!Subtarget->isTargetWin64()">;
> > +def IsNaCl       : Predicate<"Subtarget->isTargetNaCl()">,
> > +                             AssemblerPredicate<"ModeNaCl">;
> > +def IsNaCl32     : Predicate<"Subtarget->isTargetNaCl32()">,
> > +                             AssemblerPredicate<"ModeNaCl,!Mode64Bit">;
> > +def IsNaCl64     : Predicate<"Subtarget->isTargetNaCl64()">,
> > +                             AssemblerPredicate<"ModeNaCl,Mode64Bit">;
> > +def NotNaCl      : Predicate<"!Subtarget->isTargetNaCl()">,
> > +                             AssemblerPredicate<"!ModeNaCl">;
> > def SmallCode    : Predicate<"TM.getCodeModel() == CodeModel::Small">;
> > def KernelCode   : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
> > def FarData      : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
> >
> > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
> > +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Sep  5 16:51:43 2011
> > @@ -260,7 +260,8 @@
> >   // FIXME: this is a known good value for Yonah. How about others?
> >   , MaxInlineSizeThreshold(128)
> >   , TargetTriple(TT)
> > -  , In64BitMode(is64Bit) {
> > +  , In64BitMode(is64Bit)
> > +  , InNaClMode(false) {
> >   // Determine default and user specified characteristics
> >   if (!FS.empty() || !CPU.empty()) {
> >     std::string CPUName = CPU;
> > @@ -306,6 +307,11 @@
> >   if (In64BitMode)
> >     ToggleFeature(X86::Mode64Bit);
> >
> > +  if (isTargetNaCl()) {
> > +    InNaClMode = true;
> > +    ToggleFeature(X86::ModeNaCl);
> > +  }
> > +
> >   if (HasAVX)
> >     X86SSELevel = NoMMXSSE;
> >
> >
> > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=139125&r1=139124&r2=139125&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
> > +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Sep  5 16:51:43 2011
> > @@ -119,6 +119,9 @@
> >   /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
> >   bool In64BitMode;
> >
> > +  /// InNaClMode - True if compiling for Native Client target.
> > +  bool InNaClMode;
> > +
> > public:
> >
> >   /// This constructor initializes the data members to match that
> > @@ -190,6 +193,11 @@
> >     return !isTargetDarwin() && !isTargetWindows() && !isTargetCygMing();
> >   }
> >   bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
> > +  bool isTargetNaCl() const {
> > +    return TargetTriple.getOS() == Triple::NativeClient;
> > +  }
> > +  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
> > +  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
> >
> >   bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
> >   bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 


From resistor at me.com  Tue Sep  6 15:44:36 2011
From: resistor at me.com (Owen Anderson)
Date: Tue, 06 Sep 2011 13:44:36 -0700
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and
	resolve	(safe) ambiguous instruction encodings
In-Reply-To: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>
References: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>
Message-ID: <C3CBC2F0-CA9B-4393-BB0D-EAD4AD60A0E0@me.com>

James,

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
> is created.**

What exactly is the issue with STC's?  My copy of the ISA reference shows the encoding being the same for ARM and Thumb2 modes, other than the lack of a predicate operand in Thumb2 mode.

--Owen

From grosbach at apple.com  Tue Sep  6 15:44:17 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 20:44:17 -0000
Subject: [llvm-commits] [llvm] r139177 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110906204417.7518F2A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep  6 15:44:17 2011
New Revision: 139177

URL: http://llvm.org/viewvc/llvm-project?rev=139177&view=rev
Log:
Thumb2 parsing and encoding for CLZ.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139177&r1=139176&r2=139177&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep  6 15:44:17 2011
@@ -305,6 +305,18 @@
 
 
 @------------------------------------------------------------------------------
+@ CLZ
+ at ------------------------------------------------------------------------------
+        clz r1, r2
+        it eq
+        clzeq r1, r2
+
+@ CHECK: clz	r1, r2                  @ encoding: [0xb2,0xfa,0x82,0xf1]
+@ CHECK: it	eq                      @ encoding: [0x08,0xbf]
+@ CHECK: clzeq	r1, r2                  @ encoding: [0xb2,0xfa,0x82,0xf1]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From jasonwkim at google.com  Tue Sep  6 15:50:51 2011
From: jasonwkim at google.com (Jason Kim)
Date: Tue, 6 Sep 2011 13:50:51 -0700
Subject: [llvm-commits] [llvm] r139125 - in /llvm/trunk/lib/Target:
 ARM/ARM.td ARM/ARMInstrInfo.td ARM/ARMSubtarget.cpp ARM/ARMSubtarget.h
 ARM/MCTargetDesc/ARMMCTargetDesc.cpp X86/MCTargetDesc/X86MCTargetDesc.cpp
 X86/X86.td X86/X86InstrInfo.td X86/X86Subt
In-Reply-To: <29E9E482-304C-4BBC-9C15-2B182432F263@apple.com>
References: <CABR3mn7-dFnQW7g8-Oxd1U76kBeQQz2+uZJEhizb6nYnfVmUxA@mail.gmail.com>
	<29E9E482-304C-4BBC-9C15-2B182432F263@apple.com>
Message-ID: <CABR3mn4+JeHYzw+0Q9n=YSWaH2ScxwbxpjtryD1FgCUW1N_j+g@mail.gmail.com>

On Tue, Sep 6, 2011 at 1:37 PM, Jim Grosbach <grosbach at apple.com> wrote:

> Side note. Quotes don't seem to be nesting correctly. Don't know why.
> On Sep 6, 2011, at 1:32 PM, Jason Kim wrote:
>
> > Hi Jim!
> >
> > On Tue, Sep 6, 2011 at 10:05 AM, Jim Grosbach <grosbach at apple.com>
> wrote:
> > Hi Nick,
> >
> > I have a few concerns about this that hopefully won't be too hard to
> alleviate. On the more trite side, we generally try to keep the nomenclature
> descriptive of purpose rather than of use. This patch names the sub-target
> feature according to purpose (native client) and doesn't give any indication
> of what it actually does. Is this really a sub-target feature at all?
> Honestly, my general impression is that this is more accurately a target
> platform in the triple akin to Linux or Darwin. For example,
> thumbv7-unknown-nacl.
> >
> > That is exactly right - Native Client mode acts like a new "ostype" -
> which entails changes to the backends - Specifically, instruction sequences
> deemed "unsafe" are either disallowed or is transformed into their safe
> equivalents.
> >
> > Assuming so (and it looks like that is indeed how it's specified?), why
> isn't querying the triple directly a-la ARMSubtarget->isTargetDarwin(),
> sufficient?
> >
> > In order to enable this for multiple OS's and architectures (linux AND
> darwin, ARM AND x86) we need a switch to turn on NaCl mode as a feature
> across the supported matrix.
> >
>
> Why isn't the target triple sufficient in and of itself? If NaCl is the
> target OS in the triple, then it should be orthogonal to the actual host OS.
> That is, the code doesn't specify both Linux and NaCl; it's just NaCl as the
> target OS in the triple, right?


That is correct. From the outside world, NaCl mode acts like a whole new
OSType. However,  NaCl mode is "mostly" linux (on linux) and mostly darwin
on macos - there is a shared code that does instruction processing which is
shared between nacl darwin x86 and nacl linux x86 -  but for the most part -
nacl ostype exists as a slight modification on the existing ostypes - we
felt that having a subfeature switch to activate the required processing was
the least invasive way to go.

-Jason



> > Lastly, speculating here as this patch doesn't go into these details, but
> be very careful with alignment
> > changes in code sections, as the ARM backend is very sensitive to small
> changes. Specifically, the constant island pass tracks instruction alignment
> and relative distances as exactly as it can, and will n!
> >  eed to be taught how to deal with these changes.
> >
> > Yep - we are in the middle of refactoring our local work in constant
> islands for eventual upstreaming.
> >
> > Hope this clarifies things!
> >
> > -jason
> >
> > -Jim
> >
> > On Sep 5, 2011, at 2:51 PM, Nick Lewycky wrote:
> >
> > > Author: nicholas
> > > Date: Mon Sep  5 16:51:43 2011
> > > New Revision: 139125
> > >
> > > URL: http://llvm.org/viewvc/llvm-project?rev=139125&view=rev
> > > Log:
> > > Add a new MC bit for NaCl (Native Client) mode. NaCl requires that
> certain
> > > instructions are more aligned than the CPU requires, and adds some
> additional
> > > directives, to follow in future patches. Patch by David Meyer!
> > >
> > > Modified:
> > >    llvm/trunk/lib/Target/ARM/ARM.td
> > >    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> > >    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> > >    llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> > >    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> > >    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> > >    llvm/trunk/lib/Target/X86/X86.td
> > >    llvm/trunk/lib/Target/X86/X86InstrInfo.td
> > >    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> > >    llvm/trunk/lib/Target/X86/X86Subtarget.h
> > >
> > > Modified: llvm/trunk/lib/Target/ARM/ARM.td
> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=139125&r1=139124&r2=139125&view=diff
> > >
> ==============================================================================
> > > --- llvm/trunk/lib/Target/ARM/ARM.td (original)
> > > +++ llvm/trunk/lib/Target/ARM/ARM.td Mon Sep  5 16:51:43 2011
> > > @@ -23,6 +23,9 @@
> > > def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
> > >                                   "Thumb mode">;
> > >
> > > +def ModeNaCl   : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
> > > +                                  "Native client mode">;
> > > +
> > >
> //===----------------------------------------------------------------------===//
> > > // ARM Subtarget features.
> > > //
> > >
> > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
> > >
> ==============================================================================
> > > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> > > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep  5 16:51:43 2011
> > > @@ -209,6 +209,8 @@
> > >                                  AssemblerPredicate<"!ModeThumb">;
> > > def IsDarwin         : Predicate<"Subtarget->isTargetDarwin()">;
> > > def IsNotDarwin      : Predicate<"!Subtarget->isTargetDarwin()">;
> > > +def IsNaCl           : Predicate<"Subtarget->isTargetNaCl()">,
> > > +                                 AssemblerPredicate<"ModeNaCl">;
> > >
> > > // FIXME: Eventually this will be just "hasV6T2Ops".
> > > def UseMovt          : Predicate<"Subtarget->useMovt()">;
> > >
> > > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
> > >
> ==============================================================================
> > > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
> > > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Sep  5 16:51:43 2011
> > > @@ -53,6 +53,7 @@
> > >   , HasVMLxForwarding(false)
> > >   , SlowFPBrcc(false)
> > >   , InThumbMode(false)
> > > +  , InNaClMode(false)
> > >   , HasThumb2(false)
> > >   , NoARM(false)
> > >   , PostRAScheduler(false)
> > >
> > > Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=139125&r1=139124&r2=139125&view=diff
> > >
> ==============================================================================
> > > --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
> > > +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Sep  5 16:51:43 2011
> > > @@ -70,6 +70,9 @@
> > >   /// InThumbMode - True if compiling for Thumb, false for ARM.
> > >   bool InThumbMode;
> > >
> > > +  /// InNaClMode - True if targeting Native Client
> > > +  bool InNaClMode;
> > > +
> > >   /// HasThumb2 - True if Thumb2 instructions are supported.
> > >   bool HasThumb2;
> > >
> > > @@ -209,6 +212,9 @@
> > >   const Triple &getTargetTriple() const { return TargetTriple; }
> > >
> > >   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
> > > +  bool isTargetNaCl() const {
> > > +    return TargetTriple.getOS() == Triple::NativeClient;
> > > +  }
> > >   bool isTargetELF() const { return !isTargetDarwin(); }
> > >
> > >   bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
> > >
> > > Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
> > >
> ==============================================================================
> > > --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> (original)
> > > +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Sep
>  5 16:51:43 2011
> > > @@ -86,6 +86,14 @@
> > >       ARMArchFeature += ",+thumb-mode";
> > >   }
> > >
> > > +  Triple TheTriple(TT);
> > > +  if (TheTriple.getOS() == Triple::NativeClient) {
> > > +    if (ARMArchFeature.empty())
> > > +      ARMArchFeature = "+nacl-mode";
> > > +    else
> > > +      ARMArchFeature += ",+nacl-mode";
> > > +  }
> > > +
> > >   return ARMArchFeature;
> > > }
> > >
> > >
> > > Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
> > >
> ==============================================================================
> > > --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> (original)
> > > +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Sep
>  5 16:51:43 2011
> > > @@ -40,9 +40,16 @@
> > >
> > > std::string X86_MC::ParseX86Triple(StringRef TT) {
> > >   Triple TheTriple(TT);
> > > +  std::string FS;
> > >   if (TheTriple.getArch() == Triple::x86_64)
> > > -    return "+64bit-mode";
> > > -  return "-64bit-mode";
> > > +    FS = "+64bit-mode";
> > > +  else
> > > +    FS = "-64bit-mode";
> > > +  if (TheTriple.getOS() == Triple::NativeClient)
> > > +    FS += ",+nacl-mode";
> > > +  else
> > > +    FS += ",-nacl-mode";
> > > +  return FS;
> > > }
> > >
> > > /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4
> values in the
> > >
> > > Modified: llvm/trunk/lib/Target/X86/X86.td
> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=139125&r1=139124&r2=139125&view=diff
> > >
> ==============================================================================
> > > --- llvm/trunk/lib/Target/X86/X86.td (original)
> > > +++ llvm/trunk/lib/Target/X86/X86.td Mon Sep  5 16:51:43 2011
> > > @@ -23,6 +23,9 @@
> > > def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
> > >                                   "64-bit mode (x86_64)">;
> > >
> > > +def ModeNaCl  : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
> > > +                                 "Native Client mode">;
> > > +
> > >
> //===----------------------------------------------------------------------===//
> > > // X86 Subtarget features.
> > >
> //===----------------------------------------------------------------------===//
> > >
> > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
> > >
> ==============================================================================
> > > --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> > > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep  5 16:51:43 2011
> > > @@ -482,6 +482,14 @@
> > >                              AssemblerPredicate<"Mode64Bit">;
> > > def IsWin64      : Predicate<"Subtarget->isTargetWin64()">;
> > > def NotWin64     : Predicate<"!Subtarget->isTargetWin64()">;
> > > +def IsNaCl       : Predicate<"Subtarget->isTargetNaCl()">,
> > > +                             AssemblerPredicate<"ModeNaCl">;
> > > +def IsNaCl32     : Predicate<"Subtarget->isTargetNaCl32()">,
> > > +
> AssemblerPredicate<"ModeNaCl,!Mode64Bit">;
> > > +def IsNaCl64     : Predicate<"Subtarget->isTargetNaCl64()">,
> > > +                             AssemblerPredicate<"ModeNaCl,Mode64Bit">;
> > > +def NotNaCl      : Predicate<"!Subtarget->isTargetNaCl()">,
> > > +                             AssemblerPredicate<"!ModeNaCl">;
> > > def SmallCode    : Predicate<"TM.getCodeModel() == CodeModel::Small">;
> > > def KernelCode   : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
> > > def FarData      : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
> > >
> > > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
> > >
> ==============================================================================
> > > --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
> > > +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Sep  5 16:51:43 2011
> > > @@ -260,7 +260,8 @@
> > >   // FIXME: this is a known good value for Yonah. How about others?
> > >   , MaxInlineSizeThreshold(128)
> > >   , TargetTriple(TT)
> > > -  , In64BitMode(is64Bit) {
> > > +  , In64BitMode(is64Bit)
> > > +  , InNaClMode(false) {
> > >   // Determine default and user specified characteristics
> > >   if (!FS.empty() || !CPU.empty()) {
> > >     std::string CPUName = CPU;
> > > @@ -306,6 +307,11 @@
> > >   if (In64BitMode)
> > >     ToggleFeature(X86::Mode64Bit);
> > >
> > > +  if (isTargetNaCl()) {
> > > +    InNaClMode = true;
> > > +    ToggleFeature(X86::ModeNaCl);
> > > +  }
> > > +
> > >   if (HasAVX)
> > >     X86SSELevel = NoMMXSSE;
> > >
> > >
> > > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
> > > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=139125&r1=139124&r2=139125&view=diff
> > >
> ==============================================================================
> > > --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
> > > +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Sep  5 16:51:43 2011
> > > @@ -119,6 +119,9 @@
> > >   /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
> > >   bool In64BitMode;
> > >
> > > +  /// InNaClMode - True if compiling for Native Client target.
> > > +  bool InNaClMode;
> > > +
> > > public:
> > >
> > >   /// This constructor initializes the data members to match that
> > > @@ -190,6 +193,11 @@
> > >     return !isTargetDarwin() && !isTargetWindows() &&
> !isTargetCygMing();
> > >   }
> > >   bool isTargetLinux() const { return TargetTriple.getOS() ==
> Triple::Linux; }
> > > +  bool isTargetNaCl() const {
> > > +    return TargetTriple.getOS() == Triple::NativeClient;
> > > +  }
> > > +  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
> > > +  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
> > >
> > >   bool isTargetWindows() const { return TargetTriple.getOS() ==
> Triple::Win32; }
> > >   bool isTargetMingw() const { return TargetTriple.getOS() ==
> Triple::MinGW32; }
> > >
> > >
> > > _______________________________________________
> > > llvm-commits mailing list
> > > llvm-commits at cs.uiuc.edu
> > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >
>
>
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From eli.friedman at gmail.com  Tue Sep  6 15:53:37 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 06 Sep 2011 20:53:37 -0000
Subject: [llvm-commits] [llvm] r139179 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20110906205337.7D7F52A6C12C@llvm.org>

Author: efriedma
Date: Tue Sep  6 15:53:37 2011
New Revision: 139179

URL: http://llvm.org/viewvc/llvm-project?rev=139179&view=rev
Log:
Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions.


Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139179&r1=139178&r2=139179&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Sep  6 15:53:37 2011
@@ -1611,7 +1611,7 @@
 
 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
 // (These psuedos use a hand-written selection code).
-let usesCustomInserter = 1, Defs = [CPSR] in {
+let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
 def ATOMOR6432   : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
                               (ins GPR:$addr, GPR:$src1, GPR:$src2),
                               NoItinerary, []>;



From James.Molloy at arm.com  Tue Sep  6 16:27:03 2011
From: James.Molloy at arm.com (James Molloy)
Date: Tue, 6 Sep 2011 22:27:03 +0100
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and
	resolve	(safe) ambiguous instruction encodings
In-Reply-To: <C3CBC2F0-CA9B-4393-BB0D-EAD4AD60A0E0@me.com>
References: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>,
	<C3CBC2F0-CA9B-4393-BB0D-EAD4AD60A0E0@me.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA473757133E1@GEORGE.Emea.Arm.com>

Owen,

I don't have the ISA reference in front of me right now (not at work), but IIRC the problem was less that the encoding was wrong and more that there wasn't a Thumb2 STC instruction node at all, only an ARM-mode one.

Therefore it failed to decode now that the predicate checks are correctly in place. Creating a t2STC2 insn node is the answer to fix it, but I didn't want to stuff everything into one patch. I can fix that as a followup.

James
________________________________________
From: Owen Anderson [resistor at me.com]
Sent: 06 September 2011 21:44
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve      (safe) ambiguous instruction encodings

James,

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
> is created.**

What exactly is the issue with STC's?  My copy of the ISA reference shows the encoding being the same for ARM and Thumb2 modes, other than the lack of a predicate operand in Thumb2 mode.

--Owen



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From James.Molloy at arm.com  Tue Sep  6 16:29:28 2011
From: James.Molloy at arm.com (James Molloy)
Date: Tue, 6 Sep 2011 22:29:28 +0100
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and
	resolve	(safe) ambiguous instruction encodings
In-Reply-To: <718C7FA3-810A-486A-80BD-F3476C59DBFF@me.com>
References: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>,
	<718C7FA3-810A-486A-80BD-F3476C59DBFF@me.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA473757133E2@GEORGE.Emea.Arm.com>

Hi Owen,

Sorry for taking so long getting back to you on this - make check has crashed my laptop twice now with what appears to be an errant llc process. I'm looking into that now (doesn't happen when running lit manually...)

Anyway, the patch attached applies to ToT now and has no conflicts. All targets build correctly and the regression tests pass.

Cheers,

James
________________________________________
From: Owen Anderson [resistor at me.com]
Sent: 06 September 2011 19:43
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve      (safe) ambiguous instruction encodings

James,

Patch 0 seems to be missing some necessary changes to non-ARM targets to make LLVM build with it applied.  I see a lot of errors of the form:

MipsMCTargetDesc.cpp:109:41: error: cannot initialize a parameter of type 'Target::MCInstPrinterCtorTy' (aka 'llvm::MCInstPrinter *(*)(const llvm::Target
      &, unsigned int, const llvm::MCAsmInfo &, const llvm::MCSubtargetInfo &)') with an lvalue of type 'llvm::MCInstPrinter *(const llvm::Target &,
      unsigned int, const llvm::MCAsmInfo &)'
                                        createMipsMCInstPrinter);
                                        ^~~~~~~~~~~~~~~~~~~~~~~

--Owen

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:

> Hi,
>
> The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M series
> not allowing the correct mask names.
>
> The patch becomes difficult because:
>  * There is no way to determine in the InstPrinter any subtarget specific
> features (such as "operating on an m-class core?").
>  * There is currently no subtarget feature for "M-class core?"; the nearest is
> IsThumb2 && !HasARM.
>  * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
> a way that makes them deterministically separable. This causes non-conflicting
> ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
> both code paths are emitted but only one will ever be hit.
>
> The solution is:
>  * Add subtarget info to InstPrinter so it can determine what to do with the
> mask immediate.
>  * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
> IsARClass == !IsMClass. This feature only has semantic sense on v6+
> architectures.
>  * The conflicts occur because the FixedLenDecoderEmitter does not honour the
> Predicates field of instructions in the tablegen description. If the island
> checking also checked the AssemblerPredicates field (if defined), ambiguous
> instruction encodings that are disambiguated by predicates would (do) work fine.
>
> The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and MCDisassembler.
> They can use this (in patch #2) to determine what mask names to accept (primask?
> or cpsr_zxvf?)
>
> The second enhances FixedLenPredicateEncoder to emit predicate checks for
> instructions before it accepts an encoding - this allows ambiguous instructions
> to be disambiguated by the Predicates field in TableGen. This required changing
> llvm-mc to accept -mattr, and tests to set the correct features they rely upon.
>
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
> is created.**
>
> The third patch adds a new predicate "IsMClass" along with its counterpart
> "IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
> Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
> encodings respectively. It also fixes mask printing for MRS/MSR in the
> ARMMCInstPrinter and ARMMCAsmParser.
>
> Testcases added with the final patch.
>
> Comments? Is it OK?
>
> Cheers,
>
> James
>
> [N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout myself
> after review]
> <patch0-add-sti-to-instprinter.patch><patch1-modify-fixedlendecoderemitter.patch><patch2-fix-msr-mrs.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




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From nicholas at mxc.ca  Tue Sep  6 16:42:18 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 06 Sep 2011 21:42:18 -0000
Subject: [llvm-commits] [llvm] r139186 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp
 test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
Message-ID: <20110906214218.C887D2A6C12C@llvm.org>

Author: nicholas
Date: Tue Sep  6 16:42:18 2011
New Revision: 139186

URL: http://llvm.org/viewvc/llvm-project?rev=139186&view=rev
Log:
This transform only handles two-operand AddRec's. Prevent it from trying to
handle anything more complex. Fixes PR10383 again!

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139186&r1=139185&r2=139186&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Sep  6 16:42:18 2011
@@ -1974,7 +1974,8 @@
     // multiplied together.  If so, we can fold them.
     for (unsigned OtherIdx = Idx+1;
          OtherIdx < Ops.size() && isa<SCEVAddRecExpr>(Ops[OtherIdx]);
-         ++OtherIdx)
+         ++OtherIdx) {
+      bool Retry = false;
       if (AddRecLoop == cast<SCEVAddRecExpr>(Ops[OtherIdx])->getLoop()) {
         // {A,+,B}<L> * {C,+,D}<L>  -->  {A*C,+,A*D + B*C + B*D,+,2*B*D}<L>
         //
@@ -1985,7 +1986,7 @@
         // Rearranging, X = x, Y = y+z, Z = 2z.
         //
         // x = A*C, y = (A*D + B*C), z = B*D.
-        // Therefore X = A*C, Y = (A*D + B*C) + B*D and Z = 2*B*D.
+        // Therefore X = A*C, Y = A*D + B*C + B*D and Z = 2*B*D.
         for (; OtherIdx != Ops.size() && isa<SCEVAddRecExpr>(Ops[OtherIdx]);
              ++OtherIdx)
           if (const SCEVAddRecExpr *OtherAddRec =
@@ -2002,19 +2003,28 @@
               const SCEV *NewSecondOrderStep =
                   getMulExpr(BD, getConstant(BD->getType(), 2));
 
-              SmallVector<const SCEV *, 3> AddRecOps;
-              AddRecOps.push_back(NewStart);
-              AddRecOps.push_back(NewStep);
-              AddRecOps.push_back(NewSecondOrderStep);
-              const SCEV *NewAddRec = getAddRecExpr(AddRecOps,
-                                                    AddRec->getLoop(),
-                                                    SCEV::FlagAnyWrap);
-              if (Ops.size() == 2) return NewAddRec;
-              Ops[Idx] = AddRec = cast<SCEVAddRecExpr>(NewAddRec);
-              Ops.erase(Ops.begin() + OtherIdx); --OtherIdx;
+              // This can happen when AddRec or OtherAddRec have >3 operands.
+              // TODO: support these add-recs.
+              if (isLoopInvariant(NewStart, AddRecLoop) &&
+                  isLoopInvariant(NewStep, AddRecLoop) &&
+                  isLoopInvariant(NewSecondOrderStep, AddRecLoop)) {
+                SmallVector<const SCEV *, 3> AddRecOps;
+                AddRecOps.push_back(NewStart);
+                AddRecOps.push_back(NewStep);
+                AddRecOps.push_back(NewSecondOrderStep);
+                const SCEV *NewAddRec = getAddRecExpr(AddRecOps,
+                                                      AddRec->getLoop(),
+                                                      SCEV::FlagAnyWrap);
+                if (Ops.size() == 2) return NewAddRec;
+                Ops[Idx] = AddRec = cast<SCEVAddRecExpr>(NewAddRec);
+                Ops.erase(Ops.begin() + OtherIdx); --OtherIdx;
+                Retry = true;
+              }
             }
-        return getMulExpr(Ops);
+        if (Retry)
+          return getMulExpr(Ops);
       }
+    }
 
     // Otherwise couldn't fold anything into this recurrence.  Move onto the
     // next one.

Modified: llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll?rev=139186&r1=139185&r2=139186&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll Tue Sep  6 16:42:18 2011
@@ -35,7 +35,7 @@
 
 
 ; PR10383
-; This used to crash.
+; These next two used to crash.
 
 define void @test2(i1 %cmp, i64 %n) {
 entry:
@@ -61,3 +61,22 @@
   ret void
 }
 ; CHECK: Determining loop execution counts for: @test2
+
+define i32 @test3() {
+if.then466:
+  br i1 undef, label %for.cond539.preheader, label %for.inc479
+
+for.inc479:
+  %a2.07 = phi i32 [ %add495, %for.inc479 ], [ 0, %if.then466 ]
+  %j.36 = phi i32 [ %inc497, %for.inc479 ], [ undef, %if.then466 ]
+  %mul484 = mul nsw i32 %j.36, %j.36
+  %mul491 = mul i32 %j.36, %j.36
+  %mul493 = mul i32 %mul491, %mul484
+  %add495 = add nsw i32 %mul493, %a2.07
+  %inc497 = add nsw i32 %j.36, 1
+  br i1 undef, label %for.cond539.preheader, label %for.inc479
+
+for.cond539.preheader:
+  unreachable
+}
+; CHECK: Determining loop execution counts for: @test3



From grosbach at apple.com  Tue Sep  6 16:44:58 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 21:44:58 -0000
Subject: [llvm-commits] [llvm] r139188 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110906214458.A92C42A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep  6 16:44:58 2011
New Revision: 139188

URL: http://llvm.org/viewvc/llvm-project?rev=139188&view=rev
Log:
Thumb2 parsing and encoding for CMN and CMP.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139188&r1=139187&r2=139188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep  6 16:44:58 2011
@@ -798,7 +798,7 @@
   def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
      (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
                                                     ty:$imm, pred:$p,
-                                                    cc_out:$s)>;
+                                                   cc_out:$s)>;
   def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
      (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
                                                     rGPR:$Rm, pred:$p,
@@ -818,15 +818,15 @@
 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
 /// a explicit result, only implicitly set CPSR.
-let isCompare = 1, Defs = [CPSR] in {
 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
-                       PatFrag opnode> {
+                       PatFrag opnode, string baseOpc> {
+let isCompare = 1, Defs = [CPSR] in {
    // shifted imm
    def ri : T2OneRegCmpImm<
-                (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
+                (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
                 opc, ".w\t$Rn, $imm",
-                [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
+                [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
      let Inst{31-27} = 0b11110;
      let Inst{25} = 0;
      let Inst{24-21} = opcod;
@@ -836,9 +836,9 @@
    }
    // register
    def rr : T2TwoRegCmp<
-                (outs), (ins GPR:$Rn, rGPR:$Rm), iir,
+                (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
                 opc, ".w\t$Rn, $Rm",
-                [(opnode GPR:$Rn, rGPR:$Rm)]> {
+                [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
@@ -850,9 +850,9 @@
    }
    // shifted register
    def rs : T2OneRegCmpShiftedReg<
-                (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
+                (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
                 opc, ".w\t$Rn, $ShiftedRm",
-                [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
+                [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
@@ -860,6 +860,17 @@
      let Inst{11-8} = 0b1111; // Rd
    }
 }
+
+  // Assembler aliases w/o the ".w" suffix.
+  // No alias here for 'rr' version as not all instantiations of this
+  // multiclass want one (CMP in particular, does not).
+  def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
+     (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
+                                                    t2_so_imm:$imm, pred:$p)>;
+  def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
+     (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
+                                                    t2_so_reg:$shift,
+                                                    pred:$p)>;
 }
 
 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
@@ -2646,14 +2657,14 @@
 //
 defm t2CMP  : T2I_cmp_irs<0b1101, "cmp",
                           IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
-                          BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
+                          BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
 
-def : T2Pat<(ARMcmpZ  GPR:$lhs, t2_so_imm:$imm),
-            (t2CMPri  GPR:$lhs, t2_so_imm:$imm)>;
-def : T2Pat<(ARMcmpZ  GPR:$lhs, rGPR:$rhs),
-            (t2CMPrr  GPR:$lhs, rGPR:$rhs)>;
-def : T2Pat<(ARMcmpZ  GPR:$lhs, t2_so_reg:$rhs),
-            (t2CMPrs  GPR:$lhs, t2_so_reg:$rhs)>;
+def : T2Pat<(ARMcmpZ  GPRnopc:$lhs, t2_so_imm:$imm),
+            (t2CMPri  GPRnopc:$lhs, t2_so_imm:$imm)>;
+def : T2Pat<(ARMcmpZ  GPRnopc:$lhs, rGPR:$rhs),
+            (t2CMPrr  GPRnopc:$lhs, rGPR:$rhs)>;
+def : T2Pat<(ARMcmpZ  GPRnopc:$lhs, t2_so_reg:$rhs),
+            (t2CMPrs  GPRnopc:$lhs, t2_so_reg:$rhs)>;
 
 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
 //       Compare-to-zero still works out, just not the relationals
@@ -2661,20 +2672,23 @@
 //                          BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
                           IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
-                          BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
+                          BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
+                          "t2CMNz">;
 
 //def : T2Pat<(ARMcmp  GPR:$src, t2_so_imm_neg:$imm),
 //            (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
 
-def : T2Pat<(ARMcmpZ  GPR:$src, t2_so_imm_neg:$imm),
-            (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
+def : T2Pat<(ARMcmpZ  GPRnopc:$src, t2_so_imm_neg:$imm),
+            (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
 
 defm t2TST  : T2I_cmp_irs<0b0000, "tst",
                           IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
-                         BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
+                         BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
+                          "t2TST">;
 defm t2TEQ  : T2I_cmp_irs<0b0100, "teq",
                           IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
-                         BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
+                         BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
+                          "t2TEQ">;
 
 // Conditional moves
 // FIXME: should be able to write a pattern for ARMcmov, but can't use
@@ -3567,3 +3581,12 @@
 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
                   (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
                            pred:$p, cc_out:$s)>;
+
+// Alias for compares without the ".w" optional width specifier.
+def : t2InstAlias<"cmn${p} $Rn, $Rm",
+                  (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
+def : t2InstAlias<"teq${p} $Rn, $Rm",
+                  (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
+def : t2InstAlias<"tst${p} $Rn, $Rm",
+                  (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
+

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139188&r1=139187&r2=139188&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep  6 16:44:58 2011
@@ -317,6 +317,46 @@
 
 
 @------------------------------------------------------------------------------
+@ CMN
+ at ------------------------------------------------------------------------------
+        cmn r1, #0xf
+        cmn r8, r6
+        cmn r1, r6, lsl #10
+        cmn r1, r6, lsr #10
+        cmn sp, r6, lsr #10
+        cmn r1, r6, asr #10
+        cmn r1, r6, ror #10
+
+@ CHECK: cmn.w	r1, #15                 @ encoding: [0x11,0xf1,0x0f,0x0f]
+@ CHECK: cmn.w	r8, r6                  @ encoding: [0x18,0xeb,0x06,0x0f]
+@ CHECK: cmn.w	r1, r6, lsl #10         @ encoding: [0x11,0xeb,0x86,0x2f]
+@ CHECK: cmn.w	r1, r6, lsr #10         @ encoding: [0x11,0xeb,0x96,0x2f]
+@ CHECK: cmn.w	sp, r6, lsr #10         @ encoding: [0x1d,0xeb,0x96,0x2f]
+@ CHECK: cmn.w	r1, r6, asr #10         @ encoding: [0x11,0xeb,0xa6,0x2f]
+@ CHECK: cmn.w	r1, r6, ror #10         @ encoding: [0x11,0xeb,0xb6,0x2f]
+
+
+ at ------------------------------------------------------------------------------
+@ CMP
+ at ------------------------------------------------------------------------------
+        cmp r5, #0xff00
+        cmp.w r4, r12
+        cmp r9, r6, lsl #12
+        cmp r3, r7, lsr #31
+        cmp sp, r6, lsr #1
+        cmp r2, r5, asr #24
+        cmp r1, r4, ror #15
+
+@ CHECK: cmp.w	r5, #65280              @ encoding: [0xb5,0xf5,0x7f,0x4f]
+@ CHECK: cmp.w	r4, r12                 @ encoding: [0xb4,0xeb,0x0c,0x0f]
+@ CHECK: cmp.w	r9, r6, lsl #12         @ encoding: [0xb9,0xeb,0x06,0x3f]
+@ CHECK: cmp.w	r3, r7, lsr #31         @ encoding: [0xb3,0xeb,0xd7,0x7f]
+@ CHECK: cmp.w	sp, r6, lsr #1          @ encoding: [0xbd,0xeb,0x56,0x0f]
+@ CHECK: cmp.w	r2, r5, asr #24         @ encoding: [0xb2,0xeb,0x25,0x6f]
+@ CHECK: cmp.w	r1, r4, ror #15         @ encoding: [0xb1,0xeb,0xf4,0x3f]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From evan.cheng at apple.com  Tue Sep  6 16:53:30 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 06 Sep 2011 14:53:30 -0700
Subject: [llvm-commits] [llvm] r139157 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td
 lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/carry.ll
In-Reply-To: <FF1F6AE9-14EB-464F-BD2B-C719715395B5@apple.com>
References: <20110906185221.2FCBE2A6C12C@llvm.org>
	<FF1F6AE9-14EB-464F-BD2B-C719715395B5@apple.com>
Message-ID: <2E1F03FA-67AE-4635-8266-9DA8CD94D20F@apple.com>


On Sep 6, 2011, at 1:23 PM, Jim Grosbach wrote:

> Hi Evan,
> 
> In that case, can we get rid of the distinct ADDS definitions entirely and just use the ADD instructions w/ the cc_out operand set appropriately?

I'd like to but current TableGen technology doesn't allow it. See FIXME in code.

Evan

> 
> -Jim
> 
> On Sep 6, 2011, at 11:52 AM, Evan Cheng wrote:
> 
>> Author: evancheng
>> Date: Tue Sep  6 13:52:20 2011
>> New Revision: 139157
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=139157&view=rev
>> Log:
>> Fix fall outs from my recent change on how carry bit is modeled during isel.
>> Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
>> Also fix isel hook to correctly set the optional operand.
>> rdar://10073745
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>   llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>>   llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>>   llvm/trunk/test/CodeGen/ARM/carry.ll
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=139157&r1=139156&r2=139157&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Sep  6 13:52:20 2011
>> @@ -5708,7 +5708,7 @@
>>  // the optional operand to CPSR. Otherwise, remove the CPSR implicit def.
>>  const MCInstrDesc &MCID = MI->getDesc();
>>  if (Node->hasAnyUseOfValue(1)) {
>> -    MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 2);
>> +    MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 1);
>>    MO.setReg(ARM::CPSR);
>>    MO.setIsDef(true);
>>  } else {
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139157&r1=139156&r2=139157&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Sep  6 13:52:20 2011
>> @@ -1037,8 +1037,8 @@
>> 
>> }
>> 
>> -/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except sets 's' bit.
>> -let isCodeGenOnly = 1, Defs = [CPSR] in {
>> +/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except it sets 's' bit by default.
>> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
>> multiclass AsI1_rbin_s_is<bits<4> opcod, string opc,
>>                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
>>                        PatFrag opnode, bit Commutable = 0> {
>> @@ -1101,25 +1101,25 @@
>> }
>> }
>> 
>> -/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
>> -/// instruction modifies the CPSR register.
>> -let isCodeGenOnly = 1, Defs = [CPSR] in {
>> -multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
>> +/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
>> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
>> +multiclass AsI1_bin_s_irs<bits<4> opcod, string opc,
>>                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
>>                         PatFrag opnode, bit Commutable = 0> {
>> -  def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
>> +  let isReMaterializable = 1 in {
>> +  def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
>>               iii, opc, "\t$Rd, $Rn, $imm",
>>               [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]> {
>>    bits<4> Rd;
>>    bits<4> Rn;
>>    bits<12> imm;
>>    let Inst{25} = 1;
>> -    let Inst{20} = 1;
>>    let Inst{19-16} = Rn;
>>    let Inst{15-12} = Rd;
>>    let Inst{11-0} = imm;
>>  }
>> -  def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
>> +  }
>> +  def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
>>               iir, opc, "\t$Rd, $Rn, $Rm",
>>               [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
>>    bits<4> Rd;
>> @@ -1127,13 +1127,12 @@
>>    bits<4> Rm;
>>    let isCommutable = Commutable;
>>    let Inst{25} = 0;
>> -    let Inst{20} = 1;
>>    let Inst{19-16} = Rn;
>>    let Inst{15-12} = Rd;
>>    let Inst{11-4} = 0b00000000;
>>    let Inst{3-0} = Rm;
>>  }
>> -  def rsi : AI1<opcod, (outs GPR:$Rd),
>> +  def rsi : AsI1<opcod, (outs GPR:$Rd),
>>               (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
>>               iis, opc, "\t$Rd, $Rn, $shift",
>>               [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
>> @@ -1141,7 +1140,6 @@
>>    bits<4> Rn;
>>    bits<12> shift;
>>    let Inst{25} = 0;
>> -    let Inst{20} = 1;
>>    let Inst{19-16} = Rn;
>>    let Inst{15-12} = Rd;
>>    let Inst{11-5} = shift{11-5};
>> @@ -1149,7 +1147,7 @@
>>    let Inst{3-0} = shift{3-0};
>>  }
>> 
>> -  def rsr : AI1<opcod, (outs GPR:$Rd),
>> +  def rsr : AsI1<opcod, (outs GPR:$Rd),
>>               (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
>>               iis, opc, "\t$Rd, $Rn, $shift",
>>               [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
>> @@ -3136,10 +3134,12 @@
>>                         BinOpFrag<(sub  node:$LHS, node:$RHS)>, "SUB">;
>> 
>> // ADD and SUB with 's' bit set.
>> -defm ADDS : AI1_bin_s_irs<0b0100, "adds",
>> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
>> +// CPSR and the implicit def of CPSR is not needed.
>> +defm ADDS : AsI1_bin_s_irs<0b0100, "add",
>>                          IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>>                          BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
>> -defm SUBS : AI1_bin_s_irs<0b0010, "subs",
>> +defm SUBS : AsI1_bin_s_irs<0b0010, "sub",
>>                          IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>>                          BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
>> 
>> @@ -3153,6 +3153,9 @@
>> defm RSB  : AsI1_rbin_irs <0b0011, "rsb",
>>                         IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>>                         BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
>> +
>> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
>> +// CPSR and the implicit def of CPSR is not needed.
>> defm RSBS : AsI1_rbin_s_is<0b0011, "rsb",
>>                         IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>>                         BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139157&r1=139156&r2=139157&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep  6 13:52:20 2011
>> @@ -588,44 +588,41 @@
>> 
>> /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
>> /// instruction modifies the CPSR register.
>> -let isCodeGenOnly = 1, Defs = [CPSR] in {
>> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
>> multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
>>                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
>>                         PatFrag opnode, bit Commutable = 0> {
>>   // shifted imm
>> -   def ri : T2TwoRegImm<
>> +   def ri : T2sTwoRegImm<
>>                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
>> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
>> +                opc, ".w\t$Rd, $Rn, $imm",
>>                [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
>>     let Inst{31-27} = 0b11110;
>>     let Inst{25} = 0;
>>     let Inst{24-21} = opcod;
>> -     let Inst{20} = 1; // The S bit.
>>     let Inst{15} = 0;
>>   }
>>   // register
>> -   def rr : T2ThreeReg<
>> +   def rr : T2sThreeReg<
>>                (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
>> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
>> +                opc, ".w\t$Rd, $Rn, $Rm",
>>                [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
>>     let isCommutable = Commutable;
>>     let Inst{31-27} = 0b11101;
>>     let Inst{26-25} = 0b01;
>>     let Inst{24-21} = opcod;
>> -     let Inst{20} = 1; // The S bit.
>>     let Inst{14-12} = 0b000; // imm3
>>     let Inst{7-6} = 0b00; // imm2
>>     let Inst{5-4} = 0b00; // type
>>   }
>>   // shifted register
>> -   def rs : T2TwoRegShiftedReg<
>> +   def rs : T2sTwoRegShiftedReg<
>>                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
>> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
>> +                opc, ".w\t$Rd, $Rn, $ShiftedRm",
>>               [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
>>     let Inst{31-27} = 0b11101;
>>     let Inst{26-25} = 0b01;
>>     let Inst{24-21} = opcod;
>> -     let Inst{20} = 1; // The S bit.
>>   }
>> }
>> }
>> @@ -737,28 +734,26 @@
>> 
>> /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
>> /// version is not needed since this is only for codegen.
>> -let isCodeGenOnly = 1, Defs = [CPSR] in {
>> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
>> multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
>>   // shifted imm
>> -   def ri : T2TwoRegImm<
>> +   def ri : T2sTwoRegImm<
>>                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
>> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
>> +                opc, ".w\t$Rd, $Rn, $imm",
>>                [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
>>     let Inst{31-27} = 0b11110;
>>     let Inst{25} = 0;
>>     let Inst{24-21} = opcod;
>> -     let Inst{20} = 1; // The S bit.
>>     let Inst{15} = 0;
>>   }
>>   // shifted register
>> -   def rs : T2TwoRegShiftedReg<
>> +   def rs : T2sTwoRegShiftedReg<
>>                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
>> -                IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
>> +                IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
>>              [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
>>     let Inst{31-27} = 0b11101;
>>     let Inst{26-25} = 0b01;
>>     let Inst{24-21} = opcod;
>> -     let Inst{20} = 1; // The S bit.
>>   }
>> }
>> }
>> @@ -1699,6 +1694,8 @@
>>                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
>> 
>> // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
>> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
>> +// CPSR and the implicit def of CPSR is not needed.
>> defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
>>                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
>>                             BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
>> @@ -1716,6 +1713,9 @@
>> // RSB
>> defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb",
>>                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
>> +
>> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
>> +// CPSR and the implicit def of CPSR is not needed.
>> defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
>>                             BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
>> 
>> 
>> Modified: llvm/trunk/test/CodeGen/ARM/carry.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/carry.ll?rev=139157&r1=139156&r2=139157&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/carry.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/carry.ll Tue Sep  6 13:52:20 2011
>> @@ -35,3 +35,13 @@
>> 	%dw = add i64 %ch, %bw
>> 	ret i64 %dw
>> }
>> +
>> +; rdar://10073745
>> +define i64 @f4(i64 %x) nounwind readnone {
>> +entry:
>> +; CHECK: f4:
>> +; CHECK: rsbs r
>> +; CHECK: rsc r
>> +  %0 = sub nsw i64 0, %x
>> +  ret i64 %0
>> +}
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 


From bob.wilson at apple.com  Tue Sep  6 16:53:06 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 06 Sep 2011 21:53:06 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r139189 - in /llvm-gcc-4.2/trunk/gcc:
 config/arm/llvm-arm-target.h config/arm/llvm-arm.cpp
 config/i386/llvm-i386-target.h config/mips/llvm-mips-target.h
 config/rs6000/rs6000.h config/sparc/sparc.h llvm-abi-default.cpp llvm-abi.h
 llvm-convert.cpp
Message-ID: <20110906215306.7E2592A6C12C@llvm.org>

Author: bwilson
Date: Tue Sep  6 16:53:06 2011
New Revision: 139189

URL: http://llvm.org/viewvc/llvm-project?rev=139189&view=rev
Log:
Disable ARM byval. It is not supported as of r138977. <rdar://problem/10066897>
--- Reverse-merging r132251 into '.':
U    gcc/config/arm/llvm-arm.cpp
--- Reverse-merging r130447 into '.':
G    gcc/config/arm/llvm-arm.cpp
--- Reverse-merging r130406 into '.':
U    gcc/llvm-convert.cpp
U    gcc/llvm-abi-default.cpp
U    gcc/llvm-abi.h
U    gcc/config/sparc/sparc.h
U    gcc/config/i386/llvm-i386-target.h
U    gcc/config/rs6000/rs6000.h
U    gcc/config/arm/llvm-arm-target.h
G    gcc/config/arm/llvm-arm.cpp
U    gcc/config/mips/llvm-mips-target.h


Modified:
    llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h
    llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp
    llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
    llvm-gcc-4.2/trunk/gcc/config/mips/llvm-mips-target.h
    llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h
    llvm-gcc-4.2/trunk/gcc/config/sparc/sparc.h
    llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp
    llvm-gcc-4.2/trunk/gcc/llvm-abi.h
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h?rev=139189&r1=139188&r2=139189&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h Tue Sep  6 16:53:06 2011
@@ -98,14 +98,6 @@
 #define LLVM_SHOULD_NOT_USE_SHADOW_RETURN(X, CC) \
     llvm_arm_should_pass_or_return_aggregate_in_regs((X), (CC))
 
-extern
-bool llvm_arm_should_pass_aggregate_using_byval_attr(tree, Type *,
-                                                     CallingConv::ID &CC);
-
-#define LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(X, TY, CC)        \
-    (llvm_arm_should_pass_aggregate_using_byval_attr((X), (TY), (CC)))
-
-
 /* Vectors bigger than 128 are returned using sret.  */
 #define LLVM_SHOULD_RETURN_VECTOR_AS_SHADOW(X, isBuiltin) \
   (TREE_INT_CST_LOW(TYPE_SIZE(X)) > 128)

Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp?rev=139189&r1=139188&r2=139189&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Tue Sep  6 16:53:06 2011
@@ -2873,19 +2873,4 @@
   return result && !TREE_ADDRESSABLE(TreeType);
 }
 
-/* Target hook for llvm-abi.h. It returns true if an aggregate of the
-   specified type should be passed with the 'byval' attribute. */
-bool llvm_arm_should_pass_aggregate_using_byval_attr(tree TreeType,
-                                                     Type *Ty,
-                                                     CallingConv::ID &CC) {
-  if (CC == CallingConv::ARM_APCS ||
-      (CC == CallingConv::C && !TARGET_AAPCS_BASED)) {
-    enum machine_mode Mode = TYPE_MODE(TreeType);
-    HOST_WIDE_INT Bytes = (Mode == BLKmode) ? int_size_in_bytes(TreeType) :
-      (int) GET_MODE_SIZE(Mode);
-    return Bytes > 64;
-  }
-  return false;
-}
-
 /* LLVM LOCAL end (ENTIRE FILE!)  */

Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=139189&r1=139188&r2=139189&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Tue Sep  6 16:53:06 2011
@@ -227,7 +227,7 @@
 
 extern bool llvm_x86_should_pass_aggregate_in_memory(tree, Type *);
 
-#define LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(X, TY, CC)     \
+#define LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(X, TY)      \
   llvm_x86_should_pass_aggregate_in_memory(X, TY)
 
 

Modified: llvm-gcc-4.2/trunk/gcc/config/mips/llvm-mips-target.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/mips/llvm-mips-target.h?rev=139189&r1=139188&r2=139189&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/mips/llvm-mips-target.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/mips/llvm-mips-target.h Tue Sep  6 16:53:06 2011
@@ -27,7 +27,7 @@
 /* LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR - Return true if this aggregate
    value should be passed by value, i.e. passing its address with the byval
    attribute bit set. The default is false.  */
-#define LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(X, TY, CC)     \
+#define LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(X, TY) \
   llvm_mips_should_pass_aggregate_in_memory(X, TY)
 
 extern bool

Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=139189&r1=139188&r2=139189&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Tue Sep  6 16:53:06 2011
@@ -3499,7 +3499,7 @@
 
 extern bool llvm_rs6000_should_pass_aggregate_byval(tree, Type *);
 
-#define LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(X, TY, CC)     \
+#define LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(X, TY)      \
   llvm_rs6000_should_pass_aggregate_byval((X), (TY))
 
 extern bool llvm_rs6000_should_pass_vector_in_integer_regs(tree);

Modified: llvm-gcc-4.2/trunk/gcc/config/sparc/sparc.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/sparc/sparc.h?rev=139189&r1=139188&r2=139189&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/sparc/sparc.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/sparc/sparc.h Tue Sep  6 16:53:06 2011
@@ -2488,7 +2488,7 @@
  */
 #define LLVM_TARGET_NAME Sparc
 
-#define LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(X, TY, CC)     \
+#define LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(X, TY) \
   true
 
 #endif /* ENABLE_LLVM */

Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp?rev=139189&r1=139188&r2=139189&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp Tue Sep  6 16:53:06 2011
@@ -117,7 +117,7 @@
 	  Attribute::constructAlignmentFromInt(LLVM_BYVAL_ALIGNMENT(type));
       }
     }
-  } else if (LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(type, Ty, C.getCallingConv())) {
+  } else if (LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(type, Ty)) {
     C.HandleByValArgument(Ty, type);
     if (Attributes) {
       *Attributes |= Attribute::ByVal;
@@ -144,7 +144,7 @@
 	// (We know there currently are no other such cases active because
 	// they would hit the assert in FunctionPrologArgumentConversion::
 	// HandleByValArgument.)
-	if (!LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(Ftype, FTy, C.getCallingConv())) {
+	if (!LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(Ftype, FTy)) {
 	  C.EnterField(FNo, Ty);
 	  HandleArgument(getDeclaredType(Field), ScalarElts);
 	  C.ExitField();

Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=139189&r1=139188&r2=139189&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Tue Sep  6 16:53:06 2011
@@ -274,7 +274,7 @@
 // value should be passed by value, i.e. passing its address with the byval
 // attribute bit set. The default is false.
 #ifndef LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR
-#define LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(X, TY, CC)     \
+#define LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(X, TY) \
     false
 #endif
 

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=139189&r1=139188&r2=139189&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Sep  6 16:53:06 2011
@@ -437,7 +437,7 @@
 static bool isPassedByVal(tree type, Type *Ty,
                           std::vector<Type*> &ScalarArgs,
                           CallingConv::ID &CC) {
-  if (LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(type, Ty, CC))
+  if (LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(type, Ty))
     return true;
 
   std::vector<Type*> Args;



From grosbach at apple.com  Tue Sep  6 16:59:46 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 14:59:46 -0700
Subject: [llvm-commits] [llvm] r139157 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td
 lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/carry.ll
In-Reply-To: <2E1F03FA-67AE-4635-8266-9DA8CD94D20F@apple.com>
References: <20110906185221.2FCBE2A6C12C@llvm.org>
	<FF1F6AE9-14EB-464F-BD2B-C719715395B5@apple.com>
	<2E1F03FA-67AE-4635-8266-9DA8CD94D20F@apple.com>
Message-ID: <8D8A1819-A518-441A-9591-17936003EB79@apple.com>


On Sep 6, 2011, at 2:53 PM, Evan Cheng wrote:

> 
> On Sep 6, 2011, at 1:23 PM, Jim Grosbach wrote:
> 
>> Hi Evan,
>> 
>> In that case, can we get rid of the distinct ADDS definitions entirely and just use the ADD instructions w/ the cc_out operand set appropriately?
> 
> I'd like to but current TableGen technology doesn't allow it. See FIXME in code.
> 

Drat. :(

-j

> Evan
> 
>> 
>> -Jim
>> 
>> On Sep 6, 2011, at 11:52 AM, Evan Cheng wrote:
>> 
>>> Author: evancheng
>>> Date: Tue Sep  6 13:52:20 2011
>>> New Revision: 139157
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=139157&view=rev
>>> Log:
>>> Fix fall outs from my recent change on how carry bit is modeled during isel.
>>> Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
>>> Also fix isel hook to correctly set the optional operand.
>>> rdar://10073745
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>>  llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>>>  llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>>>  llvm/trunk/test/CodeGen/ARM/carry.ll
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=139157&r1=139156&r2=139157&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Sep  6 13:52:20 2011
>>> @@ -5708,7 +5708,7 @@
>>> // the optional operand to CPSR. Otherwise, remove the CPSR implicit def.
>>> const MCInstrDesc &MCID = MI->getDesc();
>>> if (Node->hasAnyUseOfValue(1)) {
>>> -    MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 2);
>>> +    MachineOperand &MO = MI->getOperand(MCID.getNumOperands() - 1);
>>>   MO.setReg(ARM::CPSR);
>>>   MO.setIsDef(true);
>>> } else {
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139157&r1=139156&r2=139157&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Sep  6 13:52:20 2011
>>> @@ -1037,8 +1037,8 @@
>>> 
>>> }
>>> 
>>> -/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except sets 's' bit.
>>> -let isCodeGenOnly = 1, Defs = [CPSR] in {
>>> +/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except it sets 's' bit by default.
>>> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
>>> multiclass AsI1_rbin_s_is<bits<4> opcod, string opc,
>>>                    InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
>>>                       PatFrag opnode, bit Commutable = 0> {
>>> @@ -1101,25 +1101,25 @@
>>> }
>>> }
>>> 
>>> -/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
>>> -/// instruction modifies the CPSR register.
>>> -let isCodeGenOnly = 1, Defs = [CPSR] in {
>>> -multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
>>> +/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
>>> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
>>> +multiclass AsI1_bin_s_irs<bits<4> opcod, string opc,
>>>                    InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
>>>                        PatFrag opnode, bit Commutable = 0> {
>>> -  def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
>>> +  let isReMaterializable = 1 in {
>>> +  def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
>>>              iii, opc, "\t$Rd, $Rn, $imm",
>>>              [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]> {
>>>   bits<4> Rd;
>>>   bits<4> Rn;
>>>   bits<12> imm;
>>>   let Inst{25} = 1;
>>> -    let Inst{20} = 1;
>>>   let Inst{19-16} = Rn;
>>>   let Inst{15-12} = Rd;
>>>   let Inst{11-0} = imm;
>>> }
>>> -  def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
>>> +  }
>>> +  def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
>>>              iir, opc, "\t$Rd, $Rn, $Rm",
>>>              [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
>>>   bits<4> Rd;
>>> @@ -1127,13 +1127,12 @@
>>>   bits<4> Rm;
>>>   let isCommutable = Commutable;
>>>   let Inst{25} = 0;
>>> -    let Inst{20} = 1;
>>>   let Inst{19-16} = Rn;
>>>   let Inst{15-12} = Rd;
>>>   let Inst{11-4} = 0b00000000;
>>>   let Inst{3-0} = Rm;
>>> }
>>> -  def rsi : AI1<opcod, (outs GPR:$Rd),
>>> +  def rsi : AsI1<opcod, (outs GPR:$Rd),
>>>              (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
>>>              iis, opc, "\t$Rd, $Rn, $shift",
>>>              [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
>>> @@ -1141,7 +1140,6 @@
>>>   bits<4> Rn;
>>>   bits<12> shift;
>>>   let Inst{25} = 0;
>>> -    let Inst{20} = 1;
>>>   let Inst{19-16} = Rn;
>>>   let Inst{15-12} = Rd;
>>>   let Inst{11-5} = shift{11-5};
>>> @@ -1149,7 +1147,7 @@
>>>   let Inst{3-0} = shift{3-0};
>>> }
>>> 
>>> -  def rsr : AI1<opcod, (outs GPR:$Rd),
>>> +  def rsr : AsI1<opcod, (outs GPR:$Rd),
>>>              (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
>>>              iis, opc, "\t$Rd, $Rn, $shift",
>>>              [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
>>> @@ -3136,10 +3134,12 @@
>>>                        BinOpFrag<(sub  node:$LHS, node:$RHS)>, "SUB">;
>>> 
>>> // ADD and SUB with 's' bit set.
>>> -defm ADDS : AI1_bin_s_irs<0b0100, "adds",
>>> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
>>> +// CPSR and the implicit def of CPSR is not needed.
>>> +defm ADDS : AsI1_bin_s_irs<0b0100, "add",
>>>                         IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>>>                         BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
>>> -defm SUBS : AI1_bin_s_irs<0b0010, "subs",
>>> +defm SUBS : AsI1_bin_s_irs<0b0010, "sub",
>>>                         IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>>>                         BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
>>> 
>>> @@ -3153,6 +3153,9 @@
>>> defm RSB  : AsI1_rbin_irs <0b0011, "rsb",
>>>                        IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>>>                        BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
>>> +
>>> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
>>> +// CPSR and the implicit def of CPSR is not needed.
>>> defm RSBS : AsI1_rbin_s_is<0b0011, "rsb",
>>>                        IIC_iALUi, IIC_iALUr, IIC_iALUsr,
>>>                        BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139157&r1=139156&r2=139157&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep  6 13:52:20 2011
>>> @@ -588,44 +588,41 @@
>>> 
>>> /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
>>> /// instruction modifies the CPSR register.
>>> -let isCodeGenOnly = 1, Defs = [CPSR] in {
>>> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
>>> multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
>>>                    InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
>>>                        PatFrag opnode, bit Commutable = 0> {
>>>  // shifted imm
>>> -   def ri : T2TwoRegImm<
>>> +   def ri : T2sTwoRegImm<
>>>               (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
>>> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
>>> +                opc, ".w\t$Rd, $Rn, $imm",
>>>               [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
>>>    let Inst{31-27} = 0b11110;
>>>    let Inst{25} = 0;
>>>    let Inst{24-21} = opcod;
>>> -     let Inst{20} = 1; // The S bit.
>>>    let Inst{15} = 0;
>>>  }
>>>  // register
>>> -   def rr : T2ThreeReg<
>>> +   def rr : T2sThreeReg<
>>>               (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
>>> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
>>> +                opc, ".w\t$Rd, $Rn, $Rm",
>>>               [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
>>>    let isCommutable = Commutable;
>>>    let Inst{31-27} = 0b11101;
>>>    let Inst{26-25} = 0b01;
>>>    let Inst{24-21} = opcod;
>>> -     let Inst{20} = 1; // The S bit.
>>>    let Inst{14-12} = 0b000; // imm3
>>>    let Inst{7-6} = 0b00; // imm2
>>>    let Inst{5-4} = 0b00; // type
>>>  }
>>>  // shifted register
>>> -   def rs : T2TwoRegShiftedReg<
>>> +   def rs : T2sTwoRegShiftedReg<
>>>               (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
>>> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
>>> +                opc, ".w\t$Rd, $Rn, $ShiftedRm",
>>>              [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
>>>    let Inst{31-27} = 0b11101;
>>>    let Inst{26-25} = 0b01;
>>>    let Inst{24-21} = opcod;
>>> -     let Inst{20} = 1; // The S bit.
>>>  }
>>> }
>>> }
>>> @@ -737,28 +734,26 @@
>>> 
>>> /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
>>> /// version is not needed since this is only for codegen.
>>> -let isCodeGenOnly = 1, Defs = [CPSR] in {
>>> +let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
>>> multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
>>>  // shifted imm
>>> -   def ri : T2TwoRegImm<
>>> +   def ri : T2sTwoRegImm<
>>>               (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
>>> -                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
>>> +                opc, ".w\t$Rd, $Rn, $imm",
>>>               [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
>>>    let Inst{31-27} = 0b11110;
>>>    let Inst{25} = 0;
>>>    let Inst{24-21} = opcod;
>>> -     let Inst{20} = 1; // The S bit.
>>>    let Inst{15} = 0;
>>>  }
>>>  // shifted register
>>> -   def rs : T2TwoRegShiftedReg<
>>> +   def rs : T2sTwoRegShiftedReg<
>>>               (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
>>> -                IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
>>> +                IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
>>>             [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
>>>    let Inst{31-27} = 0b11101;
>>>    let Inst{26-25} = 0b01;
>>>    let Inst{24-21} = opcod;
>>> -     let Inst{20} = 1; // The S bit.
>>>  }
>>> }
>>> }
>>> @@ -1699,6 +1694,8 @@
>>>                            BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
>>> 
>>> // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
>>> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
>>> +// CPSR and the implicit def of CPSR is not needed.
>>> defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
>>>                            IIC_iALUi, IIC_iALUr, IIC_iALUsi,
>>>                            BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
>>> @@ -1716,6 +1713,9 @@
>>> // RSB
>>> defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb",
>>>                            BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
>>> +
>>> +// FIXME: Eliminate them if we can write def : Pat patterns which defines
>>> +// CPSR and the implicit def of CPSR is not needed.
>>> defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
>>>                            BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
>>> 
>>> 
>>> Modified: llvm/trunk/test/CodeGen/ARM/carry.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/carry.ll?rev=139157&r1=139156&r2=139157&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/ARM/carry.ll (original)
>>> +++ llvm/trunk/test/CodeGen/ARM/carry.ll Tue Sep  6 13:52:20 2011
>>> @@ -35,3 +35,13 @@
>>> 	%dw = add i64 %ch, %bw
>>> 	ret i64 %dw
>>> }
>>> +
>>> +; rdar://10073745
>>> +define i64 @f4(i64 %x) nounwind readnone {
>>> +entry:
>>> +; CHECK: f4:
>>> +; CHECK: rsbs r
>>> +; CHECK: rsc r
>>> +  %0 = sub nsw i64 0, %x
>>> +  ret i64 %0
>>> +}
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 


From grosbach at apple.com  Tue Sep  6 17:06:40 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 22:06:40 -0000
Subject: [llvm-commits] [llvm] r139191 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110906220640.860052A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep  6 17:06:40 2011
New Revision: 139191

URL: http://llvm.org/viewvc/llvm-project?rev=139191&view=rev
Log:
Thumb2 parsing and encoding for DBG.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139191&r1=139190&r2=139191&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep  6 17:06:40 2011
@@ -3173,13 +3173,11 @@
 def t2SEV   : T2I_hint<0b00000100, "sev",   ".w">;
 
 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
-  let Inst{31-20} = 0xf3a;
-  let Inst{15-14} = 0b10;
-  let Inst{12} = 0;
-  let Inst{10-8} = 0b000;
-  let Inst{7-4} = 0b1111;
-
   bits<4> opt;
+  let Inst{31-20} = 0b111100111010;
+  let Inst{19-16} = 0b1111;
+  let Inst{15-8} = 0b10000000;
+  let Inst{7-4} = 0b1111;
   let Inst{3-0} = opt;
 }
 

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139191&r1=139190&r2=139191&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep  6 17:06:40 2011
@@ -357,6 +357,18 @@
 
 
 @------------------------------------------------------------------------------
+@ DBG
+ at ------------------------------------------------------------------------------
+        dbg #5
+        dbg #0
+        dbg #15
+
+@ CHECK: dbg	#5                      @ encoding: [0xaf,0xf3,0xf5,0x80]
+@ CHECK: dbg	#0                      @ encoding: [0xaf,0xf3,0xf0,0x80]
+@ CHECK: dbg	#15                     @ encoding: [0xaf,0xf3,0xff,0x80]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From nicholas at mxc.ca  Tue Sep  6 17:08:18 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 06 Sep 2011 22:08:18 -0000
Subject: [llvm-commits] [llvm] r139192 - in /llvm/trunk/test/CodeGen:
 ARM/2011-06-09-TailCallByVal.ll Mips/cprestore.ll Mips/largeimmprinting.ll
 Thumb/2011-05-11-DAGLegalizer.ll
Message-ID: <20110906220818.957422A6C12C@llvm.org>

Author: nicholas
Date: Tue Sep  6 17:08:18 2011
New Revision: 139192

URL: http://llvm.org/viewvc/llvm-project?rev=139192&view=rev
Log:
Disable these tests harder. They're XFAIL'd, but that means they still run, and
these tests all infinitely recurse, bringing my system down into swapping hell.

Modified:
    llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll
    llvm/trunk/test/CodeGen/Mips/cprestore.ll
    llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
    llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll

Modified: llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll?rev=139192&r1=139191&r2=139192&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll Tue Sep  6 17:08:18 2011
@@ -1,4 +1,5 @@
-; RUN: llc < %s -relocation-model=pic -mcpu=cortex-a8 -arm-tail-calls=1 | FileCheck %s
+; DISABLED: llc < %s -relocation-model=pic -mcpu=cortex-a8 -arm-tail-calls=1 | FileCheck %s
+; RUN: false
 
 ; byval is currently unsupported.
 ; XFAIL: *

Modified: llvm/trunk/test/CodeGen/Mips/cprestore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cprestore.ll?rev=139192&r1=139191&r2=139192&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cprestore.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cprestore.ll Tue Sep  6 17:08:18 2011
@@ -1,4 +1,5 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; DISABLED: llc -march=mipsel < %s | FileCheck %s
+; RUN: false
 
 ; byval is currently unsupported.
 ; XFAIL: *

Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=139192&r1=139191&r2=139192&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Tue Sep  6 17:08:18 2011
@@ -1,4 +1,5 @@
-; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+; DISABLED: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+; RUN: false
 
 ; byval is currently unsupported.
 ; XFAIL: *

Modified: llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll?rev=139192&r1=139191&r2=139192&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll Tue Sep  6 17:08:18 2011
@@ -1,4 +1,5 @@
-; RUN: llc -mtriple=thumbv6-apple-darwin < %s
+; DISABLED: llc -mtriple=thumbv6-apple-darwin < %s
+; RUN: false
 ; rdar://problem/9416774
 ; ModuleID = 'reduced.ll'
 



From grosbach at apple.com  Tue Sep  6 17:14:58 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 22:14:58 -0000
Subject: [llvm-commits] [llvm] r139193 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110906221458.B14782A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep  6 17:14:58 2011
New Revision: 139193

URL: http://llvm.org/viewvc/llvm-project?rev=139193&view=rev
Log:
Thumb2 parsing and encoding for DMB.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139193&r1=139192&r2=139193&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep  6 17:14:58 2011
@@ -3588,3 +3588,7 @@
 def : t2InstAlias<"tst${p} $Rn, $Rm",
                   (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
 
+// Memory barriers
+def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
+def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
+//def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139193&r1=139192&r2=139193&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep  6 17:14:58 2011
@@ -369,6 +369,38 @@
 
 
 @------------------------------------------------------------------------------
+@ DMB
+ at ------------------------------------------------------------------------------
+        dmb sy
+        dmb st
+        dmb sh
+        dmb ish
+        dmb shst
+        dmb ishst
+        dmb un
+        dmb nsh
+        dmb unst
+        dmb nshst
+        dmb osh
+        dmb oshst
+        dmb
+
+@ CHECK: dmb	sy                      @ encoding: [0xbf,0xf3,0x5f,0x8f]
+@ CHECK: dmb	st                      @ encoding: [0xbf,0xf3,0x5e,0x8f]
+@ CHECK: dmb	ish                     @ encoding: [0xbf,0xf3,0x5b,0x8f]
+@ CHECK: dmb	ish                     @ encoding: [0xbf,0xf3,0x5b,0x8f]
+@ CHECK: dmb	ishst                   @ encoding: [0xbf,0xf3,0x5a,0x8f]
+@ CHECK: dmb	ishst                   @ encoding: [0xbf,0xf3,0x5a,0x8f]
+@ CHECK: dmb	nsh                     @ encoding: [0xbf,0xf3,0x57,0x8f]
+@ CHECK: dmb	nsh                     @ encoding: [0xbf,0xf3,0x57,0x8f]
+@ CHECK: dmb	nshst                   @ encoding: [0xbf,0xf3,0x56,0x8f]
+@ CHECK: dmb	nshst                   @ encoding: [0xbf,0xf3,0x56,0x8f]
+@ CHECK: dmb	osh                     @ encoding: [0xbf,0xf3,0x53,0x8f]
+@ CHECK: dmb	oshst                   @ encoding: [0xbf,0xf3,0x52,0x8f]
+@ CHECK: dmb	sy                      @ encoding: [0xbf,0xf3,0x5f,0x8f]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From grosbach at apple.com  Tue Sep  6 17:19:40 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 22:19:40 -0000
Subject: [llvm-commits] [llvm] r139194 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110906221940.96E282A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep  6 17:19:40 2011
New Revision: 139194

URL: http://llvm.org/viewvc/llvm-project?rev=139194&view=rev
Log:
Thumb2 parsing and encoding for DSB.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139194&r1=139193&r2=139194&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep  6 17:19:40 2011
@@ -401,6 +401,38 @@
 
 
 @------------------------------------------------------------------------------
+@ DSB
+ at ------------------------------------------------------------------------------
+        dsb sy
+        dsb st
+        dsb sh
+        dsb ish
+        dsb shst
+        dsb ishst
+        dsb un
+        dsb nsh
+        dsb unst
+        dsb nshst
+        dsb osh
+        dsb oshst
+        dsb
+
+@ CHECK: dsb	sy                      @ encoding: [0xbf,0xf3,0x4f,0x8f]
+@ CHECK: dsb	st                      @ encoding: [0xbf,0xf3,0x4e,0x8f]
+@ CHECK: dsb	ish                     @ encoding: [0xbf,0xf3,0x4b,0x8f]
+@ CHECK: dsb	ish                     @ encoding: [0xbf,0xf3,0x4b,0x8f]
+@ CHECK: dsb	ishst                   @ encoding: [0xbf,0xf3,0x4a,0x8f]
+@ CHECK: dsb	ishst                   @ encoding: [0xbf,0xf3,0x4a,0x8f]
+@ CHECK: dsb	nsh                     @ encoding: [0xbf,0xf3,0x47,0x8f]
+@ CHECK: dsb	nsh                     @ encoding: [0xbf,0xf3,0x47,0x8f]
+@ CHECK: dsb	nshst                   @ encoding: [0xbf,0xf3,0x46,0x8f]
+@ CHECK: dsb	nshst                   @ encoding: [0xbf,0xf3,0x46,0x8f]
+@ CHECK: dsb	osh                     @ encoding: [0xbf,0xf3,0x43,0x8f]
+@ CHECK: dsb	oshst                   @ encoding: [0xbf,0xf3,0x42,0x8f]
+@ CHECK: dsb	sy                      @ encoding: [0xbf,0xf3,0x4f,0x8f]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From grosbach at apple.com  Tue Sep  6 17:25:04 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 15:25:04 -0700
Subject: [llvm-commits] [llvm] r139192 - in /llvm/trunk/test/CodeGen:
 ARM/2011-06-09-TailCallByVal.ll Mips/cprestore.ll Mips/largeimmprinting.ll
 Thumb/2011-05-11-DAGLegalizer.ll
In-Reply-To: <20110906220818.957422A6C12C@llvm.org>
References: <20110906220818.957422A6C12C@llvm.org>
Message-ID: <708E6E2A-5D2B-48DA-9B6D-4B40D91FF39F@apple.com>

That's bad. They should still compile and run OK, even w/o the byval stuff enabled. Mind filing a PR?

-Jim

On Sep 6, 2011, at 3:08 PM, Nick Lewycky wrote:

> Author: nicholas
> Date: Tue Sep  6 17:08:18 2011
> New Revision: 139192
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=139192&view=rev
> Log:
> Disable these tests harder. They're XFAIL'd, but that means they still run, and
> these tests all infinitely recurse, bringing my system down into swapping hell.
> 
> Modified:
>    llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll
>    llvm/trunk/test/CodeGen/Mips/cprestore.ll
>    llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
>    llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
> 
> Modified: llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll?rev=139192&r1=139191&r2=139192&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll Tue Sep  6 17:08:18 2011
> @@ -1,4 +1,5 @@
> -; RUN: llc < %s -relocation-model=pic -mcpu=cortex-a8 -arm-tail-calls=1 | FileCheck %s
> +; DISABLED: llc < %s -relocation-model=pic -mcpu=cortex-a8 -arm-tail-calls=1 | FileCheck %s
> +; RUN: false
> 
> ; byval is currently unsupported.
> ; XFAIL: *
> 
> Modified: llvm/trunk/test/CodeGen/Mips/cprestore.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cprestore.ll?rev=139192&r1=139191&r2=139192&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/cprestore.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/cprestore.ll Tue Sep  6 17:08:18 2011
> @@ -1,4 +1,5 @@
> -; RUN: llc -march=mipsel < %s | FileCheck %s
> +; DISABLED: llc -march=mipsel < %s | FileCheck %s
> +; RUN: false
> 
> ; byval is currently unsupported.
> ; XFAIL: *
> 
> Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=139192&r1=139191&r2=139192&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Tue Sep  6 17:08:18 2011
> @@ -1,4 +1,5 @@
> -; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
> +; DISABLED: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
> +; RUN: false
> 
> ; byval is currently unsupported.
> ; XFAIL: *
> 
> Modified: llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll?rev=139192&r1=139191&r2=139192&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll (original)
> +++ llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll Tue Sep  6 17:08:18 2011
> @@ -1,4 +1,5 @@
> -; RUN: llc -mtriple=thumbv6-apple-darwin < %s
> +; DISABLED: llc -mtriple=thumbv6-apple-darwin < %s
> +; RUN: false
> ; rdar://problem/9416774
> ; ModuleID = 'reduced.ll'
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From resistor at me.com  Tue Sep  6 17:27:54 2011
From: resistor at me.com (resistor at me.com)
Date: Tue, 06 Sep 2011 22:27:54 +0000 (GMT)
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS
	and	resolve	(safe) ambiguous instruction encodings
In-Reply-To: <F01D8B85CFF58440B2A13965FBA90CA473757133E2@GEORGE.Emea.Arm.com>
Message-ID: <2d7245b3-74a7-e6a6-f45d-ee682d3f7fb9@me.com>

Thanks James,

Patch 0 now applies for me, and looks fine in general, with the caveat that there's a dependent change in the clang driver (tools/clang/tools/driver/cc1as.cpp) that is needed as well. ?I'm not totally happy about having to expose the subtarget info to the decoder and printer, but after looking at the reference manual I don't really see a way around it.

Patch 1 has some issues. ?It looks like ARMDisassemblercpp needs to be updated to pass the subtarget info object to the individual decoder methods.

--Owen

On Sep 06, 2011, at 02:29 PM, James Molloy <James.Molloy at arm.com> wrote:

Hi Owen,

Sorry for taking so long getting back to you on this - make check has crashed my laptop twice now with what appears to be an errant llc process. I'm looking into that now (doesn't happen when running lit manually...)

Anyway, the patch attached applies to ToT now and has no conflicts. All targets build correctly and the regression tests pass.

Cheers,

James
________________________________________
From: Owen Anderson [resistor at me.com]
Sent: 06 September 2011 19:43
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve (safe) ambiguous instruction encodings

James,

Patch 0 seems to be missing some necessary changes to non-ARM targets to make LLVM build with it applied. I see a lot of errors of the form:

MipsMCTargetDesccpp:109:41: error: cannot initialize a parameter of type 'Target::MCInstPrinterCtorTy' (aka 'llvm::MCInstPrinter *(*)(const llvm::Target
&, unsigned int, const llvm::MCAsmInfo &, const llvm::MCSubtargetInfo &)') with an lvalue of type 'llvm::MCInstPrinter *(const llvm::Target &,
unsigned int, const llvm::MCAsmInfo &)'
createMipsMCInstPrinter);
^~~~~~~~~~~~~~~~~~~~~~~

--Owen

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:

> Hi,
>
> The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M series
> not allowing the correct mask names.
>
> The patch becomes difficult because:
> * There is no way to determine in the InstPrinter any subtarget specific
> features (such as "operating on an m-class core?").
> * There is currently no subtarget feature for "M-class core?"; the nearest is
> IsThumb2 && !HasARM.
> * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
> a way that makes them deterministically separable. This causes non-conflicting
> ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
> both code paths are emitted but only one will ever be hit.
>
> The solution is:
> * Add subtarget info to InstPrinter so it can determine what to do with the
> mask immediate.
> * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
> IsARClass == !IsMClass. This feature only has semantic sense on v6+
> architectures.
> * The conflicts occur because the FixedLenDecoderEmitter does not honour the
> Predicates field of instructions in the tablegen description. If the island
> checking also checked the AssemblerPredicates field (if defined), ambiguous
> instruction encodings that are disambiguated by predicates would (do) work fine.
>
> The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and MCDisassembler.
> They can use this (in patch #2) to determine what mask names to accept (primask?
> or cpsr_zxvf?)
>
> The second enhances FixedLenPredicateEncoder to emit predicate checks for
> instructions before it accepts an encoding - this allows ambiguous instructions
> to be disambiguated by the Predicates field in TableGen. This required changing
> llvm-mc to accept -mattr, and tests to set the correct features they rely upon.
>
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
> is created.**
>
> The third patch adds a new predicate "IsMClass" along with its counterpart
> "IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
> Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
> encodings respectively. It also fixes mask printing for MRS/MSR in the
> ARMMCInstPrinter and ARMMCAsmParser.
>
> Testcases added with the final patch.
>
> Comments? Is it OK?
>
> Cheers,
>
> James
>
> [N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout myself
> after review]
> <patch0-add-sti-to-instprinter.patch><patch1-modify-fixedlendecoderemitter.patch><patch2-fix-msr-mrs.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiucedu/mailman/listinfo/llvm-commits




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From nlewycky at google.com  Tue Sep  6 17:31:31 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Tue, 6 Sep 2011 15:31:31 -0700
Subject: [llvm-commits] [llvm] r139192 - in /llvm/trunk/test/CodeGen:
 ARM/2011-06-09-TailCallByVal.ll Mips/cprestore.ll Mips/largeimmprinting.ll
 Thumb/2011-05-11-DAGLegalizer.ll
In-Reply-To: <708E6E2A-5D2B-48DA-9B6D-4B40D91FF39F@apple.com>
References: <20110906220818.957422A6C12C@llvm.org>
	<708E6E2A-5D2B-48DA-9B6D-4B40D91FF39F@apple.com>
Message-ID: <CADbEz-jO4Ro=fQRv4R2Q3JX_VdQUc3dH5=Jo1fE3SxesgJX4Vg@mail.gmail.com>

On 6 September 2011 15:25, Jim Grosbach <grosbach at apple.com> wrote:

> That's bad. They should still compile and run OK, even w/o the byval stuff
> enabled. Mind filing a PR?
>

PR10876.


>
> -Jim
>
> On Sep 6, 2011, at 3:08 PM, Nick Lewycky wrote:
>
> > Author: nicholas
> > Date: Tue Sep  6 17:08:18 2011
> > New Revision: 139192
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=139192&view=rev
> > Log:
> > Disable these tests harder. They're XFAIL'd, but that means they still
> run, and
> > these tests all infinitely recurse, bringing my system down into swapping
> hell.
> >
> > Modified:
> >    llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll
> >    llvm/trunk/test/CodeGen/Mips/cprestore.ll
> >    llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
> >    llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
>
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From grosbach at apple.com  Tue Sep  6 17:44:50 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 22:44:50 -0000
Subject: [llvm-commits] [llvm] r139199 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110906224450.DB9262A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep  6 17:44:50 2011
New Revision: 139199

URL: http://llvm.org/viewvc/llvm-project?rev=139199&view=rev
Log:
Thumb2 parsing and encoding for EOR.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139199&r1=139198&r2=139199&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep  6 17:44:50 2011
@@ -433,6 +433,26 @@
 
 
 @------------------------------------------------------------------------------
+@ EOR
+ at ------------------------------------------------------------------------------
+        eor r4, r5, #0xf000
+        eor r4, r5, r6
+        eor r4, r5, r6, lsl #5
+        eor r4, r5, r6, lsr #5
+        eor r4, r5, r6, lsr #5
+        eor r4, r5, r6, asr #5
+        eor r4, r5, r6, ror #5
+
+@ CHECK: eor	r4, r5, #61440          @ encoding: [0x85,0xf4,0x70,0x44]
+@ CHECK: eor.w	r4, r5, r6              @ encoding: [0x85,0xea,0x06,0x04]
+@ CHECK: eor.w	r4, r5, r6, lsl #5      @ encoding: [0x85,0xea,0x46,0x14]
+@ CHECK: eor.w	r4, r5, r6, lsr #5      @ encoding: [0x85,0xea,0x56,0x14]
+@ CHECK: eor.w	r4, r5, r6, lsr #5      @ encoding: [0x85,0xea,0x56,0x14]
+@ CHECK: eor.w	r4, r5, r6, asr #5      @ encoding: [0x85,0xea,0x66,0x14]
+@ CHECK: eor.w	r4, r5, r6, ror #5      @ encoding: [0x85,0xea,0x76,0x14]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From grosbach at apple.com  Tue Sep  6 17:53:27 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 22:53:27 -0000
Subject: [llvm-commits] [llvm] r139200 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110906225327.BB0DA2A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep  6 17:53:27 2011
New Revision: 139200

URL: http://llvm.org/viewvc/llvm-project?rev=139200&view=rev
Log:
Thumb2 parsing and encoding for ISB.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139200&r1=139199&r2=139200&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep  6 17:53:27 2011
@@ -2794,20 +2794,19 @@
 }
 
 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
-                  "dsb", "\t$opt",
-                  [/* For disassembly only; pattern left blank */]>,
+                  "dsb", "\t$opt", []>,
                   Requires<[IsThumb, HasDB]> {
   bits<4> opt;
   let Inst{31-4} = 0xf3bf8f4;
   let Inst{3-0} = opt;
 }
 
-// ISB has only full system option -- for disassembly only
-def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
-                  [/* For disassembly only; pattern left blank */]>,
-                  Requires<[IsThumb2, HasV7]> {
+def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
+                  "isb", "\t$opt",
+                  []>, Requires<[IsThumb2, HasV7]> {
+  bits<4> opt;
   let Inst{31-4} = 0xf3bf8f6;
-  let Inst{3-0} = 0b1111;
+  let Inst{3-0} = opt;
 }
 
 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
@@ -3591,4 +3590,4 @@
 // Memory barriers
 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
-//def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
+def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139200&r1=139199&r2=139200&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep  6 17:53:27 2011
@@ -453,6 +453,16 @@
 
 
 @------------------------------------------------------------------------------
+@ ISB
+ at ------------------------------------------------------------------------------
+        isb sy
+        isb
+
+@ CHECK: isb	sy                      @ encoding: [0xbf,0xf3,0x6f,0x8f]
+@ CHECK: isb	sy                      @ encoding: [0xbf,0xf3,0x6f,0x8f]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From eli.friedman at gmail.com  Tue Sep  6 18:06:23 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 6 Sep 2011 16:06:23 -0700
Subject: [llvm-commits] [llvm] r139200 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
In-Reply-To: <20110906225327.BB0DA2A6C12C@llvm.org>
References: <20110906225327.BB0DA2A6C12C@llvm.org>
Message-ID: <CAJdarcEA2yzCh1OmSd__OKS=KSRjtUcm7q2i54Ca-1n92mQ01g@mail.gmail.com>

On Tue, Sep 6, 2011 at 3:53 PM, Jim Grosbach <grosbach at apple.com> wrote:
> Author: grosbach
> Date: Tue Sep ?6 17:53:27 2011
> New Revision: 139200
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139200&view=rev
> Log:
> Thumb2 parsing and encoding for ISB.
>
> Modified:
> ? ?llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> ? ?llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139200&r1=139199&r2=139200&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep ?6 17:53:27 2011
> @@ -2794,20 +2794,19 @@
> ?}
>
> ?def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
> - ? ? ? ? ? ? ? ? ?"dsb", "\t$opt",
> - ? ? ? ? ? ? ? ? ?[/* For disassembly only; pattern left blank */]>,
> + ? ? ? ? ? ? ? ? ?"dsb", "\t$opt", []>,
> ? ? ? ? ? ? ? ? ? Requires<[IsThumb, HasDB]> {
> ? bits<4> opt;
> ? let Inst{31-4} = 0xf3bf8f4;
> ? let Inst{3-0} = opt;
> ?}
>
> -// ISB has only full system option -- for disassembly only
> -def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
> - ? ? ? ? ? ? ? ? ?[/* For disassembly only; pattern left blank */]>,
> - ? ? ? ? ? ? ? ? ?Requires<[IsThumb2, HasV7]> {
> +def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
> + ? ? ? ? ? ? ? ? ?"isb", "\t$opt",
> + ? ? ? ? ? ? ? ? ?[]>, Requires<[IsThumb2, HasV7]> {

Should this be HasDB?

-Eli

> + ?bits<4> opt;
> ? let Inst{31-4} = 0xf3bf8f6;
> - ?let Inst{3-0} = 0b1111;
> + ?let Inst{3-0} = opt;
> ?}
>
> ?class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
> @@ -3591,4 +3590,4 @@
> ?// Memory barriers
> ?def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
> ?def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
> -//def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
> +def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
>
> Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139200&r1=139199&r2=139200&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
> +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep ?6 17:53:27 2011
> @@ -453,6 +453,16 @@
>
>
> ?@------------------------------------------------------------------------------
> +@ ISB
> + at ------------------------------------------------------------------------------
> + ? ? ? ?isb sy
> + ? ? ? ?isb
> +
> +@ CHECK: isb ? sy ? ? ? ? ? ? ? ? ? ? ?@ encoding: [0xbf,0xf3,0x6f,0x8f]
> +@ CHECK: isb ? sy ? ? ? ? ? ? ? ? ? ? ?@ encoding: [0xbf,0xf3,0x6f,0x8f]
> +
> +
> + at ------------------------------------------------------------------------------
> ?@ IT
> ?@------------------------------------------------------------------------------
> ?@ Test encodings of a few full IT blocks, not just the IT instruction
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From grosbach at apple.com  Tue Sep  6 18:09:19 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 23:09:19 -0000
Subject: [llvm-commits] [llvm] r139202 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
Message-ID: <20110906230919.BF5F02A6C12C@llvm.org>

Author: grosbach
Date: Tue Sep  6 18:09:19 2011
New Revision: 139202

URL: http://llvm.org/viewvc/llvm-project?rev=139202&view=rev
Log:
ISB is HasDB, not just HasV7.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139202&r1=139201&r2=139202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep  6 18:09:19 2011
@@ -2803,7 +2803,7 @@
 
 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
                   "isb", "\t$opt",
-                  []>, Requires<[IsThumb2, HasV7]> {
+                  []>, Requires<[IsThumb2, HasDB]> {
   bits<4> opt;
   let Inst{31-4} = 0xf3bf8f6;
   let Inst{3-0} = opt;



From grosbach at apple.com  Tue Sep  6 18:10:45 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 06 Sep 2011 16:10:45 -0700
Subject: [llvm-commits] [llvm] r139200 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
In-Reply-To: <CAJdarcEA2yzCh1OmSd__OKS=KSRjtUcm7q2i54Ca-1n92mQ01g@mail.gmail.com>
References: <20110906225327.BB0DA2A6C12C@llvm.org>
	<CAJdarcEA2yzCh1OmSd__OKS=KSRjtUcm7q2i54Ca-1n92mQ01g@mail.gmail.com>
Message-ID: <1C66ED33-E4FE-4F46-9680-A16882B483B8@apple.com>

Yup. Fixed r139202.

On Sep 6, 2011, at 4:06 PM, Eli Friedman wrote:

> On Tue, Sep 6, 2011 at 3:53 PM, Jim Grosbach <grosbach at apple.com> wrote:
>> Author: grosbach
>> Date: Tue Sep  6 17:53:27 2011
>> New Revision: 139200
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=139200&view=rev
>> Log:
>> Thumb2 parsing and encoding for ISB.
>> 
>> Modified:
>>    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>>    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139200&r1=139199&r2=139200&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep  6 17:53:27 2011
>> @@ -2794,20 +2794,19 @@
>>  }
>> 
>>  def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
>> -                  "dsb", "\t$opt",
>> -                  [/* For disassembly only; pattern left blank */]>,
>> +                  "dsb", "\t$opt", []>,
>>                   Requires<[IsThumb, HasDB]> {
>>   bits<4> opt;
>>   let Inst{31-4} = 0xf3bf8f4;
>>   let Inst{3-0} = opt;
>>  }
>> 
>> -// ISB has only full system option -- for disassembly only
>> -def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
>> -                  [/* For disassembly only; pattern left blank */]>,
>> -                  Requires<[IsThumb2, HasV7]> {
>> +def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
>> +                  "isb", "\t$opt",
>> +                  []>, Requires<[IsThumb2, HasV7]> {
> 
> Should this be HasDB?
> 
> -Eli
> 
>> +  bits<4> opt;
>>   let Inst{31-4} = 0xf3bf8f6;
>> -  let Inst{3-0} = 0b1111;
>> +  let Inst{3-0} = opt;
>>  }
>> 
>>  class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
>> @@ -3591,4 +3590,4 @@
>>  // Memory barriers
>>  def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
>>  def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
>> -//def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
>> +def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
>> 
>> Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139200&r1=139199&r2=139200&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
>> +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep  6 17:53:27 2011
>> @@ -453,6 +453,16 @@
>> 
>> 
>>  @------------------------------------------------------------------------------
>> +@ ISB
>> + at ------------------------------------------------------------------------------
>> +        isb sy
>> +        isb
>> +
>> +@ CHECK: isb   sy                      @ encoding: [0xbf,0xf3,0x6f,0x8f]
>> +@ CHECK: isb   sy                      @ encoding: [0xbf,0xf3,0x6f,0x8f]
>> +
>> +
>> + at ------------------------------------------------------------------------------
>>  @ IT
>>  @------------------------------------------------------------------------------
>>  @ Test encodings of a few full IT blocks, not just the IT instruction
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 


From resistor at mac.com  Tue Sep  6 18:33:25 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 06 Sep 2011 23:33:25 -0000
Subject: [llvm-commits] [llvm] r139204 - in /llvm/trunk:
 lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/memset_pattern.ll
Message-ID: <20110906233325.90A302A6C12C@llvm.org>

Author: resistor
Date: Tue Sep  6 18:33:25 2011
New Revision: 139204

URL: http://llvm.org/viewvc/llvm-project?rev=139204&view=rev
Log:
Teach BasicAA about the aliasing properties of memset_pattern16.
Fixes PR10872 and <rdar://problem/10065079>.

Added:
    llvm/trunk/test/Analysis/BasicAA/memset_pattern.ll
Modified:
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=139204&r1=139203&r2=139204&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Sep  6 18:33:25 2011
@@ -30,6 +30,7 @@
 #include "llvm/Analysis/InstructionSimplify.h"
 #include "llvm/Analysis/ValueTracking.h"
 #include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetLibraryInfo.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -468,6 +469,7 @@
 
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
       AU.addRequired<AliasAnalysis>();
+      AU.addRequired<TargetLibraryInfo>();
     }
 
     virtual AliasResult alias(const Location &LocA,
@@ -550,10 +552,15 @@
 
 // Register this pass...
 char BasicAliasAnalysis::ID = 0;
-INITIALIZE_AG_PASS(BasicAliasAnalysis, AliasAnalysis, "basicaa",
+INITIALIZE_AG_PASS_BEGIN(BasicAliasAnalysis, AliasAnalysis, "basicaa",
+                   "Basic Alias Analysis (stateless AA impl)",
+                   false, true, false)
+INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfo)
+INITIALIZE_AG_PASS_END(BasicAliasAnalysis, AliasAnalysis, "basicaa",
                    "Basic Alias Analysis (stateless AA impl)",
                    false, true, false)
 
+
 ImmutablePass *llvm::createBasicAliasAnalysisPass() {
   return new BasicAliasAnalysis();
 }
@@ -717,6 +724,7 @@
       return NoModRef;
   }
 
+  const TargetLibraryInfo &TLI = getAnalysis<TargetLibraryInfo>();
   ModRefResult Min = ModRef;
 
   // Finally, handle specific knowledge of intrinsics.
@@ -819,6 +827,37 @@
     }
     }
 
+  // We can bound the aliasing properties of memset_pattern16 just as we can
+  // for memcpy/memset.  This is particularly important because the 
+  // LoopIdiomRecognizer likes to turn loops into calls to memset_pattern16
+  // whenever possible.
+  else if (TLI.has(LibFunc::memset_pattern16) &&
+           CS.getCalledFunction() &&
+           CS.getCalledFunction()->getName() == "memset_pattern16") {
+    const Function *MS = CS.getCalledFunction();
+    FunctionType *MemsetType = MS->getFunctionType();
+    if (!MemsetType->isVarArg() && MemsetType->getNumParams() == 3 &&
+        isa<PointerType>(MemsetType->getParamType(0)) &&
+        isa<PointerType>(MemsetType->getParamType(1)) &&
+        isa<IntegerType>(MemsetType->getParamType(2))) {
+      uint64_t Len = UnknownSize;
+      if (const ConstantInt *LenCI = dyn_cast<ConstantInt>(CS.getArgument(2)))
+        Len = LenCI->getZExtValue();
+      const Value *Dest = CS.getArgument(0);
+      const Value *Src = CS.getArgument(1);
+      // If it can't overlap the source dest, then it doesn't modref the loc.
+      if (isNoAlias(Location(Dest, Len), Loc)) {
+        if (isNoAlias(Location(Src, 2), Loc))
+          return NoModRef;
+        // If it can't overlap the dest, then worst case it reads the loc.
+        Min = Ref;
+      } else if (isNoAlias(Location(Src, 2), Loc)) {
+        // If it can't overlap the source, then worst case it mutates the loc.
+        Min = Mod;
+      }
+    }
+  }
+
   // The AliasAnalysis base class has some smarts, lets use them.
   return ModRefResult(AliasAnalysis::getModRefInfo(CS, Loc) & Min);
 }

Added: llvm/trunk/test/Analysis/BasicAA/memset_pattern.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/memset_pattern.ll?rev=139204&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/BasicAA/memset_pattern.ll (added)
+++ llvm/trunk/test/Analysis/BasicAA/memset_pattern.ll Tue Sep  6 18:33:25 2011
@@ -0,0 +1,21 @@
+; RUN: opt -S -basicaa -gvn < %s | FileCheck %s
+; PR10872
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.7"
+
+ at z = internal global i32 0, align 4
+ at y = internal global i32 0, align 4
+ at x = internal constant i32 0, align 4
+
+; CHECK: @test
+define i32 @test() nounwind uwtable ssp {
+entry:
+  store i32 1, i32* @z
+  tail call void @memset_pattern16(i8* bitcast (i32* @y to i8*), i8* bitcast (i32* @x to i8*), i64 4) nounwind
+; CHECK-NOT: load
+  %l = load i32* @z
+; CHECK: ret i32 1
+  ret i32 %l
+}
+
+declare void @memset_pattern16(i8*, i8*, i64)



From eli.friedman at gmail.com  Tue Sep  6 18:39:51 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 6 Sep 2011 16:39:51 -0700
Subject: [llvm-commits] [llvm] r139204 - in /llvm/trunk:
 lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/memset_pattern.ll
In-Reply-To: <20110906233325.90A302A6C12C@llvm.org>
References: <20110906233325.90A302A6C12C@llvm.org>
Message-ID: <CAJdarcEDoaJdD2MFhC8Di8nd5xTffTxZ50gcU9WZcF9W2Eo36g@mail.gmail.com>

On Tue, Sep 6, 2011 at 4:33 PM, Owen Anderson <resistor at mac.com> wrote:
> Author: resistor
> Date: Tue Sep ?6 18:33:25 2011
> New Revision: 139204
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139204&view=rev
> Log:
> Teach BasicAA about the aliasing properties of memset_pattern16.
> Fixes PR10872 and <rdar://problem/10065079>.
>
> Added:
> ? ?llvm/trunk/test/Analysis/BasicAA/memset_pattern.ll
> Modified:
> ? ?llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
>
> Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=139204&r1=139203&r2=139204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
> +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Sep ?6 18:33:25 2011
> @@ -30,6 +30,7 @@
> ?#include "llvm/Analysis/InstructionSimplify.h"
> ?#include "llvm/Analysis/ValueTracking.h"
> ?#include "llvm/Target/TargetData.h"
> +#include "llvm/Target/TargetLibraryInfo.h"
> ?#include "llvm/ADT/SmallPtrSet.h"
> ?#include "llvm/ADT/SmallVector.h"
> ?#include "llvm/Support/ErrorHandling.h"
> @@ -468,6 +469,7 @@
>
> ? ? virtual void getAnalysisUsage(AnalysisUsage &AU) const {
> ? ? ? AU.addRequired<AliasAnalysis>();
> + ? ? ?AU.addRequired<TargetLibraryInfo>();
> ? ? }
>
> ? ? virtual AliasResult alias(const Location &LocA,
> @@ -550,10 +552,15 @@
>
> ?// Register this pass...
> ?char BasicAliasAnalysis::ID = 0;
> -INITIALIZE_AG_PASS(BasicAliasAnalysis, AliasAnalysis, "basicaa",
> +INITIALIZE_AG_PASS_BEGIN(BasicAliasAnalysis, AliasAnalysis, "basicaa",
> + ? ? ? ? ? ? ? ? ? "Basic Alias Analysis (stateless AA impl)",
> + ? ? ? ? ? ? ? ? ? false, true, false)
> +INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfo)
> +INITIALIZE_AG_PASS_END(BasicAliasAnalysis, AliasAnalysis, "basicaa",
> ? ? ? ? ? ? ? ? ? ?"Basic Alias Analysis (stateless AA impl)",
> ? ? ? ? ? ? ? ? ? ?false, true, false)
>
> +
> ?ImmutablePass *llvm::createBasicAliasAnalysisPass() {
> ? return new BasicAliasAnalysis();
> ?}
> @@ -717,6 +724,7 @@
> ? ? ? return NoModRef;
> ? }
>
> + ?const TargetLibraryInfo &TLI = getAnalysis<TargetLibraryInfo>();
> ? ModRefResult Min = ModRef;
>
> ? // Finally, handle specific knowledge of intrinsics.
> @@ -819,6 +827,37 @@
> ? ? }
> ? ? }
>
> + ?// We can bound the aliasing properties of memset_pattern16 just as we can
> + ?// for memcpy/memset. ?This is particularly important because the
> + ?// LoopIdiomRecognizer likes to turn loops into calls to memset_pattern16
> + ?// whenever possible.
> + ?else if (TLI.has(LibFunc::memset_pattern16) &&
> + ? ? ? ? ? CS.getCalledFunction() &&
> + ? ? ? ? ? CS.getCalledFunction()->getName() == "memset_pattern16") {
> + ? ?const Function *MS = CS.getCalledFunction();
> + ? ?FunctionType *MemsetType = MS->getFunctionType();
> + ? ?if (!MemsetType->isVarArg() && MemsetType->getNumParams() == 3 &&
> + ? ? ? ?isa<PointerType>(MemsetType->getParamType(0)) &&
> + ? ? ? ?isa<PointerType>(MemsetType->getParamType(1)) &&
> + ? ? ? ?isa<IntegerType>(MemsetType->getParamType(2))) {
> + ? ? ?uint64_t Len = UnknownSize;
> + ? ? ?if (const ConstantInt *LenCI = dyn_cast<ConstantInt>(CS.getArgument(2)))
> + ? ? ? ?Len = LenCI->getZExtValue();
> + ? ? ?const Value *Dest = CS.getArgument(0);
> + ? ? ?const Value *Src = CS.getArgument(1);
> + ? ? ?// If it can't overlap the source dest, then it doesn't modref the loc.
> + ? ? ?if (isNoAlias(Location(Dest, Len), Loc)) {
> + ? ? ? ?if (isNoAlias(Location(Src, 2), Loc))
> + ? ? ? ? ?return NoModRef;
> + ? ? ? ?// If it can't overlap the dest, then worst case it reads the loc.
> + ? ? ? ?Min = Ref;
> + ? ? ?} else if (isNoAlias(Location(Src, 2), Loc)) {
> + ? ? ? ?// If it can't overlap the source, then worst case it mutates the loc.
> + ? ? ? ?Min = Mod;

Where does the magic constant 2 come from?

-Eli


From resistor at mac.com  Tue Sep  6 18:43:26 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 06 Sep 2011 23:43:26 -0000
Subject: [llvm-commits] [llvm] r139205 -
	/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
Message-ID: <20110906234326.C3EFF2A6C12C@llvm.org>

Author: resistor
Date: Tue Sep  6 18:43:26 2011
New Revision: 139205

URL: http://llvm.org/viewvc/llvm-project?rev=139205&view=rev
Log:
memset_pattern16 uses a 16 BYTE pattern, not a 16 BIT pattern.  Add comments to that effect.

Modified:
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=139205&r1=139204&r2=139205&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Sep  6 18:43:26 2011
@@ -847,11 +847,13 @@
       const Value *Src = CS.getArgument(1);
       // If it can't overlap the source dest, then it doesn't modref the loc.
       if (isNoAlias(Location(Dest, Len), Loc)) {
-        if (isNoAlias(Location(Src, 2), Loc))
+        // Always reads 16 bytes of the source.
+        if (isNoAlias(Location(Src, 16), Loc))
           return NoModRef;
         // If it can't overlap the dest, then worst case it reads the loc.
         Min = Ref;
-      } else if (isNoAlias(Location(Src, 2), Loc)) {
+      // Always reads 16 bytes of the source.
+      } else if (isNoAlias(Location(Src, 16), Loc)) {
         // If it can't overlap the source, then worst case it mutates the loc.
         Min = Mod;
       }



From resistor at mac.com  Tue Sep  6 18:46:05 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 06 Sep 2011 16:46:05 -0700
Subject: [llvm-commits] [llvm] r139204 - in /llvm/trunk:
 lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/memset_pattern.ll
In-Reply-To: <CAJdarcEDoaJdD2MFhC8Di8nd5xTffTxZ50gcU9WZcF9W2Eo36g@mail.gmail.com>
References: <20110906233325.90A302A6C12C@llvm.org>
	<CAJdarcEDoaJdD2MFhC8Di8nd5xTffTxZ50gcU9WZcF9W2Eo36g@mail.gmail.com>
Message-ID: <93F30C1A-439E-4986-81B2-605B2E13EC0C@mac.com>

On Sep 6, 2011, at 4:39 PM, Eli Friedman wrote:
> Where does the magic constant 2 come from?

memset_pattern16 reads a fixed-sized 16 byte pattern from the source operand, which is what determines the magic constant.  Though apparently it should be 16 rather than 2 (bytes vs bits).  Fixed now.

--Owen

From isanbard at gmail.com  Tue Sep  6 18:47:14 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 06 Sep 2011 23:47:14 -0000
Subject: [llvm-commits] [llvm] r139206 -
	/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
Message-ID: <20110906234714.7B8FC2A6C12C@llvm.org>

Author: void
Date: Tue Sep  6 18:47:14 2011
New Revision: 139206

URL: http://llvm.org/viewvc/llvm-project?rev=139206&view=rev
Log:
Reenable compact unwind by default. However, also emit the old version of unwind
information for older linkers.

Modified:
    llvm/trunk/lib/Target/X86/X86FrameLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=139206&r1=139205&r2=139206&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Sep  6 18:47:14 2011
@@ -35,13 +35,6 @@
 // FIXME: completely move here.
 extern cl::opt<bool> ForceStackAlign;
 
-// FIXME: Remove once linker support is available. The feature exists only on
-// Darwin at the moment.
-static cl::opt<bool>
-GenerateCompactUnwind("gen-compact-unwind",
-                      cl::desc("Generate compact unwind encoding"),
-                      cl::Hidden);
-
 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
   return !MF.getFrameInfo()->hasVarSizedObjects();
 }
@@ -908,7 +901,7 @@
   }
 
   // Darwin 10.7 and greater has support for compact unwind encoding.
-  if (GenerateCompactUnwind && STI.getTargetTriple().isMacOSX() &&
+  if (STI.getTargetTriple().isMacOSX() &&
       !STI.getTargetTriple().isMacOSXVersionLT(10, 7))
     MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF));
 }



From pdox at google.com  Tue Sep  6 18:57:24 2011
From: pdox at google.com (David Meyer)
Date: Tue, 6 Sep 2011 16:57:24 -0700
Subject: [llvm-commits] [PATCH] Clean up RegOp2MemOp tables in
	X86InstrInfo.cpp
In-Reply-To: <6CF9FE3C-ABC0-4BB8-89A8-A27A45803A7A@2pi.dk>
References: <CAAU48JKT3LE1gCzvWtv5Me4AsQLTbGa+boxFyZsjuKOP+8BanQ@mail.gmail.com>
	<6CF9FE3C-ABC0-4BB8-89A8-A27A45803A7A@2pi.dk>
Message-ID: <CAAU48JJ-55X_sfnhvB1uudKbTPdhvue9P4jVL5B2meojxL9Y_g@mail.gmail.com>

Hi Jakob,

I added a brief comment to each. New patch attached.

Thanks,
 - pdox

On Tue, Sep 6, 2011 at 10:06 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>
> On Sep 5, 2011, at 9:40 PM, David Meyer wrote:
>
>> Hello!
>>
>> This patch:
>>
>> * Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
>> single field (Flags), which is a bitwise OR of items from the TB_*
>> enum. This makes it easier to add new information in the future.
>>
>> * Gives every static array an equivalent layout: { RegOp, MemOp, Flags }
>>
>> * Adds a helper function, AddTableEntry, to avoid duplication of the
>> insertion code.
>>
>> * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.
>>
>> * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
>> it prevents addition of the Reg->Mem entry. (This is going to be used
>> by Native Client, in the next CL).
>
> Looks good, but please add an explanation of the TB_INDEX* and TB_ALIGN* enums.
>
> /jakob
>
>
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From dpatel at apple.com  Tue Sep  6 19:07:59 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 07 Sep 2011 00:07:59 -0000
Subject: [llvm-commits] [llvm] r139208 - in /llvm/trunk:
 lib/CodeGen/MachineSink.cpp test/CodeGen/X86/MachineSink-DbgValue.ll
Message-ID: <20110907000759.1F60A2A6C12C@llvm.org>

Author: dpatel
Date: Tue Sep  6 19:07:58 2011
New Revision: 139208

URL: http://llvm.org/viewvc/llvm-project?rev=139208&view=rev
Log:
While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor.

Added:
    llvm/trunk/test/CodeGen/X86/MachineSink-DbgValue.ll
Modified:
    llvm/trunk/lib/CodeGen/MachineSink.cpp

Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=139208&r1=139207&r2=139208&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Tue Sep  6 19:07:58 2011
@@ -382,6 +382,25 @@
   return MI->isInsertSubreg() || MI->isSubregToReg() || MI->isRegSequence();
 }
 
+/// collectDebgValues - Scan instructions following MI and collect any 
+/// matching DBG_VALUEs.
+static void collectDebugValues(MachineInstr *MI, 
+                               SmallVector<MachineInstr *, 2> & DbgValues) {
+  DbgValues.clear();
+  if (!MI->getOperand(0).isReg())
+    return;
+
+  MachineBasicBlock::iterator DI = MI; ++DI;
+  for (MachineBasicBlock::iterator DE = MI->getParent()->end();
+       DI != DE; ++DI) {
+    if (!DI->isDebugValue())
+      return;
+    if (DI->getOperand(0).isReg() &&
+        DI->getOperand(0).getReg() == MI->getOperand(0).getReg())
+      DbgValues.push_back(DI);
+  }
+}
+
 /// SinkInstruction - Determine whether it is safe to sink the specified machine
 /// instruction out of its current block into a successor.
 bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
@@ -598,10 +617,22 @@
   while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI())
     ++InsertPos;
 
+  // collect matching debug values.
+  SmallVector<MachineInstr *, 2> DbgValuesToSink;
+  collectDebugValues(MI, DbgValuesToSink);
+
   // Move the instruction.
   SuccToSinkTo->splice(InsertPos, ParentBlock, MI,
                        ++MachineBasicBlock::iterator(MI));
 
+  // Move debug values.
+  for (SmallVector<MachineInstr *, 2>::iterator DBI = DbgValuesToSink.begin(),
+         DBE = DbgValuesToSink.end(); DBI != DBE; ++DBI) {
+    MachineInstr *DbgMI = *DBI;
+    SuccToSinkTo->splice(InsertPos, ParentBlock,  DbgMI,
+                         ++MachineBasicBlock::iterator(DbgMI));
+  }
+
   // Conservatively, clear any kill flags, since it's possible that they are no
   // longer correct.
   MI->clearKillInfo();

Added: llvm/trunk/test/CodeGen/X86/MachineSink-DbgValue.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/MachineSink-DbgValue.ll?rev=139208&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/MachineSink-DbgValue.ll (added)
+++ llvm/trunk/test/CodeGen/X86/MachineSink-DbgValue.ll Tue Sep  6 19:07:58 2011
@@ -0,0 +1,49 @@
+; RUN: llc < %s | FileCheck %s
+; Should sink matching DBG_VALUEs also.
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-macosx10.7.0"
+
+define i32 @foo(i32 %i, i32* nocapture %c) nounwind uwtable readonly ssp {
+  tail call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !6), !dbg !12
+  %ab = load i32* %c, align 1, !dbg !14
+  tail call void @llvm.dbg.value(metadata !{i32* %c}, i64 0, metadata !7), !dbg !13
+  tail call void @llvm.dbg.value(metadata !{i32 %ab}, i64 0, metadata !10), !dbg !14
+  %cd = icmp eq i32 %i, 42, !dbg !15
+  br i1 %cd, label %bb1, label %bb2, !dbg !15
+
+bb1:                                     ; preds = %0
+;CHECK: DEBUG_VALUE: a
+;CHECK-NEXT: 	.loc	1 5 5
+;CHECK-NEXT:	addl
+  %gh = add nsw i32 %ab, 2, !dbg !16
+  br label %bb2, !dbg !16
+
+bb2:
+  %.0 = phi i32 [ %gh, %bb1 ], [ 0, %0 ]
+  ret i32 %.0, !dbg !17
+}
+
+declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
+
+!llvm.dbg.cu = !{!0}
+!llvm.dbg.sp = !{!1}
+!llvm.dbg.lv.foo = !{!6, !7, !10}
+
+!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"a.c", metadata !"/private/tmp", metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @foo, null, null} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 589865, metadata !"a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!4 = metadata !{metadata !5}
+!5 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 590081, metadata !1, metadata !"i", metadata !2, i32 16777218, metadata !5, i32 0} ; [ DW_TAG_arg_variable ]
+!7 = metadata !{i32 590081, metadata !1, metadata !"c", metadata !2, i32 33554434, metadata !8, i32 0} ; [ DW_TAG_arg_variable ]
+!8 = metadata !{i32 589839, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ]
+!9 = metadata !{i32 589860, metadata !0, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!10 = metadata !{i32 590080, metadata !11, metadata !"a", metadata !2, i32 3, metadata !9, i32 0} ; [ DW_TAG_auto_variable ]
+!11 = metadata !{i32 589835, metadata !1, i32 2, i32 25, metadata !2, i32 0} ; [ DW_TAG_lexical_block ]
+!12 = metadata !{i32 2, i32 13, metadata !1, null}
+!13 = metadata !{i32 2, i32 22, metadata !1, null}
+!14 = metadata !{i32 3, i32 14, metadata !11, null}
+!15 = metadata !{i32 4, i32 3, metadata !11, null}
+!16 = metadata !{i32 5, i32 5, metadata !11, null}
+!17 = metadata !{i32 7, i32 1, metadata !11, null}



From nlewycky at google.com  Tue Sep  6 19:13:44 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Tue, 6 Sep 2011 17:13:44 -0700
Subject: [llvm-commits] [llvm] r139204 - in /llvm/trunk:
 lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/memset_pattern.ll
In-Reply-To: <20110906233325.90A302A6C12C@llvm.org>
References: <20110906233325.90A302A6C12C@llvm.org>
Message-ID: <CADbEz-iPrXqnVMVb-7q9irFQGupzBDwzAsbhzMiPWJ2vAYmAZw@mail.gmail.com>

On 6 September 2011 16:33, Owen Anderson <resistor at mac.com> wrote:

> Author: resistor
> Date: Tue Sep  6 18:33:25 2011
> New Revision: 139204
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139204&view=rev
> Log:
> Teach BasicAA about the aliasing properties of memset_pattern16.
> Fixes PR10872 and <rdar://problem/10065079>.
>
> Added:
>    llvm/trunk/test/Analysis/BasicAA/memset_pattern.ll
> Modified:
>    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
>

Any particular reason not to use a LibCallAA for this?
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From isanbard at gmail.com  Tue Sep  6 19:50:54 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 07 Sep 2011 00:50:54 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r139212 - in /llvm-gcc-4.2/trunk/gcc:
 llvm-convert.cpp llvm-internal.h
Message-ID: <20110907005055.11EAA2A6C12C@llvm.org>

Author: void
Date: Tue Sep  6 19:50:54 2011
New Revision: 139212

URL: http://llvm.org/viewvc/llvm-project?rev=139212&view=rev
Log:
Reapply r138984 with changes suggested by Duncan:

Update to use the new EH scheme.

This uses the landingpad instruction in place of the llvm.eh.exception and
llvm.eh.selector calls. The values returned by the instruction are always
stored. The 'resume' instruction replaces the direct call to _Unwind_Resume.

This is based partially off of dragonegg's EH implementation.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
    llvm-gcc-4.2/trunk/gcc/llvm-internal.h

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=139212&r1=139211&r2=139212&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Sep  6 19:50:54 2011
@@ -188,7 +188,6 @@
   GreatestAlignment = TheTarget->getFrameLowering()->getStackAlignment();
   SeenVLA = NULL;
 
-  CatchAll = 0;
   ExceptionValue = 0;
   ExceptionSelectorValue = 0;
   FuncEHException = 0;
@@ -2164,25 +2163,6 @@
                                               Intrinsic::eh_selector);
   FuncEHGetTypeID = Intrinsic::getDeclaration(TheModule,
                                               Intrinsic::eh_typeid_for);
-
-  CatchAll = TheModule->getGlobalVariable("llvm.eh.catch.all.value");
-  if (!CatchAll && lang_eh_catch_all) {
-    Constant *Init = 0;
-    tree catch_all_type = lang_eh_catch_all();
-    if (catch_all_type == NULL_TREE)
-      // Use a C++ style null catch-all object.
-      Init = Constant::getNullValue(Type::getInt8PtrTy(Context));
-    else
-      // This language has a type that catches all others.
-      Init = cast<Constant>(Emit(catch_all_type, 0));
-
-    CatchAll = new GlobalVariable(*TheModule, Init->getType(), true,
-                                  GlobalVariable::LinkOnceAnyLinkage,
-                                  Init, "llvm.eh.catch.all.value");
-    CatchAll->setUnnamedAddr(true);
-    CatchAll->setSection("llvm.metadata");
-    AttributeUsedGlobals.insert(CatchAll);
-  }
 }
 
 /// getPostPad - Return the post landing pad for the given exception handling
@@ -2205,9 +2185,10 @@
 
 /// EmitLandingPads - Emit EH landing pads.
 void TreeToLLVM::EmitLandingPads() {
-  std::vector<Value*> Args;
   std::vector<struct eh_region *> Handlers;
 
+  Type *UnwindDataTy = StructType::get(Builder.getInt8PtrTy(),
+                                       Builder.getInt32Ty(), NULL);
   for (unsigned i = 1; i < LandingPads.size(); ++i) {
     BasicBlock *LandingPad = LandingPads[i];
 
@@ -2225,11 +2206,19 @@
     // Fetch and store the exception selector.
 
     // The exception and the personality function.
-    Args.push_back(Builder.CreateLoad(ExceptionValue, "eh_ptr"));
     assert(llvm_eh_personality_libfunc
            && "no exception handling personality function!");
-    Args.push_back(BitCastToType(DECL_LLVM(llvm_eh_personality_libfunc),
-                                 Type::getInt8PtrTy(Context)));
+    LandingPadInst *LPadInst =
+      Builder.CreateLandingPad(UnwindDataTy,
+                               BitCastToType(DECL_LLVM(llvm_eh_personality_libfunc),
+                                             Type::getInt8PtrTy(Context)),
+                               0, "exc");
+
+    Value *ExcPtr = Builder.CreateExtractValue(LPadInst, 0, "exc_ptr");
+    Builder.CreateStore(ExcPtr, ExceptionValue);
+
+    Value *Select = Builder.CreateExtractValue(LPadInst, 1, "filter");
+    Builder.CreateStore(Select, ExceptionSelectorValue);
 
     // Add selections for each handler.
     foreach_reachable_handler(i, false, AddHandler, &Handlers);
@@ -2246,31 +2235,34 @@
 
       int RegionKind = classify_eh_handler(region);
       if (RegionKind < 0) {
-        // Filter - note the length.
+        // Filter.
         tree TypeList = get_eh_type_list(region);
-        unsigned Length = list_length(TypeList);
-        Args.reserve(Args.size() + Length + 1);
-        Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), Length + 1));
 
         // Add the type infos.
+        std::vector<Constant*> TypeInfos;
         for (; TypeList; TypeList = TREE_CHAIN(TypeList)) {
           tree TType = lookup_type_for_runtime(TREE_VALUE(TypeList));
-          Args.push_back(Emit(TType, 0));
+          TypeInfos.push_back(cast<Constant>(Emit(TType, 0)));
         }
+
+        // Add the list of typeinfos as a filter clause.
+        ArrayType *FilterTy = ArrayType::get(Builder.getInt8PtrTy(),
+                                             TypeInfos.size());
+        LPadInst->addClause(ConstantArray::get(FilterTy, TypeInfos));
       } else if (RegionKind > 0) {
         // Catch.
         tree TypeList = get_eh_type_list(region);
 
         if (!TypeList) {
           // Catch-all - push the catch-all object.
-          assert(CatchAll && "Language did not define lang_eh_catch_all?");
-          Args.push_back(CatchAll);
+          LPadInst->
+            addClause(Constant::getNullValue(Type::getInt8PtrTy(Context)));
           HasCatchAll = true;
         } else {
           // Add the type infos.
           for (; TypeList; TypeList = TREE_CHAIN(TypeList)) {
             tree TType = lookup_type_for_runtime(TREE_VALUE(TypeList));
-            Args.push_back(Emit(TType, 0));
+            LPadInst->addClause(Emit(TType, 0));
           }
         }
       } else {
@@ -2279,32 +2271,14 @@
       }
     }
 
-    if (can_throw_external_1(i, false)) {
-      if (HasCleanup) {
-        if (Args.size() == 2 || USING_SJLJ_EXCEPTIONS || !lang_eh_catch_all) {
-          // Insert the sentinal indicating that this is a cleanup-only
-          // selector.  It may also be the representation of a catch-all for
-          // some languages.
-          Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), 0));
-        } else if (!HasCatchAll) {
-          // Some exceptions from this region may not be caught by any handler.
-          // Since invokes are required to branch to the unwind label no matter
-          // what exception is being unwound, append a catch-all.
-          assert(CatchAll && "Language did not define lang_eh_catch_all?");
-          Args.push_back(CatchAll);
-        }
-      }
-    }
+    if (can_throw_external_1(i, false) && HasCleanup)
+      LPadInst->setCleanup(true);
 
-    // Emit the selector call.
-    Value *Select = Builder.CreateCall(FuncEHSelector, Args, "eh_select");
-    Builder.CreateStore(Select, ExceptionSelectorValue);
     // Branch to the post landing pad for the first reachable handler.
     assert(!Handlers.empty() && "Landing pad but no handler?");
     Builder.CreateBr(getPostPad(get_eh_region_number(*Handlers.begin())));
 
     Handlers.clear();
-    Args.clear();
   }
 }
 
@@ -2424,29 +2398,19 @@
 
 /// EmitUnwindBlock - Emit the lazily created EH unwind block.
 void TreeToLLVM::EmitUnwindBlock() {
-  if (UnwindBB) {
-    CreateExceptionValues();
-    EmitBlock(UnwindBB);
-    // Fetch and store exception handler.
-    Value *Arg = Builder.CreateLoad(ExceptionValue, "eh_ptr");
-    assert(llvm_unwind_resume_libfunc && "no unwind resume function!");
-
-    // As we're emitting a naked call (not an expression) going through
-    // EmitCallOf would be wasteful and incorrect. Manually adjust
-    // the calling convention for this call here if necessary.
-#ifdef TARGET_ADJUST_LLVM_CC
-    tree fntype = TREE_TYPE(llvm_unwind_resume_libfunc);
-    CallingConv::ID CallingConvention = CallingConv::C;
+  if (!UnwindBB) return;
 
-    TARGET_ADJUST_LLVM_CC(CallingConvention, fntype);
-    CallInst *Call = Builder.CreateCall(DECL_LLVM(llvm_unwind_resume_libfunc),
-                                        Arg);
-    Call->setCallingConv(CallingConvention);
-#else
-    Builder.CreateCall(DECL_LLVM(llvm_unwind_resume_libfunc), Arg);
-#endif
-    Builder.CreateUnreachable();
-  }
+  CreateExceptionValues();
+  EmitBlock(UnwindBB);
+
+  Value *ExcPtr = Builder.CreateLoad(ExceptionValue, "eh_ptr");
+  Value *Filter = Builder.CreateLoad(ExceptionSelectorValue, "eh_sel");
+  Type *UnwindDataTy = StructType::get(Builder.getInt8PtrTy(),
+                                       Builder.getInt32Ty(), NULL);
+  Value *UnwindData = UndefValue::get(UnwindDataTy);
+  UnwindData = Builder.CreateInsertValue(UnwindData, ExcPtr, 0, "exc_ptr");
+  UnwindData = Builder.CreateInsertValue(UnwindData, Filter, 1, "filter");
+  Builder.CreateResume(UnwindData);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=139212&r1=139211&r2=139212&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Tue Sep  6 19:50:54 2011
@@ -317,9 +317,6 @@
   /// PostPads - The post landing pad for a given EH region.
   IndexedMap<BasicBlock *> PostPads;
 
-  /// CatchAll - Language specific catch-all object.
-  GlobalVariable *CatchAll;
-
   /// ExceptionValue - Is the local to receive the current exception.
   Value *ExceptionValue;
 



From STPWORLD at yandex.ru  Tue Sep  6 18:44:31 2011
From: STPWORLD at yandex.ru (Stepan Dyatkovskiy)
Date: Wed, 07 Sep 2011 03:44:31 +0400
Subject: [llvm-commits] [LLVM,
	llvm-mc] bugfix for bug #10869: Unclear error for files without
	newline at the end of file (ARM, x86).
Message-ID: <919681315352671@web61.yandex.ru>

Hello everyone,

Please find attached a patch for review.
It fixes bug #10869 and adds a regression test for it.

Best regards,
Stepan.
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From joerg at bec.de  Tue Sep  6 21:12:03 2011
From: joerg at bec.de (Joerg Sonnenberger)
Date: Wed, 07 Sep 2011 02:12:03 -0000
Subject: [llvm-commits] [llvm] r139220 -
	/llvm/trunk/utils/TableGen/TableGen.cpp
Message-ID: <20110907021203.B62BF2A6C12C@llvm.org>

Author: joerg
Date: Tue Sep  6 21:12:03 2011
New Revision: 139220

URL: http://llvm.org/viewvc/llvm-project?rev=139220&view=rev
Log:
Dependency should be on the output file name, not the dependency file
name.

Modified:
    llvm/trunk/utils/TableGen/TableGen.cpp

Modified: llvm/trunk/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=139220&r1=139219&r2=139220&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TableGen.cpp (original)
+++ llvm/trunk/utils/TableGen/TableGen.cpp Tue Sep  6 21:12:03 2011
@@ -242,7 +242,7 @@
           << ":" << Error << "\n";
         return 1;
       }
-      DepOut.os() << DependFilename << ":";
+      DepOut.os() << OutputFilename << ":";
       const std::vector<std::string> &Dependencies = Parser.getDependencies();
       for (std::vector<std::string>::const_iterator I = Dependencies.begin(),
                                                           E = Dependencies.end();



From eli.friedman at gmail.com  Tue Sep  6 21:23:42 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 07 Sep 2011 02:23:42 -0000
Subject: [llvm-commits] [llvm] r139221 - in /llvm/trunk:
 include/llvm/CodeGen/SelectionDAGNodes.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 test/CodeGen/ARM/atomic-load-store.ll
Message-ID: <20110907022342.D37A62A6C12C@llvm.org>

Author: efriedma
Date: Tue Sep  6 21:23:42 2011
New Revision: 139221

URL: http://llvm.org/viewvc/llvm-project?rev=139221&view=rev
Log:
Relax the MemOperands on atomics a bit.  Fixes -verify-machineinstrs failures for atomic laod/store on ARM.

(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.)


Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=139221&r1=139220&r2=139221&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Sep  6 21:23:42 2011
@@ -998,8 +998,10 @@
     assert(getOrdering() == Ordering && "Ordering encoding error!");
     assert(getSynchScope() == SynchScope && "Synch-scope encoding error!");
 
-    assert(readMem() && "Atomic MachineMemOperand is not a load!");
-    assert(writeMem() && "Atomic MachineMemOperand is not a store!");
+    assert((readMem() || getOrdering() <= Monotonic) &&
+           "Acquire/Release MachineMemOperand must be a load!");
+    assert((writeMem() || getOrdering() <= Monotonic) &&
+           "Acquire/Release MachineMemOperand must be a store!");
   }
 
 public:

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=139221&r1=139220&r2=139221&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep  6 21:23:42 2011
@@ -3840,6 +3840,8 @@
   unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
 
   // For now, atomics are considered to be volatile always.
+  // FIXME: Volatile isn't really correct; we should keep track of atomic
+  // orderings in the memoperand.
   Flags |= MachineMemOperand::MOVolatile;
 
   MachineMemOperand *MMO =
@@ -3889,9 +3891,16 @@
     Alignment = getEVTAlignment(MemVT);
 
   MachineFunction &MF = getMachineFunction();
-  unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
+  // A monotonic store does not load; a release store "loads" in the sense
+  // that other stores cannot be sunk past it.
+  // (An atomicrmw obviously both loads and stores.)
+  unsigned Flags = MachineMemOperand::MOStore;
+  if (Opcode != ISD::ATOMIC_STORE || Ordering > Monotonic)
+    Flags |= MachineMemOperand::MOLoad;
 
   // For now, atomics are considered to be volatile always.
+  // FIXME: Volatile isn't really correct; we should keep track of atomic
+  // orderings in the memoperand.
   Flags |= MachineMemOperand::MOVolatile;
 
   MachineMemOperand *MMO =
@@ -3954,9 +3963,15 @@
     Alignment = getEVTAlignment(MemVT);
 
   MachineFunction &MF = getMachineFunction();
-  unsigned Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
+  // A monotonic load does not store; an acquire load "stores" in the sense
+  // that other loads cannot be hoisted past it.
+  unsigned Flags = MachineMemOperand::MOLoad;
+  if (Ordering > Monotonic)
+    Flags |= MachineMemOperand::MOStore;
 
   // For now, atomics are considered to be volatile always.
+  // FIXME: Volatile isn't really correct; we should keep track of atomic
+  // orderings in the memoperand.
   Flags |= MachineMemOperand::MOVolatile;
 
   MachineMemOperand *MMO =

Modified: llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll?rev=139221&r1=139220&r2=139221&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/atomic-load-store.ll Tue Sep  6 21:23:42 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s -check-prefix=ARM
+; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=ARM
 ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=ARM
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s -check-prefix=THUMBTWO
 ; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE



From james.molloy at arm.com  Wed Sep  7 01:58:12 2011
From: james.molloy at arm.com (James Molloy)
Date: Wed, 7 Sep 2011 07:58:12 +0100
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS
	and	resolve	(safe) ambiguous instruction encodings
In-Reply-To: <2d7245b3-74a7-e6a6-f45d-ee682d3f7fb9@me.com>
References: <F01D8B85CFF58440B2A13965FBA90CA473757133E2@GEORGE.Emea.Arm.com>
	<2d7245b3-74a7-e6a6-f45d-ee682d3f7fb9@me.com>
Message-ID: <000101cc6d2b$8329d580$897d8080$@molloy@arm.com>

Hi Owen,

 

Given the invasive nature of the patches, I didn't honestly expect them to apply
cleanly to ToT for more than a day or two after the patch was created. I was
going to deal with the merge fallout myself ideally after review, but I'll
rebase to ToT today and send updated patches for you.

 

Thanks for letting me know about the clang driver - I'll ensure that's updated
too.

 

Cheers,

 

James

 

From: resistor at me.com [mailto:resistor at me.com] 
Sent: 06 September 2011 23:28
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve
(safe) ambiguous instruction encodings

 

Thanks James,

 

Patch 0 now applies for me, and looks fine in general, with the caveat that
there's a dependent change in the clang driver
(tools/clang/tools/driver/cc1as.cpp) that is needed as well.  I'm not totally
happy about having to expose the subtarget info to the decoder and printer, but
after looking at the reference manual I don't really see a way around it.

 

Patch 1 has some issues.  It looks like ARMDisassembler.cpp needs to be updated
to pass the subtarget info object to the individual decoder methods.

 

--Owen

On Sep 06, 2011, at 02:29 PM, James Molloy <James.Molloy at arm.com> wrote:

Hi Owen,

Sorry for taking so long getting back to you on this - make check has crashed my
laptop twice now with what appears to be an errant llc process. I'm looking into
that now (doesn't happen when running lit manually...)

Anyway, the patch attached applies to ToT now and has no conflicts. All targets
build correctly and the regression tests pass.

Cheers,

James
________________________________________
From: Owen Anderson [resistor at me.com]
Sent: 06 September 2011 19:43
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve
(safe) ambiguous instruction encodings

James,

Patch 0 seems to be missing some necessary changes to non-ARM targets to make
LLVM build with it applied. I see a lot of errors of the form:

MipsMCTargetDesc.cpp:109:41: error: cannot initialize a parameter of type
'Target::MCInstPrinterCtorTy' (aka 'llvm::MCInstPrinter *(*)(const llvm::Target
&, unsigned int, const llvm::MCAsmInfo &, const llvm::MCSubtargetInfo &)') with
an lvalue of type 'llvm::MCInstPrinter *(const llvm::Target &,
unsigned int, const llvm::MCAsmInfo &)'
createMipsMCInstPrinter);
^~~~~~~~~~~~~~~~~~~~~~~

--Owen

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:

> Hi,
>
> The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M
series
> not allowing the correct mask names.
>
> The patch becomes difficult because:
> * There is no way to determine in the InstPrinter any subtarget specific
> features (such as "operating on an m-class core?").
> * There is currently no subtarget feature for "M-class core?"; the nearest is
> IsThumb2 && !HasARM.
> * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
> a way that makes them deterministically separable. This causes non-conflicting
> ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
> both code paths are emitted but only one will ever be hit
>
> The solution is:
> * Add subtarget info to InstPrinter so it can determine what to do with the
> mask immediate.
> * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
> IsARClass == !IsMClass. This feature only has semantic sense on v6+
> architectures.
> * The conflicts occur because the FixedLenDecoderEmitter does not honour the
> Predicates field of instructions in the tablegen description. If the island
> checking also checked the AssemblerPredicates field (if defined), ambiguous
> instruction encodings that are disambiguated by predicates would (do) work
fine.
>
> The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and
MCDisassembler.
> They can use this (in patch #2) to determine what mask names to accept
(primask?
> or cpsr_zxvf?)
>
> The second enhances FixedLenPredicateEncoder to emit predicate checks for
> instructions before it accepts an encoding - this allows ambiguous
instructions
> to be disambiguated by the Predicates field in TableGen This required changing
> llvm-mc to accept -mattr, and tests to set the correct features they rely
upon.
>
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were
being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2
STC/STC2
> is created.**
>
> The third patch adds a new predicate "IsMClass" along with its counterpart
> "IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
> Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
> encodings respectively. It also fixes mask printing for MRS/MSR in the
> ARMMCInstPrinter and ARMMCAsmParser.
>
> Testcases added with the final patch.
>
> Comments? Is it OK?
>
> Cheers,
>
> James
>
> [N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout
myself
> after review]
>
<patch0-add-sti-to-instprinter.patch><patch1-modify-fixedlendecoderemitter.patch
><patch2-fix-msr-mrs.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




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From baldrick at free.fr  Wed Sep  7 04:21:38 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 07 Sep 2011 09:21:38 -0000
Subject: [llvm-commits] [llvm] r139229 -
 /llvm/trunk/test/Transforms/InstCombine/2011-09-03-Trampoline.ll
Message-ID: <20110907092139.0681F2A6C12C@llvm.org>

Author: baldrick
Date: Wed Sep  7 04:21:38 2011
New Revision: 139229

URL: http://llvm.org/viewvc/llvm-project?rev=139229&view=rev
Log:
Forgot to add this trampoline testcase.

Added:
    llvm/trunk/test/Transforms/InstCombine/2011-09-03-Trampoline.ll

Added: llvm/trunk/test/Transforms/InstCombine/2011-09-03-Trampoline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2011-09-03-Trampoline.ll?rev=139229&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/2011-09-03-Trampoline.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/2011-09-03-Trampoline.ll Wed Sep  7 04:21:38 2011
@@ -0,0 +1,87 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+declare void @llvm.init.trampoline(i8*, i8*, i8*)
+declare i8* @llvm.adjust.trampoline(i8*)
+declare i32 @f(i8 * nest, i32)
+
+; Most common case
+define i32 @test0(i32 %n) {
+  %alloca = alloca [10 x i8], align 16
+  %gep = getelementptr [10 x i8]* %alloca, i32 0, i32 0
+  call void @llvm.init.trampoline(i8* %gep, i8* bitcast (i32 (i8*, i32)* @f to i8*),
+                                  i8* null)
+  %tramp = call i8* @llvm.adjust.trampoline(i8* %gep)
+  %function = bitcast i8* %tramp to i32(i32)*
+  %ret = call i32 %function(i32 %n)
+  ret i32 %ret
+
+; CHECK: define i32 @test0(i32 %n) {
+; CHECK: %ret = call i32 @f(i8* nest null, i32 %n)
+}
+
+define i32 @test1(i32 %n, i8* %trampmem) {
+  call void @llvm.init.trampoline(i8* %trampmem,
+                                  i8* bitcast (i32 (i8*, i32)* @f to i8*),
+                                  i8* null)
+  %tramp = call i8* @llvm.adjust.trampoline(i8* %trampmem)
+  %function = bitcast i8* %tramp to i32(i32)*
+  %ret = call i32 %function(i32 %n)
+  ret i32 %ret
+; CHECK: define i32 @test1(i32 %n, i8* %trampmem) {
+; CHECK: %ret = call i32 @f(i8* nest null, i32 %n)
+}
+
+define i32 @test2(i32 %n, i8* %trampmem) {
+  %tramp = call i8* @llvm.adjust.trampoline(i8* %trampmem)
+  %functiona = bitcast i8* %tramp to i32(i32)*
+  %ret = call i32 %functiona(i32 %n)
+  ret i32 %ret
+; CHECK: define i32 @test2(i32 %n, i8* %trampmem) {
+; CHECK: %ret = call i32 %functiona(i32 %n)
+}
+
+define i32 @test3(i32 %n, i8* %trampmem) {
+  call void @llvm.init.trampoline(i8* %trampmem,
+                                  i8* bitcast (i32 (i8*, i32)* @f to i8*),
+                                  i8* null)
+
+; CHECK: define i32 @test3(i32 %n, i8* %trampmem) {
+; CHECK: %ret0 = call i32 @f(i8* nest null, i32 %n)
+  %tramp0 = call i8* @llvm.adjust.trampoline(i8* %trampmem)
+  %function0 = bitcast i8* %tramp0 to i32(i32)*
+  %ret0 = call i32 %function0(i32 %n)
+
+  ;; Not optimized since previous call could be writing.
+  %tramp1 = call i8* @llvm.adjust.trampoline(i8* %trampmem)
+  %function1 = bitcast i8* %tramp1 to i32(i32)*
+  %ret1 = call i32 %function1(i32 %n)
+; CHECK: %ret1 = call i32 %function1(i32 %n)
+
+  ret i32 %ret1
+}
+
+define i32 @test4(i32 %n) {
+  %alloca = alloca [10 x i8], align 16
+  %gep = getelementptr [10 x i8]* %alloca, i32 0, i32 0
+  call void @llvm.init.trampoline(i8* %gep, i8* bitcast (i32 (i8*, i32)* @f to i8*),
+                                  i8* null)
+
+  %tramp0 = call i8* @llvm.adjust.trampoline(i8* %gep)
+  %function0 = bitcast i8* %tramp0 to i32(i32)*
+  %ret0 = call i32 %function0(i32 %n)
+
+  %tramp1 = call i8* @llvm.adjust.trampoline(i8* %gep)
+  %function1 = bitcast i8* %tramp0 to i32(i32)*
+  %ret1 = call i32 %function1(i32 %n)
+
+  %tramp2 = call i8* @llvm.adjust.trampoline(i8* %gep)
+  %function2 = bitcast i8* %tramp2 to i32(i32)*
+  %ret2 = call i32 %function2(i32 %n)
+
+  ret i32 %ret2
+
+; CHECK: define i32 @test4(i32 %n) {
+; CHECK: %ret0 = call i32 @f(i8* nest null, i32 %n)
+; CHECK: %ret1 = call i32 @f(i8* nest null, i32 %n)
+; CHECK: %ret2 = call i32 @f(i8* nest null, i32 %n)
+}



From baldrick at free.fr  Wed Sep  7 05:05:15 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 07 Sep 2011 10:05:15 -0000
Subject: [llvm-commits] [llvm] r139230 -
	/llvm/trunk/test/CodeGen/X86/2011-08-23-Trampoline.ll
Message-ID: <20110907100515.1C96D2A6C12C@llvm.org>

Author: baldrick
Date: Wed Sep  7 05:05:14 2011
New Revision: 139230

URL: http://llvm.org/viewvc/llvm-project?rev=139230&view=rev
Log:
Another forgotten trampoline testcase.

Added:
    llvm/trunk/test/CodeGen/X86/2011-08-23-Trampoline.ll

Added: llvm/trunk/test/CodeGen/X86/2011-08-23-Trampoline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-08-23-Trampoline.ll?rev=139230&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-08-23-Trampoline.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2011-08-23-Trampoline.ll Wed Sep  7 05:05:14 2011
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
+
+	%struct.FRAME.gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets = type { i32, i32, void (i32, i32)*, i8 (i32, i32)* }
+
+define fastcc i32 @gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets.5146(i64 %table.0.0, i64 %table.0.1, i32 %last, i32 %pos) {
+entry:
+	call void @llvm.init.trampoline( i8* null, i8* bitcast (void (%struct.FRAME.gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets*, i32, i32)* @gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets__move.5177 to i8*), i8* null )		; <i8*> [#uses=0]
+        %tramp22 = call i8* @llvm.adjust.trampoline( i8* null)
+	unreachable
+}
+
+declare void @gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets__move.5177(%struct.FRAME.gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets* nest , i32, i32) nounwind 
+
+declare void @llvm.init.trampoline(i8*, i8*, i8*) nounwind 
+declare i8* @llvm.adjust.trampoline(i8*) nounwind 



From baldrick at free.fr  Wed Sep  7 06:08:31 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 07 Sep 2011 11:08:31 -0000
Subject: [llvm-commits] [dragonegg] r139231 -
	/dragonegg/trunk/src/Backend.cpp
Message-ID: <20110907110831.183AE2A6C12C@llvm.org>

Author: baldrick
Date: Wed Sep  7 06:08:30 2011
New Revision: 139231

URL: http://llvm.org/viewvc/llvm-project?rev=139231&view=rev
Log:
Enable an experimental codegen feature that legalizes vectors
of i1 by promoting the element type.

Modified:
    dragonegg/trunk/src/Backend.cpp

Modified: dragonegg/trunk/src/Backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=139231&r1=139230&r2=139231&view=diff
==============================================================================
--- dragonegg/trunk/src/Backend.cpp (original)
+++ dragonegg/trunk/src/Backend.cpp Wed Sep  7 06:08:30 2011
@@ -326,6 +326,8 @@
   if (flag_split_stack)
     Args.push_back("--segmented-stacks");
 #endif
+  // Enable the experimental vector type legalization by element promotion code.
+  Args.push_back("--promote-elements");
 
   // If there are options that should be passed through to the LLVM backend
   // directly from the command line, do so now.  This is mainly for debugging



From dmalyshev at accesssoftek.com  Wed Sep  7 08:09:03 2011
From: dmalyshev at accesssoftek.com (Danil Malyshev)
Date: Wed, 7 Sep 2011 06:09:03 -0700
Subject: [llvm-commits] ObjectFile RelocationRef
Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE17F9B4DBFE@mail.accesssoftek.com>

Hello everyone,


Please find attached the patch for review. It adds relocations to the ObjectFile.

By the way, ObjectFile as it is now implements only a reader. If it is not intended to modify MemoryBuffer content then how about using const MemoryBuffer instead?


Regards,
Danil
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From echristo at apple.com  Wed Sep  7 10:22:18 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 07 Sep 2011 08:22:18 -0700
Subject: [llvm-commits] ObjectFile RelocationRef
In-Reply-To: <6AE1604EE3EC5F4296C096518C6B77EE17F9B4DBFE@mail.accesssoftek.com>
References: <6AE1604EE3EC5F4296C096518C6B77EE17F9B4DBFE@mail.accesssoftek.com>
Message-ID: <9F94CB44-2002-4081-A5EA-604D7585AED3@apple.com>


On Sep 7, 2011, at 6:09 AM, Danil Malyshev wrote:

>  If it is not intended to modify MemoryBuffer content 

Eventually I believe the goal is to read and write :)

-eric
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From grosbach at apple.com  Wed Sep  7 11:06:04 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 16:06:04 -0000
Subject: [llvm-commits] [llvm] r139232 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20110907160604.BC2172A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 11:06:04 2011
New Revision: 139232

URL: http://llvm.org/viewvc/llvm-project?rev=139232&view=rev
Log:
Better diagnostic location information for mnemonic suffices.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139232&r1=139231&r2=139232&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Sep  7 11:06:04 2011
@@ -3233,8 +3233,10 @@
     // For now, we're only parsing Thumb1 (for the most part), so
     // just ignore ".n" qualifiers. We'll use them to restrict
     // matching when we do Thumb2.
-    if (ExtraToken != ".n")
-      Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
+    if (ExtraToken != ".n") {
+      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
+      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
+    }
   }
 
   // Read the remaining operands.



From rafael.espindola at gmail.com  Wed Sep  7 11:10:57 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 07 Sep 2011 16:10:57 -0000
Subject: [llvm-commits] [llvm] r139233 -
	/llvm/trunk/lib/Target/X86/X86Subtarget.cpp
Message-ID: <20110907161057.A52322A6C12C@llvm.org>

Author: rafael
Date: Wed Sep  7 11:10:57 2011
New Revision: 139233

URL: http://llvm.org/viewvc/llvm-project?rev=139233&view=rev
Log:
Detect attempt to use segmented stacks on non ELF systems and error
(not assert) early.

Modified:
    llvm/trunk/lib/Target/X86/X86Subtarget.cpp

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=139233&r1=139232&r2=139233&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Wed Sep  7 11:10:57 2011
@@ -16,9 +16,11 @@
 #include "X86InstrInfo.h"
 #include "llvm/GlobalValue.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/SmallVector.h"
 
 #define GET_SUBTARGETINFO_TARGET_DESC
@@ -321,6 +323,9 @@
   assert((!In64BitMode || HasX86_64) &&
          "64-bit code requested on a subtarget that doesn't support it!");
 
+  if(EnableSegmentedStacks && !isTargetELF())
+    report_fatal_error("Segmented stacks are only implemented on ELF.");
+
   // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
   // 32 and 64 bit) and for all 64-bit targets.
   if (StackAlignOverride)



From grosbach at apple.com  Wed Sep  7 11:22:42 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 16:22:42 -0000
Subject: [llvm-commits] [llvm] r139234 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
Message-ID: <20110907162242.CE5A42A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 11:22:42 2011
New Revision: 139234

URL: http://llvm.org/viewvc/llvm-project?rev=139234&view=rev
Log:
Thumb2 use 'ldm' as default mnemonic.

Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139234&r1=139233&r2=139234&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep  7 11:22:42 2011
@@ -1494,7 +1494,7 @@
                             InstrItinClass itin_upd, bit L_bit> {
   def IA :
     T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
-         itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
+         itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
     bits<4>  Rn;
     bits<16> regs;
 
@@ -1509,7 +1509,7 @@
   }
   def IA_UPD :
     T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
-          itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
+          itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
     bits<4>  Rn;
     bits<16> regs;
 



From baldrick at free.fr  Wed Sep  7 11:44:14 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 07 Sep 2011 16:44:14 -0000
Subject: [llvm-commits] [llvm] r139236 - in /llvm/trunk:
 include/llvm/Intrinsics.td test/Transforms/GVN/2011-09-07-TypeIdFor.ll
Message-ID: <20110907164414.B60312A6C12C@llvm.org>

Author: baldrick
Date: Wed Sep  7 11:44:14 2011
New Revision: 139236

URL: http://llvm.org/viewvc/llvm-project?rev=139236&view=rev
Log:
When inlining exception handling code into another function, ensure that
duplicate tests are eliminated (for example if the two functions both have
a catch clause catching the same type, ensure the redundant one is removed).
Note that it would probably be safe to say that eh.typeid.for is 'const',
but since two calls to it with the same argument can give different results
(but only if the calls are in different functions), it seems more correct to
mark it only 'pure'; this doesn't get in the way of the optimization.

Added:
    llvm/trunk/test/Transforms/GVN/2011-09-07-TypeIdFor.ll
Modified:
    llvm/trunk/include/llvm/Intrinsics.td

Modified: llvm/trunk/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=139236&r1=139235&r2=139236&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Wed Sep  7 11:44:14 2011
@@ -309,7 +309,7 @@
                                  [llvm_ptr_ty, llvm_ptr_ty, llvm_vararg_ty]>;
 def int_eh_resume    : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [Throws]>;
 
-def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
+def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem]>;
 
 def int_eh_return_i32 : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>;
 def int_eh_return_i64 : Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty]>;

Added: llvm/trunk/test/Transforms/GVN/2011-09-07-TypeIdFor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2011-09-07-TypeIdFor.ll?rev=139236&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/GVN/2011-09-07-TypeIdFor.ll (added)
+++ llvm/trunk/test/Transforms/GVN/2011-09-07-TypeIdFor.ll Wed Sep  7 11:44:14 2011
@@ -0,0 +1,78 @@
+; RUN: opt < %s -basicaa -gvn -S | FileCheck %s
+%struct.__fundamental_type_info_pseudo = type { %struct.__type_info_pseudo }
+%struct.__type_info_pseudo = type { i8*, i8* }
+
+ at _ZTIi = external constant %struct.__fundamental_type_info_pseudo
+ at _ZTIb = external constant %struct.__fundamental_type_info_pseudo
+
+declare void @_Z4barv()
+
+declare i32 @llvm.eh.typeid.for(i8*) nounwind readonly
+
+declare i8* @__cxa_begin_catch(i8*) nounwind
+
+declare void @__cxa_end_catch()
+
+declare i32 @__gxx_personality_v0(i32, i64, i8*, i8*)
+
+define void @_Z3foov() uwtable {
+entry:
+  invoke void @_Z4barv()
+          to label %return unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i32 (i32, i64, i8*, i8*)* @__gxx_personality_v0
+          catch %struct.__fundamental_type_info_pseudo* @_ZTIi
+          catch %struct.__fundamental_type_info_pseudo* @_ZTIb
+          catch %struct.__fundamental_type_info_pseudo* @_ZTIi
+          catch %struct.__fundamental_type_info_pseudo* @_ZTIb
+  %exc_ptr2.i = extractvalue { i8*, i32 } %0, 0
+  %filter3.i = extractvalue { i8*, i32 } %0, 1
+  %typeid.i = tail call i32 @llvm.eh.typeid.for(i8* bitcast (%struct.__fundamental_type_info_pseudo* @_ZTIi to i8*))
+; CHECK: call i32 @llvm.eh.typeid.for
+  %1 = icmp eq i32 %filter3.i, %typeid.i
+  br i1 %1, label %ppad, label %next
+
+next:                                             ; preds = %lpad
+  %typeid1.i = tail call i32 @llvm.eh.typeid.for(i8* bitcast (%struct.__fundamental_type_info_pseudo* @_ZTIb to i8*))
+; CHECK: call i32 @llvm.eh.typeid.for
+  %2 = icmp eq i32 %filter3.i, %typeid1.i
+  br i1 %2, label %ppad2, label %next2
+
+ppad:                                             ; preds = %lpad
+  %3 = tail call i8* @__cxa_begin_catch(i8* %exc_ptr2.i) nounwind
+  tail call void @__cxa_end_catch() nounwind
+  br label %return
+
+ppad2:                                            ; preds = %next
+  %D.2073_5.i = tail call i8* @__cxa_begin_catch(i8* %exc_ptr2.i) nounwind
+  tail call void @__cxa_end_catch() nounwind
+  br label %return
+
+next2:                                            ; preds = %next
+  %typeid = tail call i32 @llvm.eh.typeid.for(i8* bitcast (%struct.__fundamental_type_info_pseudo* @_ZTIi to i8*))
+; CHECK-NOT: call i32 @llvm.eh.typeid.for
+  %4 = icmp eq i32 %filter3.i, %typeid
+  br i1 %4, label %ppad3, label %next3
+
+next3:                                            ; preds = %next2
+  %typeid1 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (%struct.__fundamental_type_info_pseudo* @_ZTIb to i8*))
+  %5 = icmp eq i32 %filter3.i, %typeid1
+  br i1 %5, label %ppad4, label %unwind
+
+unwind:                                           ; preds = %next3
+  resume { i8*, i32 } %0
+
+ppad3:                                            ; preds = %next2
+  %6 = tail call i8* @__cxa_begin_catch(i8* %exc_ptr2.i) nounwind
+  tail call void @__cxa_end_catch() nounwind
+  br label %return
+
+ppad4:                                            ; preds = %next3
+  %D.2080_5 = tail call i8* @__cxa_begin_catch(i8* %exc_ptr2.i) nounwind
+  tail call void @__cxa_end_catch() nounwind
+  br label %return
+
+return:                                           ; preds = %ppad4, %ppad3, %ppad2, %ppad, %entry
+  ret void
+}



From echristo at apple.com  Wed Sep  7 11:51:56 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 07 Sep 2011 09:51:56 -0700
Subject: [llvm-commits] [llvm] r139233 -
 /llvm/trunk/lib/Target/X86/X86Subtarget.cpp
In-Reply-To: <20110907161057.A52322A6C12C@llvm.org>
References: <20110907161057.A52322A6C12C@llvm.org>
Message-ID: <B860B3AC-E26E-46CC-9002-8BE42A946654@apple.com>


On Sep 7, 2011, at 9:10 AM, Rafael Espindola wrote:

> Detect attempt to use segmented stacks on non ELF systems and error
> (not assert) early.

Thanks!

-eric
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From resistor at mac.com  Wed Sep  7 12:10:59 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 07 Sep 2011 10:10:59 -0700
Subject: [llvm-commits] [llvm] r139204 - in /llvm/trunk:
 lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/memset_pattern.ll
In-Reply-To: <CADbEz-iPrXqnVMVb-7q9irFQGupzBDwzAsbhzMiPWJ2vAYmAZw@mail.gmail.com>
References: <20110906233325.90A302A6C12C@llvm.org>
	<CADbEz-iPrXqnVMVb-7q9irFQGupzBDwzAsbhzMiPWJ2vAYmAZw@mail.gmail.com>
Message-ID: <FA807E2D-6743-4FB5-8984-DF151DC32347@mac.com>


On Sep 6, 2011, at 5:13 PM, Nick Lewycky wrote:

> On 6 September 2011 16:33, Owen Anderson <resistor at mac.com> wrote:
> Author: resistor
> Date: Tue Sep  6 18:33:25 2011
> New Revision: 139204
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=139204&view=rev
> Log:
> Teach BasicAA about the aliasing properties of memset_pattern16.
> Fixes PR10872 and <rdar://problem/10065079>.
> 
> Added:
>    llvm/trunk/test/Analysis/BasicAA/memset_pattern.ll
> Modified:
>    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
> 
> Any particular reason not to use a LibCallAA for this?

I asked Chris about this before implementing it.  We don't currently use LibCallAA in the standard pass pipeline at all, and he considers it more intended for non-C users to describe the aliasing properties of runtime calls in their language implementations.

--Owen
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From benny.kra at googlemail.com  Wed Sep  7 12:14:09 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Wed, 7 Sep 2011 10:14:09 -0700
Subject: [llvm-commits] ObjectFile RelocationRef
In-Reply-To: <6AE1604EE3EC5F4296C096518C6B77EE17F9B4DBFE@mail.accesssoftek.com>
References: <AcxtX1CyMEhmaMQgR0awFXVqoa29vg==>
	<6AE1604EE3EC5F4296C096518C6B77EE17F9B4DBFE@mail.accesssoftek.com>
Message-ID: <CAL3drCokdsAmrfj8RN4u7z0=PReOESCz6fR-5nB51L3YFPtH=g@mail.gmail.com>

On Wed, Sep 7, 2011 at 06:09, Danil Malyshev <dmalyshev at accesssoftek.com> wrote:
> Hello everyone,
> Please find attached the patch for review. It adds relocations to the
> ObjectFile.

Can you make the macros (ELF_REL_GET_VALUE etc.) static functions?
Macros with side effects like that one make the code much harder to
follow. Looks good otherwise.

> By the way, ObjectFile as it is now implements only a reader. If it is not
> intended to modify MemoryBuffer content then how about using const
> MemoryBuffer instead?

MemoryBuffers are meant to be immutable and have only const methods,
so making the MemoryBuffer itself const doesn't make a difference.
Some code in LLVM cheats and uses const_cast to write to the
underlying memory, but that's another issue.

- Ben

From james.molloy at arm.com  Wed Sep  7 12:24:38 2011
From: james.molloy at arm.com (James Molloy)
Date: Wed, 07 Sep 2011 17:24:38 -0000
Subject: [llvm-commits] [llvm] r139237 - in /llvm/trunk: include/llvm/MC/
 include/llvm/Support/ lib/CodeGen/ lib/MC/MCDisassembler/
 lib/Target/ARM/Disassembler/ lib/Target/ARM/InstPrinter/
 lib/Target/ARM/MCTargetDesc/ lib/Target/MBlaze/Disassembler/
 lib/Target/MBlaze/MCTargetDesc/ lib/Target/MSP430/InstPrinter/
 lib/Target/MSP430/MCTargetDesc/ lib/Target/Mips/MCTargetDesc/
 lib/Target/PowerPC/MCTargetDesc/ lib/Target/X86/Disassembler/
 lib/Target/X86/MCTargetDesc/ tools/llvm-mc/ tools/llvm-objdump/
Message-ID: <20110907172438.CA34A2A6C12C@llvm.org>

Author: jamesm
Date: Wed Sep  7 12:24:38 2011
New Revision: 139237

URL: http://llvm.org/viewvc/llvm-project?rev=139237&view=rev
Log:
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.

Modified:
    llvm/trunk/include/llvm/MC/MCDisassembler.h
    llvm/trunk/include/llvm/Support/TargetRegistry.h
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
    llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
    llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp
    llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
    llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
    llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h
    llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp
    llvm/trunk/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h
    llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
    llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
    llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
    llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
    llvm/trunk/tools/llvm-mc/Disassembler.cpp
    llvm/trunk/tools/llvm-mc/Disassembler.h
    llvm/trunk/tools/llvm-mc/llvm-mc.cpp
    llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp

Modified: llvm/trunk/include/llvm/MC/MCDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDisassembler.h?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCDisassembler.h (original)
+++ llvm/trunk/include/llvm/MC/MCDisassembler.h Wed Sep  7 12:24:38 2011
@@ -15,6 +15,7 @@
 namespace llvm {
   
 class MCInst;
+class MCSubtargetInfo;
 class MemoryObject;
 class raw_ostream;
 class MCContext;
@@ -54,7 +55,7 @@
   };
 
   /// Constructor     - Performs initial setup for the disassembler.
-  MCDisassembler() : GetOpInfo(0), DisInfo(0), Ctx(0) {}
+  MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), DisInfo(0), Ctx(0), STI(STI) {}
   
   virtual ~MCDisassembler();
   
@@ -98,6 +99,9 @@
   // The assembly context for creating symbols and MCExprs in place of
   // immediate operands when there is symbolic information.
   MCContext *Ctx;
+protected:
+  // Subtarget information, for instruction decoding predicates if required.
+  const MCSubtargetInfo &STI;
 
 public:
   void setupForSymbolicDisassembly(LLVMOpInfoCallback getOpInfo,

Modified: llvm/trunk/include/llvm/Support/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetRegistry.h?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetRegistry.h (original)
+++ llvm/trunk/include/llvm/Support/TargetRegistry.h Wed Sep  7 12:24:38 2011
@@ -94,10 +94,12 @@
                                                   const MCAsmInfo &MAI);
     typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI,
                                                     MCAsmParser &P);
-    typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
+    typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,
+                                                    const MCSubtargetInfo &STI);
     typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
                                                   unsigned SyntaxVariant,
-                                                  const MCAsmInfo &MAI);
+                                                  const MCAsmInfo &MAI,
+                                                  const MCSubtargetInfo &STI);
     typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,
                                                   const MCSubtargetInfo &STI,
                                                   MCContext &Ctx);
@@ -373,17 +375,18 @@
       return AsmPrinterCtorFn(TM, Streamer);
     }
 
-    MCDisassembler *createMCDisassembler() const {
+    MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI) const {
       if (!MCDisassemblerCtorFn)
         return 0;
-      return MCDisassemblerCtorFn(*this);
+      return MCDisassemblerCtorFn(*this, STI);
     }
 
     MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant,
-                                       const MCAsmInfo &MAI) const {
+                                       const MCAsmInfo &MAI,
+                                       const MCSubtargetInfo &STI) const {
       if (!MCInstPrinterCtorFn)
         return 0;
-      return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI);
+      return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, STI);
     }
 
 

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Sep  7 12:24:38 2011
@@ -131,13 +131,14 @@
     Context->setAllowTemporaryLabels(false);
 
   const MCAsmInfo &MAI = *getMCAsmInfo();
+  const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
   OwningPtr<MCStreamer> AsmStreamer;
 
   switch (FileType) {
   default: return true;
   case CGFT_AssemblyFile: {
     MCInstPrinter *InstPrinter =
-      getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
+      getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, STI);
 
     // Create a code emitter if asked to show the encoding.
     MCCodeEmitter *MCE = 0;
@@ -161,7 +162,6 @@
   case CGFT_ObjectFile: {
     // Create the code emitter for the target if it exists.  If not, .o file
     // emission fails.
-    const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
     MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI,
                                                          *Context);
     MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());

Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Wed Sep  7 12:24:38 2011
@@ -57,19 +57,23 @@
   std::string FeaturesStr;
   std::string CPU;
 
+  const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(TripleName, CPU,
+                                                                FeaturesStr);
+  assert(STI && "Unable to create subtarget info!");
+
   // Set up the MCContext for creating symbols and MCExpr's.
   MCContext *Ctx = new MCContext(*MAI, *MRI, 0);
   assert(Ctx && "Unable to create MCContext!");
 
   // Set up disassembler.
-  MCDisassembler *DisAsm = TheTarget->createMCDisassembler();
+  MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI);
   assert(DisAsm && "Unable to create disassembler!");
   DisAsm->setupForSymbolicDisassembly(GetOpInfo, DisInfo, Ctx);
 
   // Set up the instruction printer.
   int AsmPrinterVariant = MAI->getAssemblerDialect();
   MCInstPrinter *IP = TheTarget->createMCInstPrinter(AsmPrinterVariant,
-                                                     *MAI);
+                                                     *MAI, *STI);
   assert(IP && "Unable to create instruction printer!");
 
   LLVMDisasmContext *DC = new LLVMDisasmContext(TripleName, DisInfo, TagType,

Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Wed Sep  7 12:24:38 2011
@@ -178,7 +178,12 @@
   if (!AsmInfo)
     return;
 
-  Disassembler.reset(Tgt->createMCDisassembler());
+  STI.reset(Tgt->createMCSubtargetInfo(tripleString, "", ""));
+  
+  if (!STI)
+    return;
+
+  Disassembler.reset(Tgt->createMCDisassembler(*STI));
   
   if (!Disassembler)
     return;
@@ -187,7 +192,7 @@
   
   InstString.reset(new std::string);
   InstStream.reset(new raw_string_ostream(*InstString));
-  InstPrinter.reset(Tgt->createMCInstPrinter(LLVMSyntaxVariant, *AsmInfo));
+  InstPrinter.reset(Tgt->createMCInstPrinter(LLVMSyntaxVariant, *AsmInfo, *STI));
   
   if (!InstPrinter)
     return;

Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h (original)
+++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h Wed Sep  7 12:24:38 2011
@@ -137,6 +137,8 @@
   const llvm::Target *Tgt;
   /// The assembly information for the target architecture
   llvm::OwningPtr<const llvm::MCAsmInfo> AsmInfo;
+  /// The subtarget information for the target architecture
+  llvm::OwningPtr<const llvm::MCSubtargetInfo> STI;
   // The register information for the target architecture.
   llvm::OwningPtr<const llvm::MCRegisterInfo> MRI;
   /// The disassembler for the target architecture

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Sep  7 12:24:38 2011
@@ -11,6 +11,7 @@
 
 #include "ARM.h"
 #include "ARMRegisterInfo.h"
+#include "ARMSubtarget.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
 #include "MCTargetDesc/ARMBaseInfo.h"
 #include "llvm/MC/EDInstInfo.h"
@@ -34,8 +35,8 @@
 public:
   /// Constructor     - Initializes the disassembler.
   ///
-  ARMDisassembler() :
-    MCDisassembler() {
+  ARMDisassembler(const MCSubtargetInfo &STI) :
+    MCDisassembler(STI) {
   }
 
   ~ARMDisassembler() {
@@ -58,8 +59,8 @@
 public:
   /// Constructor     - Initializes the disassembler.
   ///
-  ThumbDisassembler() :
-    MCDisassembler() {
+  ThumbDisassembler(const MCSubtargetInfo &STI) :
+    MCDisassembler(STI) {
   }
 
   ~ThumbDisassembler() {
@@ -296,12 +297,12 @@
 #include "ARMGenInstrInfo.inc"
 #include "ARMGenEDInfo.inc"
 
-static MCDisassembler *createARMDisassembler(const Target &T) {
-  return new ARMDisassembler;
+static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
+  return new ARMDisassembler(STI);
 }
 
-static MCDisassembler *createThumbDisassembler(const Target &T) {
-  return new ThumbDisassembler;
+static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
+  return new ThumbDisassembler(STI);
 }
 
 EDInstInfo *ARMDisassembler::getEDInfo() const {

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Sep  7 12:24:38 2011
@@ -35,6 +35,14 @@
   return imm;
 }
 
+
+ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
+                               const MCSubtargetInfo &STI) :
+  MCInstPrinter(MAI) {
+  // Initialize the set of available features.
+  setAvailableFeatures(STI.getFeatureBits());
+}
+
 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
   return getInstructionName(Opcode);
 }

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Wed Sep  7 12:24:38 2011
@@ -15,6 +15,7 @@
 #define ARMINSTPRINTER_H
 
 #include "llvm/MC/MCInstPrinter.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 
 namespace llvm {
 
@@ -22,8 +23,7 @@
 
 class ARMInstPrinter : public MCInstPrinter {
 public:
-  ARMInstPrinter(const MCAsmInfo &MAI)
-    : MCInstPrinter(MAI) {}
+    ARMInstPrinter(const MCAsmInfo &MAI, const MCSubtargetInfo &STI);
 
   virtual void printInst(const MCInst *MI, raw_ostream &O);
   virtual StringRef getOpcodeName(unsigned Opcode) const;

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Sep  7 12:24:38 2011
@@ -164,9 +164,10 @@
 
 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
                                              unsigned SyntaxVariant,
-                                             const MCAsmInfo &MAI) {
+                                             const MCAsmInfo &MAI,
+                                             const MCSubtargetInfo &STI) {
   if (SyntaxVariant == 0)
-    return new ARMInstPrinter(MAI);
+    return new ARMInstPrinter(MAI, STI);
   return 0;
 }
 

Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Wed Sep  7 12:24:38 2011
@@ -696,8 +696,9 @@
   return Success;
 }
 
-static MCDisassembler *createMBlazeDisassembler(const Target &T) {
-  return new MBlazeDisassembler;
+static MCDisassembler *createMBlazeDisassembler(const Target &T,
+                                                const MCSubtargetInfo &STI) {
+  return new MBlazeDisassembler(STI);
 }
 
 extern "C" void LLVMInitializeMBlazeDisassembler() {

Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h (original)
+++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h Wed Sep  7 12:24:38 2011
@@ -32,8 +32,8 @@
 public:
   /// Constructor     - Initializes the disassembler.
   ///
-  MBlazeDisassembler() :
-    MCDisassembler() {
+  MBlazeDisassembler(const MCSubtargetInfo &STI) :
+    MCDisassembler(STI) {
   }
 
   ~MBlazeDisassembler() {

Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Wed Sep  7 12:24:38 2011
@@ -95,7 +95,8 @@
 
 static MCInstPrinter *createMBlazeMCInstPrinter(const Target &T,
                                                 unsigned SyntaxVariant,
-                                                const MCAsmInfo &MAI) {
+                                                const MCAsmInfo &MAI,
+                                                const MCSubtargetInfo &STI) {
   if (SyntaxVariant == 0)
     return new MBlazeInstPrinter(MAI);
   return 0;

Modified: llvm/trunk/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h (original)
+++ llvm/trunk/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h Wed Sep  7 12:24:38 2011
@@ -22,7 +22,7 @@
   class MSP430InstPrinter : public MCInstPrinter {
   public:
     MSP430InstPrinter(const MCAsmInfo &MAI)
-      : MCInstPrinter(MAI) {}
+        : MCInstPrinter(MAI) {}
 
     virtual void printInst(const MCInst *MI, raw_ostream &O);
 

Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp Wed Sep  7 12:24:38 2011
@@ -59,7 +59,8 @@
 
 static MCInstPrinter *createMSP430MCInstPrinter(const Target &T,
                                                 unsigned SyntaxVariant,
-                                                const MCAsmInfo &MAI) {
+                                                const MCAsmInfo &MAI,
+                                                const MCSubtargetInfo &STI) {
   if (SyntaxVariant == 0)
     return new MSP430InstPrinter(MAI);
   return 0;

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Wed Sep  7 12:24:38 2011
@@ -78,7 +78,8 @@
 
 static MCInstPrinter *createMipsMCInstPrinter(const Target &T,
                                               unsigned SyntaxVariant,
-                                              const MCAsmInfo &MAI) {
+                                              const MCAsmInfo &MAI,
+                                              const MCSubtargetInfo &STI) {
   return new MipsInstPrinter(MAI);
 }
 

Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Wed Sep  7 12:24:38 2011
@@ -105,7 +105,8 @@
 
 static MCInstPrinter *createPPCMCInstPrinter(const Target &T,
                                              unsigned SyntaxVariant,
-                                             const MCAsmInfo &MAI) {
+                                             const MCAsmInfo &MAI,
+                                             const MCSubtargetInfo &STI) {
   return new PPCInstPrinter(MAI, SyntaxVariant);
 }
 

Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Wed Sep  7 12:24:38 2011
@@ -21,6 +21,7 @@
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MemoryObject.h"
 #include "llvm/Support/TargetRegistry.h"
@@ -66,8 +67,8 @@
 static bool translateInstruction(MCInst &target,
                                 InternalInstruction &source);
 
-X86GenericDisassembler::X86GenericDisassembler(DisassemblerMode mode) :
-    MCDisassembler(),
+X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode) :
+    MCDisassembler(STI),
     fMode(mode) {
 }
 
@@ -578,12 +579,12 @@
   return false;
 }
 
-static MCDisassembler *createX86_32Disassembler(const Target &T) {
-  return new X86Disassembler::X86_32Disassembler;
+static MCDisassembler *createX86_32Disassembler(const Target &T, const MCSubtargetInfo &STI) {
+  return new X86Disassembler::X86_32Disassembler(STI);
 }
 
-static MCDisassembler *createX86_64Disassembler(const Target &T) {
-  return new X86Disassembler::X86_64Disassembler;
+static MCDisassembler *createX86_64Disassembler(const Target &T, const MCSubtargetInfo &STI) {
+  return new X86Disassembler::X86_64Disassembler(STI);
 }
 
 extern "C" void LLVMInitializeX86Disassembler() { 

Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h Wed Sep  7 12:24:38 2011
@@ -92,6 +92,7 @@
 namespace llvm {
   
 class MCInst;
+class MCSubtargetInfo;
 class MemoryObject;
 class raw_ostream;
 
@@ -107,7 +108,7 @@
   /// Constructor     - Initializes the disassembler.
   ///
   /// @param mode     - The X86 architecture mode to decode for.
-  X86GenericDisassembler(DisassemblerMode mode);
+  X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode);
 public:
   ~X86GenericDisassembler();
 
@@ -127,24 +128,24 @@
 /// X86_16Disassembler - 16-bit X86 disassembler.
 class X86_16Disassembler : public X86GenericDisassembler {
 public:
-  X86_16Disassembler() :
-    X86GenericDisassembler(MODE_16BIT) {
+  X86_16Disassembler(const MCSubtargetInfo &STI) :
+    X86GenericDisassembler(STI, MODE_16BIT) {
   }
 };  
 
 /// X86_16Disassembler - 32-bit X86 disassembler.
 class X86_32Disassembler : public X86GenericDisassembler {
 public:
-  X86_32Disassembler() :
-    X86GenericDisassembler(MODE_32BIT) {
+  X86_32Disassembler(const MCSubtargetInfo &STI) :
+    X86GenericDisassembler(STI, MODE_32BIT) {
   }
 };
 
 /// X86_16Disassembler - 64-bit X86 disassembler.
 class X86_64Disassembler : public X86GenericDisassembler {
 public:
-  X86_64Disassembler() :
-    X86GenericDisassembler(MODE_64BIT) {
+  X86_64Disassembler(const MCSubtargetInfo &STI) :
+    X86GenericDisassembler(STI, MODE_64BIT) {
   }
 };
 

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Wed Sep  7 12:24:38 2011
@@ -394,7 +394,8 @@
 
 static MCInstPrinter *createX86MCInstPrinter(const Target &T,
                                              unsigned SyntaxVariant,
-                                             const MCAsmInfo &MAI) {
+                                             const MCAsmInfo &MAI,
+                                             const MCSubtargetInfo &STI) {
   if (SyntaxVariant == 0)
     return new X86ATTInstPrinter(MAI);
   if (SyntaxVariant == 1)

Modified: llvm/trunk/tools/llvm-mc/Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/Disassembler.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/Disassembler.cpp (original)
+++ llvm/trunk/tools/llvm-mc/Disassembler.cpp Wed Sep  7 12:24:38 2011
@@ -21,6 +21,7 @@
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstPrinter.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/ADT/OwningPtr.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/ADT/Twine.h"
@@ -140,6 +141,8 @@
 
 int Disassembler::disassemble(const Target &T,
                               const std::string &Triple,
+                              const std::string &Cpu,
+                              const std::string &FeaturesStr,
                               MemoryBuffer &Buffer,
                               raw_ostream &Out) {
   // Set up disassembler.
@@ -150,7 +153,13 @@
     return -1;
   }
 
-  OwningPtr<const MCDisassembler> DisAsm(T.createMCDisassembler());
+  OwningPtr<const MCSubtargetInfo> STI(T.createMCSubtargetInfo(Triple, Cpu, FeaturesStr));
+  if (!STI) {
+    errs() << "error: no subtarget info for target " << Triple << "\n";
+    return -1;
+  }
+  
+  OwningPtr<const MCDisassembler> DisAsm(T.createMCDisassembler(*STI));
   if (!DisAsm) {
     errs() << "error: no disassembler for target " << Triple << "\n";
     return -1;
@@ -158,7 +167,7 @@
 
   int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
   OwningPtr<MCInstPrinter> IP(T.createMCInstPrinter(AsmPrinterVariant,
-                                                    *AsmInfo));
+                                                    *AsmInfo, *STI));
   if (!IP) {
     errs() << "error: no instruction printer for target " << Triple << '\n';
     return -1;

Modified: llvm/trunk/tools/llvm-mc/Disassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/Disassembler.h?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/Disassembler.h (original)
+++ llvm/trunk/tools/llvm-mc/Disassembler.h Wed Sep  7 12:24:38 2011
@@ -27,6 +27,8 @@
 public:
   static int disassemble(const Target &target,
                          const std::string &tripleString,
+                         const std::string &Cpu,
+                         const std::string &FeaturesStr,
                          MemoryBuffer &buffer,
                          raw_ostream &Out);
 

Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Sep  7 12:24:38 2011
@@ -108,6 +108,12 @@
      cl::value_desc("cpu-name"),
      cl::init(""));
 
+static cl::list<std::string>
+MAttrs("mattr",
+  cl::CommaSeparated,
+  cl::desc("Target specific attributes (-mattr=help for details)"),
+  cl::value_desc("a1,+a2,-a3,..."));
+
 static cl::opt<Reloc::Model>
 RelocModel("relocation-model",
              cl::desc("Choose relocation model"),
@@ -361,9 +367,6 @@
   llvm::OwningPtr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
   assert(MRI && "Unable to create target register info!");
 
-  // Package up features to be passed to target/subtarget
-  std::string FeaturesStr;
-
   // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and
   // MCObjectFileInfo needs a MCContext reference in order to initialize itself.
   OwningPtr<MCObjectFileInfo> MOFI(new MCObjectFileInfo());
@@ -373,6 +376,15 @@
   if (SaveTempLabels)
     Ctx.setAllowTemporaryLabels(false);
 
+  // Package up features to be passed to target/subtarget
+  std::string FeaturesStr;
+  if (MAttrs.size()) {
+    SubtargetFeatures Features;
+    for (unsigned i = 0; i != MAttrs.size(); ++i)
+      Features.AddFeature(MAttrs[i]);
+    FeaturesStr = Features.getString();
+  }
+
   OwningPtr<tool_output_file> Out(GetOutputStream());
   if (!Out)
     return 1;
@@ -387,7 +399,7 @@
   // FIXME: There is a bit of code duplication with addPassesToEmitFile.
   if (FileType == OFT_AssemblyFile) {
     MCInstPrinter *IP =
-      TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI);
+      TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI, *STI);
     MCCodeEmitter *CE = 0;
     MCAsmBackend *MAB = 0;
     if (ShowEncoding) {
@@ -453,7 +465,16 @@
     Res =
       Disassembler::disassembleEnhanced(TripleName, *Buffer.take(), Out->os());
   } else {
-    Res = Disassembler::disassemble(*TheTarget, TripleName,
+    // Package up features to be passed to target/subtarget
+    std::string FeaturesStr;
+    if (MAttrs.size()) {
+      SubtargetFeatures Features;
+      for (unsigned i = 0; i != MAttrs.size(); ++i)
+        Features.AddFeature(MAttrs[i]);
+      FeaturesStr = Features.getString();
+    }
+
+    Res = Disassembler::disassemble(*TheTarget, TripleName, MCPU, FeaturesStr,
                                     *Buffer.take(), Out->os());
   }
 

Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=139237&r1=139236&r2=139237&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Wed Sep  7 12:24:38 2011
@@ -25,6 +25,7 @@
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Format.h"
@@ -217,7 +218,14 @@
       return;
     }
 
-    OwningPtr<const MCDisassembler> DisAsm(TheTarget->createMCDisassembler());
+    OwningPtr<const MCSubtargetInfo> STI(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
+
+    if (!STI) {
+      errs() << "error: no subtarget info for target " << TripleName << "\n";
+      return;
+    }
+
+    OwningPtr<const MCDisassembler> DisAsm(TheTarget->createMCDisassembler(*STI));
     if (!DisAsm) {
       errs() << "error: no disassembler for target " << TripleName << "\n";
       return;
@@ -225,7 +233,7 @@
 
     int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
     OwningPtr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
-                                  AsmPrinterVariant, *AsmInfo));
+                                AsmPrinterVariant, *AsmInfo, *STI));
     if (!IP) {
       errs() << "error: no instruction printer for target " << TripleName << '\n';
       return;



From james.molloy at arm.com  Wed Sep  7 12:44:12 2011
From: james.molloy at arm.com (James Molloy)
Date: Wed, 7 Sep 2011 18:44:12 +0100
Subject: [llvm-commits] [PATCH] Fix cortex-m class
	MSR/MRS	and	resolve	(safe) ambiguous instruction encodings
In-Reply-To: <000101cc6d2b$8329d580$897d8080$@molloy@arm.com>
References: <F01D8B85CFF58440B2A13965FBA90CA473757133E2@GEORGE.Emea.Arm.com>	<2d7245b3-74a7-e6a6-f45d-ee682d3f7fb9@me.com>
	<000101cc6d2b$8329d580$897d8080$@molloy@arm.com>
Message-ID: <000601cc6d85$c1cb0ed0$45612c70$@molloy@arm.com>

Owen,

 

I committed patch 0 after your review. Thanks for that.

 

Newer version of patch 1 attached, updated for ToT. Patch 2 still applies
cleanly (patch 0 was the really invasive one).

 

Cheers,

 

James

 

From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu]
On Behalf Of James Molloy
Sent: 07 September 2011 07:58
To: resistor at me.com
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve
(safe) ambiguous instruction encodings

 

Hi Owen,

 

Given the invasive nature of the patches, I didn't honestly expect them to apply
cleanly to ToT for more than a day or two after the patch was created. I was
going to deal with the merge fallout myself ideally after review, but I'll
rebase to ToT today and send updated patches for you.

 

Thanks for letting me know about the clang driver - I'll ensure that's updated
too.

 

Cheers,

 

James

 

From: resistor at me.com [mailto:resistor at me.com] 
Sent: 06 September 2011 23:28
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve
(safe) ambiguous instruction encodings

 

Thanks James,

 

Patch 0 now applies for me, and looks fine in general, with the caveat that
there's a dependent change in the clang driver
(tools/clang/tools/driver/cc1as.cpp) that is needed as well.  I'm not totally
happy about having to expose the subtarget info to the decoder and printer, but
after looking at the reference manual I don't really see a way around it.

 

Patch 1 has some issues.  It looks like ARMDisassembler.cpp needs to be updated
to pass the subtarget info object to the individual decoder methods.

 

--Owen

On Sep 06, 2011, at 02:29 PM, James Molloy <James.Molloy at arm.com> wrote:

Hi Owen,

Sorry for taking so long getting back to you on this - make check has crashed my
laptop twice now with what appears to be an errant llc process. I'm looking into
that now (doesn't happen when running lit manually...)

Anyway, the patch attached applies to ToT now and has no conflicts. All targets
build correctly and the regression tests pass.

Cheers,

James
________________________________________
From: Owen Anderson [resistor at me.com]
Sent: 06 September 2011 19:43
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve
(safe) ambiguous instruction encodings

James,

Patch 0 seems to be missing some necessary changes to non-ARM targets to make
LLVM build with it applied. I see a lot of errors of the form:

MipsMCTargetDesc.cpp:109:41: error: cannot initialize a parameter of type
'Target::MCInstPrinterCtorTy' (aka 'llvm::MCInstPrinter *(*)(const llvm::Target
&, unsigned int, const llvm::MCAsmInfo &, const llvm::MCSubtargetInfo &)') with
an lvalue of type 'llvm::MCInstPrinter *(const llvm::Target &,
unsigned int, const llvm::MCAsmInfo &)'
createMipsMCInstPrinter);
^~~~~~~~~~~~~~~~~~~~~~~

--Owen

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:

> Hi,
>
> The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M
series
> not allowing the correct mask names.
>
> The patch becomes difficult because:
> * There is no way to determine in the InstPrinter any subtarget specific
> features (such as "operating on an m-class core?").
> * There is currently no subtarget feature for "M-class core?"; the nearest is
> IsThumb2 && !HasARM.
> * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
> a way that makes them deterministically separable. This causes non-conflicting
> ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
> both code paths are emitted but only one will ever be hit
>
> The solution is:
> * Add subtarget info to InstPrinter so it can determine what to do with the
> mask immediate.
> * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
> IsARClass == !IsMClass. This feature only has semantic sense on v6+
> architectures.
> * The conflicts occur because the FixedLenDecoderEmitter does not honour the
> Predicates field of instructions in the tablegen description. If the island
> checking also checked the AssemblerPredicates field (if defined), ambiguous
> instruction encodings that are disambiguated by predicates would (do) work
fine.
>
> The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and
MCDisassembler.
> They can use this (in patch #2) to determine what mask names to accept
(primask?
> or cpsr_zxvf?)
>
> The second enhances FixedLenPredicateEncoder to emit predicate checks for
> instructions before it accepts an encoding - this allows ambiguous
instructions
> to be disambiguated by the Predicates field in TableGen This required changing
> llvm-mc to accept -mattr, and tests to set the correct features they rely
upon.
>
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were
being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2
STC/STC2
> is created.**
>
> The third patch adds a new predicate "IsMClass" along with its counterpart
> "IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
> Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
> encodings respectively. It also fixes mask printing for MRS/MSR in the
> ARMMCInstPrinter and ARMMCAsmParser.
>
> Testcases added with the final patch.
>
> Comments? Is it OK?
>
> Cheers,
>
> James
>
> [N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout
myself
> after review]
>
<patch0-add-sti-to-instprinter.patch><patch1-modify-fixedlendecoderemitter.patch
><patch2-fix-msr-mrs.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




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From isanbard at gmail.com  Wed Sep  7 12:46:21 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 07 Sep 2011 17:46:21 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r139239 - in /llvm-gcc-4.2/trunk/gcc:
 llvm-convert.cpp llvm-internal.h
Message-ID: <20110907174621.3EC242A6C12C@llvm.org>

Author: void
Date: Wed Sep  7 12:46:21 2011
New Revision: 139239

URL: http://llvm.org/viewvc/llvm-project?rev=139239&view=rev
Log:
Revert r139212 until I can fix failures.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
    llvm-gcc-4.2/trunk/gcc/llvm-internal.h

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=139239&r1=139238&r2=139239&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Sep  7 12:46:21 2011
@@ -188,6 +188,7 @@
   GreatestAlignment = TheTarget->getFrameLowering()->getStackAlignment();
   SeenVLA = NULL;
 
+  CatchAll = 0;
   ExceptionValue = 0;
   ExceptionSelectorValue = 0;
   FuncEHException = 0;
@@ -2163,6 +2164,25 @@
                                               Intrinsic::eh_selector);
   FuncEHGetTypeID = Intrinsic::getDeclaration(TheModule,
                                               Intrinsic::eh_typeid_for);
+
+  CatchAll = TheModule->getGlobalVariable("llvm.eh.catch.all.value");
+  if (!CatchAll && lang_eh_catch_all) {
+    Constant *Init = 0;
+    tree catch_all_type = lang_eh_catch_all();
+    if (catch_all_type == NULL_TREE)
+      // Use a C++ style null catch-all object.
+      Init = Constant::getNullValue(Type::getInt8PtrTy(Context));
+    else
+      // This language has a type that catches all others.
+      Init = cast<Constant>(Emit(catch_all_type, 0));
+
+    CatchAll = new GlobalVariable(*TheModule, Init->getType(), true,
+                                  GlobalVariable::LinkOnceAnyLinkage,
+                                  Init, "llvm.eh.catch.all.value");
+    CatchAll->setUnnamedAddr(true);
+    CatchAll->setSection("llvm.metadata");
+    AttributeUsedGlobals.insert(CatchAll);
+  }
 }
 
 /// getPostPad - Return the post landing pad for the given exception handling
@@ -2185,10 +2205,9 @@
 
 /// EmitLandingPads - Emit EH landing pads.
 void TreeToLLVM::EmitLandingPads() {
+  std::vector<Value*> Args;
   std::vector<struct eh_region *> Handlers;
 
-  Type *UnwindDataTy = StructType::get(Builder.getInt8PtrTy(),
-                                       Builder.getInt32Ty(), NULL);
   for (unsigned i = 1; i < LandingPads.size(); ++i) {
     BasicBlock *LandingPad = LandingPads[i];
 
@@ -2206,19 +2225,11 @@
     // Fetch and store the exception selector.
 
     // The exception and the personality function.
+    Args.push_back(Builder.CreateLoad(ExceptionValue, "eh_ptr"));
     assert(llvm_eh_personality_libfunc
            && "no exception handling personality function!");
-    LandingPadInst *LPadInst =
-      Builder.CreateLandingPad(UnwindDataTy,
-                               BitCastToType(DECL_LLVM(llvm_eh_personality_libfunc),
-                                             Type::getInt8PtrTy(Context)),
-                               0, "exc");
-
-    Value *ExcPtr = Builder.CreateExtractValue(LPadInst, 0, "exc_ptr");
-    Builder.CreateStore(ExcPtr, ExceptionValue);
-
-    Value *Select = Builder.CreateExtractValue(LPadInst, 1, "filter");
-    Builder.CreateStore(Select, ExceptionSelectorValue);
+    Args.push_back(BitCastToType(DECL_LLVM(llvm_eh_personality_libfunc),
+                                 Type::getInt8PtrTy(Context)));
 
     // Add selections for each handler.
     foreach_reachable_handler(i, false, AddHandler, &Handlers);
@@ -2235,34 +2246,31 @@
 
       int RegionKind = classify_eh_handler(region);
       if (RegionKind < 0) {
-        // Filter.
+        // Filter - note the length.
         tree TypeList = get_eh_type_list(region);
+        unsigned Length = list_length(TypeList);
+        Args.reserve(Args.size() + Length + 1);
+        Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), Length + 1));
 
         // Add the type infos.
-        std::vector<Constant*> TypeInfos;
         for (; TypeList; TypeList = TREE_CHAIN(TypeList)) {
           tree TType = lookup_type_for_runtime(TREE_VALUE(TypeList));
-          TypeInfos.push_back(cast<Constant>(Emit(TType, 0)));
+          Args.push_back(Emit(TType, 0));
         }
-
-        // Add the list of typeinfos as a filter clause.
-        ArrayType *FilterTy = ArrayType::get(Builder.getInt8PtrTy(),
-                                             TypeInfos.size());
-        LPadInst->addClause(ConstantArray::get(FilterTy, TypeInfos));
       } else if (RegionKind > 0) {
         // Catch.
         tree TypeList = get_eh_type_list(region);
 
         if (!TypeList) {
           // Catch-all - push the catch-all object.
-          LPadInst->
-            addClause(Constant::getNullValue(Type::getInt8PtrTy(Context)));
+          assert(CatchAll && "Language did not define lang_eh_catch_all?");
+          Args.push_back(CatchAll);
           HasCatchAll = true;
         } else {
           // Add the type infos.
           for (; TypeList; TypeList = TREE_CHAIN(TypeList)) {
             tree TType = lookup_type_for_runtime(TREE_VALUE(TypeList));
-            LPadInst->addClause(Emit(TType, 0));
+            Args.push_back(Emit(TType, 0));
           }
         }
       } else {
@@ -2271,14 +2279,32 @@
       }
     }
 
-    if (can_throw_external_1(i, false) && HasCleanup)
-      LPadInst->setCleanup(true);
+    if (can_throw_external_1(i, false)) {
+      if (HasCleanup) {
+        if (Args.size() == 2 || USING_SJLJ_EXCEPTIONS || !lang_eh_catch_all) {
+          // Insert the sentinal indicating that this is a cleanup-only
+          // selector.  It may also be the representation of a catch-all for
+          // some languages.
+          Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), 0));
+        } else if (!HasCatchAll) {
+          // Some exceptions from this region may not be caught by any handler.
+          // Since invokes are required to branch to the unwind label no matter
+          // what exception is being unwound, append a catch-all.
+          assert(CatchAll && "Language did not define lang_eh_catch_all?");
+          Args.push_back(CatchAll);
+        }
+      }
+    }
 
+    // Emit the selector call.
+    Value *Select = Builder.CreateCall(FuncEHSelector, Args, "eh_select");
+    Builder.CreateStore(Select, ExceptionSelectorValue);
     // Branch to the post landing pad for the first reachable handler.
     assert(!Handlers.empty() && "Landing pad but no handler?");
     Builder.CreateBr(getPostPad(get_eh_region_number(*Handlers.begin())));
 
     Handlers.clear();
+    Args.clear();
   }
 }
 
@@ -2398,19 +2424,29 @@
 
 /// EmitUnwindBlock - Emit the lazily created EH unwind block.
 void TreeToLLVM::EmitUnwindBlock() {
-  if (!UnwindBB) return;
-
-  CreateExceptionValues();
-  EmitBlock(UnwindBB);
+  if (UnwindBB) {
+    CreateExceptionValues();
+    EmitBlock(UnwindBB);
+    // Fetch and store exception handler.
+    Value *Arg = Builder.CreateLoad(ExceptionValue, "eh_ptr");
+    assert(llvm_unwind_resume_libfunc && "no unwind resume function!");
+
+    // As we're emitting a naked call (not an expression) going through
+    // EmitCallOf would be wasteful and incorrect. Manually adjust
+    // the calling convention for this call here if necessary.
+#ifdef TARGET_ADJUST_LLVM_CC
+    tree fntype = TREE_TYPE(llvm_unwind_resume_libfunc);
+    CallingConv::ID CallingConvention = CallingConv::C;
 
-  Value *ExcPtr = Builder.CreateLoad(ExceptionValue, "eh_ptr");
-  Value *Filter = Builder.CreateLoad(ExceptionSelectorValue, "eh_sel");
-  Type *UnwindDataTy = StructType::get(Builder.getInt8PtrTy(),
-                                       Builder.getInt32Ty(), NULL);
-  Value *UnwindData = UndefValue::get(UnwindDataTy);
-  UnwindData = Builder.CreateInsertValue(UnwindData, ExcPtr, 0, "exc_ptr");
-  UnwindData = Builder.CreateInsertValue(UnwindData, Filter, 1, "filter");
-  Builder.CreateResume(UnwindData);
+    TARGET_ADJUST_LLVM_CC(CallingConvention, fntype);
+    CallInst *Call = Builder.CreateCall(DECL_LLVM(llvm_unwind_resume_libfunc),
+                                        Arg);
+    Call->setCallingConv(CallingConvention);
+#else
+    Builder.CreateCall(DECL_LLVM(llvm_unwind_resume_libfunc), Arg);
+#endif
+    Builder.CreateUnreachable();
+  }
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=139239&r1=139238&r2=139239&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Wed Sep  7 12:46:21 2011
@@ -317,6 +317,9 @@
   /// PostPads - The post landing pad for a given EH region.
   IndexedMap<BasicBlock *> PostPads;
 
+  /// CatchAll - Language specific catch-all object.
+  GlobalVariable *CatchAll;
+
   /// ExceptionValue - Is the local to receive the current exception.
   Value *ExceptionValue;
 



From resistor at mac.com  Wed Sep  7 12:55:19 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 07 Sep 2011 17:55:19 -0000
Subject: [llvm-commits] [llvm] r139240 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/thumb2.txt
Message-ID: <20110907175519.F13552A6C12C@llvm.org>

Author: resistor
Date: Wed Sep  7 12:55:19 2011
New Revision: 139240

URL: http://llvm.org/viewvc/llvm-project?rev=139240&view=rev
Log:
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139240&r1=139239&r2=139240&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Sep  7 12:55:19 2011
@@ -2786,7 +2786,7 @@
         break;
       case 0xf3bf8f6:
         Inst.setOpcode(ARM::t2ISB);
-        return MCDisassembler::Success;
+        break;
     }
 
     unsigned imm = fieldFromInstruction32(Insn, 0, 4);

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt?rev=139240&r1=139239&r2=139240&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt Wed Sep  7 12:55:19 2011
@@ -244,6 +244,164 @@
 0x1f 0xb9
 0x37 0xb9
 
+#------------------------------------------------------------------------------
+# CDP/CDP2
+#------------------------------------------------------------------------------
+# CHECK: cdp  p7, #1, c1, c1, c1, #4
+# CHECK: cdp2  p7, #1, c1, c1, c1, #4
+
+0x11 0xee 0x81 0x17
+0x11 0xfe 0x81 0x17
+
+
+#------------------------------------------------------------------------------
+# CLREX
+#------------------------------------------------------------------------------
+#CHECK: clrex
+#CHECK: it ne
+#CHECK: clrexne
+
+0xbf 0xf3 0x2f 0x8f
+0x18 0xbf
+0xbf 0xf3 0x2f 0x8f
+
+
+#------------------------------------------------------------------------------
+# CLZ
+#------------------------------------------------------------------------------
+#CHECK: clz r1, r2
+#CHECK: it eq
+#CHECK: clzeq r1, r2
+
+0xb2 0xfa 0x82 0xf1
+0x08 0xbf
+0xb2 0xfa 0x82 0xf1
+
+
+#------------------------------------------------------------------------------
+# CMN
+#------------------------------------------------------------------------------
+#CHECK: cmn.w r1, #15
+#CHECK: cmn.w r8, r6
+#CHECK: cmn.w r1, r6, lsl #10
+#CHECK: cmn.w r1, r6, lsr #10
+#CHECK: cmn.w sp, r6, lsr #10
+#CHECK: cmn.w r1, r6, asr #10
+#CHECK: cmn.w r1, r6, ror #10
+
+0x11 0xf1 0x0f 0x0f
+0x18 0xeb 0x06 0x0f
+0x11 0xeb 0x86 0x2f
+0x11 0xeb 0x96 0x2f
+0x1d 0xeb 0x96 0x2f
+0x11 0xeb 0xa6 0x2f
+0x11 0xeb 0xb6 0x2f
+
+
+#------------------------------------------------------------------------------
+# CMP
+#------------------------------------------------------------------------------
+#CHECK: cmp.w r5, #65280
+#CHECK: cmp.w r4, r12
+#CHECK: cmp.w r9, r6, lsl #12
+#CHECK: cmp.w r3, r7, lsr #31
+#CHECK: cmp.w sp, r6, lsr #1
+#CHECK: cmp.w r2, r5, asr #24
+#CHECK: cmp.w r1, r4, ror #15
+
+0xb5 0xf5 0x7f 0x4f
+0xb4 0xeb 0x0c 0x0f
+0xb9 0xeb 0x06 0x3f
+0xb3 0xeb 0xd7 0x7f
+0xbd 0xeb 0x56 0x0f
+0xb2 0xeb 0x25 0x6f
+0xb1 0xeb 0xf4 0x3f
+
+
+#------------------------------------------------------------------------------
+# DBG
+#------------------------------------------------------------------------------
+#CHECK: dbg #5
+#CHECK: dbg #0
+#CHECK: dbg #15
+
+0xaf 0xf3 0xf5 0x80
+0xaf 0xf3 0xf0 0x80
+0xaf 0xf3 0xff 0x80
+
+
+#------------------------------------------------------------------------------
+# DMB
+#------------------------------------------------------------------------------
+#CHECK: dmb sy
+#CHECK: dmb st
+#CHECK: dmb ish
+#CHECK: dmb ishst
+#CHECK: dmb nsh
+#CHECK: dmb nshst
+#CHECK: dmb osh
+#CHECK: dmb oshst
+#CHECK: dmb
+
+0xbf 0xf3 0x5f 0x8f
+0xbf 0xf3 0x5e 0x8f
+0xbf 0xf3 0x5b 0x8f
+0xbf 0xf3 0x5a 0x8f
+0xbf 0xf3 0x57 0x8f
+0xbf 0xf3 0x56 0x8f
+0xbf 0xf3 0x53 0x8f
+0xbf 0xf3 0x52 0x8f
+0xbf 0xf3 0x5f 0x8f
+
+
+#------------------------------------------------------------------------------
+# DSB
+#------------------------------------------------------------------------------
+#CHECK: dsb sy
+#CHECK: dsb st
+#CHECK: dsb ish
+#CHECK: dsb ishst
+#CHECK: dsb nsh
+#CHECK: dsb nshst
+#CHECK: dsb osh
+#CHECK: dsb oshst
+
+0xbf 0xf3 0x4f 0x8f
+0xbf 0xf3 0x4e 0x8f
+0xbf 0xf3 0x4b 0x8f
+0xbf 0xf3 0x4a 0x8f
+0xbf 0xf3 0x47 0x8f
+0xbf 0xf3 0x46 0x8f
+0xbf 0xf3 0x43 0x8f
+0xbf 0xf3 0x42 0x8f
+
+
+#------------------------------------------------------------------------------
+# EOR
+#------------------------------------------------------------------------------
+#CHECK: eor r4, r5, #61440
+#CHECK: eor.w r4, r5, r6
+#CHECK: eor.w r4, r5, r6, lsl #5
+#CHECK: eor.w r4, r5, r6, lsr #5
+#CHECK: eor.w r4, r5, r6, lsr #5
+#CHECK: eor.w r4, r5, r6, asr #5
+#CHECK: eor.w r4, r5, r6, ror #5
+
+0x85 0xf4 0x70 0x44
+0x85 0xea 0x06 0x04
+0x85 0xea 0x46 0x14
+0x85 0xea 0x56 0x14
+0x85 0xea 0x56 0x14
+0x85 0xea 0x66 0x14
+0x85 0xea 0x76 0x14
+
+
+#------------------------------------------------------------------------------
+# ISB
+#------------------------------------------------------------------------------
+#CHECK: isb sy
+
+0xbf 0xf3 0x6f 0x8f
 
 #------------------------------------------------------------------------------
 # IT



From isanbard at gmail.com  Wed Sep  7 13:04:00 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 07 Sep 2011 18:04:00 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r139241 - in /llvm-gcc-4.2/trunk/gcc:
 llvm-convert.cpp llvm-internal.h
Message-ID: <20110907180400.25B1B2A6C12C@llvm.org>

Author: void
Date: Wed Sep  7 13:03:59 2011
New Revision: 139241

URL: http://llvm.org/viewvc/llvm-project?rev=139241&view=rev
Log:
Reapply r139212, but don't emit a call to llvm.eh.exception. *sigh*

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
    llvm-gcc-4.2/trunk/gcc/llvm-internal.h

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=139241&r1=139240&r2=139241&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Sep  7 13:03:59 2011
@@ -188,11 +188,8 @@
   GreatestAlignment = TheTarget->getFrameLowering()->getStackAlignment();
   SeenVLA = NULL;
 
-  CatchAll = 0;
   ExceptionValue = 0;
   ExceptionSelectorValue = 0;
-  FuncEHException = 0;
-  FuncEHSelector = 0;
   FuncEHGetTypeID = 0;
 
   assert(TheTreeToLLVM == 0 && "Reentering function creation?");
@@ -2158,31 +2155,8 @@
   ExceptionSelectorValue = CreateTemporary(Type::getInt32Ty(Context));
   ExceptionSelectorValue->setName("eh_selector");
 
-  FuncEHException = Intrinsic::getDeclaration(TheModule,
-                                              Intrinsic::eh_exception);
-  FuncEHSelector  = Intrinsic::getDeclaration(TheModule,
-                                              Intrinsic::eh_selector);
   FuncEHGetTypeID = Intrinsic::getDeclaration(TheModule,
                                               Intrinsic::eh_typeid_for);
-
-  CatchAll = TheModule->getGlobalVariable("llvm.eh.catch.all.value");
-  if (!CatchAll && lang_eh_catch_all) {
-    Constant *Init = 0;
-    tree catch_all_type = lang_eh_catch_all();
-    if (catch_all_type == NULL_TREE)
-      // Use a C++ style null catch-all object.
-      Init = Constant::getNullValue(Type::getInt8PtrTy(Context));
-    else
-      // This language has a type that catches all others.
-      Init = cast<Constant>(Emit(catch_all_type, 0));
-
-    CatchAll = new GlobalVariable(*TheModule, Init->getType(), true,
-                                  GlobalVariable::LinkOnceAnyLinkage,
-                                  Init, "llvm.eh.catch.all.value");
-    CatchAll->setUnnamedAddr(true);
-    CatchAll->setSection("llvm.metadata");
-    AttributeUsedGlobals.insert(CatchAll);
-  }
 }
 
 /// getPostPad - Return the post landing pad for the given exception handling
@@ -2205,9 +2179,10 @@
 
 /// EmitLandingPads - Emit EH landing pads.
 void TreeToLLVM::EmitLandingPads() {
-  std::vector<Value*> Args;
   std::vector<struct eh_region *> Handlers;
 
+  Type *UnwindDataTy = StructType::get(Builder.getInt8PtrTy(),
+                                       Builder.getInt32Ty(), NULL);
   for (unsigned i = 1; i < LandingPads.size(); ++i) {
     BasicBlock *LandingPad = LandingPads[i];
 
@@ -2218,18 +2193,20 @@
 
     EmitBlock(LandingPad);
 
-    // Fetch and store the exception.
-    Value *Ex = Builder.CreateCall(FuncEHException, "eh_ptr");
-    Builder.CreateStore(Ex, ExceptionValue);
-
-    // Fetch and store the exception selector.
-
     // The exception and the personality function.
-    Args.push_back(Builder.CreateLoad(ExceptionValue, "eh_ptr"));
     assert(llvm_eh_personality_libfunc
            && "no exception handling personality function!");
-    Args.push_back(BitCastToType(DECL_LLVM(llvm_eh_personality_libfunc),
-                                 Type::getInt8PtrTy(Context)));
+    LandingPadInst *LPadInst =
+      Builder.CreateLandingPad(UnwindDataTy,
+                               BitCastToType(DECL_LLVM(llvm_eh_personality_libfunc),
+                                             Type::getInt8PtrTy(Context)),
+                               0, "exc");
+
+    Value *ExcPtr = Builder.CreateExtractValue(LPadInst, 0, "exc_ptr");
+    Builder.CreateStore(ExcPtr, ExceptionValue);
+
+    Value *Select = Builder.CreateExtractValue(LPadInst, 1, "filter");
+    Builder.CreateStore(Select, ExceptionSelectorValue);
 
     // Add selections for each handler.
     foreach_reachable_handler(i, false, AddHandler, &Handlers);
@@ -2246,31 +2223,34 @@
 
       int RegionKind = classify_eh_handler(region);
       if (RegionKind < 0) {
-        // Filter - note the length.
+        // Filter.
         tree TypeList = get_eh_type_list(region);
-        unsigned Length = list_length(TypeList);
-        Args.reserve(Args.size() + Length + 1);
-        Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), Length + 1));
 
         // Add the type infos.
+        std::vector<Constant*> TypeInfos;
         for (; TypeList; TypeList = TREE_CHAIN(TypeList)) {
           tree TType = lookup_type_for_runtime(TREE_VALUE(TypeList));
-          Args.push_back(Emit(TType, 0));
+          TypeInfos.push_back(cast<Constant>(Emit(TType, 0)));
         }
+
+        // Add the list of typeinfos as a filter clause.
+        ArrayType *FilterTy = ArrayType::get(Builder.getInt8PtrTy(),
+                                             TypeInfos.size());
+        LPadInst->addClause(ConstantArray::get(FilterTy, TypeInfos));
       } else if (RegionKind > 0) {
         // Catch.
         tree TypeList = get_eh_type_list(region);
 
         if (!TypeList) {
           // Catch-all - push the catch-all object.
-          assert(CatchAll && "Language did not define lang_eh_catch_all?");
-          Args.push_back(CatchAll);
+          LPadInst->
+            addClause(Constant::getNullValue(Type::getInt8PtrTy(Context)));
           HasCatchAll = true;
         } else {
           // Add the type infos.
           for (; TypeList; TypeList = TREE_CHAIN(TypeList)) {
             tree TType = lookup_type_for_runtime(TREE_VALUE(TypeList));
-            Args.push_back(Emit(TType, 0));
+            LPadInst->addClause(Emit(TType, 0));
           }
         }
       } else {
@@ -2279,32 +2259,14 @@
       }
     }
 
-    if (can_throw_external_1(i, false)) {
-      if (HasCleanup) {
-        if (Args.size() == 2 || USING_SJLJ_EXCEPTIONS || !lang_eh_catch_all) {
-          // Insert the sentinal indicating that this is a cleanup-only
-          // selector.  It may also be the representation of a catch-all for
-          // some languages.
-          Args.push_back(ConstantInt::get(Type::getInt32Ty(Context), 0));
-        } else if (!HasCatchAll) {
-          // Some exceptions from this region may not be caught by any handler.
-          // Since invokes are required to branch to the unwind label no matter
-          // what exception is being unwound, append a catch-all.
-          assert(CatchAll && "Language did not define lang_eh_catch_all?");
-          Args.push_back(CatchAll);
-        }
-      }
-    }
+    if (can_throw_external_1(i, false) && HasCleanup)
+      LPadInst->setCleanup(true);
 
-    // Emit the selector call.
-    Value *Select = Builder.CreateCall(FuncEHSelector, Args, "eh_select");
-    Builder.CreateStore(Select, ExceptionSelectorValue);
     // Branch to the post landing pad for the first reachable handler.
     assert(!Handlers.empty() && "Landing pad but no handler?");
     Builder.CreateBr(getPostPad(get_eh_region_number(*Handlers.begin())));
 
     Handlers.clear();
-    Args.clear();
   }
 }
 
@@ -2424,29 +2386,19 @@
 
 /// EmitUnwindBlock - Emit the lazily created EH unwind block.
 void TreeToLLVM::EmitUnwindBlock() {
-  if (UnwindBB) {
-    CreateExceptionValues();
-    EmitBlock(UnwindBB);
-    // Fetch and store exception handler.
-    Value *Arg = Builder.CreateLoad(ExceptionValue, "eh_ptr");
-    assert(llvm_unwind_resume_libfunc && "no unwind resume function!");
-
-    // As we're emitting a naked call (not an expression) going through
-    // EmitCallOf would be wasteful and incorrect. Manually adjust
-    // the calling convention for this call here if necessary.
-#ifdef TARGET_ADJUST_LLVM_CC
-    tree fntype = TREE_TYPE(llvm_unwind_resume_libfunc);
-    CallingConv::ID CallingConvention = CallingConv::C;
+  if (!UnwindBB) return;
 
-    TARGET_ADJUST_LLVM_CC(CallingConvention, fntype);
-    CallInst *Call = Builder.CreateCall(DECL_LLVM(llvm_unwind_resume_libfunc),
-                                        Arg);
-    Call->setCallingConv(CallingConvention);
-#else
-    Builder.CreateCall(DECL_LLVM(llvm_unwind_resume_libfunc), Arg);
-#endif
-    Builder.CreateUnreachable();
-  }
+  CreateExceptionValues();
+  EmitBlock(UnwindBB);
+
+  Value *ExcPtr = Builder.CreateLoad(ExceptionValue, "eh_ptr");
+  Value *Filter = Builder.CreateLoad(ExceptionSelectorValue, "eh_sel");
+  Type *UnwindDataTy = StructType::get(Builder.getInt8PtrTy(),
+                                       Builder.getInt32Ty(), NULL);
+  Value *UnwindData = UndefValue::get(UnwindDataTy);
+  UnwindData = Builder.CreateInsertValue(UnwindData, ExcPtr, 0, "exc_ptr");
+  UnwindData = Builder.CreateInsertValue(UnwindData, Filter, 1, "filter");
+  Builder.CreateResume(UnwindData);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=139241&r1=139240&r2=139241&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Wed Sep  7 13:03:59 2011
@@ -317,9 +317,6 @@
   /// PostPads - The post landing pad for a given EH region.
   IndexedMap<BasicBlock *> PostPads;
 
-  /// CatchAll - Language specific catch-all object.
-  GlobalVariable *CatchAll;
-
   /// ExceptionValue - Is the local to receive the current exception.
   Value *ExceptionValue;
 
@@ -327,12 +324,6 @@
   /// selector.
   Value *ExceptionSelectorValue;
 
-  /// FuncEHException - Function used to receive the exception.
-  Function *FuncEHException;
-
-  /// FuncEHSelector - Function used to receive the exception selector.
-  Function *FuncEHSelector;
-
   /// FuncEHGetTypeID - Function used to return type id for give typeinfo.
   Function *FuncEHGetTypeID;
 



From grosbach at apple.com  Wed Sep  7 13:05:34 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 18:05:34 -0000
Subject: [llvm-commits] [llvm] r139242 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110907180534.84CCC2A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 13:05:34 2011
New Revision: 139242

URL: http://llvm.org/viewvc/llvm-project?rev=139242&view=rev
Log:
Thumb2 parsing and encoding for LDMIA.

Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139242&r1=139241&r2=139242&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Sep  7 13:05:34 2011
@@ -3339,6 +3339,17 @@
   return false;
 }
 
+// Check if the specified regisgter is in the register list of the inst,
+// starting at the indicated operand number.
+static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
+  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
+    unsigned OpReg = Inst.getOperand(i).getReg();
+    if (OpReg == Reg)
+      return true;
+  }
+  return false;
+}
+
 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
 // the ARMInsts array) instead. Getting that here requires awkward
 // API changes, though. Better way?
@@ -3430,6 +3441,11 @@
     return false;
   }
   case ARM::tLDMIA: {
+    // If we're parsing Thumb2, the .w variant is available and handles
+    // most cases that are normally illegal for a Thumb1 LDM
+    // instruction. We'll make the transformation in processInstruction()
+    // if necessary.
+    //
     // Thumb LDM instructions are writeback iff the base register is not
     // in the register list.
     unsigned Rn = Inst.getOperand(0).getReg();
@@ -3437,14 +3453,15 @@
       (static_cast<ARMOperand*>(Operands[3])->isToken() &&
        static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
     bool listContainsBase;
-    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase))
+    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
       return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
                    "registers must be in range r0-r7");
     // If we should have writeback, then there should be a '!' token.
-    if (!listContainsBase && !hasWritebackToken)
+    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
       return Error(Operands[2]->getStartLoc(),
                    "writeback operator '!' expected");
-    // Likewise, if we should not have writeback, there must not be a '!'
+    // If we should not have writeback, there must not be a '!'. This is
+    // true even for the 32-bit wide encodings.
     if (listContainsBase && hasWritebackToken)
       return Error(Operands[3]->getStartLoc(),
                    "writeback operator '!' not allowed when base register "
@@ -3452,6 +3469,13 @@
 
     break;
   }
+  case ARM::t2LDMIA_UPD: {
+    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
+      return Error(Operands[4]->getStartLoc(),
+                   "writeback operator '!' not allowed when base register "
+                   "in register list");
+    break;
+  }
   case ARM::tPOP: {
     bool listContainsBase;
     if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
@@ -3533,6 +3557,30 @@
     if (Inst.getOperand(1).getImm() == ARMCC::AL)
       Inst.setOpcode(ARM::tB);
     break;
+  case ARM::tLDMIA: {
+    // If the register list contains any high registers, or if the writeback
+    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
+    // instead if we're in Thumb2. Otherwise, this should have generated
+    // an error in validateInstruction().
+    unsigned Rn = Inst.getOperand(0).getReg();
+    bool hasWritebackToken =
+      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
+       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
+    bool listContainsBase;
+    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
+        (!listContainsBase && !hasWritebackToken) ||
+        (listContainsBase && hasWritebackToken)) {
+      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
+      assert (isThumbTwo());
+      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
+      // If we're switching to the updating version, we need to insert
+      // the writeback tied operand.
+      if (hasWritebackToken)
+        Inst.insert(Inst.begin(),
+                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
+    }
+    break;
+  }
   case ARM::t2IT: {
     // The mask bits for all but the first condition are represented as
     // the low bit of the condition code value implies 't'. We currently

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139242&r1=139241&r2=139242&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep  7 13:05:34 2011
@@ -463,6 +463,44 @@
 
 
 @------------------------------------------------------------------------------
+@ LDMIA
+ at ------------------------------------------------------------------------------
+        ldmia.w r4, {r4, r5, r8, r9}
+        ldmia.w r4, {r5, r6}
+        ldmia.w r5!, {r3, r8}
+        ldm.w r4, {r4, r5, r8, r9}
+        ldm.w r4, {r5, r6}
+        ldm.w r5!, {r3, r8}
+        ldm.w r5!, {r1, r2}
+        ldm.w r2, {r1, r2}
+
+        ldmia r4, {r4, r5, r8, r9}
+        ldmia r4, {r5, r6}
+        ldmia r5!, {r3, r8}
+        ldm r4, {r4, r5, r8, r9}
+        ldm r4, {r5, r6}
+        ldm r5!, {r3, r8}
+        ldmfd r5!, {r3, r8}
+
+@ CHECK: ldm.w	r4, {r4, r5, r8, r9}    @ encoding: [0x94,0xe8,0x30,0x03]
+@ CHECK: ldm.w	r4, {r5, r6}            @ encoding: [0x94,0xe8,0x60,0x00]
+@ CHECK: ldm.w	r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
+@ CHECK: ldm.w	r4, {r4, r5, r8, r9}    @ encoding: [0x94,0xe8,0x30,0x03]
+@ CHECK: ldm.w	r4, {r5, r6}            @ encoding: [0x94,0xe8,0x60,0x00]
+@ CHECK: ldm.w	r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
+@ CHECK: ldm.w	r5!, {r1, r2}           @ encoding: [0xb5,0xe8,0x06,0x00]
+@ CHECK: ldm.w	r2, {r1, r2}            @ encoding: [0x92,0xe8,0x06,0x00]
+
+@ CHECK: ldm.w	r4, {r4, r5, r8, r9}    @ encoding: [0x94,0xe8,0x30,0x03]
+@ CHECK: ldm.w	r4, {r5, r6}            @ encoding: [0x94,0xe8,0x60,0x00]
+@ CHECK: ldm.w	r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
+@ CHECK: ldm.w	r4, {r4, r5, r8, r9}    @ encoding: [0x94,0xe8,0x30,0x03]
+@ CHECK: ldm.w	r4, {r5, r6}            @ encoding: [0x94,0xe8,0x60,0x00]
+@ CHECK: ldm.w	r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
+@ CHECK: ldm.w	r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From eli.friedman at gmail.com  Wed Sep  7 13:13:11 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 7 Sep 2011 11:13:11 -0700
Subject: [llvm-commits] [llvm] r139242 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s
In-Reply-To: <20110907180534.84CCC2A6C12C@llvm.org>
References: <20110907180534.84CCC2A6C12C@llvm.org>
Message-ID: <CAJdarcGRT+DRS7pA8bmrLg9wu7nBsdQ4CV=x-mEH_i5DbqQXQg@mail.gmail.com>

On Wed, Sep 7, 2011 at 11:05 AM, Jim Grosbach <grosbach at apple.com> wrote:
> Author: grosbach
> Date: Wed Sep ?7 13:05:34 2011
> New Revision: 139242
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139242&view=rev
> Log:
> Thumb2 parsing and encoding for LDMIA.
>
> Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
> as match classes are insufficient to handle the context-sensitiveness of
> the writeback operand's legality for the 16-bit encodings.
>
> Modified:
> ? ?llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> ? ?llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
>
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139242&r1=139241&r2=139242&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Sep ?7 13:05:34 2011
> @@ -3339,6 +3339,17 @@
> ? return false;
> ?}
>
> +// Check if the specified regisgter is in the register list of the inst,
> +// starting at the indicated operand number.
> +static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
> + ?for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
> + ? ?unsigned OpReg = Inst.getOperand(i).getReg();
> + ? ?if (OpReg == Reg)
> + ? ? ?return true;
> + ?}
> + ?return false;
> +}
> +
> ?// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
> ?// the ARMInsts array) instead. Getting that here requires awkward
> ?// API changes, though. Better way?
> @@ -3430,6 +3441,11 @@
> ? ? return false;
> ? }
> ? case ARM::tLDMIA: {
> + ? ?// If we're parsing Thumb2, the .w variant is available and handles
> + ? ?// most cases that are normally illegal for a Thumb1 LDM
> + ? ?// instruction. We'll make the transformation in processInstruction()
> + ? ?// if necessary.
> + ? ?//
> ? ? // Thumb LDM instructions are writeback iff the base register is not
> ? ? // in the register list.
> ? ? unsigned Rn = Inst.getOperand(0).getReg();
> @@ -3437,14 +3453,15 @@
> ? ? ? (static_cast<ARMOperand*>(Operands[3])->isToken() &&
> ? ? ? ?static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
> ? ? bool listContainsBase;
> - ? ?if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase))
> + ? ?if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
> ? ? ? return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
> ? ? ? ? ? ? ? ? ? ?"registers must be in range r0-r7");
> ? ? // If we should have writeback, then there should be a '!' token.
> - ? ?if (!listContainsBase && !hasWritebackToken)
> + ? ?if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
> ? ? ? return Error(Operands[2]->getStartLoc(),
> ? ? ? ? ? ? ? ? ? ?"writeback operator '!' expected");

Does this correctly give an error for an illegal ldm.n?

-Eli

> - ? ?// Likewise, if we should not have writeback, there must not be a '!'
> + ? ?// If we should not have writeback, there must not be a '!'. This is
> + ? ?// true even for the 32-bit wide encodings.
> ? ? if (listContainsBase && hasWritebackToken)
> ? ? ? return Error(Operands[3]->getStartLoc(),
> ? ? ? ? ? ? ? ? ? ?"writeback operator '!' not allowed when base register "
> @@ -3452,6 +3469,13 @@
>
> ? ? break;
> ? }
> + ?case ARM::t2LDMIA_UPD: {
> + ? ?if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
> + ? ? ?return Error(Operands[4]->getStartLoc(),
> + ? ? ? ? ? ? ? ? ? "writeback operator '!' not allowed when base register "
> + ? ? ? ? ? ? ? ? ? "in register list");
> + ? ?break;
> + ?}
> ? case ARM::tPOP: {
> ? ? bool listContainsBase;
> ? ? if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
> @@ -3533,6 +3557,30 @@
> ? ? if (Inst.getOperand(1).getImm() == ARMCC::AL)
> ? ? ? Inst.setOpcode(ARM::tB);
> ? ? break;
> + ?case ARM::tLDMIA: {
> + ? ?// If the register list contains any high registers, or if the writeback
> + ? ?// doesn't match what tLDMIA can do, we need to use the 32-bit encoding
> + ? ?// instead if we're in Thumb2. Otherwise, this should have generated
> + ? ?// an error in validateInstruction().
> + ? ?unsigned Rn = Inst.getOperand(0).getReg();
> + ? ?bool hasWritebackToken =
> + ? ? ?(static_cast<ARMOperand*>(Operands[3])->isToken() &&
> + ? ? ? static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
> + ? ?bool listContainsBase;
> + ? ?if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
> + ? ? ? ?(!listContainsBase && !hasWritebackToken) ||
> + ? ? ? ?(listContainsBase && hasWritebackToken)) {
> + ? ? ?// 16-bit encoding isn't sufficient. Switch to the 32-bit version.
> + ? ? ?assert (isThumbTwo());
> + ? ? ?Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
> + ? ? ?// If we're switching to the updating version, we need to insert
> + ? ? ?// the writeback tied operand.
> + ? ? ?if (hasWritebackToken)
> + ? ? ? ?Inst.insert(Inst.begin(),
> + ? ? ? ? ? ? ? ? ? ?MCOperand::CreateReg(Inst.getOperand(0).getReg()));
> + ? ?}
> + ? ?break;
> + ?}
> ? case ARM::t2IT: {
> ? ? // The mask bits for all but the first condition are represented as
> ? ? // the low bit of the condition code value implies 't'. We currently
>
> Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139242&r1=139241&r2=139242&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
> +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep ?7 13:05:34 2011
> @@ -463,6 +463,44 @@
>
>
> ?@------------------------------------------------------------------------------
> +@ LDMIA
> + at ------------------------------------------------------------------------------
> + ? ? ? ?ldmia.w r4, {r4, r5, r8, r9}
> + ? ? ? ?ldmia.w r4, {r5, r6}
> + ? ? ? ?ldmia.w r5!, {r3, r8}
> + ? ? ? ?ldm.w r4, {r4, r5, r8, r9}
> + ? ? ? ?ldm.w r4, {r5, r6}
> + ? ? ? ?ldm.w r5!, {r3, r8}
> + ? ? ? ?ldm.w r5!, {r1, r2}
> + ? ? ? ?ldm.w r2, {r1, r2}
> +
> + ? ? ? ?ldmia r4, {r4, r5, r8, r9}
> + ? ? ? ?ldmia r4, {r5, r6}
> + ? ? ? ?ldmia r5!, {r3, r8}
> + ? ? ? ?ldm r4, {r4, r5, r8, r9}
> + ? ? ? ?ldm r4, {r5, r6}
> + ? ? ? ?ldm r5!, {r3, r8}
> + ? ? ? ?ldmfd r5!, {r3, r8}
> +
> +@ CHECK: ldm.w r4, {r4, r5, r8, r9} ? ?@ encoding: [0x94,0xe8,0x30,0x03]
> +@ CHECK: ldm.w r4, {r5, r6} ? ? ? ? ? ?@ encoding: [0x94,0xe8,0x60,0x00]
> +@ CHECK: ldm.w r5!, {r3, r8} ? ? ? ? ? @ encoding: [0xb5,0xe8,0x08,0x01]
> +@ CHECK: ldm.w r4, {r4, r5, r8, r9} ? ?@ encoding: [0x94,0xe8,0x30,0x03]
> +@ CHECK: ldm.w r4, {r5, r6} ? ? ? ? ? ?@ encoding: [0x94,0xe8,0x60,0x00]
> +@ CHECK: ldm.w r5!, {r3, r8} ? ? ? ? ? @ encoding: [0xb5,0xe8,0x08,0x01]
> +@ CHECK: ldm.w r5!, {r1, r2} ? ? ? ? ? @ encoding: [0xb5,0xe8,0x06,0x00]
> +@ CHECK: ldm.w r2, {r1, r2} ? ? ? ? ? ?@ encoding: [0x92,0xe8,0x06,0x00]
> +
> +@ CHECK: ldm.w r4, {r4, r5, r8, r9} ? ?@ encoding: [0x94,0xe8,0x30,0x03]
> +@ CHECK: ldm.w r4, {r5, r6} ? ? ? ? ? ?@ encoding: [0x94,0xe8,0x60,0x00]
> +@ CHECK: ldm.w r5!, {r3, r8} ? ? ? ? ? @ encoding: [0xb5,0xe8,0x08,0x01]
> +@ CHECK: ldm.w r4, {r4, r5, r8, r9} ? ?@ encoding: [0x94,0xe8,0x30,0x03]
> +@ CHECK: ldm.w r4, {r5, r6} ? ? ? ? ? ?@ encoding: [0x94,0xe8,0x60,0x00]
> +@ CHECK: ldm.w r5!, {r3, r8} ? ? ? ? ? @ encoding: [0xb5,0xe8,0x08,0x01]
> +@ CHECK: ldm.w r5!, {r3, r8} ? ? ? ? ? @ encoding: [0xb5,0xe8,0x08,0x01]
> +
> +
> + at ------------------------------------------------------------------------------
> ?@ IT
> ?@------------------------------------------------------------------------------
> ?@ Test encodings of a few full IT blocks, not just the IT instruction
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From grosbach at apple.com  Wed Sep  7 13:22:15 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 11:22:15 -0700
Subject: [llvm-commits] [llvm] r139242 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s
In-Reply-To: <CAJdarcGRT+DRS7pA8bmrLg9wu7nBsdQ4CV=x-mEH_i5DbqQXQg@mail.gmail.com>
References: <20110907180534.84CCC2A6C12C@llvm.org>
	<CAJdarcGRT+DRS7pA8bmrLg9wu7nBsdQ4CV=x-mEH_i5DbqQXQg@mail.gmail.com>
Message-ID: <E23B6227-BC9A-4608-B286-761D9039B967@apple.com>


On Sep 7, 2011, at 11:13 AM, Eli Friedman wrote:

> On Wed, Sep 7, 2011 at 11:05 AM, Jim Grosbach <grosbach at apple.com> wrote:
>> Author: grosbach
>> Date: Wed Sep  7 13:05:34 2011
>> New Revision: 139242
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=139242&view=rev
>> Log:
>> Thumb2 parsing and encoding for LDMIA.
>> 
>> Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
>> as match classes are insufficient to handle the context-sensitiveness of
>> the writeback operand's legality for the 16-bit encodings.
>> 
>> Modified:
>>    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>>    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
>> 
>> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139242&r1=139241&r2=139242&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Sep  7 13:05:34 2011
>> @@ -3339,6 +3339,17 @@
>>   return false;
>>  }
>> 
>> +// Check if the specified regisgter is in the register list of the inst,
>> +// starting at the indicated operand number.
>> +static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
>> +  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
>> +    unsigned OpReg = Inst.getOperand(i).getReg();
>> +    if (OpReg == Reg)
>> +      return true;
>> +  }
>> +  return false;
>> +}
>> +
>>  // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
>>  // the ARMInsts array) instead. Getting that here requires awkward
>>  // API changes, though. Better way?
>> @@ -3430,6 +3441,11 @@
>>     return false;
>>   }
>>   case ARM::tLDMIA: {
>> +    // If we're parsing Thumb2, the .w variant is available and handles
>> +    // most cases that are normally illegal for a Thumb1 LDM
>> +    // instruction. We'll make the transformation in processInstruction()
>> +    // if necessary.
>> +    //
>>     // Thumb LDM instructions are writeback iff the base register is not
>>     // in the register list.
>>     unsigned Rn = Inst.getOperand(0).getReg();
>> @@ -3437,14 +3453,15 @@
>>       (static_cast<ARMOperand*>(Operands[3])->isToken() &&
>>        static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
>>     bool listContainsBase;
>> -    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase))
>> +    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
>>       return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
>>                    "registers must be in range r0-r7");
>>     // If we should have writeback, then there should be a '!' token.
>> -    if (!listContainsBase && !hasWritebackToken)
>> +    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
>>       return Error(Operands[2]->getStartLoc(),
>>                    "writeback operator '!' expected");
> 
> Does this correctly give an error for an illegal ldm.n?
> 

Not yet. Correctly restricting things to 16-bit encodings via ".n" is one of the things that's on the list once I get Thumb2 parsing everything correctly w/o it. These diagnostics will be enabled even in t2 when a .n is present.

-Jim

> -Eli
> 
>> -    // Likewise, if we should not have writeback, there must not be a '!'
>> +    // If we should not have writeback, there must not be a '!'. This is
>> +    // true even for the 32-bit wide encodings.
>>     if (listContainsBase && hasWritebackToken)
>>       return Error(Operands[3]->getStartLoc(),
>>                    "writeback operator '!' not allowed when base register "
>> @@ -3452,6 +3469,13 @@
>> 
>>     break;
>>   }
>> +  case ARM::t2LDMIA_UPD: {
>> +    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
>> +      return Error(Operands[4]->getStartLoc(),
>> +                   "writeback operator '!' not allowed when base register "
>> +                   "in register list");
>> +    break;
>> +  }
>>   case ARM::tPOP: {
>>     bool listContainsBase;
>>     if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
>> @@ -3533,6 +3557,30 @@
>>     if (Inst.getOperand(1).getImm() == ARMCC::AL)
>>       Inst.setOpcode(ARM::tB);
>>     break;
>> +  case ARM::tLDMIA: {
>> +    // If the register list contains any high registers, or if the writeback
>> +    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
>> +    // instead if we're in Thumb2. Otherwise, this should have generated
>> +    // an error in validateInstruction().
>> +    unsigned Rn = Inst.getOperand(0).getReg();
>> +    bool hasWritebackToken =
>> +      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
>> +       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
>> +    bool listContainsBase;
>> +    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
>> +        (!listContainsBase && !hasWritebackToken) ||
>> +        (listContainsBase && hasWritebackToken)) {
>> +      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
>> +      assert (isThumbTwo());
>> +      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
>> +      // If we're switching to the updating version, we need to insert
>> +      // the writeback tied operand.
>> +      if (hasWritebackToken)
>> +        Inst.insert(Inst.begin(),
>> +                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
>> +    }
>> +    break;
>> +  }
>>   case ARM::t2IT: {
>>     // The mask bits for all but the first condition are represented as
>>     // the low bit of the condition code value implies 't'. We currently
>> 
>> Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139242&r1=139241&r2=139242&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
>> +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep  7 13:05:34 2011
>> @@ -463,6 +463,44 @@
>> 
>> 
>>  @------------------------------------------------------------------------------
>> +@ LDMIA
>> + at ------------------------------------------------------------------------------
>> +        ldmia.w r4, {r4, r5, r8, r9}
>> +        ldmia.w r4, {r5, r6}
>> +        ldmia.w r5!, {r3, r8}
>> +        ldm.w r4, {r4, r5, r8, r9}
>> +        ldm.w r4, {r5, r6}
>> +        ldm.w r5!, {r3, r8}
>> +        ldm.w r5!, {r1, r2}
>> +        ldm.w r2, {r1, r2}
>> +
>> +        ldmia r4, {r4, r5, r8, r9}
>> +        ldmia r4, {r5, r6}
>> +        ldmia r5!, {r3, r8}
>> +        ldm r4, {r4, r5, r8, r9}
>> +        ldm r4, {r5, r6}
>> +        ldm r5!, {r3, r8}
>> +        ldmfd r5!, {r3, r8}
>> +
>> +@ CHECK: ldm.w r4, {r4, r5, r8, r9}    @ encoding: [0x94,0xe8,0x30,0x03]
>> +@ CHECK: ldm.w r4, {r5, r6}            @ encoding: [0x94,0xe8,0x60,0x00]
>> +@ CHECK: ldm.w r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
>> +@ CHECK: ldm.w r4, {r4, r5, r8, r9}    @ encoding: [0x94,0xe8,0x30,0x03]
>> +@ CHECK: ldm.w r4, {r5, r6}            @ encoding: [0x94,0xe8,0x60,0x00]
>> +@ CHECK: ldm.w r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
>> +@ CHECK: ldm.w r5!, {r1, r2}           @ encoding: [0xb5,0xe8,0x06,0x00]
>> +@ CHECK: ldm.w r2, {r1, r2}            @ encoding: [0x92,0xe8,0x06,0x00]
>> +
>> +@ CHECK: ldm.w r4, {r4, r5, r8, r9}    @ encoding: [0x94,0xe8,0x30,0x03]
>> +@ CHECK: ldm.w r4, {r5, r6}            @ encoding: [0x94,0xe8,0x60,0x00]
>> +@ CHECK: ldm.w r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
>> +@ CHECK: ldm.w r4, {r4, r5, r8, r9}    @ encoding: [0x94,0xe8,0x30,0x03]
>> +@ CHECK: ldm.w r4, {r5, r6}            @ encoding: [0x94,0xe8,0x60,0x00]
>> +@ CHECK: ldm.w r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
>> +@ CHECK: ldm.w r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
>> +
>> +
>> + at ------------------------------------------------------------------------------
>>  @ IT
>>  @------------------------------------------------------------------------------
>>  @ Test encodings of a few full IT blocks, not just the IT instruction
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 


From grosbach at apple.com  Wed Sep  7 13:39:47 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 18:39:47 -0000
Subject: [llvm-commits] [llvm] r139243 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
Message-ID: <20110907183947.303E12A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 13:39:47 2011
New Revision: 139243

URL: http://llvm.org/viewvc/llvm-project?rev=139243&view=rev
Log:
Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix.

There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139243&r1=139242&r2=139243&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep  7 13:39:47 2011
@@ -1524,7 +1524,7 @@
   }
   def DB :
     T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
-         itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
+         itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
     bits<4>  Rn;
     bits<16> regs;
 
@@ -1539,7 +1539,7 @@
   }
   def DB_UPD :
     T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
-          itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
+          itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
     bits<4>  Rn;
     bits<16> regs;
 



From grosbach at apple.com  Wed Sep  7 13:40:06 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 18:40:06 -0000
Subject: [llvm-commits] [llvm] r139244 -
	/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
Message-ID: <20110907184006.4C3312A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 13:40:06 2011
New Revision: 139244

URL: http://llvm.org/viewvc/llvm-project?rev=139244&view=rev
Log:
Update test for 139243

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=139244&r1=139243&r2=139244&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Wed Sep  7 13:40:06 2011
@@ -143,7 +143,7 @@
 # CHECK:	vcmpe.f64	d8, #0
 0xb5 0xee 0xc0 0x8b
 
-# CHECK:	stmdb.w	sp, {r0, r2, r3, r8, r11, lr}
+# CHECK:	stmdb	sp, {r0, r2, r3, r8, r11, lr}
 0x0d 0xe9 0x0d 0x49
 
 # CHECK:	stm	r5!, {r0, r1, r2, r3, r4}



From eli.friedman at gmail.com  Wed Sep  7 13:48:32 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 07 Sep 2011 18:48:32 -0000
Subject: [llvm-commits] [llvm] r139245 - in /llvm/trunk:
 lib/Target/X86/X86InstrCompiler.td lib/Target/X86/X86MCInstLower.cpp
 test/CodeGen/X86/atomic-load-store.ll
Message-ID: <20110907184832.C7BE72A6C12C@llvm.org>

Author: efriedma
Date: Wed Sep  7 13:48:32 2011
New Revision: 139245

URL: http://llvm.org/viewvc/llvm-project?rev=139245&view=rev
Log:
Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).

This isn't exactly ideal, but it is good enough for the moment.


Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td
    llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
    llvm/trunk/test/CodeGen/X86/atomic-load-store.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=139245&r1=139244&r2=139245&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Wed Sep  7 13:48:32 2011
@@ -741,6 +741,32 @@
                 TB, LOCK;
 }
 
+def ACQUIRE_MOV8rm  : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
+                      "#ACQUIRE_MOV PSEUDO!",
+                      [(set GR8:$dst,  (atomic_load_8  addr:$src))]>;
+def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
+                      "#ACQUIRE_MOV PSEUDO!",
+                      [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
+def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
+                      "#ACQUIRE_MOV PSEUDO!",
+                      [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
+def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
+                      "#ACQUIRE_MOV PSEUDO!",
+                      [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
+
+def RELEASE_MOV8mr  : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
+                        "#RELEASE_MOV PSEUDO!",
+                        [(atomic_store_8  addr:$dst, GR8 :$src)]>;
+def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
+                        "#RELEASE_MOV PSEUDO!",
+                        [(atomic_store_16 addr:$dst, GR16:$src)]>;
+def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
+                        "#RELEASE_MOV PSEUDO!",
+                        [(atomic_store_32 addr:$dst, GR32:$src)]>;
+def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
+                        "#RELEASE_MOV PSEUDO!",
+                        [(atomic_store_64 addr:$dst, GR64:$src)]>;
+
 //===----------------------------------------------------------------------===//
 // Conditional Move Pseudo Instructions.
 //===----------------------------------------------------------------------===//
@@ -1709,17 +1735,3 @@
           (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
           (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
-
-def : Pat<(atomic_load_8 addr:$src), (MOV8rm addr:$src)>;
-def : Pat<(atomic_load_16 addr:$src), (MOV16rm addr:$src)>;
-def : Pat<(atomic_load_32 addr:$src), (MOV32rm addr:$src)>;
-def : Pat<(atomic_load_64 addr:$src), (MOV64rm addr:$src)>;
-
-def : Pat<(atomic_store_8 addr:$ptr, GR8:$val),
-          (MOV8mr addr:$ptr, GR8:$val)>;
-def : Pat<(atomic_store_16 addr:$ptr, GR16:$val),
-          (MOV16mr addr:$ptr, GR16:$val)>;
-def : Pat<(atomic_store_32 addr:$ptr, GR32:$val),
-          (MOV32mr addr:$ptr, GR32:$val)>;
-def : Pat<(atomic_store_64 addr:$ptr, GR64:$val),
-          (MOV64mr addr:$ptr, GR64:$val)>;

Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=139245&r1=139244&r2=139245&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Wed Sep  7 13:48:32 2011
@@ -469,6 +469,18 @@
   case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
   case X86::JG_4:  OutMI.setOpcode(X86::JG_1); break;
 
+  // Atomic load and store require a separate pseudo-inst because Acquire
+  // implies mayStore and Release implies mayLoad; fix these to regular MOV
+  // instructions here
+  case X86::ACQUIRE_MOV8rm:  OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
+  case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
+  case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
+  case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
+  case X86::RELEASE_MOV8mr:  OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
+  case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
+  case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
+  case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
+
   // We don't currently select the correct instruction form for instructions
   // which have a short %eax, etc. form. Handle this by custom lowering, for
   // now.

Modified: llvm/trunk/test/CodeGen/X86/atomic-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic-load-store.ll?rev=139245&r1=139244&r2=139245&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atomic-load-store.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atomic-load-store.ll Wed Sep  7 13:48:32 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -O0 | FileCheck %s
 
 define void @test1(i32* %ptr, i32 %val1) {



From stoklund at 2pi.dk  Wed Sep  7 14:07:31 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 07 Sep 2011 19:07:31 -0000
Subject: [llvm-commits] [llvm] r139247 -
	/llvm/trunk/lib/CodeGen/InlineSpiller.cpp
Message-ID: <20110907190731.B251A2A6C12C@llvm.org>

Author: stoklund
Date: Wed Sep  7 14:07:31 2011
New Revision: 139247

URL: http://llvm.org/viewvc/llvm-project?rev=139247&view=rev
Log:
Cache intermediate results during traceSiblingValue.

In some cases such as interpreters using indirectbr, the CFG can be very
complicated, and live range splitting may be forced to insert a large
number of phi-defs.  When that happens, traceSiblingValue can spend a
lot of time zipping around in the CFG looking for defs and reloads.

This patch causes more information to be cached in SibValues, and the
cached values are used to terminate searches early.  This speeds up
spilling by 20x in one interpreter test case.  For more typical code,
this is just a 10% speedup of spilling.

Modified:
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=139247&r1=139246&r2=139247&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Wed Sep  7 14:07:31 2011
@@ -17,6 +17,7 @@
 #include "LiveRangeEdit.h"
 #include "VirtRegMap.h"
 #include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/TinyPtrVector.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
 #include "llvm/CodeGen/LiveStackAnalysis.h"
@@ -75,30 +76,55 @@
   // Values that failed to remat at some point.
   SmallPtrSet<VNInfo*, 8> UsedValues;
 
+public:
   // Information about a value that was defined by a copy from a sibling
   // register.
   struct SibValueInfo {
     // True when all reaching defs were reloads: No spill is necessary.
     bool AllDefsAreReloads;
 
+    // True when value is defined by an original PHI not from splitting.
+    bool DefByOrigPHI;
+
     // The preferred register to spill.
     unsigned SpillReg;
 
     // The value of SpillReg that should be spilled.
     VNInfo *SpillVNI;
 
+    // The block where SpillVNI should be spilled. Currently, this must be the
+    // block containing SpillVNI->def.
+    MachineBasicBlock *SpillMBB;
+
     // A defining instruction that is not a sibling copy or a reload, or NULL.
     // This can be used as a template for rematerialization.
     MachineInstr *DefMI;
 
+    // List of values that depend on this one.  These values are actually the
+    // same, but live range splitting has placed them in different registers,
+    // or SSA update needed to insert PHI-defs to preserve SSA form.  This is
+    // copies of the current value and phi-kills.  Usually only phi-kills cause
+    // more than one dependent value.
+    TinyPtrVector<VNInfo*> Deps;
+
     SibValueInfo(unsigned Reg, VNInfo *VNI)
-      : AllDefsAreReloads(false), SpillReg(Reg), SpillVNI(VNI), DefMI(0) {}
+      : AllDefsAreReloads(true), DefByOrigPHI(false),
+        SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
+
+    // Returns true when a def has been found.
+    bool hasDef() const { return DefByOrigPHI || DefMI; }
   };
 
+private:
   // Values in RegsToSpill defined by sibling copies.
   typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap;
   SibValueMap SibValues;
 
+  // Values live-out from basic blocks.  This is the same as
+  // LI.getVNInfoAt(LIS.getMBBEndIdx(MBB).getPrevSlot())
+  typedef DenseMap<MachineBasicBlock*, VNInfo*> LiveOutMap;
+  LiveOutMap LiveOutValues;
+
   // Dead defs generated during spilling.
   SmallVector<MachineInstr*, 8> DeadDefs;
 
@@ -134,6 +160,7 @@
 
   bool isSibling(unsigned Reg);
   MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*);
+  void propagateSiblingValue(SibValueMap::iterator, VNInfo *VNI = 0);
   void analyzeSiblingValues();
 
   bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
@@ -282,6 +309,135 @@
            VRM.getOriginal(Reg) == Original;
 }
 
+#ifndef NDEBUG
+static raw_ostream &operator<<(raw_ostream &OS,
+                               const InlineSpiller::SibValueInfo &SVI) {
+  OS << "spill " << PrintReg(SVI.SpillReg) << ':'
+     << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def;
+  if (SVI.AllDefsAreReloads)
+    OS << " all-reloads";
+  if (SVI.DefByOrigPHI)
+    OS << " orig-phi";
+  if (SVI.DefMI)
+    OS << " def: " << *SVI.DefMI;
+  else
+    OS << '\n';
+  return OS;
+}
+#endif
+
+/// propagateSiblingValue - Propagate the value in SVI to dependents if it is
+/// known.  Otherwise remember the dependency for later.
+///
+/// @param SVI SibValues entry to propagate.
+/// @param VNI Dependent value, or NULL to propagate to all saved dependents.
+void InlineSpiller::propagateSiblingValue(SibValueMap::iterator SVI,
+                                          VNInfo *VNI) {
+  SibValueInfo &SV = SVI->second;
+
+  if (!SV.SpillMBB)
+    SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
+
+  // Should this value be propagated as a preferred spill candidate?  We don't
+  // propagate values of registers that are about to spill.
+  bool PropSpill = !isRegToSpill(SV.SpillReg);
+  unsigned SpillDepth = ~0u;
+
+  // Further values that need to be updated.
+  SmallVector<VNInfo*, 8> WorkList;
+
+  // Defer propagation if the value is not known yet.
+  if (VNI) {
+    SV.Deps.push_back(VNI);
+    // Don't propagate to other dependents than VNI. SVI hasn't changed.
+    WorkList.push_back(VNI);
+  } else {
+    // No VNI given, update all Deps.
+    WorkList.append(SV.Deps.begin(), SV.Deps.end());
+  }
+
+  // Has the value been completely determined yet?  If not, defer propagation.
+  if (!SV.hasDef())
+    return;
+
+  while (!WorkList.empty()) {
+    SibValueMap::iterator DepSVI = SibValues.find(WorkList.pop_back_val());
+    assert(DepSVI != SibValues.end() && "Dependent value not in SibValues");
+    SibValueInfo &DepSV = DepSVI->second;
+    bool Changed = false;
+
+    if (!DepSV.SpillMBB)
+      DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
+
+    // Propagate defining instruction.
+    if (!DepSV.hasDef()) {
+      Changed = true;
+      DepSV.DefMI = SV.DefMI;
+      DepSV.DefByOrigPHI = SV.DefByOrigPHI;
+    }
+
+    // Propagate AllDefsAreReloads.  For PHI values, this computes an AND of
+    // all predecessors.
+    if (!SV.AllDefsAreReloads && DepSV.AllDefsAreReloads) {
+      Changed = true;
+      DepSV.AllDefsAreReloads = false;
+    }
+
+    // Propagate best spill value.
+    if (PropSpill && SV.SpillVNI != DepSV.SpillVNI) {
+      if (SV.SpillMBB == DepSV.SpillMBB) {
+        // DepSV is in the same block.  Hoist when dominated.
+        if (SV.SpillVNI->def < DepSV.SpillVNI->def) {
+          // This is an alternative def earlier in the same MBB.
+          // Hoist the spill as far as possible in SpillMBB. This can ease
+          // register pressure:
+          //
+          //   x = def
+          //   y = use x
+          //   s = copy x
+          //
+          // Hoisting the spill of s to immediately after the def removes the
+          // interference between x and y:
+          //
+          //   x = def
+          //   spill x
+          //   y = use x<kill>
+          //
+          Changed = true;
+          DepSV.SpillReg = SV.SpillReg;
+          DepSV.SpillVNI = SV.SpillVNI;
+          DepSV.SpillMBB = SV.SpillMBB;
+        }
+      } else {
+        // DepSV is in a different block.
+        if (SpillDepth == ~0u)
+          SpillDepth = Loops.getLoopDepth(SV.SpillMBB);
+
+        // Also hoist spills to blocks with smaller loop depth, but make sure
+        // that the new value dominates.  Non-phi dependents are always
+        // dominated, phis need checking.
+        if ((Loops.getLoopDepth(DepSV.SpillMBB) > SpillDepth) &&
+            (!DepSVI->first->isPHIDef() ||
+             MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
+          Changed = true;
+          DepSV.SpillReg = SV.SpillReg;
+          DepSV.SpillVNI = SV.SpillVNI;
+          DepSV.SpillMBB = SV.SpillMBB;
+        }
+      }
+    }
+
+    if (!Changed)
+      continue;
+
+    // Something changed in DepSVI. Propagate to dependents.
+    WorkList.append(DepSV.Deps.begin(), DepSV.Deps.end());
+
+    DEBUG(dbgs() << "  update " << DepSVI->first->id << '@'
+                 << DepSVI->first->def << " to:\t" << DepSV);
+  }
+}
+
 /// traceSiblingValue - Trace a value that is about to be spilled back to the
 /// real defining instructions by looking through sibling copies. Always stay
 /// within the range of OrigVNI so the registers are known to carry the same
@@ -294,84 +450,68 @@
 ///
 MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
                                                VNInfo *OrigVNI) {
+  // Check if a cached value already exists.
+  SibValueMap::iterator SVI;
+  bool Inserted;
+  tie(SVI, Inserted) =
+    SibValues.insert(std::make_pair(UseVNI, SibValueInfo(UseReg, UseVNI)));
+  if (!Inserted) {
+    DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':'
+                 << UseVNI->id << '@' << UseVNI->def << ' ' << SVI->second);
+    return SVI->second.DefMI;
+  }
+
   DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
                << UseVNI->id << '@' << UseVNI->def << '\n');
-  SmallPtrSet<VNInfo*, 8> Visited;
+
+  // List of (Reg, VNI) that have been inserted into SibValues, but need to be
+  // processed.
   SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList;
   WorkList.push_back(std::make_pair(UseReg, UseVNI));
 
-  // Best spill candidate seen so far. This must dominate UseVNI.
-  SibValueInfo SVI(UseReg, UseVNI);
-  MachineBasicBlock *UseMBB = LIS.getMBBFromIndex(UseVNI->def);
-  MachineBasicBlock *SpillMBB = UseMBB;
-  unsigned SpillDepth = Loops.getLoopDepth(SpillMBB);
-  bool SeenOrigPHI = false; // Original PHI met.
-
   do {
     unsigned Reg;
     VNInfo *VNI;
     tie(Reg, VNI) = WorkList.pop_back_val();
-    if (!Visited.insert(VNI))
-      continue;
+    DEBUG(dbgs() << "  " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
+                 << ":\t");
 
-    // Is this value a better spill candidate?
-    if (!isRegToSpill(Reg)) {
-      MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
-      if (MBB == SpillMBB) {
-        // This is an alternative def earlier in the same MBB.
-        // Hoist the spill as far as possible in SpillMBB. This can ease
-        // register pressure:
-        //
-        //   x = def
-        //   y = use x
-        //   s = copy x
-        //
-        // Hoisting the spill of s to immediately after the def removes the
-        // interference between x and y:
-        //
-        //   x = def
-        //   spill x
-        //   y = use x<kill>
-        //
-        if (VNI->def < SVI.SpillVNI->def) {
-          DEBUG(dbgs() << "  hoist in BB#" << MBB->getNumber() << ": "
-                       << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
-                       << '\n');
-          SVI.SpillReg = Reg;
-          SVI.SpillVNI = VNI;
-        }
-      } else if (MBB != UseMBB && MDT.dominates(MBB, UseMBB)) {
-        // This is a valid spill location dominating UseVNI.
-        // Prefer to spill at a smaller loop depth.
-        unsigned Depth = Loops.getLoopDepth(MBB);
-        if (Depth < SpillDepth) {
-          DEBUG(dbgs() << "  spill depth " << Depth << ": " << PrintReg(Reg)
-                       << ':' << VNI->id << '@' << VNI->def << '\n');
-          SVI.SpillReg = Reg;
-          SVI.SpillVNI = VNI;
-          SpillMBB = MBB;
-          SpillDepth = Depth;
-        }
-      }
-    }
+    // First check if this value has already been computed.
+    SVI = SibValues.find(VNI);
+    assert(SVI != SibValues.end() && "Missing SibValues entry");
 
     // Trace through PHI-defs created by live range splitting.
     if (VNI->isPHIDef()) {
       if (VNI->def == OrigVNI->def) {
-        DEBUG(dbgs() << "  orig phi value " << PrintReg(Reg) << ':'
-                     << VNI->id << '@' << VNI->def << '\n');
-        SeenOrigPHI = true;
+        DEBUG(dbgs() << "orig phi value\n");
+        SVI->second.DefByOrigPHI = true;
+        SVI->second.AllDefsAreReloads = false;
+        propagateSiblingValue(SVI);
         continue;
       }
       // Get values live-out of predecessors.
       LiveInterval &LI = LIS.getInterval(Reg);
       MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
+      DEBUG(dbgs() << "split phi value, check " << MBB->pred_size()
+                   << " preds\n");
       for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
              PE = MBB->pred_end(); PI != PE; ++PI) {
-        VNInfo *PVNI = LI.getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
-        if (PVNI)
+        // Use a cache of block live-out values.  This is faster than using
+        // getVNInfoAt on complex intervals.
+        VNInfo *&PVNI = LiveOutValues[*PI];
+        if (!PVNI)
+          PVNI = LI.getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
+        if (!PVNI)
+          continue;
+        // Known predecessor value? Try an insertion.
+        tie(SVI, Inserted) =
+          SibValues.insert(std::make_pair(PVNI, SibValueInfo(Reg, PVNI)));
+        // This is the first time we see PVNI, add it to the worklist.
+        if (Inserted)
           WorkList.push_back(std::make_pair(Reg, PVNI));
+        propagateSiblingValue(SVI, VNI);
       }
+      // Next work list item.
       continue;
     }
 
@@ -384,46 +524,43 @@
         LiveInterval &SrcLI = LIS.getInterval(SrcReg);
         VNInfo *SrcVNI = SrcLI.getVNInfoAt(VNI->def.getUseIndex());
         assert(SrcVNI && "Copy from non-existing value");
-        DEBUG(dbgs() << "  copy of " << PrintReg(SrcReg) << ':'
+        DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':'
                      << SrcVNI->id << '@' << SrcVNI->def << '\n');
-        WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
+        // Known sibling source value? Try an insertion.
+        tie(SVI, Inserted) = SibValues.insert(std::make_pair(SrcVNI,
+                                                 SibValueInfo(SrcReg, SrcVNI)));
+        // This is the first time we see Src, add it to the worklist.
+        if (Inserted)
+          WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
+        propagateSiblingValue(SVI, VNI);
+        // Next work list item.
         continue;
       }
     }
 
     // Track reachable reloads.
+    SVI->second.DefMI = MI;
+    SVI->second.SpillMBB = MI->getParent();
     int FI;
     if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
-      DEBUG(dbgs() << "  reload " << PrintReg(Reg) << ':'
-                   << VNI->id << "@" << VNI->def << '\n');
-      SVI.AllDefsAreReloads = true;
+      DEBUG(dbgs() << "reload\n");
+      propagateSiblingValue(SVI);
+      // Next work list item.
       continue;
     }
 
-    // We have an 'original' def. Don't record trivial cases.
-    if (VNI == UseVNI) {
-      DEBUG(dbgs() << "Not a sibling copy.\n");
-      return MI;
-    }
-
     // Potential remat candidate.
-    DEBUG(dbgs() << "  def " << PrintReg(Reg) << ':'
-                 << VNI->id << '@' << VNI->def << '\t' << *MI);
-    SVI.DefMI = MI;
+    DEBUG(dbgs() << "def " << *MI);
+    SVI->second.AllDefsAreReloads = false;
+    propagateSiblingValue(SVI);
   } while (!WorkList.empty());
 
-  if (SeenOrigPHI || SVI.DefMI)
-    SVI.AllDefsAreReloads = false;
-
-  DEBUG({
-    if (SVI.AllDefsAreReloads)
-      dbgs() << "All defs are reloads.\n";
-    else
-      dbgs() << "Prefer to spill " << PrintReg(SVI.SpillReg) << ':'
-             << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def << '\n';
-  });
-  SibValues.insert(std::make_pair(UseVNI, SVI));
-  return SVI.DefMI;
+  // Look up the value we were looking for.  We already did this lokup at the
+  // top of the function, but SibValues may have been invalidated.
+  SVI = SibValues.find(UseVNI);
+  assert(SVI != SibValues.end() && "Didn't compute requested info");
+  DEBUG(dbgs() << "  traced to:\t" << SVI->second);
+  return SVI->second.DefMI;
 }
 
 /// analyzeSiblingValues - Trace values defined by sibling copies back to
@@ -432,6 +569,7 @@
 /// Keep track of values that may be rematerializable.
 void InlineSpiller::analyzeSiblingValues() {
   SibValues.clear();
+  LiveOutValues.clear();
 
   // No siblings at all?
   if (Edit->getReg() == Original)
@@ -506,6 +644,7 @@
 
   // Already spilled everywhere.
   if (SVI.AllDefsAreReloads) {
+    DEBUG(dbgs() << "\tno spill needed: " << SVI);
     ++NumOmitReloadSpill;
     return true;
   }



From james.molloy at arm.com  Wed Sep  7 14:42:28 2011
From: james.molloy at arm.com (James Molloy)
Date: Wed, 07 Sep 2011 19:42:28 -0000
Subject: [llvm-commits] [llvm] r139250 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ test/MC/Disassembler/ARM/ utils/TableGen/
Message-ID: <20110907194229.097E02A6C12C@llvm.org>

Author: jamesm
Date: Wed Sep  7 14:42:28 2011
New Revision: 139250

URL: http://llvm.org/viewvc/llvm-project?rev=139250&view=rev
Log:
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
    llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
    llvm/trunk/test/MC/Disassembler/ARM/neon.txt
    llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
    llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
    llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
    llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Sep  7 14:42:28 2011
@@ -97,6 +97,7 @@
   return false;
 }
 
+
 // Forward declare these because the autogenerated code will reference them.
 // Definitions are further down.
 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
@@ -319,6 +320,9 @@
                                              raw_ostream &os) const {
   uint8_t bytes[4];
 
+  assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
+         "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
+
   // We want to read exactly 4 bytes of data.
   if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
     Size = 0;
@@ -332,7 +336,7 @@
                   (bytes[0] <<  0);
 
   // Calling the auto-generated decoder function.
-  DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
+  DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
     return result;
@@ -342,7 +346,7 @@
   // FIXME: This shouldn't really exist.  It's an artifact of the
   // fact that we fail to encode a few instructions properly for Thumb.
   MI.clear();
-  result = decodeCommonInstruction32(MI, insn, Address, this);
+  result = decodeCommonInstruction32(MI, insn, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
     return result;
@@ -351,14 +355,14 @@
   // VFP and NEON instructions, similarly, are shared between ARM
   // and Thumb modes.
   MI.clear();
-  result = decodeVFPInstruction32(MI, insn, Address, this);
+  result = decodeVFPInstruction32(MI, insn, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
     return result;
   }
 
   MI.clear();
-  result = decodeNEONDataInstruction32(MI, insn, Address, this);
+  result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
     // Add a fake predicate operand, because we share these instruction
@@ -369,7 +373,7 @@
   }
 
   MI.clear();
-  result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
+  result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
     // Add a fake predicate operand, because we share these instruction
@@ -380,7 +384,7 @@
   }
 
   MI.clear();
-  result = decodeNEONDupInstruction32(MI, insn, Address, this);
+  result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
     // Add a fake predicate operand, because we share these instruction
@@ -505,6 +509,9 @@
                                                raw_ostream &os) const {
   uint8_t bytes[4];
 
+  assert((STI.getFeatureBits() & ARM::ModeThumb) &&
+         "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
+
   // We want to read exactly 2 bytes of data.
   if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
     Size = 0;
@@ -512,7 +519,7 @@
   }
 
   uint16_t insn16 = (bytes[1] << 8) | bytes[0];
-  DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
+  DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 2;
     AddThumbPredicate(MI);
@@ -520,7 +527,7 @@
   }
 
   MI.clear();
-  result = decodeThumbSBitInstruction16(MI, insn16, Address, this);
+  result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
   if (result) {
     Size = 2;
     bool InITBlock = !ITBlock.empty();
@@ -530,7 +537,7 @@
   }
 
   MI.clear();
-  result = decodeThumb2Instruction16(MI, insn16, Address, this);
+  result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 2;
     AddThumbPredicate(MI);
@@ -570,7 +577,7 @@
                     (bytes[1] << 24) |
                     (bytes[0] << 16);
   MI.clear();
-  result = decodeThumbInstruction32(MI, insn32, Address, this);
+  result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
     bool InITBlock = ITBlock.size();
@@ -580,7 +587,7 @@
   }
 
   MI.clear();
-  result = decodeThumb2Instruction32(MI, insn32, Address, this);
+  result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
     AddThumbPredicate(MI);
@@ -588,7 +595,7 @@
   }
 
   MI.clear();
-  result = decodeCommonInstruction32(MI, insn32, Address, this);
+  result = decodeCommonInstruction32(MI, insn32, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
     AddThumbPredicate(MI);
@@ -596,7 +603,7 @@
   }
 
   MI.clear();
-  result = decodeVFPInstruction32(MI, insn32, Address, this);
+  result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
     UpdateThumbVFPPredicate(MI);
@@ -604,7 +611,7 @@
   }
 
   MI.clear();
-  result = decodeNEONDupInstruction32(MI, insn32, Address, this);
+  result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
     AddThumbPredicate(MI);
@@ -616,7 +623,7 @@
     uint32_t NEONLdStInsn = insn32;
     NEONLdStInsn &= 0xF0FFFFFF;
     NEONLdStInsn |= 0x04000000;
-    result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
+    result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
     if (result != MCDisassembler::Fail) {
       Size = 4;
       AddThumbPredicate(MI);
@@ -630,7 +637,7 @@
     NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
     NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
     NEONDataInsn |= 0x12000000; // Set bits 28 and 25
-    result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
+    result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
     if (result != MCDisassembler::Fail) {
       Size = 4;
       AddThumbPredicate(MI);

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mattr +mp | FileCheck %s
 
 # CHECK:	addpl	r4, pc, #318767104
 0x4c 0x45 0x8f 0x52

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding}
 # XFAIL: *
 
 # Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding}
 # XFAIL: *
 
 # Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30)

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding}
 # XFAIL: *
 
 # Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding}
 # XFAIL: *
 
 # Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding}
 # XFAIL: *
 
 # Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25)

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding}
 # XFAIL: *
 
 # Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25)

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding}
 # XFAIL: *
 
 # Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25)

Modified: llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 | FileCheck %s
 
 # CHECK:	vbif	q15, q7, q0
 0x50 0xe1 0x7e 0xf3

Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple armv7-unknown-unknown -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple armv7-unknown-unknown -disassemble -mattr +fp16 < %s | FileCheck %s
 
 0x20 0x03 0xf1 0xf3
 # CHECK: vabs.s8	d16, d16

Modified: llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neont2.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neont2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neont2.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple thumbv7-unknown-unknown -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple thumbv7-unknown-unknown -disassemble -mattr +fp16 < %s | FileCheck %s
 
 0xf1 0xff 0x20 0x03
 # CHECK: vabs.s8	d16, d16

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 | FileCheck %s
 
 # CHECK:	push	{r0, r1, r2, r3}
 # CHECK-NEXT:	push	{r4, r5, r7, lr}

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Wed Sep  7 14:42:28 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mattr +t2xtpk,+mp | FileCheck %s
 
 # CHECK:	add	r5, sp, #68
 0x11 0xad
@@ -218,8 +218,11 @@
 # CHECK:	pld	[r5, #30]
 0x95 0xf8 0x1e 0xf0
 
-# CHECK:	stc2	p12, cr15, [r9], {137}
-0x89 0xfc 0x89 0xfc
+# Test disabled as it was originally checking for
+# the ARM encoding of stc2, and thumb2 stc2 is
+# not implemented yet.
+# CHECK-:	stc2	p12, cr15, [r9], {137}
+#0x89 0xfc 0x89 0xfc
 
 # CHECK:	vmov	r1, r0, d11
 0x50 0xec 0x1b 0x1b

Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp Wed Sep  7 14:42:28 2011
@@ -132,11 +132,12 @@
   if (Target.getName() == "ARM" ||
       Target.getName() == "Thumb") {
     FixedLenDecoderEmitter(Records,
+                           "ARM",
                            "if (!Check(S, ", ")) return MCDisassembler::Fail;",
                            "S", "MCDisassembler::Fail",
-                           "MCDisassembler::DecodeStatus S = MCDisassembler::Success;\n(void)S;").run(OS);
+                           "  MCDisassembler::DecodeStatus S = MCDisassembler::Success;\n(void)S;").run(OS);
     return;
   }
 
-  FixedLenDecoderEmitter(Records).run(OS);
+  FixedLenDecoderEmitter(Records, Target.getName()).run(OS);
 }

Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Wed Sep  7 14:42:28 2011
@@ -330,6 +330,10 @@
       std::vector<unsigned> &EndBits, std::vector<uint64_t> &FieldVals,
       insn_t &Insn);
 
+  // Emits code to check the Predicates member of an instruction are true.
+  // Returns true if predicate matches were emitted, false otherwise.
+  bool emitPredicateMatch(raw_ostream &o, unsigned &Indentation,unsigned Opc);
+
   // Emits code to decode the singleton.  Return true if we have matched all the
   // well-known bits.
   bool emitSingletonDecoder(raw_ostream &o, unsigned &Indentation,unsigned Opc);
@@ -571,8 +575,9 @@
   o.indent(Indentation) <<
     "static MCDisassembler::DecodeStatus decode" << Namespace << "Instruction" << BitWidth
     << "(MCInst &MI, uint" << BitWidth << "_t insn, uint64_t Address, "
-    << "const void *Decoder) {\n";
+    << "const void *Decoder, const MCSubtargetInfo &STI) {\n";
   o.indent(Indentation) << "  unsigned tmp = 0;\n  (void)tmp;\n" << Emitter->Locals << "\n";
+  o.indent(Indentation) << "  unsigned Bits = STI.getFeatureBits();\n";
 
   ++Indentation; ++Indentation;
   // Emits code to decode the instructions.
@@ -757,6 +762,43 @@
 
 }
 
+static void emitSinglePredicateMatch(raw_ostream &o, StringRef str,
+                                     std::string PredicateNamespace) {
+  const char *X = str.str().c_str();
+  if (X[0] == '!')
+    o << "!(Bits & " << PredicateNamespace << "::" << &X[1] << ")";
+  else
+    o << "(Bits & " << PredicateNamespace << "::" << X << ")";
+}
+
+bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation,
+                                           unsigned Opc) {
+  ListInit *Predicates = AllInstructions[Opc]->TheDef->getValueAsListInit("Predicates");
+  for (unsigned i = 0; i < Predicates->getSize(); ++i) {
+    Record *Pred = Predicates->getElementAsRecord(i);
+    if (!Pred->getValue("AssemblerMatcherPredicate"))
+      continue;
+
+    std::string P = Pred->getValueAsString("AssemblerCondString");
+
+    if (!P.length())
+      continue;
+
+    if (i != 0)
+      o << " && ";
+
+    StringRef SR(P);
+    std::pair<StringRef, StringRef> pairs = SR.split(',');
+    while (pairs.second.size()) {
+      emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace);
+      o << " && ";
+      pairs = pairs.second.split(',');
+    }
+    emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace);
+  }
+  return Predicates->getSize() > 0;
+}  
+
 // Emits code to decode the singleton.  Return true if we have matched all the
 // well-known bits.
 bool FilterChooser::emitSingletonDecoder(raw_ostream &o, unsigned &Indentation,
@@ -775,7 +817,9 @@
 
   // If we have matched all the well-known bits, just issue a return.
   if (Size == 0) {
-    o.indent(Indentation) << "{\n";
+    o.indent(Indentation) << "if (";
+    emitPredicateMatch(o, Indentation, Opc);
+    o << ") {\n";
     o.indent(Indentation) << "  MI.setOpcode(" << Opc << ");\n";
     std::vector<OperandInfo>& InsnOperands = Operands[Opc];
     for (std::vector<OperandInfo>::iterator
@@ -792,7 +836,7 @@
 
     o.indent(Indentation) << "  return " << Emitter->ReturnOK << "; // " << nameWithID(Opc)
                           << '\n';
-    o.indent(Indentation) << "}\n";
+    o.indent(Indentation) << "}\n"; // Closing predicate block.
     return true;
   }
 
@@ -804,12 +848,16 @@
   for (I = Size; I != 0; --I) {
     o << "Inst{" << EndBits[I-1] << '-' << StartBits[I-1] << "} ";
     if (I > 1)
-      o << "&& ";
+      o << " && ";
     else
       o << "for singleton decoding...\n";
   }
 
   o.indent(Indentation) << "if (";
+  if (emitPredicateMatch(o, Indentation, Opc) > 0) {
+    o << " &&\n";
+    o.indent(Indentation+4);
+  }
 
   for (I = Size; I != 0; --I) {
     NumBits = EndBits[I-1] - StartBits[I-1] + 1;

Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h?rev=139250&r1=139249&r2=139250&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h (original)
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h Wed Sep  7 14:42:28 2011
@@ -50,6 +50,7 @@
 class FixedLenDecoderEmitter : public TableGenBackend {
 public:
   FixedLenDecoderEmitter(RecordKeeper &R,
+                         std::string PredicateNamespace,
                          std::string GPrefix  = "if (",
                          std::string GPostfix = " == MCDisassembler::Fail) return MCDisassembler::Fail;",
                          std::string ROK      = "MCDisassembler::Success",
@@ -57,6 +58,7 @@
                          std::string L        = "") :
     Records(R), Target(R),
     NumberedInstructions(Target.getInstructionsByEnumValue()),
+    PredicateNamespace(PredicateNamespace),
     GuardPrefix(GPrefix), GuardPostfix(GPostfix),
     ReturnOK(ROK), ReturnFail(RFail), Locals(L) {}
 
@@ -70,6 +72,7 @@
   std::vector<unsigned> Opcodes;
   std::map<unsigned, std::vector<OperandInfo> > Operands;
 public:
+  std::string PredicateNamespace;
   std::string GuardPrefix, GuardPostfix;
   std::string ReturnOK, ReturnFail;
   std::string Locals;



From grosbach at apple.com  Wed Sep  7 14:57:53 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 19:57:53 -0000
Subject: [llvm-commits] [llvm] r139251 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110907195753.99F602A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 14:57:53 2011
New Revision: 139251

URL: http://llvm.org/viewvc/llvm-project?rev=139251&view=rev
Log:
Thumb2 parsing and encoding for LDMDB.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139251&r1=139250&r2=139251&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Sep  7 14:57:53 2011
@@ -4907,6 +4907,7 @@
 // Load / Store Multiple
 def : MnemonicAlias<"ldmfd", "ldm">;
 def : MnemonicAlias<"ldmia", "ldm">;
+def : MnemonicAlias<"ldmea", "ldmdb">;
 def : MnemonicAlias<"stmfd", "stmdb">;
 def : MnemonicAlias<"stmia", "stm">;
 def : MnemonicAlias<"stmea", "stm">;

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139251&r1=139250&r2=139251&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep  7 14:57:53 2011
@@ -501,6 +501,20 @@
 
 
 @------------------------------------------------------------------------------
+@ LDMDB
+ at ------------------------------------------------------------------------------
+        ldmdb r4, {r4, r5, r8, r9}
+        ldmdb r4, {r5, r6}
+        ldmdb r5!, {r3, r8}
+        ldmea r5!, {r3, r8}
+
+@ CHECK: ldmdb	r4, {r4, r5, r8, r9}    @ encoding: [0x14,0xe9,0x30,0x03]
+@ CHECK: ldmdb	r4, {r5, r6}            @ encoding: [0x14,0xe9,0x60,0x00]
+@ CHECK: ldmdb	r5!, {r3, r8}           @ encoding: [0x35,0xe9,0x08,0x01]
+@ CHECK: ldmdb	r5!, {r3, r8}           @ encoding: [0x35,0xe9,0x08,0x01]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From resistor at me.com  Wed Sep  7 15:11:24 2011
From: resistor at me.com (Owen Anderson)
Date: Wed, 07 Sep 2011 13:11:24 -0700
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and
	resolve	(safe) ambiguous instruction encodings
In-Reply-To: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>
References: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>
Message-ID: <53D05C9F-E666-48AA-9150-67E78A720ED0@me.com>

Patch 2 is fine as well, but please add a decoding test for the M-class msr/mrs encodings.

--Owen

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:

> Hi,
> 
> The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M series
> not allowing the correct mask names.
> 
> The patch becomes difficult because:
>  * There is no way to determine in the InstPrinter any subtarget specific
> features (such as "operating on an m-class core?").
>  * There is currently no subtarget feature for "M-class core?"; the nearest is
> IsThumb2 && !HasARM.
>  * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
> a way that makes them deterministically separable. This causes non-conflicting
> ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
> both code paths are emitted but only one will ever be hit.
> 
> The solution is:
>  * Add subtarget info to InstPrinter so it can determine what to do with the
> mask immediate.
>  * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
> IsARClass == !IsMClass. This feature only has semantic sense on v6+
> architectures.
>  * The conflicts occur because the FixedLenDecoderEmitter does not honour the
> Predicates field of instructions in the tablegen description. If the island
> checking also checked the AssemblerPredicates field (if defined), ambiguous
> instruction encodings that are disambiguated by predicates would (do) work fine.
> 
> The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and MCDisassembler.
> They can use this (in patch #2) to determine what mask names to accept (primask?
> or cpsr_zxvf?)
> 
> The second enhances FixedLenPredicateEncoder to emit predicate checks for
> instructions before it accepts an encoding - this allows ambiguous instructions
> to be disambiguated by the Predicates field in TableGen. This required changing
> llvm-mc to accept -mattr, and tests to set the correct features they rely upon.
> 
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
> is created.**
> 
> The third patch adds a new predicate "IsMClass" along with its counterpart
> "IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
> Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
> encodings respectively. It also fixes mask printing for MRS/MSR in the
> ARMMCInstPrinter and ARMMCAsmParser.
> 
> Testcases added with the final patch.
> 
> Comments? Is it OK?
> 
> Cheers,
> 
> James
> 
> [N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout myself
> after review]
> <patch0-add-sti-to-instprinter.patch><patch1-modify-fixedlendecoderemitter.patch><patch2-fix-msr-mrs.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From James.Molloy at arm.com  Wed Sep  7 15:29:06 2011
From: James.Molloy at arm.com (James Molloy)
Date: Wed, 7 Sep 2011 21:29:06 +0100
Subject: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and
	resolve	(safe) ambiguous instruction encodings
In-Reply-To: <53D05C9F-E666-48AA-9150-67E78A720ED0@me.com>
References: <005a01cc6986$58d21980$0a764c80$%molloy@arm.com>,
	<53D05C9F-E666-48AA-9150-67E78A720ED0@me.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA473757133E3@GEORGE.Emea.Arm.com>

Will do, thanks!
________________________________________
From: Owen Anderson [resistor at me.com]
Sent: 07 September 2011 21:11
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve      (safe) ambiguous instruction encodings

Patch 2 is fine as well, but please add a decoding test for the M-class msr/mrs encodings.

--Owen

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:

> Hi,
>
> The attached three patches fix Kurt Lidl's problem of MRS/MSR on Cortex-M series
> not allowing the correct mask names.
>
> The patch becomes difficult because:
>  * There is no way to determine in the InstPrinter any subtarget specific
> features (such as "operating on an m-class core?").
>  * There is currently no subtarget feature for "M-class core?"; the nearest is
> IsThumb2 && !HasARM.
>  * The encoding for M-class (v{6,7}m) MSR/MRS differs from v{6,7}ar, but not in
> a way that makes them deterministically separable. This causes non-conflicting
> ambiguity between the M and AR class insns in the FixedLenDecoderEmitter where
> both code paths are emitted but only one will ever be hit.
>
> The solution is:
>  * Add subtarget info to InstPrinter so it can determine what to do with the
> mask immediate.
>  * Add a new SubtargetFeature "IsMClass" which is true on v{6,7}m. The inverse
> IsARClass == !IsMClass. This feature only has semantic sense on v6+
> architectures.
>  * The conflicts occur because the FixedLenDecoderEmitter does not honour the
> Predicates field of instructions in the tablegen description. If the island
> checking also checked the AssemblerPredicates field (if defined), ambiguous
> instruction encodings that are disambiguated by predicates would (do) work fine.
>
> The first patch (#0) adds a MCSubtargetInfo to MCInstPrinter and MCDisassembler.
> They can use this (in patch #2) to determine what mask names to accept (primask?
> or cpsr_zxvf?)
>
> The second enhances FixedLenPredicateEncoder to emit predicate checks for
> instructions before it accepts an encoding - this allows ambiguous instructions
> to be disambiguated by the Predicates field in TableGen. This required changing
> llvm-mc to accept -mattr, and tests to set the correct features they rely upon.
>
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
> is created.**
>
> The third patch adds a new predicate "IsMClass" along with its counterpart
> "IsARClass = !IsMClass". The T2 MRS instruction is duplicated; one
> Requires<[IsMClass]> the other Requires<[IsARClass]> with their differing
> encodings respectively. It also fixes mask printing for MRS/MSR in the
> ARMMCInstPrinter and ARMMCAsmParser.
>
> Testcases added with the final patch.
>
> Comments? Is it OK?
>
> Cheers,
>
> James
>
> [N.B.: Patch was against ToT~3 days, so I'll deal with any merge fallout myself
> after review]
> <patch0-add-sti-to-instprinter.patch><patch1-modify-fixedlendecoderemitter.patch><patch2-fix-msr-mrs.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.



From grosbach at apple.com  Wed Sep  7 15:58:58 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 20:58:58 -0000
Subject: [llvm-commits] [llvm] r139254 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 utils/TableGen/EDEmitter.cpp
Message-ID: <20110907205858.2DA6E2A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 15:58:57 2011
New Revision: 139254

URL: http://llvm.org/viewvc/llvm-project?rev=139254&view=rev
Log:
Thumb2 parsing and encoding for LDR(immediate).

The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139254&r1=139253&r2=139254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep  7 15:58:57 2011
@@ -101,11 +101,13 @@
 // Define Thumb2 specific addressing modes.
 
 // t2addrmode_imm12  := reg + imm12
+def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
 def t2addrmode_imm12 : Operand<i32>,
                        ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
   let PrintMethod = "printAddrModeImm12Operand";
   let EncoderMethod = "getAddrModeImm12OpValue";
   let DecoderMethod = "DecodeT2AddrModeImm12";
+  let ParserMatchClass = t2addrmode_imm12_asmoperand;
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
 }
 
@@ -121,6 +123,17 @@
 }
 
 
+// t2addrmode_negimm8  := reg - imm8
+def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
+def t2addrmode_negimm8 : Operand<i32>,
+                      ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
+  let PrintMethod = "printT2AddrModeImm8Operand";
+  let EncoderMethod = "getT2AddrModeImm8OpValue";
+  let DecoderMethod = "DecodeT2AddrModeImm8";
+  let ParserMatchClass = MemNegImm8OffsetAsmOperand;
+  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
+}
+
 // t2addrmode_imm8  := reg +/- imm8
 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
 def t2addrmode_imm8 : Operand<i32>,
@@ -880,42 +893,35 @@
   def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
                    opc, ".w\t$Rt, $addr",
                    [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
-    let Inst{31-27} = 0b11111;
-    let Inst{26-25} = 0b00;
+    bits<4> Rt;
+    bits<17> addr;
+    let Inst{31-25} = 0b1111100;
     let Inst{24} = signed;
     let Inst{23} = 1;
     let Inst{22-21} = opcod;
     let Inst{20} = 1; // load
-
-    bits<4> Rt;
-    let Inst{15-12} = Rt;
-
-    bits<17> addr;
-    let addr{12}    = 1;           // add = TRUE
     let Inst{19-16} = addr{16-13}; // Rn
-    let Inst{23}    = addr{12};    // U
+    let Inst{15-12} = Rt;
     let Inst{11-0}  = addr{11-0};  // imm
   }
-  def i8  : T2Ii8 <(outs target:$Rt), (ins t2addrmode_imm8:$addr), iii,
+  def i8  : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
                    opc, "\t$Rt, $addr",
-                   [(set target:$Rt, (opnode t2addrmode_imm8:$addr))]> {
+                   [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
+    bits<4> Rt;
+    bits<13> addr;
     let Inst{31-27} = 0b11111;
     let Inst{26-25} = 0b00;
     let Inst{24} = signed;
     let Inst{23} = 0;
     let Inst{22-21} = opcod;
     let Inst{20} = 1; // load
+    let Inst{19-16} = addr{12-9}; // Rn
+    let Inst{15-12} = Rt;
     let Inst{11} = 1;
     // Offset: index==TRUE, wback==FALSE
     let Inst{10} = 1; // The P bit.
-    let Inst{8} = 0; // The W bit.
-
-    bits<4> Rt;
-    let Inst{15-12} = Rt;
-
-    bits<13> addr;
-    let Inst{19-16} = addr{12-9}; // Rn
     let Inst{9}     = addr{8};    // U
+    let Inst{8} = 0; // The W bit.
     let Inst{7-0}   = addr{7-0};  // imm
   }
   def s   : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
@@ -980,9 +986,9 @@
     let Inst{23}    = addr{12};    // U
     let Inst{11-0}  = addr{11-0};  // imm
   }
-  def i8  : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_imm8:$addr), iii,
+  def i8  : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
                    opc, "\t$Rt, $addr",
-                   [(opnode target:$Rt, t2addrmode_imm8:$addr)]> {
+                   [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0000;
     let Inst{22-21} = opcod;
@@ -1181,8 +1187,8 @@
 // zextload i1 -> zextload i8
 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
             (t2LDRBi12  t2addrmode_imm12:$addr)>;
-def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
-            (t2LDRBi8   t2addrmode_imm8:$addr)>;
+def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
+            (t2LDRBi8   t2addrmode_negimm8:$addr)>;
 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
             (t2LDRBs    t2addrmode_so_reg:$addr)>;
 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
@@ -1193,8 +1199,8 @@
 // earlier?
 def : T2Pat<(extloadi1  t2addrmode_imm12:$addr),
             (t2LDRBi12  t2addrmode_imm12:$addr)>;
-def : T2Pat<(extloadi1  t2addrmode_imm8:$addr),
-            (t2LDRBi8   t2addrmode_imm8:$addr)>;
+def : T2Pat<(extloadi1  t2addrmode_negimm8:$addr),
+            (t2LDRBi8   t2addrmode_negimm8:$addr)>;
 def : T2Pat<(extloadi1  t2addrmode_so_reg:$addr),
             (t2LDRBs    t2addrmode_so_reg:$addr)>;
 def : T2Pat<(extloadi1  (ARMWrapper tconstpool:$addr)),
@@ -1202,8 +1208,8 @@
 
 def : T2Pat<(extloadi8  t2addrmode_imm12:$addr),
             (t2LDRBi12  t2addrmode_imm12:$addr)>;
-def : T2Pat<(extloadi8  t2addrmode_imm8:$addr),
-            (t2LDRBi8   t2addrmode_imm8:$addr)>;
+def : T2Pat<(extloadi8  t2addrmode_negimm8:$addr),
+            (t2LDRBi8   t2addrmode_negimm8:$addr)>;
 def : T2Pat<(extloadi8  t2addrmode_so_reg:$addr),
             (t2LDRBs    t2addrmode_so_reg:$addr)>;
 def : T2Pat<(extloadi8  (ARMWrapper tconstpool:$addr)),
@@ -1211,8 +1217,8 @@
 
 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
             (t2LDRHi12  t2addrmode_imm12:$addr)>;
-def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
-            (t2LDRHi8   t2addrmode_imm8:$addr)>;
+def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
+            (t2LDRHi8   t2addrmode_negimm8:$addr)>;
 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
             (t2LDRHs    t2addrmode_so_reg:$addr)>;
 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
@@ -1444,9 +1450,9 @@
     let Inst{11-0}  = addr{11-0};  // imm12
   }
 
-  def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
+  def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
                 "\t$addr",
-               [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
+            [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
     let Inst{31-25} = 0b1111100;
     let Inst{24} = instr;
     let Inst{23} = 0; // U = 0
@@ -3514,38 +3520,38 @@
 // Atomic load/store patterns
 def : T2Pat<(atomic_load_8   t2addrmode_imm12:$addr),
             (t2LDRBi12  t2addrmode_imm12:$addr)>;
-def : T2Pat<(atomic_load_8   t2addrmode_imm8:$addr),
-            (t2LDRBi8   t2addrmode_imm8:$addr)>;
+def : T2Pat<(atomic_load_8   t2addrmode_negimm8:$addr),
+            (t2LDRBi8   t2addrmode_negimm8:$addr)>;
 def : T2Pat<(atomic_load_8   t2addrmode_so_reg:$addr),
             (t2LDRBs    t2addrmode_so_reg:$addr)>;
 def : T2Pat<(atomic_load_16  t2addrmode_imm12:$addr),
             (t2LDRHi12  t2addrmode_imm12:$addr)>;
-def : T2Pat<(atomic_load_16  t2addrmode_imm8:$addr),
-            (t2LDRHi8   t2addrmode_imm8:$addr)>;
+def : T2Pat<(atomic_load_16  t2addrmode_negimm8:$addr),
+            (t2LDRHi8   t2addrmode_negimm8:$addr)>;
 def : T2Pat<(atomic_load_16  t2addrmode_so_reg:$addr),
             (t2LDRHs    t2addrmode_so_reg:$addr)>;
 def : T2Pat<(atomic_load_32  t2addrmode_imm12:$addr),
             (t2LDRi12   t2addrmode_imm12:$addr)>;
-def : T2Pat<(atomic_load_32  t2addrmode_imm8:$addr),
-            (t2LDRi8    t2addrmode_imm8:$addr)>;
+def : T2Pat<(atomic_load_32  t2addrmode_negimm8:$addr),
+            (t2LDRi8    t2addrmode_negimm8:$addr)>;
 def : T2Pat<(atomic_load_32  t2addrmode_so_reg:$addr),
             (t2LDRs     t2addrmode_so_reg:$addr)>;
 def : T2Pat<(atomic_store_8  t2addrmode_imm12:$addr, GPR:$val),
             (t2STRBi12  GPR:$val, t2addrmode_imm12:$addr)>;
-def : T2Pat<(atomic_store_8  t2addrmode_imm8:$addr, GPR:$val),
-            (t2STRBi8   GPR:$val, t2addrmode_imm8:$addr)>;
+def : T2Pat<(atomic_store_8  t2addrmode_negimm8:$addr, GPR:$val),
+            (t2STRBi8   GPR:$val, t2addrmode_negimm8:$addr)>;
 def : T2Pat<(atomic_store_8  t2addrmode_so_reg:$addr, GPR:$val),
             (t2STRBs    GPR:$val, t2addrmode_so_reg:$addr)>;
 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
             (t2STRHi12  GPR:$val, t2addrmode_imm12:$addr)>;
-def : T2Pat<(atomic_store_16 t2addrmode_imm8:$addr, GPR:$val),
-            (t2STRHi8   GPR:$val, t2addrmode_imm8:$addr)>;
+def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
+            (t2STRHi8   GPR:$val, t2addrmode_negimm8:$addr)>;
 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
             (t2STRHs    GPR:$val, t2addrmode_so_reg:$addr)>;
 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
             (t2STRi12   GPR:$val, t2addrmode_imm12:$addr)>;
-def : T2Pat<(atomic_store_32 t2addrmode_imm8:$addr, GPR:$val),
-            (t2STRi8    GPR:$val, t2addrmode_imm8:$addr)>;
+def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
+            (t2STRi8    GPR:$val, t2addrmode_negimm8:$addr)>;
 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
             (t2STRs     GPR:$val, t2addrmode_so_reg:$addr)>;
 
@@ -3591,3 +3597,7 @@
 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
+
+// Alias for LDRi12 without the ".w" optional width specifier.
+def : t2InstAlias<"ldr${p} $Rd, $addr",
+                  (t2LDRi12 GPR:$Rd, t2addrmode_imm12:$addr, pred:$p)>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139254&r1=139253&r2=139254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Sep  7 15:58:57 2011
@@ -732,6 +732,28 @@
     int64_t Val = Mem.OffsetImm->getValue();
     return Val > -256 && Val < 256;
   }
+  bool isMemNegImm8Offset() const {
+    if (Kind != Memory || Mem.OffsetRegNum != 0)
+      return false;
+    // Immediate offset in range [-255, -1].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return Val > -256 && Val < 0;
+  }
+  bool isMemUImm12Offset() const {
+    // If we have an immediate that's not a constant, treat it as a label
+    // reference needing a fixup. If it is a constant, it's something else
+    // and we reject it.
+    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
+      return true;
+
+    if (Kind != Memory || Mem.OffsetRegNum != 0)
+      return false;
+    // Immediate offset in range [0, 4095].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return (Val >= 0 && Val < 4096);
+  }
   bool isMemImm12Offset() const {
     // If we have an immediate that's not a constant, treat it as a label
     // reference needing a fixup. If it is a constant, it's something else
@@ -1077,6 +1099,28 @@
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
+  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Val));
+  }
+
+  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    // If this is an immediate, it's a label reference.
+    if (Kind == Immediate) {
+      addExpr(Inst, getImm());
+      Inst.addOperand(MCOperand::CreateImm(0));
+      return;
+    }
+
+    // Otherwise, it's a normal memory reg+offset.
+    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Val));
+  }
+
   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     // If this is an immediate, it's a label reference.

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=139254&r1=139253&r2=139254&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Wed Sep  7 15:58:57 2011
@@ -666,6 +666,7 @@
   MISC("spr_reglist", "kOperandTypeARMSPRRegisterList");          // I, R, ...
   MISC("it_mask", "kOperandTypeThumbITMask");                     // I
   MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg");        // R
+  MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8");   // R, I
   MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8");      // R, I
   MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
   MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12");    // R, I



From grosbach at apple.com  Wed Sep  7 16:06:46 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 21:06:46 -0000
Subject: [llvm-commits] [llvm] r139255 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110907210646.B20BC2A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 16:06:46 2011
New Revision: 139255

URL: http://llvm.org/viewvc/llvm-project?rev=139255&view=rev
Log:
Add tests for Thumb2 LDR(immediate) from r139254.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139255&r1=139254&r2=139255&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep  7 16:06:46 2011
@@ -515,6 +515,22 @@
 
 
 @------------------------------------------------------------------------------
+@ LDR(immediate)
+ at ------------------------------------------------------------------------------
+        ldr r5, [r5, #-4]
+        ldr r5, [r6, #32]
+        ldr r5, [r6, #33]
+        ldr r5, [r6, #257]
+        ldr.w pc, [r7, #257]
+
+@ CHECK: ldr	r5, [r5, #-4]           @ encoding: [0x55,0xf8,0x04,0x5c]
+@ CHECK: ldr	r5, [r6, #32]           @ encoding: [0x35,0x6a]
+@ CHECK: ldr.w	r5, [r6, #33]           @ encoding: [0xd6,0xf8,0x21,0x50]
+@ CHECK: ldr.w	r5, [r6, #257]          @ encoding: [0xd6,0xf8,0x01,0x51]
+@ CHECK: ldr.w	pc, [r7, #257]          @ encoding: [0xd7,0xf8,0x01,0xf1]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From resistor at mac.com  Wed Sep  7 16:10:42 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 07 Sep 2011 21:10:42 -0000
Subject: [llvm-commits] [llvm] r139256 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/thumb-tests.txt
Message-ID: <20110907211042.55FA32A6C12C@llvm.org>

Author: resistor
Date: Wed Sep  7 16:10:42 2011
New Revision: 139256

URL: http://llvm.org/viewvc/llvm-project?rev=139256&view=rev
Log:
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139256&r1=139255&r2=139256&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep  7 16:10:42 2011
@@ -3294,6 +3294,110 @@
               [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
                                            imm:$cp))]>,
                Requires<[IsThumb2]>;
+//===----------------------------------------------------------------------===//
+// Coprocessor load/store -- for disassembly only
+//
+class T2CI<dag oops, dag iops, string opc, string asm>
+  : T2I<oops, iops, NoItinerary, opc, asm, []> {
+  let Inst{27-25} = 0b110;
+}
+
+multiclass T2LdStCop<bits<4> op31_28, bit load, string opc> {
+  def _OFFSET : T2CI<(outs),
+      (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
+      opc, "\tp$cop, cr$CRd, $addr"> {
+    let Inst{31-28} = op31_28;
+    let Inst{24} = 1; // P = 1
+    let Inst{21} = 0; // W = 0
+    let Inst{22} = 0; // D = 0
+    let Inst{20} = load;
+    let DecoderMethod = "DecodeCopMemInstruction";
+  }
+
+  def _PRE : T2CI<(outs),
+      (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
+      opc, "\tp$cop, cr$CRd, $addr!"> {
+    let Inst{31-28} = op31_28;
+    let Inst{24} = 1; // P = 1
+    let Inst{21} = 1; // W = 1
+    let Inst{22} = 0; // D = 0
+    let Inst{20} = load;
+    let DecoderMethod = "DecodeCopMemInstruction";
+  }
+
+  def _POST : T2CI<(outs),
+      (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
+      opc, "\tp$cop, cr$CRd, $addr"> {
+    let Inst{31-28} = op31_28;
+    let Inst{24} = 0; // P = 0
+    let Inst{21} = 1; // W = 1
+    let Inst{22} = 0; // D = 0
+    let Inst{20} = load;
+    let DecoderMethod = "DecodeCopMemInstruction";
+  }
+
+  def _OPTION : T2CI<(outs),
+      (ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
+      opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
+    let Inst{31-28} = op31_28;
+    let Inst{24} = 0; // P = 0
+    let Inst{23} = 1; // U = 1
+    let Inst{21} = 0; // W = 0
+    let Inst{22} = 0; // D = 0
+    let Inst{20} = load;
+    let DecoderMethod = "DecodeCopMemInstruction";
+  }
+
+  def L_OFFSET : T2CI<(outs),
+      (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
+      !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
+    let Inst{31-28} = op31_28;
+    let Inst{24} = 1; // P = 1
+    let Inst{21} = 0; // W = 0
+    let Inst{22} = 1; // D = 1
+    let Inst{20} = load;
+    let DecoderMethod = "DecodeCopMemInstruction";
+  }
+
+  def L_PRE : T2CI<(outs),
+      (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
+      !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
+    let Inst{31-28} = op31_28;
+    let Inst{24} = 1; // P = 1
+    let Inst{21} = 1; // W = 1
+    let Inst{22} = 1; // D = 1
+    let Inst{20} = load;
+    let DecoderMethod = "DecodeCopMemInstruction";
+  }
+
+  def L_POST : T2CI<(outs),
+      (ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
+            postidx_imm8s4:$offset),
+      !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> {
+    let Inst{31-28} = op31_28;
+    let Inst{24} = 0; // P = 0
+    let Inst{21} = 1; // W = 1
+    let Inst{22} = 1; // D = 1
+    let Inst{20} = load;
+    let DecoderMethod = "DecodeCopMemInstruction";
+  }
+
+  def L_OPTION : T2CI<(outs),
+      (ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
+      !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
+    let Inst{31-28} = op31_28;
+    let Inst{24} = 0; // P = 0
+    let Inst{23} = 1; // U = 1
+    let Inst{21} = 0; // W = 0
+    let Inst{22} = 1; // D = 1
+    let Inst{20} = load;
+    let DecoderMethod = "DecodeCopMemInstruction";
+  }
+}
+
+defm t2LDC  : T2LdStCop<0b1111, 1, "ldc">;
+defm t2STC  : T2LdStCop<0b1111, 0, "stc">;
+
 
 //===----------------------------------------------------------------------===//
 // Move between special register and ARM core register -- for disassembly only

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139256&r1=139255&r2=139256&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Sep  7 16:10:42 2011
@@ -997,6 +997,22 @@
     case ARM::STCL_PRE:
     case ARM::STCL_POST:
     case ARM::STCL_OPTION:
+    case ARM::t2LDC_OFFSET:
+    case ARM::t2LDC_PRE:
+    case ARM::t2LDC_POST:
+    case ARM::t2LDC_OPTION:
+    case ARM::t2LDCL_OFFSET:
+    case ARM::t2LDCL_PRE:
+    case ARM::t2LDCL_POST:
+    case ARM::t2LDCL_OPTION:
+    case ARM::t2STC_OFFSET:
+    case ARM::t2STC_PRE:
+    case ARM::t2STC_POST:
+    case ARM::t2STC_OPTION:
+    case ARM::t2STCL_OFFSET:
+    case ARM::t2STCL_PRE:
+    case ARM::t2STCL_POST:
+    case ARM::t2STCL_OPTION:
       if (coproc == 0xA || coproc == 0xB)
         return MCDisassembler::Fail;
       break;
@@ -1021,6 +1037,12 @@
     case ARM::STCL_POST:
     case ARM::LDC2L_POST:
     case ARM::STC2L_POST:
+    case ARM::t2LDC_OPTION:
+    case ARM::t2LDCL_OPTION:
+    case ARM::t2STC_OPTION:
+    case ARM::t2STCL_OPTION:
+    case ARM::t2LDCL_POST:
+    case ARM::t2STCL_POST:
       break;
     default:
       Inst.addOperand(MCOperand::CreateReg(0));
@@ -1040,6 +1062,8 @@
   switch (Inst.getOpcode()) {
     case ARM::LDCL_POST:
     case ARM::STCL_POST:
+    case ARM::t2LDCL_POST:
+    case ARM::t2STCL_POST:
     case ARM::LDC2L_POST:
     case ARM::STC2L_POST:
       imm |= U << 8;
@@ -1051,6 +1075,10 @@
     case ARM::STCL_OPTION:
     case ARM::STC2_OPTION:
     case ARM::STC2L_OPTION:
+    case ARM::t2LDC_OPTION:
+    case ARM::t2LDCL_OPTION:
+    case ARM::t2STC_OPTION:
+    case ARM::t2STCL_OPTION:
       Inst.addOperand(MCOperand::CreateImm(imm));
       break;
     default:

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=139256&r1=139255&r2=139256&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Wed Sep  7 16:10:42 2011
@@ -218,11 +218,8 @@
 # CHECK:	pld	[r5, #30]
 0x95 0xf8 0x1e 0xf0
 
-# Test disabled as it was originally checking for
-# the ARM encoding of stc2, and thumb2 stc2 is
-# not implemented yet.
-# CHECK-:	stc2	p12, cr15, [r9], {137}
-#0x89 0xfc 0x89 0xfc
+# CHECK:	stc	p12, cr15, [r9], {137}
+0x89 0xfc 0x89 0xfc
 
 # CHECK:	vmov	r1, r0, d11
 0x50 0xec 0x1b 0x1b



From grosbach at apple.com  Wed Sep  7 16:33:16 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 21:33:16 -0000
Subject: [llvm-commits] [llvm] r139257 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110907213316.405DB2A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 16:33:16 2011
New Revision: 139257

URL: http://llvm.org/viewvc/llvm-project?rev=139257&view=rev
Log:
Thumb2 assembly parsing and encoding for LDR(literal).

Need branch relocation support to distinguish this encoding from the
16-bit Thumb1 encoding w/o the explicit .w suffix. That comes later, though.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139257&r1=139256&r2=139257&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep  7 16:33:16 2011
@@ -531,6 +531,15 @@
 
 
 @------------------------------------------------------------------------------
+@ LDR(literal)
+ at ------------------------------------------------------------------------------
+        ldr.w r5, _foo
+
+@ CHECK: ldr.w	r5, _foo                @ encoding: [0x5f'A',0xf8'A',A,0x50'A']
+            @   fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From grosbach at apple.com  Wed Sep  7 16:41:25 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 21:41:25 -0000
Subject: [llvm-commits] [llvm] r139258 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110907214125.B3BE22A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 16:41:25 2011
New Revision: 139258

URL: http://llvm.org/viewvc/llvm-project?rev=139258&view=rev
Log:
Thumb2 assembly parsing and encoding for LDRB(immediate).

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139258&r1=139257&r2=139258&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep  7 16:41:25 2011
@@ -3702,6 +3702,10 @@
 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
 
-// Alias for LDRi12 without the ".w" optional width specifier.
-def : t2InstAlias<"ldr${p} $Rd, $addr",
-                  (t2LDRi12 GPR:$Rd, t2addrmode_imm12:$addr, pred:$p)>;
+// Alias for LDR, LDRB, LDRH without the ".w" optional width specifier.
+def : t2InstAlias<"ldr${p} $Rt, $addr",
+                  (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
+def : t2InstAlias<"ldrb${p} $Rt, $addr",
+                  (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
+def : t2InstAlias<"ldrh${p} $Rt, $addr",
+                  (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139258&r1=139257&r2=139258&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep  7 16:41:25 2011
@@ -540,6 +540,22 @@
 
 
 @------------------------------------------------------------------------------
+@ LDRB(immediate)
+ at ------------------------------------------------------------------------------
+        ldrb r5, [r5, #-4]
+        ldrb r5, [r6, #32]
+        ldrb r5, [r6, #33]
+        ldrb r5, [r6, #257]
+        ldrb.w lr, [r7, #257]
+
+@ CHECK: ldrb	r5, [r5, #-4]           @ encoding: [0x15,0xf8,0x04,0x5c]
+@ CHECK: ldrb.w	r5, [r6, #32]           @ encoding: [0x96,0xf8,0x20,0x50]
+@ CHECK: ldrb.w	r5, [r6, #33]           @ encoding: [0x96,0xf8,0x21,0x50]
+@ CHECK: ldrb.w	r5, [r6, #257]          @ encoding: [0x96,0xf8,0x01,0x51]
+@ CHECK: ldrb.w	lr, [r7, #257]          @ encoding: [0x97,0xf8,0x01,0xe1]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From stoklund at 2pi.dk  Wed Sep  7 16:43:53 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 07 Sep 2011 21:43:53 -0000
Subject: [llvm-commits] [llvm] r139259 -
	/llvm/trunk/lib/CodeGen/InlineSpiller.cpp
Message-ID: <20110907214353.28AEC2A6C12C@llvm.org>

Author: stoklund
Date: Wed Sep  7 16:43:52 2011
New Revision: 139259

URL: http://llvm.org/viewvc/llvm-project?rev=139259&view=rev
Log:
Revert r139247 "Cache intermediate results during traceSiblingValue."

It broke the self host and clang-x86_64-darwin10-RA.

Modified:
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=139259&r1=139258&r2=139259&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Wed Sep  7 16:43:52 2011
@@ -17,7 +17,6 @@
 #include "LiveRangeEdit.h"
 #include "VirtRegMap.h"
 #include "llvm/ADT/Statistic.h"
-#include "llvm/ADT/TinyPtrVector.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
 #include "llvm/CodeGen/LiveStackAnalysis.h"
@@ -76,55 +75,30 @@
   // Values that failed to remat at some point.
   SmallPtrSet<VNInfo*, 8> UsedValues;
 
-public:
   // Information about a value that was defined by a copy from a sibling
   // register.
   struct SibValueInfo {
     // True when all reaching defs were reloads: No spill is necessary.
     bool AllDefsAreReloads;
 
-    // True when value is defined by an original PHI not from splitting.
-    bool DefByOrigPHI;
-
     // The preferred register to spill.
     unsigned SpillReg;
 
     // The value of SpillReg that should be spilled.
     VNInfo *SpillVNI;
 
-    // The block where SpillVNI should be spilled. Currently, this must be the
-    // block containing SpillVNI->def.
-    MachineBasicBlock *SpillMBB;
-
     // A defining instruction that is not a sibling copy or a reload, or NULL.
     // This can be used as a template for rematerialization.
     MachineInstr *DefMI;
 
-    // List of values that depend on this one.  These values are actually the
-    // same, but live range splitting has placed them in different registers,
-    // or SSA update needed to insert PHI-defs to preserve SSA form.  This is
-    // copies of the current value and phi-kills.  Usually only phi-kills cause
-    // more than one dependent value.
-    TinyPtrVector<VNInfo*> Deps;
-
     SibValueInfo(unsigned Reg, VNInfo *VNI)
-      : AllDefsAreReloads(true), DefByOrigPHI(false),
-        SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
-
-    // Returns true when a def has been found.
-    bool hasDef() const { return DefByOrigPHI || DefMI; }
+      : AllDefsAreReloads(false), SpillReg(Reg), SpillVNI(VNI), DefMI(0) {}
   };
 
-private:
   // Values in RegsToSpill defined by sibling copies.
   typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap;
   SibValueMap SibValues;
 
-  // Values live-out from basic blocks.  This is the same as
-  // LI.getVNInfoAt(LIS.getMBBEndIdx(MBB).getPrevSlot())
-  typedef DenseMap<MachineBasicBlock*, VNInfo*> LiveOutMap;
-  LiveOutMap LiveOutValues;
-
   // Dead defs generated during spilling.
   SmallVector<MachineInstr*, 8> DeadDefs;
 
@@ -160,7 +134,6 @@
 
   bool isSibling(unsigned Reg);
   MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*);
-  void propagateSiblingValue(SibValueMap::iterator, VNInfo *VNI = 0);
   void analyzeSiblingValues();
 
   bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
@@ -309,135 +282,6 @@
            VRM.getOriginal(Reg) == Original;
 }
 
-#ifndef NDEBUG
-static raw_ostream &operator<<(raw_ostream &OS,
-                               const InlineSpiller::SibValueInfo &SVI) {
-  OS << "spill " << PrintReg(SVI.SpillReg) << ':'
-     << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def;
-  if (SVI.AllDefsAreReloads)
-    OS << " all-reloads";
-  if (SVI.DefByOrigPHI)
-    OS << " orig-phi";
-  if (SVI.DefMI)
-    OS << " def: " << *SVI.DefMI;
-  else
-    OS << '\n';
-  return OS;
-}
-#endif
-
-/// propagateSiblingValue - Propagate the value in SVI to dependents if it is
-/// known.  Otherwise remember the dependency for later.
-///
-/// @param SVI SibValues entry to propagate.
-/// @param VNI Dependent value, or NULL to propagate to all saved dependents.
-void InlineSpiller::propagateSiblingValue(SibValueMap::iterator SVI,
-                                          VNInfo *VNI) {
-  SibValueInfo &SV = SVI->second;
-
-  if (!SV.SpillMBB)
-    SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
-
-  // Should this value be propagated as a preferred spill candidate?  We don't
-  // propagate values of registers that are about to spill.
-  bool PropSpill = !isRegToSpill(SV.SpillReg);
-  unsigned SpillDepth = ~0u;
-
-  // Further values that need to be updated.
-  SmallVector<VNInfo*, 8> WorkList;
-
-  // Defer propagation if the value is not known yet.
-  if (VNI) {
-    SV.Deps.push_back(VNI);
-    // Don't propagate to other dependents than VNI. SVI hasn't changed.
-    WorkList.push_back(VNI);
-  } else {
-    // No VNI given, update all Deps.
-    WorkList.append(SV.Deps.begin(), SV.Deps.end());
-  }
-
-  // Has the value been completely determined yet?  If not, defer propagation.
-  if (!SV.hasDef())
-    return;
-
-  while (!WorkList.empty()) {
-    SibValueMap::iterator DepSVI = SibValues.find(WorkList.pop_back_val());
-    assert(DepSVI != SibValues.end() && "Dependent value not in SibValues");
-    SibValueInfo &DepSV = DepSVI->second;
-    bool Changed = false;
-
-    if (!DepSV.SpillMBB)
-      DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
-
-    // Propagate defining instruction.
-    if (!DepSV.hasDef()) {
-      Changed = true;
-      DepSV.DefMI = SV.DefMI;
-      DepSV.DefByOrigPHI = SV.DefByOrigPHI;
-    }
-
-    // Propagate AllDefsAreReloads.  For PHI values, this computes an AND of
-    // all predecessors.
-    if (!SV.AllDefsAreReloads && DepSV.AllDefsAreReloads) {
-      Changed = true;
-      DepSV.AllDefsAreReloads = false;
-    }
-
-    // Propagate best spill value.
-    if (PropSpill && SV.SpillVNI != DepSV.SpillVNI) {
-      if (SV.SpillMBB == DepSV.SpillMBB) {
-        // DepSV is in the same block.  Hoist when dominated.
-        if (SV.SpillVNI->def < DepSV.SpillVNI->def) {
-          // This is an alternative def earlier in the same MBB.
-          // Hoist the spill as far as possible in SpillMBB. This can ease
-          // register pressure:
-          //
-          //   x = def
-          //   y = use x
-          //   s = copy x
-          //
-          // Hoisting the spill of s to immediately after the def removes the
-          // interference between x and y:
-          //
-          //   x = def
-          //   spill x
-          //   y = use x<kill>
-          //
-          Changed = true;
-          DepSV.SpillReg = SV.SpillReg;
-          DepSV.SpillVNI = SV.SpillVNI;
-          DepSV.SpillMBB = SV.SpillMBB;
-        }
-      } else {
-        // DepSV is in a different block.
-        if (SpillDepth == ~0u)
-          SpillDepth = Loops.getLoopDepth(SV.SpillMBB);
-
-        // Also hoist spills to blocks with smaller loop depth, but make sure
-        // that the new value dominates.  Non-phi dependents are always
-        // dominated, phis need checking.
-        if ((Loops.getLoopDepth(DepSV.SpillMBB) > SpillDepth) &&
-            (!DepSVI->first->isPHIDef() ||
-             MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
-          Changed = true;
-          DepSV.SpillReg = SV.SpillReg;
-          DepSV.SpillVNI = SV.SpillVNI;
-          DepSV.SpillMBB = SV.SpillMBB;
-        }
-      }
-    }
-
-    if (!Changed)
-      continue;
-
-    // Something changed in DepSVI. Propagate to dependents.
-    WorkList.append(DepSV.Deps.begin(), DepSV.Deps.end());
-
-    DEBUG(dbgs() << "  update " << DepSVI->first->id << '@'
-                 << DepSVI->first->def << " to:\t" << DepSV);
-  }
-}
-
 /// traceSiblingValue - Trace a value that is about to be spilled back to the
 /// real defining instructions by looking through sibling copies. Always stay
 /// within the range of OrigVNI so the registers are known to carry the same
@@ -450,68 +294,84 @@
 ///
 MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
                                                VNInfo *OrigVNI) {
-  // Check if a cached value already exists.
-  SibValueMap::iterator SVI;
-  bool Inserted;
-  tie(SVI, Inserted) =
-    SibValues.insert(std::make_pair(UseVNI, SibValueInfo(UseReg, UseVNI)));
-  if (!Inserted) {
-    DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':'
-                 << UseVNI->id << '@' << UseVNI->def << ' ' << SVI->second);
-    return SVI->second.DefMI;
-  }
-
   DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
                << UseVNI->id << '@' << UseVNI->def << '\n');
-
-  // List of (Reg, VNI) that have been inserted into SibValues, but need to be
-  // processed.
+  SmallPtrSet<VNInfo*, 8> Visited;
   SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList;
   WorkList.push_back(std::make_pair(UseReg, UseVNI));
 
+  // Best spill candidate seen so far. This must dominate UseVNI.
+  SibValueInfo SVI(UseReg, UseVNI);
+  MachineBasicBlock *UseMBB = LIS.getMBBFromIndex(UseVNI->def);
+  MachineBasicBlock *SpillMBB = UseMBB;
+  unsigned SpillDepth = Loops.getLoopDepth(SpillMBB);
+  bool SeenOrigPHI = false; // Original PHI met.
+
   do {
     unsigned Reg;
     VNInfo *VNI;
     tie(Reg, VNI) = WorkList.pop_back_val();
-    DEBUG(dbgs() << "  " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
-                 << ":\t");
+    if (!Visited.insert(VNI))
+      continue;
 
-    // First check if this value has already been computed.
-    SVI = SibValues.find(VNI);
-    assert(SVI != SibValues.end() && "Missing SibValues entry");
+    // Is this value a better spill candidate?
+    if (!isRegToSpill(Reg)) {
+      MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
+      if (MBB == SpillMBB) {
+        // This is an alternative def earlier in the same MBB.
+        // Hoist the spill as far as possible in SpillMBB. This can ease
+        // register pressure:
+        //
+        //   x = def
+        //   y = use x
+        //   s = copy x
+        //
+        // Hoisting the spill of s to immediately after the def removes the
+        // interference between x and y:
+        //
+        //   x = def
+        //   spill x
+        //   y = use x<kill>
+        //
+        if (VNI->def < SVI.SpillVNI->def) {
+          DEBUG(dbgs() << "  hoist in BB#" << MBB->getNumber() << ": "
+                       << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
+                       << '\n');
+          SVI.SpillReg = Reg;
+          SVI.SpillVNI = VNI;
+        }
+      } else if (MBB != UseMBB && MDT.dominates(MBB, UseMBB)) {
+        // This is a valid spill location dominating UseVNI.
+        // Prefer to spill at a smaller loop depth.
+        unsigned Depth = Loops.getLoopDepth(MBB);
+        if (Depth < SpillDepth) {
+          DEBUG(dbgs() << "  spill depth " << Depth << ": " << PrintReg(Reg)
+                       << ':' << VNI->id << '@' << VNI->def << '\n');
+          SVI.SpillReg = Reg;
+          SVI.SpillVNI = VNI;
+          SpillMBB = MBB;
+          SpillDepth = Depth;
+        }
+      }
+    }
 
     // Trace through PHI-defs created by live range splitting.
     if (VNI->isPHIDef()) {
       if (VNI->def == OrigVNI->def) {
-        DEBUG(dbgs() << "orig phi value\n");
-        SVI->second.DefByOrigPHI = true;
-        SVI->second.AllDefsAreReloads = false;
-        propagateSiblingValue(SVI);
+        DEBUG(dbgs() << "  orig phi value " << PrintReg(Reg) << ':'
+                     << VNI->id << '@' << VNI->def << '\n');
+        SeenOrigPHI = true;
         continue;
       }
       // Get values live-out of predecessors.
       LiveInterval &LI = LIS.getInterval(Reg);
       MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
-      DEBUG(dbgs() << "split phi value, check " << MBB->pred_size()
-                   << " preds\n");
       for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
              PE = MBB->pred_end(); PI != PE; ++PI) {
-        // Use a cache of block live-out values.  This is faster than using
-        // getVNInfoAt on complex intervals.
-        VNInfo *&PVNI = LiveOutValues[*PI];
-        if (!PVNI)
-          PVNI = LI.getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
-        if (!PVNI)
-          continue;
-        // Known predecessor value? Try an insertion.
-        tie(SVI, Inserted) =
-          SibValues.insert(std::make_pair(PVNI, SibValueInfo(Reg, PVNI)));
-        // This is the first time we see PVNI, add it to the worklist.
-        if (Inserted)
+        VNInfo *PVNI = LI.getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
+        if (PVNI)
           WorkList.push_back(std::make_pair(Reg, PVNI));
-        propagateSiblingValue(SVI, VNI);
       }
-      // Next work list item.
       continue;
     }
 
@@ -524,43 +384,46 @@
         LiveInterval &SrcLI = LIS.getInterval(SrcReg);
         VNInfo *SrcVNI = SrcLI.getVNInfoAt(VNI->def.getUseIndex());
         assert(SrcVNI && "Copy from non-existing value");
-        DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':'
+        DEBUG(dbgs() << "  copy of " << PrintReg(SrcReg) << ':'
                      << SrcVNI->id << '@' << SrcVNI->def << '\n');
-        // Known sibling source value? Try an insertion.
-        tie(SVI, Inserted) = SibValues.insert(std::make_pair(SrcVNI,
-                                                 SibValueInfo(SrcReg, SrcVNI)));
-        // This is the first time we see Src, add it to the worklist.
-        if (Inserted)
-          WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
-        propagateSiblingValue(SVI, VNI);
-        // Next work list item.
+        WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
         continue;
       }
     }
 
     // Track reachable reloads.
-    SVI->second.DefMI = MI;
-    SVI->second.SpillMBB = MI->getParent();
     int FI;
     if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
-      DEBUG(dbgs() << "reload\n");
-      propagateSiblingValue(SVI);
-      // Next work list item.
+      DEBUG(dbgs() << "  reload " << PrintReg(Reg) << ':'
+                   << VNI->id << "@" << VNI->def << '\n');
+      SVI.AllDefsAreReloads = true;
       continue;
     }
 
+    // We have an 'original' def. Don't record trivial cases.
+    if (VNI == UseVNI) {
+      DEBUG(dbgs() << "Not a sibling copy.\n");
+      return MI;
+    }
+
     // Potential remat candidate.
-    DEBUG(dbgs() << "def " << *MI);
-    SVI->second.AllDefsAreReloads = false;
-    propagateSiblingValue(SVI);
+    DEBUG(dbgs() << "  def " << PrintReg(Reg) << ':'
+                 << VNI->id << '@' << VNI->def << '\t' << *MI);
+    SVI.DefMI = MI;
   } while (!WorkList.empty());
 
-  // Look up the value we were looking for.  We already did this lokup at the
-  // top of the function, but SibValues may have been invalidated.
-  SVI = SibValues.find(UseVNI);
-  assert(SVI != SibValues.end() && "Didn't compute requested info");
-  DEBUG(dbgs() << "  traced to:\t" << SVI->second);
-  return SVI->second.DefMI;
+  if (SeenOrigPHI || SVI.DefMI)
+    SVI.AllDefsAreReloads = false;
+
+  DEBUG({
+    if (SVI.AllDefsAreReloads)
+      dbgs() << "All defs are reloads.\n";
+    else
+      dbgs() << "Prefer to spill " << PrintReg(SVI.SpillReg) << ':'
+             << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def << '\n';
+  });
+  SibValues.insert(std::make_pair(UseVNI, SVI));
+  return SVI.DefMI;
 }
 
 /// analyzeSiblingValues - Trace values defined by sibling copies back to
@@ -569,7 +432,6 @@
 /// Keep track of values that may be rematerializable.
 void InlineSpiller::analyzeSiblingValues() {
   SibValues.clear();
-  LiveOutValues.clear();
 
   // No siblings at all?
   if (Edit->getReg() == Original)
@@ -644,7 +506,6 @@
 
   // Already spilled everywhere.
   if (SVI.AllDefsAreReloads) {
-    DEBUG(dbgs() << "\tno spill needed: " << SVI);
     ++NumOmitReloadSpill;
     return true;
   }



From benny.kra at googlemail.com  Wed Sep  7 17:49:26 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Wed, 07 Sep 2011 22:49:26 -0000
Subject: [llvm-commits] [llvm] r139263 - /llvm/trunk/lib/Target/README.txt
Message-ID: <20110907224926.A9B8C2A6C12C@llvm.org>

Author: d0k
Date: Wed Sep  7 17:49:26 2011
New Revision: 139263

URL: http://llvm.org/viewvc/llvm-project?rev=139263&view=rev
Log:
Add two notes for correlated-expression optimizations.

Modified:
    llvm/trunk/lib/Target/README.txt

Modified: llvm/trunk/lib/Target/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=139263&r1=139262&r2=139263&view=diff
==============================================================================
--- llvm/trunk/lib/Target/README.txt (original)
+++ llvm/trunk/lib/Target/README.txt Wed Sep  7 17:49:26 2011
@@ -2348,3 +2348,13 @@
 probably best to do this in the code generator.
 
 //===---------------------------------------------------------------------===//
+
+unsigned foo(unsigned x, unsigned y) { return (x & y) == 0 || x == 0; }
+should fold to (x & y) == 0.
+
+//===---------------------------------------------------------------------===//
+
+unsigned foo(unsigned x, unsigned y) { return x > y && x != 0; }
+should fold to x > y.
+
+//===---------------------------------------------------------------------===//



From grosbach at apple.com  Wed Sep  7 18:10:15 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 23:10:15 -0000
Subject: [llvm-commits] [llvm] r139264 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110907231015.790082A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 18:10:15 2011
New Revision: 139264

URL: http://llvm.org/viewvc/llvm-project?rev=139264&view=rev
Log:
Thumb2 assembly parsing and encoding for LDR(register).

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139264&r1=139263&r2=139264&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep  7 18:10:15 2011
@@ -167,11 +167,13 @@
 }
 
 // t2addrmode_so_reg  := reg + (reg << imm2)
+def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
 def t2addrmode_so_reg : Operand<i32>,
                         ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
   let PrintMethod = "printT2AddrModeSoRegOperand";
   let EncoderMethod = "getT2AddrModeSORegOpValue";
   let DecoderMethod = "DecodeT2AddrModeSOReg";
+  let ParserMatchClass = t2addrmode_so_reg_asmoperand;
   let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
 }
 
@@ -3709,3 +3711,9 @@
                   (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
 def : t2InstAlias<"ldrh${p} $Rt, $addr",
                   (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
+def : t2InstAlias<"ldr${p} $Rt, $addr",
+                  (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
+def : t2InstAlias<"ldrb${p} $Rt, $addr",
+                  (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
+def : t2InstAlias<"ldrh${p} $Rt, $addr",
+                  (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139264&r1=139263&r2=139264&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Sep  7 18:10:15 2011
@@ -680,6 +680,16 @@
       return false;
     return true;
   }
+  bool isT2MemRegOffset() const {
+    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative)
+      return false;
+    // Only lsl #{0, 1, 2, 3} allowed.
+    if (Mem.ShiftType == ARM_AM::no_shift)
+      return true;
+    if (Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm > 3)
+      return false;
+    return true;
+  }
   bool isMemThumbRR() const {
     // Thumb reg+reg addressing is simple. Just two registers, a base and
     // an offset. No shifts, negations or any other complicating factors.
@@ -844,7 +854,6 @@
       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
   }
 
-
   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
@@ -1145,6 +1154,13 @@
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
+  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 3 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Mem.ShiftImm));
+  }
+
   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139264&r1=139263&r2=139264&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep  7 18:10:15 2011
@@ -540,6 +540,24 @@
 
 
 @------------------------------------------------------------------------------
+@ LDR(register)
+ at ------------------------------------------------------------------------------
+        ldr r1, [r8, r1]
+        ldr.w r4, [r5, r2]
+        ldr r6, [r0, r2, lsl #3]
+        ldr r8, [r8, r2, lsl #2]
+        ldr r7, [sp, r2, lsl #1]
+        ldr r7, [sp, r2, lsl #0]
+
+@ CHECK: ldr.w	r1, [r8, r1]            @ encoding: [0x58,0xf8,0x01,0x10]
+@ CHECK: ldr.w	r4, [r5, r2]            @ encoding: [0x55,0xf8,0x02,0x40]
+@ CHECK: ldr.w	r6, [r0, r2, lsl #3]    @ encoding: [0x50,0xf8,0x32,0x60]
+@ CHECK: ldr.w	r8, [r8, r2, lsl #2]    @ encoding: [0x58,0xf8,0x22,0x80]
+@ CHECK: ldr.w	r7, [sp, r2, lsl #1]    @ encoding: [0x5d,0xf8,0x12,0x70]
+@ CHECK: ldr.w	r7, [sp, r2]            @ encoding: [0x5d,0xf8,0x02,0x70]
+
+
+ at ------------------------------------------------------------------------------
 @ LDRB(immediate)
 @------------------------------------------------------------------------------
         ldrb r5, [r5, #-4]



From grosbach at apple.com  Wed Sep  7 18:17:01 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 23:17:01 -0000
Subject: [llvm-commits] [llvm] r139266 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110907231701.213002A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 18:17:00 2011
New Revision: 139266

URL: http://llvm.org/viewvc/llvm-project?rev=139266&view=rev
Log:
Thumb2 assembly parsing and encoding for LDRB(register).

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139266&r1=139265&r2=139266&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep  7 18:17:00 2011
@@ -574,6 +574,24 @@
 
 
 @------------------------------------------------------------------------------
+@ LDRB(register)
+ at ------------------------------------------------------------------------------
+        ldrb r1, [r8, r1]
+        ldrb.w r4, [r5, r2]
+        ldrb r6, [r0, r2, lsl #3]
+        ldrb r8, [r8, r2, lsl #2]
+        ldrb r7, [sp, r2, lsl #1]
+        ldrb r7, [sp, r2, lsl #0]
+
+@ CHECK: ldrb.w	r1, [r8, r1]            @ encoding: [0x18,0xf8,0x01,0x10]
+@ CHECK: ldrb.w	r4, [r5, r2]            @ encoding: [0x15,0xf8,0x02,0x40]
+@ CHECK: ldrb.w	r6, [r0, r2, lsl #3]    @ encoding: [0x10,0xf8,0x32,0x60]
+@ CHECK: ldrb.w	r8, [r8, r2, lsl #2]    @ encoding: [0x18,0xf8,0x22,0x80]
+@ CHECK: ldrb.w	r7, [sp, r2, lsl #1]    @ encoding: [0x1d,0xf8,0x12,0x70]
+@ CHECK: ldrb.w	r7, [sp, r2]            @ encoding: [0x1d,0xf8,0x02,0x70]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From pdox at google.com  Wed Sep  7 18:40:08 2011
From: pdox at google.com (David Meyer)
Date: Wed, 7 Sep 2011 16:40:08 -0700
Subject: [llvm-commits] [PATCH] Clean up RegOp2MemOp tables in
	X86InstrInfo.cpp
In-Reply-To: <CAAU48JJ-55X_sfnhvB1uudKbTPdhvue9P4jVL5B2meojxL9Y_g@mail.gmail.com>
References: <CAAU48JKT3LE1gCzvWtv5Me4AsQLTbGa+boxFyZsjuKOP+8BanQ@mail.gmail.com>
	<6CF9FE3C-ABC0-4BB8-89A8-A27A45803A7A@2pi.dk>
	<CAAU48JJ-55X_sfnhvB1uudKbTPdhvue9P4jVL5B2meojxL9Y_g@mail.gmail.com>
Message-ID: <CAAU48J+3G3Kps_N87nLq-oZghp9fJuoZ9aWvN+8bW7+0sRzfpQ@mail.gmail.com>

Jakob,

Was the last patch OK?

Thanks,
 - pdox

On Tue, Sep 6, 2011 at 4:57 PM, David Meyer <pdox at google.com> wrote:
> Hi Jakob,
>
> I added a brief comment to each. New patch attached.
>
> Thanks,
> ?- pdox
>
> On Tue, Sep 6, 2011 at 10:06 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>>
>> On Sep 5, 2011, at 9:40 PM, David Meyer wrote:
>>
>>> Hello!
>>>
>>> This patch:
>>>
>>> * Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
>>> single field (Flags), which is a bitwise OR of items from the TB_*
>>> enum. This makes it easier to add new information in the future.
>>>
>>> * Gives every static array an equivalent layout: { RegOp, MemOp, Flags }
>>>
>>> * Adds a helper function, AddTableEntry, to avoid duplication of the
>>> insertion code.
>>>
>>> * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.
>>>
>>> * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
>>> it prevents addition of the Reg->Mem entry. (This is going to be used
>>> by Native Client, in the next CL).
>>
>> Looks good, but please add an explanation of the TB_INDEX* and TB_ALIGN* enums.
>>
>> /jakob
>>
>>
>


From grosbach at apple.com  Wed Sep  7 18:39:14 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 07 Sep 2011 23:39:14 -0000
Subject: [llvm-commits] [llvm] r139267 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s utils/TableGen/EDEmitter.cpp
Message-ID: <20110907233914.4C18F2A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 18:39:14 2011
New Revision: 139267

URL: http://llvm.org/viewvc/llvm-project?rev=139267&view=rev
Log:
Thumb2 assembly parsing and encoding for LDRBT.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139267&r1=139266&r2=139267&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep  7 18:39:14 2011
@@ -123,6 +123,16 @@
 }
 
 
+// t2addrmode_posimm8  := reg + imm8
+def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
+def t2addrmode_posimm8 : Operand<i32> {
+  let PrintMethod = "printT2AddrModeImm8Operand";
+  let EncoderMethod = "getT2AddrModeImm8OpValue";
+  let DecoderMethod = "DecodeT2AddrModeImm8";
+  let ParserMatchClass = MemPosImm8OffsetAsmOperand;
+  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
+}
+
 // t2addrmode_negimm8  := reg - imm8
 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
 def t2addrmode_negimm8 : Operand<i32>,
@@ -1291,26 +1301,24 @@
                             []>;
 } // mayLoad = 1, neverHasSideEffects = 1
 
-// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
-// for disassembly only.
+// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
-  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
+  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
           "\t$Rt, $addr", []> {
+  bits<4> Rt;
+  bits<13> addr;
   let Inst{31-27} = 0b11111;
   let Inst{26-25} = 0b00;
   let Inst{24} = signed;
   let Inst{23} = 0;
   let Inst{22-21} = type;
   let Inst{20} = 1; // load
+  let Inst{19-16} = addr{12-9};
+  let Inst{15-12} = Rt;
   let Inst{11} = 1;
   let Inst{10-8} = 0b110; // PUW.
-
-  bits<4> Rt;
-  bits<13> addr;
-  let Inst{15-12} = Rt;
-  let Inst{19-16} = addr{12-9};
-  let Inst{7-0}   = addr{7-0};
+  let Inst{7-0} = addr{7-0};
 }
 
 def t2LDRT   : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139267&r1=139266&r2=139267&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Sep  7 18:39:14 2011
@@ -742,6 +742,14 @@
     int64_t Val = Mem.OffsetImm->getValue();
     return Val > -256 && Val < 256;
   }
+  bool isMemPosImm8Offset() const {
+    if (Kind != Memory || Mem.OffsetRegNum != 0)
+      return false;
+    // Immediate offset in range [0, 255].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return Val >= 0 && Val < 256;
+  }
   bool isMemNegImm8Offset() const {
     if (Kind != Memory || Mem.OffsetRegNum != 0)
       return false;
@@ -1108,11 +1116,12 @@
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
+  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
+    addMemImm8OffsetOperands(Inst, N);
+  }
+
   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
-    assert(N == 2 && "Invalid number of operands!");
-    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
-    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
-    Inst.addOperand(MCOperand::CreateImm(Val));
+    addMemImm8OffsetOperands(Inst, N);
   }
 
   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139267&r1=139266&r2=139267&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep  7 18:39:14 2011
@@ -592,6 +592,20 @@
 
 
 @------------------------------------------------------------------------------
+@ LDRBT
+ at ------------------------------------------------------------------------------
+        ldrbt r1, [r2]
+        ldrbt r1, [r8, #0]
+        ldrbt r1, [r8, #3]
+        ldrbt r1, [r8, #255]
+
+@ CHECK: ldrbt	r1, [r2]                @ encoding: [0x12,0xf8,0x00,0x1e]
+@ CHECK: ldrbt	r1, [r8]                @ encoding: [0x18,0xf8,0x00,0x1e]
+@ CHECK: ldrbt	r1, [r8, #3]            @ encoding: [0x18,0xf8,0x03,0x1e]
+@ CHECK: ldrbt	r1, [r8, #255]          @ encoding: [0x18,0xf8,0xff,0x1e]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=139267&r1=139266&r2=139267&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Wed Sep  7 18:39:14 2011
@@ -666,6 +666,7 @@
   MISC("spr_reglist", "kOperandTypeARMSPRRegisterList");          // I, R, ...
   MISC("it_mask", "kOperandTypeThumbITMask");                     // I
   MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg");        // R
+  MISC("t2addrmode_posimm8", "kOperandTypeThumb2AddrModeImm8");   // R, I
   MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8");   // R, I
   MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8");      // R, I
   MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I



From stoklund at 2pi.dk  Wed Sep  7 18:41:20 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 07 Sep 2011 16:41:20 -0700
Subject: [llvm-commits] [PATCH] Clean up RegOp2MemOp tables in
 X86InstrInfo.cpp
In-Reply-To: <CAAU48J+3G3Kps_N87nLq-oZghp9fJuoZ9aWvN+8bW7+0sRzfpQ@mail.gmail.com>
References: <CAAU48JKT3LE1gCzvWtv5Me4AsQLTbGa+boxFyZsjuKOP+8BanQ@mail.gmail.com>
	<6CF9FE3C-ABC0-4BB8-89A8-A27A45803A7A@2pi.dk>
	<CAAU48JJ-55X_sfnhvB1uudKbTPdhvue9P4jVL5B2meojxL9Y_g@mail.gmail.com>
	<CAAU48J+3G3Kps_N87nLq-oZghp9fJuoZ9aWvN+8bW7+0sRzfpQ@mail.gmail.com>
Message-ID: <BAB05FBC-F778-46B1-8724-45C7B088EF4F@2pi.dk>


On Sep 7, 2011, at 4:40 PM, David Meyer wrote:

> Jakob,
> 
> Was the last patch OK?

Yes. Sorry, I haven't had time to commit it.

/jakob


From geek4civic at gmail.com  Wed Sep  7 19:07:10 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Thu, 8 Sep 2011 09:07:10 +0900
Subject: [llvm-commits] [llvm] r139250 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ test/MC/Disassembler/ARM/ utils/TableGen/
In-Reply-To: <20110907194229.097E02A6C12C@llvm.org>
References: <20110907194229.097E02A6C12C@llvm.org>
Message-ID: <CADiQthOBjzzbZ=7HTvp5eLu2+4egv1G+VRB2qN_+CUCMTz2R=w@mail.gmail.com>

2011/9/8 James Molloy <james.molloy at arm.com>:
> Author: jamesm
> Date: Wed Sep ?7 14:42:28 2011
> New Revision: 139250
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139250&view=rev
> Log:
> Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
>
> Modified:
> ? ?llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> ? ?llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/neon.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
> ? ?llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
> ? ?llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
> ? ?llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
> ? ?llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h

James, I saw weird emissions by tblgen, on cygwin gcc-4.3 and msvc10.
I will investigate a few hours after, too.

...Takumi
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From resistor at mac.com  Wed Sep  7 19:11:18 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 08 Sep 2011 00:11:18 -0000
Subject: [llvm-commits] [llvm] r139268 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrInfo.td Disassembler/ARMDisassembler.cpp
Message-ID: <20110908001118.800A72A6C12C@llvm.org>

Author: resistor
Date: Wed Sep  7 19:11:18 2011
New Revision: 139268

URL: http://llvm.org/viewvc/llvm-project?rev=139268&view=rev
Log:
Remove the "common" set of instructions shared between ARM and Thumb2 modes.  This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139268&r1=139267&r2=139268&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Sep  7 19:11:18 2011
@@ -4320,7 +4320,6 @@
 }
 
 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
-  let DecoderNamespace = "Common" in {
   def _OFFSET : ACI<(outs),
       !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
       !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
@@ -4416,7 +4415,6 @@
     let Inst{20} = load;
     let DecoderMethod = "DecodeCopMemInstruction";
   }
-  }
 }
 
 defm LDC  : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc",  "${p}">;

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139268&r1=139267&r2=139268&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Sep  7 19:11:18 2011
@@ -342,16 +342,6 @@
     return result;
   }
 
-  // Instructions that are shared between ARM and Thumb modes.
-  // FIXME: This shouldn't really exist.  It's an artifact of the
-  // fact that we fail to encode a few instructions properly for Thumb.
-  MI.clear();
-  result = decodeCommonInstruction32(MI, insn, Address, this, STI);
-  if (result != MCDisassembler::Fail) {
-    Size = 4;
-    return result;
-  }
-
   // VFP and NEON instructions, similarly, are shared between ARM
   // and Thumb modes.
   MI.clear();
@@ -595,14 +585,6 @@
   }
 
   MI.clear();
-  result = decodeCommonInstruction32(MI, insn32, Address, this, STI);
-  if (result != MCDisassembler::Fail) {
-    Size = 4;
-    AddThumbPredicate(MI);
-    return result;
-  }
-
-  MI.clear();
   result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;



From krasin at chromium.org  Wed Sep  7 19:38:23 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Wed, 7 Sep 2011 17:38:23 -0700
Subject: [llvm-commits] [PATCH]lto/addAsmGlobalSymbols: fast path when no
	module level asm is present
Message-ID: <CAOei5ReYh8CnQjz6x9pgrMscvjZPS6UMU4Gi-XwQXNpqoW-OYg@mail.gmail.com>

Hi llvm team,

this patch adds a fast path for LTOModule::addAsmGlobalSymbols when
where's no assembly defined in the module.

Please, find the patch attached or online:
http://codereview.chromium.org/7850008/

OK to commit?

krasin
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From grosbach at apple.com  Wed Sep  7 19:39:19 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Sep 2011 00:39:19 -0000
Subject: [llvm-commits] [llvm] r139270 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrThumb2.td
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110908003919.5FF042A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 19:39:19 2011
New Revision: 139270

URL: http://llvm.org/viewvc/llvm-project?rev=139270&view=rev
Log:
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.

Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=139270&r1=139269&r2=139270&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Sep  7 19:39:19 2011
@@ -1161,8 +1161,8 @@
             string asm, string cstr, list<dag> pattern>
   : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
 
-// T2Iidxldst - Thumb2 indexed load / store instructions.
-class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
+// T2Ipreldst - Thumb2 pre-indexed load / store instructions.
+class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
                  dag oops, dag iops,
                  AddrMode am, IndexMode im, InstrItinClass itin,
                  string opc, string asm, string cstr, list<dag> pattern>
@@ -1173,25 +1173,55 @@
   let Pattern = pattern;
   list<Predicate> Predicates = [IsThumb2];
   let DecoderNamespace = "Thumb2";
+
+  bits<4> Rt;
+  bits<13> addr;
   let Inst{31-27} = 0b11111;
   let Inst{26-25} = 0b00;
   let Inst{24}    = signed;
   let Inst{23}    = 0;
   let Inst{22-21} = opcod;
   let Inst{20}    = load;
+  let Inst{19-16} = addr{12-9};
+  let Inst{15-12} = Rt{3-0};
   let Inst{11}    = 1;
   // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
   let Inst{10}    = pre; // The P bit.
+  let Inst{9}     = addr{8}; // Sign bit
   let Inst{8}     = 1; // The W bit.
+  let Inst{7-0}   = addr{7-0};
+}
 
-  bits<9> addr;
-  let Inst{7-0} = addr{7-0};
-  let Inst{9}   = addr{8}; // Sign bit
+// T2Ipostldst - Thumb2 post-indexed load / store instructions.
+class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
+                 dag oops, dag iops,
+                 AddrMode am, IndexMode im, InstrItinClass itin,
+                 string opc, string asm, string cstr, list<dag> pattern>
+  : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
+  let OutOperandList = oops;
+  let InOperandList = !con(iops, (ins pred:$p));
+  let AsmString = !strconcat(opc, "${p}", asm);
+  let Pattern = pattern;
+  list<Predicate> Predicates = [IsThumb2];
+  let DecoderNamespace = "Thumb2";
 
   bits<4> Rt;
   bits<4> Rn;
+  bits<9> addr;
+  let Inst{31-27} = 0b11111;
+  let Inst{26-25} = 0b00;
+  let Inst{24}    = signed;
+  let Inst{23}    = 0;
+  let Inst{22-21} = opcod;
+  let Inst{20}    = load;
+  let Inst{19-16} = Rn;
   let Inst{15-12} = Rt{3-0};
-  let Inst{19-16} = Rn{3-0};
+  let Inst{11}    = 1;
+  // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
+  let Inst{10}    = pre; // The P bit.
+  let Inst{9}     = addr{8}; // Sign bit
+  let Inst{8}     = 1; // The W bit.
+  let Inst{7-0}   = addr{7-0};
 }
 
 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139270&r1=139269&r2=139270&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep  7 19:39:19 2011
@@ -1244,61 +1244,66 @@
 // Indexed loads
 
 let mayLoad = 1, neverHasSideEffects = 1 in {
-def t2LDR_PRE  : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
+def t2LDR_PRE  : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
                             (ins t2addrmode_imm8:$addr),
                             AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
-                            "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
-                            []>;
+                            "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
+                            []> {
+  let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
+}
 
-def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
-                            (ins GPR:$base, t2am_imm8_offset:$addr),
+def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
+                            (ins GPR:$Rn, t2am_imm8_offset:$addr),
                             AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
-                          "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
-                            []>;
+                            "ldr", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>;
 
-def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
+def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
                             (ins t2addrmode_imm8:$addr),
                             AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
-                            "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
-                            []>;
-def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
-                            (ins GPR:$base, t2am_imm8_offset:$addr),
+                            "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
+                            []> {
+  let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
+}
+def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
+                            (ins GPR:$Rn, t2am_imm8_offset:$addr),
                             AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
-                         "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
-                            []>;
+                            "ldrb", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>;
 
-def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
+def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
                             (ins t2addrmode_imm8:$addr),
                             AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
-                            "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
-                            []>;
-def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
-                            (ins GPR:$base, t2am_imm8_offset:$addr),
+                            "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
+                            []> {
+  let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
+}
+def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
+                            (ins GPR:$Rn, t2am_imm8_offset:$addr),
                             AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
-                         "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
-                            []>;
+                            "ldrh", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>;
 
-def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
+def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
                             (ins t2addrmode_imm8:$addr),
                             AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
-                            "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
-                            []>;
-def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
-                            (ins GPR:$base, t2am_imm8_offset:$addr),
+                            "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
+                            []> {
+  let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
+}
+def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
+                            (ins GPR:$Rn, t2am_imm8_offset:$addr),
                             AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
-                        "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
-                            []>;
+                            "ldrsb", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>;
 
-def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
+def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
                             (ins t2addrmode_imm8:$addr),
                             AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
-                            "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
-                            []>;
-def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
-                            (ins GPR:$base, t2am_imm8_offset:$addr),
+                            "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
+                            []> {
+  let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
+}
+def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
+                            (ins GPR:$Rn, t2am_imm8_offset:$addr),
                             AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
-                        "ldrsh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
-                            []>;
+                            "ldrsh", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>;
 } // mayLoad = 1, neverHasSideEffects = 1
 
 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
@@ -1342,52 +1347,52 @@
                IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
 
 // Indexed stores
-def t2STR_PRE  : T2Iidxldst<0, 0b10, 0, 1, (outs GPRnopc:$base_wb),
+def t2STR_PRE  : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
                             (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
                             AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
                          "str", "\t$Rt, [$Rn, $addr]!",
-                         "$Rn = $base_wb, at earlyclobber $base_wb",
-             [(set GPRnopc:$base_wb,
+                         "$Rn = $Rn_wb, at earlyclobber $Rn_wb",
+             [(set GPRnopc:$Rn_wb,
                    (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
 
-def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPRnopc:$base_wb),
+def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
                             (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
                             AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
                           "str", "\t$Rt, [$Rn], $addr",
-                          "$Rn = $base_wb, at earlyclobber $base_wb",
-             [(set GPRnopc:$base_wb,
+                          "$Rn = $Rn_wb, at earlyclobber $Rn_wb",
+             [(set GPRnopc:$Rn_wb,
                   (post_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
 
-def t2STRH_PRE  : T2Iidxldst<0, 0b01, 0, 1, (outs GPRnopc:$base_wb),
+def t2STRH_PRE  : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
                             (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
                             AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
                         "strh", "\t$Rt, [$Rn, $addr]!",
-                        "$Rn = $base_wb, at earlyclobber $base_wb",
-        [(set GPRnopc:$base_wb,
+                        "$Rn = $Rn_wb, at earlyclobber $Rn_wb",
+        [(set GPRnopc:$Rn_wb,
               (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
 
-def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPRnopc:$base_wb),
+def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
                             (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
                             AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
                          "strh", "\t$Rt, [$Rn], $addr",
-                         "$Rn = $base_wb, at earlyclobber $base_wb",
-       [(set GPRnopc:$base_wb,
+                         "$Rn = $Rn_wb, at earlyclobber $Rn_wb",
+       [(set GPRnopc:$Rn_wb,
              (post_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
 
-def t2STRB_PRE  : T2Iidxldst<0, 0b00, 0, 1, (outs GPRnopc:$base_wb),
+def t2STRB_PRE  : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
                             (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
                             AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
                         "strb", "\t$Rt, [$Rn, $addr]!",
-                        "$Rn = $base_wb, at earlyclobber $base_wb",
-         [(set GPRnopc:$base_wb,
+                        "$Rn = $Rn_wb, at earlyclobber $Rn_wb",
+         [(set GPRnopc:$Rn_wb,
                (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
 
-def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPRnopc:$base_wb),
+def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
                             (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
                             AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
                          "strb", "\t$Rt, [$Rn], $addr",
-                         "$Rn = $base_wb, at earlyclobber $base_wb",
-        [(set GPRnopc:$base_wb,
+                         "$Rn = $Rn_wb, at earlyclobber $Rn_wb",
+        [(set GPRnopc:$Rn_wb,
               (post_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
 
 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139270&r1=139269&r2=139270&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Sep  7 19:39:19 2011
@@ -158,6 +158,8 @@
   OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
 
   // Asm Match Converter Methods
+  bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
+                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
   bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
   bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
@@ -2398,6 +2400,22 @@
   return MatchOperand_Success;
 }
 
+/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
+/// Needed here because the Asm Gen Matcher can't handle properly tied operands
+/// when they refer multiple MIOperands inside a single one.
+bool ARMAsmParser::
+cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
+                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
+
+  // Create a writeback register dummy placeholder.
+  Inst.addOperand(MCOperand::CreateImm(0));
+
+  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
+  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
+  return true;
+}
+
 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
 /// when they refer multiple MIOperands inside a single one.

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139270&r1=139269&r2=139270&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep  7 19:39:19 2011
@@ -548,6 +548,9 @@
         ldr r8, [r8, r2, lsl #2]
         ldr r7, [sp, r2, lsl #1]
         ldr r7, [sp, r2, lsl #0]
+        ldr r2, [r4, #255]!
+        ldr r8, [sp, #4]!
+        ldr lr, [sp, #-4]!
 
 @ CHECK: ldr.w	r1, [r8, r1]            @ encoding: [0x58,0xf8,0x01,0x10]
 @ CHECK: ldr.w	r4, [r5, r2]            @ encoding: [0x55,0xf8,0x02,0x40]
@@ -555,6 +558,9 @@
 @ CHECK: ldr.w	r8, [r8, r2, lsl #2]    @ encoding: [0x58,0xf8,0x22,0x80]
 @ CHECK: ldr.w	r7, [sp, r2, lsl #1]    @ encoding: [0x5d,0xf8,0x12,0x70]
 @ CHECK: ldr.w	r7, [sp, r2]            @ encoding: [0x5d,0xf8,0x02,0x70]
+@ CHECK: ldr	r2, [r4, #255]!         @ encoding: [0x54,0xf8,0xff,0x2f]
+@ CHECK: ldr	r8, [sp, #4]!           @ encoding: [0x5d,0xf8,0x04,0x8f]
+@ CHECK: ldr	lr, [sp, #-4]!          @ encoding: [0x5d,0xf8,0x04,0xed]
 
 
 @------------------------------------------------------------------------------



From krasin at chromium.org  Wed Sep  7 19:42:16 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Wed, 7 Sep 2011 17:42:16 -0700
Subject: [llvm-commits] [PATCH]lto/addAsmGlobalSymbols: fail fracefully when
 the target does not define AsmParser
Message-ID: <CAOei5RdvnVG8wpG8Sr3FLz97g9Efw-P7D0_wYgR+o=BYvGCi8Q@mail.gmail.com>

Hi llvm team,

this patch makes LTO fail gracefully if the target does not define
AsmParser instead of aborting on null pointer.

Please, find the patch attached or online:
http://codereview.chromium.org/7847007/

OK to commit?

krasin
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From eli.friedman at gmail.com  Wed Sep  7 19:48:26 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 7 Sep 2011 17:48:26 -0700
Subject: [llvm-commits] [PATCH]lto/addAsmGlobalSymbols: fast path when
 no module level asm is present
In-Reply-To: <CAOei5ReYh8CnQjz6x9pgrMscvjZPS6UMU4Gi-XwQXNpqoW-OYg@mail.gmail.com>
References: <CAOei5ReYh8CnQjz6x9pgrMscvjZPS6UMU4Gi-XwQXNpqoW-OYg@mail.gmail.com>
Message-ID: <CAJdarcEpgyMcw=1nxrrUXyaYV6_0sV3PPHmLvC-GdyFjGUvegg@mail.gmail.com>

On Wed, Sep 7, 2011 at 5:38 PM, Ivan Krasin <krasin at chromium.org> wrote:
> Hi llvm team,
>
> this patch adds a fast path for LTOModule::addAsmGlobalSymbols when
> where's no assembly defined in the module.
>
> Please, find the patch attached or online:
> http://codereview.chromium.org/7850008/
>
> OK to commit?

Yes, fine.

-Eli

From eli.friedman at gmail.com  Wed Sep  7 19:51:39 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 7 Sep 2011 17:51:39 -0700
Subject: [llvm-commits] [PATCH]lto/addAsmGlobalSymbols: fail fracefully
 when the target does not define AsmParser
In-Reply-To: <CAOei5RdvnVG8wpG8Sr3FLz97g9Efw-P7D0_wYgR+o=BYvGCi8Q@mail.gmail.com>
References: <CAOei5RdvnVG8wpG8Sr3FLz97g9Efw-P7D0_wYgR+o=BYvGCi8Q@mail.gmail.com>
Message-ID: <CAJdarcGPAt2h=JO-aZHVGRff1AVmn4w36XrOccTt_906EejSFA@mail.gmail.com>

On Wed, Sep 7, 2011 at 5:42 PM, Ivan Krasin <krasin at chromium.org> wrote:
> Hi llvm team,
>
> this patch makes LTO fail gracefully if the target does not define
> AsmParser instead of aborting on null pointer.
>
> Please, find the patch attached or online:
> http://codereview.chromium.org/7847007/
>
> OK to commit?

What exactly does the error output look like with this patch?  I'm
guessing it isn't that informative if you aren't setting errMsg...

-Eli

From grosbach at apple.com  Wed Sep  7 20:01:32 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Sep 2011 01:01:32 -0000
Subject: [llvm-commits] [llvm] r139272 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrThumb2.td
 test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110908010133.06CE32A6C12C@llvm.org>

Author: grosbach
Date: Wed Sep  7 20:01:32 2011
New Revision: 139272

URL: http://llvm.org/viewvc/llvm-project?rev=139272&view=rev
Log:
Thumb2 assembly parsing and encoding for LDR post-indexed.

More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=139272&r1=139271&r2=139272&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Sep  7 20:01:32 2011
@@ -1207,7 +1207,7 @@
 
   bits<4> Rt;
   bits<4> Rn;
-  bits<9> addr;
+  bits<9> offset;
   let Inst{31-27} = 0b11111;
   let Inst{26-25} = 0b00;
   let Inst{24}    = signed;
@@ -1219,9 +1219,9 @@
   let Inst{11}    = 1;
   // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
   let Inst{10}    = pre; // The P bit.
-  let Inst{9}     = addr{8}; // Sign bit
+  let Inst{9}     = offset{8}; // Sign bit
   let Inst{8}     = 1; // The W bit.
-  let Inst{7-0}   = addr{7-0};
+  let Inst{7-0}   = offset{7-0};
 }
 
 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139272&r1=139271&r2=139272&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep  7 20:01:32 2011
@@ -1253,9 +1253,9 @@
 }
 
 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
-                            (ins GPR:$Rn, t2am_imm8_offset:$addr),
-                            AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
-                            "ldr", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>;
+                          (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
+                          AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
+                          "ldr", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
 
 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
                             (ins t2addrmode_imm8:$addr),
@@ -1265,9 +1265,9 @@
   let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
 }
 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
-                            (ins GPR:$Rn, t2am_imm8_offset:$addr),
-                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
-                            "ldrb", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>;
+                          (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
+                          AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
+                          "ldrb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
 
 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
                             (ins t2addrmode_imm8:$addr),
@@ -1277,9 +1277,9 @@
   let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
 }
 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
-                            (ins GPR:$Rn, t2am_imm8_offset:$addr),
-                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
-                            "ldrh", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>;
+                          (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
+                          AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
+                          "ldrh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
 
 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
                             (ins t2addrmode_imm8:$addr),
@@ -1289,9 +1289,9 @@
   let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
 }
 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
-                            (ins GPR:$Rn, t2am_imm8_offset:$addr),
-                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
-                            "ldrsb", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>;
+                          (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
+                          AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
+                          "ldrsb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
 
 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
                             (ins t2addrmode_imm8:$addr),
@@ -1301,9 +1301,9 @@
   let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
 }
 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
-                            (ins GPR:$Rn, t2am_imm8_offset:$addr),
-                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
-                            "ldrsh", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>;
+                          (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
+                          AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
+                          "ldrsh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
 } // mayLoad = 1, neverHasSideEffects = 1
 
 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
@@ -1356,12 +1356,12 @@
                    (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
 
 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
-                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
+                            (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
                             AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
-                          "str", "\t$Rt, [$Rn], $addr",
+                          "str", "\t$Rt, $Rn, $offset",
                           "$Rn = $Rn_wb, at earlyclobber $Rn_wb",
              [(set GPRnopc:$Rn_wb,
-                  (post_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
+                  (post_store rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
 
 def t2STRH_PRE  : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
                             (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
@@ -1372,12 +1372,12 @@
               (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
 
 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
-                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
+                            (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
                             AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
-                         "strh", "\t$Rt, [$Rn], $addr",
+                         "strh", "\t$Rt, $Rn, $offset",
                          "$Rn = $Rn_wb, at earlyclobber $Rn_wb",
        [(set GPRnopc:$Rn_wb,
-             (post_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
+             (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
 
 def t2STRB_PRE  : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
                             (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
@@ -1388,12 +1388,12 @@
                (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
 
 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
-                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
+                            (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset),
                             AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
-                         "strb", "\t$Rt, [$Rn], $addr",
+                         "strb", "\t$Rt, $Rn, $offset",
                          "$Rn = $Rn_wb, at earlyclobber $Rn_wb",
         [(set GPRnopc:$Rn_wb,
-              (post_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
+              (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>;
 
 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
 // only.

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139272&r1=139271&r2=139272&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep  7 20:01:32 2011
@@ -551,6 +551,9 @@
         ldr r2, [r4, #255]!
         ldr r8, [sp, #4]!
         ldr lr, [sp, #-4]!
+        ldr r2, [r4], #255
+        ldr r8, [sp], #4
+        ldr lr, [sp], #-4
 
 @ CHECK: ldr.w	r1, [r8, r1]            @ encoding: [0x58,0xf8,0x01,0x10]
 @ CHECK: ldr.w	r4, [r5, r2]            @ encoding: [0x55,0xf8,0x02,0x40]
@@ -561,6 +564,9 @@
 @ CHECK: ldr	r2, [r4, #255]!         @ encoding: [0x54,0xf8,0xff,0x2f]
 @ CHECK: ldr	r8, [sp, #4]!           @ encoding: [0x5d,0xf8,0x04,0x8f]
 @ CHECK: ldr	lr, [sp, #-4]!          @ encoding: [0x5d,0xf8,0x04,0xed]
+@ CHECK: ldr	r2, [r4], #255          @ encoding: [0x54,0xf8,0xff,0x2b]
+@ CHECK: ldr	r8, [sp], #4            @ encoding: [0x5d,0xf8,0x04,0x8b]
+@ CHECK: ldr	lr, [sp], #-4           @ encoding: [0x5d,0xf8,0x04,0xe9]
 
 
 @------------------------------------------------------------------------------



From atrick at apple.com  Wed Sep  7 20:19:21 2011
From: atrick at apple.com (Andrew Trick)
Date: Wed, 07 Sep 2011 18:19:21 -0700
Subject: [llvm-commits] [llvm] r139250 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ test/MC/Disassembler/ARM/ utils/TableGen/
In-Reply-To: <CADiQthOBjzzbZ=7HTvp5eLu2+4egv1G+VRB2qN_+CUCMTz2R=w@mail.gmail.com>
References: <20110907194229.097E02A6C12C@llvm.org>
	<CADiQthOBjzzbZ=7HTvp5eLu2+4egv1G+VRB2qN_+CUCMTz2R=w@mail.gmail.com>
Message-ID: <49E8D98A-013B-4395-A94E-FA0B7927B9E9@apple.com>

Our windows testers are hitting it too. Let me know if you can confirm this is the cause.
-Andy

On Sep 7, 2011, at 5:07 PM, NAKAMURA Takumi wrote:

> 2011/9/8 James Molloy <james.molloy at arm.com>:
>> Author: jamesm
>> Date: Wed Sep  7 14:42:28 2011
>> New Revision: 139250
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=139250&view=rev
>> Log:
>> Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
>> 
>> Modified:
>>    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
>>    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/neon.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
>>    llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
>>    llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
>>    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
>>    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h
> 
> James, I saw weird emissions by tblgen, on cygwin gcc-4.3 and msvc10.
> I will investigate a few hours after, too.
> 
> ...Takumi
> <cyg.txt.gz><vs.txt.gz>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From eli.friedman at gmail.com  Wed Sep  7 21:23:31 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 08 Sep 2011 02:23:31 -0000
Subject: [llvm-commits] [llvm] r139276 - in /llvm/trunk:
 lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/gep-alias.ll
Message-ID: <20110908022331.DF8912A6C12C@llvm.org>

Author: efriedma
Date: Wed Sep  7 21:23:31 2011
New Revision: 139276

URL: http://llvm.org/viewvc/llvm-project?rev=139276&view=rev
Log:
Fix the logic in BasicAliasAnalysis::aliasGEP for comparing GEP's with variable differences so that it actually does something sane. Fixes PR10881.


Modified:
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
    llvm/trunk/test/Analysis/BasicAA/gep-alias.ll

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=139276&r1=139275&r2=139276&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Wed Sep  7 21:23:31 2011
@@ -955,43 +955,43 @@
   if (GEP1BaseOffset == 0 && GEP1VariableIndices.empty())
     return MustAlias;
 
-  // If there is a difference between the pointers, but the difference is
-  // less than the size of the associated memory object, then we know
-  // that the objects are partially overlapping.
+  // If there is a constant difference between the pointers, but the difference
+  // is less than the size of the associated memory object, then we know
+  // that the objects are partially overlapping.  If the difference is
+  // greater, we know they do not overlap.
   if (GEP1BaseOffset != 0 && GEP1VariableIndices.empty()) {
-    if (GEP1BaseOffset >= 0 ?
-        (V2Size != UnknownSize && (uint64_t)GEP1BaseOffset < V2Size) :
-        (V1Size != UnknownSize && -(uint64_t)GEP1BaseOffset < V1Size &&
-         GEP1BaseOffset != INT64_MIN))
-      return PartialAlias;
+    if (GEP1BaseOffset >= 0) {
+      if (V2Size != UnknownSize) {
+        if ((uint64_t)GEP1BaseOffset < V2Size)
+          return PartialAlias;
+        return NoAlias;
+      }
+    } else {
+      if (V1Size != UnknownSize) {
+        if (-(uint64_t)GEP1BaseOffset < V1Size)
+          return PartialAlias;
+        return NoAlias;
+      }
+    }
   }
 
-  // If we have a known constant offset, see if this offset is larger than the
-  // access size being queried.  If so, and if no variable indices can remove
-  // pieces of this constant, then we know we have a no-alias.  For example,
-  //   &A[100] != &A.
-  
-  // In order to handle cases like &A[100][i] where i is an out of range
-  // subscript, we have to ignore all constant offset pieces that are a multiple
-  // of a scaled index.  Do this by removing constant offsets that are a
-  // multiple of any of our variable indices.  This allows us to transform
-  // things like &A[i][1] because i has a stride of (e.g.) 8 bytes but the 1
-  // provides an offset of 4 bytes (assuming a <= 4 byte access).
+  // Try to distinguish something like &A[i][1] against &A[42][0].
+  // Grab the least significant bit set in any of the scales.
+  uint64_t Modulo = 0;
   for (unsigned i = 0, e = GEP1VariableIndices.size();
-       i != e && GEP1BaseOffset;++i)
-    if (int64_t RemovedOffset = GEP1BaseOffset/GEP1VariableIndices[i].Scale)
-      GEP1BaseOffset -= RemovedOffset*GEP1VariableIndices[i].Scale;
-  
-  // If our known offset is bigger than the access size, we know we don't have
-  // an alias.
-  if (GEP1BaseOffset) {
-    if (GEP1BaseOffset >= 0 ?
-        (V2Size != UnknownSize && (uint64_t)GEP1BaseOffset >= V2Size) :
-        (V1Size != UnknownSize && -(uint64_t)GEP1BaseOffset >= V1Size &&
-         GEP1BaseOffset != INT64_MIN))
-      return NoAlias;
-  }
-  
+       i != e; ++i)
+    Modulo |= (uint64_t)GEP1VariableIndices[0].Scale;
+  Modulo = Modulo ^ (Modulo & (Modulo - 1));
+
+  // We can compute the difference between the two addresses
+  // mod Modulo. Check whether that difference guarantees that the
+  // two locations do not alias.
+  uint64_t ModOffset = (uint64_t)GEP1BaseOffset & (Modulo - 1);
+  if (V1Size != UnknownSize && V2Size != UnknownSize &&
+      ModOffset >= V2Size && V1Size <= Modulo - ModOffset)
+    return NoAlias;
+
+
   // Statically, we can see that the base objects are the same, but the
   // pointers have dynamic offsets which we can't resolve. And none of our
   // little tricks above worked.

Modified: llvm/trunk/test/Analysis/BasicAA/gep-alias.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/gep-alias.ll?rev=139276&r1=139275&r2=139276&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/BasicAA/gep-alias.ll (original)
+++ llvm/trunk/test/Analysis/BasicAA/gep-alias.ll Wed Sep  7 21:23:31 2011
@@ -169,3 +169,35 @@
 ; CHECK: @test10
 ; CHECK: ret i8 0
 }
+
+; (This was a miscompilation.)
+define float @test11(i32 %indvar, [4 x [2 x float]]* %q) nounwind ssp {
+  %tmp = mul i32 %indvar, -1
+  %dec = add i32 %tmp, 3
+  %scevgep = getelementptr [4 x [2 x float]]* %q, i32 0, i32 %dec
+  %scevgep35 = bitcast [2 x float]* %scevgep to i64*
+  %arrayidx28 = getelementptr inbounds [4 x [2 x float]]* %q, i32 0, i32 0
+  %y29 = getelementptr inbounds [2 x float]* %arrayidx28, i32 0, i32 1
+  store float 1.0, float* %y29, align 4
+  store i64 0, i64* %scevgep35, align 4
+  %tmp30 = load float* %y29, align 4
+  ret float %tmp30
+  ; CHECK: @test11
+  ; CHECK: ret float %tmp30
+}
+
+; (This was a miscompilation.)
+define i32 @test12(i32 %x, i32 %y, i8* %p) nounwind {
+  %a = bitcast i8* %p to [13 x i8]*
+  %b = getelementptr [13 x i8]* %a, i32 %x
+  %c = bitcast [13 x i8]* %b to [15 x i8]*
+  %d = getelementptr [15 x i8]* %c, i32 %y, i32 8
+  %castd = bitcast i8* %d to i32*
+  %castp = bitcast i8* %p to i32*
+  store i32 1, i32* %castp
+  store i32 0, i32* %castd
+  %r = load i32* %castp
+  ret i32 %r
+  ; CHECK: @test12
+  ; CHECK: ret i32 %r
+}



From eli.friedman at gmail.com  Wed Sep  7 21:37:07 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 08 Sep 2011 02:37:07 -0000
Subject: [llvm-commits] [llvm] r139277 -
	/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
Message-ID: <20110908023707.BBCDF2A6C12C@llvm.org>

Author: efriedma
Date: Wed Sep  7 21:37:07 2011
New Revision: 139277

URL: http://llvm.org/viewvc/llvm-project?rev=139277&view=rev
Log:
A couple minor corrections to r139276.


Modified:
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=139277&r1=139276&r2=139277&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Wed Sep  7 21:37:07 2011
@@ -977,20 +977,20 @@
 
   // Try to distinguish something like &A[i][1] against &A[42][0].
   // Grab the least significant bit set in any of the scales.
-  uint64_t Modulo = 0;
-  for (unsigned i = 0, e = GEP1VariableIndices.size();
-       i != e; ++i)
-    Modulo |= (uint64_t)GEP1VariableIndices[0].Scale;
-  Modulo = Modulo ^ (Modulo & (Modulo - 1));
-
-  // We can compute the difference between the two addresses
-  // mod Modulo. Check whether that difference guarantees that the
-  // two locations do not alias.
-  uint64_t ModOffset = (uint64_t)GEP1BaseOffset & (Modulo - 1);
-  if (V1Size != UnknownSize && V2Size != UnknownSize &&
-      ModOffset >= V2Size && V1Size <= Modulo - ModOffset)
-    return NoAlias;
-
+  if (!GEP1VariableIndices.empty()) {
+    uint64_t Modulo = 0;
+    for (unsigned i = 0, e = GEP1VariableIndices.size(); i != e; ++i)
+      Modulo |= (uint64_t)GEP1VariableIndices[i].Scale;
+    Modulo = Modulo ^ (Modulo & (Modulo - 1));
+
+    // We can compute the difference between the two addresses
+    // mod Modulo. Check whether that difference guarantees that the
+    // two locations do not alias.
+    uint64_t ModOffset = (uint64_t)GEP1BaseOffset & (Modulo - 1);
+    if (V1Size != UnknownSize && V2Size != UnknownSize &&
+        ModOffset >= V2Size && V1Size <= Modulo - ModOffset)
+      return NoAlias;
+  }
 
   // Statically, we can see that the base objects are the same, but the
   // pointers have dynamic offsets which we can't resolve. And none of our



From atrick at apple.com  Thu Sep  8 00:23:15 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 08 Sep 2011 05:23:15 -0000
Subject: [llvm-commits] [llvm] r139278 -
	/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
Message-ID: <20110908052315.0D4C82A6C12C@llvm.org>

Author: atrick
Date: Thu Sep  8 00:23:14 2011
New Revision: 139278

URL: http://llvm.org/viewvc/llvm-project?rev=139278&view=rev
Log:
whitespace

Modified:
    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp

Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=139278&r1=139277&r2=139278&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Thu Sep  8 00:23:14 2011
@@ -749,7 +749,7 @@
     for (OperandInfo::iterator OI = OpInfo.begin(), OE = OpInfo.end();
          OI != OE; ++OI) {
       o.indent(Indentation) << "  tmp |= (fieldFromInstruction" << BitWidth
-                            << "(insn, " << OI->Base << ", " << OI->Width 
+                            << "(insn, " << OI->Base << ", " << OI->Width
                             << ") << " << OI->Offset << ");\n";
     }
   }
@@ -797,7 +797,7 @@
     emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace);
   }
   return Predicates->getSize() > 0;
-}  
+}
 
 // Emits code to decode the singleton.  Return true if we have matched all the
 // well-known bits.



From atrick at apple.com  Thu Sep  8 00:25:49 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 08 Sep 2011 05:25:49 -0000
Subject: [llvm-commits] [llvm] r139279 -
	/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
Message-ID: <20110908052549.AFEE12A6C12C@llvm.org>

Author: atrick
Date: Thu Sep  8 00:25:49 2011
New Revision: 139279

URL: http://llvm.org/viewvc/llvm-project?rev=139279&view=rev
Log:
Fix a use of freed string contents.

Speculatively try to fix our windows testers with a patch I found on the internet.

Modified:
    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp

Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=139279&r1=139278&r2=139279&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Thu Sep  8 00:25:49 2011
@@ -764,11 +764,11 @@
 
 static void emitSinglePredicateMatch(raw_ostream &o, StringRef str,
                                      std::string PredicateNamespace) {
-  const char *X = str.str().c_str();
-  if (X[0] == '!')
-    o << "!(Bits & " << PredicateNamespace << "::" << &X[1] << ")";
+  if (str[0] == '!')
+    o << "!(Bits & " << PredicateNamespace << "::"
+      << str.slice(1,str.size()) << ")";
   else
-    o << "(Bits & " << PredicateNamespace << "::" << X << ")";
+    o << "(Bits & " << PredicateNamespace << "::" << str << ")";
 }
 
 bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation,



From dblaikie at gmail.com  Thu Sep  8 00:32:49 2011
From: dblaikie at gmail.com (David Blaikie)
Date: Thu, 08 Sep 2011 05:32:49 -0000
Subject: [llvm-commits] [llvm] r139280 - /llvm/trunk/CREDITS.TXT
Message-ID: <20110908053249.641922A6C12C@llvm.org>

Author: dblaikie
Date: Thu Sep  8 00:32:49 2011
New Revision: 139280

URL: http://llvm.org/viewvc/llvm-project?rev=139280&view=rev
Log:
Adding myself to test my new commit powers.

Modified:
    llvm/trunk/CREDITS.TXT

Modified: llvm/trunk/CREDITS.TXT
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=139280&r1=139279&r2=139280&view=diff
==============================================================================
--- llvm/trunk/CREDITS.TXT (original)
+++ llvm/trunk/CREDITS.TXT Thu Sep  8 00:32:49 2011
@@ -32,6 +32,10 @@
 D: ET-Forest implementation.
 D: Sparse bitmap
 
+N: David Blaikie
+E: dblaikie at gmail.com
+D: General bug fixing/fit & finish, mostly in Clang
+
 N: Neil Booth
 E: neil at daikokuya.co.uk
 D: APFloat implementation.



From krasin at chromium.org  Thu Sep  8 02:13:54 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Thu, 8 Sep 2011 00:13:54 -0700
Subject: [llvm-commits] [PATCH]lto/addAsmGlobalSymbols: fail fracefully
 when the target does not define AsmParser
In-Reply-To: <CAJdarcGPAt2h=JO-aZHVGRff1AVmn4w36XrOccTt_906EejSFA@mail.gmail.com>
References: <CAOei5RdvnVG8wpG8Sr3FLz97g9Efw-P7D0_wYgR+o=BYvGCi8Q@mail.gmail.com>
	<CAJdarcGPAt2h=JO-aZHVGRff1AVmn4w36XrOccTt_906EejSFA@mail.gmail.com>
Message-ID: <CAOei5RcrR_3qf3KwoYkmMPBP9+wBe+qd4gog72g=uoRQoGG9Mw@mail.gmail.com>

On Wed, Sep 7, 2011 at 5:51 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Wed, Sep 7, 2011 at 5:42 PM, Ivan Krasin <krasin at chromium.org> wrote:
>> Hi llvm team,
>>
>> this patch makes LTO fail gracefully if the target does not define
>> AsmParser instead of aborting on null pointer.
>>
>> Please, find the patch attached or online:
>> http://codereview.chromium.org/7847007/
>>
>> OK to commit?
>
> What exactly does the error output look like with this patch? ?I'm
> guessing it isn't that informative if you aren't setting errMsg...
Thanks, Eli, it's a good comment. Could you please take a look at it now?

Note: it appears that gold-plugin does not use lto_get_error_message
at all, so this assigned message will be unused in gold-plugin (but
will be used in other proper clients of tools/lto).
Should I fix gold plugin as well (as a separate patch)?

krasin
>
> -Eli
>
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From james.molloy at arm.com  Thu Sep  8 02:26:05 2011
From: james.molloy at arm.com (James Molloy)
Date: Thu, 8 Sep 2011 08:26:05 +0100
Subject: [llvm-commits] [llvm] r139250 - in /llvm/trunk:
	lib/Target/ARM/Disassembler/ test/MC/Disassembler/ARM/
	utils/TableGen/
In-Reply-To: <49E8D98A-013B-4395-A94E-FA0B7927B9E9@apple.com>
References: <20110907194229.097E02A6C12C@llvm.org>
	<CADiQthOBjzzbZ=7HTvp5eLu2+4egv1G+VRB2qN_+CUCMTz2R=w@mail.gmail.com>
	<49E8D98A-013B-4395-A94E-FA0B7927B9E9@apple.com>
Message-ID: <000c01cc6df8$921309e0$b6391da0$@molloy@arm.com>

Hi,

I don't see this, at least on linux with gcc 4.1.2.

Our windows buildbot picked a warning up in FixedLenDecoderEmitter.cpp:857 - is
that what you're referring to? I'll fix that now.

Otherwise, if you could provide an example of the warning/error, that would be
much appreciated.

Cheers,

James

> -----Original Message-----
> From: Andrew Trick [mailto:atrick at apple.com]
> Sent: 08 September 2011 02:19
> To: NAKAMURA Takumi; James Molloy
> Cc: llvm-commits
> Subject: Re: [llvm-commits] [llvm] r139250 - in /llvm/trunk:
> lib/Target/ARM/Disassembler/ test/MC/Disassembler/ARM/ utils/TableGen/
> 
> Our windows testers are hitting it too. Let me know if you can confirm this
> is the cause.
> -Andy
> 
> On Sep 7, 2011, at 5:07 PM, NAKAMURA Takumi wrote:
> 
> > 2011/9/8 James Molloy <james.molloy at arm.com>:
> >> Author: jamesm
> >> Date: Wed Sep  7 14:42:28 2011
> >> New Revision: 139250
> >>
> >> URL: http://llvm.org/viewvc/llvm-project?rev=139250&view=rev
> >> Log:
> >> Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This
> adds predicate checking to the Disassembler.
> >>
> >> Modified:
> >>    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> >>    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/neon.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
> >>    llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
> >>    llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
> >>    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
> >>    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h
> >
> > James, I saw weird emissions by tblgen, on cygwin gcc-4.3 and msvc10.
> > I will investigate a few hours after, too.
> >
> > ...Takumi
> > <cyg.txt.gz><vs.txt.gz>_______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 




From baldrick at free.fr  Thu Sep  8 02:31:00 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 08 Sep 2011 09:31:00 +0200
Subject: [llvm-commits] [llvm] r139263 -
	/llvm/trunk/lib/Target/README.txt
In-Reply-To: <20110907224926.A9B8C2A6C12C@llvm.org>
References: <20110907224926.A9B8C2A6C12C@llvm.org>
Message-ID: <4E686F34.3010200@free.fr>

Hi Benjamin,

>   //===---------------------------------------------------------------------===//
> +
> +unsigned foo(unsigned x, unsigned y) { return (x&  y) == 0 || x == 0; }
> +should fold to (x&  y) == 0.
> +
> +//===---------------------------------------------------------------------===//
> +
> +unsigned foo(unsigned x, unsigned y) { return x>  y&&  x != 0; }
> +should fold to x>  y.
> +
> +//===---------------------------------------------------------------------===//

according to my bitcode harvester these kinds of things are the most common
simplifications that could be handled by instsimplify but aren't.  I have a
plan, but no time :(

Ciao, Duncan.

From eli.friedman at gmail.com  Thu Sep  8 02:34:47 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 8 Sep 2011 00:34:47 -0700
Subject: [llvm-commits] [PATCH]lto/addAsmGlobalSymbols: fail fracefully
 when the target does not define AsmParser
In-Reply-To: <CAOei5RcrR_3qf3KwoYkmMPBP9+wBe+qd4gog72g=uoRQoGG9Mw@mail.gmail.com>
References: <CAOei5RdvnVG8wpG8Sr3FLz97g9Efw-P7D0_wYgR+o=BYvGCi8Q@mail.gmail.com>
	<CAJdarcGPAt2h=JO-aZHVGRff1AVmn4w36XrOccTt_906EejSFA@mail.gmail.com>
	<CAOei5RcrR_3qf3KwoYkmMPBP9+wBe+qd4gog72g=uoRQoGG9Mw@mail.gmail.com>
Message-ID: <CAJdarcHDF_rH6C--WZ9ygVd+oosCYiVshk5-nEU67_SJ1CJMQA@mail.gmail.com>

On Thu, Sep 8, 2011 at 12:13 AM, Ivan Krasin <krasin at chromium.org> wrote:
> On Wed, Sep 7, 2011 at 5:51 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
>> On Wed, Sep 7, 2011 at 5:42 PM, Ivan Krasin <krasin at chromium.org> wrote:
>>> Hi llvm team,
>>>
>>> this patch makes LTO fail gracefully if the target does not define
>>> AsmParser instead of aborting on null pointer.
>>>
>>> Please, find the patch attached or online:
>>> http://codereview.chromium.org/7847007/
>>>
>>> OK to commit?
>>
>> What exactly does the error output look like with this patch? ?I'm
>> guessing it isn't that informative if you aren't setting errMsg...
> Thanks, Eli, it's a good comment. Could you please take a look at it now?

Looks fine.

> Note: it appears that gold-plugin does not use lto_get_error_message
> at all, so this assigned message will be unused in gold-plugin (but
> will be used in other proper clients of tools/lto).
> Should I fix gold plugin as well (as a separate patch)?

That would be nice.

-Eli


From james.molloy at arm.com  Thu Sep  8 02:34:45 2011
From: james.molloy at arm.com (James Molloy)
Date: Thu, 8 Sep 2011 08:34:45 +0100
Subject: [llvm-commits] [llvm] r139279
	-	/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
In-Reply-To: <20110908052549.AFEE12A6C12C@llvm.org>
References: <20110908052549.AFEE12A6C12C@llvm.org>
Message-ID: <000d01cc6df9$c86db8e0$59492aa0$@molloy@arm.com>

Hi Andrew,

Thanks for fixing this - interesting that neither our windows build nor our
linux builds picked this up.

The alternative would have been to declare the return value from .str() as a
stack-local variable, then it would have been forced to exist for the entire
stack frame.

Rookie mistake on my part, sorry!

James 

> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of Andrew Trick
> Sent: 08 September 2011 06:26
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm-commits] [llvm] r139279 -
> /llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
> 
> Author: atrick
> Date: Thu Sep  8 00:25:49 2011
> New Revision: 139279
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=139279&view=rev
> Log:
> Fix a use of freed string contents.
> 
> Speculatively try to fix our windows testers with a patch I found on the
> internet.
> 
> Modified:
>     llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
> 
> Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=139279&r1=
> 139278&r2=139279&view=diff
> ===========================================================================
> ===
> --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Thu Sep  8
> 00:25:49 2011
> @@ -764,11 +764,11 @@
> 
>  static void emitSinglePredicateMatch(raw_ostream &o, StringRef str,
>                                       std::string PredicateNamespace) {
> -  const char *X = str.str().c_str();
> -  if (X[0] == '!')
> -    o << "!(Bits & " << PredicateNamespace << "::" << &X[1] << ")";
> +  if (str[0] == '!')
> +    o << "!(Bits & " << PredicateNamespace << "::"
> +      << str.slice(1,str.size()) << ")";
>    else
> -    o << "(Bits & " << PredicateNamespace << "::" << X << ")";
> +    o << "(Bits & " << PredicateNamespace << "::" << str << ")";
>  }
> 
>  bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned
> &Indentation,
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From krasin at chromium.org  Thu Sep  8 02:36:39 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Thu, 08 Sep 2011 07:36:39 -0000
Subject: [llvm-commits] [llvm] r139283 - in /llvm/trunk/tools/lto:
	LTOModule.cpp LTOModule.h
Message-ID: <20110908073639.42B9F2A6C12D@llvm.org>

Author: krasin
Date: Thu Sep  8 02:36:39 2011
New Revision: 139283

URL: http://llvm.org/viewvc/llvm-project?rev=139283&view=rev
Log:
lto/addAsmGlobalSymbols: fail fracefully when the target does not define AsmParser.


Modified:
    llvm/trunk/tools/lto/LTOModule.cpp
    llvm/trunk/tools/lto/LTOModule.h

Modified: llvm/trunk/tools/lto/LTOModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=139283&r1=139282&r2=139283&view=diff
==============================================================================
--- llvm/trunk/tools/lto/LTOModule.cpp (original)
+++ llvm/trunk/tools/lto/LTOModule.cpp Thu Sep  8 02:36:39 2011
@@ -165,7 +165,7 @@
   std::string CPU;
   TargetMachine *target = march->createTargetMachine(Triple, CPU, FeatureStr);
   LTOModule *Ret = new LTOModule(m.take(), target);
-  bool Err = Ret->ParseSymbols();
+  bool Err = Ret->ParseSymbols(errMsg);
   if (Err) {
     delete Ret;
     return NULL;
@@ -613,7 +613,7 @@
   };
 }
 
-bool LTOModule::addAsmGlobalSymbols(MCContext &Context) {
+bool LTOModule::addAsmGlobalSymbols(MCContext &Context, std::string &errMsg) {
   const std::string &inlineAsm = _module->getModuleInlineAsm();
 
   OwningPtr<RecordStreamer> Streamer(new RecordStreamer(Context));
@@ -629,6 +629,12 @@
                                             _target->getTargetFeatureString()));
   OwningPtr<MCTargetAsmParser>
     TAP(_target->getTarget().createMCAsmParser(*STI, *Parser.get()));
+  if (!TAP) {
+    errMsg = "target " + std::string(_target->getTarget().getName()) +
+        " does not define AsmParser.";
+    return true;
+  }
+
   Parser->setTargetParser(*TAP);
   int Res = Parser->Run(false);
   if (Res)
@@ -661,7 +667,7 @@
   return isDeclaration(*V.getAliasedGlobal());
 }
 
-bool LTOModule::ParseSymbols() {
+bool LTOModule::ParseSymbols(std::string &errMsg) {
   // Use mangler to add GlobalPrefix to names to match linker names.
   MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(),NULL);
   Mangler mangler(Context, *_target->getTargetData());
@@ -684,7 +690,7 @@
   }
 
   // add asm globals
-  if (addAsmGlobalSymbols(Context))
+  if (addAsmGlobalSymbols(Context, errMsg))
     return true;
 
   // add aliases

Modified: llvm/trunk/tools/lto/LTOModule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.h?rev=139283&r1=139282&r2=139283&view=diff
==============================================================================
--- llvm/trunk/tools/lto/LTOModule.h (original)
+++ llvm/trunk/tools/lto/LTOModule.h Thu Sep  8 02:36:39 2011
@@ -76,7 +76,7 @@
 private:
                             LTOModule(llvm::Module* m, llvm::TargetMachine* t);
 
-    bool                    ParseSymbols();
+    bool                    ParseSymbols(std::string &errMsg);
     void                    addDefinedSymbol(llvm::GlobalValue* def, 
                                                     llvm::Mangler& mangler, 
                                                     bool isFunction);
@@ -86,7 +86,8 @@
                                                         llvm::Mangler &mangler);
     void                    addDefinedDataSymbol(llvm::GlobalValue* v, 
                                                         llvm::Mangler &mangler);
-    bool                    addAsmGlobalSymbols(llvm::MCContext &Context);
+    bool                    addAsmGlobalSymbols(llvm::MCContext &Context,
+                                                std::string &errMsg);
     void                    addAsmGlobalSymbol(const char *,
                                                lto_symbol_attributes scope);
     void                    addAsmGlobalSymbolUndef(const char *);



From krasin at google.com  Thu Sep  8 02:38:12 2011
From: krasin at google.com (Ivan Krasin)
Date: Thu, 8 Sep 2011 00:38:12 -0700
Subject: [llvm-commits] [PATCH]lto/addAsmGlobalSymbols: fail fracefully
 when the target does not define AsmParser
In-Reply-To: <CAJdarcHDF_rH6C--WZ9ygVd+oosCYiVshk5-nEU67_SJ1CJMQA@mail.gmail.com>
References: <CAOei5RdvnVG8wpG8Sr3FLz97g9Efw-P7D0_wYgR+o=BYvGCi8Q@mail.gmail.com>
	<CAJdarcGPAt2h=JO-aZHVGRff1AVmn4w36XrOccTt_906EejSFA@mail.gmail.com>
	<CAOei5RcrR_3qf3KwoYkmMPBP9+wBe+qd4gog72g=uoRQoGG9Mw@mail.gmail.com>
	<CAJdarcHDF_rH6C--WZ9ygVd+oosCYiVshk5-nEU67_SJ1CJMQA@mail.gmail.com>
Message-ID: <CAOei5Rfxj1i0JFXDN+znn6Hah1CoSa844NvwiKcwHYsRGUKooQ@mail.gmail.com>

Thanks, r139283.

On Thu, Sep 8, 2011 at 12:34 AM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Thu, Sep 8, 2011 at 12:13 AM, Ivan Krasin <krasin at chromium.org> wrote:
>> On Wed, Sep 7, 2011 at 5:51 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
>>> On Wed, Sep 7, 2011 at 5:42 PM, Ivan Krasin <krasin at chromium.org> wrote:
>>>> Hi llvm team,
>>>>
>>>> this patch makes LTO fail gracefully if the target does not define
>>>> AsmParser instead of aborting on null pointer.
>>>>
>>>> Please, find the patch attached or online:
>>>> http://codereview.chromium.org/7847007/
>>>>
>>>> OK to commit?
>>>
>>> What exactly does the error output look like with this patch? ?I'm
>>> guessing it isn't that informative if you aren't setting errMsg...
>> Thanks, Eli, it's a good comment. Could you please take a look at it now?
>
> Looks fine.
>
>> Note: it appears that gold-plugin does not use lto_get_error_message
>> at all, so this assigned message will be unused in gold-plugin (but
>> will be used in other proper clients of tools/lto).
>> Should I fix gold plugin as well (as a separate patch)?
>
> That would be nice.
>
> -Eli
>


From krasin at chromium.org  Thu Sep  8 02:38:25 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Thu, 08 Sep 2011 07:38:25 -0000
Subject: [llvm-commits] [llvm] r139284 - /llvm/trunk/tools/lto/LTOModule.cpp
Message-ID: <20110908073825.D28112A6C12D@llvm.org>

Author: krasin
Date: Thu Sep  8 02:38:25 2011
New Revision: 139284

URL: http://llvm.org/viewvc/llvm-project?rev=139284&view=rev
Log:
lto/addAsmGlobalSymbols: fast path when no module level asm is present.


Modified:
    llvm/trunk/tools/lto/LTOModule.cpp

Modified: llvm/trunk/tools/lto/LTOModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=139284&r1=139283&r2=139284&view=diff
==============================================================================
--- llvm/trunk/tools/lto/LTOModule.cpp (original)
+++ llvm/trunk/tools/lto/LTOModule.cpp Thu Sep  8 02:38:25 2011
@@ -615,6 +615,8 @@
 
 bool LTOModule::addAsmGlobalSymbols(MCContext &Context, std::string &errMsg) {
   const std::string &inlineAsm = _module->getModuleInlineAsm();
+  if (inlineAsm.empty())
+    return false;
 
   OwningPtr<RecordStreamer> Streamer(new RecordStreamer(Context));
   MemoryBuffer *Buffer = MemoryBuffer::getMemBuffer(inlineAsm);



From dblaikie at gmail.com  Thu Sep  8 02:43:18 2011
From: dblaikie at gmail.com (David Blaikie)
Date: Thu, 8 Sep 2011 00:43:18 -0700
Subject: [llvm-commits] [llvm] r139279 -
	/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
In-Reply-To: <20110908052549.AFEE12A6C12C@llvm.org>
References: <20110908052549.AFEE12A6C12C@llvm.org>
Message-ID: <CAENS6EuSXkNzU5VN86M5GjEtijUtWewbstLt2-mT31bkZZSi4g@mail.gmail.com>

>
> str.slice(1,str.size())
>

This could be written more simply as str.substr(1), if I'm not mistaken.

- David
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From krasin at chromium.org  Thu Sep  8 02:50:06 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Thu, 8 Sep 2011 00:50:06 -0700
Subject: [llvm-commits] gold plugin: report errors occured in
	lto_module_create_from_*
Message-ID: <CAOei5RdN2tE5mb_fxUqRG+7o1dSWKnnh7KWuR2i8YgqDCH1cEg@mail.gmail.com>

Hi llvm team!

It appears that gold plugin does not check for errors occured in
lto_module_create_from_*. It just silently returns with LDPS_OK
status.
This patch makes it to report occurred errors (if any).

Is it fine to commit?

krasin
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From nadav.rotem at intel.com  Thu Sep  8 03:11:20 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Thu, 08 Sep 2011 08:11:20 -0000
Subject: [llvm-commits] [llvm] r139285 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/Generic/promote-integers.ll
Message-ID: <20110908081120.3B4E02A6C12D@llvm.org>

Author: nadav
Date: Thu Sep  8 03:11:19 2011
New Revision: 139285

URL: http://llvm.org/viewvc/llvm-project?rev=139285&view=rev
Log:
Add X86-SSE4 codegen support for vector-select.


Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/Generic/promote-integers.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139285&r1=139284&r2=139285&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep  8 03:11:19 2011
@@ -917,6 +917,13 @@
     setOperationAction(ISD::SHL,                MVT::v4i32, Custom);
     setOperationAction(ISD::SHL,                MVT::v16i8, Custom);
 
+    setOperationAction(ISD::VSELECT,            MVT::v2f64, Custom);
+    setOperationAction(ISD::VSELECT,            MVT::v2i64, Custom);
+    setOperationAction(ISD::VSELECT,            MVT::v16i8, Custom);
+    setOperationAction(ISD::VSELECT,            MVT::v8i16, Custom);
+    setOperationAction(ISD::VSELECT,            MVT::v4i32, Custom);
+    setOperationAction(ISD::VSELECT,            MVT::v4f32, Custom);
+
     // i8 and i16 vectors are custom , because the source register and source
     // source memory operand types are not the same width.  f32 vectors are
     // custom since the immediate controlling the insert encodes additional
@@ -8684,6 +8691,32 @@
   return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
 }
 
+SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
+  SDValue Cond  = Op.getOperand(0);
+  SDValue Op1 = Op.getOperand(1);
+  SDValue Op2 = Op.getOperand(2);
+  DebugLoc DL = Op.getDebugLoc();
+
+  SDValue Ops[] = {Cond, Op1, Op2};
+
+  assert(Op1.getValueType().isVector() && "Op1 must be a vector");
+  assert(Op2.getValueType().isVector() && "Op2 must be a vector");
+  assert(Cond.getValueType().isVector() && "Cond must be a vector");
+  assert(Op1.getValueType() == Op2.getValueType() && "Type mismatch");
+  
+  switch (Op1.getValueType().getSimpleVT().SimpleTy) {
+    default: break;
+    case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
+    case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
+    case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
+    case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
+    case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
+  }
+  
+  return SDValue();
+}
+
+
 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
 // from the AND / OR.
@@ -10350,6 +10383,7 @@
   case ISD::FGETSIGN:           return LowerFGETSIGN(Op, DAG);
   case ISD::SETCC:              return LowerSETCC(Op, DAG);
   case ISD::SELECT:             return LowerSELECT(Op, DAG);
+  case ISD::VSELECT:            return LowerVSELECT(Op, DAG);
   case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
   case ISD::VASTART:            return LowerVASTART(Op, DAG);

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=139285&r1=139284&r2=139285&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Sep  8 03:11:19 2011
@@ -175,8 +175,10 @@
       /// PSIGNB/W/D - Copy integer sign.
       PSIGNB, PSIGNW, PSIGND,
 
-      /// PBLENDVB - Variable blend
+      /// BLENDVXX family of opcodes
       PBLENDVB,
+      BLENDVPD,
+      BLENDVPS,
 
       /// FMAX, FMIN - Floating point max and min.
       ///
@@ -809,6 +811,7 @@
     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;

Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=139285&r1=139284&r2=139285&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Thu Sep  8 03:11:19 2011
@@ -58,9 +58,15 @@
 def X86psignd  : SDNode<"X86ISD::PSIGND",
                  SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>]>>;
-def X86pblendv : SDNode<"X86ISD::PBLENDVB",
+def X86pblendvb : SDNode<"X86ISD::PBLENDVB",
                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
+def X86blendvpd : SDNode<"X86ISD::BLENDVPD", 
+                  SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
+                                       SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
+def X86blendvps : SDNode<"X86ISD::BLENDVPS", 
+                 SDTypeProfile<1, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
+                                      SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
 def X86pextrw  : SDNode<"X86ISD::PEXTRW",

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139285&r1=139284&r2=139285&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep  8 03:11:19 2011
@@ -5843,7 +5843,7 @@
 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
                                          memopv32i8, int_x86_avx_blendv_ps_256>;
 
-def : Pat<(X86pblendv VR128:$src1, VR128:$src2, VR128:$src3),
+def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, VR128:$src3),
           (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$src3)>,
           Requires<[HasAVX]>;
 
@@ -5871,8 +5871,12 @@
 defm BLENDVPS     : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
 defm PBLENDVB     : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
 
-def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
+def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0),
           (PBLENDVBrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
+def : Pat<(X86blendvpd  XMM0, VR128:$src1, VR128:$src2),
+          (BLENDVPDrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
+def : Pat<(X86blendvps  XMM0, VR128:$src1, VR128:$src2),
+          (BLENDVPSrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
 
 let Predicates = [HasAVX] in
 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),

Modified: llvm/trunk/test/CodeGen/Generic/promote-integers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/promote-integers.ll?rev=139285&r1=139284&r2=139285&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Generic/promote-integers.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/promote-integers.ll Thu Sep  8 03:11:19 2011
@@ -3,8 +3,8 @@
 
 ; This test is the poster-child for integer-element-promotion.
 ; Until this feature is complete, we mark this test as expected to fail.
-; XFAIL: *
 ; CHECK: vector_code
+; CHECK: blend
 ; CHECK: ret
 define <4 x float> @vector_code(<4 x i64> %A, <4 x i64> %B, <4 x float> %R0, <4 x float> %R1 )  {
    %C = icmp eq <4 x i64> %A, %B



From james.molloy at arm.com  Thu Sep  8 03:12:01 2011
From: james.molloy at arm.com (James Molloy)
Date: Thu, 08 Sep 2011 08:12:01 -0000
Subject: [llvm-commits] [llvm] r139286 -
	/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
Message-ID: <20110908081201.EC6BE2A6C12D@llvm.org>

Author: jamesm
Date: Thu Sep  8 03:12:01 2011
New Revision: 139286

URL: http://llvm.org/viewvc/llvm-project?rev=139286&view=rev
Log:
Fix warning on windows; use of comparison with bool argument.

Modified:
    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp

Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=139286&r1=139285&r2=139286&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Thu Sep  8 03:12:01 2011
@@ -854,7 +854,7 @@
   }
 
   o.indent(Indentation) << "if (";
-  if (emitPredicateMatch(o, Indentation, Opc) > 0) {
+  if (emitPredicateMatch(o, Indentation, Opc)) {
     o << " &&\n";
     o.indent(Indentation+4);
   }



From nadav.rotem at intel.com  Thu Sep  8 03:31:31 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Thu, 08 Sep 2011 08:31:31 -0000
Subject: [llvm-commits] [llvm] r139287 - /llvm/trunk/test/CodeGen/X86/vsel.ll
Message-ID: <20110908083131.E414A2A6C12D@llvm.org>

Author: nadav
Date: Thu Sep  8 03:31:31 2011
New Revision: 139287

URL: http://llvm.org/viewvc/llvm-project?rev=139287&view=rev
Log:
add a testcase for the previous patch

Added:
    llvm/trunk/test/CodeGen/X86/vsel.ll

Added: llvm/trunk/test/CodeGen/X86/vsel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vsel.ll?rev=139287&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vsel.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vsel.ll Thu Sep  8 03:31:31 2011
@@ -0,0 +1,47 @@
+; RUN: llc < %s -march=x86 -promote-elements -mattr=+sse41 | FileCheck %s
+
+;CHECK: vsel_float
+;CHECK: blendvps
+;CHECK: ret
+define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
+  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
+  ret <4 x float> %vsel
+}
+
+
+;CHECK: vsel_i32
+;CHECK: blendvps
+;CHECK: ret
+define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
+  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2
+  ret <4 x i32> %vsel
+}
+
+
+;CHECK: vsel_double
+;CHECK: blendvpd
+;CHECK: ret
+define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
+  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> %v1, <4 x double> %v2
+  ret <4 x double> %vsel
+}
+
+
+;CHECK: vsel_i64
+;CHECK: blendvpd
+;CHECK: ret
+define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
+  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> %v1, <4 x i64> %v2
+  ret <4 x i64> %vsel
+}
+
+
+;CHECK: vsel_i8
+;CHECK: pblendvb
+;CHECK: ret
+define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
+  %vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
+  ret <16 x i8> %vsel
+}
+
+



From eli.friedman at gmail.com  Thu Sep  8 03:35:17 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 8 Sep 2011 01:35:17 -0700
Subject: [llvm-commits] [llvm] r139285 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/Generic/promote-integers.ll
In-Reply-To: <20110908081120.3B4E02A6C12D@llvm.org>
References: <20110908081120.3B4E02A6C12D@llvm.org>
Message-ID: <CAJdarcE4ZhqDBH6FpMJm4cbNHJ4RwGQdY8strX9MsbJ6e8ZSpQ@mail.gmail.com>

On Thu, Sep 8, 2011 at 1:11 AM, Nadav Rotem <nadav.rotem at intel.com> wrote:
> Author: nadav
> Date: Thu Sep ?8 03:11:19 2011
> New Revision: 139285
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139285&view=rev
> Log:
> Add X86-SSE4 codegen support for vector-select.
>
>
> Modified:
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.h
> ? ?llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> ? ?llvm/trunk/lib/Target/X86/X86InstrSSE.td
> ? ?llvm/trunk/test/CodeGen/Generic/promote-integers.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139285&r1=139284&r2=139285&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep ?8 03:11:19 2011
> @@ -917,6 +917,13 @@
> ? ? setOperationAction(ISD::SHL, ? ? ? ? ? ? ? ?MVT::v4i32, Custom);
> ? ? setOperationAction(ISD::SHL, ? ? ? ? ? ? ? ?MVT::v16i8, Custom);
>
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v2f64, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v2i64, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v16i8, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v8i16, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4i32, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4f32, Custom);
> +
> ? ? // i8 and i16 vectors are custom , because the source register and source
> ? ? // source memory operand types are not the same width. ?f32 vectors are
> ? ? // custom since the immediate controlling the insert encodes additional
> @@ -8684,6 +8691,32 @@
> ? return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
> ?}
>
> +SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
> + ?SDValue Cond ?= Op.getOperand(0);
> + ?SDValue Op1 = Op.getOperand(1);
> + ?SDValue Op2 = Op.getOperand(2);
> + ?DebugLoc DL = Op.getDebugLoc();
> +
> + ?SDValue Ops[] = {Cond, Op1, Op2};
> +
> + ?assert(Op1.getValueType().isVector() && "Op1 must be a vector");
> + ?assert(Op2.getValueType().isVector() && "Op2 must be a vector");
> + ?assert(Cond.getValueType().isVector() && "Cond must be a vector");
> + ?assert(Op1.getValueType() == Op2.getValueType() && "Type mismatch");
> +
> + ?switch (Op1.getValueType().getSimpleVT().SimpleTy) {
> + ? ?default: break;
> + ? ?case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ?}
> +
> + ?return SDValue();
> +}
> +
> +
> ?// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
> ?// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
> ?// from the AND / OR.
> @@ -10350,6 +10383,7 @@
> ? case ISD::FGETSIGN: ? ? ? ? ? return LowerFGETSIGN(Op, DAG);
> ? case ISD::SETCC: ? ? ? ? ? ? ?return LowerSETCC(Op, DAG);
> ? case ISD::SELECT: ? ? ? ? ? ? return LowerSELECT(Op, DAG);
> + ?case ISD::VSELECT: ? ? ? ? ? ?return LowerVSELECT(Op, DAG);
> ? case ISD::BRCOND: ? ? ? ? ? ? return LowerBRCOND(Op, DAG);
> ? case ISD::JumpTable: ? ? ? ? ?return LowerJumpTable(Op, DAG);
> ? case ISD::VASTART: ? ? ? ? ? ?return LowerVASTART(Op, DAG);
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=139285&r1=139284&r2=139285&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Sep ?8 03:11:19 2011
> @@ -175,8 +175,10 @@
> ? ? ? /// PSIGNB/W/D - Copy integer sign.
> ? ? ? PSIGNB, PSIGNW, PSIGND,
>
> - ? ? ?/// PBLENDVB - Variable blend
> + ? ? ?/// BLENDVXX family of opcodes
> ? ? ? PBLENDVB,
> + ? ? ?BLENDVPD,
> + ? ? ?BLENDVPS,
>
> ? ? ? /// FMAX, FMIN - Floating point max and min.
> ? ? ? ///
> @@ -809,6 +811,7 @@
> ? ? SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
> + ? ?SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=139285&r1=139284&r2=139285&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Thu Sep ?8 03:11:19 2011
> @@ -58,9 +58,15 @@
> ?def X86psignd ?: SDNode<"X86ISD::PSIGND",
> ? ? ? ? ? ? ? ? ?SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisSameAs<0,2>]>>;
> -def X86pblendv : SDNode<"X86ISD::PBLENDVB",
> +def X86pblendvb : SDNode<"X86ISD::PBLENDVB",
> ? ? ? ? ? ? ? ? ?SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
> +def X86blendvpd : SDNode<"X86ISD::BLENDVPD",
> + ? ? ? ? ? ? ? ? ?SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
> +def X86blendvps : SDNode<"X86ISD::BLENDVPS",
> + ? ? ? ? ? ? ? ? SDTypeProfile<1, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
> ?def X86pextrb ?: SDNode<"X86ISD::PEXTRB",
> ? ? ? ? ? ? ? ? ?SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
> ?def X86pextrw ?: SDNode<"X86ISD::PEXTRW",
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139285&r1=139284&r2=139285&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep ?8 03:11:19 2011
> @@ -5843,7 +5843,7 @@
> ?defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?memopv32i8, int_x86_avx_blendv_ps_256>;
>
> -def : Pat<(X86pblendv VR128:$src1, VR128:$src2, VR128:$src3),
> +def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, VR128:$src3),
> ? ? ? ? ? (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$src3)>,
> ? ? ? ? ? Requires<[HasAVX]>;
>
> @@ -5871,8 +5871,12 @@
> ?defm BLENDVPS ? ? : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
> ?defm PBLENDVB ? ? : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
>
> -def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
> +def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0),
> ? ? ? ? ? (PBLENDVBrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
> +def : Pat<(X86blendvpd ?XMM0, VR128:$src1, VR128:$src2),
> + ? ? ? ? ?(BLENDVPDrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
> +def : Pat<(X86blendvps ?XMM0, VR128:$src1, VR128:$src2),
> + ? ? ? ? ?(BLENDVPSrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
>
> ?let Predicates = [HasAVX] in
> ?def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
>
> Modified: llvm/trunk/test/CodeGen/Generic/promote-integers.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/promote-integers.ll?rev=139285&r1=139284&r2=139285&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Generic/promote-integers.ll (original)
> +++ llvm/trunk/test/CodeGen/Generic/promote-integers.ll Thu Sep ?8 03:11:19 2011
> @@ -3,8 +3,8 @@
>
> ?; This test is the poster-child for integer-element-promotion.
> ?; Until this feature is complete, we mark this test as expected to fail.
> -; XFAIL: *
> ?; CHECK: vector_code
> +; CHECK: blend
> ?; CHECK: ret
> ?define <4 x float> @vector_code(<4 x i64> %A, <4 x i64> %B, <4 x float> %R0, <4 x float> %R1 ) ?{
> ? ?%C = icmp eq <4 x i64> %A, %B

x86-specific tests should be in test/CodeGen/X86/

-Eli


From nadav.rotem at intel.com  Thu Sep  8 03:43:24 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Thu, 08 Sep 2011 08:43:24 -0000
Subject: [llvm-commits] [llvm] r139288 -
	/llvm/trunk/test/CodeGen/Generic/promote-integers.ll
Message-ID: <20110908084324.1A2C32A6C12C@llvm.org>

Author: nadav
Date: Thu Sep  8 03:43:23 2011
New Revision: 139288

URL: http://llvm.org/viewvc/llvm-project?rev=139288&view=rev
Log:
This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll

Removed:
    llvm/trunk/test/CodeGen/Generic/promote-integers.ll

Removed: llvm/trunk/test/CodeGen/Generic/promote-integers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/promote-integers.ll?rev=139287&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Generic/promote-integers.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/promote-integers.ll (removed)
@@ -1,15 +0,0 @@
-; Test that vectors are scalarized/lowered correctly.
-; RUN: llc -march=x86 -promote-elements < %s | FileCheck %s
-
-; This test is the poster-child for integer-element-promotion.
-; Until this feature is complete, we mark this test as expected to fail.
-; CHECK: vector_code
-; CHECK: blend
-; CHECK: ret
-define <4 x float> @vector_code(<4 x i64> %A, <4 x i64> %B, <4 x float> %R0, <4 x float> %R1 )  {
-   %C = icmp eq <4 x i64> %A, %B
-   %K = xor <4 x i1> <i1 1, i1 1, i1 1, i1 1>, %C
-   %D = select <4 x i1> %K, <4 x float> %R1, <4 x float> %R0
-   ret <4 x float> %D
-}
-



From baldrick at free.fr  Thu Sep  8 04:17:14 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 08 Sep 2011 11:17:14 +0200
Subject: [llvm-commits] [llvm] r139285 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/Generic/promote-integers.ll
In-Reply-To: <20110908081120.3B4E02A6C12D@llvm.org>
References: <20110908081120.3B4E02A6C12D@llvm.org>
Message-ID: <4E68881A.3070509@free.fr>

Hi Nadav,

> Add X86-SSE4 codegen support for vector-select.

yay!

> +  switch (Op1.getValueType().getSimpleVT().SimpleTy) {
> +    default: break;
> +    case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> +    case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> +    case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> +    case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> +    case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> +  }

If you switched on the type of the condition you would reduce the number of
cases, since you wouldn't need v2f64 or v4f32.

Ciao, Duncan.

From rengolin at systemcall.org  Thu Sep  8 04:52:22 2011
From: rengolin at systemcall.org (Renato Golin)
Date: Thu, 08 Sep 2011 09:52:22 -0000
Subject: [llvm-commits] [www] r139289 -
	/www/trunk/devmtg/2011-09-16/index.html
Message-ID: <20110908095222.0BAEB2A6C12C@llvm.org>

Author: rengolin
Date: Thu Sep  8 04:52:21 2011
New Revision: 139289

URL: http://llvm.org/viewvc/llvm-project?rev=139289&view=rev
Log:
schedule including side sessions

Modified:
    www/trunk/devmtg/2011-09-16/index.html

Modified: www/trunk/devmtg/2011-09-16/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-09-16/index.html?rev=139289&r1=139288&r2=139289&view=diff
==============================================================================
--- www/trunk/devmtg/2011-09-16/index.html (original)
+++ www/trunk/devmtg/2011-09-16/index.html Thu Sep  8 04:52:21 2011
@@ -93,8 +93,8 @@
 <td>
   <b>Tea Break</b>
 </td>
-<td>Side session</td>
-<td>Side session</td>
+<td>Side session: Target Inpendent LLVM Bitcode, Jin-Gu Kang</td>
+<td>Side session: Polly, Tobias Grosser</td>
 </tr>
 
 <tr>
@@ -128,19 +128,17 @@
 <td>
   <b>Lightning Talks</b>
 </td>
-<td>Side session</td>
-<td>Side session</td>
+<td>Side session: ARM Back-end: Anton Korobeynikov</td>
+<td>Side session: Escaping from LLVM-GCC: Duncan Sands</td>
 </tr>
 
 <tr class="alt">
 <td align="center">
   17:30
 </td>
-<td>
-  <b>Tea Break</b>
-</td>
-<td>Side session</td>
-<td>Side session</td>
+<td>&nbsp;</td>
+<td>Side session: OpenCL, Anton Lokhmotov</td>
+<td>Side session: Euro-LLVM 2012 / LLVM Community discussions</td>
 </tr>
 
 <tr class="alt">



From rengolin at systemcall.org  Thu Sep  8 05:01:46 2011
From: rengolin at systemcall.org (Renato Golin)
Date: Thu, 08 Sep 2011 10:01:46 -0000
Subject: [llvm-commits] [www] r139290 -
	/www/trunk/devmtg/2011-09-16/index.html
Message-ID: <20110908100146.D4AF32A6C12C@llvm.org>

Author: rengolin
Date: Thu Sep  8 05:01:46 2011
New Revision: 139290

URL: http://llvm.org/viewvc/llvm-project?rev=139290&view=rev
Log:
the agenda is not tentative anymore

Modified:
    www/trunk/devmtg/2011-09-16/index.html

Modified: www/trunk/devmtg/2011-09-16/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-09-16/index.html?rev=139290&r1=139289&r2=139290&view=diff
==============================================================================
--- www/trunk/devmtg/2011-09-16/index.html (original)
+++ www/trunk/devmtg/2011-09-16/index.html Thu Sep  8 05:01:46 2011
@@ -47,7 +47,7 @@
 <p>If you need funding to attend the meeting, please tell us in your
 registration email (to Euro-LLVM at arm.com).</p>
 
-<div class="www_sectiontitle" id="agenda">Tentative Agenda</div>
+<div class="www_sectiontitle" id="agenda">Agenda</div>
 <p></p>
 
 <table id="devmtg">



From geek4civic at gmail.com  Thu Sep  8 05:10:19 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Thu, 8 Sep 2011 19:10:19 +0900
Subject: [llvm-commits] [llvm] r139279 -
	/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
In-Reply-To: <CAENS6EuSXkNzU5VN86M5GjEtijUtWewbstLt2-mT31bkZZSi4g@mail.gmail.com>
References: <20110908052549.AFEE12A6C12C@llvm.org>
	<CAENS6EuSXkNzU5VN86M5GjEtijUtWewbstLt2-mT31bkZZSi4g@mail.gmail.com>
Message-ID: <CADiQthPdCaY4b74cZHQgW3FMutkDWtEdFhFZ4+1cvhJMWpzsOw@mail.gmail.com>

Andy, cheers to the Internet! ;)
Arigato!

James,
I wish clang could detect such a temporary_std_string.c_str().
FYI, I found the issue here; http://bb.pgr.jp/

David,
>> str.slice(1,str.size())
> This could be written more simply as str.substr(1), if I'm not mistaken.

Sure. I reminded StringRef::substr(1) would be shorter since when I
had seen the snippet on the Internet.
(yeah, it's trivial though it is not in LLVM libs)

...Takumi

From undingen at gmail.com  Thu Sep  8 07:53:13 2011
From: undingen at gmail.com (Marius Wachtler)
Date: Thu, 8 Sep 2011 14:53:13 +0200
Subject: [llvm-commits] [llvm] r139263 -
	/llvm/trunk/lib/Target/README.txt
In-Reply-To: <4E686F34.3010200@free.fr>
References: <20110907224926.A9B8C2A6C12C@llvm.org> <4E686F34.3010200@free.fr>
Message-ID: <CANycJ-BANEfDD3Ci7MEN=9S_CxicqRVjyrh+WTb_QjN0UQ-QUQ@mail.gmail.com>

Hello

I am trying to implement this as an exercise for me.
Attached you can find a patch which should implement the first
transformation as an InstructionSimplify optimization.

Can you please give me feedback if I'm on the right track to do this
in InstSimplify and using the matcher?
My pattern looks complicated and very specific is there a easy/better
way to do it?

Thanks
Marius Wachtler
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From atrick at apple.com  Thu Sep  8 10:55:22 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 08 Sep 2011 08:55:22 -0700
Subject: [llvm-commits] [llvm] r139279 -
 /llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
In-Reply-To: <CADiQthPdCaY4b74cZHQgW3FMutkDWtEdFhFZ4+1cvhJMWpzsOw@mail.gmail.com>
References: <20110908052549.AFEE12A6C12C@llvm.org>
	<CAENS6EuSXkNzU5VN86M5GjEtijUtWewbstLt2-mT31bkZZSi4g@mail.gmail.com>
	<CADiQthPdCaY4b74cZHQgW3FMutkDWtEdFhFZ4+1cvhJMWpzsOw@mail.gmail.com>
Message-ID: <7412C614-15A9-4E50-8EC8-FCFEAE52464A@apple.com>

Takumi,

Thanks for the IRC hint. Can you confirm that this fixes it for you!

-Andy

On Sep 8, 2011, at 3:10 AM, NAKAMURA Takumi wrote:

> Andy, cheers to the Internet! ;)
> Arigato!
> 
> James,
> I wish clang could detect such a temporary_std_string.c_str().
> FYI, I found the issue here; http://bb.pgr.jp/
> 
> David,
>>> str.slice(1,str.size())
>> This could be written more simply as str.substr(1), if I'm not mistaken.
> 
> Sure. I reminded StringRef::substr(1) would be shorter since when I
> had seen the snippet on the Internet.
> (yeah, it's trivial though it is not in LLVM libs)
> 
> ...Takumi


From bruno.cardoso at gmail.com  Thu Sep  8 11:49:35 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 8 Sep 2011 09:49:35 -0700
Subject: [llvm-commits] [llvm] r139285 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/Generic/promote-integers.ll
In-Reply-To: <20110908081120.3B4E02A6C12D@llvm.org>
References: <20110908081120.3B4E02A6C12D@llvm.org>
Message-ID: <CACk9FxZWx=tNjMEc7pVdN3_QjZJ+03kodUu84+CPh0dpLLqBAA@mail.gmail.com>

Cool!

On Thu, Sep 8, 2011 at 1:11 AM, Nadav Rotem <nadav.rotem at intel.com> wrote:
> Author: nadav
> Date: Thu Sep ?8 03:11:19 2011
> New Revision: 139285
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139285&view=rev
> Log:
> Add X86-SSE4 codegen support for vector-select.
>
>
> Modified:
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.h
> ? ?llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> ? ?llvm/trunk/lib/Target/X86/X86InstrSSE.td
> ? ?llvm/trunk/test/CodeGen/Generic/promote-integers.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139285&r1=139284&r2=139285&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep ?8 03:11:19 2011
> @@ -917,6 +917,13 @@
> ? ? setOperationAction(ISD::SHL, ? ? ? ? ? ? ? ?MVT::v4i32, Custom);
> ? ? setOperationAction(ISD::SHL, ? ? ? ? ? ? ? ?MVT::v16i8, Custom);
>
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v2f64, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v2i64, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v16i8, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v8i16, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4i32, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4f32, Custom);
> +
> ? ? // i8 and i16 vectors are custom , because the source register and source
> ? ? // source memory operand types are not the same width. ?f32 vectors are
> ? ? // custom since the immediate controlling the insert encodes additional
> @@ -8684,6 +8691,32 @@
> ? return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
> ?}
>
> +SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
> + ?SDValue Cond ?= Op.getOperand(0);
> + ?SDValue Op1 = Op.getOperand(1);
> + ?SDValue Op2 = Op.getOperand(2);
> + ?DebugLoc DL = Op.getDebugLoc();
> +
> + ?SDValue Ops[] = {Cond, Op1, Op2};
> +
> + ?assert(Op1.getValueType().isVector() && "Op1 must be a vector");
> + ?assert(Op2.getValueType().isVector() && "Op2 must be a vector");
> + ?assert(Cond.getValueType().isVector() && "Cond must be a vector");
> + ?assert(Op1.getValueType() == Op2.getValueType() && "Type mismatch");
> +
> + ?switch (Op1.getValueType().getSimpleVT().SimpleTy) {
> + ? ?default: break;
> + ? ?case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ?}

This also breaks 80-columns restriction

> + ?return SDValue();
> +}
> +
> +
> ?// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
> ?// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
> ?// from the AND / OR.
> @@ -10350,6 +10383,7 @@
> ? case ISD::FGETSIGN: ? ? ? ? ? return LowerFGETSIGN(Op, DAG);
> ? case ISD::SETCC: ? ? ? ? ? ? ?return LowerSETCC(Op, DAG);
> ? case ISD::SELECT: ? ? ? ? ? ? return LowerSELECT(Op, DAG);
> + ?case ISD::VSELECT: ? ? ? ? ? ?return LowerVSELECT(Op, DAG);
> ? case ISD::BRCOND: ? ? ? ? ? ? return LowerBRCOND(Op, DAG);
> ? case ISD::JumpTable: ? ? ? ? ?return LowerJumpTable(Op, DAG);
> ? case ISD::VASTART: ? ? ? ? ? ?return LowerVASTART(Op, DAG);
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=139285&r1=139284&r2=139285&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Sep ?8 03:11:19 2011
> @@ -175,8 +175,10 @@
> ? ? ? /// PSIGNB/W/D - Copy integer sign.
> ? ? ? PSIGNB, PSIGNW, PSIGND,
>
> - ? ? ?/// PBLENDVB - Variable blend
> + ? ? ?/// BLENDVXX family of opcodes
> ? ? ? PBLENDVB,
> + ? ? ?BLENDVPD,
> + ? ? ?BLENDVPS,
>
> ? ? ? /// FMAX, FMIN - Floating point max and min.
> ? ? ? ///
> @@ -809,6 +811,7 @@
> ? ? SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
> + ? ?SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=139285&r1=139284&r2=139285&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Thu Sep ?8 03:11:19 2011
> @@ -58,9 +58,15 @@
> ?def X86psignd ?: SDNode<"X86ISD::PSIGND",
> ? ? ? ? ? ? ? ? ?SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisSameAs<0,2>]>>;
> -def X86pblendv : SDNode<"X86ISD::PBLENDVB",
> +def X86pblendvb : SDNode<"X86ISD::PBLENDVB",
> ? ? ? ? ? ? ? ? ?SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
> +def X86blendvpd : SDNode<"X86ISD::BLENDVPD",
> + ? ? ? ? ? ? ? ? ?SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
> +def X86blendvps : SDNode<"X86ISD::BLENDVPS",
> + ? ? ? ? ? ? ? ? SDTypeProfile<1, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
> ?def X86pextrb ?: SDNode<"X86ISD::PEXTRB",
> ? ? ? ? ? ? ? ? ?SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
> ?def X86pextrw ?: SDNode<"X86ISD::PEXTRW",
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139285&r1=139284&r2=139285&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep ?8 03:11:19 2011
> @@ -5843,7 +5843,7 @@
> ?defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?memopv32i8, int_x86_avx_blendv_ps_256>;
>
> -def : Pat<(X86pblendv VR128:$src1, VR128:$src2, VR128:$src3),
> +def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, VR128:$src3),
> ? ? ? ? ? (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$src3)>,
> ? ? ? ? ? Requires<[HasAVX]>;
>
> @@ -5871,8 +5871,12 @@
> ?defm BLENDVPS ? ? : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
> ?defm PBLENDVB ? ? : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
>
> -def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
> +def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0),
> ? ? ? ? ? (PBLENDVBrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
> +def : Pat<(X86blendvpd ?XMM0, VR128:$src1, VR128:$src2),
> + ? ? ? ? ?(BLENDVPDrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
> +def : Pat<(X86blendvps ?XMM0, VR128:$src1, VR128:$src2),
> + ? ? ? ? ?(BLENDVPSrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;

I will do it this time, but next time can you add the AVX versions
when adding SSE ones? Usually all you need are the same patterns but
with a different predicate!

> ?let Predicates = [HasAVX] in
> ?def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
>
> Modified: llvm/trunk/test/CodeGen/Generic/promote-integers.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/promote-integers.ll?rev=139285&r1=139284&r2=139285&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Generic/promote-integers.ll (original)
> +++ llvm/trunk/test/CodeGen/Generic/promote-integers.ll Thu Sep ?8 03:11:19 2011
> @@ -3,8 +3,8 @@
>
> ?; This test is the poster-child for integer-element-promotion.
> ?; Until this feature is complete, we mark this test as expected to fail.
> -; XFAIL: *
> ?; CHECK: vector_code
> +; CHECK: blend
> ?; CHECK: ret
> ?define <4 x float> @vector_code(<4 x i64> %A, <4 x i64> %B, <4 x float> %R0, <4 x float> %R1 ) ?{
> ? ?%C = icmp eq <4 x i64> %A, %B
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From atrick at apple.com  Thu Sep  8 11:49:25 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 08 Sep 2011 09:49:25 -0700
Subject: [llvm-commits] [llvm] r139250 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ test/MC/Disassembler/ARM/ utils/TableGen/
In-Reply-To: <000c01cc6df8$921309e0$b6391da0$%molloy@arm.com>
References: <20110907194229.097E02A6C12C@llvm.org>
	<CADiQthOBjzzbZ=7HTvp5eLu2+4egv1G+VRB2qN_+CUCMTz2R=w@mail.gmail.com>
	<49E8D98A-013B-4395-A94E-FA0B7927B9E9@apple.com>
	<000c01cc6df8$921309e0$b6391da0$%molloy@arm.com>
Message-ID: <B66098B1-B191-4355-95FB-03A41F3241F4@apple.com>

Hi James,

ARMGenDisassemblerTables.inc is trashed by tblgen leading to compilation errors starting with:

ARMGenDisassemblerTables.inc(51) : error C2589: ')' : illegal token on right side of '::'
...

Takumi kindly attached an example ARMGenDisassemblerTables.inc in an earlier email (see vs.txt). I don't even have easy access to that file, so many thanks to Takumi.

-Andy

On Sep 8, 2011, at 12:26 AM, James Molloy wrote:

> Hi,
> 
> I don't see this, at least on linux with gcc 4.1.2.
> 
> Our windows buildbot picked a warning up in FixedLenDecoderEmitter.cpp:857 - is
> that what you're referring to? I'll fix that now.
> 
> Otherwise, if you could provide an example of the warning/error, that would be
> much appreciated.
> 
> Cheers,
> 
> James
> 
>> -----Original Message-----
>> From: Andrew Trick [mailto:atrick at apple.com]
>> Sent: 08 September 2011 02:19
>> To: NAKAMURA Takumi; James Molloy
>> Cc: llvm-commits
>> Subject: Re: [llvm-commits] [llvm] r139250 - in /llvm/trunk:
>> lib/Target/ARM/Disassembler/ test/MC/Disassembler/ARM/ utils/TableGen/
>> 
>> Our windows testers are hitting it too. Let me know if you can confirm this
>> is the cause.
>> -Andy
>> 
>> On Sep 7, 2011, at 5:07 PM, NAKAMURA Takumi wrote:
>> 
>>> 2011/9/8 James Molloy <james.molloy at arm.com>:
>>>> Author: jamesm
>>>> Date: Wed Sep  7 14:42:28 2011
>>>> New Revision: 139250
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=139250&view=rev
>>>> Log:
>>>> Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This
>> adds predicate checking to the Disassembler.
>>>> 
>>>> Modified:
>>>>   llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
>>>>   llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/neon.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
>>>>   llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
>>>>   llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
>>>>   llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
>>>>   llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h
>>> 
>>> James, I saw weird emissions by tblgen, on cygwin gcc-4.3 and msvc10.
>>> I will investigate a few hours after, too.
>>> 
>>> ...Takumi
>>> <cyg.txt.gz><vs.txt.gz>_______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
>> 
> 
> 
> 


From grosbach at apple.com  Thu Sep  8 11:49:36 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Sep 2011 16:49:36 -0000
Subject: [llvm-commits] [llvm] r139292 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110908164936.CE71F2A6C12C@llvm.org>

Author: grosbach
Date: Thu Sep  8 11:49:36 2011
New Revision: 139292

URL: http://llvm.org/viewvc/llvm-project?rev=139292&view=rev
Log:
Add tests for Thumb2 LDRB indexed addressing w/ writeback.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139292&r1=139291&r2=139292&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Thu Sep  8 11:49:36 2011
@@ -594,6 +594,12 @@
         ldrb r8, [r8, r2, lsl #2]
         ldrb r7, [sp, r2, lsl #1]
         ldrb r7, [sp, r2, lsl #0]
+        ldrb r5, [r8, #255]!
+        ldrb r2, [r5, #4]!
+        ldrb r1, [r4, #-4]!
+        ldrb lr, [r3], #255
+        ldrb r9, [r2], #4
+        ldrb r3, [sp], #-4
 
 @ CHECK: ldrb.w	r1, [r8, r1]            @ encoding: [0x18,0xf8,0x01,0x10]
 @ CHECK: ldrb.w	r4, [r5, r2]            @ encoding: [0x15,0xf8,0x02,0x40]
@@ -601,6 +607,12 @@
 @ CHECK: ldrb.w	r8, [r8, r2, lsl #2]    @ encoding: [0x18,0xf8,0x22,0x80]
 @ CHECK: ldrb.w	r7, [sp, r2, lsl #1]    @ encoding: [0x1d,0xf8,0x12,0x70]
 @ CHECK: ldrb.w	r7, [sp, r2]            @ encoding: [0x1d,0xf8,0x02,0x70]
+@ CHECK: ldrb	r5, [r8, #255]!         @ encoding: [0x18,0xf8,0xff,0x5f]
+@ CHECK: ldrb	r2, [r5, #4]!           @ encoding: [0x15,0xf8,0x04,0x2f]
+@ CHECK: ldrb	r1, [r4, #-4]!          @ encoding: [0x14,0xf8,0x04,0x1d]
+@ CHECK: ldrb	lr, [r3], #255          @ encoding: [0x13,0xf8,0xff,0xeb]
+@ CHECK: ldrb	r9, [r2], #4            @ encoding: [0x12,0xf8,0x04,0x9b]
+@ CHECK: ldrb	r3, [sp], #-4           @ encoding: [0x1d,0xf8,0x04,0x39]
 
 
 @------------------------------------------------------------------------------



From benny.kra at googlemail.com  Thu Sep  8 12:37:07 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 8 Sep 2011 10:37:07 -0700
Subject: [llvm-commits] [llvm] r139263 -
	/llvm/trunk/lib/Target/README.txt
In-Reply-To: <CANycJ-BANEfDD3Ci7MEN=9S_CxicqRVjyrh+WTb_QjN0UQ-QUQ@mail.gmail.com>
References: <20110907224926.A9B8C2A6C12C@llvm.org> <4E686F34.3010200@free.fr>
	<CANycJ-BANEfDD3Ci7MEN=9S_CxicqRVjyrh+WTb_QjN0UQ-QUQ@mail.gmail.com>
Message-ID: <CAL3drCrbFXnXuccckjL=onB8qZa_+SDsarKDix0Kx2qsiTx7BA@mail.gmail.com>

On Thu, Sep 8, 2011 at 05:53, Marius Wachtler <undingen at gmail.com> wrote:
> Hello
>
> I am trying to implement this as an exercise for me.
> Attached you can find a patch which should implement the first
> transformation as an InstructionSimplify optimization.
>
> Can you please give me feedback if I'm on the right track to do this
> in InstSimplify and using the matcher?
> My pattern looks complicated and very specific is there a easy/better
> way to do it?

These patterns are fine, but indeed very specific. I think there is a
more general way to do this. What I had in mind (maybe Duncan's idea
is different and he knows InstSimplify a lot better than me), is to
substitute the value from the equality comparison into the expression
on the other side and see if it evaluates to true.

(A == 0) | ((A & ?) == 0) -> (A == 0) | ((0 & ?) == 0) -> (A == 0) | true
Now we know that the first expression is redundant and we can drop it.
We can use the same trick for & with != and false.

We have similar code in InstCombineSelect.cpp (look for
SimplifyWithOpReplaced). To get this kind of cases it has to be
enhanced to do the substitution on multiple levels though, I don't
know how hard that is with the current InstSimplify machinery.

- Ben

From supertri at google.com  Thu Sep  8 12:40:49 2011
From: supertri at google.com (Caitlin Sadowski)
Date: Thu, 08 Sep 2011 17:40:49 -0000
Subject: [llvm-commits] [llvm] r139300 - in /llvm/trunk/utils/TableGen:
 ClangAttrEmitter.cpp ClangAttrEmitter.h TableGen.cpp
Message-ID: <20110908174049.DFC832A6C12C@llvm.org>

Author: supertri
Date: Thu Sep  8 12:40:49 2011
New Revision: 139300

URL: http://llvm.org/viewvc/llvm-project?rev=139300&view=rev
Log:
Added LateParsed property to TableGen attributes.

This patch was written by DeLesley Hutchins.

Modified:
    llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp
    llvm/trunk/utils/TableGen/ClangAttrEmitter.h
    llvm/trunk/utils/TableGen/TableGen.cpp

Modified: llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp?rev=139300&r1=139299&r2=139300&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp Thu Sep  8 12:40:49 2011
@@ -758,3 +758,26 @@
   }
 
 }
+
+void ClangAttrLateParsedListEmitter::run(raw_ostream &OS) {
+  OS << "// This file is generated by TableGen. Do not edit.\n\n";
+
+  std::vector<Record*> Attrs = Records.getAllDerivedDefinitions("Attr");
+
+  for (std::vector<Record*>::iterator I = Attrs.begin(), E = Attrs.end();
+       I != E; ++I) {
+    Record &Attr = **I;
+
+    bool LateParsed = Attr.getValueAsBit("LateParsed");
+
+    if (LateParsed) {
+      std::vector<StringRef> Spellings =
+        getValueAsListOfStrings(Attr, "Spellings");
+
+      for (std::vector<StringRef>::const_iterator I = Spellings.begin(),
+           E = Spellings.end(); I != E; ++I) {
+        OS << ".Case(\"" << (*I) << "\", " << LateParsed << ")\n";
+      }
+    }
+  }
+}

Modified: llvm/trunk/utils/TableGen/ClangAttrEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ClangAttrEmitter.h?rev=139300&r1=139299&r2=139300&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ClangAttrEmitter.h (original)
+++ llvm/trunk/utils/TableGen/ClangAttrEmitter.h Thu Sep  8 12:40:49 2011
@@ -96,6 +96,19 @@
   void run(raw_ostream &OS);
 };
 
+/// ClangAttrLateParsedListEmitter emits the LateParsed property for attributes
+/// for clang.
+class ClangAttrLateParsedListEmitter : public TableGenBackend {
+  RecordKeeper &Records;
+
+ public:
+  explicit ClangAttrLateParsedListEmitter(RecordKeeper &R)
+    : Records(R)
+    {}
+
+  void run(raw_ostream &OS);
+};
+
 }
 
 #endif

Modified: llvm/trunk/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=139300&r1=139299&r2=139300&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TableGen.cpp (original)
+++ llvm/trunk/utils/TableGen/TableGen.cpp Thu Sep  8 12:40:49 2011
@@ -68,6 +68,7 @@
   GenClangAttrPCHRead,
   GenClangAttrPCHWrite,
   GenClangAttrSpellingList,
+  GenClangAttrLateParsedList,
   GenClangDiagsDefs,
   GenClangDiagGroups,
   GenClangDiagsIndexName,
@@ -139,6 +140,9 @@
                     clEnumValN(GenClangAttrSpellingList,
                                "gen-clang-attr-spelling-list",
                                "Generate a clang attribute spelling list"),
+                    clEnumValN(GenClangAttrLateParsedList,
+                               "gen-clang-attr-late-parsed-list",
+                               "Generate a clang attribute LateParsed list"),
                     clEnumValN(GenClangDiagsDefs, "gen-clang-diags-defs",
                                "Generate Clang diagnostics definitions"),
                     clEnumValN(GenClangDiagGroups, "gen-clang-diag-groups",
@@ -296,6 +300,9 @@
     case GenClangAttrSpellingList:
       ClangAttrSpellingListEmitter(Records).run(Out.os());
       break;
+    case GenClangAttrLateParsedList:
+      ClangAttrLateParsedListEmitter(Records).run(Out.os());
+      break;
     case GenClangDiagsDefs:
       ClangDiagsDefsEmitter(Records, ClangComponent).run(Out.os());
       break;



From pdox at google.com  Thu Sep  8 12:52:06 2011
From: pdox at google.com (David Meyer)
Date: Thu, 8 Sep 2011 10:52:06 -0700
Subject: [llvm-commits] [PATCH] Clean up RegOp2MemOp tables in
	X86InstrInfo.cpp
In-Reply-To: <BAB05FBC-F778-46B1-8724-45C7B088EF4F@2pi.dk>
References: <CAAU48JKT3LE1gCzvWtv5Me4AsQLTbGa+boxFyZsjuKOP+8BanQ@mail.gmail.com>
	<6CF9FE3C-ABC0-4BB8-89A8-A27A45803A7A@2pi.dk>
	<CAAU48JJ-55X_sfnhvB1uudKbTPdhvue9P4jVL5B2meojxL9Y_g@mail.gmail.com>
	<CAAU48J+3G3Kps_N87nLq-oZghp9fJuoZ9aWvN+8bW7+0sRzfpQ@mail.gmail.com>
	<BAB05FBC-F778-46B1-8724-45C7B088EF4F@2pi.dk>
Message-ID: <CAAU48J+co5fzoD7ftCn0bKs7eDDu4CxXBK3CUw6Q-1KUXOXAQg@mail.gmail.com>

Anybody else?

- pdox

On Wed, Sep 7, 2011 at 4:41 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>> Was the last patch OK?
>
> Yes. Sorry, I haven't had time to commit it.
>
> /jakob
>
>

From bruno.cardoso at gmail.com  Thu Sep  8 13:05:02 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 08 Sep 2011 18:05:02 -0000
Subject: [llvm-commits] [llvm] r139304 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-load-store.ll
Message-ID: <20110908180503.16B782A6C12C@llvm.org>

Author: bruno
Date: Thu Sep  8 13:05:02 2011
New Revision: 139304

URL: http://llvm.org/viewvc/llvm-project?rev=139304&view=rev
Log:
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/avx-load-store.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139304&r1=139303&r2=139304&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep  8 13:05:02 2011
@@ -536,15 +536,15 @@
   // Move scalar to XMM zero-extended, zeroing a VR128 then do a
   // MOVS{S,D} to the lower bits.
   def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
-            (VMOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
+            (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)>;
   def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
-            (VMOVSSrr (v4f32 (V_SET0PS)),
+            (VMOVSSrr (v4f32 (AVX_SET0PS)),
                       (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
   def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
-            (VMOVSSrr (v4i32 (V_SET0PI)),
+            (VMOVSSrr (v4i32 (AVX_SET0PI)),
                       (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
   def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
-            (VMOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
+            (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)>;
   }
 
   let AddedComplexity = 20 in {
@@ -579,6 +579,16 @@
                    (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
             (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
   }
+  def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
+                   (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
+            (SUBREG_TO_REG (i32 0),
+                           (v4f32 (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)),
+                           sub_xmm)>;
+  def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
+                   (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
+            (SUBREG_TO_REG (i64 0),
+                           (v2f64 (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)),
+                           sub_xmm)>;
 
   // Extract and store.
   def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),

Modified: llvm/trunk/test/CodeGen/X86/avx-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-load-store.ll?rev=139304&r1=139303&r2=139304&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-load-store.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-load-store.ll Thu Sep  8 13:05:02 2011
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+; RUN: llc -O0 < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s -check-prefix=CHECK_O0
 
 ; CHECK: vmovaps
 ; CHECK: vmovaps
@@ -78,3 +79,27 @@
   ret void
 }
 
+declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x float>, <8 x float>) nounwind
+
+; CHECK_O0: _f_f
+; CHECK-O0: vmovss LCPI
+; CHECK-O0: vxorps  %xmm
+; CHECK-O0: vmovss %xmm
+define void @f_f() nounwind {
+allocas:
+  br i1 undef, label %cif_mask_all, label %cif_mask_mixed
+
+cif_mask_all:                                     ; preds = %allocas
+  unreachable
+
+cif_mask_mixed:                                   ; preds = %allocas
+  br i1 undef, label %cif_mixed_test_all, label %cif_mixed_test_any_check
+
+cif_mixed_test_all:                               ; preds = %cif_mask_mixed
+  call void @llvm.x86.avx.maskstore.ps.256(i8* undef, <8 x float> <float 0xFFFFFFFFE0000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, <8 x float> undef) nounwind
+  unreachable
+
+cif_mixed_test_any_check:                         ; preds = %cif_mask_mixed
+  unreachable
+}
+



From bruno.cardoso at gmail.com  Thu Sep  8 13:05:08 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 08 Sep 2011 18:05:08 -0000
Subject: [llvm-commits] [llvm] r139305 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFragmentsSIMD.td
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-blend.ll
 test/CodeGen/X86/sse41-blend.ll test/CodeGen/X86/vsel.ll
Message-ID: <20110908180508.D70972A6C12D@llvm.org>

Author: bruno
Date: Thu Sep  8 13:05:08 2011
New Revision: 139305

URL: http://llvm.org/viewvc/llvm-project?rev=139305&view=rev
Log:
Add AVX versions of blend vector operations and fix some issues noticed
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

Added:
    llvm/trunk/test/CodeGen/X86/avx-blend.ll
      - copied, changed from r139304, llvm/trunk/test/CodeGen/X86/vsel.ll
    llvm/trunk/test/CodeGen/X86/sse41-blend.ll
      - copied, changed from r139304, llvm/trunk/test/CodeGen/X86/vsel.ll
Removed:
    llvm/trunk/test/CodeGen/X86/vsel.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139305&r1=139304&r2=139305&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep  8 13:05:08 2011
@@ -8697,7 +8697,7 @@
   SDValue Op2 = Op.getOperand(2);
   DebugLoc DL = Op.getDebugLoc();
 
-  SDValue Ops[] = {Cond, Op1, Op2};
+  SDValue Ops[] = {Op1, Op2, Cond};
 
   assert(Op1.getValueType().isVector() && "Op1 must be a vector");
   assert(Op2.getValueType().isVector() && "Op2 must be a vector");

Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=139305&r1=139304&r2=139305&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Thu Sep  8 13:05:08 2011
@@ -61,10 +61,10 @@
 def X86pblendvb : SDNode<"X86ISD::PBLENDVB",
                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
-def X86blendvpd : SDNode<"X86ISD::BLENDVPD", 
+def X86blendvpd : SDNode<"X86ISD::BLENDVPD",
                   SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
                                        SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
-def X86blendvps : SDNode<"X86ISD::BLENDVPS", 
+def X86blendvps : SDNode<"X86ISD::BLENDVPS",
                  SDTypeProfile<1, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
 def X86pextrb  : SDNode<"X86ISD::PEXTRB",

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139305&r1=139304&r2=139305&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep  8 13:05:08 2011
@@ -5853,9 +5853,14 @@
 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
                                          memopv32i8, int_x86_avx_blendv_ps_256>;
 
-def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, VR128:$src3),
-          (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$src3)>,
-          Requires<[HasAVX]>;
+let Predicates = [HasAVX] in {
+  def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, VR128:$mask),
+            (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+  def : Pat<(X86blendvpd VR128:$src1, VR128:$src2, VR128:$mask),
+            (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+  def : Pat<(X86blendvps VR128:$src1, VR128:$src2, VR128:$mask),
+            (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+}
 
 /// SS41I_ternary_int - SSE 4.1 ternary operator
 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
@@ -5877,16 +5882,18 @@
   }
 }
 
-defm BLENDVPD     : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
-defm BLENDVPS     : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
-defm PBLENDVB     : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
-
-def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0),
-          (PBLENDVBrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
-def : Pat<(X86blendvpd  XMM0, VR128:$src1, VR128:$src2),
-          (BLENDVPDrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
-def : Pat<(X86blendvps  XMM0, VR128:$src1, VR128:$src2),
-          (BLENDVPSrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
+defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
+defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
+defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
+
+let Predicates = [HasSSE41] in {
+  def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0),
+            (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
+  def : Pat<(X86blendvpd VR128:$src1, VR128:$src2, XMM0),
+            (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
+  def : Pat<(X86blendvps VR128:$src1, VR128:$src2, XMM0),
+            (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
+}
 
 let Predicates = [HasAVX] in
 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),

Copied: llvm/trunk/test/CodeGen/X86/avx-blend.ll (from r139304, llvm/trunk/test/CodeGen/X86/vsel.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?p2=llvm/trunk/test/CodeGen/X86/avx-blend.ll&p1=llvm/trunk/test/CodeGen/X86/vsel.ll&r1=139304&r2=139305&rev=139305&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vsel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-blend.ll Thu Sep  8 13:05:08 2011
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=x86 -promote-elements -mattr=+sse41 | FileCheck %s
+; RUN: llc < %s -mattr=+avx -march=x86 | FileCheck %s
 
 ;CHECK: vsel_float
-;CHECK: blendvps
+;CHECK: vblendvps
 ;CHECK: ret
 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
   %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
@@ -10,7 +10,7 @@
 
 
 ;CHECK: vsel_i32
-;CHECK: blendvps
+;CHECK: vblendvps
 ;CHECK: ret
 define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
   %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2
@@ -19,25 +19,25 @@
 
 
 ;CHECK: vsel_double
-;CHECK: blendvpd
+;CHECK: vblendvpd
 ;CHECK: ret
-define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
-  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> %v1, <4 x double> %v2
-  ret <4 x double> %vsel
+define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
+  %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2
+  ret <2 x double> %vsel
 }
 
 
 ;CHECK: vsel_i64
-;CHECK: blendvpd
+;CHECK: vblendvpd
 ;CHECK: ret
-define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
-  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> %v1, <4 x i64> %v2
-  ret <4 x i64> %vsel
+define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
+  %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2
+  ret <2 x i64> %vsel
 }
 
 
 ;CHECK: vsel_i8
-;CHECK: pblendvb
+;CHECK: vpblendvb
 ;CHECK: ret
 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
   %vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2

Copied: llvm/trunk/test/CodeGen/X86/sse41-blend.ll (from r139304, llvm/trunk/test/CodeGen/X86/vsel.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?p2=llvm/trunk/test/CodeGen/X86/sse41-blend.ll&p1=llvm/trunk/test/CodeGen/X86/vsel.ll&r1=139304&r2=139305&rev=139305&view=diff
==============================================================================
    (empty)

Removed: llvm/trunk/test/CodeGen/X86/vsel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vsel.ll?rev=139304&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vsel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vsel.ll (removed)
@@ -1,47 +0,0 @@
-; RUN: llc < %s -march=x86 -promote-elements -mattr=+sse41 | FileCheck %s
-
-;CHECK: vsel_float
-;CHECK: blendvps
-;CHECK: ret
-define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
-  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
-  ret <4 x float> %vsel
-}
-
-
-;CHECK: vsel_i32
-;CHECK: blendvps
-;CHECK: ret
-define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
-  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2
-  ret <4 x i32> %vsel
-}
-
-
-;CHECK: vsel_double
-;CHECK: blendvpd
-;CHECK: ret
-define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
-  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> %v1, <4 x double> %v2
-  ret <4 x double> %vsel
-}
-
-
-;CHECK: vsel_i64
-;CHECK: blendvpd
-;CHECK: ret
-define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
-  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> %v1, <4 x i64> %v2
-  ret <4 x i64> %vsel
-}
-
-
-;CHECK: vsel_i8
-;CHECK: pblendvb
-;CHECK: ret
-define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
-  %vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
-  ret <16 x i8> %vsel
-}
-
-



From bruno.cardoso at gmail.com  Thu Sep  8 13:11:36 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 8 Sep 2011 11:11:36 -0700
Subject: [llvm-commits] [llvm] r139285 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/Generic/promote-integers.ll
In-Reply-To: <20110908081120.3B4E02A6C12D@llvm.org>
References: <20110908081120.3B4E02A6C12D@llvm.org>
Message-ID: <CACk9FxZqn=ek3_9Cu9ZqVE1-uF02bB89GMm49C46nbkaN3ZFQQ@mail.gmail.com>

A couple more comments:

> + ?switch (Op1.getValueType().getSimpleVT().SimpleTy) {
> + ? ?default: break;
> + ? ?case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ? ?case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + ?}

Although you did right in tablegen, PBLENDVB operands here are wrong.
I changed the order in r139305

> +def X86blendvpd : SDNode<"X86ISD::BLENDVPD",
> + ? ? ? ? ? ? ? ? ?SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
> +def X86blendvps : SDNode<"X86ISD::BLENDVPS",
> + ? ? ? ? ? ? ? ? SDTypeProfile<1, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;

Could you please change this to be only one node "X86blendv", and then
have tablegen match the instruction by the node type?

> +def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0),
> ? ? ? ? ? (PBLENDVBrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
> +def : Pat<(X86blendvpd ?XMM0, VR128:$src1, VR128:$src2),
> + ? ? ? ? ?(BLENDVPDrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
> +def : Pat<(X86blendvps ?XMM0, VR128:$src1, VR128:$src2),
> + ? ? ? ? ?(BLENDVPSrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;

Also changed it in r139305

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From baldrick at free.fr  Thu Sep  8 13:17:54 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 08 Sep 2011 20:17:54 +0200
Subject: [llvm-commits] [llvm] r139285 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/Generic/promote-integers.ll
In-Reply-To: <CACk9FxZWx=tNjMEc7pVdN3_QjZJ+03kodUu84+CPh0dpLLqBAA@mail.gmail.com>
References: <20110908081120.3B4E02A6C12D@llvm.org>
	<CACk9FxZWx=tNjMEc7pVdN3_QjZJ+03kodUu84+CPh0dpLLqBAA@mail.gmail.com>
Message-ID: <4E6906D2.1040100@free.fr>

Now I come to think about it, is there any need to custom lower: since vselect
maps directly onto processor instructions, can't it be done entirely using
tablegen patterns?  That said, I have no idea how tablegen works, so feel free
to ignore me if this makes no sense :)

Ciao, Duncan.

On 08/09/11 18:49, Bruno Cardoso Lopes wrote:
> Cool!
>
> On Thu, Sep 8, 2011 at 1:11 AM, Nadav Rotem<nadav.rotem at intel.com>  wrote:
>> Author: nadav
>> Date: Thu Sep  8 03:11:19 2011
>> New Revision: 139285
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=139285&view=rev
>> Log:
>> Add X86-SSE4 codegen support for vector-select.
>>
>>
>> Modified:
>>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>     llvm/trunk/lib/Target/X86/X86ISelLowering.h
>>     llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
>>     llvm/trunk/lib/Target/X86/X86InstrSSE.td
>>     llvm/trunk/test/CodeGen/Generic/promote-integers.ll
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139285&r1=139284&r2=139285&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep  8 03:11:19 2011
>> @@ -917,6 +917,13 @@
>>      setOperationAction(ISD::SHL,                MVT::v4i32, Custom);
>>      setOperationAction(ISD::SHL,                MVT::v16i8, Custom);
>>
>> +    setOperationAction(ISD::VSELECT,            MVT::v2f64, Custom);
>> +    setOperationAction(ISD::VSELECT,            MVT::v2i64, Custom);
>> +    setOperationAction(ISD::VSELECT,            MVT::v16i8, Custom);
>> +    setOperationAction(ISD::VSELECT,            MVT::v8i16, Custom);
>> +    setOperationAction(ISD::VSELECT,            MVT::v4i32, Custom);
>> +    setOperationAction(ISD::VSELECT,            MVT::v4f32, Custom);
>> +
>>      // i8 and i16 vectors are custom , because the source register and source
>>      // source memory operand types are not the same width.  f32 vectors are
>>      // custom since the immediate controlling the insert encodes additional
>> @@ -8684,6 +8691,32 @@
>>    return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
>>   }
>>
>> +SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG&DAG) const {
>> +  SDValue Cond  = Op.getOperand(0);
>> +  SDValue Op1 = Op.getOperand(1);
>> +  SDValue Op2 = Op.getOperand(2);
>> +  DebugLoc DL = Op.getDebugLoc();
>> +
>> +  SDValue Ops[] = {Cond, Op1, Op2};
>> +
>> +  assert(Op1.getValueType().isVector()&&  "Op1 must be a vector");
>> +  assert(Op2.getValueType().isVector()&&  "Op2 must be a vector");
>> +  assert(Cond.getValueType().isVector()&&  "Cond must be a vector");
>> +  assert(Op1.getValueType() == Op2.getValueType()&&  "Type mismatch");
>> +
>> +  switch (Op1.getValueType().getSimpleVT().SimpleTy) {
>> +    default: break;
>> +    case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
>> +    case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
>> +    case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
>> +    case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
>> +    case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
>> +  }
>
> This also breaks 80-columns restriction
>
>> +  return SDValue();
>> +}
>> +
>> +
>>   // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
>>   // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
>>   // from the AND / OR.
>> @@ -10350,6 +10383,7 @@
>>    case ISD::FGETSIGN:           return LowerFGETSIGN(Op, DAG);
>>    case ISD::SETCC:              return LowerSETCC(Op, DAG);
>>    case ISD::SELECT:             return LowerSELECT(Op, DAG);
>> +  case ISD::VSELECT:            return LowerVSELECT(Op, DAG);
>>    case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
>>    case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
>>    case ISD::VASTART:            return LowerVASTART(Op, DAG);
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=139285&r1=139284&r2=139285&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Sep  8 03:11:19 2011
>> @@ -175,8 +175,10 @@
>>        /// PSIGNB/W/D - Copy integer sign.
>>        PSIGNB, PSIGNW, PSIGND,
>>
>> -      /// PBLENDVB - Variable blend
>> +      /// BLENDVXX family of opcodes
>>        PBLENDVB,
>> +      BLENDVPD,
>> +      BLENDVPS,
>>
>>        /// FMAX, FMIN - Floating point max and min.
>>        ///
>> @@ -809,6 +811,7 @@
>>      SDValue LowerSETCC(SDValue Op, SelectionDAG&DAG) const;
>>      SDValue LowerVSETCC(SDValue Op, SelectionDAG&DAG) const;
>>      SDValue LowerSELECT(SDValue Op, SelectionDAG&DAG) const;
>> +    SDValue LowerVSELECT(SDValue Op, SelectionDAG&DAG) const;
>>      SDValue LowerBRCOND(SDValue Op, SelectionDAG&DAG) const;
>>      SDValue LowerMEMSET(SDValue Op, SelectionDAG&DAG) const;
>>      SDValue LowerJumpTable(SDValue Op, SelectionDAG&DAG) const;
>>
>> Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=139285&r1=139284&r2=139285&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Thu Sep  8 03:11:19 2011
>> @@ -58,9 +58,15 @@
>>   def X86psignd  : SDNode<"X86ISD::PSIGND",
>>                   SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
>>                                        SDTCisSameAs<0,2>]>>;
>> -def X86pblendv : SDNode<"X86ISD::PBLENDVB",
>> +def X86pblendvb : SDNode<"X86ISD::PBLENDVB",
>>                   SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
>>                                        SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
>> +def X86blendvpd : SDNode<"X86ISD::BLENDVPD",
>> +                  SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
>> +                                       SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
>> +def X86blendvps : SDNode<"X86ISD::BLENDVPS",
>> +                 SDTypeProfile<1, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
>> +                                      SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
>>   def X86pextrb  : SDNode<"X86ISD::PEXTRB",
>>                   SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
>>   def X86pextrw  : SDNode<"X86ISD::PEXTRW",
>>
>> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139285&r1=139284&r2=139285&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep  8 03:11:19 2011
>> @@ -5843,7 +5843,7 @@
>>   defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
>>                                           memopv32i8, int_x86_avx_blendv_ps_256>;
>>
>> -def : Pat<(X86pblendv VR128:$src1, VR128:$src2, VR128:$src3),
>> +def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, VR128:$src3),
>>            (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$src3)>,
>>            Requires<[HasAVX]>;
>>
>> @@ -5871,8 +5871,12 @@
>>   defm BLENDVPS     : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
>>   defm PBLENDVB     : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
>>
>> -def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
>> +def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0),
>>            (PBLENDVBrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
>> +def : Pat<(X86blendvpd  XMM0, VR128:$src1, VR128:$src2),
>> +          (BLENDVPDrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
>> +def : Pat<(X86blendvps  XMM0, VR128:$src1, VR128:$src2),
>> +          (BLENDVPSrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
>
> I will do it this time, but next time can you add the AVX versions
> when adding SSE ones? Usually all you need are the same patterns but
> with a different predicate!
>
>>   let Predicates = [HasAVX] in
>>   def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
>>
>> Modified: llvm/trunk/test/CodeGen/Generic/promote-integers.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/promote-integers.ll?rev=139285&r1=139284&r2=139285&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/Generic/promote-integers.ll (original)
>> +++ llvm/trunk/test/CodeGen/Generic/promote-integers.ll Thu Sep  8 03:11:19 2011
>> @@ -3,8 +3,8 @@
>>
>>   ; This test is the poster-child for integer-element-promotion.
>>   ; Until this feature is complete, we mark this test as expected to fail.
>> -; XFAIL: *
>>   ; CHECK: vector_code
>> +; CHECK: blend
>>   ; CHECK: ret
>>   define<4 x float>  @vector_code(<4 x i64>  %A,<4 x i64>  %B,<4 x float>  %R0,<4 x float>  %R1 )  {
>>     %C = icmp eq<4 x i64>  %A, %B
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>
>
>


From bruno.cardoso at gmail.com  Thu Sep  8 13:27:06 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 8 Sep 2011 11:27:06 -0700
Subject: [llvm-commits] [llvm] r139285 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/Generic/promote-integers.ll
In-Reply-To: <4E6906D2.1040100@free.fr>
References: <20110908081120.3B4E02A6C12D@llvm.org>
	<CACk9FxZWx=tNjMEc7pVdN3_QjZJ+03kodUu84+CPh0dpLLqBAA@mail.gmail.com>
	<4E6906D2.1040100@free.fr>
Message-ID: <CACk9Fxak3Bym=HjJMs=XsEimMkodXG8nj6wAijuk2ZjOm5oxXA@mail.gmail.com>

On Thu, Sep 8, 2011 at 11:17 AM, Duncan Sands <baldrick at free.fr> wrote:
> Now I come to think about it, is there any need to custom lower: since vselect
> maps directly onto processor instructions, can't it be done entirely using
> tablegen patterns? ?That said, I have no idea how tablegen works, so feel free
> to ignore me if this makes no sense :)

True! I don't see any direct reasons why that wouldn't work and would
be much nicer! Nadav, can you try it?

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From bruno.cardoso at gmail.com  Thu Sep  8 13:32:36 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 08 Sep 2011 18:32:36 -0000
Subject: [llvm-commits] [llvm] r139309 -
	/llvm/trunk/test/CodeGen/X86/avx-blend.ll
Message-ID: <20110908183236.E8ED32A6C12C@llvm.org>

Author: bruno
Date: Thu Sep  8 13:32:36 2011
New Revision: 139309

URL: http://llvm.org/viewvc/llvm-project?rev=139309&view=rev
Log:
Remove this crashing test, until I figure out what's going wrong here

Removed:
    llvm/trunk/test/CodeGen/X86/avx-blend.ll

Removed: llvm/trunk/test/CodeGen/X86/avx-blend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?rev=139308&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-blend.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-blend.ll (removed)
@@ -1,47 +0,0 @@
-; RUN: llc < %s -mattr=+avx -march=x86 | FileCheck %s
-
-;CHECK: vsel_float
-;CHECK: vblendvps
-;CHECK: ret
-define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
-  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
-  ret <4 x float> %vsel
-}
-
-
-;CHECK: vsel_i32
-;CHECK: vblendvps
-;CHECK: ret
-define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
-  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2
-  ret <4 x i32> %vsel
-}
-
-
-;CHECK: vsel_double
-;CHECK: vblendvpd
-;CHECK: ret
-define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
-  %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2
-  ret <2 x double> %vsel
-}
-
-
-;CHECK: vsel_i64
-;CHECK: vblendvpd
-;CHECK: ret
-define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
-  %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2
-  ret <2 x i64> %vsel
-}
-
-
-;CHECK: vsel_i8
-;CHECK: vpblendvb
-;CHECK: ret
-define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
-  %vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
-  ret <16 x i8> %vsel
-}
-
-



From bruno.cardoso at gmail.com  Thu Sep  8 13:35:57 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 08 Sep 2011 18:35:57 -0000
Subject: [llvm-commits] [llvm] r139311 - in /llvm/trunk/lib/Target/X86:
 X86InstrInfo.cpp X86InstrInfo.h
Message-ID: <20110908183557.71D2E2A6C12C@llvm.org>

Author: bruno
Date: Thu Sep  8 13:35:57 2011
New Revision: 139311

URL: http://llvm.org/viewvc/llvm-project?rev=139311&view=rev
Log:
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.

* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }

* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.

* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.

* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).

Patch by David Meyer

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=139311&r1=139310&r2=139311&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Sep  8 13:35:57 2011
@@ -53,6 +53,36 @@
                  cl::desc("Re-materialize load from stub in PIC mode"),
                  cl::init(false), cl::Hidden);
 
+enum {
+  // Select which memory operand is being unfolded.
+  // (stored in bits 0 - 7)
+  TB_INDEX_0    = 0,
+  TB_INDEX_1    = 1,
+  TB_INDEX_2    = 2,
+  TB_INDEX_MASK = 0xff,
+
+  // Minimum alignment required for load/store.
+  // Used for RegOp->MemOp conversion.
+  // (stored in bits 8 - 15)
+  TB_ALIGN_SHIFT = 8,
+  TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
+  TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
+  TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
+  TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT,
+
+  // Do not insert the reverse map (MemOp -> RegOp) into the table.
+  // This may be needed because there is a many -> one mapping.
+  TB_NO_REVERSE   = 1 << 16,
+
+  // Do not insert the forward map (RegOp -> MemOp) into the table.
+  // This is needed for Native Client, which prohibits branch
+  // instructions from using a memory operand.
+  TB_NO_FORWARD   = 1 << 17,
+
+  TB_FOLDED_LOAD  = 1 << 18,
+  TB_FOLDED_STORE = 1 << 19
+};
+
 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
   : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
                      ? X86::ADJCALLSTACKDOWN64
@@ -61,661 +91,633 @@
                      ? X86::ADJCALLSTACKUP64
                      : X86::ADJCALLSTACKUP32)),
     TM(tm), RI(tm, *this) {
-  enum {
-    TB_NOT_REVERSABLE = 1U << 31,
-    TB_FLAGS = TB_NOT_REVERSABLE
-  };
 
-  static const unsigned OpTbl2Addr[][2] = {
-    { X86::ADC32ri,     X86::ADC32mi },
-    { X86::ADC32ri8,    X86::ADC32mi8 },
-    { X86::ADC32rr,     X86::ADC32mr },
-    { X86::ADC64ri32,   X86::ADC64mi32 },
-    { X86::ADC64ri8,    X86::ADC64mi8 },
-    { X86::ADC64rr,     X86::ADC64mr },
-    { X86::ADD16ri,     X86::ADD16mi },
-    { X86::ADD16ri8,    X86::ADD16mi8 },
-    { X86::ADD16ri_DB,  X86::ADD16mi  | TB_NOT_REVERSABLE },
-    { X86::ADD16ri8_DB, X86::ADD16mi8 | TB_NOT_REVERSABLE },
-    { X86::ADD16rr,     X86::ADD16mr },
-    { X86::ADD16rr_DB,  X86::ADD16mr | TB_NOT_REVERSABLE },
-    { X86::ADD32ri,     X86::ADD32mi },
-    { X86::ADD32ri8,    X86::ADD32mi8 },
-    { X86::ADD32ri_DB,  X86::ADD32mi | TB_NOT_REVERSABLE },
-    { X86::ADD32ri8_DB, X86::ADD32mi8 | TB_NOT_REVERSABLE },
-    { X86::ADD32rr,     X86::ADD32mr },
-    { X86::ADD32rr_DB,  X86::ADD32mr | TB_NOT_REVERSABLE },
-    { X86::ADD64ri32,   X86::ADD64mi32 },
-    { X86::ADD64ri8,    X86::ADD64mi8 },
-    { X86::ADD64ri32_DB,X86::ADD64mi32 | TB_NOT_REVERSABLE },
-    { X86::ADD64ri8_DB, X86::ADD64mi8 | TB_NOT_REVERSABLE },
-    { X86::ADD64rr,     X86::ADD64mr },
-    { X86::ADD64rr_DB,  X86::ADD64mr | TB_NOT_REVERSABLE },
-    { X86::ADD8ri,      X86::ADD8mi },
-    { X86::ADD8rr,      X86::ADD8mr },
-    { X86::AND16ri,     X86::AND16mi },
-    { X86::AND16ri8,    X86::AND16mi8 },
-    { X86::AND16rr,     X86::AND16mr },
-    { X86::AND32ri,     X86::AND32mi },
-    { X86::AND32ri8,    X86::AND32mi8 },
-    { X86::AND32rr,     X86::AND32mr },
-    { X86::AND64ri32,   X86::AND64mi32 },
-    { X86::AND64ri8,    X86::AND64mi8 },
-    { X86::AND64rr,     X86::AND64mr },
-    { X86::AND8ri,      X86::AND8mi },
-    { X86::AND8rr,      X86::AND8mr },
-    { X86::DEC16r,      X86::DEC16m },
-    { X86::DEC32r,      X86::DEC32m },
-    { X86::DEC64_16r,   X86::DEC64_16m },
-    { X86::DEC64_32r,   X86::DEC64_32m },
-    { X86::DEC64r,      X86::DEC64m },
-    { X86::DEC8r,       X86::DEC8m },
-    { X86::INC16r,      X86::INC16m },
-    { X86::INC32r,      X86::INC32m },
-    { X86::INC64_16r,   X86::INC64_16m },
-    { X86::INC64_32r,   X86::INC64_32m },
-    { X86::INC64r,      X86::INC64m },
-    { X86::INC8r,       X86::INC8m },
-    { X86::NEG16r,      X86::NEG16m },
-    { X86::NEG32r,      X86::NEG32m },
-    { X86::NEG64r,      X86::NEG64m },
-    { X86::NEG8r,       X86::NEG8m },
-    { X86::NOT16r,      X86::NOT16m },
-    { X86::NOT32r,      X86::NOT32m },
-    { X86::NOT64r,      X86::NOT64m },
-    { X86::NOT8r,       X86::NOT8m },
-    { X86::OR16ri,      X86::OR16mi },
-    { X86::OR16ri8,     X86::OR16mi8 },
-    { X86::OR16rr,      X86::OR16mr },
-    { X86::OR32ri,      X86::OR32mi },
-    { X86::OR32ri8,     X86::OR32mi8 },
-    { X86::OR32rr,      X86::OR32mr },
-    { X86::OR64ri32,    X86::OR64mi32 },
-    { X86::OR64ri8,     X86::OR64mi8 },
-    { X86::OR64rr,      X86::OR64mr },
-    { X86::OR8ri,       X86::OR8mi },
-    { X86::OR8rr,       X86::OR8mr },
-    { X86::ROL16r1,     X86::ROL16m1 },
-    { X86::ROL16rCL,    X86::ROL16mCL },
-    { X86::ROL16ri,     X86::ROL16mi },
-    { X86::ROL32r1,     X86::ROL32m1 },
-    { X86::ROL32rCL,    X86::ROL32mCL },
-    { X86::ROL32ri,     X86::ROL32mi },
-    { X86::ROL64r1,     X86::ROL64m1 },
-    { X86::ROL64rCL,    X86::ROL64mCL },
-    { X86::ROL64ri,     X86::ROL64mi },
-    { X86::ROL8r1,      X86::ROL8m1 },
-    { X86::ROL8rCL,     X86::ROL8mCL },
-    { X86::ROL8ri,      X86::ROL8mi },
-    { X86::ROR16r1,     X86::ROR16m1 },
-    { X86::ROR16rCL,    X86::ROR16mCL },
-    { X86::ROR16ri,     X86::ROR16mi },
-    { X86::ROR32r1,     X86::ROR32m1 },
-    { X86::ROR32rCL,    X86::ROR32mCL },
-    { X86::ROR32ri,     X86::ROR32mi },
-    { X86::ROR64r1,     X86::ROR64m1 },
-    { X86::ROR64rCL,    X86::ROR64mCL },
-    { X86::ROR64ri,     X86::ROR64mi },
-    { X86::ROR8r1,      X86::ROR8m1 },
-    { X86::ROR8rCL,     X86::ROR8mCL },
-    { X86::ROR8ri,      X86::ROR8mi },
-    { X86::SAR16r1,     X86::SAR16m1 },
-    { X86::SAR16rCL,    X86::SAR16mCL },
-    { X86::SAR16ri,     X86::SAR16mi },
-    { X86::SAR32r1,     X86::SAR32m1 },
-    { X86::SAR32rCL,    X86::SAR32mCL },
-    { X86::SAR32ri,     X86::SAR32mi },
-    { X86::SAR64r1,     X86::SAR64m1 },
-    { X86::SAR64rCL,    X86::SAR64mCL },
-    { X86::SAR64ri,     X86::SAR64mi },
-    { X86::SAR8r1,      X86::SAR8m1 },
-    { X86::SAR8rCL,     X86::SAR8mCL },
-    { X86::SAR8ri,      X86::SAR8mi },
-    { X86::SBB32ri,     X86::SBB32mi },
-    { X86::SBB32ri8,    X86::SBB32mi8 },
-    { X86::SBB32rr,     X86::SBB32mr },
-    { X86::SBB64ri32,   X86::SBB64mi32 },
-    { X86::SBB64ri8,    X86::SBB64mi8 },
-    { X86::SBB64rr,     X86::SBB64mr },
-    { X86::SHL16rCL,    X86::SHL16mCL },
-    { X86::SHL16ri,     X86::SHL16mi },
-    { X86::SHL32rCL,    X86::SHL32mCL },
-    { X86::SHL32ri,     X86::SHL32mi },
-    { X86::SHL64rCL,    X86::SHL64mCL },
-    { X86::SHL64ri,     X86::SHL64mi },
-    { X86::SHL8rCL,     X86::SHL8mCL },
-    { X86::SHL8ri,      X86::SHL8mi },
-    { X86::SHLD16rrCL,  X86::SHLD16mrCL },
-    { X86::SHLD16rri8,  X86::SHLD16mri8 },
-    { X86::SHLD32rrCL,  X86::SHLD32mrCL },
-    { X86::SHLD32rri8,  X86::SHLD32mri8 },
-    { X86::SHLD64rrCL,  X86::SHLD64mrCL },
-    { X86::SHLD64rri8,  X86::SHLD64mri8 },
-    { X86::SHR16r1,     X86::SHR16m1 },
-    { X86::SHR16rCL,    X86::SHR16mCL },
-    { X86::SHR16ri,     X86::SHR16mi },
-    { X86::SHR32r1,     X86::SHR32m1 },
-    { X86::SHR32rCL,    X86::SHR32mCL },
-    { X86::SHR32ri,     X86::SHR32mi },
-    { X86::SHR64r1,     X86::SHR64m1 },
-    { X86::SHR64rCL,    X86::SHR64mCL },
-    { X86::SHR64ri,     X86::SHR64mi },
-    { X86::SHR8r1,      X86::SHR8m1 },
-    { X86::SHR8rCL,     X86::SHR8mCL },
-    { X86::SHR8ri,      X86::SHR8mi },
-    { X86::SHRD16rrCL,  X86::SHRD16mrCL },
-    { X86::SHRD16rri8,  X86::SHRD16mri8 },
-    { X86::SHRD32rrCL,  X86::SHRD32mrCL },
-    { X86::SHRD32rri8,  X86::SHRD32mri8 },
-    { X86::SHRD64rrCL,  X86::SHRD64mrCL },
-    { X86::SHRD64rri8,  X86::SHRD64mri8 },
-    { X86::SUB16ri,     X86::SUB16mi },
-    { X86::SUB16ri8,    X86::SUB16mi8 },
-    { X86::SUB16rr,     X86::SUB16mr },
-    { X86::SUB32ri,     X86::SUB32mi },
-    { X86::SUB32ri8,    X86::SUB32mi8 },
-    { X86::SUB32rr,     X86::SUB32mr },
-    { X86::SUB64ri32,   X86::SUB64mi32 },
-    { X86::SUB64ri8,    X86::SUB64mi8 },
-    { X86::SUB64rr,     X86::SUB64mr },
-    { X86::SUB8ri,      X86::SUB8mi },
-    { X86::SUB8rr,      X86::SUB8mr },
-    { X86::XOR16ri,     X86::XOR16mi },
-    { X86::XOR16ri8,    X86::XOR16mi8 },
-    { X86::XOR16rr,     X86::XOR16mr },
-    { X86::XOR32ri,     X86::XOR32mi },
-    { X86::XOR32ri8,    X86::XOR32mi8 },
-    { X86::XOR32rr,     X86::XOR32mr },
-    { X86::XOR64ri32,   X86::XOR64mi32 },
-    { X86::XOR64ri8,    X86::XOR64mi8 },
-    { X86::XOR64rr,     X86::XOR64mr },
-    { X86::XOR8ri,      X86::XOR8mi },
-    { X86::XOR8rr,      X86::XOR8mr }
+  static const unsigned OpTbl2Addr[][3] = {
+    { X86::ADC32ri,     X86::ADC32mi,    0 },
+    { X86::ADC32ri8,    X86::ADC32mi8,   0 },
+    { X86::ADC32rr,     X86::ADC32mr,    0 },
+    { X86::ADC64ri32,   X86::ADC64mi32,  0 },
+    { X86::ADC64ri8,    X86::ADC64mi8,   0 },
+    { X86::ADC64rr,     X86::ADC64mr,    0 },
+    { X86::ADD16ri,     X86::ADD16mi,    0 },
+    { X86::ADD16ri8,    X86::ADD16mi8,   0 },
+    { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
+    { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
+    { X86::ADD16rr,     X86::ADD16mr,    0 },
+    { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
+    { X86::ADD32ri,     X86::ADD32mi,    0 },
+    { X86::ADD32ri8,    X86::ADD32mi8,   0 },
+    { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
+    { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
+    { X86::ADD32rr,     X86::ADD32mr,    0 },
+    { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
+    { X86::ADD64ri32,   X86::ADD64mi32,  0 },
+    { X86::ADD64ri8,    X86::ADD64mi8,   0 },
+    { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
+    { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
+    { X86::ADD64rr,     X86::ADD64mr,    0 },
+    { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
+    { X86::ADD8ri,      X86::ADD8mi,     0 },
+    { X86::ADD8rr,      X86::ADD8mr,     0 },
+    { X86::AND16ri,     X86::AND16mi,    0 },
+    { X86::AND16ri8,    X86::AND16mi8,   0 },
+    { X86::AND16rr,     X86::AND16mr,    0 },
+    { X86::AND32ri,     X86::AND32mi,    0 },
+    { X86::AND32ri8,    X86::AND32mi8,   0 },
+    { X86::AND32rr,     X86::AND32mr,    0 },
+    { X86::AND64ri32,   X86::AND64mi32,  0 },
+    { X86::AND64ri8,    X86::AND64mi8,   0 },
+    { X86::AND64rr,     X86::AND64mr,    0 },
+    { X86::AND8ri,      X86::AND8mi,     0 },
+    { X86::AND8rr,      X86::AND8mr,     0 },
+    { X86::DEC16r,      X86::DEC16m,     0 },
+    { X86::DEC32r,      X86::DEC32m,     0 },
+    { X86::DEC64_16r,   X86::DEC64_16m,  0 },
+    { X86::DEC64_32r,   X86::DEC64_32m,  0 },
+    { X86::DEC64r,      X86::DEC64m,     0 },
+    { X86::DEC8r,       X86::DEC8m,      0 },
+    { X86::INC16r,      X86::INC16m,     0 },
+    { X86::INC32r,      X86::INC32m,     0 },
+    { X86::INC64_16r,   X86::INC64_16m,  0 },
+    { X86::INC64_32r,   X86::INC64_32m,  0 },
+    { X86::INC64r,      X86::INC64m,     0 },
+    { X86::INC8r,       X86::INC8m,      0 },
+    { X86::NEG16r,      X86::NEG16m,     0 },
+    { X86::NEG32r,      X86::NEG32m,     0 },
+    { X86::NEG64r,      X86::NEG64m,     0 },
+    { X86::NEG8r,       X86::NEG8m,      0 },
+    { X86::NOT16r,      X86::NOT16m,     0 },
+    { X86::NOT32r,      X86::NOT32m,     0 },
+    { X86::NOT64r,      X86::NOT64m,     0 },
+    { X86::NOT8r,       X86::NOT8m,      0 },
+    { X86::OR16ri,      X86::OR16mi,     0 },
+    { X86::OR16ri8,     X86::OR16mi8,    0 },
+    { X86::OR16rr,      X86::OR16mr,     0 },
+    { X86::OR32ri,      X86::OR32mi,     0 },
+    { X86::OR32ri8,     X86::OR32mi8,    0 },
+    { X86::OR32rr,      X86::OR32mr,     0 },
+    { X86::OR64ri32,    X86::OR64mi32,   0 },
+    { X86::OR64ri8,     X86::OR64mi8,    0 },
+    { X86::OR64rr,      X86::OR64mr,     0 },
+    { X86::OR8ri,       X86::OR8mi,      0 },
+    { X86::OR8rr,       X86::OR8mr,      0 },
+    { X86::ROL16r1,     X86::ROL16m1,    0 },
+    { X86::ROL16rCL,    X86::ROL16mCL,   0 },
+    { X86::ROL16ri,     X86::ROL16mi,    0 },
+    { X86::ROL32r1,     X86::ROL32m1,    0 },
+    { X86::ROL32rCL,    X86::ROL32mCL,   0 },
+    { X86::ROL32ri,     X86::ROL32mi,    0 },
+    { X86::ROL64r1,     X86::ROL64m1,    0 },
+    { X86::ROL64rCL,    X86::ROL64mCL,   0 },
+    { X86::ROL64ri,     X86::ROL64mi,    0 },
+    { X86::ROL8r1,      X86::ROL8m1,     0 },
+    { X86::ROL8rCL,     X86::ROL8mCL,    0 },
+    { X86::ROL8ri,      X86::ROL8mi,     0 },
+    { X86::ROR16r1,     X86::ROR16m1,    0 },
+    { X86::ROR16rCL,    X86::ROR16mCL,   0 },
+    { X86::ROR16ri,     X86::ROR16mi,    0 },
+    { X86::ROR32r1,     X86::ROR32m1,    0 },
+    { X86::ROR32rCL,    X86::ROR32mCL,   0 },
+    { X86::ROR32ri,     X86::ROR32mi,    0 },
+    { X86::ROR64r1,     X86::ROR64m1,    0 },
+    { X86::ROR64rCL,    X86::ROR64mCL,   0 },
+    { X86::ROR64ri,     X86::ROR64mi,    0 },
+    { X86::ROR8r1,      X86::ROR8m1,     0 },
+    { X86::ROR8rCL,     X86::ROR8mCL,    0 },
+    { X86::ROR8ri,      X86::ROR8mi,     0 },
+    { X86::SAR16r1,     X86::SAR16m1,    0 },
+    { X86::SAR16rCL,    X86::SAR16mCL,   0 },
+    { X86::SAR16ri,     X86::SAR16mi,    0 },
+    { X86::SAR32r1,     X86::SAR32m1,    0 },
+    { X86::SAR32rCL,    X86::SAR32mCL,   0 },
+    { X86::SAR32ri,     X86::SAR32mi,    0 },
+    { X86::SAR64r1,     X86::SAR64m1,    0 },
+    { X86::SAR64rCL,    X86::SAR64mCL,   0 },
+    { X86::SAR64ri,     X86::SAR64mi,    0 },
+    { X86::SAR8r1,      X86::SAR8m1,     0 },
+    { X86::SAR8rCL,     X86::SAR8mCL,    0 },
+    { X86::SAR8ri,      X86::SAR8mi,     0 },
+    { X86::SBB32ri,     X86::SBB32mi,    0 },
+    { X86::SBB32ri8,    X86::SBB32mi8,   0 },
+    { X86::SBB32rr,     X86::SBB32mr,    0 },
+    { X86::SBB64ri32,   X86::SBB64mi32,  0 },
+    { X86::SBB64ri8,    X86::SBB64mi8,   0 },
+    { X86::SBB64rr,     X86::SBB64mr,    0 },
+    { X86::SHL16rCL,    X86::SHL16mCL,   0 },
+    { X86::SHL16ri,     X86::SHL16mi,    0 },
+    { X86::SHL32rCL,    X86::SHL32mCL,   0 },
+    { X86::SHL32ri,     X86::SHL32mi,    0 },
+    { X86::SHL64rCL,    X86::SHL64mCL,   0 },
+    { X86::SHL64ri,     X86::SHL64mi,    0 },
+    { X86::SHL8rCL,     X86::SHL8mCL,    0 },
+    { X86::SHL8ri,      X86::SHL8mi,     0 },
+    { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
+    { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
+    { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
+    { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
+    { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
+    { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
+    { X86::SHR16r1,     X86::SHR16m1,    0 },
+    { X86::SHR16rCL,    X86::SHR16mCL,   0 },
+    { X86::SHR16ri,     X86::SHR16mi,    0 },
+    { X86::SHR32r1,     X86::SHR32m1,    0 },
+    { X86::SHR32rCL,    X86::SHR32mCL,   0 },
+    { X86::SHR32ri,     X86::SHR32mi,    0 },
+    { X86::SHR64r1,     X86::SHR64m1,    0 },
+    { X86::SHR64rCL,    X86::SHR64mCL,   0 },
+    { X86::SHR64ri,     X86::SHR64mi,    0 },
+    { X86::SHR8r1,      X86::SHR8m1,     0 },
+    { X86::SHR8rCL,     X86::SHR8mCL,    0 },
+    { X86::SHR8ri,      X86::SHR8mi,     0 },
+    { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
+    { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
+    { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
+    { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
+    { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
+    { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
+    { X86::SUB16ri,     X86::SUB16mi,    0 },
+    { X86::SUB16ri8,    X86::SUB16mi8,   0 },
+    { X86::SUB16rr,     X86::SUB16mr,    0 },
+    { X86::SUB32ri,     X86::SUB32mi,    0 },
+    { X86::SUB32ri8,    X86::SUB32mi8,   0 },
+    { X86::SUB32rr,     X86::SUB32mr,    0 },
+    { X86::SUB64ri32,   X86::SUB64mi32,  0 },
+    { X86::SUB64ri8,    X86::SUB64mi8,   0 },
+    { X86::SUB64rr,     X86::SUB64mr,    0 },
+    { X86::SUB8ri,      X86::SUB8mi,     0 },
+    { X86::SUB8rr,      X86::SUB8mr,     0 },
+    { X86::XOR16ri,     X86::XOR16mi,    0 },
+    { X86::XOR16ri8,    X86::XOR16mi8,   0 },
+    { X86::XOR16rr,     X86::XOR16mr,    0 },
+    { X86::XOR32ri,     X86::XOR32mi,    0 },
+    { X86::XOR32ri8,    X86::XOR32mi8,   0 },
+    { X86::XOR32rr,     X86::XOR32mr,    0 },
+    { X86::XOR64ri32,   X86::XOR64mi32,  0 },
+    { X86::XOR64ri8,    X86::XOR64mi8,   0 },
+    { X86::XOR64rr,     X86::XOR64mr,    0 },
+    { X86::XOR8ri,      X86::XOR8mi,     0 },
+    { X86::XOR8rr,      X86::XOR8mr,     0 }
   };
 
   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
     unsigned RegOp = OpTbl2Addr[i][0];
-    unsigned MemOp = OpTbl2Addr[i][1] & ~TB_FLAGS;
-    assert(!RegOp2MemOpTable2Addr.count(RegOp) && "Duplicated entries?");
-    RegOp2MemOpTable2Addr[RegOp] = std::make_pair(MemOp, 0U);
-
-    // If this is not a reversible operation (because there is a many->one)
-    // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
-    if (OpTbl2Addr[i][1] & TB_NOT_REVERSABLE)
-      continue;
-
-    // Index 0, folded load and store, no alignment requirement.
-    unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
-
-    assert(!MemOp2RegOpTable.count(MemOp) &&
-            "Duplicated entries in unfolding maps?");
-    MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
-  }
-
-  // If the third value is 1, then it's folding either a load or a store.
-  static const unsigned OpTbl0[][4] = {
-    { X86::BT16ri8,     X86::BT16mi8, 1, 0 },
-    { X86::BT32ri8,     X86::BT32mi8, 1, 0 },
-    { X86::BT64ri8,     X86::BT64mi8, 1, 0 },
-    { X86::CALL32r,     X86::CALL32m, 1, 0 },
-    { X86::CALL64r,     X86::CALL64m, 1, 0 },
-    { X86::WINCALL64r,  X86::WINCALL64m, 1, 0 },
-    { X86::CMP16ri,     X86::CMP16mi, 1, 0 },
-    { X86::CMP16ri8,    X86::CMP16mi8, 1, 0 },
-    { X86::CMP16rr,     X86::CMP16mr, 1, 0 },
-    { X86::CMP32ri,     X86::CMP32mi, 1, 0 },
-    { X86::CMP32ri8,    X86::CMP32mi8, 1, 0 },
-    { X86::CMP32rr,     X86::CMP32mr, 1, 0 },
-    { X86::CMP64ri32,   X86::CMP64mi32, 1, 0 },
-    { X86::CMP64ri8,    X86::CMP64mi8, 1, 0 },
-    { X86::CMP64rr,     X86::CMP64mr, 1, 0 },
-    { X86::CMP8ri,      X86::CMP8mi, 1, 0 },
-    { X86::CMP8rr,      X86::CMP8mr, 1, 0 },
-    { X86::DIV16r,      X86::DIV16m, 1, 0 },
-    { X86::DIV32r,      X86::DIV32m, 1, 0 },
-    { X86::DIV64r,      X86::DIV64m, 1, 0 },
-    { X86::DIV8r,       X86::DIV8m, 1, 0 },
-    { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
-    { X86::FsMOVAPDrr,  X86::MOVSDmr | TB_NOT_REVERSABLE , 0, 0 },
-    { X86::FsMOVAPSrr,  X86::MOVSSmr | TB_NOT_REVERSABLE , 0, 0 },
-    { X86::FsVMOVAPDrr, X86::VMOVSDmr | TB_NOT_REVERSABLE , 0, 0 },
-    { X86::FsVMOVAPSrr, X86::VMOVSSmr | TB_NOT_REVERSABLE , 0, 0 },
-    { X86::IDIV16r,     X86::IDIV16m, 1, 0 },
-    { X86::IDIV32r,     X86::IDIV32m, 1, 0 },
-    { X86::IDIV64r,     X86::IDIV64m, 1, 0 },
-    { X86::IDIV8r,      X86::IDIV8m, 1, 0 },
-    { X86::IMUL16r,     X86::IMUL16m, 1, 0 },
-    { X86::IMUL32r,     X86::IMUL32m, 1, 0 },
-    { X86::IMUL64r,     X86::IMUL64m, 1, 0 },
-    { X86::IMUL8r,      X86::IMUL8m, 1, 0 },
-    { X86::JMP32r,      X86::JMP32m, 1, 0 },
-    { X86::JMP64r,      X86::JMP64m, 1, 0 },
-    { X86::MOV16ri,     X86::MOV16mi, 0, 0 },
-    { X86::MOV16rr,     X86::MOV16mr, 0, 0 },
-    { X86::MOV32ri,     X86::MOV32mi, 0, 0 },
-    { X86::MOV32rr,     X86::MOV32mr, 0, 0 },
-    { X86::MOV64ri32,   X86::MOV64mi32, 0, 0 },
-    { X86::MOV64rr,     X86::MOV64mr, 0, 0 },
-    { X86::MOV8ri,      X86::MOV8mi, 0, 0 },
-    { X86::MOV8rr,      X86::MOV8mr, 0, 0 },
-    { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
-    { X86::MOVAPDrr,    X86::MOVAPDmr, 0, 16 },
-    { X86::MOVAPSrr,    X86::MOVAPSmr, 0, 16 },
-    { X86::MOVDQArr,    X86::MOVDQAmr, 0, 16 },
-    { X86::VMOVAPDYrr,  X86::VMOVAPDYmr, 0, 32 },
-    { X86::VMOVAPSYrr,  X86::VMOVAPSYmr, 0, 32 },
-    { X86::VMOVDQAYrr,  X86::VMOVDQAYmr, 0, 32 },
-    { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
-    { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
-    { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
-    { X86::MOVSS2DIrr,  X86::MOVSS2DImr, 0, 0 },
-    { X86::MOVUPDrr,    X86::MOVUPDmr, 0, 0 },
-    { X86::MOVUPSrr,    X86::MOVUPSmr, 0, 0 },
-    { X86::VMOVUPDYrr,  X86::VMOVUPDYmr, 0, 0 },
-    { X86::VMOVUPSYrr,  X86::VMOVUPSYmr, 0, 0 },
-    { X86::MUL16r,      X86::MUL16m, 1, 0 },
-    { X86::MUL32r,      X86::MUL32m, 1, 0 },
-    { X86::MUL64r,      X86::MUL64m, 1, 0 },
-    { X86::MUL8r,       X86::MUL8m, 1, 0 },
-    { X86::SETAEr,      X86::SETAEm, 0, 0 },
-    { X86::SETAr,       X86::SETAm, 0, 0 },
-    { X86::SETBEr,      X86::SETBEm, 0, 0 },
-    { X86::SETBr,       X86::SETBm, 0, 0 },
-    { X86::SETEr,       X86::SETEm, 0, 0 },
-    { X86::SETGEr,      X86::SETGEm, 0, 0 },
-    { X86::SETGr,       X86::SETGm, 0, 0 },
-    { X86::SETLEr,      X86::SETLEm, 0, 0 },
-    { X86::SETLr,       X86::SETLm, 0, 0 },
-    { X86::SETNEr,      X86::SETNEm, 0, 0 },
-    { X86::SETNOr,      X86::SETNOm, 0, 0 },
-    { X86::SETNPr,      X86::SETNPm, 0, 0 },
-    { X86::SETNSr,      X86::SETNSm, 0, 0 },
-    { X86::SETOr,       X86::SETOm, 0, 0 },
-    { X86::SETPr,       X86::SETPm, 0, 0 },
-    { X86::SETSr,       X86::SETSm, 0, 0 },
-    { X86::TAILJMPr,    X86::TAILJMPm, 1, 0 },
-    { X86::TAILJMPr64,  X86::TAILJMPm64, 1, 0 },
-    { X86::TEST16ri,    X86::TEST16mi, 1, 0 },
-    { X86::TEST32ri,    X86::TEST32mi, 1, 0 },
-    { X86::TEST64ri32,  X86::TEST64mi32, 1, 0 },
-    { X86::TEST8ri,     X86::TEST8mi, 1, 0 }
+    unsigned MemOp = OpTbl2Addr[i][1];
+    unsigned Flags = OpTbl2Addr[i][2];
+    AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
+                  RegOp, MemOp,
+                  // Index 0, folded load and store, no alignment requirement.
+                  Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
+  }
+
+  static const unsigned OpTbl0[][3] = {
+    { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
+    { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
+    { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
+    { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
+    { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
+    { X86::WINCALL64r,  X86::WINCALL64m,    TB_FOLDED_LOAD },
+    { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
+    { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
+    { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
+    { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
+    { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
+    { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
+    { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
+    { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
+    { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
+    { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
+    { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
+    { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
+    { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
+    { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
+    { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
+    { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE | TB_ALIGN_16 },
+    { X86::FsMOVAPDrr,  X86::MOVSDmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
+    { X86::FsMOVAPSrr,  X86::MOVSSmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
+    { X86::FsVMOVAPDrr, X86::VMOVSDmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
+    { X86::FsVMOVAPSrr, X86::VMOVSSmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
+    { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
+    { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
+    { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
+    { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
+    { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
+    { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
+    { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
+    { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
+    { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
+    { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
+    { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
+    { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
+    { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
+    { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
+    { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
+    { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
+    { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
+    { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
+    { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
+    { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
+    { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
+    { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
+    { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
+    { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
+    { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
+    { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
+    { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
+    { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
+    { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
+    { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
+    { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
+    { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
+    { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
+    { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
+    { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
+    { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
+    { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
+    { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
+    { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
+    { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
+    { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
+    { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
+    { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
+    { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
+    { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
+    { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
+    { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
+    { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
+    { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
+    { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
+    { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
+    { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
+    { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
+    { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
+    { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
+    { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
+    { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
+    { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
+    { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD }
   };
 
   for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
     unsigned RegOp      = OpTbl0[i][0];
-    unsigned MemOp      = OpTbl0[i][1] & ~TB_FLAGS;
-    unsigned FoldedLoad = OpTbl0[i][2];
-    unsigned Align      = OpTbl0[i][3];
-    assert(!RegOp2MemOpTable0.count(RegOp) && "Duplicated entries?");
-    RegOp2MemOpTable0[RegOp] = std::make_pair(MemOp, Align);
-
-    // If this is not a reversible operation (because there is a many->one)
-    // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
-    if (OpTbl0[i][1] & TB_NOT_REVERSABLE)
-      continue;
-
-    // Index 0, folded load or store.
-    unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
-    assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries?");
-    MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
+    unsigned MemOp      = OpTbl0[i][1];
+    unsigned Flags      = OpTbl0[i][2];
+    AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
+                  RegOp, MemOp, TB_INDEX_0 | Flags);
   }
 
   static const unsigned OpTbl1[][3] = {
-    { X86::CMP16rr,         X86::CMP16rm, 0 },
-    { X86::CMP32rr,         X86::CMP32rm, 0 },
-    { X86::CMP64rr,         X86::CMP64rm, 0 },
-    { X86::CMP8rr,          X86::CMP8rm, 0 },
-    { X86::CVTSD2SSrr,      X86::CVTSD2SSrm, 0 },
-    { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm, 0 },
-    { X86::CVTSI2SDrr,      X86::CVTSI2SDrm, 0 },
-    { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm, 0 },
-    { X86::CVTSI2SSrr,      X86::CVTSI2SSrm, 0 },
-    { X86::CVTSS2SDrr,      X86::CVTSS2SDrm, 0 },
-    { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm, 0 },
-    { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm, 0 },
-    { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm, 0 },
-    { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm, 0 },
-    { X86::FsMOVAPDrr,      X86::MOVSDrm | TB_NOT_REVERSABLE , 0 },
-    { X86::FsMOVAPSrr,      X86::MOVSSrm | TB_NOT_REVERSABLE , 0 },
-    { X86::FsVMOVAPDrr,     X86::VMOVSDrm | TB_NOT_REVERSABLE , 0 },
-    { X86::FsVMOVAPSrr,     X86::VMOVSSrm | TB_NOT_REVERSABLE , 0 },
-    { X86::IMUL16rri,       X86::IMUL16rmi, 0 },
-    { X86::IMUL16rri8,      X86::IMUL16rmi8, 0 },
-    { X86::IMUL32rri,       X86::IMUL32rmi, 0 },
-    { X86::IMUL32rri8,      X86::IMUL32rmi8, 0 },
-    { X86::IMUL64rri32,     X86::IMUL64rmi32, 0 },
-    { X86::IMUL64rri8,      X86::IMUL64rmi8, 0 },
-    { X86::Int_COMISDrr,    X86::Int_COMISDrm, 0 },
-    { X86::Int_COMISSrr,    X86::Int_COMISSrm, 0 },
-    { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm, 16 },
-    { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm, 16 },
-    { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm, 16 },
-    { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm, 16 },
-    { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm, 16 },
-    { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm, 0 },
-    { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm, 0 },
-    { X86::CVTSD2SIrr,      X86::CVTSD2SIrm, 0 },
-    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm, 0 },
-    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
-    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm, 0 },
-    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
-    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm, 0 },
-    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm, 0 },
-    { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm, 16 },
-    { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm, 16 },
-    { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
-    { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
-    { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
-    { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
-    { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm, 0 },
-    { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm, 0 },
-    { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm, 0 },
-    { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm, 0 },
-    { X86::MOV16rr,         X86::MOV16rm, 0 },
-    { X86::MOV32rr,         X86::MOV32rm, 0 },
-    { X86::MOV64rr,         X86::MOV64rm, 0 },
-    { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm, 0 },
-    { X86::MOV64toSDrr,     X86::MOV64toSDrm, 0 },
-    { X86::MOV8rr,          X86::MOV8rm, 0 },
-    { X86::MOVAPDrr,        X86::MOVAPDrm, 16 },
-    { X86::MOVAPSrr,        X86::MOVAPSrm, 16 },
-    { X86::VMOVAPDYrr,      X86::VMOVAPDYrm, 32 },
-    { X86::VMOVAPSYrr,      X86::VMOVAPSYrm, 32 },
-    { X86::MOVDDUPrr,       X86::MOVDDUPrm, 0 },
-    { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm, 0 },
-    { X86::MOVDI2SSrr,      X86::MOVDI2SSrm, 0 },
-    { X86::MOVDQArr,        X86::MOVDQArm, 16 },
-    { X86::VMOVDQAYrr,      X86::VMOVDQAYrm, 16 },
-    { X86::MOVSHDUPrr,      X86::MOVSHDUPrm, 16 },
-    { X86::MOVSLDUPrr,      X86::MOVSLDUPrm, 16 },
-    { X86::MOVSX16rr8,      X86::MOVSX16rm8, 0 },
-    { X86::MOVSX32rr16,     X86::MOVSX32rm16, 0 },
-    { X86::MOVSX32rr8,      X86::MOVSX32rm8, 0 },
-    { X86::MOVSX64rr16,     X86::MOVSX64rm16, 0 },
-    { X86::MOVSX64rr32,     X86::MOVSX64rm32, 0 },
-    { X86::MOVSX64rr8,      X86::MOVSX64rm8, 0 },
-    { X86::MOVUPDrr,        X86::MOVUPDrm, 16 },
-    { X86::MOVUPSrr,        X86::MOVUPSrm, 0 },
-    { X86::VMOVUPDYrr,      X86::VMOVUPDYrm, 0 },
-    { X86::VMOVUPSYrr,      X86::VMOVUPSYrm, 0 },
-    { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm, 0 },
-    { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm, 0 },
-    { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
-    { X86::MOVZX16rr8,      X86::MOVZX16rm8, 0 },
-    { X86::MOVZX32rr16,     X86::MOVZX32rm16, 0 },
-    { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
-    { X86::MOVZX32rr8,      X86::MOVZX32rm8, 0 },
-    { X86::MOVZX64rr16,     X86::MOVZX64rm16, 0 },
-    { X86::MOVZX64rr32,     X86::MOVZX64rm32, 0 },
-    { X86::MOVZX64rr8,      X86::MOVZX64rm8, 0 },
-    { X86::PSHUFDri,        X86::PSHUFDmi, 16 },
-    { X86::PSHUFHWri,       X86::PSHUFHWmi, 16 },
-    { X86::PSHUFLWri,       X86::PSHUFLWmi, 16 },
-    { X86::RCPPSr,          X86::RCPPSm, 16 },
-    { X86::RCPPSr_Int,      X86::RCPPSm_Int, 16 },
-    { X86::RSQRTPSr,        X86::RSQRTPSm, 16 },
-    { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int, 16 },
-    { X86::RSQRTSSr,        X86::RSQRTSSm, 0 },
-    { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int, 0 },
-    { X86::SQRTPDr,         X86::SQRTPDm, 16 },
-    { X86::SQRTPDr_Int,     X86::SQRTPDm_Int, 16 },
-    { X86::SQRTPSr,         X86::SQRTPSm, 16 },
-    { X86::SQRTPSr_Int,     X86::SQRTPSm_Int, 16 },
-    { X86::SQRTSDr,         X86::SQRTSDm, 0 },
-    { X86::SQRTSDr_Int,     X86::SQRTSDm_Int, 0 },
-    { X86::SQRTSSr,         X86::SQRTSSm, 0 },
-    { X86::SQRTSSr_Int,     X86::SQRTSSm_Int, 0 },
-    { X86::TEST16rr,        X86::TEST16rm, 0 },
-    { X86::TEST32rr,        X86::TEST32rm, 0 },
-    { X86::TEST64rr,        X86::TEST64rm, 0 },
-    { X86::TEST8rr,         X86::TEST8rm, 0 },
+    { X86::CMP16rr,         X86::CMP16rm,             0 },
+    { X86::CMP32rr,         X86::CMP32rm,             0 },
+    { X86::CMP64rr,         X86::CMP64rm,             0 },
+    { X86::CMP8rr,          X86::CMP8rm,              0 },
+    { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
+    { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
+    { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
+    { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
+    { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
+    { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
+    { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
+    { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
+    { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
+    { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
+    { X86::FsMOVAPDrr,      X86::MOVSDrm,             TB_NO_REVERSE },
+    { X86::FsMOVAPSrr,      X86::MOVSSrm,             TB_NO_REVERSE },
+    { X86::FsVMOVAPDrr,     X86::VMOVSDrm,            TB_NO_REVERSE },
+    { X86::FsVMOVAPSrr,     X86::VMOVSSrm,            TB_NO_REVERSE },
+    { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
+    { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
+    { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
+    { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
+    { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
+    { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
+    { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
+    { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
+    { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm,      TB_ALIGN_16 },
+    { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm,      TB_ALIGN_16 },
+    { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm,      TB_ALIGN_16 },
+    { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm,      TB_ALIGN_16 },
+    { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm,      TB_ALIGN_16 },
+    { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm,      0 },
+    { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
+    { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
+    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
+    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
+    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
+    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
+    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
+    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
+    { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
+    { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
+    { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
+    { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
+    { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
+    { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
+    { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
+    { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
+    { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
+    { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
+    { X86::MOV16rr,         X86::MOV16rm,             0 },
+    { X86::MOV32rr,         X86::MOV32rm,             0 },
+    { X86::MOV64rr,         X86::MOV64rm,             0 },
+    { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
+    { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
+    { X86::MOV8rr,          X86::MOV8rm,              0 },
+    { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
+    { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
+    { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
+    { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
+    { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
+    { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
+    { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
+    { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
+    { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_16 },
+    { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
+    { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
+    { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
+    { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
+    { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
+    { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
+    { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
+    { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
+    { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
+    { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
+    { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
+    { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
+    { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm,        0 },
+    { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
+    { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
+    { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
+    { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
+    { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
+    { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
+    { X86::MOVZX64rr16,     X86::MOVZX64rm16,         0 },
+    { X86::MOVZX64rr32,     X86::MOVZX64rm32,         0 },
+    { X86::MOVZX64rr8,      X86::MOVZX64rm8,          0 },
+    { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
+    { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
+    { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
+    { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
+    { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
+    { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
+    { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
+    { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
+    { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
+    { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
+    { X86::SQRTPDr_Int,     X86::SQRTPDm_Int,         TB_ALIGN_16 },
+    { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
+    { X86::SQRTPSr_Int,     X86::SQRTPSm_Int,         TB_ALIGN_16 },
+    { X86::SQRTSDr,         X86::SQRTSDm,             0 },
+    { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
+    { X86::SQRTSSr,         X86::SQRTSSm,             0 },
+    { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
+    { X86::TEST16rr,        X86::TEST16rm,            0 },
+    { X86::TEST32rr,        X86::TEST32rm,            0 },
+    { X86::TEST64rr,        X86::TEST64rm,            0 },
+    { X86::TEST8rr,         X86::TEST8rm,             0 },
     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
-    { X86::UCOMISDrr,       X86::UCOMISDrm, 0 },
-    { X86::UCOMISSrr,       X86::UCOMISSrm, 0 },
-    { X86::VUCOMISDrr,      X86::VUCOMISDrm, 0 },
-    { X86::VUCOMISSrr,      X86::VUCOMISSrm, 0 }
+    { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
+    { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
+    { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
+    { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 }
   };
 
   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
     unsigned RegOp = OpTbl1[i][0];
-    unsigned MemOp = OpTbl1[i][1] & ~TB_FLAGS;
-    unsigned Align = OpTbl1[i][2];
-    assert(!RegOp2MemOpTable1.count(RegOp) && "Duplicate entries");
-    RegOp2MemOpTable1[RegOp] = std::make_pair(MemOp, Align);
-
-    // If this is not a reversible operation (because there is a many->one)
-    // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
-    if (OpTbl1[i][1] & TB_NOT_REVERSABLE)
-      continue;
-
-    // Index 1, folded load
-    unsigned AuxInfo = 1 | (1 << 4);
-    assert(!MemOp2RegOpTable.count(MemOp) && "Duplicate entries");
-    MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
+    unsigned MemOp = OpTbl1[i][1];
+    unsigned Flags = OpTbl1[i][2];
+    AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
+                  RegOp, MemOp,
+                  // Index 1, folded load
+                  Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
   }
 
   static const unsigned OpTbl2[][3] = {
-    { X86::ADC32rr,         X86::ADC32rm, 0 },
-    { X86::ADC64rr,         X86::ADC64rm, 0 },
-    { X86::ADD16rr,         X86::ADD16rm, 0 },
-    { X86::ADD16rr_DB,      X86::ADD16rm | TB_NOT_REVERSABLE, 0 },
-    { X86::ADD32rr,         X86::ADD32rm, 0 },
-    { X86::ADD32rr_DB,      X86::ADD32rm | TB_NOT_REVERSABLE, 0 },
-    { X86::ADD64rr,         X86::ADD64rm, 0 },
-    { X86::ADD64rr_DB,      X86::ADD64rm | TB_NOT_REVERSABLE, 0 },
-    { X86::ADD8rr,          X86::ADD8rm, 0 },
-    { X86::ADDPDrr,         X86::ADDPDrm, 16 },
-    { X86::ADDPSrr,         X86::ADDPSrm, 16 },
-    { X86::ADDSDrr,         X86::ADDSDrm, 0 },
-    { X86::ADDSSrr,         X86::ADDSSrm, 0 },
-    { X86::ADDSUBPDrr,      X86::ADDSUBPDrm, 16 },
-    { X86::ADDSUBPSrr,      X86::ADDSUBPSrm, 16 },
-    { X86::AND16rr,         X86::AND16rm, 0 },
-    { X86::AND32rr,         X86::AND32rm, 0 },
-    { X86::AND64rr,         X86::AND64rm, 0 },
-    { X86::AND8rr,          X86::AND8rm, 0 },
-    { X86::ANDNPDrr,        X86::ANDNPDrm, 16 },
-    { X86::ANDNPSrr,        X86::ANDNPSrm, 16 },
-    { X86::ANDPDrr,         X86::ANDPDrm, 16 },
-    { X86::ANDPSrr,         X86::ANDPSrm, 16 },
-    { X86::CMOVA16rr,       X86::CMOVA16rm, 0 },
-    { X86::CMOVA32rr,       X86::CMOVA32rm, 0 },
-    { X86::CMOVA64rr,       X86::CMOVA64rm, 0 },
-    { X86::CMOVAE16rr,      X86::CMOVAE16rm, 0 },
-    { X86::CMOVAE32rr,      X86::CMOVAE32rm, 0 },
-    { X86::CMOVAE64rr,      X86::CMOVAE64rm, 0 },
-    { X86::CMOVB16rr,       X86::CMOVB16rm, 0 },
-    { X86::CMOVB32rr,       X86::CMOVB32rm, 0 },
-    { X86::CMOVB64rr,       X86::CMOVB64rm, 0 },
-    { X86::CMOVBE16rr,      X86::CMOVBE16rm, 0 },
-    { X86::CMOVBE32rr,      X86::CMOVBE32rm, 0 },
-    { X86::CMOVBE64rr,      X86::CMOVBE64rm, 0 },
-    { X86::CMOVE16rr,       X86::CMOVE16rm, 0 },
-    { X86::CMOVE32rr,       X86::CMOVE32rm, 0 },
-    { X86::CMOVE64rr,       X86::CMOVE64rm, 0 },
-    { X86::CMOVG16rr,       X86::CMOVG16rm, 0 },
-    { X86::CMOVG32rr,       X86::CMOVG32rm, 0 },
-    { X86::CMOVG64rr,       X86::CMOVG64rm, 0 },
-    { X86::CMOVGE16rr,      X86::CMOVGE16rm, 0 },
-    { X86::CMOVGE32rr,      X86::CMOVGE32rm, 0 },
-    { X86::CMOVGE64rr,      X86::CMOVGE64rm, 0 },
-    { X86::CMOVL16rr,       X86::CMOVL16rm, 0 },
-    { X86::CMOVL32rr,       X86::CMOVL32rm, 0 },
-    { X86::CMOVL64rr,       X86::CMOVL64rm, 0 },
-    { X86::CMOVLE16rr,      X86::CMOVLE16rm, 0 },
-    { X86::CMOVLE32rr,      X86::CMOVLE32rm, 0 },
-    { X86::CMOVLE64rr,      X86::CMOVLE64rm, 0 },
-    { X86::CMOVNE16rr,      X86::CMOVNE16rm, 0 },
-    { X86::CMOVNE32rr,      X86::CMOVNE32rm, 0 },
-    { X86::CMOVNE64rr,      X86::CMOVNE64rm, 0 },
-    { X86::CMOVNO16rr,      X86::CMOVNO16rm, 0 },
-    { X86::CMOVNO32rr,      X86::CMOVNO32rm, 0 },
-    { X86::CMOVNO64rr,      X86::CMOVNO64rm, 0 },
-    { X86::CMOVNP16rr,      X86::CMOVNP16rm, 0 },
-    { X86::CMOVNP32rr,      X86::CMOVNP32rm, 0 },
-    { X86::CMOVNP64rr,      X86::CMOVNP64rm, 0 },
-    { X86::CMOVNS16rr,      X86::CMOVNS16rm, 0 },
-    { X86::CMOVNS32rr,      X86::CMOVNS32rm, 0 },
-    { X86::CMOVNS64rr,      X86::CMOVNS64rm, 0 },
-    { X86::CMOVO16rr,       X86::CMOVO16rm, 0 },
-    { X86::CMOVO32rr,       X86::CMOVO32rm, 0 },
-    { X86::CMOVO64rr,       X86::CMOVO64rm, 0 },
-    { X86::CMOVP16rr,       X86::CMOVP16rm, 0 },
-    { X86::CMOVP32rr,       X86::CMOVP32rm, 0 },
-    { X86::CMOVP64rr,       X86::CMOVP64rm, 0 },
-    { X86::CMOVS16rr,       X86::CMOVS16rm, 0 },
-    { X86::CMOVS32rr,       X86::CMOVS32rm, 0 },
-    { X86::CMOVS64rr,       X86::CMOVS64rm, 0 },
-    { X86::CMPPDrri,        X86::CMPPDrmi, 16 },
-    { X86::CMPPSrri,        X86::CMPPSrmi, 16 },
-    { X86::CMPSDrr,         X86::CMPSDrm, 0 },
-    { X86::CMPSSrr,         X86::CMPSSrm, 0 },
-    { X86::DIVPDrr,         X86::DIVPDrm, 16 },
-    { X86::DIVPSrr,         X86::DIVPSrm, 16 },
-    { X86::DIVSDrr,         X86::DIVSDrm, 0 },
-    { X86::DIVSSrr,         X86::DIVSSrm, 0 },
-    { X86::FsANDNPDrr,      X86::FsANDNPDrm, 16 },
-    { X86::FsANDNPSrr,      X86::FsANDNPSrm, 16 },
-    { X86::FsANDPDrr,       X86::FsANDPDrm, 16 },
-    { X86::FsANDPSrr,       X86::FsANDPSrm, 16 },
-    { X86::FsORPDrr,        X86::FsORPDrm, 16 },
-    { X86::FsORPSrr,        X86::FsORPSrm, 16 },
-    { X86::FsXORPDrr,       X86::FsXORPDrm, 16 },
-    { X86::FsXORPSrr,       X86::FsXORPSrm, 16 },
-    { X86::HADDPDrr,        X86::HADDPDrm, 16 },
-    { X86::HADDPSrr,        X86::HADDPSrm, 16 },
-    { X86::HSUBPDrr,        X86::HSUBPDrm, 16 },
-    { X86::HSUBPSrr,        X86::HSUBPSrm, 16 },
-    { X86::IMUL16rr,        X86::IMUL16rm, 0 },
-    { X86::IMUL32rr,        X86::IMUL32rm, 0 },
-    { X86::IMUL64rr,        X86::IMUL64rm, 0 },
-    { X86::Int_CMPSDrr,     X86::Int_CMPSDrm, 0 },
-    { X86::Int_CMPSSrr,     X86::Int_CMPSSrm, 0 },
-    { X86::MAXPDrr,         X86::MAXPDrm, 16 },
-    { X86::MAXPDrr_Int,     X86::MAXPDrm_Int, 16 },
-    { X86::MAXPSrr,         X86::MAXPSrm, 16 },
-    { X86::MAXPSrr_Int,     X86::MAXPSrm_Int, 16 },
-    { X86::MAXSDrr,         X86::MAXSDrm, 0 },
-    { X86::MAXSDrr_Int,     X86::MAXSDrm_Int, 0 },
-    { X86::MAXSSrr,         X86::MAXSSrm, 0 },
-    { X86::MAXSSrr_Int,     X86::MAXSSrm_Int, 0 },
-    { X86::MINPDrr,         X86::MINPDrm, 16 },
-    { X86::MINPDrr_Int,     X86::MINPDrm_Int, 16 },
-    { X86::MINPSrr,         X86::MINPSrm, 16 },
-    { X86::MINPSrr_Int,     X86::MINPSrm_Int, 16 },
-    { X86::MINSDrr,         X86::MINSDrm, 0 },
-    { X86::MINSDrr_Int,     X86::MINSDrm_Int, 0 },
-    { X86::MINSSrr,         X86::MINSSrm, 0 },
-    { X86::MINSSrr_Int,     X86::MINSSrm_Int, 0 },
-    { X86::MULPDrr,         X86::MULPDrm, 16 },
-    { X86::MULPSrr,         X86::MULPSrm, 16 },
-    { X86::MULSDrr,         X86::MULSDrm, 0 },
-    { X86::MULSSrr,         X86::MULSSrm, 0 },
-    { X86::OR16rr,          X86::OR16rm, 0 },
-    { X86::OR32rr,          X86::OR32rm, 0 },
-    { X86::OR64rr,          X86::OR64rm, 0 },
-    { X86::OR8rr,           X86::OR8rm, 0 },
-    { X86::ORPDrr,          X86::ORPDrm, 16 },
-    { X86::ORPSrr,          X86::ORPSrm, 16 },
-    { X86::PACKSSDWrr,      X86::PACKSSDWrm, 16 },
-    { X86::PACKSSWBrr,      X86::PACKSSWBrm, 16 },
-    { X86::PACKUSWBrr,      X86::PACKUSWBrm, 16 },
-    { X86::PADDBrr,         X86::PADDBrm, 16 },
-    { X86::PADDDrr,         X86::PADDDrm, 16 },
-    { X86::PADDQrr,         X86::PADDQrm, 16 },
-    { X86::PADDSBrr,        X86::PADDSBrm, 16 },
-    { X86::PADDSWrr,        X86::PADDSWrm, 16 },
-    { X86::PADDWrr,         X86::PADDWrm, 16 },
-    { X86::PANDNrr,         X86::PANDNrm, 16 },
-    { X86::PANDrr,          X86::PANDrm, 16 },
-    { X86::PAVGBrr,         X86::PAVGBrm, 16 },
-    { X86::PAVGWrr,         X86::PAVGWrm, 16 },
-    { X86::PCMPEQBrr,       X86::PCMPEQBrm, 16 },
-    { X86::PCMPEQDrr,       X86::PCMPEQDrm, 16 },
-    { X86::PCMPEQWrr,       X86::PCMPEQWrm, 16 },
-    { X86::PCMPGTBrr,       X86::PCMPGTBrm, 16 },
-    { X86::PCMPGTDrr,       X86::PCMPGTDrm, 16 },
-    { X86::PCMPGTWrr,       X86::PCMPGTWrm, 16 },
-    { X86::PINSRWrri,       X86::PINSRWrmi, 16 },
-    { X86::PMADDWDrr,       X86::PMADDWDrm, 16 },
-    { X86::PMAXSWrr,        X86::PMAXSWrm, 16 },
-    { X86::PMAXUBrr,        X86::PMAXUBrm, 16 },
-    { X86::PMINSWrr,        X86::PMINSWrm, 16 },
-    { X86::PMINUBrr,        X86::PMINUBrm, 16 },
-    { X86::PMULDQrr,        X86::PMULDQrm, 16 },
-    { X86::PMULHUWrr,       X86::PMULHUWrm, 16 },
-    { X86::PMULHWrr,        X86::PMULHWrm, 16 },
-    { X86::PMULLDrr,        X86::PMULLDrm, 16 },
-    { X86::PMULLWrr,        X86::PMULLWrm, 16 },
-    { X86::PMULUDQrr,       X86::PMULUDQrm, 16 },
-    { X86::PORrr,           X86::PORrm, 16 },
-    { X86::PSADBWrr,        X86::PSADBWrm, 16 },
-    { X86::PSLLDrr,         X86::PSLLDrm, 16 },
-    { X86::PSLLQrr,         X86::PSLLQrm, 16 },
-    { X86::PSLLWrr,         X86::PSLLWrm, 16 },
-    { X86::PSRADrr,         X86::PSRADrm, 16 },
-    { X86::PSRAWrr,         X86::PSRAWrm, 16 },
-    { X86::PSRLDrr,         X86::PSRLDrm, 16 },
-    { X86::PSRLQrr,         X86::PSRLQrm, 16 },
-    { X86::PSRLWrr,         X86::PSRLWrm, 16 },
-    { X86::PSUBBrr,         X86::PSUBBrm, 16 },
-    { X86::PSUBDrr,         X86::PSUBDrm, 16 },
-    { X86::PSUBSBrr,        X86::PSUBSBrm, 16 },
-    { X86::PSUBSWrr,        X86::PSUBSWrm, 16 },
-    { X86::PSUBWrr,         X86::PSUBWrm, 16 },
-    { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm, 16 },
-    { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm, 16 },
-    { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm, 16 },
-    { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm, 16 },
-    { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm, 16 },
-    { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm, 16 },
-    { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm, 16 },
-    { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm, 16 },
-    { X86::PXORrr,          X86::PXORrm, 16 },
-    { X86::SBB32rr,         X86::SBB32rm, 0 },
-    { X86::SBB64rr,         X86::SBB64rm, 0 },
-    { X86::SHUFPDrri,       X86::SHUFPDrmi, 16 },
-    { X86::SHUFPSrri,       X86::SHUFPSrmi, 16 },
-    { X86::SUB16rr,         X86::SUB16rm, 0 },
-    { X86::SUB32rr,         X86::SUB32rm, 0 },
-    { X86::SUB64rr,         X86::SUB64rm, 0 },
-    { X86::SUB8rr,          X86::SUB8rm, 0 },
-    { X86::SUBPDrr,         X86::SUBPDrm, 16 },
-    { X86::SUBPSrr,         X86::SUBPSrm, 16 },
-    { X86::SUBSDrr,         X86::SUBSDrm, 0 },
-    { X86::SUBSSrr,         X86::SUBSSrm, 0 },
+    { X86::ADC32rr,         X86::ADC32rm,       0 },
+    { X86::ADC64rr,         X86::ADC64rm,       0 },
+    { X86::ADD16rr,         X86::ADD16rm,       0 },
+    { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
+    { X86::ADD32rr,         X86::ADD32rm,       0 },
+    { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
+    { X86::ADD64rr,         X86::ADD64rm,       0 },
+    { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
+    { X86::ADD8rr,          X86::ADD8rm,        0 },
+    { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
+    { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
+    { X86::ADDSDrr,         X86::ADDSDrm,       0 },
+    { X86::ADDSSrr,         X86::ADDSSrm,       0 },
+    { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
+    { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
+    { X86::AND16rr,         X86::AND16rm,       0 },
+    { X86::AND32rr,         X86::AND32rm,       0 },
+    { X86::AND64rr,         X86::AND64rm,       0 },
+    { X86::AND8rr,          X86::AND8rm,        0 },
+    { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
+    { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
+    { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
+    { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
+    { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
+    { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
+    { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
+    { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
+    { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
+    { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
+    { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
+    { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
+    { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
+    { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
+    { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
+    { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
+    { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
+    { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
+    { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
+    { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
+    { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
+    { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
+    { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
+    { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
+    { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
+    { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
+    { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
+    { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
+    { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
+    { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
+    { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
+    { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
+    { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
+    { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
+    { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
+    { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
+    { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
+    { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
+    { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
+    { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
+    { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
+    { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
+    { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
+    { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
+    { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
+    { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
+    { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
+    { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
+    { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
+    { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
+    { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
+    { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
+    { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
+    { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
+    { X86::CMPSDrr,         X86::CMPSDrm,       0 },
+    { X86::CMPSSrr,         X86::CMPSSrm,       0 },
+    { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
+    { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
+    { X86::DIVSDrr,         X86::DIVSDrm,       0 },
+    { X86::DIVSSrr,         X86::DIVSSrm,       0 },
+    { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
+    { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
+    { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
+    { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
+    { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
+    { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
+    { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
+    { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
+    { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
+    { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
+    { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
+    { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
+    { X86::IMUL16rr,        X86::IMUL16rm,      0 },
+    { X86::IMUL32rr,        X86::IMUL32rm,      0 },
+    { X86::IMUL64rr,        X86::IMUL64rm,      0 },
+    { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
+    { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
+    { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
+    { X86::MAXPDrr_Int,     X86::MAXPDrm_Int,   TB_ALIGN_16 },
+    { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
+    { X86::MAXPSrr_Int,     X86::MAXPSrm_Int,   TB_ALIGN_16 },
+    { X86::MAXSDrr,         X86::MAXSDrm,       0 },
+    { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
+    { X86::MAXSSrr,         X86::MAXSSrm,       0 },
+    { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
+    { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
+    { X86::MINPDrr_Int,     X86::MINPDrm_Int,   TB_ALIGN_16 },
+    { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
+    { X86::MINPSrr_Int,     X86::MINPSrm_Int,   TB_ALIGN_16 },
+    { X86::MINSDrr,         X86::MINSDrm,       0 },
+    { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
+    { X86::MINSSrr,         X86::MINSSrm,       0 },
+    { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
+    { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
+    { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
+    { X86::MULSDrr,         X86::MULSDrm,       0 },
+    { X86::MULSSrr,         X86::MULSSrm,       0 },
+    { X86::OR16rr,          X86::OR16rm,        0 },
+    { X86::OR32rr,          X86::OR32rm,        0 },
+    { X86::OR64rr,          X86::OR64rm,        0 },
+    { X86::OR8rr,           X86::OR8rm,         0 },
+    { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
+    { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
+    { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
+    { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
+    { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
+    { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
+    { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
+    { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
+    { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
+    { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
+    { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
+    { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
+    { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
+    { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
+    { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
+    { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
+    { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
+    { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
+    { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
+    { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
+    { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
+    { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
+    { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
+    { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
+    { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
+    { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
+    { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
+    { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
+    { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
+    { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
+    { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
+    { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
+    { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
+    { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
+    { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
+    { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
+    { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
+    { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
+    { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
+    { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
+    { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
+    { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
+    { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
+    { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
+    { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
+    { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
+    { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
+    { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
+    { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
+    { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
+    { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
+    { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
+    { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
+    { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
+    { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
+    { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
+    { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
+    { X86::SBB32rr,         X86::SBB32rm,       0 },
+    { X86::SBB64rr,         X86::SBB64rm,       0 },
+    { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
+    { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
+    { X86::SUB16rr,         X86::SUB16rm,       0 },
+    { X86::SUB32rr,         X86::SUB32rm,       0 },
+    { X86::SUB64rr,         X86::SUB64rm,       0 },
+    { X86::SUB8rr,          X86::SUB8rm,        0 },
+    { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
+    { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
+    { X86::SUBSDrr,         X86::SUBSDrm,       0 },
+    { X86::SUBSSrr,         X86::SUBSSrm,       0 },
     // FIXME: TEST*rr -> swapped operand of TEST*mr.
-    { X86::UNPCKHPDrr,      X86::UNPCKHPDrm, 16 },
-    { X86::UNPCKHPSrr,      X86::UNPCKHPSrm, 16 },
-    { X86::UNPCKLPDrr,      X86::UNPCKLPDrm, 16 },
-    { X86::UNPCKLPSrr,      X86::UNPCKLPSrm, 16 },
-    { X86::XOR16rr,         X86::XOR16rm, 0 },
-    { X86::XOR32rr,         X86::XOR32rm, 0 },
-    { X86::XOR64rr,         X86::XOR64rm, 0 },
-    { X86::XOR8rr,          X86::XOR8rm, 0 },
-    { X86::XORPDrr,         X86::XORPDrm, 16 },
-    { X86::XORPSrr,         X86::XORPSrm, 16 }
+    { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
+    { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
+    { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
+    { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
+    { X86::XOR16rr,         X86::XOR16rm,       0 },
+    { X86::XOR32rr,         X86::XOR32rm,       0 },
+    { X86::XOR64rr,         X86::XOR64rm,       0 },
+    { X86::XOR8rr,          X86::XOR8rm,        0 },
+    { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
+    { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 }
   };
 
   for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
     unsigned RegOp = OpTbl2[i][0];
-    unsigned MemOp = OpTbl2[i][1] & ~TB_FLAGS;
-    unsigned Align = OpTbl2[i][2];
-
-    assert(!RegOp2MemOpTable2.count(RegOp) && "Duplicate entry!");
-    RegOp2MemOpTable2[RegOp] = std::make_pair(MemOp, Align);
-
-    // If this is not a reversible operation (because there is a many->one)
-    // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
-    if (OpTbl2[i][1] & TB_NOT_REVERSABLE)
-      continue;
+    unsigned MemOp = OpTbl2[i][1];
+    unsigned Flags = OpTbl2[i][2];
+    AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
+                  RegOp, MemOp,
+                  // Index 2, folded load
+                  Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
+  }
+}
 
-    // Index 2, folded load
-    unsigned AuxInfo = 2 | (1 << 4);
-    assert(!MemOp2RegOpTable.count(MemOp) &&
+void
+X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
+                            MemOp2RegOpTableType &M2RTable,
+                            unsigned RegOp, unsigned MemOp, unsigned Flags) {
+    if ((Flags & TB_NO_FORWARD) == 0) {
+      assert(!R2MTable.count(RegOp) && "Duplicate entry!");
+      R2MTable[RegOp] = std::make_pair(MemOp, Flags);
+    }
+    if ((Flags & TB_NO_REVERSE) == 0) {
+      assert(!M2RTable.count(MemOp) &&
            "Duplicated entries in unfolding maps?");
-    MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
-  }
+      M2RTable[MemOp] = std::make_pair(RegOp, Flags);
+    }
 }
 
 bool
@@ -2286,7 +2288,7 @@
       OpcodeTablePtr->find(MI->getOpcode());
     if (I != OpcodeTablePtr->end()) {
       unsigned Opcode = I->second.first;
-      unsigned MinAlign = I->second.second;
+      unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
       if (Align < MinAlign)
         return NULL;
       bool NarrowToMOV32rm = false;
@@ -2601,9 +2603,9 @@
   if (I == MemOp2RegOpTable.end())
     return false;
   unsigned Opc = I->second.first;
-  unsigned Index = I->second.second & 0xf;
-  bool FoldedLoad = I->second.second & (1 << 4);
-  bool FoldedStore = I->second.second & (1 << 5);
+  unsigned Index = I->second.second & TB_INDEX_MASK;
+  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
+  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
   if (UnfoldLoad && !FoldedLoad)
     return false;
   UnfoldLoad &= FoldedLoad;
@@ -2729,9 +2731,9 @@
   if (I == MemOp2RegOpTable.end())
     return false;
   unsigned Opc = I->second.first;
-  unsigned Index = I->second.second & 0xf;
-  bool FoldedLoad = I->second.second & (1 << 4);
-  bool FoldedStore = I->second.second & (1 << 5);
+  unsigned Index = I->second.second & TB_INDEX_MASK;
+  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
+  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
   const MCInstrDesc &MCID = get(Opc);
   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
   unsigned NumDefs = MCID.NumDefs;
@@ -2829,14 +2831,14 @@
     MemOp2RegOpTable.find(Opc);
   if (I == MemOp2RegOpTable.end())
     return 0;
-  bool FoldedLoad = I->second.second & (1 << 4);
-  bool FoldedStore = I->second.second & (1 << 5);
+  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
+  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
   if (UnfoldLoad && !FoldedLoad)
     return 0;
   if (UnfoldStore && !FoldedStore)
     return 0;
   if (LoadRegIndex)
-    *LoadRegIndex = I->second.second & 0xf;
+    *LoadRegIndex = I->second.second & TB_INDEX_MASK;
   return I->second.first;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=139311&r1=139310&r2=139311&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Thu Sep  8 13:35:57 2011
@@ -131,14 +131,22 @@
   /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
   /// RegOp2MemOpTable2 - Load / store folding opcode maps.
   ///
-  DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr;
-  DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable0;
-  DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable1;
-  DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable2;
+  typedef DenseMap<unsigned,
+                   std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
+  RegOp2MemOpTableType RegOp2MemOpTable2Addr;
+  RegOp2MemOpTableType RegOp2MemOpTable0;
+  RegOp2MemOpTableType RegOp2MemOpTable1;
+  RegOp2MemOpTableType RegOp2MemOpTable2;
 
   /// MemOp2RegOpTable - Load / store unfolding opcode map.
   ///
-  DenseMap<unsigned, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
+  typedef DenseMap<unsigned,
+                   std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
+  MemOp2RegOpTableType MemOp2RegOpTable;
+
+  void AddTableEntry(RegOp2MemOpTableType &R2MTable,
+                     MemOp2RegOpTableType &M2RTable,
+                     unsigned RegOp, unsigned MemOp, unsigned Flags);
 
 public:
   explicit X86InstrInfo(X86TargetMachine &tm);



From bruno.cardoso at gmail.com  Thu Sep  8 13:37:40 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 8 Sep 2011 11:37:40 -0700
Subject: [llvm-commits] [PATCH] Clean up RegOp2MemOp tables in
	X86InstrInfo.cpp
In-Reply-To: <CAAU48J+co5fzoD7ftCn0bKs7eDDu4CxXBK3CUw6Q-1KUXOXAQg@mail.gmail.com>
References: <CAAU48JKT3LE1gCzvWtv5Me4AsQLTbGa+boxFyZsjuKOP+8BanQ@mail.gmail.com>
	<6CF9FE3C-ABC0-4BB8-89A8-A27A45803A7A@2pi.dk>
	<CAAU48JJ-55X_sfnhvB1uudKbTPdhvue9P4jVL5B2meojxL9Y_g@mail.gmail.com>
	<CAAU48J+3G3Kps_N87nLq-oZghp9fJuoZ9aWvN+8bW7+0sRzfpQ@mail.gmail.com>
	<BAB05FBC-F778-46B1-8724-45C7B088EF4F@2pi.dk>
	<CAAU48J+co5fzoD7ftCn0bKs7eDDu4CxXBK3CUw6Q-1KUXOXAQg@mail.gmail.com>
Message-ID: <CACk9FxYCs6NROs6cv029sRL=Eh1TCd4C_4hTuk0gh5HeJ3Ha6Q@mail.gmail.com>

On Thu, Sep 8, 2011 at 10:52 AM, David Meyer <pdox at google.com> wrote:
> Anybody else?

Committed r139311

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc

From rjmccall at apple.com  Thu Sep  8 14:22:29 2011
From: rjmccall at apple.com (John McCall)
Date: Thu, 08 Sep 2011 12:22:29 -0700
Subject: [llvm-commits] [llvm] r139236 - in /llvm/trunk:
 include/llvm/Intrinsics.td test/Transforms/GVN/2011-09-07-TypeIdFor.ll
In-Reply-To: <20110907164414.B60312A6C12C@llvm.org>
References: <20110907164414.B60312A6C12C@llvm.org>
Message-ID: <B8C75AE9-9387-4E4F-B0F0-AF3B8577631F@apple.com>

On Sep 7, 2011, at 9:44 AM, Duncan Sands wrote:
> Author: baldrick
> Date: Wed Sep  7 11:44:14 2011
> New Revision: 139236
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=139236&view=rev
> Log:
> When inlining exception handling code into another function, ensure that
> duplicate tests are eliminated (for example if the two functions both have
> a catch clause catching the same type, ensure the redundant one is removed).
> Note that it would probably be safe to say that eh.typeid.for is 'const',
> but since two calls to it with the same argument can give different results
> (but only if the calls are in different functions), it seems more correct to
> mark it only 'pure'; this doesn't get in the way of the optimization.

It could if there were an intervening cleanup.  I see no reason not to mark it 'const'.

John.

From dmalyshev at accesssoftek.com  Thu Sep  8 15:00:21 2011
From: dmalyshev at accesssoftek.com (Danil Malyshev)
Date: Thu, 8 Sep 2011 13:00:21 -0700
Subject: [llvm-commits] ObjectFile RelocationRef
In-Reply-To: <CAL3drCokdsAmrfj8RN4u7z0=PReOESCz6fR-5nB51L3YFPtH=g@mail.gmail.com>
References: <AcxtX1CyMEhmaMQgR0awFXVqoa29vg==>
	<6AE1604EE3EC5F4296C096518C6B77EE17F9B4DBFE@mail.accesssoftek.com>
	<CAL3drCokdsAmrfj8RN4u7z0=PReOESCz6fR-5nB51L3YFPtH=g@mail.gmail.com>
Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE17F9B4DCFB@mail.accesssoftek.com>

Hi everyone,

> Can you make the macros (ELF_REL_GET_VALUE etc.) static functions?
> Macros with side effects like that one make the code much harder to 
> follow. Looks good otherwise.

I removed all macroses. Changed patch is attached.


Regards,
Danil
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From krasin at google.com  Thu Sep  8 15:49:31 2011
From: krasin at google.com (Ivan Krasin)
Date: Thu, 8 Sep 2011 13:49:31 -0700
Subject: [llvm-commits] gold plugin: report errors occured in
	lto_module_create_from_*
In-Reply-To: <CAOei5RdN2tE5mb_fxUqRG+7o1dSWKnnh7KWuR2i8YgqDCH1cEg@mail.gmail.com>
References: <CAOei5RdN2tE5mb_fxUqRG+7o1dSWKnnh7KWuR2i8YgqDCH1cEg@mail.gmail.com>
Message-ID: <CAOei5ReXr_vdqrupC=AvGfrpO+hG_TL+gz+J5T1T0gbu3cS4yw@mail.gmail.com>

Friendly ping

On Thu, Sep 8, 2011 at 12:50 AM, Ivan Krasin <krasin at chromium.org> wrote:
> Hi llvm team!
>
> It appears that gold plugin does not check for errors occured in
> lto_module_create_from_*. It just silently returns with LDPS_OK
> status.
> This patch makes it to report occurred errors (if any).
>
> Is it fine to commit?
>
> krasin
>

From benny.kra at googlemail.com  Thu Sep  8 15:52:17 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 08 Sep 2011 20:52:17 -0000
Subject: [llvm-commits] [llvm] r139314 - in /llvm/trunk:
 include/llvm/Object/COFF.h include/llvm/Object/ObjectFile.h
 lib/Object/COFFObjectFile.cpp lib/Object/ELFObjectFile.cpp
 lib/Object/MachOObjectFile.cpp
Message-ID: <20110908205217.935612A6C12C@llvm.org>

Author: d0k
Date: Thu Sep  8 15:52:17 2011
New Revision: 139314

URL: http://llvm.org/viewvc/llvm-project?rev=139314&view=rev
Log:
Add support for relocations to ObjectFile.

Patch by Danil Malyshev!

Modified:
    llvm/trunk/include/llvm/Object/COFF.h
    llvm/trunk/include/llvm/Object/ObjectFile.h
    llvm/trunk/lib/Object/COFFObjectFile.cpp
    llvm/trunk/lib/Object/ELFObjectFile.cpp
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/include/llvm/Object/COFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=139314&r1=139313&r2=139314&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/COFF.h (original)
+++ llvm/trunk/include/llvm/Object/COFF.h Thu Sep  8 15:52:17 2011
@@ -67,6 +67,12 @@
   support::ulittle32_t Characteristics;
 };
 
+struct coff_relocation {
+  support::ulittle32_t VirtualAddress;
+  support::ulittle32_t SymbolTableIndex;
+  support::ulittle16_t Type;
+};
+
 class COFFObjectFile : public ObjectFile {
 private:
   const coff_file_header *Header;
@@ -81,6 +87,7 @@
 
   const coff_symbol      *toSymb(DataRefImpl Symb) const;
   const coff_section     *toSec(DataRefImpl Sec) const;
+  const coff_relocation  *toRel(DataRefImpl Rel) const;
 
 protected:
   virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
@@ -99,12 +106,24 @@
   virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Symb,
                                            bool &Result) const;
 
+  virtual error_code getRelocationNext(DataRefImpl Rel,
+                                       RelocationRef &Res) const;
+  virtual error_code getRelocationAddress(DataRefImpl Rel,
+                                          uint64_t &Res) const;
+  virtual error_code getRelocationSymbol(DataRefImpl Rel,
+                                         SymbolRef &Res) const;
+  virtual error_code getRelocationType(DataRefImpl Rel,
+                                       uint32_t &Res) const;
+  virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
+                                                 int64_t &Res) const;
 public:
   COFFObjectFile(MemoryBuffer *Object, error_code &ec);
   virtual symbol_iterator begin_symbols() const;
   virtual symbol_iterator end_symbols() const;
   virtual section_iterator begin_sections() const;
   virtual section_iterator end_sections() const;
+  virtual relocation_iterator begin_relocations() const;
+  virtual relocation_iterator end_relocations() const;
 
   virtual uint8_t getBytesInAddress() const;
   virtual StringRef getFileFormatName() const;

Modified: llvm/trunk/include/llvm/Object/ObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=139314&r1=139313&r2=139314&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/ObjectFile.h (original)
+++ llvm/trunk/include/llvm/Object/ObjectFile.h Thu Sep  8 15:52:17 2011
@@ -39,22 +39,6 @@
   return std::memcmp(&a, &b, sizeof(DataRefImpl)) == 0;
 }
 
-class RelocationRef {
-  DataRefImpl RelocationPimpl;
-  const ObjectFile *OwningObject;
-
-public:
-  RelocationRef() : OwningObject(NULL) {
-    std::memset(&RelocationPimpl, 0, sizeof(RelocationPimpl));
-  }
-
-  RelocationRef(DataRefImpl RelocationP, const ObjectFile *Owner);
-
-  bool operator==(const RelocationRef &Other) const;
-
-  error_code getNext(RelocationRef &Result);
-};
-
 /// SymbolRef - This is a value type class that represents a single symbol in
 /// the list of symbols in the object file.
 class SymbolRef {
@@ -86,6 +70,29 @@
   error_code isInternal(bool &Result) const;
 };
 
+/// RelocationRef - This is a value type class that represents a single
+/// relocation in the list of relocations in the object file.
+class RelocationRef {
+  DataRefImpl RelocationPimpl;
+  const ObjectFile *OwningObject;
+
+public:
+  RelocationRef() : OwningObject(NULL) {
+    std::memset(&RelocationPimpl, 0, sizeof(RelocationPimpl));
+  }
+
+  RelocationRef(DataRefImpl RelocationP, const ObjectFile *Owner);
+
+  bool operator==(const RelocationRef &Other) const;
+
+  error_code getNext(RelocationRef &Result) const;
+
+  error_code getAddress(uint64_t &Result) const;
+  error_code getSymbol(SymbolRef &Result) const;
+  error_code getType(uint32_t &Result) const;
+  error_code getAdditionalInfo(int64_t &Result) const;
+};
+
 /// SectionRef - This is a value type class that represents a single section in
 /// the list of sections in the object file.
 class SectionRef {
@@ -160,6 +167,19 @@
                                            bool &Result) const = 0;
 
 
+  // Same as above for RelocationRef.
+  friend class RelocationRef;
+  virtual error_code getRelocationNext(DataRefImpl Rel,
+                                       RelocationRef &Res) const = 0;
+  virtual error_code getRelocationAddress(DataRefImpl Rel,
+                                          uint64_t &Res) const =0;
+  virtual error_code getRelocationSymbol(DataRefImpl Rel,
+                                         SymbolRef &Res) const = 0;
+  virtual error_code getRelocationType(DataRefImpl Rel,
+                                       uint32_t &Res) const = 0;
+  virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
+                                                 int64_t &Res) const = 0;
+
 public:
   template<class content_type>
   class content_iterator {
@@ -196,6 +216,7 @@
 
   typedef content_iterator<SymbolRef> symbol_iterator;
   typedef content_iterator<SectionRef> section_iterator;
+  typedef content_iterator<RelocationRef> relocation_iterator;
 
   virtual symbol_iterator begin_symbols() const = 0;
   virtual symbol_iterator end_symbols() const = 0;
@@ -203,6 +224,9 @@
   virtual section_iterator begin_sections() const = 0;
   virtual section_iterator end_sections() const = 0;
 
+  virtual relocation_iterator begin_relocations() const = 0;
+  virtual relocation_iterator end_relocations() const = 0;
+
   /// @brief The number of bytes used to represent an address in this object
   ///        file format.
   virtual uint8_t getBytesInAddress() const = 0;
@@ -302,6 +326,37 @@
                                              Result);
 }
 
+
+/// RelocationRef
+inline RelocationRef::RelocationRef(DataRefImpl RelocationP,
+                              const ObjectFile *Owner)
+  : RelocationPimpl(RelocationP)
+  , OwningObject(Owner) {}
+
+inline bool RelocationRef::operator==(const RelocationRef &Other) const {
+  return RelocationPimpl == Other.RelocationPimpl;
+}
+
+inline error_code RelocationRef::getNext(RelocationRef &Result) const {
+  return OwningObject->getRelocationNext(RelocationPimpl, Result);
+}
+
+inline error_code RelocationRef::getAddress(uint64_t &Result) const {
+  return OwningObject->getRelocationAddress(RelocationPimpl, Result);
+}
+
+inline error_code RelocationRef::getSymbol(SymbolRef &Result) const {
+  return OwningObject->getRelocationSymbol(RelocationPimpl, Result);
+}
+
+inline error_code RelocationRef::getType(uint32_t &Result) const {
+  return OwningObject->getRelocationType(RelocationPimpl, Result);
+}
+
+inline error_code RelocationRef::getAdditionalInfo(int64_t &Result) const {
+  return OwningObject->getRelocationAdditionalInfo(RelocationPimpl, Result);
+}
+
 } // end namespace object
 } // end namespace llvm
 

Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=139314&r1=139313&r2=139314&view=diff
==============================================================================
--- llvm/trunk/lib/Object/COFFObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/COFFObjectFile.cpp Thu Sep  8 15:52:17 2011
@@ -327,7 +327,7 @@
   Header = reinterpret_cast<const coff_file_header *>(base() + HeaderStart);
   if (!checkAddr(Data, ec, uintptr_t(Header), sizeof(coff_file_header)))
     return;
-  
+
   SectionTable =
     reinterpret_cast<const coff_section *>( base()
                                           + HeaderStart
@@ -360,7 +360,7 @@
     ec = object_error::parse_failed;
     return;
   }
-  
+
   ec = object_error::success;
 }
 
@@ -445,6 +445,77 @@
   return object_error::success;
 }
 
+const coff_relocation *COFFObjectFile::toRel(DataRefImpl Rel) const {
+  assert(Rel.d.b < Header->NumberOfSections && "Section index out of range!");
+  const coff_section *Sect;
+  getSection(Rel.d.b, Sect);
+  assert(Rel.d.a < Sect->NumberOfRelocations && "Relocation index out of range!");
+  return
+    reinterpret_cast<const coff_relocation*>(base() +
+                                             Sect->PointerToRelocations) +
+                                             Rel.d.a;
+}
+error_code COFFObjectFile::getRelocationNext(DataRefImpl Rel,
+                                             RelocationRef &Res) const {
+  const coff_section *Sect = NULL;
+  if (error_code ec = getSection(Rel.d.b, Sect))
+    return ec;
+  if (++Rel.d.a >= Sect->NumberOfRelocations) {
+    Rel.d.a = 0;
+    while (++Rel.d.b < Header->NumberOfSections) {
+      const coff_section *Sect;
+      getSection(Rel.d.b, Sect);
+      if (Sect->NumberOfRelocations > 0)
+        break;
+    }
+  }
+  Res = RelocationRef(Rel, this);
+  return object_error::success;
+}
+error_code COFFObjectFile::getRelocationAddress(DataRefImpl Rel,
+                                                uint64_t &Res) const {
+  const coff_section *Sect;
+  if (error_code ec = getSection(Rel.d.b, Sect))
+    return ec;
+  const coff_relocation* R = toRel(Rel);
+  Res = reinterpret_cast<uintptr_t>(base() +
+                                    Sect->PointerToRawData +
+                                    R->VirtualAddress);
+  return object_error::success;
+}
+error_code COFFObjectFile::getRelocationSymbol(DataRefImpl Rel,
+                                               SymbolRef &Res) const {
+  const coff_relocation* R = toRel(Rel);
+  DataRefImpl Symb;
+  Symb.p = reinterpret_cast<uintptr_t>(SymbolTable + R->SymbolTableIndex);
+  Res = SymbolRef(Symb, this);
+  return object_error::success;
+}
+error_code COFFObjectFile::getRelocationType(DataRefImpl Rel,
+                                             uint32_t &Res) const {
+  const coff_relocation* R = toRel(Rel);
+  Res = R->Type;
+  return object_error::success;
+}
+error_code COFFObjectFile::getRelocationAdditionalInfo(DataRefImpl Rel,
+                                                       int64_t &Res) const {
+  Res = 0;
+  return object_error::success;
+}
+ObjectFile::relocation_iterator COFFObjectFile::begin_relocations() const {
+  DataRefImpl ret;
+  ret.d.a = 0;
+  ret.d.b = 1;
+  return relocation_iterator(RelocationRef(ret, this));
+}
+ObjectFile::relocation_iterator COFFObjectFile::end_relocations() const {
+  DataRefImpl ret;
+  ret.d.a = 0;
+  ret.d.b = Header->NumberOfSections;
+  return relocation_iterator(RelocationRef(ret, this));
+}
+
+
 namespace llvm {
 
   ObjectFile *ObjectFile::createCOFFObjectFile(MemoryBuffer *Object) {

Modified: llvm/trunk/lib/Object/ELFObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ELFObjectFile.cpp?rev=139314&r1=139313&r2=139314&view=diff
==============================================================================
--- llvm/trunk/lib/Object/ELFObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/ELFObjectFile.cpp Thu Sep  8 15:52:17 2011
@@ -14,6 +14,7 @@
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/Object/ObjectFile.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/Endian.h"
@@ -176,12 +177,89 @@
 }
 
 namespace {
+template<support::endianness target_endianness, bool is64Bits, bool isRela>
+struct Elf_Rel_Base;
+
+template<support::endianness target_endianness>
+struct Elf_Rel_Base<target_endianness, false, false> {
+  LLVM_ELF_IMPORT_TYPES(target_endianness, false)
+  Elf_Addr      r_offset; // Location (file byte offset, or program virtual addr)
+  Elf_Word      r_info;  // Symbol table index and type of relocation to apply
+};
+
+template<support::endianness target_endianness>
+struct Elf_Rel_Base<target_endianness, true, false> {
+  LLVM_ELF_IMPORT_TYPES(target_endianness, true)
+  Elf_Addr      r_offset; // Location (file byte offset, or program virtual addr)
+  Elf_Xword     r_info;   // Symbol table index and type of relocation to apply
+};
+
+template<support::endianness target_endianness>
+struct Elf_Rel_Base<target_endianness, false, true> {
+  LLVM_ELF_IMPORT_TYPES(target_endianness, false)
+  Elf_Addr      r_offset; // Location (file byte offset, or program virtual addr)
+  Elf_Word      r_info;   // Symbol table index and type of relocation to apply
+  Elf_Sword     r_addend; // Compute value for relocatable field by adding this
+};
+
+template<support::endianness target_endianness>
+struct Elf_Rel_Base<target_endianness, true, true> {
+  LLVM_ELF_IMPORT_TYPES(target_endianness, true)
+  Elf_Addr      r_offset; // Location (file byte offset, or program virtual addr)
+  Elf_Xword     r_info;   // Symbol table index and type of relocation to apply
+  Elf_Sxword    r_addend; // Compute value for relocatable field by adding this.
+};
+
+template<support::endianness target_endianness, bool is64Bits, bool isRela>
+struct Elf_Rel_Impl;
+
+template<support::endianness target_endianness, bool isRela>
+struct Elf_Rel_Impl<target_endianness, true, isRela>
+       : Elf_Rel_Base<target_endianness, true, isRela> {
+  using Elf_Rel_Base<target_endianness, true, isRela>::r_info;
+  LLVM_ELF_IMPORT_TYPES(target_endianness, true)
+
+  // These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TYPE,
+  // and ELF64_R_INFO macros defined in the ELF specification:
+  uint64_t getSymbol() const { return (r_info >> 32); }
+  unsigned char getType() const {
+    return (unsigned char) (r_info & 0xffffffffL);
+  }
+  void setSymbol(uint64_t s) { setSymbolAndType(s, getType()); }
+  void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }
+  void setSymbolAndType(uint64_t s, unsigned char t) {
+    r_info = (s << 32) + (t&0xffffffffL);
+  }
+};
+
+template<support::endianness target_endianness, bool isRela>
+struct Elf_Rel_Impl<target_endianness, false, isRela>
+       : Elf_Rel_Base<target_endianness, false, isRela> {
+  using Elf_Rel_Base<target_endianness, false, isRela>::r_info;
+  LLVM_ELF_IMPORT_TYPES(target_endianness, false)
+
+  // These accessors and mutators correspond to the ELF32_R_SYM, ELF32_R_TYPE,
+  // and ELF32_R_INFO macros defined in the ELF specification:
+  uint32_t getSymbol() const { return (r_info >> 8); }
+  unsigned char getType() const { return (unsigned char) (r_info & 0x0ff); }
+  void setSymbol(uint32_t s) { setSymbolAndType(s, getType()); }
+  void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }
+  void setSymbolAndType(uint32_t s, unsigned char t) {
+    r_info = (s << 8) + t;
+  }
+};
+
+}
+
+namespace {
 template<support::endianness target_endianness, bool is64Bits>
 class ELFObjectFile : public ObjectFile {
   LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits)
 
   typedef Elf_Shdr_Impl<target_endianness, is64Bits> Elf_Shdr;
   typedef Elf_Sym_Impl<target_endianness, is64Bits> Elf_Sym;
+  typedef Elf_Rel_Impl<target_endianness, is64Bits, false> Elf_Rel;
+  typedef Elf_Rel_Impl<target_endianness, is64Bits, true> Elf_Rela;
 
   struct Elf_Ehdr {
     unsigned char e_ident[ELF::EI_NIDENT]; // ELF Identification bytes
@@ -206,18 +284,26 @@
     unsigned char getDataEncoding() const { return e_ident[ELF::EI_DATA]; }
   };
 
-  typedef SmallVector<const Elf_Shdr*, 1> SymbolTableSections_t;
+  typedef SmallVector<const Elf_Shdr*, 1> Sections_t;
+  typedef DenseMap<unsigned, unsigned> IndexMap_t;
 
   const Elf_Ehdr *Header;
   const Elf_Shdr *SectionHeaderTable;
   const Elf_Shdr *dot_shstrtab_sec; // Section header string table.
   const Elf_Shdr *dot_strtab_sec;   // Symbol header string table.
-  SymbolTableSections_t SymbolTableSections;
+  Sections_t SymbolTableSections;
+  IndexMap_t SymbolTableSectionsIndexMap;
+  Sections_t RelocationTableSections;
 
   void            validateSymbol(DataRefImpl Symb) const;
+  bool            isRelocationHasAddend(DataRefImpl Rel) const;
+  template<typename T>
+  const T        *getEntry(DataRefImpl Entry, Sections_t Sections) const;
   const Elf_Sym  *getSymbol(DataRefImpl Symb) const;
   const Elf_Shdr *getSection(DataRefImpl index) const;
   const Elf_Shdr *getSection(uint16_t index) const;
+  const Elf_Rel  *getRel(DataRefImpl Rel) const;
+  const Elf_Rela *getRela(DataRefImpl Rela) const;
   const char     *getString(uint16_t section, uint32_t offset) const;
   const char     *getString(const Elf_Shdr *section, uint32_t offset) const;
 
@@ -238,12 +324,25 @@
   virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Symb,
                                            bool &Result) const;
 
+  virtual error_code getRelocationNext(DataRefImpl Rel,
+                                       RelocationRef &Res) const;
+  virtual error_code getRelocationAddress(DataRefImpl Rel,
+                                          uint64_t &Res) const;
+  virtual error_code getRelocationSymbol(DataRefImpl Rel,
+                                         SymbolRef &Res) const;
+  virtual error_code getRelocationType(DataRefImpl Rel,
+                                       uint32_t &Res) const;
+  virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
+                                                 int64_t &Res) const;
+
 public:
   ELFObjectFile(MemoryBuffer *Object, error_code &ec);
   virtual symbol_iterator begin_symbols() const;
   virtual symbol_iterator end_symbols() const;
   virtual section_iterator begin_sections() const;
   virtual section_iterator end_sections() const;
+  virtual relocation_iterator begin_relocations() const;
+  virtual relocation_iterator end_relocations() const;
 
   virtual uint8_t getBytesInAddress() const;
   virtual StringRef getFileFormatName() const;
@@ -416,7 +515,8 @@
       return ec;
     Result = StringSwitch<char>(name)
       .StartsWith(".debug", 'N')
-      .StartsWith(".note", 'n');
+      .StartsWith(".note", 'n')
+      .Default('?');
     return object_error::success;
   }
 
@@ -507,6 +607,121 @@
   return object_error::success;
 }
 
+// Relocations
+template<support::endianness target_endianness, bool is64Bits>
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getRelocationNext(DataRefImpl Rel,
+                                            RelocationRef &Result) const {
+  const Elf_Shdr *RelocationTableSection = RelocationTableSections[Rel.d.b];
+
+  // Check to see if we are at the end of this relocation table.
+  if (++Rel.d.a >= RelocationTableSection->getEntityCount()) {
+    // We are at the end. If there are other relocation tables, jump to them.
+    Rel.d.a = 0;
+    // Otherwise return the terminator.
+    if (++Rel.d.b >= SymbolTableSections.size()) {
+      Rel.d.a = std::numeric_limits<uint32_t>::max();
+      Rel.d.b = std::numeric_limits<uint32_t>::max();
+    }
+  }
+
+  Result = RelocationRef(Rel, this);
+  return object_error::success;
+}
+
+template<support::endianness target_endianness, bool is64Bits>
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getRelocationSymbol(DataRefImpl Rel,
+                                              SymbolRef &Result) const {
+  uint32_t symbolIdx;
+  const Elf_Shdr *sec = RelocationTableSections[Rel.d.b];
+  switch (sec->sh_type) {
+    default :
+      report_fatal_error("Invalid section type in Rel!");
+    case ELF::SHT_REL : {
+      symbolIdx = getRel(Rel)->getSymbol();
+      break;
+    }
+    case ELF::SHT_RELA : {
+      symbolIdx = getRela(Rel)->getSymbol();
+      break;
+    }
+  }
+  DataRefImpl SymbolData;
+  IndexMap_t::const_iterator it = SymbolTableSectionsIndexMap.find(sec->sh_link);
+  if (it == SymbolTableSectionsIndexMap.end())
+    report_fatal_error("Relocation symbol table not found!");
+  SymbolData.d.a = symbolIdx;
+  SymbolData.d.b = it->second;
+  Result = SymbolRef(SymbolData, this);
+  return object_error::success;
+}
+
+template<support::endianness target_endianness, bool is64Bits>
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getRelocationAddress(DataRefImpl Rel,
+                                               uint64_t &Result) const {
+  uint64_t offset;
+  const Elf_Shdr *sec = RelocationTableSections[Rel.d.b];
+  switch (sec->sh_type) {
+    default :
+      report_fatal_error("Invalid section type in Rel!");
+    case ELF::SHT_REL : {
+      offset = getRel(Rel)->r_offset;
+      break;
+    }
+    case ELF::SHT_RELA : {
+      offset = getRela(Rel)->r_offset;
+      break;
+    }
+  }
+
+  const Elf_Shdr *secAddr = getSection(sec->sh_info);
+  Result = offset + reinterpret_cast<uintptr_t>(base() + secAddr->sh_offset);
+  return object_error::success;
+}
+
+template<support::endianness target_endianness, bool is64Bits>
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getRelocationType(DataRefImpl Rel,
+                                            uint32_t &Result) const {
+  const Elf_Shdr *sec = RelocationTableSections[Rel.d.b];
+  switch (sec->sh_type) {
+    default :
+      report_fatal_error("Invalid section type in Rel!");
+    case ELF::SHT_REL : {
+      Result = getRel(Rel)->getType();
+      break;
+    }
+    case ELF::SHT_RELA : {
+      Result = getRela(Rel)->getType();
+      break;
+    }
+  }
+  return object_error::success;
+}
+
+template<support::endianness target_endianness, bool is64Bits>
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getRelocationAdditionalInfo(DataRefImpl Rel,
+                                                      int64_t &Result) const {
+  const Elf_Shdr *sec = RelocationTableSections[Rel.d.b];
+  switch (sec->sh_type) {
+    default :
+      report_fatal_error("Invalid section type in Rel!");
+    case ELF::SHT_REL : {
+      Result = 0;
+      return object_error::success;
+    }
+    case ELF::SHT_RELA : {
+      Result = getRela(Rel)->r_addend;
+      return object_error::success;
+    }
+  }
+}
+
+
+
 template<support::endianness target_endianness, bool is64Bits>
 ELFObjectFile<target_endianness, is64Bits>::ELFObjectFile(MemoryBuffer *Object
                                                           , error_code &ec)
@@ -529,13 +744,17 @@
 
 
   // To find the symbol tables we walk the section table to find SHT_STMTAB.
-  for (const char *i = reinterpret_cast<const char *>(SectionHeaderTable),
-                  *e = i + Header->e_shnum * Header->e_shentsize;
-                   i != e; i += Header->e_shentsize) {
-    const Elf_Shdr *sh = reinterpret_cast<const Elf_Shdr*>(i);
+  const Elf_Shdr* sh =
+                    reinterpret_cast<const Elf_Shdr*>(SectionHeaderTable);
+  for (unsigned i = 0; i < Header->e_shnum; ++i) {
     if (sh->sh_type == ELF::SHT_SYMTAB) {
+      SymbolTableSectionsIndexMap[i] = SymbolTableSections.size();
       SymbolTableSections.push_back(sh);
     }
+    if (sh->sh_type == ELF::SHT_REL || sh->sh_type == ELF::SHT_RELA) {
+      RelocationTableSections.push_back(sh);
+    }
+    ++sh;
   }
 
   // Get string table sections.
@@ -615,6 +834,31 @@
 }
 
 template<support::endianness target_endianness, bool is64Bits>
+ObjectFile::relocation_iterator ELFObjectFile<target_endianness, is64Bits>
+                                         ::begin_relocations() const {
+  DataRefImpl RelData;
+  memset(&RelData, 0, sizeof(RelData));
+  if (RelocationTableSections.size() == 0) {
+    RelData.d.a = std::numeric_limits<uint32_t>::max();
+    RelData.d.b = std::numeric_limits<uint32_t>::max();
+  } else {
+    RelData.d.a = 0;
+    RelData.d.b = 0;
+  }
+  return relocation_iterator(RelocationRef(RelData, this));
+}
+
+template<support::endianness target_endianness, bool is64Bits>
+ObjectFile::relocation_iterator ELFObjectFile<target_endianness, is64Bits>
+                                         ::end_relocations() const {
+  DataRefImpl RelData;
+  memset(&RelData, 0, sizeof(RelData));
+  RelData.d.a = std::numeric_limits<uint32_t>::max();
+  RelData.d.b = std::numeric_limits<uint32_t>::max();
+  return relocation_iterator(RelocationRef(RelData, this));
+}
+
+template<support::endianness target_endianness, bool is64Bits>
 uint8_t ELFObjectFile<target_endianness, is64Bits>::getBytesInAddress() const {
   return is64Bits ? 8 : 4;
 }
@@ -629,6 +873,8 @@
       return "ELF32-i386";
     case ELF::EM_X86_64:
       return "ELF32-x86-64";
+    case ELF::EM_ARM:
+      return "ELF32-arm";
     default:
       return "ELF32-unknown";
     }
@@ -654,19 +900,41 @@
     return Triple::x86;
   case ELF::EM_X86_64:
     return Triple::x86_64;
+  case ELF::EM_ARM:
+    return Triple::arm;
   default:
     return Triple::UnknownArch;
   }
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Sym *
-ELFObjectFile<target_endianness, is64Bits>::getSymbol(DataRefImpl Symb) const {
-  const Elf_Shdr *sec = SymbolTableSections[Symb.d.b];
-  return reinterpret_cast<const Elf_Sym *>(
+template<typename T>
+inline const T *
+ELFObjectFile<target_endianness, is64Bits>::getEntry(DataRefImpl Entry,
+                                                     Sections_t Sections) const {
+  const Elf_Shdr *sec = Sections[Entry.d.b];
+  return reinterpret_cast<const T *>(
            base()
            + sec->sh_offset
-           + (Symb.d.a * sec->sh_entsize));
+           + (Entry.d.a * sec->sh_entsize));
+}
+
+template<support::endianness target_endianness, bool is64Bits>
+const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Sym *
+ELFObjectFile<target_endianness, is64Bits>::getSymbol(DataRefImpl Symb) const {
+  return getEntry<Elf_Sym>(Symb, SymbolTableSections);
+}
+
+template<support::endianness target_endianness, bool is64Bits>
+const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Rel *
+ELFObjectFile<target_endianness, is64Bits>::getRel(DataRefImpl Rel) const {
+  return getEntry<Elf_Rel>(Rel, RelocationTableSections);
+}
+
+template<support::endianness target_endianness, bool is64Bits>
+const typename ELFObjectFile<target_endianness, is64Bits>::Elf_Rela *
+ELFObjectFile<target_endianness, is64Bits>::getRela(DataRefImpl Rela) const {
+  return getEntry<Elf_Rela>(Rela, RelocationTableSections);
 }
 
 template<support::endianness target_endianness, bool is64Bits>

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=139314&r1=139313&r2=139314&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Thu Sep  8 15:52:17 2011
@@ -18,6 +18,7 @@
 #include "llvm/Object/ObjectFile.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/MachO.h"
+#include "llvm/ADT/SmallVector.h"
 
 #include <cctype>
 #include <cstring>
@@ -32,15 +33,14 @@
 
 class MachOObjectFile : public ObjectFile {
 public:
-  MachOObjectFile(MemoryBuffer *Object, MachOObject *MOO, error_code &ec)
-    : ObjectFile(Binary::isMachO, Object, ec),
-      MachOObj(MOO),
-      RegisteredStringTable(std::numeric_limits<uint32_t>::max()) {}
+  MachOObjectFile(MemoryBuffer *Object, MachOObject *MOO, error_code &ec);
 
   virtual symbol_iterator begin_symbols() const;
   virtual symbol_iterator end_symbols() const;
   virtual section_iterator begin_sections() const;
   virtual section_iterator end_sections() const;
+  virtual relocation_iterator begin_relocations() const;
+  virtual relocation_iterator end_relocations() const;
 
   virtual uint8_t getBytesInAddress() const;
   virtual StringRef getFileFormatName() const;
@@ -63,9 +63,22 @@
   virtual error_code sectionContainsSymbol(DataRefImpl DRI, DataRefImpl S,
                                            bool &Result) const;
 
+  virtual error_code getRelocationNext(DataRefImpl Rel,
+                                       RelocationRef &Res) const;
+  virtual error_code getRelocationAddress(DataRefImpl Rel,
+                                          uint64_t &Res) const;
+  virtual error_code getRelocationSymbol(DataRefImpl Rel,
+                                         SymbolRef &Res) const;
+  virtual error_code getRelocationType(DataRefImpl Rel,
+                                       uint32_t &Res) const;
+  virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
+                                                 int64_t &Res) const;
 private:
   MachOObject *MachOObj;
   mutable uint32_t RegisteredStringTable;
+  typedef SmallVector<DataRefImpl, 1> SectionList;
+  SectionList Sections;
+
 
   void moveToNextSection(DataRefImpl &DRI) const;
   void getSymbolTableEntry(DataRefImpl DRI,
@@ -76,8 +89,35 @@
   void getSection(DataRefImpl DRI, InMemoryStruct<macho::Section> &Res) const;
   void getSection64(DataRefImpl DRI,
                     InMemoryStruct<macho::Section64> &Res) const;
+  void getRelocation(DataRefImpl Rel,
+                     InMemoryStruct<macho::RelocationEntry> &Res) const;
 };
 
+MachOObjectFile::MachOObjectFile(MemoryBuffer *Object, MachOObject *MOO,
+                                 error_code &ec)
+    : ObjectFile(Binary::isMachO, Object, ec),
+      MachOObj(MOO),
+      RegisteredStringTable(std::numeric_limits<uint32_t>::max()) {
+  DataRefImpl DRI;
+  DRI.d.a = DRI.d.b = 0;
+  moveToNextSection(DRI);
+  uint32_t LoadCommandCount = MachOObj->getHeader().NumLoadCommands;
+  while (DRI.d.a < LoadCommandCount) {
+    Sections.push_back(DRI);
+    uint64_t Addr;
+    uint64_t Size;
+    StringRef Name;
+    getSectionAddress(DRI, Addr);
+    getSectionSize(DRI, Size);
+    getSectionName(DRI, Name);
+    InMemoryStruct<macho::Section> Sect;
+    getSection(DRI, Sect);
+    DRI.d.b++;
+    moveToNextSection(DRI);
+  }
+}
+
+
 ObjectFile *ObjectFile::createMachOObjectFile(MemoryBuffer *Buffer) {
   error_code ec;
   std::string Err;
@@ -414,6 +454,125 @@
   return section_iterator(SectionRef(DRI, this));
 }
 
+/*===-- Relocations -------------------------------------------------------===*/
+
+void MachOObjectFile::
+getRelocation(DataRefImpl Rel,
+              InMemoryStruct<macho::RelocationEntry> &Res) const {
+  uint32_t relOffset;
+  if (MachOObj->is64Bit()) {
+    InMemoryStruct<macho::Section64> Sect;
+    getSection64(Sections[Rel.d.b], Sect);
+    relOffset = Sect->RelocationTableOffset;
+  } else {
+    InMemoryStruct<macho::Section> Sect;
+    getSection(Sections[Rel.d.b], Sect);
+    relOffset = Sect->RelocationTableOffset;
+  }
+  MachOObj->ReadRelocationEntry(relOffset, Rel.d.a, Res);
+}
+error_code MachOObjectFile::getRelocationNext(DataRefImpl Rel,
+                                              RelocationRef &Res) const {
+  ++Rel.d.a;
+  while (Rel.d.b < Sections.size()) {
+    unsigned relocationCount;
+    if (MachOObj->is64Bit()) {
+      InMemoryStruct<macho::Section64> Sect;
+      getSection64(Sections[Rel.d.b], Sect);
+      relocationCount = Sect->NumRelocationTableEntries;
+    } else {
+      InMemoryStruct<macho::Section> Sect;
+      getSection(Sections[Rel.d.b], Sect);
+      relocationCount = Sect->NumRelocationTableEntries;
+    }
+    if (Rel.d.a < relocationCount)
+      break;
+
+    Rel.d.a = 0;
+    ++Rel.d.b;
+  }
+  Res = RelocationRef(Rel, this);
+  return object_error::success;
+}
+error_code MachOObjectFile::getRelocationAddress(DataRefImpl Rel,
+                                                 uint64_t &Res) const {
+  const uint8_t* sectAddress = base();
+  if (MachOObj->is64Bit()) {
+    InMemoryStruct<macho::Section64> Sect;
+    getSection64(Sections[Rel.d.b], Sect);
+    sectAddress += Sect->Offset;
+  } else {
+    InMemoryStruct<macho::Section> Sect;
+    getSection(Sections[Rel.d.b], Sect);
+    sectAddress += Sect->Offset;
+  }
+  InMemoryStruct<macho::RelocationEntry> RE;
+  getRelocation(Rel, RE);
+  Res = reinterpret_cast<uintptr_t>(sectAddress + RE->Word0);
+  return object_error::success;
+}
+error_code MachOObjectFile::getRelocationSymbol(DataRefImpl Rel,
+                                                SymbolRef &Res) const {
+  InMemoryStruct<macho::RelocationEntry> RE;
+  getRelocation(Rel, RE);
+  uint32_t SymbolIdx = RE->Word1 & 0xffffff;
+  bool isExtern = (RE->Word1 >> 27) & 1;
+
+  DataRefImpl Sym;
+  Sym.d.a = Sym.d.b = 0;
+  moveToNextSymbol(Sym);
+  uint32_t NumLoadCommands = MachOObj->getHeader().NumLoadCommands;
+  if (isExtern) {
+    for (unsigned i = 0; i < SymbolIdx; i++) {
+      Sym.d.b++;
+      moveToNextSymbol(Sym);
+      assert(Sym.d.a < NumLoadCommands &&
+             "Relocation symbol index out of range!");
+    }
+  }
+  Res = SymbolRef(Sym, this);
+  return object_error::success;
+}
+error_code MachOObjectFile::getRelocationType(DataRefImpl Rel,
+                                              uint32_t &Res) const {
+  InMemoryStruct<macho::RelocationEntry> RE;
+  getRelocation(Rel, RE);
+  Res = RE->Word1;
+  return object_error::success;
+}
+error_code MachOObjectFile::getRelocationAdditionalInfo(DataRefImpl Rel,
+                                                        int64_t &Res) const {
+  InMemoryStruct<macho::RelocationEntry> RE;
+  getRelocation(Rel, RE);
+  bool isExtern = (RE->Word1 >> 27) & 1;
+  Res = 0;
+  if (!isExtern) {
+    const uint8_t* sectAddress = base();
+    if (MachOObj->is64Bit()) {
+      InMemoryStruct<macho::Section64> Sect;
+      getSection64(Sections[Rel.d.b], Sect);
+      sectAddress += Sect->Offset;
+    } else {
+      InMemoryStruct<macho::Section> Sect;
+      getSection(Sections[Rel.d.b], Sect);
+      sectAddress += Sect->Offset;
+    }
+    Res = reinterpret_cast<uintptr_t>(sectAddress);
+  }
+  return object_error::success;
+}
+ObjectFile::relocation_iterator MachOObjectFile::begin_relocations() const {
+  DataRefImpl ret;
+  ret.d.a = ret.d.b = 0;
+  return relocation_iterator(RelocationRef(ret, this));
+}
+ObjectFile::relocation_iterator MachOObjectFile::end_relocations() const {
+  DataRefImpl ret;
+  ret.d.a = 0;
+  ret.d.b = Sections.size();
+  return relocation_iterator(RelocationRef(ret, this));
+}
+
 /*===-- Miscellaneous -----------------------------------------------------===*/
 
 uint8_t MachOObjectFile::getBytesInAddress() const {



From benny.kra at googlemail.com  Thu Sep  8 15:54:02 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 8 Sep 2011 13:54:02 -0700
Subject: [llvm-commits] ObjectFile RelocationRef
In-Reply-To: <6AE1604EE3EC5F4296C096518C6B77EE17F9B4DCFB@mail.accesssoftek.com>
References: <6AE1604EE3EC5F4296C096518C6B77EE17F9B4DBFE@mail.accesssoftek.com>
	<CAL3drCokdsAmrfj8RN4u7z0=PReOESCz6fR-5nB51L3YFPtH=g@mail.gmail.com>
	<6AE1604EE3EC5F4296C096518C6B77EE17F9B4DCFB@mail.accesssoftek.com>
Message-ID: <CAL3drCpnsU7eY=t_sFA+W2BtLhuuwq8Nd4z=NLGDZFhMpBHBdQ@mail.gmail.com>

On Thu, Sep 8, 2011 at 13:00, Danil Malyshev <dmalyshev at accesssoftek.com> wrote:
> Hi everyone,
>
>> Can you make the macros (ELF_REL_GET_VALUE etc.) static functions?
>> Macros with side effects like that one make the code much harder to
>> follow. Looks good otherwise.
>
> I removed all macroses. Changed patch is attached.

Committed in r139314. Thanks for working on this!

- Ben

From enderby at apple.com  Thu Sep  8 15:53:44 2011
From: enderby at apple.com (Kevin Enderby)
Date: Thu, 08 Sep 2011 20:53:44 -0000
Subject: [llvm-commits] [llvm] r139316 - in /llvm/trunk:
 lib/MC/MachObjectWriter.cpp test/MC/MachO/darwin-x86_64-nobase-relocs.s
Message-ID: <20110908205344.9C8DD2A6C12C@llvm.org>

Author: enderby
Date: Thu Sep  8 15:53:44 2011
New Revision: 139316

URL: http://llvm.org/viewvc/llvm-project?rev=139316&view=rev
Log:
Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom
without a base symbol that must not have a relocation entry.

Added:
    llvm/trunk/test/MC/MachO/darwin-x86_64-nobase-relocs.s
Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=139316&r1=139315&r2=139316&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Sep  8 15:53:44 2011
@@ -590,6 +590,16 @@
         return false;
       return true;
     }
+    // For Darwin x86_64, there is one special case when the reference IsPCRel.
+    // If the fragment with the reference does not have a base symbol but meets
+    // the simple way of dealing with this, in that it is a temporary symbol in
+    // the same atom then it is assumed to be fully resolved.  This is needed so
+    // a relocation entry is not created and so the staitic linker does not
+    // mess up the reference later.
+    else if(!FB.getAtom() &&
+            SA.isTemporary() && SA.isInSection() && &SecA == &SecB){
+      return true;
+    }
   } else {
     if (!TargetObjectWriter->useAggressiveSymbolFolding())
       return false;

Added: llvm/trunk/test/MC/MachO/darwin-x86_64-nobase-relocs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/darwin-x86_64-nobase-relocs.s?rev=139316&view=auto
==============================================================================
--- llvm/trunk/test/MC/MachO/darwin-x86_64-nobase-relocs.s (added)
+++ llvm/trunk/test/MC/MachO/darwin-x86_64-nobase-relocs.s Thu Sep  8 15:53:44 2011
@@ -0,0 +1,58 @@
+// RUN: llvm-mc -n -triple x86_64-apple-darwin9 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s
+
+// Test case for rdar://10062261
+
+// Must be no base, non-temporary, symbol before the reference to Lbar at the
+// start of the section.  What we are testing for is that the reference does not
+// create a relocation entry.
+.text
+Ladd:
+	nop
+	jmp Lbar
+	.byte 0x0f,0x1f,0x40,0x00
+	.byte 0x0f,0x1f,0x40,0x00
+Lbar:	
+	mov $1, %eax
+	ret
+
+// CHECK: ('cputype', 16777223)
+// CHECK: ('cpusubtype', 3)
+// CHECK: ('filetype', 1)
+// CHECK: ('num_load_commands', 1)
+// CHECK: ('load_commands_size', 152)
+// CHECK: ('flag', 0)
+// CHECK: ('reserved', 0)
+// CHECK: ('load_commands', [
+// CHECK:   # Load Command 0
+// CHECK:  (('command', 25)
+// CHECK:   ('size', 152)
+// CHECK:   ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+// CHECK:   ('vm_addr', 0)
+// CHECK:   ('vm_size', 17)
+// CHECK:   ('file_offset', 184)
+// CHECK:   ('file_size', 17)
+// CHECK:   ('maxprot', 7)
+// CHECK:   ('initprot', 7)
+// CHECK:   ('num_sections', 1)
+// CHECK:   ('flags', 0)
+// CHECK:   ('sections', [
+// CHECK:     # Section 0
+// CHECK:    (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+// CHECK:     ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+// CHECK:     ('address', 0)
+// CHECK:     ('size', 17)
+// CHECK:     ('offset', 184)
+// CHECK:     ('alignment', 0)
+// CHECK:     ('reloc_offset', 0)
+// CHECK:     ('num_reloc', 0)
+// CHECK:     ('flags', 0x80000400)
+// CHECK:     ('reserved1', 0)
+// CHECK:     ('reserved2', 0)
+// CHECK:     ('reserved3', 0)
+// CHECK:    ),
+// CHECK:   ('_relocations', [
+// CHECK:   ])
+// CHECK:   ('_section_data', '90eb080f 1f40000f 1f4000b8 01000000 c3')
+// CHECK:   ])
+// CHECK:  ),
+// CHECK: ])



From eli.friedman at gmail.com  Thu Sep  8 16:00:31 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 08 Sep 2011 21:00:31 -0000
Subject: [llvm-commits] [llvm] r139317 -
	/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
Message-ID: <20110908210032.00BE12A6C12C@llvm.org>

Author: efriedma
Date: Thu Sep  8 16:00:31 2011
New Revision: 139317

URL: http://llvm.org/viewvc/llvm-project?rev=139317&view=rev
Log:
Make sure to handle the case where emitPredicateMatch returns false.  Noticed by inspection.


Modified:
    llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp

Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=139317&r1=139316&r2=139317&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Thu Sep  8 16:00:31 2011
@@ -818,7 +818,8 @@
   // If we have matched all the well-known bits, just issue a return.
   if (Size == 0) {
     o.indent(Indentation) << "if (";
-    emitPredicateMatch(o, Indentation, Opc);
+    if (!emitPredicateMatch(o, Indentation, Opc))
+      o << "1";
     o << ") {\n";
     o.indent(Indentation) << "  MI.setOpcode(" << Opc << ");\n";
     std::vector<OperandInfo>& InsnOperands = Operands[Opc];



From bruno.cardoso at gmail.com  Thu Sep  8 16:05:44 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 08 Sep 2011 21:05:44 -0000
Subject: [llvm-commits] [llvm] r139318 -
	/llvm/trunk/test/CodeGen/X86/avx-blend.ll
Message-ID: <20110908210544.172EB2A6C12C@llvm.org>

Author: bruno
Date: Thu Sep  8 16:05:43 2011
New Revision: 139318

URL: http://llvm.org/viewvc/llvm-project?rev=139318&view=rev
Log:
Reapply testcase from r139309!

Added:
    llvm/trunk/test/CodeGen/X86/avx-blend.ll

Added: llvm/trunk/test/CodeGen/X86/avx-blend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?rev=139318&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-blend.ll (added)
+++ llvm/trunk/test/CodeGen/X86/avx-blend.ll Thu Sep  8 16:05:43 2011
@@ -0,0 +1,47 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -promote-elements -mattr=+avx | FileCheck %s
+
+;CHECK: vsel_float
+;CHECK: vblendvps
+;CHECK: ret
+define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
+  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
+  ret <4 x float> %vsel
+}
+
+
+;CHECK: vsel_i32
+;CHECK: vblendvps
+;CHECK: ret
+define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
+  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2
+  ret <4 x i32> %vsel
+}
+
+
+;CHECK: vsel_double
+;CHECK: vblendvpd
+;CHECK: ret
+define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
+  %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2
+  ret <2 x double> %vsel
+}
+
+
+;CHECK: vsel_i64
+;CHECK: vblendvpd
+;CHECK: ret
+define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
+  %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2
+  ret <2 x i64> %vsel
+}
+
+
+;CHECK: vsel_i8
+;CHECK: vpblendvb
+;CHECK: ret
+define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
+  %vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
+  ret <16 x i8> %vsel
+}
+
+



From bruno.cardoso at gmail.com  Thu Sep  8 16:52:33 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 08 Sep 2011 21:52:33 -0000
Subject: [llvm-commits] [llvm] r139320 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-bitcast.ll
Message-ID: <20110908215233.DD3222A6C12C@llvm.org>

Author: bruno
Date: Thu Sep  8 16:52:33 2011
New Revision: 139320

URL: http://llvm.org/viewvc/llvm-project?rev=139320&view=rev
Log:
Add a AVX version of a simple i64 -> f64 bitcast. This could be
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

Added:
    llvm/trunk/test/CodeGen/X86/avx-bitcast.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139320&r1=139319&r2=139320&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep  8 16:52:33 2011
@@ -4090,16 +4090,30 @@
                          "mov{d|q}\t{$src, $dst|$dst, $src}",
                          [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
                                            (iPTR 0)))]>;
+//===---------------------------------------------------------------------===//
+// Bitcast FR64 <-> GR64
+//
+let Predicates = [HasAVX] in
+def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
+                        "vmovq\t{$src, $dst|$dst, $src}",
+                        [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
+                        VEX;
+def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
+                         "mov{d|q}\t{$src, $dst|$dst, $src}",
+                         [(set GR64:$dst, (bitconvert FR64:$src))]>;
+def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
+                         "movq\t{$src, $dst|$dst, $src}",
+                         [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
+
 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
                        "movq\t{$src, $dst|$dst, $src}",
                        [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
-
-def MOVSDto64rr  : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
-                        "mov{d|q}\t{$src, $dst|$dst, $src}",
-                        [(set GR64:$dst, (bitconvert FR64:$src))]>;
-def MOVSDto64mr  : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
-                        "movq\t{$src, $dst|$dst, $src}",
-                        [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
+def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
+                       "mov{d|q}\t{$src, $dst|$dst, $src}",
+                       [(set GR64:$dst, (bitconvert FR64:$src))]>;
+def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
+                       "movq\t{$src, $dst|$dst, $src}",
+                       [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
 
 //===---------------------------------------------------------------------===//
 // Move Scalar Single to Double Int

Added: llvm/trunk/test/CodeGen/X86/avx-bitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-bitcast.ll?rev=139320&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-bitcast.ll (added)
+++ llvm/trunk/test/CodeGen/X86/avx-bitcast.ll Thu Sep  8 16:52:33 2011
@@ -0,0 +1,10 @@
+; RUN: llc < %s -O0 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
+
+; CHECK: vmovsd (%
+; CHECK-NEXT: vmovd %xmm
+define i64 @bitcasti64tof64() {
+  %a = load double* undef
+  %b = bitcast double %a to i64
+  ret i64 %b
+}
+



From grosbach at apple.com  Thu Sep  8 17:07:06 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Sep 2011 22:07:06 -0000
Subject: [llvm-commits] [llvm] r139322 - in /llvm/trunk:
 lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrFormats.td
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
 test/MC/ARM/basic-thumb2-instructions.s
 test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
Message-ID: <20110908220706.B90732A6C12C@llvm.org>

Author: grosbach
Date: Thu Sep  8 17:07:06 2011
New Revision: 139322

URL: http://llvm.org/viewvc/llvm-project?rev=139322&view=rev
Log:
Thumb2 assembly parsing and encoding for LDRD(immediate).

Refactor operand handling for STRD as well. Tests for that forthcoming.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
    llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=139322&r1=139321&r2=139322&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Sep  8 17:07:06 2011
@@ -207,6 +207,8 @@
       const { return 0; }
     unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
+    unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)
+      const { return 0; }
     unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=139322&r1=139321&r2=139322&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Sep  8 17:07:06 2011
@@ -1100,8 +1100,8 @@
             string opc, string asm, list<dag> pattern>
   : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
-              string opc, string asm, list<dag> pattern>
-  : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, "",
+              string opc, string asm, string cstr, list<dag> pattern>
+  : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
             pattern> {
   bits<4> Rt;
   bits<4> Rt2;
@@ -1117,14 +1117,14 @@
   let Inst{11-8}  = Rt2{3-0};
   let Inst{7-0}   = addr{7-0};
 }
-
-class T2Ii8s4Tied<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
-              string opc, string asm, list<dag> pattern>
-  : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, "$base = $wb",
+class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops,
+                  InstrItinClass itin, string opc, string asm, string cstr,
+                  list<dag> pattern>
+  : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
             pattern> {
   bits<4> Rt;
   bits<4> Rt2;
-  bits<4> base;
+  bits<4> addr;
   bits<9> imm;
   let Inst{31-25} = 0b1110100;
   let Inst{24}    = P;
@@ -1132,13 +1132,12 @@
   let Inst{22}    = 1;
   let Inst{21}    = W;
   let Inst{20}    = isLoad;
-  let Inst{19-16} = base{3-0};
+  let Inst{19-16} = addr;
   let Inst{15-12} = Rt{3-0};
   let Inst{11-8}  = Rt2{3-0};
   let Inst{7-0}   = imm{7-0};
 }
 
-
 class T2sI<dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, list<dag> pattern>
   : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139322&r1=139321&r2=139322&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Sep  8 17:07:06 2011
@@ -164,15 +164,19 @@
 }
 
 // t2addrmode_imm8s4  := reg +/- (imm8 << 2)
+def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
 def t2addrmode_imm8s4 : Operand<i32> {
   let PrintMethod = "printT2AddrModeImm8s4Operand";
   let EncoderMethod = "getT2AddrModeImm8s4OpValue";
   let DecoderMethod = "DecodeT2AddrModeImm8s4";
+  let ParserMatchClass = MemImm8s4OffsetAsmOperand;
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
 }
 
+def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
 def t2am_imm8s4_offset : Operand<i32> {
   let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
+  let EncoderMethod = "getT2Imm8s4OpValue";
   let DecoderMethod = "DecodeT2Imm8S4";
 }
 
@@ -1193,7 +1197,7 @@
 // Load doubleword
 def t2LDRDi8  : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
                         (ins t2addrmode_imm8s4:$addr),
-                        IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
+                        IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
 
 // zextload i1 -> zextload i8
@@ -1344,7 +1348,7 @@
 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
                        (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
-               IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
+               IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
 
 // Indexed stores
 def t2STR_PRE  : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
@@ -1424,23 +1428,31 @@
 // ldrd / strd pre / post variants
 // For disassembly only.
 
-def t2LDRD_PRE  : T2Ii8s4Tied<1, 1, 1,
-                 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
-                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
-                 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
-
-def t2LDRD_POST : T2Ii8s4Tied<0, 1, 1,
-                 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
-                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
-                 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
-
-def t2STRD_PRE  : T2Ii8s4Tied<1, 1, 0, (outs GPR:$wb),
-                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
-                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
-
-def t2STRD_POST : T2Ii8s4Tied<0, 1, 0, (outs GPR:$wb),
-                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
-                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
+def t2LDRD_PRE  : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
+                 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
+                 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
+  let AsmMatchConverter = "cvtT2LdrdPre";
+  let DecoderMethod = "DecodeT2LDRDPreInstruction";
+}
+
+def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
+                 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
+                 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr, $imm",
+                 "$addr.base = $wb", []>;
+
+def t2STRD_PRE  : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
+                 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
+                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
+                 "$addr.base = $wb", []> {
+  let AsmMatchConverter = "cvtT2StrdPre";
+  let DecoderMethod = "DecodeT2STRDPreInstruction";
+}
+
+def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
+                 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
+                      t2am_imm8s4_offset:$imm),
+                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr, $imm",
+                 "$addr.base = $wb", []>;
 
 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
 // data/instruction access.  These are for disassembly only.

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139322&r1=139321&r2=139322&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Sep  8 17:07:06 2011
@@ -158,6 +158,10 @@
   OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
 
   // Asm Match Converter Methods
+  bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
+                    const SmallVectorImpl<MCParsedAsmOperand*> &);
+  bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
+                    const SmallVectorImpl<MCParsedAsmOperand*> &);
   bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
   bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
@@ -463,6 +467,14 @@
   bool isITMask() const { return Kind == ITCondMask; }
   bool isITCondCode() const { return Kind == CondCode; }
   bool isImm() const { return Kind == Immediate; }
+  bool isImm8s4() const {
+    if (Kind != Immediate)
+      return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
+  }
   bool isImm0_1020s4() const {
     if (Kind != Immediate)
       return false;
@@ -736,6 +748,14 @@
     int64_t Val = Mem.OffsetImm->getValue();
     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
   }
+  bool isMemImm8s4Offset() const {
+    if (Kind != Memory || Mem.OffsetRegNum != 0)
+      return false;
+    // Immediate offset a multiple of 4 in range [-1020, 1020].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
+  }
   bool isMemImm8Offset() const {
     if (Kind != Memory || Mem.OffsetRegNum != 0)
       return false;
@@ -908,6 +928,14 @@
     addExpr(Inst, getImm());
   }
 
+  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // FIXME: We really want to scale the value here, but the LDRD/STRD
+    // instruction don't encode operands that way yet.
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+  }
+
   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     // The immediate is scaled by four in the encoding and is stored
@@ -1111,6 +1139,13 @@
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
+  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Val));
+  }
+
   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
@@ -2400,6 +2435,42 @@
   return MatchOperand_Success;
 }
 
+/// cvtT2LdrdPre - Convert parsed operands to MCInst.
+/// Needed here because the Asm Gen Matcher can't handle properly tied operands
+/// when they refer multiple MIOperands inside a single one.
+bool ARMAsmParser::
+cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
+             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  // Rt, Rt2
+  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
+  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
+  // Create a writeback register dummy placeholder.
+  Inst.addOperand(MCOperand::CreateReg(0));
+  // addr
+  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
+  // pred
+  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
+  return true;
+}
+
+/// cvtT2StrdPre - Convert parsed operands to MCInst.
+/// Needed here because the Asm Gen Matcher can't handle properly tied operands
+/// when they refer multiple MIOperands inside a single one.
+bool ARMAsmParser::
+cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
+             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  // Create a writeback register dummy placeholder.
+  Inst.addOperand(MCOperand::CreateReg(0));
+  // Rt, Rt2
+  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
+  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
+  // addr
+  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
+  // pred
+  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
+  return true;
+}
+
 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
 /// when they refer multiple MIOperands inside a single one.

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139322&r1=139321&r2=139322&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Sep  8 17:07:06 2011
@@ -293,6 +293,10 @@
                                 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
+                               uint64_t Address, const void *Decoder);
 
 #include "ARMGenDisassemblerTables.inc"
 #include "ARMGenInstrInfo.inc"
@@ -3649,3 +3653,75 @@
   Inst.addOperand(MCOperand::CreateImm(mask));
   return S;
 }
+
+static DecodeStatus
+DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
+                           uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+  unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned addr = fieldFromInstruction32(Insn, 0, 8);
+  unsigned W = fieldFromInstruction32(Insn, 21, 1);
+  unsigned U = fieldFromInstruction32(Insn, 23, 1);
+  unsigned P = fieldFromInstruction32(Insn, 24, 1);
+  bool writeback = (W == 1) | (P == 0);
+
+  addr |= (U << 8) | (Rn << 9);
+
+  if (writeback && (Rn == Rt || Rn == Rt2))
+    Check(S, MCDisassembler::SoftFail);
+  if (Rt == Rt2)
+    Check(S, MCDisassembler::SoftFail);
+
+  // Rt
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
+    return MCDisassembler::Fail;
+  // Rt2
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
+    return MCDisassembler::Fail;
+  // Writeback operand
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  // addr
+  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}
+
+static DecodeStatus
+DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
+                           uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+  unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned addr = fieldFromInstruction32(Insn, 0, 8);
+  unsigned W = fieldFromInstruction32(Insn, 21, 1);
+  unsigned U = fieldFromInstruction32(Insn, 23, 1);
+  unsigned P = fieldFromInstruction32(Insn, 24, 1);
+  bool writeback = (W == 1) | (P == 0);
+
+  addr |= (U << 8) | (Rn << 9);
+
+  if (writeback && (Rn == Rt || Rn == Rt2))
+    Check(S, MCDisassembler::SoftFail);
+
+  // Writeback operand
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  // Rt
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
+    return MCDisassembler::Fail;
+  // Rt2
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
+    return MCDisassembler::Fail;
+  // addr
+  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=139322&r1=139321&r2=139322&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Thu Sep  8 17:07:06 2011
@@ -144,6 +144,10 @@
   /// operand.
   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
                                    SmallVectorImpl<MCFixup> &Fixups) const;
+  /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
+  /// operand.
+  uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
+                              SmallVectorImpl<MCFixup> &Fixups) const;
 
 
   /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
@@ -720,6 +724,37 @@
   return Binary;
 }
 
+/// getT2Imm8s4OpValue - Return encoding info for
+/// '+/- imm8<<2' operand.
+uint32_t ARMMCCodeEmitter::
+getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
+                   SmallVectorImpl<MCFixup> &Fixups) const {
+  // FIXME: The immediate operand should have already been encoded like this
+  // before ever getting here. The encoder method should just need to combine
+  // the MI operands for the register and the offset into a single
+  // representation for the complex operand in the .td file. This isn't just
+  // style, unfortunately. As-is, we can't represent the distinct encoding
+  // for #-0.
+
+  // {8}    = (U)nsigned (add == '1', sub == '0')
+  // {7-0}  = imm8
+  int32_t Imm8 = MI.getOperand(OpIdx).getImm();
+  bool isAdd = Imm8 >= 0;
+
+  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
+  if (Imm8 < 0)
+    Imm8 = -Imm8;
+
+  // Scaled by 4.
+  Imm8 /= 4;
+
+  uint32_t Binary = Imm8 & 0xff;
+  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
+  if (isAdd)
+    Binary |= (1 << 8);
+  return Binary;
+}
+
 /// getT2AddrModeImm8s4OpValue - Return encoding info for
 /// 'reg +/- imm8<<2' operand.
 uint32_t ARMMCCodeEmitter::
@@ -746,6 +781,12 @@
   } else
     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
 
+  // FIXME: The immediate operand should have already been encoded like this
+  // before ever getting here. The encoder method should just need to combine
+  // the MI operands for the register and the offset into a single
+  // representation for the complex operand in the .td file. This isn't just
+  // style, unfortunately. As-is, we can't represent the distinct encoding
+  // for #-0.
   uint32_t Binary = (Imm8 >> 2) & 0xff;
   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
   if (isAdd)

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139322&r1=139321&r2=139322&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Thu Sep  8 17:07:06 2011
@@ -630,6 +630,24 @@
 
 
 @------------------------------------------------------------------------------
+@ LDRD(immediate)
+ at ------------------------------------------------------------------------------
+        ldrd r3, r5, [r6, #24]
+        ldrd r3, r5, [r6, #24]!
+        ldrd r3, r5, [r6], #4
+        ldrd r3, r5, [r6], #-8
+        ldrd r3, r5, [r6]
+        ldrd r8, r1, [r3, #0]
+
+@ CHECK: ldrd	r3, r5, [r6, #24]       @ encoding: [0xd6,0xe9,0x06,0x35]
+@ CHECK: ldrd	r3, r5, [r6, #24]!      @ encoding: [0xf6,0xe9,0x06,0x35]
+@ CHECK: ldrd	r3, r5, [r6], #4        @ encoding: [0xf6,0xe8,0x01,0x35]
+@ CHECK: ldrd	r3, r5, [r6], #-8       @ encoding: [0x76,0xe8,0x02,0x35]
+@ CHECK: ldrd	r3, r5, [r6]            @ encoding: [0xd6,0xe9,0x00,0x35]
+@ CHECK: ldrd	r8, r1, [r3]            @ encoding: [0xd3,0xe9,0x00,0x81]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt?rev=139322&r1=139321&r2=139322&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt Thu Sep  8 17:07:06 2011
@@ -1,5 +1,4 @@
 # RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
 
 # Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 



From nadav.rotem at intel.com  Thu Sep  8 17:17:35 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Thu, 08 Sep 2011 22:17:35 -0000
Subject: [llvm-commits] [llvm] r139324 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20110908221735.DDF772A6C12C@llvm.org>

Author: nadav
Date: Thu Sep  8 17:17:35 2011
New Revision: 139324

URL: http://llvm.org/viewvc/llvm-project?rev=139324&view=rev
Log:
Dix the 80-columns and remove unsupported v8i16 type from the list of legal vselect types.


Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139324&r1=139323&r2=139324&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep  8 17:17:35 2011
@@ -920,7 +920,6 @@
     setOperationAction(ISD::VSELECT,            MVT::v2f64, Custom);
     setOperationAction(ISD::VSELECT,            MVT::v2i64, Custom);
     setOperationAction(ISD::VSELECT,            MVT::v16i8, Custom);
-    setOperationAction(ISD::VSELECT,            MVT::v8i16, Custom);
     setOperationAction(ISD::VSELECT,            MVT::v4i32, Custom);
     setOperationAction(ISD::VSELECT,            MVT::v4f32, Custom);
 
@@ -8703,16 +8702,20 @@
   assert(Op2.getValueType().isVector() && "Op2 must be a vector");
   assert(Cond.getValueType().isVector() && "Cond must be a vector");
   assert(Op1.getValueType() == Op2.getValueType() && "Type mismatch");
-  
-  switch (Op1.getValueType().getSimpleVT().SimpleTy) {
+
+  EVT VT = Op1.getValueType();
+  switch (VT.getSimpleVT().SimpleTy) {
     default: break;
-    case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
-    case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
-    case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
-    case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
-    case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
+    case MVT::v2i64:
+    case MVT::v2f64:
+         return DAG.getNode(X86ISD::BLENDVPD, DL, VT, Ops, array_lengthof(Ops));
+    case MVT::v4i32:
+    case MVT::v4f32:
+         return DAG.getNode(X86ISD::BLENDVPS, DL, VT , Ops, array_lengthof(Ops));
+    case MVT::v16i8:
+         return DAG.getNode(X86ISD::PBLENDVB, DL, VT , Ops, array_lengthof(Ops));
   }
-  
+
   return SDValue();
 }
 



From echristo at apple.com  Thu Sep  8 17:17:40 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 08 Sep 2011 22:17:40 -0000
Subject: [llvm-commits] [llvm] r139325 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20110908221740.95B572A6C12D@llvm.org>

Author: echristo
Date: Thu Sep  8 17:17:40 2011
New Revision: 139325

URL: http://llvm.org/viewvc/llvm-project?rev=139325&view=rev
Log:
Formatting and typo.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=139325&r1=139324&r2=139325&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Sep  8 17:17:40 2011
@@ -594,7 +594,7 @@
     // If the fragment with the reference does not have a base symbol but meets
     // the simple way of dealing with this, in that it is a temporary symbol in
     // the same atom then it is assumed to be fully resolved.  This is needed so
-    // a relocation entry is not created and so the staitic linker does not
+    // a relocation entry is not created and so the static linker does not
     // mess up the reference later.
     else if(!FB.getAtom() &&
             SA.isTemporary() && SA.isInSection() && &SecA == &SecB){
@@ -627,7 +627,8 @@
   return false;
 }
 
-void MachObjectWriter::WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout) {
+void MachObjectWriter::WriteObject(MCAssembler &Asm,
+				   const MCAsmLayout &Layout) {
   unsigned NumSections = Asm.size();
 
   // The section data starts after the header, the segment load command (and



From wendling at apple.com  Thu Sep  8 17:32:43 2011
From: wendling at apple.com (Bill Wendling)
Date: Thu, 08 Sep 2011 15:32:43 -0700
Subject: [llvm-commits] gold plugin: report errors occured in
 lto_module_create_from_*
In-Reply-To: <CAOei5ReXr_vdqrupC=AvGfrpO+hG_TL+gz+J5T1T0gbu3cS4yw@mail.gmail.com>
References: <CAOei5RdN2tE5mb_fxUqRG+7o1dSWKnnh7KWuR2i8YgqDCH1cEg@mail.gmail.com>
	<CAOei5ReXr_vdqrupC=AvGfrpO+hG_TL+gz+J5T1T0gbu3cS4yw@mail.gmail.com>
Message-ID: <2BCC61FA-8748-4E2C-A4B8-DE8E0616CE00@apple.com>

Hi Krasin,

This looks okay. But could you reverse the error and ok bits?

    const char* msg = lto_get_error_message();
    if (msg) {
      (*message)(LDPL_ERROR, "Failed to create LTO module: %s", msg);
      return LDPS_ERR;
    }
    return LDPS_OK;

Or more concise:

    if (const char* msg = lto_get_error_message()) {
      (*message)(LDPL_ERROR, "Failed to create LTO module: %s", msg);
      return LDPS_ERR;
    }
    return LDPS_OK;


-bw

On Sep 8, 2011, at 1:49 PM, Ivan Krasin wrote:

> Friendly ping
> 
> On Thu, Sep 8, 2011 at 12:50 AM, Ivan Krasin <krasin at chromium.org> wrote:
>> Hi llvm team!
>> 
>> It appears that gold plugin does not check for errors occured in
>> lto_module_create_from_*. It just silently returns with LDPS_OK
>> status.
>> This patch makes it to report occurred errors (if any).
>> 
>> Is it fine to commit?
>> 
>> krasin
>> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From resistor at mac.com  Thu Sep  8 17:42:49 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 08 Sep 2011 22:42:49 -0000
Subject: [llvm-commits] [llvm] r139328 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt
Message-ID: <20110908224249.4A7F92A6C12C@llvm.org>

Author: resistor
Date: Thu Sep  8 17:42:49 2011
New Revision: 139328

URL: http://llvm.org/viewvc/llvm-project?rev=139328&view=rev
Log:
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139328&r1=139327&r2=139328&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Sep  8 17:42:49 2011
@@ -77,7 +77,7 @@
   EDInstInfo *getEDInfo() const;
 private:
   mutable std::vector<unsigned> ITBlock;
-  void AddThumbPredicate(MCInst&) const;
+  DecodeStatus AddThumbPredicate(MCInst&) const;
   void UpdateThumbVFPPredicate(MCInst&) const;
 };
 }
@@ -422,13 +422,20 @@
 // encoding, but rather get their predicates from IT context.  We need
 // to fix up the predicate operands using this context information as a
 // post-pass.
-void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
+MCDisassembler::DecodeStatus
+ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
   // A few instructions actually have predicates encoded in them.  Don't
   // try to overwrite it if we're seeing one of those.
   switch (MI.getOpcode()) {
     case ARM::tBcc:
     case ARM::t2Bcc:
-      return;
+      return Success;
+    case ARM::tCBZ:
+    case ARM::tCBNZ:
+      // Some instructions are not allowed in IT blocks.
+      if (!ITBlock.empty())
+        return SoftFail;
+      break;
     default:
       break;
   }
@@ -456,7 +463,7 @@
         MI.insert(I, MCOperand::CreateReg(0));
       else
         MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
-      return;
+      return Success;
     }
   }
 
@@ -466,6 +473,8 @@
     MI.insert(I, MCOperand::CreateReg(0));
   else
     MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
+
+  return Success;
 }
 
 // Thumb VFP instructions are a special case.  Because we share their
@@ -516,7 +525,7 @@
   DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 2;
-    AddThumbPredicate(MI);
+    Check(result, AddThumbPredicate(MI));
     return result;
   }
 
@@ -525,7 +534,7 @@
   if (result) {
     Size = 2;
     bool InITBlock = !ITBlock.empty();
-    AddThumbPredicate(MI);
+    Check(result, AddThumbPredicate(MI));
     AddThumb1SBit(MI, InITBlock);
     return result;
   }
@@ -534,7 +543,7 @@
   result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 2;
-    AddThumbPredicate(MI);
+    Check(result, AddThumbPredicate(MI));
 
     // If we find an IT instruction, we need to parse its condition
     // code and mask operands so that we can apply them correctly
@@ -575,7 +584,7 @@
   if (result != MCDisassembler::Fail) {
     Size = 4;
     bool InITBlock = ITBlock.size();
-    AddThumbPredicate(MI);
+    Check(result, AddThumbPredicate(MI));
     AddThumb1SBit(MI, InITBlock);
     return result;
   }
@@ -584,7 +593,7 @@
   result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
-    AddThumbPredicate(MI);
+    Check(result, AddThumbPredicate(MI));
     return result;
   }
 
@@ -600,7 +609,7 @@
   result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
   if (result != MCDisassembler::Fail) {
     Size = 4;
-    AddThumbPredicate(MI);
+    Check(result, AddThumbPredicate(MI));
     return result;
   }
 
@@ -612,7 +621,7 @@
     result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
     if (result != MCDisassembler::Fail) {
       Size = 4;
-      AddThumbPredicate(MI);
+      Check(result, AddThumbPredicate(MI));
       return result;
     }
   }
@@ -626,7 +635,7 @@
     result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
     if (result != MCDisassembler::Fail) {
       Size = 4;
-      AddThumbPredicate(MI);
+      Check(result, AddThumbPredicate(MI));
       return result;
     }
   }

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt?rev=139328&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt Thu Sep  8 17:42:49 2011
@@ -0,0 +1,5 @@
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding}
+
+# CBZ / CBNZ not allowed in IT block.
+
+0xdb 0xbf 0x42 0xbb



From resistor at mac.com  Thu Sep  8 17:48:37 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 08 Sep 2011 22:48:37 -0000
Subject: [llvm-commits] [llvm] r139329 -
	/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Message-ID: <20110908224837.F33012A6C12C@llvm.org>

Author: resistor
Date: Thu Sep  8 17:48:37 2011
New Revision: 139329

URL: http://llvm.org/viewvc/llvm-project?rev=139329&view=rev
Log:
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139329&r1=139328&r2=139329&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Sep  8 17:48:37 2011
@@ -429,12 +429,13 @@
   switch (MI.getOpcode()) {
     case ARM::tBcc:
     case ARM::t2Bcc:
-      return Success;
     case ARM::tCBZ:
     case ARM::tCBNZ:
-      // Some instructions are not allowed in IT blocks.
+      // Some instructions (mostly conditional branches) are not
+      // allowed in IT blocks.
       if (!ITBlock.empty())
         return SoftFail;
+      return Success;
       break;
     default:
       break;



From dpatel at apple.com  Thu Sep  8 17:59:09 2011
From: dpatel at apple.com (Devang Patel)
Date: Thu, 08 Sep 2011 22:59:09 -0000
Subject: [llvm-commits] [llvm] r139330 - in /llvm/trunk:
 include/llvm/CodeGen/FunctionLoweringInfo.h
 lib/CodeGen/SelectionDAG/FastISel.cpp
 lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 test/CodeGen/ARM/debug-info-arg.ll
Message-ID: <20110908225910.149792A6C12C@llvm.org>

Author: dpatel
Date: Thu Sep  8 17:59:09 2011
New Revision: 139330

URL: http://llvm.org/viewvc/llvm-project?rev=139330&view=rev
Log:
Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.

Added:
    llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll
Modified:
    llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h?rev=139330&r1=139329&r2=139330&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h Thu Sep  8 17:59:09 2011
@@ -199,12 +199,12 @@
     LiveOutRegInfo[Reg].IsValid = false;
   }
 
-  /// setByValArgumentFrameIndex - Record frame index for the byval
+  /// setArgumentFrameIndex - Record frame index for the byval
   /// argument.
-  void setByValArgumentFrameIndex(const Argument *A, int FI);
+  void setArgumentFrameIndex(const Argument *A, int FI);
   
-  /// getByValArgumentFrameIndex - Get frame index for the byval argument.
-  int getByValArgumentFrameIndex(const Argument *A);
+  /// getArgumentFrameIndex - Get frame index for the byval argument.
+  int getArgumentFrameIndex(const Argument *A);
 
 private:
   /// LiveOutRegInfo - Information about live out vregs.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=139330&r1=139329&r2=139330&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Sep  8 17:59:09 2011
@@ -531,13 +531,10 @@
     unsigned Reg = 0;
     unsigned Offset = 0;
     if (const Argument *Arg = dyn_cast<Argument>(Address)) {
-      if (Arg->hasByValAttr()) {
-        // Byval arguments' frame index is recorded during argument lowering.
-        // Use this info directly.
-        Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
-        if (Offset)
-          Reg = TRI.getFrameRegister(*FuncInfo.MF);
-      }
+      // Some arguments' frame index is recorded during argument lowering.
+      Offset = FuncInfo.getArgumentFrameIndex(Arg);
+      if (Offset)
+	Reg = TRI.getFrameRegister(*FuncInfo.MF);
     }
     if (!Reg)
       Reg = getRegForValue(Address);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=139330&r1=139329&r2=139330&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Thu Sep  8 17:59:09 2011
@@ -351,20 +351,18 @@
   }
 }
 
-/// setByValArgumentFrameIndex - Record frame index for the byval
+/// setArgumentFrameIndex - Record frame index for the byval
 /// argument. This overrides previous frame index entry for this argument,
 /// if any.
-void FunctionLoweringInfo::setByValArgumentFrameIndex(const Argument *A,
+void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
                                                       int FI) {
-  assert (A->hasByValAttr() && "Argument does not have byval attribute!");
   ByValArgFrameIndexMap[A] = FI;
 }
 
-/// getByValArgumentFrameIndex - Get frame index for the byval argument.
+/// getArgumentFrameIndex - Get frame index for the byval argument.
 /// If the argument does not have any assigned frame index then 0 is
 /// returned.
-int FunctionLoweringInfo::getByValArgumentFrameIndex(const Argument *A) {
-  assert (A->hasByValAttr() && "Argument does not have byval attribute!");
+int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
   DenseMap<const Argument *, int>::iterator I =
     ByValArgFrameIndexMap.find(A);
   if (I != ByValArgFrameIndexMap.end())

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=139330&r1=139329&r2=139330&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Sep  8 17:59:09 2011
@@ -4394,17 +4394,12 @@
     return false;
 
   unsigned Reg = 0;
-  if (Arg->hasByValAttr()) {
-    // Byval arguments' frame index is recorded during argument lowering.
-    // Use this info directly.
-    Reg = TRI->getFrameRegister(MF);
-    Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
-    // If byval argument ofset is not recorded then ignore this.
-    if (!Offset)
-      Reg = 0;
-  }
+  // Some arguments' frame index is recorded during argument lowering.
+  Offset = FuncInfo.getArgumentFrameIndex(Arg);
+  if (Offset)
+      Reg = TRI->getFrameRegister(MF);
 
-  if (N.getNode()) {
+  if (!Reg && N.getNode()) {
     if (N.getOpcode() == ISD::CopyFromReg)
       Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
     else
@@ -6733,15 +6728,22 @@
     if (ArgValues.empty())
       continue;
 
-    // Note down frame index for byval arguments.
-    if (I->hasByValAttr())
-      if (FrameIndexSDNode *FI =
-          dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
-        FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
+    // Note down frame index.
+    if (FrameIndexSDNode *FI =
+	dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
+      FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
 
     SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
                                      SDB->getCurDebugLoc());
+
     SDB->setValue(I, Res);
+    if (!EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
+      if (LoadSDNode *LNode = 
+          dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
+        if (FrameIndexSDNode *FI =
+            dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
+        FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
+    }
 
     // If this argument is live outside of the entry block, insert a copy from
     // wherever we got it to the vreg that other BB's will reference it as.

Added: llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll?rev=139330&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll Thu Sep  8 17:59:09 2011
@@ -0,0 +1,65 @@
+; RUN: llc < %s | FileCheck %s
+; Test to check argument y's debug info uses FI
+; Radar 10048772
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32"
+target triple = "thumbv7-apple-macosx10.7.0"
+
+%struct.tag_s = type { i32, i32, i32 }
+
+define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64 %y, %struct.tag_s* nocapture %ptr1, %struct.tag_s* nocapture %ptr2) nounwind ssp {
+  tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %this}, i64 0, metadata !5), !dbg !20
+  tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %c}, i64 0, metadata !13), !dbg !21
+  tail call void @llvm.dbg.value(metadata !{i64 %x}, i64 0, metadata !14), !dbg !22
+  tail call void @llvm.dbg.value(metadata !{i64 %y}, i64 0, metadata !17), !dbg !23
+;CHECK:	@DEBUG_VALUE: foo:y <- R7+4294967295
+  tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr1}, i64 0, metadata !18), !dbg !24
+  tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr2}, i64 0, metadata !19), !dbg !25
+  %1 = icmp eq %struct.tag_s* %c, null, !dbg !26
+  br i1 %1, label %3, label %2, !dbg !26
+
+; <label>:2                                       ; preds = %0
+  tail call void @foobar(i64 %x, i64 %y) nounwind, !dbg !28
+  br label %3, !dbg !28
+
+; <label>:3                                       ; preds = %0, %2
+  ret void, !dbg !29
+}
+
+declare void @foobar(i64, i64)
+
+declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
+
+!llvm.dbg.cu = !{!0}
+!llvm.dbg.sp = !{!1}
+!llvm.dbg.lv.foo = !{!5, !13, !14, !17, !18, !19}
+
+!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"one.c", metadata !"/Volumes/Athwagate/R10048772", metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, null, null} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 589865, metadata !"one.c", metadata !"/Volumes/Athwagate/R10048772", metadata !0} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!4 = metadata !{null}
+!5 = metadata !{i32 590081, metadata !1, metadata !"this", metadata !2, i32 16777227, metadata !6, i32 0} ; [ DW_TAG_arg_variable ]
+!6 = metadata !{i32 589839, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ]
+!7 = metadata !{i32 589843, metadata !0, metadata !"tag_s", metadata !2, i32 5, i64 96, i64 32, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_structure_type ]
+!8 = metadata !{metadata !9, metadata !11, metadata !12}
+!9 = metadata !{i32 589837, metadata !7, metadata !"x", metadata !2, i32 6, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ]
+!10 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!11 = metadata !{i32 589837, metadata !7, metadata !"y", metadata !2, i32 7, i64 32, i64 32, i64 32, i32 0, metadata !10} ; [ DW_TAG_member ]
+!12 = metadata !{i32 589837, metadata !7, metadata !"z", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !10} ; [ DW_TAG_member ]
+!13 = metadata !{i32 590081, metadata !1, metadata !"c", metadata !2, i32 33554443, metadata !6, i32 0} ; [ DW_TAG_arg_variable ]
+!14 = metadata !{i32 590081, metadata !1, metadata !"x", metadata !2, i32 50331659, metadata !15, i32 0} ; [ DW_TAG_arg_variable ]
+!15 = metadata !{i32 589846, metadata !0, metadata !"UInt64", metadata !2, i32 1, i64 0, i64 0, i64 0, i32 0, metadata !16} ; [ DW_TAG_typedef ]
+!16 = metadata !{i32 589860, metadata !0, metadata !"long long unsigned int", null, i32 0, i64 64, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!17 = metadata !{i32 590081, metadata !1, metadata !"y", metadata !2, i32 67108875, metadata !15, i32 0} ; [ DW_TAG_arg_variable ]
+!18 = metadata !{i32 590081, metadata !1, metadata !"ptr1", metadata !2, i32 83886091, metadata !6, i32 0} ; [ DW_TAG_arg_variable ]
+!19 = metadata !{i32 590081, metadata !1, metadata !"ptr2", metadata !2, i32 100663307, metadata !6, i32 0} ; [ DW_TAG_arg_variable ]
+!20 = metadata !{i32 11, i32 24, metadata !1, null}
+!21 = metadata !{i32 11, i32 44, metadata !1, null}
+!22 = metadata !{i32 11, i32 54, metadata !1, null}
+!23 = metadata !{i32 11, i32 64, metadata !1, null}
+!24 = metadata !{i32 11, i32 81, metadata !1, null}
+!25 = metadata !{i32 11, i32 101, metadata !1, null}
+!26 = metadata !{i32 12, i32 3, metadata !27, null}
+!27 = metadata !{i32 589835, metadata !1, i32 11, i32 107, metadata !2, i32 0} ; [ DW_TAG_lexical_block ]
+!28 = metadata !{i32 13, i32 5, metadata !27, null}
+!29 = metadata !{i32 14, i32 1, metadata !27, null}



From krasin at google.com  Thu Sep  8 18:22:00 2011
From: krasin at google.com (Ivan Krasin)
Date: Thu, 8 Sep 2011 16:22:00 -0700
Subject: [llvm-commits] gold plugin: report errors occured in
	lto_module_create_from_*
In-Reply-To: <2BCC61FA-8748-4E2C-A4B8-DE8E0616CE00@apple.com>
References: <CAOei5RdN2tE5mb_fxUqRG+7o1dSWKnnh7KWuR2i8YgqDCH1cEg@mail.gmail.com>
	<CAOei5ReXr_vdqrupC=AvGfrpO+hG_TL+gz+J5T1T0gbu3cS4yw@mail.gmail.com>
	<2BCC61FA-8748-4E2C-A4B8-DE8E0616CE00@apple.com>
Message-ID: <CAOei5Rc-dKqLNdEqt+0uPn7QOd_GdPEd9xBQKZ-ScCbFvwBGsQ@mail.gmail.com>

Hi Bill,

On Thu, Sep 8, 2011 at 3:32 PM, Bill Wendling <wendling at apple.com> wrote:
> Hi Krasin,
>
> This looks okay. But could you reverse the error and ok bits?
Your concern is valid (I ought to realize it myself!). Please, find
the proper patch attached.

krasin

>
> ? ?const char* msg = lto_get_error_message();
> ? ?if (msg) {
> ? ? ?(*message)(LDPL_ERROR, "Failed to create LTO module: %s", msg);
> ? ? ?return LDPS_ERR;
> ? ?}
> ? ?return LDPS_OK;
>
> Or more concise:
>
> ? ?if (const char* msg = lto_get_error_message()) {
> ? ? ?(*message)(LDPL_ERROR, "Failed to create LTO module: %s", msg);
> ? ? ?return LDPS_ERR;
> ? ?}
> ? ?return LDPS_OK;
>
>
> -bw
>
> On Sep 8, 2011, at 1:49 PM, Ivan Krasin wrote:
>
>> Friendly ping
>>
>> On Thu, Sep 8, 2011 at 12:50 AM, Ivan Krasin <krasin at chromium.org> wrote:
>>> Hi llvm team!
>>>
>>> It appears that gold plugin does not check for errors occured in
>>> lto_module_create_from_*. It just silently returns with LDPS_OK
>>> status.
>>> This patch makes it to report occurred errors (if any).
>>>
>>> Is it fine to commit?
>>>
>>> krasin
>>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
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From gkistanova at gmail.com  Thu Sep  8 18:25:55 2011
From: gkistanova at gmail.com (Galina Kistanova)
Date: Thu, 8 Sep 2011 16:25:55 -0700
Subject: [llvm-commits] Some builders are available here
Message-ID: <CAJ8eiNxkiZV7XGGLqr+ddRd4EkzOrhTESxMawcy+ubordgLG4w@mail.gmail.com>

Hello everyone,

As a temporally solution, subset of builders from llvm buildmaster are
available here:
http://63.145.236.72:8011
This temporally master is not reporting to IRC.

Thanks

Galina

From chandlerc at google.com  Thu Sep  8 18:35:36 2011
From: chandlerc at google.com (Chandler Carruth)
Date: Thu, 8 Sep 2011 16:35:36 -0700
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
Message-ID: <CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>

FYI,

I've looked again at this patch recently, and talked to several others about
it...

I think there are some big issues with the implementation, bit I think they
could probably be addressed. The one that I see the most is the x86 assembly
just being dumped as a blob. I think that really needs to be resolved before
this can move forward.

It seems like this should be do-able in some way with the llvm.trap
intrinsic. If anything, we might need another intrinsic or an extension of
llvm.trap that allows feeding the SIGILL signal handler the
data arguments it needs; I'd need to read up on exactly what is required for
that to figure out how best to represent that in IR, but it shouldn't be
that hard.

That said, maybe to improve the discussion of the patch and make reviewing
it easier, you could just switch to emitting the call to the runtime library
function in all cases? That should be a strictly simpler patch, and then how
to improve performance by avoiding the runtime call can be a followup.

Maybe others could comment on other implementation issues? I'm sadly not an
expert at LLVM...
-------------- next part --------------
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From echristo at apple.com  Thu Sep  8 18:43:06 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 08 Sep 2011 16:43:06 -0700
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
Message-ID: <E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>


On Sep 8, 2011, at 4:35 PM, Chandler Carruth wrote:

> FYI,
> 
> I've looked again at this patch recently, and talked to several others about it...
> 
> I think there are some big issues with the implementation, bit I think they could probably be addressed. The one that I see the most is the x86 assembly just being dumped as a blob. I think that really needs to be resolved before this can move forward.
> 
> It seems like this should be do-able in some way with the llvm.trap intrinsic. If anything, we might need another intrinsic or an extension of llvm.trap that allows feeding the SIGILL signal handler the data arguments it needs; I'd need to read up on exactly what is required for that to figure out how best to represent that in IR, but it shouldn't be that hard.
> 
> That said, maybe to improve the discussion of the patch and make reviewing it easier, you could just switch to emitting the call to the runtime library function in all cases? That should be a strictly simpler patch, and then how to improve performance by avoiding the runtime call can be a followup.
> 

This encompasses most of my concerns with the patch.

> Maybe others could comment on other implementation issues? I'm sadly not an expert at LLVM...

In a glance I didn't see a lot, but the other bits were somewhat hiding it. How about when we get a new patch we can take a bit more of a look at it.

-eric

From wendling at apple.com  Thu Sep  8 19:13:20 2011
From: wendling at apple.com (Bill Wendling)
Date: Thu, 08 Sep 2011 17:13:20 -0700
Subject: [llvm-commits] gold plugin: report errors occured in
 lto_module_create_from_*
In-Reply-To: <CAOei5Rc-dKqLNdEqt+0uPn7QOd_GdPEd9xBQKZ-ScCbFvwBGsQ@mail.gmail.com>
References: <CAOei5RdN2tE5mb_fxUqRG+7o1dSWKnnh7KWuR2i8YgqDCH1cEg@mail.gmail.com>
	<CAOei5ReXr_vdqrupC=AvGfrpO+hG_TL+gz+J5T1T0gbu3cS4yw@mail.gmail.com>
	<2BCC61FA-8748-4E2C-A4B8-DE8E0616CE00@apple.com>
	<CAOei5Rc-dKqLNdEqt+0uPn7QOd_GdPEd9xBQKZ-ScCbFvwBGsQ@mail.gmail.com>
Message-ID: <65C2DAFD-1E7C-4328-A6CB-23B9FA5CA741@apple.com>

That looks good. Do you have commit access?

-bw

On Sep 8, 2011, at 4:22 PM, Ivan Krasin wrote:

> Hi Bill,
> 
> On Thu, Sep 8, 2011 at 3:32 PM, Bill Wendling <wendling at apple.com> wrote:
>> Hi Krasin,
>> 
>> This looks okay. But could you reverse the error and ok bits?
> Your concern is valid (I ought to realize it myself!). Please, find
> the proper patch attached.
> 
> krasin
> 
>> 
>>    const char* msg = lto_get_error_message();
>>    if (msg) {
>>      (*message)(LDPL_ERROR, "Failed to create LTO module: %s", msg);
>>      return LDPS_ERR;
>>    }
>>    return LDPS_OK;
>> 
>> Or more concise:
>> 
>>    if (const char* msg = lto_get_error_message()) {
>>      (*message)(LDPL_ERROR, "Failed to create LTO module: %s", msg);
>>      return LDPS_ERR;
>>    }
>>    return LDPS_OK;
>> 
>> 
>> -bw
>> 
>> On Sep 8, 2011, at 1:49 PM, Ivan Krasin wrote:
>> 
>>> Friendly ping
>>> 
>>> On Thu, Sep 8, 2011 at 12:50 AM, Ivan Krasin <krasin at chromium.org> wrote:
>>>> Hi llvm team!
>>>> 
>>>> It appears that gold plugin does not check for errors occured in
>>>> lto_module_create_from_*. It just silently returns with LDPS_OK
>>>> status.
>>>> This patch makes it to report occurred errors (if any).
>>>> 
>>>> Is it fine to commit?
>>>> 
>>>> krasin
>>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
>> 
> <gold_err_ok.patch>


From kcc at google.com  Thu Sep  8 19:14:38 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 8 Sep 2011 17:14:38 -0700
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
Message-ID: <CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>

On Thu, Sep 8, 2011 at 4:43 PM, Eric Christopher <echristo at apple.com> wrote:

>
> On Sep 8, 2011, at 4:35 PM, Chandler Carruth wrote:
>
> > FYI,
> >
> > I've looked again at this patch recently, and talked to several others
> about it...
> >
> > I think there are some big issues with the implementation, bit I think
> they could probably be addressed. The one that I see the most is the x86
> assembly just being dumped as a blob. I think that really needs to be
> resolved before this can move forward.
> >
> > It seems like this should be do-able in some way with the llvm.trap
> intrinsic. If anything, we might need another intrinsic or an extension of
> llvm.trap that allows feeding the SIGILL signal handler the data arguments
> it needs; I'd need to read up on exactly what is required for that to figure
> out how best to represent that in IR, but it shouldn't be that hard.
> >
> > That said, maybe to improve the discussion of the patch and make
> reviewing it easier, you could just switch to emitting the call to the
> runtime library function in all cases? That should be a strictly simpler
> patch, and then how to improve performance by avoiding the runtime call can
> be a followup.
> >
>
> This encompasses most of my concerns with the patch.
>
> > Maybe others could comment on other implementation issues? I'm sadly not
> an expert at LLVM...
>
> In a glance I didn't see a lot, but the other bits were somewhat hiding it.
> How about when we get a new patch we can take a bit more of a look at it.
>

I dropped the assembly part and updated the patch at
http://codereview.appspot.com/4867059/ (also in attachment).
We can figure out how to make it more efficient later (something
like llvm.trap intrinsic with a parameter).

This patch is 570 LOC plus few lines of trivial changes and a test.
It implements only basic functionality: detection of out-of-bounds and
use-after-free in heap.

The complete version of LLVM pass is ~1000 LOC (
http://code.google.com/p/address-sanitizer/source/browse/trunk/llvm/AddressSanitizer.cpp
).
It also handles out-of-bounds for stack and global objects and (recently
added) stack use-after-return bugs.

--kcc



>
> -eric
>
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From ahatanak at gmail.com  Thu Sep  8 19:13:35 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 09 Sep 2011 00:13:35 -0000
Subject: [llvm-commits] [llvm] r139339 - in /llvm/trunk/lib/Target/Mips:
 InstPrinter/MipsInstPrinter.cpp InstPrinter/MipsInstPrinter.h
 MipsMCInstLower.h
Message-ID: <20110909001335.D9EA12A6C12C@llvm.org>

Author: ahatanak
Date: Thu Sep  8 19:13:35 2011
New Revision: 139339

URL: http://llvm.org/viewvc/llvm-project?rev=139339&view=rev
Log:
80 columns.

Modified:
    llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
    llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.h
    llvm/trunk/lib/Target/Mips/MipsMCInstLower.h

Modified: llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp?rev=139339&r1=139338&r2=139339&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp Thu Sep  8 19:13:35 2011
@@ -1,4 +1,4 @@
-//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax --------===//
+//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
 //
 //                     The LLVM Compiler Infrastructure
 //

Modified: llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.h?rev=139339&r1=139338&r2=139339&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.h (original)
+++ llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.h Thu Sep  8 19:13:35 2011
@@ -1,4 +1,4 @@
-//===-- MipsInstPrinter.h - Convert Mips MCInst to assembly syntax ----------===//
+//===-- MipsInstPrinter.h - Convert Mips MCInst to assembly syntax --------===//
 //
 //                     The LLVM Compiler Infrastructure
 //

Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.h?rev=139339&r1=139338&r2=139339&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Thu Sep  8 19:13:35 2011
@@ -1,4 +1,4 @@
-//===-- MipsMCInstLower.h - Lower MachineInstr to MCInst -------------------===//
+//===-- MipsMCInstLower.h - Lower MachineInstr to MCInst -------------------==//
 //
 //                     The LLVM Compiler Infrastructure
 //



From krasin at chromium.org  Thu Sep  8 19:14:04 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Fri, 09 Sep 2011 00:14:04 -0000
Subject: [llvm-commits] [llvm] r139340 -
	/llvm/trunk/tools/gold/gold-plugin.cpp
Message-ID: <20110909001404.29F222A6C12C@llvm.org>

Author: krasin
Date: Thu Sep  8 19:14:04 2011
New Revision: 139340

URL: http://llvm.org/viewvc/llvm-project?rev=139340&view=rev
Log:
gold plugin: report errors occured in lto_module_create_from_*


Modified:
    llvm/trunk/tools/gold/gold-plugin.cpp

Modified: llvm/trunk/tools/gold/gold-plugin.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=139340&r1=139339&r2=139340&view=diff
==============================================================================
--- llvm/trunk/tools/gold/gold-plugin.cpp (original)
+++ llvm/trunk/tools/gold/gold-plugin.cpp Thu Sep  8 19:14:04 2011
@@ -251,8 +251,13 @@
   } else {
     M = lto_module_create_from_fd(file->fd, file->name, file->filesize);
   }
-  if (!M)
+  if (!M) {
+    if (const char* msg = lto_get_error_message()) {
+      (*message)(LDPL_ERROR, "Failed to create LTO module: %s", msg);
+      return LDPS_ERR;
+    }
     return LDPS_OK;
+  }
 
   *claimed = 1;
   Modules.resize(Modules.size() + 1);



From krasin at google.com  Thu Sep  8 19:15:50 2011
From: krasin at google.com (Ivan Krasin)
Date: Thu, 8 Sep 2011 17:15:50 -0700
Subject: [llvm-commits] gold plugin: report errors occured in
	lto_module_create_from_*
In-Reply-To: <65C2DAFD-1E7C-4328-A6CB-23B9FA5CA741@apple.com>
References: <CAOei5RdN2tE5mb_fxUqRG+7o1dSWKnnh7KWuR2i8YgqDCH1cEg@mail.gmail.com>
	<CAOei5ReXr_vdqrupC=AvGfrpO+hG_TL+gz+J5T1T0gbu3cS4yw@mail.gmail.com>
	<2BCC61FA-8748-4E2C-A4B8-DE8E0616CE00@apple.com>
	<CAOei5Rc-dKqLNdEqt+0uPn7QOd_GdPEd9xBQKZ-ScCbFvwBGsQ@mail.gmail.com>
	<65C2DAFD-1E7C-4328-A6CB-23B9FA5CA741@apple.com>
Message-ID: <CAOei5RdhW-4tsNAUDh6rqGDWNDK_xTgyhd-7EUUCopbui5YXkg@mail.gmail.com>

On Thu, Sep 8, 2011 at 5:13 PM, Bill Wendling <wendling at apple.com> wrote:
> That looks good. Do you have commit access?
Yes, I have. Thank you for the review, r139340.

>
> -bw
>
> On Sep 8, 2011, at 4:22 PM, Ivan Krasin wrote:
>
>> Hi Bill,
>>
>> On Thu, Sep 8, 2011 at 3:32 PM, Bill Wendling <wendling at apple.com> wrote:
>>> Hi Krasin,
>>>
>>> This looks okay. But could you reverse the error and ok bits?
>> Your concern is valid (I ought to realize it myself!). Please, find
>> the proper patch attached.
>>
>> krasin
>>
>>>
>>> ? ?const char* msg = lto_get_error_message();
>>> ? ?if (msg) {
>>> ? ? ?(*message)(LDPL_ERROR, "Failed to create LTO module: %s", msg);
>>> ? ? ?return LDPS_ERR;
>>> ? ?}
>>> ? ?return LDPS_OK;
>>>
>>> Or more concise:
>>>
>>> ? ?if (const char* msg = lto_get_error_message()) {
>>> ? ? ?(*message)(LDPL_ERROR, "Failed to create LTO module: %s", msg);
>>> ? ? ?return LDPS_ERR;
>>> ? ?}
>>> ? ?return LDPS_OK;
>>>
>>>
>>> -bw
>>>
>>> On Sep 8, 2011, at 1:49 PM, Ivan Krasin wrote:
>>>
>>>> Friendly ping
>>>>
>>>> On Thu, Sep 8, 2011 at 12:50 AM, Ivan Krasin <krasin at chromium.org> wrote:
>>>>> Hi llvm team!
>>>>>
>>>>> It appears that gold plugin does not check for errors occured in
>>>>> lto_module_create_from_*. It just silently returns with LDPS_OK
>>>>> status.
>>>>> This patch makes it to report occurred errors (if any).
>>>>>
>>>>> Is it fine to commit?
>>>>>
>>>>> krasin
>>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
>>>
>> <gold_err_ok.patch>
>
>


From nicholas at mxc.ca  Thu Sep  8 19:16:50 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Fri, 09 Sep 2011 00:16:50 -0000
Subject: [llvm-commits] [llvm] r139341 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20110909001650.73EA02A6C12C@llvm.org>

Author: nicholas
Date: Thu Sep  8 19:16:50 2011
New Revision: 139341

URL: http://llvm.org/viewvc/llvm-project?rev=139341&view=rev
Log:
Fix release build:
MachOObjectFile.cpp:524: error: unused variable 'NumLoadCommands' [-Wunused-variable]

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=139341&r1=139340&r2=139341&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Thu Sep  8 19:16:50 2011
@@ -521,12 +521,11 @@
   DataRefImpl Sym;
   Sym.d.a = Sym.d.b = 0;
   moveToNextSymbol(Sym);
-  uint32_t NumLoadCommands = MachOObj->getHeader().NumLoadCommands;
   if (isExtern) {
     for (unsigned i = 0; i < SymbolIdx; i++) {
       Sym.d.b++;
       moveToNextSymbol(Sym);
-      assert(Sym.d.a < NumLoadCommands &&
+      assert(Sym.d.a < MachOObj->getHeader().NumLoadCommands &&
              "Relocation symbol index out of range!");
     }
   }
@@ -625,4 +624,3 @@
 }
 
 } // end namespace llvm
-



From benny.kra at googlemail.com  Thu Sep  8 19:22:05 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Fri, 09 Sep 2011 00:22:05 -0000
Subject: [llvm-commits] [llvm] r139343 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20110909002205.B51CF2A6C12C@llvm.org>

Author: d0k
Date: Thu Sep  8 19:22:05 2011
New Revision: 139343

URL: http://llvm.org/viewvc/llvm-project?rev=139343&view=rev
Log:
Remove dead code.

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=139343&r1=139342&r2=139343&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Thu Sep  8 19:22:05 2011
@@ -104,14 +104,6 @@
   uint32_t LoadCommandCount = MachOObj->getHeader().NumLoadCommands;
   while (DRI.d.a < LoadCommandCount) {
     Sections.push_back(DRI);
-    uint64_t Addr;
-    uint64_t Size;
-    StringRef Name;
-    getSectionAddress(DRI, Addr);
-    getSectionSize(DRI, Size);
-    getSectionName(DRI, Name);
-    InMemoryStruct<macho::Section> Sect;
-    getSection(DRI, Sect);
     DRI.d.b++;
     moveToNextSection(DRI);
   }



From echristo at apple.com  Thu Sep  8 19:38:19 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 08 Sep 2011 17:38:19 -0700
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
Message-ID: <1137D6EF-A4A8-4C7B-AAA7-831E5E36124F@apple.com>


On Sep 8, 2011, at 5:14 PM, Kostya Serebryany wrote:

> 
> 
> On Thu, Sep 8, 2011 at 4:43 PM, Eric Christopher <echristo at apple.com> wrote:
> 
> On Sep 8, 2011, at 4:35 PM, Chandler Carruth wrote:
> 
> > FYI,
> >
> > I've looked again at this patch recently, and talked to several others about it...
> >
> > I think there are some big issues with the implementation, bit I think they could probably be addressed. The one that I see the most is the x86 assembly just being dumped as a blob. I think that really needs to be resolved before this can move forward.
> >
> > It seems like this should be do-able in some way with the llvm.trap intrinsic. If anything, we might need another intrinsic or an extension of llvm.trap that allows feeding the SIGILL signal handler the data arguments it needs; I'd need to read up on exactly what is required for that to figure out how best to represent that in IR, but it shouldn't be that hard.
> >
> > That said, maybe to improve the discussion of the patch and make reviewing it easier, you could just switch to emitting the call to the runtime library function in all cases? That should be a strictly simpler patch, and then how to improve performance by avoiding the runtime call can be a followup.
> >
> 
> This encompasses most of my concerns with the patch.
> 
> > Maybe others could comment on other implementation issues? I'm sadly not an expert at LLVM...
> 
> In a glance I didn't see a lot, but the other bits were somewhat hiding it. How about when we get a new patch we can take a bit more of a look at it.
> 
> I dropped the assembly part and updated the patch at http://codereview.appspot.com/4867059/ (also in attachment).
> We can figure out how to make it more efficient later (something like llvm.trap intrinsic with a parameter).
> 
> This patch is 570 LOC plus few lines of trivial changes and a test.
> It implements only basic functionality: detection of out-of-bounds and use-after-free in heap.
> 
> The complete version of LLVM pass is ~1000 LOC (http://code.google.com/p/address-sanitizer/source/browse/trunk/llvm/AddressSanitizer.cpp).
> It also handles out-of-bounds for stack and global objects and (recently added) stack use-after-return bugs. 

Some somewhat trivial issues:

a) Please go ahead and hide the non-user visible flags.

b) Not a big fan of this style of avoid 80-col wrap:

+Instruction *AddressSanitizer::generateCrashCode(
+    IRBuilder<> &IRB, Value *Addr, int TelltaleValue) {

c) +  // which will be lowered to a cusom assembly.

s/cusom/custom

d) 

+  if (TypeSize != 8 && TypeSize != 16 &&
+      TypeSize != 32 && TypeSize != 64 && TypeSize != 128) {
+    // TODO(kcc): do something better.
+    return;
+  }

What's the reason behind this?

Perhaps not so trivial:

a) Where are the asan_* functions? Where are they supposed to live?

I'll probably have more, but it's a start and the discussion on the library functions probably should happen sooner rather than later.

-eric
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From eli.friedman at gmail.com  Thu Sep  8 19:46:25 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 8 Sep 2011 17:46:25 -0700
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
Message-ID: <CAJdarcH-q+Hx78BH1uxANio1uwAJ9pvf2NKL-sHNDCesKJaGYw@mail.gmail.com>

On Thu, Sep 8, 2011 at 5:14 PM, Kostya Serebryany <kcc at google.com> wrote:
>
>
> On Thu, Sep 8, 2011 at 4:43 PM, Eric Christopher <echristo at apple.com> wrote:
>>
>> On Sep 8, 2011, at 4:35 PM, Chandler Carruth wrote:
>>
>> > FYI,
>> >
>> > I've looked again at this patch recently, and talked to several others
>> > about it...
>> >
>> > I think there are some big issues with the implementation, bit I think
>> > they could probably be addressed. The one that I see the most is the x86
>> > assembly just being dumped as a blob. I think that really needs to be
>> > resolved before this can move forward.
>> >
>> > It seems like this should be do-able in some way with the llvm.trap
>> > intrinsic. If anything, we might need another intrinsic or an extension of
>> > llvm.trap that allows feeding the SIGILL signal handler the data arguments
>> > it needs; I'd need to read up on exactly what is required for that to figure
>> > out how best to represent that in IR, but it shouldn't be that hard.
>> >
>> > That said, maybe to improve the discussion of the patch and make
>> > reviewing it easier, you could just switch to emitting the call to the
>> > runtime library function in all cases? That should be a strictly simpler
>> > patch, and then how to improve performance by avoiding the runtime call can
>> > be a followup.
>> >
>>
>> This encompasses most of my concerns with the patch.
>>
>> > Maybe others could comment on other implementation issues? I'm sadly not
>> > an expert at LLVM...
>>
>> In a glance I didn't see a lot, but the other bits were somewhat hiding
>> it. How about when we get a new patch we can take a bit more of a look at
>> it.
>
> I dropped the assembly part and?updated the patch
> at?http://codereview.appspot.com/4867059/?(also in attachment).
> We can figure out how to make it more efficient later (something
> like?llvm.trap intrinsic with a parameter).
> This patch is 570 LOC plus few lines of trivial changes and a test.
> It implements only basic functionality: detection of out-of-bounds and
> use-after-free in heap.

A couple review comments:

AddressSanitizer::appendToGlobalCtors is messy at best; is there
really no better way to get the asan init function to run when it
needs to?

Please get rid of blockHasException and the dependent code; the
eh_exception intrinsic is going away very soon, and you shouldn't run
into similar issues with the new exception handling framework.

+  GlobalValue *asan_mapping_offset =
+      new GlobalVariable(M, IntPtrTy, true, GlobalValue::LinkOnceODRLinkage,
+                     ConstantInt::get(IntPtrTy, 1ULL << MappingOffsetLog),
+                     "__asan_mapping_offset");
+  GlobalValue *asan_mapping_scale =
+      new GlobalVariable(M, IntPtrTy, true, GlobalValue::LinkOnceODRLinkage,
+                         ConstantInt::get(IntPtrTy, MappingScale),
+                         "__asan_mapping_scale");

If you use WeakLinkage for these, you won't need the fake loads.

-Eli


From kcc at google.com  Thu Sep  8 19:48:00 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 8 Sep 2011 17:48:00 -0700
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <1137D6EF-A4A8-4C7B-AAA7-831E5E36124F@apple.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
	<1137D6EF-A4A8-4C7B-AAA7-831E5E36124F@apple.com>
Message-ID: <CAN=P9phn2dnY78GOAPcYA2nLE=5BVoeLTqwKsZ-k-bYDSTkdFw@mail.gmail.com>

>
> Some somewhat trivial issues:
>
> a) Please go ahead and hide the non-user visible flags.
>

How? (sorry for ignorance)


>
> b) Not a big fan of this style of avoid 80-col wrap:
>
> +Instruction *AddressSanitizer::generateCrashCode(
> +    IRBuilder<> &IRB, Value *Addr, int TelltaleValue) {
>

Hmmm. This is in the coding style, isn't it??


>
> c) +  // which will be lowered to a cusom assembly.
>
> s/cusom/custom
>

fixed.


>
> d)
>
> +  if (TypeSize != 8 && TypeSize != 16 &&
> +      TypeSize != 32 && TypeSize != 64 && TypeSize != 128) {
> +    // TODO(kcc): do something better.
> +    return;
> +  }
>
> What's the reason behind this?
>

We may have a load of some different size, can't we?
E.g. size==1 will indicate that we are actually loading something like a bit
field.



>
> Perhaps not so trivial:
>
> a) Where are the asan_* functions? Where are they supposed to live?
>

There is the whole run-time library, which was described in my initial post
3 months ago.
http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-June/040800.html
The code resides in
http://code.google.com/p/address-sanitizer/source/browse/#svn%2Ftrunk%2Fasan
I'd be willing to contribute this code to LLVM as well, but it'll have to be
a separate thing.
--kcc



>
> I'll probably have more, but it's a start and the discussion on the library
> functions probably should happen sooner rather than later.
>
> -eric
>
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From kcc at google.com  Thu Sep  8 19:57:34 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 8 Sep 2011 17:57:34 -0700
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <CAJdarcH-q+Hx78BH1uxANio1uwAJ9pvf2NKL-sHNDCesKJaGYw@mail.gmail.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
	<CAJdarcH-q+Hx78BH1uxANio1uwAJ9pvf2NKL-sHNDCesKJaGYw@mail.gmail.com>
Message-ID: <CAN=P9phTgbv3a2TKKSDGcPNqxBP4VO+B2p+bHN5ikzcU2ZSsEg@mail.gmail.com>

>
>
>
> A couple review comments:
>
> AddressSanitizer::appendToGlobalCtors is messy at best;


Agree (the code is stolen from some other part of LLVM and fixed to actually
work).

is there
> really no better way to get the asan init function to run when it
> needs to?
>

I see no other way other than to append to llvm.global_ctors.
Given that I didn't find whether LLVM guaranties the particular order of
CTOR execution, I have to call them twice, at the beginning and at the end
of llvm.global_ctors
Suggestions?


>
> Please get rid of blockHasException and the dependent code; the
> eh_exception intrinsic is going away very soon, and you shouldn't run
> into similar issues with the new exception handling framework.
>

Done.



>
> +  GlobalValue *asan_mapping_offset =
> +      new GlobalVariable(M, IntPtrTy, true,
> GlobalValue::LinkOnceODRLinkage,
> +                     ConstantInt::get(IntPtrTy, 1ULL << MappingOffsetLog),
> +                     "__asan_mapping_offset");
> +  GlobalValue *asan_mapping_scale =
> +      new GlobalVariable(M, IntPtrTy, true,
> GlobalValue::LinkOnceODRLinkage,
> +                         ConstantInt::get(IntPtrTy, MappingScale),
> +                         "__asan_mapping_scale");
>
> If you use WeakLinkage for these, you won't need the fake loads.
>

Surprisingly these globals *were* optimized away at -O3, at least at some
point.
Dropped the fake loads for now.


>
> -Eli
>
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From ahatanak at gmail.com  Thu Sep  8 20:13:27 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 09 Sep 2011 01:13:27 -0000
Subject: [llvm-commits] [llvm] r139344 - in /llvm/trunk:
 lib/Target/Mips/Mips.td lib/Target/Mips/MipsSubtarget.cpp
 test/CodeGen/Mips/2010-07-20-Select.ll test/CodeGen/Mips/fpcmp.ll
 test/CodeGen/Mips/mips1f64ldst.ll test/CodeGen/Mips/select.ll
Message-ID: <20110909011327.3C5132A6C12C@llvm.org>

Author: ahatanak
Date: Thu Sep  8 20:13:27 2011
New Revision: 139344

URL: http://llvm.org/viewvc/llvm-project?rev=139344&view=rev
Log:
Change default target architecture from Mips1 to Mips32r1 in preparation for
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

Modified:
    llvm/trunk/lib/Target/Mips/Mips.td
    llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
    llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll
    llvm/trunk/test/CodeGen/Mips/fpcmp.ll
    llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll
    llvm/trunk/test/CodeGen/Mips/select.ll

Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=139344&r1=139343&r2=139344&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Thu Sep  8 20:13:27 2011
@@ -79,6 +79,7 @@
 def : Proc<"mips2", [FeatureMips2]>;
 def : Proc<"r6000", [FeatureMips2]>;
 
+def : Proc<"mips32r1", [FeatureMips32]>;
 def : Proc<"4ke", [FeatureMips32r2]>;
 
 // Allegrex is a 32bit subset of r4000, both for integer and fp registers,

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=139344&r1=139343&r2=139344&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Thu Sep  8 20:13:27 2011
@@ -31,8 +31,7 @@
 {
   std::string CPUName = CPU;
   if (CPUName.empty())
-    CPUName = "mips1";
-  MipsArchVersion = Mips1;
+    CPUName = "mips32r1";
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);

Modified: llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll?rev=139344&r1=139343&r2=139344&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll Thu Sep  8 20:13:27 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s
-; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s
+; RUN: llc < %s -march=mips -relocation-model=static -mcpu=mips1 | FileCheck %s
+; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic -mcpu=mips1 | FileCheck %s
 ; Fix PR7473
 
 define i32 @main() nounwind readnone {

Modified: llvm/trunk/test/CodeGen/Mips/fpcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fpcmp.ll?rev=139344&r1=139343&r2=139344&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fpcmp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fpcmp.ll Thu Sep  8 20:13:27 2011
@@ -1,5 +1,5 @@
 ; RUN: llc  < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
-; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS1
+; RUN: llc  < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-MIPS1
 
 @g1 = external global i32
 

Modified: llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll?rev=139344&r1=139343&r2=139344&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll Thu Sep  8 20:13:27 2011
@@ -1,5 +1,5 @@
-; RUN: llc  < %s -march=mipsel  | FileCheck %s -check-prefix=CHECK-EL
-; RUN: llc  < %s -march=mips  | FileCheck %s -check-prefix=CHECK-EB
+; RUN: llc  < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-EL
+; RUN: llc  < %s -march=mips -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-EB
 
 @g1 = common global double 0.000000e+00, align 8
 @g2 = common global double 0.000000e+00, align 8

Modified: llvm/trunk/test/CodeGen/Mips/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/select.ll?rev=139344&r1=139343&r2=139344&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/select.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/select.ll Thu Sep  8 20:13:27 2011
@@ -1,5 +1,5 @@
 ; RUN: llc  < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
-; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS1
+; RUN: llc  < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-MIPS1
 
 @d2 = external global double
 @d3 = external global double



From craig.topper at gmail.com  Fri Sep  9 00:40:53 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Fri, 09 Sep 2011 05:40:53 -0000
Subject: [llvm-commits] [llvm] r139353 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <20110909054053.83E9A2A6C12C@llvm.org>

Author: ctopper
Date: Fri Sep  9 00:40:53 2011
New Revision: 139353

URL: http://llvm.org/viewvc/llvm-project?rev=139353&view=rev
Log:
Fix handling of Intel syntax disassembling of movs and stos to stop being blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=139353&r1=139352&r2=139353&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Sep  9 00:40:53 2011
@@ -802,30 +802,30 @@
 
 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
-def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
-def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
-def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
+def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", []>;
+def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", []>, OpSize;
+def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", []>;
 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
 }
 
 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
-def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
+def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", []>;
 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
-def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
+def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", []>, OpSize;
 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
-def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
+def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", []>;
 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
 
-def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
-def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
-def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
+def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", []>;
+def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", []>, OpSize;
+def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", []>;
 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
 
-def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
-def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
-def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
+def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", []>;
+def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", []>, OpSize;
+def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", []>;
 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
 
 



From clattner at apple.com  Fri Sep  9 00:44:47 2011
From: clattner at apple.com (Chris Lattner)
Date: Thu, 08 Sep 2011 22:44:47 -0700
Subject: [llvm-commits] [llvm] r139125 - in /llvm/trunk/lib/Target:
 ARM/ARM.td ARM/ARMInstrInfo.td ARM/ARMSubtarget.cpp ARM/ARMSubtarget.h
 ARM/MCTargetDesc/ARMMCTargetDesc.cpp X86/MCTargetDesc/X86MCTargetDesc.cpp
 X86/X86.td X86/X86InstrInfo.td X86/X86Subtarget.cpp X86/X86Subtarget.h
In-Reply-To: <79B5A5D3-E8C4-4768-8C9B-58C526765027@apple.com>
References: <20110905215143.A17032A6C12C@llvm.org>
	<79B5A5D3-E8C4-4768-8C9B-58C526765027@apple.com>
Message-ID: <B5E23FFC-561B-434A-ACF3-A437728C29C1@apple.com>


On Sep 6, 2011, at 10:05 AM, Jim Grosbach wrote:

> Hi Nick,
> 
> I have a few concerns about this that hopefully won't be too hard to alleviate. On the more trite side, we generally try to keep the nomenclature descriptive of purpose rather than of use. This patch names the sub-target feature according to purpose (native client) and doesn't give any indication of what it actually does. Is this really a sub-target feature at all? Honestly, my general impression is that this is more accurately a target platform in the triple akin to Linux or Darwin. For example, thumbv7-unknown-nacl. Assuming so (and it looks like that is indeed how it's specified?), why isn't querying the triple directly a-la ARMSubtarget->isTargetDarwin(), sufficient? Lastly, speculating here as this patch doesn't go into these details, but be very careful with alignment changes in code sections, as the ARM backend is very sensitive to small changes. Specifically, the constant island pass tracks instruction alignment and relative distances as exactly as it can, and will!
  n!
> eed to be taught how to deal with these changes.

I agree in principle, but I can see it go both ways.  Note that 64-bit support is also a "subtarget feature" which is also very odd, but convenient.

That said, if "NaCL mode" is really just normal codegen plus a few tweaks, it would be much better to add subtarget features for the tweaks, and nacl mode could enable those tweaks.  This respect is very different than 64-bit support.

-Chris

> 
> -Jim
> 
> On Sep 5, 2011, at 2:51 PM, Nick Lewycky wrote:
> 
>> Author: nicholas
>> Date: Mon Sep  5 16:51:43 2011
>> New Revision: 139125
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=139125&view=rev
>> Log:
>> Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
>> instructions are more aligned than the CPU requires, and adds some additional
>> directives, to follow in future patches. Patch by David Meyer!
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARM.td
>>   llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>>   llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>>   llvm/trunk/lib/Target/ARM/ARMSubtarget.h
>>   llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
>>   llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
>>   llvm/trunk/lib/Target/X86/X86.td
>>   llvm/trunk/lib/Target/X86/X86InstrInfo.td
>>   llvm/trunk/lib/Target/X86/X86Subtarget.cpp
>>   llvm/trunk/lib/Target/X86/X86Subtarget.h
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARM.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=139125&r1=139124&r2=139125&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARM.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARM.td Mon Sep  5 16:51:43 2011
>> @@ -23,6 +23,9 @@
>> def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
>>                                  "Thumb mode">;
>> 
>> +def ModeNaCl   : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
>> +                                  "Native client mode">;
>> +
>> //===----------------------------------------------------------------------===//
>> // ARM Subtarget features.
>> //
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep  5 16:51:43 2011
>> @@ -209,6 +209,8 @@
>>                                 AssemblerPredicate<"!ModeThumb">;
>> def IsDarwin         : Predicate<"Subtarget->isTargetDarwin()">;
>> def IsNotDarwin      : Predicate<"!Subtarget->isTargetDarwin()">;
>> +def IsNaCl           : Predicate<"Subtarget->isTargetNaCl()">,
>> +                                 AssemblerPredicate<"ModeNaCl">;
>> 
>> // FIXME: Eventually this will be just "hasV6T2Ops".
>> def UseMovt          : Predicate<"Subtarget->useMovt()">;
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Sep  5 16:51:43 2011
>> @@ -53,6 +53,7 @@
>>  , HasVMLxForwarding(false)
>>  , SlowFPBrcc(false)
>>  , InThumbMode(false)
>> +  , InNaClMode(false)
>>  , HasThumb2(false)
>>  , NoARM(false)
>>  , PostRAScheduler(false)
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=139125&r1=139124&r2=139125&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Sep  5 16:51:43 2011
>> @@ -70,6 +70,9 @@
>>  /// InThumbMode - True if compiling for Thumb, false for ARM.
>>  bool InThumbMode;
>> 
>> +  /// InNaClMode - True if targeting Native Client
>> +  bool InNaClMode;
>> +
>>  /// HasThumb2 - True if Thumb2 instructions are supported.
>>  bool HasThumb2;
>> 
>> @@ -209,6 +212,9 @@
>>  const Triple &getTargetTriple() const { return TargetTriple; }
>> 
>>  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
>> +  bool isTargetNaCl() const {
>> +    return TargetTriple.getOS() == Triple::NativeClient;
>> +  }
>>  bool isTargetELF() const { return !isTargetDarwin(); }
>> 
>>  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
>> 
>> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Sep  5 16:51:43 2011
>> @@ -86,6 +86,14 @@
>>      ARMArchFeature += ",+thumb-mode";
>>  }
>> 
>> +  Triple TheTriple(TT);
>> +  if (TheTriple.getOS() == Triple::NativeClient) {
>> +    if (ARMArchFeature.empty())
>> +      ARMArchFeature = "+nacl-mode";
>> +    else
>> +      ARMArchFeature += ",+nacl-mode";
>> +  }
>> +
>>  return ARMArchFeature;
>> }
>> 
>> 
>> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Sep  5 16:51:43 2011
>> @@ -40,9 +40,16 @@
>> 
>> std::string X86_MC::ParseX86Triple(StringRef TT) {
>>  Triple TheTriple(TT);
>> +  std::string FS;
>>  if (TheTriple.getArch() == Triple::x86_64)
>> -    return "+64bit-mode";
>> -  return "-64bit-mode";
>> +    FS = "+64bit-mode";
>> +  else
>> +    FS = "-64bit-mode";
>> +  if (TheTriple.getOS() == Triple::NativeClient)
>> +    FS += ",+nacl-mode";
>> +  else
>> +    FS += ",-nacl-mode";
>> +  return FS;
>> }
>> 
>> /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=139125&r1=139124&r2=139125&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86.td Mon Sep  5 16:51:43 2011
>> @@ -23,6 +23,9 @@
>> def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
>>                                  "64-bit mode (x86_64)">;
>> 
>> +def ModeNaCl  : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
>> +                                 "Native Client mode">;
>> +
>> //===----------------------------------------------------------------------===//
>> // X86 Subtarget features.
>> //===----------------------------------------------------------------------===//
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep  5 16:51:43 2011
>> @@ -482,6 +482,14 @@
>>                             AssemblerPredicate<"Mode64Bit">;
>> def IsWin64      : Predicate<"Subtarget->isTargetWin64()">;
>> def NotWin64     : Predicate<"!Subtarget->isTargetWin64()">;
>> +def IsNaCl       : Predicate<"Subtarget->isTargetNaCl()">,
>> +                             AssemblerPredicate<"ModeNaCl">;
>> +def IsNaCl32     : Predicate<"Subtarget->isTargetNaCl32()">,
>> +                             AssemblerPredicate<"ModeNaCl,!Mode64Bit">;
>> +def IsNaCl64     : Predicate<"Subtarget->isTargetNaCl64()">,
>> +                             AssemblerPredicate<"ModeNaCl,Mode64Bit">;
>> +def NotNaCl      : Predicate<"!Subtarget->isTargetNaCl()">,
>> +                             AssemblerPredicate<"!ModeNaCl">;
>> def SmallCode    : Predicate<"TM.getCodeModel() == CodeModel::Small">;
>> def KernelCode   : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
>> def FarData      : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Sep  5 16:51:43 2011
>> @@ -260,7 +260,8 @@
>>  // FIXME: this is a known good value for Yonah. How about others?
>>  , MaxInlineSizeThreshold(128)
>>  , TargetTriple(TT)
>> -  , In64BitMode(is64Bit) {
>> +  , In64BitMode(is64Bit)
>> +  , InNaClMode(false) {
>>  // Determine default and user specified characteristics
>>  if (!FS.empty() || !CPU.empty()) {
>>    std::string CPUName = CPU;
>> @@ -306,6 +307,11 @@
>>  if (In64BitMode)
>>    ToggleFeature(X86::Mode64Bit);
>> 
>> +  if (isTargetNaCl()) {
>> +    InNaClMode = true;
>> +    ToggleFeature(X86::ModeNaCl);
>> +  }
>> +
>>  if (HasAVX)
>>    X86SSELevel = NoMMXSSE;
>> 
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=139125&r1=139124&r2=139125&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
>> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Sep  5 16:51:43 2011
>> @@ -119,6 +119,9 @@
>>  /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
>>  bool In64BitMode;
>> 
>> +  /// InNaClMode - True if compiling for Native Client target.
>> +  bool InNaClMode;
>> +
>> public:
>> 
>>  /// This constructor initializes the data members to match that
>> @@ -190,6 +193,11 @@
>>    return !isTargetDarwin() && !isTargetWindows() && !isTargetCygMing();
>>  }
>>  bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
>> +  bool isTargetNaCl() const {
>> +    return TargetTriple.getOS() == Triple::NativeClient;
>> +  }
>> +  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
>> +  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
>> 
>>  bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
>>  bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From clattner at apple.com  Fri Sep  9 00:51:15 2011
From: clattner at apple.com (Chris Lattner)
Date: Thu, 08 Sep 2011 22:51:15 -0700
Subject: [llvm-commits] Patch to Add SAFECode as a LLVM Sub-Project
In-Reply-To: <4E552194.1000807@illinois.edu>
References: <4E552194.1000807@illinois.edu>
Message-ID: <6F48BB93-1A52-4436-9EEC-75530C1DC7AF@apple.com>

Looks fine to me, please commit.

-Chris

On Aug 24, 2011, at 9:06 AM, John Criswell wrote:

> Dear All,
> 
> Yesterday, I asked Chris if SAFECode qualified as an LLVM sub-project, and he replied that it did.
> 
> To that end, I've created a patch to add SAFECode to the list of LLVM sub-projects on the main LLVM web page.  The patch is attached for review.  I have commit access, so I can commit the patch once someone reviews it.
> 
> Thanks in advance,
> 
> John Criswell
> 
> <wwwpatch.txt>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From baldrick at free.fr  Fri Sep  9 01:14:34 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 09 Sep 2011 08:14:34 +0200
Subject: [llvm-commits] [llvm] r139340 -
	/llvm/trunk/tools/gold/gold-plugin.cpp
In-Reply-To: <20110909001404.29F222A6C12C@llvm.org>
References: <20110909001404.29F222A6C12C@llvm.org>
Message-ID: <4E69AECA.5040206@free.fr>

Hi Ivan,

> -  if (!M)
> +  if (!M) {
> +    if (const char* msg = lto_get_error_message()) {
> +      (*message)(LDPL_ERROR, "Failed to create LTO module: %s", msg);

maybe this should mention LLVM?  If you are doing GCC and LLVM LTO at the
same time, just mentioning LTO is ambiguous.  But perhaps the name of the
plugin is printed, and that makes it clear?

Ciao, Duncan.

> +      return LDPS_ERR;
> +    }
>       return LDPS_OK;
> +  }
>
>     *claimed = 1;
>     Modules.resize(Modules.size() + 1);
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From craig.topper at gmail.com  Fri Sep  9 01:35:44 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Fri, 09 Sep 2011 06:35:44 -0000
Subject: [llvm-commits] [llvm] r139356 -
	/llvm/trunk/test/MC/Disassembler/X86/intel-syntax.txt
Message-ID: <20110909063544.C73C52A6C12C@llvm.org>

Author: ctopper
Date: Fri Sep  9 01:35:44 2011
New Revision: 139356

URL: http://llvm.org/viewvc/llvm-project?rev=139356&view=rev
Log:
Add disassembler test for Intel syntax. Tests r139353.

Added:
    llvm/trunk/test/MC/Disassembler/X86/intel-syntax.txt

Added: llvm/trunk/test/MC/Disassembler/X86/intel-syntax.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/intel-syntax.txt?rev=139356&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/intel-syntax.txt (added)
+++ llvm/trunk/test/MC/Disassembler/X86/intel-syntax.txt Fri Sep  9 01:35:44 2011
@@ -0,0 +1,13 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 -x86-asm-syntax=intel | FileCheck %s
+
+# CHECK: movsb
+0xa4
+
+# CHECK: movsw
+0x66 0xa5
+
+# CHECK: movsd
+0xa5
+
+# CHECK: movsq
+0x48 0xa5



From krasin at google.com  Fri Sep  9 02:16:33 2011
From: krasin at google.com (Ivan Krasin)
Date: Fri, 9 Sep 2011 00:16:33 -0700
Subject: [llvm-commits] [llvm] r139340 -
	/llvm/trunk/tools/gold/gold-plugin.cpp
In-Reply-To: <4E69AECA.5040206@free.fr>
References: <20110909001404.29F222A6C12C@llvm.org> <4E69AECA.5040206@free.fr>
Message-ID: <CAOei5Rf2zW0VwDLRpKtWtyWLrYHKCvfH58TOd-bRUBgq1j1Ang@mail.gmail.com>

Hi Duncan,

On Thu, Sep 8, 2011 at 11:14 PM, Duncan Sands <baldrick at free.fr> wrote:
> Hi Ivan,
>
>> - ?if (!M)
>> + ?if (!M) {
>> + ? ?if (const char* msg = lto_get_error_message()) {
>> + ? ? ?(*message)(LDPL_ERROR, "Failed to create LTO module: %s", msg);
>
> maybe this should mention LLVM? ?If you are doing GCC and LLVM LTO at the
> same time, just mentioning LTO is ambiguous. ?But perhaps the name of the
> plugin is printed, and that makes it clear?
the idea looks good to me.

Please, find the patch attached. It makes the diagnostics more precise
and adds a fast path for skipping non-bitcode files, if Gold version
supports get_view (i.e. gold is more-or-less recent). The latter is
important for two reasons:

- it's the common case for linking with the Gold plugin. It's good to
avoid creating heavy-weight Bitcode reader.
- after the change that has enabled these diagnostic messages, the
users have started to see warnings like "bfd plugin: Failed to create
LTO module: Invalid bitcode signature" which is definitely not
desirable.

OK to commit?

krasin

>
> Ciao, Duncan.
>
>> + ? ? ?return LDPS_ERR;
>> + ? ?}
>> ? ? ? return LDPS_OK;
>> + ?}
>>
>> ? ? *claimed = 1;
>> ? ? Modules.resize(Modules.size() + 1);
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From James.Molloy at arm.com  Fri Sep  9 02:18:29 2011
From: James.Molloy at arm.com (James Molloy)
Date: Fri, 9 Sep 2011 08:18:29 +0100
Subject: [llvm-commits] [llvm] r139250 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ test/MC/Disassembler/ARM/ utils/TableGen/
In-Reply-To: <B66098B1-B191-4355-95FB-03A41F3241F4@apple.com>
References: <20110907194229.097E02A6C12C@llvm.org>
	<CADiQthOBjzzbZ=7HTvp5eLu2+4egv1G+VRB2qN_+CUCMTz2R=w@mail.gmail.com>
	<49E8D98A-013B-4395-A94E-FA0B7927B9E9@apple.com>
	<000c01cc6df8$921309e0$b6391da0$%molloy@arm.com>
	<B66098B1-B191-4355-95FB-03A41F3241F4@apple.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA47375987749@GEORGE.Emea.Arm.com>

Hi Andy,

Thanks, for some reason I hadn't seen the attachments on Takumi's original email.

Cheers,

James

> -----Original Message-----
> From: Andrew Trick [mailto:atrick at apple.com]
> Sent: 08 September 2011 17:49
> To: James Molloy
> Cc: NAKAMURA Takumi; llvm-commits
> Subject: Re: [llvm-commits] [llvm] r139250 - in /llvm/trunk:
> lib/Target/ARM/Disassembler/ test/MC/Disassembler/ARM/ utils/TableGen/
>
> Hi James,
>
> ARMGenDisassemblerTables.inc is trashed by tblgen leading to compilation
> errors starting with:
>
> ARMGenDisassemblerTables.inc(51) : error C2589: ')' : illegal token on
> right side of '::'
> ...
>
> Takumi kindly attached an example ARMGenDisassemblerTables.inc in an
> earlier email (see vs.txt). I don't even have easy access to that file, so
> many thanks to Takumi.
>
> -Andy
>
> On Sep 8, 2011, at 12:26 AM, James Molloy wrote:
>
> > Hi,
> >
> > I don't see this, at least on linux with gcc 4.1.2.
> >
> > Our windows buildbot picked a warning up in
> FixedLenDecoderEmitter.cpp:857 - is
> > that what you're referring to? I'll fix that now.
> >
> > Otherwise, if you could provide an example of the warning/error, that
> would be
> > much appreciated.
> >
> > Cheers,
> >
> > James
> >
> >> -----Original Message-----
> >> From: Andrew Trick [mailto:atrick at apple.com]
> >> Sent: 08 September 2011 02:19
> >> To: NAKAMURA Takumi; James Molloy
> >> Cc: llvm-commits
> >> Subject: Re: [llvm-commits] [llvm] r139250 - in /llvm/trunk:
> >> lib/Target/ARM/Disassembler/ test/MC/Disassembler/ARM/ utils/TableGen/
> >>
> >> Our windows testers are hitting it too. Let me know if you can confirm
> this
> >> is the cause.
> >> -Andy
> >>
> >> On Sep 7, 2011, at 5:07 PM, NAKAMURA Takumi wrote:
> >>
> >>> 2011/9/8 James Molloy <james.molloy at arm.com>:
> >>>> Author: jamesm
> >>>> Date: Wed Sep  7 14:42:28 2011
> >>>> New Revision: 139250
> >>>>
> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=139250&view=rev
> >>>> Log:
> >>>> Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This
> >> adds predicate checking to the Disassembler.
> >>>>
> >>>> Modified:
> >>>>   llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/neon.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
> >>>>   llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
> >>>>   llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
> >>>>   llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
> >>>>   llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h
> >>>
> >>> James, I saw weird emissions by tblgen, on cygwin gcc-4.3 and msvc10.
> >>> I will investigate a few hours after, too.
> >>>
> >>> ...Takumi
> >>> <cyg.txt.gz><vs.txt.gz>_______________________________________________
> >>> llvm-commits mailing list
> >>> llvm-commits at cs.uiuc.edu
> >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >>
> >>
> >
> >
> >
>
>


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.



From baldrick at free.fr  Fri Sep  9 02:50:37 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 09 Sep 2011 07:50:37 -0000
Subject: [llvm-commits] [llvm] r139360 - in /llvm/trunk:
 include/llvm/Intrinsics.td test/Transforms/GVN/2011-09-07-TypeIdFor.ll
Message-ID: <20110909075037.44C4A2A6C12D@llvm.org>

Author: baldrick
Date: Fri Sep  9 02:50:37 2011
New Revision: 139360

URL: http://llvm.org/viewvc/llvm-project?rev=139360&view=rev
Log:
Mark the eh.typeid.for intrinsic as being 'const', which it is inside
any given function.  As pointed out by John McCall, this is needed to
have redundant eh.typeid.for tests be eliminated in the presence of
cleanups.

Modified:
    llvm/trunk/include/llvm/Intrinsics.td
    llvm/trunk/test/Transforms/GVN/2011-09-07-TypeIdFor.ll

Modified: llvm/trunk/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=139360&r1=139359&r2=139360&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Fri Sep  9 02:50:37 2011
@@ -309,7 +309,9 @@
                                  [llvm_ptr_ty, llvm_ptr_ty, llvm_vararg_ty]>;
 def int_eh_resume    : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [Throws]>;
 
-def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem]>;
+// The result of eh.typeid.for depends on the enclosing function, but inside a
+// given function it is 'const' and may be CSE'd etc.
+def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
 
 def int_eh_return_i32 : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>;
 def int_eh_return_i64 : Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty]>;

Modified: llvm/trunk/test/Transforms/GVN/2011-09-07-TypeIdFor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2011-09-07-TypeIdFor.ll?rev=139360&r1=139359&r2=139360&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/GVN/2011-09-07-TypeIdFor.ll (original)
+++ llvm/trunk/test/Transforms/GVN/2011-09-07-TypeIdFor.ll Fri Sep  9 02:50:37 2011
@@ -7,6 +7,8 @@
 
 declare void @_Z4barv()
 
+declare void @_Z7cleanupv()
+
 declare i32 @llvm.eh.typeid.for(i8*) nounwind readonly
 
 declare i8* @__cxa_begin_catch(i8*) nounwind
@@ -50,6 +52,7 @@
   br label %return
 
 next2:                                            ; preds = %next
+  call void @_Z7cleanupv()
   %typeid = tail call i32 @llvm.eh.typeid.for(i8* bitcast (%struct.__fundamental_type_info_pseudo* @_ZTIi to i8*))
 ; CHECK-NOT: call i32 @llvm.eh.typeid.for
   %4 = icmp eq i32 %filter3.i, %typeid



From baldrick at free.fr  Fri Sep  9 02:52:40 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 09 Sep 2011 09:52:40 +0200
Subject: [llvm-commits] [llvm] r139236 - in /llvm/trunk:
 include/llvm/Intrinsics.td test/Transforms/GVN/2011-09-07-TypeIdFor.ll
In-Reply-To: <B8C75AE9-9387-4E4F-B0F0-AF3B8577631F@apple.com>
References: <20110907164414.B60312A6C12C@llvm.org>
	<B8C75AE9-9387-4E4F-B0F0-AF3B8577631F@apple.com>
Message-ID: <4E69C5C8.5080004@free.fr>

Hi John,

>> When inlining exception handling code into another function, ensure that
>> duplicate tests are eliminated (for example if the two functions both have
>> a catch clause catching the same type, ensure the redundant one is removed).
>> Note that it would probably be safe to say that eh.typeid.for is 'const',
>> but since two calls to it with the same argument can give different results
>> (but only if the calls are in different functions), it seems more correct to
>> mark it only 'pure'; this doesn't get in the way of the optimization.
>
> It could if there were an intervening cleanup.  I see no reason not to mark it 'const'.

thanks for pointing this out.  I've now marked it 'const'.

Ciao, Duncan.

From pdox at google.com  Fri Sep  9 03:05:27 2011
From: pdox at google.com (David Meyer)
Date: Fri, 9 Sep 2011 01:05:27 -0700
Subject: [llvm-commits] [PATCH] Native Client: Set correct ELF metadata
Message-ID: <CAAU48JLL8tUyV7ckntm7a6aHUDWuFy5W3Qsgs2szkenZcnU5zA@mail.gmail.com>

This patch teaches MC/ELFObjectWriter to set the correct ABI version,
OS ABI, and EFlags for emitting Native Client ELF objects.

- pdox
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From tobias at grosser.es  Fri Sep  9 03:40:50 2011
From: tobias at grosser.es (Tobias Grosser)
Date: Fri, 09 Sep 2011 09:40:50 +0100
Subject: [llvm-commits] [LLVMdev] Some builders are available here
In-Reply-To: <CAJ8eiNxkiZV7XGGLqr+ddRd4EkzOrhTESxMawcy+ubordgLG4w@mail.gmail.com>
References: <CAJ8eiNxkiZV7XGGLqr+ddRd4EkzOrhTESxMawcy+ubordgLG4w@mail.gmail.com>
Message-ID: <4E69D112.1070405@grosser.es>

On 09/09/2011 12:25 AM, Galina Kistanova wrote:
> Hello everyone,
>
> As a temporally solution, subset of builders from llvm buildmaster are
> available here:
> http://63.145.236.72:8011
> This temporally master is not reporting to IRC.

Hi,

I have found the console display does not work.

Cheers
Tobi


From grosser at fim.uni-passau.de  Fri Sep  9 04:08:09 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Fri, 09 Sep 2011 09:08:09 -0000
Subject: [llvm-commits] [polly] r139362 - /polly/trunk/www/get_started.html
Message-ID: <20110909090809.C02972A6C12C@llvm.org>

Author: grosser
Date: Fri Sep  9 04:08:09 2011
New Revision: 139362

URL: http://llvm.org/viewvc/llvm-project?rev=139362&view=rev
Log:
Change installation instruction to use a fixed isl version

Modified:
    polly/trunk/www/get_started.html

Modified: polly/trunk/www/get_started.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/get_started.html?rev=139362&r1=139361&r2=139362&view=diff
==============================================================================
--- polly/trunk/www/get_started.html (original)
+++ polly/trunk/www/get_started.html Fri Sep  9 04:08:09 2011
@@ -28,36 +28,31 @@
 <h3> Install ISL / CLooG libraries </h3>
 
 Polly requires the latest versions of <a href="http://www.cloog.org">CLooG</a>
-and the version of <a href="http://repo.or.cz/w/isl.git">isl</a> included with
-CLooG. To install both use the following commands.
+and <a href="http://repo.or.cz/w/isl.git">isl</a> checked out at
+commit cd1939ed06617d00159e8e51b72a804b467e98b4.
 
+<h4> First installation</h4>
 <pre>
 git clone git://repo.or.cz/cloog.git
 cd cloog
 ./get_submodules.sh
+cd isl
+git remote update
+git checkout cd1939ed06617d00159e8e51b72a804b467e98b4
+cd ..
 ./autogen.sh
 ./configure --with-gmp-prefix=/path/to/gmp/installation --prefix=/path/to/cloog/installation
 make
 make install
 </pre>
 
-<h4 id="islTrunk">Use isl trunk</h4>
-
-In rare case it is necessary to use an isl version that is even newer than
-the one included in CLooG. This may happen, because we work in close interaction
-with the developers of isl such that Polly sometimes uses features that are not
-yet available in the version of isl which is included with CLooG.  To get the
-most recent version of isl perform these additional steps.<br />
-<em>Only perform these steps if a recent mailing list message asks you to do
-so.</em>
-
+<h4> Update an earlier installation</h4>
 <pre>
+git pull
 cd isl
 git remote update
-git checkout origin/master
+git checkout cd1939ed06617d00159e8e51b72a804b467e98b4
 cd ..
-./autogen.sh
-./configure  --with-gmp-prefix=/path/to/gmp/installation --prefix=/path/to/cloog/installation
 make
 make install
 </pre>



From wendling at apple.com  Fri Sep  9 04:39:52 2011
From: wendling at apple.com (Bill Wendling)
Date: Fri, 09 Sep 2011 02:39:52 -0700
Subject: [llvm-commits] [PATCH] Native Client: Set correct ELF metadata
In-Reply-To: <CAAU48JLL8tUyV7ckntm7a6aHUDWuFy5W3Qsgs2szkenZcnU5zA@mail.gmail.com>
References: <CAAU48JLL8tUyV7ckntm7a6aHUDWuFy5W3Qsgs2szkenZcnU5zA@mail.gmail.com>
Message-ID: <3F91B6EC-BEE8-4445-B27E-3B15DC8CB7A8@apple.com>

On Sep 9, 2011, at 1:05 AM, David Meyer wrote:

> This patch teaches MC/ELFObjectWriter to set the correct ABI version,
> OS ABI, and EFlags for emitting Native Client ELF objects.
> 
These switches seem a bit heavy-handed. Why not just if-then-else statements?

+  // e_ident[EI_ABIVERSION]
+  switch (TargetObjectWriter->getOSType()) {
+    case Triple::NativeClient: Write8(ELF::ELFABIVERSION_NACL); break;
+    default:                   Write8(0); break;
+  }
+
   WriteZeros(ELF::EI_NIDENT - ELF::EI_PAD);
 
   Write16(ELF::ET_REL);             // e_type
@@ -1283,7 +1289,12 @@
 
 // FIXME: get the real EABI Version from the Triple.
 void ARMELFObjectWriter::WriteEFlags() {
-  Write32(ELF::EF_ARM_EABIMASK & DefaultEABIVersion);
+  unsigned EFlags = ELF::EF_ARM_EABIMASK & DefaultEABIVersion;
+  switch (TargetObjectWriter->getOSType()) {
+    case Triple::NativeClient: EFlags |= ELF::EF_NACL_ALIGN_16; break;
+    default: break;
+  }
+  Write32(EFlags);
 }
 
 // In ARM, _MergedGlobals and other most symbols get emitted directly.
@@ -1642,6 +1653,15 @@
 X86ELFObjectWriter::~X86ELFObjectWriter()
 {}
 
+void X86ELFObjectWriter::WriteEFlags() {
+  unsigned EFlags = 0;
+  switch (TargetObjectWriter->getOSType()) {
+    case Triple::NativeClient: EFlags |= ELF::EF_NACL_ALIGN_32; break;
+    default: break;
+  }
+  Write32(EFlags);


-bw


From grosser at fim.uni-passau.de  Fri Sep  9 06:02:10 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Fri, 09 Sep 2011 11:02:10 -0000
Subject: [llvm-commits] [polly] r139363 - /polly/trunk/www/get_started.html
Message-ID: <20110909110210.D813D2A6C12C@llvm.org>

Author: grosser
Date: Fri Sep  9 06:02:10 2011
New Revision: 139363

URL: http://llvm.org/viewvc/llvm-project?rev=139363&view=rev
Log:
Also force a fixed version of cloog

Modified:
    polly/trunk/www/get_started.html

Modified: polly/trunk/www/get_started.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/get_started.html?rev=139363&r1=139362&r2=139363&view=diff
==============================================================================
--- polly/trunk/www/get_started.html (original)
+++ polly/trunk/www/get_started.html Fri Sep  9 06:02:10 2011
@@ -35,6 +35,7 @@
 <pre>
 git clone git://repo.or.cz/cloog.git
 cd cloog
+git checkout cloog-0.16.3
 ./get_submodules.sh
 cd isl
 git remote update
@@ -48,7 +49,9 @@
 
 <h4> Update an earlier installation</h4>
 <pre>
-git pull
+cd cloog
+git remote update
+git checkout cloog-0.16.3
 cd isl
 git remote update
 git checkout cd1939ed06617d00159e8e51b72a804b467e98b4



From baldrick at free.fr  Fri Sep  9 08:06:41 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 09 Sep 2011 15:06:41 +0200
Subject: [llvm-commits] [llvm] r139340 -
	/llvm/trunk/tools/gold/gold-plugin.cpp
In-Reply-To: <CAOei5Rf2zW0VwDLRpKtWtyWLrYHKCvfH58TOd-bRUBgq1j1Ang@mail.gmail.com>
References: <20110909001404.29F222A6C12C@llvm.org> <4E69AECA.5040206@free.fr>
	<CAOei5Rf2zW0VwDLRpKtWtyWLrYHKCvfH58TOd-bRUBgq1j1Ang@mail.gmail.com>
Message-ID: <4E6A0F61.505@free.fr>

Hi Ivan,

> Please, find the patch attached. It makes the diagnostics more precise
> and adds a fast path for skipping non-bitcode files, if Gold version
> supports get_view (i.e. gold is more-or-less recent). The latter is
> important for two reasons:
>
> - it's the common case for linking with the Gold plugin. It's good to
> avoid creating heavy-weight Bitcode reader.
> - after the change that has enabled these diagnostic messages, the
> users have started to see warnings like "bfd plugin: Failed to create
> LTO module: Invalid bitcode signature" which is definitely not
> desirable.
>
> OK to commit?

I'm not competent to review this patch, sorry.

Ciao, Duncan.

From baldrick at free.fr  Fri Sep  9 09:24:39 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 09 Sep 2011 16:24:39 +0200
Subject: [llvm-commits] [llvm] r139263 -
	/llvm/trunk/lib/Target/README.txt
In-Reply-To: <CAL3drCrbFXnXuccckjL=onB8qZa_+SDsarKDix0Kx2qsiTx7BA@mail.gmail.com>
References: <20110907224926.A9B8C2A6C12C@llvm.org> <4E686F34.3010200@free.fr>
	<CANycJ-BANEfDD3Ci7MEN=9S_CxicqRVjyrh+WTb_QjN0UQ-QUQ@mail.gmail.com>
	<CAL3drCrbFXnXuccckjL=onB8qZa_+SDsarKDix0Kx2qsiTx7BA@mail.gmail.com>
Message-ID: <4E6A21A7.8030704@free.fr>

Hi Benjamin,

>> I am trying to implement this as an exercise for me.
>> Attached you can find a patch which should implement the first
>> transformation as an InstructionSimplify optimization.
>>
>> Can you please give me feedback if I'm on the right track to do this
>> in InstSimplify and using the matcher?
>> My pattern looks complicated and very specific is there a easy/better
>> way to do it?
>
> These patterns are fine, but indeed very specific.

right - there are vast numbers of variations on this theme that occur in
practice.

  I think there is a
> more general way to do this. What I had in mind (maybe Duncan's idea
> is different and he knows InstSimplify a lot better than me), is to
> substitute the value from the equality comparison into the expression
> on the other side and see if it evaluates to true.
>
> (A == 0) | ((A&  ?) == 0) ->  (A == 0) | ((0&  ?) == 0) ->  (A == 0) | true
> Now we know that the first expression is redundant and we can drop it.
> We can use the same trick for&  with != and false.

My idea is along these lines but a bit more general.  First off, observe that
if X and Y are expressions and X => Y is true (X implies Y) then X & Y is
equivalent to X.  Similarly, if Y => X is true (Y implies X) than X | Y is
equivalent to X.

For example, if
   X := (A & ?) == 0
and
   Y := A == 0
then Y => X (if A is zero then certainly A & ? is zero).  Thus X | Y simplifies
to X which was the proposed transformation.

So to handle both & and | (and more besides) you need a way of determining when
ExpressionA => ExpressionB is true.  This can be done by assuming that
ExpressionA is true, and then simplifying ExpressionB using that.  If you can
simplify it to the constant "true" then you have shown that ExpressionA implies
ExpressionB.

In the above example, you would assume that "A == 0" is true (i.e. 0 can be
substituted for A), and then perform simplifications on "A & ? == 0" using
this fact.

How to do this in practice?  I'm imagining the following: define a "Facts"
class, into which you can push facts known to be true (push_true) and facts
know to be false (push_false), where a "fact" is an LLVM Value* with i1 type
(perhaps vector of i1 should be allowed too).  All the internal instsimplify
methods would get a Facts* argument, which can be null if there are no facts.

When trying to simplify a boolean X | Y, you would then do (schematically):

facts.push_true(Y);
Value *V = instsimplify(X, &facts);
facts.pop_back();
if (V && V->isAllOnesValue()) // X simplified to true when Y assumed true?
   // Yes!  X | Y simplifies to X.
   return X;
facts.push_true(X);
V = instsimplify(Y, &facts);
facts.pop_back();
if (V && V->isAllOnesValue()) // Y simplified to true when X assumed true?
   // Yes!  X | Y simplifies to Y.
   return Y;

Inside the various instsimplify routines, for example SimplifyICmpInst (which
is where you get when trying to simplify "A & ? == 0"), if the facts object is
not null, first the routine would try to simplify the arguments using the known
facts (i.e. it would call instsimplify with the expression "A & ?" and the
facts, and the expression "0" and the facts), and then continue with its usual
logic using the possibly simplified arguments.  So at the beginning of
SimplifyICmpInst,  SimplifyAndInst will be called with operands "A" and "?"
(and the facts).  It will try to simplify "A" in the presence of the fact
"A == 0", which will simplify A to 0 (here is where the facts are actually
used).  Maybe "?" will simplify or not, it doesn't matter.  Then the
SimplifyAndInst will continue its usual logic with the operands "0" and "?",
and return 0.  Then SimplifyICmpInst will continue with the operands "0" and
"0" and return "true".  And you're done.

Given the very limited amount of recursion that instsimplify does, the number
of facts would never exceed 2 or 3, so a very simple implementation would be
fine.  To get started, it would be enough to have it do something useful only
with equality facts like "A == 0 known true", but inequality facts turn up in
practice all the time so that can be added as an enhancement.

Well, maybe this is all too "heavy".  But that was what I had in mind.

>
> We have similar code in InstCombineSelect.cpp (look for
> SimplifyWithOpReplaced). To get this kind of cases it has to be
> enhanced to do the substitution on multiple levels though, I don't
> know how hard that is with the current InstSimplify machinery.

Pretty easy I think.

Ciao, Duncan.

From james.molloy at arm.com  Fri Sep  9 09:43:59 2011
From: james.molloy at arm.com (James Molloy)
Date: Fri, 9 Sep 2011 15:43:59 +0100
Subject: [llvm-commits] [PATCH] Bug 10897 - Seg fault during NEON
	compilation with short3/4 division
Message-ID: <000e01cc6efe$e8d78a10$ba869e30$@molloy@arm.com>

Hi,

The attached patch fixes bug 10897.

The issue was in the DAGCombiner, when constant-folding "insert_vector_emt"
nodes on a vector that had been size-extended (<3 x int> -> <4 x int> for
example).

The DAGCombiner was inserting UNDEFs for all values in the vector, and the
folded insert_vector_emt nodes replace those UNDEFs with actual content. But the
padding at the end, in the case where the original vector was not a power of 2,
isn't changed.

This is fine, apart from the type that was being used for UNDEF was the type of
the vector element, which may not be legal. As DAGTypeLegalizer has already run
by this point, inserting illegal nodes causes assertion failures later down the
line.

The fix is to ensure the type of the UNDEFs are legal types:

+    if (!isTypeLegal(EltVT))
+        EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
+    assert(isTypeLegal(EltVT) && "Vector element type was not legal!");

----

Aside: The documentation for TargetLowering::getTypeToTransformTo() states that
if the input parameter is legal, the function is equivalent to the identity
function. I should therefore not need the "isTypeLegal" check on the line above.

Changing this however broke a lot of codegen tests, both in the ARM and X86
backends. Does anyone know why that might be the case? For the X86 test I looked
at, getTypeToTransformTo appeared to be changing an i64 to a v2i64 (IIRC).

Patch attached, testcase added. OK to commit?

Cheers,


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From pdox at google.com  Fri Sep  9 10:11:40 2011
From: pdox at google.com (David Meyer)
Date: Fri, 9 Sep 2011 08:11:40 -0700
Subject: [llvm-commits] [PATCH] Native Client: Set correct ELF metadata
In-Reply-To: <3F91B6EC-BEE8-4445-B27E-3B15DC8CB7A8@apple.com>
References: <CAAU48JLL8tUyV7ckntm7a6aHUDWuFy5W3Qsgs2szkenZcnU5zA@mail.gmail.com>
	<3F91B6EC-BEE8-4445-B27E-3B15DC8CB7A8@apple.com>
Message-ID: <CAAU48J+6PAwseF5FGGK5X+dU7voce0As_QfZWK2zHMi9BvZUXg@mail.gmail.com>

Bill,

Premature generalization? New patch attached.

- pdox

On Fri, Sep 9, 2011 at 2:39 AM, Bill Wendling <wendling at apple.com> wrote:
> On Sep 9, 2011, at 1:05 AM, David Meyer wrote:
>
>> This patch teaches MC/ELFObjectWriter to set the correct ABI version,
>> OS ABI, and EFlags for emitting Native Client ELF objects.
>>
> These switches seem a bit heavy-handed. Why not just if-then-else statements?
>
> + ?// e_ident[EI_ABIVERSION]
> + ?switch (TargetObjectWriter->getOSType()) {
> + ? ?case Triple::NativeClient: Write8(ELF::ELFABIVERSION_NACL); break;
> + ? ?default: ? ? ? ? ? ? ? ? ? Write8(0); break;
> + ?}
> +
> ? WriteZeros(ELF::EI_NIDENT - ELF::EI_PAD);
>
> ? Write16(ELF::ET_REL); ? ? ? ? ? ? // e_type
> @@ -1283,7 +1289,12 @@
>
> ?// FIXME: get the real EABI Version from the Triple.
> ?void ARMELFObjectWriter::WriteEFlags() {
> - ?Write32(ELF::EF_ARM_EABIMASK & DefaultEABIVersion);
> + ?unsigned EFlags = ELF::EF_ARM_EABIMASK & DefaultEABIVersion;
> + ?switch (TargetObjectWriter->getOSType()) {
> + ? ?case Triple::NativeClient: EFlags |= ELF::EF_NACL_ALIGN_16; break;
> + ? ?default: break;
> + ?}
> + ?Write32(EFlags);
> ?}
>
> ?// In ARM, _MergedGlobals and other most symbols get emitted directly.
> @@ -1642,6 +1653,15 @@
> ?X86ELFObjectWriter::~X86ELFObjectWriter()
> ?{}
>
> +void X86ELFObjectWriter::WriteEFlags() {
> + ?unsigned EFlags = 0;
> + ?switch (TargetObjectWriter->getOSType()) {
> + ? ?case Triple::NativeClient: EFlags |= ELF::EF_NACL_ALIGN_32; break;
> + ? ?default: break;
> + ?}
> + ?Write32(EFlags);
>
>
> -bw
>
>
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From criswell at illinois.edu  Fri Sep  9 10:21:25 2011
From: criswell at illinois.edu (John Criswell)
Date: Fri, 9 Sep 2011 10:21:25 -0500
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <CAN=P9phTgbv3a2TKKSDGcPNqxBP4VO+B2p+bHN5ikzcU2ZSsEg@mail.gmail.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
	<CAJdarcH-q+Hx78BH1uxANio1uwAJ9pvf2NKL-sHNDCesKJaGYw@mail.gmail.com>
	<CAN=P9phTgbv3a2TKKSDGcPNqxBP4VO+B2p+bHN5ikzcU2ZSsEg@mail.gmail.com>
Message-ID: <4E6A2EF5.3030307@illinois.edu>

On 9/8/11 7:57 PM, Kostya Serebryany wrote:
>
>
>
>     A couple review comments:
>
>     AddressSanitizer::appendToGlobalCtors is messy at best; 
>
>
> Agree (the code is stolen from some other part of LLVM and fixed to 
> actually work).
>
>     is there
>     really no better way to get the asan init function to run when it
>     needs to?
>
>
> I see no other way other than to append to llvm.global_ctors.
> Given that I didn't find whether LLVM guaranties the particular order 
> of CTOR execution, I have to call them twice, at the beginning and at 
> the end of llvm.global_ctors
> Suggestions?

SAFECode also adds calls in llvm.global_ctors in 
lib/InsertPoolChecks/RegisterRuntimeInitializer.cpp (line 144).  At the 
time I wrote the code, ctor priorities were not honored as documented in 
the Language Reference Manual.  Through experimentation, I determined 
that they were executed in one order on Linux and another on Mac OS X, 
and the code in RegisterRuntimeInitializer.cpp uses that information.

That said, I seem to recall seeing a commit recently that may have fixed 
the problem with ctor priority numbers.  Has that, in fact, been fixed?  
If so, it would be better to rely upon the documented priority numbers 
instead of on undocumented behavior observed in the wild.
:)

-- John T.


>
>     Please get rid of blockHasException and the dependent code; the
>     eh_exception intrinsic is going away very soon, and you shouldn't run
>     into similar issues with the new exception handling framework.
>
>
> Done.
>
>
>     +  GlobalValue *asan_mapping_offset =
>     +      new GlobalVariable(M, IntPtrTy, true,
>     GlobalValue::LinkOnceODRLinkage,
>     +                     ConstantInt::get(IntPtrTy, 1ULL <<
>     MappingOffsetLog),
>     +                     "__asan_mapping_offset");
>     +  GlobalValue *asan_mapping_scale =
>     +      new GlobalVariable(M, IntPtrTy, true,
>     GlobalValue::LinkOnceODRLinkage,
>     +                         ConstantInt::get(IntPtrTy, MappingScale),
>     +                         "__asan_mapping_scale");
>
>     If you use WeakLinkage for these, you won't need the fake loads.
>
>
> Surprisingly these globals *were* optimized away at -O3, at least at 
> some point.
> Dropped the fake loads for now.
>
>
>     -Eli
>
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From baldrick at free.fr  Fri Sep  9 10:31:24 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 09 Sep 2011 17:31:24 +0200
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <4E6A2EF5.3030307@illinois.edu>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
	<CAJdarcH-q+Hx78BH1uxANio1uwAJ9pvf2NKL-sHNDCesKJaGYw@mail.gmail.com>
	<CAN=P9phTgbv3a2TKKSDGcPNqxBP4VO+B2p+bHN5ikzcU2ZSsEg@mail.gmail.com>
	<4E6A2EF5.3030307@illinois.edu>
Message-ID: <4E6A314C.8050400@free.fr>

Hi John,

> SAFECode also adds calls in llvm.global_ctors in
> lib/InsertPoolChecks/RegisterRuntimeInitializer.cpp (line 144). At the time I
> wrote the code, ctor priorities were not honored as documented in the Language
> Reference Manual. Through experimentation, I determined that they were executed
> in one order on Linux and another on Mac OS X, and the code in
> RegisterRuntimeInitializer.cpp uses that information.
>
> That said, I seem to recall seeing a commit recently that may have fixed the
> problem with ctor priority numbers. Has that, in fact, been fixed?

yes, it has been fixed.

Best wishes, Duncan.

  If so, it
> would be better to rely upon the documented priority numbers instead of on
> undocumented behavior observed in the wild.
> :)
>
> -- John T.
>
>
>>
>>     Please get rid of blockHasException and the dependent code; the
>>     eh_exception intrinsic is going away very soon, and you shouldn't run
>>     into similar issues with the new exception handling framework.
>>
>>
>> Done.
>>
>>
>>     + GlobalValue *asan_mapping_offset =
>>     + new GlobalVariable(M, IntPtrTy, true, GlobalValue::LinkOnceODRLinkage,
>>     + ConstantInt::get(IntPtrTy, 1ULL << MappingOffsetLog),
>>     + "__asan_mapping_offset");
>>     + GlobalValue *asan_mapping_scale =
>>     + new GlobalVariable(M, IntPtrTy, true, GlobalValue::LinkOnceODRLinkage,
>>     + ConstantInt::get(IntPtrTy, MappingScale),
>>     + "__asan_mapping_scale");
>>
>>     If you use WeakLinkage for these, you won't need the fake loads.
>>
>>
>> Surprisingly these globals *were* optimized away at -O3, at least at some point.
>> Dropped the fake loads for now.
>>
>>
>>     -Eli
>>
>>
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu  <mailto:llvm-commits at cs.uiuc.edu>
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From criswell at uiuc.edu  Fri Sep  9 10:45:15 2011
From: criswell at uiuc.edu (John Criswell)
Date: Fri, 09 Sep 2011 15:45:15 -0000
Subject: [llvm-commits] [www] r139366 - /www/trunk/index.html
Message-ID: <20110909154515.D06C12A6C12C@llvm.org>

Author: criswell
Date: Fri Sep  9 10:45:15 2011
New Revision: 139366

URL: http://llvm.org/viewvc/llvm-project?rev=139366&view=rev
Log:
Adding SAFECode as an LLVM sub-project.

Modified:
    www/trunk/index.html

Modified: www/trunk/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=139366&r1=139365&r2=139366&view=diff
==============================================================================
--- www/trunk/index.html (original)
+++ www/trunk/index.html Fri Sep  9 10:45:15 2011
@@ -90,6 +90,13 @@
     properties of functions.  A major feature of klee is that it can produce a
     testcase in the event that it detects a bug.</p></li>
 
+<li><p>The <b><a href="http://safecode.cs.illinois.edu">SAFECode</a></b>
+    project is a memory safety compiler for C/C++ programs.  It instruments
+    code with run-time checks to detect memory safety errors (e.g., buffer
+    overflows) at run-time.  It can be used to protect software from
+    security attacks and can also be used as a memory safety error debugging
+    tool like Valgrind.</p></li>
+
 </ol>
 
 <p>In addition to official subprojects of LLVM, there are a broad variety of



From criswell at illinois.edu  Fri Sep  9 10:47:47 2011
From: criswell at illinois.edu (John Criswell)
Date: Fri, 9 Sep 2011 10:47:47 -0500
Subject: [llvm-commits] Patch to Add SAFECode as a LLVM Sub-Project
In-Reply-To: <6F48BB93-1A52-4436-9EEC-75530C1DC7AF@apple.com>
References: <4E552194.1000807@illinois.edu>
	<6F48BB93-1A52-4436-9EEC-75530C1DC7AF@apple.com>
Message-ID: <4E6A3523.8080708@illinois.edu>

On 9/9/11 12:51 AM, Chris Lattner wrote:
> Looks fine to me, please commit.

Thanks!  Committed.

I made an earlier formatting change that hasn't appeared on llvm.org 
yet.  Do I need to manually do an svn up on the LLVM web server?

-- John T.

>
> -Chris
>
> On Aug 24, 2011, at 9:06 AM, John Criswell wrote:
>
>> Dear All,
>>
>> Yesterday, I asked Chris if SAFECode qualified as an LLVM sub-project, and he replied that it did.
>>
>> To that end, I've created a patch to add SAFECode to the list of LLVM sub-projects on the main LLVM web page.  The patch is attached for review.  I have commit access, so I can commit the patch once someone reviews it.
>>
>> Thanks in advance,
>>
>> John Criswell
>>
>> <wwwpatch.txt>_______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From insoar at gmail.com  Fri Sep  9 08:04:50 2011
From: insoar at gmail.com (Stepan Dyatkovskiy)
Date: Fri, 9 Sep 2011 17:04:50 +0400
Subject: [llvm-commits] [LLVM,
 llvm-mc] bugfix for bug #10869: Unclear error for files without
 newline at the end of file (ARM, x86).
Message-ID: <CACbV80nhxkyBB=En4E8n7LkBt-tk=x_BCjiRKMqkApMfhGsatQ@mail.gmail.com>

ping...

P.S:
I reattached the patch. In a case of some problems with previous
attachment downloading, use this one. Thats why I used another email
account.

07.09.2011, 03:44, "Stepan Dyatkovskiy" <STPWORLD at yandex.ru>:
> Hello everyone,
>
> Please find attached a patch for review.
> It fixes bug #10869 and adds a regression test for it.
>
> Best regards,
> Stepan.
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
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From kcc at google.com  Fri Sep  9 11:09:49 2011
From: kcc at google.com (Kostya Serebryany)
Date: Fri, 9 Sep 2011 09:09:49 -0700
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <4E6A314C.8050400@free.fr>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
	<CAJdarcH-q+Hx78BH1uxANio1uwAJ9pvf2NKL-sHNDCesKJaGYw@mail.gmail.com>
	<CAN=P9phTgbv3a2TKKSDGcPNqxBP4VO+B2p+bHN5ikzcU2ZSsEg@mail.gmail.com>
	<4E6A2EF5.3030307@illinois.edu> <4E6A314C.8050400@free.fr>
Message-ID: <CAN=P9ph+1GDSVvSaXt-Wny62fz7ENaWqBmp3dtXk8LQyXfq8OA@mail.gmail.com>

On Fri, Sep 9, 2011 at 8:31 AM, Duncan Sands <baldrick at free.fr> wrote:

> Hi John,
>
> > SAFECode also adds calls in llvm.global_ctors in
> > lib/InsertPoolChecks/RegisterRuntimeInitializer.cpp (line 144). At the
> time I
> > wrote the code, ctor priorities were not honored as documented in the
> Language
> > Reference Manual. Through experimentation, I determined that they were
> executed
> > in one order on Linux and another on Mac OS X, and the code in
> > RegisterRuntimeInitializer.cpp uses that information.
> >
> > That said, I seem to recall seeing a commit recently that may have fixed
> the
> > problem with ctor priority numbers. Has that, in fact, been fixed?
>
> yes, it has been fixed.
>
This makes the code simpler indeed. Patch updated.

--kcc




>
> Best wishes, Duncan.
>
>  If so, it
> > would be better to rely upon the documented priority numbers instead of
> on
> > undocumented behavior observed in the wild.
> > :)
> >
> > -- John T.
> >
> >
> >>
> >>     Please get rid of blockHasException and the dependent code; the
> >>     eh_exception intrinsic is going away very soon, and you shouldn't
> run
> >>     into similar issues with the new exception handling framework.
> >>
> >>
> >> Done.
> >>
> >>
> >>     + GlobalValue *asan_mapping_offset =
> >>     + new GlobalVariable(M, IntPtrTy, true,
> GlobalValue::LinkOnceODRLinkage,
> >>     + ConstantInt::get(IntPtrTy, 1ULL << MappingOffsetLog),
> >>     + "__asan_mapping_offset");
> >>     + GlobalValue *asan_mapping_scale =
> >>     + new GlobalVariable(M, IntPtrTy, true,
> GlobalValue::LinkOnceODRLinkage,
> >>     + ConstantInt::get(IntPtrTy, MappingScale),
> >>     + "__asan_mapping_scale");
> >>
> >>     If you use WeakLinkage for these, you won't need the fake loads.
> >>
> >>
> >> Surprisingly these globals *were* optimized away at -O3, at least at
> some point.
> >> Dropped the fake loads for now.
> >>
> >>
> >>     -Eli
> >>
> >>
> >>
> >>
> >> _______________________________________________
> >> llvm-commits mailing list
> >> llvm-commits at cs.uiuc.edu  <mailto:llvm-commits at cs.uiuc.edu>
> >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From krasin at chromium.org  Fri Sep  9 11:17:33 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Fri, 9 Sep 2011 09:17:33 -0700
Subject: [llvm-commits] [PATCH]Add fast path in gold plugin for ELF files
Message-ID: <CAOei5RfBAP-E=w3PP-=EtVcqEKGaWso2KcNemWwKALa19rA9Sw@mail.gmail.com>

HI llvm team!

The attached patch makes the diagnostics in gold-plugin a little bit
more precise
and adds a fast path for skipping non-bitcode files, if Gold version
supports get_view (i.e. gold is more-or-less recent). The latter is
important for two reasons:

- it's the common case for linking with the Gold plugin. It's good to
avoid creating heavy-weight Bitcode reader.
- after the change that has enabled these diagnostic messages, the
users have started to see warnings like "bfd plugin: Failed to create
LTO module: Invalid bitcode signature" which is definitely not
desirable.

OK to commit?

krasin
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From james.molloy at arm.com  Fri Sep  9 11:22:45 2011
From: james.molloy at arm.com (James Molloy)
Date: Fri, 9 Sep 2011 17:22:45 +0100
Subject: [llvm-commits] [LLVM,
	llvm-mc] bugfix for bug #10869: Unclear error for files without
	newline at the end of file (ARM, x86).
In-Reply-To: <CACbV80nhxkyBB=En4E8n7LkBt-tk=x_BCjiRKMqkApMfhGsatQ@mail.gmail.com>
References: <CACbV80nhxkyBB=En4E8n7LkBt-tk=x_BCjiRKMqkApMfhGsatQ@mail.gmail.com>
Message-ID: <001201cc6f0c$b5081c00$1f185400$@molloy@arm.com>

Hi,

Wouldn't it be better to fix the parsers themselves to handle EOF correctly? I
find it slightly unintuitive to have EOF cause two tokens to be emitted -
EndOfStatement and EOF.

Or is this not practicable for some reason?

Cheers,

James

> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of Stepan Dyatkovskiy
> Sent: 09 September 2011 14:05
> To: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [LLVM, llvm-mc] bugfix for bug #10869: Unclear
> error for files without newline at the end of file (ARM, x86).
> 
> ping...
> 
> P.S:
> I reattached the patch. In a case of some problems with previous
> attachment downloading, use this one. Thats why I used another email
> account.
> 
> 07.09.2011, 03:44, "Stepan Dyatkovskiy" <STPWORLD at yandex.ru>:
> > Hello everyone,
> >
> > Please find attached a patch for review.
> > It fixes bug #10869 and adds a regression test for it.
> >
> > Best regards,
> > Stepan.
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From eli.friedman at gmail.com  Fri Sep  9 11:45:14 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Fri, 9 Sep 2011 09:45:14 -0700
Subject: [llvm-commits] [PATCH] Bug 10897 - Seg fault during NEON
 compilation with short3/4 division
In-Reply-To: <4e6a26bc.11ef960a.1641.ffff988dSMTPIN_ADDED@mx.google.com>
References: <4e6a26bc.11ef960a.1641.ffff988dSMTPIN_ADDED@mx.google.com>
Message-ID: <CAJdarcF7=yuYvV6GtiA1rpLD3FZzypK=NcXNiuhi33cio2yi7g@mail.gmail.com>

On Fri, Sep 9, 2011 at 7:43 AM, James Molloy <james.molloy at arm.com> wrote:
> Hi,
>
> The attached patch fixes bug 10897.
>
> The issue was in the DAGCombiner, when constant-folding "insert_vector_emt"
> nodes on a vector that had been size-extended (<3 x int> -> <4 x int> for
> example).
>
> The DAGCombiner was inserting UNDEFs for all values in the vector, and the
> folded insert_vector_emt nodes replace those UNDEFs with actual content. But the
> padding at the end, in the case where the original vector was not a power of 2,
> isn't changed.
>
> This is fine, apart from the type that was being used for UNDEF was the type of
> the vector element, which may not be legal. As DAGTypeLegalizer has already run
> by this point, inserting illegal nodes causes assertion failures later down the
> line.
>
> The fix is to ensure the type of the UNDEFs are legal types:
>
> + ? ?if (!isTypeLegal(EltVT))
> + ? ? ? ?EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
> + ? ?assert(isTypeLegal(EltVT) && "Vector element type was not legal!");

This fix is not right; it will just end up exploding in the same way
on a different testcase.

I've already taken a look at the bug; I wanted to briefly discuss it
with Dan first before committing a fix.

> ----
>
> Aside: The documentation for TargetLowering::getTypeToTransformTo() states that
> if the input parameter is legal, the function is equivalent to the identity
> function. I should therefore not need the "isTypeLegal" check on the line above.
>
> Changing this however broke a lot of codegen tests, both in the ARM and X86
> backends. Does anyone know why that might be the case? For the X86 test I looked
> at, getTypeToTransformTo appeared to be changing an i64 to a v2i64 (IIRC).

That's strange... no idea.

-Eli


From grosbach at apple.com  Fri Sep  9 11:45:31 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 16:45:31 -0000
Subject: [llvm-commits] [llvm] r139371 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909164531.D8BF62A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 11:45:31 2011
New Revision: 139371

URL: http://llvm.org/viewvc/llvm-project?rev=139371&view=rev
Log:
Add FIXME.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139371&r1=139370&r2=139371&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 11:45:31 2011
@@ -648,6 +648,11 @@
 
 
 @------------------------------------------------------------------------------
+@ FIXME: LDRD(literal)
+ at ------------------------------------------------------------------------------
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From james.molloy at arm.com  Fri Sep  9 11:53:40 2011
From: james.molloy at arm.com (James Molloy)
Date: Fri, 9 Sep 2011 17:53:40 +0100
Subject: [llvm-commits] [PATCH] Bug 10897 - Seg fault during NEON
	compilation with short3/4 division
In-Reply-To: <CAJdarcF7=yuYvV6GtiA1rpLD3FZzypK=NcXNiuhi33cio2yi7g@mail.gmail.com>
References: <4e6a26bc.11ef960a.1641.ffff988dSMTPIN_ADDED@mx.google.com>
	<CAJdarcF7=yuYvV6GtiA1rpLD3FZzypK=NcXNiuhi33cio2yi7g@mail.gmail.com>
Message-ID: <001301cc6f11$06bc4270$1434c750$@molloy@arm.com>

Hi Eli,

Thanks for the quick response - I'd noticed you'd commented on the issue but as
you hadn't assigned it, I thought it was dormant.

I admit that my experience in the SelectionDAG code is lacking - could you
please explain (briefly) what the correct fix is, for my information?

Cheers,

James

> -----Original Message-----
> From: Eli Friedman [mailto:eli.friedman at gmail.com]
> Sent: 09 September 2011 17:45
> To: James Molloy
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [PATCH] Bug 10897 - Seg fault during NEON
> compilation with short3/4 division
> 
> On Fri, Sep 9, 2011 at 7:43 AM, James Molloy <james.molloy at arm.com> wrote:
> > Hi,
> >
> > The attached patch fixes bug 10897.
> >
> > The issue was in the DAGCombiner, when constant-folding
> "insert_vector_emt"
> > nodes on a vector that had been size-extended (<3 x int> -> <4 x int> for
> > example).
> >
> > The DAGCombiner was inserting UNDEFs for all values in the vector, and
> the
> > folded insert_vector_emt nodes replace those UNDEFs with actual content.
> But the
> > padding at the end, in the case where the original vector was not a power
> of 2,
> > isn't changed.
> >
> > This is fine, apart from the type that was being used for UNDEF was the
> type of
> > the vector element, which may not be legal. As DAGTypeLegalizer has
> already run
> > by this point, inserting illegal nodes causes assertion failures later
> down the
> > line.
> >
> > The fix is to ensure the type of the UNDEFs are legal types:
> >
> > + ? ?if (!isTypeLegal(EltVT))
> > + ? ? ? ?EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
> > + ? ?assert(isTypeLegal(EltVT) && "Vector element type was not legal!");
> 
> This fix is not right; it will just end up exploding in the same way
> on a different testcase.
> 
> I've already taken a look at the bug; I wanted to briefly discuss it
> with Dan first before committing a fix.
> 
> > ----
> >
> > Aside: The documentation for TargetLowering::getTypeToTransformTo()
> states that
> > if the input parameter is legal, the function is equivalent to the
> identity
> > function. I should therefore not need the "isTypeLegal" check on the line
> above.
> >
> > Changing this however broke a lot of codegen tests, both in the ARM and
> X86
> > backends. Does anyone know why that might be the case? For the X86 test I
> looked
> > at, getTypeToTransformTo appeared to be changing an i64 to a v2i64
> (IIRC).
> 
> That's strange... no idea.
> 
> -Eli





From dpatel at apple.com  Fri Sep  9 12:07:15 2011
From: dpatel at apple.com (Devang Patel)
Date: Fri, 09 Sep 2011 17:07:15 -0000
Subject: [llvm-commits] [llvm] r139374 -
	/llvm/trunk/docs/SourceLevelDebugging.html
Message-ID: <20110909170715.569052A6C12C@llvm.org>

Author: dpatel
Date: Fri Sep  9 12:07:15 2011
New Revision: 139374

URL: http://llvm.org/viewvc/llvm-project?rev=139374&view=rev
Log:
Update docs to reflect recent addition of new CompileUnit elements.

Modified:
    llvm/trunk/docs/SourceLevelDebugging.html

Modified: llvm/trunk/docs/SourceLevelDebugging.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=139374&r1=139373&r2=139374&view=diff
==============================================================================
--- llvm/trunk/docs/SourceLevelDebugging.html (original)
+++ llvm/trunk/docs/SourceLevelDebugging.html Fri Sep  9 12:07:15 2011
@@ -324,6 +324,10 @@
   i1,        ;; True if this is optimized.
   metadata,  ;; Flags
   i32        ;; Runtime version
+  metadata   ;; List of enums types
+  metadata   ;; List of retained types
+  metadata   ;; List of subprograms
+  metadata   ;; List of global variables
 }
 </pre>
 </div>
@@ -337,7 +341,8 @@
 <p>Compile unit descriptors provide the root context for objects declared in a
    specific compilation unit. File descriptors are defined using this context.
    These descriptors are collected by a named metadata 
-   <tt>!llvm.dbg.cu</tt>.
+   <tt>!llvm.dbg.cu</tt>. Compile unit descriptor keeps track of subprograms,
+   global variables and type information.
 
 </div>
 



From pdox at google.com  Fri Sep  9 12:23:18 2011
From: pdox at google.com (David Meyer)
Date: Fri, 9 Sep 2011 10:23:18 -0700
Subject: [llvm-commits] [PATCH] Native Client: Set correct ELF metadata
In-Reply-To: <CAAU48J+6PAwseF5FGGK5X+dU7voce0As_QfZWK2zHMi9BvZUXg@mail.gmail.com>
References: <CAAU48JLL8tUyV7ckntm7a6aHUDWuFy5W3Qsgs2szkenZcnU5zA@mail.gmail.com>
	<3F91B6EC-BEE8-4445-B27E-3B15DC8CB7A8@apple.com>
	<CAAU48J+6PAwseF5FGGK5X+dU7voce0As_QfZWK2zHMi9BvZUXg@mail.gmail.com>
Message-ID: <CAAU48JLnLEcSxyzRYzJLo22oKiFF596hsoMNnTOLd_wQLaGt9g@mail.gmail.com>

Bill and everyone,

Please ignore this patch, it is not needed anymore.

- pdox

From atrick at apple.com  Fri Sep  9 12:35:11 2011
From: atrick at apple.com (Andrew Trick)
Date: Fri, 09 Sep 2011 17:35:11 -0000
Subject: [llvm-commits] [llvm] r139375 -
	/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
Message-ID: <20110909173511.264B82A6C12C@llvm.org>

Author: atrick
Date: Fri Sep  9 12:35:10 2011
New Revision: 139375

URL: http://llvm.org/viewvc/llvm-project?rev=139375&view=rev
Log:
Comment formatting.

Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=139375&r1=139374&r2=139375&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Fri Sep  9 12:35:10 2011
@@ -621,12 +621,12 @@
 //  To be replaced by -disable-iv-rewrite.
 //===----------------------------------------------------------------------===//
 
-// FIXME: It is an extremely bad idea to indvar substitute anything more
-// complex than affine induction variables.  Doing so will put expensive
-// polynomial evaluations inside of the loop, and the str reduction pass
-// currently can only reduce affine polynomials.  For now just disable
-// indvar subst on anything more complex than an affine addrec, unless
-// it can be expanded to a trivial value.
+/// FIXME: It is an extremely bad idea to indvar substitute anything more
+/// complex than affine induction variables.  Doing so will put expensive
+/// polynomial evaluations inside of the loop, and the str reduction pass
+/// currently can only reduce affine polynomials.  For now just disable
+/// indvar subst on anything more complex than an affine addrec, unless
+/// it can be expanded to a trivial value.
 static bool isSafe(const SCEV *S, const Loop *L, ScalarEvolution *SE) {
   // Loop-invariant values are safe.
   if (SE->isLoopInvariant(S, L)) return true;
@@ -637,7 +637,8 @@
     return AR->isAffine();
 
   // An add is safe it all its operands are safe.
-  if (const SCEVCommutativeExpr *Commutative = dyn_cast<SCEVCommutativeExpr>(S)) {
+  if (const SCEVCommutativeExpr *Commutative
+      = dyn_cast<SCEVCommutativeExpr>(S)) {
     for (SCEVCommutativeExpr::op_iterator I = Commutative->op_begin(),
          E = Commutative->op_end(); I != E; ++I)
       if (!isSafe(*I, L, SE)) return false;
@@ -950,11 +951,11 @@
   return true;
 }
 
-// GetWideRecurrence - Is this instruction potentially interesting from IVUsers'
-// perspective after widening it's type? In other words, can the extend be
-// safely hoisted out of the loop with SCEV reducing the value to a recurrence
-// on the same loop. If so, return the sign or zero extended
-// recurrence. Otherwise return NULL.
+/// GetWideRecurrence - Is this instruction potentially interesting from
+/// IVUsers' perspective after widening it's type? In other words, can the
+/// extend be safely hoisted out of the loop with SCEV reducing the value to a
+/// recurrence on the same loop. If so, return the sign or zero extended
+/// recurrence. Otherwise return NULL.
 const SCEVAddRecExpr *WidenIV::GetWideRecurrence(Instruction *NarrowUse) {
   if (!SE->isSCEVable(NarrowUse->getType()))
     return 0;
@@ -1270,9 +1271,9 @@
 //  LinearFunctionTestReplace and its kin. Rewrite the loop exit condition.
 //===----------------------------------------------------------------------===//
 
-// Check for expressions that ScalarEvolution generates to compute
-// BackedgeTakenInfo. If these expressions have not been reduced, then expanding
-// them may incur additional cost (albeit in the loop preheader).
+/// Check for expressions that ScalarEvolution generates to compute
+/// BackedgeTakenInfo. If these expressions have not been reduced, then
+/// expanding them may incur additional cost (albeit in the loop preheader).
 static bool isHighCostExpansion(const SCEV *S, BranchInst *BI,
                                 ScalarEvolution *SE) {
   // If the backedge-taken count is a UDiv, it's very likely a UDiv that



From clattner at apple.com  Fri Sep  9 12:40:48 2011
From: clattner at apple.com (Chris Lattner)
Date: Fri, 09 Sep 2011 10:40:48 -0700
Subject: [llvm-commits] Patch to Add SAFECode as a LLVM Sub-Project
In-Reply-To: <4E6A3523.8080708@illinois.edu>
References: <4E552194.1000807@illinois.edu>
	<6F48BB93-1A52-4436-9EEC-75530C1DC7AF@apple.com>
	<4E6A3523.8080708@illinois.edu>
Message-ID: <E1E66326-FB45-4957-8402-0D368CF86049@apple.com>

That is really weird, the post-commit script is supposed to keep the website up to date.  It looks like it is broken.

-Chris

On Sep 9, 2011, at 8:47 AM, John Criswell wrote:

> On 9/9/11 12:51 AM, Chris Lattner wrote:
>> Looks fine to me, please commit.
> 
> Thanks!  Committed.
> 
> I made an earlier formatting change that hasn't appeared on llvm.org yet.  Do I need to manually do an svn up on the LLVM web server?
> 
> -- John T.
> 
>> 
>> -Chris
>> 
>> On Aug 24, 2011, at 9:06 AM, John Criswell wrote:
>> 
>>> Dear All,
>>> 
>>> Yesterday, I asked Chris if SAFECode qualified as an LLVM sub-project, and he replied that it did.
>>> 
>>> To that end, I've created a patch to add SAFECode to the list of LLVM sub-projects on the main LLVM web page.  The patch is attached for review.  I have commit access, so I can commit the patch once someone reviews it.
>>> 
>>> Thanks in advance,
>>> 
>>> John Criswell
>>> 
>>> <wwwpatch.txt>_______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 


From criswell at illinois.edu  Fri Sep  9 12:54:37 2011
From: criswell at illinois.edu (John Criswell)
Date: Fri, 9 Sep 2011 12:54:37 -0500
Subject: [llvm-commits] Patch to Add SAFECode as a LLVM Sub-Project
In-Reply-To: <E1E66326-FB45-4957-8402-0D368CF86049@apple.com>
References: <4E552194.1000807@illinois.edu>
	<6F48BB93-1A52-4436-9EEC-75530C1DC7AF@apple.com>
	<4E6A3523.8080708@illinois.edu>
	<E1E66326-FB45-4957-8402-0D368CF86049@apple.com>
Message-ID: <4E6A52DD.6040507@illinois.edu>

On 9/9/11 12:40 PM, Chris Lattner wrote:
> That is really weird, the post-commit script is supposed to keep the website up to date.  It looks like it is broken.

Just to be certain I'm doing things right, I should be committing to 
http://llvm.org/svn/llvm-project/www/trunk, right?

-- John T.

>
> -Chris
>
> On Sep 9, 2011, at 8:47 AM, John Criswell wrote:
>
>> On 9/9/11 12:51 AM, Chris Lattner wrote:
>>> Looks fine to me, please commit.
>> Thanks!  Committed.
>>
>> I made an earlier formatting change that hasn't appeared on llvm.org yet.  Do I need to manually do an svn up on the LLVM web server?
>>
>> -- John T.
>>
>>> -Chris
>>>
>>> On Aug 24, 2011, at 9:06 AM, John Criswell wrote:
>>>
>>>> Dear All,
>>>>
>>>> Yesterday, I asked Chris if SAFECode qualified as an LLVM sub-project, and he replied that it did.
>>>>
>>>> To that end, I've created a patch to add SAFECode to the list of LLVM sub-projects on the main LLVM web page.  The patch is attached for review.  I have commit access, so I can commit the patch once someone reviews it.
>>>>
>>>> Thanks in advance,
>>>>
>>>> John Criswell
>>>>
>>>> <wwwpatch.txt>_______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From stoklund at 2pi.dk  Fri Sep  9 13:11:42 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 09 Sep 2011 18:11:42 -0000
Subject: [llvm-commits] [llvm] r139378 -
	/llvm/trunk/lib/CodeGen/InlineSpiller.cpp
Message-ID: <20110909181142.2B3BE2A6C12C@llvm.org>

Author: stoklund
Date: Fri Sep  9 13:11:41 2011
New Revision: 139378

URL: http://llvm.org/viewvc/llvm-project?rev=139378&view=rev
Log:
Reapply r139247: Cache intermediate results during traceSiblingValue.

In some cases such as interpreters using indirectbr, the CFG can be very
complicated, and live range splitting may be forced to insert a large
number of phi-defs.  When that happens, traceSiblingValue can spend a
lot of time zipping around in the CFG looking for defs and reloads.

This patch causes more information to be cached in SibValues, and the
cached values are used to terminate searches early.  This speeds up
spilling by 20x in one interpreter test case.  For more typical code,
this is just a 10% speedup of spilling.

The previous version had bugs that caused miscompilations. They have
been fixed.

Modified:
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=139378&r1=139377&r2=139378&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Fri Sep  9 13:11:41 2011
@@ -17,6 +17,7 @@
 #include "LiveRangeEdit.h"
 #include "VirtRegMap.h"
 #include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/TinyPtrVector.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
 #include "llvm/CodeGen/LiveStackAnalysis.h"
@@ -75,30 +76,55 @@
   // Values that failed to remat at some point.
   SmallPtrSet<VNInfo*, 8> UsedValues;
 
+public:
   // Information about a value that was defined by a copy from a sibling
   // register.
   struct SibValueInfo {
     // True when all reaching defs were reloads: No spill is necessary.
     bool AllDefsAreReloads;
 
+    // True when value is defined by an original PHI not from splitting.
+    bool DefByOrigPHI;
+
     // The preferred register to spill.
     unsigned SpillReg;
 
     // The value of SpillReg that should be spilled.
     VNInfo *SpillVNI;
 
+    // The block where SpillVNI should be spilled. Currently, this must be the
+    // block containing SpillVNI->def.
+    MachineBasicBlock *SpillMBB;
+
     // A defining instruction that is not a sibling copy or a reload, or NULL.
     // This can be used as a template for rematerialization.
     MachineInstr *DefMI;
 
+    // List of values that depend on this one.  These values are actually the
+    // same, but live range splitting has placed them in different registers,
+    // or SSA update needed to insert PHI-defs to preserve SSA form.  This is
+    // copies of the current value and phi-kills.  Usually only phi-kills cause
+    // more than one dependent value.
+    TinyPtrVector<VNInfo*> Deps;
+
     SibValueInfo(unsigned Reg, VNInfo *VNI)
-      : AllDefsAreReloads(false), SpillReg(Reg), SpillVNI(VNI), DefMI(0) {}
+      : AllDefsAreReloads(true), DefByOrigPHI(false),
+        SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
+
+    // Returns true when a def has been found.
+    bool hasDef() const { return DefByOrigPHI || DefMI; }
   };
 
+private:
   // Values in RegsToSpill defined by sibling copies.
   typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap;
   SibValueMap SibValues;
 
+  // Values live-out from basic blocks.  This is the same as
+  // LI.getVNInfoAt(LIS.getMBBEndIdx(MBB).getPrevSlot())
+  typedef DenseMap<MachineBasicBlock*, VNInfo*> LiveOutMap;
+  LiveOutMap LiveOutValues;
+
   // Dead defs generated during spilling.
   SmallVector<MachineInstr*, 8> DeadDefs;
 
@@ -134,6 +160,7 @@
 
   bool isSibling(unsigned Reg);
   MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*);
+  void propagateSiblingValue(SibValueMap::iterator, VNInfo *VNI = 0);
   void analyzeSiblingValues();
 
   bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
@@ -282,6 +309,153 @@
            VRM.getOriginal(Reg) == Original;
 }
 
+#ifndef NDEBUG
+static raw_ostream &operator<<(raw_ostream &OS,
+                               const InlineSpiller::SibValueInfo &SVI) {
+  OS << "spill " << PrintReg(SVI.SpillReg) << ':'
+     << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def;
+  if (SVI.SpillMBB)
+    OS << " in BB#" << SVI.SpillMBB->getNumber();
+  if (SVI.AllDefsAreReloads)
+    OS << " all-reloads";
+  if (SVI.DefByOrigPHI)
+    OS << " orig-phi";
+  OS << " deps[";
+  for (unsigned i = 0, e = SVI.Deps.size(); i != e; ++i)
+    OS << ' ' << SVI.Deps[i]->id << '@' << SVI.Deps[i]->def;
+  OS << " ]";
+  if (SVI.DefMI)
+    OS << " def: " << *SVI.DefMI;
+  else
+    OS << '\n';
+  return OS;
+}
+#endif
+
+/// propagateSiblingValue - Propagate the value in SVI to dependents if it is
+/// known.  Otherwise remember the dependency for later.
+///
+/// @param SVI SibValues entry to propagate.
+/// @param VNI Dependent value, or NULL to propagate to all saved dependents.
+void InlineSpiller::propagateSiblingValue(SibValueMap::iterator SVI,
+                                          VNInfo *VNI) {
+  // When VNI is non-NULL, add it to SVI's deps, and only propagate to that.
+  TinyPtrVector<VNInfo*> FirstDeps;
+  if (VNI) {
+    FirstDeps.push_back(VNI);
+    SVI->second.Deps.push_back(VNI);
+  }
+
+  // Has the value been completely determined yet?  If not, defer propagation.
+  if (!SVI->second.hasDef())
+    return;
+
+  // Work list of values to propagate.  It would be nice to use a SetVector
+  // here, but then we would be forced to use a SmallSet.
+  SmallVector<SibValueMap::iterator, 8> WorkList(1, SVI);
+  SmallPtrSet<VNInfo*, 8> WorkSet;
+
+  do {
+    SVI = WorkList.pop_back_val();
+    WorkSet.erase(SVI->first);
+    TinyPtrVector<VNInfo*> *Deps = VNI ? &FirstDeps : &SVI->second.Deps;
+    VNI = 0;
+
+    SibValueInfo &SV = SVI->second;
+    if (!SV.SpillMBB)
+      SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
+
+    DEBUG(dbgs() << "  prop to " << Deps->size() << ": "
+                 << SVI->first->id << '@' << SVI->first->def << ":\t" << SV);
+
+    assert(SV.hasDef() && "Propagating undefined value");
+
+    // Should this value be propagated as a preferred spill candidate?  We don't
+    // propagate values of registers that are about to spill.
+    bool PropSpill = !isRegToSpill(SV.SpillReg);
+    unsigned SpillDepth = ~0u;
+
+    for (TinyPtrVector<VNInfo*>::iterator DepI = Deps->begin(),
+         DepE = Deps->end(); DepI != DepE; ++DepI) {
+      SibValueMap::iterator DepSVI = SibValues.find(*DepI);
+      assert(DepSVI != SibValues.end() && "Dependent value not in SibValues");
+      SibValueInfo &DepSV = DepSVI->second;
+      if (!DepSV.SpillMBB)
+        DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
+
+      bool Changed = false;
+
+      // Propagate defining instruction.
+      if (!DepSV.hasDef()) {
+        Changed = true;
+        DepSV.DefMI = SV.DefMI;
+        DepSV.DefByOrigPHI = SV.DefByOrigPHI;
+      }
+
+      // Propagate AllDefsAreReloads.  For PHI values, this computes an AND of
+      // all predecessors.
+      if (!SV.AllDefsAreReloads && DepSV.AllDefsAreReloads) {
+        Changed = true;
+        DepSV.AllDefsAreReloads = false;
+      }
+
+      // Propagate best spill value.
+      if (PropSpill && SV.SpillVNI != DepSV.SpillVNI) {
+        if (SV.SpillMBB == DepSV.SpillMBB) {
+          // DepSV is in the same block.  Hoist when dominated.
+          if (SV.SpillVNI->def < DepSV.SpillVNI->def) {
+            // This is an alternative def earlier in the same MBB.
+            // Hoist the spill as far as possible in SpillMBB. This can ease
+            // register pressure:
+            //
+            //   x = def
+            //   y = use x
+            //   s = copy x
+            //
+            // Hoisting the spill of s to immediately after the def removes the
+            // interference between x and y:
+            //
+            //   x = def
+            //   spill x
+            //   y = use x<kill>
+            //
+            Changed = true;
+            DepSV.SpillReg = SV.SpillReg;
+            DepSV.SpillVNI = SV.SpillVNI;
+            DepSV.SpillMBB = SV.SpillMBB;
+          }
+        } else {
+          // DepSV is in a different block.
+          if (SpillDepth == ~0u)
+            SpillDepth = Loops.getLoopDepth(SV.SpillMBB);
+
+          // Also hoist spills to blocks with smaller loop depth, but make sure
+          // that the new value dominates.  Non-phi dependents are always
+          // dominated, phis need checking.
+          if ((Loops.getLoopDepth(DepSV.SpillMBB) > SpillDepth) &&
+              (!DepSVI->first->isPHIDef() ||
+               MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
+            Changed = true;
+            DepSV.SpillReg = SV.SpillReg;
+            DepSV.SpillVNI = SV.SpillVNI;
+            DepSV.SpillMBB = SV.SpillMBB;
+          }
+        }
+      }
+
+      if (!Changed)
+        continue;
+
+      // Something changed in DepSVI. Propagate to dependents.
+      if (WorkSet.insert(DepSVI->first))
+        WorkList.push_back(DepSVI);
+
+      DEBUG(dbgs() << "  update " << DepSVI->first->id << '@'
+            << DepSVI->first->def << " to:\t" << DepSV);
+    }
+  } while (!WorkList.empty());
+}
+
 /// traceSiblingValue - Trace a value that is about to be spilled back to the
 /// real defining instructions by looking through sibling copies. Always stay
 /// within the range of OrigVNI so the registers are known to carry the same
@@ -294,84 +468,68 @@
 ///
 MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
                                                VNInfo *OrigVNI) {
+  // Check if a cached value already exists.
+  SibValueMap::iterator SVI;
+  bool Inserted;
+  tie(SVI, Inserted) =
+    SibValues.insert(std::make_pair(UseVNI, SibValueInfo(UseReg, UseVNI)));
+  if (!Inserted) {
+    DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':'
+                 << UseVNI->id << '@' << UseVNI->def << ' ' << SVI->second);
+    return SVI->second.DefMI;
+  }
+
   DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
                << UseVNI->id << '@' << UseVNI->def << '\n');
-  SmallPtrSet<VNInfo*, 8> Visited;
+
+  // List of (Reg, VNI) that have been inserted into SibValues, but need to be
+  // processed.
   SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList;
   WorkList.push_back(std::make_pair(UseReg, UseVNI));
 
-  // Best spill candidate seen so far. This must dominate UseVNI.
-  SibValueInfo SVI(UseReg, UseVNI);
-  MachineBasicBlock *UseMBB = LIS.getMBBFromIndex(UseVNI->def);
-  MachineBasicBlock *SpillMBB = UseMBB;
-  unsigned SpillDepth = Loops.getLoopDepth(SpillMBB);
-  bool SeenOrigPHI = false; // Original PHI met.
-
   do {
     unsigned Reg;
     VNInfo *VNI;
     tie(Reg, VNI) = WorkList.pop_back_val();
-    if (!Visited.insert(VNI))
-      continue;
+    DEBUG(dbgs() << "  " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
+                 << ":\t");
 
-    // Is this value a better spill candidate?
-    if (!isRegToSpill(Reg)) {
-      MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
-      if (MBB == SpillMBB) {
-        // This is an alternative def earlier in the same MBB.
-        // Hoist the spill as far as possible in SpillMBB. This can ease
-        // register pressure:
-        //
-        //   x = def
-        //   y = use x
-        //   s = copy x
-        //
-        // Hoisting the spill of s to immediately after the def removes the
-        // interference between x and y:
-        //
-        //   x = def
-        //   spill x
-        //   y = use x<kill>
-        //
-        if (VNI->def < SVI.SpillVNI->def) {
-          DEBUG(dbgs() << "  hoist in BB#" << MBB->getNumber() << ": "
-                       << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
-                       << '\n');
-          SVI.SpillReg = Reg;
-          SVI.SpillVNI = VNI;
-        }
-      } else if (MBB != UseMBB && MDT.dominates(MBB, UseMBB)) {
-        // This is a valid spill location dominating UseVNI.
-        // Prefer to spill at a smaller loop depth.
-        unsigned Depth = Loops.getLoopDepth(MBB);
-        if (Depth < SpillDepth) {
-          DEBUG(dbgs() << "  spill depth " << Depth << ": " << PrintReg(Reg)
-                       << ':' << VNI->id << '@' << VNI->def << '\n');
-          SVI.SpillReg = Reg;
-          SVI.SpillVNI = VNI;
-          SpillMBB = MBB;
-          SpillDepth = Depth;
-        }
-      }
-    }
+    // First check if this value has already been computed.
+    SVI = SibValues.find(VNI);
+    assert(SVI != SibValues.end() && "Missing SibValues entry");
 
     // Trace through PHI-defs created by live range splitting.
     if (VNI->isPHIDef()) {
       if (VNI->def == OrigVNI->def) {
-        DEBUG(dbgs() << "  orig phi value " << PrintReg(Reg) << ':'
-                     << VNI->id << '@' << VNI->def << '\n');
-        SeenOrigPHI = true;
+        DEBUG(dbgs() << "orig phi value\n");
+        SVI->second.DefByOrigPHI = true;
+        SVI->second.AllDefsAreReloads = false;
+        propagateSiblingValue(SVI);
         continue;
       }
       // Get values live-out of predecessors.
       LiveInterval &LI = LIS.getInterval(Reg);
       MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
+      DEBUG(dbgs() << "split phi value, check " << MBB->pred_size()
+                   << " preds\n");
       for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
              PE = MBB->pred_end(); PI != PE; ++PI) {
-        VNInfo *PVNI = LI.getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
-        if (PVNI)
+        // Use a cache of block live-out values.  This is faster than using
+        // getVNInfoAt on complex intervals.
+        VNInfo *&PVNI = LiveOutValues[*PI];
+        if (!PVNI)
+          PVNI = LI.getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
+        if (!PVNI)
+          continue;
+        // Known predecessor value? Try an insertion.
+        tie(SVI, Inserted) =
+          SibValues.insert(std::make_pair(PVNI, SibValueInfo(Reg, PVNI)));
+        // This is the first time we see PVNI, add it to the worklist.
+        if (Inserted)
           WorkList.push_back(std::make_pair(Reg, PVNI));
+        propagateSiblingValue(SVI, VNI);
       }
+      // Next work list item.
       continue;
     }
 
@@ -384,46 +542,43 @@
         LiveInterval &SrcLI = LIS.getInterval(SrcReg);
         VNInfo *SrcVNI = SrcLI.getVNInfoAt(VNI->def.getUseIndex());
         assert(SrcVNI && "Copy from non-existing value");
-        DEBUG(dbgs() << "  copy of " << PrintReg(SrcReg) << ':'
+        DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':'
                      << SrcVNI->id << '@' << SrcVNI->def << '\n');
-        WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
+        // Known sibling source value? Try an insertion.
+        tie(SVI, Inserted) = SibValues.insert(std::make_pair(SrcVNI,
+                                                 SibValueInfo(SrcReg, SrcVNI)));
+        // This is the first time we see Src, add it to the worklist.
+        if (Inserted)
+          WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
+        propagateSiblingValue(SVI, VNI);
+        // Next work list item.
         continue;
       }
     }
 
     // Track reachable reloads.
+    SVI->second.DefMI = MI;
+    SVI->second.SpillMBB = MI->getParent();
     int FI;
     if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
-      DEBUG(dbgs() << "  reload " << PrintReg(Reg) << ':'
-                   << VNI->id << "@" << VNI->def << '\n');
-      SVI.AllDefsAreReloads = true;
+      DEBUG(dbgs() << "reload\n");
+      propagateSiblingValue(SVI);
+      // Next work list item.
       continue;
     }
 
-    // We have an 'original' def. Don't record trivial cases.
-    if (VNI == UseVNI) {
-      DEBUG(dbgs() << "Not a sibling copy.\n");
-      return MI;
-    }
-
     // Potential remat candidate.
-    DEBUG(dbgs() << "  def " << PrintReg(Reg) << ':'
-                 << VNI->id << '@' << VNI->def << '\t' << *MI);
-    SVI.DefMI = MI;
+    DEBUG(dbgs() << "def " << *MI);
+    SVI->second.AllDefsAreReloads = false;
+    propagateSiblingValue(SVI);
   } while (!WorkList.empty());
 
-  if (SeenOrigPHI || SVI.DefMI)
-    SVI.AllDefsAreReloads = false;
-
-  DEBUG({
-    if (SVI.AllDefsAreReloads)
-      dbgs() << "All defs are reloads.\n";
-    else
-      dbgs() << "Prefer to spill " << PrintReg(SVI.SpillReg) << ':'
-             << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def << '\n';
-  });
-  SibValues.insert(std::make_pair(UseVNI, SVI));
-  return SVI.DefMI;
+  // Look up the value we were looking for.  We already did this lokup at the
+  // top of the function, but SibValues may have been invalidated.
+  SVI = SibValues.find(UseVNI);
+  assert(SVI != SibValues.end() && "Didn't compute requested info");
+  DEBUG(dbgs() << "  traced to:\t" << SVI->second);
+  return SVI->second.DefMI;
 }
 
 /// analyzeSiblingValues - Trace values defined by sibling copies back to
@@ -432,6 +587,7 @@
 /// Keep track of values that may be rematerializable.
 void InlineSpiller::analyzeSiblingValues() {
   SibValues.clear();
+  LiveOutValues.clear();
 
   // No siblings at all?
   if (Edit->getReg() == Original)
@@ -506,6 +662,7 @@
 
   // Already spilled everywhere.
   if (SVI.AllDefsAreReloads) {
+    DEBUG(dbgs() << "\tno spill needed: " << SVI);
     ++NumOmitReloadSpill;
     return true;
   }



From jvoung at google.com  Fri Sep  9 13:22:56 2011
From: jvoung at google.com (Jan Voung)
Date: Fri, 9 Sep 2011 11:22:56 -0700
Subject: [llvm-commits] [llvm] [PATCH] pruning llvm -- only include
 intrinsics for targets S, given --enable-targets=S
In-Reply-To: <CACfqt7iatV2dat_mV_ibHvOWE+_7KOG_RRCWL98btmukdQLiUA@mail.gmail.com>
References: <CACfqt7iatV2dat_mV_ibHvOWE+_7KOG_RRCWL98btmukdQLiUA@mail.gmail.com>
Message-ID: <CACfqt7jhxuGGmQwfFAhEyHnRn=yayig+UuAgbq-YDyho+et7Fg@mail.gmail.com>

Attached is one more patch for dragonegg to go with these other patches.
It simply generates a Make error when there is a mismatch between the
dragonegg target and the backend targets enabled in llvm, by asking
llvm-config.
It also possible to go without this patch and simply have compile errors
when the intrinsics referenced by dragonegg aren't actually defined by llvm
(since it's been pruned out), but the error would be more mysterious.

Otherwise, the previously attached llvm and clang patches should still apply
(checked at rev 139374).

Thanks!

On Thu, Sep 1, 2011 at 1:42 PM, Jan Voung <jvoung at google.com> wrote:

> Hi all,
>
> Here is a set of patches (one llvm, one clang) that could trim the size of
> the llvm backends. This is one changes Intrinsics.td to only include
> Intrinsics for the targets that were enabled via --enable-targets=X,Y,Z.
> This is about ~100KB savings if you only enable X86 (haven't measured
> others, but it should be greater for targets with fewer intrinsics).
>
> "size llc" w/ only x86
> BEFORE:
> text data bss dec hex filename
> 11328502 502632 36976 11868110 b517ce Release+Asserts/bin/llc
>
> AFTER:
> text data bss dec hex filename
> 11232165 499080 36976 11768221 b3919d Release+Asserts/bin/llc
>
> NOTE:* *this affects the "opt" tool and other bitcode tools that may
> depend on Intrinsics.td having all intrinsics available.
>
> I'm not sure how to properly get "svn mv"'ed stuff to show up in the
> attached files, but they show up in the online views:
> http://codereview.chromium.org/7792066/
> http://codereview.chromium.org/7824006/
>
> Other detail:
>
> (a) This is done by adding an "include_if" directive to TableGen (vs trying
> to do a full-fledged #if def / #else / #endif).
>
> (b) Add CPP defines to handle inline code the depends on these intrinsics
> (e.g., in InstCombine). See second attached patch for clang side changes.
> I haven't looked into llvm-gcc or dragon egg dependencies on LLVM's
> Intrinsics.td, so it may take some more work to land.
>
> (c) move tests that are target dependent into target-specific directories.
> Previously tests would assume that "opt" understood target specific
> intrinsics.
>
> TEST= build llvm w/ --enable-targets=all, --enable-targets=x86,
> --enable-targets=arm, run "make check" in each case. They pass, except for
> JIT and generic tests w/ --enable-target=arm since my host machine is x86.
> Are there other tests, I should try?
>
> As noted above, there might be more work needed for dragon egg and
> llvm-gcc, but is the overall approach okay? Thanks!
>
> - Jan
>
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From grosbach at apple.com  Fri Sep  9 13:37:27 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 18:37:27 -0000
Subject: [llvm-commits] [llvm] r139381 - in /llvm/trunk:
 lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMISelLowering.cpp
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
 lib/Target/ARM/InstPrinter/ARMInstPrinter.h
 lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
 test/MC/ARM/basic-thumb2-instructions.s utils/TableGen/EDEmitter.cpp
Message-ID: <20110909183727.EB7CE2A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 13:37:27 2011
New Revision: 139381

URL: http://llvm.org/viewvc/llvm-project?rev=139381&view=rev
Log:
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=139381&r1=139380&r2=139381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Fri Sep  9 13:37:27 2011
@@ -211,6 +211,8 @@
       const { return 0; }
     unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
+    unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op)
+      const { return 0; }
     unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
       const { return 0; }
     unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=139381&r1=139380&r2=139381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Sep  9 13:37:27 2011
@@ -5067,7 +5067,10 @@
   //   cmp dest, oldval
   //   bne exitMBB
   BB = loop1MBB;
-  AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
+  MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
+  if (ldrOpc == ARM::t2LDREX)
+    MIB.addImm(0);
+  AddDefaultPred(MIB);
   AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
                  .addReg(dest).addReg(oldval));
   BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
@@ -5080,8 +5083,10 @@
   //   cmp scratch, #0
   //   bne loop1MBB
   BB = loop2MBB;
-  AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
-                 .addReg(ptr));
+  MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
+  if (strOpc == ARM::t2STREX)
+    MIB.addImm(0);
+  AddDefaultPred(MIB);
   AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
                  .addReg(scratch).addImm(0));
   BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
@@ -5167,7 +5172,10 @@
   //   bne- loopMBB
   //   fallthrough --> exitMBB
   BB = loopMBB;
-  AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
+  MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
+  if (ldrOpc == ARM::t2LDREX)
+    MIB.addImm(0);
+  AddDefaultPred(MIB);
   if (BinOpcode) {
     // operand order needs to go the other way for NAND
     if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
@@ -5178,8 +5186,10 @@
                      addReg(dest).addReg(incr)).addReg(0);
   }
 
-  AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
-                 .addReg(ptr));
+  MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
+  if (strOpc == ARM::t2STREX)
+    MIB.addImm(0);
+  AddDefaultPred(MIB);
   AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
                  .addReg(scratch).addImm(0));
   BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
@@ -5274,7 +5284,10 @@
   //   bne- loopMBB
   //   fallthrough --> exitMBB
   BB = loopMBB;
-  AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
+  MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
+  if (ldrOpc == ARM::t2LDREX)
+    MIB.addImm(0);
+  AddDefaultPred(MIB);
 
   // Sign extend the value, if necessary.
   if (signExtend && extendOpc) {
@@ -5290,8 +5303,10 @@
   BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
          .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
 
-  AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
-                 .addReg(ptr));
+  MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
+  if (strOpc == ARM::t2STREX)
+    MIB.addImm(0);
+  AddDefaultPred(MIB);
   AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
                  .addReg(scratch).addImm(0));
   BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139381&r1=139380&r2=139381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Sep  9 13:37:27 2011
@@ -180,6 +180,18 @@
   let DecoderMethod = "DecodeT2Imm8S4";
 }
 
+// t2addrmode_imm0_1020s4  := reg + (imm8 << 2)
+def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
+  let Name = "MemImm0_1020s4Offset";
+}
+def t2addrmode_imm0_1020s4 : Operand<i32> {
+  let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
+  let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
+  let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
+  let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
+  let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
+}
+
 // t2addrmode_so_reg  := reg + (reg << imm2)
 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
 def t2addrmode_so_reg : Operand<i32>,
@@ -191,16 +203,6 @@
   let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
 }
 
-// t2addrmode_reg := reg
-// Used by load/store exclusive instructions. Useful to enable right assembly
-// parsing and printing. Not used for any codegen matching.
-//
-def t2addrmode_reg : Operand<i32> {
-  let PrintMethod = "printAddrMode7Operand";
-  let DecoderMethod = "DecodeGPRRegisterClass";
-  let MIOperandInfo = (ops GPR);
-}
-
 //===----------------------------------------------------------------------===//
 // Multiclass helpers...
 //
@@ -2877,28 +2879,27 @@
 }
 
 let mayLoad = 1 in {
-def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
+def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldrexb", "\t$Rt, $addr", "", []>;
-def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
+def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldrexh", "\t$Rt, $addr", "", []>;
-def t2LDREX  : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
+def t2LDREX  : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
                        AddrModeNone, 4, NoItinerary,
                        "ldrex", "\t$Rt, $addr", "", []> {
+  bits<4> Rt;
+  bits<12> addr;
   let Inst{31-27} = 0b11101;
   let Inst{26-20} = 0b0000101;
-  let Inst{11-8} = 0b1111;
-  let Inst{7-0} = 0b00000000; // imm8 = 0
-
-  bits<4> Rt;
-  bits<4> addr;
-  let Inst{19-16} = addr;
+  let Inst{19-16} = addr{11-8};
   let Inst{15-12} = Rt;
+  let Inst{11-8} = 0b1111;
+  let Inst{7-0} = addr{7-0};
 }
 let hasExtraDefRegAllocReq = 1 in
 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
-                         (ins t2addrmode_reg:$addr),
+                         (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldrexd", "\t$Rt, $Rt2, $addr", "",
                          [], {?, ?, ?, ?}> {
@@ -2909,33 +2910,33 @@
 
 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
-                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
+                         (ins rGPR:$Rt, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "strexb", "\t$Rd, $Rt, $addr", "", []>;
 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
-                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
+                         (ins rGPR:$Rt, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "strexh", "\t$Rd, $Rt, $addr", "", []>;
-def t2STREX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
+def t2STREX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
+                             t2addrmode_imm0_1020s4:$addr),
                   AddrModeNone, 4, NoItinerary,
                   "strex", "\t$Rd, $Rt, $addr", "",
                   []> {
-  let Inst{31-27} = 0b11101;
-  let Inst{26-20} = 0b0000100;
-  let Inst{7-0} = 0b00000000; // imm8 = 0
-
   bits<4> Rd;
-  bits<4> addr;
   bits<4> Rt;
-  let Inst{11-8}  = Rd;
-  let Inst{19-16} = addr;
+  bits<12> addr;
+  let Inst{31-27} = 0b11101;
+  let Inst{26-20} = 0b0000100;
+  let Inst{19-16} = addr{11-8};
   let Inst{15-12} = Rt;
+  let Inst{11-8}  = Rd;
+  let Inst{7-0} = addr{7-0};
 }
 }
 
 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
-                         (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
+                         (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
                          {?, ?, ?, ?}> {

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139381&r1=139380&r2=139381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Sep  9 13:37:27 2011
@@ -756,6 +756,14 @@
     int64_t Val = Mem.OffsetImm->getValue();
     return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
   }
+  bool isMemImm0_1020s4Offset() const {
+    if (Kind != Memory || Mem.OffsetRegNum != 0)
+      return false;
+    // Immediate offset a multiple of 4 in range [0, 1020].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
+  }
   bool isMemImm8Offset() const {
     if (Kind != Memory || Mem.OffsetRegNum != 0)
       return false;
@@ -1146,6 +1154,14 @@
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
+  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    // The lower two bits are always zero and as such are not encoded.
+    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Val));
+  }
+
   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139381&r1=139380&r2=139381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Sep  9 13:37:27 2011
@@ -269,6 +269,8 @@
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
+                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
@@ -2669,6 +2671,21 @@
   return S;
 }
 
+static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
+                                   uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Rn = fieldFromInstruction32(Val, 8, 4);
+  unsigned imm = fieldFromInstruction32(Val, 0, 8);
+
+  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::CreateImm(imm));
+
+  return S;
+}
+
 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
                          uint64_t Address, const void *Decoder) {
   int imm = Val & 0xFF;

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=139381&r1=139380&r2=139381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Fri Sep  9 13:37:27 2011
@@ -812,6 +812,18 @@
   O << "]";
 }
 
+void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
+                                                       unsigned OpNum,
+                                                       raw_ostream &O) {
+  const MCOperand &MO1 = MI->getOperand(OpNum);
+  const MCOperand &MO2 = MI->getOperand(OpNum+1);
+
+  O << "[" << getRegisterName(MO1.getReg());
+  if (MO2.getImm())
+    O << ", #" << MO2.getImm() * 4;
+  O << "]";
+}
+
 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
                                                       unsigned OpNum,
                                                       raw_ostream &O) {

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=139381&r1=139380&r2=139381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Fri Sep  9 13:37:27 2011
@@ -96,6 +96,8 @@
                                   raw_ostream &O);
   void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum,
                                     raw_ostream &O);
+  void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum,
+                                    raw_ostream &O);
   void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum,
                                         raw_ostream &O);
   void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum,

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=139381&r1=139380&r2=139381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Fri Sep  9 13:37:27 2011
@@ -144,6 +144,12 @@
   /// operand.
   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
                                    SmallVectorImpl<MCFixup> &Fixups) const;
+
+  /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
+  /// operand.
+  uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
+                                   SmallVectorImpl<MCFixup> &Fixups) const;
+
   /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
   /// operand.
   uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
@@ -795,6 +801,20 @@
   return Binary;
 }
 
+/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
+/// 'reg + imm8<<2' operand.
+uint32_t ARMMCCodeEmitter::
+getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
+                        SmallVectorImpl<MCFixup> &Fixups) const {
+  // {11-8} = reg
+  // {7-0}  = imm8
+  const MCOperand &MO = MI.getOperand(OpIdx);
+  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
+  unsigned Reg = getARMRegisterNumbering(MO.getReg());
+  unsigned Imm8 = MO1.getImm();
+  return (Reg << 8) | Imm8;
+}
+
 // FIXME: This routine assumes that a binary
 // expression will always result in a PCRel expression
 // In reality, its only true if one or more subexpressions

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139381&r1=139380&r2=139381&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 13:37:27 2011
@@ -646,6 +646,23 @@
 @ CHECK: ldrd	r3, r5, [r6]            @ encoding: [0xd6,0xe9,0x00,0x35]
 @ CHECK: ldrd	r8, r1, [r3]            @ encoding: [0xd3,0xe9,0x00,0x81]
 
+ at ------------------------------------------------------------------------------
+@ LDREX/LDREXB/LDREXH/LDREXD
+ at ------------------------------------------------------------------------------
+        ldrex r1, [r4]
+        ldrex r8, [r4, #0]
+        ldrex r2, [sp, #128]
+        ldrexb r5, [r7]
+        ldrexh r9, [r12]
+        ldrexd r9, r3, [r4]
+
+@ CHECK: ldrex	r1, [r4]                @ encoding: [0x54,0xe8,0x00,0x1f]
+@ CHECK: ldrex	r8, [r4]                @ encoding: [0x54,0xe8,0x00,0x8f]
+@ CHECK: ldrex	r2, [sp, #128]          @ encoding: [0x5d,0xe8,0x20,0x2f]
+@ CHECK: ldrexb	r5, [r7]                @ encoding: [0xd7,0xe8,0x4f,0x5f]
+@ CHECK: ldrexh	r9, [r12]               @ encoding: [0xdc,0xe8,0x5f,0x9f]
+@ CHECK: ldrexd	r9, r3, [r4]            @ encoding: [0xd4,0xe8,0x7f,0x93]
+
 
 @------------------------------------------------------------------------------
 @ FIXME: LDRD(literal)

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=139381&r1=139380&r2=139381&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Fri Sep  9 13:37:27 2011
@@ -673,6 +673,7 @@
   MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12");    // R, I
   MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg");   // R, R, I
   MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4");  // R, I
+  MISC("t2addrmode_imm0_1020s4", "kOperandTypeThumb2AddrModeImm8s4");  // R, I
   MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
                                                                   // R, I
   MISC("tb_addrmode", "kOperandTypeARMTBAddrMode");               // I



From dblaikie at gmail.com  Fri Sep  9 13:42:50 2011
From: dblaikie at gmail.com (David Blaikie)
Date: Fri, 9 Sep 2011 11:42:50 -0700
Subject: [llvm-commits] [patch] Adding architecture selection (64 bit & 32
 bit x86 for now) to llvm demo page
Message-ID: <CAENS6Eu6dX-nGZJiiNGuLVSca-M61A3gUmVN1-ey7ER1RtPJ1g@mail.gmail.com>

Just moving this over to the right commits list to hopefully get some
visibility.

On Tue, Aug 30, 2011 at 10:08 PM, David Blaikie <dblaikie at gmail.com> wrote:

>
> Why not build a bunch of cross-compilers, and use the right one depending
>>> on the
>>> target?
>>
>>
>> I honestly don't know what it takes to setup a cross compiler, and I
>> wouldn't be the one doing it - I expect this would fall on Tanya's plate.
>>
>>
>> Not worth the maintenance cost IMO.
>>
>
> With that in mind, then, here's a modified version of Bjarke's patch that
> only provides 4 targets (x86, x86-64, llvm bitcode, llvm C++ api). I also
> stripped out Bjarke's work to support multiple front ends (llvm-gcc and
> clang) - I thought about preserving it or switching it to dragonegg, but I'm
> not sure that's worthwhile or in the domain of the llvm demo page.
>
> & I stripped out some old file types/extensions that clang doesn't support
> (Java, Fortran) while I was here.
>
> - David
>
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From ahatanak at gmail.com  Fri Sep  9 14:00:51 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 09 Sep 2011 19:00:51 -0000
Subject: [llvm-commits] [llvm] r139383 - in /llvm/trunk:
 lib/Target/Mips/Mips.td lib/Target/Mips/MipsSubtarget.cpp
 test/CodeGen/Mips/2008-07-05-ByVal.ll
 test/CodeGen/Mips/2008-07-06-fadd64.ll
 test/CodeGen/Mips/2008-07-07-FPExtend.ll
 test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
 test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
 test/CodeGen/Mips/2008-08-03-fabs64.ll
 test/CodeGen/Mips/2008-08-07-FPRound.ll
 test/CodeGen/Mips/2008-08-08-bswap.ll
Message-ID: <20110909190051.E74D92A6C12C@llvm.org>

Author: ahatanak
Date: Fri Sep  9 14:00:51 2011
New Revision: 139383

URL: http://llvm.org/viewvc/llvm-project?rev=139383&view=rev
Log:
Drop support for Allegrex. Allegrex implements a variant of Mips2.

Modified:
    llvm/trunk/lib/Target/Mips/Mips.td
    llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
    llvm/trunk/test/CodeGen/Mips/2008-07-05-ByVal.ll
    llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll
    llvm/trunk/test/CodeGen/Mips/2008-07-07-FPExtend.ll
    llvm/trunk/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
    llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
    llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll
    llvm/trunk/test/CodeGen/Mips/2008-08-07-FPRound.ll
    llvm/trunk/test/CodeGen/Mips/2008-08-08-bswap.ll

Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=139383&r1=139382&r2=139383&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Fri Sep  9 14:00:51 2011
@@ -82,13 +82,6 @@
 def : Proc<"mips32r1", [FeatureMips32]>;
 def : Proc<"4ke", [FeatureMips32r2]>;
 
-// Allegrex is a 32bit subset of r4000, both for integer and fp registers,
-// but much more similar to Mips2 than Mips3. It also contains some of
-// Mips32/Mips32r2 instructions and a custom vector fpu processor.
-def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
-      FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
-      FeatureMinMax, FeatureSwap, FeatureBitCount]>;
-
 def MipsAsmWriter : AsmWriter {
   string AsmWriterClassName  = "InstPrinter";
   bit isMCAsmWriter = 1;

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=139383&r1=139382&r2=139383&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Fri Sep  9 14:00:51 2011
@@ -42,20 +42,4 @@
   // Is the target system Linux ?
   if (TT.find("linux") == std::string::npos)
     IsLinux = false;
-
-  // When only the target triple is specified and is
-  // a allegrex target, set the features. We also match
-  // big and little endian allegrex cores (dont really
-  // know if a big one exists)
-  if (TT.find("mipsallegrex") != std::string::npos ||
-      TT.find("psp") != std::string::npos) {
-    MipsABI = EABI;
-    IsSingleFloat = true;
-    MipsArchVersion = Mips2;
-    HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
-    HasSEInReg = true;
-    HasBitCount = true;
-    HasSwap = true;
-    HasCondMov = true;
-  }
 }

Modified: llvm/trunk/test/CodeGen/Mips/2008-07-05-ByVal.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-05-ByVal.ll?rev=139383&r1=139382&r2=139383&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-05-ByVal.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-05-ByVal.ll Fri Sep  9 14:00:51 2011
@@ -1,4 +1,6 @@
-; RUN: llc < %s -march=mips | grep {lw.*(\$4)} | count 2
+; DISABLED: llc < %s -march=mips | grep {lw.*(\$4)} | count 2
+; RUN: false
+; XFAIL: *
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"

Modified: llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll?rev=139383&r1=139382&r2=139383&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll Fri Sep  9 14:00:51 2011
@@ -1,4 +1,6 @@
-; RUN: llc < %s -march=mips | grep __adddf3
+; DISABLED: llc < %s -march=mips | grep __adddf3
+; RUN: false
+; XFAIL: *
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"

Modified: llvm/trunk/test/CodeGen/Mips/2008-07-07-FPExtend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-07-FPExtend.ll?rev=139383&r1=139382&r2=139383&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-07-FPExtend.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-07-FPExtend.ll Fri Sep  9 14:00:51 2011
@@ -1,4 +1,6 @@
-; RUN: llc < %s -march=mips | grep __extendsfdf2
+; DISABLED: llc < %s -march=mips | grep __extendsfdf2
+; RUN: false
+; XFAIL: *
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"

Modified: llvm/trunk/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll?rev=139383&r1=139382&r2=139383&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll Fri Sep  9 14:00:51 2011
@@ -1,8 +1,10 @@
-; RUN: llc < %s -march=mips -o %t
-; RUN: grep __floatsidf   %t | count 1
-; RUN: grep __floatunsidf %t | count 1
-; RUN: grep __fixdfsi %t | count 1
-; RUN: grep __fixunsdfsi %t  | count 1
+; DISABLED: llc < %s -march=mips -o %t
+; DISABLED: grep __floatsidf   %t | count 1
+; DISABLED: grep __floatunsidf %t | count 1
+; DISABLED: grep __fixdfsi %t | count 1
+; DISABLED: grep __fixunsdfsi %t  | count 1
+; RUN: false
+; XFAIL: *
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"

Modified: llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll?rev=139383&r1=139382&r2=139383&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll Fri Sep  9 14:00:51 2011
@@ -1,6 +1,8 @@
-; RUN: llc < %s -march=mips -o %t
-; RUN: grep seh %t | count 1
-; RUN: grep seb %t | count 1
+; DISABLED: llc < %s -march=mips -o %t
+; DISABLED: grep seh %t | count 1
+; DISABLED: grep seb %t | count 1
+; RUN: false
+; XFAIL: *
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"

Modified: llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll?rev=139383&r1=139382&r2=139383&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll Fri Sep  9 14:00:51 2011
@@ -1,6 +1,8 @@
-; RUN: llc < %s -march=mips -o %t
-; RUN: grep {lui.*32767} %t | count 1
-; RUN: grep {ori.*65535} %t | count 1
+; DISABLED: llc < %s -march=mips -o %t
+; DISABLED: grep {lui.*32767} %t | count 1
+; DISABLED: grep {ori.*65535} %t | count 1
+; RUN: false
+; XFAIL: *
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"

Modified: llvm/trunk/test/CodeGen/Mips/2008-08-07-FPRound.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-07-FPRound.ll?rev=139383&r1=139382&r2=139383&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-08-07-FPRound.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-08-07-FPRound.ll Fri Sep  9 14:00:51 2011
@@ -1,4 +1,6 @@
-; RUN: llc < %s -march=mips | grep __truncdfsf2 | count 1
+; DISABLED: llc < %s -march=mips | grep __truncdfsf2 | count 1
+; RUN: false
+; XFAIL: *
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"

Modified: llvm/trunk/test/CodeGen/Mips/2008-08-08-bswap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-08-bswap.ll?rev=139383&r1=139382&r2=139383&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-08-08-bswap.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-08-08-bswap.ll Fri Sep  9 14:00:51 2011
@@ -1,4 +1,7 @@
-; RUN: llc < %s | grep wsbw | count 1
+; DISABLED: llc < %s | grep wsbw | count 1
+; RUN: false
+; XFAIL: *
+
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "psp"



From echristo at apple.com  Fri Sep  9 14:04:38 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 09 Sep 2011 12:04:38 -0700
Subject: [llvm-commits] [llvm] r139383 - in /llvm/trunk:
 lib/Target/Mips/Mips.td lib/Target/Mips/MipsSubtarget.cpp
 test/CodeGen/Mips/2008-07-05-ByVal.ll
 test/CodeGen/Mips/2008-07-06-fadd64.ll
 test/CodeGen/Mips/2008-07-07-FPExtend.ll
 test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
 test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
 test/CodeGen/Mips/2008-08-03-fabs64.ll
 test/CodeGen/Mips/2008-08-07-FPRound.ll
 test/CodeGen/Mips/2008-08-08-bswap.ll
In-Reply-To: <20110909190051.E74D92A6C12C@llvm.org>
References: <20110909190051.E74D92A6C12C@llvm.org>
Message-ID: <AC9A7432-3C6D-4515-B962-95A0A5531BD5@apple.com>


On Sep 9, 2011, at 12:00 PM, Akira Hatanaka wrote:

> Drop support for Allegrex. Allegrex implements a variant of Mips2.

Curious. Any reason?

-eric
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From grosbach at apple.com  Fri Sep  9 14:09:54 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 19:09:54 -0000
Subject: [llvm-commits] [llvm] r139385 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909190955.2765A2A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 14:09:54 2011
New Revision: 139385

URL: http://llvm.org/viewvc/llvm-project?rev=139385&view=rev
Log:
Shuffle a bit.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139385&r1=139384&r2=139385&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 14:09:54 2011
@@ -646,6 +646,12 @@
 @ CHECK: ldrd	r3, r5, [r6]            @ encoding: [0xd6,0xe9,0x00,0x35]
 @ CHECK: ldrd	r8, r1, [r3]            @ encoding: [0xd3,0xe9,0x00,0x81]
 
+
+ at ------------------------------------------------------------------------------
+@ FIXME: LDRD(literal)
+ at ------------------------------------------------------------------------------
+
+
 @------------------------------------------------------------------------------
 @ LDREX/LDREXB/LDREXH/LDREXD
 @------------------------------------------------------------------------------
@@ -665,11 +671,6 @@
 
 
 @------------------------------------------------------------------------------
-@ FIXME: LDRD(literal)
- at ------------------------------------------------------------------------------
-
-
- at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From gkistanova at gmail.com  Fri Sep  9 14:13:58 2011
From: gkistanova at gmail.com (Galina Kistanova)
Date: Fri, 09 Sep 2011 19:13:58 -0000
Subject: [llvm-commits] [zorg] r139387 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20110909191358.11FE82A6C12D@llvm.org>

Author: gkistanova
Date: Fri Sep  9 14:13:57 2011
New Revision: 139387

URL: http://llvm.org/viewvc/llvm-project?rev=139387&view=rev
Log:
Turn on testing for two stage clang-native-mingw32 builder.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=139387&r1=139386&r2=139387&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Sep  9 14:13:57 2011
@@ -305,7 +305,7 @@
         'slavenames':["kistanova8"],
          'builddir':"clang-native-mingw32-win7",
          'factory' : ClangBuilder.getClangBuildFactory(triple='i686-pc-mingw32',
-                                                       useTwoStage=True, test=False,
+                                                       useTwoStage=True, test=True,
                                                        stage1_config='Release+Asserts',
                                                        stage2_config='Release+Asserts'),
          'category' : 'clang'},



From grosbach at apple.com  Fri Sep  9 14:13:53 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 19:13:53 -0000
Subject: [llvm-commits] [llvm] r139386 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909191353.F36DE2A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 14:13:53 2011
New Revision: 139386

URL: http://llvm.org/viewvc/llvm-project?rev=139386&view=rev
Log:
Thumb2 assembly parsing and encoding for LDRH.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139386&r1=139385&r2=139386&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 14:13:53 2011
@@ -671,6 +671,61 @@
 
 
 @------------------------------------------------------------------------------
+@ LDRH(immediate)
+ at ------------------------------------------------------------------------------
+        ldrh r5, [r5, #-4]
+        ldrh r5, [r6, #32]
+        ldrh r5, [r6, #33]
+        ldrh r5, [r6, #257]
+        ldrh.w lr, [r7, #257]
+
+@ CHECK: ldrh	r5, [r5, #-4]           @ encoding: [0x35,0xf8,0x04,0x5c]
+@ CHECK: ldrh	r5, [r6, #32]           @ encoding: [0x35,0x8c]
+@ CHECK: ldrh.w	r5, [r6, #33]           @ encoding: [0xb6,0xf8,0x21,0x50]
+@ CHECK: ldrh.w	r5, [r6, #257]          @ encoding: [0xb6,0xf8,0x01,0x51]
+@ CHECK: ldrh.w	lr, [r7, #257]          @ encoding: [0xb7,0xf8,0x01,0xe1]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRH(register)
+ at ------------------------------------------------------------------------------
+        ldrh r1, [r8, r1]
+        ldrh.w r4, [r5, r2]
+        ldrh r6, [r0, r2, lsl #3]
+        ldrh r8, [r8, r2, lsl #2]
+        ldrh r7, [sp, r2, lsl #1]
+        ldrh r7, [sp, r2, lsl #0]
+        ldrh r5, [r8, #255]!
+        ldrh r2, [r5, #4]!
+        ldrh r1, [r4, #-4]!
+        ldrh lr, [r3], #255
+        ldrh r9, [r2], #4
+        ldrh r3, [sp], #-4
+
+@ CHECK: ldrh.w	r1, [r8, r1]            @ encoding: [0x38,0xf8,0x01,0x10]
+@ CHECK: ldrh.w	r4, [r5, r2]            @ encoding: [0x35,0xf8,0x02,0x40]
+@ CHECK: ldrh.w	r6, [r0, r2, lsl #3]    @ encoding: [0x30,0xf8,0x32,0x60]
+@ CHECK: ldrh.w	r8, [r8, r2, lsl #2]    @ encoding: [0x38,0xf8,0x22,0x80]
+@ CHECK: ldrh.w	r7, [sp, r2, lsl #1]    @ encoding: [0x3d,0xf8,0x12,0x70]
+@ CHECK: ldrh.w	r7, [sp, r2]            @ encoding: [0x3d,0xf8,0x02,0x70]
+@ CHECK: ldrh	r5, [r8, #255]!         @ encoding: [0x38,0xf8,0xff,0x5f]
+@ CHECK: ldrh	r2, [r5, #4]!           @ encoding: [0x35,0xf8,0x04,0x2f]
+@ CHECK: ldrh	r1, [r4, #-4]!          @ encoding: [0x34,0xf8,0x04,0x1d]
+@ CHECK: ldrh	lr, [r3], #255          @ encoding: [0x33,0xf8,0xff,0xeb]
+@ CHECK: ldrh	r9, [r2], #4            @ encoding: [0x32,0xf8,0x04,0x9b]
+@ CHECK: ldrh	r3, [sp], #-4           @ encoding: [0x3d,0xf8,0x04,0x39]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRH(literal)
+ at ------------------------------------------------------------------------------
+        ldrh r5, _bar
+
+@ CHECK: ldrh.w	r5, _bar                @ encoding: [0xbf'A',0xf8'A',A,0x50'A']
+@ CHECK:     @   fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From ahatanak at gmail.com  Fri Sep  9 14:21:01 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 9 Sep 2011 12:21:01 -0700
Subject: [llvm-commits] [llvm] r139383 - in /llvm/trunk:
 lib/Target/Mips/Mips.td lib/Target/Mips/MipsSubtarget.cpp
 test/CodeGen/Mips/2008-07-05-ByVal.ll
 test/CodeGen/Mips/2008-07-06-fadd64.ll
 test/CodeGen/Mips/2008-07-07-FPExtend.ll test/CodeGen/Mips/2008
Message-ID: <CAB297QwXZQQLcvZmwnsUbW0Le5OY849F=fdauHGKamoyie10iw@mail.gmail.com>

The reason is that I am making changes needed for removing support for
Mips1 and Mips2, which will make the Mips backend simpler and cleaner
(e.g. you can drop support for floating point 16x32bit register
files), and Allegrex implements a variant of Mips2.

On Fri, Sep 9, 2011 at 12:04 PM, Eric Christopher <echristo at apple.com> wrote:
>
> On Sep 9, 2011, at 12:00 PM, Akira Hatanaka wrote:
>
> Drop support for Allegrex. Allegrex implements a variant of Mips2.
>
> Curious. Any reason?
> -eric

From echristo at apple.com  Fri Sep  9 14:25:19 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 09 Sep 2011 12:25:19 -0700
Subject: [llvm-commits] [llvm] r139383 - in /llvm/trunk:
 lib/Target/Mips/Mips.td lib/Target/Mips/MipsSubtarget.cpp
 test/CodeGen/Mips/2008-07-05-ByVal.ll
 test/CodeGen/Mips/2008-07-06-fadd64.ll
 test/CodeGen/Mips/2008-07-07-FPExtend.ll test/CodeGen/Mips/2008
In-Reply-To: <CAB297QwXZQQLcvZmwnsUbW0Le5OY849F=fdauHGKamoyie10iw@mail.gmail.com>
References: <CAB297QwXZQQLcvZmwnsUbW0Le5OY849F=fdauHGKamoyie10iw@mail.gmail.com>
Message-ID: <F403BC48-E4A8-4663-983B-76E77C5E8861@apple.com>


On Sep 9, 2011, at 12:21 PM, Akira Hatanaka wrote:

> The reason is that I am making changes needed for removing support for
> Mips1 and Mips2, which will make the Mips backend simpler and cleaner
> (e.g. you can drop support for floating point 16x32bit register
> files), and Allegrex implements a variant of Mips2.

OK. Just to have the newer mips cores supported?

-eric

From ahatanak at gmail.com  Fri Sep  9 14:27:07 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 9 Sep 2011 12:27:07 -0700
Subject: [llvm-commits] [llvm] r139383 - in /llvm/trunk:
 lib/Target/Mips/Mips.td lib/Target/Mips/MipsSubtarget.cpp
 test/CodeGen/Mips/2008-07-05-ByVal.ll
 test/CodeGen/Mips/2008-07-06-fadd64.ll
 test/CodeGen/Mips/2008-07-07-FPExtend.ll test/CodeGen/Mips/2008
In-Reply-To: <F403BC48-E4A8-4663-983B-76E77C5E8861@apple.com>
References: <CAB297QwXZQQLcvZmwnsUbW0Le5OY849F=fdauHGKamoyie10iw@mail.gmail.com>
	<F403BC48-E4A8-4663-983B-76E77C5E8861@apple.com>
Message-ID: <CAB297Qx9nnu1+fry5p166C5M8NV+zZGCbrjUC-OCGZ0sQtioQw@mail.gmail.com>

Yes.

On Fri, Sep 9, 2011 at 12:25 PM, Eric Christopher <echristo at apple.com> wrote:
>
> On Sep 9, 2011, at 12:21 PM, Akira Hatanaka wrote:
>
>> The reason is that I am making changes needed for removing support for
>> Mips1 and Mips2, which will make the Mips backend simpler and cleaner
>> (e.g. you can drop support for floating point 16x32bit register
>> files), and Allegrex implements a variant of Mips2.
>
> OK. Just to have the newer mips cores supported?
>
> -eric
>

From echristo at apple.com  Fri Sep  9 14:32:53 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 09 Sep 2011 12:32:53 -0700
Subject: [llvm-commits] [llvm] r139383 - in /llvm/trunk:
 lib/Target/Mips/Mips.td lib/Target/Mips/MipsSubtarget.cpp
 test/CodeGen/Mips/2008-07-05-ByVal.ll
 test/CodeGen/Mips/2008-07-06-fadd64.ll
 test/CodeGen/Mips/2008-07-07-FPExtend.ll test/CodeGen/Mips/2008
In-Reply-To: <CAB297Qx9nnu1+fry5p166C5M8NV+zZGCbrjUC-OCGZ0sQtioQw@mail.gmail.com>
References: <CAB297QwXZQQLcvZmwnsUbW0Le5OY849F=fdauHGKamoyie10iw@mail.gmail.com>
	<F403BC48-E4A8-4663-983B-76E77C5E8861@apple.com>
	<CAB297Qx9nnu1+fry5p166C5M8NV+zZGCbrjUC-OCGZ0sQtioQw@mail.gmail.com>
Message-ID: <14F5585E-B8DE-418A-A981-F3C191A064A5@apple.com>

I'll assume you've talked this over with Bruno? :)

-eric

On Sep 9, 2011, at 12:27 PM, Akira Hatanaka wrote:

> Yes.
> 
> On Fri, Sep 9, 2011 at 12:25 PM, Eric Christopher <echristo at apple.com> wrote:
>> 
>> On Sep 9, 2011, at 12:21 PM, Akira Hatanaka wrote:
>> 
>>> The reason is that I am making changes needed for removing support for
>>> Mips1 and Mips2, which will make the Mips backend simpler and cleaner
>>> (e.g. you can drop support for floating point 16x32bit register
>>> files), and Allegrex implements a variant of Mips2.
>> 
>> OK. Just to have the newer mips cores supported?
>> 
>> -eric
>> 


From ahatanak at gmail.com  Fri Sep  9 14:37:44 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 9 Sep 2011 12:37:44 -0700
Subject: [llvm-commits] [llvm] r139383 - in /llvm/trunk:
 lib/Target/Mips/Mips.td lib/Target/Mips/MipsSubtarget.cpp
 test/CodeGen/Mips/2008-07-05-ByVal.ll
 test/CodeGen/Mips/2008-07-06-fadd64.ll
 test/CodeGen/Mips/2008-07-07-FPExtend.ll test/CodeGen/Mips/2008
In-Reply-To: <14F5585E-B8DE-418A-A981-F3C191A064A5@apple.com>
References: <CAB297QwXZQQLcvZmwnsUbW0Le5OY849F=fdauHGKamoyie10iw@mail.gmail.com>
	<F403BC48-E4A8-4663-983B-76E77C5E8861@apple.com>
	<CAB297Qx9nnu1+fry5p166C5M8NV+zZGCbrjUC-OCGZ0sQtioQw@mail.gmail.com>
	<14F5585E-B8DE-418A-A981-F3C191A064A5@apple.com>
Message-ID: <CAB297QyLVFxn_RebZ9WsKVUu8WQ6UiZ9X_OM__8EGwMcHX7Q=g@mail.gmail.com>

Yes. We have already discussed this, and actually Bruno suggested we
clean up the backend.

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110905/127672.html

On Fri, Sep 9, 2011 at 12:32 PM, Eric Christopher <echristo at apple.com> wrote:
> I'll assume you've talked this over with Bruno? :)
>
> -eric
>
> On Sep 9, 2011, at 12:27 PM, Akira Hatanaka wrote:
>
>> Yes.
>>
>> On Fri, Sep 9, 2011 at 12:25 PM, Eric Christopher <echristo at apple.com> wrote:
>>>
>>> On Sep 9, 2011, at 12:21 PM, Akira Hatanaka wrote:
>>>
>>>> The reason is that I am making changes needed for removing support for
>>>> Mips1 and Mips2, which will make the Mips backend simpler and cleaner
>>>> (e.g. you can drop support for floating point 16x32bit register
>>>> files), and Allegrex implements a variant of Mips2.
>>>
>>> OK. Just to have the newer mips cores supported?
>>>
>>> -eric
>>>
>
>

From echristo at apple.com  Fri Sep  9 14:38:08 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 09 Sep 2011 12:38:08 -0700
Subject: [llvm-commits] [llvm] r139383 - in /llvm/trunk:
 lib/Target/Mips/Mips.td lib/Target/Mips/MipsSubtarget.cpp
 test/CodeGen/Mips/2008-07-05-ByVal.ll
 test/CodeGen/Mips/2008-07-06-fadd64.ll
 test/CodeGen/Mips/2008-07-07-FPExtend.ll test/CodeGen/Mips/2008
In-Reply-To: <CAB297QyLVFxn_RebZ9WsKVUu8WQ6UiZ9X_OM__8EGwMcHX7Q=g@mail.gmail.com>
References: <CAB297QwXZQQLcvZmwnsUbW0Le5OY849F=fdauHGKamoyie10iw@mail.gmail.com>
	<F403BC48-E4A8-4663-983B-76E77C5E8861@apple.com>
	<CAB297Qx9nnu1+fry5p166C5M8NV+zZGCbrjUC-OCGZ0sQtioQw@mail.gmail.com>
	<14F5585E-B8DE-418A-A981-F3C191A064A5@apple.com>
	<CAB297QyLVFxn_RebZ9WsKVUu8WQ6UiZ9X_OM__8EGwMcHX7Q=g@mail.gmail.com>
Message-ID: <F18115CC-C7E3-4A44-ACE2-34F65476C55F@apple.com>


On Sep 9, 2011, at 12:37 PM, Akira Hatanaka wrote:

> Yes. We have already discussed this, and actually Bruno suggested we
> clean up the backend.
> 
> http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110905/127672.html

Aha. Excellent. Just ignore me then :)

-eric

From bruno.cardoso at gmail.com  Fri Sep  9 14:39:04 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Fri, 9 Sep 2011 12:39:04 -0700
Subject: [llvm-commits] [llvm] r139383 - in /llvm/trunk:
 lib/Target/Mips/Mips.td lib/Target/Mips/MipsSubtarget.cpp
 test/CodeGen/Mips/2008-07-05-ByVal.ll
 test/CodeGen/Mips/2008-07-06-fadd64.ll
 test/CodeGen/Mips/2008-07-07-FPExtend.ll test/CodeGen/Mips/2008
Message-ID: <CACk9FxY0BBGdav88u=tUwNY8upEHCeDf5-pfui-86iZ+jhoYAg@mail.gmail.com>

> Curious. Any reason?

I've implemented this in the past. We have no users and I'm not even
sure this works as expected anymore. So we are heading towards to keep
only useful stuff


-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc

From baldrick at free.fr  Fri Sep  9 14:40:06 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 09 Sep 2011 19:40:06 -0000
Subject: [llvm-commits] [dragonegg] r139388 -
	/dragonegg/trunk/include/x86/dragonegg/Target.h
Message-ID: <20110909194006.A63BE2A6C12C@llvm.org>

Author: baldrick
Date: Fri Sep  9 14:40:06 2011
New Revision: 139388

URL: http://llvm.org/viewvc/llvm-project?rev=139388&view=rev
Log:
Add support for some extra x86 target features that are selectable
(or deselectable) from the command line: aes, cmpxchg16b, fma4 and popcnt.

Modified:
    dragonegg/trunk/include/x86/dragonegg/Target.h

Modified: dragonegg/trunk/include/x86/dragonegg/Target.h
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/x86/dragonegg/Target.h?rev=139388&r1=139387&r2=139388&view=diff
==============================================================================
--- dragonegg/trunk/include/x86/dragonegg/Target.h (original)
+++ dragonegg/trunk/include/x86/dragonegg/Target.h Fri Sep  9 14:40:06 2011
@@ -273,11 +273,6 @@
     else if (target_flags_explicit & OPTION_MASK_ISA_64BIT)	\
       F.AddFeature("64bit", false);				\
 								\
-    if (TARGET_MMX)						\
-      F.AddFeature("mmx");					\
-    else if (target_flags_explicit & OPTION_MASK_ISA_MMX)	\
-      F.AddFeature("mmx", false);				\
-								\
     if (TARGET_3DNOW)						\
       F.AddFeature("3dnow");					\
     else if (target_flags_explicit & OPTION_MASK_ISA_3DNOW)	\
@@ -288,6 +283,41 @@
     else if (target_flags_explicit & OPTION_MASK_ISA_3DNOW_A)	\
       F.AddFeature("3dnowa", false);				\
 								\
+    if (TARGET_AES)						\
+      F.AddFeature("aes");					\
+    else if (target_flags_explicit & OPTION_MASK_ISA_AES)	\
+      F.AddFeature("aes", false);				\
+								\
+    if (TARGET_AVX)						\
+      F.AddFeature("avx");					\
+    else if (target_flags_explicit & OPTION_MASK_ISA_AVX)	\
+      F.AddFeature("avx", false);				\
+								\
+    if (TARGET_CMPXCHG16B)					\
+      F.AddFeature("cmpxchg16b");				\
+    else if (target_flags_explicit & OPTION_MASK_ISA_CX16)	\
+      F.AddFeature("cmpxchg16b", false);			\
+								\
+    if (TARGET_FMA)						\
+      F.AddFeature("fma3");					\
+    else if (target_flags_explicit & OPTION_MASK_ISA_FMA)	\
+      F.AddFeature("fma3", false);				\
+								\
+    if (TARGET_FMA4)						\
+      F.AddFeature("fma4");					\
+    else if (target_flags_explicit & OPTION_MASK_ISA_FMA4)	\
+      F.AddFeature("fma4", false);				\
+								\
+    if (TARGET_MMX)						\
+      F.AddFeature("mmx");					\
+    else if (target_flags_explicit & OPTION_MASK_ISA_MMX)	\
+      F.AddFeature("mmx", false);				\
+								\
+    if (TARGET_POPCNT)						\
+      F.AddFeature("popcnt");					\
+    else if (target_flags_explicit & OPTION_MASK_ISA_POPCNT)	\
+      F.AddFeature("popcnt", false);				\
+								\
     if (TARGET_SSE)						\
       F.AddFeature("sse");					\
     else if (target_flags_explicit & OPTION_MASK_ISA_SSE)	\
@@ -303,11 +333,6 @@
     else if (target_flags_explicit & OPTION_MASK_ISA_SSE3)	\
       F.AddFeature("sse3", false);				\
 								\
-    if (TARGET_SSSE3)						\
-      F.AddFeature("ssse3");					\
-    else if (target_flags_explicit & OPTION_MASK_ISA_SSSE3)	\
-      F.AddFeature("ssse3", false);				\
-								\
     if (TARGET_SSE4_1)						\
       F.AddFeature("sse41");					\
     else if (target_flags_explicit & OPTION_MASK_ISA_SSE4_1)	\
@@ -318,20 +343,15 @@
     else if (target_flags_explicit & OPTION_MASK_ISA_SSE4_2)	\
       F.AddFeature("sse42", false);				\
 								\
-    if (TARGET_AVX)						\
-      F.AddFeature("avx");					\
-    else if (target_flags_explicit & OPTION_MASK_ISA_AVX)	\
-      F.AddFeature("avx", false);				\
-								\
-    if (TARGET_FMA)						\
-      F.AddFeature("fma3");					\
-    else if (target_flags_explicit & OPTION_MASK_ISA_FMA)	\
-      F.AddFeature("fma3", false);				\
-								\
     if (TARGET_SSE4A)						\
       F.AddFeature("sse4a");					\
     else if (target_flags_explicit & OPTION_MASK_ISA_SSE4A)	\
       F.AddFeature("sse4a", false);				\
+								\
+    if (TARGET_SSSE3)						\
+      F.AddFeature("ssse3");					\
+    else if (target_flags_explicit & OPTION_MASK_ISA_SSSE3)	\
+      F.AddFeature("ssse3", false);				\
   }
 
 #define LLVM_SET_IMPLICIT_FLOAT(flag_no_implicit_float)       \



From grosbach at apple.com  Fri Sep  9 14:42:40 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 19:42:40 -0000
Subject: [llvm-commits] [llvm] r139389 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909194240.89C802A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 14:42:40 2011
New Revision: 139389

URL: http://llvm.org/viewvc/llvm-project?rev=139389&view=rev
Log:
Thumb2 assembly parsing and encoding for LDRSB.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139389&r1=139388&r2=139389&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Sep  9 14:42:40 2011
@@ -3730,16 +3730,26 @@
 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
 
-// Alias for LDR, LDRB, LDRH without the ".w" optional width specifier.
+// Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
+// width specifier.
 def : t2InstAlias<"ldr${p} $Rt, $addr",
                   (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
 def : t2InstAlias<"ldrb${p} $Rt, $addr",
                   (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
 def : t2InstAlias<"ldrh${p} $Rt, $addr",
                   (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
+def : t2InstAlias<"ldrsb${p} $Rt, $addr",
+                  (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
+def : t2InstAlias<"ldrsh${p} $Rt, $addr",
+                  (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
+
 def : t2InstAlias<"ldr${p} $Rt, $addr",
                   (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
 def : t2InstAlias<"ldrb${p} $Rt, $addr",
                   (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
 def : t2InstAlias<"ldrh${p} $Rt, $addr",
                   (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
+def : t2InstAlias<"ldrsb${p} $Rt, $addr",
+                  (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
+def : t2InstAlias<"ldrsh${p} $Rt, $addr",
+                  (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139389&r1=139388&r2=139389&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 14:42:40 2011
@@ -726,6 +726,61 @@
 
 
 @------------------------------------------------------------------------------
+@ LDRSB(immediate)
+ at ------------------------------------------------------------------------------
+        ldrsb r5, [r5, #-4]
+        ldrsb r5, [r6, #32]
+        ldrsb r5, [r6, #33]
+        ldrsb r5, [r6, #257]
+        ldrsb.w lr, [r7, #257]
+
+@ CHECK: ldrsb	r5, [r5, #-4]            @ encoding: [0x15,0xf9,0x04,0x5c]
+@ CHECK: ldrsb.w r5, [r6, #32]           @ encoding: [0x96,0xf9,0x20,0x50]
+@ CHECK: ldrsb.w r5, [r6, #33]           @ encoding: [0x96,0xf9,0x21,0x50]
+@ CHECK: ldrsb.w r5, [r6, #257]          @ encoding: [0x96,0xf9,0x01,0x51]
+@ CHECK: ldrsb.w lr, [r7, #257]          @ encoding: [0x97,0xf9,0x01,0xe1]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRSB(register)
+ at ------------------------------------------------------------------------------
+        ldrsb r1, [r8, r1]
+        ldrsb.w r4, [r5, r2]
+        ldrsb r6, [r0, r2, lsl #3]
+        ldrsb r8, [r8, r2, lsl #2]
+        ldrsb r7, [sp, r2, lsl #1]
+        ldrsb r7, [sp, r2, lsl #0]
+        ldrsb r5, [r8, #255]!
+        ldrsb r2, [r5, #4]!
+        ldrsb r1, [r4, #-4]!
+        ldrsb lr, [r3], #255
+        ldrsb r9, [r2], #4
+        ldrsb r3, [sp], #-4
+
+@ CHECK: ldrsb.w r1, [r8, r1]           @ encoding: [0x18,0xf9,0x01,0x10]
+@ CHECK: ldrsb.w r4, [r5, r2]           @ encoding: [0x15,0xf9,0x02,0x40]
+@ CHECK: ldrsb.w r6, [r0, r2, lsl #3]   @ encoding: [0x10,0xf9,0x32,0x60]
+@ CHECK: ldrsb.w r8, [r8, r2, lsl #2]   @ encoding: [0x18,0xf9,0x22,0x80]
+@ CHECK: ldrsb.w r7, [sp, r2, lsl #1]   @ encoding: [0x1d,0xf9,0x12,0x70]
+@ CHECK: ldrsb.w r7, [sp, r2]           @ encoding: [0x1d,0xf9,0x02,0x70]
+@ CHECK: ldrsb	r5, [r8, #255]!         @ encoding: [0x18,0xf9,0xff,0x5f]
+@ CHECK: ldrsb	r2, [r5, #4]!           @ encoding: [0x15,0xf9,0x04,0x2f]
+@ CHECK: ldrsb	r1, [r4, #-4]!          @ encoding: [0x14,0xf9,0x04,0x1d]
+@ CHECK: ldrsb	lr, [r3], #255          @ encoding: [0x13,0xf9,0xff,0xeb]
+@ CHECK: ldrsb	r9, [r2], #4            @ encoding: [0x12,0xf9,0x04,0x9b]
+@ CHECK: ldrsb	r3, [sp], #-4           @ encoding: [0x1d,0xf9,0x04,0x39]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRSB(literal)
+ at ------------------------------------------------------------------------------
+        ldrsb r5, _bar
+
+@ CHECK: ldrsb.w r5, _bar               @ encoding: [0x9f'A',0xf9'A',A,0x50'A']
+@ CHECK:      @   fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From kcc at google.com  Fri Sep  9 14:48:36 2011
From: kcc at google.com (Kostya Serebryany)
Date: Fri, 9 Sep 2011 12:48:36 -0700
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <1137D6EF-A4A8-4C7B-AAA7-831E5E36124F@apple.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
	<1137D6EF-A4A8-4C7B-AAA7-831E5E36124F@apple.com>
Message-ID: <CAN=P9pjg6r7r-csthwB0or1Y5h1GFXxdn4Tpj_jdtkn9SsDfcA@mail.gmail.com>

On Thu, Sep 8, 2011 at 5:38 PM, Eric Christopher <echristo at apple.com> wrote:

>
> On Sep 8, 2011, at 5:14 PM, Kostya Serebryany wrote:
>
>
>
> On Thu, Sep 8, 2011 at 4:43 PM, Eric Christopher <echristo at apple.com>wrote:
>
>>
>> On Sep 8, 2011, at 4:35 PM, Chandler Carruth wrote:
>>
>> > FYI,
>> >
>> > I've looked again at this patch recently, and talked to several others
>> about it...
>> >
>> > I think there are some big issues with the implementation, bit I think
>> they could probably be addressed. The one that I see the most is the x86
>> assembly just being dumped as a blob. I think that really needs to be
>> resolved before this can move forward.
>> >
>> > It seems like this should be do-able in some way with the llvm.trap
>> intrinsic. If anything, we might need another intrinsic or an extension of
>> llvm.trap that allows feeding the SIGILL signal handler the data arguments
>> it needs; I'd need to read up on exactly what is required for that to figure
>> out how best to represent that in IR, but it shouldn't be that hard.
>> >
>> > That said, maybe to improve the discussion of the patch and make
>> reviewing it easier, you could just switch to emitting the call to the
>> runtime library function in all cases? That should be a strictly simpler
>> patch, and then how to improve performance by avoiding the runtime call can
>> be a followup.
>> >
>>
>> This encompasses most of my concerns with the patch.
>>
>> > Maybe others could comment on other implementation issues? I'm sadly not
>> an expert at LLVM...
>>
>> In a glance I didn't see a lot, but the other bits were somewhat hiding
>> it. How about when we get a new patch we can take a bit more of a look at
>> it.
>>
>
> I dropped the assembly part and updated the patch at
> http://codereview.appspot.com/4867059/ (also in attachment).
> We can figure out how to make it more efficient later (something
> like llvm.trap intrinsic with a parameter).
>
> This patch is 570 LOC plus few lines of trivial changes and a test.
> It implements only basic functionality: detection of out-of-bounds and
> use-after-free in heap.
>
> The complete version of LLVM pass is ~1000 LOC (
> http://code.google.com/p/address-sanitizer/source/browse/trunk/llvm/AddressSanitizer.cpp
> ).
> It also handles out-of-bounds for stack and global objects and (recently
> added) stack use-after-return bugs.
>
>
> Some somewhat trivial issues:
>
> a) Please go ahead and hide the non-user visible flags.
>
done

>
> b) Not a big fan of this style of avoid 80-col wrap:
>
> +Instruction *AddressSanitizer::generateCrashCode(
> +    IRBuilder<> &IRB, Value *Addr, int TelltaleValue) {
>
done

>
> c) +  // which will be lowered to a cusom assembly.
>
> s/cusom/custom
>
> d)
>
> +  if (TypeSize != 8 && TypeSize != 16 &&
> +      TypeSize != 32 && TypeSize != 64 && TypeSize != 128) {
> +    // TODO(kcc): do something better.
> +    return;
> +  }
>
> What's the reason behind this?
>

Changed the comment.


>
> Perhaps not so trivial:
>
> a) Where are the asan_* functions? Where are they supposed to live?
>
> I'll probably have more, but it's a start and the discussion on the library
> functions probably should happen sooner rather than later.
>
> -eric
>
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From grosbach at apple.com  Fri Sep  9 14:49:07 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 19:49:07 -0000
Subject: [llvm-commits] [llvm] r139390 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909194907.12B112A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 14:49:06 2011
New Revision: 139390

URL: http://llvm.org/viewvc/llvm-project?rev=139390&view=rev
Log:
Thumb2 assembly parsing and encoding for LDRSBT.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139390&r1=139389&r2=139390&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 14:49:06 2011
@@ -781,6 +781,20 @@
 
 
 @------------------------------------------------------------------------------
+@ LDRSBT
+ at ------------------------------------------------------------------------------
+        ldrsbt r1, [r2]
+        ldrsbt r1, [r8, #0]
+        ldrsbt r1, [r8, #3]
+        ldrsbt r1, [r8, #255]
+
+@ CHECK: ldrsbt	r1, [r2]                @ encoding: [0x12,0xf9,0x00,0x1e]
+@ CHECK: ldrsbt	r1, [r8]                @ encoding: [0x18,0xf9,0x00,0x1e]
+@ CHECK: ldrsbt	r1, [r8, #3]            @ encoding: [0x18,0xf9,0x03,0x1e]
+@ CHECK: ldrsbt	r1, [r8, #255]          @ encoding: [0x18,0xf9,0xff,0x1e]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From grosbach at apple.com  Fri Sep  9 14:54:30 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 19:54:30 -0000
Subject: [llvm-commits] [llvm] r139391 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909195430.CFAFD2A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 14:54:30 2011
New Revision: 139391

URL: http://llvm.org/viewvc/llvm-project?rev=139391&view=rev
Log:
Thumb2 assembly parsing and encoding for LDRSH.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139391&r1=139390&r2=139391&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 14:54:30 2011
@@ -795,6 +795,61 @@
 
 
 @------------------------------------------------------------------------------
+@ LDRSH(immediate)
+ at ------------------------------------------------------------------------------
+        ldrsh r5, [r5, #-4]
+        ldrsh r5, [r6, #32]
+        ldrsh r5, [r6, #33]
+        ldrsh r5, [r6, #257]
+        ldrsh.w lr, [r7, #257]
+
+@ CHECK: ldrsh	r5, [r5, #-4]           @ encoding: [0x35,0xf9,0x04,0x5c]
+@ CHECK: ldrsh.w r5, [r6, #32]          @ encoding: [0xb6,0xf9,0x20,0x50]
+@ CHECK: ldrsh.w r5, [r6, #33]          @ encoding: [0xb6,0xf9,0x21,0x50]
+@ CHECK: ldrsh.w r5, [r6, #257]         @ encoding: [0xb6,0xf9,0x01,0x51]
+@ CHECK: ldrsh.w lr, [r7, #257]         @ encoding: [0xb7,0xf9,0x01,0xe1]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRSH(register)
+ at ------------------------------------------------------------------------------
+        ldrsh r1, [r8, r1]
+        ldrsh.w r4, [r5, r2]
+        ldrsh r6, [r0, r2, lsl #3]
+        ldrsh r8, [r8, r2, lsl #2]
+        ldrsh r7, [sp, r2, lsl #1]
+        ldrsh r7, [sp, r2, lsl #0]
+        ldrsh r5, [r8, #255]!
+        ldrsh r2, [r5, #4]!
+        ldrsh r1, [r4, #-4]!
+        ldrsh lr, [r3], #255
+        ldrsh r9, [r2], #4
+        ldrsh r3, [sp], #-4
+
+@ CHECK: ldrsh.w r1, [r8, r1]           @ encoding: [0x38,0xf9,0x01,0x10]
+@ CHECK: ldrsh.w r4, [r5, r2]           @ encoding: [0x35,0xf9,0x02,0x40]
+@ CHECK: ldrsh.w r6, [r0, r2, lsl #3]   @ encoding: [0x30,0xf9,0x32,0x60]
+@ CHECK: ldrsh.w r8, [r8, r2, lsl #2]   @ encoding: [0x38,0xf9,0x22,0x80]
+@ CHECK: ldrsh.w r7, [sp, r2, lsl #1]   @ encoding: [0x3d,0xf9,0x12,0x70]
+@ CHECK: ldrsh.w r7, [sp, r2]           @ encoding: [0x3d,0xf9,0x02,0x70]
+@ CHECK: ldrsh	r5, [r8, #255]!         @ encoding: [0x38,0xf9,0xff,0x5f]
+@ CHECK: ldrsh	r2, [r5, #4]!           @ encoding: [0x35,0xf9,0x04,0x2f]
+@ CHECK: ldrsh	r1, [r4, #-4]!          @ encoding: [0x34,0xf9,0x04,0x1d]
+@ CHECK: ldrsh	lr, [r3], #255          @ encoding: [0x33,0xf9,0xff,0xeb]
+@ CHECK: ldrsh	r9, [r2], #4            @ encoding: [0x32,0xf9,0x04,0x9b]
+@ CHECK: ldrsh	r3, [sp], #-4           @ encoding: [0x3d,0xf9,0x04,0x39]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRSH(literal)
+ at ------------------------------------------------------------------------------
+        ldrsh r5, _bar
+
+@ CHECK: ldrsh.w r5, _bar               @ encoding: [0xbf'A',0xf9'A',A,0x50'A']
+@ CHECK:      @   fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From grosbach at apple.com  Fri Sep  9 15:01:18 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 20:01:18 -0000
Subject: [llvm-commits] [llvm] r139392 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909200118.922642A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 15:01:18 2011
New Revision: 139392

URL: http://llvm.org/viewvc/llvm-project?rev=139392&view=rev
Log:
Thumb2 assembly parsing and encoding for LDRSHT.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139392&r1=139391&r2=139392&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 15:01:18 2011
@@ -850,6 +850,20 @@
 
 
 @------------------------------------------------------------------------------
+@ LDRSHT
+ at ------------------------------------------------------------------------------
+        ldrsht r1, [r2]
+        ldrsht r1, [r8, #0]
+        ldrsht r1, [r8, #3]
+        ldrsht r1, [r8, #255]
+
+@ CHECK: ldrsht	r1, [r2]                @ encoding: [0x32,0xf9,0x00,0x1e]
+@ CHECK: ldrsht	r1, [r8]                @ encoding: [0x38,0xf9,0x00,0x1e]
+@ CHECK: ldrsht	r1, [r8, #3]            @ encoding: [0x38,0xf9,0x03,0x1e]
+@ CHECK: ldrsht	r1, [r8, #255]          @ encoding: [0x38,0xf9,0xff,0x1e]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From grosbach at apple.com  Fri Sep  9 15:02:15 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 20:02:15 -0000
Subject: [llvm-commits] [llvm] r139393 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909200215.7D4322A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 15:02:15 2011
New Revision: 139393

URL: http://llvm.org/viewvc/llvm-project?rev=139393&view=rev
Log:
Thumb2 assembly parsing and encoding for LDRT.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139393&r1=139392&r2=139393&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 15:02:15 2011
@@ -864,6 +864,20 @@
 
 
 @------------------------------------------------------------------------------
+@ LDRT
+ at ------------------------------------------------------------------------------
+        ldrt r1, [r2]
+        ldrt r2, [r6, #0]
+        ldrt r3, [r7, #3]
+        ldrt r4, [r9, #255]
+
+@ CHECK: ldrt	r1, [r2]                @ encoding: [0x52,0xf8,0x00,0x1e]
+@ CHECK: ldrt	r2, [r6]                @ encoding: [0x56,0xf8,0x00,0x2e]
+@ CHECK: ldrt	r3, [r7, #3]            @ encoding: [0x57,0xf8,0x03,0x3e]
+@ CHECK: ldrt	r4, [r9, #255]          @ encoding: [0x59,0xf8,0xff,0x4e]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From grosbach at apple.com  Fri Sep  9 15:05:38 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 20:05:38 -0000
Subject: [llvm-commits] [llvm] r139395 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909200538.695982A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 15:05:38 2011
New Revision: 139395

URL: http://llvm.org/viewvc/llvm-project?rev=139395&view=rev
Log:
Thumb2 assembly parsing and encoding for LSL.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139395&r1=139394&r2=139395&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 15:05:38 2011
@@ -878,6 +878,44 @@
 
 
 @------------------------------------------------------------------------------
+@ LSL (immediate)
+ at ------------------------------------------------------------------------------
+        lsl r2, r3, #12
+        lsls r8, r3, #31
+        lsls.w r2, r3, #1
+        lsl r2, r3, #4
+        lsls r2, r12, #15
+
+        lsl r3, #19
+        lsls r8, #2
+        lsls.w r7, #5
+        lsl.w r12, #21
+
+@ CHECK: lsl.w	r2, r3, #12             @ encoding: [0x4f,0xea,0x03,0x32]
+@ CHECK: lsls.w	r8, r3, #31             @ encoding: [0x5f,0xea,0xc3,0x78]
+@ CHECK: lsls.w	r2, r3, #1              @ encoding: [0x5f,0xea,0x43,0x02]
+@ CHECK: lsl.w	r2, r3, #4              @ encoding: [0x4f,0xea,0x03,0x12]
+@ CHECK: lsls.w	r2, r12, #15            @ encoding: [0x5f,0xea,0xcc,0x32]
+
+@ CHECK: lsl.w	r3, r3, #19             @ encoding: [0x4f,0xea,0xc3,0x43]
+@ CHECK: lsls.w	r8, r8, #2              @ encoding: [0x5f,0xea,0x88,0x08]
+@ CHECK: lsls.w	r7, r7, #5              @ encoding: [0x5f,0xea,0x47,0x17]
+@ CHECK: lsl.w	r12, r12, #21           @ encoding: [0x4f,0xea,0x4c,0x5c]
+
+
+ at ------------------------------------------------------------------------------
+@ LSL (register)
+ at ------------------------------------------------------------------------------
+        lsl r3, r4, r2
+        lsl.w r1, r2
+        lsls r3, r4, r8
+
+@ CHECK: lsl.w	r3, r4, r2              @ encoding: [0x04,0xfa,0x02,0xf3]
+@ CHECK: lsl.w	r1, r1, r2              @ encoding: [0x01,0xfa,0x02,0xf1]
+@ CHECK: lsls.w	r3, r4, r8              @ encoding: [0x14,0xfa,0x08,0xf3]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From dmalyshev at accesssoftek.com  Fri Sep  9 15:10:57 2011
From: dmalyshev at accesssoftek.com (Danil Malyshev)
Date: Fri, 9 Sep 2011 13:10:57 -0700
Subject: [llvm-commits] ObjectFile additional SymbolRef parameters
Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE17F9B4DDF9@mail.accesssoftek.com>

Hello everyone,


Please find attached the patch for review.
This patch makes the following changes into SymbolRef:

- Add enum SymbolType and function getSymbolType()

- Add function isGlobal() - it's returns true for symbols that can be used in another objects, such as library functions.

- Rename function getAddress() to getOffset() and add new function getAddress(), because currently getAddress() returns section offset of symbol first byte. new getAddress() return symbol address.

- Change usage SumbolRef::getAddress() to getOffset() in tools/llvm-nm and tools/llvm-objdump.



Regards,
Danil

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From grosbach at apple.com  Fri Sep  9 15:17:49 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 20:17:49 -0000
Subject: [llvm-commits] [llvm] r139396 -
	/llvm/trunk/test/MC/ARM/basic-arm-instructions.s
Message-ID: <20110909201749.920452A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 15:17:49 2011
New Revision: 139396

URL: http://llvm.org/viewvc/llvm-project?rev=139396&view=rev
Log:
Tidy up formatting a bit.

Modified:
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=139396&r1=139395&r2=139396&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Fri Sep  9 15:17:49 2011
@@ -14,18 +14,18 @@
 @------------------------------------------------------------------------------
 @ ADC (immediate)
 @------------------------------------------------------------------------------
-  adc r1, r2, #0xf
-  adc r1, r2, #0xf0
-  adc r1, r2, #0xf00
-  adc r1, r2, #0xf000
-  adc r1, r2, #0xf0000
-  adc r1, r2, #0xf00000
-  adc r1, r2, #0xf000000
-  adc r1, r2, #0xf0000000
-  adc r1, r2, #0xf000000f
-  adcs r1, r2, #0xf00
-  adcseq r1, r2, #0xf00
-  adceq r1, r2, #0xf00
+        adc r1, r2, #0xf
+        adc r1, r2, #0xf0
+        adc r1, r2, #0xf00
+        adc r1, r2, #0xf000
+        adc r1, r2, #0xf0000
+        adc r1, r2, #0xf00000
+        adc r1, r2, #0xf000000
+        adc r1, r2, #0xf0000000
+        adc r1, r2, #0xf000000f
+        adcs r1, r2, #0xf00
+        adcseq r1, r2, #0xf00
+        adceq r1, r2, #0xf00
 
 @ CHECK: adc	r1, r2, #15             @ encoding: [0x0f,0x10,0xa2,0xe2]
 @ CHECK: adc	r1, r2, #240            @ encoding: [0xf0,0x10,0xa2,0xe2]
@@ -45,44 +45,44 @@
 @ ADC (register)
 @ ADC (shifted register)
 @------------------------------------------------------------------------------
-  adc r4, r5, r6
-  @ Constant shifts
-  adc r4, r5, r6, lsl #1
-  adc r4, r5, r6, lsl #31
-  adc r4, r5, r6, lsr #1
-  adc r4, r5, r6, lsr #31
-  adc r4, r5, r6, lsr #32
-  adc r4, r5, r6, asr #1
-  adc r4, r5, r6, asr #31
-  adc r4, r5, r6, asr #32
-  adc r4, r5, r6, ror #1
-  adc r4, r5, r6, ror #31
-
-  @ Register shifts
-  adc r6, r7, r8, lsl r9
-  adc r6, r7, r8, lsr r9
-  adc r6, r7, r8, asr r9
-  adc r6, r7, r8, ror r9
-  adc r4, r5, r6, rrx
-
-  @ Destination register is optional
-  adc r5, r6
-  adc r4, r5, lsl #1
-  adc r4, r5, lsl #31
-  adc r4, r5, lsr #1
-  adc r4, r5, lsr #31
-  adc r4, r5, lsr #32
-  adc r4, r5, asr #1
-  adc r4, r5, asr #31
-  adc r4, r5, asr #32
-  adc r4, r5, ror #1
-  adc r4, r5, ror #31
-  adc r4, r5, rrx
-  adc r6, r7, lsl r9
-  adc r6, r7, lsr r9
-  adc r6, r7, asr r9
-  adc r6, r7, ror r9
-  adc r4, r5, rrx
+        adc r4, r5, r6
+        @ Constant shifts
+        adc r4, r5, r6, lsl #1
+        adc r4, r5, r6, lsl #31
+        adc r4, r5, r6, lsr #1
+        adc r4, r5, r6, lsr #31
+        adc r4, r5, r6, lsr #32
+        adc r4, r5, r6, asr #1
+        adc r4, r5, r6, asr #31
+        adc r4, r5, r6, asr #32
+        adc r4, r5, r6, ror #1
+        adc r4, r5, r6, ror #31
+
+        @ Register shifts
+        adc r6, r7, r8, lsl r9
+        adc r6, r7, r8, lsr r9
+        adc r6, r7, r8, asr r9
+        adc r6, r7, r8, ror r9
+        adc r4, r5, r6, rrx
+
+        @ Destination register is optional
+        adc r5, r6
+        adc r4, r5, lsl #1
+        adc r4, r5, lsl #31
+        adc r4, r5, lsr #1
+        adc r4, r5, lsr #31
+        adc r4, r5, lsr #32
+        adc r4, r5, asr #1
+        adc r4, r5, asr #31
+        adc r4, r5, asr #32
+        adc r4, r5, ror #1
+        adc r4, r5, ror #31
+        adc r4, r5, rrx
+        adc r6, r7, lsl r9
+        adc r6, r7, lsr r9
+        adc r6, r7, asr r9
+        adc r6, r7, ror r9
+        adc r4, r5, rrx
 
 @ CHECK: adc	r4, r5, r6              @ encoding: [0x06,0x40,0xa5,0xe0]
 
@@ -126,11 +126,11 @@
 @ ADR
 @------------------------------------------------------------------------------
 Lback:
-  adr r2, Lback
-  adr r3, Lforward
+        adr r2, Lback
+        adr r3, Lforward
 Lforward:
-  adr	r2, #3
-  adr	r2, #-3
+        adr	r2, #3
+        adr	r2, #-3
 
 @ CHECK: Lback:
 @ CHECK: adr	r2, Lback    @ encoding: [0bAAAAAAA0,0x20'A',0x0f'A',0b1110001A]
@@ -145,32 +145,32 @@
 @------------------------------------------------------------------------------
 @ ADD
 @------------------------------------------------------------------------------
-  add r4, r5, #0xf000
-  add r4, r5, r6
-  add r4, r5, r6, lsl #5
-  add r4, r5, r6, lsr #5
-  add r4, r5, r6, lsr #5
-  add r4, r5, r6, asr #5
-  add r4, r5, r6, ror #5
-  add r6, r7, r8, lsl r9
-  add r6, r7, r8, lsr r9
-  add r6, r7, r8, asr r9
-  add r6, r7, r8, ror r9
-  add r4, r5, r6, rrx
-
-  @ destination register is optional
-  add r5, #0xf000
-  add r4, r5
-  add r4, r5, lsl #5
-  add r4, r5, lsr #5
-  add r4, r5, lsr #5
-  add r4, r5, asr #5
-  add r4, r5, ror #5
-  add r6, r7, lsl r9
-  add r6, r7, lsr r9
-  add r6, r7, asr r9
-  add r6, r7, ror r9
-  add r4, r5, rrx
+        add r4, r5, #0xf000
+        add r4, r5, r6
+        add r4, r5, r6, lsl #5
+        add r4, r5, r6, lsr #5
+        add r4, r5, r6, lsr #5
+        add r4, r5, r6, asr #5
+        add r4, r5, r6, ror #5
+        add r6, r7, r8, lsl r9
+        add r6, r7, r8, lsr r9
+        add r6, r7, r8, asr r9
+        add r6, r7, r8, ror r9
+        add r4, r5, r6, rrx
+
+        @ destination register is optional
+        add r5, #0xf000
+        add r4, r5
+        add r4, r5, lsl #5
+        add r4, r5, lsr #5
+        add r4, r5, lsr #5
+        add r4, r5, asr #5
+        add r4, r5, ror #5
+        add r6, r7, lsl r9
+        add r6, r7, lsr r9
+        add r6, r7, asr r9
+        add r6, r7, ror r9
+        add r4, r5, rrx
 
 @ CHECK: add	r4, r5, #61440          @ encoding: [0x0f,0x4a,0x85,0xe2]
 @ CHECK: add	r4, r5, r6              @ encoding: [0x06,0x40,0x85,0xe0]
@@ -203,32 +203,32 @@
 @------------------------------------------------------------------------------
 @ AND
 @------------------------------------------------------------------------------
-  and r10, r1, #0xf
-  and r10, r1, r6
-  and r10, r1, r6, lsl #10
-  and r10, r1, r6, lsr #10
-  and r10, r1, r6, lsr #10
-  and r10, r1, r6, asr #10
-  and r10, r1, r6, ror #10
-  and r6, r7, r8, lsl r2
-  and r6, r7, r8, lsr r2
-  and r6, r7, r8, asr r2
-  and r6, r7, r8, ror r2
-  and r10, r1, r6, rrx
-
-  @ destination register is optional
-  and r1, #0xf
-  and r10, r1
-  and r10, r1, lsl #10
-  and r10, r1, lsr #10
-  and r10, r1, lsr #10
-  and r10, r1, asr #10
-  and r10, r1, ror #10
-  and r6, r7, lsl r2
-  and r6, r7, lsr r2
-  and r6, r7, asr r2
-  and r6, r7, ror r2
-  and r10, r1, rrx
+    and r10, r1, #0xf
+    and r10, r1, r6
+    and r10, r1, r6, lsl #10
+    and r10, r1, r6, lsr #10
+    and r10, r1, r6, lsr #10
+    and r10, r1, r6, asr #10
+    and r10, r1, r6, ror #10
+    and r6, r7, r8, lsl r2
+    and r6, r7, r8, lsr r2
+    and r6, r7, r8, asr r2
+    and r6, r7, r8, ror r2
+    and r10, r1, r6, rrx
+
+    @ destination register is optional
+    and r1, #0xf
+    and r10, r1
+    and r10, r1, lsl #10
+    and r10, r1, lsr #10
+    and r10, r1, lsr #10
+    and r10, r1, asr #10
+    and r10, r1, ror #10
+    and r6, r7, lsl r2
+    and r6, r7, lsr r2
+    and r6, r7, asr r2
+    and r6, r7, ror r2
+    and r10, r1, rrx
 
 @ CHECK: and	r10, r1, #15            @ encoding: [0x0f,0xa0,0x01,0xe2]
 @ CHECK: and	r10, r1, r6             @ encoding: [0x06,0xa0,0x01,0xe0]
@@ -266,16 +266,16 @@
         beq _baz
 
 @ CHECK: b	_bar                    @ encoding: [A,A,A,0xea]
-                                        @   fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
+             @   fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
 @ CHECK: beq	_baz                    @ encoding: [A,A,A,0x0a]
-                                        @   fixup A - offset: 0, value: _baz, kind: fixup_arm_condbranch
+             @   fixup A - offset: 0, value: _baz, kind: fixup_arm_condbranch
 
 
 @------------------------------------------------------------------------------
 @ BFC
 @------------------------------------------------------------------------------
-  bfc r5, #3, #17
-  bfccc r5, #3, #17
+        bfc r5, #3, #17
+        bfccc r5, #3, #17
 
 @ CHECK: bfc	r5, #3, #17             @ encoding: [0x9f,0x51,0xd3,0xe7]
 @ CHECK: bfclo	r5, #3, #17             @ encoding: [0x9f,0x51,0xd3,0x37]
@@ -284,8 +284,8 @@
 @------------------------------------------------------------------------------
 @ BFI
 @------------------------------------------------------------------------------
-  bfi r5, r2, #3, #17
-  bfine r5, r2, #3, #17
+        bfi r5, r2, #3, #17
+        bfine r5, r2, #3, #17
 
 @ CHECK: bfi	r5, r2, #3, #17         @ encoding: [0x92,0x51,0xd3,0xe7]
 @ CHECK: bfine	r5, r2, #3, #17         @ encoding: [0x92,0x51,0xd3,0x17]
@@ -294,32 +294,32 @@
 @------------------------------------------------------------------------------
 @ BIC
 @------------------------------------------------------------------------------
-  bic r10, r1, #0xf
-  bic r10, r1, r6
-  bic r10, r1, r6, lsl #10
-  bic r10, r1, r6, lsr #10
-  bic r10, r1, r6, lsr #10
-  bic r10, r1, r6, asr #10
-  bic r10, r1, r6, ror #10
-  bic r6, r7, r8, lsl r2
-  bic r6, r7, r8, lsr r2
-  bic r6, r7, r8, asr r2
-  bic r6, r7, r8, ror r2
-  bic r10, r1, r6, rrx
-
-  @ destination register is optional
-  bic r1, #0xf
-  bic r10, r1
-  bic r10, r1, lsl #10
-  bic r10, r1, lsr #10
-  bic r10, r1, lsr #10
-  bic r10, r1, asr #10
-  bic r10, r1, ror #10
-  bic r6, r7, lsl r2
-  bic r6, r7, lsr r2
-  bic r6, r7, asr r2
-  bic r6, r7, ror r2
-  bic r10, r1, rrx
+        bic r10, r1, #0xf
+        bic r10, r1, r6
+        bic r10, r1, r6, lsl #10
+        bic r10, r1, r6, lsr #10
+        bic r10, r1, r6, lsr #10
+        bic r10, r1, r6, asr #10
+        bic r10, r1, r6, ror #10
+        bic r6, r7, r8, lsl r2
+        bic r6, r7, r8, lsr r2
+        bic r6, r7, r8, asr r2
+        bic r6, r7, r8, ror r2
+        bic r10, r1, r6, rrx
+
+        @ destination register is optional
+        bic r1, #0xf
+        bic r10, r1
+        bic r10, r1, lsl #10
+        bic r10, r1, lsr #10
+        bic r10, r1, lsr #10
+        bic r10, r1, asr #10
+        bic r10, r1, ror #10
+        bic r6, r7, lsl r2
+        bic r6, r7, lsr r2
+        bic r6, r7, asr r2
+        bic r6, r7, ror r2
+        bic r10, r1, rrx
 
 @ CHECK: bic	r10, r1, #15            @ encoding: [0x0f,0xa0,0xc1,0xe3]
 @ CHECK: bic	r10, r1, r6             @ encoding: [0x06,0xa0,0xc1,0xe1]
@@ -351,8 +351,8 @@
 @------------------------------------------------------------------------------
 @ BKPT
 @------------------------------------------------------------------------------
-  bkpt #10
-  bkpt #65535
+        bkpt #10
+        bkpt #65535
 
 @ CHECK: bkpt  #10                      @ encoding: [0x7a,0x00,0x20,0xe1]
 @ CHECK: bkpt  #65535                   @ encoding: [0x7f,0xff,0x2f,0xe1]
@@ -361,11 +361,11 @@
 @ BL/BLX (immediate)
 @------------------------------------------------------------------------------
 
-  bl _bar
-  blx _bar
-  blls #28634268
-  blx	#32424576
-  blx	#16212288
+        bl _bar
+        blx _bar
+        blls #28634268
+        blx	#32424576
+        blx	#16212288
 
 @ CHECK: bl  _bar @ encoding: [A,A,A,0xeb]
 @ CHECK:   @   fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
@@ -377,8 +377,8 @@
 @------------------------------------------------------------------------------
 @ BLX (register)
 @------------------------------------------------------------------------------
-  blx r2
-  blxne r2
+        blx r2
+        blxne r2
 
 @ CHECK: blx r2                         @ encoding: [0x32,0xff,0x2f,0xe1]
 @ CHECK: blxne r2                       @ encoding: [0x32,0xff,0x2f,0x11]
@@ -386,9 +386,8 @@
 @------------------------------------------------------------------------------
 @ BX
 @------------------------------------------------------------------------------
-
-  bx r2
-  bxne r2
+        bx r2
+        bxne r2
 
 @ CHECK: bx	r2                      @ encoding: [0x12,0xff,0x2f,0xe1]
 @ CHECK: bxne	r2                      @ encoding: [0x12,0xff,0x2f,0x11]
@@ -396,9 +395,8 @@
 @------------------------------------------------------------------------------
 @ BXJ
 @------------------------------------------------------------------------------
-
-  bxj r2
-  bxjne r2
+        bxj r2
+        bxjne r2
 
 @ CHECK: bxj	r2                      @ encoding: [0x22,0xff,0x2f,0xe1]
 @ CHECK: bxjne	r2                      @ encoding: [0x22,0xff,0x2f,0x11]
@@ -407,8 +405,8 @@
 @------------------------------------------------------------------------------
 @ CDP/CDP2
 @------------------------------------------------------------------------------
-  cdp  p7, #1, c1, c1, c1, #4
-  cdp2  p7, #1, c1, c1, c1, #4
+        cdp  p7, #1, c1, c1, c1, #4
+        cdp2  p7, #1, c1, c1, c1, #4
 
 @ CHECK: cdp  p7, #1, c1, c1, c1, #4     @ encoding: [0x81,0x17,0x11,0xee]
 @ CHECK: cdp2  p7, #1, c1, c1, c1, #4    @ encoding: [0x81,0x17,0x11,0xfe]
@@ -417,7 +415,7 @@
 @------------------------------------------------------------------------------
 @ CLREX
 @------------------------------------------------------------------------------
-  clrex
+        clrex
 
 @ CHECK: clrex                           @ encoding: [0x1f,0xf0,0x7f,0xf5]
 
@@ -425,8 +423,8 @@
 @------------------------------------------------------------------------------
 @ CLZ
 @------------------------------------------------------------------------------
-  clz r1, r2
-  clzeq r1, r2
+    clz r1, r2
+    clzeq r1, r2
 
 @ CHECK: clz r1, r2                      @ encoding: [0x12,0x1f,0x6f,0xe1]
 @ CHECK: clzeq r1, r2                    @ encoding: [0x12,0x1f,0x6f,0x01]
@@ -434,18 +432,18 @@
 @------------------------------------------------------------------------------
 @ CMN
 @------------------------------------------------------------------------------
-  cmn r1, #0xf
-  cmn r1, r6
-  cmn r1, r6, lsl #10
-  cmn r1, r6, lsr #10
-  cmn sp, r6, lsr #10
-  cmn r1, r6, asr #10
-  cmn r1, r6, ror #10
-  cmn r7, r8, lsl r2
-  cmn sp, r8, lsr r2
-  cmn r7, r8, asr r2
-  cmn r7, r8, ror r2
-  cmn r1, r6, rrx
+        cmn r1, #0xf
+        cmn r1, r6
+        cmn r1, r6, lsl #10
+        cmn r1, r6, lsr #10
+        cmn sp, r6, lsr #10
+        cmn r1, r6, asr #10
+        cmn r1, r6, ror #10
+        cmn r7, r8, lsl r2
+        cmn sp, r8, lsr r2
+        cmn r7, r8, asr r2
+        cmn r7, r8, ror r2
+        cmn r1, r6, rrx
 
 @ CHECK: cmn	r1, #15                 @ encoding: [0x0f,0x00,0x71,0xe3]
 @ CHECK: cmn	r1, r6                  @ encoding: [0x06,0x00,0x71,0xe1]
@@ -463,18 +461,18 @@
 @------------------------------------------------------------------------------
 @ CMP
 @------------------------------------------------------------------------------
-  cmp r1, #0xf
-  cmp r1, r6
-  cmp r1, r6, lsl #10
-  cmp r1, r6, lsr #10
-  cmp sp, r6, lsr #10
-  cmp r1, r6, asr #10
-  cmp r1, r6, ror #10
-  cmp r7, r8, lsl r2
-  cmp sp, r8, lsr r2
-  cmp r7, r8, asr r2
-  cmp r7, r8, ror r2
-  cmp r1, r6, rrx
+        cmp r1, #0xf
+        cmp r1, r6
+        cmp r1, r6, lsl #10
+        cmp r1, r6, lsr #10
+        cmp sp, r6, lsr #10
+        cmp r1, r6, asr #10
+        cmp r1, r6, ror #10
+        cmp r7, r8, lsl r2
+        cmp sp, r8, lsr r2
+        cmp r7, r8, asr r2
+        cmp r7, r8, ror r2
+        cmp r1, r6, rrx
 
 @ CHECK: cmp	r1, #15                 @ encoding: [0x0f,0x00,0x51,0xe3]
 @ CHECK: cmp	r1, r6                  @ encoding: [0x06,0x00,0x51,0xe1]
@@ -505,9 +503,9 @@
 @------------------------------------------------------------------------------
 @ DBG
 @------------------------------------------------------------------------------
-  dbg #0
-  dbg #5
-  dbg #15
+        dbg #0
+        dbg #5
+        dbg #15
 
 @ CHECK: dbg #0                         @ encoding: [0xf0,0xf0,0x20,0xe3]
 @ CHECK: dbg #5                         @ encoding: [0xf5,0xf0,0x20,0xe3]
@@ -517,19 +515,19 @@
 @------------------------------------------------------------------------------
 @ DMB
 @------------------------------------------------------------------------------
-  dmb sy
-  dmb st
-  dmb sh
-  dmb ish
-  dmb shst
-  dmb ishst
-  dmb un
-  dmb nsh
-  dmb unst
-  dmb nshst
-  dmb osh
-  dmb oshst
-  dmb
+        dmb sy
+        dmb st
+        dmb sh
+        dmb ish
+        dmb shst
+        dmb ishst
+        dmb un
+        dmb nsh
+        dmb unst
+        dmb nshst
+        dmb osh
+        dmb oshst
+        dmb
 
 @ CHECK: dmb	sy                      @ encoding: [0x5f,0xf0,0x7f,0xf5]
 @ CHECK: dmb	st                      @ encoding: [0x5e,0xf0,0x7f,0xf5]
@@ -548,19 +546,19 @@
 @------------------------------------------------------------------------------
 @ DSB
 @------------------------------------------------------------------------------
-  dsb sy
-  dsb st
-  dsb sh
-  dsb ish
-  dsb shst
-  dsb ishst
-  dsb un
-  dsb nsh
-  dsb unst
-  dsb nshst
-  dsb osh
-  dsb oshst
-  dsb
+        dsb sy
+        dsb st
+        dsb sh
+        dsb ish
+        dsb shst
+        dsb ishst
+        dsb un
+        dsb nsh
+        dsb unst
+        dsb nshst
+        dsb osh
+        dsb oshst
+        dsb
 
 @ CHECK: dsb	sy                      @ encoding: [0x4f,0xf0,0x7f,0xf5]
 @ CHECK: dsb	st                      @ encoding: [0x4e,0xf0,0x7f,0xf5]
@@ -579,32 +577,32 @@
 @------------------------------------------------------------------------------
 @ EOR
 @------------------------------------------------------------------------------
-  eor r4, r5, #0xf000
-  eor r4, r5, r6
-  eor r4, r5, r6, lsl #5
-  eor r4, r5, r6, lsr #5
-  eor r4, r5, r6, lsr #5
-  eor r4, r5, r6, asr #5
-  eor r4, r5, r6, ror #5
-  eor r6, r7, r8, lsl r9
-  eor r6, r7, r8, lsr r9
-  eor r6, r7, r8, asr r9
-  eor r6, r7, r8, ror r9
-  eor r4, r5, r6, rrx
-
-  @ destination register is optional
-  eor r5, #0xf000
-  eor r4, r5
-  eor r4, r5, lsl #5
-  eor r4, r5, lsr #5
-  eor r4, r5, lsr #5
-  eor r4, r5, asr #5
-  eor r4, r5, ror #5
-  eor r6, r7, lsl r9
-  eor r6, r7, lsr r9
-  eor r6, r7, asr r9
-  eor r6, r7, ror r9
-  eor r4, r5, rrx
+        eor r4, r5, #0xf000
+        eor r4, r5, r6
+        eor r4, r5, r6, lsl #5
+        eor r4, r5, r6, lsr #5
+        eor r4, r5, r6, lsr #5
+        eor r4, r5, r6, asr #5
+        eor r4, r5, r6, ror #5
+        eor r6, r7, r8, lsl r9
+        eor r6, r7, r8, lsr r9
+        eor r6, r7, r8, asr r9
+        eor r6, r7, r8, ror r9
+        eor r4, r5, r6, rrx
+
+        @ destination register is optional
+        eor r5, #0xf000
+        eor r4, r5
+        eor r4, r5, lsl #5
+        eor r4, r5, lsr #5
+        eor r4, r5, lsr #5
+        eor r4, r5, asr #5
+        eor r4, r5, ror #5
+        eor r6, r7, lsl r9
+        eor r6, r7, lsr r9
+        eor r6, r7, asr r9
+        eor r6, r7, ror r9
+        eor r4, r5, rrx
 
 @ CHECK: eor	r4, r5, #61440          @ encoding: [0x0f,0x4a,0x25,0xe2]
 @ CHECK: eor	r4, r5, r6              @ encoding: [0x06,0x40,0x25,0xe0]
@@ -693,8 +691,8 @@
         ldrhthi	r8, [r11], #-0
         ldrhthi	r8, [r11], #0
 
-@ CHECK: ldrhthi	r8, [r11], #-0          @ encoding: [0xb0,0x80,0x7b,0x80]
-@ CHECK: ldrhthi	r8, [r11], #0           @ encoding: [0xb0,0x80,0xfb,0x80]
+@ CHECK: ldrhthi r8, [r11], #-0         @ encoding: [0xb0,0x80,0x7b,0x80]
+@ CHECK: ldrhthi r8, [r11], #0          @ encoding: [0xb0,0x80,0xfb,0x80]
 
 @------------------------------------------------------------------------------
 @ FIXME: LSL
@@ -747,14 +745,14 @@
 @------------------------------------------------------------------------------
 @ MOV (immediate)
 @------------------------------------------------------------------------------
-    mov r3, #7
-    mov r4, #0xff0
-    mov r5, #0xff0000
-    mov r6, #0xffff
-    movw r9, #0xffff
-    movs r3, #7
-    moveq r4, #0xff0
-    movseq r5, #0xff0000
+        mov r3, #7
+        mov r4, #0xff0
+        mov r5, #0xff0000
+        mov r6, #0xffff
+        movw r9, #0xffff
+        movs r3, #7
+        moveq r4, #0xff0
+        movseq r5, #0xff0000
 
 @ CHECK: mov	r3, #7                  @ encoding: [0x07,0x30,0xa0,0xe3]
 @ CHECK: mov	r4, #4080               @ encoding: [0xff,0x4e,0xa0,0xe3]
@@ -781,9 +779,9 @@
 @------------------------------------------------------------------------------
 @ MOVT
 @------------------------------------------------------------------------------
-    movt r3, #7
-    movt r6, #0xffff
-    movteq r4, #0xff0
+        movt r3, #7
+        movt r6, #0xffff
+        movteq r4, #0xff0
 
 @ CHECK: movt	r3, #7                  @ encoding: [0x07,0x30,0x40,0xe3]
 @ CHECK: movt	r6, #65535              @ encoding: [0xff,0x6f,0x4f,0xe3]
@@ -888,11 +886,10 @@
 @------------------------------------------------------------------------------
 @ MUL
 @------------------------------------------------------------------------------
-
-  mul r5, r6, r7
-  muls r5, r6, r7
-  mulgt r5, r6, r7
-  mulsle r5, r6, r7
+        mul r5, r6, r7
+        muls r5, r6, r7
+        mulgt r5, r6, r7
+        mulsle r5, r6, r7
 
 @ CHECK: mul	r5, r6, r7              @ encoding: [0x96,0x07,0x05,0xe0]
 @ CHECK: muls	r5, r6, r7              @ encoding: [0x96,0x07,0x15,0xe0]
@@ -903,12 +900,12 @@
 @------------------------------------------------------------------------------
 @ MVN (immediate)
 @------------------------------------------------------------------------------
-    mvn r3, #7
-    mvn r4, #0xff0
-    mvn r5, #0xff0000
-    mvns r3, #7
-    mvneq r4, #0xff0
-    mvnseq r5, #0xff0000
+        mvn r3, #7
+        mvn r4, #0xff0
+        mvn r5, #0xff0000
+        mvns r3, #7
+        mvneq r4, #0xff0
+        mvnseq r5, #0xff0000
 
 @ CHECK: mvn	r3, #7                  @ encoding: [0x07,0x30,0xe0,0xe3]
 @ CHECK: mvn	r4, #4080               @ encoding: [0xff,0x4e,0xe0,0xe3]



From grosbach at apple.com  Fri Sep  9 15:19:28 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 20:19:28 -0000
Subject: [llvm-commits] [llvm] r139397 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909201928.EB2122A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 15:19:28 2011
New Revision: 139397

URL: http://llvm.org/viewvc/llvm-project?rev=139397&view=rev
Log:
Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139397&r1=139396&r2=139397&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 15:19:28 2011
@@ -916,6 +916,63 @@
 
 
 @------------------------------------------------------------------------------
+@ LSR (immediate)
+ at ------------------------------------------------------------------------------
+        lsr r2, r3, #12
+        lsrs r8, r3, #32
+        lsrs.w r2, r3, #1
+        lsr r2, r3, #4
+        lsrs r2, r12, #15
+
+        lsr r3, #19
+        lsrs r8, #2
+        lsrs.w r7, #5
+        lsr.w r12, #21
+
+@ CHECK: lsr.w	r2, r3, #12             @ encoding: [0x4f,0xea,0x13,0x32]
+@ CHECK: lsrs.w	r8, r3, #32             @ encoding: [0x5f,0xea,0x13,0x08]
+@ CHECK: lsrs.w	r2, r3, #1              @ encoding: [0x5f,0xea,0x53,0x02]
+@ CHECK: lsr.w	r2, r3, #4              @ encoding: [0x4f,0xea,0x13,0x12]
+@ CHECK: lsrs.w	r2, r12, #15            @ encoding: [0x5f,0xea,0xdc,0x32]
+
+@ CHECK: lsr.w	r3, r3, #19             @ encoding: [0x4f,0xea,0xd3,0x43]
+@ CHECK: lsrs.w	r8, r8, #2              @ encoding: [0x5f,0xea,0x98,0x08]
+@ CHECK: lsrs.w	r7, r7, #5              @ encoding: [0x5f,0xea,0x57,0x17]
+@ CHECK: lsr.w	r12, r12, #21           @ encoding: [0x4f,0xea,0x5c,0x5c]
+
+
+ at ------------------------------------------------------------------------------
+@ LSR (register)
+ at ------------------------------------------------------------------------------
+        lsr r3, r4, r2
+        lsr.w r1, r2
+        lsrs r3, r4, r8
+
+@ CHECK: lsr.w	r3, r4, r2              @ encoding: [0x24,0xfa,0x02,0xf3]
+@ CHECK: lsr.w	r1, r1, r2              @ encoding: [0x21,0xfa,0x02,0xf1]
+@ CHECK: lsrs.w	r3, r4, r8              @ encoding: [0x34,0xfa,0x08,0xf3]
+
+ at ------------------------------------------------------------------------------
+@ MCR/MCR2
+ at ------------------------------------------------------------------------------
+        mcr  p7, #1, r5, c1, c1, #4
+        mcr2  p7, #1, r5, c1, c1, #4
+
+@ CHECK: mcr	p7, #1, r5, c1, c1, #4  @ encoding: [0x21,0xee,0x91,0x57]
+@ CHECK: mcr2	p7, #1, r5, c1, c1, #4  @ encoding: [0x21,0xfe,0x91,0x57]
+
+
+ at ------------------------------------------------------------------------------
+@ MCRR/MCRR2
+ at ------------------------------------------------------------------------------
+        mcrr  p7, #15, r5, r4, c1
+        mcrr2  p7, #15, r5, r4, c1
+
+@ CHECK: mcrr	p7, #15, r5, r4, c1     @ encoding: [0x44,0xec,0xf1,0x57]
+@ CHECK: mcrr2	p7, #15, r5, r4, c1     @ encoding: [0x44,0xfc,0xf1,0x57]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From baldrick at free.fr  Fri Sep  9 15:22:48 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 09 Sep 2011 20:22:48 -0000
Subject: [llvm-commits] [llvm] r139398 -
	/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
Message-ID: <20110909202248.802C12A6C12C@llvm.org>

Author: baldrick
Date: Fri Sep  9 15:22:48 2011
New Revision: 139398

URL: http://llvm.org/viewvc/llvm-project?rev=139398&view=rev
Log:
Don't tack "Instruction not interpretable yet!" onto the end of
the instruction.

Modified:
    llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h

Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h?rev=139398&r1=139397&r2=139398&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h (original)
+++ llvm/trunk/lib/ExecutionEngine/Interpreter/Interpreter.h Fri Sep  9 15:22:48 2011
@@ -174,7 +174,7 @@
 
   void visitVAArgInst(VAArgInst &I);
   void visitInstruction(Instruction &I) {
-    errs() << I;
+    errs() << I << "\n";
     llvm_unreachable("Instruction not interpretable yet!");
   }
 



From grosbach at apple.com  Fri Sep  9 15:24:45 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 09 Sep 2011 20:24:45 -0000
Subject: [llvm-commits] [llvm] r139399 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909202445.EC08A2A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 15:24:45 2011
New Revision: 139399

URL: http://llvm.org/viewvc/llvm-project?rev=139399&view=rev
Log:
Thumb2 assembly parsing and encoding for MLA and MLS.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139399&r1=139398&r2=139399&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Sep  9 15:24:45 2011
@@ -3184,9 +3184,9 @@
       Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
       Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
-      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
+      Mnemonic == "sbc" || Mnemonic == "umull" ||
       Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
-      (Mnemonic == "mov" && !isThumb())) {
+      ((Mnemonic == "mov" || Mnemonic == "mla") && !isThumb())) {
     CanAcceptCarrySet = true;
   } else {
     CanAcceptCarrySet = false;

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139399&r1=139398&r2=139399&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 15:24:45 2011
@@ -973,6 +973,16 @@
 
 
 @------------------------------------------------------------------------------
+@ MLA/MLS
+ at ------------------------------------------------------------------------------
+        mla  r1,r2,r3,r4
+        mls  r1,r2,r3,r4
+
+@ CHECK: mla	r1, r2, r3, r4          @ encoding: [0x02,0xfb,0x03,0x41]
+@ CHECK: mls	r1, r2, r3, r4          @ encoding: [0x02,0xfb,0x13,0x41]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From nadav.rotem at intel.com  Fri Sep  9 15:29:17 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Fri, 09 Sep 2011 20:29:17 -0000
Subject: [llvm-commits] [llvm] r139400 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/X86/avx-blend.ll
Message-ID: <20110909202917.AC4092A6C12C@llvm.org>

Author: nadav
Date: Fri Sep  9 15:29:17 2011
New Revision: 139400

URL: http://llvm.org/viewvc/llvm-project?rev=139400&view=rev
Log:
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/avx-blend.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139400&r1=139399&r2=139400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep  9 15:29:17 2011
@@ -1019,6 +1019,11 @@
     setOperationAction(ISD::SELECT,            MVT::v4i64, Custom);
     setOperationAction(ISD::SELECT,            MVT::v8f32, Custom);
 
+    setOperationAction(ISD::VSELECT,            MVT::v4f64, Custom);
+    setOperationAction(ISD::VSELECT,            MVT::v4i64, Custom);
+    setOperationAction(ISD::VSELECT,            MVT::v8i32, Custom);
+    setOperationAction(ISD::VSELECT,            MVT::v8f32, Custom);
+
     setOperationAction(ISD::ADD,               MVT::v4i64, Custom);
     setOperationAction(ISD::ADD,               MVT::v8i32, Custom);
     setOperationAction(ISD::ADD,               MVT::v16i16, Custom);
@@ -8706,14 +8711,21 @@
   EVT VT = Op1.getValueType();
   switch (VT.getSimpleVT().SimpleTy) {
     default: break;
+    // SSE4:
     case MVT::v2i64:
     case MVT::v2f64:
-         return DAG.getNode(X86ISD::BLENDVPD, DL, VT, Ops, array_lengthof(Ops));
     case MVT::v4i32:
     case MVT::v4f32:
-         return DAG.getNode(X86ISD::BLENDVPS, DL, VT , Ops, array_lengthof(Ops));
     case MVT::v16i8:
-         return DAG.getNode(X86ISD::PBLENDVB, DL, VT , Ops, array_lengthof(Ops));
+    case MVT::v8i16:
+    // AVX:
+    case MVT::v4i64:
+    case MVT::v4f64:
+    case MVT::v8i32:
+    case MVT::v8f32:
+    case MVT::v32i8:
+    case MVT::v16i16:
+      return DAG.getNode(X86ISD::BLENDV, DL, VT, Ops, array_lengthof(Ops));
   }
 
   return SDValue();
@@ -9973,7 +9985,7 @@
     M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
                     DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
                     DAG.getConstant(4, MVT::i32));
-    R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
+    R = DAG.getNode(X86ISD::BLENDV, dl, VT, R, M, Op);
     // a += a
     Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
 
@@ -9988,12 +10000,12 @@
     M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
                     DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
                     DAG.getConstant(2, MVT::i32));
-    R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
+    R = DAG.getNode(X86ISD::BLENDV, dl, VT, R, M, Op);
     // a += a
     Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
 
     // return pblendv(r, r+r, a);
-    R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
+    R = DAG.getNode(X86ISD::BLENDV, dl, VT,
                     R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
     return R;
   }
@@ -10631,7 +10643,7 @@
   case X86ISD::PSIGNB:             return "X86ISD::PSIGNB";
   case X86ISD::PSIGNW:             return "X86ISD::PSIGNW";
   case X86ISD::PSIGND:             return "X86ISD::PSIGND";
-  case X86ISD::PBLENDVB:           return "X86ISD::PBLENDVB";
+  case X86ISD::BLENDV:             return "X86ISD::BLENDV";
   case X86ISD::FMAX:               return "X86ISD::FMAX";
   case X86ISD::FMIN:               return "X86ISD::FMIN";
   case X86ISD::FRSQRT:             return "X86ISD::FRSQRT";
@@ -13361,7 +13373,7 @@
         X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
         Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
         Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
-        Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
+        Mask = DAG.getNode(X86ISD::BLENDV, DL, MVT::v16i8, X, Y, Mask);
         return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
       }
     }

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=139400&r1=139399&r2=139400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Fri Sep  9 15:29:17 2011
@@ -175,10 +175,8 @@
       /// PSIGNB/W/D - Copy integer sign.
       PSIGNB, PSIGNW, PSIGND,
 
-      /// BLENDVXX family of opcodes
-      PBLENDVB,
-      BLENDVPD,
-      BLENDVPS,
+      /// BLEND family of opcodes
+      BLENDV,
 
       /// FMAX, FMIN - Floating point max and min.
       ///

Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=139400&r1=139399&r2=139400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Fri Sep  9 15:29:17 2011
@@ -58,14 +58,8 @@
 def X86psignd  : SDNode<"X86ISD::PSIGND",
                  SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>]>>;
-def X86pblendvb : SDNode<"X86ISD::PBLENDVB",
-                 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
-                                      SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
-def X86blendvpd : SDNode<"X86ISD::BLENDVPD",
-                  SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
-                                       SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
-def X86blendvps : SDNode<"X86ISD::BLENDVPS",
-                 SDTypeProfile<1, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
+def X86blendv : SDNode<"X86ISD::BLENDV",
+                 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
                                       SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139400&r1=139399&r2=139400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Sep  9 15:29:17 2011
@@ -5868,12 +5868,37 @@
                                          memopv32i8, int_x86_avx_blendv_ps_256>;
 
 let Predicates = [HasAVX] in {
-  def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, VR128:$mask),
-            (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
-  def : Pat<(X86blendvpd VR128:$src1, VR128:$src2, VR128:$mask),
-            (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
-  def : Pat<(X86blendvps VR128:$src1, VR128:$src2, VR128:$mask),
-            (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2),
+                  VR128:$mask)),
+    (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+def : Pat<(v4i32 (X86blendv (v4i32 VR128:$src1), (v4i32 VR128:$src2),
+                  VR128:$mask)),
+    (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+def : Pat<(v4f32 (X86blendv (v4f32 VR128:$src1), (v4f32 VR128:$src2),
+                  VR128:$mask)),
+    (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+def : Pat<(v2i64 (X86blendv (v2i64 VR128:$src1), (v2i64 VR128:$src2),
+                  VR128:$mask)),
+    (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+def : Pat<(v2f64 (X86blendv (v2f64 VR128:$src1), (v2f64 VR128:$src2),
+                  VR128:$mask)),
+    (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+
+
+def : Pat<(v8i32 (X86blendv (v8i32 VR256:$src1), (v8i32 VR256:$src2),
+                  VR256:$mask)),
+    (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+def : Pat<(v8f32 (X86blendv (v8f32 VR256:$src1), (v8f32 VR256:$src2),
+                  VR256:$mask)),
+    (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+
+
+def : Pat<(v4i64 (X86blendv (v4i64 VR256:$src1), (v4i64 VR256:$src2),
+                  VR256:$mask)),
+    (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+def : Pat<(v4f64 (X86blendv (v4f64 VR256:$src1), (v4f64 VR256:$src2),
+                  VR256:$mask)),
+    (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
 }
 
 /// SS41I_ternary_int - SSE 4.1 ternary operator
@@ -5901,12 +5926,16 @@
 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
 
 let Predicates = [HasSSE41] in {
-  def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0),
+  def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2), XMM0)),
             (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
-  def : Pat<(X86blendvpd VR128:$src1, VR128:$src2, XMM0),
-            (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
-  def : Pat<(X86blendvps VR128:$src1, VR128:$src2, XMM0),
+  def : Pat<(v4i32 (X86blendv (v4i32 VR128:$src1), (v4i32 VR128:$src2), XMM0)),
+            (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v4f32 (X86blendv (v4f32 VR128:$src1), (v4f32 VR128:$src2), XMM0)),
             (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v2i64 (X86blendv (v2i64 VR128:$src1), (v2i64 VR128:$src2), XMM0)),
+            (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v2f64 (X86blendv (v2f64 VR128:$src1), (v2f64 VR128:$src2), XMM0)),
+            (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
 }
 
 let Predicates = [HasAVX] in

Modified: llvm/trunk/test/CodeGen/X86/avx-blend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?rev=139400&r1=139399&r2=139400&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-blend.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-blend.ll Fri Sep  9 15:29:17 2011
@@ -1,5 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -promote-elements -mattr=+avx | FileCheck %s
 
+; AVX128 tests:
+
 ;CHECK: vsel_float
 ;CHECK: vblendvps
 ;CHECK: ret
@@ -45,3 +47,39 @@
 }
 
 
+; AVX256 tests:
+
+
+;CHECK: vsel_float
+;CHECK: vblendvps
+;CHECK: ret
+define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
+  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x float> %v1, <8 x float> %v2
+  ret <8 x float> %vsel
+}
+
+;CHECK: vsel_i32
+;CHECK: vblendvps
+;CHECK: ret
+define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
+  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i32> %v1, <8 x i32> %v2
+  ret <8 x i32> %vsel
+}
+
+;CHECK: vsel_double
+;CHECK: vblendvpd
+;CHECK: ret
+define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
+  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x double> %v1, <8 x double> %v2
+  ret <8 x double> %vsel
+}
+
+;CHECK: vsel_i64
+;CHECK: vblendvpd
+;CHECK: ret
+define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
+  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i64> %v1, <8 x i64> %v2
+  ret <8 x i64> %vsel
+}
+
+



From ahatanak at gmail.com  Fri Sep  9 15:45:50 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 09 Sep 2011 20:45:50 -0000
Subject: [llvm-commits] [llvm] r139405 - in /llvm/trunk: lib/Target/Mips/
	test/CodeGen/Mips/
Message-ID: <20110909204550.7ECBF2A6C12C@llvm.org>

Author: ahatanak
Date: Fri Sep  9 15:45:50 2011
New Revision: 139405

URL: http://llvm.org/viewvc/llvm-project?rev=139405&view=rev
Log:
Drop support for Mips1 and Mips2.

Removed:
    llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll
Modified:
    llvm/trunk/lib/Target/Mips/Mips.td
    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
    llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
    llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
    llvm/trunk/lib/Target/Mips/MipsSubtarget.h
    llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll
    llvm/trunk/test/CodeGen/Mips/atomic.ll
    llvm/trunk/test/CodeGen/Mips/fpcmp.ll
    llvm/trunk/test/CodeGen/Mips/frame-address.ll
    llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
    llvm/trunk/test/CodeGen/Mips/select.ll
    llvm/trunk/test/CodeGen/Mips/tls.ll

Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Fri Sep  9 15:45:50 2011
@@ -54,10 +54,6 @@
                                 "Enable 'byte/half swap' instructions.">;
 def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
                                 "Enable 'count leading bits' instructions.">;
-def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
-                                "Mips1 ISA Support">;
-def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
-                                "Mips2 ISA Support">;
 def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
                                 "Mips32 ISA Support",
                                 [FeatureCondMov, FeatureBitCount]>;
@@ -72,13 +68,6 @@
 class Proc<string Name, list<SubtargetFeature> Features>
  : Processor<Name, MipsGenericItineraries, Features>;
 
-def : Proc<"mips1", [FeatureMips1]>;
-def : Proc<"r2000", [FeatureMips1]>;
-def : Proc<"r3000", [FeatureMips1]>;
-
-def : Proc<"mips2", [FeatureMips2]>;
-def : Proc<"r6000", [FeatureMips2]>;
-
 def : Proc<"mips32r1", [FeatureMips32]>;
 def : Proc<"4ke", [FeatureMips32r2]>;
 

Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Fri Sep  9 15:45:50 2011
@@ -36,7 +36,6 @@
 #include "llvm/Target/TargetLoweringObjectFile.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/SmallString.h"
-#include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/TargetRegistry.h"
@@ -56,23 +55,6 @@
 
   MipsMCInstLower MCInstLowering(Mang, *MF, *this);
   unsigned Opc = MI->getOpcode();
-
-  // If target is Mips1, expand double precision load/store to two single
-  // precision loads/stores (and delay slot if MI is a load).
-  if (Subtarget->isMips1() && (Opc == Mips::LDC1 || Opc == Mips::SDC1)) {
-    SmallVector<MCInst, 4> MCInsts;
-    const unsigned* SubReg = 
-      TM.getRegisterInfo()->getSubRegisters(MI->getOperand(0).getReg());
-    MCInstLowering.LowerMips1F64LoadStore(MI, Opc, MCInsts,
-                                          Subtarget->isLittle(), SubReg);
-    
-    for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
-         I != MCInsts.end(); ++I)
-      OutStreamer.EmitInstruction(*I);
-
-    return;
-  }
-
   MCInst TmpInst0;
   MCInstLowering.Lower(MI, TmpInst0);
   

Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Fri Sep  9 15:45:50 2011
@@ -60,9 +60,7 @@
   bool Changed = false;
   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
     const MCInstrDesc& MCid = I->getDesc();
-    if (MCid.hasDelaySlot() &&
-        (TM.getSubtarget<MipsSubtarget>().isMips1() ||
-         MCid.isCall() || MCid.isBranch() || MCid.isReturn())) {
+    if (MCid.hasDelaySlot()) {
       MachineBasicBlock::iterator J = I;
       ++J;
       BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP));

Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Fri Sep  9 15:45:50 2011
@@ -58,7 +58,6 @@
 def In32BitMode      : Predicate<"!Subtarget.isFP64bit()">;
 def IsSingleFloat    : Predicate<"Subtarget.isSingleFloat()">;
 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
-def IsNotMipsI       : Predicate<"!Subtarget.isMips1()">;
 
 //===----------------------------------------------------------------------===//
 // Instruction Class Templates
@@ -254,7 +253,7 @@
 def MIPS_FCOND_NGT  : PatLeaf<(i32 15)>;
 
 /// Floating Point Compare
-let hasDelaySlot = 1, Defs=[FCR31] in {
+let Defs=[FCR31] in {
   def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
                      "c.$cc.s\t$fs, $ft",
                      [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Sep  9 15:45:50 2011
@@ -273,7 +273,7 @@
       [], IIAlu>;
 
 // Memory Load/Store
-let canFoldAsLoad = 1, hasDelaySlot = 1 in
+let canFoldAsLoad = 1 in
 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
   FI<op, (outs CPURegs:$dst), (ins mem:$addr),
      !strconcat(instr_asm, "\t$dst, $addr"),
@@ -571,7 +571,7 @@
 }
 
 /// Load-linked, Store-conditional
-let mayLoad = 1, hasDelaySlot = 1 in
+let mayLoad = 1 in
   def LL    : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr),
               "ll\t$dst, $addr", [], IILoad>;
 let mayStore = 1, Constraints = "$src = $dst" in

Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Fri Sep  9 15:45:50 2011
@@ -83,50 +83,6 @@
                                                            Ctx));
 }
 
-// If target is Mips1, expand double precision load/store to two single
-// precision loads/stores.
-// 
-//  ldc1 $f0, lo($CPI0_0)($5) gets expanded to the following two instructions:
-//  (little endian)
-//   lwc1 $f0, lo($CPI0_0)($5) and
-//   lwc1 $f1, lo($CPI0_0+4)($5)
-//  (big endian)
-//   lwc1 $f1, lo($CPI0_0)($5) and
-//   lwc1 $f0, lo($CPI0_0+4)($5)
-void MipsMCInstLower::LowerMips1F64LoadStore(const MachineInstr *MI,
-                                             unsigned Opc,
-                                             SmallVector<MCInst, 4>& MCInsts,
-                                             bool isLittle,
-                                             const unsigned *SubReg) const {
-  MCInst InstLo, InstHi, DelaySlot;
-  unsigned SingleOpc = (Opc == Mips::LDC1 ? Mips::LWC1 : Mips::SWC1);
-  unsigned RegLo = isLittle ? *SubReg : *(SubReg + 1);
-  unsigned RegHi = isLittle ? *(SubReg + 1) : *SubReg;
-  const MachineOperand &MO1 = MI->getOperand(1);
-  const MachineOperand &MO2 = MI->getOperand(2);
-
-  InstLo.setOpcode(SingleOpc);
-  InstLo.addOperand(MCOperand::CreateReg(RegLo));
-  InstLo.addOperand(LowerOperand(MO1));
-  InstLo.addOperand(LowerOperand(MO2));
-  MCInsts.push_back(InstLo);
-
-  InstHi.setOpcode(SingleOpc);
-  InstHi.addOperand(MCOperand::CreateReg(RegHi));
-  InstHi.addOperand(LowerOperand(MO1));
-  if (MO2.isImm())// The offset of addr operand is an immediate: e.g. 0($sp)
-    InstHi.addOperand(MCOperand::CreateImm(MO2.getImm() + 4));
-  else// Otherwise, the offset must be a symbol: e.g. lo($CPI0_0)($5)
-    InstHi.addOperand(LowerSymbolOperand(MO2, MO2.getType(), 4));
-  MCInsts.push_back(InstHi);
-
-  // Need to insert a NOP in LWC1's delay slot.
-  if (SingleOpc == Mips::LWC1) {
-    DelaySlot.setOpcode(Mips::NOP);
-    MCInsts.push_back(DelaySlot);
-  }
-}
-
 MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO) const {
   MachineOperandType MOTy = MO.getType();
   

Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.h?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Fri Sep  9 15:45:50 2011
@@ -9,7 +9,6 @@
 
 #ifndef MIPSMCINSTLOWER_H
 #define MIPSMCINSTLOWER_H
-#include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/Support/Compiler.h"
 
@@ -35,9 +34,6 @@
   MipsMCInstLower(Mangler *mang, const MachineFunction &MF,
                   MipsAsmPrinter &asmprinter);  
   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
-  void LowerMips1F64LoadStore(const MachineInstr *MI, unsigned Opc,
-                              SmallVector<MCInst, 4>& MCInsts,
-                              bool isLittle, const unsigned *SubReg) const;
 private:
   MCOperand LowerSymbolOperand(const MachineOperand &MO,
                                MachineOperandType MOTy, unsigned Offset) const;

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Fri Sep  9 15:45:50 2011
@@ -24,7 +24,7 @@
 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
                              const std::string &FS, bool little) :
   MipsGenSubtargetInfo(TT, CPU, FS),
-  MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
+  MipsArchVersion(Mips32), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
   IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
   HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
   HasSwap(false), HasBitCount(false)

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Fri Sep  9 15:45:50 2011
@@ -34,7 +34,7 @@
 protected:
 
   enum MipsArchEnum {
-    Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2
+    Mips32, Mips32r2
   };
 
   // Mips architecture version
@@ -102,7 +102,6 @@
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
-  bool isMips1() const { return MipsArchVersion == Mips1; }
   bool isMips32() const { return MipsArchVersion >= Mips32; }
   bool isMips32r2() const { return MipsArchVersion == Mips32r2; }
 

Modified: llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll Fri Sep  9 15:45:50 2011
@@ -1,7 +1,10 @@
-; RUN: llc < %s -march=mips -relocation-model=static -mcpu=mips1 | FileCheck %s
-; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic -mcpu=mips1 | FileCheck %s
+; DISABLED: llc < %s -march=mips -relocation-model=static | FileCheck %s
+; DISABLED: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s
+; RUN: false
++; XFAIL: *
 ; Fix PR7473
 
+
 define i32 @main() nounwind readnone {
 entry:
   %a = alloca i32, align 4                        ; <i32*> [#uses=2]

Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/atomic.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/atomic.ll Fri Sep  9 15:45:50 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
+; RUN: llc -march=mipsel < %s | FileCheck %s
 
 
 declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind

Modified: llvm/trunk/test/CodeGen/Mips/fpcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fpcmp.ll?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fpcmp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fpcmp.ll Fri Sep  9 15:45:50 2011
@@ -1,5 +1,4 @@
 ; RUN: llc  < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
-; RUN: llc  < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-MIPS1
 
 @g1 = external global i32
 
@@ -9,10 +8,6 @@
 ; CHECK-MIPS32R2: movt
 ; CHECK-MIPS32R2: c.olt.s
 ; CHECK-MIPS32R2: movt
-; CHECK-MIPS1: c.olt.s
-; CHECK-MIPS1: bc1t
-; CHECK-MIPS1: c.olt.s
-; CHECK-MIPS1: bc1t
   %cmp = fcmp olt float %f0, %f1
   %conv = zext i1 %cmp to i32
   %tmp2 = load i32* @g1, align 4

Modified: llvm/trunk/test/CodeGen/Mips/frame-address.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/frame-address.ll?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/frame-address.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/frame-address.ll Fri Sep  9 15:45:50 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
+; RUN: llc -march=mipsel < %s | FileCheck %s
 
 declare i8* @llvm.frameaddress(i32) nounwind readnone
 

Removed: llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll?rev=139404&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll (removed)
@@ -1,36 +0,0 @@
-; RUN: llc  < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-EL
-; RUN: llc  < %s -march=mips -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-EB
-
- at g1 = common global double 0.000000e+00, align 8
- at g2 = common global double 0.000000e+00, align 8
-
-define double @foo0(double %d0) nounwind {
-entry:
-; CHECK-EL: lw  $[[R0:[0-9]+]], %got($CPI0_0)
-; CHECK-EL: lwc1  $f[[R1:[0-9]+]], %lo($CPI0_0)($[[R0]])
-; CHECK-EL: lwc1  $f{{[0-9]+}}, %lo($CPI0_0+4)($[[R0]])
-; CHECK-EL: add.d $f[[R2:[0-9]+]], $f12, $f[[R1]]
-; CHECK-EL: lw  $[[R3:[0-9]+]], %got(g1)
-; CHECK-EL: swc1  $f[[R2]], 0($[[R3]])
-; CHECK-EL: swc1  $f{{[0-9]+}}, 4($[[R3]])
-; CHECK-EL: lw  $[[R4:[0-9]+]], %got(g2)
-; CHECK-EL: lwc1  $f0, 0($[[R4]])
-; CHECK-EL: lwc1  $f1, 4($[[R4]])
-
-; CHECK-EB: lw  $[[R0:[0-9]+]], %got($CPI0_0)
-; CHECK-EB: lwc1  $f{{[0-9]+}}, %lo($CPI0_0)($[[R0]])
-; CHECK-EB: lwc1  $f[[R1:[0-9]+]], %lo($CPI0_0+4)($[[R0]])
-; CHECK-EB: add.d $f[[R2:[0-9]+]], $f12, $f[[R1]]
-; CHECK-EB: lw  $[[R3:[0-9]+]], %got(g1)
-; CHECK-EB: swc1  $f{{[0-9]+}}, 0($[[R3]])
-; CHECK-EB: swc1  $f[[R2]], 4($[[R3]])
-; CHECK-EB: lw  $[[R4:[0-9]+]], %got(g2)
-; CHECK-EB: lwc1  $f1, 0($[[R4]])
-; CHECK-EB: lwc1  $f0, 4($[[R4]])
-
-  %add = fadd double %d0, 2.000000e+00
-  store double %add, double* @g1, align 8
-  %tmp1 = load double* @g2, align 8
-  ret double %tmp1
-}
-

Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll Fri Sep  9 15:45:50 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s
+; RUN: llc -march=mipsel -pre-RA-sched=source < %s | FileCheck %s
 
 
 ; All test functions do the same thing - they return the first variable

Modified: llvm/trunk/test/CodeGen/Mips/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/select.ll?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/select.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/select.ll Fri Sep  9 15:45:50 2011
@@ -1,5 +1,4 @@
 ; RUN: llc  < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
-; RUN: llc  < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-MIPS1
 
 @d2 = external global double
 @d3 = external global double
@@ -7,7 +6,6 @@
 define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone {
 entry:
 ; CHECK-MIPS32R2: movn
-; CHECK-MIPS1: beq
   %tobool = icmp ne i32 %s, 0
   %cond = select i1 %tobool, i32 %f1, i32 %f0
   ret i32 %cond
@@ -16,7 +14,6 @@
 define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone {
 entry:
 ; CHECK-MIPS32R2: movn.s
-; CHECK-MIPS1: beq
   %tobool = icmp ne i32 %s, 0
   %cond = select i1 %tobool, float %f0, float %f1
   ret float %cond
@@ -25,7 +22,6 @@
 define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone {
 entry:
 ; CHECK-MIPS32R2: movn.d
-; CHECK-MIPS1: bne
   %tobool = icmp ne i32 %s, 0
   %cond = select i1 %tobool, double %f0, double %f1
   ret double %cond
@@ -35,8 +31,6 @@
 entry:
 ; CHECK-MIPS32R2: c.eq.s
 ; CHECK-MIPS32R2: movt.s
-; CHECK-MIPS1: c.eq.s
-; CHECK-MIPS1: bc1f
   %cmp = fcmp oeq float %f2, %f3
   %cond = select i1 %cmp, float %f0, float %f1
   ret float %cond
@@ -46,8 +40,6 @@
 entry:
 ; CHECK-MIPS32R2: c.olt.s
 ; CHECK-MIPS32R2: movt.s
-; CHECK-MIPS1: c.olt.s
-; CHECK-MIPS1: bc1f
   %cmp = fcmp olt float %f2, %f3
   %cond = select i1 %cmp, float %f0, float %f1
   ret float %cond
@@ -57,8 +49,6 @@
 entry:
 ; CHECK-MIPS32R2: c.ule.s
 ; CHECK-MIPS32R2: movf.s
-; CHECK-MIPS1: c.ule.s
-; CHECK-MIPS1: bc1t
   %cmp = fcmp ogt float %f2, %f3
   %cond = select i1 %cmp, float %f0, float %f1
   ret float %cond
@@ -68,8 +58,6 @@
 entry:
 ; CHECK-MIPS32R2: c.ule.s
 ; CHECK-MIPS32R2: movf.d
-; CHECK-MIPS1: c.ule.s
-; CHECK-MIPS1: bc1t
   %cmp = fcmp ogt float %f2, %f3
   %cond = select i1 %cmp, double %f0, double %f1
   ret double %cond
@@ -79,8 +67,6 @@
 entry:
 ; CHECK-MIPS32R2: c.eq.d
 ; CHECK-MIPS32R2: movt.d
-; CHECK-MIPS1: c.eq.d
-; CHECK-MIPS1: bc1f
   %cmp = fcmp oeq double %f2, %f3
   %cond = select i1 %cmp, double %f0, double %f1
   ret double %cond
@@ -90,8 +76,6 @@
 entry:
 ; CHECK-MIPS32R2: c.olt.d
 ; CHECK-MIPS32R2: movt.d
-; CHECK-MIPS1: c.olt.d
-; CHECK-MIPS1: bc1f
   %cmp = fcmp olt double %f2, %f3
   %cond = select i1 %cmp, double %f0, double %f1
   ret double %cond
@@ -101,8 +85,6 @@
 entry:
 ; CHECK-MIPS32R2: c.ule.d
 ; CHECK-MIPS32R2: movf.d
-; CHECK-MIPS1: c.ule.d
-; CHECK-MIPS1: bc1t
   %cmp = fcmp ogt double %f2, %f3
   %cond = select i1 %cmp, double %f0, double %f1
   ret double %cond
@@ -112,8 +94,6 @@
 entry:
 ; CHECK-MIPS32R2: c.ule.d
 ; CHECK-MIPS32R2: movf.s
-; CHECK-MIPS1: c.ule.d
-; CHECK-MIPS1: bc1t
   %cmp = fcmp ogt double %f2, %f3
   %cond = select i1 %cmp, float %f0, float %f1
   ret float %cond
@@ -123,8 +103,6 @@
 entry:
 ; CHECK-MIPS32R2: c.eq.s
 ; CHECK-MIPS32R2: movt
-; CHECK-MIPS1: c.eq.s
-; CHECK-MIPS1: bc1f
   %cmp = fcmp oeq float %f2, %f3
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
@@ -134,8 +112,6 @@
 entry:
 ; CHECK-MIPS32R2: c.olt.s
 ; CHECK-MIPS32R2: movt
-; CHECK-MIPS1: c.olt.s
-; CHECK-MIPS1: bc1f
   %cmp = fcmp olt float %f2, %f3
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
@@ -145,8 +121,6 @@
 entry:
 ; CHECK-MIPS32R2: c.ule.s
 ; CHECK-MIPS32R2: movf
-; CHECK-MIPS1: c.ule.s
-; CHECK-MIPS1: bc1t
   %cmp = fcmp ogt float %f2, %f3
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
@@ -156,8 +130,6 @@
 entry:
 ; CHECK-MIPS32R2: c.eq.d
 ; CHECK-MIPS32R2: movt
-; CHECK-MIPS1: c.eq.d
-; CHECK-MIPS1: bc1f
   %tmp = load double* @d2, align 8, !tbaa !0
   %tmp1 = load double* @d3, align 8, !tbaa !0
   %cmp = fcmp oeq double %tmp, %tmp1
@@ -169,8 +141,6 @@
 entry:
 ; CHECK-MIPS32R2: c.olt.d
 ; CHECK-MIPS32R2: movt
-; CHECK-MIPS1: c.olt.d
-; CHECK-MIPS1: bc1f
   %tmp = load double* @d2, align 8, !tbaa !0
   %tmp1 = load double* @d3, align 8, !tbaa !0
   %cmp = fcmp olt double %tmp, %tmp1
@@ -182,8 +152,6 @@
 entry:
 ; CHECK-MIPS32R2: c.ule.d
 ; CHECK-MIPS32R2: movf
-; CHECK-MIPS1: c.ule.d
-; CHECK-MIPS1: bc1t
   %tmp = load double* @d2, align 8, !tbaa !0
   %tmp1 = load double* @d3, align 8, !tbaa !0
   %cmp = fcmp ogt double %tmp, %tmp1

Modified: llvm/trunk/test/CodeGen/Mips/tls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tls.ll?rev=139405&r1=139404&r2=139405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/tls.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/tls.ll Fri Sep  9 15:45:50 2011
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s -check-prefix=PIC
-; RUN: llc -march=mipsel -mcpu=mips2 -relocation-model=static < %s \
+; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=PIC
+; RUN: llc -march=mipsel -relocation-model=static < %s \
 ; RUN:                             | FileCheck %s -check-prefix=STATIC
 
 



From eli.friedman at gmail.com  Fri Sep  9 15:51:14 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Fri, 9 Sep 2011 13:51:14 -0700
Subject: [llvm-commits] [PATCH] Bug 10897 - Seg fault during NEON
 compilation with short3/4 division
In-Reply-To: <4e6a44a7.87edd80a.5a47.2bb1SMTPIN_ADDED@mx.google.com>
References: <4e6a26bc.11ef960a.1641.ffff988dSMTPIN_ADDED@mx.google.com>
	<CAJdarcF7=yuYvV6GtiA1rpLD3FZzypK=NcXNiuhi33cio2yi7g@mail.gmail.com>
	<4e6a44a7.87edd80a.5a47.2bb1SMTPIN_ADDED@mx.google.com>
Message-ID: <CAJdarcGq42gzpkLrGdXcZaZKCtubbSr12mWZSRrSMjNC2GkiXQ@mail.gmail.com>

On Fri, Sep 9, 2011 at 9:53 AM, James Molloy <james.molloy at arm.com> wrote:
> Hi Eli,
>
> Thanks for the quick response - I'd noticed you'd commented on the issue but as
> you hadn't assigned it, I thought it was dormant.
>
> I admit that my experience in the SelectionDAG code is lacking - could you
> please explain (briefly) what the correct fix is, for my information?

Your fix is in the right direction... but you're going to end up
triggering the exact opposite problem: before type legalization first
runs, the undef's will be wider than the inserted elements.

I have a fix I will be committing shortly; thanks for the testcase.

-Eli

> Cheers,
>
> James
>
>> -----Original Message-----
>> From: Eli Friedman [mailto:eli.friedman at gmail.com]
>> Sent: 09 September 2011 17:45
>> To: James Molloy
>> Cc: llvm-commits at cs.uiuc.edu
>> Subject: Re: [llvm-commits] [PATCH] Bug 10897 - Seg fault during NEON
>> compilation with short3/4 division
>>
>> On Fri, Sep 9, 2011 at 7:43 AM, James Molloy <james.molloy at arm.com> wrote:
>> > Hi,
>> >
>> > The attached patch fixes bug 10897.
>> >
>> > The issue was in the DAGCombiner, when constant-folding
>> "insert_vector_emt"
>> > nodes on a vector that had been size-extended (<3 x int> -> <4 x int> for
>> > example).
>> >
>> > The DAGCombiner was inserting UNDEFs for all values in the vector, and
>> the
>> > folded insert_vector_emt nodes replace those UNDEFs with actual content.
>> But the
>> > padding at the end, in the case where the original vector was not a power
>> of 2,
>> > isn't changed.
>> >
>> > This is fine, apart from the type that was being used for UNDEF was the
>> type of
>> > the vector element, which may not be legal. As DAGTypeLegalizer has
>> already run
>> > by this point, inserting illegal nodes causes assertion failures later
>> down the
>> > line.
>> >
>> > The fix is to ensure the type of the UNDEFs are legal types:
>> >
>> > + ? ?if (!isTypeLegal(EltVT))
>> > + ? ? ? ?EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
>> > + ? ?assert(isTypeLegal(EltVT) && "Vector element type was not legal!");
>>
>> This fix is not right; it will just end up exploding in the same way
>> on a different testcase.
>>
>> I've already taken a look at the bug; I wanted to briefly discuss it
>> with Dan first before committing a fix.
>>
>> > ----
>> >
>> > Aside: The documentation for TargetLowering::getTypeToTransformTo()
>> states that
>> > if the input parameter is legal, the function is equivalent to the
>> identity
>> > function. I should therefore not need the "isTypeLegal" check on the line
>> above.
>> >
>> > Changing this however broke a lot of codegen tests, both in the ARM and
>> X86
>> > backends. Does anyone know why that might be the case? For the X86 test I
>> looked
>> > at, getTypeToTransformTo appeared to be changing an i64 to a v2i64
>> (IIRC).
>>
>> That's strange... no idea.
>>
>> -Eli
>
>
>
>


From bruno.cardoso at gmail.com  Fri Sep  9 16:05:11 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Fri, 9 Sep 2011 14:05:11 -0700
Subject: [llvm-commits] [llvm] r139405 - in /llvm/trunk:
	lib/Target/Mips/ test/CodeGen/Mips/
In-Reply-To: <20110909204550.7ECBF2A6C12C@llvm.org>
References: <20110909204550.7ECBF2A6C12C@llvm.org>
Message-ID: <CACk9FxY3iDWdNtShjWOM-QFx+kzSkU+v5himU-V+3W5U9HquDg@mail.gmail.com>

yay! :D

On Fri, Sep 9, 2011 at 1:45 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Author: ahatanak
> Date: Fri Sep ?9 15:45:50 2011
> New Revision: 139405
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139405&view=rev
> Log:
> Drop support for Mips1 and Mips2.
>
> Removed:
> ? ?llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll
> Modified:
> ? ?llvm/trunk/lib/Target/Mips/Mips.td
> ? ?llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
> ? ?llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
> ? ?llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
> ? ?llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> ? ?llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
> ? ?llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
> ? ?llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
> ? ?llvm/trunk/lib/Target/Mips/MipsSubtarget.h
> ? ?llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll
> ? ?llvm/trunk/test/CodeGen/Mips/atomic.ll
> ? ?llvm/trunk/test/CodeGen/Mips/fpcmp.ll
> ? ?llvm/trunk/test/CodeGen/Mips/frame-address.ll
> ? ?llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
> ? ?llvm/trunk/test/CodeGen/Mips/select.ll
> ? ?llvm/trunk/test/CodeGen/Mips/tls.ll
>
> Modified: llvm/trunk/lib/Target/Mips/Mips.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/Mips.td (original)
> +++ llvm/trunk/lib/Target/Mips/Mips.td Fri Sep ?9 15:45:50 2011
> @@ -54,10 +54,6 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "Enable 'byte/half swap' instructions.">;
> ?def FeatureBitCount ? ?: SubtargetFeature<"bitcount", "HasBitCount", "true",
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "Enable 'count leading bits' instructions.">;
> -def FeatureMips1 ? ? ? : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"Mips1 ISA Support">;
> -def FeatureMips2 ? ? ? : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"Mips2 ISA Support">;
> ?def FeatureMips32 ? ? ?: SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "Mips32 ISA Support",
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? [FeatureCondMov, FeatureBitCount]>;
> @@ -72,13 +68,6 @@
> ?class Proc<string Name, list<SubtargetFeature> Features>
> ?: Processor<Name, MipsGenericItineraries, Features>;
>
> -def : Proc<"mips1", [FeatureMips1]>;
> -def : Proc<"r2000", [FeatureMips1]>;
> -def : Proc<"r3000", [FeatureMips1]>;
> -
> -def : Proc<"mips2", [FeatureMips2]>;
> -def : Proc<"r6000", [FeatureMips2]>;
> -
> ?def : Proc<"mips32r1", [FeatureMips32]>;
> ?def : Proc<"4ke", [FeatureMips32r2]>;
>
>
> Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Fri Sep ?9 15:45:50 2011
> @@ -36,7 +36,6 @@
> ?#include "llvm/Target/TargetLoweringObjectFile.h"
> ?#include "llvm/Target/TargetOptions.h"
> ?#include "llvm/ADT/SmallString.h"
> -#include "llvm/ADT/SmallVector.h"
> ?#include "llvm/ADT/StringExtras.h"
> ?#include "llvm/ADT/Twine.h"
> ?#include "llvm/Support/TargetRegistry.h"
> @@ -56,23 +55,6 @@
>
> ? MipsMCInstLower MCInstLowering(Mang, *MF, *this);
> ? unsigned Opc = MI->getOpcode();
> -
> - ?// If target is Mips1, expand double precision load/store to two single
> - ?// precision loads/stores (and delay slot if MI is a load).
> - ?if (Subtarget->isMips1() && (Opc == Mips::LDC1 || Opc == Mips::SDC1)) {
> - ? ?SmallVector<MCInst, 4> MCInsts;
> - ? ?const unsigned* SubReg =
> - ? ? ?TM.getRegisterInfo()->getSubRegisters(MI->getOperand(0).getReg());
> - ? ?MCInstLowering.LowerMips1F64LoadStore(MI, Opc, MCInsts,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Subtarget->isLittle(), SubReg);
> -
> - ? ?for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
> - ? ? ? ? I != MCInsts.end(); ++I)
> - ? ? ?OutStreamer.EmitInstruction(*I);
> -
> - ? ?return;
> - ?}
> -
> ? MCInst TmpInst0;
> ? MCInstLowering.Lower(MI, TmpInst0);
>
>
> Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Fri Sep ?9 15:45:50 2011
> @@ -60,9 +60,7 @@
> ? bool Changed = false;
> ? for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
> ? ? const MCInstrDesc& MCid = I->getDesc();
> - ? ?if (MCid.hasDelaySlot() &&
> - ? ? ? ?(TM.getSubtarget<MipsSubtarget>().isMips1() ||
> - ? ? ? ? MCid.isCall() || MCid.isBranch() || MCid.isReturn())) {
> + ? ?if (MCid.hasDelaySlot()) {
> ? ? ? MachineBasicBlock::iterator J = I;
> ? ? ? ++J;
> ? ? ? BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP));
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Fri Sep ?9 15:45:50 2011
> @@ -58,7 +58,6 @@
> ?def In32BitMode ? ? ?: Predicate<"!Subtarget.isFP64bit()">;
> ?def IsSingleFloat ? ?: Predicate<"Subtarget.isSingleFloat()">;
> ?def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
> -def IsNotMipsI ? ? ? : Predicate<"!Subtarget.isMips1()">;
>
> ?//===----------------------------------------------------------------------===//
> ?// Instruction Class Templates
> @@ -254,7 +253,7 @@
> ?def MIPS_FCOND_NGT ?: PatLeaf<(i32 15)>;
>
> ?/// Floating Point Compare
> -let hasDelaySlot = 1, Defs=[FCR31] in {
> +let Defs=[FCR31] in {
> ? def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
> ? ? ? ? ? ? ? ? ? ? ?"c.$cc.s\t$fs, $ft",
> ? ? ? ? ? ? ? ? ? ? ?[(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Sep ?9 15:45:50 2011
> @@ -273,7 +273,7 @@
> ? ? ? [], IIAlu>;
>
> ?// Memory Load/Store
> -let canFoldAsLoad = 1, hasDelaySlot = 1 in
> +let canFoldAsLoad = 1 in
> ?class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
> ? FI<op, (outs CPURegs:$dst), (ins mem:$addr),
> ? ? ?!strconcat(instr_asm, "\t$dst, $addr"),
> @@ -571,7 +571,7 @@
> ?}
>
> ?/// Load-linked, Store-conditional
> -let mayLoad = 1, hasDelaySlot = 1 in
> +let mayLoad = 1 in
> ? def LL ? ?: FI<0x30, (outs CPURegs:$dst), (ins mem:$addr),
> ? ? ? ? ? ? ? "ll\t$dst, $addr", [], IILoad>;
> ?let mayStore = 1, Constraints = "$src = $dst" in
>
> Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Fri Sep ?9 15:45:50 2011
> @@ -83,50 +83,6 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Ctx));
> ?}
>
> -// If target is Mips1, expand double precision load/store to two single
> -// precision loads/stores.
> -//
> -// ?ldc1 $f0, lo($CPI0_0)($5) gets expanded to the following two instructions:
> -// ?(little endian)
> -// ? lwc1 $f0, lo($CPI0_0)($5) and
> -// ? lwc1 $f1, lo($CPI0_0+4)($5)
> -// ?(big endian)
> -// ? lwc1 $f1, lo($CPI0_0)($5) and
> -// ? lwc1 $f0, lo($CPI0_0+4)($5)
> -void MipsMCInstLower::LowerMips1F64LoadStore(const MachineInstr *MI,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned Opc,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SmallVector<MCInst, 4>& MCInsts,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool isLittle,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const unsigned *SubReg) const {
> - ?MCInst InstLo, InstHi, DelaySlot;
> - ?unsigned SingleOpc = (Opc == Mips::LDC1 ? Mips::LWC1 : Mips::SWC1);
> - ?unsigned RegLo = isLittle ? *SubReg : *(SubReg + 1);
> - ?unsigned RegHi = isLittle ? *(SubReg + 1) : *SubReg;
> - ?const MachineOperand &MO1 = MI->getOperand(1);
> - ?const MachineOperand &MO2 = MI->getOperand(2);
> -
> - ?InstLo.setOpcode(SingleOpc);
> - ?InstLo.addOperand(MCOperand::CreateReg(RegLo));
> - ?InstLo.addOperand(LowerOperand(MO1));
> - ?InstLo.addOperand(LowerOperand(MO2));
> - ?MCInsts.push_back(InstLo);
> -
> - ?InstHi.setOpcode(SingleOpc);
> - ?InstHi.addOperand(MCOperand::CreateReg(RegHi));
> - ?InstHi.addOperand(LowerOperand(MO1));
> - ?if (MO2.isImm())// The offset of addr operand is an immediate: e.g. 0($sp)
> - ? ?InstHi.addOperand(MCOperand::CreateImm(MO2.getImm() + 4));
> - ?else// Otherwise, the offset must be a symbol: e.g. lo($CPI0_0)($5)
> - ? ?InstHi.addOperand(LowerSymbolOperand(MO2, MO2.getType(), 4));
> - ?MCInsts.push_back(InstHi);
> -
> - ?// Need to insert a NOP in LWC1's delay slot.
> - ?if (SingleOpc == Mips::LWC1) {
> - ? ?DelaySlot.setOpcode(Mips::NOP);
> - ? ?MCInsts.push_back(DelaySlot);
> - ?}
> -}
> -
> ?MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO) const {
> ? MachineOperandType MOTy = MO.getType();
>
>
> Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.h?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Fri Sep ?9 15:45:50 2011
> @@ -9,7 +9,6 @@
>
> ?#ifndef MIPSMCINSTLOWER_H
> ?#define MIPSMCINSTLOWER_H
> -#include "llvm/ADT/SmallVector.h"
> ?#include "llvm/CodeGen/MachineOperand.h"
> ?#include "llvm/Support/Compiler.h"
>
> @@ -35,9 +34,6 @@
> ? MipsMCInstLower(Mangler *mang, const MachineFunction &MF,
> ? ? ? ? ? ? ? ? ? MipsAsmPrinter &asmprinter);
> ? void Lower(const MachineInstr *MI, MCInst &OutMI) const;
> - ?void LowerMips1F64LoadStore(const MachineInstr *MI, unsigned Opc,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SmallVector<MCInst, 4>& MCInsts,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool isLittle, const unsigned *SubReg) const;
> ?private:
> ? MCOperand LowerSymbolOperand(const MachineOperand &MO,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineOperandType MOTy, unsigned Offset) const;
>
> Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Fri Sep ?9 15:45:50 2011
> @@ -24,7 +24,7 @@
> ?MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const std::string &FS, bool little) :
> ? MipsGenSubtargetInfo(TT, CPU, FS),
> - ?MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
> + ?MipsArchVersion(Mips32), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
> ? IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
> ? HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
> ? HasSwap(false), HasBitCount(false)
>
> Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Fri Sep ?9 15:45:50 2011
> @@ -34,7 +34,7 @@
> ?protected:
>
> ? enum MipsArchEnum {
> - ? ?Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2
> + ? ?Mips32, Mips32r2
> ? };
>
> ? // Mips architecture version
> @@ -102,7 +102,6 @@
> ? /// subtarget options. ?Definition of function is auto generated by tblgen.
> ? void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
>
> - ?bool isMips1() const { return MipsArchVersion == Mips1; }
> ? bool isMips32() const { return MipsArchVersion >= Mips32; }
> ? bool isMips32r2() const { return MipsArchVersion == Mips32r2; }
>
>
> Modified: llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll Fri Sep ?9 15:45:50 2011
> @@ -1,7 +1,10 @@
> -; RUN: llc < %s -march=mips -relocation-model=static -mcpu=mips1 | FileCheck %s
> -; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic -mcpu=mips1 | FileCheck %s
> +; DISABLED: llc < %s -march=mips -relocation-model=static | FileCheck %s
> +; DISABLED: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s
> +; RUN: false
> ++; XFAIL: *
> ?; Fix PR7473
>
> +
> ?define i32 @main() nounwind readnone {
> ?entry:
> ? %a = alloca i32, align 4 ? ? ? ? ? ? ? ? ? ? ? ?; <i32*> [#uses=2]
>
> Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/atomic.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/atomic.ll Fri Sep ?9 15:45:50 2011
> @@ -1,4 +1,4 @@
> -; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
> +; RUN: llc -march=mipsel < %s | FileCheck %s
>
>
> ?declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind
>
> Modified: llvm/trunk/test/CodeGen/Mips/fpcmp.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fpcmp.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/fpcmp.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/fpcmp.ll Fri Sep ?9 15:45:50 2011
> @@ -1,5 +1,4 @@
> ?; RUN: llc ?< %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
> -; RUN: llc ?< %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-MIPS1
>
> ?@g1 = external global i32
>
> @@ -9,10 +8,6 @@
> ?; CHECK-MIPS32R2: movt
> ?; CHECK-MIPS32R2: c.olt.s
> ?; CHECK-MIPS32R2: movt
> -; CHECK-MIPS1: c.olt.s
> -; CHECK-MIPS1: bc1t
> -; CHECK-MIPS1: c.olt.s
> -; CHECK-MIPS1: bc1t
> ? %cmp = fcmp olt float %f0, %f1
> ? %conv = zext i1 %cmp to i32
> ? %tmp2 = load i32* @g1, align 4
>
> Modified: llvm/trunk/test/CodeGen/Mips/frame-address.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/frame-address.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/frame-address.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/frame-address.ll Fri Sep ?9 15:45:50 2011
> @@ -1,4 +1,4 @@
> -; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
> +; RUN: llc -march=mipsel < %s | FileCheck %s
>
> ?declare i8* @llvm.frameaddress(i32) nounwind readnone
>
>
> Removed: llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll?rev=139404&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll (removed)
> @@ -1,36 +0,0 @@
> -; RUN: llc ?< %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-EL
> -; RUN: llc ?< %s -march=mips -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-EB
> -
> - at g1 = common global double 0.000000e+00, align 8
> - at g2 = common global double 0.000000e+00, align 8
> -
> -define double @foo0(double %d0) nounwind {
> -entry:
> -; CHECK-EL: lw ?$[[R0:[0-9]+]], %got($CPI0_0)
> -; CHECK-EL: lwc1 ?$f[[R1:[0-9]+]], %lo($CPI0_0)($[[R0]])
> -; CHECK-EL: lwc1 ?$f{{[0-9]+}}, %lo($CPI0_0+4)($[[R0]])
> -; CHECK-EL: add.d $f[[R2:[0-9]+]], $f12, $f[[R1]]
> -; CHECK-EL: lw ?$[[R3:[0-9]+]], %got(g1)
> -; CHECK-EL: swc1 ?$f[[R2]], 0($[[R3]])
> -; CHECK-EL: swc1 ?$f{{[0-9]+}}, 4($[[R3]])
> -; CHECK-EL: lw ?$[[R4:[0-9]+]], %got(g2)
> -; CHECK-EL: lwc1 ?$f0, 0($[[R4]])
> -; CHECK-EL: lwc1 ?$f1, 4($[[R4]])
> -
> -; CHECK-EB: lw ?$[[R0:[0-9]+]], %got($CPI0_0)
> -; CHECK-EB: lwc1 ?$f{{[0-9]+}}, %lo($CPI0_0)($[[R0]])
> -; CHECK-EB: lwc1 ?$f[[R1:[0-9]+]], %lo($CPI0_0+4)($[[R0]])
> -; CHECK-EB: add.d $f[[R2:[0-9]+]], $f12, $f[[R1]]
> -; CHECK-EB: lw ?$[[R3:[0-9]+]], %got(g1)
> -; CHECK-EB: swc1 ?$f{{[0-9]+}}, 0($[[R3]])
> -; CHECK-EB: swc1 ?$f[[R2]], 4($[[R3]])
> -; CHECK-EB: lw ?$[[R4:[0-9]+]], %got(g2)
> -; CHECK-EB: lwc1 ?$f1, 0($[[R4]])
> -; CHECK-EB: lwc1 ?$f0, 4($[[R4]])
> -
> - ?%add = fadd double %d0, 2.000000e+00
> - ?store double %add, double* @g1, align 8
> - ?%tmp1 = load double* @g2, align 8
> - ?ret double %tmp1
> -}
> -
>
> Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll Fri Sep ?9 15:45:50 2011
> @@ -1,4 +1,4 @@
> -; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s
> +; RUN: llc -march=mipsel -pre-RA-sched=source < %s | FileCheck %s
>
>
> ?; All test functions do the same thing - they return the first variable
>
> Modified: llvm/trunk/test/CodeGen/Mips/select.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/select.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/select.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/select.ll Fri Sep ?9 15:45:50 2011
> @@ -1,5 +1,4 @@
> ?; RUN: llc ?< %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
> -; RUN: llc ?< %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-MIPS1
>
> ?@d2 = external global double
> ?@d3 = external global double
> @@ -7,7 +6,6 @@
> ?define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone {
> ?entry:
> ?; CHECK-MIPS32R2: movn
> -; CHECK-MIPS1: beq
> ? %tobool = icmp ne i32 %s, 0
> ? %cond = select i1 %tobool, i32 %f1, i32 %f0
> ? ret i32 %cond
> @@ -16,7 +14,6 @@
> ?define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone {
> ?entry:
> ?; CHECK-MIPS32R2: movn.s
> -; CHECK-MIPS1: beq
> ? %tobool = icmp ne i32 %s, 0
> ? %cond = select i1 %tobool, float %f0, float %f1
> ? ret float %cond
> @@ -25,7 +22,6 @@
> ?define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone {
> ?entry:
> ?; CHECK-MIPS32R2: movn.d
> -; CHECK-MIPS1: bne
> ? %tobool = icmp ne i32 %s, 0
> ? %cond = select i1 %tobool, double %f0, double %f1
> ? ret double %cond
> @@ -35,8 +31,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.eq.s
> ?; CHECK-MIPS32R2: movt.s
> -; CHECK-MIPS1: c.eq.s
> -; CHECK-MIPS1: bc1f
> ? %cmp = fcmp oeq float %f2, %f3
> ? %cond = select i1 %cmp, float %f0, float %f1
> ? ret float %cond
> @@ -46,8 +40,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.olt.s
> ?; CHECK-MIPS32R2: movt.s
> -; CHECK-MIPS1: c.olt.s
> -; CHECK-MIPS1: bc1f
> ? %cmp = fcmp olt float %f2, %f3
> ? %cond = select i1 %cmp, float %f0, float %f1
> ? ret float %cond
> @@ -57,8 +49,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.ule.s
> ?; CHECK-MIPS32R2: movf.s
> -; CHECK-MIPS1: c.ule.s
> -; CHECK-MIPS1: bc1t
> ? %cmp = fcmp ogt float %f2, %f3
> ? %cond = select i1 %cmp, float %f0, float %f1
> ? ret float %cond
> @@ -68,8 +58,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.ule.s
> ?; CHECK-MIPS32R2: movf.d
> -; CHECK-MIPS1: c.ule.s
> -; CHECK-MIPS1: bc1t
> ? %cmp = fcmp ogt float %f2, %f3
> ? %cond = select i1 %cmp, double %f0, double %f1
> ? ret double %cond
> @@ -79,8 +67,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.eq.d
> ?; CHECK-MIPS32R2: movt.d
> -; CHECK-MIPS1: c.eq.d
> -; CHECK-MIPS1: bc1f
> ? %cmp = fcmp oeq double %f2, %f3
> ? %cond = select i1 %cmp, double %f0, double %f1
> ? ret double %cond
> @@ -90,8 +76,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.olt.d
> ?; CHECK-MIPS32R2: movt.d
> -; CHECK-MIPS1: c.olt.d
> -; CHECK-MIPS1: bc1f
> ? %cmp = fcmp olt double %f2, %f3
> ? %cond = select i1 %cmp, double %f0, double %f1
> ? ret double %cond
> @@ -101,8 +85,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.ule.d
> ?; CHECK-MIPS32R2: movf.d
> -; CHECK-MIPS1: c.ule.d
> -; CHECK-MIPS1: bc1t
> ? %cmp = fcmp ogt double %f2, %f3
> ? %cond = select i1 %cmp, double %f0, double %f1
> ? ret double %cond
> @@ -112,8 +94,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.ule.d
> ?; CHECK-MIPS32R2: movf.s
> -; CHECK-MIPS1: c.ule.d
> -; CHECK-MIPS1: bc1t
> ? %cmp = fcmp ogt double %f2, %f3
> ? %cond = select i1 %cmp, float %f0, float %f1
> ? ret float %cond
> @@ -123,8 +103,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.eq.s
> ?; CHECK-MIPS32R2: movt
> -; CHECK-MIPS1: c.eq.s
> -; CHECK-MIPS1: bc1f
> ? %cmp = fcmp oeq float %f2, %f3
> ? %cond = select i1 %cmp, i32 %f0, i32 %f1
> ? ret i32 %cond
> @@ -134,8 +112,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.olt.s
> ?; CHECK-MIPS32R2: movt
> -; CHECK-MIPS1: c.olt.s
> -; CHECK-MIPS1: bc1f
> ? %cmp = fcmp olt float %f2, %f3
> ? %cond = select i1 %cmp, i32 %f0, i32 %f1
> ? ret i32 %cond
> @@ -145,8 +121,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.ule.s
> ?; CHECK-MIPS32R2: movf
> -; CHECK-MIPS1: c.ule.s
> -; CHECK-MIPS1: bc1t
> ? %cmp = fcmp ogt float %f2, %f3
> ? %cond = select i1 %cmp, i32 %f0, i32 %f1
> ? ret i32 %cond
> @@ -156,8 +130,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.eq.d
> ?; CHECK-MIPS32R2: movt
> -; CHECK-MIPS1: c.eq.d
> -; CHECK-MIPS1: bc1f
> ? %tmp = load double* @d2, align 8, !tbaa !0
> ? %tmp1 = load double* @d3, align 8, !tbaa !0
> ? %cmp = fcmp oeq double %tmp, %tmp1
> @@ -169,8 +141,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.olt.d
> ?; CHECK-MIPS32R2: movt
> -; CHECK-MIPS1: c.olt.d
> -; CHECK-MIPS1: bc1f
> ? %tmp = load double* @d2, align 8, !tbaa !0
> ? %tmp1 = load double* @d3, align 8, !tbaa !0
> ? %cmp = fcmp olt double %tmp, %tmp1
> @@ -182,8 +152,6 @@
> ?entry:
> ?; CHECK-MIPS32R2: c.ule.d
> ?; CHECK-MIPS32R2: movf
> -; CHECK-MIPS1: c.ule.d
> -; CHECK-MIPS1: bc1t
> ? %tmp = load double* @d2, align 8, !tbaa !0
> ? %tmp1 = load double* @d3, align 8, !tbaa !0
> ? %cmp = fcmp ogt double %tmp, %tmp1
>
> Modified: llvm/trunk/test/CodeGen/Mips/tls.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tls.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/tls.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/tls.ll Fri Sep ?9 15:45:50 2011
> @@ -1,5 +1,5 @@
> -; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s -check-prefix=PIC
> -; RUN: llc -march=mipsel -mcpu=mips2 -relocation-model=static < %s \
> +; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=PIC
> +; RUN: llc -march=mipsel -relocation-model=static < %s \
> ?; RUN: ? ? ? ? ? ? ? ? ? ? ? ? ? ? | FileCheck %s -check-prefix=STATIC
>
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From eli.friedman at gmail.com  Fri Sep  9 16:04:06 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Fri, 09 Sep 2011 21:04:06 -0000
Subject: [llvm-commits] [llvm] r139407 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
Message-ID: <20110909210407.1C2DB2A6C12C@llvm.org>

Author: efriedma
Date: Fri Sep  9 16:04:06 2011
New Revision: 139407

URL: http://llvm.org/viewvc/llvm-project?rev=139407&view=rev
Log:
Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type.  Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs.  Fixes PR10897.


Added:
    llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=139407&r1=139406&r2=139407&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Sep  9 16:04:06 2011
@@ -6770,6 +6770,7 @@
   SDValue InVec = N->getOperand(0);
   SDValue InVal = N->getOperand(1);
   SDValue EltNo = N->getOperand(2);
+  DebugLoc dl = N->getDebugLoc();
 
   // If the inserted element is an UNDEF, just use the input vector.
   if (InVal.getOpcode() == ISD::UNDEF)
@@ -6781,32 +6782,40 @@
   if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
     return SDValue();
 
-  // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
-  // vector with the inserted element.
-  if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
-    unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
-    SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
-                                InVec.getNode()->op_end());
-    if (Elt < Ops.size())
-      Ops[Elt] = InVal;
-    return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
-                       VT, &Ops[0], Ops.size());
-  }
-  // If the invec is an UNDEF and if EltNo is a constant, create a new
-  // BUILD_VECTOR with undef elements and the inserted element.
-  if (InVec.getOpcode() == ISD::UNDEF &&
-      isa<ConstantSDNode>(EltNo)) {
-    EVT EltVT = VT.getVectorElementType();
+  // Check that we know which element is being inserted
+  if (!isa<ConstantSDNode>(EltNo))
+    return SDValue();
+  unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
+
+  // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
+  // be converted to a BUILD_VECTOR).  Fill in the Ops vector with the
+  // vector elements.
+  SmallVector<SDValue, 8> Ops;
+  if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
+    Ops.append(InVec.getNode()->op_begin(),
+               InVec.getNode()->op_end());
+  } else if (InVec.getOpcode() == ISD::UNDEF) {
     unsigned NElts = VT.getVectorNumElements();
-    SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
+    Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
+  } else {
+    return SDValue();
+  }
 
-    unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
-    if (Elt < Ops.size())
-      Ops[Elt] = InVal;
-    return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
-                       VT, &Ops[0], Ops.size());
+  // Insert the element
+  if (Elt < Ops.size()) {
+    // All the operands of BUILD_VECTOR must have the same type;
+    // we enforce that here.
+    EVT OpVT = Ops[0].getValueType();
+    if (InVal.getValueType() != OpVT)
+      InVal = OpVT.bitsGT(InVal.getValueType()) ?
+                DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
+                DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
+    Ops[Elt] = InVal;
   }
-  return SDValue();
+
+  // Return the new vector
+  return DAG.getNode(ISD::BUILD_VECTOR, dl,
+                     VT, &Ops[0], Ops.size());
 }
 
 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=139407&r1=139406&r2=139407&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Sep  9 16:04:06 2011
@@ -771,11 +771,14 @@
     assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
            "Wrong number of operands!");
     EVT EltVT = N->getValueType(0).getVectorElementType();
-    for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
+    for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) {
       assert((I->getValueType() == EltVT ||
              (EltVT.isInteger() && I->getValueType().isInteger() &&
               EltVT.bitsLE(I->getValueType()))) &&
             "Wrong operand type!");
+      assert(I->getValueType() == N->getOperand(0).getValueType() &&
+             "Operands must all have the same type");
+    }
     break;
   }
   }

Added: llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll?rev=139407&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll Fri Sep  9 16:04:06 2011
@@ -0,0 +1,23 @@
+; RUN: llc -mtriple=armv7-- %s -mattr=-neon
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32"
+target triple = "armv7-none-linux-gnueabi"
+
+ at x1 = common global <3 x i16> zeroinitializer
+ at y1 = common global <3 x i16> zeroinitializer
+ at z1 = common global <3 x i16> zeroinitializer
+ at x2 = common global <4 x i16> zeroinitializer
+ at y2 = common global <4 x i16> zeroinitializer
+ at z2 = common global <4 x i16> zeroinitializer
+
+define void @f() {
+  %1 = load <3 x i16>* @x1
+  %2 = load <3 x i16>* @y1
+  %3 = sdiv <3 x i16> %1, %2
+  store <3 x i16> %3, <3 x i16>* @z1
+  %4 = load <4 x i16>* @x2
+  %5 = load <4 x i16>* @y2
+  %6 = sdiv <4 x i16> %4, %5
+  store <4 x i16> %6, <4 x i16>* @z2
+  ret void
+}



From ahatanak at gmail.com  Fri Sep  9 16:31:46 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 09 Sep 2011 21:31:46 -0000
Subject: [llvm-commits] [llvm] r139412 -
	/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
Message-ID: <20110909213146.DAAFD2A6C12C@llvm.org>

Author: ahatanak
Date: Fri Sep  9 16:31:46 2011
New Revision: 139412

URL: http://llvm.org/viewvc/llvm-project?rev=139412&view=rev
Log:
Mips32 does not reserve even-numbered floating point registers.

Modified:
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=139412&r1=139411&r2=139412&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Fri Sep  9 16:31:46 2011
@@ -132,11 +132,6 @@
   Reserved.set(Mips::F31);
   Reserved.set(Mips::D15);
 
-  // SRV4 requires that odd register can't be used.
-  if (!Subtarget.isSingleFloat() && !Subtarget.isMips32())
-    for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
-      Reserved.set(FReg);
-
   return Reserved;
 }
 



From dgregor at apple.com  Fri Sep  9 16:37:30 2011
From: dgregor at apple.com (Douglas Gregor)
Date: Fri, 09 Sep 2011 21:37:30 -0000
Subject: [llvm-commits] [llvm] r139414 -
	/llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp
Message-ID: <20110909213730.0EF682A6C12C@llvm.org>

Author: dgregor
Date: Fri Sep  9 16:37:29 2011
New Revision: 139414

URL: http://llvm.org/viewvc/llvm-project?rev=139414&view=rev
Log:
Update Clang AST attribute reader tblgen generation to match with ASTReader change

Modified:
    llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp

Modified: llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp?rev=139414&r1=139413&r2=139414&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp Fri Sep  9 16:37:29 2011
@@ -701,7 +701,7 @@
       Args.push_back(A);
       A->writePCHReadDecls(OS);
     }
-    OS << "    New = new (*Context) " << R.getName() << "Attr(Loc, *Context";
+    OS << "    New = new (Context) " << R.getName() << "Attr(Loc, Context";
     for (ri = Args.begin(), re = Args.end(); ri != re; ++ri) {
       OS << ", ";
       (*ri)->writePCHReadArgs(OS);



From resistor at mac.com  Fri Sep  9 16:48:23 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 09 Sep 2011 21:48:23 -0000
Subject: [llvm-commits] [llvm] r139415 - in /llvm/trunk:
 lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp
 lib/Target/ARM/ARMConstantIslandPass.cpp
 lib/Target/ARM/ARMFrameLowering.cpp lib/Target/ARM/ARMISelLowering.cpp
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMInstrThumb2.td
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110909214823.DF8B62A6C12C@llvm.org>

Author: resistor
Date: Fri Sep  9 16:48:23 2011
New Revision: 139415

URL: http://llvm.org/viewvc/llvm-project?rev=139415&view=rev
Log:
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
    llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=139415&r1=139414&r2=139415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Sep  9 16:48:23 2011
@@ -963,6 +963,8 @@
       MCInst BrInst;
       BrInst.setOpcode(ARM::t2B);
       BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
+      BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      BrInst.addOperand(MCOperand::CreateReg(0));
       OutStreamer.EmitInstruction(BrInst);
       continue;
     }
@@ -1677,6 +1679,8 @@
       MCInst TmpInst;
       TmpInst.setOpcode(ARM::tB);
       TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
       OutStreamer.EmitInstruction(TmpInst);
     }
     {

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=139415&r1=139414&r2=139415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Sep  9 16:48:23 2011
@@ -404,7 +404,8 @@
     ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
   int BccOpc = !AFI->isThumbFunction()
     ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
-
+  bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
+ 
   // Shouldn't be a fall through.
   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
   assert((Cond.size() == 2 || Cond.size() == 0) &&
@@ -412,7 +413,10 @@
 
   if (FBB == 0) {
     if (Cond.empty()) // Unconditional branch?
-      BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
+      if (isThumb)
+        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
+      else
+        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
     else
       BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
         .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
@@ -422,7 +426,10 @@
   // Two-way conditional branch.
   BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
     .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
-  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
+  if (isThumb)
+    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
+  else
+    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
   return 2;
 }
 

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=139415&r1=139414&r2=139415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Fri Sep  9 16:48:23 2011
@@ -739,7 +739,11 @@
   // There doesn't seem to be meaningful DebugInfo available; this doesn't
   // correspond to anything in the source.
   unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
-  BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
+  if (!isThumb)
+    BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
+  else
+    BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB)
+            .addImm(ARMCC::AL).addReg(0);
   ++NumSplit;
 
   // Update the CFG.  All succs of OrigBB are now succs of NewBB.
@@ -1151,7 +1155,11 @@
     // targets will be exchanged, and the altered branch may be out of
     // range, so the machinery has to know about it.
     int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
-    BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
+    if (!isThumb)
+      BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
+    else
+      BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB)
+              .addImm(ARMCC::AL).addReg(0);
     unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
     ImmBranches.push_back(ImmBranch(&UserMBB->back(),
                           MaxDisp, false, UncondBr));
@@ -1893,7 +1901,8 @@
   // There doesn't seem to be meaningful DebugInfo available; this doesn't
   // correspond directly to anything in the source.
   assert (isThumb2 && "Adjusting for TB[BH] but not in Thumb2?");
-  BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)).addMBB(BB);
+  BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)).addMBB(BB)
+          .addImm(ARMCC::AL).addReg(0);
 
   // Update internal data structures to account for the newly inserted MBB.
   MF.RenumberBlocks(NewBB);

Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=139415&r1=139414&r2=139415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Fri Sep  9 16:48:23 2011
@@ -414,6 +414,9 @@
         MIB.addExternalSymbol(JumpTarget.getSymbolName(),
                               JumpTarget.getTargetFlags());
       }
+
+      // Add the default predicate in Thumb mode.
+      if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
     } else if (RetOpcode == ARM::TCRETURNri) {
       BuildMI(MBB, MBBI, dl,
               TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=139415&r1=139414&r2=139415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Sep  9 16:48:23 2011
@@ -5713,8 +5713,10 @@
 
     BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
       .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
-    BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
-      .addMBB(exitMBB);
+    if (isThumb2)
+      AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
+    else
+      BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
 
     MI->eraseFromParent();   // The pseudo instruction is gone now.
     return BB;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=139415&r1=139414&r2=139415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Sep  9 16:48:23 2011
@@ -487,8 +487,8 @@
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
   let isPredicable = 1 in
-  def tB   : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
-                 "b\t$target", [(br bb:$target)]>,
+  def tB   : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
+                 "b", "\t$target", [(br bb:$target)]>,
              T1Encoding<{1,1,1,0,0,?}> {
     bits<11> target;
     let Inst{10-0} = target;
@@ -537,9 +537,10 @@
   // Non-Darwin versions (the difference is R9).
   let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
       Uses = [SP] in {
-    def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
+    def tTAILJMPdND : tPseudoExpand<(outs),
+                   (ins t_brtarget:$dst, pred:$p, variable_ops),
                    4, IIC_Br, [],
-                   (tB t_brtarget:$dst)>,
+                   (tB t_brtarget:$dst, pred:$p)>,
                  Requires<[IsThumb, IsNotDarwin]>;
     def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
                      4, IIC_Br, [],

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139415&r1=139414&r2=139415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Sep  9 16:48:23 2011
@@ -3004,8 +3004,8 @@
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
 let isPredicable = 1 in
-def t2B   : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
-                 "b.w\t$target",
+def t2B   : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
+                 "b", ".w\t$target",
                  [(br bb:$target)]> {
   let Inst{31-27} = 0b11110;
   let Inst{15-14} = 0b10;
@@ -3060,7 +3060,7 @@
 } // isBranch, isTerminator, isBarrier
 
 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
-// a two-value operand where a dag node expects two operands. :(
+// a two-value operand where a dag node expects ", "two operands. :(
 let isBranch = 1, isTerminator = 1 in
 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
                 "b", ".w\t$target",
@@ -3088,9 +3088,10 @@
   // Darwin version.
   let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
       Uses = [SP] in
-  def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops),
+  def tTAILJMPd: tPseudoExpand<(outs),
+                   (ins uncondbrtarget:$dst, pred:$p, variable_ops),
                    4, IIC_Br, [],
-                   (t2B uncondbrtarget:$dst)>,
+                   (t2B uncondbrtarget:$dst, pred:$p)>,
                  Requires<[IsThumb2, IsDarwin]>;
 }
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139415&r1=139414&r2=139415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Sep  9 16:48:23 2011
@@ -3567,8 +3567,8 @@
   // Check for non-'al' condition codes outside of the IT block.
   } else if (isThumbTwo() && MCID.isPredicable() &&
              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
-             ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
-             Inst.getOpcode() != ARM::t2Bcc)
+             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
+             Inst.getOpcode() != ARM::t2B)
     return Error(Loc, "predicated instructions must be in IT block");
 
   switch (Inst.getOpcode()) {
@@ -3721,6 +3721,16 @@
     if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
       Inst.setOpcode(ARM::tADDi3);
     break;
+  case ARM::tB:
+    // A Thumb conditional branch outside of an IT block is a tBcc.
+    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
+      Inst.setOpcode(ARM::tBcc);
+    break;
+  case ARM::t2B:
+    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
+    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
+      Inst.setOpcode(ARM::t2Bcc);
+    break;
   case ARM::t2Bcc:
     // If the conditional is AL or we're in an IT block, we really want t2B.
     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139415&r1=139414&r2=139415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Sep  9 16:48:23 2011
@@ -426,6 +426,8 @@
 // post-pass.
 MCDisassembler::DecodeStatus
 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
+  MCDisassembler::DecodeStatus S = Success;
+
   // A few instructions actually have predicates encoded in them.  Don't
   // try to overwrite it if we're seeing one of those.
   switch (MI.getOpcode()) {
@@ -436,8 +438,16 @@
       // Some instructions (mostly conditional branches) are not
       // allowed in IT blocks.
       if (!ITBlock.empty())
-        return SoftFail;
-      return Success;
+        S = SoftFail;
+      else
+        return Success;
+      break;
+    case ARM::tB:
+    case ARM::t2B:
+      // Some instructions (mostly unconditional branches) can
+      // only appears at the end of, or outside of, an IT.
+      if (ITBlock.size() > 1)
+        S = SoftFail;
       break;
     default:
       break;
@@ -466,7 +476,7 @@
         MI.insert(I, MCOperand::CreateReg(0));
       else
         MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
-      return Success;
+      return S;
     }
   }
 
@@ -477,7 +487,7 @@
   else
     MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
 
-  return Success;
+  return S;
 }
 
 // Thumb VFP instructions are a special case.  Because we share their

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139415&r1=139414&r2=139415&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 16:48:23 2011
@@ -188,7 +188,7 @@
 @ CHECK: beq.w	_bar                    @ encoding: [A,0xf0'A',A,0x80'A']
           @   fixup A - offset: 0, value: _bar, kind: fixup_t2_condbranch
 @ CHECK: it	eq                      @ encoding: [0x08,0xbf]
-@ CHECK: b.w	_bar                    @ encoding: [A,0xf0'A',A,0x90'A']
+@ CHECK: beq.w	_bar                    @ encoding: [A,0xf0'A',A,0x90'A']
           @   fixup A - offset: 0, value: _bar, kind: fixup_t2_uncondbranch
 @ CHECK: bmi.w   #-183396                @ encoding: [0x13,0xf5,0xce,0xa9]
 



From sabre at nondot.org  Fri Sep  9 17:06:59 2011
From: sabre at nondot.org (Chris Lattner)
Date: Fri, 09 Sep 2011 22:06:59 -0000
Subject: [llvm-commits] [llvm] r139419 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20110909220659.E01C42A6C12C@llvm.org>

Author: lattner
Date: Fri Sep  9 17:06:59 2011
New Revision: 139419

URL: http://llvm.org/viewvc/llvm-project?rev=139419&view=rev
Log:
tidy up a bit

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=139419&r1=139418&r2=139419&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Sep  9 17:06:59 2011
@@ -2002,10 +2002,10 @@
 }
 
 /// handleJTSwitchCase - Emit jumptable for current switch case range
-bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
-                                             CaseRecVector& WorkList,
-                                             const Value* SV,
-                                             MachineBasicBlock* Default,
+bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
+                                             CaseRecVector &WorkList,
+                                             const Value *SV,
+                                             MachineBasicBlock *Default,
                                              MachineBasicBlock *SwitchBB) {
   Case& FrontCase = *CR.Range.first;
   Case& BackCase  = *(CR.Range.second-1);
@@ -2014,8 +2014,7 @@
   const APInt &Last  = cast<ConstantInt>(BackCase.High)->getValue();
 
   APInt TSize(First.getBitWidth(), 0);
-  for (CaseItr I = CR.Range.first, E = CR.Range.second;
-       I!=E; ++I)
+  for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
     TSize += I->size();
 
   if (!areJTsAllowed(TLI) || TSize.ult(4))
@@ -2093,7 +2092,6 @@
     visitJumpTableHeader(JT, JTH, SwitchBB);
 
   JTCases.push_back(JumpTableBlock(JTH, JT));
-
   return true;
 }
 



From ahatanak at gmail.com  Fri Sep  9 17:11:26 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 09 Sep 2011 22:11:26 -0000
Subject: [llvm-commits] [llvm] r139420 - in /llvm/trunk/lib/Target/Mips:
 MipsRegisterInfo.cpp MipsRegisterInfo.td
Message-ID: <20110909221126.8B5C52A6C12C@llvm.org>

Author: ahatanak
Date: Fri Sep  9 17:11:26 2011
New Revision: 139420

URL: http://llvm.org/viewvc/llvm-project?rev=139420&view=rev
Log:
Make F31 and D15 non-reserved registers.

Modified:
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=139420&r1=139419&r2=139420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Fri Sep  9 17:11:26 2011
@@ -129,8 +129,6 @@
   Reserved.set(Mips::SP);
   Reserved.set(Mips::FP);
   Reserved.set(Mips::RA);
-  Reserved.set(Mips::F31);
-  Reserved.set(Mips::D15);
 
   return Reserved;
 }

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=139420&r1=139419&r2=139420&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Fri Sep  9 17:11:26 2011
@@ -182,9 +182,7 @@
   // Not preserved across procedure calls
   D2, D3, D4, D5, D8, D9,
   // Callee save
-  D10, D11, D12, D13, D14,
-  // Reserved
-  D15)> {
+  D10, D11, D12, D13, D14, D15)> {
   let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)];
 }
 



From ahatanak at gmail.com  Fri Sep  9 17:22:48 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 09 Sep 2011 22:22:48 -0000
Subject: [llvm-commits] [llvm] r139421 - in /llvm/trunk/lib/Target/Mips:
 MipsAsmPrinter.cpp MipsSubtarget.h
Message-ID: <20110909222248.8CA7E2A6C12C@llvm.org>

Author: ahatanak
Date: Fri Sep  9 17:22:48 2011
New Revision: 139421

URL: http://llvm.org/viewvc/llvm-project?rev=139421&view=rev
Log:
O64 will not be supported.

Modified:
    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/MipsSubtarget.h

Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=139421&r1=139420&r2=139421&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Fri Sep  9 17:22:48 2011
@@ -209,7 +209,6 @@
 const char *MipsAsmPrinter::getCurrentABIString() const {
   switch (Subtarget->getTargetABI()) {
   case MipsSubtarget::O32:  return "abi32";
-  case MipsSubtarget::O64:  return "abiO64";
   case MipsSubtarget::N32:  return "abiN32";
   case MipsSubtarget::N64:  return "abi64";
   case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=139421&r1=139420&r2=139421&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Fri Sep  9 17:22:48 2011
@@ -28,7 +28,7 @@
 
 public:
   enum MipsABIEnum {
-    O32, O64, N32, N64, EABI
+    O32, N32, N64, EABI
   };
 
 protected:



From resistor at mac.com  Fri Sep  9 17:24:36 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 09 Sep 2011 22:24:36 -0000
Subject: [llvm-commits] [llvm] r139422 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
 test/MC/ARM/basic-thumb2-instructions.s test/MC/Disassembler/ARM/thumb2.txt
Message-ID: <20110909222436.CFE542A6C12C@llvm.org>

Author: resistor
Date: Fri Sep  9 17:24:36 2011
New Revision: 139422

URL: http://llvm.org/viewvc/llvm-project?rev=139422&view=rev
Log:
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
    llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139422&r1=139421&r2=139422&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Sep  9 17:24:36 2011
@@ -1146,7 +1146,7 @@
 // assembler.
 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
               (ins t2adrlabel:$addr, pred:$p),
-              IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
+              IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
   let Inst{31-27} = 0b11110;
   let Inst{25-24} = 0b10;
   // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
@@ -1163,6 +1163,8 @@
   let Inst{26}    = addr{11};
   let Inst{14-12} = addr{10-8};
   let Inst{7-0}   = addr{7-0};
+
+  let DecoderMethod = "DecodeT2Adr";
 }
 
 let neverHasSideEffects = 1, isReMaterializable = 1 in

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139422&r1=139421&r2=139422&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Sep  9 17:24:36 2011
@@ -299,6 +299,8 @@
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
+                                uint64_t Address, const void *Decoder);
 
 #include "ARMGenDisassemblerTables.inc"
 #include "ARMGenInstrInfo.inc"
@@ -3762,3 +3764,19 @@
 
   return S;
 }
+
+static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
+                                uint64_t Address, const void *Decoder) {
+  unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
+  unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
+  if (sign1 != sign2) return MCDisassembler::Fail;
+
+  unsigned Val = fieldFromInstruction32(Insn, 0, 8);
+  Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
+  Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
+  Val |= sign1 << 12;
+  Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
+
+  return MCDisassembler::Success;
+}
+

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=139422&r1=139421&r2=139422&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Fri Sep  9 17:24:36 2011
@@ -662,7 +662,12 @@
   if (MO.isExpr())
     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
                                     Fixups);
-  return MO.getImm();
+  int32_t Val = MO.getImm();
+  if (Val < 0) {
+    Val *= -1;
+    Val |= 0x1000;
+  }
+  return Val;
 }
 
 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139422&r1=139421&r2=139422&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 17:24:36 2011
@@ -107,6 +107,12 @@
 @ FIXME: ADR
 @------------------------------------------------------------------------------
 
+        subw r11, pc, #3270
+        adr.w r11, #-826
+
+@ CHECK: subw	r11, pc, #3270          @ encoding: [0xaf,0xf6,0xc6,0x4b]
+@ CHECK: adr.w	r11, #-826              @ encoding: [0xaf,0xf2,0x3a,0x3b]
+
 @------------------------------------------------------------------------------
 @ AND (immediate)
 @------------------------------------------------------------------------------

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt?rev=139422&r1=139421&r2=139422&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt Fri Sep  9 17:24:36 2011
@@ -88,8 +88,13 @@
 
 
 #------------------------------------------------------------------------------
-# FIXME: ADR
+# ADR
 #------------------------------------------------------------------------------
+# CHECK: subw r11, pc, #3270
+# CHECK: subw r11, pc, #826
+
+0xaf 0xf6 0xc6 0x4b
+0xaf 0xf2 0x3a 0x3b
 
 #------------------------------------------------------------------------------
 # AND (immediate)



From clattner at apple.com  Fri Sep  9 17:51:40 2011
From: clattner at apple.com (Chris Lattner)
Date: Fri, 09 Sep 2011 15:51:40 -0700
Subject: [llvm-commits] Patch to Add SAFECode as a LLVM Sub-Project
In-Reply-To: <4E6A52DD.6040507@illinois.edu>
References: <4E552194.1000807@illinois.edu>
	<6F48BB93-1A52-4436-9EEC-75530C1DC7AF@apple.com>
	<4E6A3523.8080708@illinois.edu>
	<E1E66326-FB45-4957-8402-0D368CF86049@apple.com>
	<4E6A52DD.6040507@illinois.edu>
Message-ID: <0A0A9545-BDBE-468D-B3B7-0F01F2C7942C@apple.com>


On Sep 9, 2011, at 10:54 AM, John Criswell wrote:

> On 9/9/11 12:40 PM, Chris Lattner wrote:
>> That is really weird, the post-commit script is supposed to keep the website up to date.  It looks like it is broken.
> 
> Just to be certain I'm doing things right, I should be committing to http://llvm.org/svn/llvm-project/www/trunk, right?

Yep, that should just work.  Most likely cause of failure is a permission problem on the server.

-Chris
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From resistor at mac.com  Fri Sep  9 18:05:14 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 09 Sep 2011 23:05:14 -0000
Subject: [llvm-commits] [llvm] r139429 -
	/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
Message-ID: <20110909230514.90D4D2A6C12C@llvm.org>

Author: resistor
Date: Fri Sep  9 18:05:14 2011
New Revision: 139429

URL: http://llvm.org/viewvc/llvm-project?rev=139429&view=rev
Log:
Fix buildbot breakage caused by r139415.  I missed one instance of a manually create ARM::tB.

Modified:
    llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=139429&r1=139428&r2=139429&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Fri Sep  9 18:05:14 2011
@@ -1522,7 +1522,11 @@
     .addMBB(NextBB).addImm(CC).addReg(CCReg);
   Br.MI = &MBB->back();
   BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
-  BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
+  if (isThumb)
+    BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)
+            .addImm(ARMCC::AL).addReg(0);
+  else
+    BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
   BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
   unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
   ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));



From resistor at mac.com  Fri Sep  9 18:13:02 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 09 Sep 2011 23:13:02 -0000
Subject: [llvm-commits] [llvm] r139431 -
	/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
Message-ID: <20110909231302.9C66C2A6C12C@llvm.org>

Author: resistor
Date: Fri Sep  9 18:13:02 2011
New Revision: 139431

URL: http://llvm.org/viewvc/llvm-project?rev=139431&view=rev
Log:
Fix an ambiguously nested if.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=139431&r1=139430&r2=139431&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Sep  9 18:13:02 2011
@@ -412,12 +412,12 @@
          "ARM branch conditions have two components!");
 
   if (FBB == 0) {
-    if (Cond.empty()) // Unconditional branch?
+    if (Cond.empty()) { // Unconditional branch?
       if (isThumb)
         BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
       else
         BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
-    else
+    } else
       BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
         .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
     return 1;



From resistor at mac.com  Fri Sep  9 18:13:33 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 09 Sep 2011 23:13:33 -0000
Subject: [llvm-commits] [llvm] r139432 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/invalid-LDM-thumb.txt
Message-ID: <20110909231333.552BF2A6C12C@llvm.org>

Author: resistor
Date: Fri Sep  9 18:13:33 2011
New Revision: 139432

URL: http://llvm.org/viewvc/llvm-project?rev=139432&view=rev
Log:
LDM writeback is not allowed if Rn is in the target register list.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139432&r1=139431&r2=139432&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Sep  9 18:13:33 2011
@@ -918,12 +918,31 @@
                                  uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
+  bool writebackLoad = false;
+  unsigned writebackReg = 0;
+  switch (Inst.getOpcode()) {
+    default:
+      break;
+    case ARM::LDMIA_UPD:
+    case ARM::LDMDB_UPD:
+    case ARM::LDMIB_UPD:
+    case ARM::LDMDA_UPD:
+    case ARM::t2LDMIA_UPD:
+    case ARM::t2LDMDB_UPD:
+      writebackLoad = true;
+      writebackReg = Inst.getOperand(0).getReg();
+      break;
+  }
+
   // Empty register lists are not allowed.
   if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
   for (unsigned i = 0; i < 16; ++i) {
     if (Val & (1 << i)) {
       if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
         return MCDisassembler::Fail;
+      // Writeback not allowed if Rn is in the target list.
+      if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
+        Check(S, MCDisassembler::SoftFail);
     }
   }
 

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt?rev=139432&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt Fri Sep  9 18:13:33 2011
@@ -0,0 +1,5 @@
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding}
+
+# Writeback is not allowed is Rn is in the target register list.
+
+0xb4 0xe8 0x34 0x04



From ahatanak at gmail.com  Fri Sep  9 18:14:58 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 09 Sep 2011 23:14:58 -0000
Subject: [llvm-commits] [llvm] r139433 - in /llvm/trunk/test/CodeGen/Mips:
 2010-11-09-CountLeading.ll 2010-11-09-Mul.ll alloca.ll cmov.ll
 double2int.ll eh.ll fcopysign.ll fpcmp.ll i64arg.ll inlineasmmemop.ll
 internalfunc.ll madd-msub.ll o32_cc.ll o32_cc_byval.ll select.ll
Message-ID: <20110909231458.7DCF42A6C12C@llvm.org>

Author: ahatanak
Date: Fri Sep  9 18:14:58 2011
New Revision: 139433

URL: http://llvm.org/viewvc/llvm-project?rev=139433&view=rev
Log:
Fix test cases.
Generate code for Mips32r1 unless a Mips32r2 feature is tested.

Modified:
    llvm/trunk/test/CodeGen/Mips/2010-11-09-CountLeading.ll
    llvm/trunk/test/CodeGen/Mips/2010-11-09-Mul.ll
    llvm/trunk/test/CodeGen/Mips/alloca.ll
    llvm/trunk/test/CodeGen/Mips/cmov.ll
    llvm/trunk/test/CodeGen/Mips/double2int.ll
    llvm/trunk/test/CodeGen/Mips/eh.ll
    llvm/trunk/test/CodeGen/Mips/fcopysign.ll
    llvm/trunk/test/CodeGen/Mips/fpcmp.ll
    llvm/trunk/test/CodeGen/Mips/i64arg.ll
    llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
    llvm/trunk/test/CodeGen/Mips/internalfunc.ll
    llvm/trunk/test/CodeGen/Mips/madd-msub.ll
    llvm/trunk/test/CodeGen/Mips/o32_cc.ll
    llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
    llvm/trunk/test/CodeGen/Mips/select.ll

Modified: llvm/trunk/test/CodeGen/Mips/2010-11-09-CountLeading.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-11-09-CountLeading.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2010-11-09-CountLeading.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2010-11-09-CountLeading.ll Fri Sep  9 18:14:58 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mips < %s | FileCheck %s
 
 ; CHECK: clz $2, $4
 define i32 @t1(i32 %X) nounwind readnone {

Modified: llvm/trunk/test/CodeGen/Mips/2010-11-09-Mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-11-09-Mul.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2010-11-09-Mul.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2010-11-09-Mul.ll Fri Sep  9 18:14:58 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mips < %s | FileCheck %s
 
 ; CHECK: mul $2, $5, $4
 define i32 @mul1(i32 %a, i32 %b) nounwind readnone {

Modified: llvm/trunk/test/CodeGen/Mips/alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/alloca.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/alloca.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/alloca.ll Fri Sep  9 18:14:58 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mipsel < %s | FileCheck %s
 
 define i32 @twoalloca(i32 %size) nounwind {
 entry:

Modified: llvm/trunk/test/CodeGen/Mips/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cmov.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cmov.ll Fri Sep  9 18:14:58 2011
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
-; RUN: llc -march=mips -mcpu=4ke -regalloc=basic < %s | FileCheck %s
+; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s
 
 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
 @i3 = common global i32* null, align 4

Modified: llvm/trunk/test/CodeGen/Mips/double2int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/double2int.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/double2int.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/double2int.ll Fri Sep  9 18:14:58 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mips < %s | FileCheck %s
 
 define i32 @f1(double %d) nounwind readnone {
 entry:

Modified: llvm/trunk/test/CodeGen/Mips/eh.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/eh.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/eh.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/eh.ll Fri Sep  9 18:14:58 2011
@@ -1,5 +1,5 @@
-; RUN: llc  < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL
-; RUN: llc  < %s -march=mips   -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB
+; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL
+; RUN: llc  < %s -march=mips   | FileCheck %s -check-prefix=CHECK-EB
 
 @g1 = global double 0.000000e+00, align 8
 @_ZTId = external constant i8*

Modified: llvm/trunk/test/CodeGen/Mips/fcopysign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcopysign.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fcopysign.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fcopysign.ll Fri Sep  9 18:14:58 2011
@@ -1,5 +1,5 @@
-; RUN: llc  < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL
-; RUN: llc  < %s -march=mips -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB
+; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL
+; RUN: llc  < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB
 
 define double @func0(double %d0, double %d1) nounwind readnone {
 entry:

Modified: llvm/trunk/test/CodeGen/Mips/fpcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fpcmp.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fpcmp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fpcmp.ll Fri Sep  9 18:14:58 2011
@@ -1,13 +1,13 @@
-; RUN: llc  < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
+; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS32
 
 @g1 = external global i32
 
 define i32 @f(float %f0, float %f1) nounwind {
 entry:
-; CHECK-MIPS32R2: c.olt.s
-; CHECK-MIPS32R2: movt
-; CHECK-MIPS32R2: c.olt.s
-; CHECK-MIPS32R2: movt
+; CHECK-MIPS32: c.olt.s
+; CHECK-MIPS32: movt
+; CHECK-MIPS32: c.olt.s
+; CHECK-MIPS32: movt
   %cmp = fcmp olt float %f0, %f1
   %conv = zext i1 %cmp to i32
   %tmp2 = load i32* @g1, align 4

Modified: llvm/trunk/test/CodeGen/Mips/i64arg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/i64arg.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/i64arg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/i64arg.ll Fri Sep  9 18:14:58 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mips < %s | FileCheck %s
 
 define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind {
 entry:

Modified: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll Fri Sep  9 18:14:58 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mipsel < %s | FileCheck %s
 
 @g1 = external global i32
 

Modified: llvm/trunk/test/CodeGen/Mips/internalfunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/internalfunc.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/internalfunc.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/internalfunc.ll Fri Sep  9 18:14:58 2011
@@ -1,4 +1,4 @@
-; RUN: llc  < %s -march=mipsel -mcpu=4ke  | FileCheck %s
+; RUN: llc  < %s -march=mipsel | FileCheck %s
 
 @caller.sf1 = internal unnamed_addr global void (...)* null, align 4
 @gf1 = external global void (...)*

Modified: llvm/trunk/test/CodeGen/Mips/madd-msub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/madd-msub.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/madd-msub.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/madd-msub.ll Fri Sep  9 18:14:58 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mips < %s | FileCheck %s
 
 ; CHECK: madd $5, $4
 define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {

Modified: llvm/trunk/test/CodeGen/Mips/o32_cc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc.ll Fri Sep  9 18:14:58 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mips < %s | FileCheck %s
 
 ; FIXME: Disabled because it unpredictably fails on certain platforms.
 ; REQUIRES: disabled

Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Fri Sep  9 18:14:58 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mipsel < %s | FileCheck %s
 
 %0 = type { i8, i16, i32, i64, double, i32, [4 x i8] }
 %struct.S1 = type { i8, i16, i32, i64, double, i32 }

Modified: llvm/trunk/test/CodeGen/Mips/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/select.ll?rev=139433&r1=139432&r2=139433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/select.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/select.ll Fri Sep  9 18:14:58 2011
@@ -1,11 +1,11 @@
-; RUN: llc  < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
+; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK
 
 @d2 = external global double
 @d3 = external global double
 
 define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: movn
+; CHECK: movn
   %tobool = icmp ne i32 %s, 0
   %cond = select i1 %tobool, i32 %f1, i32 %f0
   ret i32 %cond
@@ -13,7 +13,7 @@
 
 define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: movn.s
+; CHECK: movn.s
   %tobool = icmp ne i32 %s, 0
   %cond = select i1 %tobool, float %f0, float %f1
   ret float %cond
@@ -21,7 +21,7 @@
 
 define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: movn.d
+; CHECK: movn.d
   %tobool = icmp ne i32 %s, 0
   %cond = select i1 %tobool, double %f0, double %f1
   ret double %cond
@@ -29,8 +29,8 @@
 
 define float @sel3(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: c.eq.s
-; CHECK-MIPS32R2: movt.s
+; CHECK: c.eq.s
+; CHECK: movt.s
   %cmp = fcmp oeq float %f2, %f3
   %cond = select i1 %cmp, float %f0, float %f1
   ret float %cond
@@ -38,8 +38,8 @@
 
 define float @sel4(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: c.olt.s
-; CHECK-MIPS32R2: movt.s
+; CHECK: c.olt.s
+; CHECK: movt.s
   %cmp = fcmp olt float %f2, %f3
   %cond = select i1 %cmp, float %f0, float %f1
   ret float %cond
@@ -47,8 +47,8 @@
 
 define float @sel5(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: c.ule.s
-; CHECK-MIPS32R2: movf.s
+; CHECK: c.ule.s
+; CHECK: movf.s
   %cmp = fcmp ogt float %f2, %f3
   %cond = select i1 %cmp, float %f0, float %f1
   ret float %cond
@@ -56,8 +56,8 @@
 
 define double @sel5_1(double %f0, double %f1, float %f2, float %f3) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: c.ule.s
-; CHECK-MIPS32R2: movf.d
+; CHECK: c.ule.s
+; CHECK: movf.d
   %cmp = fcmp ogt float %f2, %f3
   %cond = select i1 %cmp, double %f0, double %f1
   ret double %cond
@@ -65,8 +65,8 @@
 
 define double @sel6(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: c.eq.d
-; CHECK-MIPS32R2: movt.d
+; CHECK: c.eq.d
+; CHECK: movt.d
   %cmp = fcmp oeq double %f2, %f3
   %cond = select i1 %cmp, double %f0, double %f1
   ret double %cond
@@ -74,8 +74,8 @@
 
 define double @sel7(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: c.olt.d
-; CHECK-MIPS32R2: movt.d
+; CHECK: c.olt.d
+; CHECK: movt.d
   %cmp = fcmp olt double %f2, %f3
   %cond = select i1 %cmp, double %f0, double %f1
   ret double %cond
@@ -83,8 +83,8 @@
 
 define double @sel8(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: c.ule.d
-; CHECK-MIPS32R2: movf.d
+; CHECK: c.ule.d
+; CHECK: movf.d
   %cmp = fcmp ogt double %f2, %f3
   %cond = select i1 %cmp, double %f0, double %f1
   ret double %cond
@@ -92,8 +92,8 @@
 
 define float @sel8_1(float %f0, float %f1, double %f2, double %f3) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: c.ule.d
-; CHECK-MIPS32R2: movf.s
+; CHECK: c.ule.d
+; CHECK: movf.s
   %cmp = fcmp ogt double %f2, %f3
   %cond = select i1 %cmp, float %f0, float %f1
   ret float %cond
@@ -101,8 +101,8 @@
 
 define i32 @sel9(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: c.eq.s
-; CHECK-MIPS32R2: movt
+; CHECK: c.eq.s
+; CHECK: movt
   %cmp = fcmp oeq float %f2, %f3
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
@@ -110,8 +110,8 @@
 
 define i32 @sel10(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: c.olt.s
-; CHECK-MIPS32R2: movt
+; CHECK: c.olt.s
+; CHECK: movt
   %cmp = fcmp olt float %f2, %f3
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
@@ -119,8 +119,8 @@
 
 define i32 @sel11(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
 entry:
-; CHECK-MIPS32R2: c.ule.s
-; CHECK-MIPS32R2: movf
+; CHECK: c.ule.s
+; CHECK: movf
   %cmp = fcmp ogt float %f2, %f3
   %cond = select i1 %cmp, i32 %f0, i32 %f1
   ret i32 %cond
@@ -128,8 +128,8 @@
 
 define i32 @sel12(i32 %f0, i32 %f1) nounwind readonly {
 entry:
-; CHECK-MIPS32R2: c.eq.d
-; CHECK-MIPS32R2: movt
+; CHECK: c.eq.d
+; CHECK: movt
   %tmp = load double* @d2, align 8, !tbaa !0
   %tmp1 = load double* @d3, align 8, !tbaa !0
   %cmp = fcmp oeq double %tmp, %tmp1
@@ -139,8 +139,8 @@
 
 define i32 @sel13(i32 %f0, i32 %f1) nounwind readonly {
 entry:
-; CHECK-MIPS32R2: c.olt.d
-; CHECK-MIPS32R2: movt
+; CHECK: c.olt.d
+; CHECK: movt
   %tmp = load double* @d2, align 8, !tbaa !0
   %tmp1 = load double* @d3, align 8, !tbaa !0
   %cmp = fcmp olt double %tmp, %tmp1
@@ -150,8 +150,8 @@
 
 define i32 @sel14(i32 %f0, i32 %f1) nounwind readonly {
 entry:
-; CHECK-MIPS32R2: c.ule.d
-; CHECK-MIPS32R2: movf
+; CHECK: c.ule.d
+; CHECK: movf
   %tmp = load double* @d2, align 8, !tbaa !0
   %tmp1 = load double* @d3, align 8, !tbaa !0
   %cmp = fcmp ogt double %tmp, %tmp1



From grosbach at apple.com  Fri Sep  9 19:15:36 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Sat, 10 Sep 2011 00:15:36 -0000
Subject: [llvm-commits] [llvm] r139440 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20110910001536.3E2422A6C12C@llvm.org>

Author: grosbach
Date: Fri Sep  9 19:15:36 2011
New Revision: 139440

URL: http://llvm.org/viewvc/llvm-project?rev=139440&view=rev
Log:
Thumb2 parsing and encoding for MOV(immediate).

Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139440&r1=139439&r2=139440&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Sep  9 19:15:36 2011
@@ -1607,7 +1607,7 @@
 //
 
 let neverHasSideEffects = 1 in
-def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
+def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
                    "mov", ".w\t$Rd, $Rm", []> {
   let Inst{31-27} = 0b11101;
   let Inst{26-25} = 0b01;
@@ -1616,6 +1616,10 @@
   let Inst{14-12} = 0b000;
   let Inst{7-4} = 0b0000;
 }
+def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
+                                                 pred:$p, CPSR)>;
+def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
+                                               pred:$p, CPSR)>;
 
 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
@@ -1630,8 +1634,17 @@
   let Inst{15} = 0;
 }
 
-def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
-                                                   pred:$p, cc_out:$s)>;
+// cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
+// Use aliases to get that to play nice here.
+def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
+                                                pred:$p, CPSR)>;
+def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
+                                                pred:$p, CPSR)>;
+
+def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
+                                                 pred:$p, zero_reg)>;
+def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
+                                               pred:$p, zero_reg)>;
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=139440&r1=139439&r2=139440&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Sep  9 19:15:36 2011
@@ -3203,7 +3203,7 @@
        !isThumb()) ||
       ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
        !isThumb()) ||
-      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
+      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
     CanAcceptPredicationCode = false;
   } else {
     CanAcceptPredicationCode = true;
@@ -3765,6 +3765,47 @@
     }
     break;
   }
+  case ARM::t2MOVi: {
+    // If we can use the 16-bit encoding and the user didn't explicitly
+    // request the 32-bit variant, transform it here.
+    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
+        Inst.getOperand(1).getImm() <= 255 &&
+        Inst.getOperand(2).getImm() == ARMCC::AL &&
+        Inst.getOperand(4).getReg() == ARM::CPSR &&
+        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
+         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
+      // The operands aren't in the same order for tMOVi8...
+      MCInst TmpInst;
+      TmpInst.setOpcode(ARM::tMOVi8);
+      TmpInst.addOperand(Inst.getOperand(0));
+      TmpInst.addOperand(Inst.getOperand(4));
+      TmpInst.addOperand(Inst.getOperand(1));
+      TmpInst.addOperand(Inst.getOperand(2));
+      TmpInst.addOperand(Inst.getOperand(3));
+      Inst = TmpInst;
+    }
+    break;
+  }
+  case ARM::t2MOVr: {
+    // If we can use the 16-bit encoding and the user didn't explicitly
+    // request the 32-bit variant, transform it here.
+    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
+        isARMLowRegister(Inst.getOperand(1).getReg()) &&
+        Inst.getOperand(2).getImm() == ARMCC::AL &&
+        Inst.getOperand(4).getReg() == ARM::CPSR &&
+        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
+         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
+      // The operands aren't the same for tMOV[S]r... (no cc_out)
+      MCInst TmpInst;
+      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
+      TmpInst.addOperand(Inst.getOperand(0));
+      TmpInst.addOperand(Inst.getOperand(1));
+      TmpInst.addOperand(Inst.getOperand(2));
+      TmpInst.addOperand(Inst.getOperand(3));
+      Inst = TmpInst;
+    }
+    break;
+  }
   case ARM::t2IT: {
     // The mask bits for all but the first condition are represented as
     // the low bit of the condition code value implies 't'. We currently

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139440&r1=139439&r2=139440&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep  9 19:15:36 2011
@@ -989,6 +989,30 @@
 
 
 @------------------------------------------------------------------------------
+@ MOV(immediate)
+ at ------------------------------------------------------------------------------
+        movs r1, #21
+        movs.w r1, #21
+        movs r8, #21
+        movw r0, #65535
+        movw r1, #43777
+        movw r1, #43792
+        mov.w r0, #0x3fc0000
+        mov r0, #0x3fc0000
+        movs.w r0, #0x3fc0000
+
+@ CHECK: movs	r1, #21                 @ encoding: [0x15,0x21]
+@ CHECK: movs.w	r1, #21                 @ encoding: [0x5f,0xf0,0x15,0x01]
+@ CHECK: movs.w	r8, #21                 @ encoding: [0x5f,0xf0,0x15,0x08]
+@ CHECK: movw	r0, #65535              @ encoding: [0x4f,0xf6,0xff,0x70]
+@ CHECK: movw	r1, #43777              @ encoding: [0x4a,0xf6,0x01,0x31]
+@ CHECK: movw	r1, #43792              @ encoding: [0x4a,0xf6,0x10,0x31]
+@ CHECK: mov.w	r0, #66846720           @ encoding: [0x4f,0xf0,0x7f,0x70]
+@ CHECK: mov.w	r0, #66846720           @ encoding: [0x4f,0xf0,0x7f,0x70]
+@ CHECK: movs.w	r0, #66846720           @ encoding: [0x5f,0xf0,0x7f,0x70]
+
+
+ at ------------------------------------------------------------------------------
 @ IT
 @------------------------------------------------------------------------------
 @ Test encodings of a few full IT blocks, not just the IT instruction



From atrick at apple.com  Fri Sep  9 20:09:50 2011
From: atrick at apple.com (Andrew Trick)
Date: Sat, 10 Sep 2011 01:09:50 -0000
Subject: [llvm-commits] [llvm] r139450 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20110910010950.A09B82A6C12C@llvm.org>

Author: atrick
Date: Fri Sep  9 20:09:50 2011
New Revision: 139450

URL: http://llvm.org/viewvc/llvm-project?rev=139450&view=rev
Log:
Set NSW/NUW flags on SCEVAddExpr when the operation is flagged as
such.

I'm doing this now for completeness because I can't think of/remember
any reason that it was left out. I'm not sure it will help anything,
but if we don't do it we need to explain why in comments.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=139450&r1=139449&r2=139450&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Fri Sep  9 20:09:50 2011
@@ -3546,7 +3546,13 @@
         AddOps.push_back(Op1);
     }
     AddOps.push_back(getSCEV(U->getOperand(0)));
-    return getAddExpr(AddOps);
+    SCEV::NoWrapFlags Flags = SCEV::FlagAnyWrap;
+    OverflowingBinaryOperator *OBO = cast<OverflowingBinaryOperator>(V);
+    if (OBO->hasNoSignedWrap())
+      setFlags(Flags, SCEV::FlagNSW);
+    if (OBO->hasNoUnsignedWrap())
+      setFlags(Flags, SCEV::FlagNUW);
+    return getAddExpr(AddOps, Flags);
   }
   case Instruction::Mul: {
     // See the Add code above.



From atrick at apple.com  Fri Sep  9 20:24:17 2011
From: atrick at apple.com (Andrew Trick)
Date: Sat, 10 Sep 2011 01:24:17 -0000
Subject: [llvm-commits] [llvm] r139453 -
	/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
Message-ID: <20110910012417.46D032A6C12C@llvm.org>

Author: atrick
Date: Fri Sep  9 20:24:17 2011
New Revision: 139453

URL: http://llvm.org/viewvc/llvm-project?rev=139453&view=rev
Log:
[disable-iv-rewrite] Allow WidenIV to handle NSW/NUW operations
better.

Don't immediately give up when an add operation can't be trivially
sign/zero-extended within a loop. If it has NSW/NUW flags, generate a
new expression with sign extended (non-recurrent) operand. As before,
if SCEV says that all sign extends are loop invariant, then we can
widen the operation.

Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=139453&r1=139452&r2=139453&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Fri Sep  9 20:24:17 2011
@@ -858,6 +858,8 @@
 
   const SCEVAddRecExpr *GetWideRecurrence(Instruction *NarrowUse);
 
+  const SCEVAddRecExpr* GetExtendedOperandRecurrence(NarrowIVDefUse DU);
+
   Instruction *WidenIVUse(NarrowIVDefUse DU);
 
   void pushNarrowIVUsers(Instruction *NarrowDef, Instruction *WideDef);
@@ -951,6 +953,41 @@
   return true;
 }
 
+/// No-wrap operations can transfer sign extension of their result to their
+/// operands. Generate the SCEV value for the widened operation without
+/// actually modifying the IR yet. If the expression after extending the
+/// operands is an AddRec for this loop, return it.
+const SCEVAddRecExpr* WidenIV::GetExtendedOperandRecurrence(NarrowIVDefUse DU) {
+  // Handle the common case of add<nsw/nuw>
+  if (DU.NarrowUse->getOpcode() != Instruction::Add)
+    return 0;
+
+  // One operand (NarrowDef) has already been extended to WideDef. Now determine
+  // if extending the other will lead to a recurrence.
+  unsigned ExtendOperIdx = DU.NarrowUse->getOperand(0) == DU.NarrowDef ? 1 : 0;
+  assert(DU.NarrowUse->getOperand(1-ExtendOperIdx) == DU.NarrowDef && "bad DU");
+
+  const SCEV *ExtendOperExpr = 0;
+  const OverflowingBinaryOperator *OBO =
+    cast<OverflowingBinaryOperator>(DU.NarrowUse);
+  if (IsSigned && OBO->hasNoSignedWrap())
+    ExtendOperExpr = SE->getSignExtendExpr(
+      SE->getSCEV(DU.NarrowUse->getOperand(ExtendOperIdx)), WideType);
+  else if(!IsSigned && OBO->hasNoUnsignedWrap())
+    ExtendOperExpr = SE->getZeroExtendExpr(
+      SE->getSCEV(DU.NarrowUse->getOperand(ExtendOperIdx)), WideType);
+  else
+    return 0;
+
+  const SCEVAddRecExpr *AddRec = dyn_cast<SCEVAddRecExpr>(
+    SE->getAddExpr(SE->getSCEV(DU.WideDef), ExtendOperExpr,
+                   IsSigned ? SCEV::FlagNSW : SCEV::FlagNUW));
+
+  if (!AddRec || AddRec->getLoop() != L)
+    return 0;
+  return AddRec;
+}
+
 /// GetWideRecurrence - Is this instruction potentially interesting from
 /// IVUsers' perspective after widening it's type? In other words, can the
 /// extend be safely hoisted out of the loop with SCEV reducing the value to a
@@ -974,7 +1011,6 @@
   const SCEVAddRecExpr *AddRec = dyn_cast<SCEVAddRecExpr>(WideExpr);
   if (!AddRec || AddRec->getLoop() != L)
     return 0;
-
   return AddRec;
 }
 
@@ -1028,6 +1064,9 @@
   // Does this user itself evaluate to a recurrence after widening?
   const SCEVAddRecExpr *WideAddRec = GetWideRecurrence(DU.NarrowUse);
   if (!WideAddRec) {
+      WideAddRec = GetExtendedOperandRecurrence(DU);
+  }
+  if (!WideAddRec) {
     // This user does not evaluate to a recurence after widening, so don't
     // follow it. Instead insert a Trunc to kill off the original use,
     // eventually isolating the original narrow IV so it can be removed.



From eli.friedman at gmail.com  Fri Sep  9 21:01:42 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Sat, 10 Sep 2011 02:01:42 -0000
Subject: [llvm-commits] [llvm] r139458 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20110910020142.AB0B92A6C12C@llvm.org>

Author: efriedma
Date: Fri Sep  9 21:01:42 2011
New Revision: 139458

URL: http://llvm.org/viewvc/llvm-project?rev=139458&view=rev
Log:
r139454 activates an assert in a case where we were doing the right thing anyway.  Make that explicit, and un-XFAIL the testcase.


Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139458&r1=139457&r2=139458&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep  9 21:01:42 2011
@@ -4615,8 +4615,16 @@
       DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
                            ShuffleMask);
       break;
+    case X86ISD::MOVDDUP:
+    case X86ISD::MOVLHPD:
+    case X86ISD::MOVLPD:
+    case X86ISD::MOVLPS:
+    case X86ISD::MOVSHDUP:
+    case X86ISD::MOVSLDUP:
+    case X86ISD::PALIGN:
+      return SDValue(); // Not yet implemented.
     default:
-      assert(0 && "not implemented for target shuffle node");
+      assert(0 && "unknown target shuffle node");
       return SDValue();
     }
 



From eli.friedman at gmail.com  Fri Sep  9 21:02:27 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Sat, 10 Sep 2011 02:02:27 -0000
Subject: [llvm-commits] [llvm] r139459 -
	/llvm/trunk/test/CodeGen/X86/palignr.ll
Message-ID: <20110910020227.DFABB2A6C12C@llvm.org>

Author: efriedma
Date: Fri Sep  9 21:02:27 2011
New Revision: 139459

URL: http://llvm.org/viewvc/llvm-project?rev=139459&view=rev
Log:
Really un-XFAIL the testcase, like I said I would in r139458.


Modified:
    llvm/trunk/test/CodeGen/X86/palignr.ll

Modified: llvm/trunk/test/CodeGen/X86/palignr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/palignr.ll?rev=139459&r1=139458&r2=139459&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/palignr.ll (original)
+++ llvm/trunk/test/CodeGen/X86/palignr.ll Fri Sep  9 21:02:27 2011
@@ -1,6 +1,5 @@
 ; RUN: llc < %s -march=x86 -mcpu=core2 -mattr=+ssse3 | FileCheck %s
 ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck --check-prefix=YONAH %s
-; XFAIL: *
 
 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
 ; CHECK: test1:



From rtrieu at google.com  Fri Sep  9 20:07:54 2011
From: rtrieu at google.com (Richard Trieu)
Date: Sat, 10 Sep 2011 01:07:54 -0000
Subject: [llvm-commits] [llvm] r139449 - in /llvm/trunk/lib/CodeGen:
 ELFCodeEmitter.cpp ELFCodeEmitter.h
Message-ID: <20110910010754.A7F912A6C12C@llvm.org>

Author: rtrieu
Date: Fri Sep  9 20:07:54 2011
New Revision: 139449

URL: http://llvm.org/viewvc/llvm-project?rev=139449&view=rev
Log:
Fix asserts in CodeGen from:

  assert("error");

to:

  assert(0 && "error");


Modified:
    llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp
    llvm/trunk/lib/CodeGen/ELFCodeEmitter.h

Modified: llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp?rev=139449&r1=139448&r2=139449&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp Fri Sep  9 20:07:54 2011
@@ -155,7 +155,7 @@
     CPSections.push_back(CstPool.SectionIdx);
 
     if (CPE.isMachineConstantPoolEntry())
-      assert("CPE.isMachineConstantPoolEntry not supported yet");
+      assert(0 && "CPE.isMachineConstantPoolEntry not supported yet");
 
     // Emit the constant to constant pool section
     EW.EmitGlobalConstant(CPE.Val.ConstVal, CstPool);

Modified: llvm/trunk/lib/CodeGen/ELFCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFCodeEmitter.h?rev=139449&r1=139448&r2=139449&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ELFCodeEmitter.h (original)
+++ llvm/trunk/lib/CodeGen/ELFCodeEmitter.h Fri Sep  9 20:07:54 2011
@@ -58,13 +58,13 @@
 
     /// emitLabel - Emits a label
     virtual void emitLabel(MCSymbol *Label) {
-      assert("emitLabel not implemented");
+      assert(0 && "emitLabel not implemented");
     }
 
     /// getLabelAddress - Return the address of the specified LabelID, 
     /// only usable after the LabelID has been emitted.
     virtual uintptr_t getLabelAddress(MCSymbol *Label) const {
-      assert("getLabelAddress not implemented");
+      assert(0 && "getLabelAddress not implemented");
       return 0;
     }
 



From rtrieu at google.com  Fri Sep  9 20:26:21 2011
From: rtrieu at google.com (Richard Trieu)
Date: Sat, 10 Sep 2011 01:26:21 -0000
Subject: [llvm-commits] [llvm] r139454 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/palignr.ll
Message-ID: <20110910012622.00A132A6C12C@llvm.org>

Author: rtrieu
Date: Fri Sep  9 20:26:21 2011
New Revision: 139454

URL: http://llvm.org/viewvc/llvm-project?rev=139454&view=rev
Log:
Fixed an assert from:

  assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.


Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/palignr.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139454&r1=139453&r2=139454&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep  9 20:26:21 2011
@@ -4616,7 +4616,7 @@
                            ShuffleMask);
       break;
     default:
-      assert("not implemented for target shuffle node");
+      assert(0 && "not implemented for target shuffle node");
       return SDValue();
     }
 

Modified: llvm/trunk/test/CodeGen/X86/palignr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/palignr.ll?rev=139454&r1=139453&r2=139454&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/palignr.ll (original)
+++ llvm/trunk/test/CodeGen/X86/palignr.ll Fri Sep  9 20:26:21 2011
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -march=x86 -mcpu=core2 -mattr=+ssse3 | FileCheck %s
 ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck --check-prefix=YONAH %s
+; XFAIL: *
 
 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
 ; CHECK: test1:



From rtrieu at google.com  Fri Sep  9 20:42:07 2011
From: rtrieu at google.com (Richard Trieu)
Date: Sat, 10 Sep 2011 01:42:07 -0000
Subject: [llvm-commits] [llvm] r139456 - in /llvm/trunk/lib:
 ExecutionEngine/MCJIT/MCJIT.cpp Target/X86/X86ELFWriterInfo.cpp
Message-ID: <20110910014207.414B22A6C12C@llvm.org>

Author: rtrieu
Date: Fri Sep  9 20:42:07 2011
New Revision: 139456

URL: http://llvm.org/viewvc/llvm-project?rev=139456&view=rev
Log:
Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp and
lib/ExecutionEngine/MCJIT/MCJIT.cpp from:

  assert("error");

to:

  assert(0 && "error");


Modified:
    llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp
    llvm/trunk/lib/Target/X86/X86ELFWriterInfo.cpp

Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp?rev=139456&r1=139455&r2=139456&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Fri Sep  9 20:42:07 2011
@@ -216,6 +216,6 @@
     }
   }
 
-  assert("Full-featured argument passing not supported yet!");
+  assert(0 && "Full-featured argument passing not supported yet!");
   return GenericValue();
 }

Modified: llvm/trunk/lib/Target/X86/X86ELFWriterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ELFWriterInfo.cpp?rev=139456&r1=139455&r2=139456&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ELFWriterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ELFWriterInfo.cpp Fri Sep  9 20:42:07 2011
@@ -147,7 +147,7 @@
   if (RelTy == ELF::R_X86_64_PC32 || RelTy == ELF::R_386_PC32)
     return SymOffset - (RelOffset + 4);
   else
-    assert("computeRelocation unknown for this relocation type");
+    assert(0 && "computeRelocation unknown for this relocation type");
 
   return 0;
 }



From James.Molloy at arm.com  Sat Sep 10 03:27:11 2011
From: James.Molloy at arm.com (James Molloy)
Date: Sat, 10 Sep 2011 09:27:11 +0100
Subject: [llvm-commits] [llvm] r139407 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
In-Reply-To: <20110909210407.1C2DB2A6C12C@llvm.org>
References: <20110909210407.1C2DB2A6C12C@llvm.org>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA473757133E4@GEORGE.Emea.Arm.com>

Hi Eli,

This makes sense, thanks. A related question though, and please excuse my ignorance because the documentation of SelectionDAG is incomplete at best - under what situations could the DAGCombiner run before the DAGTypeLegalizer? My stepping with GDB found the opposite.

Or is it certain combinations of optimization passes?

Cheers,

James
________________________________________
From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Eli Friedman [eli.friedman at gmail.com]
Sent: 09 September 2011 22:04
To: llvm-commits at cs.uiuc.edu
Subject: [llvm-commits] [llvm] r139407 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll

Author: efriedma
Date: Fri Sep  9 16:04:06 2011
New Revision: 139407

URL: http://llvm.org/viewvc/llvm-project?rev=139407&view=rev
Log:
Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type.  Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs.  Fixes PR10897.


Added:
    llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=139407&r1=139406&r2=139407&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Sep  9 16:04:06 2011
@@ -6770,6 +6770,7 @@
   SDValue InVec = N->getOperand(0);
   SDValue InVal = N->getOperand(1);
   SDValue EltNo = N->getOperand(2);
+  DebugLoc dl = N->getDebugLoc();

   // If the inserted element is an UNDEF, just use the input vector.
   if (InVal.getOpcode() == ISD::UNDEF)
@@ -6781,32 +6782,40 @@
   if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
     return SDValue();

-  // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
-  // vector with the inserted element.
-  if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
-    unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
-    SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
-                                InVec.getNode()->op_end());
-    if (Elt < Ops.size())
-      Ops[Elt] = InVal;
-    return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
-                       VT, &Ops[0], Ops.size());
-  }
-  // If the invec is an UNDEF and if EltNo is a constant, create a new
-  // BUILD_VECTOR with undef elements and the inserted element.
-  if (InVec.getOpcode() == ISD::UNDEF &&
-      isa<ConstantSDNode>(EltNo)) {
-    EVT EltVT = VT.getVectorElementType();
+  // Check that we know which element is being inserted
+  if (!isa<ConstantSDNode>(EltNo))
+    return SDValue();
+  unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
+
+  // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
+  // be converted to a BUILD_VECTOR).  Fill in the Ops vector with the
+  // vector elements.
+  SmallVector<SDValue, 8> Ops;
+  if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
+    Ops.append(InVec.getNode()->op_begin(),
+               InVec.getNode()->op_end());
+  } else if (InVec.getOpcode() == ISD::UNDEF) {
     unsigned NElts = VT.getVectorNumElements();
-    SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
+    Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
+  } else {
+    return SDValue();
+  }

-    unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
-    if (Elt < Ops.size())
-      Ops[Elt] = InVal;
-    return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
-                       VT, &Ops[0], Ops.size());
+  // Insert the element
+  if (Elt < Ops.size()) {
+    // All the operands of BUILD_VECTOR must have the same type;
+    // we enforce that here.
+    EVT OpVT = Ops[0].getValueType();
+    if (InVal.getValueType() != OpVT)
+      InVal = OpVT.bitsGT(InVal.getValueType()) ?
+                DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
+                DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
+    Ops[Elt] = InVal;
   }
-  return SDValue();
+
+  // Return the new vector
+  return DAG.getNode(ISD::BUILD_VECTOR, dl,
+                     VT, &Ops[0], Ops.size());
 }

 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=139407&r1=139406&r2=139407&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Sep  9 16:04:06 2011
@@ -771,11 +771,14 @@
     assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
            "Wrong number of operands!");
     EVT EltVT = N->getValueType(0).getVectorElementType();
-    for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
+    for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) {
       assert((I->getValueType() == EltVT ||
              (EltVT.isInteger() && I->getValueType().isInteger() &&
               EltVT.bitsLE(I->getValueType()))) &&
             "Wrong operand type!");
+      assert(I->getValueType() == N->getOperand(0).getValueType() &&
+             "Operands must all have the same type");
+    }
     break;
   }
   }

Added: llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll?rev=139407&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll Fri Sep  9 16:04:06 2011
@@ -0,0 +1,23 @@
+; RUN: llc -mtriple=armv7-- %s -mattr=-neon
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32"
+target triple = "armv7-none-linux-gnueabi"
+
+ at x1 = common global <3 x i16> zeroinitializer
+ at y1 = common global <3 x i16> zeroinitializer
+ at z1 = common global <3 x i16> zeroinitializer
+ at x2 = common global <4 x i16> zeroinitializer
+ at y2 = common global <4 x i16> zeroinitializer
+ at z2 = common global <4 x i16> zeroinitializer
+
+define void @f() {
+  %1 = load <3 x i16>* @x1
+  %2 = load <3 x i16>* @y1
+  %3 = sdiv <3 x i16> %1, %2
+  store <3 x i16> %3, <3 x i16>* @z1
+  %4 = load <4 x i16>* @x2
+  %5 = load <4 x i16>* @y2
+  %6 = sdiv <4 x i16> %4, %5
+  store <4 x i16> %6, <4 x i16>* @z2
+  ret void
+}


_______________________________________________
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llvm-commits at cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


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From eli.friedman at gmail.com  Sat Sep 10 05:46:59 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Sat, 10 Sep 2011 03:46:59 -0700
Subject: [llvm-commits] [llvm] r139407 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
In-Reply-To: <F01D8B85CFF58440B2A13965FBA90CA473757133E4@GEORGE.Emea.Arm.com>
References: <20110909210407.1C2DB2A6C12C@llvm.org>
	<F01D8B85CFF58440B2A13965FBA90CA473757133E4@GEORGE.Emea.Arm.com>
Message-ID: <CAJdarcGBXwS3=QFMSzhniiDhTCzkC6gTZ_eViA3SvG2AaGawsg@mail.gmail.com>

On Sat, Sep 10, 2011 at 1:27 AM, James Molloy <James.Molloy at arm.com> wrote:
> Hi Eli,
>
> This makes sense, thanks. A related question though, and please excuse my ignorance because the documentation of SelectionDAG is incomplete at best - under what situations could the DAGCombiner run before the DAGTypeLegalizer? My stepping with GDB found the opposite.

The DAGCombiner always runs before the type legalizer... and after the
type legalizer... and after the type legalizer runs again... see
SelectionDAGISel::CodeGenAndEmitDAG().

-Eli


From James.Molloy at arm.com  Sat Sep 10 05:57:54 2011
From: James.Molloy at arm.com (James Molloy)
Date: Sat, 10 Sep 2011 11:57:54 +0100
Subject: [llvm-commits] [llvm] r139407 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
In-Reply-To: <CAJdarcGBXwS3=QFMSzhniiDhTCzkC6gTZ_eViA3SvG2AaGawsg@mail.gmail.com>
References: <20110909210407.1C2DB2A6C12C@llvm.org>
	<F01D8B85CFF58440B2A13965FBA90CA473757133E4@GEORGE.Emea.Arm.com>,
	<CAJdarcGBXwS3=QFMSzhniiDhTCzkC6gTZ_eViA3SvG2AaGawsg@mail.gmail.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA473757133E6@GEORGE.Emea.Arm.com>

So wouldn't a better solution be to make the TypeLegalizer actually legalize the types of BUILD_VECTOR?

>From LegalizeVectorOps.cpp:

// This does not legalize vector manipulations like ISD::BUILD_VECTOR,
// or operations that happen to take a vector which are custom-lowered;
// the legalization for such operations never produces nodes
// with illegal types, so it's okay to put off legalizing them until
// SelectionDAG::Legalize runs.

It seems to me that this statement is false - BUILD_VECTOR can contain illegal types after DAGCombine, so it is *not* safe to put off legalizing them.

Unless the legalization should be done in SelectionDAG::Legalize...?:

  case ISD::BUILD_VECTOR:
    // A weird case: legalization for BUILD_VECTOR never legalizes the
    // operands!
    // FIXME: This really sucks... changing it isn't semantically incorrect,
    // but it massively pessimizes the code for floating-point BUILD_VECTORs
    // because ConstantFP operands get legalized into constant pool loads
    // before the BUILD_VECTOR code can see them.  It doesn't usually bite,
    // though, because BUILD_VECTORS usually get lowered into other nodes
    // which get legalized properly.
    SimpleFinishLegalizing = false;
    break;

It seems to me that there is code elsewhere outside of the DAGCombiner that is not sticking to its pre or postconditions, so fixing the DAGCombiner to produce legal types isn't the best solution. I had originally thought that the type legalization was only done before DAGCombine, which is why I proposed my original solution (which was similar to yours).

Am I missing something here? There could be other places in the DAGCombiner that produces illegal types that aren't legalized that we haven't caught yet...

Cheers,

James


________________________________________
From: Eli Friedman [eli.friedman at gmail.com]
Sent: 10 September 2011 11:46
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [llvm] r139407 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll

On Sat, Sep 10, 2011 at 1:27 AM, James Molloy <James.Molloy at arm.com> wrote:
> Hi Eli,
>
> This makes sense, thanks. A related question though, and please excuse my ignorance because the documentation of SelectionDAG is incomplete at best - under what situations could the DAGCombiner run before the DAGTypeLegalizer? My stepping with GDB found the opposite.

The DAGCombiner always runs before the type legalizer... and after the
type legalizer... and after the type legalizer runs again... see
SelectionDAGISel::CodeGenAndEmitDAG().

-Eli


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.



From baldrick at free.fr  Sat Sep 10 06:38:21 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sat, 10 Sep 2011 13:38:21 +0200
Subject: [llvm-commits] [llvm] r139400 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/X86/avx-blend.ll
In-Reply-To: <20110909202917.AC4092A6C12C@llvm.org>
References: <20110909202917.AC4092A6C12C@llvm.org>
Message-ID: <4E6B4C2D.7080600@free.fr>

Hi Nadav,

> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep  9 15:29:17 2011
> @@ -1019,6 +1019,11 @@
>       setOperationAction(ISD::SELECT,            MVT::v4i64, Custom);
>       setOperationAction(ISD::SELECT,            MVT::v8f32, Custom);
>
> +    setOperationAction(ISD::VSELECT,            MVT::v4f64, Custom);
> +    setOperationAction(ISD::VSELECT,            MVT::v4i64, Custom);
> +    setOperationAction(ISD::VSELECT,            MVT::v8i32, Custom);
> +    setOperationAction(ISD::VSELECT,            MVT::v8f32, Custom);
> +
>       setOperationAction(ISD::ADD,               MVT::v4i64, Custom);
>       setOperationAction(ISD::ADD,               MVT::v8i32, Custom);
>       setOperationAction(ISD::ADD,               MVT::v16i16, Custom);

I don't see why you need to custom lower them at all.  My understanding is that
custom lowering is for the case when the node (VSELECT) does *not* directly
correspond to a processor instruction.  If it does directly correspond, like
here, then you can do everything via tablegen.  Hopefully Bruno can explain how
this is done, because I don't know.

Ciao, Duncan.

From baldrick at free.fr  Sat Sep 10 06:43:43 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sat, 10 Sep 2011 13:43:43 +0200
Subject: [llvm-commits] [llvm] r139407 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
In-Reply-To: <F01D8B85CFF58440B2A13965FBA90CA473757133E6@GEORGE.Emea.Arm.com>
References: <20110909210407.1C2DB2A6C12C@llvm.org>
	<F01D8B85CFF58440B2A13965FBA90CA473757133E4@GEORGE.Emea.Arm.com>,
	<CAJdarcGBXwS3=QFMSzhniiDhTCzkC6gTZ_eViA3SvG2AaGawsg@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA473757133E6@GEORGE.Emea.Arm.com>
Message-ID: <4E6B4D6F.7080102@free.fr>

Hi James,

> So wouldn't a better solution be to make the TypeLegalizer actually legalize the types of BUILD_VECTOR?

it does.  LegalizeVectorOps is not part of the type legalizer.

Ciao, Duncan.

>
>> From LegalizeVectorOps.cpp:
>
> // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
> // or operations that happen to take a vector which are custom-lowered;
> // the legalization for such operations never produces nodes
> // with illegal types, so it's okay to put off legalizing them until
> // SelectionDAG::Legalize runs.
>
> It seems to me that this statement is false - BUILD_VECTOR can contain illegal types after DAGCombine, so it is *not* safe to put off legalizing them.
>
> Unless the legalization should be done in SelectionDAG::Legalize...?:
>
>    case ISD::BUILD_VECTOR:
>      // A weird case: legalization for BUILD_VECTOR never legalizes the
>      // operands!
>      // FIXME: This really sucks... changing it isn't semantically incorrect,
>      // but it massively pessimizes the code for floating-point BUILD_VECTORs
>      // because ConstantFP operands get legalized into constant pool loads
>      // before the BUILD_VECTOR code can see them.  It doesn't usually bite,
>      // though, because BUILD_VECTORS usually get lowered into other nodes
>      // which get legalized properly.
>      SimpleFinishLegalizing = false;
>      break;
>
> It seems to me that there is code elsewhere outside of the DAGCombiner that is not sticking to its pre or postconditions, so fixing the DAGCombiner to produce legal types isn't the best solution. I had originally thought that the type legalization was only done before DAGCombine, which is why I proposed my original solution (which was similar to yours).
>
> Am I missing something here? There could be other places in the DAGCombiner that produces illegal types that aren't legalized that we haven't caught yet...
>
> Cheers,
>
> James
>
>
> ________________________________________
> From: Eli Friedman [eli.friedman at gmail.com]
> Sent: 10 September 2011 11:46
> To: James Molloy
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [llvm] r139407 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
>
> On Sat, Sep 10, 2011 at 1:27 AM, James Molloy<James.Molloy at arm.com>  wrote:
>> Hi Eli,
>>
>> This makes sense, thanks. A related question though, and please excuse my ignorance because the documentation of SelectionDAG is incomplete at best - under what situations could the DAGCombiner run before the DAGTypeLegalizer? My stepping with GDB found the opposite.
>
> The DAGCombiner always runs before the type legalizer... and after the
> type legalizer... and after the type legalizer runs again... see
> SelectionDAGISel::CodeGenAndEmitDAG().
>
> -Eli
>
>
> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From James.Molloy at arm.com  Sat Sep 10 08:46:03 2011
From: James.Molloy at arm.com (James Molloy)
Date: Sat, 10 Sep 2011 14:46:03 +0100
Subject: [llvm-commits] [llvm] r139407 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
In-Reply-To: <4E6B4D6F.7080102@free.fr>
References: <20110909210407.1C2DB2A6C12C@llvm.org>
	<F01D8B85CFF58440B2A13965FBA90CA473757133E4@GEORGE.Emea.Arm.com>,
	<CAJdarcGBXwS3=QFMSzhniiDhTCzkC6gTZ_eViA3SvG2AaGawsg@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA473757133E6@GEORGE.Emea.Arm.com>,
	<4E6B4D6F.7080102@free.fr>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA473757133E8@GEORGE.Emea.Arm.com>

Hi Duncan (& Eli),

Please bear with me, because I'm trying to unravel and learn the design of SelectionDAG at the same time as querying this fix.

If I've read the code right, the sequence goes something like:

1) Run DAGCombine in unrestricted mode.
2) Run LegalizeTypes(): postcondition: "[the DAG] only uses operations and types that the target supports".
3) If LegalizeTypes() changed the DAG, run DAGCombine in strictly-legal mode again.
4) Run LegalizeVectors(); if this changed the DAG, run LegalizeTypes then DAGCombine again, again in strict mode.
5) Legalize()
6) DAGCombine again, strict mode.

So by my understanding, before Eli's patch, DAGCombine emitted a DAG containing an illegal type as an operand of a BUILD_VECTOR.
LegalizeTypes() did not legalize that operand (by design or fault), so the output of LegalizeTypes() is illegal and seemingly does not adhere to its postcondition in SelectionDAGIsel.cpp.

I see the problem as in LegalizeTypes(), not in DAGCombine. What am I missing here? (apart from a good knowledge of the target independent codegen!)

Cheers for any help,

James
________________________________________
From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands [baldrick at free.fr]
Sent: 10 September 2011 12:43
To: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [llvm] r139407 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll

Hi James,

> So wouldn't a better solution be to make the TypeLegalizer actually legalize the types of BUILD_VECTOR?

it does.  LegalizeVectorOps is not part of the type legalizer.

Ciao, Duncan.

>
>> From LegalizeVectorOps.cpp:
>
> // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
> // or operations that happen to take a vector which are custom-lowered;
> // the legalization for such operations never produces nodes
> // with illegal types, so it's okay to put off legalizing them until
> // SelectionDAG::Legalize runs.
>
> It seems to me that this statement is false - BUILD_VECTOR can contain illegal types after DAGCombine, so it is *not* safe to put off legalizing them.
>
> Unless the legalization should be done in SelectionDAG::Legalize...?:
>
>    case ISD::BUILD_VECTOR:
>      // A weird case: legalization for BUILD_VECTOR never legalizes the
>      // operands!
>      // FIXME: This really sucks... changing it isn't semantically incorrect,
>      // but it massively pessimizes the code for floating-point BUILD_VECTORs
>      // because ConstantFP operands get legalized into constant pool loads
>      // before the BUILD_VECTOR code can see them.  It doesn't usually bite,
>      // though, because BUILD_VECTORS usually get lowered into other nodes
>      // which get legalized properly.
>      SimpleFinishLegalizing = false;
>      break;
>
> It seems to me that there is code elsewhere outside of the DAGCombiner that is not sticking to its pre or postconditions, so fixing the DAGCombiner to produce legal types isn't the best solution. I had originally thought that the type legalization was only done before DAGCombine, which is why I proposed my original solution (which was similar to yours).
>
> Am I missing something here? There could be other places in the DAGCombiner that produces illegal types that aren't legalized that we haven't caught yet...
>
> Cheers,
>
> James
>
>
> ________________________________________
> From: Eli Friedman [eli.friedman at gmail.com]
> Sent: 10 September 2011 11:46
> To: James Molloy
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [llvm] r139407 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll
>
> On Sat, Sep 10, 2011 at 1:27 AM, James Molloy<James.Molloy at arm.com>  wrote:
>> Hi Eli,
>>
>> This makes sense, thanks. A related question though, and please excuse my ignorance because the documentation of SelectionDAG is incomplete at best - under what situations could the DAGCombiner run before the DAGTypeLegalizer? My stepping with GDB found the opposite.
>
> The DAGCombiner always runs before the type legalizer... and after the
> type legalizer... and after the type legalizer runs again... see
> SelectionDAGISel::CodeGenAndEmitDAG().
>
> -Eli
>
>
> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

_______________________________________________
llvm-commits mailing list
llvm-commits at cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.



From bruno.cardoso at gmail.com  Sat Sep 10 12:56:39 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Sat, 10 Sep 2011 10:56:39 -0700
Subject: [llvm-commits] [llvm] r139400 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/X86/avx-blend.ll
In-Reply-To: <4E6B4C2D.7080600@free.fr>
References: <20110909202917.AC4092A6C12C@llvm.org> <4E6B4C2D.7080600@free.fr>
Message-ID: <CACk9FxanZxh_e8gBEJzMEKTDJT7vVhDkhpboQD_4T=C4qwz4sg@mail.gmail.com>

> I don't see why you need to custom lower them at all.  My understanding is
that
> custom lowering is for the case when the node (VSELECT) does *not*
directly
> correspond to a processor instruction.  If it does directly correspond,
like
> here, then you can do everything via tablegen.  Hopefully Bruno can
explain how
> this is done, because I don't know.

I totally agree with you Duncan. This should be straightforward to represent
in the .td files, can you do it Nadav?

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc
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From undingen at gmail.com  Sat Sep 10 17:14:28 2011
From: undingen at gmail.com (Marius Wachtler)
Date: Sun, 11 Sep 2011 00:14:28 +0200
Subject: [llvm-commits] [llvm] r139263 -
	/llvm/trunk/lib/Target/README.txt
In-Reply-To: <4E6A21A7.8030704@free.fr>
References: <20110907224926.A9B8C2A6C12C@llvm.org> <4E686F34.3010200@free.fr>
	<CANycJ-BANEfDD3Ci7MEN=9S_CxicqRVjyrh+WTb_QjN0UQ-QUQ@mail.gmail.com>
	<CAL3drCrbFXnXuccckjL=onB8qZa_+SDsarKDix0Kx2qsiTx7BA@mail.gmail.com>
	<4E6A21A7.8030704@free.fr>
Message-ID: <CANycJ-A5TrmXbMy5kNS6D-1vmHZ4y9zPFCWv3XSsSL9VUuQ-qQ@mail.gmail.com>

Hello

I have now implemented it more general, in the style of the InstComp
select optimization.
Attached you can find my patch, but its not very nice and I have not
measured how bad this influences compile time, or if it brakes
anything.

I like Duncans idea, maybe I will try to implement it next.

Thanks
Marius Wachtler
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From nadav.rotem at intel.com  Sun Sep 11 10:02:23 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Sun, 11 Sep 2011 15:02:23 -0000
Subject: [llvm-commits] [llvm] r139479 - in /llvm/trunk:
 include/llvm/Target/TargetSelectionDAG.td
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrSSE.td
Message-ID: <20110911150223.F09E12A6C12D@llvm.org>

Author: nadav
Date: Sun Sep 11 10:02:23 2011
New Revision: 139479

URL: http://llvm.org/viewvc/llvm-project?rev=139479&view=rev
Log:
CR fixes per Bruno's request.

Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.


Modified:
    llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=139479&r1=139478&r2=139479&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Sun Sep 11 10:02:23 2011
@@ -149,6 +149,10 @@
   SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
 ]>;
 
+def SDTVSelect : SDTypeProfile<1, 3, [       // vselect
+  SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
+]>;
+
 def SDTSelectCC : SDTypeProfile<1, 5, [     // select_cc
   SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
   SDTCisVT<5, OtherVT>
@@ -390,8 +394,8 @@
 
 def setcc      : SDNode<"ISD::SETCC"      , SDTSetCC>;
 def select     : SDNode<"ISD::SELECT"     , SDTSelect>;
+def vselect    : SDNode<"ISD::VSELECT"    , SDTVSelect>;
 def selectcc   : SDNode<"ISD::SELECT_CC"  , SDTSelectCC>;
-def vsetcc     : SDNode<"ISD::VSETCC"     , SDTSetCC>;
 
 def brcond     : SDNode<"ISD::BRCOND"     , SDTBrcond, [SDNPHasChain]>;
 def brind      : SDNode<"ISD::BRIND"      , SDTBrind,  [SDNPHasChain]>;

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139479&r1=139478&r2=139479&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Sep 11 10:02:23 2011
@@ -917,11 +917,11 @@
     setOperationAction(ISD::SHL,                MVT::v4i32, Custom);
     setOperationAction(ISD::SHL,                MVT::v16i8, Custom);
 
-    setOperationAction(ISD::VSELECT,            MVT::v2f64, Custom);
-    setOperationAction(ISD::VSELECT,            MVT::v2i64, Custom);
-    setOperationAction(ISD::VSELECT,            MVT::v16i8, Custom);
-    setOperationAction(ISD::VSELECT,            MVT::v4i32, Custom);
-    setOperationAction(ISD::VSELECT,            MVT::v4f32, Custom);
+    setOperationAction(ISD::VSELECT,            MVT::v2f64, Legal);
+    setOperationAction(ISD::VSELECT,            MVT::v2i64, Legal);
+    setOperationAction(ISD::VSELECT,            MVT::v16i8, Legal);
+    setOperationAction(ISD::VSELECT,            MVT::v4i32, Legal);
+    setOperationAction(ISD::VSELECT,            MVT::v4f32, Legal);
 
     // i8 and i16 vectors are custom , because the source register and source
     // source memory operand types are not the same width.  f32 vectors are
@@ -1019,10 +1019,10 @@
     setOperationAction(ISD::SELECT,            MVT::v4i64, Custom);
     setOperationAction(ISD::SELECT,            MVT::v8f32, Custom);
 
-    setOperationAction(ISD::VSELECT,            MVT::v4f64, Custom);
-    setOperationAction(ISD::VSELECT,            MVT::v4i64, Custom);
-    setOperationAction(ISD::VSELECT,            MVT::v8i32, Custom);
-    setOperationAction(ISD::VSELECT,            MVT::v8f32, Custom);
+    setOperationAction(ISD::VSELECT,            MVT::v4f64, Legal);
+    setOperationAction(ISD::VSELECT,            MVT::v4i64, Legal);
+    setOperationAction(ISD::VSELECT,            MVT::v8i32, Legal);
+    setOperationAction(ISD::VSELECT,            MVT::v8f32, Legal);
 
     setOperationAction(ISD::ADD,               MVT::v4i64, Custom);
     setOperationAction(ISD::ADD,               MVT::v8i32, Custom);
@@ -8703,43 +8703,6 @@
   return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
 }
 
-SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
-  SDValue Cond  = Op.getOperand(0);
-  SDValue Op1 = Op.getOperand(1);
-  SDValue Op2 = Op.getOperand(2);
-  DebugLoc DL = Op.getDebugLoc();
-
-  SDValue Ops[] = {Op1, Op2, Cond};
-
-  assert(Op1.getValueType().isVector() && "Op1 must be a vector");
-  assert(Op2.getValueType().isVector() && "Op2 must be a vector");
-  assert(Cond.getValueType().isVector() && "Cond must be a vector");
-  assert(Op1.getValueType() == Op2.getValueType() && "Type mismatch");
-
-  EVT VT = Op1.getValueType();
-  switch (VT.getSimpleVT().SimpleTy) {
-    default: break;
-    // SSE4:
-    case MVT::v2i64:
-    case MVT::v2f64:
-    case MVT::v4i32:
-    case MVT::v4f32:
-    case MVT::v16i8:
-    case MVT::v8i16:
-    // AVX:
-    case MVT::v4i64:
-    case MVT::v4f64:
-    case MVT::v8i32:
-    case MVT::v8f32:
-    case MVT::v32i8:
-    case MVT::v16i16:
-      return DAG.getNode(X86ISD::BLENDV, DL, VT, Ops, array_lengthof(Ops));
-  }
-
-  return SDValue();
-}
-
-
 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
 // from the AND / OR.
@@ -9993,7 +9956,7 @@
     M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
                     DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
                     DAG.getConstant(4, MVT::i32));
-    R = DAG.getNode(X86ISD::BLENDV, dl, VT, R, M, Op);
+    R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
     // a += a
     Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
 
@@ -10008,13 +9971,13 @@
     M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
                     DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
                     DAG.getConstant(2, MVT::i32));
-    R = DAG.getNode(X86ISD::BLENDV, dl, VT, R, M, Op);
+    R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
     // a += a
     Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
 
     // return pblendv(r, r+r, a);
-    R = DAG.getNode(X86ISD::BLENDV, dl, VT,
-                    R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
+    R = DAG.getNode(ISD::VSELECT, dl, VT, Op,
+                    R, DAG.getNode(ISD::ADD, dl, VT, R, R));
     return R;
   }
   return SDValue();
@@ -10406,7 +10369,6 @@
   case ISD::FGETSIGN:           return LowerFGETSIGN(Op, DAG);
   case ISD::SETCC:              return LowerSETCC(Op, DAG);
   case ISD::SELECT:             return LowerSELECT(Op, DAG);
-  case ISD::VSELECT:            return LowerVSELECT(Op, DAG);
   case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
   case ISD::VASTART:            return LowerVASTART(Op, DAG);
@@ -10651,7 +10613,6 @@
   case X86ISD::PSIGNB:             return "X86ISD::PSIGNB";
   case X86ISD::PSIGNW:             return "X86ISD::PSIGNW";
   case X86ISD::PSIGND:             return "X86ISD::PSIGND";
-  case X86ISD::BLENDV:             return "X86ISD::BLENDV";
   case X86ISD::FMAX:               return "X86ISD::FMAX";
   case X86ISD::FMIN:               return "X86ISD::FMIN";
   case X86ISD::FRSQRT:             return "X86ISD::FRSQRT";
@@ -13381,7 +13342,7 @@
         X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
         Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
         Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
-        Mask = DAG.getNode(X86ISD::BLENDV, DL, MVT::v16i8, X, Y, Mask);
+        Mask = DAG.getNode(ISD::VSELECT, DL, MVT::v16i8, Mask, X, Y);
         return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
       }
     }

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=139479&r1=139478&r2=139479&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sun Sep 11 10:02:23 2011
@@ -809,7 +809,6 @@
     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139479&r1=139478&r2=139479&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Sep 11 10:02:23 2011
@@ -5869,36 +5869,27 @@
 
 let Predicates = [HasAVX] in {
 def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2),
-                  VR128:$mask)),
-    (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
-def : Pat<(v4i32 (X86blendv (v4i32 VR128:$src1), (v4i32 VR128:$src2),
-                  VR128:$mask)),
-    (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
-def : Pat<(v4f32 (X86blendv (v4f32 VR128:$src1), (v4f32 VR128:$src2),
-                  VR128:$mask)),
-    (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
-def : Pat<(v2i64 (X86blendv (v2i64 VR128:$src1), (v2i64 VR128:$src2),
-                  VR128:$mask)),
-    (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
-def : Pat<(v2f64 (X86blendv (v2f64 VR128:$src1), (v2f64 VR128:$src2),
-                  VR128:$mask)),
-    (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
-
-
-def : Pat<(v8i32 (X86blendv (v8i32 VR256:$src1), (v8i32 VR256:$src2),
-                  VR256:$mask)),
-    (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
-def : Pat<(v8f32 (X86blendv (v8f32 VR256:$src1), (v8f32 VR256:$src2),
-                  VR256:$mask)),
-    (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
-
-
-def : Pat<(v4i64 (X86blendv (v4i64 VR256:$src1), (v4i64 VR256:$src2),
-                  VR256:$mask)),
-    (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
-def : Pat<(v4f64 (X86blendv (v4f64 VR256:$src1), (v4f64 VR256:$src2),
-                  VR256:$mask)),
-    (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+ VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+
+def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
+ (v16i8 VR128:$src2))), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
+ (v4i32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
+ (v4f32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
+ (v2i64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
+ (v2f64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
+ (v8i32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
+ (v8f32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
+ (v4i64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
+ (v4f64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+
 }
 
 /// SS41I_ternary_int - SSE 4.1 ternary operator
@@ -5926,16 +5917,19 @@
 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
 
 let Predicates = [HasSSE41] in {
-  def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2), XMM0)),
-            (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4i32 (X86blendv (v4i32 VR128:$src1), (v4i32 VR128:$src2), XMM0)),
-            (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4f32 (X86blendv (v4f32 VR128:$src1), (v4f32 VR128:$src2), XMM0)),
-            (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v2i64 (X86blendv (v2i64 VR128:$src1), (v2i64 VR128:$src2), XMM0)),
-            (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v2f64 (X86blendv (v2f64 VR128:$src1), (v2f64 VR128:$src2), XMM0)),
-            (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
+def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2),
+ VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+
+  def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
+ (v16i8 VR128:$src2))), (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
+ (v4i32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
+ (v4f32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
+ (v2i64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
+ (v2f64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
 }
 
 let Predicates = [HasAVX] in



From nicholas at mxc.ca  Sun Sep 11 10:30:09 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Sun, 11 Sep 2011 15:30:09 -0000
Subject: [llvm-commits] [llvm] r139480 - /llvm/trunk/docs/Atomics.html
Message-ID: <20110911153009.232D02A6C12C@llvm.org>

Author: nicholas
Date: Sun Sep 11 10:30:08 2011
New Revision: 139480

URL: http://llvm.org/viewvc/llvm-project?rev=139480&view=rev
Log:
Fix verb tense agreement.

Modified:
    llvm/trunk/docs/Atomics.html

Modified: llvm/trunk/docs/Atomics.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Atomics.html?rev=139480&r1=139479&r2=139480&view=diff
==============================================================================
--- llvm/trunk/docs/Atomics.html (original)
+++ llvm/trunk/docs/Atomics.html Sun Sep 11 10:30:08 2011
@@ -308,7 +308,7 @@
       which would make those optimizations useful.</dd>
   <dt>Notes for code generation</dt>
   <dd>Code generation is essentially the same as that for unordered for loads
-     and stores.  No fences is required.  <code>cmpxchg</code> and 
+     and stores.  No fences are required.  <code>cmpxchg</code> and 
      <code>atomicrmw</code> are required to appear as a single operation.</dd>
 </dl>
 



From nicholas at mxc.ca  Sun Sep 11 10:50:05 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Sun, 11 Sep 2011 15:50:05 -0000
Subject: [llvm-commits] [llvm] r139481 - /llvm/trunk/docs/Atomics.html
Message-ID: <20110911155006.0154F2A6C12C@llvm.org>

Author: nicholas
Date: Sun Sep 11 10:50:05 2011
New Revision: 139481

URL: http://llvm.org/viewvc/llvm-project?rev=139481&view=rev
Log:
s/SequeuentiallyConsistent/SequentiallyConsistent/g

Modified:
    llvm/trunk/docs/Atomics.html

Modified: llvm/trunk/docs/Atomics.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Atomics.html?rev=139481&r1=139480&r2=139481&view=diff
==============================================================================
--- llvm/trunk/docs/Atomics.html (original)
+++ llvm/trunk/docs/Atomics.html Sun Sep 11 10:50:05 2011
@@ -437,10 +437,10 @@
       SequentiallyConsistent operations may not be reordered.</dd>
   <dt>Notes for code generation</dt>
   <dd>SequentiallyConsistent loads minimally require the same barriers
-     as Acquire operations and SequeuentiallyConsistent stores require
+     as Acquire operations and SequentiallyConsistent stores require
      Release barriers. Additionally, the code generator must enforce
-     ordering between SequeuentiallyConsistent stores followed by
-     SequeuentiallyConsistent loads. This is usually done by emitting
+     ordering between SequentiallyConsistent stores followed by
+     SequentiallyConsistent loads. This is usually done by emitting
      either a full fence before the loads or a full fence after the
      stores; which is preferred varies by architecture.</dd>
 </dl>



From bruno.cardoso at gmail.com  Sun Sep 11 14:47:23 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Sun, 11 Sep 2011 12:47:23 -0700
Subject: [llvm-commits] [llvm] r139479 - in /llvm/trunk:
 include/llvm/Target/TargetSelectionDAG.td
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
 lib/Target/X86/X86InstrSSE.td
In-Reply-To: <20110911150223.F09E12A6C12D@llvm.org>
References: <20110911150223.F09E12A6C12D@llvm.org>
Message-ID: <CACk9FxazdN7=nsPE3ZXDAL6t2khLaQCMzrj6KzT8S5tkpnyA0A@mail.gmail.com>

Hi Nadav,

On Sun, Sep 11, 2011 at 8:02 AM, Nadav Rotem <nadav.rotem at intel.com> wrote:
> Author: nadav
> Date: Sun Sep 11 10:02:23 2011
> New Revision: 139479
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139479&view=rev
> Log:
> CR fixes per Bruno's request.
>
> Undo the changes from r139285 which added custom lowering to vselect.
> Add tablegen lowering for vselect.
>
>
> Modified:
> ? ?llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.h
> ? ?llvm/trunk/lib/Target/X86/X86InstrSSE.td
>
> Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=139479&r1=139478&r2=139479&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
> +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Sun Sep 11 10:02:23 2011
> @@ -149,6 +149,10 @@
> ? SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
> ?]>;
>
> +def SDTVSelect : SDTypeProfile<1, 3, [ ? ? ? // vselect
> + ?SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
> +]>;
> +
> ?def SDTSelectCC : SDTypeProfile<1, 5, [ ? ? // select_cc
> ? SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
> ? SDTCisVT<5, OtherVT>
> @@ -390,8 +394,8 @@
>
> ?def setcc ? ? ?: SDNode<"ISD::SETCC" ? ? ?, SDTSetCC>;
> ?def select ? ? : SDNode<"ISD::SELECT" ? ? , SDTSelect>;
> +def vselect ? ?: SDNode<"ISD::VSELECT" ? ?, SDTVSelect>;
> ?def selectcc ? : SDNode<"ISD::SELECT_CC" ?, SDTSelectCC>;
> -def vsetcc ? ? : SDNode<"ISD::VSETCC" ? ? , SDTSetCC>;
>
> ?def brcond ? ? : SDNode<"ISD::BRCOND" ? ? , SDTBrcond, [SDNPHasChain]>;
> ?def brind ? ? ?: SDNode<"ISD::BRIND" ? ? ?, SDTBrind, ?[SDNPHasChain]>;
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139479&r1=139478&r2=139479&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Sep 11 10:02:23 2011
> @@ -917,11 +917,11 @@
> ? ? setOperationAction(ISD::SHL, ? ? ? ? ? ? ? ?MVT::v4i32, Custom);
> ? ? setOperationAction(ISD::SHL, ? ? ? ? ? ? ? ?MVT::v16i8, Custom);
>
> - ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v2f64, Custom);
> - ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v2i64, Custom);
> - ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v16i8, Custom);
> - ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4i32, Custom);
> - ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4f32, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v2f64, Legal);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v2i64, Legal);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v16i8, Legal);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4i32, Legal);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4f32, Legal);
>
> ? ? // i8 and i16 vectors are custom , because the source register and source
> ? ? // source memory operand types are not the same width. ?f32 vectors are
> @@ -1019,10 +1019,10 @@
> ? ? setOperationAction(ISD::SELECT, ? ? ? ? ? ?MVT::v4i64, Custom);
> ? ? setOperationAction(ISD::SELECT, ? ? ? ? ? ?MVT::v8f32, Custom);
>
> - ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4f64, Custom);
> - ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4i64, Custom);
> - ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v8i32, Custom);
> - ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v8f32, Custom);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4f64, Legal);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v4i64, Legal);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v8i32, Legal);
> + ? ?setOperationAction(ISD::VSELECT, ? ? ? ? ? ?MVT::v8f32, Legal);
>
> ? ? setOperationAction(ISD::ADD, ? ? ? ? ? ? ? MVT::v4i64, Custom);
> ? ? setOperationAction(ISD::ADD, ? ? ? ? ? ? ? MVT::v8i32, Custom);
> @@ -8703,43 +8703,6 @@
> ? return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
> ?}
>
> -SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
> - ?SDValue Cond ?= Op.getOperand(0);
> - ?SDValue Op1 = Op.getOperand(1);
> - ?SDValue Op2 = Op.getOperand(2);
> - ?DebugLoc DL = Op.getDebugLoc();
> -
> - ?SDValue Ops[] = {Op1, Op2, Cond};
> -
> - ?assert(Op1.getValueType().isVector() && "Op1 must be a vector");
> - ?assert(Op2.getValueType().isVector() && "Op2 must be a vector");
> - ?assert(Cond.getValueType().isVector() && "Cond must be a vector");
> - ?assert(Op1.getValueType() == Op2.getValueType() && "Type mismatch");
> -
> - ?EVT VT = Op1.getValueType();
> - ?switch (VT.getSimpleVT().SimpleTy) {
> - ? ?default: break;
> - ? ?// SSE4:
> - ? ?case MVT::v2i64:
> - ? ?case MVT::v2f64:
> - ? ?case MVT::v4i32:
> - ? ?case MVT::v4f32:
> - ? ?case MVT::v16i8:
> - ? ?case MVT::v8i16:
> - ? ?// AVX:
> - ? ?case MVT::v4i64:
> - ? ?case MVT::v4f64:
> - ? ?case MVT::v8i32:
> - ? ?case MVT::v8f32:
> - ? ?case MVT::v32i8:
> - ? ?case MVT::v16i16:
> - ? ? ?return DAG.getNode(X86ISD::BLENDV, DL, VT, Ops, array_lengthof(Ops));
> - ?}
> -
> - ?return SDValue();
> -}
> -
> -
> ?// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
> ?// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
> ?// from the AND / OR.
> @@ -9993,7 +9956,7 @@
> ? ? M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> ? ? ? ? ? ? ? ? ? ? DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
> ? ? ? ? ? ? ? ? ? ? DAG.getConstant(4, MVT::i32));
> - ? ?R = DAG.getNode(X86ISD::BLENDV, dl, VT, R, M, Op);
> + ? ?R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
> ? ? // a += a
> ? ? Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
>
> @@ -10008,13 +9971,13 @@
> ? ? M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> ? ? ? ? ? ? ? ? ? ? DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
> ? ? ? ? ? ? ? ? ? ? DAG.getConstant(2, MVT::i32));
> - ? ?R = DAG.getNode(X86ISD::BLENDV, dl, VT, R, M, Op);
> + ? ?R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
> ? ? // a += a
> ? ? Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
>
> ? ? // return pblendv(r, r+r, a);
> - ? ?R = DAG.getNode(X86ISD::BLENDV, dl, VT,
> - ? ? ? ? ? ? ? ? ? ?R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
> + ? ?R = DAG.getNode(ISD::VSELECT, dl, VT, Op,
> + ? ? ? ? ? ? ? ? ? ?R, DAG.getNode(ISD::ADD, dl, VT, R, R));
> ? ? return R;
> ? }
> ? return SDValue();
> @@ -10406,7 +10369,6 @@
> ? case ISD::FGETSIGN: ? ? ? ? ? return LowerFGETSIGN(Op, DAG);
> ? case ISD::SETCC: ? ? ? ? ? ? ?return LowerSETCC(Op, DAG);
> ? case ISD::SELECT: ? ? ? ? ? ? return LowerSELECT(Op, DAG);
> - ?case ISD::VSELECT: ? ? ? ? ? ?return LowerVSELECT(Op, DAG);
> ? case ISD::BRCOND: ? ? ? ? ? ? return LowerBRCOND(Op, DAG);
> ? case ISD::JumpTable: ? ? ? ? ?return LowerJumpTable(Op, DAG);
> ? case ISD::VASTART: ? ? ? ? ? ?return LowerVASTART(Op, DAG);
> @@ -10651,7 +10613,6 @@
> ? case X86ISD::PSIGNB: ? ? ? ? ? ? return "X86ISD::PSIGNB";
> ? case X86ISD::PSIGNW: ? ? ? ? ? ? return "X86ISD::PSIGNW";
> ? case X86ISD::PSIGND: ? ? ? ? ? ? return "X86ISD::PSIGND";
> - ?case X86ISD::BLENDV: ? ? ? ? ? ? return "X86ISD::BLENDV";
> ? case X86ISD::FMAX: ? ? ? ? ? ? ? return "X86ISD::FMAX";
> ? case X86ISD::FMIN: ? ? ? ? ? ? ? return "X86ISD::FMIN";
> ? case X86ISD::FRSQRT: ? ? ? ? ? ? return "X86ISD::FRSQRT";
> @@ -13381,7 +13342,7 @@
> ? ? ? ? X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
> ? ? ? ? Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
> ? ? ? ? Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
> - ? ? ? ?Mask = DAG.getNode(X86ISD::BLENDV, DL, MVT::v16i8, X, Y, Mask);
> + ? ? ? ?Mask = DAG.getNode(ISD::VSELECT, DL, MVT::v16i8, Mask, X, Y);
> ? ? ? ? return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
> ? ? ? }
> ? ? }
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=139479&r1=139478&r2=139479&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sun Sep 11 10:02:23 2011
> @@ -809,7 +809,6 @@
> ? ? SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
> - ? ?SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
> ? ? SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139479&r1=139478&r2=139479&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Sep 11 10:02:23 2011
> @@ -5869,36 +5869,27 @@
>
> ?let Predicates = [HasAVX] in {
> ?def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2),
> - ? ? ? ? ? ? ? ? ?VR128:$mask)),
> - ? ?(VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
> -def : Pat<(v4i32 (X86blendv (v4i32 VR128:$src1), (v4i32 VR128:$src2),
> - ? ? ? ? ? ? ? ? ?VR128:$mask)),
> - ? ?(VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
> -def : Pat<(v4f32 (X86blendv (v4f32 VR128:$src1), (v4f32 VR128:$src2),
> - ? ? ? ? ? ? ? ? ?VR128:$mask)),
> - ? ?(VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
> -def : Pat<(v2i64 (X86blendv (v2i64 VR128:$src1), (v2i64 VR128:$src2),
> - ? ? ? ? ? ? ? ? ?VR128:$mask)),
> - ? ?(VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
> -def : Pat<(v2f64 (X86blendv (v2f64 VR128:$src1), (v2f64 VR128:$src2),
> - ? ? ? ? ? ? ? ? ?VR128:$mask)),
> - ? ?(VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
> -
> -
> -def : Pat<(v8i32 (X86blendv (v8i32 VR256:$src1), (v8i32 VR256:$src2),
> - ? ? ? ? ? ? ? ? ?VR256:$mask)),
> - ? ?(VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
> -def : Pat<(v8f32 (X86blendv (v8f32 VR256:$src1), (v8f32 VR256:$src2),
> - ? ? ? ? ? ? ? ? ?VR256:$mask)),
> - ? ?(VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
> -
> -
> -def : Pat<(v4i64 (X86blendv (v4i64 VR256:$src1), (v4i64 VR256:$src2),
> - ? ? ? ? ? ? ? ? ?VR256:$mask)),
> - ? ?(VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
> -def : Pat<(v4f64 (X86blendv (v4f64 VR256:$src1), (v4f64 VR256:$src2),
> - ? ? ? ? ? ? ? ? ?VR256:$mask)),
> - ? ?(VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
> + VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
> +
> +def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
> + (v16i8 VR128:$src2))), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
> +def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
> + (v4i32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
> +def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
> + (v4f32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
> +def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
> + (v2i64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
> +def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
> + (v2f64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
> +def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
> + (v8i32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
> +def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
> + (v8f32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
> +def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
> + (v4i64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
> +def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
> + (v4f64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
> +
> ?}
>
> ?/// SS41I_ternary_int - SSE 4.1 ternary operator
> @@ -5926,16 +5917,19 @@
> ?defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
>
> ?let Predicates = [HasSSE41] in {
> - ?def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2), XMM0)),
> - ? ? ? ? ? ?(PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
> - ?def : Pat<(v4i32 (X86blendv (v4i32 VR128:$src1), (v4i32 VR128:$src2), XMM0)),
> - ? ? ? ? ? ?(BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
> - ?def : Pat<(v4f32 (X86blendv (v4f32 VR128:$src1), (v4f32 VR128:$src2), XMM0)),
> - ? ? ? ? ? ?(BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
> - ?def : Pat<(v2i64 (X86blendv (v2i64 VR128:$src1), (v2i64 VR128:$src2), XMM0)),
> - ? ? ? ? ? ?(BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
> - ?def : Pat<(v2f64 (X86blendv (v2f64 VR128:$src1), (v2f64 VR128:$src2), XMM0)),
> - ? ? ? ? ? ?(BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
> +def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2),
> + VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;

Why is this pattern above still here? Haven't you removed the BLENDV
node? Please remove this here and it from X86InstrFragments.td

> + ?def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
> + (v16i8 VR128:$src2))), (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
> + ?def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
> + (v4i32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
> + ?def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
> + (v4f32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
> + ?def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
> + (v2i64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
> + ?def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
> + (v2f64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
> ?}

Align the declaration of the patterns in the same it was before to be
consistent with the other ones in the .td file. Also please
canonicalize the mask to be last operand, as it was before.

Thanks

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From dblaikie at gmail.com  Sun Sep 11 14:54:48 2011
From: dblaikie at gmail.com (David Blaikie)
Date: Sun, 11 Sep 2011 19:54:48 -0000
Subject: [llvm-commits] [www] r139483 - /www/trunk/demo/index.cgi
Message-ID: <20110911195448.602A72A6C12C@llvm.org>

Author: dblaikie
Date: Sun Sep 11 14:54:48 2011
New Revision: 139483

URL: http://llvm.org/viewvc/llvm-project?rev=139483&view=rev
Log:
Fix demo to submit back to itself rather than no-existent test.cgi

Modified:
    www/trunk/demo/index.cgi

Modified: www/trunk/demo/index.cgi
URL: http://llvm.org/viewvc/llvm-project/www/trunk/demo/index.cgi?rev=139483&r1=139482&r2=139483&view=diff
==============================================================================
--- www/trunk/demo/index.cgi (original)
+++ www/trunk/demo/index.cgi Sun Sep 11 14:54:48 2011
@@ -16,7 +16,7 @@
 if ( !-d $ROOT ) { mkdir( $ROOT, 0777 ); }
 
 my $LOGFILE         = "$ROOT/log.txt";
-my $FORM_URL        = 'test.cgi';
+my $FORM_URL        = 'index.cgi';
 my $MAILADDR        = 'sabre at nondot.org';
 my $CONTACT_ADDRESS = 'Questions or comments?  Email the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVMdev mailing list</a>.';
 my $LOGO_IMAGE_URL  = '../img/DragonSmall.png';



From craig.topper at gmail.com  Sun Sep 11 15:23:20 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sun, 11 Sep 2011 20:23:20 -0000
Subject: [llvm-commits] [llvm] r139484 - in /llvm/trunk:
 test/MC/Disassembler/X86/simple-tests.txt
 utils/TableGen/X86DisassemblerTables.cpp
 utils/TableGen/X86RecognizableInstr.cpp
Message-ID: <20110911202320.5E5632A6C12C@llvm.org>

Author: ctopper
Date: Sun Sep 11 15:23:20 2011
New Revision: 139484

URL: http://llvm.org/viewvc/llvm-project?rev=139484&view=rev
Log:
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.

Modified:
    llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
    llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
    llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp

Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=139484&r1=139483&r2=139484&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Sun Sep 11 15:23:20 2011
@@ -158,3 +158,6 @@
 
 # CHECK: vinsertps $129, %xmm3, %xmm2, %xmm1
 0xc4 0xe3 0x69 0x21 0xcb 0x81
+
+# CHECK: pause
+0xf3 0x90

Modified: llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp?rev=139484&r1=139483&r2=139484&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp (original)
+++ llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp Sun Sep 11 15:23:20 2011
@@ -613,8 +613,10 @@
         if(newInfo.filtered)
           continue; // filtered instructions get lowest priority
         
-        if(previousInfo.name == "NOOP")
-          continue; // special case for XCHG32ar and NOOP
+        if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
+                                           newInfo.name == "XCHG32ar" ||
+                                           newInfo.name == "XCHG64ar"))
+          continue; // special case for XCHG*ar and NOOP
 
         if (outranks(previousInfo.insnContext, newInfo.insnContext))
           continue;

Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=139484&r1=139483&r2=139484&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Sun Sep 11 15:23:20 2011
@@ -325,7 +325,7 @@
       insnContext = IC_OPSIZE;
     else if (Prefix == X86Local::XD)
       insnContext = IC_XD;
-    else if (Prefix == X86Local::XS)
+    else if (Prefix == X86Local::XS || Prefix == X86Local::REP)
       insnContext = IC_XS;
     else
       insnContext = IC;
@@ -882,6 +882,7 @@
     }
     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
     break;
+  case X86Local::REP:
   default:
     opcodeType = ONEBYTE;
     switch (Opcode) {



From craig.topper at gmail.com  Sun Sep 11 16:41:45 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sun, 11 Sep 2011 21:41:45 -0000
Subject: [llvm-commits] [llvm] r139485 - in /llvm/trunk:
 lib/Target/X86/X86InstrArithmetic.td
 test/MC/Disassembler/X86/simple-tests.txt
 utils/TableGen/X86RecognizableInstr.cpp
Message-ID: <20110911214145.839512A6C12C@llvm.org>

Author: ctopper
Date: Sun Sep 11 16:41:45 2011
New Revision: 139485

URL: http://llvm.org/viewvc/llvm-project?rev=139485&view=rev
Log:
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
    llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
    llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=139485&r1=139484&r2=139485&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Sun Sep 11 16:41:45 2011
@@ -650,6 +650,15 @@
   let isCodeGenOnly = 1;
 }
 
+// BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding).
+class BinOpRR_F_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
+  : ITy<opcode, MRMSrcReg, typeinfo, (outs),
+        (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
+        mnemonic, "{$src2, $src1|$src1, $src2}", []> {
+  // The disassembler should know about this, but not the asmparser.
+  let isCodeGenOnly = 1;
+}
+
 // BinOpRM - Instructions like "add reg, reg, [mem]".
 class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
               dag outlist, list<dag> pattern>
@@ -1017,10 +1026,10 @@
       def #NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
     } // isCommutable
 
-    def #NAME#8rr_REV  : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
-    def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
-    def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
-    def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
+    def #NAME#8rr_REV  : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi8>;
+    def #NAME#16rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi16>;
+    def #NAME#32rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi32>;
+    def #NAME#64rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi64>;
 
     def #NAME#8rm   : BinOpRM_F<BaseOpc2, mnemonic, Xi8 , opnode>;
     def #NAME#16rm  : BinOpRM_F<BaseOpc2, mnemonic, Xi16, opnode>;

Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=139485&r1=139484&r2=139485&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Sun Sep 11 16:41:45 2011
@@ -161,3 +161,15 @@
 
 # CHECK: pause
 0xf3 0x90
+
+# CHECK: addl %eax, %edi
+0x01 0xc7
+
+# CHECK: addl %edi, %eax
+0x03 0xc7
+
+# CHECK: movl %eax, %edi
+0x89 0xc7
+
+# CHECK: movl %edi, %eax
+0x8b 0xc7

Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=139485&r1=139484&r2=139485&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Sun Sep 11 16:41:45 2011
@@ -345,7 +345,7 @@
     return FILTER_STRONG;
   
   if (Form == X86Local::Pseudo ||
-      IsCodeGenOnly)
+      (IsCodeGenOnly && Name.find("_REV") == Name.npos))
     return FILTER_STRONG;
   
   if (Form == X86Local::MRMInitReg)



From craig.topper at gmail.com  Sun Sep 11 18:19:54 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sun, 11 Sep 2011 23:19:54 -0000
Subject: [llvm-commits] [llvm] r139486 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/Disassembler/X86/simple-tests.txt
Message-ID: <20110911231954.BAFEA2A6C12C@llvm.org>

Author: ctopper
Date: Sun Sep 11 18:19:54 2011
New Revision: 139486

URL: http://llvm.org/viewvc/llvm-project?rev=139486&view=rev
Log:
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139486&r1=139485&r2=139486&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Sep 11 18:19:54 2011
@@ -356,6 +356,18 @@
 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
                 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
 
+// For the disassembler
+let isCodeGenOnly = 1 in {
+  def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
+                        (ins VR128:$src1, FR32:$src2),
+                        "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+                        XS, VEX_4V;
+  def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
+                        (ins VR128:$src1, FR64:$src2),
+                        "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+                        XD, VEX_4V;
+}
+
 let canFoldAsLoad = 1, isReMaterializable = 1 in {
   def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
   let AddedComplexity = 20 in
@@ -375,6 +387,16 @@
                           "movss\t{$src2, $dst|$dst, $src2}">, XS;
   def MOVSDrr : sse12_move_rr<FR64, v2f64,
                           "movsd\t{$src2, $dst|$dst, $src2}">, XD;
+
+  // For the disassembler
+  let isCodeGenOnly = 1 in {
+    def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
+                         (ins VR128:$src1, FR32:$src2),
+                         "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
+    def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
+                         (ins VR128:$src1, FR64:$src2),
+                         "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
+  }
 }
 
 let canFoldAsLoad = 1, isReMaterializable = 1 in {
@@ -706,6 +728,34 @@
                    "movupd\t{$src, $dst|$dst, $src}",
                    [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
 
+// For disassembler
+let isCodeGenOnly = 1 in {
+  def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
+                          (ins VR128:$src),
+                          "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
+  def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
+                           (ins VR128:$src),
+                           "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
+  def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
+                           (ins VR128:$src),
+                           "movups\t{$src, $dst|$dst, $src}", []>, VEX;
+  def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
+                           (ins VR128:$src),
+                           "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
+  def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
+                            (ins VR256:$src),
+                            "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
+  def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
+                            (ins VR256:$src),
+                            "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
+  def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
+                            (ins VR256:$src),
+                            "movups\t{$src, $dst|$dst, $src}", []>, VEX;
+  def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
+                            (ins VR256:$src),
+                            "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
+}
+
 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
           (VMOVUPSYmr addr:$dst, VR256:$src)>;
@@ -727,6 +777,18 @@
                    "movupd\t{$src, $dst|$dst, $src}",
                    [(store (v2f64 VR128:$src), addr:$dst)]>;
 
+// For disassembler
+let isCodeGenOnly = 1 in {
+  def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
+                         "movaps\t{$src, $dst|$dst, $src}", []>;
+  def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
+                         "movapd\t{$src, $dst|$dst, $src}", []>;
+  def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
+                         "movups\t{$src, $dst|$dst, $src}", []>;
+  def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
+                         "movupd\t{$src, $dst|$dst, $src}", []>;
+}
+
 let Predicates = [HasAVX] in {
   def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
             (VMOVUPSmr addr:$dst, VR128:$src)>;

Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=139486&r1=139485&r2=139486&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Sun Sep 11 18:19:54 2011
@@ -173,3 +173,63 @@
 
 # CHECK: movl %edi, %eax
 0x8b 0xc7
+
+# CHECK: movups %xmm1, %xmm0
+0x0f 0x10 0xc1
+
+# CHECK: movups %xmm0, %xmm1
+0x0f 0x11 0xc1
+
+# CHECK: movaps %xmm1, %xmm0
+0x0f 0x28 0xc1
+
+# CHECK: movaps %xmm0, %xmm1
+0x0f 0x29 0xc1
+
+# CHECK: movupd %xmm1, %xmm0
+0x66 0x0f 0x10 0xc1
+
+# CHECK: movupd %xmm0, %xmm1
+0x66 0x0f 0x11 0xc1
+
+# CHECK: movapd %xmm1, %xmm0
+0x66 0x0f 0x28 0xc1
+
+# CHECK: movapd %xmm0, %xmm1
+0x66 0x0f 0x29 0xc1
+
+# CHECK: vmovups %xmm1, %xmm0
+0xc5 0xf0 0x10 0xc1
+
+# CHECK: vmovups %xmm0, %xmm1
+0xc5 0xf0 0x11 0xc1
+
+# CHECK: vmovaps %xmm1, %xmm0
+0xc5 0xf0 0x28 0xc1
+
+# CHECK: vmovaps %xmm0, %xmm1
+0xc5 0xf0 0x29 0xc1
+
+# CHECK: vmovupd %xmm1, %xmm0
+0xc5 0xf1 0x10 0xc1
+
+# CHECK: vmovupd %xmm0, %xmm1
+0xc5 0xf1 0x11 0xc1
+
+# CHECK: vmovapd %xmm1, %xmm0
+0xc5 0xf1 0x28 0xc1
+
+# CHECK: vmovapd %xmm0, %xmm1
+0xc5 0xf1 0x29 0xc1
+
+# CHECK: vmovups %ymm1, %ymm0
+0xc5 0xf4 0x10 0xc1
+
+# CHECK: vmovups %ymm0, %ymm1
+0xc5 0xf4 0x11 0xc1
+
+# CHECK: vmovaps %ymm1, %ymm0
+0xc5 0xf4 0x28 0xc1
+
+# CHECK: vmovaps %ymm0, %ymm1
+0xc5 0xf4 0x29 0xc1