From nadav.rotem at intel.com Mon Sep 12 01:02:29 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Mon, 12 Sep 2011 09:02:29 +0300 Subject: [llvm-commits] [llvm] r139479 - in /llvm/trunk: include/llvm/Target/TargetSelectionDAG.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrSSE.td In-Reply-To: References: <20110911150223.F09E12A6C12D@llvm.org> Message-ID: <6594DDFF12B03D4E89690887C248699402972811C8@hasmsx504.ger.corp.intel.com> Hi Bruno, Thanks for the review. >> +def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2), >> + VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; >Why is this pattern above still here? Haven't you removed the BLENDV >node? Please remove this here and it from X86InstrFragments.td Okay. I will remove them. BTW, do we need to do anything for FastISel ? >> + ?def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1), >> + (v2f64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; >> ?} >Align the declaration of the patterns in the same it was before to be >consistent with the other ones in the .td file. Also please >canonicalize the mask to be last operand, as it was before. I will change the alignment. I don't understand the second comment. Do you want me to change the order of the operands in ISD::VSELECT ? Thanks, Nadav --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From bruno.cardoso at gmail.com Mon Sep 12 02:29:07 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 12 Sep 2011 00:29:07 -0700 Subject: [llvm-commits] [llvm] r139479 - in /llvm/trunk: include/llvm/Target/TargetSelectionDAG.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrSSE.td In-Reply-To: <6594DDFF12B03D4E89690887C248699402972811C8@hasmsx504.ger.corp.intel.com> References: <20110911150223.F09E12A6C12D@llvm.org> <6594DDFF12B03D4E89690887C248699402972811C8@hasmsx504.ger.corp.intel.com> Message-ID: 2011/9/11 Rotem, Nadav : > Hi Bruno, > > Thanks for the review. > >>> +def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2), >>> + VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; >>Why is this pattern above still here? Haven't you removed the BLENDV >>node? Please remove this here and it from X86InstrFragments.td > > Okay. I will remove them. ?BTW, do we need to do anything for FastISel ? Not that I'm aware! >>> + ?def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1), >>> + (v2f64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; >>> ?} > >>Align the declaration of the patterns in the same it was before to be >>consistent with the other ones in the .td file. Also please >>canonicalize the mask to be last operand, as it was before. > > I will change the alignment. I don't understand the second comment. Do you want me to change the order of the operands in ISD::VSELECT ? Cool. I was confused because of the BLENDV order, nevermind. Thanks Nadav, -- Bruno Cardoso Lopes http://www.brunocardoso.cc From bruno.cardoso at gmail.com Mon Sep 12 03:14:05 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 12 Sep 2011 01:14:05 -0700 Subject: [llvm-commits] [llvm] r139485 - in /llvm/trunk: lib/Target/X86/X86InstrArithmetic.td test/MC/Disassembler/X86/simple-tests.txt utils/TableGen/X86RecognizableInstr.cpp In-Reply-To: <20110911214145.839512A6C12C@llvm.org> References: <20110911214145.839512A6C12C@llvm.org> Message-ID: Hi Craig, On Sun, Sep 11, 2011 at 2:41 PM, Craig Topper wrote: > Author: ctopper > Date: Sun Sep 11 16:41:45 2011 > New Revision: 139485 > > URL: http://llvm.org/viewvc/llvm-project?rev=139485&view=rev > Log: > Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. > > Modified: > ? ?llvm/trunk/lib/Target/X86/X86InstrArithmetic.td > ? ?llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt > ? ?llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp > > Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=139485&r1=139484&r2=139485&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Sun Sep 11 16:41:45 2011 > @@ -650,6 +650,15 @@ > ? let isCodeGenOnly = 1; > ?} > > +// BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding). > +class BinOpRR_F_Rev opcode, string mnemonic, X86TypeInfo typeinfo> > + ?: ITy + ? ? ? ?(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2), > + ? ? ? ?mnemonic, "{$src2, $src1|$src1, $src2}", []> { > + ?// The disassembler should know about this, but not the asmparser. > + ?let isCodeGenOnly = 1; > +} > + > ?// BinOpRM - Instructions like "add reg, reg, [mem]". > ?class BinOpRM opcode, string mnemonic, X86TypeInfo typeinfo, > ? ? ? ? ? ? ? dag outlist, list pattern> > @@ -1017,10 +1026,10 @@ > ? ? ? def #NAME#64rr : BinOpRR_F; > ? ? } // isCommutable > > - ? ?def #NAME#8rr_REV ?: BinOpRR_Rev; > - ? ?def #NAME#16rr_REV : BinOpRR_Rev; > - ? ?def #NAME#32rr_REV : BinOpRR_Rev; > - ? ?def #NAME#64rr_REV : BinOpRR_Rev; > + ? ?def #NAME#8rr_REV ?: BinOpRR_F_Rev; > + ? ?def #NAME#16rr_REV : BinOpRR_F_Rev; > + ? ?def #NAME#32rr_REV : BinOpRR_F_Rev; > + ? ?def #NAME#64rr_REV : BinOpRR_F_Rev; > > ? ? def #NAME#8rm ? : BinOpRM_F; > ? ? def #NAME#16rm ?: BinOpRM_F; > > Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=139485&r1=139484&r2=139485&view=diff > ============================================================================== > --- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original) > +++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Sun Sep 11 16:41:45 2011 > @@ -161,3 +161,15 @@ > > ?# CHECK: pause > ?0xf3 0x90 > + > +# CHECK: addl %eax, %edi > +0x01 0xc7 > + > +# CHECK: addl %edi, %eax > +0x03 0xc7 > + > +# CHECK: movl %eax, %edi > +0x89 0xc7 > + > +# CHECK: movl %edi, %eax > +0x8b 0xc7 > > Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=139485&r1=139484&r2=139485&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original) > +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Sun Sep 11 16:41:45 2011 > @@ -345,7 +345,7 @@ > ? ? return FILTER_STRONG; > > ? if (Form == X86Local::Pseudo || > - ? ? ?IsCodeGenOnly) > + ? ? ?(IsCodeGenOnly && Name.find("_REV") == Name.npos)) > ? ? return FILTER_STRONG; I know that the "_REV" patterns were already there before you hack into this code. We would like eventually to remove all logic dependent on name suffixes or prefixes ("_REV", "_Int", "Int_" ... ), and create InstAliases, patterns or even add more flags like TB, XS, and so on... Since you're investigating and fixing disassembler stuff, do you have ideas on how to achieve the same results without duplicating instructions and appending the _REV suffix? Would that be possible? -- Bruno Cardoso Lopes http://www.brunocardoso.cc From eli.friedman at gmail.com Mon Sep 12 03:38:59 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 12 Sep 2011 01:38:59 -0700 Subject: [llvm-commits] [llvm] r139485 - in /llvm/trunk: lib/Target/X86/X86InstrArithmetic.td test/MC/Disassembler/X86/simple-tests.txt utils/TableGen/X86RecognizableInstr.cpp In-Reply-To: References: <20110911214145.839512A6C12C@llvm.org> Message-ID: On Mon, Sep 12, 2011 at 1:14 AM, Bruno Cardoso Lopes wrote: > Hi Craig, > > On Sun, Sep 11, 2011 at 2:41 PM, Craig Topper wrote: >> Author: ctopper >> Date: Sun Sep 11 16:41:45 2011 >> New Revision: 139485 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=139485&view=rev >> Log: >> Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. >> >> Modified: >> ? ?llvm/trunk/lib/Target/X86/X86InstrArithmetic.td >> ? ?llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt >> ? ?llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp >> >> Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=139485&r1=139484&r2=139485&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original) >> +++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Sun Sep 11 16:41:45 2011 >> @@ -650,6 +650,15 @@ >> ? let isCodeGenOnly = 1; >> ?} >> >> +// BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding). >> +class BinOpRR_F_Rev opcode, string mnemonic, X86TypeInfo typeinfo> >> + ?: ITy> + ? ? ? ?(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2), >> + ? ? ? ?mnemonic, "{$src2, $src1|$src1, $src2}", []> { >> + ?// The disassembler should know about this, but not the asmparser. >> + ?let isCodeGenOnly = 1; >> +} >> + >> ?// BinOpRM - Instructions like "add reg, reg, [mem]". >> ?class BinOpRM opcode, string mnemonic, X86TypeInfo typeinfo, >> ? ? ? ? ? ? ? dag outlist, list pattern> >> @@ -1017,10 +1026,10 @@ >> ? ? ? def #NAME#64rr : BinOpRR_F; >> ? ? } // isCommutable >> >> - ? ?def #NAME#8rr_REV ?: BinOpRR_Rev; >> - ? ?def #NAME#16rr_REV : BinOpRR_Rev; >> - ? ?def #NAME#32rr_REV : BinOpRR_Rev; >> - ? ?def #NAME#64rr_REV : BinOpRR_Rev; >> + ? ?def #NAME#8rr_REV ?: BinOpRR_F_Rev; >> + ? ?def #NAME#16rr_REV : BinOpRR_F_Rev; >> + ? ?def #NAME#32rr_REV : BinOpRR_F_Rev; >> + ? ?def #NAME#64rr_REV : BinOpRR_F_Rev; >> >> ? ? def #NAME#8rm ? : BinOpRM_F; >> ? ? def #NAME#16rm ?: BinOpRM_F; >> >> Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=139485&r1=139484&r2=139485&view=diff >> ============================================================================== >> --- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original) >> +++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Sun Sep 11 16:41:45 2011 >> @@ -161,3 +161,15 @@ >> >> ?# CHECK: pause >> ?0xf3 0x90 >> + >> +# CHECK: addl %eax, %edi >> +0x01 0xc7 >> + >> +# CHECK: addl %edi, %eax >> +0x03 0xc7 >> + >> +# CHECK: movl %eax, %edi >> +0x89 0xc7 >> + >> +# CHECK: movl %edi, %eax >> +0x8b 0xc7 >> >> Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=139485&r1=139484&r2=139485&view=diff >> ============================================================================== >> --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original) >> +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Sun Sep 11 16:41:45 2011 >> @@ -345,7 +345,7 @@ >> ? ? return FILTER_STRONG; >> >> ? if (Form == X86Local::Pseudo || >> - ? ? ?IsCodeGenOnly) >> + ? ? ?(IsCodeGenOnly && Name.find("_REV") == Name.npos)) >> ? ? return FILTER_STRONG; > > I know that the "_REV" patterns were already there before you hack > into this code. We would like eventually to remove all logic dependent > on name suffixes or prefixes ("_REV", "_Int", "Int_" ... ), and create > InstAliases, patterns or even add more flags like TB, XS, and so on... > Since you're investigating and fixing disassembler stuff, do you have > ideas on how to achieve the same results without duplicating > instructions and appending the _REV suffix? Would that be possible? It's worth noting that these aren't really duplicates; unlike the Int_ and _Int cases, from the perspective of x86 encoding, the _REV instructions are distinct instructions that happen to do the same thing as some other instruction. Trying to merge them with the functionally equivalent instructions would require a significant rearchitecture which I doubt is worthwhile. -Eli From nadav.rotem at intel.com Mon Sep 12 03:41:50 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Mon, 12 Sep 2011 08:41:50 -0000 Subject: [llvm-commits] [llvm] r139491 - in /llvm/trunk/lib/Target/X86: X86InstrFragmentsSIMD.td X86InstrSSE.td Message-ID: <20110912084150.E2E622A6C12C@llvm.org> Author: nadav Date: Mon Sep 12 03:41:50 2011 New Revision: 139491 URL: http://llvm.org/viewvc/llvm-project?rev=139491&view=rev Log: Format patterns, remove unused X86blend patterns Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=139491&r1=139490&r2=139491&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Mon Sep 12 03:41:50 2011 @@ -58,9 +58,6 @@ def X86psignd : SDNode<"X86ISD::PSIGND", SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>>; -def X86blendv : SDNode<"X86ISD::BLENDV", - SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, - SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>; def X86pextrb : SDNode<"X86ISD::PEXTRB", SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; def X86pextrw : SDNode<"X86ISD::PEXTRW", Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139491&r1=139490&r2=139491&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Sep 12 03:41:50 2011 @@ -5930,27 +5930,34 @@ memopv32i8, int_x86_avx_blendv_ps_256>; let Predicates = [HasAVX] in { -def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2), - VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1), - (v16i8 VR128:$src2))), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (v16i8 VR128:$src2))), + (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1), - (v4i32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (v4i32 VR128:$src2))), + (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1), - (v4f32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (v4f32 VR128:$src2))), + (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1), - (v2i64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (v2i64 VR128:$src2))), + (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1), - (v2f64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>; + (v2f64 VR128:$src2))), + (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>; def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1), - (v8i32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (v8i32 VR256:$src2))), + (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>; def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1), - (v8f32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (v8f32 VR256:$src2))), + (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>; def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1), - (v4i64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (v4i64 VR256:$src2))), + (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>; def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1), - (v4f64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>; + (v4f64 VR256:$src2))), + (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>; } @@ -5979,19 +5986,22 @@ defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>; let Predicates = [HasSSE41] in { -def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2), - VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; - def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1), - (v16i8 VR128:$src2))), (PBLENDVBrr0 VR128:$src1, VR128:$src2)>; - def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1), - (v4i32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>; - def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1), - (v4f32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>; - def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1), - (v2i64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; - def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1), - (v2f64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; +def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1), + (v16i8 VR128:$src2))), + (PBLENDVBrr0 VR128:$src1, VR128:$src2)>; +def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1), + (v4i32 VR128:$src2))), + (BLENDVPSrr0 VR128:$src1, VR128:$src2)>; +def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1), + (v4f32 VR128:$src2))), + (BLENDVPSrr0 VR128:$src1, VR128:$src2)>; +def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1), + (v2i64 VR128:$src2))), + (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; +def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1), + (v2f64 VR128:$src2))), + (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; } let Predicates = [HasAVX] in From baldrick at free.fr Mon Sep 12 06:31:18 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 12 Sep 2011 13:31:18 +0200 Subject: [llvm-commits] [llvm] r139407 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll In-Reply-To: References: <20110909210407.1C2DB2A6C12C@llvm.org> , , <4E6B4D6F.7080102@free.fr> Message-ID: <4E6DED86.4030606@free.fr> Hi James, > Please bear with me, because I'm trying to unravel and learn the design of SelectionDAG at the same time as querying this fix. > > If I've read the code right, the sequence goes something like: > > 1) Run DAGCombine in unrestricted mode. > 2) Run LegalizeTypes(): postcondition: "[the DAG] only uses operations and types that the target supports". > 3) If LegalizeTypes() changed the DAG, run DAGCombine in strictly-legal mode again. > 4) Run LegalizeVectors(); if this changed the DAG, run LegalizeTypes then DAGCombine again, again in strict mode. > 5) Legalize() > 6) DAGCombine again, strict mode. > > So by my understanding, before Eli's patch, DAGCombine emitted a DAG containing an illegal type as an operand of a BUILD_VECTOR. > LegalizeTypes() did not legalize that operand (by design or fault), so the output of LegalizeTypes() is illegal and seemingly does not adhere to its postcondition in SelectionDAGIsel.cpp. I don't know where you got the idea that LegalizeTypes doesn't type legalize BUILD_VECTOR nodes. It does. I didn't follow this thread from the beginning, but most likely one of the DAGCombiner runs after LegalizeTypes introduced a BUILD_VECTOR with an illegal type (a bug in DAGCombiner; there have been a lot of bugs like this in the DAGCombiner in the past). Ciao, Duncan. > > I see the problem as in LegalizeTypes(), not in DAGCombine. What am I missing here? (apart from a good knowledge of the target independent codegen!) > > Cheers for any help, > > James > ________________________________________ > From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands [baldrick at free.fr] > Sent: 10 September 2011 12:43 > To: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [llvm] r139407 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll > > Hi James, > >> So wouldn't a better solution be to make the TypeLegalizer actually legalize the types of BUILD_VECTOR? > > it does. LegalizeVectorOps is not part of the type legalizer. > > Ciao, Duncan. > >> >>> From LegalizeVectorOps.cpp: >> >> // This does not legalize vector manipulations like ISD::BUILD_VECTOR, >> // or operations that happen to take a vector which are custom-lowered; >> // the legalization for such operations never produces nodes >> // with illegal types, so it's okay to put off legalizing them until >> // SelectionDAG::Legalize runs. >> >> It seems to me that this statement is false - BUILD_VECTOR can contain illegal types after DAGCombine, so it is *not* safe to put off legalizing them. >> >> Unless the legalization should be done in SelectionDAG::Legalize...?: >> >> case ISD::BUILD_VECTOR: >> // A weird case: legalization for BUILD_VECTOR never legalizes the >> // operands! >> // FIXME: This really sucks... changing it isn't semantically incorrect, >> // but it massively pessimizes the code for floating-point BUILD_VECTORs >> // because ConstantFP operands get legalized into constant pool loads >> // before the BUILD_VECTOR code can see them. It doesn't usually bite, >> // though, because BUILD_VECTORS usually get lowered into other nodes >> // which get legalized properly. >> SimpleFinishLegalizing = false; >> break; >> >> It seems to me that there is code elsewhere outside of the DAGCombiner that is not sticking to its pre or postconditions, so fixing the DAGCombiner to produce legal types isn't the best solution. I had originally thought that the type legalization was only done before DAGCombine, which is why I proposed my original solution (which was similar to yours). >> >> Am I missing something here? There could be other places in the DAGCombiner that produces illegal types that aren't legalized that we haven't caught yet... >> >> Cheers, >> >> James >> >> >> ________________________________________ >> From: Eli Friedman [eli.friedman at gmail.com] >> Sent: 10 September 2011 11:46 >> To: James Molloy >> Cc: llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] [llvm] r139407 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll >> >> On Sat, Sep 10, 2011 at 1:27 AM, James Molloy wrote: >>> Hi Eli, >>> >>> This makes sense, thanks. A related question though, and please excuse my ignorance because the documentation of SelectionDAG is incomplete at best - under what situations could the DAGCombiner run before the DAGTypeLegalizer? My stepping with GDB found the opposite. >> >> The DAGCombiner always runs before the type legalizer... and after the >> type legalizer... and after the type legalizer runs again... see >> SelectionDAGISel::CodeGenAndEmitDAG(). >> >> -Eli >> >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. > From james.molloy at arm.com Mon Sep 12 08:04:48 2011 From: james.molloy at arm.com (James Molloy) Date: Mon, 12 Sep 2011 14:04:48 +0100 Subject: [llvm-commits] [llvm] r139407 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll In-Reply-To: <4E6DED86.4030606@free.fr> References: <20110909210407.1C2DB2A6C12C@llvm.org> , , <4E6B4D6F.7080102@free.fr> <4E6DED86.4030606@free.fr> Message-ID: <001401cc714c$8e0fe000$aa2fa000$@molloy@arm.com> Hi Duncan, Thanks for your reply. I see that where I was going wrong was I was thinking the DAGCombiner had a precondition of receiving a legal DAG, and LegalizeTypes was responsible for "cleaning up" any illegalalities the DAGCombiner made during its pass. I realise now as you're explained it, that the DAGCombiner itself has a postcondition on generating legal types only (when in strict mode), so it's not LegalizeTypes' responsibility. Thanks for the clarification, and apologies for extending this thread so long! James > -----Original Message----- > From: Duncan Sands [mailto:baldrick at free.fr] > Sent: 12 September 2011 12:31 > To: James Molloy > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] [llvm] r139407 - in /llvm/trunk: > lib/CodeGen/SelectionDAG/DAGCombiner.cpp > lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09- > OddVectorDivision.ll > > Hi James, > > > Please bear with me, because I'm trying to unravel and learn the design > of SelectionDAG at the same time as querying this fix. > > > > If I've read the code right, the sequence goes something like: > > > > 1) Run DAGCombine in unrestricted mode. > > 2) Run LegalizeTypes(): postcondition: "[the DAG] only uses operations > and types that the target supports". > > 3) If LegalizeTypes() changed the DAG, run DAGCombine in strictly-legal > mode again. > > 4) Run LegalizeVectors(); if this changed the DAG, run LegalizeTypes then > DAGCombine again, again in strict mode. > > 5) Legalize() > > 6) DAGCombine again, strict mode. > > > > So by my understanding, before Eli's patch, DAGCombine emitted a DAG > containing an illegal type as an operand of a BUILD_VECTOR. > > LegalizeTypes() did not legalize that operand (by design or fault), so > the output of LegalizeTypes() is illegal and seemingly does not adhere to > its postcondition in SelectionDAGIsel.cpp. > > I don't know where you got the idea that LegalizeTypes doesn't type > legalize > BUILD_VECTOR nodes. It does. I didn't follow this thread from the > beginning, > but most likely one of the DAGCombiner runs after LegalizeTypes introduced > a > BUILD_VECTOR with an illegal type (a bug in DAGCombiner; there have been a > lot > of bugs like this in the DAGCombiner in the past). > > Ciao, Duncan. > > > > > I see the problem as in LegalizeTypes(), not in DAGCombine. What am I > missing here? (apart from a good knowledge of the target independent > codegen!) > > > > Cheers for any help, > > > > James > > ________________________________________ > > From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] > On Behalf Of Duncan Sands [baldrick at free.fr] > > Sent: 10 September 2011 12:43 > > To: llvm-commits at cs.uiuc.edu > > Subject: Re: [llvm-commits] [llvm] r139407 - in /llvm/trunk: > lib/CodeGen/SelectionDAG/DAGCombiner.cpp > lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09- > OddVectorDivision.ll > > > > Hi James, > > > >> So wouldn't a better solution be to make the TypeLegalizer actually > legalize the types of BUILD_VECTOR? > > > > it does. LegalizeVectorOps is not part of the type legalizer. > > > > Ciao, Duncan. > > > >> > >>> From LegalizeVectorOps.cpp: > >> > >> // This does not legalize vector manipulations like ISD::BUILD_VECTOR, > >> // or operations that happen to take a vector which are custom-lowered; > >> // the legalization for such operations never produces nodes > >> // with illegal types, so it's okay to put off legalizing them until > >> // SelectionDAG::Legalize runs. > >> > >> It seems to me that this statement is false - BUILD_VECTOR can contain > illegal types after DAGCombine, so it is *not* safe to put off legalizing > them. > >> > >> Unless the legalization should be done in SelectionDAG::Legalize...?: > >> > >> case ISD::BUILD_VECTOR: > >> // A weird case: legalization for BUILD_VECTOR never legalizes the > >> // operands! > >> // FIXME: This really sucks... changing it isn't semantically > incorrect, > >> // but it massively pessimizes the code for floating-point > BUILD_VECTORs > >> // because ConstantFP operands get legalized into constant pool > loads > >> // before the BUILD_VECTOR code can see them. It doesn't usually > bite, > >> // though, because BUILD_VECTORS usually get lowered into other > nodes > >> // which get legalized properly. > >> SimpleFinishLegalizing = false; > >> break; > >> > >> It seems to me that there is code elsewhere outside of the DAGCombiner > that is not sticking to its pre or postconditions, so fixing the > DAGCombiner to produce legal types isn't the best solution. I had > originally thought that the type legalization was only done before > DAGCombine, which is why I proposed my original solution (which was similar > to yours). > >> > >> Am I missing something here? There could be other places in the > DAGCombiner that produces illegal types that aren't legalized that we > haven't caught yet... > >> > >> Cheers, > >> > >> James > >> > >> > >> ________________________________________ > >> From: Eli Friedman [eli.friedman at gmail.com] > >> Sent: 10 September 2011 11:46 > >> To: James Molloy > >> Cc: llvm-commits at cs.uiuc.edu > >> Subject: Re: [llvm-commits] [llvm] r139407 - in /llvm/trunk: > lib/CodeGen/SelectionDAG/DAGCombiner.cpp > lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09- > OddVectorDivision.ll > >> > >> On Sat, Sep 10, 2011 at 1:27 AM, James Molloy > wrote: > >>> Hi Eli, > >>> > >>> This makes sense, thanks. A related question though, and please excuse > my ignorance because the documentation of SelectionDAG is incomplete at > best - under what situations could the DAGCombiner run before the > DAGTypeLegalizer? My stepping with GDB found the opposite. > >> > >> The DAGCombiner always runs before the type legalizer... and after the > >> type legalizer... and after the type legalizer runs again... see > >> SelectionDAGISel::CodeGenAndEmitDAG(). > >> > >> -Eli > >> > >> > >> -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > >> > >> > >> _______________________________________________ > >> llvm-commits mailing list > >> llvm-commits at cs.uiuc.edu > >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > > From richard at xmos.com Mon Sep 12 09:41:31 2011 From: richard at xmos.com (Richard Osborne) Date: Mon, 12 Sep 2011 14:41:31 -0000 Subject: [llvm-commits] [llvm] r139494 - /llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Message-ID: <20110912144131.BD64F2A6C12C@llvm.org> Author: friedgold Date: Mon Sep 12 09:41:31 2011 New Revision: 139494 URL: http://llvm.org/viewvc/llvm-project?rev=139494&view=rev Log: Mark LDWCP as having no side effects. Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=139494&r1=139493&r2=139494&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Mon Sep 12 09:41:31 2011 @@ -572,7 +572,7 @@ [(store GRRegs:$val, ADDRdpii:$addr)]>; //let Uses = [CP] in .. -let mayLoad = 1, isReMaterializable = 1 in +let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in defm LDWCP : FRU6_LRU6_cp<"ldw">; let Uses = [SP] in { From richard at xmos.com Mon Sep 12 09:43:23 2011 From: richard at xmos.com (Richard Osborne) Date: Mon, 12 Sep 2011 14:43:23 -0000 Subject: [llvm-commits] [llvm] r139495 - in /llvm/trunk: lib/Target/XCore/XCoreISelDAGToDAG.cpp test/CodeGen/XCore/licm-ldwcp.ll Message-ID: <20110912144323.8CEBF2A6C12C@llvm.org> Author: friedgold Date: Mon Sep 12 09:43:23 2011 New Revision: 139495 URL: http://llvm.org/viewvc/llvm-project?rev=139495&view=rev Log: Associate a MemOperand with LDWCP nodes introduced during ISel. This information is required if we want LDWCP to be hoisted out of loops. Added: llvm/trunk/test/CodeGen/XCore/licm-ldwcp.ll Modified: llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp?rev=139495&r1=139494&r2=139495&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp Mon Sep 12 09:43:23 2011 @@ -169,9 +169,14 @@ CurDAG->getTargetConstantPool(ConstantInt::get( Type::getInt32Ty(*CurDAG->getContext()), Val), TLI.getPointerTy()); - return CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, - MVT::Other, CPIdx, - CurDAG->getEntryNode()); + SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, + MVT::Other, CPIdx, + CurDAG->getEntryNode()); + MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); + MemOp[0] = MF->getMachineMemOperand( + MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad, 4, 4); + cast(node)->setMemRefs(MemOp, MemOp + 1); + return node; } break; } Added: llvm/trunk/test/CodeGen/XCore/licm-ldwcp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/licm-ldwcp.ll?rev=139495&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/XCore/licm-ldwcp.ll (added) +++ llvm/trunk/test/CodeGen/XCore/licm-ldwcp.ll Mon Sep 12 09:43:23 2011 @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=xcore -asm-verbose=0 | FileCheck %s + +; MachineLICM should hoist the LDWCP out of the loop. + +; CHECK: f: +; CHECK-NEXT: ldw [[REG:r[0-9]+]], cp[.LCPI0_0] +; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: stw [[REG]], r0[0] +; CHECK-NEXT: bu .LBB0_1 + +define void @f(i32* nocapture %p) noreturn nounwind { +entry: + br label %bb + +bb: ; preds = %bb, %entry + volatile store i32 525509670, i32* %p, align 4 + br label %bb +} From stoklund at 2pi.dk Mon Sep 12 11:03:26 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 12 Sep 2011 16:03:26 -0000 Subject: [llvm-commits] [llvm] r139498 - /llvm/trunk/lib/CodeGen/SplitKit.h Message-ID: <20110912160326.372972A6C12C@llvm.org> Author: stoklund Date: Mon Sep 12 11:03:26 2011 New Revision: 139498 URL: http://llvm.org/viewvc/llvm-project?rev=139498&view=rev Log: Update comments to reflect some (not so) recent changes. Modified: llvm/trunk/lib/CodeGen/SplitKit.h Modified: llvm/trunk/lib/CodeGen/SplitKit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=139498&r1=139497&r2=139498&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.h (original) +++ llvm/trunk/lib/CodeGen/SplitKit.h Mon Sep 12 11:03:26 2011 @@ -255,7 +255,7 @@ // live-out value and its defining block. // One of these conditions shall be true: // - // 1. !LiveOutCache.count(MBB) + // 1. !LiveOutSeen.count(MBB->getNumber()) // 2. LiveOutCache[MBB].second.getNode() == MBB // 3. forall P in preds(MBB): LiveOutCache[P] == LiveOutCache[MBB] // @@ -264,12 +264,13 @@ // VNI = Edit.get(RegIdx)->getVNInfoAt(LIS.getMBBEndIdx(MBB)) // Node = mbt_[LIS.getMBBFromIndex(VNI->def)] // - // The cache is also used as a visited set by extendRange(). It can be shared - // by all the new registers because at most one is live out of each block. + // The cache can be shared by all the new registers because at most one is + // live out of each block. LiveOutMap LiveOutCache; // LiveOutSeen - Indexed by MBB->getNumber(), a bit is set for each valid - // entry in LiveOutCache. + // entry in LiveOutCache. This is also used as a visited set for + // findReachingDefs(). BitVector LiveOutSeen; /// LiveInBlock - Info for updateSSA() about a block where a register is From bruno.cardoso at gmail.com Mon Sep 12 11:12:13 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 12 Sep 2011 09:12:13 -0700 Subject: [llvm-commits] [llvm] r139485 - in /llvm/trunk: lib/Target/X86/X86InstrArithmetic.td test/MC/Disassembler/X86/simple-tests.txt utils/TableGen/X86RecognizableInstr.cpp In-Reply-To: References: <20110911214145.839512A6C12C@llvm.org> Message-ID: On Mon, Sep 12, 2011 at 1:38 AM, Eli Friedman wrote: > On Mon, Sep 12, 2011 at 1:14 AM, Bruno Cardoso Lopes > wrote: >> Hi Craig, >> >> On Sun, Sep 11, 2011 at 2:41 PM, Craig Topper wrote: >>> Author: ctopper >>> Date: Sun Sep 11 16:41:45 2011 >>> New Revision: 139485 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=139485&view=rev >>> Log: >>> Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. >>> >>> Modified: >>> ? ?llvm/trunk/lib/Target/X86/X86InstrArithmetic.td >>> ? ?llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt >>> ? ?llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp >>> >>> Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=139485&r1=139484&r2=139485&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original) >>> +++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Sun Sep 11 16:41:45 2011 >>> @@ -650,6 +650,15 @@ >>> ? let isCodeGenOnly = 1; >>> ?} >>> >>> +// BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding). >>> +class BinOpRR_F_Rev opcode, string mnemonic, X86TypeInfo typeinfo> >>> + ?: ITy>> + ? ? ? ?(ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2), >>> + ? ? ? ?mnemonic, "{$src2, $src1|$src1, $src2}", []> { >>> + ?// The disassembler should know about this, but not the asmparser. >>> + ?let isCodeGenOnly = 1; >>> +} >>> + >>> ?// BinOpRM - Instructions like "add reg, reg, [mem]". >>> ?class BinOpRM opcode, string mnemonic, X86TypeInfo typeinfo, >>> ? ? ? ? ? ? ? dag outlist, list pattern> >>> @@ -1017,10 +1026,10 @@ >>> ? ? ? def #NAME#64rr : BinOpRR_F; >>> ? ? } // isCommutable >>> >>> - ? ?def #NAME#8rr_REV ?: BinOpRR_Rev; >>> - ? ?def #NAME#16rr_REV : BinOpRR_Rev; >>> - ? ?def #NAME#32rr_REV : BinOpRR_Rev; >>> - ? ?def #NAME#64rr_REV : BinOpRR_Rev; >>> + ? ?def #NAME#8rr_REV ?: BinOpRR_F_Rev; >>> + ? ?def #NAME#16rr_REV : BinOpRR_F_Rev; >>> + ? ?def #NAME#32rr_REV : BinOpRR_F_Rev; >>> + ? ?def #NAME#64rr_REV : BinOpRR_F_Rev; >>> >>> ? ? def #NAME#8rm ? : BinOpRM_F; >>> ? ? def #NAME#16rm ?: BinOpRM_F; >>> >>> Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=139485&r1=139484&r2=139485&view=diff >>> ============================================================================== >>> --- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original) >>> +++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Sun Sep 11 16:41:45 2011 >>> @@ -161,3 +161,15 @@ >>> >>> ?# CHECK: pause >>> ?0xf3 0x90 >>> + >>> +# CHECK: addl %eax, %edi >>> +0x01 0xc7 >>> + >>> +# CHECK: addl %edi, %eax >>> +0x03 0xc7 >>> + >>> +# CHECK: movl %eax, %edi >>> +0x89 0xc7 >>> + >>> +# CHECK: movl %edi, %eax >>> +0x8b 0xc7 >>> >>> Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=139485&r1=139484&r2=139485&view=diff >>> ============================================================================== >>> --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original) >>> +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Sun Sep 11 16:41:45 2011 >>> @@ -345,7 +345,7 @@ >>> ? ? return FILTER_STRONG; >>> >>> ? if (Form == X86Local::Pseudo || >>> - ? ? ?IsCodeGenOnly) >>> + ? ? ?(IsCodeGenOnly && Name.find("_REV") == Name.npos)) >>> ? ? return FILTER_STRONG; >> >> I know that the "_REV" patterns were already there before you hack >> into this code. We would like eventually to remove all logic dependent >> on name suffixes or prefixes ("_REV", "_Int", "Int_" ... ), and create >> InstAliases, patterns or even add more flags like TB, XS, and so on... >> Since you're investigating and fixing disassembler stuff, do you have >> ideas on how to achieve the same results without duplicating >> instructions and appending the _REV suffix? Would that be possible? > > It's worth noting that these aren't really duplicates; unlike the Int_ > and _Int cases, from the perspective of x86 encoding, the _REV > instructions are distinct instructions that happen to do the same > thing as some other instruction. ?Trying to merge them with the > functionally equivalent instructions would require a significant > rearchitecture which I doubt is worthwhile. I see. Thanks for the explanation Eli! -- Bruno Cardoso Lopes http://www.brunocardoso.cc From stoklund at 2pi.dk Mon Sep 12 11:36:32 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 12 Sep 2011 09:36:32 -0700 Subject: [llvm-commits] [llvm] r139407 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll In-Reply-To: <20110909210407.1C2DB2A6C12C@llvm.org> References: <20110909210407.1C2DB2A6C12C@llvm.org> Message-ID: On Sep 9, 2011, at 2:04 PM, Eli Friedman wrote: > --- llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll (added) > +++ llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll Fri Sep 9 16:04:06 2011 > @@ -0,0 +1,23 @@ > +; RUN: llc -mtriple=armv7-- %s -mattr=-neon Eli, This test is leaving temporary files in the test directory. Please use '< %s' instead of '%s'. /jakob From stoklund at 2pi.dk Mon Sep 12 11:49:21 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 12 Sep 2011 16:49:21 -0000 Subject: [llvm-commits] [llvm] r139500 - in /llvm/trunk/lib/CodeGen: RegAllocGreedy.cpp SplitKit.cpp SplitKit.h Message-ID: <20110912164921.D34D12A6C12C@llvm.org> Author: stoklund Date: Mon Sep 12 11:49:21 2011 New Revision: 139500 URL: http://llvm.org/viewvc/llvm-project?rev=139500&view=rev Log: Add an interface for SplitKit complement spill modes. SplitKit always computes a complement live range to cover the places where the original live range was live, but no explicit region has been allocated. Currently, the complement live range is created to be as small as possible - it never overlaps any of the regions. This minimizes register pressure, but if the complement is going to be spilled anyway, that is not very important. The spiller will eliminate redundant spills, and hoist others by making the spill slot live range overlap some of the regions created by splitting. Stack slots are cheap. This patch adds the interface to enable spill modes in SplitKit. In spill mode, SplitKit will assume that the complement is going to spill, so it will allow it to overlap regions in order to avoid back-copies. By doing some of the spiller's work early, the complement live range becomes simpler. In some cases, it can become much simpler because no extra PHI-defs are required. This will speed up both splitting and spilling. This is only the interface to enable spill modes, no implementation yet. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp llvm/trunk/lib/CodeGen/SplitKit.cpp llvm/trunk/lib/CodeGen/SplitKit.h Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=139500&r1=139499&r2=139500&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Sep 12 11:49:21 2011 @@ -53,6 +53,15 @@ static cl::opt CompactRegions("compact-regions", cl::init(true)); +static cl::opt +SplitSpillMode("split-spill-mode", cl::Hidden, + cl::desc("Spill mode for splitting live ranges"), + cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"), + clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"), + clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed"), + clEnumValEnd), + cl::init(SplitEditor::SM_Partition)); + static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator", createGreedyRegisterAllocator); @@ -1166,7 +1175,7 @@ // Prepare split editor. LiveRangeEdit LREdit(VirtReg, NewVRegs, this); - SE->reset(LREdit); + SE->reset(LREdit, SplitSpillMode); // Assign all edge bundles to the preferred candidate, or NoCand. BundleCand.assign(Bundles->getNumBundles(), NoCand); @@ -1214,7 +1223,7 @@ unsigned Reg = VirtReg.reg; bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); LiveRangeEdit LREdit(VirtReg, NewVRegs, this); - SE->reset(LREdit); + SE->reset(LREdit, SplitSpillMode); ArrayRef UseBlocks = SA->getUseBlocks(); for (unsigned i = 0; i != UseBlocks.size(); ++i) { const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=139500&r1=139499&r2=139500&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Mon Sep 12 11:49:21 2011 @@ -309,11 +309,13 @@ TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()), Edit(0), OpenIdx(0), + SpillMode(SM_Partition), RegAssign(Allocator) {} -void SplitEditor::reset(LiveRangeEdit &lre) { - Edit = &lre; +void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) { + Edit = &LRE; + SpillMode = SM; OpenIdx = 0; RegAssign.clear(); Values.clear(); Modified: llvm/trunk/lib/CodeGen/SplitKit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=139500&r1=139499&r2=139500&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.h (original) +++ llvm/trunk/lib/CodeGen/SplitKit.h Mon Sep 12 11:49:21 2011 @@ -217,6 +217,36 @@ const TargetInstrInfo &TII; const TargetRegisterInfo &TRI; +public: + + /// ComplementSpillMode - Select how the complement live range should be + /// created. SplitEditor automatically creates interval 0 to contain + /// anything that isn't added to another interval. This complement interval + /// can get quite complicated, and it can sometimes be an advantage to allow + /// it to overlap the other intervals. If it is going to spill anyway, no + /// registers are wasted by keeping a value in two places at the same time. + enum ComplementSpillMode { + /// SM_Partition(Default) - Try to create the complement interval so it + /// doesn't overlap any other intervals, and the original interval is + /// partitioned. This may require a large number of back copies and extra + /// PHI-defs. Only segments marked with overlapIntv will be overlapping. + SM_Partition, + + /// SM_Size - Overlap intervals to minimize the number of inserted COPY + /// instructions. Copies to the complement interval are hoisted to their + /// common dominator, so only one COPY is required per value in the + /// complement interval. This also means that no extra PHI-defs need to be + /// inserted in the complement interval. + SM_Size, + + /// SM_Speed - Overlap intervals to minimize the expected execution + /// frequency of the inserted copies. This is very similar to SM_Size, but + /// the complement interval may get some extra PHI-defs. + SM_Speed + }; + +private: + /// Edit - The current parent register and new intervals created. LiveRangeEdit *Edit; @@ -225,6 +255,9 @@ /// openIntv will be 1. unsigned OpenIdx; + /// The current spill mode, selected by reset(). + ComplementSpillMode SpillMode; + typedef IntervalMap RegAssignMap; /// Allocator for the interval map. This will eventually be shared with @@ -354,7 +387,7 @@ MachineDominatorTree&); /// reset - Prepare for a new split. - void reset(LiveRangeEdit&); + void reset(LiveRangeEdit&, ComplementSpillMode = SM_Partition); /// Create a new virtual register and live interval. /// Return the interval index, starting from 1. Interval index 0 is the From stoklund at 2pi.dk Mon Sep 12 11:54:42 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 12 Sep 2011 16:54:42 -0000 Subject: [llvm-commits] [llvm] r139501 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Message-ID: <20110912165443.0B3A12A6C12C@llvm.org> Author: stoklund Date: Mon Sep 12 11:54:42 2011 New Revision: 139501 URL: http://llvm.org/viewvc/llvm-project?rev=139501&view=rev Log: Remove the -compact-regions flag. It has been enabled by default for a while, it was only there to allow performance comparisons. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=139501&r1=139500&r2=139501&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Sep 12 11:54:42 2011 @@ -51,8 +51,6 @@ STATISTIC(NumLocalSplits, "Number of split local live ranges"); STATISTIC(NumEvicted, "Number of interferences evicted"); -static cl::opt CompactRegions("compact-regions", cl::init(true)); - static cl::opt SplitSpillMode("split-spill-mode", cl::Hidden, cl::desc("Spill mode for splitting live ranges"), @@ -410,15 +408,11 @@ if (ExtraRegInfo[Reg].Stage == RS_Split) { // Unsplit ranges that couldn't be allocated immediately are deferred until - // everything else has been allocated. Long ranges are allocated last so - // they are split against realistic interference. - if (CompactRegions) - Prio = Size; - else - Prio = (1u << 31) - Size; + // everything else has been allocated. + Prio = Size; } else { - // Everything else is allocated in long->short order. Long ranges that don't - // fit should be spilled ASAP so they don't create interference. + // Everything is allocated in long->short order. Long ranges that don't fit + // should be spilled (or split) ASAP so they don't create interference. Prio = (1u << 31) + Size; // Boost ranges that have a physical register hint. @@ -1092,7 +1086,7 @@ SmallVector UsedCands; // Check if we can split this live range around a compact region. - bool HasCompact = CompactRegions && calcCompactRegion(GlobalCand.front()); + bool HasCompact = calcCompactRegion(GlobalCand.front()); if (HasCompact) { // Yes, keep GlobalCand[0] as the compact region candidate. NumCands = 1; From dpatel at apple.com Mon Sep 12 12:18:20 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 12 Sep 2011 17:18:20 -0000 Subject: [llvm-commits] [llvm] r139503 - in /llvm/trunk: include/llvm/Support/Dwarf.h lib/Support/Dwarf.cpp Message-ID: <20110912171820.BD3F42A6C12C@llvm.org> Author: dpatel Date: Mon Sep 12 12:18:20 2011 New Revision: 139503 URL: http://llvm.org/viewvc/llvm-project?rev=139503&view=rev Log: Add DW_ATE_UTF, which clang started using in my previous commit! Modified: llvm/trunk/include/llvm/Support/Dwarf.h llvm/trunk/lib/Support/Dwarf.cpp Modified: llvm/trunk/include/llvm/Support/Dwarf.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Dwarf.h?rev=139503&r1=139502&r2=139503&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Dwarf.h (original) +++ llvm/trunk/include/llvm/Support/Dwarf.h Mon Sep 12 12:18:20 2011 @@ -428,6 +428,7 @@ DW_ATE_unsigned = 0x07, DW_ATE_unsigned_char = 0x08, DW_ATE_imaginary_float = 0x09, + DW_ATE_UTF = 0x10, DW_ATE_packed_decimal = 0x0a, DW_ATE_numeric_string = 0x0b, DW_ATE_edited = 0x0c, Modified: llvm/trunk/lib/Support/Dwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Dwarf.cpp?rev=139503&r1=139502&r2=139503&view=diff ============================================================================== --- llvm/trunk/lib/Support/Dwarf.cpp (original) +++ llvm/trunk/lib/Support/Dwarf.cpp Mon Sep 12 12:18:20 2011 @@ -416,6 +416,7 @@ case DW_ATE_unsigned: return "DW_ATE_unsigned"; case DW_ATE_unsigned_char: return "DW_ATE_unsigned_char"; case DW_ATE_imaginary_float: return "DW_ATE_imaginary_float"; + case DW_ATE_UTF: return "DW_ATE_UTF"; case DW_ATE_packed_decimal: return "DW_ATE_packed_decimal"; case DW_ATE_numeric_string: return "DW_ATE_numeric_string"; case DW_ATE_edited: return "DW_ATE_edited"; From atrick at apple.com Mon Sep 12 12:20:57 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 12 Sep 2011 17:20:57 -0000 Subject: [llvm-commits] [llvm] r139504 - /llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll Message-ID: <20110912172057.E6ADD2A6C12C@llvm.org> Author: atrick Date: Mon Sep 12 12:20:57 2011 New Revision: 139504 URL: http://llvm.org/viewvc/llvm-project?rev=139504&view=rev Log: Test case for r139453, WidenIV::GetExtendedOperandRecurrence. Added: llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll Added: llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll?rev=139504&view=auto ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll (added) +++ llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll Mon Sep 12 12:20:57 2011 @@ -0,0 +1,30 @@ +; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s +; Test WidenIV::GetExtendedOperandRecurrence. +; add219 should be extended to i64 because it is nsw, even though its +; sext cannot be hoisted outside the loop. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +define void @test() nounwind { +entry: + br i1 undef, label %for.body11, label %for.end285 + +for.body11: ; preds = %entry + %shl = shl i32 1, 1 + %shl132 = shl i32 %shl, 1 + br label %for.body153 + +for.body153: ; preds = %for.body153, %for.body11 + br i1 undef, label %for.body170, label %for.body153 + +; CHECK: add nsw i64 %indvars.iv, 1 +for.body170: ; preds = %for.body170, %for.body153 + %i2.19 = phi i32 [ %add249, %for.body170 ], [ undef, %for.body153 ] + %add219 = add nsw i32 %i2.19, 1 + %idxprom220 = sext i32 %add219 to i64 + %add249 = add nsw i32 %i2.19, %shl132 + br label %for.body170 + +for.end285: ; preds = %entry + ret void +} From eli.friedman at gmail.com Mon Sep 12 12:32:58 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 12 Sep 2011 17:32:58 -0000 Subject: [llvm-commits] [llvm] r139505 - /llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll Message-ID: <20110912173258.4F9D62A6C12C@llvm.org> Author: efriedma Date: Mon Sep 12 12:32:58 2011 New Revision: 139505 URL: http://llvm.org/viewvc/llvm-project?rev=139505&view=rev Log: Fix mistake in test runline. Modified: llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll Modified: llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll?rev=139505&r1=139504&r2=139505&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll Mon Sep 12 12:32:58 2011 @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=armv7-- %s -mattr=-neon +; RUN: llc -mtriple=armv7-- < %s -mattr=-neon target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32" target triple = "armv7-none-linux-gnueabi" From eli.friedman at gmail.com Mon Sep 12 12:34:44 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 12 Sep 2011 10:34:44 -0700 Subject: [llvm-commits] [llvm] r139407 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll In-Reply-To: References: <20110909210407.1C2DB2A6C12C@llvm.org> Message-ID: On Mon, Sep 12, 2011 at 9:36 AM, Jakob Stoklund Olesen wrote: > > On Sep 9, 2011, at 2:04 PM, Eli Friedman wrote: > >> --- llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll (added) >> +++ llvm/trunk/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll Fri Sep ?9 16:04:06 2011 >> @@ -0,0 +1,23 @@ >> +; RUN: llc -mtriple=armv7-- %s -mattr=-neon > > Eli, > > This test is leaving temporary files in the test directory. > > Please use '< %s' instead of '%s'. r139505 -Eli From STPWORLD at yandex.ru Mon Sep 12 13:04:12 2011 From: STPWORLD at yandex.ru (Stepan Dyatkovskiy) Date: Mon, 12 Sep 2011 22:04:12 +0400 Subject: [llvm-commits] [LLVM, llvm-mc] bugfix for bug #10869: Unclear error for files without newline at the end of file (ARM, x86). In-Reply-To: <001201cc6f0c$b5081c00$1f185400$@molloy@arm.com> References: <001201cc6f0c$b5081c00$1f185400$@molloy@arm.com> Message-ID: <970541315850652@web27.yandex.ru> Hi, It is a commonly encountered problem for AsmParser and for all its extensions (like an ARMAsmParser or MBlazeAsmParser). Now the finishing of instruction parsing in extensions looks like this: ARMAsmParser::ParseInstruction(...) { //... if (Token == EndOfStatement) { // finish parse instruction } } In a case of your suggestion fix will look like this: ARMAsmParser::ParseInstruction(...) { //... if (Token == EndOfStatement /*the fix: */ && Token == EOF) { // finish parse instruction } } I think that for AsmParser extensions EOF means also End-Of-Statment. So probably it will be more comfortable for them to see the EndOfStatement first and only after it EOF? Stepan 09.09.2011, 20:22, "James Molloy" : > Hi, > > Wouldn't it be better to fix the parsers themselves to handle EOF correctly? I > find it slightly unintuitive to have EOF cause two tokens to be emitted - > EndOfStatement and EOF. > > Or is this not practicable for some reason? > > Cheers, > > James > >> ?-----Original Message----- >> ?From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits- >> ?bounces at cs.uiuc.edu] On Behalf Of Stepan Dyatkovskiy >> ?Sent: 09 September 2011 14:05 >> ?To: llvm-commits at cs.uiuc.edu >> ?Subject: Re: [llvm-commits] [LLVM, llvm-mc] bugfix for bug #10869: Unclear >> ?error for files without newline at the end of file (ARM, x86). >> >> ?ping... >> >> ?P.S: >> ?I reattached the patch. In a case of some problems with previous >> ?attachment downloading, use this one. Thats why I used another email >> ?account. >> >> ?07.09.2011, 03:44, "Stepan Dyatkovskiy" : >>> ?Hello everyone, >>> >>> ?Please find attached a patch for review. >>> ?It fixes bug #10869 and adds a regression test for it. >>> >>> ?Best regards, >>> ?Stepan. >>> >>> ?_______________________________________________ >>> ?llvm-commits mailing list >>> ?llvm-commits at cs.uiuc.edu >>> ?http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Mon Sep 12 13:09:13 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 12 Sep 2011 11:09:13 -0700 Subject: [llvm-commits] [PATCH] Rename LLVM_MULTITHREADED define and fix build without threads In-Reply-To: References: Message-ID: On Aug 31, 2011, at 5:06 AM, arrowdodger wrote: > On Sat, Aug 6, 2011 at 2:21 PM, arrowdodger <6yearold at gmail.com> wrote: > Hi, there is LLVM_MULTITHREADED define which is actually indicates presence of atomic builtins in the host system. Such name may confuse developers in future and already confused someone at lib/Support/Threading.cpp - he used this define to check whether LLVM is built with threading support. This mistake is currently blocking single-threaded build on Unix. > > This patch do following things: > 1. Rename LLVM_MULTITHREADED to LLVM_HAVE_ATOMICS in CMake checking code and configure.ac, fix description of this option. > 2. Replaces all uses of old define with new one. > 3. Fix lib/Support/Threading.cpp file by using ENABLE_THREADS define instead of LLVM_MULTITHREADED. > > Ping. > _______________________________________________ Sorry for the delay. In general the patch is fine, could you change these couple of things? LLVM_HAVE_ATOMICS -> LLVM_HAS_ATOMICS and -#if LLVM_MULTITHREADED==0 +#if LLVM_HAVE_ATOMICS==0 || !defined(LLVM_HAVE_ATOMICS) to just #if LLVM_HAS_ATOMICS this latter is ok because we define it either way so there's always a value at least as far as the autoconf bits are concerned. If this isn't true for the cmake bits let me know. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110912/e4e7cc43/attachment.html From dpatel at apple.com Mon Sep 12 13:26:08 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 12 Sep 2011 18:26:08 -0000 Subject: [llvm-commits] [llvm] r139515 - /llvm/trunk/lib/Analysis/DIBuilder.cpp Message-ID: <20110912182608.C8B092A6C12C@llvm.org> Author: dpatel Date: Mon Sep 12 13:26:08 2011 New Revision: 139515 URL: http://llvm.org/viewvc/llvm-project?rev=139515&view=rev Log: Add asserts to keep front-ends honest while encoding debug info into LLVM IR using DIBuilder. Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=139515&r1=139514&r2=139515&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DIBuilder.cpp (original) +++ llvm/trunk/lib/Analysis/DIBuilder.cpp Mon Sep 12 13:26:08 2011 @@ -76,6 +76,10 @@ StringRef Directory, StringRef Producer, bool isOptimized, StringRef Flags, unsigned RunTimeVer) { + assert (Lang <= dwarf::DW_LANG_D && Lang >= dwarf::DW_LANG_C89 + && "Invalid Language tag"); + assert (!Filename.empty() + && "Unable to create compile unit without filename"); Value *TElts[] = { GetTagConstant(VMContext, DW_TAG_base_type) }; TempEnumTypes = MDNode::getTemporary(VMContext, TElts); Value *THElts[] = { TempEnumTypes }; @@ -121,6 +125,7 @@ /// for a file. DIFile DIBuilder::createFile(StringRef Filename, StringRef Directory) { assert(TheCU && "Unable to create DW_TAG_file_type without CompileUnit"); + assert(!Filename.empty() && "Unable to create file without name"); Value *Elts[] = { GetTagConstant(VMContext, dwarf::DW_TAG_file_type), MDString::get(VMContext, Filename), @@ -132,6 +137,7 @@ /// createEnumerator - Create a single enumerator value. DIEnumerator DIBuilder::createEnumerator(StringRef Name, uint64_t Val) { + assert(!Name.empty() && "Unable to create enumerator without name"); Value *Elts[] = { GetTagConstant(VMContext, dwarf::DW_TAG_enumerator), MDString::get(VMContext, Name), @@ -145,6 +151,7 @@ DIType DIBuilder::createBasicType(StringRef Name, uint64_t SizeInBits, uint64_t AlignInBits, unsigned Encoding) { + assert(!Name.empty() && "Unable to create type without name"); // Basic types are encoded in DIBasicType format. Line number, filename, // offset and flags are always empty here. Value *Elts[] = { @@ -202,6 +209,7 @@ /// createReferenceType - Create debugging information entry for a reference. DIType DIBuilder::createReferenceType(DIType RTy) { + assert(RTy.Verify() && "Unable to create reference type"); // References are encoded in DIDerivedType format. Value *Elts[] = { GetTagConstant(VMContext, dwarf::DW_TAG_reference_type), @@ -262,6 +270,7 @@ /// inheritnace relationship between two types. DIType DIBuilder::createInheritance(DIType Ty, DIType BaseTy, uint64_t BaseOffset, unsigned Flags) { + assert(Ty.Verify() && "Unable to create inheritance"); // TAG_inheritance is encoded in DIDerivedType format. Value *Elts[] = { GetTagConstant(VMContext, dwarf::DW_TAG_inheritance), From atrick at apple.com Mon Sep 12 13:28:44 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 12 Sep 2011 18:28:44 -0000 Subject: [llvm-commits] [llvm] r139517 - in /llvm/trunk: lib/Transforms/Scalar/ test/Transforms/IndVarSimplify/ test/Transforms/LoopUnroll/ Message-ID: <20110912182844.A20DE2A6C12C@llvm.org> Author: atrick Date: Mon Sep 12 13:28:44 2011 New Revision: 139517 URL: http://llvm.org/viewvc/llvm-project?rev=139517&view=rev Log: Rename -disable-iv-rewrite to -enable-iv-rewrite=false in preparation for default change. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll llvm/trunk/test/Transforms/IndVarSimplify/iv-fold.ll llvm/trunk/test/Transforms/IndVarSimplify/iv-zext.ll llvm/trunk/test/Transforms/IndVarSimplify/lftr-reuse.ll llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll llvm/trunk/test/Transforms/IndVarSimplify/preserve-signed-wrap.ll llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll llvm/trunk/test/Transforms/LoopUnroll/2011-08-09-IVSimplify.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=139517&r1=139516&r2=139517&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Sep 12 13:28:44 2011 @@ -11,17 +11,6 @@ // computations derived from them) into simpler forms suitable for subsequent // analysis and transformation. // -// Additionally, unless -disable-iv-rewrite is on, this transformation makes the -// following changes to each loop with an identifiable induction variable: -// 1. All loops are transformed to have a SINGLE canonical induction variable -// which starts at zero and steps by one. -// 2. The canonical induction variable is guaranteed to be the first PHI node -// in the loop header block. -// 3. The canonical induction variable is guaranteed to be in a wide enough -// type so that IV expressions need not be (directly) zero-extended or -// sign-extended. -// 4. Any pointer arithmetic recurrences are raised to use array subscripts. -// // If the trip count of a loop is computable, this pass also makes the following // changes: // 1. The exit condition for the loop is canonicalized to compare the @@ -33,9 +22,6 @@ // purpose of the loop is to compute the exit value of some derived // expression, this transformation will make the loop dead. // -// This transformation should be followed by strength reduction after all of the -// desired loop transformations have been performed. -// //===----------------------------------------------------------------------===// #define DEBUG_TYPE "indvars" @@ -73,9 +59,9 @@ STATISTIC(NumElimIV , "Number of congruent IVs eliminated"); namespace llvm { - cl::opt DisableIVRewrite( - "disable-iv-rewrite", cl::Hidden, - cl::desc("Disable canonical induction variable rewriting")); + cl::opt EnableIVRewrite( + "enable-iv-rewrite", cl::Hidden, cl::init(true), + cl::desc("Enable canonical induction variable rewriting")); // Trip count verification can be enabled by default under NDEBUG if we // implement a strong expression equivalence checker in SCEV. Until then, we @@ -85,12 +71,6 @@ cl::desc("Verify the ScalarEvolution result after running indvars")); } -// Temporary flag for use with -disable-iv-rewrite to force a canonical IV for -// LFTR purposes. -static cl::opt ForceLFTR( - "force-lftr", cl::Hidden, - cl::desc("Enable forced linear function test replacement")); - namespace { class IndVarSimplify : public LoopPass { IVUsers *IU; @@ -117,12 +97,12 @@ AU.addRequired(); AU.addRequiredID(LoopSimplifyID); AU.addRequiredID(LCSSAID); - if (!DisableIVRewrite) + if (EnableIVRewrite) AU.addRequired(); AU.addPreserved(); AU.addPreservedID(LoopSimplifyID); AU.addPreservedID(LCSSAID); - if (!DisableIVRewrite) + if (EnableIVRewrite) AU.addPreserved(); AU.setPreservesCFG(); } @@ -618,7 +598,7 @@ //===----------------------------------------------------------------------===// // Rewrite IV users based on a canonical IV. -// To be replaced by -disable-iv-rewrite. +// Only for use with -enable-iv-rewrite. //===----------------------------------------------------------------------===// /// FIXME: It is an extremely bad idea to indvar substitute anything more @@ -1333,7 +1313,7 @@ } } - if (!DisableIVRewrite || ForceLFTR) + if (EnableIVRewrite) return false; // Recurse past add expressions, which commonly occur in the @@ -1610,10 +1590,9 @@ assert(canExpandBackedgeTakenCount(L, SE) && "precondition"); BranchInst *BI = cast(L->getExitingBlock()->getTerminator()); - // In DisableIVRewrite mode, IndVar is not necessarily a canonical IV. In this - // mode, LFTR can ignore IV overflow and truncate to the width of + // LFTR can ignore IV overflow and truncate to the width of // BECount. This avoids materializing the add(zext(add)) expression. - Type *CntTy = DisableIVRewrite ? + Type *CntTy = !EnableIVRewrite ? BackedgeTakenCount->getType() : IndVar->getType(); const SCEV *IVLimit = BackedgeTakenCount; @@ -1663,7 +1642,7 @@ const SCEV *IVInit = AR->getStart(); // For pointer types, sign extend BECount in order to materialize a GEP. - // Note that for DisableIVRewrite, we never run SCEVExpander on a + // Note that for without EnableIVRewrite, we never run SCEVExpander on a // pointer type, because we must preserve the existing GEPs. Instead we // directly generate a GEP later. if (IVInit->getType()->isPointerTy()) { @@ -1841,7 +1820,7 @@ if (!L->isLoopSimplifyForm()) return false; - if (!DisableIVRewrite) + if (EnableIVRewrite) IU = &getAnalysis(); LI = &getAnalysis(); SE = &getAnalysis(); @@ -1866,7 +1845,7 @@ // attempt to avoid evaluating SCEVs for sign/zero extend operations until // other expressions involving loop IVs have been evaluated. This helps SCEV // set no-wrap flags before normalizing sign/zero extension. - if (DisableIVRewrite) { + if (!EnableIVRewrite) { Rewriter.disableCanonicalMode(); SimplifyAndExtend(L, Rewriter, LPM); } @@ -1881,26 +1860,25 @@ RewriteLoopExitValues(L, Rewriter); // Eliminate redundant IV users. - if (!DisableIVRewrite) + if (EnableIVRewrite) Changed |= simplifyIVUsers(IU, SE, &LPM, DeadInsts); // Eliminate redundant IV cycles. - if (DisableIVRewrite) + if (!EnableIVRewrite) SimplifyCongruentIVs(L); // Compute the type of the largest recurrence expression, and decide whether // a canonical induction variable should be inserted. Type *LargestType = 0; bool NeedCannIV = false; - bool ReuseIVForExit = DisableIVRewrite && !ForceLFTR; bool ExpandBECount = canExpandBackedgeTakenCount(L, SE); - if (ExpandBECount && !ReuseIVForExit) { + if (EnableIVRewrite && ExpandBECount) { // If we have a known trip count and a single exit block, we'll be // rewriting the loop exit test condition below, which requires a // canonical induction variable. NeedCannIV = true; Type *Ty = BackedgeTakenCount->getType(); - if (DisableIVRewrite) { + if (!EnableIVRewrite) { // In this mode, SimplifyIVUsers may have already widened the IV used by // the backedge test and inserted a Trunc on the compare's operand. Get // the wider type to avoid creating a redundant narrow IV only used by the @@ -1912,7 +1890,7 @@ SE->getTypeSizeInBits(LargestType)) LargestType = SE->getEffectiveSCEVType(Ty); } - if (!DisableIVRewrite) { + if (EnableIVRewrite) { for (IVUsers::const_iterator I = IU->begin(), E = IU->end(); I != E; ++I) { NeedCannIV = true; Type *Ty = @@ -1957,7 +1935,7 @@ OldCannIV->insertBefore(L->getHeader()->getFirstInsertionPt()); } } - else if (ExpandBECount && ReuseIVForExit && needsLFTR(L, DT)) { + else if (!EnableIVRewrite && ExpandBECount && needsLFTR(L, DT)) { IndVar = FindLoopCounter(L, BackedgeTakenCount, SE, DT, TD); } // If we have a trip count expression, rewrite the loop's exit condition @@ -1978,7 +1956,7 @@ LinearFunctionTestReplace(L, BackedgeTakenCount, IndVar, Rewriter); } // Rewrite IV-derived expressions. - if (!DisableIVRewrite) + if (EnableIVRewrite) RewriteIVExpressions(L, Rewriter); // Clear the rewriter cache, because values that are in the rewriter's cache @@ -2015,7 +1993,7 @@ // Verify that LFTR, and any other change have not interfered with SCEV's // ability to compute trip count. #ifndef NDEBUG - if (DisableIVRewrite && VerifyIndvars && + if (!EnableIVRewrite && VerifyIndvars && !isa(BackedgeTakenCount)) { SE->forgetLoop(L); const SCEV *NewBECount = SE->getBackedgeTakenCount(L); Modified: llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll?rev=139517&r1=139516&r2=139517&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll Mon Sep 12 13:28:44 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s +; RUN: opt < %s -indvars -enable-iv-rewrite=false -S | FileCheck %s ; Test WidenIV::GetExtendedOperandRecurrence. ; add219 should be extended to i64 because it is nsw, even though its ; sext cannot be hoisted outside the loop. Modified: llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll?rev=139517&r1=139516&r2=139517&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll Mon Sep 12 13:28:44 2011 @@ -1,5 +1,5 @@ ; RUN: opt < %s -indvars -S | FileCheck %s -; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s +; RUN: opt < %s -indvars -enable-iv-rewrite=false -S | FileCheck %s ; ; PR1301 Modified: llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll?rev=139517&r1=139516&r2=139517&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll Mon Sep 12 13:28:44 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s +; RUN: opt < %s -indvars -enable-iv-rewrite=false -S | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" Modified: llvm/trunk/test/Transforms/IndVarSimplify/iv-fold.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/iv-fold.ll?rev=139517&r1=139516&r2=139517&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/iv-fold.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/iv-fold.ll Mon Sep 12 13:28:44 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s +; RUN: opt < %s -indvars -enable-iv-rewrite=false -S | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n:32:64" Modified: llvm/trunk/test/Transforms/IndVarSimplify/iv-zext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/iv-zext.ll?rev=139517&r1=139516&r2=139517&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/iv-zext.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/iv-zext.ll Mon Sep 12 13:28:44 2011 @@ -1,5 +1,5 @@ ; RUN: opt < %s -indvars -S | FileCheck %s -; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s +; RUN: opt < %s -indvars -enable-iv-rewrite=false -S | FileCheck %s ; CHECK-NOT: and ; CHECK-NOT: zext Modified: llvm/trunk/test/Transforms/IndVarSimplify/lftr-reuse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/lftr-reuse.ll?rev=139517&r1=139516&r2=139517&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/lftr-reuse.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/lftr-reuse.ll Mon Sep 12 13:28:44 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s +; RUN: opt < %s -indvars -enable-iv-rewrite=false -S | FileCheck %s ; ; Make sure that indvars can perform LFTR without a canonical IV. Modified: llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll?rev=139517&r1=139516&r2=139517&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Mon Sep 12 13:28:44 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s +; RUN: opt < %s -indvars -enable-iv-rewrite=false -S | FileCheck %s ; ; Make sure that indvars isn't inserting canonical IVs. ; This is kinda hard to do until linear function test replacement is removed. Modified: llvm/trunk/test/Transforms/IndVarSimplify/preserve-signed-wrap.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/preserve-signed-wrap.ll?rev=139517&r1=139516&r2=139517&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/preserve-signed-wrap.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/preserve-signed-wrap.ll Mon Sep 12 13:28:44 2011 @@ -1,5 +1,5 @@ ; RUN: opt < %s -indvars -S | FileCheck %s -; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s +; RUN: opt < %s -indvars -enable-iv-rewrite=false -S | FileCheck %s ; Indvars should insert a 64-bit induction variable to eliminate the ; sext for the addressing, however it shouldn't eliminate the sext Modified: llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll?rev=139517&r1=139516&r2=139517&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll Mon Sep 12 13:28:44 2011 @@ -1,5 +1,5 @@ ; RUN: opt < %s -indvars -instcombine -S | FileCheck %s -; RUN: opt < %s -indvars -disable-iv-rewrite -instcombine -S | FileCheck %s +; RUN: opt < %s -indvars -enable-iv-rewrite=false -instcombine -S | FileCheck %s ; ; Test that -indvars can reduce variable stride IVs. If it can reduce variable ; stride iv's, it will make %iv. and %m.0.0 isomorphic to each other without Modified: llvm/trunk/test/Transforms/LoopUnroll/2011-08-09-IVSimplify.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnroll/2011-08-09-IVSimplify.ll?rev=139517&r1=139516&r2=139517&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LoopUnroll/2011-08-09-IVSimplify.ll (original) +++ llvm/trunk/test/Transforms/LoopUnroll/2011-08-09-IVSimplify.ll Mon Sep 12 13:28:44 2011 @@ -1,4 +1,4 @@ -; RUN: opt -S < %s -loop-unroll -unroll-count=4 -disable-iv-rewrite | FileCheck %s +; RUN: opt -S < %s -loop-unroll -unroll-count=4 -enable-iv-rewrite=false | FileCheck %s ; ; Test induction variable simplify after loop unrolling. It should ; expose nice opportunities for GVN. From atrick at apple.com Mon Sep 12 13:33:08 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 12 Sep 2011 18:33:08 -0000 Subject: [llvm-commits] [llvm] r139518 - in /llvm/trunk/test/Transforms/IndVarSimplify: 2003-09-12-MultiplePred.ll 2003-12-21-IndVarSize.ll max-pointer.ll pointer-indvars.ll pointer.ll subtract.ll Message-ID: <20110912183308.4D5E42A6C12C@llvm.org> Author: atrick Date: Mon Sep 12 13:33:08 2011 New Revision: 139518 URL: http://llvm.org/viewvc/llvm-project?rev=139518&view=rev Log: Removing indvars tests that directly test canonical IVs and nothing else. Removed: llvm/trunk/test/Transforms/IndVarSimplify/2003-09-12-MultiplePred.ll llvm/trunk/test/Transforms/IndVarSimplify/2003-12-21-IndVarSize.ll llvm/trunk/test/Transforms/IndVarSimplify/max-pointer.ll llvm/trunk/test/Transforms/IndVarSimplify/pointer-indvars.ll llvm/trunk/test/Transforms/IndVarSimplify/pointer.ll llvm/trunk/test/Transforms/IndVarSimplify/subtract.ll Removed: llvm/trunk/test/Transforms/IndVarSimplify/2003-09-12-MultiplePred.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2003-09-12-MultiplePred.ll?rev=139517&view=auto ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/2003-09-12-MultiplePred.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/2003-09-12-MultiplePred.ll (removed) @@ -1,15 +0,0 @@ -; RUN: opt < %s -indvars -S | grep indvar - -define i32 @test() { -;