From zwarich at apple.com Mon Sep 26 00:11:15 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Sun, 25 Sep 2011 22:11:15 -0700 Subject: [llvm-commits] [PATCH] Fix PR11004: Crash in llc arm backend In-Reply-To: References: <30A02F8B-795B-4AA3-BAC8-83DEACF90A0F@apple.com> <42E83160-1E33-430C-8E3F-715567B46C4A@apple.com> <47AE444F-E4A6-491C-907E-5746A9A4187C@apple.com> Message-ID: <79185C84-95D4-4C41-A6E6-558BB5D9995B@apple.com> On Sep 25, 2011, at 5:45 PM, David Meyer wrote: > Cameron, > > With regards to your comment that it is inconsiderate to break the tree intentionally, you are forgetting that this was an experimental feature that never worked outside of small test cases. Neither Clang nor llvm-gcc will generate byval on ARM, so it gets no real testing. It might be more considerate to users to just add an assert saying that ARM byval doesn't work. > > I dislike the idea of selective IR support. This creates a hidden (undocumented) contract between the frontends and backends, which limits the IR that is valid. It also treats external producers of bitcode as second-class citizens, since they must effectively mimic Clang or DragonEgg to guarantee that their output will be supported. It is nicer if every backend can handle any valid bitcode (even if doing so is not terribly efficient). I dislike it too, but be warned that there are other things that just plain aren't supported by the ARM backend, e.g. arbitrary vector types. > If there are no more objections, I'll commit, and un-XFAIL the tests which now pass. > (2011-06-09-TailCallByVal.ll and 2010-11-04-BigByval.ll) No objections from me. Cameron -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110925/66ab3b92/attachment.html From craig.topper at gmail.com Mon Sep 26 00:12:43 2011 From: craig.topper at gmail.com (Craig Topper) Date: Mon, 26 Sep 2011 05:12:43 -0000 Subject: [llvm-commits] [llvm] r140515 - in /llvm/trunk: lib/Target/X86/Disassembler/X86DisassemblerDecoder.c test/MC/Disassembler/X86/x86-32.txt Message-ID: <20110926051243.A7E6E2A6C12C@llvm.org> Author: ctopper Date: Mon Sep 26 00:12:43 2011 New Revision: 140515 URL: http://llvm.org/viewvc/llvm-project?rev=140515&view=rev Log: Fix VEX decoding in i386 mode. Fixes PR11008. Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c?rev=140515&r1=140514&r2=140515&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c (original) +++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c Mon Sep 26 00:12:43 2011 @@ -391,7 +391,7 @@ return -1; } - if (insn->mode == MODE_64BIT || byte1 & 0x8) { + if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) { insn->vexSize = 3; insn->necessaryPrefixLocation = insn->readerCursor - 1; } @@ -433,7 +433,7 @@ return -1; } - if (insn->mode == MODE_64BIT || byte1 & 0x8) { + if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) { insn->vexSize = 2; } else { Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=140515&r1=140514&r2=140515&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original) +++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Mon Sep 26 00:12:43 2011 @@ -30,3 +30,292 @@ # CHECK: crc32w %ax, %eax 0x66 0xf2 0x0f 0x38 0xf1 0xc0 + + +# CHECK: int $33 +0xCD 0x21 + +# CHECK: int $33 +0xCD 0x21 + + +# CHECK: addb %al, (%eax) +0 0 + +# CHECK: calll -1234 +0xe8 0x2e 0xfb 0xff 0xff + +# CHECK: lfence +0x0f 0xae 0xe8 + +# CHECK: mfence +0x0f 0xae 0xf0 + +# CHECK: monitor +0x0f 0x01 0xc8 + +# CHECK: mwait +0x0f 0x01 0xc9 + +# CHECK: vmcall +0x0f 0x01 0xc1 + +# CHECK: vmlaunch +0x0f 0x01 0xc2 + +# CHECK: vmresume +0x0f 0x01 0xc3 + +# CHECK: vmxoff +0x0f 0x01 0xc4 + +# CHECK: swapgs +0x0f 0x01 0xf8 + +# CHECK: rdtscp +0x0f 0x01 0xf9 + +# CHECK: vmxon +0xf3 0x0f 0xc7 0x30 + +# CHECK: vmptrld +0x0f 0xc7 0x30 + +# CHECK: vmptrst +0x0f 0xc7 0x38 + +# CHECK: movl $0, -4(%ebp) +0xc7 0x45 0xfc 0x00 0x00 0x00 0x00 + +# CHECK: movl %cr0, %ecx +0x0f 0x20 0xc1 + +# CHECK: leal 4(%esp), %ecx +0x8d 0x4c 0x24 0x04 + +# CHECK: enter $1, $2 +0xc8 0x01 0x00 0x02 + +# CHECK: movw $47416, -66(%ebp) +0x66 0xc7 0x45 0xbe 0x38 0xb9 + +# CHECK: vaddpd %ymm13, %ymm1, %ymm0 +0xc4 0xc1 0x75 0x58 0xc5 + +# CHECK: vaddps %ymm3, %ymm1, %ymm0 +0xc5 0xf4 0x58 0xc3 + +# CHECK: vandpd %ymm13, %ymm1, %ymm0 +0xc4 0xc1 0x75 0x54 0xc5 + +# CHECK: vandps %ymm3, %ymm1, %ymm0 +0xc5 0xf4 0x54 0xc3 + +# CHECK: vzeroall +0xc5 0xfc 0x77 + +# CHECK: vcvtps2pd %xmm0, %ymm0 +0xc5 0xfc 0x5a 0xc0 + +# CHECK: vandps (%edx), %xmm1, %xmm7 +0xc5 0xf0 0x54 0x3a + +# CHECK: vcvtss2sil %xmm0, %eax +0xc5 0xfa 0x2d 0xc0 + +# CHECK: vcvtsd2si %xmm0, %eax +0xc5 0xfb 0x2d 0xc0 + +# CHECK: vcvtsd2si %xmm0, %rax +0xc4 0xe1 0xfb 0x2d 0xc0 + +# CHECK: vmaskmovpd %xmm0, %xmm1, (%eax) +0xc4 0xe2 0x71 0x2f 0x00 + +# CHECK: vmovapd %xmm0, %xmm2 +0xc5 0xf9 0x28 0xd0 + +# Check these special case instructions that the immediate is not sign-extend. +# CHECK: blendps $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x0c 0xca 0x81 + +# CHECK: blendpd $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x0d 0xca 0x81 + +# CHECK: pblendw $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x0e 0xca 0x81 + +# CHECK: mpsadbw $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x42 0xca 0x81 + +# CHECK: dpps $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x40 0xca 0x81 + +# CHECK: dppd $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x41 0xca 0x81 + +# CHECK: insertps $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x21 0xca 0x81 + +# CHECK: vblendps $129, %ymm2, %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0c 0xca 0x81 + +# CHECK: vblendps $129, (%eax), %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0c 0x08 0x81 + +# CHECK: vblendpd $129, %ymm2, %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0d 0xca 0x81 + +# CHECK: vblendpd $129, (%eax), %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0d 0x08 0x81 + +# CHECK: vpblendw $129, %xmm2, %xmm5, %xmm1 +0xc4 0xe3 0x51 0x0e 0xca 0x81 + +# CHECK: vmpsadbw $129, %xmm2, %xmm5, %xmm1 +0xc4 0xe3 0x51 0x42 0xca 0x81 + +# CHECK: vdpps $129, %ymm2, %ymm5, %ymm1 +0xc4 0xe3 0x55 0x40 0xca 0x81 + +# CHECK: vdpps $129, (%eax), %ymm5, %ymm1 +0xc4 0xe3 0x55 0x40 0x08 0x81 + +# CHECK: vdppd $129, %xmm2, %xmm5, %xmm1 +0xc4 0xe3 0x51 0x41 0xca 0x81 + +# CHECK: vinsertps $129, %xmm3, %xmm2, %xmm1 +0xc4 0xe3 0x69 0x21 0xcb 0x81 + +# CHECK: pause +0xf3 0x90 + +# CHECK: addl %eax, %edi +0x01 0xc7 + +# CHECK: addl %edi, %eax +0x03 0xc7 + +# CHECK: movl %eax, %edi +0x89 0xc7 + +# CHECK: movl %edi, %eax +0x8b 0xc7 + +# CHECK: movups %xmm1, %xmm0 +0x0f 0x10 0xc1 + +# CHECK: movups %xmm0, %xmm1 +0x0f 0x11 0xc1 + +# CHECK: movaps %xmm1, %xmm0 +0x0f 0x28 0xc1 + +# CHECK: movaps %xmm0, %xmm1 +0x0f 0x29 0xc1 + +# CHECK: movupd %xmm1, %xmm0 +0x66 0x0f 0x10 0xc1 + +# CHECK: movupd %xmm0, %xmm1 +0x66 0x0f 0x11 0xc1 + +# CHECK: movapd %xmm1, %xmm0 +0x66 0x0f 0x28 0xc1 + +# CHECK: movapd %xmm0, %xmm1 +0x66 0x0f 0x29 0xc1 + +# CHECK: vmovups %xmm1, %xmm0 +0xc5 0xf8 0x10 0xc1 + +# CHECK: vmovups %xmm0, %xmm1 +0xc5 0xf8 0x11 0xc1 + +# CHECK: vmovaps %xmm1, %xmm0 +0xc5 0xf8 0x28 0xc1 + +# CHECK: vmovaps %xmm0, %xmm1 +0xc5 0xf8 0x29 0xc1 + +# CHECK: vmovupd %xmm1, %xmm0 +0xc5 0xf9 0x10 0xc1 + +# CHECK: vmovupd %xmm0, %xmm1 +0xc5 0xf9 0x11 0xc1 + +# CHECK: vmovapd %xmm1, %xmm0 +0xc5 0xf9 0x28 0xc1 + +# CHECK: vmovapd %xmm0, %xmm1 +0xc5 0xf9 0x29 0xc1 + +# CHECK: vmovups %ymm1, %ymm0 +0xc5 0xfc 0x10 0xc1 + +# CHECK: vmovups %ymm0, %ymm1 +0xc5 0xfc 0x11 0xc1 + +# CHECK: vmovaps %ymm1, %ymm0 +0xc5 0xfc 0x28 0xc1 + +# CHECK: vmovaps %ymm0, %ymm1 +0xc5 0xfc 0x29 0xc1 + +# CHECK: movdqa %xmm1, %xmm0 +0x66 0x0f 0x6f 0xc1 + +# CHECK: movdqa %xmm0, %xmm1 +0x66 0x0f 0x7f 0xc1 + +# CHECK: movdqu %xmm1, %xmm0 +0xf3 0x0f 0x6f 0xc1 + +# CHECK: movdqu %xmm0, %xmm1 +0xf3 0x0f 0x7f 0xc1 + +# CHECK: vmovdqa %xmm1, %xmm0 +0xc5 0xf9 0x6f 0xc1 + +# CHECK: vmovdqa %xmm0, %xmm1 +0xc5 0xf9 0x7f 0xc1 + +# CHECK: vmovdqa %ymm1, %ymm0 +0xc5 0xfd 0x6f 0xc1 + +# CHECK: vmovdqa %ymm0, %ymm1 +0xc5 0xfd 0x7f 0xc1 + +# CHECK: vmovdqu %xmm1, %xmm0 +0xc5 0xfa 0x6f 0xc1 + +# CHECK: vmovdqu %xmm0, %xmm1 +0xc5 0xfa 0x7f 0xc1 + +# CHECK: vmovdqu %ymm1, %ymm0 +0xc5 0xfe 0x6f 0xc1 + +# CHECK: vmovdqu %ymm0, %ymm1 +0xc5 0xfe 0x7f 0xc1 + +# CHECK: vblendvps %xmm4, %xmm1, %xmm2, %xmm3 +0xc4 0xe3 0x69 0x4a 0xd9 0x41 + +# CHECK: vroundpd $0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x09 0xc0 0x00 + +# CHECK: vroundps $0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x08 0xc0 0x00 + +# CHECK: vroundpd $0, %ymm0, %ymm0 +0xc4 0xe3 0x7d 0x09 0xc0 0x00 + +# CHECK: vroundps $0, %ymm0, %ymm0 +0xc4 0xe3 0x7d 0x08 0xc0 0x00 + +# CHECK: vroundss $0, %xmm0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x0a 0xc0 0x00 + +# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x0b 0xc0 0x00 + From pdox at google.com Mon Sep 26 01:13:20 2011 From: pdox at google.com (David Meyer) Date: Mon, 26 Sep 2011 06:13:20 -0000 Subject: [llvm-commits] [llvm] r140516 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2011-06-09-TailCallByVal.ll test/CodeGen/Generic/2010-11-04-BigByval.ll Message-ID: <20110926061320.7B4632A6C12C@llvm.org> Author: pdox Date: Mon Sep 26 01:13:20 2011 New Revision: 140516 URL: http://llvm.org/viewvc/llvm-project?rev=140516&view=rev Log: PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=140516&r1=140515&r2=140516&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Sep 26 01:13:20 2011 @@ -1340,10 +1340,12 @@ SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset); SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, MVT::i32); + // TODO: Disable AlwaysInline when it becomes possible + // to emit a nested call sequence. MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), /*isVolatile=*/false, - /*AlwaysInline=*/false, + /*AlwaysInline=*/true, MachinePointerInfo(0), MachinePointerInfo(0))); Modified: llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll?rev=140516&r1=140515&r2=140516&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll Mon Sep 26 01:13:20 2011 @@ -1,8 +1,4 @@ -; DISABLED: llc < %s -relocation-model=pic -mcpu=cortex-a8 -arm-tail-calls=1 | FileCheck %s -; RUN: false - -; byval is currently unsupported. -; XFAIL: * +; RUN: llc < %s -relocation-model=pic -mcpu=cortex-a8 -arm-tail-calls=1 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10" Modified: llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll?rev=140516&r1=140515&r2=140516&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll Mon Sep 26 01:13:20 2011 @@ -1,6 +1,5 @@ ; RUN: llc < %s ; PR7170 -; XFAIL: arm %big = type [131072 x i8] From pdox at google.com Mon Sep 26 01:44:27 2011 From: pdox at google.com (David Meyer) Date: Mon, 26 Sep 2011 06:44:27 -0000 Subject: [llvm-commits] [llvm] r140517 - /llvm/trunk/test/CodeGen/CBackend/X86/dg.exp Message-ID: <20110926064427.743B02A6C12C@llvm.org> Author: pdox Date: Mon Sep 26 01:44:27 2011 New Revision: 140517 URL: http://llvm.org/viewvc/llvm-project?rev=140517&view=rev Log: Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported Modified: llvm/trunk/test/CodeGen/CBackend/X86/dg.exp Modified: llvm/trunk/test/CodeGen/CBackend/X86/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/X86/dg.exp?rev=140517&r1=140516&r2=140517&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CBackend/X86/dg.exp (original) +++ llvm/trunk/test/CodeGen/CBackend/X86/dg.exp Mon Sep 26 01:44:27 2011 @@ -1,5 +1,5 @@ load_lib llvm.exp -if { [llvm_supports_target X86] } { +if { [llvm_supports_target X86] && [llvm_supports_target CBackend] } { RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp,s}]] } From James.Molloy at arm.com Mon Sep 26 02:04:35 2011 From: James.Molloy at arm.com (James Molloy) Date: Mon, 26 Sep 2011 08:04:35 +0100 Subject: [llvm-commits] [PATCH] Fix PR11004: Crash in llc arm backend In-Reply-To: <79185C84-95D4-4C41-A6E6-558BB5D9995B@apple.com> References: <30A02F8B-795B-4AA3-BAC8-83DEACF90A0F@apple.com> <42E83160-1E33-430C-8E3F-715567B46C4A@apple.com> <47AE444F-E4A6-491C-907E-5746A9A4187C@apple.com> <79185C84-95D4-4C41-A6E6-558BB5D9995B@apple.com> Message-ID: Hi Cameron, My testing found most obvious vector types to be supported in codegen (<{1,2,3,4,8,16,32,64} x {float,i8,16,i32,i64}>) - were there any types in particular that aren't supported? Cheers, James From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Cameron Zwarich Sent: 26 September 2011 06:11 To: David Meyer Cc: Commit Messages and Patches for LLVM Subject: Re: [llvm-commits] [PATCH] Fix PR11004: Crash in llc arm backend On Sep 25, 2011, at 5:45 PM, David Meyer wrote: Cameron, With regards to your comment that it is inconsiderate to break the tree intentionally, you are forgetting that this was an experimental feature that never worked outside of small test cases. Neither Clang nor llvm-gcc will generate byval on ARM, so it gets no real testing. It might be more considerate to users to just add an assert saying that ARM byval doesn't work. I dislike the idea of selective IR support. This creates a hidden (undocumented) contract between the frontends and backends, which limits the IR that is valid. It also treats external producers of bitcode as second-class citizens, since they must effectively mimic Clang or DragonEgg to guarantee that their output will be supported. It is nicer if every backend can handle any valid bitcode (even if doing so is not terribly efficient). I dislike it too, but be warned that there are other things that just plain aren't supported by the ARM backend, e.g. arbitrary vector types. If there are no more objections, I'll commit, and un-XFAIL the tests which now pass. (2011-06-09-TailCallByVal.ll and 2010-11-04-BigByval.ll) No objections from me. Cameron -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110926/4cf83034/attachment.html From zwarich at apple.com Mon Sep 26 02:16:51 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Mon, 26 Sep 2011 00:16:51 -0700 Subject: [llvm-commits] [PATCH] Fix PR11004: Crash in llc arm backend In-Reply-To: References: <30A02F8B-795B-4AA3-BAC8-83DEACF90A0F@apple.com> <42E83160-1E33-430C-8E3F-715567B46C4A@apple.com> <47AE444F-E4A6-491C-907E-5746A9A4187C@apple.com> <79185C84-95D4-4C41-A6E6-558BB5D9995B@apple.com> Message-ID: The obvious ones work, but something like 113 x i396 does not. Cameron On Sep 26, 2011, at 12:04 AM, James Molloy wrote: > Hi Cameron, > > My testing found most obvious vector types to be supported in codegen (<{1,2,3,4,8,16,32,64} x {float,i8,16,i32,i64}>) ? were there any types in particular that aren?t supported? > > Cheers, > > James > > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Cameron Zwarich > Sent: 26 September 2011 06:11 > To: David Meyer > Cc: Commit Messages and Patches for LLVM > Subject: Re: [llvm-commits] [PATCH] Fix PR11004: Crash in llc arm backend > > On Sep 25, 2011, at 5:45 PM, David Meyer wrote: > > > Cameron, > > With regards to your comment that it is inconsiderate to break the tree intentionally, you are forgetting that this was an experimental feature that never worked outside of small test cases. Neither Clang nor llvm-gcc will generate byval on ARM, so it gets no real testing. It might be more considerate to users to just add an assert saying that ARM byval doesn't work. > > I dislike the idea of selective IR support. This creates a hidden (undocumented) contract between the frontends and backends, which limits the IR that is valid. It also treats external producers of bitcode as second-class citizens, since they must effectively mimic Clang or DragonEgg to guarantee that their output will be supported. It is nicer if every backend can handle any valid bitcode (even if doing so is not terribly efficient). > > I dislike it too, but be warned that there are other things that just plain aren't supported by the ARM backend, e.g. arbitrary vector types. > > > If there are no more objections, I'll commit, and un-XFAIL the tests which now pass. > (2011-06-09-TailCallByVal.ll and 2010-11-04-BigByval.ll) > > No objections from me. > > Cameron > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110926/34c7e3f2/attachment-0001.html From James.Molloy at arm.com Mon Sep 26 02:17:32 2011 From: James.Molloy at arm.com (James Molloy) Date: Mon, 26 Sep 2011 08:17:32 +0100 Subject: [llvm-commits] [PATCH] Fix PR11004: Crash in llc arm backend In-Reply-To: References: <30A02F8B-795B-4AA3-BAC8-83DEACF90A0F@apple.com> <42E83160-1E33-430C-8E3F-715567B46C4A@apple.com> <47AE444F-E4A6-491C-907E-5746A9A4187C@apple.com> <79185C84-95D4-4C41-A6E6-558BB5D9995B@apple.com> Message-ID: Ah, I see. Well that's fine then. From: Cameron Zwarich [mailto:zwarich at apple.com] Sent: 26 September 2011 08:17 To: James Molloy Cc: David Meyer; Commit Messages and Patches for LLVM Subject: Re: [llvm-commits] [PATCH] Fix PR11004: Crash in llc arm backend The obvious ones work, but something like 113 x i396 does not. Cameron On Sep 26, 2011, at 12:04 AM, James Molloy wrote: Hi Cameron, My testing found most obvious vector types to be supported in codegen (<{1,2,3,4,8,16,32,64} x {float,i8,16,i32,i64}>) - were there any types in particular that aren't supported? Cheers, James From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Cameron Zwarich Sent: 26 September 2011 06:11 To: David Meyer Cc: Commit Messages and Patches for LLVM Subject: Re: [llvm-commits] [PATCH] Fix PR11004: Crash in llc arm backend On Sep 25, 2011, at 5:45 PM, David Meyer wrote: Cameron, With regards to your comment that it is inconsiderate to break the tree intentionally, you are forgetting that this was an experimental feature that never worked outside of small test cases. Neither Clang nor llvm-gcc will generate byval on ARM, so it gets no real testing. It might be more considerate to users to just add an assert saying that ARM byval doesn't work. I dislike the idea of selective IR support. This creates a hidden (undocumented) contract between the frontends and backends, which limits the IR that is valid. It also treats external producers of bitcode as second-class citizens, since they must effectively mimic Clang or DragonEgg to guarantee that their output will be supported. It is nicer if every backend can handle any valid bitcode (even if doing so is not terribly efficient). I dislike it too, but be warned that there are other things that just plain aren't supported by the ARM backend, e.g. arbitrary vector types. If there are no more objections, I'll commit, and un-XFAIL the tests which now pass. (2011-06-09-TailCallByVal.ll and 2010-11-04-BigByval.ll) No objections from me. Cameron -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110926/12b170aa/attachment.html From baldrick at free.fr Mon Sep 26 03:54:18 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 26 Sep 2011 10:54:18 +0200 Subject: [llvm-commits] [llvm] r140471 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp In-Reply-To: <20110925185942.9C6582A6C12C@llvm.org> References: <20110925185942.9C6582A6C12C@llvm.org> Message-ID: <4E803DBA.7080606@free.fr> Hi Nadav, > [vector-select] Address one of the issues in pr10902. EXTRACT_VECTOR_ELEMENT > SDNodes may return values which are wider than the incoming element types. In > this patch we fix the integer promotion of these nodes. > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sun Sep 25 13:59:42 2011 > @@ -2987,8 +2987,13 @@ > SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, > V0->getValueType(0).getScalarType(), V0, V1); > > - return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext); > - > + // EXTRACT_VECTOR_ELT can return types which are wider than the incoming > + // element types (see PromoteIntRes_EXTRACT_VECTOR_ELT). If this is the case this is already explained in ISDOpcodes.h, so that would be a better place to refer to. But given that the very place that defines EXTRACT_VECTOR_ELT talks about this, I think you can just drop the "(see XYZ") cross-reference. > + // then we need to expand the outgoing value and not truncate it. > + bool trunc = (N->getValueType(0).getSizeInBits()< > + Ext.getValueType().getSizeInBits()); > + return DAG.getNode(trunc ? ISD::TRUNCATE : ISD::ANY_EXTEND, > + dl, N->getValueType(0), Ext); I suggest you add a method getAnyExtOrTrunc to go along with the existing getSExtOrTrunc and getZExtOrTrunc methods, and use that instead. Ciao, Duncan. From baldrick at free.fr Mon Sep 26 04:07:27 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 26 Sep 2011 11:07:27 +0200 Subject: [llvm-commits] [llvm] r140464 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp In-Reply-To: <20110924194819.7822A2A6C12C@llvm.org> References: <20110924194819.7822A2A6C12C@llvm.org> Message-ID: <4E8040CF.2010101@free.fr> Hi Nadav, > Implement Duncan's suggestion to use the result of getSetCCResultType if it is legal > (this is always the case for scalars), otherwise use the promoted result type. > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sat Sep 24 14:48:19 2011 > @@ -503,8 +503,15 @@ > > SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { > EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); > - // Vector setcc result types need to be leglized. > - SVT = TLI.getTypeToTransformTo(*DAG.getContext(), SVT); > + > + // Convert to the expected type. This comment doesn't make any sense here. Better to have left it where it was. > + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); > + > + // Only use the result of getSetCCResultType if it is legal, > + // otherwise just use the promoted result type (NVT). > + if (getTypeAction(SVT) != TargetLowering::TypeLegal) { Simpler: TLI.isTypeLegal(SVT) > + SVT = NVT; > + } No need for curly brackets {}. Ciao, Duncan. From baldrick at free.fr Mon Sep 26 07:21:07 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 26 Sep 2011 12:21:07 -0000 Subject: [llvm-commits] [dragonegg] r140527 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110926122107.7C0382A6C12C@llvm.org> Author: baldrick Date: Mon Sep 26 07:21:07 2011 New Revision: 140527 URL: http://llvm.org/viewvc/llvm-project?rev=140527&view=rev Log: Don't crash on ABS_EXPR with a 128 bit floating point operand. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=140527&r1=140526&r2=140527&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Mon Sep 26 07:21:07 2011 @@ -124,7 +124,8 @@ } /// SelectFPName - Helper for choosing a name depending on whether a floating -/// point type is float, double or long double. +/// point type is float, double or long double. Returns an empty string for +/// other types, such as the x86 128 bit floating point type. static StringRef SelectFPName(tree type, StringRef FloatName, StringRef DoubleName, StringRef LongDoubleName) { assert(SCALAR_FLOAT_TYPE_P(type) && "Expected a floating point type!"); @@ -132,9 +133,9 @@ return FloatName; if (TYPE_MODE(type) == TYPE_MODE(double_type_node)) return DoubleName; - assert(TYPE_MODE(type) == TYPE_MODE(long_double_type_node) && - "Unknown floating point type!"); - return LongDoubleName; + if (TYPE_MODE(type) == TYPE_MODE(long_double_type_node)) + return LongDoubleName; + return StringRef(); } @@ -4607,6 +4608,7 @@ // First call the appropriate version of "ceil". tree op = gimple_call_arg(stmt, 0); StringRef Name = SelectFPName(TREE_TYPE(op), "ceilf", "ceil", "ceill"); + assert(!Name.empty() && "Unsupported floating point type!"); CallInst *Call = EmitSimpleCall(Name, TREE_TYPE(op), op, NULL); Call->setDoesNotThrow(); Call->setDoesNotAccessMemory(); @@ -4626,6 +4628,7 @@ // First call the appropriate version of "floor". tree op = gimple_call_arg(stmt, 0); StringRef Name = SelectFPName(TREE_TYPE(op), "floorf", "floor", "floorl"); + assert(!Name.empty() && "Unsupported floating point type!"); CallInst *Call = EmitSimpleCall(Name, TREE_TYPE(op), op, NULL); Call->setDoesNotThrow(); Call->setDoesNotAccessMemory(); @@ -4647,6 +4650,7 @@ tree arg = gimple_call_arg(stmt, 0); tree arg_type = TREE_TYPE(arg); StringRef Name = SelectFPName(arg_type, "sincosf", "sincos", "sincosl"); + assert(!Name.empty() && "Unsupported floating point type!"); // Create stack slots to store the real (cos) and imaginary (sin) parts in. Value *Val = EmitRegister(arg); @@ -4693,6 +4697,7 @@ tree arg = gimple_call_arg(stmt, 0); tree arg_type = TREE_TYPE(arg); StringRef Name = SelectFPName(arg_type, "cexpf", "cexp", "cexpl"); + assert(!Name.empty() && "Unsupported floating point type!"); // Get the GCC and LLVM function types for cexp. tree cplx_type = gimple_call_return_type(stmt); @@ -6275,7 +6280,9 @@ Value *Cmp = Builder.CreateICmp(pred, Op, Constant::getNullValue(Op->getType()), "abscond"); return Builder.CreateSelect(Cmp, Op, OpN, Op->getName()+"abs"); - } else if (TREE_CODE(TREE_TYPE(op)) == VECTOR_TYPE) { + } + + if (TREE_CODE(TREE_TYPE(op)) == VECTOR_TYPE) { // Clear the sign bits. Value *Op = EmitRegister(op); VectorType *VecTy = cast(Op->getType()); @@ -6297,10 +6304,29 @@ // Turn FP abs into fabs/fabsf. StringRef Name = SelectFPName(TREE_TYPE(op), "fabsf", "fabs", "fabsl"); - CallInst *Call = EmitSimpleCall(Name, TREE_TYPE(op), op, NULL); - Call->setDoesNotThrow(); - Call->setDoesNotAccessMemory(); - return Call; + if (!Name.empty()) { + CallInst *Call = EmitSimpleCall(Name, TREE_TYPE(op), op, NULL); + Call->setDoesNotThrow(); + Call->setDoesNotAccessMemory(); + return Call; + } + + // Otherwise clear the sign bit. + Value *Op = EmitRegister(op); + Type *Ty = Op->getType(); + + // Mask = ~(1 << (Bits-1)). + unsigned Bits = Ty->getPrimitiveSizeInBits(); + Type *IntTy = IntegerType::get(Context, Bits); + APInt API = APInt::getAllOnesValue(Bits); + API.clearBit(Bits-1); + Constant *Mask = ConstantInt::get(IntTy, API); + + // Zap the sign bit. + Op = Builder.CreateBitCast(Op, IntTy); + Op = Builder.CreateAnd(Op, Mask); + Op = Builder.CreateBitCast(Op, Ty); + return Op; } Value *TreeToLLVM::EmitReg_BIT_NOT_EXPR(tree op) { From James.Molloy at arm.com Mon Sep 26 11:03:49 2011 From: James.Molloy at arm.com (James Molloy) Date: Mon, 26 Sep 2011 17:03:49 +0100 Subject: [llvm-commits] [PATCH] Fix emission of debug data for global variables Message-ID: Hi, With the new debug information changes, global variables aren't emitted properly to DWARF. The DW_AT_decl_file field is incorrect. This stems from DwarfCompileUnit.cpp:138: unsigned FileID = DD->GetOrCreateSourceID(G.getContext().getFilename(), G.getContext().getDirectory()); G.getContext() returns a NULL metadatum for the new metadata format (it used to return the CompileUnit). This causes a new SourceID to be generated for the "null" file, and the global is assigned this incorrect SourceID. Attached is a testcase and proposed patch. It inlines getFilename() and getDirectory() into DIGlobalVariable, returning the original getContext().getFilename() for old versions of the debug info and getFieldAs(6).getFilename() for new versions. I've implemented it this way so that the old code path is identical to before. I'm not sure if this is the most perfect fix - as getFieldAs(6) is valid (seemingly) for all debug info versions, perhaps the best idea would be to remove the conditionalization and always return getFieldAs(6).getFilename/getDirectory() ? Cheers, James -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -------------- next part -------------- A non-text attachment was scrubbed... Name: 2011-09-26-GlobalVarContext.patch Type: application/octet-stream Size: 4836 bytes Desc: 2011-09-26-GlobalVarContext.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110926/97849988/attachment.obj From patrik.h.hagglund at ericsson.com Mon Sep 26 05:42:54 2011 From: patrik.h.hagglund at ericsson.com (=?iso-8859-1?Q?Patrik_H=E4gglund_H?=) Date: Mon, 26 Sep 2011 12:42:54 +0200 Subject: [llvm-commits] [PATCH] avoid substituting -clang in lit Message-ID: I tried to build in a subdirectory 'build-clang'. That made 'make check' fail: /local/scratch/uabpath/master/build-clang/test/BugPoint/Output/metadata.ll.script: line 2: /local/scratch/uabpath/master/build-/local/scratch/uabpath/master/build-clang/Debug+Asserts/bin/clang/Debug+Asserts/bin/bugpoint: No such file or directory Here is a patch: diff --git a/test/lit.cfg b/test/lit.cfg index c588efa..85f54d8 100644 --- a/test/lit.cfg +++ b/test/lit.cfg @@ -177,12 +177,12 @@ for sub in ['llvmgcc', 'llvmgxx', 'emitir', 'compile_cxx', 'compile_c', # includes every tool placed in $(LLVM_OBJ_ROOT)/$(BuildMode)/bin # (llvm_tools_dir in lit parlance). # Don't match 'bugpoint-' or 'clang-'. - # Don't match '/clang'. + # Don't match '/clang' or '-clang'. if os.pathsep == ';': pathext = os.environ.get('PATHEXT', '').split(';') else: pathext = [''] -for pattern in [r"\bbugpoint\b(?!-)", r"(? Author: jholewinski Date: Mon Sep 26 11:20:36 2011 New Revision: 140536 URL: http://llvm.org/viewvc/llvm-project?rev=140536&view=rev Log: PTX: SM > 2.0 implies +double Modified: llvm/trunk/lib/Target/PTX/PTX.td Modified: llvm/trunk/lib/Target/PTX/PTX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.td?rev=140536&r1=140535&r2=140536&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTX.td (original) +++ llvm/trunk/lib/Target/PTX/PTX.td Mon Sep 26 11:20:36 2011 @@ -52,13 +52,13 @@ def FeatureSM13 : SubtargetFeature<"sm13", "PTXTarget", "PTX_SM_1_3", "Use Shader Model 1.3">; def FeatureSM20 : SubtargetFeature<"sm20", "PTXTarget", "PTX_SM_2_0", - "Use Shader Model 2.0">; + "Use Shader Model 2.0", [FeatureDouble]>; def FeatureSM21 : SubtargetFeature<"sm21", "PTXTarget", "PTX_SM_2_1", - "Use Shader Model 2.1">; + "Use Shader Model 2.1", [FeatureDouble]>; def FeatureSM22 : SubtargetFeature<"sm22", "PTXTarget", "PTX_SM_2_2", - "Use Shader Model 2.2">; + "Use Shader Model 2.2", [FeatureDouble]>; def FeatureSM23 : SubtargetFeature<"sm23", "PTXTarget", "PTX_SM_2_3", - "Use Shader Model 2.3">; + "Use Shader Model 2.3", [FeatureDouble]>; def FeatureCOMPUTE10 : SubtargetFeature<"compute10", "PTXTarget", "PTX_COMPUTE_1_0", @@ -74,7 +74,8 @@ "Use Compute Compatibility 1.3">; def FeatureCOMPUTE20 : SubtargetFeature<"compute20", "PTXTarget", "PTX_COMPUTE_2_0", - "Use Compute Compatibility 2.0">; + "Use Compute Compatibility 2.0", + [FeatureDouble]>; //===----------------------------------------------------------------------===// // PTX supported processors From justin.holewinski at gmail.com Mon Sep 26 11:20:31 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Mon, 26 Sep 2011 16:20:31 -0000 Subject: [llvm-commits] [llvm] r140534 - in /llvm/trunk/lib/Target/PTX: PTXInstrInfo.cpp PTXInstrInfo.td PTXInstrLoadStore.td Message-ID: <20110926162031.E5E182A6C12E@llvm.org> Author: jholewinski Date: Mon Sep 26 11:20:31 2011 New Revision: 140534 URL: http://llvm.org/viewvc/llvm-project?rev=140534&view=rev Log: PTX: Split up the TableGen instruction definitions into logical units Added: llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=140534&r1=140533&r2=140534&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Mon Sep 26 11:20:31 2011 @@ -302,34 +302,7 @@ unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - MachineInstr& MI = *MII; - DebugLoc DL = MI.getDebugLoc(); - - DEBUG(dbgs() << "storeRegToStackSlot: " << MI); - - int OpCode; - - // Select the appropriate opcode based on the register class - if (RC == PTX::RegI16RegisterClass) { - OpCode = PTX::STACKSTOREI16; - } else if (RC == PTX::RegI32RegisterClass) { - OpCode = PTX::STACKSTOREI32; - } else if (RC == PTX::RegI64RegisterClass) { - OpCode = PTX::STACKSTOREI32; - } else if (RC == PTX::RegF32RegisterClass) { - OpCode = PTX::STACKSTOREF32; - } else if (RC == PTX::RegF64RegisterClass) { - OpCode = PTX::STACKSTOREF64; - } else { - llvm_unreachable("Unknown PTX register class!"); - } - - // Build the store instruction (really a mov) - MachineInstrBuilder MIB = BuildMI(MBB, MII, DL, get(OpCode)); - MIB.addFrameIndex(FrameIdx); - MIB.addReg(SrcReg); - - AddDefaultPredicate(MIB); + assert(false && "storeRegToStackSlot should not be called for PTX"); } void PTXInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, @@ -337,34 +310,7 @@ unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - MachineInstr& MI = *MII; - DebugLoc DL = MI.getDebugLoc(); - - DEBUG(dbgs() << "loadRegToStackSlot: " << MI); - - int OpCode; - - // Select the appropriate opcode based on the register class - if (RC == PTX::RegI16RegisterClass) { - OpCode = PTX::STACKLOADI16; - } else if (RC == PTX::RegI32RegisterClass) { - OpCode = PTX::STACKLOADI32; - } else if (RC == PTX::RegI64RegisterClass) { - OpCode = PTX::STACKLOADI32; - } else if (RC == PTX::RegF32RegisterClass) { - OpCode = PTX::STACKLOADF32; - } else if (RC == PTX::RegF64RegisterClass) { - OpCode = PTX::STACKLOADF64; - } else { - llvm_unreachable("Unknown PTX register class!"); - } - - // Build the load instruction (really a mov) - MachineInstrBuilder MIB = BuildMI(MBB, MII, DL, get(OpCode)); - MIB.addReg(DestReg); - MIB.addFrameIndex(FrameIdx); - - AddDefaultPredicate(MIB); + assert(false && "loadRegFromStackSlot should not be called for PTX"); } // static helper routines Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=140534&r1=140533&r2=140534&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Mon Sep 26 11:20:31 2011 @@ -21,10 +21,6 @@ // Code Generation Predicates //===----------------------------------------------------------------------===// -// Addressing -def Use32BitAddresses : Predicate<"!getSubtarget().is64Bit()">; -def Use64BitAddresses : Predicate<"getSubtarget().is64Bit()">; - // Shader Model Support def FDivNeedsRoundingMode : Predicate<"getSubtarget().fdivNeedsRoundingMode()">; def FDivNoRoundingMode : Predicate<"!getSubtarget().fdivNeedsRoundingMode()">; @@ -43,136 +39,7 @@ def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">; def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">; -//===----------------------------------------------------------------------===// -// Instruction Pattern Stuff -//===----------------------------------------------------------------------===// -def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - const Value *Src; - const PointerType *PT; - const SDValue &MemOp = N->getOperand(1); - if ((MemOp.getOpcode() != ISD::FrameIndex) && - (Src = cast(N)->getSrcValue()) && - (PT = dyn_cast(Src->getType()))) - return PT->getAddressSpace() == PTX::GLOBAL; - return false; -}]>; - -def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - const Value *Src; - const PointerType *PT; - if ((Src = cast(N)->getSrcValue()) && - (PT = dyn_cast(Src->getType()))) - return PT->getAddressSpace() == PTX::CONSTANT; - return false; -}]>; - -def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - const SDValue &MemOp = N->getOperand(1); - return MemOp.getOpcode() == ISD::FrameIndex; -}]>; - -def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - const Value *Src; - const PointerType *PT; - if ((Src = cast(N)->getSrcValue()) && - (PT = dyn_cast(Src->getType()))) - return PT->getAddressSpace() == PTX::PARAMETER; - return false; -}]>; - -def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - const Value *Src; - const PointerType *PT; - if ((Src = cast(N)->getSrcValue()) && - (PT = dyn_cast(Src->getType()))) - return PT->getAddressSpace() == PTX::SHARED; - return false; -}]>; - -def store_global - : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ - const Value *Src; - const PointerType *PT; - const SDValue &MemOp = N->getOperand(2); - if ((MemOp.getOpcode() != ISD::FrameIndex) && - (Src = cast(N)->getSrcValue()) && - (PT = dyn_cast(Src->getType()))) - return PT->getAddressSpace() == PTX::GLOBAL; - return false; -}]>; - -def store_local - : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ - const SDValue &MemOp = N->getOperand(2); - return MemOp.getOpcode() == ISD::FrameIndex; -}]>; - -def store_parameter - : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ - const Value *Src; - const PointerType *PT; - if ((Src = cast(N)->getSrcValue()) && - (PT = dyn_cast(Src->getType()))) - return PT->getAddressSpace() == PTX::PARAMETER; - return false; -}]>; - -def store_shared - : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ - const Value *Src; - const PointerType *PT; - if ((Src = cast(N)->getSrcValue()) && - (PT = dyn_cast(Src->getType()))) - return PT->getAddressSpace() == PTX::SHARED; - return false; -}]>; - -// Addressing modes. -def ADDRrr32 : ComplexPattern; -def ADDRrr64 : ComplexPattern; -def ADDRri32 : ComplexPattern; -def ADDRri64 : ComplexPattern; -def ADDRii32 : ComplexPattern; -def ADDRii64 : ComplexPattern; -def ADDRlocal32 : ComplexPattern; -def ADDRlocal64 : ComplexPattern; - -// Address operands -def MEMri32 : Operand { - let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops RegI32, i32imm); -} -def MEMri64 : Operand { - let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops RegI64, i64imm); -} -def LOCALri32 : Operand { - let PrintMethod = "printLocalOperand"; - let MIOperandInfo = (ops RegI32, i32imm); -} -def LOCALri64 : Operand { - let PrintMethod = "printLocalOperand"; - let MIOperandInfo = (ops RegI64, i64imm); -} -def MEMii32 : Operand { - let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops i32imm, i32imm); -} -def MEMii64 : Operand { - let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops i64imm, i64imm); -} -// The operand here does not correspond to an actual address, so we -// can use i32 in 64-bit address modes. -def MEMpi : Operand { - let PrintMethod = "printParamOperand"; - let MIOperandInfo = (ops i32imm); -} -def MEMret : Operand { - let PrintMethod = "printReturnOperand"; - let MIOperandInfo = (ops i32imm); -} // def SDT_PTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; // def SDT_PTXCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; @@ -207,20 +74,7 @@ def PTXcopyaddress : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>; -// Load/store .param space -def PTXloadparam - : SDNode<"PTXISD::LOAD_PARAM", SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>, - [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>; -def PTXstoreparam - : SDNode<"PTXISD::STORE_PARAM", SDTypeProfile<0, 2, [SDTCisVT<0, i32>]>, - [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>; - -def PTXreadparam - : SDNode<"PTXISD::READ_PARAM", SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>, - [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>; -def PTXwriteparam - : SDNode<"PTXISD::WRITE_PARAM", SDTypeProfile<0, 1, []>, - [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>; + //===----------------------------------------------------------------------===// // Instruction Class Templates @@ -576,104 +430,7 @@ [(set RC:$r, (select RegPred:$a, RC:$b, RC:$c))]>; } -multiclass PTX_LD { - def rr32 : InstPTX<(outs RC:$d), - (ins MEMri32:$a), - !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (pat_load ADDRrr32:$a))]>, - Requires<[Use32BitAddresses]>; - def rr64 : InstPTX<(outs RC:$d), - (ins MEMri64:$a), - !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (pat_load ADDRrr64:$a))]>, - Requires<[Use64BitAddresses]>; - def ri32 : InstPTX<(outs RC:$d), - (ins MEMri32:$a), - !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (pat_load ADDRri32:$a))]>, - Requires<[Use32BitAddresses]>; - def ri64 : InstPTX<(outs RC:$d), - (ins MEMri64:$a), - !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (pat_load ADDRri64:$a))]>, - Requires<[Use64BitAddresses]>; - def ii32 : InstPTX<(outs RC:$d), - (ins MEMii32:$a), - !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (pat_load ADDRii32:$a))]>, - Requires<[Use32BitAddresses]>; - def ii64 : InstPTX<(outs RC:$d), - (ins MEMii64:$a), - !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (pat_load ADDRii64:$a))]>, - Requires<[Use64BitAddresses]>; -} - -multiclass PTX_LOCAL_LD_ST { - def LDri32 : InstPTX<(outs RC:$d), (ins LOCALri32:$a), - !strconcat("ld.local", !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (load_local ADDRlocal32:$a))]>; - def LDri64 : InstPTX<(outs RC:$d), (ins LOCALri64:$a), - !strconcat("ld.local", !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (load_local ADDRlocal64:$a))]>; - def STri32 : InstPTX<(outs), (ins RC:$d, LOCALri32:$a), - !strconcat("st.local", !strconcat(typestr, "\t[$a], $d")), - [(store_local RC:$d, ADDRlocal32:$a)]>; - def STri64 : InstPTX<(outs), (ins RC:$d, LOCALri64:$a), - !strconcat("st.local", !strconcat(typestr, "\t[$a], $d")), - [(store_local RC:$d, ADDRlocal64:$a)]>; -} -multiclass PTX_LD_ALL { - defm u16 : PTX_LD; - defm u32 : PTX_LD; - defm u64 : PTX_LD; - defm f32 : PTX_LD; - defm f64 : PTX_LD; -} - -multiclass PTX_ST { - def rr32 : InstPTX<(outs), - (ins RC:$d, MEMri32:$a), - !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), - [(pat_store RC:$d, ADDRrr32:$a)]>, - Requires<[Use32BitAddresses]>; - def rr64 : InstPTX<(outs), - (ins RC:$d, MEMri64:$a), - !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), - [(pat_store RC:$d, ADDRrr64:$a)]>, - Requires<[Use64BitAddresses]>; - def ri32 : InstPTX<(outs), - (ins RC:$d, MEMri32:$a), - !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), - [(pat_store RC:$d, ADDRri32:$a)]>, - Requires<[Use32BitAddresses]>; - def ri64 : InstPTX<(outs), - (ins RC:$d, MEMri64:$a), - !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), - [(pat_store RC:$d, ADDRri64:$a)]>, - Requires<[Use64BitAddresses]>; - def ii32 : InstPTX<(outs), - (ins RC:$d, MEMii32:$a), - !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), - [(pat_store RC:$d, ADDRii32:$a)]>, - Requires<[Use32BitAddresses]>; - def ii64 : InstPTX<(outs), - (ins RC:$d, MEMii64:$a), - !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), - [(pat_store RC:$d, ADDRii64:$a)]>, - Requires<[Use64BitAddresses]>; -} - -multiclass PTX_ST_ALL { - defm u16 : PTX_ST; - defm u32 : PTX_ST; - defm u64 : PTX_ST; - defm f32 : PTX_ST; - defm f64 : PTX_ST; -} //===----------------------------------------------------------------------===// // Instructions @@ -921,85 +678,6 @@ [(set RegI64:$d, (PTXcopyaddress tglobaladdr:$a))]>; } -// Loads -defm LDg : PTX_LD_ALL<"ld.global", load_global>; -defm LDc : PTX_LD_ALL<"ld.const", load_constant>; -//defm LDl : PTX_LD_ALL<"ld.local", load_local>; -defm LDs : PTX_LD_ALL<"ld.shared", load_shared>; - -// These instructions are used to load/store from the .param space for -// device and kernel parameters - -let hasSideEffects = 1 in { - def LDpiPred : InstPTX<(outs RegPred:$d), (ins MEMpi:$a), - "ld.param.pred\t$d, [$a]", - [(set RegPred:$d, (PTXloadparam timm:$a))]>; - def LDpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a), - "ld.param.u16\t$d, [$a]", - [(set RegI16:$d, (PTXloadparam timm:$a))]>; - def LDpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a), - "ld.param.u32\t$d, [$a]", - [(set RegI32:$d, (PTXloadparam timm:$a))]>; - def LDpiU64 : InstPTX<(outs RegI64:$d), (ins MEMpi:$a), - "ld.param.u64\t$d, [$a]", - [(set RegI64:$d, (PTXloadparam timm:$a))]>; - def LDpiF32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a), - "ld.param.f32\t$d, [$a]", - [(set RegF32:$d, (PTXloadparam timm:$a))]>; - def LDpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a), - "ld.param.f64\t$d, [$a]", - [(set RegF64:$d, (PTXloadparam timm:$a))]>; - - def STpiPred : InstPTX<(outs), (ins MEMpi:$d, RegPred:$a), - "st.param.pred\t[$d], $a", - [(PTXstoreparam timm:$d, RegPred:$a)]>; - def STpiU16 : InstPTX<(outs), (ins MEMpi:$d, RegI16:$a), - "st.param.u16\t[$d], $a", - [(PTXstoreparam timm:$d, RegI16:$a)]>; - def STpiU32 : InstPTX<(outs), (ins MEMpi:$d, RegI32:$a), - "st.param.u32\t[$d], $a", - [(PTXstoreparam timm:$d, RegI32:$a)]>; - def STpiU64 : InstPTX<(outs), (ins MEMpi:$d, RegI64:$a), - "st.param.u64\t[$d], $a", - [(PTXstoreparam timm:$d, RegI64:$a)]>; - def STpiF32 : InstPTX<(outs), (ins MEMpi:$d, RegF32:$a), - "st.param.f32\t[$d], $a", - [(PTXstoreparam timm:$d, RegF32:$a)]>; - def STpiF64 : InstPTX<(outs), (ins MEMpi:$d, RegF64:$a), - "st.param.f64\t[$d], $a", - [(PTXstoreparam timm:$d, RegF64:$a)]>; -} - -/* - def ri64 : InstPTX<(outs RC:$d), - (ins MEMri64:$a), - !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (pat_load ADDRri64:$a))]>, - Requires<[Use64BitAddresses]>; - - def ri64 : InstPTX<(outs), - (ins RC:$d, MEMri64:$a), - !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), - [(pat_store RC:$d, ADDRri64:$a)]>, - Requires<[Use64BitAddresses]>; - */ - -// Stores -defm STg : PTX_ST_ALL<"st.global", store_global>; -//defm STl : PTX_ST_ALL<"st.local", store_local>; -defm STs : PTX_ST_ALL<"st.shared", store_shared>; - -defm LOCALPRED : PTX_LOCAL_LD_ST<".pred", RegPred>; -defm LOCALU16 : PTX_LOCAL_LD_ST<".u16", RegI16>; -defm LOCALU32 : PTX_LOCAL_LD_ST<".u32", RegI32>; -defm LOCALU64 : PTX_LOCAL_LD_ST<".u64", RegI64>; -defm LOCALF32 : PTX_LOCAL_LD_ST<".f32", RegF32>; -defm LOCALF64 : PTX_LOCAL_LD_ST<".f64", RegF64>; - - -// defm STp : PTX_ST_ALL<"st.param", store_parameter>; -// defm LDp : PTX_LD_ALL<"ld.param", load_parameter>; -// TODO: Do something with st.param if/when it is needed. // Conversion to pred // PTX does not directly support converting to a predicate type, so we fake it @@ -1195,31 +873,6 @@ def CALL : InstPTX<(outs), (ins), "call", [(PTXcall)]>; } - -///===- Spill Instructions ------------------------------------------------===// -// Special instructions used for stack spilling -def STACKSTOREI16 : InstPTX<(outs), (ins i32imm:$d, RegI16:$a), - "mov.u16\ts$d, $a", []>; -def STACKSTOREI32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a), - "mov.u32\ts$d, $a", []>; -def STACKSTOREI64 : InstPTX<(outs), (ins i32imm:$d, RegI64:$a), - "mov.u64\ts$d, $a", []>; -def STACKSTOREF32 : InstPTX<(outs), (ins i32imm:$d, RegF32:$a), - "mov.f32\ts$d, $a", []>; -def STACKSTOREF64 : InstPTX<(outs), (ins i32imm:$d, RegF64:$a), - "mov.f64\ts$d, $a", []>; - -def STACKLOADI16 : InstPTX<(outs), (ins RegI16:$d, i32imm:$a), - "mov.u16\t$d, s$a", []>; -def STACKLOADI32 : InstPTX<(outs), (ins RegI32:$d, i32imm:$a), - "mov.u32\t$d, s$a", []>; -def STACKLOADI64 : InstPTX<(outs), (ins RegI64:$d, i32imm:$a), - "mov.u64\t$d, s$a", []>; -def STACKLOADF32 : InstPTX<(outs), (ins RegF32:$d, i32imm:$a), - "mov.f32\t$d, s$a", []>; -def STACKLOADF64 : InstPTX<(outs), (ins RegF64:$d, i32imm:$a), - "mov.f64\t$d, s$a", []>; - ///===- Parameter Passing Pseudo-Instructions -----------------------------===// def READPARAMPRED : InstPTX<(outs RegPred:$a), (ins i32imm:$b), @@ -1242,19 +895,9 @@ def WRITEPARAMF32 : InstPTX<(outs), (ins RegF32:$a), "//w", []>; def WRITEPARAMF64 : InstPTX<(outs), (ins RegF64:$a), "//w", []>; -///===- Stack Variable Loads/Stores ---------------------------------------===// - -def LOAD_LOCAL_F32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a), - "ld.local.f32\t$d, [%a]", []>; - -// Call handling -// def ADJCALLSTACKUP : -// InstPTX<(outs), (ins i32imm:$amt1, i32imm:$amt2), "", -// [(PTXcallseq_end timm:$amt1, timm:$amt2)]>; -// def ADJCALLSTACKDOWN : -// InstPTX<(outs), (ins i32imm:$amt), "", -// [(PTXcallseq_start timm:$amt)]>; - ///===- Intrinsic Instructions --------------------------------------------===// - include "PTXIntrinsicInstrInfo.td" + +///===- Load/Store Instructions -------------------------------------------===// +include "PTXInstrLoadStore.td" + Added: llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td?rev=140534&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td (added) +++ llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td Mon Sep 26 11:20:31 2011 @@ -0,0 +1,293 @@ +//===- PTXInstrLoadStore.td - PTX Load/Store Instruction Defs -*- tblgen-*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the PTX load/store instructions in TableGen format. +// +//===----------------------------------------------------------------------===// + + +// Addressing Predicates +// We have to differentiate between 32- and 64-bit pointer types +def Use32BitAddresses : Predicate<"!getSubtarget().is64Bit()">; +def Use64BitAddresses : Predicate<"getSubtarget().is64Bit()">; + +//===----------------------------------------------------------------------===// +// Pattern Fragments for Loads/Stores +//===----------------------------------------------------------------------===// + +def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + const Value *Src; + const PointerType *PT; + const SDValue &MemOp = N->getOperand(1); + if ((MemOp.getOpcode() != ISD::FrameIndex) && + (Src = cast(N)->getSrcValue()) && + (PT = dyn_cast(Src->getType()))) + return PT->getAddressSpace() == PTX::GLOBAL; + return false; +}]>; + +def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + const Value *Src; + const PointerType *PT; + if ((Src = cast(N)->getSrcValue()) && + (PT = dyn_cast(Src->getType()))) + return PT->getAddressSpace() == PTX::CONSTANT; + return false; +}]>; + +def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + const SDValue &MemOp = N->getOperand(1); + return MemOp.getOpcode() == ISD::FrameIndex; +}]>; + +def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + const Value *Src; + const PointerType *PT; + if ((Src = cast(N)->getSrcValue()) && + (PT = dyn_cast(Src->getType()))) + return PT->getAddressSpace() == PTX::SHARED; + return false; +}]>; + +def store_global + : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ + const Value *Src; + const PointerType *PT; + const SDValue &MemOp = N->getOperand(2); + if ((MemOp.getOpcode() != ISD::FrameIndex) && + (Src = cast(N)->getSrcValue()) && + (PT = dyn_cast(Src->getType()))) + return PT->getAddressSpace() == PTX::GLOBAL; + return false; +}]>; + +def store_local + : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ + const SDValue &MemOp = N->getOperand(2); + return MemOp.getOpcode() == ISD::FrameIndex; +}]>; + +def store_shared + : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ + const Value *Src; + const PointerType *PT; + if ((Src = cast(N)->getSrcValue()) && + (PT = dyn_cast(Src->getType()))) + return PT->getAddressSpace() == PTX::SHARED; + return false; +}]>; + +// Addressing modes. +def ADDRrr32 : ComplexPattern; +def ADDRrr64 : ComplexPattern; +def ADDRri32 : ComplexPattern; +def ADDRri64 : ComplexPattern; +def ADDRii32 : ComplexPattern; +def ADDRii64 : ComplexPattern; +def ADDRlocal32 : ComplexPattern; +def ADDRlocal64 : ComplexPattern; + +// Address operands +def MEMri32 : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops RegI32, i32imm); +} +def MEMri64 : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops RegI64, i64imm); +} +def LOCALri32 : Operand { + let PrintMethod = "printLocalOperand"; + let MIOperandInfo = (ops RegI32, i32imm); +} +def LOCALri64 : Operand { + let PrintMethod = "printLocalOperand"; + let MIOperandInfo = (ops RegI64, i64imm); +} +def MEMii32 : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops i32imm, i32imm); +} +def MEMii64 : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops i64imm, i64imm); +} +// The operand here does not correspond to an actual address, so we +// can use i32 in 64-bit address modes. +def MEMpi : Operand { + let PrintMethod = "printParamOperand"; + let MIOperandInfo = (ops i32imm); +} +def MEMret : Operand { + let PrintMethod = "printReturnOperand"; + let MIOperandInfo = (ops i32imm); +} + + +// Load/store .param space +def PTXloadparam + : SDNode<"PTXISD::LOAD_PARAM", SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>; +def PTXstoreparam + : SDNode<"PTXISD::STORE_PARAM", SDTypeProfile<0, 2, [SDTCisVT<0, i32>]>, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>; + +def PTXreadparam + : SDNode<"PTXISD::READ_PARAM", SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>; +def PTXwriteparam + : SDNode<"PTXISD::WRITE_PARAM", SDTypeProfile<0, 1, []>, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>; + + + +//===----------------------------------------------------------------------===// +// Classes for loads/stores +//===----------------------------------------------------------------------===// +multiclass PTX_LD { + def rr32 : InstPTX<(outs RC:$d), + (ins MEMri32:$a), + !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (pat_load ADDRrr32:$a))]>, + Requires<[Use32BitAddresses]>; + def rr64 : InstPTX<(outs RC:$d), + (ins MEMri64:$a), + !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (pat_load ADDRrr64:$a))]>, + Requires<[Use64BitAddresses]>; + def ri32 : InstPTX<(outs RC:$d), + (ins MEMri32:$a), + !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (pat_load ADDRri32:$a))]>, + Requires<[Use32BitAddresses]>; + def ri64 : InstPTX<(outs RC:$d), + (ins MEMri64:$a), + !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (pat_load ADDRri64:$a))]>, + Requires<[Use64BitAddresses]>; + def ii32 : InstPTX<(outs RC:$d), + (ins MEMii32:$a), + !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (pat_load ADDRii32:$a))]>, + Requires<[Use32BitAddresses]>; + def ii64 : InstPTX<(outs RC:$d), + (ins MEMii64:$a), + !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (pat_load ADDRii64:$a))]>, + Requires<[Use64BitAddresses]>; +} + +multiclass PTX_ST { + def rr32 : InstPTX<(outs), + (ins RC:$d, MEMri32:$a), + !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), + [(pat_store RC:$d, ADDRrr32:$a)]>, + Requires<[Use32BitAddresses]>; + def rr64 : InstPTX<(outs), + (ins RC:$d, MEMri64:$a), + !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), + [(pat_store RC:$d, ADDRrr64:$a)]>, + Requires<[Use64BitAddresses]>; + def ri32 : InstPTX<(outs), + (ins RC:$d, MEMri32:$a), + !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), + [(pat_store RC:$d, ADDRri32:$a)]>, + Requires<[Use32BitAddresses]>; + def ri64 : InstPTX<(outs), + (ins RC:$d, MEMri64:$a), + !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), + [(pat_store RC:$d, ADDRri64:$a)]>, + Requires<[Use64BitAddresses]>; + def ii32 : InstPTX<(outs), + (ins RC:$d, MEMii32:$a), + !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), + [(pat_store RC:$d, ADDRii32:$a)]>, + Requires<[Use32BitAddresses]>; + def ii64 : InstPTX<(outs), + (ins RC:$d, MEMii64:$a), + !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), + [(pat_store RC:$d, ADDRii64:$a)]>, + Requires<[Use64BitAddresses]>; +} + +multiclass PTX_LOCAL_LD_ST { + def LDri32 : InstPTX<(outs RC:$d), (ins LOCALri32:$a), + !strconcat("ld.local", !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (load_local ADDRlocal32:$a))]>; + def LDri64 : InstPTX<(outs RC:$d), (ins LOCALri64:$a), + !strconcat("ld.local", !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (load_local ADDRlocal64:$a))]>; + def STri32 : InstPTX<(outs), (ins RC:$d, LOCALri32:$a), + !strconcat("st.local", !strconcat(typestr, "\t[$a], $d")), + [(store_local RC:$d, ADDRlocal32:$a)]>; + def STri64 : InstPTX<(outs), (ins RC:$d, LOCALri64:$a), + !strconcat("st.local", !strconcat(typestr, "\t[$a], $d")), + [(store_local RC:$d, ADDRlocal64:$a)]>; +} + +multiclass PTX_PARAM_LD_ST { + let hasSideEffects = 1 in { + def LDpi : InstPTX<(outs RC:$d), (ins MEMpi:$a), + !strconcat("ld.param", !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (PTXloadparam timm:$a))]>; + def STpi : InstPTX<(outs), (ins MEMpi:$d, RC:$a), + !strconcat("st.param", !strconcat(typestr, "\t[$d], $a")), + [(PTXstoreparam timm:$d, RC:$a)]>; + } +} + +multiclass PTX_LD_ALL { + defm u16 : PTX_LD; + defm u32 : PTX_LD; + defm u64 : PTX_LD; + defm f32 : PTX_LD; + defm f64 : PTX_LD; +} + +multiclass PTX_ST_ALL { + defm u16 : PTX_ST; + defm u32 : PTX_ST; + defm u64 : PTX_ST; + defm f32 : PTX_ST; + defm f64 : PTX_ST; +} + + + +//===----------------------------------------------------------------------===// +// Instruction definitions for loads/stores +//===----------------------------------------------------------------------===// + +// Global/shared stores +defm STg : PTX_ST_ALL<"st.global", store_global>; +defm STs : PTX_ST_ALL<"st.shared", store_shared>; + +// Global/shared/constant loads +defm LDg : PTX_LD_ALL<"ld.global", load_global>; +defm LDc : PTX_LD_ALL<"ld.const", load_constant>; +defm LDs : PTX_LD_ALL<"ld.shared", load_shared>; + +// Param loads/stores +defm PARAMPRED : PTX_PARAM_LD_ST<".pred", RegPred>; +defm PARAMU16 : PTX_PARAM_LD_ST<".u16", RegI16>; +defm PARAMU32 : PTX_PARAM_LD_ST<".u32", RegI32>; +defm PARAMU64 : PTX_PARAM_LD_ST<".u64", RegI64>; +defm PARAMF32 : PTX_PARAM_LD_ST<".f32", RegF32>; +defm PARAMF64 : PTX_PARAM_LD_ST<".f64", RegF64>; + +// Local loads/stores +defm LOCALPRED : PTX_LOCAL_LD_ST<".pred", RegPred>; +defm LOCALU16 : PTX_LOCAL_LD_ST<".u16", RegI16>; +defm LOCALU32 : PTX_LOCAL_LD_ST<".u32", RegI32>; +defm LOCALU64 : PTX_LOCAL_LD_ST<".u64", RegI64>; +defm LOCALF32 : PTX_LOCAL_LD_ST<".f32", RegF32>; +defm LOCALF64 : PTX_LOCAL_LD_ST<".f64", RegF64>; + From justin.holewinski at gmail.com Mon Sep 26 11:20:28 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Mon, 26 Sep 2011 16:20:28 -0000 Subject: [llvm-commits] [llvm] r140533 - in /llvm/trunk: lib/Target/PTX/PTXAsmPrinter.cpp lib/Target/PTX/PTXInstrInfo.td lib/Target/PTX/PTXRegisterInfo.cpp test/CodeGen/PTX/ld.ll test/CodeGen/PTX/st.ll Message-ID: <20110926162028.DA20E2A6C12D@llvm.org> Author: jholewinski Date: Mon Sep 26 11:20:28 2011 New Revision: 140533 URL: http://llvm.org/viewvc/llvm-project?rev=140533&view=rev Log: PTX: Unify handling of loads/stores Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/PTXInstrInfo.td llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp llvm/trunk/test/CodeGen/PTX/ld.ll llvm/trunk/test/CodeGen/PTX/st.ll Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140533&r1=140532&r2=140533&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Mon Sep 26 11:20:28 2011 @@ -68,6 +68,8 @@ const char *Modifier = 0); void printParamOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, const char *Modifier = 0); + void printLocalOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, + const char *Modifier = 0); void printReturnOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, const char *Modifier = 0); void printPredicateOperand(const MachineInstr *MI, raw_ostream &O); @@ -297,7 +299,7 @@ if (FrameInfo->getObjectSize(i) > 0) { std::string def = "\t.local .b"; def += utostr(FrameInfo->getObjectSize(i)*8); // Convert to bits - def += " __local_"; + def += " __local"; def += utostr(i); def += ";"; OutStreamer.EmitRawText(Twine(def)); @@ -458,6 +460,11 @@ OS << "__ret"; } +void PTXAsmPrinter::printLocalOperand(const MachineInstr *MI, int opNum, + raw_ostream &OS, const char *Modifier) { + OS << "__local" << MI->getOperand(opNum).getImm(); +} + void PTXAsmPrinter::EmitVariableDeclaration(const GlobalVariable *gv) { // Check to see if this is a special global used by LLVM, if so, emit it. if (EmitSpecialLLVMGlobal(gv)) Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=140533&r1=140532&r2=140533&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Mon Sep 26 11:20:28 2011 @@ -147,6 +147,14 @@ let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops RegI64, i64imm); } +def LOCALri32 : Operand { + let PrintMethod = "printLocalOperand"; + let MIOperandInfo = (ops RegI32, i32imm); +} +def LOCALri64 : Operand { + let PrintMethod = "printLocalOperand"; + let MIOperandInfo = (ops RegI64, i64imm); +} def MEMii32 : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops i32imm, i32imm); @@ -602,6 +610,21 @@ Requires<[Use64BitAddresses]>; } +multiclass PTX_LOCAL_LD_ST { + def LDri32 : InstPTX<(outs RC:$d), (ins LOCALri32:$a), + !strconcat("ld.local", !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (load_local ADDRlocal32:$a))]>; + def LDri64 : InstPTX<(outs RC:$d), (ins LOCALri64:$a), + !strconcat("ld.local", !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (load_local ADDRlocal64:$a))]>; + def STri32 : InstPTX<(outs), (ins RC:$d, LOCALri32:$a), + !strconcat("st.local", !strconcat(typestr, "\t[$a], $d")), + [(store_local RC:$d, ADDRlocal32:$a)]>; + def STri64 : InstPTX<(outs), (ins RC:$d, LOCALri64:$a), + !strconcat("st.local", !strconcat(typestr, "\t[$a], $d")), + [(store_local RC:$d, ADDRlocal64:$a)]>; +} + multiclass PTX_LD_ALL { defm u16 : PTX_LD; defm u32 : PTX_LD; @@ -960,86 +983,18 @@ [(pat_store RC:$d, ADDRri64:$a)]>, Requires<[Use64BitAddresses]>; */ -let hasSideEffects = 1 in { - def LDLOCALpiPred : InstPTX<(outs RegPred:$d), (ins MEMri32:$a), - "ld.local.pred\t$d, [__local_$a]", - [(set RegPred:$d, (load_local ADDRlocal32:$a))]>; - def LDLOCALpiU16 : InstPTX<(outs RegI16:$d), (ins MEMri32:$a), - "ld.local.u16\t$d, [__local_$a]", - [(set RegI16:$d, (load_local ADDRlocal32:$a))]>; - def LDLOCALpiU32 : InstPTX<(outs RegI32:$d), (ins MEMri32:$a), - "ld.local.u32\t$d, [__local_$a]", - [(set RegI32:$d, (load_local ADDRlocal32:$a))]>; - def LDLOCALpiU64 : InstPTX<(outs RegI64:$d), (ins MEMri32:$a), - "ld.local.u64\t$d, [__local_$a]", - [(set RegI64:$d, (load_local ADDRlocal32:$a))]>; - def LDLOCALpiF32 : InstPTX<(outs RegF32:$d), (ins MEMri32:$a), - "ld.local.f32\t$d, [__local_$a]", - [(set RegF32:$d, (load_local ADDRlocal32:$a))]>; - def LDLOCALpiF64 : InstPTX<(outs RegF64:$d), (ins MEMri32:$a), - "ld.local.f64\t$d, [__local_$a]", - [(set RegF64:$d, (load_local ADDRlocal32:$a))]>; - - def STLOCALpiPred : InstPTX<(outs), (ins RegPred:$d, MEMri32:$a), - "st.local.pred\t[__local_$a], $d", - [(store_local RegPred:$d, ADDRlocal32:$a)]>; - def STLOCALpiU16 : InstPTX<(outs), (ins RegI16:$d, MEMri32:$a), - "st.local.u16\t[__local_$a], $d", - [(store_local RegI16:$d, ADDRlocal32:$a)]>; - def STLOCALpiU32 : InstPTX<(outs), (ins RegI32:$d, MEMri32:$a), - "st.local.u32\t[__local_$a], $d", - [(store_local RegI32:$d, ADDRlocal32:$a)]>; - def STLOCALpiU64 : InstPTX<(outs), (ins RegI64:$d, MEMri32:$a), - "st.local.u64\t[__local_$a], $d", - [(store_local RegI64:$d, ADDRlocal32:$a)]>; - def STLOCALpiF32 : InstPTX<(outs), (ins RegF32:$d, MEMri32:$a), - "st.local.f32\t[__local_$a], $d", - [(store_local RegF32:$d, ADDRlocal32:$a)]>; - def STLOCALpiF64 : InstPTX<(outs), (ins RegF64:$d, MEMri32:$a), - "st.local.f64\t[__local_$a], $d", - [(store_local RegF64:$d, ADDRlocal32:$a)]>; - - /*def LDLOCALpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a), - "ld.param.u16\t$d, [$a]", - [(set RegI16:$d, (PTXloadparam timm:$a))]>; - def LDLOCALpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a), - "ld.param.u32\t$d, [$a]", - [(set RegI32:$d, (PTXloadparam timm:$a))]>; - def LDLOCALpiU64 : InstPTX<(outs RegI64:$d), (ins MEMpi:$a), - "ld.param.u64\t$d, [$a]", - [(set RegI64:$d, (PTXloadparam timm:$a))]>; - def LDLOCALpiF32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a), - "ld.param.f32\t$d, [$a]", - [(set RegF32:$d, (PTXloadparam timm:$a))]>; - def LDLOCALpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a), - "ld.param.f64\t$d, [$a]", - [(set RegF64:$d, (PTXloadparam timm:$a))]>; - - def STLOCALpiPred : InstPTX<(outs), (ins MEMpi:$d, RegPred:$a), - "st.param.pred\t[$d], $a", - [(PTXstoreparam timm:$d, RegPred:$a)]>; - def STLOCALpiU16 : InstPTX<(outs), (ins MEMpi:$d, RegI16:$a), - "st.param.u16\t[$d], $a", - [(PTXstoreparam timm:$d, RegI16:$a)]>; - def STLOCALpiU32 : InstPTX<(outs), (ins MEMpi:$d, RegI32:$a), - "st.param.u32\t[$d], $a", - [(PTXstoreparam timm:$d, RegI32:$a)]>; - def STLOCALpiU64 : InstPTX<(outs), (ins MEMpi:$d, RegI64:$a), - "st.param.u64\t[$d], $a", - [(PTXstoreparam timm:$d, RegI64:$a)]>; - def STLOCALpiF32 : InstPTX<(outs), (ins MEMpi:$d, RegF32:$a), - "st.param.f32\t[$d], $a", - [(PTXstoreparam timm:$d, RegF32:$a)]>; - def STLOCALpiF64 : InstPTX<(outs), (ins MEMpi:$d, RegF64:$a), - "st.param.f64\t[$d], $a", - [(PTXstoreparam timm:$d, RegF64:$a)]>;*/ -} // Stores defm STg : PTX_ST_ALL<"st.global", store_global>; //defm STl : PTX_ST_ALL<"st.local", store_local>; defm STs : PTX_ST_ALL<"st.shared", store_shared>; +defm LOCALPRED : PTX_LOCAL_LD_ST<".pred", RegPred>; +defm LOCALU16 : PTX_LOCAL_LD_ST<".u16", RegI16>; +defm LOCALU32 : PTX_LOCAL_LD_ST<".u32", RegI32>; +defm LOCALU64 : PTX_LOCAL_LD_ST<".u64", RegI64>; +defm LOCALF32 : PTX_LOCAL_LD_ST<".f32", RegF32>; +defm LOCALF64 : PTX_LOCAL_LD_ST<".f64", RegF64>; // defm STp : PTX_ST_ALL<"st.param", store_parameter>; Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp?rev=140533&r1=140532&r2=140533&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp Mon Sep 26 11:20:28 2011 @@ -65,5 +65,5 @@ // This frame index is post stack slot re-use assignments //MI.getOperand(Index).ChangeToRegister(Reg, false); - MI.getOperand(Index).ChangeToImmediate(0); + MI.getOperand(Index).ChangeToImmediate(FrameIndex); } Modified: llvm/trunk/test/CodeGen/PTX/ld.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/ld.ll?rev=140533&r1=140532&r2=140533&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/ld.ll (original) +++ llvm/trunk/test/CodeGen/PTX/ld.ll Mon Sep 26 11:20:28 2011 @@ -6,9 +6,6 @@ ;CHECK: .extern .const .b8 array_constant_i16[20]; @array_constant_i16 = external addrspace(1) constant [10 x i16] -;CHECK: .extern .local .b8 array_local_i16[20]; - at array_local_i16 = external addrspace(2) global [10 x i16] - ;CHECK: .extern .shared .b8 array_shared_i16[20]; @array_shared_i16 = external addrspace(4) global [10 x i16] @@ -18,9 +15,6 @@ ;CHECK: .extern .const .b8 array_constant_i32[40]; @array_constant_i32 = external addrspace(1) constant [10 x i32] -;CHECK: .extern .local .b8 array_local_i32[40]; - at array_local_i32 = external addrspace(2) global [10 x i32] - ;CHECK: .extern .shared .b8 array_shared_i32[40]; @array_shared_i32 = external addrspace(4) global [10 x i32] @@ -30,9 +24,6 @@ ;CHECK: .extern .const .b8 array_constant_i64[80]; @array_constant_i64 = external addrspace(1) constant [10 x i64] -;CHECK: .extern .local .b8 array_local_i64[80]; - at array_local_i64 = external addrspace(2) global [10 x i64] - ;CHECK: .extern .shared .b8 array_shared_i64[80]; @array_shared_i64 = external addrspace(4) global [10 x i64] @@ -42,9 +33,6 @@ ;CHECK: .extern .const .b8 array_constant_float[40]; @array_constant_float = external addrspace(1) constant [10 x float] -;CHECK: .extern .local .b8 array_local_float[40]; - at array_local_float = external addrspace(2) global [10 x float] - ;CHECK: .extern .shared .b8 array_shared_float[40]; @array_shared_float = external addrspace(4) global [10 x float] @@ -54,9 +42,6 @@ ;CHECK: .extern .const .b8 array_constant_double[80]; @array_constant_double = external addrspace(1) constant [10 x double] -;CHECK: .extern .local .b8 array_local_double[80]; - at array_local_double = external addrspace(2) global [10 x double] - ;CHECK: .extern .shared .b8 array_shared_double[80]; @array_shared_double = external addrspace(4) global [10 x double] @@ -296,56 +281,6 @@ ret double %x } -define ptx_device i16 @t4_local_u16() { -entry: -;CHECK: mov.u32 %r[[R0:[0-9]+]], array_local_i16; -;CHECK: ld.local.u16 %ret{{[0-9]+}}, [%r[[R0]]]; -;CHECK: ret; - %i = getelementptr [10 x i16] addrspace(2)* @array_local_i16, i32 0, i32 0 - %x = load i16 addrspace(2)* %i - ret i16 %x -} - -define ptx_device i32 @t4_local_u32() { -entry: -;CHECK: mov.u32 %r[[R0:[0-9]+]], array_local_i32; -;CHECK: ld.local.u32 %ret{{[0-9]+}}, [%r[[R0]]]; -;CHECK: ret; - %i = getelementptr [10 x i32] addrspace(2)* @array_local_i32, i32 0, i32 0 - %x = load i32 addrspace(2)* %i - ret i32 %x -} - -define ptx_device i64 @t4_local_u64() { -entry: -;CHECK: mov.u32 %r[[R0:[0-9]+]], array_local_i64; -;CHECK: ld.local.u64 %ret{{[0-9]+}}, [%r[[R0]]]; -;CHECK: ret; - %i = getelementptr [10 x i64] addrspace(2)* @array_local_i64, i32 0, i32 0 - %x = load i64 addrspace(2)* %i - ret i64 %x -} - -define ptx_device float @t4_local_f32() { -entry: -;CHECK: mov.u32 %r[[R0:[0-9]+]], array_local_float; -;CHECK: ld.local.f32 %ret{{[0-9]+}}, [%r[[R0]]]; -;CHECK: ret; - %i = getelementptr [10 x float] addrspace(2)* @array_local_float, i32 0, i32 0 - %x = load float addrspace(2)* %i - ret float %x -} - -define ptx_device double @t4_local_f64() { -entry: -;CHECK: mov.u32 %r[[R0:[0-9]+]], array_local_double; -;CHECK: ld.local.f64 %ret{{[0-9]+}}, [%r[[R0]]]; -;CHECK: ret; - %i = getelementptr [10 x double] addrspace(2)* @array_local_double, i32 0, i32 0 - %x = load double addrspace(2)* %i - ret double %x -} - define ptx_device i16 @t4_shared_u16() { entry: ;CHECK: mov.u32 %r[[R0:[0-9]+]], array_shared_i16; Modified: llvm/trunk/test/CodeGen/PTX/st.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/st.ll?rev=140533&r1=140532&r2=140533&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/st.ll (original) +++ llvm/trunk/test/CodeGen/PTX/st.ll Mon Sep 26 11:20:28 2011 @@ -6,9 +6,6 @@ ;CHECK: .extern .const .b8 array_constant_i16[20]; @array_constant_i16 = external addrspace(1) constant [10 x i16] -;CHECK: .extern .local .b8 array_local_i16[20]; - at array_local_i16 = external addrspace(2) global [10 x i16] - ;CHECK: .extern .shared .b8 array_shared_i16[20]; @array_shared_i16 = external addrspace(4) global [10 x i16] @@ -18,9 +15,6 @@ ;CHECK: .extern .const .b8 array_constant_i32[40]; @array_constant_i32 = external addrspace(1) constant [10 x i32] -;CHECK: .extern .local .b8 array_local_i32[40]; - at array_local_i32 = external addrspace(2) global [10 x i32] - ;CHECK: .extern .shared .b8 array_shared_i32[40]; @array_shared_i32 = external addrspace(4) global [10 x i32] @@ -30,9 +24,6 @@ ;CHECK: .extern .const .b8 array_constant_i64[80]; @array_constant_i64 = external addrspace(1) constant [10 x i64] -;CHECK: .extern .local .b8 array_local_i64[80]; - at array_local_i64 = external addrspace(2) global [10 x i64] - ;CHECK: .extern .shared .b8 array_shared_i64[80]; @array_shared_i64 = external addrspace(4) global [10 x i64] @@ -42,9 +33,6 @@ ;CHECK: .extern .const .b8 array_constant_float[40]; @array_constant_float = external addrspace(1) constant [10 x float] -;CHECK: .extern .local .b8 array_local_float[40]; - at array_local_float = external addrspace(2) global [10 x float] - ;CHECK: .extern .shared .b8 array_shared_float[40]; @array_shared_float = external addrspace(4) global [10 x float] @@ -54,9 +42,6 @@ ;CHECK: .extern .const .b8 array_constant_double[80]; @array_constant_double = external addrspace(1) constant [10 x double] -;CHECK: .extern .local .b8 array_local_double[80]; - at array_local_double = external addrspace(2) global [10 x double] - ;CHECK: .extern .shared .b8 array_shared_double[80]; @array_shared_double = external addrspace(4) global [10 x double] @@ -251,56 +236,6 @@ ret void } -define ptx_device void @t4_local_u16(i16 %x) { -entry: -;CHECK: mov.u32 %r[[R0:[0-9]+]], array_local_i16; -;CHECK: st.local.u16 [%r[[R0]]], %rh{{[0-9]+}}; -;CHECK: ret; - %i = getelementptr [10 x i16] addrspace(2)* @array_local_i16, i32 0, i32 0 - store i16 %x, i16 addrspace(2)* %i - ret void -} - -define ptx_device void @t4_local_u32(i32 %x) { -entry: -;CHECK: mov.u32 %r[[R0:[0-9]+]], array_local_i32; -;CHECK: st.local.u32 [%r[[R0]]], %r{{[0-9]+}}; -;CHECK: ret; - %i = getelementptr [10 x i32] addrspace(2)* @array_local_i32, i32 0, i32 0 - store i32 %x, i32 addrspace(2)* %i - ret void -} - -define ptx_device void @t4_local_u64(i64 %x) { -entry: -;CHECK: mov.u32 %r[[R0:[0-9]+]], array_local_i64; -;CHECK: st.local.u64 [%r[[R0]]], %rd{{[0-9]+}}; -;CHECK: ret; - %i = getelementptr [10 x i64] addrspace(2)* @array_local_i64, i32 0, i32 0 - store i64 %x, i64 addrspace(2)* %i - ret void -} - -define ptx_device void @t4_local_f32(float %x) { -entry: -;CHECK: mov.u32 %r[[R0:[0-9]+]], array_local_float; -;CHECK: st.local.f32 [%r[[R0]]], %f{{[0-9]+}}; -;CHECK: ret; - %i = getelementptr [10 x float] addrspace(2)* @array_local_float, i32 0, i32 0 - store float %x, float addrspace(2)* %i - ret void -} - -define ptx_device void @t4_local_f64(double %x) { -entry: -;CHECK: mov.u32 %r[[R0:[0-9]+]], array_local_double; -;CHECK: st.local.f64 [%r[[R0]]], %fd{{[0-9]+}}; -;CHECK: ret; - %i = getelementptr [10 x double] addrspace(2)* @array_local_double, i32 0, i32 0 - store double %x, double addrspace(2)* %i - ret void -} - define ptx_device void @t4_shared_u16(i16 %x) { entry: ;CHECK: mov.u32 %r[[R0:[0-9]+]], array_shared_i16; From justin.holewinski at gmail.com Mon Sep 26 11:20:38 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Mon, 26 Sep 2011 16:20:38 -0000 Subject: [llvm-commits] [llvm] r140537 - /llvm/trunk/test/CodeGen/PTX/stack-object.ll Message-ID: <20110926162038.F21092A6C131@llvm.org> Author: jholewinski Date: Mon Sep 26 11:20:38 2011 New Revision: 140537 URL: http://llvm.org/viewvc/llvm-project?rev=140537&view=rev Log: PTX: Add .align tests to stack object test file Modified: llvm/trunk/test/CodeGen/PTX/stack-object.ll Modified: llvm/trunk/test/CodeGen/PTX/stack-object.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/stack-object.ll?rev=140537&r1=140536&r2=140537&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/stack-object.ll (original) +++ llvm/trunk/test/CodeGen/PTX/stack-object.ll Mon Sep 26 11:20:38 2011 @@ -1,8 +1,17 @@ ; RUN: llc < %s -march=ptx32 -mattr=sm20 | FileCheck %s define ptx_device float @stack1(float %a) { - ; CHECK: .local .b32 __local0; - %a.2 = alloca float + ; CHECK: .local .align 4 .b32 __local0; + %a.2 = alloca float, align 4 + ; CHECK: st.local.f32 [__local0], %f0 + store float %a, float* %a.2 + %a.3 = load float* %a.2 + ret float %a.3 +} + +define ptx_device float @stack1_align8(float %a) { + ; CHECK: .local .align 8 .b32 __local0; + %a.2 = alloca float, align 8 ; CHECK: st.local.f32 [__local0], %f0 store float %a, float* %a.2 %a.3 = load float* %a.2 From justin.holewinski at gmail.com Mon Sep 26 11:20:25 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Mon, 26 Sep 2011 16:20:25 -0000 Subject: [llvm-commits] [llvm] r140532 - in /llvm/trunk/lib/Target/PTX: PTXAsmPrinter.cpp PTXISelDAGToDAG.cpp PTXInstrInfo.td PTXRegisterInfo.cpp PTXRegisterInfo.h PTXTargetMachine.cpp Message-ID: <20110926162025.8CE732A6C12C@llvm.org> Author: jholewinski Date: Mon Sep 26 11:20:25 2011 New Revision: 140532 URL: http://llvm.org/viewvc/llvm-project?rev=140532&view=rev Log: PTX: Handle FrameIndex nodes Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp llvm/trunk/lib/Target/PTX/PTXInstrInfo.td llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140532&r1=140531&r2=140532&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Mon Sep 26 11:20:25 2011 @@ -295,9 +295,9 @@ for (unsigned i = 0, e = FrameInfo->getNumObjects(); i != e; ++i) { DEBUG(dbgs() << "Size of object: " << FrameInfo->getObjectSize(i) << "\n"); if (FrameInfo->getObjectSize(i) > 0) { - std::string def = "\t.reg .b"; + std::string def = "\t.local .b"; def += utostr(FrameInfo->getObjectSize(i)*8); // Convert to bits - def += " s"; + def += " __local_"; def += utostr(i); def += ";"; OutStreamer.EmitRawText(Twine(def)); Modified: llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp?rev=140532&r1=140531&r2=140532&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp Mon Sep 26 11:20:25 2011 @@ -37,6 +37,7 @@ bool SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2); bool SelectADDRri(SDValue &Addr, SDValue &Base, SDValue &Offset); bool SelectADDRii(SDValue &Addr, SDValue &Base, SDValue &Offset); + bool SelectADDRlocal(SDValue &Addr, SDValue &Base, SDValue &Offset); // Include the pieces auto'gened from the target description #include "PTXGenDAGISel.inc" @@ -48,6 +49,7 @@ SDNode *SelectREADPARAM(SDNode *Node); SDNode *SelectWRITEPARAM(SDNode *Node); + SDNode *SelectFrameIndex(SDNode *Node); bool isImm(const SDValue &operand); bool SelectImm(const SDValue &operand, SDValue &imm); @@ -75,6 +77,8 @@ return SelectREADPARAM(Node); case PTXISD::WRITE_PARAM: return SelectWRITEPARAM(Node); + case ISD::FrameIndex: + return SelectFrameIndex(Node); default: return SelectCode(Node); } @@ -173,6 +177,25 @@ return Ret; } +SDNode *PTXDAGToDAGISel::SelectFrameIndex(SDNode *Node) { + int FI = cast(Node)->getIndex(); + //dbgs() << "Selecting FrameIndex at index " << FI << "\n"; + SDValue TFI = CurDAG->getTargetFrameIndex(FI, Node->getValueType(0)); + + //unsigned OpCode = PTX::LOAD_LOCAL_F32; + + //for (SDNode::use_iterator i = Node->use_begin(), e = Node->use_end(); + // i != e; ++i) { + // SDNode *Use = *i; + // dbgs() << "USE: "; + // Use->dumpr(CurDAG); + //} + + return Node; + //return CurDAG->getMachineNode(OpCode, Node->getDebugLoc(), + // Node->getValueType(0), TFI); +} + // Match memory operand of the form [reg+reg] bool PTXDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2) { if (Addr.getOpcode() != ISD::ADD || Addr.getNumOperands() < 2 || @@ -243,6 +266,41 @@ return false; } +// Match memory operand of the form [reg], [imm+reg], and [reg+imm] +bool PTXDAGToDAGISel::SelectADDRlocal(SDValue &Addr, SDValue &Base, + SDValue &Offset) { + if (Addr.getOpcode() != ISD::ADD) { + // let SelectADDRii handle the [imm] case + if (isImm(Addr)) + return false; + // it is [reg] + + assert(Addr.getValueType().isSimple() && "Type must be simple"); + + Base = Addr; + Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT()); + + return true; + } + + if (Addr.getNumOperands() < 2) + return false; + + // let SelectADDRii handle the [imm+imm] case + if (isImm(Addr.getOperand(0)) && isImm(Addr.getOperand(1))) + return false; + + // try [reg+imm] and [imm+reg] + for (int i = 0; i < 2; i ++) + if (SelectImm(Addr.getOperand(1-i), Offset)) { + Base = Addr.getOperand(i); + return true; + } + + // neither [reg+imm] nor [imm+reg] + return false; +} + bool PTXDAGToDAGISel::isImm(const SDValue &operand) { return ConstantSDNode::classof(operand.getNode()); } Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=140532&r1=140531&r2=140532&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Mon Sep 26 11:20:25 2011 @@ -50,7 +50,9 @@ def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{ const Value *Src; const PointerType *PT; - if ((Src = cast(N)->getSrcValue()) && + const SDValue &MemOp = N->getOperand(1); + if ((MemOp.getOpcode() != ISD::FrameIndex) && + (Src = cast(N)->getSrcValue()) && (PT = dyn_cast(Src->getType()))) return PT->getAddressSpace() == PTX::GLOBAL; return false; @@ -66,12 +68,8 @@ }]>; def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - const Value *Src; - const PointerType *PT; - if ((Src = cast(N)->getSrcValue()) && - (PT = dyn_cast(Src->getType()))) - return PT->getAddressSpace() == PTX::LOCAL; - return false; + const SDValue &MemOp = N->getOperand(1); + return MemOp.getOpcode() == ISD::FrameIndex; }]>; def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{ @@ -96,7 +94,9 @@ : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ const Value *Src; const PointerType *PT; - if ((Src = cast(N)->getSrcValue()) && + const SDValue &MemOp = N->getOperand(2); + if ((MemOp.getOpcode() != ISD::FrameIndex) && + (Src = cast(N)->getSrcValue()) && (PT = dyn_cast(Src->getType()))) return PT->getAddressSpace() == PTX::GLOBAL; return false; @@ -104,12 +104,8 @@ def store_local : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ - const Value *Src; - const PointerType *PT; - if ((Src = cast(N)->getSrcValue()) && - (PT = dyn_cast(Src->getType()))) - return PT->getAddressSpace() == PTX::LOCAL; - return false; + const SDValue &MemOp = N->getOperand(2); + return MemOp.getOpcode() == ISD::FrameIndex; }]>; def store_parameter @@ -133,12 +129,14 @@ }]>; // Addressing modes. -def ADDRrr32 : ComplexPattern; -def ADDRrr64 : ComplexPattern; -def ADDRri32 : ComplexPattern; -def ADDRri64 : ComplexPattern; -def ADDRii32 : ComplexPattern; -def ADDRii64 : ComplexPattern; +def ADDRrr32 : ComplexPattern; +def ADDRrr64 : ComplexPattern; +def ADDRri32 : ComplexPattern; +def ADDRri64 : ComplexPattern; +def ADDRii32 : ComplexPattern; +def ADDRii64 : ComplexPattern; +def ADDRlocal32 : ComplexPattern; +def ADDRlocal64 : ComplexPattern; // Address operands def MEMri32 : Operand { @@ -903,7 +901,7 @@ // Loads defm LDg : PTX_LD_ALL<"ld.global", load_global>; defm LDc : PTX_LD_ALL<"ld.const", load_constant>; -defm LDl : PTX_LD_ALL<"ld.local", load_local>; +//defm LDl : PTX_LD_ALL<"ld.local", load_local>; defm LDs : PTX_LD_ALL<"ld.shared", load_shared>; // These instructions are used to load/store from the .param space for @@ -949,11 +947,101 @@ [(PTXstoreparam timm:$d, RegF64:$a)]>; } +/* + def ri64 : InstPTX<(outs RC:$d), + (ins MEMri64:$a), + !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")), + [(set RC:$d, (pat_load ADDRri64:$a))]>, + Requires<[Use64BitAddresses]>; + + def ri64 : InstPTX<(outs), + (ins RC:$d, MEMri64:$a), + !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")), + [(pat_store RC:$d, ADDRri64:$a)]>, + Requires<[Use64BitAddresses]>; + */ +let hasSideEffects = 1 in { + def LDLOCALpiPred : InstPTX<(outs RegPred:$d), (ins MEMri32:$a), + "ld.local.pred\t$d, [__local_$a]", + [(set RegPred:$d, (load_local ADDRlocal32:$a))]>; + def LDLOCALpiU16 : InstPTX<(outs RegI16:$d), (ins MEMri32:$a), + "ld.local.u16\t$d, [__local_$a]", + [(set RegI16:$d, (load_local ADDRlocal32:$a))]>; + def LDLOCALpiU32 : InstPTX<(outs RegI32:$d), (ins MEMri32:$a), + "ld.local.u32\t$d, [__local_$a]", + [(set RegI32:$d, (load_local ADDRlocal32:$a))]>; + def LDLOCALpiU64 : InstPTX<(outs RegI64:$d), (ins MEMri32:$a), + "ld.local.u64\t$d, [__local_$a]", + [(set RegI64:$d, (load_local ADDRlocal32:$a))]>; + def LDLOCALpiF32 : InstPTX<(outs RegF32:$d), (ins MEMri32:$a), + "ld.local.f32\t$d, [__local_$a]", + [(set RegF32:$d, (load_local ADDRlocal32:$a))]>; + def LDLOCALpiF64 : InstPTX<(outs RegF64:$d), (ins MEMri32:$a), + "ld.local.f64\t$d, [__local_$a]", + [(set RegF64:$d, (load_local ADDRlocal32:$a))]>; + + def STLOCALpiPred : InstPTX<(outs), (ins RegPred:$d, MEMri32:$a), + "st.local.pred\t[__local_$a], $d", + [(store_local RegPred:$d, ADDRlocal32:$a)]>; + def STLOCALpiU16 : InstPTX<(outs), (ins RegI16:$d, MEMri32:$a), + "st.local.u16\t[__local_$a], $d", + [(store_local RegI16:$d, ADDRlocal32:$a)]>; + def STLOCALpiU32 : InstPTX<(outs), (ins RegI32:$d, MEMri32:$a), + "st.local.u32\t[__local_$a], $d", + [(store_local RegI32:$d, ADDRlocal32:$a)]>; + def STLOCALpiU64 : InstPTX<(outs), (ins RegI64:$d, MEMri32:$a), + "st.local.u64\t[__local_$a], $d", + [(store_local RegI64:$d, ADDRlocal32:$a)]>; + def STLOCALpiF32 : InstPTX<(outs), (ins RegF32:$d, MEMri32:$a), + "st.local.f32\t[__local_$a], $d", + [(store_local RegF32:$d, ADDRlocal32:$a)]>; + def STLOCALpiF64 : InstPTX<(outs), (ins RegF64:$d, MEMri32:$a), + "st.local.f64\t[__local_$a], $d", + [(store_local RegF64:$d, ADDRlocal32:$a)]>; + + /*def LDLOCALpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a), + "ld.param.u16\t$d, [$a]", + [(set RegI16:$d, (PTXloadparam timm:$a))]>; + def LDLOCALpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a), + "ld.param.u32\t$d, [$a]", + [(set RegI32:$d, (PTXloadparam timm:$a))]>; + def LDLOCALpiU64 : InstPTX<(outs RegI64:$d), (ins MEMpi:$a), + "ld.param.u64\t$d, [$a]", + [(set RegI64:$d, (PTXloadparam timm:$a))]>; + def LDLOCALpiF32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a), + "ld.param.f32\t$d, [$a]", + [(set RegF32:$d, (PTXloadparam timm:$a))]>; + def LDLOCALpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a), + "ld.param.f64\t$d, [$a]", + [(set RegF64:$d, (PTXloadparam timm:$a))]>; + + def STLOCALpiPred : InstPTX<(outs), (ins MEMpi:$d, RegPred:$a), + "st.param.pred\t[$d], $a", + [(PTXstoreparam timm:$d, RegPred:$a)]>; + def STLOCALpiU16 : InstPTX<(outs), (ins MEMpi:$d, RegI16:$a), + "st.param.u16\t[$d], $a", + [(PTXstoreparam timm:$d, RegI16:$a)]>; + def STLOCALpiU32 : InstPTX<(outs), (ins MEMpi:$d, RegI32:$a), + "st.param.u32\t[$d], $a", + [(PTXstoreparam timm:$d, RegI32:$a)]>; + def STLOCALpiU64 : InstPTX<(outs), (ins MEMpi:$d, RegI64:$a), + "st.param.u64\t[$d], $a", + [(PTXstoreparam timm:$d, RegI64:$a)]>; + def STLOCALpiF32 : InstPTX<(outs), (ins MEMpi:$d, RegF32:$a), + "st.param.f32\t[$d], $a", + [(PTXstoreparam timm:$d, RegF32:$a)]>; + def STLOCALpiF64 : InstPTX<(outs), (ins MEMpi:$d, RegF64:$a), + "st.param.f64\t[$d], $a", + [(PTXstoreparam timm:$d, RegF64:$a)]>;*/ +} + // Stores defm STg : PTX_ST_ALL<"st.global", store_global>; -defm STl : PTX_ST_ALL<"st.local", store_local>; +//defm STl : PTX_ST_ALL<"st.local", store_local>; defm STs : PTX_ST_ALL<"st.shared", store_shared>; + + // defm STp : PTX_ST_ALL<"st.param", store_parameter>; // defm LDp : PTX_LD_ALL<"ld.param", load_parameter>; // TODO: Do something with st.param if/when it is needed. @@ -1199,6 +1287,11 @@ def WRITEPARAMF32 : InstPTX<(outs), (ins RegF32:$a), "//w", []>; def WRITEPARAMF64 : InstPTX<(outs), (ins RegF64:$a), "//w", []>; +///===- Stack Variable Loads/Stores ---------------------------------------===// + +def LOAD_LOCAL_F32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a), + "ld.local.f32\t$d, [%a]", []>; + // Call handling // def ADJCALLSTACKUP : // InstPTX<(outs), (ins i32imm:$amt1, i32imm:$amt2), "", Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp?rev=140532&r1=140531&r2=140532&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp Mon Sep 26 11:20:25 2011 @@ -14,6 +14,9 @@ #include "PTX.h" #include "PTXRegisterInfo.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" @@ -23,16 +26,21 @@ using namespace llvm; PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM, - const TargetInstrInfo &TII) + const TargetInstrInfo &tii) // PTX does not have a return address register. - : PTXGenRegisterInfo(0) { + : PTXGenRegisterInfo(0), TII(tii) { } void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS) const { unsigned Index; - MachineInstr& MI = *II; + MachineInstr &MI = *II; + //MachineBasicBlock &MBB = *MI.getParent(); + DebugLoc dl = MI.getDebugLoc(); + //MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); + + //unsigned Reg = MRI.createVirtualRegister(PTX::RegF32RegisterClass); Index = 0; while (!MI.getOperand(Index).isFI()) { @@ -47,6 +55,15 @@ DEBUG(dbgs() << "- SPAdj: " << SPAdj << "\n"); DEBUG(dbgs() << "- FrameIndex: " << FrameIndex << "\n"); + //MachineInstr* MI2 = BuildMI(MBB, II, dl, TII.get(PTX::LOAD_LOCAL_F32)) + //.addReg(Reg, RegState::Define).addImm(FrameIndex); + //if (MI2->findFirstPredOperandIdx() == -1) { + // MI2->addOperand(MachineOperand::CreateReg(PTX::NoRegister, /*IsDef=*/false)); + // MI2->addOperand(MachineOperand::CreateImm(PTX::PRED_NORMAL)); + //} + //MI2->dump(); + // This frame index is post stack slot re-use assignments - MI.getOperand(Index).ChangeToImmediate(FrameIndex); + //MI.getOperand(Index).ChangeToRegister(Reg, false); + MI.getOperand(Index).ChangeToImmediate(0); } Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h?rev=140532&r1=140531&r2=140532&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h (original) +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h Mon Sep 26 11:20:25 2011 @@ -25,8 +25,12 @@ class MachineFunction; struct PTXRegisterInfo : public PTXGenRegisterInfo { +private: + const TargetInstrInfo &TII; + +public: PTXRegisterInfo(PTXTargetMachine &TM, - const TargetInstrInfo &TII); + const TargetInstrInfo &tii); virtual const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const { Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=140532&r1=140531&r2=140532&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Mon Sep 26 11:20:25 2011 @@ -118,7 +118,7 @@ bool PTXTargetMachine::addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { // PTXMFInfoExtract must after register allocation! - PM.add(createPTXMFInfoExtract(*this, OptLevel)); + //PM.add(createPTXMFInfoExtract(*this, OptLevel)); return false; } @@ -365,5 +365,7 @@ if (addPreEmitPass(PM, OptLevel)) printNoVerify(PM, "After PreEmit passes"); + PM.add(createPTXMFInfoExtract(*this, OptLevel)); + return false; } From justin.holewinski at gmail.com Mon Sep 26 11:20:34 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Mon, 26 Sep 2011 16:20:34 -0000 Subject: [llvm-commits] [llvm] r140535 - in /llvm/trunk: lib/Target/PTX/PTXAsmPrinter.cpp test/CodeGen/PTX/stack-object.ll Message-ID: <20110926162034.851422A6C12F@llvm.org> Author: jholewinski Date: Mon Sep 26 11:20:34 2011 New Revision: 140535 URL: http://llvm.org/viewvc/llvm-project?rev=140535&view=rev Log: PTX: Fix some lingering issues with stack allocation Added: llvm/trunk/test/CodeGen/PTX/stack-object.ll Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140535&r1=140534&r2=140535&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Mon Sep 26 11:20:34 2011 @@ -297,7 +297,9 @@ for (unsigned i = 0, e = FrameInfo->getNumObjects(); i != e; ++i) { DEBUG(dbgs() << "Size of object: " << FrameInfo->getObjectSize(i) << "\n"); if (FrameInfo->getObjectSize(i) > 0) { - std::string def = "\t.local .b"; + std::string def = "\t.local .align "; + def += utostr(FrameInfo->getObjectAlignment(i)); + def += " .b"; def += utostr(FrameInfo->getObjectSize(i)*8); // Convert to bits def += " __local"; def += utostr(i); Added: llvm/trunk/test/CodeGen/PTX/stack-object.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/stack-object.ll?rev=140535&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PTX/stack-object.ll (added) +++ llvm/trunk/test/CodeGen/PTX/stack-object.ll Mon Sep 26 11:20:34 2011 @@ -0,0 +1,10 @@ +; RUN: llc < %s -march=ptx32 -mattr=sm20 | FileCheck %s + +define ptx_device float @stack1(float %a) { + ; CHECK: .local .b32 __local0; + %a.2 = alloca float + ; CHECK: st.local.f32 [__local0], %f0 + store float %a, float* %a.2 + %a.3 = load float* %a.2 + ret float %a.3 +} From dpatel at apple.com Mon Sep 26 12:19:00 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 26 Sep 2011 10:19:00 -0700 Subject: [llvm-commits] [PATCH] Fix emission of debug data for global variables In-Reply-To: References: Message-ID: <110CF51C-1D54-4C81-AF01-2CF4436DFA20@apple.com> James, Your patch looks good. Please apply (remove target datalayout and target triple from the test case because it is unnecessary). Thanks! - Devang On Sep 26, 2011, at 9:03 AM, James Molloy wrote: > Hi, > > With the new debug information changes, global variables aren't emitted properly to DWARF. The DW_AT_decl_file field is incorrect. > > This stems from DwarfCompileUnit.cpp:138: > > unsigned FileID = DD->GetOrCreateSourceID(G.getContext().getFilename(), > G.getContext().getDirectory()); > > G.getContext() returns a NULL metadatum for the new metadata format (it used to return the CompileUnit). This causes a new SourceID to be generated for the "null" file, and the global is assigned this incorrect SourceID. > > Attached is a testcase and proposed patch. It inlines getFilename() and getDirectory() into DIGlobalVariable, returning the original getContext().getFilename() for old versions of the debug info and getFieldAs(6).getFilename() for new versions. > > I've implemented it this way so that the old code path is identical to before. I'm not sure if this is the most perfect fix - as getFieldAs(6) is valid (seemingly) for all debug info versions, perhaps the best idea would be to remove the conditionalization and always return getFieldAs(6).getFilename/getDirectory() ? > > > Cheers, > > James > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.<2011-09-26-GlobalVarContext.patch>_______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From james.molloy at arm.com Mon Sep 26 12:20:25 2011 From: james.molloy at arm.com (James Molloy) Date: Mon, 26 Sep 2011 18:20:25 +0100 Subject: [llvm-commits] [PATCH] Fix emission of debug data for global variables In-Reply-To: <110CF51C-1D54-4C81-AF01-2CF4436DFA20@apple.com> References: <110CF51C-1D54-4C81-AF01-2CF4436DFA20@apple.com> Message-ID: <000001cc7c70$94f99df0$beecd9d0$@molloy@arm.com> Hi Devang, Thanks. As the testcase needs to compile down to assembly (to test the DWARF output), is the target triple really unnecessary? Cheers, James -----Original Message----- From: Devang Patel [mailto:dpatel at apple.com] Sent: 26 September 2011 18:19 To: James Molloy Cc: Commit Messages and Patches for LLVM Subject: Re: [llvm-commits] [PATCH] Fix emission of debug data for global variables James, Your patch looks good. Please apply (remove target datalayout and target triple from the test case because it is unnecessary). Thanks! - Devang On Sep 26, 2011, at 9:03 AM, James Molloy wrote: > Hi, > > With the new debug information changes, global variables aren't emitted properly to DWARF. The DW_AT_decl_file field is incorrect. > > This stems from DwarfCompileUnit.cpp:138: > > unsigned FileID = DD->GetOrCreateSourceID(G.getContext().getFilename(), > G.getContext().getDirectory()); > > G.getContext() returns a NULL metadatum for the new metadata format (it used to return the CompileUnit). This causes a new SourceID to be generated for the "null" file, and the global is assigned this incorrect SourceID. > > Attached is a testcase and proposed patch. It inlines getFilename() and getDirectory() into DIGlobalVariable, returning the original getContext().getFilename() for old versions of the debug info and getFieldAs(6).getFilename() for new versions. > > I've implemented it this way so that the old code path is identical to before. I'm not sure if this is the most perfect fix - as getFieldAs(6) is valid (seemingly) for all debug info versions, perhaps the best idea would be to remove the conditionalization and always return getFieldAs(6).getFilename/getDirectory() ? > > > Cheers, > > James > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.<2011-09-26-GlobalVarContext.patch>_____________________________________ __________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Mon Sep 26 12:27:21 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 26 Sep 2011 10:27:21 -0700 Subject: [llvm-commits] [PATCH] Fix emission of debug data for global variables In-Reply-To: <000001cc7c70$94f99df0$beecd9d0$%molloy@arm.com> References: <110CF51C-1D54-4C81-AF01-2CF4436DFA20@apple.com> <000001cc7c70$94f99df0$beecd9d0$%molloy@arm.com> Message-ID: On Sep 26, 2011, at 10:20 AM, James Molloy wrote: > Hi Devang, > > Thanks. As the testcase needs to compile down to assembly (to test the DWARF > output), is the target triple really unnecessary? All targets support DWARF but assembly syntax may not match, so yeah test is fine as it is. Long term, it'd be good to start using llvm-dwarfdump once it matures for such tests. - Devang > > Cheers, > > James > > -----Original Message----- > From: Devang Patel [mailto:dpatel at apple.com] > Sent: 26 September 2011 18:19 > To: James Molloy > Cc: Commit Messages and Patches for LLVM > Subject: Re: [llvm-commits] [PATCH] Fix emission of debug data for global > variables > > James, > > Your patch looks good. Please apply (remove target datalayout and target > triple from the test case because it is unnecessary). > Thanks! > - > Devang > On Sep 26, 2011, at 9:03 AM, James Molloy wrote: > >> Hi, >> >> With the new debug information changes, global variables aren't emitted > properly to DWARF. The DW_AT_decl_file field is incorrect. >> >> This stems from DwarfCompileUnit.cpp:138: >> >> unsigned FileID = DD->GetOrCreateSourceID(G.getContext().getFilename(), >> G.getContext().getDirectory()); >> >> G.getContext() returns a NULL metadatum for the new metadata format (it > used to return the CompileUnit). This causes a new SourceID to be generated > for the "null" file, and the global is assigned this incorrect SourceID. >> >> Attached is a testcase and proposed patch. It inlines getFilename() and > getDirectory() into DIGlobalVariable, returning the original > getContext().getFilename() for old versions of the debug info and > getFieldAs(6).getFilename() for new versions. >> >> I've implemented it this way so that the old code path is identical to > before. I'm not sure if this is the most perfect fix - as > getFieldAs(6) is valid (seemingly) for all debug info versions, > perhaps the best idea would be to remove the conditionalization and always > return getFieldAs(6).getFilename/getDirectory() ? >> >> >> Cheers, >> >> James >> >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank > you.<2011-09-26-GlobalVarContext.patch>_____________________________________ > __________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > > > From echristo at apple.com Mon Sep 26 12:27:39 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 26 Sep 2011 10:27:39 -0700 Subject: [llvm-commits] [PATCH] Fix emission of debug data for global variables In-Reply-To: <000001cc7c70$94f99df0$beecd9d0$%molloy@arm.com> References: <110CF51C-1D54-4C81-AF01-2CF4436DFA20@apple.com> <000001cc7c70$94f99df0$beecd9d0$%molloy@arm.com> Message-ID: Can't think of a reason it's x86 specific? That said you could also use 'llc %s -mtriple=i686-pc-linux-gnu' or something similar if I'm wrong and it is. In that case if you could put it in test/DebugInfo/X86 :) -eric On Sep 26, 2011, at 10:20 AM, James Molloy wrote: > Hi Devang, > > Thanks. As the testcase needs to compile down to assembly (to test the DWARF > output), is the target triple really unnecessary? > > Cheers, > > James > > -----Original Message----- > From: Devang Patel [mailto:dpatel at apple.com] > Sent: 26 September 2011 18:19 > To: James Molloy > Cc: Commit Messages and Patches for LLVM > Subject: Re: [llvm-commits] [PATCH] Fix emission of debug data for global > variables > > James, > > Your patch looks good. Please apply (remove target datalayout and target > triple from the test case because it is unnecessary). > Thanks! > - > Devang > On Sep 26, 2011, at 9:03 AM, James Molloy wrote: > >> Hi, >> >> With the new debug information changes, global variables aren't emitted > properly to DWARF. The DW_AT_decl_file field is incorrect. >> >> This stems from DwarfCompileUnit.cpp:138: >> >> unsigned FileID = DD->GetOrCreateSourceID(G.getContext().getFilename(), >> G.getContext().getDirectory()); >> >> G.getContext() returns a NULL metadatum for the new metadata format (it > used to return the CompileUnit). This causes a new SourceID to be generated > for the "null" file, and the global is assigned this incorrect SourceID. >> >> Attached is a testcase and proposed patch. It inlines getFilename() and > getDirectory() into DIGlobalVariable, returning the original > getContext().getFilename() for old versions of the debug info and > getFieldAs(6).getFilename() for new versions. >> >> I've implemented it this way so that the old code path is identical to > before. I'm not sure if this is the most perfect fix - as > getFieldAs(6) is valid (seemingly) for all debug info versions, > perhaps the best idea would be to remove the conditionalization and always > return getFieldAs(6).getFilename/getDirectory() ? >> >> >> Cheers, >> >> James >> >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank > you.<2011-09-26-GlobalVarContext.patch>_____________________________________ > __________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Mon Sep 26 12:31:04 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 26 Sep 2011 10:31:04 -0700 Subject: [llvm-commits] [PATCH] Fix emission of debug data for global variables In-Reply-To: References: <110CF51C-1D54-4C81-AF01-2CF4436DFA20@apple.com> <000001cc7c70$94f99df0$beecd9d0$%molloy@arm.com> Message-ID: On Sep 26, 2011, at 10:27 AM, Devang Patel wrote: > Long term, it'd be good to start using llvm-dwarfdump once it matures for such tests. That's definitely a good idea. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110926/4249e770/attachment.html From james.molloy at arm.com Mon Sep 26 12:35:23 2011 From: james.molloy at arm.com (James Molloy) Date: Mon, 26 Sep 2011 18:35:23 +0100 Subject: [llvm-commits] [PATCH] Fix emission of debug data for global variables In-Reply-To: References: <110CF51C-1D54-4C81-AF01-2CF4436DFA20@apple.com> <000001cc7c70$94f99df0$beecd9d0$%molloy@arm.com> Message-ID: <000101cc7c72$abd6f890$0384e9b0$@molloy@arm.com> I agree with everything said. Because it goes to asm (even though the asm isn't checked), the target triple is needed, and as I have to choose a target triple, X86 was the obvious choice (I also put it in the X86 directory) Llvm-dwarfdump would be much nicer :) Committing now. Thanks for the review! James -----Original Message----- From: Eric Christopher [mailto:echristo at apple.com] Sent: 26 September 2011 18:28 To: James Molloy Cc: 'Devang Patel'; Commit Messages and Patches for LLVM Subject: Re: [llvm-commits] [PATCH] Fix emission of debug data for global variables Can't think of a reason it's x86 specific. That said you could also use 'llc %s -mtriple=i686-pc-linux-gnu' or something similar if I'm wrong and it is. In that case if you could put it in test/DebugInfo/X86 :) -eric On Sep 26, 2011, at 10:20 AM, James Molloy wrote: > Hi Devang, > > Thanks. As the testcase needs to compile down to assembly (to test the DWARF > output), is the target triple really unnecessary? > > Cheers, > > James > > -----Original Message----- > From: Devang Patel [mailto:dpatel at apple.com] > Sent: 26 September 2011 18:19 > To: James Molloy > Cc: Commit Messages and Patches for LLVM > Subject: Re: [llvm-commits] [PATCH] Fix emission of debug data for global > variables > > James, > > Your patch looks good. Please apply (remove target datalayout and target > triple from the test case because it is unnecessary). > Thanks! > - > Devang > On Sep 26, 2011, at 9:03 AM, James Molloy wrote: > >> Hi, >> >> With the new debug information changes, global variables aren't emitted > properly to DWARF. The DW_AT_decl_file field is incorrect. >> >> This stems from DwarfCompileUnit.cpp:138: >> >> unsigned FileID = DD->GetOrCreateSourceID(G.getContext().getFilename(), >> G.getContext().getDirectory()); >> >> G.getContext() returns a NULL metadatum for the new metadata format (it > used to return the CompileUnit). This causes a new SourceID to be generated > for the "null" file, and the global is assigned this incorrect SourceID. >> >> Attached is a testcase and proposed patch. It inlines getFilename() and > getDirectory() into DIGlobalVariable, returning the original > getContext().getFilename() for old versions of the debug info and > getFieldAs(6).getFilename() for new versions. >> >> I've implemented it this way so that the old code path is identical to > before. I'm not sure if this is the most perfect fix - as > getFieldAs(6) is valid (seemingly) for all debug info versions, > perhaps the best idea would be to remove the conditionalization and always > return getFieldAs(6).getFilename/getDirectory() ? >> >> >> Cheers, >> >> James >> >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank > you.<2011-09-26-GlobalVarContext.patch>_____________________________________ > __________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Mon Sep 26 12:39:21 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 26 Sep 2011 10:39:21 -0700 Subject: [llvm-commits] [PATCH] Fix emission of debug data for global variables In-Reply-To: <000101cc7c72$abd6f890$0384e9b0$%molloy@arm.com> References: <110CF51C-1D54-4C81-AF01-2CF4436DFA20@apple.com> <000001cc7c70$94f99df0$beecd9d0$%molloy@arm.com> <000101cc7c72$abd6f890$0384e9b0$%molloy@arm.com> Message-ID: On Sep 26, 2011, at 10:35 AM, James Molloy wrote: > . Because it goes to asm (even though the asm > isn't checked), the target triple is needed Right. If it doesn't really matter then it could just use "whatever is the default" and so wouldn't need one :) -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110926/c5b6b306/attachment.html From james.molloy at arm.com Mon Sep 26 12:40:39 2011 From: james.molloy at arm.com (James Molloy) Date: Mon, 26 Sep 2011 18:40:39 +0100 Subject: [llvm-commits] [PATCH] Fix emission of debug data for global variables In-Reply-To: References: <110CF51C-1D54-4C81-AF01-2CF4436DFA20@apple.com> <000001cc7c70$94f99df0$beecd9d0$%molloy@arm.com> <000101cc7c72$abd6f890$0384e9b0$%molloy@arm.com> Message-ID: <000201cc7c73$681d5da0$385818e0$@molloy@arm.com> Gotcha. I didn't know whether the output may be somewhat undefined if a triple wasn't specified. I'm changing it now to be agnostic. Thanks Eric. From: Eric Christopher [mailto:echristo at apple.com] Sent: 26 September 2011 18:39 To: James Molloy Cc: 'Devang Patel'; Commit Messages and Patches for LLVM Subject: Re: [llvm-commits] [PATCH] Fix emission of debug data for global variables On Sep 26, 2011, at 10:35 AM, James Molloy wrote: . Because it goes to asm (even though the asm isn't checked), the target triple is needed Right. If it doesn't really matter then it could just use "whatever is the default" and so wouldn't need one :) -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110926/08e610e1/attachment.html From james.molloy at arm.com Mon Sep 26 12:40:42 2011 From: james.molloy at arm.com (James Molloy) Date: Mon, 26 Sep 2011 17:40:42 -0000 Subject: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll Message-ID: <20110926174042.E57FA2A6C12C@llvm.org> Author: jamesm Date: Mon Sep 26 12:40:42 2011 New Revision: 140539 URL: http://llvm.org/viewvc/llvm-project?rev=140539&view=rev Log: Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more. Added: llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll (with props) Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=140539&r1=140538&r2=140539&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Mon Sep 26 12:40:42 2011 @@ -579,6 +579,17 @@ DIFile F = getFieldAs(6); return F.getCompileUnit(); } + StringRef getFilename() const { + if (getVersion() <= llvm::LLVMDebugVersion10) + return getContext().getFilename(); + return getFieldAs(6).getFilename(); + } + StringRef getDirectory() const { + if (getVersion() <= llvm::LLVMDebugVersion10) + return getContext().getDirectory(); + return getFieldAs(6).getDirectory(); + + } unsigned getLineNumber() const { return getUnsignedField(7); } DIType getType() const { return getFieldAs(8); } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=140539&r1=140538&r2=140539&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Mon Sep 26 12:40:42 2011 @@ -135,8 +135,8 @@ unsigned Line = G.getLineNumber(); if (Line == 0) return; - unsigned FileID = DD->GetOrCreateSourceID(G.getContext().getFilename(), - G.getContext().getDirectory()); + unsigned FileID = DD->GetOrCreateSourceID(G.getFilename(), + G.getDirectory()); assert(FileID && "Invalid file id"); addUInt(Die, dwarf::DW_AT_decl_file, 0, FileID); addUInt(Die, dwarf::DW_AT_decl_line, 0, Line); Added: llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll?rev=140539&view=auto ============================================================================== --- llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll (added) +++ llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll Mon Sep 26 12:40:42 2011 @@ -0,0 +1,47 @@ +; RUN: llc -asm-verbose %s -o - | FileCheck %s + +; ModuleID = 'test.c' + + at GLOBAL = common global i32 0, align 4 + +define i32 @f() nounwind { + %LOCAL = alloca i32, align 4 + call void @llvm.dbg.declare(metadata !{i32* %LOCAL}, metadata !15), !dbg !17 + %1 = load i32* @GLOBAL, align 4, !dbg !18 + store i32 %1, i32* %LOCAL, align 4, !dbg !18 + %2 = load i32* @GLOBAL, align 4, !dbg !19 + ret i32 %2, !dbg !19 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"test.c", metadata !"/work/llvm/vanilla/test/DebugInfo", metadata !"clang version 3.0 (trunk)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !12} ; [ DW_TAG_compile_unit ] +!1 = metadata !{metadata !2} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{metadata !5} +!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"f", metadata !"f", metadata !"", metadata !6, i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @f, null, null, metadata !10} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 720937, metadata !"test.c", metadata !"/work/llvm/vanilla/test/DebugInfo", null} ; [ DW_TAG_file_type ] +!7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!8 = metadata !{metadata !9} +!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!10 = metadata !{metadata !11} +!11 = metadata !{i32 720932} ; [ DW_TAG_base_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{metadata !14} +!14 = metadata !{i32 720948, i32 0, null, metadata !"GLOBAL", metadata !"GLOBAL", metadata !"", metadata !6, i32 1, metadata !9, i32 0, i32 1, i32* @GLOBAL} ; [ DW_TAG_variable ] +!15 = metadata !{i32 721152, metadata !16, metadata !"LOCAL", metadata !6, i32 4, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ] +!16 = metadata !{i32 720907, metadata !5, i32 3, i32 9, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] +!17 = metadata !{i32 4, i32 9, metadata !16, null} +!18 = metadata !{i32 4, i32 23, metadata !16, null} +!19 = metadata !{i32 5, i32 5, metadata !16, null} + +; CHECK: .ascii "GLOBAL" # DW_AT_name +; CHECK: .byte 1 # DW_AT_decl_file +; CHECK: .byte 1 # DW_AT_decl_line + +; CHECK: .ascii "LOCAL" # DW_AT_name +; CHECK: .byte 1 # DW_AT_decl_file +; CHECK: .byte 4 # DW_AT_decl_line Propchange: llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll ------------------------------------------------------------------------------ svn:eol-style = native From stoklund at 2pi.dk Mon Sep 26 13:21:59 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 26 Sep 2011 11:21:59 -0700 Subject: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll In-Reply-To: <20110926174042.E57FA2A6C12C@llvm.org> References: <20110926174042.E57FA2A6C12C@llvm.org> Message-ID: On Sep 26, 2011, at 10:40 AM, James Molloy wrote: > Author: jamesm > Date: Mon Sep 26 12:40:42 2011 > New Revision: 140539 > > URL: http://llvm.org/viewvc/llvm-project?rev=140539&view=rev > Log: > Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more. Hi James. Please make sure your test case is platform agnostic. ******************** TEST 'LLVM :: DebugInfo/2011-09-26-GlobalVarContext.ll' FAILED ********************Script: Command Output (stderr): -- test/DebugInfo/2011-09-26-GlobalVarContext.ll:41:10: error: expected string not found in input ; CHECK: .ascii "GLOBAL" # DW_AT_name ^ :1:2: note: scanning from here .section __TEXT,__text,regular,pure_instructions ^ :75:2: note: possible intended match here .ascii "GLOBAL" ## DW_AT_name ^ -- You can for example add a triple argument. /jakob From gohman at apple.com Mon Sep 26 13:22:14 2011 From: gohman at apple.com (Dan Gohman) Date: Mon, 26 Sep 2011 11:22:14 -0700 Subject: [llvm-commits] [PATCH] Fix PR11004: Crash in llc arm backend In-Reply-To: References: <30A02F8B-795B-4AA3-BAC8-83DEACF90A0F@apple.com> <42E83160-1E33-430C-8E3F-715567B46C4A@apple.com> <47AE444F-E4A6-491C-907E-5746A9A4187C@apple.com> Message-ID: <81EB3488-0B35-4BF5-8828-0906D03D951B@apple.com> On Sep 25, 2011, at 5:45 PM, David Meyer wrote: > Cameron, > > With regards to your comment that it is inconsiderate to break the tree intentionally, you are forgetting that this was an experimental feature that never worked outside of small test cases. Neither Clang nor llvm-gcc will generate byval on ARM, so it gets no real testing. It might be more considerate to users to just add an assert saying that ARM byval doesn't work. > > I dislike the idea of selective IR support. This creates a hidden (undocumented) contract between the frontends and backends, which limits the IR that is valid. It also treats external producers of bitcode as second-class citizens, since they must effectively mimic Clang or DragonEgg to guarantee that their output will be supported. It is nicer if every backend can handle any valid bitcode (even if doing so is not terribly efficient). LLVM IR is brimming with selective IR support. It's a compiler IR, not an actual virtual machine. > I'll let someone else comment on whether we'd rather have a byval that inserts long chains of copies or just disable it entirely. If it is the former, your patch looks fine with the XFAIL of that test removed. > > Struct passing by-value is known to be an inefficient operation. Code demanding performance will usually pass around a const pointer/reference instead if the struct is large. It is a nice performance enhancement to use memcpy, but it doesn't seem too critical. Is there a specific benchmark this affects? In any case, crashing is never the answer ! Crashing reliably is better for us than silently miscompiling spuriously, which is what the code I reverted was doing. Reverting it helped us find and fix a few things accidentally still using byval on ARM much sooner than we otherwise would have. Dan -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110926/97c4cd1a/attachment.html From justin.holewinski at gmail.com Mon Sep 26 13:57:22 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Mon, 26 Sep 2011 18:57:22 -0000 Subject: [llvm-commits] [llvm] r140547 - in /llvm/trunk: lib/Target/PTX/PTXAsmPrinter.cpp lib/Target/PTX/PTXISelDAGToDAG.cpp lib/Target/PTX/PTXInstrLoadStore.td test/CodeGen/PTX/stack-object.ll Message-ID: <20110926185722.793FC2A6C12C@llvm.org> Author: jholewinski Date: Mon Sep 26 13:57:22 2011 New Revision: 140547 URL: http://llvm.org/viewvc/llvm-project?rev=140547&view=rev Log: PTX: Fix detection of stack load/store vs. global load/store, as well as fix the printing of local offsets Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td llvm/trunk/test/CodeGen/PTX/stack-object.ll Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140547&r1=140546&r2=140547&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Mon Sep 26 13:57:22 2011 @@ -299,10 +299,12 @@ if (FrameInfo->getObjectSize(i) > 0) { std::string def = "\t.local .align "; def += utostr(FrameInfo->getObjectAlignment(i)); - def += " .b"; - def += utostr(FrameInfo->getObjectSize(i)*8); // Convert to bits + def += " .b8"; def += " __local"; def += utostr(i); + def += "["; + def += utostr(FrameInfo->getObjectSize(i)); // Convert to bits + def += "]"; def += ";"; OutStreamer.EmitRawText(Twine(def)); } @@ -465,6 +467,11 @@ void PTXAsmPrinter::printLocalOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, const char *Modifier) { OS << "__local" << MI->getOperand(opNum).getImm(); + + if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() != 0){ + OS << "+"; + printOperand(MI, opNum+1, OS); + } } void PTXAsmPrinter::EmitVariableDeclaration(const GlobalVariable *gv) { Modified: llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp?rev=140547&r1=140546&r2=140547&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp Mon Sep 26 13:57:22 2011 @@ -213,14 +213,54 @@ // Match memory operand of the form [reg], [imm+reg], and [reg+imm] bool PTXDAGToDAGISel::SelectADDRri(SDValue &Addr, SDValue &Base, SDValue &Offset) { - if (Addr.getOpcode() != ISD::ADD) { + // FrameIndex addresses are handled separately + //errs() << "SelectADDRri: "; + //Addr.getNode()->dumpr(); + if (isa(Addr)) { + //errs() << "Failure\n"; + return false; + } + + if (CurDAG->isBaseWithConstantOffset(Addr)) { + Base = Addr.getOperand(0); + if (isa(Base)) { + //errs() << "Failure\n"; + return false; + } + ConstantSDNode *CN = dyn_cast(Addr.getOperand(1)); + Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); + //errs() << "Success\n"; + return true; + } + + /*if (Addr.getNumOperands() == 1) { + Base = Addr; + Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT()); + errs() << "Success\n"; + return true; + }*/ + + //errs() << "SelectADDRri fails on: "; + //Addr.getNode()->dumpr(); + + if (isImm(Addr)) { + //errs() << "Failure\n"; + return false; + } + + Base = Addr; + Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT()); + + //errs() << "Success\n"; + return true; + + /*if (Addr.getOpcode() != ISD::ADD) { // let SelectADDRii handle the [imm] case if (isImm(Addr)) return false; // it is [reg] assert(Addr.getValueType().isSimple() && "Type must be simple"); - Base = Addr; Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT()); @@ -242,7 +282,7 @@ } // neither [reg+imm] nor [imm+reg] - return false; + return false;*/ } // Match memory operand of the form [imm+imm] and [imm] @@ -269,35 +309,30 @@ // Match memory operand of the form [reg], [imm+reg], and [reg+imm] bool PTXDAGToDAGISel::SelectADDRlocal(SDValue &Addr, SDValue &Base, SDValue &Offset) { - if (Addr.getOpcode() != ISD::ADD) { - // let SelectADDRii handle the [imm] case - if (isImm(Addr)) - return false; - // it is [reg] - - assert(Addr.getValueType().isSimple() && "Type must be simple"); - + //errs() << "SelectADDRlocal: "; + //Addr.getNode()->dumpr(); + if (isa(Addr)) { Base = Addr; Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT()); - + //errs() << "Success\n"; return true; } - if (Addr.getNumOperands() < 2) - return false; - - // let SelectADDRii handle the [imm+imm] case - if (isImm(Addr.getOperand(0)) && isImm(Addr.getOperand(1))) - return false; - - // try [reg+imm] and [imm+reg] - for (int i = 0; i < 2; i ++) - if (SelectImm(Addr.getOperand(1-i), Offset)) { - Base = Addr.getOperand(i); - return true; + if (CurDAG->isBaseWithConstantOffset(Addr)) { + Base = Addr.getOperand(0); + if (!isa(Base)) { + //errs() << "Failure\n"; + return false; } + ConstantSDNode *CN = dyn_cast(Addr.getOperand(1)); + Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); + //errs() << "Offset: "; + //Offset.getNode()->dumpr(); + //errs() << "Success\n"; + return true; + } - // neither [reg+imm] nor [imm+reg] + //errs() << "Failure\n"; return false; } Modified: llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td?rev=140547&r1=140546&r2=140547&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td Mon Sep 26 13:57:22 2011 @@ -24,9 +24,7 @@ def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{ const Value *Src; const PointerType *PT; - const SDValue &MemOp = N->getOperand(1); - if ((MemOp.getOpcode() != ISD::FrameIndex) && - (Src = cast(N)->getSrcValue()) && + if ((Src = cast(N)->getSrcValue()) && (PT = dyn_cast(Src->getType()))) return PT->getAddressSpace() == PTX::GLOBAL; return false; @@ -41,11 +39,6 @@ return false; }]>; -def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - const SDValue &MemOp = N->getOperand(1); - return MemOp.getOpcode() == ISD::FrameIndex; -}]>; - def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{ const Value *Src; const PointerType *PT; @@ -59,20 +52,12 @@ : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ const Value *Src; const PointerType *PT; - const SDValue &MemOp = N->getOperand(2); - if ((MemOp.getOpcode() != ISD::FrameIndex) && - (Src = cast(N)->getSrcValue()) && + if ((Src = cast(N)->getSrcValue()) && (PT = dyn_cast(Src->getType()))) return PT->getAddressSpace() == PTX::GLOBAL; return false; }]>; -def store_local - : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ - const SDValue &MemOp = N->getOperand(2); - return MemOp.getOpcode() == ISD::FrameIndex; -}]>; - def store_shared : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{ const Value *Src; @@ -221,16 +206,16 @@ multiclass PTX_LOCAL_LD_ST { def LDri32 : InstPTX<(outs RC:$d), (ins LOCALri32:$a), !strconcat("ld.local", !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (load_local ADDRlocal32:$a))]>; + [(set RC:$d, (load_global ADDRlocal32:$a))]>; def LDri64 : InstPTX<(outs RC:$d), (ins LOCALri64:$a), !strconcat("ld.local", !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (load_local ADDRlocal64:$a))]>; + [(set RC:$d, (load_global ADDRlocal64:$a))]>; def STri32 : InstPTX<(outs), (ins RC:$d, LOCALri32:$a), !strconcat("st.local", !strconcat(typestr, "\t[$a], $d")), - [(store_local RC:$d, ADDRlocal32:$a)]>; + [(store_global RC:$d, ADDRlocal32:$a)]>; def STri64 : InstPTX<(outs), (ins RC:$d, LOCALri64:$a), !strconcat("st.local", !strconcat(typestr, "\t[$a], $d")), - [(store_local RC:$d, ADDRlocal64:$a)]>; + [(store_global RC:$d, ADDRlocal64:$a)]>; } multiclass PTX_PARAM_LD_ST { Modified: llvm/trunk/test/CodeGen/PTX/stack-object.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/stack-object.ll?rev=140547&r1=140546&r2=140547&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/stack-object.ll (original) +++ llvm/trunk/test/CodeGen/PTX/stack-object.ll Mon Sep 26 13:57:22 2011 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=ptx32 -mattr=sm20 | FileCheck %s define ptx_device float @stack1(float %a) { - ; CHECK: .local .align 4 .b32 __local0; + ; CHECK: .local .align 4 .b8 __local0[4]; %a.2 = alloca float, align 4 ; CHECK: st.local.f32 [__local0], %f0 store float %a, float* %a.2 @@ -10,7 +10,7 @@ } define ptx_device float @stack1_align8(float %a) { - ; CHECK: .local .align 8 .b32 __local0; + ; CHECK: .local .align 8 .b8 __local0[4]; %a.2 = alloca float, align 8 ; CHECK: st.local.f32 [__local0], %f0 store float %a, float* %a.2 From justin.holewinski at gmail.com Mon Sep 26 13:57:27 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Mon, 26 Sep 2011 18:57:27 -0000 Subject: [llvm-commits] [llvm] r140549 - in /llvm/trunk/lib/Target/PTX: CMakeLists.txt PTXSelectionDAGInfo.cpp PTXSelectionDAGInfo.h PTXTargetMachine.cpp PTXTargetMachine.h Message-ID: <20110926185727.55B192A6C12D@llvm.org> Author: jholewinski Date: Mon Sep 26 13:57:27 2011 New Revision: 140549 URL: http://llvm.org/viewvc/llvm-project?rev=140549&view=rev Log: PTX: Implement PTXSelectionDAGInfo Added: llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.h Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.h Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=140549&r1=140548&r2=140549&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Mon Sep 26 13:57:27 2011 @@ -18,6 +18,7 @@ PTXParamManager.cpp PTXRegAlloc.cpp PTXRegisterInfo.cpp + PTXSelectionDAGInfo.cpp PTXSubtarget.cpp PTXTargetMachine.cpp ) Added: llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp?rev=140549&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp (added) +++ llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp Mon Sep 26 13:57:27 2011 @@ -0,0 +1,148 @@ +//===-- PTXSelectionDAGInfo.cpp - PTX SelectionDAG Info -------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the PTXSelectionDAGInfo class. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "ptx-selectiondag-info" +#include "PTXTargetMachine.h" +#include "llvm/DerivedTypes.h" +#include "llvm/CodeGen/SelectionDAG.h" +using namespace llvm; + +PTXSelectionDAGInfo::PTXSelectionDAGInfo(const TargetMachine &TM) + : TargetSelectionDAGInfo(TM), + Subtarget(&TM.getSubtarget()) { +} + +PTXSelectionDAGInfo::~PTXSelectionDAGInfo() { +} + +SDValue +PTXSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, + SDValue Chain, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, + bool isVolatile, bool AlwaysInline, + MachinePointerInfo DstPtrInfo, + MachinePointerInfo SrcPtrInfo) const { + // Do repeated 4-byte loads and stores. To be improved. + // This requires 4-byte alignment. + if ((Align & 3) != 0) + return SDValue(); + // This requires the copy size to be a constant, preferably + // within a subtarget-specific limit. + ConstantSDNode *ConstantSize = dyn_cast(Size); + if (!ConstantSize) + return SDValue(); + uint64_t SizeVal = ConstantSize->getZExtValue(); + // Always inline memcpys. In PTX, we do not have a C library that provides + // a memcpy function. + //if (!AlwaysInline) + // return SDValue(); + + unsigned BytesLeft = SizeVal & 3; + unsigned NumMemOps = SizeVal >> 2; + unsigned EmittedNumMemOps = 0; + EVT VT = MVT::i32; + unsigned VTSize = 4; + unsigned i = 0; + const unsigned MAX_LOADS_IN_LDM = 6; + SDValue TFOps[MAX_LOADS_IN_LDM]; + SDValue Loads[MAX_LOADS_IN_LDM]; + uint64_t SrcOff = 0, DstOff = 0; + + // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the + // same number of stores. The loads and stores will get combined into + // ldm/stm later on. + while (EmittedNumMemOps < NumMemOps) { + for (i = 0; + i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { + Loads[i] = DAG.getLoad(VT, dl, Chain, + DAG.getNode(ISD::ADD, dl, MVT::i32, Src, + DAG.getConstant(SrcOff, MVT::i32)), + SrcPtrInfo.getWithOffset(SrcOff), isVolatile, + false, 0); + TFOps[i] = Loads[i].getValue(1); + SrcOff += VTSize; + } + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); + + for (i = 0; + i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { + TFOps[i] = DAG.getStore(Chain, dl, Loads[i], + DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, + DAG.getConstant(DstOff, MVT::i32)), + DstPtrInfo.getWithOffset(DstOff), + isVolatile, false, 0); + DstOff += VTSize; + } + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); + + EmittedNumMemOps += i; + } + + if (BytesLeft == 0) + return Chain; + + // Issue loads / stores for the trailing (1 - 3) bytes. + unsigned BytesLeftSave = BytesLeft; + i = 0; + while (BytesLeft) { + if (BytesLeft >= 2) { + VT = MVT::i16; + VTSize = 2; + } else { + VT = MVT::i8; + VTSize = 1; + } + + Loads[i] = DAG.getLoad(VT, dl, Chain, + DAG.getNode(ISD::ADD, dl, MVT::i32, Src, + DAG.getConstant(SrcOff, MVT::i32)), + SrcPtrInfo.getWithOffset(SrcOff), false, false, 0); + TFOps[i] = Loads[i].getValue(1); + ++i; + SrcOff += VTSize; + BytesLeft -= VTSize; + } + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); + + i = 0; + BytesLeft = BytesLeftSave; + while (BytesLeft) { + if (BytesLeft >= 2) { + VT = MVT::i16; + VTSize = 2; + } else { + VT = MVT::i8; + VTSize = 1; + } + + TFOps[i] = DAG.getStore(Chain, dl, Loads[i], + DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, + DAG.getConstant(DstOff, MVT::i32)), + DstPtrInfo.getWithOffset(DstOff), false, false, 0); + ++i; + DstOff += VTSize; + BytesLeft -= VTSize; + } + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); +} + +SDValue PTXSelectionDAGInfo:: +EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, + SDValue Chain, SDValue Dst, + SDValue Src, SDValue Size, + unsigned Align, bool isVolatile, + MachinePointerInfo DstPtrInfo) const { + llvm_unreachable("memset lowering not implemented for PTX yet"); +} + Added: llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.h?rev=140549&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.h (added) +++ llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.h Mon Sep 26 13:57:27 2011 @@ -0,0 +1,53 @@ +//===-- PTXSelectionDAGInfo.h - PTX SelectionDAG Info -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the PTX subclass for TargetSelectionDAGInfo. +// +//===----------------------------------------------------------------------===// + +#ifndef PTXSELECTIONDAGINFO_H +#define PTXSELECTIONDAGINFO_H + +#include "llvm/Target/TargetSelectionDAGInfo.h" + +namespace llvm { + +/// PTXSelectionDAGInfo - TargetSelectionDAGInfo sub-class for the PTX target. +/// At the moment, this is mostly just a copy of ARMSelectionDAGInfo. +class PTXSelectionDAGInfo : public TargetSelectionDAGInfo { + /// Subtarget - Keep a pointer to the PTXSubtarget around so that we can + /// make the right decision when generating code for different targets. + const PTXSubtarget *Subtarget; + +public: + explicit PTXSelectionDAGInfo(const TargetMachine &TM); + ~PTXSelectionDAGInfo(); + + virtual + SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, + SDValue Chain, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, + bool isVolatile, bool AlwaysInline, + MachinePointerInfo DstPtrInfo, + MachinePointerInfo SrcPtrInfo) const; + + virtual + SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, + SDValue Chain, + SDValue Op1, SDValue Op2, + SDValue Op3, unsigned Align, + bool isVolatile, + MachinePointerInfo DstPtrInfo) const; +}; + +} + +#endif + Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=140549&r1=140548&r2=140549&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Mon Sep 26 13:57:27 2011 @@ -94,6 +94,7 @@ Subtarget(TT, CPU, FS, is64Bit), FrameLowering(Subtarget), InstrInfo(*this), + TSInfo(*this), TLInfo(*this) { } Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.h?rev=140549&r1=140548&r2=140549&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.h (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.h Mon Sep 26 13:57:27 2011 @@ -17,6 +17,7 @@ #include "PTXISelLowering.h" #include "PTXInstrInfo.h" #include "PTXFrameLowering.h" +#include "PTXSelectionDAGInfo.h" #include "PTXSubtarget.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameLowering.h" @@ -25,11 +26,12 @@ namespace llvm { class PTXTargetMachine : public LLVMTargetMachine { private: - const TargetData DataLayout; - PTXSubtarget Subtarget; // has to be initialized before FrameLowering - PTXFrameLowering FrameLowering; - PTXInstrInfo InstrInfo; - PTXTargetLowering TLInfo; + const TargetData DataLayout; + PTXSubtarget Subtarget; // has to be initialized before FrameLowering + PTXFrameLowering FrameLowering; + PTXInstrInfo InstrInfo; + PTXSelectionDAGInfo TSInfo; + PTXTargetLowering TLInfo; public: PTXTargetMachine(const Target &T, StringRef TT, @@ -50,6 +52,10 @@ virtual const PTXTargetLowering *getTargetLowering() const { return &TLInfo; } + virtual const PTXSelectionDAGInfo* getSelectionDAGInfo() const { + return &TSInfo; + } + virtual const PTXSubtarget *getSubtargetImpl() const { return &Subtarget; } virtual bool addInstSelector(PassManagerBase &PM, From justin.holewinski at gmail.com Mon Sep 26 13:57:24 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Mon, 26 Sep 2011 18:57:24 -0000 Subject: [llvm-commits] [llvm] r140548 - /llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Message-ID: <20110926185725.0079D2A6C12C@llvm.org> Author: jholewinski Date: Mon Sep 26 13:57:24 2011 New Revision: 140548 URL: http://llvm.org/viewvc/llvm-project?rev=140548&view=rev Log: PTX: Implement ISD::ANY_EXTEND Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=140548&r1=140547&r2=140548&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Mon Sep 26 13:57:24 2011 @@ -849,6 +849,18 @@ : InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a", [(set RegF64:$d, (fextend RegF32:$a))]>; +// NOTE: These are temporarily here to help test some Clang-generated code. +// We really need to properly introduce anyext and bitconvert into the back-end. +// ANY_EXTEND +def ANY_EXTEND_I64_I32 + : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a", + [(set RegI64:$d, (anyext RegI32:$a))]>; + +// BITCAST +def BITCAST_I32_F32 + : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "mov.b32\t$d, $a", + [(set RegI32:$d, (bitconvert RegF32:$a))]>; + ///===- Control Flow Instructions -----------------------------------------===// let isBranch = 1, isTerminator = 1, isBarrier = 1 in { From eli.friedman at gmail.com Mon Sep 26 14:13:47 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 26 Sep 2011 19:13:47 -0000 Subject: [llvm-commits] [llvm] r140553 - /llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll Message-ID: <20110926191347.AA2512A6C12C@llvm.org> Author: efriedma Date: Mon Sep 26 14:13:47 2011 New Revision: 140553 URL: http://llvm.org/viewvc/llvm-project?rev=140553&view=rev Log: Fix this test so it doesn't fail on Mac. Modified: llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll Modified: llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll?rev=140553&r1=140552&r2=140553&view=diff ============================================================================== --- llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll (original) +++ llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll Mon Sep 26 14:13:47 2011 @@ -38,10 +38,10 @@ !18 = metadata !{i32 4, i32 23, metadata !16, null} !19 = metadata !{i32 5, i32 5, metadata !16, null} -; CHECK: .ascii "GLOBAL" # DW_AT_name -; CHECK: .byte 1 # DW_AT_decl_file -; CHECK: .byte 1 # DW_AT_decl_line +; CHECK: .ascii "GLOBAL" +; CHECK: .byte 1 +; CHECK: .byte 1 -; CHECK: .ascii "LOCAL" # DW_AT_name -; CHECK: .byte 1 # DW_AT_decl_file -; CHECK: .byte 4 # DW_AT_decl_line +; CHECK: .ascii "LOCAL" +; CHECK: .byte 1 +; CHECK: .byte 4 From justin.holewinski at gmail.com Mon Sep 26 14:19:48 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Mon, 26 Sep 2011 19:19:48 -0000 Subject: [llvm-commits] [llvm] r140556 - /llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp Message-ID: <20110926191948.9CBFB2A6C12C@llvm.org> Author: jholewinski Date: Mon Sep 26 14:19:48 2011 New Revision: 140556 URL: http://llvm.org/viewvc/llvm-project?rev=140556&view=rev Log: PTX: Fix memcpy intrinsic to handle 64-bit pointers Modified: llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp Modified: llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp?rev=140556&r1=140555&r2=140556&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp Mon Sep 26 14:19:48 2011 @@ -58,6 +58,7 @@ SDValue TFOps[MAX_LOADS_IN_LDM]; SDValue Loads[MAX_LOADS_IN_LDM]; uint64_t SrcOff = 0, DstOff = 0; + EVT PointerType = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the // same number of stores. The loads and stores will get combined into @@ -66,8 +67,8 @@ for (i = 0; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { Loads[i] = DAG.getLoad(VT, dl, Chain, - DAG.getNode(ISD::ADD, dl, MVT::i32, Src, - DAG.getConstant(SrcOff, MVT::i32)), + DAG.getNode(ISD::ADD, dl, PointerType, Src, + DAG.getConstant(SrcOff, PointerType)), SrcPtrInfo.getWithOffset(SrcOff), isVolatile, false, 0); TFOps[i] = Loads[i].getValue(1); @@ -78,8 +79,8 @@ for (i = 0; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { TFOps[i] = DAG.getStore(Chain, dl, Loads[i], - DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, - DAG.getConstant(DstOff, MVT::i32)), + DAG.getNode(ISD::ADD, dl, PointerType, Dst, + DAG.getConstant(DstOff, PointerType)), DstPtrInfo.getWithOffset(DstOff), isVolatile, false, 0); DstOff += VTSize; @@ -105,8 +106,8 @@ } Loads[i] = DAG.getLoad(VT, dl, Chain, - DAG.getNode(ISD::ADD, dl, MVT::i32, Src, - DAG.getConstant(SrcOff, MVT::i32)), + DAG.getNode(ISD::ADD, dl, PointerType, Src, + DAG.getConstant(SrcOff, PointerType)), SrcPtrInfo.getWithOffset(SrcOff), false, false, 0); TFOps[i] = Loads[i].getValue(1); ++i; @@ -127,8 +128,8 @@ } TFOps[i] = DAG.getStore(Chain, dl, Loads[i], - DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, - DAG.getConstant(DstOff, MVT::i32)), + DAG.getNode(ISD::ADD, dl, PointerType, Dst, + DAG.getConstant(DstOff, PointerType)), DstPtrInfo.getWithOffset(DstOff), false, false, 0); ++i; DstOff += VTSize; From James.Molloy at arm.com Mon Sep 26 14:36:12 2011 From: James.Molloy at arm.com (James Molloy) Date: Mon, 26 Sep 2011 20:36:12 +0100 Subject: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll In-Reply-To: References: <20110926174042.E57FA2A6C12C@llvm.org>, Message-ID: Hi Jakob, I thought I needed one, but after discussion with Devang and Eric I was convinced it was fine to remove it! I'll re-add it immediately. Thanks for bringing this to my attention. Out of interest, what platform are you running on where it managed to fail? Cheers, James ________________________________________ From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Jakob Stoklund Olesen [stoklund at 2pi.dk] Sent: 26 September 2011 19:21 To: James Molloy Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll On Sep 26, 2011, at 10:40 AM, James Molloy wrote: > Author: jamesm > Date: Mon Sep 26 12:40:42 2011 > New Revision: 140539 > > URL: http://llvm.org/viewvc/llvm-project?rev=140539&view=rev > Log: > Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more. Hi James. Please make sure your test case is platform agnostic. ******************** TEST 'LLVM :: DebugInfo/2011-09-26-GlobalVarContext.ll' FAILED ********************Script: Command Output (stderr): -- test/DebugInfo/2011-09-26-GlobalVarContext.ll:41:10: error: expected string not found in input ; CHECK: .ascii "GLOBAL" # DW_AT_name ^ :1:2: note: scanning from here .section __TEXT,__text,regular,pure_instructions ^ :75:2: note: possible intended match here .ascii "GLOBAL" ## DW_AT_name ^ -- You can for example add a triple argument. /jakob _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From James.Molloy at arm.com Mon Sep 26 14:38:23 2011 From: James.Molloy at arm.com (James Molloy) Date: Mon, 26 Sep 2011 20:38:23 +0100 Subject: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll In-Reply-To: References: <20110926174042.E57FA2A6C12C@llvm.org>, , Message-ID: Hi, Strike that, I see Eli already committed a fix. Apologies to any concerned - I hadn't thought the asm output would be different on Darwin! Cheers, James ________________________________________ From: James Molloy Sent: 26 September 2011 20:36 To: Jakob Stoklund Olesen Cc: llvm-commits at cs.uiuc.edu Subject: RE: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll Hi Jakob, I thought I needed one, but after discussion with Devang and Eric I was convinced it was fine to remove it! I'll re-add it immediately. Thanks for bringing this to my attention. Out of interest, what platform are you running on where it managed to fail? Cheers, James ________________________________________ From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Jakob Stoklund Olesen [stoklund at 2pi.dk] Sent: 26 September 2011 19:21 To: James Molloy Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll On Sep 26, 2011, at 10:40 AM, James Molloy wrote: > Author: jamesm > Date: Mon Sep 26 12:40:42 2011 > New Revision: 140539 > > URL: http://llvm.org/viewvc/llvm-project?rev=140539&view=rev > Log: > Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more. Hi James. Please make sure your test case is platform agnostic. ******************** TEST 'LLVM :: DebugInfo/2011-09-26-GlobalVarContext.ll' FAILED ********************Script: Command Output (stderr): -- test/DebugInfo/2011-09-26-GlobalVarContext.ll:41:10: error: expected string not found in input ; CHECK: .ascii "GLOBAL" # DW_AT_name ^ :1:2: note: scanning from here .section __TEXT,__text,regular,pure_instructions ^ :75:2: note: possible intended match here .ascii "GLOBAL" ## DW_AT_name ^ -- You can for example add a triple argument. /jakob _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From stoklund at 2pi.dk Mon Sep 26 15:03:38 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 26 Sep 2011 13:03:38 -0700 Subject: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll In-Reply-To: References: <20110926174042.E57FA2A6C12C@llvm.org> Message-ID: On Sep 26, 2011, at 12:36 PM, James Molloy wrote: > Hi Jakob, > > I thought I needed one, but after discussion with Devang and Eric I was convinced it was fine to remove it! > > I'll re-add it immediately. > > Thanks for bringing this to my attention. Out of interest, what platform are you running on where it managed to fail? Darwin11 a.k.a. OS X Lion. /jakob From echristo at apple.com Mon Sep 26 15:04:34 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 26 Sep 2011 13:04:34 -0700 Subject: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll In-Reply-To: References: <20110926174042.E57FA2A6C12C@llvm.org> Message-ID: On Sep 26, 2011, at 12:36 PM, James Molloy wrote: > Hi Jakob, > > I thought I needed one, but after discussion with Devang and Eric I was convinced it was fine to remove it! > I saw that too and laughed. Sorry about that. In general you can make them independent, you may just have to be clever about how you write the matching. -eric From stoklund at 2pi.dk Mon Sep 26 15:07:45 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 26 Sep 2011 13:07:45 -0700 Subject: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll In-Reply-To: References: <20110926174042.E57FA2A6C12C@llvm.org> Message-ID: <734A9099-D8A7-48B1-87BE-981B6453DB4D@2pi.dk> On Sep 26, 2011, at 1:04 PM, Eric Christopher wrote: > > On Sep 26, 2011, at 12:36 PM, James Molloy wrote: > >> Hi Jakob, >> >> I thought I needed one, but after discussion with Devang and Eric I was convinced it was fine to remove it! >> > > I saw that too and laughed. Sorry about that. > > In general you can make them independent, you may just have to be clever about how you write the matching. In fact, no triple and clever matching gives you better test coverage. Most people chicken out and add a triple, though. /jakob From echristo at apple.com Mon Sep 26 15:08:27 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 26 Sep 2011 13:08:27 -0700 Subject: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll In-Reply-To: <734A9099-D8A7-48B1-87BE-981B6453DB4D@2pi.dk> References: <20110926174042.E57FA2A6C12C@llvm.org> <734A9099-D8A7-48B1-87BE-981B6453DB4D@2pi.dk> Message-ID: <2B1D1D41-40B3-4746-8703-F78823D576D5@apple.com> On Sep 26, 2011, at 1:07 PM, Jakob Stoklund Olesen wrote: > > On Sep 26, 2011, at 1:04 PM, Eric Christopher wrote: > >> >> On Sep 26, 2011, at 12:36 PM, James Molloy wrote: >> >>> Hi Jakob, >>> >>> I thought I needed one, but after discussion with Devang and Eric I was convinced it was fine to remove it! >>> >> >> I saw that too and laughed. Sorry about that. >> >> In general you can make them independent, you may just have to be clever about how you write the matching. > > In fact, no triple and clever matching gives you better test coverage. > > Most people chicken out and add a triple, though. Heh. That was why we were trying to get James not to do so :) -eric From echristo at apple.com Mon Sep 26 15:11:02 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 26 Sep 2011 13:11:02 -0700 Subject: [llvm-commits] [llvm] r140517 - /llvm/trunk/test/CodeGen/CBackend/X86/dg.exp In-Reply-To: <20110926064427.743B02A6C12C@llvm.org> References: <20110926064427.743B02A6C12C@llvm.org> Message-ID: <09CE3E7E-C464-43D7-89D7-E76785D5E6F6@apple.com> On Sep 25, 2011, at 11:44 PM, David Meyer wrote: > Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported Ah thanks. Looks like none of the bots run --enable-targets= -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110926/73dde8bd/attachment.html From eli.friedman at gmail.com Mon Sep 26 15:15:28 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 26 Sep 2011 20:15:28 -0000 Subject: [llvm-commits] [llvm] r140557 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll test/Analysis/BasicAA/cas.ll Message-ID: <20110926201528.8410D2A6C12C@llvm.org> Author: efriedma Date: Mon Sep 26 15:15:28 2011 New Revision: 140557 URL: http://llvm.org/viewvc/llvm-project?rev=140557&view=rev Log: Enhance alias analysis for atomic instructions a bit. Upgrade a couple alias-analysis tests to the new atomic instructions. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll llvm/trunk/test/Analysis/BasicAA/cas.ll Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=140557&r1=140556&r2=140557&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Mon Sep 26 15:15:28 2011 @@ -136,6 +136,8 @@ Location getLocation(const LoadInst *LI); Location getLocation(const StoreInst *SI); Location getLocation(const VAArgInst *VI); + Location getLocation(const AtomicCmpXchgInst *CXI); + Location getLocation(const AtomicRMWInst *RMWI); static Location getLocationForSource(const MemTransferInst *MTI); static Location getLocationForDest(const MemIntrinsic *MI); @@ -426,10 +428,7 @@ /// getModRefInfo (for cmpxchges) - Return whether information about whether /// a particular cmpxchg modifies or reads the specified memory location. - ModRefResult getModRefInfo(const AtomicCmpXchgInst *CX, const Location &Loc) { - // Conservatively correct. (But there are obvious ways to be smarter.) - return ModRef; - } + ModRefResult getModRefInfo(const AtomicCmpXchgInst *CX, const Location &Loc); /// getModRefInfo (for cmpxchges) - A convenience wrapper. ModRefResult getModRefInfo(const AtomicCmpXchgInst *CX, @@ -439,10 +438,7 @@ /// getModRefInfo (for atomicrmws) - Return whether information about whether /// a particular atomicrmw modifies or reads the specified memory location. - ModRefResult getModRefInfo(const AtomicRMWInst *RMW, const Location &Loc) { - // Conservatively correct. (But there are obvious ways to be smarter.) - return ModRef; - } + ModRefResult getModRefInfo(const AtomicRMWInst *RMW, const Location &Loc); /// getModRefInfo (for atomicrmws) - A convenience wrapper. ModRefResult getModRefInfo(const AtomicRMWInst *RMW, Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=140557&r1=140556&r2=140557&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Mon Sep 26 15:15:28 2011 @@ -237,6 +237,19 @@ VI->getMetadata(LLVMContext::MD_tbaa)); } +AliasAnalysis::Location +AliasAnalysis::getLocation(const AtomicCmpXchgInst *CXI) { + return Location(CXI->getPointerOperand(), + getTypeStoreSize(CXI->getCompareOperand()->getType()), + CXI->getMetadata(LLVMContext::MD_tbaa)); +} + +AliasAnalysis::Location +AliasAnalysis::getLocation(const AtomicRMWInst *RMWI) { + return Location(RMWI->getPointerOperand(), + getTypeStoreSize(RMWI->getValOperand()->getType()), + RMWI->getMetadata(LLVMContext::MD_tbaa)); +} AliasAnalysis::Location AliasAnalysis::getLocationForSource(const MemTransferInst *MTI) { @@ -317,6 +330,33 @@ return ModRef; } +AliasAnalysis::ModRefResult +AliasAnalysis::getModRefInfo(const AtomicCmpXchgInst *CX, const Location &Loc) { + // Acquire/Release cmpxchg has properties that matter for arbitrary addresses. + if (CX->getOrdering() > Monotonic) + return ModRef; + + // If the cmpxchg address does not alias the location, it does not access it. + if (!alias(getLocation(CX), Loc)) + return NoModRef; + + return ModRef; +} + +AliasAnalysis::ModRefResult +AliasAnalysis::getModRefInfo(const AtomicRMWInst *RMW, const Location &Loc) { + // Acquire/Release atomicrmw has properties that matter for arbitrary addresses. + if (RMW->getOrdering() > Monotonic) + return ModRef; + + // If the atomicrmw address does not alias the location, it does not access it. + if (!alias(getLocation(RMW), Loc)) + return NoModRef; + + return ModRef; +} + + // AliasAnalysis destructor: DO NOT move this to the header file for // AliasAnalysis or else clients of the AliasAnalysis class may not depend on // the AliasAnalysis.o file in the current .a file, causing alias analysis Modified: llvm/trunk/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll?rev=140557&r1=140556&r2=140557&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll (original) +++ llvm/trunk/test/Analysis/BasicAA/2009-10-13-AtomicModRef.ll Mon Sep 26 15:15:28 2011 @@ -1,14 +1,12 @@ ; RUN: opt -basicaa -gvn -instcombine -S < %s | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" -declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) - define i8 @foo(i8* %ptr) { %P = getelementptr i8* %ptr, i32 0 %Q = getelementptr i8* %ptr, i32 1 ; CHECK: getelementptr %X = load i8* %P - %Y = call i8 @llvm.atomic.load.add.i8.p0i8(i8* %Q, i8 1) + %Y = atomicrmw add i8* %Q, i8 1 monotonic %Z = load i8* %P ; CHECK-NOT: = load %A = sub i8 %X, %Z Modified: llvm/trunk/test/Analysis/BasicAA/cas.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/cas.ll?rev=140557&r1=140556&r2=140557&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/cas.ll (original) +++ llvm/trunk/test/Analysis/BasicAA/cas.ll Mon Sep 26 15:15:28 2011 @@ -6,10 +6,8 @@ define i32 @main() { %a = load i32* @flag0 - %b = tail call i32 @llvm.atomic.swap.i32.p0i32(i32* @turn, i32 1) + %b = atomicrmw xchg i32* @turn, i32 1 monotonic %c = load i32* @flag0 %d = sub i32 %a, %c ret i32 %d } - -declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind From eli.friedman at gmail.com Mon Sep 26 15:15:56 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 26 Sep 2011 20:15:56 -0000 Subject: [llvm-commits] [llvm] r140558 - in /llvm/trunk/test/Transforms/LowerAtomic: atomic-load.ll atomic-swap.ll Message-ID: <20110926201556.98EA12A6C12C@llvm.org> Author: efriedma Date: Mon Sep 26 15:15:56 2011 New Revision: 140558 URL: http://llvm.org/viewvc/llvm-project?rev=140558&view=rev Log: Upgrade a couple more tests to the new atomic instructions. Modified: llvm/trunk/test/Transforms/LowerAtomic/atomic-load.ll llvm/trunk/test/Transforms/LowerAtomic/atomic-swap.ll Modified: llvm/trunk/test/Transforms/LowerAtomic/atomic-load.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LowerAtomic/atomic-load.ll?rev=140558&r1=140557&r2=140558&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LowerAtomic/atomic-load.ll (original) +++ llvm/trunk/test/Transforms/LowerAtomic/atomic-load.ll Mon Sep 26 15:15:56 2011 @@ -1,13 +1,9 @@ ; RUN: opt < %s -loweratomic -S | FileCheck %s -declare i8 @llvm.atomic.load.add.i8.p0i8(i8* %ptr, i8 %delta) -declare i8 @llvm.atomic.load.nand.i8.p0i8(i8* %ptr, i8 %delta) -declare i8 @llvm.atomic.load.min.i8.p0i8(i8* %ptr, i8 %delta) - define i8 @add() { ; CHECK: @add %i = alloca i8 - %j = call i8 @llvm.atomic.load.add.i8.p0i8(i8* %i, i8 42) + %j = atomicrmw add i8* %i, i8 42 monotonic ; CHECK: [[INST:%[a-z0-9]+]] = load ; CHECK-NEXT: add ; CHECK-NEXT: store @@ -18,7 +14,7 @@ define i8 @nand() { ; CHECK: @nand %i = alloca i8 - %j = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* %i, i8 42) + %j = atomicrmw nand i8* %i, i8 42 monotonic ; CHECK: [[INST:%[a-z0-9]+]] = load ; CHECK-NEXT: and ; CHECK-NEXT: xor @@ -30,7 +26,7 @@ define i8 @min() { ; CHECK: @min %i = alloca i8 - %j = call i8 @llvm.atomic.load.min.i8.p0i8(i8* %i, i8 42) + %j = atomicrmw min i8* %i, i8 42 monotonic ; CHECK: [[INST:%[a-z0-9]+]] = load ; CHECK-NEXT: icmp ; CHECK-NEXT: select Modified: llvm/trunk/test/Transforms/LowerAtomic/atomic-swap.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LowerAtomic/atomic-swap.ll?rev=140558&r1=140557&r2=140558&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LowerAtomic/atomic-swap.ll (original) +++ llvm/trunk/test/Transforms/LowerAtomic/atomic-swap.ll Mon Sep 26 15:15:56 2011 @@ -1,12 +1,9 @@ ; RUN: opt < %s -loweratomic -S | FileCheck %s -declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* %ptr, i8 %cmp, i8 %val) -declare i8 @llvm.atomic.swap.i8.p0i8(i8* %ptr, i8 %val) - define i8 @cmpswap() { ; CHECK: @cmpswap %i = alloca i8 - %j = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* %i, i8 0, i8 42) + %j = cmpxchg i8* %i, i8 0, i8 42 monotonic ; CHECK: [[INST:%[a-z0-9]+]] = load ; CHECK-NEXT: icmp ; CHECK-NEXT: select @@ -18,7 +15,7 @@ define i8 @swap() { ; CHECK: @swap %i = alloca i8 - %j = call i8 @llvm.atomic.swap.i8.p0i8(i8* %i, i8 42) + %j = atomicrmw xchg i8* %i, i8 42 monotonic ; CHECK: [[INST:%[a-z0-9]+]] = load ; CHECK-NEXT: store ret i8 %j From eli.friedman at gmail.com Mon Sep 26 15:27:49 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 26 Sep 2011 20:27:49 -0000 Subject: [llvm-commits] [llvm] r140559 - in /llvm/trunk/test: CodeGen/ARM/atomic-cmp.ll CodeGen/ARM/atomic-op.ll CodeGen/Mips/atomic.ll Transforms/LowerAtomic/barrier.ll Message-ID: <20110926202749.E9C162A6C12C@llvm.org> Author: efriedma Date: Mon Sep 26 15:27:49 2011 New Revision: 140559 URL: http://llvm.org/viewvc/llvm-project?rev=140559&view=rev Log: Convert more tests over to the new atomic instructions. Modified: llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll llvm/trunk/test/CodeGen/ARM/atomic-op.ll llvm/trunk/test/CodeGen/Mips/atomic.ll llvm/trunk/test/Transforms/LowerAtomic/barrier.ll Modified: llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll?rev=140559&r1=140558&r2=140559&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll (original) +++ llvm/trunk/test/CodeGen/ARM/atomic-cmp.ll Mon Sep 26 15:27:49 2011 @@ -10,8 +10,6 @@ ; T2: t: ; T2: ldrexb ; T2: strexb - %tmp0 = tail call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* %a, i8 %b, i8 %c) + %tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic ret i8 %tmp0 } - -declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* nocapture, i8, i8) nounwind Modified: llvm/trunk/test/CodeGen/ARM/atomic-op.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=140559&r1=140558&r2=140559&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/atomic-op.ll (original) +++ llvm/trunk/test/CodeGen/ARM/atomic-op.ll Mon Sep 26 15:27:49 2011 @@ -24,80 +24,58 @@ ; CHECK: ldrex ; CHECK: add ; CHECK: strex - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val1, i32 %tmp ) ; :0 [#uses=1] + %0 = atomicrmw add i32* %val1, i32 %tmp monotonic store i32 %0, i32* %old ; CHECK: ldrex ; CHECK: sub ; CHECK: strex - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 30 ) ; :1 [#uses=1] + %1 = atomicrmw sub i32* %val2, i32 30 monotonic store i32 %1, i32* %old ; CHECK: ldrex ; CHECK: add ; CHECK: strex - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val2, i32 1 ) ; :2 [#uses=1] + %2 = atomicrmw add i32* %val2, i32 1 monotonic store i32 %2, i32* %old ; CHECK: ldrex ; CHECK: sub ; CHECK: strex - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 1 ) ; :3 [#uses=1] + %3 = atomicrmw sub i32* %val2, i32 1 monotonic store i32 %3, i32* %old ; CHECK: ldrex ; CHECK: and ; CHECK: strex - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %andt, i32 4080 ) ; :4 [#uses=1] + %4 = atomicrmw and i32* %andt, i32 4080 monotonic store i32 %4, i32* %old ; CHECK: ldrex ; CHECK: or ; CHECK: strex - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %ort, i32 4080 ) ; :5 [#uses=1] + %5 = atomicrmw or i32* %ort, i32 4080 monotonic store i32 %5, i32* %old ; CHECK: ldrex ; CHECK: eor ; CHECK: strex - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %xort, i32 4080 ) ; :6 [#uses=1] + %6 = atomicrmw xor i32* %xort, i32 4080 monotonic store i32 %6, i32* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 16 ) ; :7 [#uses=1] + %7 = atomicrmw min i32* %val2, i32 16 monotonic store i32 %7, i32* %old %neg = sub i32 0, 1 ; [#uses=1] ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 %neg ) ; :8 [#uses=1] + %8 = atomicrmw min i32* %val2, i32 %neg monotonic store i32 %8, i32* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 1 ) ; :9 [#uses=1] + %9 = atomicrmw max i32* %val2, i32 1 monotonic store i32 %9, i32* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 0 ) ; :10 [#uses=1] + %10 = atomicrmw max i32* %val2, i32 0 monotonic store i32 %10, i32* %old ret void } - -declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.min.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.max.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.umax.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.umin.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=140559&r1=140558&r2=140559&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/atomic.ll (original) +++ llvm/trunk/test/CodeGen/Mips/atomic.ll Mon Sep 26 15:27:49 2011 @@ -1,24 +1,10 @@ ; RUN: llc -march=mipsel < %s | FileCheck %s - -declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind -declare i32 @llvm.atomic.load.nand.i32.p0i32(i32* nocapture, i32) nounwind -declare i32 @llvm.atomic.swap.i32.p0i32(i32* nocapture, i32) nounwind -declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* nocapture, i32, i32) nounwind - -declare i8 @llvm.atomic.load.add.i8.p0i8(i8* nocapture, i8) nounwind -declare i8 @llvm.atomic.load.sub.i8.p0i8(i8* nocapture, i8) nounwind -declare i8 @llvm.atomic.load.nand.i8.p0i8(i8* nocapture, i8) nounwind -declare i8 @llvm.atomic.swap.i8.p0i8(i8* nocapture, i8) nounwind -declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* nocapture, i8, i8) nounwind - -declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind - @x = common global i32 0, align 4 define i32 @AtomicLoadAdd32(i32 %incr) nounwind { entry: - %0 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* @x, i32 %incr) + %0 = atomicrmw add i32* @x, i32 %incr monotonic ret i32 %0 ; CHECK: AtomicLoadAdd32: @@ -32,7 +18,7 @@ define i32 @AtomicLoadNand32(i32 %incr) nounwind { entry: - %0 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* @x, i32 %incr) + %0 = atomicrmw nand i32* @x, i32 %incr monotonic ret i32 %0 ; CHECK: AtomicLoadNand32: @@ -50,7 +36,7 @@ %newval.addr = alloca i32, align 4 store i32 %newval, i32* %newval.addr, align 4 %tmp = load i32* %newval.addr, align 4 - %0 = call i32 @llvm.atomic.swap.i32.p0i32(i32* @x, i32 %tmp) + %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic ret i32 %0 ; CHECK: AtomicSwap32: @@ -66,7 +52,7 @@ %newval.addr = alloca i32, align 4 store i32 %newval, i32* %newval.addr, align 4 %tmp = load i32* %newval.addr, align 4 - %0 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* @x, i32 %oldval, i32 %tmp) + %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic ret i32 %0 ; CHECK: AtomicCmpSwap32: @@ -85,7 +71,7 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { entry: - %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @y, i8 %incr) + %0 = atomicrmw add i8* @y, i8 %incr monotonic ret i8 %0 ; CHECK: AtomicLoadAdd8: @@ -116,7 +102,7 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { entry: - %0 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @y, i8 %incr) + %0 = atomicrmw sub i8* @y, i8 %incr monotonic ret i8 %0 ; CHECK: AtomicLoadSub8: @@ -147,7 +133,7 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { entry: - %0 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @y, i8 %incr) + %0 = atomicrmw nand i8* @y, i8 %incr monotonic ret i8 %0 ; CHECK: AtomicLoadNand8: @@ -179,7 +165,7 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { entry: - %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @y, i8 %newval) + %0 = atomicrmw xchg i8* @y, i8 %newval monotonic ret i8 %0 ; CHECK: AtomicSwap8: @@ -208,7 +194,7 @@ define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind { entry: - %0 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @y, i8 %oldval, i8 %newval) + %0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic ret i8 %0 ; CHECK: AtomicCmpSwap8: @@ -245,9 +231,7 @@ define i32 @CheckSync(i32 %v) nounwind noinline { entry: - tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) - %0 = tail call i32 @llvm.atomic.load.add.i32.p0i32(i32* @countsint, i32 %v) - tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + %0 = atomicrmw add i32* @countsint, i32 %v seq_cst ret i32 %0 ; CHECK: CheckSync: Modified: llvm/trunk/test/Transforms/LowerAtomic/barrier.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LowerAtomic/barrier.ll?rev=140559&r1=140558&r2=140559&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LowerAtomic/barrier.ll (original) +++ llvm/trunk/test/Transforms/LowerAtomic/barrier.ll Mon Sep 26 15:27:49 2011 @@ -1,10 +1,8 @@ ; RUN: opt < %s -loweratomic -S | FileCheck %s -declare void @llvm.memory.barrier(i1 %ll, i1 %ls, i1 %sl, i1 %ss, i1 %device) - define void @barrier() { ; CHECK: @barrier - call void @llvm.memory.barrier(i1 0, i1 0, i1 0, i1 0, i1 0) + fence seq_cst ; CHECK-NEXT: ret ret void } From resistor at mac.com Mon Sep 26 16:06:22 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 26 Sep 2011 21:06:22 -0000 Subject: [llvm-commits] [llvm] r140560 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/Disassembler/ARMDisassembler.cpp utils/TableGen/EDEmitter.cpp Message-ID: <20110926210623.12A7A2A6C12C@llvm.org> Author: resistor Date: Mon Sep 26 16:06:22 2011 New Revision: 140560 URL: http://llvm.org/viewvc/llvm-project?rev=140560&view=rev Log: ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=140560&r1=140559&r2=140560&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Sep 26 16:06:22 2011 @@ -28,6 +28,18 @@ let ParserMatchClass = it_mask_asmoperand; } +// t2_shift_imm: An integer that encodes a shift amount and the type of shift +// (asr or lsl). The 6-bit immediate encodes as: +// {5} 0 ==> lsl +// 1 asr +// {4-0} imm5 shift amount. +// asr #32 not allowed +def t2_shift_imm : Operand { + let PrintMethod = "printShiftImmOperand"; + let ParserMatchClass = ShifterImmAsmOperand; + let DecoderMethod = "DecodeT2ShifterImmOperand"; +} + // Shifted operands. No register controlled shifts for Thumb2. // Note: We do not support rrx shifted operands yet. def t2_so_reg : Operand, // reg imm @@ -2023,7 +2035,8 @@ } def t2SSAT: T2SatI< - (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh), + (outs rGPR:$Rd), + (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { let Inst{31-27} = 0b11110; let Inst{25-22} = 0b1100; @@ -2047,7 +2060,8 @@ } def t2USAT: T2SatI< - (outs rGPR:$Rd), (ins imm0_31:$sat_imm, rGPR:$Rn, shift_imm:$sh), + (outs rGPR:$Rd), + (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { let Inst{31-27} = 0b11110; let Inst{25-22} = 0b1110; @@ -3928,6 +3942,8 @@ (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; def : t2InstAlias<"sxth${p} $Rd, $Rm", (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; +def : t2InstAlias<"sxth${p} $Rd, $Rm", + (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm", (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=140560&r1=140559&r2=140560&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Sep 26 16:06:22 2011 @@ -2255,7 +2255,11 @@ Error(E, "'asr' shift amount must be in range [1,32]"); return MatchOperand_ParseFail; } - // asr #32 encoded as asr #0. + // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. + if (isThumb() && Val == 32) { + Error(E, "'asr #32' shift amount not allowed in Thumb mode"); + return MatchOperand_ParseFail; + } if (Val == 32) Val = 0; } else { // Shift amount must be in [1,32] Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=140560&r1=140559&r2=140560&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Sep 26 16:06:22 2011 @@ -307,6 +307,9 @@ uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); + #include "ARMGenDisassemblerTables.inc" @@ -3876,3 +3879,14 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, + uint64_t Address, + const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + // Shift of "asr #32" is not allowed in Thumb2 mode. + if (Val == 0x20) S = MCDisassembler::SoftFail; + Inst.addOperand(MCOperand::CreateImm(Val)); + return S; +} + Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=140560&r1=140559&r2=140560&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Sep 26 16:06:22 2011 @@ -610,6 +610,7 @@ IMM("t_adrlabel"); IMM("t2adrlabel"); IMM("shift_imm"); + IMM("t2_shift_imm"); IMM("neon_vcvt_imm32"); IMM("shr_imm8"); IMM("shr_imm16"); From isanbard at gmail.com Mon Sep 26 16:06:33 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 26 Sep 2011 21:06:33 -0000 Subject: [llvm-commits] [llvm] r140561 - /llvm/trunk/docs/ExceptionHandling.html Message-ID: <20110926210633.831B82A6C12C@llvm.org> Author: void Date: Mon Sep 26 16:06:33 2011 New Revision: 140561 URL: http://llvm.org/viewvc/llvm-project?rev=140561&view=rev Log: Some minor (and more involved) cleanups. No real context changes. Modified: llvm/trunk/docs/ExceptionHandling.html Modified: llvm/trunk/docs/ExceptionHandling.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ExceptionHandling.html?rev=140561&r1=140560&r2=140561&view=diff ============================================================================== --- llvm/trunk/docs/ExceptionHandling.html (original) +++ llvm/trunk/docs/ExceptionHandling.html Mon Sep 26 16:06:33 2011 @@ -66,7 +66,7 @@ handling information takes, which is useful for those interested in creating front-ends or dealing directly with the information. Further, this document provides specific examples of what exception handling information is used for - in C/C++.

+ in C and C++.

@@ -146,19 +146,19 @@

The runtime first attempts to find an exception frame corresponding to the function where the exception was thrown. If the programming language - (e.g. C++) supports exception handling, the exception frame contains a + supports exception handling (e.g. C++), the exception frame contains a reference to an exception table describing how to process the exception. If - the language (e.g. C) does not support exception handling, or if the + the language does not support exception handling (e.g. C), or if the exception needs to be forwarded to a prior activation, the exception frame contains information about how to unwind the current activation and restore the state of the prior activation. This process is repeated until the - exception is handled. If the exception is not handled and no activations + exception is handled. If the exception is not handled and no activations remain, then the application is terminated with an appropriate error message.

Because different programming languages have different behaviors when handling exceptions, the exception handling ABI provides a mechanism for - supplying personalities. An exception handling personality is defined + supplying personalities. An exception handling personality is defined by way of a personality function (e.g. __gxx_personality_v0 in C++), which receives the context of the exception, an exception structure containing the exception object type and value, and a reference @@ -166,19 +166,20 @@ for the current compile unit is specified in a common exception frame.

-

The organization of an exception table is language dependent. For C++, an +

The organization of an exception table is language dependent. For C++, an exception table is organized as a series of code ranges defining what to do - if an exception occurs in that range. Typically, the information associated + if an exception occurs in that range. Typically, the information associated with a range defines which types of exception objects (using C++ type info) that are handled in that range, and an associated action that - should take place. Actions typically pass control to a landing + should take place. Actions typically pass control to a landing pad.

-

A landing pad corresponds to the code found in the catch portion of - a try/catch sequence. When execution resumes at a landing - pad, it receives the exception structure and a selector corresponding to - the type of exception thrown. The selector is then used to determine - which catch should actually process the exception.

+

A landing pad corresponds roughly to the code found in the catch + portion of a try/catch sequence. When execution resumes at + a landing pad, it receives an exception structure and a + selector value corresponding to the type of exception + thrown. The selector is then used to determine which catch should + actually process the exception.

@@ -191,7 +192,7 @@
-

From the C++ developers perspective, exceptions are defined in terms of the +

From a C++ developer's perspective, exceptions are defined in terms of the throw and try/catch statements. In this section we will describe the implementation of LLVM exception handling in terms of C++ examples.

@@ -204,17 +205,19 @@

Languages that support exception handling typically provide a throw - operation to initiate the exception process. Internally, a throw operation - breaks down into two steps.

+ operation to initiate the exception process. Internally, a throw + operation breaks down into two steps.

+
  1. A request is made to allocate exception space for an exception structure. This structure needs to survive beyond the current activation. This structure will contain the type and value of the object being thrown.
    2. +
  2. A call is made to the runtime to raise the exception, passing the exception structure as an argument.
-

In C++, the allocation of the exception structure is done by then +

In C++, the allocation of the exception structure is done by the __cxa_allocate_exception runtime function. The exception raising is handled by __cxa_throw. The type of the exception is represented using a C++ RTTI structure.

@@ -229,67 +232,73 @@

A call within the scope of a try statement can potentially raise an - exception. In those circumstances, the LLVM C++ front-end replaces the call - with an invoke instruction. Unlike a call, the invoke has - two potential continuation points: where to continue when the call succeeds - as per normal; and where to continue if the call raises an exception, either - by a throw or the unwinding of a throw.

+ exception. In those circumstances, the LLVM C++ front-end replaces the call + with an invoke instruction. Unlike a call, the invoke has + two potential continuation points:

+ +
    +
  1. where to continue when the call succeeds as per normal, and
    2. + +
  2. where to continue if the call raises an exception, either by a throw or + the unwinding of a throw
    3. +

The term used to define a the place where an invoke continues after - an exception is called a landing pad. LLVM landing pads are + an exception is called a landing pad. LLVM landing pads are conceptually alternative function entry points where an exception structure - reference and a type info index are passed in as arguments. The landing pad + reference and a type info index are passed in as arguments. The landing pad saves the exception structure reference and then proceeds to select the catch block that corresponds to the type info of the exception object.

The LLVM landingpad instruction is used to convey information about the landing pad to the back end. For C++, the landingpad instruction returns a pointer and - integer pair corresponding to the pointer to the exception structure and the - "selector value" respectively.

+ integer pair corresponding to the pointer to the exception structure + and the selector value respectively.

The landingpad instruction takes a reference to the personality function to be used for this try/catch sequence. The - remainder of the instruction is a list of catch and filter - clauses. The exception is tested against the clauses sequentially from first - to last. The selector value is a positive number if the exception matched a - type info, a negative number if it matched a filter, and zero if it matched a - cleanup. If nothing is matched, the behaviour of the program - is undefined. If a type info matched, then the - selector value is the index of the type info in the exception table, which - can be obtained using the + remainder of the instruction is a list of cleanup, catch, + and filter clauses. The exception is tested against the clauses + sequentially from first to last. The selector value is a positive number if + the exception matched a type info, a negative number if it matched a filter, + and zero if it matched a cleanup. If nothing is matched, the behavior of the + program is undefined. If a type info matched, + then the selector value is the index of the type info in the exception table, + which can be obtained using the llvm.eh.typeid.for intrinsic.

Once the landing pad has the type info selector, the code branches to the code for the first catch. The catch then checks the value of the type info selector against the index of type info for that catch. Since the type info - index is not known until all the type info have been gathered in the backend, - the catch code will call the + index is not known until all the type infos have been gathered in the + backend, the catch code must call the llvm.eh.typeid.for intrinsic to determine the index for a given type info. If the catch fails to match the - selector then control is passed on to the next catch. Note: Since the landing - pad will not be used if there is no match in the list of type info on the - call to the landingpad - instruction, then neither the last catch nor catch all need to - perform the check against the selector.

+ selector then control is passed on to the next catch.

+ +

Note: Since the landing pad will not be used if there is no match in + the list of type info on the call to the landingpad instruction, + then neither the last catch nor catch all need to perform the check + against the selector.

-

Finally, the entry and exit of catch code is bracketed with calls - to __cxa_begin_catch and __cxa_end_catch.

+

Finally, the entry and exit of catch code is bracketed with calls to + __cxa_begin_catch and __cxa_end_catch.

    -
  • __cxa_begin_catch takes a exception structure reference as an +
  • __cxa_begin_catch takes an exception structure reference as an argument and returns the value of the exception object.
  • __cxa_end_catch takes no arguments. This function:

    1. Locates the most recently caught exception and decrements its handler count,
      2. -
    2. Removes the exception from the "caught" stack if the handler count - goes to zero, and
      3. -
    3. Destroys the exception if the handler count goes to zero, and the +
    4. Removes the exception from the caught stack if the handler + count goes to zero, and
      5. +
    5. Destroys the exception if the handler count goes to zero and the exception was not re-thrown by throw.
    -

    Note: a rethrow from within the catch may replace this call with +

    Note: a rethrow from within the catch may replace this call with a __cxa_rethrow.

@@ -303,24 +312,24 @@

A cleanup is extra code which needs to be run as part of unwinding a scope. - C++ destructors are a prominent example, but other languages and language - extensions provide a variety of different kinds of cleanup. In general, a + C++ destructors are a typical example, but other languages and language + extensions provide a variety of different kinds of cleanups. In general, a landing pad may need to run arbitrary amounts of cleanup code before actually - entering a catch block. To indicate the presence of cleanups, a + entering a catch block. To indicate the presence of cleanups, a landingpad instruction should have a cleanup clause. Otherwise, the unwinder will not stop at the landing pad if there are no catches or filters that require it to.

-

Do not allow a new exception to propagate out of the execution of a - cleanup. This can corrupt the internal state of the unwinder. - Different languages describe different high-level semantics for - these situations: for example, C++ requires that the process be - terminated, whereas Ada cancels both exceptions and throws a third.

+

Note: Do not allow a new exception to propagate out of the execution + of a cleanup. This can corrupt the internal state of the unwinder. + Different languages describe different high-level semantics for these + situations: for example, C++ requires that the process be terminated, whereas + Ada cancels both exceptions and throws a third.

-

When all cleanups have completed, if the exception is not handled - by the current function, resume unwinding by calling the +

When all cleanups are finished, if the exception is not handled by the + current function, resume unwinding by calling the resume instruction, passing in - the results of the landingpad instruction for the original landing + the result of the landingpad instruction for the original landing pad.

@@ -332,9 +341,9 @@
-

C++ allows the specification of which exception types can be thrown from a - function. To represent this a top level landing pad may exist to filter out - invalid types. To express this in LLVM code the +

C++ allows the specification of which exception types may be thrown from a + function. To represent this, a top level landing pad may exist to filter out + invalid types. To express this in LLVM code the landingpad instruction will have a filter clause. The clause consists of an array of type infos. landingpad will return a negative value if the exception does not @@ -358,22 +367,22 @@

The unwinder delegates the decision of whether to stop in a call frame to - that call frame's language-specific personality function. Not all - personalities functions guarantee that they will stop to perform - cleanups. For example, the GNU C++ personality doesn't do so unless the - exception is actually caught somewhere further up the stack. When using this - personality to implement EH for a language that guarantees that cleanups will - always be run, be sure to indicate a catch-all in the + that call frame's language-specific personality function. Not all personality + functions guarantee that they will stop to perform cleanups. For example, the + GNU C++ personality function doesn't do so unless the exception is actually + caught somewhere further up the stack. When using this personality to + implement EH for a language that guarantees that cleanups will always be run + (e.g. Ada), be sure to indicate a catch-all in the landingpad instruction rather than just cleanups.

In order for inlining to behave correctly, landing pads must be prepared to - handle selector results that they did not originally advertise. Suppose that + handle selector results that they did not originally advertise. Suppose that a function catches exceptions of type A, and it's inlined into a - function that catches exceptions of type B. The inliner will update + function that catches exceptions of type B. The inliner will update the landingpad instruction for the inlined landing pad to include - the fact that B is caught. If that landing pad assumes that it will - only be entered to catch an A, it's in for a rude surprise. + the fact that B is also caught. If that landing pad assumes that it + will only be entered to catch an A, it's in for a rude awakening. Consequently, landing pads must test for the selector results they understand and then resume exception propagation with the resume instruction if none of @@ -393,7 +402,7 @@

In addition to the landingpad and resume instructions, LLVM uses - several intrinsic functions (name prefixed with "llvm.eh") to + several intrinsic functions (name prefixed with llvm.eh) to provide exception handling information at various points in generated code.

@@ -405,7 +414,7 @@ 
-  i32 %llvm.eh.typeid.for(i8*)
+  i32 @llvm.eh.typeid.for(i8* %type_info)

This intrinsic returns the type info index in the exception table of the @@ -423,16 +432,16 @@ 

-  i32 %llvm.eh.sjlj.setjmp(i8*)
+  i32 @llvm.eh.sjlj.setjmp(i8* %setjmp_buf)
-

The SJLJ exception handling uses this intrinsic to force register saving for - the current function and to store the address of the following instruction - for use as a destination address by - llvm.eh.sjlj.longjmp. The buffer format and the overall - functioning of this intrinsic is compatible with the GCC - __builtin_setjmp implementation, allowing code built with the - two compilers to interoperate.

+

For SJLJ based exception handling, this intrinsic forces register saving for + the current function and stores the address of the following instruction for + use as a destination address + by llvm.eh.sjlj.longjmp. The + buffer format and the overall functioning of this intrinsic is compatible + with the GCC __builtin_setjmp implementation allowing code built + with the clang and GCC to interoperate.

The single parameter is a pointer to a five word buffer in which the calling context is saved. The front end places the frame pointer in the first word, @@ -452,16 +461,15 @@ 

-  void %llvm.eh.sjlj.setjmp(i8*)
+  void @llvm.eh.sjlj.longjmp(i8* %setjmp_buf)
-

The llvm.eh.sjlj.longjmp - intrinsic is used to implement __builtin_longjmp() for SJLJ - style exception handling. The single parameter is a pointer to a - buffer populated by - llvm.eh.sjlj.setjmp. The frame pointer and stack pointer - are restored from the buffer, then control is transferred to the - destination address.

+

For SJLJ based exception handling, the llvm.eh.sjlj.longjmp + intrinsic is used to implement __builtin_longjmp(). The single + parameter is a pointer to a buffer populated + by llvm.eh.sjlj.setjmp. The frame + pointer and stack pointer are restored from the buffer, then control is + transferred to the destination address.

@@ -472,14 +480,13 @@ 
-  i8* %llvm.eh.sjlj.lsda()
+  i8* @llvm.eh.sjlj.lsda()
-

Used for SJLJ based exception handling, the - llvm.eh.sjlj.lsda intrinsic returns the address of the Language - Specific Data Area (LSDA) for the current function. The SJLJ front-end code - stores this address in the exception handling function context for use by the - runtime.

+

For SJLJ based exception handling, the llvm.eh.sjlj.lsda intrinsic + returns the address of the Language Specific Data Area (LSDA) for the current + function. The SJLJ front-end code stores this address in the exception + handling function context for use by the runtime.

@@ -491,13 +498,13 @@ 
-  void %llvm.eh.sjlj.callsite(i32)
+  void @llvm.eh.sjlj.callsite(i32 %call_site_num)
-

For SJLJ based exception handling, the - llvm.eh.sjlj.callsite intrinsic identifies the callsite value - associated with the following invoke instruction. This is used to ensure - that landing pad entries in the LSDA are generated in the matching order.

+

For SJLJ based exception handling, the llvm.eh.sjlj.callsite + intrinsic identifies the callsite value associated with the + following invoke instruction. This is used to ensure that landing + pad entries in the LSDA are generated in matching order.

@@ -509,12 +516,12 @@ 
-  void %llvm.eh.sjlj.dispatchsetup(i32)
+  void @llvm.eh.sjlj.dispatchsetup(i32 %dispatch_value)
-

For SJLJ based exception handling, the - llvm.eh.sjlj.dispatchsetup intrinsic is used by targets to do - any unwind-edge setup they need. By default, no action is taken.

+

For SJLJ based exception handling, the llvm.eh.sjlj.dispatchsetup + intrinsic is used by targets to do any unwind edge setup they need. By + default, no action is taken.

@@ -528,7 +535,7 @@

There are two tables that are used by the exception handling runtime to - determine which actions should take place when an exception is thrown.

+ determine which actions should be taken when an exception is thrown.

@@ -538,13 +545,13 @@

An exception handling frame eh_frame is very similar to the unwind - frame used by dwarf debug info. The frame contains all the information + frame used by DWARF debug info. The frame contains all the information necessary to tear down the current frame and restore the state of the prior - frame. There is an exception handling frame for each function in a compile + frame. There is an exception handling frame for each function in a compile unit, plus a common exception handling frame that defines information common to all functions in the unit.

-

Todo - Table details here.

+
@@ -556,31 +563,17 @@

An exception table contains information about what actions to take when an - exception is thrown in a particular part of a function's code. There is one - exception table per function except leaf routines and functions that have - only calls to non-throwing functions will not need an exception table.

+ exception is thrown in a particular part of a function's code. There is one + exception table per function, except leaf functions and functions that have + calls only to non-throwing functions. They do not need an exception + table.

-

Todo - Table details here.

+

- -

- ToDo -

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    - -
  1. Testing/Testing/Testing.
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From isanbard at gmail.com Mon Sep 26 16:08:28 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 26 Sep 2011 21:08:28 -0000 Subject: [llvm-commits] [llvm] r140563 - /llvm/trunk/docs/ExceptionHandling.html Message-ID: <20110926210828.D93B12A6C12C@llvm.org> Author: void Date: Mon Sep 26 16:08:28 2011 New Revision: 140563 URL: http://llvm.org/viewvc/llvm-project?rev=140563&view=rev Log: Remove dead table entry. Modified: llvm/trunk/docs/ExceptionHandling.html Modified: llvm/trunk/docs/ExceptionHandling.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ExceptionHandling.html?rev=140563&r1=140562&r2=140563&view=diff ============================================================================== --- llvm/trunk/docs/ExceptionHandling.html (original) +++ llvm/trunk/docs/ExceptionHandling.html Mon Sep 26 16:08:28 2011 @@ -45,7 +45,6 @@
  • Exception Handling Frame
  • Exception Tables
    • -
  • ToDo
    • From isanbard at gmail.com Mon Sep 26 16:10:31 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 26 Sep 2011 21:10:31 -0000 Subject: [llvm-commits] [llvm] r140564 - /llvm/trunk/docs/ExceptionHandling.html Message-ID: <20110926211031.C67492A6C12C@llvm.org> Author: void Date: Mon Sep 26 16:10:31 2011 New Revision: 140564 URL: http://llvm.org/viewvc/llvm-project?rev=140564&view=rev Log: Fix grammar. Modified: llvm/trunk/docs/ExceptionHandling.html Modified: llvm/trunk/docs/ExceptionHandling.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ExceptionHandling.html?rev=140564&r1=140563&r2=140564&view=diff ============================================================================== --- llvm/trunk/docs/ExceptionHandling.html (original) +++ llvm/trunk/docs/ExceptionHandling.html Mon Sep 26 16:10:31 2011 @@ -261,8 +261,8 @@ and filter clauses. The exception is tested against the clauses sequentially from first to last. The selector value is a positive number if the exception matched a type info, a negative number if it matched a filter, - and zero if it matched a cleanup. If nothing is matched, the behavior of the - program is undefined. If a type info matched, + and zero if it matched to a cleanup. If nothing is matched, the behavior of + the program is undefined. If a type info matched, then the selector value is the index of the type info in the exception table, which can be obtained using the llvm.eh.typeid.for intrinsic.

    From James.Molloy at arm.com Mon Sep 26 16:12:16 2011 From: James.Molloy at arm.com (James Molloy) Date: Mon, 26 Sep 2011 22:12:16 +0100 Subject: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll In-Reply-To: <2B1D1D41-40B3-4746-8703-F78823D576D5@apple.com> References: <20110926174042.E57FA2A6C12C@llvm.org> <734A9099-D8A7-48B1-87BE-981B6453DB4D@2pi.dk>, <2B1D1D41-40B3-4746-8703-F78823D576D5@apple.com> Message-ID: Heh, Thanks Eric, as long as I'm not being judged for landing broken commits :) All this might just give me enough clout with management to get myself a nice brutish iMac, excellent! ;) Cheers, James ________________________________________ From: Eric Christopher [echristo at apple.com] Sent: 26 September 2011 21:08 To: Jakob Stoklund Olesen Cc: James Molloy; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r140539 - in /llvm/trunk: include/llvm/Analysis/DebugInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp test/DebugInfo/2011-09-26-GlobalVarContext.ll On Sep 26, 2011, at 1:07 PM, Jakob Stoklund Olesen wrote: > > On Sep 26, 2011, at 1:04 PM, Eric Christopher wrote: > >> >> On Sep 26, 2011, at 12:36 PM, James Molloy wrote: >> >>> Hi Jakob, >>> >>> I thought I needed one, but after discussion with Devang and Eric I was convinced it was fine to remove it! >>> >> >> I saw that too and laughed. Sorry about that. >> >> In general you can make them independent, you may just have to be clever about how you write the matching. > > In fact, no triple and clever matching gives you better test coverage. > > Most people chicken out and add a triple, though. Heh. That was why we were trying to get James not to do so :) -eric -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From eli.friedman at gmail.com Mon Sep 26 16:30:18 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 26 Sep 2011 21:30:18 -0000 Subject: [llvm-commits] [llvm] r140566 - in /llvm/trunk/test/CodeGen: Alpha/mb.ll Alpha/wmb.ll PowerPC/Atomics-32.ll PowerPC/Atomics-64.ll PowerPC/atomic-1.ll PowerPC/atomic-2.ll Message-ID: <20110926213018.584A72A6C12C@llvm.org> Author: efriedma Date: Mon Sep 26 16:30:17 2011 New Revision: 140566 URL: http://llvm.org/viewvc/llvm-project?rev=140566&view=rev Log: Convert more tests over to the new atomic instructions. I did not convert Atomics-32.ll and Atomics-64.ll by hand; the diff is autoupgrade output. The wmb test is gone because there isn't any way to express wmb with the new atomic instructions; if someone really needs a non-asm way to write a wmb on Alpha, a platform-specific intrisic could be added. Removed: llvm/trunk/test/CodeGen/Alpha/wmb.ll Modified: llvm/trunk/test/CodeGen/Alpha/mb.ll llvm/trunk/test/CodeGen/PowerPC/Atomics-32.ll llvm/trunk/test/CodeGen/PowerPC/Atomics-64.ll llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll Modified: llvm/trunk/test/CodeGen/Alpha/mb.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Alpha/mb.ll?rev=140566&r1=140565&r2=140566&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Alpha/mb.ll (original) +++ llvm/trunk/test/CodeGen/Alpha/mb.ll Mon Sep 26 16:30:17 2011 @@ -1,8 +1,6 @@ ; RUN: llc < %s -march=alpha | grep mb -declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1) - define void @test() { - call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true , i1 true) + fence seq_cst ret void } Removed: llvm/trunk/test/CodeGen/Alpha/wmb.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Alpha/wmb.ll?rev=140565&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Alpha/wmb.ll (original) +++ llvm/trunk/test/CodeGen/Alpha/wmb.ll (removed) @@ -1,8 +0,0 @@ -; RUN: llc < %s -march=alpha | grep wmb - -declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1) - -define void @test() { - call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true , i1 true) - ret void -} Modified: llvm/trunk/test/CodeGen/PowerPC/Atomics-32.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/Atomics-32.ll?rev=140566&r1=140565&r2=140566&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/Atomics-32.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/Atomics-32.ll Mon Sep 26 16:30:17 2011 @@ -1,749 +1,699 @@ ; RUN: llc < %s -march=ppc32 -; ModuleID = 'Atomics.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin9" - at sc = common global i8 0 ; [#uses=52] - at uc = common global i8 0 ; [#uses=100] - at ss = common global i16 0 ; [#uses=15] - at us = common global i16 0 ; [#uses=15] - at si = common global i32 0 ; [#uses=15] - at ui = common global i32 0 ; [#uses=23] - at sl = common global i32 0 ; [#uses=15] - at ul = common global i32 0 ; [#uses=15] - at sll = common global i64 0, align 8 ; [#uses=1] - at ull = common global i64 0, align 8 ; [#uses=1] + + at sc = common global i8 0 + at uc = common global i8 0 + at ss = common global i16 0 + at us = common global i16 0 + at si = common global i32 0 + at ui = common global i32 0 + at sl = common global i32 0 + at ul = common global i32 0 + at sll = common global i64 0, align 8 + at ull = common global i64 0, align 8 define void @test_op_ignore() nounwind { entry: - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 1 ) ; :0 [#uses=0] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 1 ) ; :1 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; :3 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; :5 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 1 ) ; :7 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 1 ) ; :9 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :10 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %10, i32 1 ) ; :11 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :12 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %12, i32 1 ) ; :13 [#uses=0] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 1 ) ; :14 [#uses=0] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 1 ) ; :15 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :16 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 1 ) ; :17 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :18 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 1 ) ; :19 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :20 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 1 ) ; :21 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :22 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 1 ) ; :23 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :24 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 1 ) ; :25 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :26 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 1 ) ; :27 [#uses=0] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 1 ) ; :28 [#uses=0] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 1 ) ; :29 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :30 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 1 ) ; :31 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :32 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 1 ) ; :33 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :34 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 1 ) ; :35 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :36 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 1 ) ; :37 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :38 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %38, i32 1 ) ; :39 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :40 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %40, i32 1 ) ; :41 [#uses=0] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 1 ) ; :42 [#uses=0] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 1 ) ; :43 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :44 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 1 ) ; :45 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :46 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 1 ) ; :47 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :48 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 1 ) ; :49 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :50 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 1 ) ; :51 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :52 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %52, i32 1 ) ; :53 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :54 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %54, i32 1 ) ; :55 [#uses=0] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 1 ) ; :56 [#uses=0] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 1 ) ; :57 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :58 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 1 ) ; :59 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :60 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 1 ) ; :61 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :62 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 1 ) ; :63 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :64 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 1 ) ; :65 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :66 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %66, i32 1 ) ; :67 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :68 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %68, i32 1 ) ; :69 [#uses=0] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 1 ) ; :70 [#uses=0] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 1 ) ; :71 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :72 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 1 ) ; :73 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :74 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 1 ) ; :75 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :76 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 1 ) ; :77 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :78 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 1 ) ; :79 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :80 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %80, i32 1 ) ; :81 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :82 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %82, i32 1 ) ; :83 [#uses=0] - br label %return + %0 = atomicrmw add i8* @sc, i8 1 monotonic + %1 = atomicrmw add i8* @uc, i8 1 monotonic + %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %3 = atomicrmw add i16* %2, i16 1 monotonic + %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %5 = atomicrmw add i16* %4, i16 1 monotonic + %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %7 = atomicrmw add i32* %6, i32 1 monotonic + %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %9 = atomicrmw add i32* %8, i32 1 monotonic + %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %11 = atomicrmw add i32* %10, i32 1 monotonic + %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %13 = atomicrmw add i32* %12, i32 1 monotonic + %14 = atomicrmw sub i8* @sc, i8 1 monotonic + %15 = atomicrmw sub i8* @uc, i8 1 monotonic + %16 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %17 = atomicrmw sub i16* %16, i16 1 monotonic + %18 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %19 = atomicrmw sub i16* %18, i16 1 monotonic + %20 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %21 = atomicrmw sub i32* %20, i32 1 monotonic + %22 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %23 = atomicrmw sub i32* %22, i32 1 monotonic + %24 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %25 = atomicrmw sub i32* %24, i32 1 monotonic + %26 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %27 = atomicrmw sub i32* %26, i32 1 monotonic + %28 = atomicrmw or i8* @sc, i8 1 monotonic + %29 = atomicrmw or i8* @uc, i8 1 monotonic + %30 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %31 = atomicrmw or i16* %30, i16 1 monotonic + %32 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %33 = atomicrmw or i16* %32, i16 1 monotonic + %34 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %35 = atomicrmw or i32* %34, i32 1 monotonic + %36 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %37 = atomicrmw or i32* %36, i32 1 monotonic + %38 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %39 = atomicrmw or i32* %38, i32 1 monotonic + %40 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %41 = atomicrmw or i32* %40, i32 1 monotonic + %42 = atomicrmw xor i8* @sc, i8 1 monotonic + %43 = atomicrmw xor i8* @uc, i8 1 monotonic + %44 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %45 = atomicrmw xor i16* %44, i16 1 monotonic + %46 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %47 = atomicrmw xor i16* %46, i16 1 monotonic + %48 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %49 = atomicrmw xor i32* %48, i32 1 monotonic + %50 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %51 = atomicrmw xor i32* %50, i32 1 monotonic + %52 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %53 = atomicrmw xor i32* %52, i32 1 monotonic + %54 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %55 = atomicrmw xor i32* %54, i32 1 monotonic + %56 = atomicrmw and i8* @sc, i8 1 monotonic + %57 = atomicrmw and i8* @uc, i8 1 monotonic + %58 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %59 = atomicrmw and i16* %58, i16 1 monotonic + %60 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %61 = atomicrmw and i16* %60, i16 1 monotonic + %62 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %63 = atomicrmw and i32* %62, i32 1 monotonic + %64 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %65 = atomicrmw and i32* %64, i32 1 monotonic + %66 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %67 = atomicrmw and i32* %66, i32 1 monotonic + %68 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %69 = atomicrmw and i32* %68, i32 1 monotonic + %70 = atomicrmw nand i8* @sc, i8 1 monotonic + %71 = atomicrmw nand i8* @uc, i8 1 monotonic + %72 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %73 = atomicrmw nand i16* %72, i16 1 monotonic + %74 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %75 = atomicrmw nand i16* %74, i16 1 monotonic + %76 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %77 = atomicrmw nand i32* %76, i32 1 monotonic + %78 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %79 = atomicrmw nand i32* %78, i32 1 monotonic + %80 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %81 = atomicrmw nand i32* %80, i32 1 monotonic + %82 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %83 = atomicrmw nand i32* %82, i32 1 monotonic + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } -declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind - -declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind - -declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind - -declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind - -declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind - -declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind - define void @test_fetch_and_op() nounwind { entry: - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 11 ) ; :0 [#uses=1] - store i8 %0, i8* @sc, align 1 - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 11 ) ; :1 [#uses=1] - store i8 %1, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 11 ) ; :3 [#uses=1] - store i16 %3, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 11 ) ; :5 [#uses=1] - store i16 %5, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 11 ) ; :7 [#uses=1] - store i32 %7, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 11 ) ; :9 [#uses=1] - store i32 %9, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :10 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %10, i32 11 ) ; :11 [#uses=1] - store i32 %11, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :12 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %12, i32 11 ) ; :13 [#uses=1] - store i32 %13, i32* @ul, align 4 - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 11 ) ; :14 [#uses=1] - store i8 %14, i8* @sc, align 1 - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 11 ) ; :15 [#uses=1] - store i8 %15, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :16 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 11 ) ; :17 [#uses=1] - store i16 %17, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :18 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 11 ) ; :19 [#uses=1] - store i16 %19, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :20 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 11 ) ; :21 [#uses=1] - store i32 %21, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :22 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 11 ) ; :23 [#uses=1] - store i32 %23, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :24 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 11 ) ; :25 [#uses=1] - store i32 %25, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :26 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 11 ) ; :27 [#uses=1] - store i32 %27, i32* @ul, align 4 - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 11 ) ; :28 [#uses=1] - store i8 %28, i8* @sc, align 1 - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 11 ) ; :29 [#uses=1] - store i8 %29, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :30 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 11 ) ; :31 [#uses=1] - store i16 %31, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :32 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 11 ) ; :33 [#uses=1] - store i16 %33, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :34 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 11 ) ; :35 [#uses=1] - store i32 %35, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :36 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 11 ) ; :37 [#uses=1] - store i32 %37, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :38 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %38, i32 11 ) ; :39 [#uses=1] - store i32 %39, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :40 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %40, i32 11 ) ; :41 [#uses=1] - store i32 %41, i32* @ul, align 4 - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 11 ) ; :42 [#uses=1] - store i8 %42, i8* @sc, align 1 - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 11 ) ; :43 [#uses=1] - store i8 %43, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :44 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 11 ) ; :45 [#uses=1] - store i16 %45, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :46 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 11 ) ; :47 [#uses=1] - store i16 %47, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :48 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 11 ) ; :49 [#uses=1] - store i32 %49, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :50 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 11 ) ; :51 [#uses=1] - store i32 %51, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :52 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %52, i32 11 ) ; :53 [#uses=1] - store i32 %53, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :54 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %54, i32 11 ) ; :55 [#uses=1] - store i32 %55, i32* @ul, align 4 - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 11 ) ; :56 [#uses=1] - store i8 %56, i8* @sc, align 1 - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 11 ) ; :57 [#uses=1] - store i8 %57, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :58 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 11 ) ; :59 [#uses=1] - store i16 %59, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :60 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 11 ) ; :61 [#uses=1] - store i16 %61, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :62 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 11 ) ; :63 [#uses=1] - store i32 %63, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :64 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 11 ) ; :65 [#uses=1] - store i32 %65, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :66 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %66, i32 11 ) ; :67 [#uses=1] - store i32 %67, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :68 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %68, i32 11 ) ; :69 [#uses=1] - store i32 %69, i32* @ul, align 4 - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 11 ) ; :70 [#uses=1] - store i8 %70, i8* @sc, align 1 - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 11 ) ; :71 [#uses=1] - store i8 %71, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :72 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 11 ) ; :73 [#uses=1] - store i16 %73, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :74 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 11 ) ; :75 [#uses=1] - store i16 %75, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :76 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 11 ) ; :77 [#uses=1] - store i32 %77, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :78 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 11 ) ; :79 [#uses=1] - store i32 %79, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :80 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %80, i32 11 ) ; :81 [#uses=1] - store i32 %81, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :82 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %82, i32 11 ) ; :83 [#uses=1] - store i32 %83, i32* @ul, align 4 - br label %return + %0 = atomicrmw add i8* @sc, i8 11 monotonic + store i8 %0, i8* @sc, align 1 + %1 = atomicrmw add i8* @uc, i8 11 monotonic + store i8 %1, i8* @uc, align 1 + %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %3 = atomicrmw add i16* %2, i16 11 monotonic + store i16 %3, i16* @ss, align 2 + %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %5 = atomicrmw add i16* %4, i16 11 monotonic + store i16 %5, i16* @us, align 2 + %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %7 = atomicrmw add i32* %6, i32 11 monotonic + store i32 %7, i32* @si, align 4 + %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %9 = atomicrmw add i32* %8, i32 11 monotonic + store i32 %9, i32* @ui, align 4 + %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %11 = atomicrmw add i32* %10, i32 11 monotonic + store i32 %11, i32* @sl, align 4 + %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %13 = atomicrmw add i32* %12, i32 11 monotonic + store i32 %13, i32* @ul, align 4 + %14 = atomicrmw sub i8* @sc, i8 11 monotonic + store i8 %14, i8* @sc, align 1 + %15 = atomicrmw sub i8* @uc, i8 11 monotonic + store i8 %15, i8* @uc, align 1 + %16 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %17 = atomicrmw sub i16* %16, i16 11 monotonic + store i16 %17, i16* @ss, align 2 + %18 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %19 = atomicrmw sub i16* %18, i16 11 monotonic + store i16 %19, i16* @us, align 2 + %20 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %21 = atomicrmw sub i32* %20, i32 11 monotonic + store i32 %21, i32* @si, align 4 + %22 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %23 = atomicrmw sub i32* %22, i32 11 monotonic + store i32 %23, i32* @ui, align 4 + %24 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %25 = atomicrmw sub i32* %24, i32 11 monotonic + store i32 %25, i32* @sl, align 4 + %26 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %27 = atomicrmw sub i32* %26, i32 11 monotonic + store i32 %27, i32* @ul, align 4 + %28 = atomicrmw or i8* @sc, i8 11 monotonic + store i8 %28, i8* @sc, align 1 + %29 = atomicrmw or i8* @uc, i8 11 monotonic + store i8 %29, i8* @uc, align 1 + %30 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %31 = atomicrmw or i16* %30, i16 11 monotonic + store i16 %31, i16* @ss, align 2 + %32 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %33 = atomicrmw or i16* %32, i16 11 monotonic + store i16 %33, i16* @us, align 2 + %34 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %35 = atomicrmw or i32* %34, i32 11 monotonic + store i32 %35, i32* @si, align 4 + %36 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %37 = atomicrmw or i32* %36, i32 11 monotonic + store i32 %37, i32* @ui, align 4 + %38 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %39 = atomicrmw or i32* %38, i32 11 monotonic + store i32 %39, i32* @sl, align 4 + %40 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %41 = atomicrmw or i32* %40, i32 11 monotonic + store i32 %41, i32* @ul, align 4 + %42 = atomicrmw xor i8* @sc, i8 11 monotonic + store i8 %42, i8* @sc, align 1 + %43 = atomicrmw xor i8* @uc, i8 11 monotonic + store i8 %43, i8* @uc, align 1 + %44 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %45 = atomicrmw xor i16* %44, i16 11 monotonic + store i16 %45, i16* @ss, align 2 + %46 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %47 = atomicrmw xor i16* %46, i16 11 monotonic + store i16 %47, i16* @us, align 2 + %48 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %49 = atomicrmw xor i32* %48, i32 11 monotonic + store i32 %49, i32* @si, align 4 + %50 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %51 = atomicrmw xor i32* %50, i32 11 monotonic + store i32 %51, i32* @ui, align 4 + %52 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %53 = atomicrmw xor i32* %52, i32 11 monotonic + store i32 %53, i32* @sl, align 4 + %54 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %55 = atomicrmw xor i32* %54, i32 11 monotonic + store i32 %55, i32* @ul, align 4 + %56 = atomicrmw and i8* @sc, i8 11 monotonic + store i8 %56, i8* @sc, align 1 + %57 = atomicrmw and i8* @uc, i8 11 monotonic + store i8 %57, i8* @uc, align 1 + %58 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %59 = atomicrmw and i16* %58, i16 11 monotonic + store i16 %59, i16* @ss, align 2 + %60 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %61 = atomicrmw and i16* %60, i16 11 monotonic + store i16 %61, i16* @us, align 2 + %62 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %63 = atomicrmw and i32* %62, i32 11 monotonic + store i32 %63, i32* @si, align 4 + %64 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %65 = atomicrmw and i32* %64, i32 11 monotonic + store i32 %65, i32* @ui, align 4 + %66 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %67 = atomicrmw and i32* %66, i32 11 monotonic + store i32 %67, i32* @sl, align 4 + %68 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %69 = atomicrmw and i32* %68, i32 11 monotonic + store i32 %69, i32* @ul, align 4 + %70 = atomicrmw nand i8* @sc, i8 11 monotonic + store i8 %70, i8* @sc, align 1 + %71 = atomicrmw nand i8* @uc, i8 11 monotonic + store i8 %71, i8* @uc, align 1 + %72 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %73 = atomicrmw nand i16* %72, i16 11 monotonic + store i16 %73, i16* @ss, align 2 + %74 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %75 = atomicrmw nand i16* %74, i16 11 monotonic + store i16 %75, i16* @us, align 2 + %76 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %77 = atomicrmw nand i32* %76, i32 11 monotonic + store i32 %77, i32* @si, align 4 + %78 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %79 = atomicrmw nand i32* %78, i32 11 monotonic + store i32 %79, i32* @ui, align 4 + %80 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %81 = atomicrmw nand i32* %80, i32 11 monotonic + store i32 %81, i32* @sl, align 4 + %82 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %83 = atomicrmw nand i32* %82, i32 11 monotonic + store i32 %83, i32* @ul, align 4 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } define void @test_op_and_fetch() nounwind { entry: - load i8* @uc, align 1 ; :0 [#uses=2] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 %0 ) ; :1 [#uses=1] - add i8 %1, %0 ; :2 [#uses=1] - store i8 %2, i8* @sc, align 1 - load i8* @uc, align 1 ; :3 [#uses=2] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 %3 ) ; :4 [#uses=1] - add i8 %4, %3 ; :5 [#uses=1] - store i8 %5, i8* @uc, align 1 - load i8* @uc, align 1 ; :6 [#uses=1] - zext i8 %6 to i16 ; :7 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :8 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %8, i16 %7 ) ; :9 [#uses=1] - add i16 %9, %7 ; :10 [#uses=1] - store i16 %10, i16* @ss, align 2 - load i8* @uc, align 1 ; :11 [#uses=1] - zext i8 %11 to i16 ; :12 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :13 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %13, i16 %12 ) ; :14 [#uses=1] - add i16 %14, %12 ; :15 [#uses=1] - store i16 %15, i16* @us, align 2 - load i8* @uc, align 1 ; :16 [#uses=1] - zext i8 %16 to i32 ; :17 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :18 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %18, i32 %17 ) ; :19 [#uses=1] - add i32 %19, %17 ; :20 [#uses=1] - store i32 %20, i32* @si, align 4 - load i8* @uc, align 1 ; :21 [#uses=1] - zext i8 %21 to i32 ; :22 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :23 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %23, i32 %22 ) ; :24 [#uses=1] - add i32 %24, %22 ; :25 [#uses=1] - store i32 %25, i32* @ui, align 4 - load i8* @uc, align 1 ; :26 [#uses=1] - zext i8 %26 to i32 ; :27 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :28 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %28, i32 %27 ) ; :29 [#uses=1] - add i32 %29, %27 ; :30 [#uses=1] - store i32 %30, i32* @sl, align 4 - load i8* @uc, align 1 ; :31 [#uses=1] - zext i8 %31 to i32 ; :32 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :33 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %33, i32 %32 ) ; :34 [#uses=1] - add i32 %34, %32 ; :35 [#uses=1] - store i32 %35, i32* @ul, align 4 - load i8* @uc, align 1 ; :36 [#uses=2] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 %36 ) ; :37 [#uses=1] - sub i8 %37, %36 ; :38 [#uses=1] - store i8 %38, i8* @sc, align 1 - load i8* @uc, align 1 ; :39 [#uses=2] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 %39 ) ; :40 [#uses=1] - sub i8 %40, %39 ; :41 [#uses=1] - store i8 %41, i8* @uc, align 1 - load i8* @uc, align 1 ; :42 [#uses=1] - zext i8 %42 to i16 ; :43 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :44 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %44, i16 %43 ) ; :45 [#uses=1] - sub i16 %45, %43 ; :46 [#uses=1] - store i16 %46, i16* @ss, align 2 - load i8* @uc, align 1 ; :47 [#uses=1] - zext i8 %47 to i16 ; :48 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :49 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %49, i16 %48 ) ; :50 [#uses=1] - sub i16 %50, %48 ; :51 [#uses=1] - store i16 %51, i16* @us, align 2 - load i8* @uc, align 1 ; :52 [#uses=1] - zext i8 %52 to i32 ; :53 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :54 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %54, i32 %53 ) ; :55 [#uses=1] - sub i32 %55, %53 ; :56 [#uses=1] - store i32 %56, i32* @si, align 4 - load i8* @uc, align 1 ; :57 [#uses=1] - zext i8 %57 to i32 ; :58 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :59 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %59, i32 %58 ) ; :60 [#uses=1] - sub i32 %60, %58 ; :61 [#uses=1] - store i32 %61, i32* @ui, align 4 - load i8* @uc, align 1 ; :62 [#uses=1] - zext i8 %62 to i32 ; :63 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :64 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %64, i32 %63 ) ; :65 [#uses=1] - sub i32 %65, %63 ; :66 [#uses=1] - store i32 %66, i32* @sl, align 4 - load i8* @uc, align 1 ; :67 [#uses=1] - zext i8 %67 to i32 ; :68 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :69 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %69, i32 %68 ) ; :70 [#uses=1] - sub i32 %70, %68 ; :71 [#uses=1] - store i32 %71, i32* @ul, align 4 - load i8* @uc, align 1 ; :72 [#uses=2] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 %72 ) ; :73 [#uses=1] - or i8 %73, %72 ; :74 [#uses=1] - store i8 %74, i8* @sc, align 1 - load i8* @uc, align 1 ; :75 [#uses=2] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 %75 ) ; :76 [#uses=1] - or i8 %76, %75 ; :77 [#uses=1] - store i8 %77, i8* @uc, align 1 - load i8* @uc, align 1 ; :78 [#uses=1] - zext i8 %78 to i16 ; :79 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :80 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %80, i16 %79 ) ; :81 [#uses=1] - or i16 %81, %79 ; :82 [#uses=1] - store i16 %82, i16* @ss, align 2 - load i8* @uc, align 1 ; :83 [#uses=1] - zext i8 %83 to i16 ; :84 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :85 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %85, i16 %84 ) ; :86 [#uses=1] - or i16 %86, %84 ; :87 [#uses=1] - store i16 %87, i16* @us, align 2 - load i8* @uc, align 1 ; :88 [#uses=1] - zext i8 %88 to i32 ; :89 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :90 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %90, i32 %89 ) ; :91 [#uses=1] - or i32 %91, %89 ; :92 [#uses=1] - store i32 %92, i32* @si, align 4 - load i8* @uc, align 1 ; :93 [#uses=1] - zext i8 %93 to i32 ; :94 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :95 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %95, i32 %94 ) ; :96 [#uses=1] - or i32 %96, %94 ; :97 [#uses=1] - store i32 %97, i32* @ui, align 4 - load i8* @uc, align 1 ; :98 [#uses=1] - zext i8 %98 to i32 ; :99 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :100 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %100, i32 %99 ) ; :101 [#uses=1] - or i32 %101, %99 ; :102 [#uses=1] - store i32 %102, i32* @sl, align 4 - load i8* @uc, align 1 ; :103 [#uses=1] - zext i8 %103 to i32 ; :104 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :105 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %105, i32 %104 ) ; :106 [#uses=1] - or i32 %106, %104 ; :107 [#uses=1] - store i32 %107, i32* @ul, align 4 - load i8* @uc, align 1 ; :108 [#uses=2] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 %108 ) ; :109 [#uses=1] - xor i8 %109, %108 ; :110 [#uses=1] - store i8 %110, i8* @sc, align 1 - load i8* @uc, align 1 ; :111 [#uses=2] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 %111 ) ; :112 [#uses=1] - xor i8 %112, %111 ; :113 [#uses=1] - store i8 %113, i8* @uc, align 1 - load i8* @uc, align 1 ; :114 [#uses=1] - zext i8 %114 to i16 ; :115 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :116 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %116, i16 %115 ) ; :117 [#uses=1] - xor i16 %117, %115 ; :118 [#uses=1] - store i16 %118, i16* @ss, align 2 - load i8* @uc, align 1 ; :119 [#uses=1] - zext i8 %119 to i16 ; :120 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :121 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %121, i16 %120 ) ; :122 [#uses=1] - xor i16 %122, %120 ; :123 [#uses=1] - store i16 %123, i16* @us, align 2 - load i8* @uc, align 1 ; :124 [#uses=1] - zext i8 %124 to i32 ; :125 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :126 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %126, i32 %125 ) ; :127 [#uses=1] - xor i32 %127, %125 ; :128 [#uses=1] - store i32 %128, i32* @si, align 4 - load i8* @uc, align 1 ; :129 [#uses=1] - zext i8 %129 to i32 ; :130 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :131 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %131, i32 %130 ) ; :132 [#uses=1] - xor i32 %132, %130 ; :133 [#uses=1] - store i32 %133, i32* @ui, align 4 - load i8* @uc, align 1 ; :134 [#uses=1] - zext i8 %134 to i32 ; :135 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :136 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %136, i32 %135 ) ; :137 [#uses=1] - xor i32 %137, %135 ; :138 [#uses=1] - store i32 %138, i32* @sl, align 4 - load i8* @uc, align 1 ; :139 [#uses=1] - zext i8 %139 to i32 ; :140 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :141 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %141, i32 %140 ) ; :142 [#uses=1] - xor i32 %142, %140 ; :143 [#uses=1] - store i32 %143, i32* @ul, align 4 - load i8* @uc, align 1 ; :144 [#uses=2] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 %144 ) ; :145 [#uses=1] - and i8 %145, %144 ; :146 [#uses=1] - store i8 %146, i8* @sc, align 1 - load i8* @uc, align 1 ; :147 [#uses=2] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 %147 ) ; :148 [#uses=1] - and i8 %148, %147 ; :149 [#uses=1] - store i8 %149, i8* @uc, align 1 - load i8* @uc, align 1 ; :150 [#uses=1] - zext i8 %150 to i16 ; :151 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :152 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %152, i16 %151 ) ; :153 [#uses=1] - and i16 %153, %151 ; :154 [#uses=1] - store i16 %154, i16* @ss, align 2 - load i8* @uc, align 1 ; :155 [#uses=1] - zext i8 %155 to i16 ; :156 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :157 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %157, i16 %156 ) ; :158 [#uses=1] - and i16 %158, %156 ; :159 [#uses=1] - store i16 %159, i16* @us, align 2 - load i8* @uc, align 1 ; :160 [#uses=1] - zext i8 %160 to i32 ; :161 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :162 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %162, i32 %161 ) ; :163 [#uses=1] - and i32 %163, %161 ; :164 [#uses=1] - store i32 %164, i32* @si, align 4 - load i8* @uc, align 1 ; :165 [#uses=1] - zext i8 %165 to i32 ; :166 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :167 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %167, i32 %166 ) ; :168 [#uses=1] - and i32 %168, %166 ; :169 [#uses=1] - store i32 %169, i32* @ui, align 4 - load i8* @uc, align 1 ; :170 [#uses=1] - zext i8 %170 to i32 ; :171 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :172 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %172, i32 %171 ) ; :173 [#uses=1] - and i32 %173, %171 ; :174 [#uses=1] - store i32 %174, i32* @sl, align 4 - load i8* @uc, align 1 ; :175 [#uses=1] - zext i8 %175 to i32 ; :176 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :177 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %177, i32 %176 ) ; :178 [#uses=1] - and i32 %178, %176 ; :179 [#uses=1] - store i32 %179, i32* @ul, align 4 - load i8* @uc, align 1 ; :180 [#uses=2] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 %180 ) ; :181 [#uses=1] - xor i8 %181, -1 ; :182 [#uses=1] - and i8 %182, %180 ; :183 [#uses=1] - store i8 %183, i8* @sc, align 1 - load i8* @uc, align 1 ; :184 [#uses=2] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 %184 ) ; :185 [#uses=1] - xor i8 %185, -1 ; :186 [#uses=1] - and i8 %186, %184 ; :187 [#uses=1] - store i8 %187, i8* @uc, align 1 - load i8* @uc, align 1 ; :188 [#uses=1] - zext i8 %188 to i16 ; :189 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :190 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %190, i16 %189 ) ; :191 [#uses=1] - xor i16 %191, -1 ; :192 [#uses=1] - and i16 %192, %189 ; :193 [#uses=1] - store i16 %193, i16* @ss, align 2 - load i8* @uc, align 1 ; :194 [#uses=1] - zext i8 %194 to i16 ; :195 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :196 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %196, i16 %195 ) ; :197 [#uses=1] - xor i16 %197, -1 ; :198 [#uses=1] - and i16 %198, %195 ; :199 [#uses=1] - store i16 %199, i16* @us, align 2 - load i8* @uc, align 1 ; :200 [#uses=1] - zext i8 %200 to i32 ; :201 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :202 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %202, i32 %201 ) ; :203 [#uses=1] - xor i32 %203, -1 ; :204 [#uses=1] - and i32 %204, %201 ; :205 [#uses=1] - store i32 %205, i32* @si, align 4 - load i8* @uc, align 1 ; :206 [#uses=1] - zext i8 %206 to i32 ; :207 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :208 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %208, i32 %207 ) ; :209 [#uses=1] - xor i32 %209, -1 ; :210 [#uses=1] - and i32 %210, %207 ; :211 [#uses=1] - store i32 %211, i32* @ui, align 4 - load i8* @uc, align 1 ; :212 [#uses=1] - zext i8 %212 to i32 ; :213 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :214 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %214, i32 %213 ) ; :215 [#uses=1] - xor i32 %215, -1 ; :216 [#uses=1] - and i32 %216, %213 ; :217 [#uses=1] - store i32 %217, i32* @sl, align 4 - load i8* @uc, align 1 ; :218 [#uses=1] - zext i8 %218 to i32 ; :219 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :220 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %220, i32 %219 ) ; :221 [#uses=1] - xor i32 %221, -1 ; :222 [#uses=1] - and i32 %222, %219 ; :223 [#uses=1] - store i32 %223, i32* @ul, align 4 - br label %return + %0 = load i8* @uc, align 1 + %1 = atomicrmw add i8* @sc, i8 %0 monotonic + %2 = add i8 %1, %0 + store i8 %2, i8* @sc, align 1 + %3 = load i8* @uc, align 1 + %4 = atomicrmw add i8* @uc, i8 %3 monotonic + %5 = add i8 %4, %3 + store i8 %5, i8* @uc, align 1 + %6 = load i8* @uc, align 1 + %7 = zext i8 %6 to i16 + %8 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %9 = atomicrmw add i16* %8, i16 %7 monotonic + %10 = add i16 %9, %7 + store i16 %10, i16* @ss, align 2 + %11 = load i8* @uc, align 1 + %12 = zext i8 %11 to i16 + %13 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %14 = atomicrmw add i16* %13, i16 %12 monotonic + %15 = add i16 %14, %12 + store i16 %15, i16* @us, align 2 + %16 = load i8* @uc, align 1 + %17 = zext i8 %16 to i32 + %18 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %19 = atomicrmw add i32* %18, i32 %17 monotonic + %20 = add i32 %19, %17 + store i32 %20, i32* @si, align 4 + %21 = load i8* @uc, align 1 + %22 = zext i8 %21 to i32 + %23 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %24 = atomicrmw add i32* %23, i32 %22 monotonic + %25 = add i32 %24, %22 + store i32 %25, i32* @ui, align 4 + %26 = load i8* @uc, align 1 + %27 = zext i8 %26 to i32 + %28 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %29 = atomicrmw add i32* %28, i32 %27 monotonic + %30 = add i32 %29, %27 + store i32 %30, i32* @sl, align 4 + %31 = load i8* @uc, align 1 + %32 = zext i8 %31 to i32 + %33 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %34 = atomicrmw add i32* %33, i32 %32 monotonic + %35 = add i32 %34, %32 + store i32 %35, i32* @ul, align 4 + %36 = load i8* @uc, align 1 + %37 = atomicrmw sub i8* @sc, i8 %36 monotonic + %38 = sub i8 %37, %36 + store i8 %38, i8* @sc, align 1 + %39 = load i8* @uc, align 1 + %40 = atomicrmw sub i8* @uc, i8 %39 monotonic + %41 = sub i8 %40, %39 + store i8 %41, i8* @uc, align 1 + %42 = load i8* @uc, align 1 + %43 = zext i8 %42 to i16 + %44 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %45 = atomicrmw sub i16* %44, i16 %43 monotonic + %46 = sub i16 %45, %43 + store i16 %46, i16* @ss, align 2 + %47 = load i8* @uc, align 1 + %48 = zext i8 %47 to i16 + %49 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %50 = atomicrmw sub i16* %49, i16 %48 monotonic + %51 = sub i16 %50, %48 + store i16 %51, i16* @us, align 2 + %52 = load i8* @uc, align 1 + %53 = zext i8 %52 to i32 + %54 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %55 = atomicrmw sub i32* %54, i32 %53 monotonic + %56 = sub i32 %55, %53 + store i32 %56, i32* @si, align 4 + %57 = load i8* @uc, align 1 + %58 = zext i8 %57 to i32 + %59 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %60 = atomicrmw sub i32* %59, i32 %58 monotonic + %61 = sub i32 %60, %58 + store i32 %61, i32* @ui, align 4 + %62 = load i8* @uc, align 1 + %63 = zext i8 %62 to i32 + %64 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %65 = atomicrmw sub i32* %64, i32 %63 monotonic + %66 = sub i32 %65, %63 + store i32 %66, i32* @sl, align 4 + %67 = load i8* @uc, align 1 + %68 = zext i8 %67 to i32 + %69 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %70 = atomicrmw sub i32* %69, i32 %68 monotonic + %71 = sub i32 %70, %68 + store i32 %71, i32* @ul, align 4 + %72 = load i8* @uc, align 1 + %73 = atomicrmw or i8* @sc, i8 %72 monotonic + %74 = or i8 %73, %72 + store i8 %74, i8* @sc, align 1 + %75 = load i8* @uc, align 1 + %76 = atomicrmw or i8* @uc, i8 %75 monotonic + %77 = or i8 %76, %75 + store i8 %77, i8* @uc, align 1 + %78 = load i8* @uc, align 1 + %79 = zext i8 %78 to i16 + %80 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %81 = atomicrmw or i16* %80, i16 %79 monotonic + %82 = or i16 %81, %79 + store i16 %82, i16* @ss, align 2 + %83 = load i8* @uc, align 1 + %84 = zext i8 %83 to i16 + %85 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %86 = atomicrmw or i16* %85, i16 %84 monotonic + %87 = or i16 %86, %84 + store i16 %87, i16* @us, align 2 + %88 = load i8* @uc, align 1 + %89 = zext i8 %88 to i32 + %90 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %91 = atomicrmw or i32* %90, i32 %89 monotonic + %92 = or i32 %91, %89 + store i32 %92, i32* @si, align 4 + %93 = load i8* @uc, align 1 + %94 = zext i8 %93 to i32 + %95 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %96 = atomicrmw or i32* %95, i32 %94 monotonic + %97 = or i32 %96, %94 + store i32 %97, i32* @ui, align 4 + %98 = load i8* @uc, align 1 + %99 = zext i8 %98 to i32 + %100 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %101 = atomicrmw or i32* %100, i32 %99 monotonic + %102 = or i32 %101, %99 + store i32 %102, i32* @sl, align 4 + %103 = load i8* @uc, align 1 + %104 = zext i8 %103 to i32 + %105 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %106 = atomicrmw or i32* %105, i32 %104 monotonic + %107 = or i32 %106, %104 + store i32 %107, i32* @ul, align 4 + %108 = load i8* @uc, align 1 + %109 = atomicrmw xor i8* @sc, i8 %108 monotonic + %110 = xor i8 %109, %108 + store i8 %110, i8* @sc, align 1 + %111 = load i8* @uc, align 1 + %112 = atomicrmw xor i8* @uc, i8 %111 monotonic + %113 = xor i8 %112, %111 + store i8 %113, i8* @uc, align 1 + %114 = load i8* @uc, align 1 + %115 = zext i8 %114 to i16 + %116 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %117 = atomicrmw xor i16* %116, i16 %115 monotonic + %118 = xor i16 %117, %115 + store i16 %118, i16* @ss, align 2 + %119 = load i8* @uc, align 1 + %120 = zext i8 %119 to i16 + %121 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %122 = atomicrmw xor i16* %121, i16 %120 monotonic + %123 = xor i16 %122, %120 + store i16 %123, i16* @us, align 2 + %124 = load i8* @uc, align 1 + %125 = zext i8 %124 to i32 + %126 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %127 = atomicrmw xor i32* %126, i32 %125 monotonic + %128 = xor i32 %127, %125 + store i32 %128, i32* @si, align 4 + %129 = load i8* @uc, align 1 + %130 = zext i8 %129 to i32 + %131 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %132 = atomicrmw xor i32* %131, i32 %130 monotonic + %133 = xor i32 %132, %130 + store i32 %133, i32* @ui, align 4 + %134 = load i8* @uc, align 1 + %135 = zext i8 %134 to i32 + %136 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %137 = atomicrmw xor i32* %136, i32 %135 monotonic + %138 = xor i32 %137, %135 + store i32 %138, i32* @sl, align 4 + %139 = load i8* @uc, align 1 + %140 = zext i8 %139 to i32 + %141 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %142 = atomicrmw xor i32* %141, i32 %140 monotonic + %143 = xor i32 %142, %140 + store i32 %143, i32* @ul, align 4 + %144 = load i8* @uc, align 1 + %145 = atomicrmw and i8* @sc, i8 %144 monotonic + %146 = and i8 %145, %144 + store i8 %146, i8* @sc, align 1 + %147 = load i8* @uc, align 1 + %148 = atomicrmw and i8* @uc, i8 %147 monotonic + %149 = and i8 %148, %147 + store i8 %149, i8* @uc, align 1 + %150 = load i8* @uc, align 1 + %151 = zext i8 %150 to i16 + %152 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %153 = atomicrmw and i16* %152, i16 %151 monotonic + %154 = and i16 %153, %151 + store i16 %154, i16* @ss, align 2 + %155 = load i8* @uc, align 1 + %156 = zext i8 %155 to i16 + %157 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %158 = atomicrmw and i16* %157, i16 %156 monotonic + %159 = and i16 %158, %156 + store i16 %159, i16* @us, align 2 + %160 = load i8* @uc, align 1 + %161 = zext i8 %160 to i32 + %162 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %163 = atomicrmw and i32* %162, i32 %161 monotonic + %164 = and i32 %163, %161 + store i32 %164, i32* @si, align 4 + %165 = load i8* @uc, align 1 + %166 = zext i8 %165 to i32 + %167 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %168 = atomicrmw and i32* %167, i32 %166 monotonic + %169 = and i32 %168, %166 + store i32 %169, i32* @ui, align 4 + %170 = load i8* @uc, align 1 + %171 = zext i8 %170 to i32 + %172 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %173 = atomicrmw and i32* %172, i32 %171 monotonic + %174 = and i32 %173, %171 + store i32 %174, i32* @sl, align 4 + %175 = load i8* @uc, align 1 + %176 = zext i8 %175 to i32 + %177 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %178 = atomicrmw and i32* %177, i32 %176 monotonic + %179 = and i32 %178, %176 + store i32 %179, i32* @ul, align 4 + %180 = load i8* @uc, align 1 + %181 = atomicrmw nand i8* @sc, i8 %180 monotonic + %182 = xor i8 %181, -1 + %183 = and i8 %182, %180 + store i8 %183, i8* @sc, align 1 + %184 = load i8* @uc, align 1 + %185 = atomicrmw nand i8* @uc, i8 %184 monotonic + %186 = xor i8 %185, -1 + %187 = and i8 %186, %184 + store i8 %187, i8* @uc, align 1 + %188 = load i8* @uc, align 1 + %189 = zext i8 %188 to i16 + %190 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %191 = atomicrmw nand i16* %190, i16 %189 monotonic + %192 = xor i16 %191, -1 + %193 = and i16 %192, %189 + store i16 %193, i16* @ss, align 2 + %194 = load i8* @uc, align 1 + %195 = zext i8 %194 to i16 + %196 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %197 = atomicrmw nand i16* %196, i16 %195 monotonic + %198 = xor i16 %197, -1 + %199 = and i16 %198, %195 + store i16 %199, i16* @us, align 2 + %200 = load i8* @uc, align 1 + %201 = zext i8 %200 to i32 + %202 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %203 = atomicrmw nand i32* %202, i32 %201 monotonic + %204 = xor i32 %203, -1 + %205 = and i32 %204, %201 + store i32 %205, i32* @si, align 4 + %206 = load i8* @uc, align 1 + %207 = zext i8 %206 to i32 + %208 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %209 = atomicrmw nand i32* %208, i32 %207 monotonic + %210 = xor i32 %209, -1 + %211 = and i32 %210, %207 + store i32 %211, i32* @ui, align 4 + %212 = load i8* @uc, align 1 + %213 = zext i8 %212 to i32 + %214 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %215 = atomicrmw nand i32* %214, i32 %213 monotonic + %216 = xor i32 %215, -1 + %217 = and i32 %216, %213 + store i32 %217, i32* @sl, align 4 + %218 = load i8* @uc, align 1 + %219 = zext i8 %218 to i32 + %220 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %221 = atomicrmw nand i32* %220, i32 %219 monotonic + %222 = xor i32 %221, -1 + %223 = and i32 %222, %219 + store i32 %223, i32* @ul, align 4 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } define void @test_compare_and_swap() nounwind { entry: - load i8* @uc, align 1 ; :0 [#uses=1] - load i8* @sc, align 1 ; :1 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %0, i8 %1 ) ; :2 [#uses=1] - store i8 %2, i8* @sc, align 1 - load i8* @uc, align 1 ; :3 [#uses=1] - load i8* @sc, align 1 ; :4 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %3, i8 %4 ) ; :5 [#uses=1] - store i8 %5, i8* @uc, align 1 - load i8* @uc, align 1 ; :6 [#uses=1] - zext i8 %6 to i16 ; :7 [#uses=1] - load i8* @sc, align 1 ; :8 [#uses=1] - sext i8 %8 to i16 ; :9 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :10 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %10, i16 %7, i16 %9 ) ; :11 [#uses=1] - store i16 %11, i16* @ss, align 2 - load i8* @uc, align 1 ; :12 [#uses=1] - zext i8 %12 to i16 ; :13 [#uses=1] - load i8* @sc, align 1 ; :14 [#uses=1] - sext i8 %14 to i16 ; :15 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :16 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %16, i16 %13, i16 %15 ) ; :17 [#uses=1] - store i16 %17, i16* @us, align 2 - load i8* @uc, align 1 ; :18 [#uses=1] - zext i8 %18 to i32 ; :19 [#uses=1] - load i8* @sc, align 1 ; :20 [#uses=1] - sext i8 %20 to i32 ; :21 [#uses=1] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :22 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %22, i32 %19, i32 %21 ) ; :23 [#uses=1] - store i32 %23, i32* @si, align 4 - load i8* @uc, align 1 ; :24 [#uses=1] - zext i8 %24 to i32 ; :25 [#uses=1] - load i8* @sc, align 1 ; :26 [#uses=1] - sext i8 %26 to i32 ; :27 [#uses=1] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :28 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %28, i32 %25, i32 %27 ) ; :29 [#uses=1] - store i32 %29, i32* @ui, align 4 - load i8* @uc, align 1 ; :30 [#uses=1] - zext i8 %30 to i32 ; :31 [#uses=1] - load i8* @sc, align 1 ; :32 [#uses=1] - sext i8 %32 to i32 ; :33 [#uses=1] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :34 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %34, i32 %31, i32 %33 ) ; :35 [#uses=1] - store i32 %35, i32* @sl, align 4 - load i8* @uc, align 1 ; :36 [#uses=1] - zext i8 %36 to i32 ; :37 [#uses=1] - load i8* @sc, align 1 ; :38 [#uses=1] - sext i8 %38 to i32 ; :39 [#uses=1] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :40 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %40, i32 %37, i32 %39 ) ; :41 [#uses=1] - store i32 %41, i32* @ul, align 4 - load i8* @uc, align 1 ; :42 [#uses=2] - load i8* @sc, align 1 ; :43 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %42, i8 %43 ) ; :44 [#uses=1] - icmp eq i8 %44, %42 ; :45 [#uses=1] - zext i1 %45 to i32 ; :46 [#uses=1] - store i32 %46, i32* @ui, align 4 - load i8* @uc, align 1 ; :47 [#uses=2] - load i8* @sc, align 1 ; :48 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %47, i8 %48 ) ; :49 [#uses=1] - icmp eq i8 %49, %47 ; :50 [#uses=1] - zext i1 %50 to i32 ; :51 [#uses=1] - store i32 %51, i32* @ui, align 4 - load i8* @uc, align 1 ; :52 [#uses=1] - zext i8 %52 to i16 ; :53 [#uses=2] - load i8* @sc, align 1 ; :54 [#uses=1] - sext i8 %54 to i16 ; :55 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :56 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %56, i16 %53, i16 %55 ) ; :57 [#uses=1] - icmp eq i16 %57, %53 ; :58 [#uses=1] - zext i1 %58 to i32 ; :59 [#uses=1] - store i32 %59, i32* @ui, align 4 - load i8* @uc, align 1 ; :60 [#uses=1] - zext i8 %60 to i16 ; :61 [#uses=2] - load i8* @sc, align 1 ; :62 [#uses=1] - sext i8 %62 to i16 ; :63 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :64 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %64, i16 %61, i16 %63 ) ; :65 [#uses=1] - icmp eq i16 %65, %61 ; :66 [#uses=1] - zext i1 %66 to i32 ; :67 [#uses=1] - store i32 %67, i32* @ui, align 4 - load i8* @uc, align 1 ; :68 [#uses=1] - zext i8 %68 to i32 ; :69 [#uses=2] - load i8* @sc, align 1 ; :70 [#uses=1] - sext i8 %70 to i32 ; :71 [#uses=1] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :72 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %72, i32 %69, i32 %71 ) ; :73 [#uses=1] - icmp eq i32 %73, %69 ; :74 [#uses=1] - zext i1 %74 to i32 ; :75 [#uses=1] - store i32 %75, i32* @ui, align 4 - load i8* @uc, align 1 ; :76 [#uses=1] - zext i8 %76 to i32 ; :77 [#uses=2] - load i8* @sc, align 1 ; :78 [#uses=1] - sext i8 %78 to i32 ; :79 [#uses=1] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :80 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %80, i32 %77, i32 %79 ) ; :81 [#uses=1] - icmp eq i32 %81, %77 ; :82 [#uses=1] - zext i1 %82 to i32 ; :83 [#uses=1] - store i32 %83, i32* @ui, align 4 - load i8* @uc, align 1 ; :84 [#uses=1] - zext i8 %84 to i32 ; :85 [#uses=2] - load i8* @sc, align 1 ; :86 [#uses=1] - sext i8 %86 to i32 ; :87 [#uses=1] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :88 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %88, i32 %85, i32 %87 ) ; :89 [#uses=1] - icmp eq i32 %89, %85 ; :90 [#uses=1] - zext i1 %90 to i32 ; :91 [#uses=1] - store i32 %91, i32* @ui, align 4 - load i8* @uc, align 1 ; :92 [#uses=1] - zext i8 %92 to i32 ; :93 [#uses=2] - load i8* @sc, align 1 ; :94 [#uses=1] - sext i8 %94 to i32 ; :95 [#uses=1] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :96 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %96, i32 %93, i32 %95 ) ; :97 [#uses=1] - icmp eq i32 %97, %93 ; :98 [#uses=1] - zext i1 %98 to i32 ; :99 [#uses=1] - store i32 %99, i32* @ui, align 4 - br label %return + %0 = load i8* @uc, align 1 + %1 = load i8* @sc, align 1 + %2 = cmpxchg i8* @sc, i8 %0, i8 %1 monotonic + store i8 %2, i8* @sc, align 1 + %3 = load i8* @uc, align 1 + %4 = load i8* @sc, align 1 + %5 = cmpxchg i8* @uc, i8 %3, i8 %4 monotonic + store i8 %5, i8* @uc, align 1 + %6 = load i8* @uc, align 1 + %7 = zext i8 %6 to i16 + %8 = load i8* @sc, align 1 + %9 = sext i8 %8 to i16 + %10 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %11 = cmpxchg i16* %10, i16 %7, i16 %9 monotonic + store i16 %11, i16* @ss, align 2 + %12 = load i8* @uc, align 1 + %13 = zext i8 %12 to i16 + %14 = load i8* @sc, align 1 + %15 = sext i8 %14 to i16 + %16 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %17 = cmpxchg i16* %16, i16 %13, i16 %15 monotonic + store i16 %17, i16* @us, align 2 + %18 = load i8* @uc, align 1 + %19 = zext i8 %18 to i32 + %20 = load i8* @sc, align 1 + %21 = sext i8 %20 to i32 + %22 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %23 = cmpxchg i32* %22, i32 %19, i32 %21 monotonic + store i32 %23, i32* @si, align 4 + %24 = load i8* @uc, align 1 + %25 = zext i8 %24 to i32 + %26 = load i8* @sc, align 1 + %27 = sext i8 %26 to i32 + %28 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %29 = cmpxchg i32* %28, i32 %25, i32 %27 monotonic + store i32 %29, i32* @ui, align 4 + %30 = load i8* @uc, align 1 + %31 = zext i8 %30 to i32 + %32 = load i8* @sc, align 1 + %33 = sext i8 %32 to i32 + %34 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %35 = cmpxchg i32* %34, i32 %31, i32 %33 monotonic + store i32 %35, i32* @sl, align 4 + %36 = load i8* @uc, align 1 + %37 = zext i8 %36 to i32 + %38 = load i8* @sc, align 1 + %39 = sext i8 %38 to i32 + %40 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %41 = cmpxchg i32* %40, i32 %37, i32 %39 monotonic + store i32 %41, i32* @ul, align 4 + %42 = load i8* @uc, align 1 + %43 = load i8* @sc, align 1 + %44 = cmpxchg i8* @sc, i8 %42, i8 %43 monotonic + %45 = icmp eq i8 %44, %42 + %46 = zext i1 %45 to i32 + store i32 %46, i32* @ui, align 4 + %47 = load i8* @uc, align 1 + %48 = load i8* @sc, align 1 + %49 = cmpxchg i8* @uc, i8 %47, i8 %48 monotonic + %50 = icmp eq i8 %49, %47 + %51 = zext i1 %50 to i32 + store i32 %51, i32* @ui, align 4 + %52 = load i8* @uc, align 1 + %53 = zext i8 %52 to i16 + %54 = load i8* @sc, align 1 + %55 = sext i8 %54 to i16 + %56 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %57 = cmpxchg i16* %56, i16 %53, i16 %55 monotonic + %58 = icmp eq i16 %57, %53 + %59 = zext i1 %58 to i32 + store i32 %59, i32* @ui, align 4 + %60 = load i8* @uc, align 1 + %61 = zext i8 %60 to i16 + %62 = load i8* @sc, align 1 + %63 = sext i8 %62 to i16 + %64 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %65 = cmpxchg i16* %64, i16 %61, i16 %63 monotonic + %66 = icmp eq i16 %65, %61 + %67 = zext i1 %66 to i32 + store i32 %67, i32* @ui, align 4 + %68 = load i8* @uc, align 1 + %69 = zext i8 %68 to i32 + %70 = load i8* @sc, align 1 + %71 = sext i8 %70 to i32 + %72 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %73 = cmpxchg i32* %72, i32 %69, i32 %71 monotonic + %74 = icmp eq i32 %73, %69 + %75 = zext i1 %74 to i32 + store i32 %75, i32* @ui, align 4 + %76 = load i8* @uc, align 1 + %77 = zext i8 %76 to i32 + %78 = load i8* @sc, align 1 + %79 = sext i8 %78 to i32 + %80 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %81 = cmpxchg i32* %80, i32 %77, i32 %79 monotonic + %82 = icmp eq i32 %81, %77 + %83 = zext i1 %82 to i32 + store i32 %83, i32* @ui, align 4 + %84 = load i8* @uc, align 1 + %85 = zext i8 %84 to i32 + %86 = load i8* @sc, align 1 + %87 = sext i8 %86 to i32 + %88 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %89 = cmpxchg i32* %88, i32 %85, i32 %87 monotonic + %90 = icmp eq i32 %89, %85 + %91 = zext i1 %90 to i32 + store i32 %91, i32* @ui, align 4 + %92 = load i8* @uc, align 1 + %93 = zext i8 %92 to i32 + %94 = load i8* @sc, align 1 + %95 = sext i8 %94 to i32 + %96 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %97 = cmpxchg i32* %96, i32 %93, i32 %95 monotonic + %98 = icmp eq i32 %97, %93 + %99 = zext i1 %98 to i32 + store i32 %99, i32* @ui, align 4 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } -declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind - -declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind - -declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind - define void @test_lock() nounwind { entry: - call i8 @llvm.atomic.swap.i8.p0i8( i8* @sc, i8 1 ) ; :0 [#uses=1] - store i8 %0, i8* @sc, align 1 - call i8 @llvm.atomic.swap.i8.p0i8( i8* @uc, i8 1 ) ; :1 [#uses=1] - store i8 %1, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.swap.i16.p0i16( i16* %2, i16 1 ) ; :3 [#uses=1] - store i16 %3, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.swap.i16.p0i16( i16* %4, i16 1 ) ; :5 [#uses=1] - store i16 %5, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %6, i32 1 ) ; :7 [#uses=1] - store i32 %7, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %8, i32 1 ) ; :9 [#uses=1] - store i32 %9, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :10 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %10, i32 1 ) ; :11 [#uses=1] - store i32 %11, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :12 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %12, i32 1 ) ; :13 [#uses=1] - store i32 %13, i32* @ul, align 4 - call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true, i1 false ) - volatile store i8 0, i8* @sc, align 1 - volatile store i8 0, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :14 [#uses=1] - volatile store i16 0, i16* %14, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :15 [#uses=1] - volatile store i16 0, i16* %15, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :16 [#uses=1] - volatile store i32 0, i32* %16, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :17 [#uses=1] - volatile store i32 0, i32* %17, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :18 [#uses=1] - volatile store i32 0, i32* %18, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :19 [#uses=1] - volatile store i32 0, i32* %19, align 4 - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :20 [#uses=1] - volatile store i64 0, i64* %20, align 8 - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :21 [#uses=1] - volatile store i64 0, i64* %21, align 8 - br label %return + %0 = atomicrmw xchg i8* @sc, i8 1 monotonic + store i8 %0, i8* @sc, align 1 + %1 = atomicrmw xchg i8* @uc, i8 1 monotonic + store i8 %1, i8* @uc, align 1 + %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %3 = atomicrmw xchg i16* %2, i16 1 monotonic + store i16 %3, i16* @ss, align 2 + %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %5 = atomicrmw xchg i16* %4, i16 1 monotonic + store i16 %5, i16* @us, align 2 + %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %7 = atomicrmw xchg i32* %6, i32 1 monotonic + store i32 %7, i32* @si, align 4 + %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %9 = atomicrmw xchg i32* %8, i32 1 monotonic + store i32 %9, i32* @ui, align 4 + %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + %11 = atomicrmw xchg i32* %10, i32 1 monotonic + store i32 %11, i32* @sl, align 4 + %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + %13 = atomicrmw xchg i32* %12, i32 1 monotonic + store i32 %13, i32* @ul, align 4 + fence seq_cst + store volatile i8 0, i8* @sc, align 1 + store volatile i8 0, i8* @uc, align 1 + %14 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + store volatile i16 0, i16* %14, align 2 + %15 = bitcast i8* bitcast (i16* @us to i8*) to i16* + store volatile i16 0, i16* %15, align 2 + %16 = bitcast i8* bitcast (i32* @si to i8*) to i32* + store volatile i32 0, i32* %16, align 4 + %17 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + store volatile i32 0, i32* %17, align 4 + %18 = bitcast i8* bitcast (i32* @sl to i8*) to i32* + store volatile i32 0, i32* %18, align 4 + %19 = bitcast i8* bitcast (i32* @ul to i8*) to i32* + store volatile i32 0, i32* %19, align 4 + %20 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + store volatile i64 0, i64* %20, align 8 + %21 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + store volatile i64 0, i64* %21, align 8 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } - -declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind - -declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind Modified: llvm/trunk/test/CodeGen/PowerPC/Atomics-64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/Atomics-64.ll?rev=140566&r1=140565&r2=140566&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/Atomics-64.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/Atomics-64.ll Mon Sep 26 16:30:17 2011 @@ -8,772 +8,707 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc64-apple-darwin9" - at sc = common global i8 0 ; [#uses=52] - at uc = common global i8 0 ; [#uses=100] - at ss = common global i16 0 ; [#uses=15] - at us = common global i16 0 ; [#uses=15] - at si = common global i32 0 ; [#uses=15] - at ui = common global i32 0 ; [#uses=23] - at sl = common global i64 0, align 8 ; [#uses=15] - at ul = common global i64 0, align 8 ; [#uses=15] - at sll = common global i64 0, align 8 ; [#uses=1] - at ull = common global i64 0, align 8 ; [#uses=1] + + at sc = common global i8 0 + at uc = common global i8 0 + at ss = common global i16 0 + at us = common global i16 0 + at si = common global i32 0 + at ui = common global i32 0 + at sl = common global i64 0, align 8 + at ul = common global i64 0, align 8 + at sll = common global i64 0, align 8 + at ull = common global i64 0, align 8 define void @test_op_ignore() nounwind { entry: - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 1 ) ; :0 [#uses=0] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 1 ) ; :1 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; :3 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; :5 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 1 ) ; :7 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 1 ) ; :9 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :10 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %10, i64 1 ) ; :11 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :12 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %12, i64 1 ) ; :13 [#uses=0] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 1 ) ; :14 [#uses=0] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 1 ) ; :15 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :16 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 1 ) ; :17 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :18 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 1 ) ; :19 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :20 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 1 ) ; :21 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :22 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 1 ) ; :23 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :24 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %24, i64 1 ) ; :25 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :26 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %26, i64 1 ) ; :27 [#uses=0] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 1 ) ; :28 [#uses=0] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 1 ) ; :29 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :30 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 1 ) ; :31 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :32 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 1 ) ; :33 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :34 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 1 ) ; :35 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :36 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 1 ) ; :37 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :38 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %38, i64 1 ) ; :39 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :40 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %40, i64 1 ) ; :41 [#uses=0] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 1 ) ; :42 [#uses=0] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 1 ) ; :43 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :44 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 1 ) ; :45 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :46 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 1 ) ; :47 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :48 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 1 ) ; :49 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :50 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 1 ) ; :51 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :52 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %52, i64 1 ) ; :53 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :54 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %54, i64 1 ) ; :55 [#uses=0] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 1 ) ; :56 [#uses=0] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 1 ) ; :57 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :58 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 1 ) ; :59 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :60 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 1 ) ; :61 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :62 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 1 ) ; :63 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :64 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 1 ) ; :65 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :66 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %66, i64 1 ) ; :67 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :68 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %68, i64 1 ) ; :69 [#uses=0] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 1 ) ; :70 [#uses=0] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 1 ) ; :71 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :72 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 1 ) ; :73 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :74 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 1 ) ; :75 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :76 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 1 ) ; :77 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :78 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 1 ) ; :79 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :80 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %80, i64 1 ) ; :81 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :82 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %82, i64 1 ) ; :83 [#uses=0] - br label %return + %0 = atomicrmw add i8* @sc, i8 1 monotonic + %1 = atomicrmw add i8* @uc, i8 1 monotonic + %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %3 = atomicrmw add i16* %2, i16 1 monotonic + %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %5 = atomicrmw add i16* %4, i16 1 monotonic + %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %7 = atomicrmw add i32* %6, i32 1 monotonic + %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %9 = atomicrmw add i32* %8, i32 1 monotonic + %10 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %11 = atomicrmw add i64* %10, i64 1 monotonic + %12 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %13 = atomicrmw add i64* %12, i64 1 monotonic + %14 = atomicrmw sub i8* @sc, i8 1 monotonic + %15 = atomicrmw sub i8* @uc, i8 1 monotonic + %16 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %17 = atomicrmw sub i16* %16, i16 1 monotonic + %18 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %19 = atomicrmw sub i16* %18, i16 1 monotonic + %20 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %21 = atomicrmw sub i32* %20, i32 1 monotonic + %22 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %23 = atomicrmw sub i32* %22, i32 1 monotonic + %24 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %25 = atomicrmw sub i64* %24, i64 1 monotonic + %26 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %27 = atomicrmw sub i64* %26, i64 1 monotonic + %28 = atomicrmw or i8* @sc, i8 1 monotonic + %29 = atomicrmw or i8* @uc, i8 1 monotonic + %30 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %31 = atomicrmw or i16* %30, i16 1 monotonic + %32 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %33 = atomicrmw or i16* %32, i16 1 monotonic + %34 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %35 = atomicrmw or i32* %34, i32 1 monotonic + %36 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %37 = atomicrmw or i32* %36, i32 1 monotonic + %38 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %39 = atomicrmw or i64* %38, i64 1 monotonic + %40 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %41 = atomicrmw or i64* %40, i64 1 monotonic + %42 = atomicrmw xor i8* @sc, i8 1 monotonic + %43 = atomicrmw xor i8* @uc, i8 1 monotonic + %44 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %45 = atomicrmw xor i16* %44, i16 1 monotonic + %46 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %47 = atomicrmw xor i16* %46, i16 1 monotonic + %48 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %49 = atomicrmw xor i32* %48, i32 1 monotonic + %50 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %51 = atomicrmw xor i32* %50, i32 1 monotonic + %52 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %53 = atomicrmw xor i64* %52, i64 1 monotonic + %54 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %55 = atomicrmw xor i64* %54, i64 1 monotonic + %56 = atomicrmw and i8* @sc, i8 1 monotonic + %57 = atomicrmw and i8* @uc, i8 1 monotonic + %58 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %59 = atomicrmw and i16* %58, i16 1 monotonic + %60 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %61 = atomicrmw and i16* %60, i16 1 monotonic + %62 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %63 = atomicrmw and i32* %62, i32 1 monotonic + %64 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %65 = atomicrmw and i32* %64, i32 1 monotonic + %66 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %67 = atomicrmw and i64* %66, i64 1 monotonic + %68 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %69 = atomicrmw and i64* %68, i64 1 monotonic + %70 = atomicrmw nand i8* @sc, i8 1 monotonic + %71 = atomicrmw nand i8* @uc, i8 1 monotonic + %72 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %73 = atomicrmw nand i16* %72, i16 1 monotonic + %74 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %75 = atomicrmw nand i16* %74, i16 1 monotonic + %76 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %77 = atomicrmw nand i32* %76, i32 1 monotonic + %78 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %79 = atomicrmw nand i32* %78, i32 1 monotonic + %80 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %81 = atomicrmw nand i64* %80, i64 1 monotonic + %82 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %83 = atomicrmw nand i64* %82, i64 1 monotonic + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } -declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.add.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.sub.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.or.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.xor.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.and.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.nand.i64.p0i64(i64*, i64) nounwind - define void @test_fetch_and_op() nounwind { entry: - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 11 ) ; :0 [#uses=1] - store i8 %0, i8* @sc, align 1 - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 11 ) ; :1 [#uses=1] - store i8 %1, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 11 ) ; :3 [#uses=1] - store i16 %3, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 11 ) ; :5 [#uses=1] - store i16 %5, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 11 ) ; :7 [#uses=1] - store i32 %7, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 11 ) ; :9 [#uses=1] - store i32 %9, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :10 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %10, i64 11 ) ; :11 [#uses=1] - store i64 %11, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :12 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %12, i64 11 ) ; :13 [#uses=1] - store i64 %13, i64* @ul, align 8 - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 11 ) ; :14 [#uses=1] - store i8 %14, i8* @sc, align 1 - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 11 ) ; :15 [#uses=1] - store i8 %15, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :16 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 11 ) ; :17 [#uses=1] - store i16 %17, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :18 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 11 ) ; :19 [#uses=1] - store i16 %19, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :20 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 11 ) ; :21 [#uses=1] - store i32 %21, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :22 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 11 ) ; :23 [#uses=1] - store i32 %23, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :24 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %24, i64 11 ) ; :25 [#uses=1] - store i64 %25, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :26 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %26, i64 11 ) ; :27 [#uses=1] - store i64 %27, i64* @ul, align 8 - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 11 ) ; :28 [#uses=1] - store i8 %28, i8* @sc, align 1 - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 11 ) ; :29 [#uses=1] - store i8 %29, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :30 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 11 ) ; :31 [#uses=1] - store i16 %31, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :32 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 11 ) ; :33 [#uses=1] - store i16 %33, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :34 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 11 ) ; :35 [#uses=1] - store i32 %35, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :36 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 11 ) ; :37 [#uses=1] - store i32 %37, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :38 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %38, i64 11 ) ; :39 [#uses=1] - store i64 %39, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :40 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %40, i64 11 ) ; :41 [#uses=1] - store i64 %41, i64* @ul, align 8 - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 11 ) ; :42 [#uses=1] - store i8 %42, i8* @sc, align 1 - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 11 ) ; :43 [#uses=1] - store i8 %43, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :44 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 11 ) ; :45 [#uses=1] - store i16 %45, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :46 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 11 ) ; :47 [#uses=1] - store i16 %47, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :48 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 11 ) ; :49 [#uses=1] - store i32 %49, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :50 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 11 ) ; :51 [#uses=1] - store i32 %51, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :52 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %52, i64 11 ) ; :53 [#uses=1] - store i64 %53, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :54 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %54, i64 11 ) ; :55 [#uses=1] - store i64 %55, i64* @ul, align 8 - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 11 ) ; :56 [#uses=1] - store i8 %56, i8* @sc, align 1 - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 11 ) ; :57 [#uses=1] - store i8 %57, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :58 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 11 ) ; :59 [#uses=1] - store i16 %59, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :60 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 11 ) ; :61 [#uses=1] - store i16 %61, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :62 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 11 ) ; :63 [#uses=1] - store i32 %63, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :64 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 11 ) ; :65 [#uses=1] - store i32 %65, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :66 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %66, i64 11 ) ; :67 [#uses=1] - store i64 %67, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :68 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %68, i64 11 ) ; :69 [#uses=1] - store i64 %69, i64* @ul, align 8 - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 11 ) ; :70 [#uses=1] - store i8 %70, i8* @sc, align 1 - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 11 ) ; :71 [#uses=1] - store i8 %71, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :72 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 11 ) ; :73 [#uses=1] - store i16 %73, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :74 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 11 ) ; :75 [#uses=1] - store i16 %75, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :76 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 11 ) ; :77 [#uses=1] - store i32 %77, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :78 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 11 ) ; :79 [#uses=1] - store i32 %79, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :80 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %80, i64 11 ) ; :81 [#uses=1] - store i64 %81, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :82 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %82, i64 11 ) ; :83 [#uses=1] - store i64 %83, i64* @ul, align 8 - br label %return + %0 = atomicrmw add i8* @sc, i8 11 monotonic + store i8 %0, i8* @sc, align 1 + %1 = atomicrmw add i8* @uc, i8 11 monotonic + store i8 %1, i8* @uc, align 1 + %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %3 = atomicrmw add i16* %2, i16 11 monotonic + store i16 %3, i16* @ss, align 2 + %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %5 = atomicrmw add i16* %4, i16 11 monotonic + store i16 %5, i16* @us, align 2 + %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %7 = atomicrmw add i32* %6, i32 11 monotonic + store i32 %7, i32* @si, align 4 + %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %9 = atomicrmw add i32* %8, i32 11 monotonic + store i32 %9, i32* @ui, align 4 + %10 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %11 = atomicrmw add i64* %10, i64 11 monotonic + store i64 %11, i64* @sl, align 8 + %12 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %13 = atomicrmw add i64* %12, i64 11 monotonic + store i64 %13, i64* @ul, align 8 + %14 = atomicrmw sub i8* @sc, i8 11 monotonic + store i8 %14, i8* @sc, align 1 + %15 = atomicrmw sub i8* @uc, i8 11 monotonic + store i8 %15, i8* @uc, align 1 + %16 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %17 = atomicrmw sub i16* %16, i16 11 monotonic + store i16 %17, i16* @ss, align 2 + %18 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %19 = atomicrmw sub i16* %18, i16 11 monotonic + store i16 %19, i16* @us, align 2 + %20 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %21 = atomicrmw sub i32* %20, i32 11 monotonic + store i32 %21, i32* @si, align 4 + %22 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %23 = atomicrmw sub i32* %22, i32 11 monotonic + store i32 %23, i32* @ui, align 4 + %24 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %25 = atomicrmw sub i64* %24, i64 11 monotonic + store i64 %25, i64* @sl, align 8 + %26 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %27 = atomicrmw sub i64* %26, i64 11 monotonic + store i64 %27, i64* @ul, align 8 + %28 = atomicrmw or i8* @sc, i8 11 monotonic + store i8 %28, i8* @sc, align 1 + %29 = atomicrmw or i8* @uc, i8 11 monotonic + store i8 %29, i8* @uc, align 1 + %30 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %31 = atomicrmw or i16* %30, i16 11 monotonic + store i16 %31, i16* @ss, align 2 + %32 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %33 = atomicrmw or i16* %32, i16 11 monotonic + store i16 %33, i16* @us, align 2 + %34 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %35 = atomicrmw or i32* %34, i32 11 monotonic + store i32 %35, i32* @si, align 4 + %36 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %37 = atomicrmw or i32* %36, i32 11 monotonic + store i32 %37, i32* @ui, align 4 + %38 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %39 = atomicrmw or i64* %38, i64 11 monotonic + store i64 %39, i64* @sl, align 8 + %40 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %41 = atomicrmw or i64* %40, i64 11 monotonic + store i64 %41, i64* @ul, align 8 + %42 = atomicrmw xor i8* @sc, i8 11 monotonic + store i8 %42, i8* @sc, align 1 + %43 = atomicrmw xor i8* @uc, i8 11 monotonic + store i8 %43, i8* @uc, align 1 + %44 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %45 = atomicrmw xor i16* %44, i16 11 monotonic + store i16 %45, i16* @ss, align 2 + %46 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %47 = atomicrmw xor i16* %46, i16 11 monotonic + store i16 %47, i16* @us, align 2 + %48 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %49 = atomicrmw xor i32* %48, i32 11 monotonic + store i32 %49, i32* @si, align 4 + %50 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %51 = atomicrmw xor i32* %50, i32 11 monotonic + store i32 %51, i32* @ui, align 4 + %52 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %53 = atomicrmw xor i64* %52, i64 11 monotonic + store i64 %53, i64* @sl, align 8 + %54 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %55 = atomicrmw xor i64* %54, i64 11 monotonic + store i64 %55, i64* @ul, align 8 + %56 = atomicrmw and i8* @sc, i8 11 monotonic + store i8 %56, i8* @sc, align 1 + %57 = atomicrmw and i8* @uc, i8 11 monotonic + store i8 %57, i8* @uc, align 1 + %58 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %59 = atomicrmw and i16* %58, i16 11 monotonic + store i16 %59, i16* @ss, align 2 + %60 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %61 = atomicrmw and i16* %60, i16 11 monotonic + store i16 %61, i16* @us, align 2 + %62 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %63 = atomicrmw and i32* %62, i32 11 monotonic + store i32 %63, i32* @si, align 4 + %64 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %65 = atomicrmw and i32* %64, i32 11 monotonic + store i32 %65, i32* @ui, align 4 + %66 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %67 = atomicrmw and i64* %66, i64 11 monotonic + store i64 %67, i64* @sl, align 8 + %68 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %69 = atomicrmw and i64* %68, i64 11 monotonic + store i64 %69, i64* @ul, align 8 + %70 = atomicrmw nand i8* @sc, i8 11 monotonic + store i8 %70, i8* @sc, align 1 + %71 = atomicrmw nand i8* @uc, i8 11 monotonic + store i8 %71, i8* @uc, align 1 + %72 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %73 = atomicrmw nand i16* %72, i16 11 monotonic + store i16 %73, i16* @ss, align 2 + %74 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %75 = atomicrmw nand i16* %74, i16 11 monotonic + store i16 %75, i16* @us, align 2 + %76 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %77 = atomicrmw nand i32* %76, i32 11 monotonic + store i32 %77, i32* @si, align 4 + %78 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %79 = atomicrmw nand i32* %78, i32 11 monotonic + store i32 %79, i32* @ui, align 4 + %80 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %81 = atomicrmw nand i64* %80, i64 11 monotonic + store i64 %81, i64* @sl, align 8 + %82 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %83 = atomicrmw nand i64* %82, i64 11 monotonic + store i64 %83, i64* @ul, align 8 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } define void @test_op_and_fetch() nounwind { entry: - load i8* @uc, align 1 ; :0 [#uses=2] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 %0 ) ; :1 [#uses=1] - add i8 %1, %0 ; :2 [#uses=1] - store i8 %2, i8* @sc, align 1 - load i8* @uc, align 1 ; :3 [#uses=2] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 %3 ) ; :4 [#uses=1] - add i8 %4, %3 ; :5 [#uses=1] - store i8 %5, i8* @uc, align 1 - load i8* @uc, align 1 ; :6 [#uses=1] - zext i8 %6 to i16 ; :7 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :8 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %8, i16 %7 ) ; :9 [#uses=1] - add i16 %9, %7 ; :10 [#uses=1] - store i16 %10, i16* @ss, align 2 - load i8* @uc, align 1 ; :11 [#uses=1] - zext i8 %11 to i16 ; :12 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :13 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %13, i16 %12 ) ; :14 [#uses=1] - add i16 %14, %12 ; :15 [#uses=1] - store i16 %15, i16* @us, align 2 - load i8* @uc, align 1 ; :16 [#uses=1] - zext i8 %16 to i32 ; :17 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :18 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %18, i32 %17 ) ; :19 [#uses=1] - add i32 %19, %17 ; :20 [#uses=1] - store i32 %20, i32* @si, align 4 - load i8* @uc, align 1 ; :21 [#uses=1] - zext i8 %21 to i32 ; :22 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :23 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %23, i32 %22 ) ; :24 [#uses=1] - add i32 %24, %22 ; :25 [#uses=1] - store i32 %25, i32* @ui, align 4 - load i8* @uc, align 1 ; :26 [#uses=1] - zext i8 %26 to i64 ; :27 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :28 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %28, i64 %27 ) ; :29 [#uses=1] - add i64 %29, %27 ; :30 [#uses=1] - store i64 %30, i64* @sl, align 8 - load i8* @uc, align 1 ; :31 [#uses=1] - zext i8 %31 to i64 ; :32 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :33 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %33, i64 %32 ) ; :34 [#uses=1] - add i64 %34, %32 ; :35 [#uses=1] - store i64 %35, i64* @ul, align 8 - load i8* @uc, align 1 ; :36 [#uses=2] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 %36 ) ; :37 [#uses=1] - sub i8 %37, %36 ; :38 [#uses=1] - store i8 %38, i8* @sc, align 1 - load i8* @uc, align 1 ; :39 [#uses=2] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 %39 ) ; :40 [#uses=1] - sub i8 %40, %39 ; :41 [#uses=1] - store i8 %41, i8* @uc, align 1 - load i8* @uc, align 1 ; :42 [#uses=1] - zext i8 %42 to i16 ; :43 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :44 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %44, i16 %43 ) ; :45 [#uses=1] - sub i16 %45, %43 ; :46 [#uses=1] - store i16 %46, i16* @ss, align 2 - load i8* @uc, align 1 ; :47 [#uses=1] - zext i8 %47 to i16 ; :48 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :49 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %49, i16 %48 ) ; :50 [#uses=1] - sub i16 %50, %48 ; :51 [#uses=1] - store i16 %51, i16* @us, align 2 - load i8* @uc, align 1 ; :52 [#uses=1] - zext i8 %52 to i32 ; :53 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :54 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %54, i32 %53 ) ; :55 [#uses=1] - sub i32 %55, %53 ; :56 [#uses=1] - store i32 %56, i32* @si, align 4 - load i8* @uc, align 1 ; :57 [#uses=1] - zext i8 %57 to i32 ; :58 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :59 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %59, i32 %58 ) ; :60 [#uses=1] - sub i32 %60, %58 ; :61 [#uses=1] - store i32 %61, i32* @ui, align 4 - load i8* @uc, align 1 ; :62 [#uses=1] - zext i8 %62 to i64 ; :63 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :64 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %64, i64 %63 ) ; :65 [#uses=1] - sub i64 %65, %63 ; :66 [#uses=1] - store i64 %66, i64* @sl, align 8 - load i8* @uc, align 1 ; :67 [#uses=1] - zext i8 %67 to i64 ; :68 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :69 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %69, i64 %68 ) ; :70 [#uses=1] - sub i64 %70, %68 ; :71 [#uses=1] - store i64 %71, i64* @ul, align 8 - load i8* @uc, align 1 ; :72 [#uses=2] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 %72 ) ; :73 [#uses=1] - or i8 %73, %72 ; :74 [#uses=1] - store i8 %74, i8* @sc, align 1 - load i8* @uc, align 1 ; :75 [#uses=2] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 %75 ) ; :76 [#uses=1] - or i8 %76, %75 ; :77 [#uses=1] - store i8 %77, i8* @uc, align 1 - load i8* @uc, align 1 ; :78 [#uses=1] - zext i8 %78 to i16 ; :79 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :80 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %80, i16 %79 ) ; :81 [#uses=1] - or i16 %81, %79 ; :82 [#uses=1] - store i16 %82, i16* @ss, align 2 - load i8* @uc, align 1 ; :83 [#uses=1] - zext i8 %83 to i16 ; :84 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :85 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %85, i16 %84 ) ; :86 [#uses=1] - or i16 %86, %84 ; :87 [#uses=1] - store i16 %87, i16* @us, align 2 - load i8* @uc, align 1 ; :88 [#uses=1] - zext i8 %88 to i32 ; :89 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :90 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %90, i32 %89 ) ; :91 [#uses=1] - or i32 %91, %89 ; :92 [#uses=1] - store i32 %92, i32* @si, align 4 - load i8* @uc, align 1 ; :93 [#uses=1] - zext i8 %93 to i32 ; :94 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :95 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %95, i32 %94 ) ; :96 [#uses=1] - or i32 %96, %94 ; :97 [#uses=1] - store i32 %97, i32* @ui, align 4 - load i8* @uc, align 1 ; :98 [#uses=1] - zext i8 %98 to i64 ; :99 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :100 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %100, i64 %99 ) ; :101 [#uses=1] - or i64 %101, %99 ; :102 [#uses=1] - store i64 %102, i64* @sl, align 8 - load i8* @uc, align 1 ; :103 [#uses=1] - zext i8 %103 to i64 ; :104 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :105 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %105, i64 %104 ) ; :106 [#uses=1] - or i64 %106, %104 ; :107 [#uses=1] - store i64 %107, i64* @ul, align 8 - load i8* @uc, align 1 ; :108 [#uses=2] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 %108 ) ; :109 [#uses=1] - xor i8 %109, %108 ; :110 [#uses=1] - store i8 %110, i8* @sc, align 1 - load i8* @uc, align 1 ; :111 [#uses=2] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 %111 ) ; :112 [#uses=1] - xor i8 %112, %111 ; :113 [#uses=1] - store i8 %113, i8* @uc, align 1 - load i8* @uc, align 1 ; :114 [#uses=1] - zext i8 %114 to i16 ; :115 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :116 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %116, i16 %115 ) ; :117 [#uses=1] - xor i16 %117, %115 ; :118 [#uses=1] - store i16 %118, i16* @ss, align 2 - load i8* @uc, align 1 ; :119 [#uses=1] - zext i8 %119 to i16 ; :120 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :121 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %121, i16 %120 ) ; :122 [#uses=1] - xor i16 %122, %120 ; :123 [#uses=1] - store i16 %123, i16* @us, align 2 - load i8* @uc, align 1 ; :124 [#uses=1] - zext i8 %124 to i32 ; :125 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :126 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %126, i32 %125 ) ; :127 [#uses=1] - xor i32 %127, %125 ; :128 [#uses=1] - store i32 %128, i32* @si, align 4 - load i8* @uc, align 1 ; :129 [#uses=1] - zext i8 %129 to i32 ; :130 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :131 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %131, i32 %130 ) ; :132 [#uses=1] - xor i32 %132, %130 ; :133 [#uses=1] - store i32 %133, i32* @ui, align 4 - load i8* @uc, align 1 ; :134 [#uses=1] - zext i8 %134 to i64 ; :135 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :136 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %136, i64 %135 ) ; :137 [#uses=1] - xor i64 %137, %135 ; :138 [#uses=1] - store i64 %138, i64* @sl, align 8 - load i8* @uc, align 1 ; :139 [#uses=1] - zext i8 %139 to i64 ; :140 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :141 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %141, i64 %140 ) ; :142 [#uses=1] - xor i64 %142, %140 ; :143 [#uses=1] - store i64 %143, i64* @ul, align 8 - load i8* @uc, align 1 ; :144 [#uses=2] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 %144 ) ; :145 [#uses=1] - and i8 %145, %144 ; :146 [#uses=1] - store i8 %146, i8* @sc, align 1 - load i8* @uc, align 1 ; :147 [#uses=2] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 %147 ) ; :148 [#uses=1] - and i8 %148, %147 ; :149 [#uses=1] - store i8 %149, i8* @uc, align 1 - load i8* @uc, align 1 ; :150 [#uses=1] - zext i8 %150 to i16 ; :151 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :152 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %152, i16 %151 ) ; :153 [#uses=1] - and i16 %153, %151 ; :154 [#uses=1] - store i16 %154, i16* @ss, align 2 - load i8* @uc, align 1 ; :155 [#uses=1] - zext i8 %155 to i16 ; :156 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :157 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %157, i16 %156 ) ; :158 [#uses=1] - and i16 %158, %156 ; :159 [#uses=1] - store i16 %159, i16* @us, align 2 - load i8* @uc, align 1 ; :160 [#uses=1] - zext i8 %160 to i32 ; :161 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :162 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %162, i32 %161 ) ; :163 [#uses=1] - and i32 %163, %161 ; :164 [#uses=1] - store i32 %164, i32* @si, align 4 - load i8* @uc, align 1 ; :165 [#uses=1] - zext i8 %165 to i32 ; :166 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :167 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %167, i32 %166 ) ; :168 [#uses=1] - and i32 %168, %166 ; :169 [#uses=1] - store i32 %169, i32* @ui, align 4 - load i8* @uc, align 1 ; :170 [#uses=1] - zext i8 %170 to i64 ; :171 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :172 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %172, i64 %171 ) ; :173 [#uses=1] - and i64 %173, %171 ; :174 [#uses=1] - store i64 %174, i64* @sl, align 8 - load i8* @uc, align 1 ; :175 [#uses=1] - zext i8 %175 to i64 ; :176 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :177 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %177, i64 %176 ) ; :178 [#uses=1] - and i64 %178, %176 ; :179 [#uses=1] - store i64 %179, i64* @ul, align 8 - load i8* @uc, align 1 ; :180 [#uses=2] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 %180 ) ; :181 [#uses=1] - xor i8 %181, -1 ; :182 [#uses=1] - and i8 %182, %180 ; :183 [#uses=1] - store i8 %183, i8* @sc, align 1 - load i8* @uc, align 1 ; :184 [#uses=2] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 %184 ) ; :185 [#uses=1] - xor i8 %185, -1 ; :186 [#uses=1] - and i8 %186, %184 ; :187 [#uses=1] - store i8 %187, i8* @uc, align 1 - load i8* @uc, align 1 ; :188 [#uses=1] - zext i8 %188 to i16 ; :189 [#uses=2] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :190 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %190, i16 %189 ) ; :191 [#uses=1] - xor i16 %191, -1 ; :192 [#uses=1] - and i16 %192, %189 ; :193 [#uses=1] - store i16 %193, i16* @ss, align 2 - load i8* @uc, align 1 ; :194 [#uses=1] - zext i8 %194 to i16 ; :195 [#uses=2] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :196 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %196, i16 %195 ) ; :197 [#uses=1] - xor i16 %197, -1 ; :198 [#uses=1] - and i16 %198, %195 ; :199 [#uses=1] - store i16 %199, i16* @us, align 2 - load i8* @uc, align 1 ; :200 [#uses=1] - zext i8 %200 to i32 ; :201 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :202 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %202, i32 %201 ) ; :203 [#uses=1] - xor i32 %203, -1 ; :204 [#uses=1] - and i32 %204, %201 ; :205 [#uses=1] - store i32 %205, i32* @si, align 4 - load i8* @uc, align 1 ; :206 [#uses=1] - zext i8 %206 to i32 ; :207 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :208 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %208, i32 %207 ) ; :209 [#uses=1] - xor i32 %209, -1 ; :210 [#uses=1] - and i32 %210, %207 ; :211 [#uses=1] - store i32 %211, i32* @ui, align 4 - load i8* @uc, align 1 ; :212 [#uses=1] - zext i8 %212 to i64 ; :213 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :214 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %214, i64 %213 ) ; :215 [#uses=1] - xor i64 %215, -1 ; :216 [#uses=1] - and i64 %216, %213 ; :217 [#uses=1] - store i64 %217, i64* @sl, align 8 - load i8* @uc, align 1 ; :218 [#uses=1] - zext i8 %218 to i64 ; :219 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :220 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %220, i64 %219 ) ; :221 [#uses=1] - xor i64 %221, -1 ; :222 [#uses=1] - and i64 %222, %219 ; :223 [#uses=1] - store i64 %223, i64* @ul, align 8 - br label %return + %0 = load i8* @uc, align 1 + %1 = atomicrmw add i8* @sc, i8 %0 monotonic + %2 = add i8 %1, %0 + store i8 %2, i8* @sc, align 1 + %3 = load i8* @uc, align 1 + %4 = atomicrmw add i8* @uc, i8 %3 monotonic + %5 = add i8 %4, %3 + store i8 %5, i8* @uc, align 1 + %6 = load i8* @uc, align 1 + %7 = zext i8 %6 to i16 + %8 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %9 = atomicrmw add i16* %8, i16 %7 monotonic + %10 = add i16 %9, %7 + store i16 %10, i16* @ss, align 2 + %11 = load i8* @uc, align 1 + %12 = zext i8 %11 to i16 + %13 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %14 = atomicrmw add i16* %13, i16 %12 monotonic + %15 = add i16 %14, %12 + store i16 %15, i16* @us, align 2 + %16 = load i8* @uc, align 1 + %17 = zext i8 %16 to i32 + %18 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %19 = atomicrmw add i32* %18, i32 %17 monotonic + %20 = add i32 %19, %17 + store i32 %20, i32* @si, align 4 + %21 = load i8* @uc, align 1 + %22 = zext i8 %21 to i32 + %23 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %24 = atomicrmw add i32* %23, i32 %22 monotonic + %25 = add i32 %24, %22 + store i32 %25, i32* @ui, align 4 + %26 = load i8* @uc, align 1 + %27 = zext i8 %26 to i64 + %28 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %29 = atomicrmw add i64* %28, i64 %27 monotonic + %30 = add i64 %29, %27 + store i64 %30, i64* @sl, align 8 + %31 = load i8* @uc, align 1 + %32 = zext i8 %31 to i64 + %33 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %34 = atomicrmw add i64* %33, i64 %32 monotonic + %35 = add i64 %34, %32 + store i64 %35, i64* @ul, align 8 + %36 = load i8* @uc, align 1 + %37 = atomicrmw sub i8* @sc, i8 %36 monotonic + %38 = sub i8 %37, %36 + store i8 %38, i8* @sc, align 1 + %39 = load i8* @uc, align 1 + %40 = atomicrmw sub i8* @uc, i8 %39 monotonic + %41 = sub i8 %40, %39 + store i8 %41, i8* @uc, align 1 + %42 = load i8* @uc, align 1 + %43 = zext i8 %42 to i16 + %44 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %45 = atomicrmw sub i16* %44, i16 %43 monotonic + %46 = sub i16 %45, %43 + store i16 %46, i16* @ss, align 2 + %47 = load i8* @uc, align 1 + %48 = zext i8 %47 to i16 + %49 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %50 = atomicrmw sub i16* %49, i16 %48 monotonic + %51 = sub i16 %50, %48 + store i16 %51, i16* @us, align 2 + %52 = load i8* @uc, align 1 + %53 = zext i8 %52 to i32 + %54 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %55 = atomicrmw sub i32* %54, i32 %53 monotonic + %56 = sub i32 %55, %53 + store i32 %56, i32* @si, align 4 + %57 = load i8* @uc, align 1 + %58 = zext i8 %57 to i32 + %59 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %60 = atomicrmw sub i32* %59, i32 %58 monotonic + %61 = sub i32 %60, %58 + store i32 %61, i32* @ui, align 4 + %62 = load i8* @uc, align 1 + %63 = zext i8 %62 to i64 + %64 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %65 = atomicrmw sub i64* %64, i64 %63 monotonic + %66 = sub i64 %65, %63 + store i64 %66, i64* @sl, align 8 + %67 = load i8* @uc, align 1 + %68 = zext i8 %67 to i64 + %69 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %70 = atomicrmw sub i64* %69, i64 %68 monotonic + %71 = sub i64 %70, %68 + store i64 %71, i64* @ul, align 8 + %72 = load i8* @uc, align 1 + %73 = atomicrmw or i8* @sc, i8 %72 monotonic + %74 = or i8 %73, %72 + store i8 %74, i8* @sc, align 1 + %75 = load i8* @uc, align 1 + %76 = atomicrmw or i8* @uc, i8 %75 monotonic + %77 = or i8 %76, %75 + store i8 %77, i8* @uc, align 1 + %78 = load i8* @uc, align 1 + %79 = zext i8 %78 to i16 + %80 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %81 = atomicrmw or i16* %80, i16 %79 monotonic + %82 = or i16 %81, %79 + store i16 %82, i16* @ss, align 2 + %83 = load i8* @uc, align 1 + %84 = zext i8 %83 to i16 + %85 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %86 = atomicrmw or i16* %85, i16 %84 monotonic + %87 = or i16 %86, %84 + store i16 %87, i16* @us, align 2 + %88 = load i8* @uc, align 1 + %89 = zext i8 %88 to i32 + %90 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %91 = atomicrmw or i32* %90, i32 %89 monotonic + %92 = or i32 %91, %89 + store i32 %92, i32* @si, align 4 + %93 = load i8* @uc, align 1 + %94 = zext i8 %93 to i32 + %95 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %96 = atomicrmw or i32* %95, i32 %94 monotonic + %97 = or i32 %96, %94 + store i32 %97, i32* @ui, align 4 + %98 = load i8* @uc, align 1 + %99 = zext i8 %98 to i64 + %100 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %101 = atomicrmw or i64* %100, i64 %99 monotonic + %102 = or i64 %101, %99 + store i64 %102, i64* @sl, align 8 + %103 = load i8* @uc, align 1 + %104 = zext i8 %103 to i64 + %105 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %106 = atomicrmw or i64* %105, i64 %104 monotonic + %107 = or i64 %106, %104 + store i64 %107, i64* @ul, align 8 + %108 = load i8* @uc, align 1 + %109 = atomicrmw xor i8* @sc, i8 %108 monotonic + %110 = xor i8 %109, %108 + store i8 %110, i8* @sc, align 1 + %111 = load i8* @uc, align 1 + %112 = atomicrmw xor i8* @uc, i8 %111 monotonic + %113 = xor i8 %112, %111 + store i8 %113, i8* @uc, align 1 + %114 = load i8* @uc, align 1 + %115 = zext i8 %114 to i16 + %116 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %117 = atomicrmw xor i16* %116, i16 %115 monotonic + %118 = xor i16 %117, %115 + store i16 %118, i16* @ss, align 2 + %119 = load i8* @uc, align 1 + %120 = zext i8 %119 to i16 + %121 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %122 = atomicrmw xor i16* %121, i16 %120 monotonic + %123 = xor i16 %122, %120 + store i16 %123, i16* @us, align 2 + %124 = load i8* @uc, align 1 + %125 = zext i8 %124 to i32 + %126 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %127 = atomicrmw xor i32* %126, i32 %125 monotonic + %128 = xor i32 %127, %125 + store i32 %128, i32* @si, align 4 + %129 = load i8* @uc, align 1 + %130 = zext i8 %129 to i32 + %131 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %132 = atomicrmw xor i32* %131, i32 %130 monotonic + %133 = xor i32 %132, %130 + store i32 %133, i32* @ui, align 4 + %134 = load i8* @uc, align 1 + %135 = zext i8 %134 to i64 + %136 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %137 = atomicrmw xor i64* %136, i64 %135 monotonic + %138 = xor i64 %137, %135 + store i64 %138, i64* @sl, align 8 + %139 = load i8* @uc, align 1 + %140 = zext i8 %139 to i64 + %141 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %142 = atomicrmw xor i64* %141, i64 %140 monotonic + %143 = xor i64 %142, %140 + store i64 %143, i64* @ul, align 8 + %144 = load i8* @uc, align 1 + %145 = atomicrmw and i8* @sc, i8 %144 monotonic + %146 = and i8 %145, %144 + store i8 %146, i8* @sc, align 1 + %147 = load i8* @uc, align 1 + %148 = atomicrmw and i8* @uc, i8 %147 monotonic + %149 = and i8 %148, %147 + store i8 %149, i8* @uc, align 1 + %150 = load i8* @uc, align 1 + %151 = zext i8 %150 to i16 + %152 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %153 = atomicrmw and i16* %152, i16 %151 monotonic + %154 = and i16 %153, %151 + store i16 %154, i16* @ss, align 2 + %155 = load i8* @uc, align 1 + %156 = zext i8 %155 to i16 + %157 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %158 = atomicrmw and i16* %157, i16 %156 monotonic + %159 = and i16 %158, %156 + store i16 %159, i16* @us, align 2 + %160 = load i8* @uc, align 1 + %161 = zext i8 %160 to i32 + %162 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %163 = atomicrmw and i32* %162, i32 %161 monotonic + %164 = and i32 %163, %161 + store i32 %164, i32* @si, align 4 + %165 = load i8* @uc, align 1 + %166 = zext i8 %165 to i32 + %167 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %168 = atomicrmw and i32* %167, i32 %166 monotonic + %169 = and i32 %168, %166 + store i32 %169, i32* @ui, align 4 + %170 = load i8* @uc, align 1 + %171 = zext i8 %170 to i64 + %172 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %173 = atomicrmw and i64* %172, i64 %171 monotonic + %174 = and i64 %173, %171 + store i64 %174, i64* @sl, align 8 + %175 = load i8* @uc, align 1 + %176 = zext i8 %175 to i64 + %177 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %178 = atomicrmw and i64* %177, i64 %176 monotonic + %179 = and i64 %178, %176 + store i64 %179, i64* @ul, align 8 + %180 = load i8* @uc, align 1 + %181 = atomicrmw nand i8* @sc, i8 %180 monotonic + %182 = xor i8 %181, -1 + %183 = and i8 %182, %180 + store i8 %183, i8* @sc, align 1 + %184 = load i8* @uc, align 1 + %185 = atomicrmw nand i8* @uc, i8 %184 monotonic + %186 = xor i8 %185, -1 + %187 = and i8 %186, %184 + store i8 %187, i8* @uc, align 1 + %188 = load i8* @uc, align 1 + %189 = zext i8 %188 to i16 + %190 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %191 = atomicrmw nand i16* %190, i16 %189 monotonic + %192 = xor i16 %191, -1 + %193 = and i16 %192, %189 + store i16 %193, i16* @ss, align 2 + %194 = load i8* @uc, align 1 + %195 = zext i8 %194 to i16 + %196 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %197 = atomicrmw nand i16* %196, i16 %195 monotonic + %198 = xor i16 %197, -1 + %199 = and i16 %198, %195 + store i16 %199, i16* @us, align 2 + %200 = load i8* @uc, align 1 + %201 = zext i8 %200 to i32 + %202 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %203 = atomicrmw nand i32* %202, i32 %201 monotonic + %204 = xor i32 %203, -1 + %205 = and i32 %204, %201 + store i32 %205, i32* @si, align 4 + %206 = load i8* @uc, align 1 + %207 = zext i8 %206 to i32 + %208 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %209 = atomicrmw nand i32* %208, i32 %207 monotonic + %210 = xor i32 %209, -1 + %211 = and i32 %210, %207 + store i32 %211, i32* @ui, align 4 + %212 = load i8* @uc, align 1 + %213 = zext i8 %212 to i64 + %214 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %215 = atomicrmw nand i64* %214, i64 %213 monotonic + %216 = xor i64 %215, -1 + %217 = and i64 %216, %213 + store i64 %217, i64* @sl, align 8 + %218 = load i8* @uc, align 1 + %219 = zext i8 %218 to i64 + %220 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %221 = atomicrmw nand i64* %220, i64 %219 monotonic + %222 = xor i64 %221, -1 + %223 = and i64 %222, %219 + store i64 %223, i64* @ul, align 8 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } define void @test_compare_and_swap() nounwind { entry: - load i8* @uc, align 1 ; :0 [#uses=1] - load i8* @sc, align 1 ; :1 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %0, i8 %1 ) ; :2 [#uses=1] - store i8 %2, i8* @sc, align 1 - load i8* @uc, align 1 ; :3 [#uses=1] - load i8* @sc, align 1 ; :4 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %3, i8 %4 ) ; :5 [#uses=1] - store i8 %5, i8* @uc, align 1 - load i8* @uc, align 1 ; :6 [#uses=1] - zext i8 %6 to i16 ; :7 [#uses=1] - load i8* @sc, align 1 ; :8 [#uses=1] - sext i8 %8 to i16 ; :9 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :10 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %10, i16 %7, i16 %9 ) ; :11 [#uses=1] - store i16 %11, i16* @ss, align 2 - load i8* @uc, align 1 ; :12 [#uses=1] - zext i8 %12 to i16 ; :13 [#uses=1] - load i8* @sc, align 1 ; :14 [#uses=1] - sext i8 %14 to i16 ; :15 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :16 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %16, i16 %13, i16 %15 ) ; :17 [#uses=1] - store i16 %17, i16* @us, align 2 - load i8* @uc, align 1 ; :18 [#uses=1] - zext i8 %18 to i32 ; :19 [#uses=1] - load i8* @sc, align 1 ; :20 [#uses=1] - sext i8 %20 to i32 ; :21 [#uses=1] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :22 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %22, i32 %19, i32 %21 ) ; :23 [#uses=1] - store i32 %23, i32* @si, align 4 - load i8* @uc, align 1 ; :24 [#uses=1] - zext i8 %24 to i32 ; :25 [#uses=1] - load i8* @sc, align 1 ; :26 [#uses=1] - sext i8 %26 to i32 ; :27 [#uses=1] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :28 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %28, i32 %25, i32 %27 ) ; :29 [#uses=1] - store i32 %29, i32* @ui, align 4 - load i8* @uc, align 1 ; :30 [#uses=1] - zext i8 %30 to i64 ; :31 [#uses=1] - load i8* @sc, align 1 ; :32 [#uses=1] - sext i8 %32 to i64 ; :33 [#uses=1] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :34 [#uses=1] - call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %34, i64 %31, i64 %33 ) ; :35 [#uses=1] - store i64 %35, i64* @sl, align 8 - load i8* @uc, align 1 ; :36 [#uses=1] - zext i8 %36 to i64 ; :37 [#uses=1] - load i8* @sc, align 1 ; :38 [#uses=1] - sext i8 %38 to i64 ; :39 [#uses=1] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :40 [#uses=1] - call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %40, i64 %37, i64 %39 ) ; :41 [#uses=1] - store i64 %41, i64* @ul, align 8 - load i8* @uc, align 1 ; :42 [#uses=2] - load i8* @sc, align 1 ; :43 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %42, i8 %43 ) ; :44 [#uses=1] - icmp eq i8 %44, %42 ; :45 [#uses=1] - zext i1 %45 to i8 ; :46 [#uses=1] - zext i8 %46 to i32 ; :47 [#uses=1] - store i32 %47, i32* @ui, align 4 - load i8* @uc, align 1 ; :48 [#uses=2] - load i8* @sc, align 1 ; :49 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %48, i8 %49 ) ; :50 [#uses=1] - icmp eq i8 %50, %48 ; :51 [#uses=1] - zext i1 %51 to i8 ; :52 [#uses=1] - zext i8 %52 to i32 ; :53 [#uses=1] - store i32 %53, i32* @ui, align 4 - load i8* @uc, align 1 ; :54 [#uses=1] - zext i8 %54 to i16 ; :55 [#uses=2] - load i8* @sc, align 1 ; :56 [#uses=1] - sext i8 %56 to i16 ; :57 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :58 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %58, i16 %55, i16 %57 ) ; :59 [#uses=1] - icmp eq i16 %59, %55 ; :60 [#uses=1] - zext i1 %60 to i8 ; :61 [#uses=1] - zext i8 %61 to i32 ; :62 [#uses=1] - store i32 %62, i32* @ui, align 4 - load i8* @uc, align 1 ; :63 [#uses=1] - zext i8 %63 to i16 ; :64 [#uses=2] - load i8* @sc, align 1 ; :65 [#uses=1] - sext i8 %65 to i16 ; :66 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :67 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %67, i16 %64, i16 %66 ) ; :68 [#uses=1] - icmp eq i16 %68, %64 ; :69 [#uses=1] - zext i1 %69 to i8 ; :70 [#uses=1] - zext i8 %70 to i32 ; :71 [#uses=1] - store i32 %71, i32* @ui, align 4 - load i8* @uc, align 1 ; :72 [#uses=1] - zext i8 %72 to i32 ; :73 [#uses=2] - load i8* @sc, align 1 ; :74 [#uses=1] - sext i8 %74 to i32 ; :75 [#uses=1] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :76 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %76, i32 %73, i32 %75 ) ; :77 [#uses=1] - icmp eq i32 %77, %73 ; :78 [#uses=1] - zext i1 %78 to i8 ; :79 [#uses=1] - zext i8 %79 to i32 ; :80 [#uses=1] - store i32 %80, i32* @ui, align 4 - load i8* @uc, align 1 ; :81 [#uses=1] - zext i8 %81 to i32 ; :82 [#uses=2] - load i8* @sc, align 1 ; :83 [#uses=1] - sext i8 %83 to i32 ; :84 [#uses=1] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :85 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %85, i32 %82, i32 %84 ) ; :86 [#uses=1] - icmp eq i32 %86, %82 ; :87 [#uses=1] - zext i1 %87 to i8 ; :88 [#uses=1] - zext i8 %88 to i32 ; :89 [#uses=1] - store i32 %89, i32* @ui, align 4 - load i8* @uc, align 1 ; :90 [#uses=1] - zext i8 %90 to i64 ; :91 [#uses=2] - load i8* @sc, align 1 ; :92 [#uses=1] - sext i8 %92 to i64 ; :93 [#uses=1] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :94 [#uses=1] - call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %94, i64 %91, i64 %93 ) ; :95 [#uses=1] - icmp eq i64 %95, %91 ; :96 [#uses=1] - zext i1 %96 to i8 ; :97 [#uses=1] - zext i8 %97 to i32 ; :98 [#uses=1] - store i32 %98, i32* @ui, align 4 - load i8* @uc, align 1 ; :99 [#uses=1] - zext i8 %99 to i64 ; :100 [#uses=2] - load i8* @sc, align 1 ; :101 [#uses=1] - sext i8 %101 to i64 ; :102 [#uses=1] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :103 [#uses=1] - call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %103, i64 %100, i64 %102 ) ; :104 [#uses=1] - icmp eq i64 %104, %100 ; :105 [#uses=1] - zext i1 %105 to i8 ; :106 [#uses=1] - zext i8 %106 to i32 ; :107 [#uses=1] - store i32 %107, i32* @ui, align 4 - br label %return + %0 = load i8* @uc, align 1 + %1 = load i8* @sc, align 1 + %2 = cmpxchg i8* @sc, i8 %0, i8 %1 monotonic + store i8 %2, i8* @sc, align 1 + %3 = load i8* @uc, align 1 + %4 = load i8* @sc, align 1 + %5 = cmpxchg i8* @uc, i8 %3, i8 %4 monotonic + store i8 %5, i8* @uc, align 1 + %6 = load i8* @uc, align 1 + %7 = zext i8 %6 to i16 + %8 = load i8* @sc, align 1 + %9 = sext i8 %8 to i16 + %10 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %11 = cmpxchg i16* %10, i16 %7, i16 %9 monotonic + store i16 %11, i16* @ss, align 2 + %12 = load i8* @uc, align 1 + %13 = zext i8 %12 to i16 + %14 = load i8* @sc, align 1 + %15 = sext i8 %14 to i16 + %16 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %17 = cmpxchg i16* %16, i16 %13, i16 %15 monotonic + store i16 %17, i16* @us, align 2 + %18 = load i8* @uc, align 1 + %19 = zext i8 %18 to i32 + %20 = load i8* @sc, align 1 + %21 = sext i8 %20 to i32 + %22 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %23 = cmpxchg i32* %22, i32 %19, i32 %21 monotonic + store i32 %23, i32* @si, align 4 + %24 = load i8* @uc, align 1 + %25 = zext i8 %24 to i32 + %26 = load i8* @sc, align 1 + %27 = sext i8 %26 to i32 + %28 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %29 = cmpxchg i32* %28, i32 %25, i32 %27 monotonic + store i32 %29, i32* @ui, align 4 + %30 = load i8* @uc, align 1 + %31 = zext i8 %30 to i64 + %32 = load i8* @sc, align 1 + %33 = sext i8 %32 to i64 + %34 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %35 = cmpxchg i64* %34, i64 %31, i64 %33 monotonic + store i64 %35, i64* @sl, align 8 + %36 = load i8* @uc, align 1 + %37 = zext i8 %36 to i64 + %38 = load i8* @sc, align 1 + %39 = sext i8 %38 to i64 + %40 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %41 = cmpxchg i64* %40, i64 %37, i64 %39 monotonic + store i64 %41, i64* @ul, align 8 + %42 = load i8* @uc, align 1 + %43 = load i8* @sc, align 1 + %44 = cmpxchg i8* @sc, i8 %42, i8 %43 monotonic + %45 = icmp eq i8 %44, %42 + %46 = zext i1 %45 to i8 + %47 = zext i8 %46 to i32 + store i32 %47, i32* @ui, align 4 + %48 = load i8* @uc, align 1 + %49 = load i8* @sc, align 1 + %50 = cmpxchg i8* @uc, i8 %48, i8 %49 monotonic + %51 = icmp eq i8 %50, %48 + %52 = zext i1 %51 to i8 + %53 = zext i8 %52 to i32 + store i32 %53, i32* @ui, align 4 + %54 = load i8* @uc, align 1 + %55 = zext i8 %54 to i16 + %56 = load i8* @sc, align 1 + %57 = sext i8 %56 to i16 + %58 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %59 = cmpxchg i16* %58, i16 %55, i16 %57 monotonic + %60 = icmp eq i16 %59, %55 + %61 = zext i1 %60 to i8 + %62 = zext i8 %61 to i32 + store i32 %62, i32* @ui, align 4 + %63 = load i8* @uc, align 1 + %64 = zext i8 %63 to i16 + %65 = load i8* @sc, align 1 + %66 = sext i8 %65 to i16 + %67 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %68 = cmpxchg i16* %67, i16 %64, i16 %66 monotonic + %69 = icmp eq i16 %68, %64 + %70 = zext i1 %69 to i8 + %71 = zext i8 %70 to i32 + store i32 %71, i32* @ui, align 4 + %72 = load i8* @uc, align 1 + %73 = zext i8 %72 to i32 + %74 = load i8* @sc, align 1 + %75 = sext i8 %74 to i32 + %76 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %77 = cmpxchg i32* %76, i32 %73, i32 %75 monotonic + %78 = icmp eq i32 %77, %73 + %79 = zext i1 %78 to i8 + %80 = zext i8 %79 to i32 + store i32 %80, i32* @ui, align 4 + %81 = load i8* @uc, align 1 + %82 = zext i8 %81 to i32 + %83 = load i8* @sc, align 1 + %84 = sext i8 %83 to i32 + %85 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %86 = cmpxchg i32* %85, i32 %82, i32 %84 monotonic + %87 = icmp eq i32 %86, %82 + %88 = zext i1 %87 to i8 + %89 = zext i8 %88 to i32 + store i32 %89, i32* @ui, align 4 + %90 = load i8* @uc, align 1 + %91 = zext i8 %90 to i64 + %92 = load i8* @sc, align 1 + %93 = sext i8 %92 to i64 + %94 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %95 = cmpxchg i64* %94, i64 %91, i64 %93 monotonic + %96 = icmp eq i64 %95, %91 + %97 = zext i1 %96 to i8 + %98 = zext i8 %97 to i32 + store i32 %98, i32* @ui, align 4 + %99 = load i8* @uc, align 1 + %100 = zext i8 %99 to i64 + %101 = load i8* @sc, align 1 + %102 = sext i8 %101 to i64 + %103 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %104 = cmpxchg i64* %103, i64 %100, i64 %102 monotonic + %105 = icmp eq i64 %104, %100 + %106 = zext i1 %105 to i8 + %107 = zext i8 %106 to i32 + store i32 %107, i32* @ui, align 4 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } -declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind - -declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind - -declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind - -declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64*, i64, i64) nounwind - define void @test_lock() nounwind { entry: - call i8 @llvm.atomic.swap.i8.p0i8( i8* @sc, i8 1 ) ; :0 [#uses=1] - store i8 %0, i8* @sc, align 1 - call i8 @llvm.atomic.swap.i8.p0i8( i8* @uc, i8 1 ) ; :1 [#uses=1] - store i8 %1, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.swap.i16.p0i16( i16* %2, i16 1 ) ; :3 [#uses=1] - store i16 %3, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.swap.i16.p0i16( i16* %4, i16 1 ) ; :5 [#uses=1] - store i16 %5, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %6, i32 1 ) ; :7 [#uses=1] - store i32 %7, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %8, i32 1 ) ; :9 [#uses=1] - store i32 %9, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :10 [#uses=1] - call i64 @llvm.atomic.swap.i64.p0i64( i64* %10, i64 1 ) ; :11 [#uses=1] - store i64 %11, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :12 [#uses=1] - call i64 @llvm.atomic.swap.i64.p0i64( i64* %12, i64 1 ) ; :13 [#uses=1] - store i64 %13, i64* @ul, align 8 - call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true, i1 false ) - volatile store i8 0, i8* @sc, align 1 - volatile store i8 0, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :14 [#uses=1] - volatile store i16 0, i16* %14, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :15 [#uses=1] - volatile store i16 0, i16* %15, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :16 [#uses=1] - volatile store i32 0, i32* %16, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :17 [#uses=1] - volatile store i32 0, i32* %17, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :18 [#uses=1] - volatile store i64 0, i64* %18, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :19 [#uses=1] - volatile store i64 0, i64* %19, align 8 - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :20 [#uses=1] - volatile store i64 0, i64* %20, align 8 - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :21 [#uses=1] - volatile store i64 0, i64* %21, align 8 - br label %return + %0 = atomicrmw xchg i8* @sc, i8 1 monotonic + store i8 %0, i8* @sc, align 1 + %1 = atomicrmw xchg i8* @uc, i8 1 monotonic + store i8 %1, i8* @uc, align 1 + %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %3 = atomicrmw xchg i16* %2, i16 1 monotonic + store i16 %3, i16* @ss, align 2 + %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %5 = atomicrmw xchg i16* %4, i16 1 monotonic + store i16 %5, i16* @us, align 2 + %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %7 = atomicrmw xchg i32* %6, i32 1 monotonic + store i32 %7, i32* @si, align 4 + %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %9 = atomicrmw xchg i32* %8, i32 1 monotonic + store i32 %9, i32* @ui, align 4 + %10 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %11 = atomicrmw xchg i64* %10, i64 1 monotonic + store i64 %11, i64* @sl, align 8 + %12 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %13 = atomicrmw xchg i64* %12, i64 1 monotonic + store i64 %13, i64* @ul, align 8 + fence seq_cst + store volatile i8 0, i8* @sc, align 1 + store volatile i8 0, i8* @uc, align 1 + %14 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + store volatile i16 0, i16* %14, align 2 + %15 = bitcast i8* bitcast (i16* @us to i8*) to i16* + store volatile i16 0, i16* %15, align 2 + %16 = bitcast i8* bitcast (i32* @si to i8*) to i32* + store volatile i32 0, i32* %16, align 4 + %17 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + store volatile i32 0, i32* %17, align 4 + %18 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + store volatile i64 0, i64* %18, align 8 + %19 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + store volatile i64 0, i64* %19, align 8 + %20 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + store volatile i64 0, i64* %20, align 8 + %21 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + store volatile i64 0, i64* %21, align 8 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } - -declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.swap.i64.p0i64(i64*, i64) nounwind - -declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind Modified: llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll?rev=140566&r1=140565&r2=140566&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/atomic-1.ll Mon Sep 26 16:30:17 2011 @@ -3,7 +3,7 @@ define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { ; CHECK: exchange_and_add: ; CHECK: lwarx - %tmp = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %mem, i32 %val) + %tmp = atomicrmw add i32* %mem, i32 %val monotonic ; CHECK: stwcx. ret i32 %tmp } @@ -11,7 +11,7 @@ define i32 @exchange_and_cmp(i32* %mem) nounwind { ; CHECK: exchange_and_cmp: ; CHECK: lwarx - %tmp = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %mem, i32 0, i32 1) + %tmp = cmpxchg i32* %mem, i32 0, i32 1 monotonic ; CHECK: stwcx. ; CHECK: stwcx. ret i32 %tmp @@ -20,13 +20,7 @@ define i32 @exchange(i32* %mem, i32 %val) nounwind { ; CHECK: exchange: ; CHECK: lwarx - %tmp = call i32 @llvm.atomic.swap.i32.p0i32(i32* %mem, i32 1) + %tmp = atomicrmw xchg i32* %mem, i32 1 monotonic ; CHECK: stwcx. ret i32 %tmp } - -declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind - -declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* nocapture, i32, i32) nounwind - -declare i32 @llvm.atomic.swap.i32.p0i32(i32* nocapture, i32) nounwind Modified: llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll?rev=140566&r1=140565&r2=140566&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll Mon Sep 26 16:30:17 2011 @@ -3,7 +3,7 @@ define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { ; CHECK: exchange_and_add: ; CHECK: ldarx - %tmp = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %mem, i64 %val) + %tmp = atomicrmw add i64* %mem, i64 %val monotonic ; CHECK: stdcx. ret i64 %tmp } @@ -11,7 +11,7 @@ define i64 @exchange_and_cmp(i64* %mem) nounwind { ; CHECK: exchange_and_cmp: ; CHECK: ldarx - %tmp = call i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* %mem, i64 0, i64 1) + %tmp = cmpxchg i64* %mem, i64 0, i64 1 monotonic ; CHECK: stdcx. ; CHECK: stdcx. ret i64 %tmp @@ -20,13 +20,7 @@ define i64 @exchange(i64* %mem, i64 %val) nounwind { ; CHECK: exchange: ; CHECK: ldarx - %tmp = call i64 @llvm.atomic.swap.i64.p0i64(i64* %mem, i64 1) + %tmp = atomicrmw xchg i64* %mem, i64 1 monotonic ; CHECK: stdcx. ret i64 %tmp } - -declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind - -declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* nocapture, i64, i64) nounwind - -declare i64 @llvm.atomic.swap.i64.p0i64(i64* nocapture, i64) nounwind From eli.friedman at gmail.com Mon Sep 26 16:36:10 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 26 Sep 2011 21:36:10 -0000 Subject: [llvm-commits] [llvm] r140567 - in /llvm/trunk/test/CodeGen: Thumb/barrier.ll Thumb2/thumb2-bcc.ll Thumb2/thumb2-branch.ll Message-ID: <20110926213610.5EF472A6C12C@llvm.org> Author: efriedma Date: Mon Sep 26 16:36:10 2011 New Revision: 140567 URL: http://llvm.org/viewvc/llvm-project?rev=140567&view=rev Log: Convert more tests to new atomic instructions. Modified: llvm/trunk/test/CodeGen/Thumb/barrier.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll Modified: llvm/trunk/test/CodeGen/Thumb/barrier.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/barrier.ll?rev=140567&r1=140566&r2=140567&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/barrier.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/barrier.ll Mon Sep 26 16:36:10 2011 @@ -2,24 +2,12 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=-db | FileCheck %s -check-prefix=V6 ; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=V6M -declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1) - define void @t1() { ; V6: t1: ; V6: blx {{_*}}sync_synchronize ; V6M: t1: -; V6M: dmb st - call void @llvm.memory.barrier(i1 false, i1 false, i1 false, i1 true, i1 true) - ret void -} - -define void @t2() { -; V6: t2: -; V6: blx {{_*}}sync_synchronize - -; V6M: t2: ; V6M: dmb ish - call void @llvm.memory.barrier(i1 true, i1 false, i1 false, i1 true, i1 false) + fence seq_cst ret void } Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll?rev=140567&r1=140566&r2=140567&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-bcc.ll Mon Sep 26 16:36:10 2011 @@ -6,20 +6,18 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) { ; CHECK: t1: ; CHECK: cbz - %tmp2 = icmp eq i32 %a, 0 - br i1 %tmp2, label %cond_false, label %cond_true + %tmp2 = icmp eq i32 %a, 0 + br i1 %tmp2, label %cond_false, label %cond_true cond_true: - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) - %tmp5 = add i32 %b, 1 - %tmp6 = and i32 %tmp5, %c - ret i32 %tmp6 + fence seq_cst + %tmp5 = add i32 %b, 1 + %tmp6 = and i32 %tmp5, %c + ret i32 %tmp6 cond_false: - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) - %tmp7 = add i32 %b, -1 - %tmp8 = xor i32 %tmp7, %c - ret i32 %tmp8 + fence seq_cst + %tmp7 = add i32 %b, -1 + %tmp8 = xor i32 %tmp7, %c + ret i32 %tmp8 } - -declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll?rev=140567&r1=140566&r2=140567&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-branch.ll Mon Sep 26 16:36:10 2011 @@ -11,12 +11,12 @@ br i1 %tmp, label %cond_true, label %return cond_true: ; preds = %entry - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) + fence seq_cst store i32 0, i32* %v ret i32 0 return: ; preds = %entry - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) + fence seq_cst ret i32 1 } @@ -28,12 +28,12 @@ br i1 %tmp, label %cond_true, label %return cond_true: ; preds = %entry - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) + fence seq_cst store i32 0, i32* %v ret i32 0 return: ; preds = %entry - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) + fence seq_cst ret i32 1 } @@ -45,12 +45,12 @@ br i1 %tmp, label %cond_true, label %return cond_true: ; preds = %entry - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) + fence seq_cst store i32 0, i32* %v ret i32 0 return: ; preds = %entry - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) + fence seq_cst ret i32 1 } @@ -62,13 +62,11 @@ br i1 %tmp, label %return, label %cond_true cond_true: ; preds = %entry - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) + fence seq_cst store i32 0, i32* %v ret i32 0 return: ; preds = %entry - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) + fence seq_cst ret i32 1 } - -declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind From ahatanak at gmail.com Mon Sep 26 16:37:50 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Mon, 26 Sep 2011 21:37:50 -0000 Subject: [llvm-commits] [llvm] r140568 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110926213750.C58262A6C12C@llvm.org> Author: ahatanak Date: Mon Sep 26 16:37:50 2011 New Revision: 140568 URL: http://llvm.org/viewvc/llvm-project?rev=140568&view=rev Log: In single float mode, double precision FP arguments are passed in integer registers, so there is no need to check here. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=140568&r1=140567&r2=140568&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Sep 26 16:37:50 2011 @@ -2267,10 +2267,9 @@ RC = Mips::CPU64RegsRegisterClass; else if (RegVT == MVT::f32) RC = Mips::FGR32RegisterClass; - else if (RegVT == MVT::f64) { - if (!Subtarget->isSingleFloat()) - RC = Mips::AFGR64RegisterClass; - } else + else if (RegVT == MVT::f64) + RC = Mips::AFGR64RegisterClass; + else llvm_unreachable("RegVT not supported by FormalArguments Lowering"); // Transform the arguments stored on From ahatanak at gmail.com Mon Sep 26 16:47:02 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Mon, 26 Sep 2011 21:47:02 -0000 Subject: [llvm-commits] [llvm] r140569 - in /llvm/trunk/lib/Target/Mips: MipsISelLowering.cpp MipsISelLowering.h Message-ID: <20110926214702.5132C2A6C12C@llvm.org> Author: ahatanak Date: Mon Sep 26 16:47:02 2011 New Revision: 140569 URL: http://llvm.org/viewvc/llvm-project?rev=140569&view=rev Log: Define variable HasMips64 in MipsTargetLowering. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.h Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=140569&r1=140568&r2=140569&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Sep 26 16:47:02 2011 @@ -82,9 +82,9 @@ MipsTargetLowering:: MipsTargetLowering(MipsTargetMachine &TM) - : TargetLowering(TM, new MipsTargetObjectFile()) { - Subtarget = &TM.getSubtarget(); - bool HasMips64 = Subtarget->hasMips64(); + : TargetLowering(TM, new MipsTargetObjectFile()), + Subtarget(&TM.getSubtarget()), + HasMips64(Subtarget->hasMips64()) { // Mips does not have i1 type, so use i32 for // setcc operations results (slt, sgt, ...). Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=140569&r1=140568&r2=140569&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Mon Sep 26 16:47:02 2011 @@ -114,7 +114,8 @@ private: // Subtarget Info const MipsSubtarget *Subtarget; - + + bool HasMips64; // Lower Operand helpers SDValue LowerCallResult(SDValue Chain, SDValue InFlag, From ahatanak at gmail.com Mon Sep 26 16:55:18 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Mon, 26 Sep 2011 21:55:18 -0000 Subject: [llvm-commits] [llvm] r140570 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110926215518.100092A6C12C@llvm.org> Author: ahatanak Date: Mon Sep 26 16:55:17 2011 New Revision: 140570 URL: http://llvm.org/viewvc/llvm-project?rev=140570&view=rev Log: Set register class of a register according to value of HasMips64. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=140570&r1=140569&r2=140570&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Sep 26 16:55:17 2011 @@ -2268,7 +2268,7 @@ else if (RegVT == MVT::f32) RC = Mips::FGR32RegisterClass; else if (RegVT == MVT::f64) - RC = Mips::AFGR64RegisterClass; + RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass; else llvm_unreachable("RegVT not supported by FormalArguments Lowering"); From resistor at mac.com Mon Sep 26 17:13:55 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 26 Sep 2011 22:13:55 -0000 Subject: [llvm-commits] [llvm] r140572 - /llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Message-ID: <20110926221355.8FB5B2A6C12C@llvm.org> Author: resistor Date: Mon Sep 26 17:13:55 2011 New Revision: 140572 URL: http://llvm.org/viewvc/llvm-project?rev=140572&view=rev Log: Remove incorrect testcases. Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=140572&r1=140571&r2=140572&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Mon Sep 26 17:13:55 2011 @@ -2070,13 +2070,11 @@ ssat r8, #1, r10 ssat r8, #1, r10, lsl #0 ssat r8, #1, r10, lsl #31 - ssat r8, #1, r10, asr #32 ssat r8, #1, r10, asr #1 @ CHECK: ssat r8, #1, r10 @ encoding: [0x0a,0xf3,0x00,0x08] @ CHECK: ssat r8, #1, r10 @ encoding: [0x0a,0xf3,0x00,0x08] @ CHECK: ssat r8, #1, r10, lsl #31 @ encoding: [0x0a,0xf3,0xc0,0x78] -@ CHECK: ssat r8, #1, r10, asr #32 @ encoding: [0x2a,0xf3,0x00,0x08] @ CHECK: ssat r8, #1, r10, asr #1 @ encoding: [0x2a,0xf3,0x40,0x08] @@ -2898,13 +2896,11 @@ usat r8, #1, r10 usat r8, #4, r10, lsl #0 usat r8, #5, r10, lsl #31 - usat r8, #31, r10, asr #32 usat r8, #16, r10, asr #1 @ CHECK: usat r8, #1, r10 @ encoding: [0x8a,0xf3,0x01,0x08] @ CHECK: usat r8, #4, r10 @ encoding: [0x8a,0xf3,0x04,0x08] @ CHECK: usat r8, #5, r10, lsl #31 @ encoding: [0x8a,0xf3,0xc5,0x78] -@ CHECK: usat r8, #31, r10, asr #32 @ encoding: [0xaa,0xf3,0x1f,0x08] @ CHECK: usat r8, #16, r10, asr #1 @ encoding: [0xaa,0xf3,0x50,0x08] From bob.wilson at apple.com Mon Sep 26 17:30:57 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 26 Sep 2011 22:30:57 -0000 Subject: [llvm-commits] [llvm] r140573 - /llvm/trunk/utils/buildit/build_llvm Message-ID: <20110926223057.A062D2A6C130@llvm.org> Author: bwilson Date: Mon Sep 26 17:30:57 2011 New Revision: 140573 URL: http://llvm.org/viewvc/llvm-project?rev=140573&view=rev Log: Remove old hack for compiling with gcc-4.0. Modified: llvm/trunk/utils/buildit/build_llvm Modified: llvm/trunk/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=140573&r1=140572&r2=140573&view=diff ============================================================================== --- llvm/trunk/utils/buildit/build_llvm (original) +++ llvm/trunk/utils/buildit/build_llvm Mon Sep 26 17:30:57 2011 @@ -142,32 +142,15 @@ LLVM_VERSION="$LLVM_SUBMIT_VERSION-$LLVM_SUBMIT_SUBVERSION" fi -GCC_VER=`cc --version 2>/dev/null | sed 1q` - -if echo "$GCC_VER" | grep GCC > /dev/null; then - GCC_VER=`echo $GCC_VER | sed -e 's/.*(GCC) \([0-9.][0-9.]*\).*/\1/'` - MAJ_VER=`echo $GCC_VER | sed 's/\..*//'` - MIN_VER=`echo $GCC_VER | sed 's/[^.]*\.\([0-9]*\).*/\1/'` -fi - -JOBS_FLAG="" - -# Note: If compiling with GCC 4.0, don't pass the -jN flag. Building universal -# already has parallelism and we don't want to make the builders hit swap by -# firing off too many gccs at the same time. -if [ "x$MAJ_VER" != "x4" -o "x$MIN_VER" != "x0" ]; then - # Figure out how many make processes to run. - SYSCTL=`sysctl -n hw.activecpu` - - # sysctl -n hw.* does not work when invoked via B&I chroot /BuildRoot. - # Builders can default to 2, since even if they are single processor, - # nothing else is running on the machine. - if [ -z "$SYSCTL" ]; then - SYSCTL=2 - fi - - JOBS_FLAG="-j $SYSCTL" +# Figure out how many make processes to run. +SYSCTL=`sysctl -n hw.activecpu` +# sysctl -n hw.* does not work when invoked via B&I chroot /BuildRoot. +# Builders can default to 2, since even if they are single processor, +# nothing else is running on the machine. +if [ -z "$SYSCTL" ]; then + SYSCTL=2 fi +JOBS_FLAG="-j $SYSCTL" make $JOBS_FLAG $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$HOSTS" \ UNIVERSAL_SDK_PATH=$SDKROOT \ From resistor at mac.com Mon Sep 26 18:08:34 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 26 Sep 2011 23:08:34 -0000 Subject: [llvm-commits] [llvm] r140579 - /llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt Message-ID: <20110926230835.012B32A6C12C@llvm.org> Author: resistor Date: Mon Sep 26 18:08:34 2011 New Revision: 140579 URL: http://llvm.org/viewvc/llvm-project?rev=140579&view=rev Log: Fix an incorrect decoder test. Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt?rev=140579&r1=140578&r2=140579&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb2.txt Mon Sep 26 18:08:34 2011 @@ -1775,9 +1775,9 @@ #------------------------------------------------------------------------------ # SSAT #------------------------------------------------------------------------------ -# CHECK: ssat r9, #30, r0, asr #32 +# CHECK: ssat r9, #30, r0, asr #2 -0x20 0xf3 0x1d 0x09 +0x20 0xf3 0x9d 0x09 #------------------------------------------------------------------------------ # STR (immediate) From eli.friedman at gmail.com Mon Sep 26 18:12:20 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 26 Sep 2011 16:12:20 -0700 Subject: [llvm-commits] [llvm] r140560 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/Disassembler/ARMDisassembler.cpp utils/TableGen/EDEmitter.cpp In-Reply-To: <20110926210623.12A7A2A6C12C@llvm.org> References: <20110926210623.12A7A2A6C12C@llvm.org> Message-ID: On Mon, Sep 26, 2011 at 2:06 PM, Owen Anderson wrote: > Author: resistor > Date: Mon Sep 26 16:06:22 2011 > New Revision: 140560 > > URL: http://llvm.org/viewvc/llvm-project?rev=140560&view=rev > Log: > ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. > > Modified: > ? ?llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > ? ?llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > ? ?llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp > ? ?llvm/trunk/utils/TableGen/EDEmitter.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=140560&r1=140559&r2=140560&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Sep 26 16:06:22 2011 > @@ -28,6 +28,18 @@ > ? let ParserMatchClass = it_mask_asmoperand; > ?} > > +// t2_shift_imm: An integer that encodes a shift amount and the type of shift > +// (asr or lsl). The 6-bit immediate encodes as: > +// ? ?{5} ? ? 0 ==> lsl > +// ? ? ? ? ? ?1 ? ? asr > +// ? ?{4-0} ? imm5 shift amount. > +// ? ? ? ? ? ?asr #32 not allowed > +def t2_shift_imm : Operand { > + ?let PrintMethod = "printShiftImmOperand"; > + ?let ParserMatchClass = ShifterImmAsmOperand; > + ?let DecoderMethod = "DecodeT2ShifterImmOperand"; > +} > + > ?// Shifted operands. No register controlled shifts for Thumb2. > ?// Note: We do not support rrx shifted operands yet. > ?def t2_so_reg : Operand, ? ?// reg imm > @@ -2023,7 +2035,8 @@ > ?} > > ?def t2SSAT: T2SatI< > - ? ? ? ? ? ? ?(outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh), > + ? ? ? ? ? ? ?(outs rGPR:$Rd), > + ? ? ? ? ? ? ?(ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), > ? ? ? ? ? ? ? NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { > ? let Inst{31-27} = 0b11110; > ? let Inst{25-22} = 0b1100; > @@ -2047,7 +2060,8 @@ > ?} > > ?def t2USAT: T2SatI< > - ? ? ? ? ? ? ? (outs rGPR:$Rd), (ins imm0_31:$sat_imm, rGPR:$Rn, shift_imm:$sh), > + ? ? ? ? ? ? ? (outs rGPR:$Rd), > + ? ? ? ? ? ? ? (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), > ? ? ? ? ? ? ? ? NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { > ? let Inst{31-27} = 0b11110; > ? let Inst{25-22} = 0b1110; > @@ -3928,6 +3942,8 @@ > ? ? ? ? ? ? ? ? (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; > ?def : t2InstAlias<"sxth${p} $Rd, $Rm", > ? ? ? ? ? ? ? ? (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; > +def : t2InstAlias<"sxth${p} $Rd, $Rm", > + ? ? ? ? ? ? ? ?(t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; Is there some non-obvious difference between this pattern and the pattern above it? -Eli From atrick at apple.com Mon Sep 26 18:11:04 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 26 Sep 2011 23:11:04 -0000 Subject: [llvm-commits] [llvm] r140580 - /llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <20110926231104.5E1B62A6C12C@llvm.org> Author: atrick Date: Mon Sep 26 18:11:04 2011 New Revision: 140580 URL: http://llvm.org/viewvc/llvm-project?rev=140580&view=rev Log: LSR cost metric minor fix and verification. The minor bug heuristic was noticed by inspection. I added the isLoser/isValid helpers because they will become more important with subsequent checkins. Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=140580&r1=140579&r2=140580&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Mon Sep 26 18:11:04 2011 @@ -670,6 +670,21 @@ void Loose(); +#ifndef NDEBUG + // Once any of the metrics loses, they must all remain losers. + bool isValid() { + return ((NumRegs | AddRecCost | NumIVMuls | NumBaseAdds + | ImmCost | SetupCost) != ~0u) + || ((NumRegs & AddRecCost & NumIVMuls & NumBaseAdds + & ImmCost & SetupCost) == ~0u); + } +#endif + + bool isLoser() { + assert(isValid() && "invalid cost"); + return NumRegs == ~0u; + } + void RateFormula(const Formula &F, SmallPtrSet &Regs, const DenseSet &VisitedRegs, @@ -710,19 +725,22 @@ (!AR->getLoop()->contains(L) && DT.dominates(L->getHeader(), AR->getLoop()->getHeader()))) { for (BasicBlock::iterator I = AR->getLoop()->getHeader()->begin(); - PHINode *PN = dyn_cast(I); ++I) + PHINode *PN = dyn_cast(I); ++I) { if (SE.isSCEVable(PN->getType()) && (SE.getEffectiveSCEVType(PN->getType()) == SE.getEffectiveSCEVType(AR->getType())) && SE.getSCEV(PN) == AR) return; - + } // If this isn't one of the addrecs that the loop already has, it // would require a costly new phi and add. TODO: This isn't // precisely modeled right now. ++NumBaseAdds; - if (!Regs.count(AR->getStart())) + if (!Regs.count(AR->getStart())) { RateRegister(AR->getStart(), Regs, L, SE, DT); + if (isLoser()) + return; + } } // Add the step value register, if it needs one. @@ -769,6 +787,8 @@ return; } RatePrimaryRegister(ScaledReg, Regs, L, SE, DT); + if (isLoser()) + return; } for (SmallVectorImpl::const_iterator I = F.BaseRegs.begin(), E = F.BaseRegs.end(); I != E; ++I) { @@ -778,6 +798,8 @@ return; } RatePrimaryRegister(BaseReg, Regs, L, SE, DT); + if (isLoser()) + return; } // Determine how many (unfolded) adds we'll need inside the loop. @@ -795,6 +817,7 @@ else if (Offset != 0) ImmCost += APInt(64, Offset, true).getMinSignedBits(); } + assert(isValid() && "invalid cost"); } /// Loose - Set this cost to a losing value. From resistor at mac.com Mon Sep 26 18:14:52 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 26 Sep 2011 16:14:52 -0700 Subject: [llvm-commits] [llvm] r140560 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/Disassembler/ARMDisassembler.cpp utils/TableGen/EDEmitter.cpp In-Reply-To: References: <20110926210623.12A7A2A6C12C@llvm.org> Message-ID: <54BB03D0-8BFE-4401-907C-51C1411E999D@mac.com> On Sep 26, 2011, at 4:12 PM, Eli Friedman wrote: >> +def : t2InstAlias<"sxth${p} $Rd, $Rm", >> + (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; > > Is there some non-obvious difference between this pattern and the > pattern above it? Nope, that would be an accidental commit. --Owen -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110926/d72ce9eb/attachment.html From resistor at mac.com Mon Sep 26 18:14:02 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 26 Sep 2011 23:14:02 -0000 Subject: [llvm-commits] [llvm] r140581 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20110926231402.6D5302A6C12C@llvm.org> Author: resistor Date: Mon Sep 26 18:14:02 2011 New Revision: 140581 URL: http://llvm.org/viewvc/llvm-project?rev=140581&view=rev Log: Remove extraneous commit garbage. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=140581&r1=140580&r2=140581&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Sep 26 18:14:02 2011 @@ -3942,8 +3942,6 @@ (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; def : t2InstAlias<"sxth${p} $Rd, $Rm", (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; -def : t2InstAlias<"sxth${p} $Rd, $Rm", - (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm", (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; From eli.friedman at gmail.com Mon Sep 26 18:15:10 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 26 Sep 2011 23:15:10 -0000 Subject: [llvm-commits] [llvm] r140582 - in /llvm/trunk/test/CodeGen/X86: 2008-08-19-SubAndFetch.ll 2008-10-02-Atomics32-2.ll 2009-10-19-atomic-cmp-eflags.ll 2010-01-08-Atomic64Bug.ll 2010-10-08-cmpxchg8b.ll atomic-or.ll atomic_add.ll coalescer-remat.ll fast-isel-atomic.ll lock-inst-encoding.ll Message-ID: <20110926231510.3F3812A6C12C@llvm.org> Author: efriedma Date: Mon Sep 26 18:15:09 2011 New Revision: 140582 URL: http://llvm.org/viewvc/llvm-project?rev=140582&view=rev Log: Convert a bunch more tests over to the new atomic instructions. Removed: llvm/trunk/test/CodeGen/X86/2008-10-02-Atomics32-2.ll Modified: llvm/trunk/test/CodeGen/X86/2008-08-19-SubAndFetch.ll llvm/trunk/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll llvm/trunk/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll llvm/trunk/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll llvm/trunk/test/CodeGen/X86/atomic-or.ll llvm/trunk/test/CodeGen/X86/atomic_add.ll llvm/trunk/test/CodeGen/X86/coalescer-remat.ll llvm/trunk/test/CodeGen/X86/fast-isel-atomic.ll llvm/trunk/test/CodeGen/X86/lock-inst-encoding.ll Modified: llvm/trunk/test/CodeGen/X86/2008-08-19-SubAndFetch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-19-SubAndFetch.ll?rev=140582&r1=140581&r2=140582&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-08-19-SubAndFetch.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-08-19-SubAndFetch.ll Mon Sep 26 18:15:09 2011 @@ -7,8 +7,6 @@ ; CHECK: main: ; CHECK: lock ; CHECK: decq - tail call i64 @llvm.atomic.load.sub.i64.p0i64( i64* @var, i64 1 ) ; :0 [#uses=0] + atomicrmw sub i64* @var, i64 1 monotonic unreachable } - -declare i64 @llvm.atomic.load.sub.i64.p0i64(i64*, i64) nounwind Removed: llvm/trunk/test/CodeGen/X86/2008-10-02-Atomics32-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-10-02-Atomics32-2.ll?rev=140581&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-10-02-Atomics32-2.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-10-02-Atomics32-2.ll (removed) @@ -1,969 +0,0 @@ -; RUN: llc < %s -march=x86 > %t -;; This version includes 64-bit version of binary operators (in 32-bit mode). -;; Swap, cmp-and-swap not supported yet in this mode. -; ModuleID = 'Atomics.c' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -target triple = "i386-apple-darwin8" - at sc = common global i8 0 ; [#uses=52] - at uc = common global i8 0 ; [#uses=112] - at ss = common global i16 0 ; [#uses=15] - at us = common global i16 0 ; [#uses=15] - at si = common global i32 0 ; [#uses=15] - at ui = common global i32 0 ; [#uses=23] - at sl = common global i32 0 ; [#uses=15] - at ul = common global i32 0 ; [#uses=15] - at sll = common global i64 0, align 8 ; [#uses=13] - at ull = common global i64 0, align 8 ; [#uses=13] - -define void @test_op_ignore() nounwind { -entry: - %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @sc, i8 1) ; [#uses=0] - %1 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @uc, i8 1) ; [#uses=0] - %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %3 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %2, i16 1) ; [#uses=0] - %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %5 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %4, i16 1) ; [#uses=0] - %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %7 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %6, i32 1) ; [#uses=0] - %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %9 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %8, i32 1) ; [#uses=0] - %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %11 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %10, i32 1) ; [#uses=0] - %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %13 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %12, i32 1) ; [#uses=0] - %14 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %15 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %14, i64 1) ; [#uses=0] - %16 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %17 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %16, i64 1) ; [#uses=0] - %18 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @sc, i8 1) ; [#uses=0] - %19 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @uc, i8 1) ; [#uses=0] - %20 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %21 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %20, i16 1) ; [#uses=0] - %22 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %23 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %22, i16 1) ; [#uses=0] - %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %25 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %24, i32 1) ; [#uses=0] - %26 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %27 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %26, i32 1) ; [#uses=0] - %28 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %29 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %28, i32 1) ; [#uses=0] - %30 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %31 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %30, i32 1) ; [#uses=0] - %32 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %33 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %32, i64 1) ; [#uses=0] - %34 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %35 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %34, i64 1) ; [#uses=0] - %36 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @sc, i8 1) ; [#uses=0] - %37 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @uc, i8 1) ; [#uses=0] - %38 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %39 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %38, i16 1) ; [#uses=0] - %40 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %41 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %40, i16 1) ; [#uses=0] - %42 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %43 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %42, i32 1) ; [#uses=0] - %44 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %45 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %44, i32 1) ; [#uses=0] - %46 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %47 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %46, i32 1) ; [#uses=0] - %48 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %49 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %48, i32 1) ; [#uses=0] - %50 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %51 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %50, i64 1) ; [#uses=0] - %52 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %53 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %52, i64 1) ; [#uses=0] - %54 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @sc, i8 1) ; [#uses=0] - %55 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @uc, i8 1) ; [#uses=0] - %56 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %57 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %56, i16 1) ; [#uses=0] - %58 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %59 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %58, i16 1) ; [#uses=0] - %60 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %61 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %60, i32 1) ; [#uses=0] - %62 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %63 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %62, i32 1) ; [#uses=0] - %64 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %65 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %64, i32 1) ; [#uses=0] - %66 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %67 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %66, i32 1) ; [#uses=0] - %68 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %69 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %68, i64 1) ; [#uses=0] - %70 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %71 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %70, i64 1) ; [#uses=0] - %72 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @sc, i8 1) ; [#uses=0] - %73 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @uc, i8 1) ; [#uses=0] - %74 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %75 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %74, i16 1) ; [#uses=0] - %76 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %77 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %76, i16 1) ; [#uses=0] - %78 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %79 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %78, i32 1) ; [#uses=0] - %80 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %81 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %80, i32 1) ; [#uses=0] - %82 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %83 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %82, i32 1) ; [#uses=0] - %84 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %85 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %84, i32 1) ; [#uses=0] - %86 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %87 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %86, i64 1) ; [#uses=0] - %88 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %89 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %88, i64 1) ; [#uses=0] - %90 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @sc, i8 1) ; [#uses=0] - %91 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @uc, i8 1) ; [#uses=0] - %92 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %93 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %92, i16 1) ; [#uses=0] - %94 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %95 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %94, i16 1) ; [#uses=0] - %96 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %97 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %96, i32 1) ; [#uses=0] - %98 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %99 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %98, i32 1) ; [#uses=0] - %100 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %101 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %100, i32 1) ; [#uses=0] - %102 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %103 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %102, i32 1) ; [#uses=0] - %104 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %105 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %104, i64 1) ; [#uses=0] - %106 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %107 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %106, i64 1) ; [#uses=0] - br label %return - -return: ; preds = %entry - ret void -} - -declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.add.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.sub.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.or.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.xor.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.and.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.nand.i64.p0i64(i64*, i64) nounwind - -define void @test_fetch_and_op() nounwind { -entry: - %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @sc, i8 11) ; [#uses=1] - store i8 %0, i8* @sc, align 1 - %1 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @uc, i8 11) ; [#uses=1] - store i8 %1, i8* @uc, align 1 - %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %3 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %2, i16 11) ; [#uses=1] - store i16 %3, i16* @ss, align 2 - %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %5 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %4, i16 11) ; [#uses=1] - store i16 %5, i16* @us, align 2 - %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %7 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %6, i32 11) ; [#uses=1] - store i32 %7, i32* @si, align 4 - %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %9 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %8, i32 11) ; [#uses=1] - store i32 %9, i32* @ui, align 4 - %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %11 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %10, i32 11) ; [#uses=1] - store i32 %11, i32* @sl, align 4 - %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %13 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %12, i32 11) ; [#uses=1] - store i32 %13, i32* @ul, align 4 - %14 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %15 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %14, i64 11) ; [#uses=1] - store i64 %15, i64* @sll, align 8 - %16 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %17 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %16, i64 11) ; [#uses=1] - store i64 %17, i64* @ull, align 8 - %18 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @sc, i8 11) ; [#uses=1] - store i8 %18, i8* @sc, align 1 - %19 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @uc, i8 11) ; [#uses=1] - store i8 %19, i8* @uc, align 1 - %20 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %21 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %20, i16 11) ; [#uses=1] - store i16 %21, i16* @ss, align 2 - %22 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %23 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %22, i16 11) ; [#uses=1] - store i16 %23, i16* @us, align 2 - %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %25 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %24, i32 11) ; [#uses=1] - store i32 %25, i32* @si, align 4 - %26 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %27 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %26, i32 11) ; [#uses=1] - store i32 %27, i32* @ui, align 4 - %28 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %29 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %28, i32 11) ; [#uses=1] - store i32 %29, i32* @sl, align 4 - %30 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %31 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %30, i32 11) ; [#uses=1] - store i32 %31, i32* @ul, align 4 - %32 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %33 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %32, i64 11) ; [#uses=1] - store i64 %33, i64* @sll, align 8 - %34 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %35 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %34, i64 11) ; [#uses=1] - store i64 %35, i64* @ull, align 8 - %36 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @sc, i8 11) ; [#uses=1] - store i8 %36, i8* @sc, align 1 - %37 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @uc, i8 11) ; [#uses=1] - store i8 %37, i8* @uc, align 1 - %38 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %39 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %38, i16 11) ; [#uses=1] - store i16 %39, i16* @ss, align 2 - %40 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %41 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %40, i16 11) ; [#uses=1] - store i16 %41, i16* @us, align 2 - %42 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %43 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %42, i32 11) ; [#uses=1] - store i32 %43, i32* @si, align 4 - %44 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %45 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %44, i32 11) ; [#uses=1] - store i32 %45, i32* @ui, align 4 - %46 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %47 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %46, i32 11) ; [#uses=1] - store i32 %47, i32* @sl, align 4 - %48 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %49 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %48, i32 11) ; [#uses=1] - store i32 %49, i32* @ul, align 4 - %50 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %51 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %50, i64 11) ; [#uses=1] - store i64 %51, i64* @sll, align 8 - %52 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %53 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %52, i64 11) ; [#uses=1] - store i64 %53, i64* @ull, align 8 - %54 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @sc, i8 11) ; [#uses=1] - store i8 %54, i8* @sc, align 1 - %55 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @uc, i8 11) ; [#uses=1] - store i8 %55, i8* @uc, align 1 - %56 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %57 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %56, i16 11) ; [#uses=1] - store i16 %57, i16* @ss, align 2 - %58 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %59 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %58, i16 11) ; [#uses=1] - store i16 %59, i16* @us, align 2 - %60 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %61 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %60, i32 11) ; [#uses=1] - store i32 %61, i32* @si, align 4 - %62 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %63 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %62, i32 11) ; [#uses=1] - store i32 %63, i32* @ui, align 4 - %64 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %65 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %64, i32 11) ; [#uses=1] - store i32 %65, i32* @sl, align 4 - %66 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %67 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %66, i32 11) ; [#uses=1] - store i32 %67, i32* @ul, align 4 - %68 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %69 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %68, i64 11) ; [#uses=1] - store i64 %69, i64* @sll, align 8 - %70 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %71 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %70, i64 11) ; [#uses=1] - store i64 %71, i64* @ull, align 8 - %72 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @sc, i8 11) ; [#uses=1] - store i8 %72, i8* @sc, align 1 - %73 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @uc, i8 11) ; [#uses=1] - store i8 %73, i8* @uc, align 1 - %74 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %75 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %74, i16 11) ; [#uses=1] - store i16 %75, i16* @ss, align 2 - %76 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %77 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %76, i16 11) ; [#uses=1] - store i16 %77, i16* @us, align 2 - %78 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %79 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %78, i32 11) ; [#uses=1] - store i32 %79, i32* @si, align 4 - %80 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %81 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %80, i32 11) ; [#uses=1] - store i32 %81, i32* @ui, align 4 - %82 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %83 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %82, i32 11) ; [#uses=1] - store i32 %83, i32* @sl, align 4 - %84 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %85 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %84, i32 11) ; [#uses=1] - store i32 %85, i32* @ul, align 4 - %86 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %87 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %86, i64 11) ; [#uses=1] - store i64 %87, i64* @sll, align 8 - %88 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %89 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %88, i64 11) ; [#uses=1] - store i64 %89, i64* @ull, align 8 - %90 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @sc, i8 11) ; [#uses=1] - store i8 %90, i8* @sc, align 1 - %91 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @uc, i8 11) ; [#uses=1] - store i8 %91, i8* @uc, align 1 - %92 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %93 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %92, i16 11) ; [#uses=1] - store i16 %93, i16* @ss, align 2 - %94 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %95 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %94, i16 11) ; [#uses=1] - store i16 %95, i16* @us, align 2 - %96 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %97 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %96, i32 11) ; [#uses=1] - store i32 %97, i32* @si, align 4 - %98 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %99 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %98, i32 11) ; [#uses=1] - store i32 %99, i32* @ui, align 4 - %100 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %101 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %100, i32 11) ; [#uses=1] - store i32 %101, i32* @sl, align 4 - %102 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %103 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %102, i32 11) ; [#uses=1] - store i32 %103, i32* @ul, align 4 - %104 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %105 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %104, i64 11) ; [#uses=1] - store i64 %105, i64* @sll, align 8 - %106 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %107 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %106, i64 11) ; [#uses=1] - store i64 %107, i64* @ull, align 8 - br label %return - -return: ; preds = %entry - ret void -} - -define void @test_op_and_fetch() nounwind { -entry: - %0 = load i8* @uc, align 1 ; [#uses=1] - %1 = zext i8 %0 to i32 ; [#uses=1] - %2 = trunc i32 %1 to i8 ; [#uses=2] - %3 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @sc, i8 %2) ; [#uses=1] - %4 = add i8 %3, %2 ; [#uses=1] - store i8 %4, i8* @sc, align 1 - %5 = load i8* @uc, align 1 ; [#uses=1] - %6 = zext i8 %5 to i32 ; [#uses=1] - %7 = trunc i32 %6 to i8 ; [#uses=2] - %8 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @uc, i8 %7) ; [#uses=1] - %9 = add i8 %8, %7 ; [#uses=1] - store i8 %9, i8* @uc, align 1 - %10 = load i8* @uc, align 1 ; [#uses=1] - %11 = zext i8 %10 to i32 ; [#uses=1] - %12 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %13 = trunc i32 %11 to i16 ; [#uses=2] - %14 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %12, i16 %13) ; [#uses=1] - %15 = add i16 %14, %13 ; [#uses=1] - store i16 %15, i16* @ss, align 2 - %16 = load i8* @uc, align 1 ; [#uses=1] - %17 = zext i8 %16 to i32 ; [#uses=1] - %18 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %19 = trunc i32 %17 to i16 ; [#uses=2] - %20 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %18, i16 %19) ; [#uses=1] - %21 = add i16 %20, %19 ; [#uses=1] - store i16 %21, i16* @us, align 2 - %22 = load i8* @uc, align 1 ; [#uses=1] - %23 = zext i8 %22 to i32 ; [#uses=2] - %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %25 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %24, i32 %23) ; [#uses=1] - %26 = add i32 %25, %23 ; [#uses=1] - store i32 %26, i32* @si, align 4 - %27 = load i8* @uc, align 1 ; [#uses=1] - %28 = zext i8 %27 to i32 ; [#uses=2] - %29 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %30 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %29, i32 %28) ; [#uses=1] - %31 = add i32 %30, %28 ; [#uses=1] - store i32 %31, i32* @ui, align 4 - %32 = load i8* @uc, align 1 ; [#uses=1] - %33 = zext i8 %32 to i32 ; [#uses=2] - %34 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %35 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %34, i32 %33) ; [#uses=1] - %36 = add i32 %35, %33 ; [#uses=1] - store i32 %36, i32* @sl, align 4 - %37 = load i8* @uc, align 1 ; [#uses=1] - %38 = zext i8 %37 to i32 ; [#uses=2] - %39 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %40 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %39, i32 %38) ; [#uses=1] - %41 = add i32 %40, %38 ; [#uses=1] - store i32 %41, i32* @ul, align 4 - %42 = load i8* @uc, align 1 ; [#uses=1] - %43 = zext i8 %42 to i64 ; [#uses=2] - %44 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %45 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %44, i64 %43) ; [#uses=1] - %46 = add i64 %45, %43 ; [#uses=1] - store i64 %46, i64* @sll, align 8 - %47 = load i8* @uc, align 1 ; [#uses=1] - %48 = zext i8 %47 to i64 ; [#uses=2] - %49 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %50 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %49, i64 %48) ; [#uses=1] - %51 = add i64 %50, %48 ; [#uses=1] - store i64 %51, i64* @ull, align 8 - %52 = load i8* @uc, align 1 ; [#uses=1] - %53 = zext i8 %52 to i32 ; [#uses=1] - %54 = trunc i32 %53 to i8 ; [#uses=2] - %55 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @sc, i8 %54) ; [#uses=1] - %56 = sub i8 %55, %54 ; [#uses=1] - store i8 %56, i8* @sc, align 1 - %57 = load i8* @uc, align 1 ; [#uses=1] - %58 = zext i8 %57 to i32 ; [#uses=1] - %59 = trunc i32 %58 to i8 ; [#uses=2] - %60 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @uc, i8 %59) ; [#uses=1] - %61 = sub i8 %60, %59 ; [#uses=1] - store i8 %61, i8* @uc, align 1 - %62 = load i8* @uc, align 1 ; [#uses=1] - %63 = zext i8 %62 to i32 ; [#uses=1] - %64 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %65 = trunc i32 %63 to i16 ; [#uses=2] - %66 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %64, i16 %65) ; [#uses=1] - %67 = sub i16 %66, %65 ; [#uses=1] - store i16 %67, i16* @ss, align 2 - %68 = load i8* @uc, align 1 ; [#uses=1] - %69 = zext i8 %68 to i32 ; [#uses=1] - %70 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %71 = trunc i32 %69 to i16 ; [#uses=2] - %72 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %70, i16 %71) ; [#uses=1] - %73 = sub i16 %72, %71 ; [#uses=1] - store i16 %73, i16* @us, align 2 - %74 = load i8* @uc, align 1 ; [#uses=1] - %75 = zext i8 %74 to i32 ; [#uses=2] - %76 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %77 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %76, i32 %75) ; [#uses=1] - %78 = sub i32 %77, %75 ; [#uses=1] - store i32 %78, i32* @si, align 4 - %79 = load i8* @uc, align 1 ; [#uses=1] - %80 = zext i8 %79 to i32 ; [#uses=2] - %81 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %82 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %81, i32 %80) ; [#uses=1] - %83 = sub i32 %82, %80 ; [#uses=1] - store i32 %83, i32* @ui, align 4 - %84 = load i8* @uc, align 1 ; [#uses=1] - %85 = zext i8 %84 to i32 ; [#uses=2] - %86 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %87 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %86, i32 %85) ; [#uses=1] - %88 = sub i32 %87, %85 ; [#uses=1] - store i32 %88, i32* @sl, align 4 - %89 = load i8* @uc, align 1 ; [#uses=1] - %90 = zext i8 %89 to i32 ; [#uses=2] - %91 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %92 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %91, i32 %90) ; [#uses=1] - %93 = sub i32 %92, %90 ; [#uses=1] - store i32 %93, i32* @ul, align 4 - %94 = load i8* @uc, align 1 ; [#uses=1] - %95 = zext i8 %94 to i64 ; [#uses=2] - %96 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %97 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %96, i64 %95) ; [#uses=1] - %98 = sub i64 %97, %95 ; [#uses=1] - store i64 %98, i64* @sll, align 8 - %99 = load i8* @uc, align 1 ; [#uses=1] - %100 = zext i8 %99 to i64 ; [#uses=2] - %101 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %102 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %101, i64 %100) ; [#uses=1] - %103 = sub i64 %102, %100 ; [#uses=1] - store i64 %103, i64* @ull, align 8 - %104 = load i8* @uc, align 1 ; [#uses=1] - %105 = zext i8 %104 to i32 ; [#uses=1] - %106 = trunc i32 %105 to i8 ; [#uses=2] - %107 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @sc, i8 %106) ; [#uses=1] - %108 = or i8 %107, %106 ; [#uses=1] - store i8 %108, i8* @sc, align 1 - %109 = load i8* @uc, align 1 ; [#uses=1] - %110 = zext i8 %109 to i32 ; [#uses=1] - %111 = trunc i32 %110 to i8 ; [#uses=2] - %112 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @uc, i8 %111) ; [#uses=1] - %113 = or i8 %112, %111 ; [#uses=1] - store i8 %113, i8* @uc, align 1 - %114 = load i8* @uc, align 1 ; [#uses=1] - %115 = zext i8 %114 to i32 ; [#uses=1] - %116 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %117 = trunc i32 %115 to i16 ; [#uses=2] - %118 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %116, i16 %117) ; [#uses=1] - %119 = or i16 %118, %117 ; [#uses=1] - store i16 %119, i16* @ss, align 2 - %120 = load i8* @uc, align 1 ; [#uses=1] - %121 = zext i8 %120 to i32 ; [#uses=1] - %122 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %123 = trunc i32 %121 to i16 ; [#uses=2] - %124 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %122, i16 %123) ; [#uses=1] - %125 = or i16 %124, %123 ; [#uses=1] - store i16 %125, i16* @us, align 2 - %126 = load i8* @uc, align 1 ; [#uses=1] - %127 = zext i8 %126 to i32 ; [#uses=2] - %128 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %129 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %128, i32 %127) ; [#uses=1] - %130 = or i32 %129, %127 ; [#uses=1] - store i32 %130, i32* @si, align 4 - %131 = load i8* @uc, align 1 ; [#uses=1] - %132 = zext i8 %131 to i32 ; [#uses=2] - %133 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %134 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %133, i32 %132) ; [#uses=1] - %135 = or i32 %134, %132 ; [#uses=1] - store i32 %135, i32* @ui, align 4 - %136 = load i8* @uc, align 1 ; [#uses=1] - %137 = zext i8 %136 to i32 ; [#uses=2] - %138 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %139 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %138, i32 %137) ; [#uses=1] - %140 = or i32 %139, %137 ; [#uses=1] - store i32 %140, i32* @sl, align 4 - %141 = load i8* @uc, align 1 ; [#uses=1] - %142 = zext i8 %141 to i32 ; [#uses=2] - %143 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %144 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %143, i32 %142) ; [#uses=1] - %145 = or i32 %144, %142 ; [#uses=1] - store i32 %145, i32* @ul, align 4 - %146 = load i8* @uc, align 1 ; [#uses=1] - %147 = zext i8 %146 to i64 ; [#uses=2] - %148 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %149 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %148, i64 %147) ; [#uses=1] - %150 = or i64 %149, %147 ; [#uses=1] - store i64 %150, i64* @sll, align 8 - %151 = load i8* @uc, align 1 ; [#uses=1] - %152 = zext i8 %151 to i64 ; [#uses=2] - %153 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %154 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %153, i64 %152) ; [#uses=1] - %155 = or i64 %154, %152 ; [#uses=1] - store i64 %155, i64* @ull, align 8 - %156 = load i8* @uc, align 1 ; [#uses=1] - %157 = zext i8 %156 to i32 ; [#uses=1] - %158 = trunc i32 %157 to i8 ; [#uses=2] - %159 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @sc, i8 %158) ; [#uses=1] - %160 = xor i8 %159, %158 ; [#uses=1] - store i8 %160, i8* @sc, align 1 - %161 = load i8* @uc, align 1 ; [#uses=1] - %162 = zext i8 %161 to i32 ; [#uses=1] - %163 = trunc i32 %162 to i8 ; [#uses=2] - %164 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @uc, i8 %163) ; [#uses=1] - %165 = xor i8 %164, %163 ; [#uses=1] - store i8 %165, i8* @uc, align 1 - %166 = load i8* @uc, align 1 ; [#uses=1] - %167 = zext i8 %166 to i32 ; [#uses=1] - %168 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %169 = trunc i32 %167 to i16 ; [#uses=2] - %170 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %168, i16 %169) ; [#uses=1] - %171 = xor i16 %170, %169 ; [#uses=1] - store i16 %171, i16* @ss, align 2 - %172 = load i8* @uc, align 1 ; [#uses=1] - %173 = zext i8 %172 to i32 ; [#uses=1] - %174 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %175 = trunc i32 %173 to i16 ; [#uses=2] - %176 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %174, i16 %175) ; [#uses=1] - %177 = xor i16 %176, %175 ; [#uses=1] - store i16 %177, i16* @us, align 2 - %178 = load i8* @uc, align 1 ; [#uses=1] - %179 = zext i8 %178 to i32 ; [#uses=2] - %180 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %181 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %180, i32 %179) ; [#uses=1] - %182 = xor i32 %181, %179 ; [#uses=1] - store i32 %182, i32* @si, align 4 - %183 = load i8* @uc, align 1 ; [#uses=1] - %184 = zext i8 %183 to i32 ; [#uses=2] - %185 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %186 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %185, i32 %184) ; [#uses=1] - %187 = xor i32 %186, %184 ; [#uses=1] - store i32 %187, i32* @ui, align 4 - %188 = load i8* @uc, align 1 ; [#uses=1] - %189 = zext i8 %188 to i32 ; [#uses=2] - %190 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %191 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %190, i32 %189) ; [#uses=1] - %192 = xor i32 %191, %189 ; [#uses=1] - store i32 %192, i32* @sl, align 4 - %193 = load i8* @uc, align 1 ; [#uses=1] - %194 = zext i8 %193 to i32 ; [#uses=2] - %195 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %196 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %195, i32 %194) ; [#uses=1] - %197 = xor i32 %196, %194 ; [#uses=1] - store i32 %197, i32* @ul, align 4 - %198 = load i8* @uc, align 1 ; [#uses=1] - %199 = zext i8 %198 to i64 ; [#uses=2] - %200 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %201 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %200, i64 %199) ; [#uses=1] - %202 = xor i64 %201, %199 ; [#uses=1] - store i64 %202, i64* @sll, align 8 - %203 = load i8* @uc, align 1 ; [#uses=1] - %204 = zext i8 %203 to i64 ; [#uses=2] - %205 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %206 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %205, i64 %204) ; [#uses=1] - %207 = xor i64 %206, %204 ; [#uses=1] - store i64 %207, i64* @ull, align 8 - %208 = load i8* @uc, align 1 ; [#uses=1] - %209 = zext i8 %208 to i32 ; [#uses=1] - %210 = trunc i32 %209 to i8 ; [#uses=2] - %211 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @sc, i8 %210) ; [#uses=1] - %212 = and i8 %211, %210 ; [#uses=1] - store i8 %212, i8* @sc, align 1 - %213 = load i8* @uc, align 1 ; [#uses=1] - %214 = zext i8 %213 to i32 ; [#uses=1] - %215 = trunc i32 %214 to i8 ; [#uses=2] - %216 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @uc, i8 %215) ; [#uses=1] - %217 = and i8 %216, %215 ; [#uses=1] - store i8 %217, i8* @uc, align 1 - %218 = load i8* @uc, align 1 ; [#uses=1] - %219 = zext i8 %218 to i32 ; [#uses=1] - %220 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %221 = trunc i32 %219 to i16 ; [#uses=2] - %222 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %220, i16 %221) ; [#uses=1] - %223 = and i16 %222, %221 ; [#uses=1] - store i16 %223, i16* @ss, align 2 - %224 = load i8* @uc, align 1 ; [#uses=1] - %225 = zext i8 %224 to i32 ; [#uses=1] - %226 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %227 = trunc i32 %225 to i16 ; [#uses=2] - %228 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %226, i16 %227) ; [#uses=1] - %229 = and i16 %228, %227 ; [#uses=1] - store i16 %229, i16* @us, align 2 - %230 = load i8* @uc, align 1 ; [#uses=1] - %231 = zext i8 %230 to i32 ; [#uses=2] - %232 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %233 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %232, i32 %231) ; [#uses=1] - %234 = and i32 %233, %231 ; [#uses=1] - store i32 %234, i32* @si, align 4 - %235 = load i8* @uc, align 1 ; [#uses=1] - %236 = zext i8 %235 to i32 ; [#uses=2] - %237 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %238 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %237, i32 %236) ; [#uses=1] - %239 = and i32 %238, %236 ; [#uses=1] - store i32 %239, i32* @ui, align 4 - %240 = load i8* @uc, align 1 ; [#uses=1] - %241 = zext i8 %240 to i32 ; [#uses=2] - %242 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %243 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %242, i32 %241) ; [#uses=1] - %244 = and i32 %243, %241 ; [#uses=1] - store i32 %244, i32* @sl, align 4 - %245 = load i8* @uc, align 1 ; [#uses=1] - %246 = zext i8 %245 to i32 ; [#uses=2] - %247 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %248 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %247, i32 %246) ; [#uses=1] - %249 = and i32 %248, %246 ; [#uses=1] - store i32 %249, i32* @ul, align 4 - %250 = load i8* @uc, align 1 ; [#uses=1] - %251 = zext i8 %250 to i64 ; [#uses=2] - %252 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %253 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %252, i64 %251) ; [#uses=1] - %254 = and i64 %253, %251 ; [#uses=1] - store i64 %254, i64* @sll, align 8 - %255 = load i8* @uc, align 1 ; [#uses=1] - %256 = zext i8 %255 to i64 ; [#uses=2] - %257 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %258 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %257, i64 %256) ; [#uses=1] - %259 = and i64 %258, %256 ; [#uses=1] - store i64 %259, i64* @ull, align 8 - %260 = load i8* @uc, align 1 ; [#uses=1] - %261 = zext i8 %260 to i32 ; [#uses=1] - %262 = trunc i32 %261 to i8 ; [#uses=2] - %263 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @sc, i8 %262) ; [#uses=1] - %264 = xor i8 %263, -1 ; [#uses=1] - %265 = and i8 %264, %262 ; [#uses=1] - store i8 %265, i8* @sc, align 1 - %266 = load i8* @uc, align 1 ; [#uses=1] - %267 = zext i8 %266 to i32 ; [#uses=1] - %268 = trunc i32 %267 to i8 ; [#uses=2] - %269 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @uc, i8 %268) ; [#uses=1] - %270 = xor i8 %269, -1 ; [#uses=1] - %271 = and i8 %270, %268 ; [#uses=1] - store i8 %271, i8* @uc, align 1 - %272 = load i8* @uc, align 1 ; [#uses=1] - %273 = zext i8 %272 to i32 ; [#uses=1] - %274 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %275 = trunc i32 %273 to i16 ; [#uses=2] - %276 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %274, i16 %275) ; [#uses=1] - %277 = xor i16 %276, -1 ; [#uses=1] - %278 = and i16 %277, %275 ; [#uses=1] - store i16 %278, i16* @ss, align 2 - %279 = load i8* @uc, align 1 ; [#uses=1] - %280 = zext i8 %279 to i32 ; [#uses=1] - %281 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %282 = trunc i32 %280 to i16 ; [#uses=2] - %283 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %281, i16 %282) ; [#uses=1] - %284 = xor i16 %283, -1 ; [#uses=1] - %285 = and i16 %284, %282 ; [#uses=1] - store i16 %285, i16* @us, align 2 - %286 = load i8* @uc, align 1 ; [#uses=1] - %287 = zext i8 %286 to i32 ; [#uses=2] - %288 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %289 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %288, i32 %287) ; [#uses=1] - %290 = xor i32 %289, -1 ; [#uses=1] - %291 = and i32 %290, %287 ; [#uses=1] - store i32 %291, i32* @si, align 4 - %292 = load i8* @uc, align 1 ; [#uses=1] - %293 = zext i8 %292 to i32 ; [#uses=2] - %294 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %295 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %294, i32 %293) ; [#uses=1] - %296 = xor i32 %295, -1 ; [#uses=1] - %297 = and i32 %296, %293 ; [#uses=1] - store i32 %297, i32* @ui, align 4 - %298 = load i8* @uc, align 1 ; [#uses=1] - %299 = zext i8 %298 to i32 ; [#uses=2] - %300 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %301 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %300, i32 %299) ; [#uses=1] - %302 = xor i32 %301, -1 ; [#uses=1] - %303 = and i32 %302, %299 ; [#uses=1] - store i32 %303, i32* @sl, align 4 - %304 = load i8* @uc, align 1 ; [#uses=1] - %305 = zext i8 %304 to i32 ; [#uses=2] - %306 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %307 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %306, i32 %305) ; [#uses=1] - %308 = xor i32 %307, -1 ; [#uses=1] - %309 = and i32 %308, %305 ; [#uses=1] - store i32 %309, i32* @ul, align 4 - %310 = load i8* @uc, align 1 ; [#uses=1] - %311 = zext i8 %310 to i64 ; [#uses=2] - %312 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - %313 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %312, i64 %311) ; [#uses=1] - %314 = xor i64 %313, -1 ; [#uses=1] - %315 = and i64 %314, %311 ; [#uses=1] - store i64 %315, i64* @sll, align 8 - %316 = load i8* @uc, align 1 ; [#uses=1] - %317 = zext i8 %316 to i64 ; [#uses=2] - %318 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - %319 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %318, i64 %317) ; [#uses=1] - %320 = xor i64 %319, -1 ; [#uses=1] - %321 = and i64 %320, %317 ; [#uses=1] - store i64 %321, i64* @ull, align 8 - br label %return - -return: ; preds = %entry - ret void -} - -define void @test_compare_and_swap() nounwind { -entry: - %0 = load i8* @sc, align 1 ; [#uses=1] - %1 = zext i8 %0 to i32 ; [#uses=1] - %2 = load i8* @uc, align 1 ; [#uses=1] - %3 = zext i8 %2 to i32 ; [#uses=1] - %4 = trunc i32 %3 to i8 ; [#uses=1] - %5 = trunc i32 %1 to i8 ; [#uses=1] - %6 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @sc, i8 %4, i8 %5) ; [#uses=1] - store i8 %6, i8* @sc, align 1 - %7 = load i8* @sc, align 1 ; [#uses=1] - %8 = zext i8 %7 to i32 ; [#uses=1] - %9 = load i8* @uc, align 1 ; [#uses=1] - %10 = zext i8 %9 to i32 ; [#uses=1] - %11 = trunc i32 %10 to i8 ; [#uses=1] - %12 = trunc i32 %8 to i8 ; [#uses=1] - %13 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @uc, i8 %11, i8 %12) ; [#uses=1] - store i8 %13, i8* @uc, align 1 - %14 = load i8* @sc, align 1 ; [#uses=1] - %15 = sext i8 %14 to i16 ; [#uses=1] - %16 = zext i16 %15 to i32 ; [#uses=1] - %17 = load i8* @uc, align 1 ; [#uses=1] - %18 = zext i8 %17 to i32 ; [#uses=1] - %19 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %20 = trunc i32 %18 to i16 ; [#uses=1] - %21 = trunc i32 %16 to i16 ; [#uses=1] - %22 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %19, i16 %20, i16 %21) ; [#uses=1] - store i16 %22, i16* @ss, align 2 - %23 = load i8* @sc, align 1 ; [#uses=1] - %24 = sext i8 %23 to i16 ; [#uses=1] - %25 = zext i16 %24 to i32 ; [#uses=1] - %26 = load i8* @uc, align 1 ; [#uses=1] - %27 = zext i8 %26 to i32 ; [#uses=1] - %28 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %29 = trunc i32 %27 to i16 ; [#uses=1] - %30 = trunc i32 %25 to i16 ; [#uses=1] - %31 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %28, i16 %29, i16 %30) ; [#uses=1] - store i16 %31, i16* @us, align 2 - %32 = load i8* @sc, align 1 ; [#uses=1] - %33 = sext i8 %32 to i32 ; [#uses=1] - %34 = load i8* @uc, align 1 ; [#uses=1] - %35 = zext i8 %34 to i32 ; [#uses=1] - %36 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %37 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %36, i32 %35, i32 %33) ; [#uses=1] - store i32 %37, i32* @si, align 4 - %38 = load i8* @sc, align 1 ; [#uses=1] - %39 = sext i8 %38 to i32 ; [#uses=1] - %40 = load i8* @uc, align 1 ; [#uses=1] - %41 = zext i8 %40 to i32 ; [#uses=1] - %42 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %43 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %42, i32 %41, i32 %39) ; [#uses=1] - store i32 %43, i32* @ui, align 4 - %44 = load i8* @sc, align 1 ; [#uses=1] - %45 = sext i8 %44 to i32 ; [#uses=1] - %46 = load i8* @uc, align 1 ; [#uses=1] - %47 = zext i8 %46 to i32 ; [#uses=1] - %48 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %49 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %48, i32 %47, i32 %45) ; [#uses=1] - store i32 %49, i32* @sl, align 4 - %50 = load i8* @sc, align 1 ; [#uses=1] - %51 = sext i8 %50 to i32 ; [#uses=1] - %52 = load i8* @uc, align 1 ; [#uses=1] - %53 = zext i8 %52 to i32 ; [#uses=1] - %54 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %55 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %54, i32 %53, i32 %51) ; [#uses=1] - store i32 %55, i32* @ul, align 4 - %56 = load i8* @sc, align 1 ; [#uses=1] - %57 = zext i8 %56 to i32 ; [#uses=1] - %58 = load i8* @uc, align 1 ; [#uses=1] - %59 = zext i8 %58 to i32 ; [#uses=1] - %60 = trunc i32 %59 to i8 ; [#uses=2] - %61 = trunc i32 %57 to i8 ; [#uses=1] - %62 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @sc, i8 %60, i8 %61) ; [#uses=1] - %63 = icmp eq i8 %62, %60 ; [#uses=1] - %64 = zext i1 %63 to i8 ; [#uses=1] - %65 = zext i8 %64 to i32 ; [#uses=1] - store i32 %65, i32* @ui, align 4 - %66 = load i8* @sc, align 1 ; [#uses=1] - %67 = zext i8 %66 to i32 ; [#uses=1] - %68 = load i8* @uc, align 1 ; [#uses=1] - %69 = zext i8 %68 to i32 ; [#uses=1] - %70 = trunc i32 %69 to i8 ; [#uses=2] - %71 = trunc i32 %67 to i8 ; [#uses=1] - %72 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @uc, i8 %70, i8 %71) ; [#uses=1] - %73 = icmp eq i8 %72, %70 ; [#uses=1] - %74 = zext i1 %73 to i8 ; [#uses=1] - %75 = zext i8 %74 to i32 ; [#uses=1] - store i32 %75, i32* @ui, align 4 - %76 = load i8* @sc, align 1 ; [#uses=1] - %77 = sext i8 %76 to i16 ; [#uses=1] - %78 = zext i16 %77 to i32 ; [#uses=1] - %79 = load i8* @uc, align 1 ; [#uses=1] - %80 = zext i8 %79 to i32 ; [#uses=1] - %81 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %82 = trunc i32 %80 to i16 ; [#uses=2] - %83 = trunc i32 %78 to i16 ; [#uses=1] - %84 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %81, i16 %82, i16 %83) ; [#uses=1] - %85 = icmp eq i16 %84, %82 ; [#uses=1] - %86 = zext i1 %85 to i8 ; [#uses=1] - %87 = zext i8 %86 to i32 ; [#uses=1] - store i32 %87, i32* @ui, align 4 - %88 = load i8* @sc, align 1 ; [#uses=1] - %89 = sext i8 %88 to i16 ; [#uses=1] - %90 = zext i16 %89 to i32 ; [#uses=1] - %91 = load i8* @uc, align 1 ; [#uses=1] - %92 = zext i8 %91 to i32 ; [#uses=1] - %93 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %94 = trunc i32 %92 to i16 ; [#uses=2] - %95 = trunc i32 %90 to i16 ; [#uses=1] - %96 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %93, i16 %94, i16 %95) ; [#uses=1] - %97 = icmp eq i16 %96, %94 ; [#uses=1] - %98 = zext i1 %97 to i8 ; [#uses=1] - %99 = zext i8 %98 to i32 ; [#uses=1] - store i32 %99, i32* @ui, align 4 - %100 = load i8* @sc, align 1 ; [#uses=1] - %101 = sext i8 %100 to i32 ; [#uses=1] - %102 = load i8* @uc, align 1 ; [#uses=1] - %103 = zext i8 %102 to i32 ; [#uses=2] - %104 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %105 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %104, i32 %103, i32 %101) ; [#uses=1] - %106 = icmp eq i32 %105, %103 ; [#uses=1] - %107 = zext i1 %106 to i8 ; [#uses=1] - %108 = zext i8 %107 to i32 ; [#uses=1] - store i32 %108, i32* @ui, align 4 - %109 = load i8* @sc, align 1 ; [#uses=1] - %110 = sext i8 %109 to i32 ; [#uses=1] - %111 = load i8* @uc, align 1 ; [#uses=1] - %112 = zext i8 %111 to i32 ; [#uses=2] - %113 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %114 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %113, i32 %112, i32 %110) ; [#uses=1] - %115 = icmp eq i32 %114, %112 ; [#uses=1] - %116 = zext i1 %115 to i8 ; [#uses=1] - %117 = zext i8 %116 to i32 ; [#uses=1] - store i32 %117, i32* @ui, align 4 - %118 = load i8* @sc, align 1 ; [#uses=1] - %119 = sext i8 %118 to i32 ; [#uses=1] - %120 = load i8* @uc, align 1 ; [#uses=1] - %121 = zext i8 %120 to i32 ; [#uses=2] - %122 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %123 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %122, i32 %121, i32 %119) ; [#uses=1] - %124 = icmp eq i32 %123, %121 ; [#uses=1] - %125 = zext i1 %124 to i8 ; [#uses=1] - %126 = zext i8 %125 to i32 ; [#uses=1] - store i32 %126, i32* @ui, align 4 - %127 = load i8* @sc, align 1 ; [#uses=1] - %128 = sext i8 %127 to i32 ; [#uses=1] - %129 = load i8* @uc, align 1 ; [#uses=1] - %130 = zext i8 %129 to i32 ; [#uses=2] - %131 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %132 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %131, i32 %130, i32 %128) ; [#uses=1] - %133 = icmp eq i32 %132, %130 ; [#uses=1] - %134 = zext i1 %133 to i8 ; [#uses=1] - %135 = zext i8 %134 to i32 ; [#uses=1] - store i32 %135, i32* @ui, align 4 - br label %return - -return: ; preds = %entry - ret void -} - -declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind - -declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind - -declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind - -define void @test_lock() nounwind { -entry: - %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @sc, i8 1) ; [#uses=1] - store i8 %0, i8* @sc, align 1 - %1 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @uc, i8 1) ; [#uses=1] - store i8 %1, i8* @uc, align 1 - %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - %3 = call i16 @llvm.atomic.swap.i16.p0i16(i16* %2, i16 1) ; [#uses=1] - store i16 %3, i16* @ss, align 2 - %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - %5 = call i16 @llvm.atomic.swap.i16.p0i16(i16* %4, i16 1) ; [#uses=1] - store i16 %5, i16* @us, align 2 - %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - %7 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %6, i32 1) ; [#uses=1] - store i32 %7, i32* @si, align 4 - %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - %9 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %8, i32 1) ; [#uses=1] - store i32 %9, i32* @ui, align 4 - %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - %11 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %10, i32 1) ; [#uses=1] - store i32 %11, i32* @sl, align 4 - %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - %13 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %12, i32 1) ; [#uses=1] - store i32 %13, i32* @ul, align 4 - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) - volatile store i8 0, i8* @sc, align 1 - volatile store i8 0, i8* @uc, align 1 - %14 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; [#uses=1] - volatile store i16 0, i16* %14, align 2 - %15 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; [#uses=1] - volatile store i16 0, i16* %15, align 2 - %16 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; [#uses=1] - volatile store i32 0, i32* %16, align 4 - %17 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; [#uses=1] - volatile store i32 0, i32* %17, align 4 - %18 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; [#uses=1] - volatile store i32 0, i32* %18, align 4 - %19 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; [#uses=1] - volatile store i32 0, i32* %19, align 4 - %20 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; [#uses=1] - volatile store i64 0, i64* %20, align 8 - %21 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; [#uses=1] - volatile store i64 0, i64* %21, align 8 - br label %return - -return: ; preds = %entry - ret void -} - -declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind - -declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind Modified: llvm/trunk/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll?rev=140582&r1=140581&r2=140582&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll Mon Sep 26 18:15:09 2011 @@ -36,7 +36,7 @@ call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind %4 = call i64 @llvm.readcyclecounter() nounwind ; [#uses=1] %5 = sub i64 %4, %2 ; [#uses=1] - %6 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* getelementptr inbounds ([1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 51), i64 %5) nounwind ; [#uses=0] + %6 = atomicrmw add i64* getelementptr inbounds ([1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 51), i64 %5 monotonic ;CHECK: lock ;CHECK-NEXT: {{xadd|addq}} %rdx, __profiling_callsite_timestamps_live ;CHECK-NEXT: cmpl $0, @@ -54,7 +54,7 @@ tail call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind %8 = tail call i64 @llvm.readcyclecounter() nounwind ; [#uses=1] %9 = sub i64 %8, %0 ; [#uses=1] - %10 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* getelementptr inbounds ([1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 50), i64 %9) ; [#uses=0] + %10 = atomicrmw add i64* getelementptr inbounds ([1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 50), i64 %9 monotonic ret i32 %7 } @@ -64,6 +64,4 @@ declare i32 @warn_dlerror(i8*) nounwind -declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind - declare i64 @llvm.readcyclecounter() nounwind Modified: llvm/trunk/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll?rev=140582&r1=140581&r2=140582&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll Mon Sep 26 18:15:09 2011 @@ -18,12 +18,6 @@ ; CHECK: lock ; CHECK: cmpxchg8b ; CHECK: jne - tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) - %0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 1) ; [#uses=0] - tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + %0 = atomicrmw add i64* %p, i64 1 seq_cst ret void } - -declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind - -declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind Modified: llvm/trunk/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll?rev=140582&r1=140581&r2=140582&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll Mon Sep 26 18:15:09 2011 @@ -18,11 +18,9 @@ loop: ; CHECK: lock ; CHECK-NEXT: cmpxchg8b - %r = call i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* %ptr, i64 0, i64 1) + %r = cmpxchg i64* %ptr, i64 0, i64 1 monotonic %stored1 = icmp eq i64 %r, 0 br i1 %stored1, label %loop, label %continue continue: ret void } - -declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* nocapture, i64, i64) nounwind Modified: llvm/trunk/test/CodeGen/X86/atomic-or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic-or.ll?rev=140582&r1=140581&r2=140582&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/atomic-or.ll (original) +++ llvm/trunk/test/CodeGen/X86/atomic-or.ll Mon Sep 26 18:15:09 2011 @@ -7,13 +7,11 @@ %p.addr = alloca i64*, align 8 store i64* %p, i64** %p.addr, align 8 %tmp = load i64** %p.addr, align 8 - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) ; CHECK: t1: ; CHECK: movl $2147483648, %eax ; CHECK: lock ; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}}) - %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648) - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + %0 = atomicrmw or i64* %tmp, i64 2147483648 seq_cst ret void } @@ -22,15 +20,9 @@ %p.addr = alloca i64*, align 8 store i64* %p, i64** %p.addr, align 8 %tmp = load i64** %p.addr, align 8 - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) ; CHECK: t2: -; CHECK-NOT: movl ; CHECK: lock ; CHECK-NEXT: orq $2147483644, (%r{{.*}}) - %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483644) - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + %0 = atomicrmw or i64* %tmp, i64 2147483644 seq_cst ret void } - -declare i64 @llvm.atomic.load.or.i64.p0i64(i64* nocapture, i64) nounwind -declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind Modified: llvm/trunk/test/CodeGen/X86/atomic_add.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic_add.ll?rev=140582&r1=140581&r2=140582&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/atomic_add.ll (original) +++ llvm/trunk/test/CodeGen/X86/atomic_add.ll Mon Sep 26 18:15:09 2011 @@ -6,80 +6,74 @@ entry: ; CHECK: sub1: ; CHECK: subl - %0 = tail call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %p, i32 %v) ; [#uses=0] - ret void + %0 = atomicrmw sub i32* %p, i32 %v monotonic + ret void } define void @inc4(i64* nocapture %p) nounwind ssp { entry: ; CHECK: inc4: ; CHECK: incq - %0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 1) ; [#uses=0] - ret void + %0 = atomicrmw add i64* %p, i64 1 monotonic + ret void } -declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind - define void @add8(i64* nocapture %p) nounwind ssp { entry: ; CHECK: add8: ; CHECK: addq $2 - %0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 2) ; [#uses=0] - ret void + %0 = atomicrmw add i64* %p, i64 2 monotonic + ret void } define void @add4(i64* nocapture %p, i32 %v) nounwind ssp { entry: ; CHECK: add4: ; CHECK: addq - %0 = sext i32 %v to i64 ; [#uses=1] - %1 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 %0) ; [#uses=0] - ret void + %0 = sext i32 %v to i64 ; [#uses=1] + %1 = atomicrmw add i64* %p, i64 %0 monotonic + ret void } define void @inc3(i8* nocapture %p) nounwind ssp { entry: ; CHECK: inc3: ; CHECK: incb - %0 = tail call i8 @llvm.atomic.load.add.i8.p0i8(i8* %p, i8 1) ; [#uses=0] - ret void + %0 = atomicrmw add i8* %p, i8 1 monotonic + ret void } -declare i8 @llvm.atomic.load.add.i8.p0i8(i8* nocapture, i8) nounwind - define void @add7(i8* nocapture %p) nounwind ssp { entry: ; CHECK: add7: ; CHECK: addb $2 - %0 = tail call i8 @llvm.atomic.load.add.i8.p0i8(i8* %p, i8 2) ; [#uses=0] - ret void + %0 = atomicrmw add i8* %p, i8 2 monotonic + ret void } define void @add3(i8* nocapture %p, i32 %v) nounwind ssp { entry: ; CHECK: add3: ; CHECK: addb - %0 = trunc i32 %v to i8 ; [#uses=1] - %1 = tail call i8 @llvm.atomic.load.add.i8.p0i8(i8* %p, i8 %0) ; [#uses=0] - ret void + %0 = trunc i32 %v to i8 ; [#uses=1] + %1 = atomicrmw add i8* %p, i8 %0 monotonic + ret void } define void @inc2(i16* nocapture %p) nounwind ssp { entry: ; CHECK: inc2: ; CHECK: incw - %0 = tail call i16 @llvm.atomic.load.add.i16.p0i16(i16* %p, i16 1) ; [#uses=0] - ret void + %0 = atomicrmw add i16* %p, i16 1 monotonic + ret void } -declare i16 @llvm.atomic.load.add.i16.p0i16(i16* nocapture, i16) nounwind - define void @add6(i16* nocapture %p) nounwind ssp { entry: ; CHECK: add6: ; CHECK: addw $2 - %0 = tail call i16 @llvm.atomic.load.add.i16.p0i16(i16* %p, i16 2) ; [#uses=0] - ret void + %0 = atomicrmw add i16* %p, i16 2 monotonic + ret void } define void @add2(i16* nocapture %p, i32 %v) nounwind ssp { @@ -87,52 +81,48 @@ ; CHECK: add2: ; CHECK: addw %0 = trunc i32 %v to i16 ; [#uses=1] - %1 = tail call i16 @llvm.atomic.load.add.i16.p0i16(i16* %p, i16 %0) ; [#uses=0] - ret void + %1 = atomicrmw add i16* %p, i16 %0 monotonic + ret void } define void @inc1(i32* nocapture %p) nounwind ssp { entry: ; CHECK: inc1: ; CHECK: incl - %0 = tail call i32 @llvm.atomic.load.add.i32.p0i32(i32* %p, i32 1) ; [#uses=0] - ret void + %0 = atomicrmw add i32* %p, i32 1 monotonic + ret void } -declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind - define void @add5(i32* nocapture %p) nounwind ssp { entry: ; CHECK: add5: ; CHECK: addl $2 - %0 = tail call i32 @llvm.atomic.load.add.i32.p0i32(i32* %p, i32 2) ; [#uses=0] - ret void + %0 = atomicrmw add i32* %p, i32 2 monotonic + ret void } define void @add1(i32* nocapture %p, i32 %v) nounwind ssp { entry: ; CHECK: add1: ; CHECK: addl - %0 = tail call i32 @llvm.atomic.load.add.i32.p0i32(i32* %p, i32 %v) ; [#uses=0] - ret void + %0 = atomicrmw add i32* %p, i32 %v monotonic + ret void } define void @dec4(i64* nocapture %p) nounwind ssp { entry: ; CHECK: dec4: ; CHECK: decq - %0 = tail call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %p, i64 1) ; [#uses=0] - ret void + %0 = atomicrmw sub i64* %p, i64 1 monotonic + ret void } -declare i64 @llvm.atomic.load.sub.i64.p0i64(i64* nocapture, i64) nounwind - define void @sub8(i64* nocapture %p) nounwind ssp { entry: ; CHECK: sub8: ; CHECK: subq $2 - %0 = tail call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %p, i64 2) ; [#uses=0] - ret void + %0 = atomicrmw sub i64* %p, i64 2 monotonic + ret void } define void @sub4(i64* nocapture %p, i32 %v) nounwind ssp { @@ -140,26 +130,24 @@ ; CHECK: sub4: ; CHECK: subq %0 = sext i32 %v to i64 ; [#uses=1] - %1 = tail call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %p, i64 %0) ; [#uses=0] - ret void + %1 = atomicrmw sub i64* %p, i64 %0 monotonic + ret void } define void @dec3(i8* nocapture %p) nounwind ssp { entry: ; CHECK: dec3: ; CHECK: decb - %0 = tail call i8 @llvm.atomic.load.sub.i8.p0i8(i8* %p, i8 1) ; [#uses=0] - ret void + %0 = atomicrmw sub i8* %p, i8 1 monotonic + ret void } -declare i8 @llvm.atomic.load.sub.i8.p0i8(i8* nocapture, i8) nounwind - define void @sub7(i8* nocapture %p) nounwind ssp { entry: ; CHECK: sub7: ; CHECK: subb $2 - %0 = tail call i8 @llvm.atomic.load.sub.i8.p0i8(i8* %p, i8 2) ; [#uses=0] - ret void + %0 = atomicrmw sub i8* %p, i8 2 monotonic + ret void } define void @sub3(i8* nocapture %p, i32 %v) nounwind ssp { @@ -167,26 +155,24 @@ ; CHECK: sub3: ; CHECK: subb %0 = trunc i32 %v to i8 ; [#uses=1] - %1 = tail call i8 @llvm.atomic.load.sub.i8.p0i8(i8* %p, i8 %0) ; [#uses=0] - ret void + %1 = atomicrmw sub i8* %p, i8 %0 monotonic + ret void } define void @dec2(i16* nocapture %p) nounwind ssp { entry: ; CHECK: dec2: ; CHECK: decw - %0 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 1) ; [#uses=0] - ret void + %0 = atomicrmw sub i16* %p, i16 1 monotonic + ret void } -declare i16 @llvm.atomic.load.sub.i16.p0i16(i16* nocapture, i16) nounwind - define void @sub6(i16* nocapture %p) nounwind ssp { entry: ; CHECK: sub6: ; CHECK: subw $2 - %0 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 2) ; [#uses=0] - ret void + %0 = atomicrmw sub i16* %p, i16 2 monotonic + ret void } define void @sub2(i16* nocapture %p, i32 %v) nounwind ssp { @@ -194,24 +180,22 @@ ; CHECK: sub2: ; CHECK: negl %0 = trunc i32 %v to i16 ; [#uses=1] - %1 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 %0) ; [#uses=0] - ret void + %1 = atomicrmw sub i16* %p, i16 %0 monotonic + ret void } define void @dec1(i32* nocapture %p) nounwind ssp { entry: ; CHECK: dec1: ; CHECK: decl - %0 = tail call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %p, i32 1) ; [#uses=0] - ret void + %0 = atomicrmw sub i32* %p, i32 1 monotonic + ret void } -declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind - define void @sub5(i32* nocapture %p) nounwind ssp { entry: ; CHECK: sub5: ; CHECK: subl $2 - %0 = tail call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %p, i32 2) ; [#uses=0] - ret void + %0 = atomicrmw sub i32* %p, i32 2 monotonic + ret void } Modified: llvm/trunk/test/CodeGen/X86/coalescer-remat.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalescer-remat.ll?rev=140582&r1=140581&r2=140582&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/coalescer-remat.ll (original) +++ llvm/trunk/test/CodeGen/X86/coalescer-remat.ll Mon Sep 26 18:15:09 2011 @@ -1,15 +1,13 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep xor | count 3 - at val = internal global i64 0 ; [#uses=1] -@"\01LC" = internal constant [7 x i8] c"0x%lx\0A\00" ; <[7 x i8]*> [#uses=1] + at val = internal global i64 0 +@"\01LC" = internal constant [7 x i8] c"0x%lx\0A\00" define i32 @main() nounwind { entry: - %0 = tail call i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* @val, i64 0, i64 1) ; [#uses=1] - %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i64 0), i64 %0) nounwind ; [#uses=0] - ret i32 0 + %0 = cmpxchg i64* @val, i64 0, i64 1 monotonic + %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i64 0), i64 %0) nounwind + ret i32 0 } -declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64*, i64, i64) nounwind - declare i32 @printf(i8*, ...) nounwind Modified: llvm/trunk/test/CodeGen/X86/fast-isel-atomic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-atomic.ll?rev=140582&r1=140581&r2=140582&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-atomic.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-atomic.ll Mon Sep 26 18:15:09 2011 @@ -5,13 +5,11 @@ @sc = external global i8 @uc = external global i8 -declare i8 @llvm.atomic.load.and.i8.p0i8(i8* nocapture, i8) nounwind - define void @test_fetch_and_op() nounwind { entry: - %tmp40 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @sc, i8 11) ; [#uses=1] + %tmp40 = atomicrmw and i8* @sc, i8 11 monotonic store i8 %tmp40, i8* @sc - %tmp41 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @uc, i8 11) ; [#uses=1] + %tmp41 = atomicrmw and i8* @uc, i8 11 monotonic store i8 %tmp41, i8* @uc ret void } Modified: llvm/trunk/test/CodeGen/X86/lock-inst-encoding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lock-inst-encoding.ll?rev=140582&r1=140581&r2=140582&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/lock-inst-encoding.ll (original) +++ llvm/trunk/test/CodeGen/X86/lock-inst-encoding.ll Mon Sep 26 18:15:09 2011 @@ -7,48 +7,38 @@ ; CHECK: addq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x01,0x37] ; CHECK: ret define void @f1(i64* %a, i64 %b) nounwind { - call i64 @llvm.atomic.load.add.i64.p0i64(i64* %a, i64 %b) nounwind + %1 = atomicrmw add i64* %a, i64 %b monotonic ret void } -declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind - ; CHECK: f2: ; CHECK: subq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x29,0x37] ; CHECK: ret define void @f2(i64* %a, i64 %b) nounwind { - call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %a, i64 %b) nounwind + %1 = atomicrmw sub i64* %a, i64 %b monotonic ret void } -declare i64 @llvm.atomic.load.sub.i64.p0i64(i64* nocapture, i64) nounwind - ; CHECK: f3: ; CHECK: andq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x21,0x37] ; CHECK: ret define void @f3(i64* %a, i64 %b) nounwind { - call i64 @llvm.atomic.load.and.i64.p0i64(i64* %a, i64 %b) nounwind + %1 = atomicrmw and i64* %a, i64 %b monotonic ret void } -declare i64 @llvm.atomic.load.and.i64.p0i64(i64* nocapture, i64) nounwind - ; CHECK: f4: ; CHECK: orq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x09,0x37] ; CHECK: ret define void @f4(i64* %a, i64 %b) nounwind { - call i64 @llvm.atomic.load.or.i64.p0i64(i64* %a, i64 %b) nounwind + %1 = atomicrmw or i64* %a, i64 %b monotonic ret void } -declare i64 @llvm.atomic.load.or.i64.p0i64(i64* nocapture, i64) nounwind - ; CHECK: f5: ; CHECK: xorq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x31,0x37] ; CHECK: ret define void @f5(i64* %a, i64 %b) nounwind { - call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %a, i64 %b) nounwind + %1 = atomicrmw xor i64* %a, i64 %b monotonic ret void } - -declare i64 @llvm.atomic.load.xor.i64.p0i64(i64* nocapture, i64) nounwind From atrick at apple.com Mon Sep 26 18:35:26 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 26 Sep 2011 23:35:26 -0000 Subject: [llvm-commits] [llvm] r140583 - /llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <20110926233526.193522A6C12C@llvm.org> Author: atrick Date: Mon Sep 26 18:35:25 2011 New Revision: 140583 URL: http://llvm.org/viewvc/llvm-project?rev=140583&view=rev Log: LSR, one of the new Cost::isLoser() checks did not get merged in the previous checkin. Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=140583&r1=140582&r2=140583&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Mon Sep 26 18:35:25 2011 @@ -745,9 +745,13 @@ // Add the step value register, if it needs one. // TODO: The non-affine case isn't precisely modeled here. - if (!AR->isAffine() || !isa(AR->getOperand(1))) - if (!Regs.count(AR->getOperand(1))) + if (!AR->isAffine() || !isa(AR->getOperand(1))) { + if (!Regs.count(AR->getOperand(1))) { RateRegister(AR->getOperand(1), Regs, L, SE, DT); + if (isLoser()) + return; + } + } } ++NumRegs; From eli.friedman at gmail.com Mon Sep 26 19:17:29 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 27 Sep 2011 00:17:29 -0000 Subject: [llvm-commits] [llvm] r140585 - in /llvm/trunk/test/CodeGen: Thumb2/thumb2-barrier.ll X86/Atomics-32.ll X86/Atomics-64.ll X86/atomic_op.ll X86/barrier-sse.ll X86/barrier.ll X86/lfence.ll X86/membarrier.ll X86/mfence.ll X86/nofence.ll X86/sfence.ll Message-ID: <20110927001730.165D42A6C12C@llvm.org> Author: efriedma Date: Mon Sep 26 19:17:29 2011 New Revision: 140585 URL: http://llvm.org/viewvc/llvm-project?rev=140585&view=rev Log: Last batch of test conversions to new atomic instructions. Removed: llvm/trunk/test/CodeGen/Thumb2/thumb2-barrier.ll llvm/trunk/test/CodeGen/X86/Atomics-32.ll llvm/trunk/test/CodeGen/X86/nofence.ll Modified: llvm/trunk/test/CodeGen/X86/Atomics-64.ll llvm/trunk/test/CodeGen/X86/atomic_op.ll llvm/trunk/test/CodeGen/X86/barrier-sse.ll llvm/trunk/test/CodeGen/X86/barrier.ll llvm/trunk/test/CodeGen/X86/lfence.ll llvm/trunk/test/CodeGen/X86/membarrier.ll llvm/trunk/test/CodeGen/X86/mfence.ll llvm/trunk/test/CodeGen/X86/sfence.ll Removed: llvm/trunk/test/CodeGen/Thumb2/thumb2-barrier.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-barrier.ll?rev=140584&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-barrier.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-barrier.ll (removed) @@ -1,31 +0,0 @@ -; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s - -declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1) - -define void @t_st() { -; CHECK: t_st: -; CHECK: dmb st - call void @llvm.memory.barrier(i1 false, i1 false, i1 false, i1 true, i1 true) - ret void -} - -define void @t_sy() { -; CHECK: t_sy: -; CHECK: dmb sy - call void @llvm.memory.barrier(i1 true, i1 false, i1 false, i1 true, i1 true) - ret void -} - -define void @t_ishst() { -; CHECK: t_ishst: -; CHECK: dmb ishst - call void @llvm.memory.barrier(i1 false, i1 false, i1 false, i1 true, i1 false) - ret void -} - -define void @t_ish() { -; CHECK: t_ish: -; CHECK: dmb ish - call void @llvm.memory.barrier(i1 true, i1 false, i1 false, i1 true, i1 false) - ret void -} Removed: llvm/trunk/test/CodeGen/X86/Atomics-32.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/Atomics-32.ll?rev=140584&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/Atomics-32.ll (original) +++ llvm/trunk/test/CodeGen/X86/Atomics-32.ll (removed) @@ -1,818 +0,0 @@ -; RUN: llc < %s -march=x86 > %t -;; Note the 64-bit variants are not supported yet (in 32-bit mode). -; ModuleID = 'Atomics.c' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -target triple = "i386-apple-darwin8" - at sc = common global i8 0 ; [#uses=52] - at uc = common global i8 0 ; [#uses=100] - at ss = common global i16 0 ; [#uses=15] - at us = common global i16 0 ; [#uses=15] - at si = common global i32 0 ; [#uses=15] - at ui = common global i32 0 ; [#uses=23] - at sl = common global i32 0 ; [#uses=15] - at ul = common global i32 0 ; [#uses=15] - -define void @test_op_ignore() nounwind { -entry: - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 1 ) ; :0 [#uses=0] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 1 ) ; :1 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; :3 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; :5 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 1 ) ; :7 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 1 ) ; :9 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :10 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %10, i32 1 ) ; :11 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :12 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %12, i32 1 ) ; :13 [#uses=0] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 1 ) ; :14 [#uses=0] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 1 ) ; :15 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :16 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 1 ) ; :17 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :18 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 1 ) ; :19 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :20 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 1 ) ; :21 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :22 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 1 ) ; :23 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :24 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 1 ) ; :25 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :26 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 1 ) ; :27 [#uses=0] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 1 ) ; :28 [#uses=0] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 1 ) ; :29 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :30 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 1 ) ; :31 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :32 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 1 ) ; :33 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :34 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 1 ) ; :35 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :36 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 1 ) ; :37 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :38 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %38, i32 1 ) ; :39 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :40 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %40, i32 1 ) ; :41 [#uses=0] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 1 ) ; :42 [#uses=0] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 1 ) ; :43 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :44 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 1 ) ; :45 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :46 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 1 ) ; :47 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :48 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 1 ) ; :49 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :50 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 1 ) ; :51 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :52 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %52, i32 1 ) ; :53 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :54 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %54, i32 1 ) ; :55 [#uses=0] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 1 ) ; :56 [#uses=0] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 1 ) ; :57 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :58 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 1 ) ; :59 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :60 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 1 ) ; :61 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :62 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 1 ) ; :63 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :64 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 1 ) ; :65 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :66 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %66, i32 1 ) ; :67 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :68 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %68, i32 1 ) ; :69 [#uses=0] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 1 ) ; :70 [#uses=0] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 1 ) ; :71 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :72 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 1 ) ; :73 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :74 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 1 ) ; :75 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :76 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 1 ) ; :77 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :78 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 1 ) ; :79 [#uses=0] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :80 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %80, i32 1 ) ; :81 [#uses=0] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :82 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %82, i32 1 ) ; :83 [#uses=0] - br label %return - -return: ; preds = %entry - ret void -} - -declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind - -declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind - -declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind - -declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind - -declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind - -declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind - -define void @test_fetch_and_op() nounwind { -entry: - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 11 ) ; :0 [#uses=1] - store i8 %0, i8* @sc, align 1 - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 11 ) ; :1 [#uses=1] - store i8 %1, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 11 ) ; :3 [#uses=1] - store i16 %3, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 11 ) ; :5 [#uses=1] - store i16 %5, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 11 ) ; :7 [#uses=1] - store i32 %7, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 11 ) ; :9 [#uses=1] - store i32 %9, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :10 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %10, i32 11 ) ; :11 [#uses=1] - store i32 %11, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :12 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %12, i32 11 ) ; :13 [#uses=1] - store i32 %13, i32* @ul, align 4 - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 11 ) ; :14 [#uses=1] - store i8 %14, i8* @sc, align 1 - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 11 ) ; :15 [#uses=1] - store i8 %15, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :16 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 11 ) ; :17 [#uses=1] - store i16 %17, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :18 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 11 ) ; :19 [#uses=1] - store i16 %19, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :20 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 11 ) ; :21 [#uses=1] - store i32 %21, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :22 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 11 ) ; :23 [#uses=1] - store i32 %23, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :24 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 11 ) ; :25 [#uses=1] - store i32 %25, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :26 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 11 ) ; :27 [#uses=1] - store i32 %27, i32* @ul, align 4 - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 11 ) ; :28 [#uses=1] - store i8 %28, i8* @sc, align 1 - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 11 ) ; :29 [#uses=1] - store i8 %29, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :30 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 11 ) ; :31 [#uses=1] - store i16 %31, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :32 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 11 ) ; :33 [#uses=1] - store i16 %33, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :34 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 11 ) ; :35 [#uses=1] - store i32 %35, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :36 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 11 ) ; :37 [#uses=1] - store i32 %37, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :38 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %38, i32 11 ) ; :39 [#uses=1] - store i32 %39, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :40 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %40, i32 11 ) ; :41 [#uses=1] - store i32 %41, i32* @ul, align 4 - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 11 ) ; :42 [#uses=1] - store i8 %42, i8* @sc, align 1 - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 11 ) ; :43 [#uses=1] - store i8 %43, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :44 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 11 ) ; :45 [#uses=1] - store i16 %45, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :46 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 11 ) ; :47 [#uses=1] - store i16 %47, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :48 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 11 ) ; :49 [#uses=1] - store i32 %49, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :50 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 11 ) ; :51 [#uses=1] - store i32 %51, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :52 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %52, i32 11 ) ; :53 [#uses=1] - store i32 %53, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :54 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %54, i32 11 ) ; :55 [#uses=1] - store i32 %55, i32* @ul, align 4 - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 11 ) ; :56 [#uses=1] - store i8 %56, i8* @sc, align 1 - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 11 ) ; :57 [#uses=1] - store i8 %57, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :58 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 11 ) ; :59 [#uses=1] - store i16 %59, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :60 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 11 ) ; :61 [#uses=1] - store i16 %61, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :62 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 11 ) ; :63 [#uses=1] - store i32 %63, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :64 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 11 ) ; :65 [#uses=1] - store i32 %65, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :66 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %66, i32 11 ) ; :67 [#uses=1] - store i32 %67, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :68 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %68, i32 11 ) ; :69 [#uses=1] - store i32 %69, i32* @ul, align 4 - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 11 ) ; :70 [#uses=1] - store i8 %70, i8* @sc, align 1 - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 11 ) ; :71 [#uses=1] - store i8 %71, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :72 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 11 ) ; :73 [#uses=1] - store i16 %73, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :74 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 11 ) ; :75 [#uses=1] - store i16 %75, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :76 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 11 ) ; :77 [#uses=1] - store i32 %77, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :78 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 11 ) ; :79 [#uses=1] - store i32 %79, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :80 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %80, i32 11 ) ; :81 [#uses=1] - store i32 %81, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :82 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %82, i32 11 ) ; :83 [#uses=1] - store i32 %83, i32* @ul, align 4 - br label %return - -return: ; preds = %entry - ret void -} - -define void @test_op_and_fetch() nounwind { -entry: - load i8* @uc, align 1 ; :0 [#uses=1] - zext i8 %0 to i32 ; :1 [#uses=1] - trunc i32 %1 to i8 ; :2 [#uses=2] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 %2 ) ; :3 [#uses=1] - add i8 %3, %2 ; :4 [#uses=1] - store i8 %4, i8* @sc, align 1 - load i8* @uc, align 1 ; :5 [#uses=1] - zext i8 %5 to i32 ; :6 [#uses=1] - trunc i32 %6 to i8 ; :7 [#uses=2] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 %7 ) ; :8 [#uses=1] - add i8 %8, %7 ; :9 [#uses=1] - store i8 %9, i8* @uc, align 1 - load i8* @uc, align 1 ; :10 [#uses=1] - zext i8 %10 to i32 ; :11 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :12 [#uses=1] - trunc i32 %11 to i16 ; :13 [#uses=2] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %12, i16 %13 ) ; :14 [#uses=1] - add i16 %14, %13 ; :15 [#uses=1] - store i16 %15, i16* @ss, align 2 - load i8* @uc, align 1 ; :16 [#uses=1] - zext i8 %16 to i32 ; :17 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :18 [#uses=1] - trunc i32 %17 to i16 ; :19 [#uses=2] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %18, i16 %19 ) ; :20 [#uses=1] - add i16 %20, %19 ; :21 [#uses=1] - store i16 %21, i16* @us, align 2 - load i8* @uc, align 1 ; :22 [#uses=1] - zext i8 %22 to i32 ; :23 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :24 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %24, i32 %23 ) ; :25 [#uses=1] - add i32 %25, %23 ; :26 [#uses=1] - store i32 %26, i32* @si, align 4 - load i8* @uc, align 1 ; :27 [#uses=1] - zext i8 %27 to i32 ; :28 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :29 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %29, i32 %28 ) ; :30 [#uses=1] - add i32 %30, %28 ; :31 [#uses=1] - store i32 %31, i32* @ui, align 4 - load i8* @uc, align 1 ; :32 [#uses=1] - zext i8 %32 to i32 ; :33 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :34 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %34, i32 %33 ) ; :35 [#uses=1] - add i32 %35, %33 ; :36 [#uses=1] - store i32 %36, i32* @sl, align 4 - load i8* @uc, align 1 ; :37 [#uses=1] - zext i8 %37 to i32 ; :38 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :39 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %39, i32 %38 ) ; :40 [#uses=1] - add i32 %40, %38 ; :41 [#uses=1] - store i32 %41, i32* @ul, align 4 - load i8* @uc, align 1 ; :42 [#uses=1] - zext i8 %42 to i32 ; :43 [#uses=1] - trunc i32 %43 to i8 ; :44 [#uses=2] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 %44 ) ; :45 [#uses=1] - sub i8 %45, %44 ; :46 [#uses=1] - store i8 %46, i8* @sc, align 1 - load i8* @uc, align 1 ; :47 [#uses=1] - zext i8 %47 to i32 ; :48 [#uses=1] - trunc i32 %48 to i8 ; :49 [#uses=2] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 %49 ) ; :50 [#uses=1] - sub i8 %50, %49 ; :51 [#uses=1] - store i8 %51, i8* @uc, align 1 - load i8* @uc, align 1 ; :52 [#uses=1] - zext i8 %52 to i32 ; :53 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :54 [#uses=1] - trunc i32 %53 to i16 ; :55 [#uses=2] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %54, i16 %55 ) ; :56 [#uses=1] - sub i16 %56, %55 ; :57 [#uses=1] - store i16 %57, i16* @ss, align 2 - load i8* @uc, align 1 ; :58 [#uses=1] - zext i8 %58 to i32 ; :59 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :60 [#uses=1] - trunc i32 %59 to i16 ; :61 [#uses=2] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %60, i16 %61 ) ; :62 [#uses=1] - sub i16 %62, %61 ; :63 [#uses=1] - store i16 %63, i16* @us, align 2 - load i8* @uc, align 1 ; :64 [#uses=1] - zext i8 %64 to i32 ; :65 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :66 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %66, i32 %65 ) ; :67 [#uses=1] - sub i32 %67, %65 ; :68 [#uses=1] - store i32 %68, i32* @si, align 4 - load i8* @uc, align 1 ; :69 [#uses=1] - zext i8 %69 to i32 ; :70 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :71 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %71, i32 %70 ) ; :72 [#uses=1] - sub i32 %72, %70 ; :73 [#uses=1] - store i32 %73, i32* @ui, align 4 - load i8* @uc, align 1 ; :74 [#uses=1] - zext i8 %74 to i32 ; :75 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :76 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %76, i32 %75 ) ; :77 [#uses=1] - sub i32 %77, %75 ; :78 [#uses=1] - store i32 %78, i32* @sl, align 4 - load i8* @uc, align 1 ; :79 [#uses=1] - zext i8 %79 to i32 ; :80 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :81 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %81, i32 %80 ) ; :82 [#uses=1] - sub i32 %82, %80 ; :83 [#uses=1] - store i32 %83, i32* @ul, align 4 - load i8* @uc, align 1 ; :84 [#uses=1] - zext i8 %84 to i32 ; :85 [#uses=1] - trunc i32 %85 to i8 ; :86 [#uses=2] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 %86 ) ; :87 [#uses=1] - or i8 %87, %86 ; :88 [#uses=1] - store i8 %88, i8* @sc, align 1 - load i8* @uc, align 1 ; :89 [#uses=1] - zext i8 %89 to i32 ; :90 [#uses=1] - trunc i32 %90 to i8 ; :91 [#uses=2] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 %91 ) ; :92 [#uses=1] - or i8 %92, %91 ; :93 [#uses=1] - store i8 %93, i8* @uc, align 1 - load i8* @uc, align 1 ; :94 [#uses=1] - zext i8 %94 to i32 ; :95 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :96 [#uses=1] - trunc i32 %95 to i16 ; :97 [#uses=2] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %96, i16 %97 ) ; :98 [#uses=1] - or i16 %98, %97 ; :99 [#uses=1] - store i16 %99, i16* @ss, align 2 - load i8* @uc, align 1 ; :100 [#uses=1] - zext i8 %100 to i32 ; :101 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :102 [#uses=1] - trunc i32 %101 to i16 ; :103 [#uses=2] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %102, i16 %103 ) ; :104 [#uses=1] - or i16 %104, %103 ; :105 [#uses=1] - store i16 %105, i16* @us, align 2 - load i8* @uc, align 1 ; :106 [#uses=1] - zext i8 %106 to i32 ; :107 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :108 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %108, i32 %107 ) ; :109 [#uses=1] - or i32 %109, %107 ; :110 [#uses=1] - store i32 %110, i32* @si, align 4 - load i8* @uc, align 1 ; :111 [#uses=1] - zext i8 %111 to i32 ; :112 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :113 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %113, i32 %112 ) ; :114 [#uses=1] - or i32 %114, %112 ; :115 [#uses=1] - store i32 %115, i32* @ui, align 4 - load i8* @uc, align 1 ; :116 [#uses=1] - zext i8 %116 to i32 ; :117 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :118 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %118, i32 %117 ) ; :119 [#uses=1] - or i32 %119, %117 ; :120 [#uses=1] - store i32 %120, i32* @sl, align 4 - load i8* @uc, align 1 ; :121 [#uses=1] - zext i8 %121 to i32 ; :122 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :123 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %123, i32 %122 ) ; :124 [#uses=1] - or i32 %124, %122 ; :125 [#uses=1] - store i32 %125, i32* @ul, align 4 - load i8* @uc, align 1 ; :126 [#uses=1] - zext i8 %126 to i32 ; :127 [#uses=1] - trunc i32 %127 to i8 ; :128 [#uses=2] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 %128 ) ; :129 [#uses=1] - xor i8 %129, %128 ; :130 [#uses=1] - store i8 %130, i8* @sc, align 1 - load i8* @uc, align 1 ; :131 [#uses=1] - zext i8 %131 to i32 ; :132 [#uses=1] - trunc i32 %132 to i8 ; :133 [#uses=2] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 %133 ) ; :134 [#uses=1] - xor i8 %134, %133 ; :135 [#uses=1] - store i8 %135, i8* @uc, align 1 - load i8* @uc, align 1 ; :136 [#uses=1] - zext i8 %136 to i32 ; :137 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :138 [#uses=1] - trunc i32 %137 to i16 ; :139 [#uses=2] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %138, i16 %139 ) ; :140 [#uses=1] - xor i16 %140, %139 ; :141 [#uses=1] - store i16 %141, i16* @ss, align 2 - load i8* @uc, align 1 ; :142 [#uses=1] - zext i8 %142 to i32 ; :143 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :144 [#uses=1] - trunc i32 %143 to i16 ; :145 [#uses=2] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %144, i16 %145 ) ; :146 [#uses=1] - xor i16 %146, %145 ; :147 [#uses=1] - store i16 %147, i16* @us, align 2 - load i8* @uc, align 1 ; :148 [#uses=1] - zext i8 %148 to i32 ; :149 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :150 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %150, i32 %149 ) ; :151 [#uses=1] - xor i32 %151, %149 ; :152 [#uses=1] - store i32 %152, i32* @si, align 4 - load i8* @uc, align 1 ; :153 [#uses=1] - zext i8 %153 to i32 ; :154 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :155 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %155, i32 %154 ) ; :156 [#uses=1] - xor i32 %156, %154 ; :157 [#uses=1] - store i32 %157, i32* @ui, align 4 - load i8* @uc, align 1 ; :158 [#uses=1] - zext i8 %158 to i32 ; :159 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :160 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %160, i32 %159 ) ; :161 [#uses=1] - xor i32 %161, %159 ; :162 [#uses=1] - store i32 %162, i32* @sl, align 4 - load i8* @uc, align 1 ; :163 [#uses=1] - zext i8 %163 to i32 ; :164 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :165 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %165, i32 %164 ) ; :166 [#uses=1] - xor i32 %166, %164 ; :167 [#uses=1] - store i32 %167, i32* @ul, align 4 - load i8* @uc, align 1 ; :168 [#uses=1] - zext i8 %168 to i32 ; :169 [#uses=1] - trunc i32 %169 to i8 ; :170 [#uses=2] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 %170 ) ; :171 [#uses=1] - and i8 %171, %170 ; :172 [#uses=1] - store i8 %172, i8* @sc, align 1 - load i8* @uc, align 1 ; :173 [#uses=1] - zext i8 %173 to i32 ; :174 [#uses=1] - trunc i32 %174 to i8 ; :175 [#uses=2] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 %175 ) ; :176 [#uses=1] - and i8 %176, %175 ; :177 [#uses=1] - store i8 %177, i8* @uc, align 1 - load i8* @uc, align 1 ; :178 [#uses=1] - zext i8 %178 to i32 ; :179 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :180 [#uses=1] - trunc i32 %179 to i16 ; :181 [#uses=2] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %180, i16 %181 ) ; :182 [#uses=1] - and i16 %182, %181 ; :183 [#uses=1] - store i16 %183, i16* @ss, align 2 - load i8* @uc, align 1 ; :184 [#uses=1] - zext i8 %184 to i32 ; :185 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :186 [#uses=1] - trunc i32 %185 to i16 ; :187 [#uses=2] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %186, i16 %187 ) ; :188 [#uses=1] - and i16 %188, %187 ; :189 [#uses=1] - store i16 %189, i16* @us, align 2 - load i8* @uc, align 1 ; :190 [#uses=1] - zext i8 %190 to i32 ; :191 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :192 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %192, i32 %191 ) ; :193 [#uses=1] - and i32 %193, %191 ; :194 [#uses=1] - store i32 %194, i32* @si, align 4 - load i8* @uc, align 1 ; :195 [#uses=1] - zext i8 %195 to i32 ; :196 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :197 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %197, i32 %196 ) ; :198 [#uses=1] - and i32 %198, %196 ; :199 [#uses=1] - store i32 %199, i32* @ui, align 4 - load i8* @uc, align 1 ; :200 [#uses=1] - zext i8 %200 to i32 ; :201 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :202 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %202, i32 %201 ) ; :203 [#uses=1] - and i32 %203, %201 ; :204 [#uses=1] - store i32 %204, i32* @sl, align 4 - load i8* @uc, align 1 ; :205 [#uses=1] - zext i8 %205 to i32 ; :206 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :207 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %207, i32 %206 ) ; :208 [#uses=1] - and i32 %208, %206 ; :209 [#uses=1] - store i32 %209, i32* @ul, align 4 - load i8* @uc, align 1 ; :210 [#uses=1] - zext i8 %210 to i32 ; :211 [#uses=1] - trunc i32 %211 to i8 ; :212 [#uses=2] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 %212 ) ; :213 [#uses=1] - xor i8 %213, -1 ; :214 [#uses=1] - and i8 %214, %212 ; :215 [#uses=1] - store i8 %215, i8* @sc, align 1 - load i8* @uc, align 1 ; :216 [#uses=1] - zext i8 %216 to i32 ; :217 [#uses=1] - trunc i32 %217 to i8 ; :218 [#uses=2] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 %218 ) ; :219 [#uses=1] - xor i8 %219, -1 ; :220 [#uses=1] - and i8 %220, %218 ; :221 [#uses=1] - store i8 %221, i8* @uc, align 1 - load i8* @uc, align 1 ; :222 [#uses=1] - zext i8 %222 to i32 ; :223 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :224 [#uses=1] - trunc i32 %223 to i16 ; :225 [#uses=2] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %224, i16 %225 ) ; :226 [#uses=1] - xor i16 %226, -1 ; :227 [#uses=1] - and i16 %227, %225 ; :228 [#uses=1] - store i16 %228, i16* @ss, align 2 - load i8* @uc, align 1 ; :229 [#uses=1] - zext i8 %229 to i32 ; :230 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :231 [#uses=1] - trunc i32 %230 to i16 ; :232 [#uses=2] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %231, i16 %232 ) ; :233 [#uses=1] - xor i16 %233, -1 ; :234 [#uses=1] - and i16 %234, %232 ; :235 [#uses=1] - store i16 %235, i16* @us, align 2 - load i8* @uc, align 1 ; :236 [#uses=1] - zext i8 %236 to i32 ; :237 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :238 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %238, i32 %237 ) ; :239 [#uses=1] - xor i32 %239, -1 ; :240 [#uses=1] - and i32 %240, %237 ; :241 [#uses=1] - store i32 %241, i32* @si, align 4 - load i8* @uc, align 1 ; :242 [#uses=1] - zext i8 %242 to i32 ; :243 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :244 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %244, i32 %243 ) ; :245 [#uses=1] - xor i32 %245, -1 ; :246 [#uses=1] - and i32 %246, %243 ; :247 [#uses=1] - store i32 %247, i32* @ui, align 4 - load i8* @uc, align 1 ; :248 [#uses=1] - zext i8 %248 to i32 ; :249 [#uses=2] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :250 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %250, i32 %249 ) ; :251 [#uses=1] - xor i32 %251, -1 ; :252 [#uses=1] - and i32 %252, %249 ; :253 [#uses=1] - store i32 %253, i32* @sl, align 4 - load i8* @uc, align 1 ; :254 [#uses=1] - zext i8 %254 to i32 ; :255 [#uses=2] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :256 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %256, i32 %255 ) ; :257 [#uses=1] - xor i32 %257, -1 ; :258 [#uses=1] - and i32 %258, %255 ; :259 [#uses=1] - store i32 %259, i32* @ul, align 4 - br label %return - -return: ; preds = %entry - ret void -} - -define void @test_compare_and_swap() nounwind { -entry: - load i8* @sc, align 1 ; :0 [#uses=1] - zext i8 %0 to i32 ; :1 [#uses=1] - load i8* @uc, align 1 ; :2 [#uses=1] - zext i8 %2 to i32 ; :3 [#uses=1] - trunc i32 %3 to i8 ; :4 [#uses=1] - trunc i32 %1 to i8 ; :5 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %4, i8 %5 ) ; :6 [#uses=1] - store i8 %6, i8* @sc, align 1 - load i8* @sc, align 1 ; :7 [#uses=1] - zext i8 %7 to i32 ; :8 [#uses=1] - load i8* @uc, align 1 ; :9 [#uses=1] - zext i8 %9 to i32 ; :10 [#uses=1] - trunc i32 %10 to i8 ; :11 [#uses=1] - trunc i32 %8 to i8 ; :12 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %11, i8 %12 ) ; :13 [#uses=1] - store i8 %13, i8* @uc, align 1 - load i8* @sc, align 1 ; :14 [#uses=1] - sext i8 %14 to i16 ; :15 [#uses=1] - zext i16 %15 to i32 ; :16 [#uses=1] - load i8* @uc, align 1 ; :17 [#uses=1] - zext i8 %17 to i32 ; :18 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :19 [#uses=1] - trunc i32 %18 to i16 ; :20 [#uses=1] - trunc i32 %16 to i16 ; :21 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %19, i16 %20, i16 %21 ) ; :22 [#uses=1] - store i16 %22, i16* @ss, align 2 - load i8* @sc, align 1 ; :23 [#uses=1] - sext i8 %23 to i16 ; :24 [#uses=1] - zext i16 %24 to i32 ; :25 [#uses=1] - load i8* @uc, align 1 ; :26 [#uses=1] - zext i8 %26 to i32 ; :27 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :28 [#uses=1] - trunc i32 %27 to i16 ; :29 [#uses=1] - trunc i32 %25 to i16 ; :30 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %28, i16 %29, i16 %30 ) ; :31 [#uses=1] - store i16 %31, i16* @us, align 2 - load i8* @sc, align 1 ; :32 [#uses=1] - sext i8 %32 to i32 ; :33 [#uses=1] - load i8* @uc, align 1 ; :34 [#uses=1] - zext i8 %34 to i32 ; :35 [#uses=1] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :36 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %36, i32 %35, i32 %33 ) ; :37 [#uses=1] - store i32 %37, i32* @si, align 4 - load i8* @sc, align 1 ; :38 [#uses=1] - sext i8 %38 to i32 ; :39 [#uses=1] - load i8* @uc, align 1 ; :40 [#uses=1] - zext i8 %40 to i32 ; :41 [#uses=1] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :42 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %42, i32 %41, i32 %39 ) ; :43 [#uses=1] - store i32 %43, i32* @ui, align 4 - load i8* @sc, align 1 ; :44 [#uses=1] - sext i8 %44 to i32 ; :45 [#uses=1] - load i8* @uc, align 1 ; :46 [#uses=1] - zext i8 %46 to i32 ; :47 [#uses=1] - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :48 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %48, i32 %47, i32 %45 ) ; :49 [#uses=1] - store i32 %49, i32* @sl, align 4 - load i8* @sc, align 1 ; :50 [#uses=1] - sext i8 %50 to i32 ; :51 [#uses=1] - load i8* @uc, align 1 ; :52 [#uses=1] - zext i8 %52 to i32 ; :53 [#uses=1] - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :54 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %54, i32 %53, i32 %51 ) ; :55 [#uses=1] - store i32 %55, i32* @ul, align 4 - load i8* @sc, align 1 ; :56 [#uses=1] - zext i8 %56 to i32 ; :57 [#uses=1] - load i8* @uc, align 1 ; :58 [#uses=1] - zext i8 %58 to i32 ; :59 [#uses=1] - trunc i32 %59 to i8 ; :60 [#uses=2] - trunc i32 %57 to i8 ; :61 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %60, i8 %61 ) ; :62 [#uses=1] - icmp eq i8 %62, %60 ; :63 [#uses=1] - zext i1 %63 to i8 ; :64 [#uses=1] - zext i8 %64 to i32 ; :65 [#uses=1] - store i32 %65, i32* @ui, align 4 - load i8* @sc, align 1 ; :66 [#uses=1] - zext i8 %66 to i32 ; :67 [#uses=1] - load i8* @uc, align 1 ; :68 [#uses=1] - zext i8 %68 to i32 ; :69 [#uses=1] - trunc i32 %69 to i8 ; :70 [#uses=2] - trunc i32 %67 to i8 ; :71 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %70, i8 %71 ) ; :72 [#uses=1] - icmp eq i8 %72, %70 ; :73 [#uses=1] - zext i1 %73 to i8 ; :74 [#uses=1] - zext i8 %74 to i32 ; :75 [#uses=1] - store i32 %75, i32* @ui, align 4 - load i8* @sc, align 1 ; :76 [#uses=1] - sext i8 %76 to i16 ; :77 [#uses=1] - zext i16 %77 to i32 ; :78 [#uses=1] - load i8* @uc, align 1 ; :79 [#uses=1] - zext i8 %79 to i32 ; :80 [#uses=1] - trunc i32 %80 to i8 ; :81 [#uses=2] - trunc i32 %78 to i8 ; :82 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i16* @ss to i8*), i8 %81, i8 %82 ) ; :83 [#uses=1] - icmp eq i8 %83, %81 ; :84 [#uses=1] - zext i1 %84 to i8 ; :85 [#uses=1] - zext i8 %85 to i32 ; :86 [#uses=1] - store i32 %86, i32* @ui, align 4 - load i8* @sc, align 1 ; :87 [#uses=1] - sext i8 %87 to i16 ; :88 [#uses=1] - zext i16 %88 to i32 ; :89 [#uses=1] - load i8* @uc, align 1 ; :90 [#uses=1] - zext i8 %90 to i32 ; :91 [#uses=1] - trunc i32 %91 to i8 ; :92 [#uses=2] - trunc i32 %89 to i8 ; :93 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i16* @us to i8*), i8 %92, i8 %93 ) ; :94 [#uses=1] - icmp eq i8 %94, %92 ; :95 [#uses=1] - zext i1 %95 to i8 ; :96 [#uses=1] - zext i8 %96 to i32 ; :97 [#uses=1] - store i32 %97, i32* @ui, align 4 - load i8* @sc, align 1 ; :98 [#uses=1] - sext i8 %98 to i32 ; :99 [#uses=1] - load i8* @uc, align 1 ; :100 [#uses=1] - zext i8 %100 to i32 ; :101 [#uses=1] - trunc i32 %101 to i8 ; :102 [#uses=2] - trunc i32 %99 to i8 ; :103 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @si to i8*), i8 %102, i8 %103 ) ; :104 [#uses=1] - icmp eq i8 %104, %102 ; :105 [#uses=1] - zext i1 %105 to i8 ; :106 [#uses=1] - zext i8 %106 to i32 ; :107 [#uses=1] - store i32 %107, i32* @ui, align 4 - load i8* @sc, align 1 ; :108 [#uses=1] - sext i8 %108 to i32 ; :109 [#uses=1] - load i8* @uc, align 1 ; :110 [#uses=1] - zext i8 %110 to i32 ; :111 [#uses=1] - trunc i32 %111 to i8 ; :112 [#uses=2] - trunc i32 %109 to i8 ; :113 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @ui to i8*), i8 %112, i8 %113 ) ; :114 [#uses=1] - icmp eq i8 %114, %112 ; :115 [#uses=1] - zext i1 %115 to i8 ; :116 [#uses=1] - zext i8 %116 to i32 ; :117 [#uses=1] - store i32 %117, i32* @ui, align 4 - load i8* @sc, align 1 ; :118 [#uses=1] - sext i8 %118 to i32 ; :119 [#uses=1] - load i8* @uc, align 1 ; :120 [#uses=1] - zext i8 %120 to i32 ; :121 [#uses=1] - trunc i32 %121 to i8 ; :122 [#uses=2] - trunc i32 %119 to i8 ; :123 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @sl to i8*), i8 %122, i8 %123 ) ; :124 [#uses=1] - icmp eq i8 %124, %122 ; :125 [#uses=1] - zext i1 %125 to i8 ; :126 [#uses=1] - zext i8 %126 to i32 ; :127 [#uses=1] - store i32 %127, i32* @ui, align 4 - load i8* @sc, align 1 ; :128 [#uses=1] - sext i8 %128 to i32 ; :129 [#uses=1] - load i8* @uc, align 1 ; :130 [#uses=1] - zext i8 %130 to i32 ; :131 [#uses=1] - trunc i32 %131 to i8 ; :132 [#uses=2] - trunc i32 %129 to i8 ; :133 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @ul to i8*), i8 %132, i8 %133 ) ; :134 [#uses=1] - icmp eq i8 %134, %132 ; :135 [#uses=1] - zext i1 %135 to i8 ; :136 [#uses=1] - zext i8 %136 to i32 ; :137 [#uses=1] - store i32 %137, i32* @ui, align 4 - br label %return - -return: ; preds = %entry - ret void -} - -declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind - -declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind - -declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind - -define void @test_lock() nounwind { -entry: - call i8 @llvm.atomic.swap.i8.p0i8( i8* @sc, i8 1 ) ; :0 [#uses=1] - store i8 %0, i8* @sc, align 1 - call i8 @llvm.atomic.swap.i8.p0i8( i8* @uc, i8 1 ) ; :1 [#uses=1] - store i8 %1, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.swap.i16.p0i16( i16* %2, i16 1 ) ; :3 [#uses=1] - store i16 %3, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.swap.i16.p0i16( i16* %4, i16 1 ) ; :5 [#uses=1] - store i16 %5, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %6, i32 1 ) ; :7 [#uses=1] - store i32 %7, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %8, i32 1 ) ; :9 [#uses=1] - store i32 %9, i32* @ui, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :10 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %10, i32 1 ) ; :11 [#uses=1] - store i32 %11, i32* @sl, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :12 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %12, i32 1 ) ; :13 [#uses=1] - store i32 %13, i32* @ul, align 4 - call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true, i1 false ) - volatile store i8 0, i8* @sc, align 1 - volatile store i8 0, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :14 [#uses=1] - volatile store i16 0, i16* %14, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :15 [#uses=1] - volatile store i16 0, i16* %15, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :16 [#uses=1] - volatile store i32 0, i32* %16, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :17 [#uses=1] - volatile store i32 0, i32* %17, align 4 - bitcast i8* bitcast (i32* @sl to i8*) to i32* ; :18 [#uses=1] - volatile store i32 0, i32* %18, align 4 - bitcast i8* bitcast (i32* @ul to i8*) to i32* ; :19 [#uses=1] - volatile store i32 0, i32* %19, align 4 - br label %return - -return: ; preds = %entry - ret void -} - -declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind - -declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind Modified: llvm/trunk/test/CodeGen/X86/Atomics-64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/Atomics-64.ll?rev=140585&r1=140584&r2=140585&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/Atomics-64.ll (original) +++ llvm/trunk/test/CodeGen/X86/Atomics-64.ll Mon Sep 26 19:17:29 2011 @@ -1,1015 +1,950 @@ ; RUN: llc < %s -march=x86-64 > %t -; ModuleID = 'Atomics.c' +; RUN: llc < %s -march=x86 > %t target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin8" - at sc = common global i8 0 ; [#uses=56] - at uc = common global i8 0 ; [#uses=116] - at ss = common global i16 0 ; [#uses=15] - at us = common global i16 0 ; [#uses=15] - at si = common global i32 0 ; [#uses=15] - at ui = common global i32 0 ; [#uses=25] - at sl = common global i64 0 ; [#uses=15] - at ul = common global i64 0 ; [#uses=15] - at sll = common global i64 0 ; [#uses=15] - at ull = common global i64 0 ; [#uses=15] + + at sc = common global i8 0 + at uc = common global i8 0 + at ss = common global i16 0 + at us = common global i16 0 + at si = common global i32 0 + at ui = common global i32 0 + at sl = common global i64 0 + at ul = common global i64 0 + at sll = common global i64 0 + at ull = common global i64 0 define void @test_op_ignore() nounwind { entry: - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 1 ) ; :0 [#uses=0] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 1 ) ; :1 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; :3 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; :5 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 1 ) ; :7 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 1 ) ; :9 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :10 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %10, i64 1 ) ; :11 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :12 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %12, i64 1 ) ; :13 [#uses=0] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :14 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %14, i64 1 ) ; :15 [#uses=0] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :16 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %16, i64 1 ) ; :17 [#uses=0] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 1 ) ; :18 [#uses=0] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 1 ) ; :19 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :20 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %20, i16 1 ) ; :21 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :22 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %22, i16 1 ) ; :23 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :24 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 1 ) ; :25 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :26 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 1 ) ; :27 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :28 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %28, i64 1 ) ; :29 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :30 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %30, i64 1 ) ; :31 [#uses=0] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :32 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %32, i64 1 ) ; :33 [#uses=0] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :34 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %34, i64 1 ) ; :35 [#uses=0] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 1 ) ; :36 [#uses=0] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 1 ) ; :37 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :38 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %38, i16 1 ) ; :39 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :40 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %40, i16 1 ) ; :41 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :42 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %42, i32 1 ) ; :43 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :44 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %44, i32 1 ) ; :45 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :46 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %46, i64 1 ) ; :47 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :48 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %48, i64 1 ) ; :49 [#uses=0] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :50 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %50, i64 1 ) ; :51 [#uses=0] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :52 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %52, i64 1 ) ; :53 [#uses=0] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 1 ) ; :54 [#uses=0] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 1 ) ; :55 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :56 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %56, i16 1 ) ; :57 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :58 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %58, i16 1 ) ; :59 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :60 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %60, i32 1 ) ; :61 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :62 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %62, i32 1 ) ; :63 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :64 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %64, i64 1 ) ; :65 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :66 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %66, i64 1 ) ; :67 [#uses=0] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :68 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %68, i64 1 ) ; :69 [#uses=0] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :70 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %70, i64 1 ) ; :71 [#uses=0] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 1 ) ; :72 [#uses=0] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 1 ) ; :73 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :74 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %74, i16 1 ) ; :75 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :76 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %76, i16 1 ) ; :77 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :78 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %78, i32 1 ) ; :79 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :80 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %80, i32 1 ) ; :81 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :82 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %82, i64 1 ) ; :83 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :84 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %84, i64 1 ) ; :85 [#uses=0] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :86 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %86, i64 1 ) ; :87 [#uses=0] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :88 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %88, i64 1 ) ; :89 [#uses=0] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 1 ) ; :90 [#uses=0] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 1 ) ; :91 [#uses=0] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :92 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %92, i16 1 ) ; :93 [#uses=0] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :94 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %94, i16 1 ) ; :95 [#uses=0] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :96 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %96, i32 1 ) ; :97 [#uses=0] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :98 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %98, i32 1 ) ; :99 [#uses=0] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :100 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %100, i64 1 ) ; :101 [#uses=0] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :102 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %102, i64 1 ) ; :103 [#uses=0] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :104 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %104, i64 1 ) ; :105 [#uses=0] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :106 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %106, i64 1 ) ; :107 [#uses=0] - br label %return + %0 = atomicrmw add i8* @sc, i8 1 monotonic + %1 = atomicrmw add i8* @uc, i8 1 monotonic + %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %3 = atomicrmw add i16* %2, i16 1 monotonic + %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %5 = atomicrmw add i16* %4, i16 1 monotonic + %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %7 = atomicrmw add i32* %6, i32 1 monotonic + %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %9 = atomicrmw add i32* %8, i32 1 monotonic + %10 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %11 = atomicrmw add i64* %10, i64 1 monotonic + %12 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %13 = atomicrmw add i64* %12, i64 1 monotonic + %14 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %15 = atomicrmw add i64* %14, i64 1 monotonic + %16 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %17 = atomicrmw add i64* %16, i64 1 monotonic + %18 = atomicrmw sub i8* @sc, i8 1 monotonic + %19 = atomicrmw sub i8* @uc, i8 1 monotonic + %20 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %21 = atomicrmw sub i16* %20, i16 1 monotonic + %22 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %23 = atomicrmw sub i16* %22, i16 1 monotonic + %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %25 = atomicrmw sub i32* %24, i32 1 monotonic + %26 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %27 = atomicrmw sub i32* %26, i32 1 monotonic + %28 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %29 = atomicrmw sub i64* %28, i64 1 monotonic + %30 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %31 = atomicrmw sub i64* %30, i64 1 monotonic + %32 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %33 = atomicrmw sub i64* %32, i64 1 monotonic + %34 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %35 = atomicrmw sub i64* %34, i64 1 monotonic + %36 = atomicrmw or i8* @sc, i8 1 monotonic + %37 = atomicrmw or i8* @uc, i8 1 monotonic + %38 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %39 = atomicrmw or i16* %38, i16 1 monotonic + %40 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %41 = atomicrmw or i16* %40, i16 1 monotonic + %42 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %43 = atomicrmw or i32* %42, i32 1 monotonic + %44 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %45 = atomicrmw or i32* %44, i32 1 monotonic + %46 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %47 = atomicrmw or i64* %46, i64 1 monotonic + %48 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %49 = atomicrmw or i64* %48, i64 1 monotonic + %50 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %51 = atomicrmw or i64* %50, i64 1 monotonic + %52 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %53 = atomicrmw or i64* %52, i64 1 monotonic + %54 = atomicrmw xor i8* @sc, i8 1 monotonic + %55 = atomicrmw xor i8* @uc, i8 1 monotonic + %56 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %57 = atomicrmw xor i16* %56, i16 1 monotonic + %58 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %59 = atomicrmw xor i16* %58, i16 1 monotonic + %60 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %61 = atomicrmw xor i32* %60, i32 1 monotonic + %62 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %63 = atomicrmw xor i32* %62, i32 1 monotonic + %64 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %65 = atomicrmw xor i64* %64, i64 1 monotonic + %66 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %67 = atomicrmw xor i64* %66, i64 1 monotonic + %68 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %69 = atomicrmw xor i64* %68, i64 1 monotonic + %70 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %71 = atomicrmw xor i64* %70, i64 1 monotonic + %72 = atomicrmw and i8* @sc, i8 1 monotonic + %73 = atomicrmw and i8* @uc, i8 1 monotonic + %74 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %75 = atomicrmw and i16* %74, i16 1 monotonic + %76 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %77 = atomicrmw and i16* %76, i16 1 monotonic + %78 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %79 = atomicrmw and i32* %78, i32 1 monotonic + %80 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %81 = atomicrmw and i32* %80, i32 1 monotonic + %82 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %83 = atomicrmw and i64* %82, i64 1 monotonic + %84 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %85 = atomicrmw and i64* %84, i64 1 monotonic + %86 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %87 = atomicrmw and i64* %86, i64 1 monotonic + %88 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %89 = atomicrmw and i64* %88, i64 1 monotonic + %90 = atomicrmw nand i8* @sc, i8 1 monotonic + %91 = atomicrmw nand i8* @uc, i8 1 monotonic + %92 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %93 = atomicrmw nand i16* %92, i16 1 monotonic + %94 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %95 = atomicrmw nand i16* %94, i16 1 monotonic + %96 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %97 = atomicrmw nand i32* %96, i32 1 monotonic + %98 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %99 = atomicrmw nand i32* %98, i32 1 monotonic + %100 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %101 = atomicrmw nand i64* %100, i64 1 monotonic + %102 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %103 = atomicrmw nand i64* %102, i64 1 monotonic + %104 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %105 = atomicrmw nand i64* %104, i64 1 monotonic + %106 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %107 = atomicrmw nand i64* %106, i64 1 monotonic + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } -declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.add.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.sub.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.or.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.xor.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.and.i64.p0i64(i64*, i64) nounwind - -declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.load.nand.i64.p0i64(i64*, i64) nounwind - define void @test_fetch_and_op() nounwind { entry: - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 11 ) ; :0 [#uses=1] - store i8 %0, i8* @sc, align 1 - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 11 ) ; :1 [#uses=1] - store i8 %1, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 11 ) ; :3 [#uses=1] - store i16 %3, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 11 ) ; :5 [#uses=1] - store i16 %5, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 11 ) ; :7 [#uses=1] - store i32 %7, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 11 ) ; :9 [#uses=1] - store i32 %9, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :10 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %10, i64 11 ) ; :11 [#uses=1] - store i64 %11, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :12 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %12, i64 11 ) ; :13 [#uses=1] - store i64 %13, i64* @ul, align 8 - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :14 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %14, i64 11 ) ; :15 [#uses=1] - store i64 %15, i64* @sll, align 8 - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :16 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %16, i64 11 ) ; :17 [#uses=1] - store i64 %17, i64* @ull, align 8 - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 11 ) ; :18 [#uses=1] - store i8 %18, i8* @sc, align 1 - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 11 ) ; :19 [#uses=1] - store i8 %19, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :20 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %20, i16 11 ) ; :21 [#uses=1] - store i16 %21, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :22 [#uses=1] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %22, i16 11 ) ; :23 [#uses=1] - store i16 %23, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :24 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 11 ) ; :25 [#uses=1] - store i32 %25, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :26 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 11 ) ; :27 [#uses=1] - store i32 %27, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :28 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %28, i64 11 ) ; :29 [#uses=1] - store i64 %29, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :30 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %30, i64 11 ) ; :31 [#uses=1] - store i64 %31, i64* @ul, align 8 - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :32 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %32, i64 11 ) ; :33 [#uses=1] - store i64 %33, i64* @sll, align 8 - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :34 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %34, i64 11 ) ; :35 [#uses=1] - store i64 %35, i64* @ull, align 8 - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 11 ) ; :36 [#uses=1] - store i8 %36, i8* @sc, align 1 - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 11 ) ; :37 [#uses=1] - store i8 %37, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :38 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %38, i16 11 ) ; :39 [#uses=1] - store i16 %39, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :40 [#uses=1] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %40, i16 11 ) ; :41 [#uses=1] - store i16 %41, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :42 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %42, i32 11 ) ; :43 [#uses=1] - store i32 %43, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :44 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %44, i32 11 ) ; :45 [#uses=1] - store i32 %45, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :46 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %46, i64 11 ) ; :47 [#uses=1] - store i64 %47, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :48 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %48, i64 11 ) ; :49 [#uses=1] - store i64 %49, i64* @ul, align 8 - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :50 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %50, i64 11 ) ; :51 [#uses=1] - store i64 %51, i64* @sll, align 8 - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :52 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %52, i64 11 ) ; :53 [#uses=1] - store i64 %53, i64* @ull, align 8 - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 11 ) ; :54 [#uses=1] - store i8 %54, i8* @sc, align 1 - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 11 ) ; :55 [#uses=1] - store i8 %55, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :56 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %56, i16 11 ) ; :57 [#uses=1] - store i16 %57, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :58 [#uses=1] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %58, i16 11 ) ; :59 [#uses=1] - store i16 %59, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :60 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %60, i32 11 ) ; :61 [#uses=1] - store i32 %61, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :62 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %62, i32 11 ) ; :63 [#uses=1] - store i32 %63, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :64 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %64, i64 11 ) ; :65 [#uses=1] - store i64 %65, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :66 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %66, i64 11 ) ; :67 [#uses=1] - store i64 %67, i64* @ul, align 8 - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :68 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %68, i64 11 ) ; :69 [#uses=1] - store i64 %69, i64* @sll, align 8 - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :70 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %70, i64 11 ) ; :71 [#uses=1] - store i64 %71, i64* @ull, align 8 - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 11 ) ; :72 [#uses=1] - store i8 %72, i8* @sc, align 1 - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 11 ) ; :73 [#uses=1] - store i8 %73, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :74 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %74, i16 11 ) ; :75 [#uses=1] - store i16 %75, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :76 [#uses=1] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %76, i16 11 ) ; :77 [#uses=1] - store i16 %77, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :78 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %78, i32 11 ) ; :79 [#uses=1] - store i32 %79, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :80 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %80, i32 11 ) ; :81 [#uses=1] - store i32 %81, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :82 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %82, i64 11 ) ; :83 [#uses=1] - store i64 %83, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :84 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %84, i64 11 ) ; :85 [#uses=1] - store i64 %85, i64* @ul, align 8 - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :86 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %86, i64 11 ) ; :87 [#uses=1] - store i64 %87, i64* @sll, align 8 - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :88 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %88, i64 11 ) ; :89 [#uses=1] - store i64 %89, i64* @ull, align 8 - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 11 ) ; :90 [#uses=1] - store i8 %90, i8* @sc, align 1 - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 11 ) ; :91 [#uses=1] - store i8 %91, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :92 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %92, i16 11 ) ; :93 [#uses=1] - store i16 %93, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :94 [#uses=1] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %94, i16 11 ) ; :95 [#uses=1] - store i16 %95, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :96 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %96, i32 11 ) ; :97 [#uses=1] - store i32 %97, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :98 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %98, i32 11 ) ; :99 [#uses=1] - store i32 %99, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :100 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %100, i64 11 ) ; :101 [#uses=1] - store i64 %101, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :102 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %102, i64 11 ) ; :103 [#uses=1] - store i64 %103, i64* @ul, align 8 - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :104 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %104, i64 11 ) ; :105 [#uses=1] - store i64 %105, i64* @sll, align 8 - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :106 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %106, i64 11 ) ; :107 [#uses=1] - store i64 %107, i64* @ull, align 8 - br label %return + %0 = atomicrmw add i8* @sc, i8 11 monotonic + store i8 %0, i8* @sc, align 1 + %1 = atomicrmw add i8* @uc, i8 11 monotonic + store i8 %1, i8* @uc, align 1 + %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %3 = atomicrmw add i16* %2, i16 11 monotonic + store i16 %3, i16* @ss, align 2 + %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %5 = atomicrmw add i16* %4, i16 11 monotonic + store i16 %5, i16* @us, align 2 + %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %7 = atomicrmw add i32* %6, i32 11 monotonic + store i32 %7, i32* @si, align 4 + %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %9 = atomicrmw add i32* %8, i32 11 monotonic + store i32 %9, i32* @ui, align 4 + %10 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %11 = atomicrmw add i64* %10, i64 11 monotonic + store i64 %11, i64* @sl, align 8 + %12 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %13 = atomicrmw add i64* %12, i64 11 monotonic + store i64 %13, i64* @ul, align 8 + %14 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %15 = atomicrmw add i64* %14, i64 11 monotonic + store i64 %15, i64* @sll, align 8 + %16 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %17 = atomicrmw add i64* %16, i64 11 monotonic + store i64 %17, i64* @ull, align 8 + %18 = atomicrmw sub i8* @sc, i8 11 monotonic + store i8 %18, i8* @sc, align 1 + %19 = atomicrmw sub i8* @uc, i8 11 monotonic + store i8 %19, i8* @uc, align 1 + %20 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %21 = atomicrmw sub i16* %20, i16 11 monotonic + store i16 %21, i16* @ss, align 2 + %22 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %23 = atomicrmw sub i16* %22, i16 11 monotonic + store i16 %23, i16* @us, align 2 + %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %25 = atomicrmw sub i32* %24, i32 11 monotonic + store i32 %25, i32* @si, align 4 + %26 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %27 = atomicrmw sub i32* %26, i32 11 monotonic + store i32 %27, i32* @ui, align 4 + %28 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %29 = atomicrmw sub i64* %28, i64 11 monotonic + store i64 %29, i64* @sl, align 8 + %30 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %31 = atomicrmw sub i64* %30, i64 11 monotonic + store i64 %31, i64* @ul, align 8 + %32 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %33 = atomicrmw sub i64* %32, i64 11 monotonic + store i64 %33, i64* @sll, align 8 + %34 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %35 = atomicrmw sub i64* %34, i64 11 monotonic + store i64 %35, i64* @ull, align 8 + %36 = atomicrmw or i8* @sc, i8 11 monotonic + store i8 %36, i8* @sc, align 1 + %37 = atomicrmw or i8* @uc, i8 11 monotonic + store i8 %37, i8* @uc, align 1 + %38 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %39 = atomicrmw or i16* %38, i16 11 monotonic + store i16 %39, i16* @ss, align 2 + %40 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %41 = atomicrmw or i16* %40, i16 11 monotonic + store i16 %41, i16* @us, align 2 + %42 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %43 = atomicrmw or i32* %42, i32 11 monotonic + store i32 %43, i32* @si, align 4 + %44 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %45 = atomicrmw or i32* %44, i32 11 monotonic + store i32 %45, i32* @ui, align 4 + %46 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %47 = atomicrmw or i64* %46, i64 11 monotonic + store i64 %47, i64* @sl, align 8 + %48 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %49 = atomicrmw or i64* %48, i64 11 monotonic + store i64 %49, i64* @ul, align 8 + %50 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %51 = atomicrmw or i64* %50, i64 11 monotonic + store i64 %51, i64* @sll, align 8 + %52 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %53 = atomicrmw or i64* %52, i64 11 monotonic + store i64 %53, i64* @ull, align 8 + %54 = atomicrmw xor i8* @sc, i8 11 monotonic + store i8 %54, i8* @sc, align 1 + %55 = atomicrmw xor i8* @uc, i8 11 monotonic + store i8 %55, i8* @uc, align 1 + %56 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %57 = atomicrmw xor i16* %56, i16 11 monotonic + store i16 %57, i16* @ss, align 2 + %58 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %59 = atomicrmw xor i16* %58, i16 11 monotonic + store i16 %59, i16* @us, align 2 + %60 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %61 = atomicrmw xor i32* %60, i32 11 monotonic + store i32 %61, i32* @si, align 4 + %62 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %63 = atomicrmw xor i32* %62, i32 11 monotonic + store i32 %63, i32* @ui, align 4 + %64 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %65 = atomicrmw xor i64* %64, i64 11 monotonic + store i64 %65, i64* @sl, align 8 + %66 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %67 = atomicrmw xor i64* %66, i64 11 monotonic + store i64 %67, i64* @ul, align 8 + %68 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %69 = atomicrmw xor i64* %68, i64 11 monotonic + store i64 %69, i64* @sll, align 8 + %70 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %71 = atomicrmw xor i64* %70, i64 11 monotonic + store i64 %71, i64* @ull, align 8 + %72 = atomicrmw and i8* @sc, i8 11 monotonic + store i8 %72, i8* @sc, align 1 + %73 = atomicrmw and i8* @uc, i8 11 monotonic + store i8 %73, i8* @uc, align 1 + %74 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %75 = atomicrmw and i16* %74, i16 11 monotonic + store i16 %75, i16* @ss, align 2 + %76 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %77 = atomicrmw and i16* %76, i16 11 monotonic + store i16 %77, i16* @us, align 2 + %78 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %79 = atomicrmw and i32* %78, i32 11 monotonic + store i32 %79, i32* @si, align 4 + %80 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %81 = atomicrmw and i32* %80, i32 11 monotonic + store i32 %81, i32* @ui, align 4 + %82 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %83 = atomicrmw and i64* %82, i64 11 monotonic + store i64 %83, i64* @sl, align 8 + %84 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %85 = atomicrmw and i64* %84, i64 11 monotonic + store i64 %85, i64* @ul, align 8 + %86 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %87 = atomicrmw and i64* %86, i64 11 monotonic + store i64 %87, i64* @sll, align 8 + %88 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %89 = atomicrmw and i64* %88, i64 11 monotonic + store i64 %89, i64* @ull, align 8 + %90 = atomicrmw nand i8* @sc, i8 11 monotonic + store i8 %90, i8* @sc, align 1 + %91 = atomicrmw nand i8* @uc, i8 11 monotonic + store i8 %91, i8* @uc, align 1 + %92 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %93 = atomicrmw nand i16* %92, i16 11 monotonic + store i16 %93, i16* @ss, align 2 + %94 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %95 = atomicrmw nand i16* %94, i16 11 monotonic + store i16 %95, i16* @us, align 2 + %96 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %97 = atomicrmw nand i32* %96, i32 11 monotonic + store i32 %97, i32* @si, align 4 + %98 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %99 = atomicrmw nand i32* %98, i32 11 monotonic + store i32 %99, i32* @ui, align 4 + %100 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %101 = atomicrmw nand i64* %100, i64 11 monotonic + store i64 %101, i64* @sl, align 8 + %102 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %103 = atomicrmw nand i64* %102, i64 11 monotonic + store i64 %103, i64* @ul, align 8 + %104 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %105 = atomicrmw nand i64* %104, i64 11 monotonic + store i64 %105, i64* @sll, align 8 + %106 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %107 = atomicrmw nand i64* %106, i64 11 monotonic + store i64 %107, i64* @ull, align 8 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } define void @test_op_and_fetch() nounwind { entry: - load i8* @uc, align 1 ; :0 [#uses=1] - zext i8 %0 to i32 ; :1 [#uses=1] - trunc i32 %1 to i8 ; :2 [#uses=2] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 %2 ) ; :3 [#uses=1] - add i8 %3, %2 ; :4 [#uses=1] - store i8 %4, i8* @sc, align 1 - load i8* @uc, align 1 ; :5 [#uses=1] - zext i8 %5 to i32 ; :6 [#uses=1] - trunc i32 %6 to i8 ; :7 [#uses=2] - call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 %7 ) ; :8 [#uses=1] - add i8 %8, %7 ; :9 [#uses=1] - store i8 %9, i8* @uc, align 1 - load i8* @uc, align 1 ; :10 [#uses=1] - zext i8 %10 to i32 ; :11 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :12 [#uses=1] - trunc i32 %11 to i16 ; :13 [#uses=2] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %12, i16 %13 ) ; :14 [#uses=1] - add i16 %14, %13 ; :15 [#uses=1] - store i16 %15, i16* @ss, align 2 - load i8* @uc, align 1 ; :16 [#uses=1] - zext i8 %16 to i32 ; :17 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :18 [#uses=1] - trunc i32 %17 to i16 ; :19 [#uses=2] - call i16 @llvm.atomic.load.add.i16.p0i16( i16* %18, i16 %19 ) ; :20 [#uses=1] - add i16 %20, %19 ; :21 [#uses=1] - store i16 %21, i16* @us, align 2 - load i8* @uc, align 1 ; :22 [#uses=1] - zext i8 %22 to i32 ; :23 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :24 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %24, i32 %23 ) ; :25 [#uses=1] - add i32 %25, %23 ; :26 [#uses=1] - store i32 %26, i32* @si, align 4 - load i8* @uc, align 1 ; :27 [#uses=1] - zext i8 %27 to i32 ; :28 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :29 [#uses=1] - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %29, i32 %28 ) ; :30 [#uses=1] - add i32 %30, %28 ; :31 [#uses=1] - store i32 %31, i32* @ui, align 4 - load i8* @uc, align 1 ; :32 [#uses=1] - zext i8 %32 to i64 ; :33 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :34 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %34, i64 %33 ) ; :35 [#uses=1] - add i64 %35, %33 ; :36 [#uses=1] - store i64 %36, i64* @sl, align 8 - load i8* @uc, align 1 ; :37 [#uses=1] - zext i8 %37 to i64 ; :38 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :39 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %39, i64 %38 ) ; :40 [#uses=1] - add i64 %40, %38 ; :41 [#uses=1] - store i64 %41, i64* @ul, align 8 - load i8* @uc, align 1 ; :42 [#uses=1] - zext i8 %42 to i64 ; :43 [#uses=2] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :44 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %44, i64 %43 ) ; :45 [#uses=1] - add i64 %45, %43 ; :46 [#uses=1] - store i64 %46, i64* @sll, align 8 - load i8* @uc, align 1 ; :47 [#uses=1] - zext i8 %47 to i64 ; :48 [#uses=2] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :49 [#uses=1] - call i64 @llvm.atomic.load.add.i64.p0i64( i64* %49, i64 %48 ) ; :50 [#uses=1] - add i64 %50, %48 ; :51 [#uses=1] - store i64 %51, i64* @ull, align 8 - load i8* @uc, align 1 ; :52 [#uses=1] - zext i8 %52 to i32 ; :53 [#uses=1] - trunc i32 %53 to i8 ; :54 [#uses=2] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 %54 ) ; :55 [#uses=1] - sub i8 %55, %54 ; :56 [#uses=1] - store i8 %56, i8* @sc, align 1 - load i8* @uc, align 1 ; :57 [#uses=1] - zext i8 %57 to i32 ; :58 [#uses=1] - trunc i32 %58 to i8 ; :59 [#uses=2] - call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 %59 ) ; :60 [#uses=1] - sub i8 %60, %59 ; :61 [#uses=1] - store i8 %61, i8* @uc, align 1 - load i8* @uc, align 1 ; :62 [#uses=1] - zext i8 %62 to i32 ; :63 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :64 [#uses=1] - trunc i32 %63 to i16 ; :65 [#uses=2] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %64, i16 %65 ) ; :66 [#uses=1] - sub i16 %66, %65 ; :67 [#uses=1] - store i16 %67, i16* @ss, align 2 - load i8* @uc, align 1 ; :68 [#uses=1] - zext i8 %68 to i32 ; :69 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :70 [#uses=1] - trunc i32 %69 to i16 ; :71 [#uses=2] - call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %70, i16 %71 ) ; :72 [#uses=1] - sub i16 %72, %71 ; :73 [#uses=1] - store i16 %73, i16* @us, align 2 - load i8* @uc, align 1 ; :74 [#uses=1] - zext i8 %74 to i32 ; :75 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :76 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %76, i32 %75 ) ; :77 [#uses=1] - sub i32 %77, %75 ; :78 [#uses=1] - store i32 %78, i32* @si, align 4 - load i8* @uc, align 1 ; :79 [#uses=1] - zext i8 %79 to i32 ; :80 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :81 [#uses=1] - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %81, i32 %80 ) ; :82 [#uses=1] - sub i32 %82, %80 ; :83 [#uses=1] - store i32 %83, i32* @ui, align 4 - load i8* @uc, align 1 ; :84 [#uses=1] - zext i8 %84 to i64 ; :85 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :86 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %86, i64 %85 ) ; :87 [#uses=1] - sub i64 %87, %85 ; :88 [#uses=1] - store i64 %88, i64* @sl, align 8 - load i8* @uc, align 1 ; :89 [#uses=1] - zext i8 %89 to i64 ; :90 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :91 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %91, i64 %90 ) ; :92 [#uses=1] - sub i64 %92, %90 ; :93 [#uses=1] - store i64 %93, i64* @ul, align 8 - load i8* @uc, align 1 ; :94 [#uses=1] - zext i8 %94 to i64 ; :95 [#uses=2] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :96 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %96, i64 %95 ) ; :97 [#uses=1] - sub i64 %97, %95 ; :98 [#uses=1] - store i64 %98, i64* @sll, align 8 - load i8* @uc, align 1 ; :99 [#uses=1] - zext i8 %99 to i64 ; :100 [#uses=2] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :101 [#uses=1] - call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %101, i64 %100 ) ; :102 [#uses=1] - sub i64 %102, %100 ; :103 [#uses=1] - store i64 %103, i64* @ull, align 8 - load i8* @uc, align 1 ; :104 [#uses=1] - zext i8 %104 to i32 ; :105 [#uses=1] - trunc i32 %105 to i8 ; :106 [#uses=2] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 %106 ) ; :107 [#uses=1] - or i8 %107, %106 ; :108 [#uses=1] - store i8 %108, i8* @sc, align 1 - load i8* @uc, align 1 ; :109 [#uses=1] - zext i8 %109 to i32 ; :110 [#uses=1] - trunc i32 %110 to i8 ; :111 [#uses=2] - call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 %111 ) ; :112 [#uses=1] - or i8 %112, %111 ; :113 [#uses=1] - store i8 %113, i8* @uc, align 1 - load i8* @uc, align 1 ; :114 [#uses=1] - zext i8 %114 to i32 ; :115 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :116 [#uses=1] - trunc i32 %115 to i16 ; :117 [#uses=2] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %116, i16 %117 ) ; :118 [#uses=1] - or i16 %118, %117 ; :119 [#uses=1] - store i16 %119, i16* @ss, align 2 - load i8* @uc, align 1 ; :120 [#uses=1] - zext i8 %120 to i32 ; :121 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :122 [#uses=1] - trunc i32 %121 to i16 ; :123 [#uses=2] - call i16 @llvm.atomic.load.or.i16.p0i16( i16* %122, i16 %123 ) ; :124 [#uses=1] - or i16 %124, %123 ; :125 [#uses=1] - store i16 %125, i16* @us, align 2 - load i8* @uc, align 1 ; :126 [#uses=1] - zext i8 %126 to i32 ; :127 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :128 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %128, i32 %127 ) ; :129 [#uses=1] - or i32 %129, %127 ; :130 [#uses=1] - store i32 %130, i32* @si, align 4 - load i8* @uc, align 1 ; :131 [#uses=1] - zext i8 %131 to i32 ; :132 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :133 [#uses=1] - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %133, i32 %132 ) ; :134 [#uses=1] - or i32 %134, %132 ; :135 [#uses=1] - store i32 %135, i32* @ui, align 4 - load i8* @uc, align 1 ; :136 [#uses=1] - zext i8 %136 to i64 ; :137 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :138 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %138, i64 %137 ) ; :139 [#uses=1] - or i64 %139, %137 ; :140 [#uses=1] - store i64 %140, i64* @sl, align 8 - load i8* @uc, align 1 ; :141 [#uses=1] - zext i8 %141 to i64 ; :142 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :143 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %143, i64 %142 ) ; :144 [#uses=1] - or i64 %144, %142 ; :145 [#uses=1] - store i64 %145, i64* @ul, align 8 - load i8* @uc, align 1 ; :146 [#uses=1] - zext i8 %146 to i64 ; :147 [#uses=2] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :148 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %148, i64 %147 ) ; :149 [#uses=1] - or i64 %149, %147 ; :150 [#uses=1] - store i64 %150, i64* @sll, align 8 - load i8* @uc, align 1 ; :151 [#uses=1] - zext i8 %151 to i64 ; :152 [#uses=2] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :153 [#uses=1] - call i64 @llvm.atomic.load.or.i64.p0i64( i64* %153, i64 %152 ) ; :154 [#uses=1] - or i64 %154, %152 ; :155 [#uses=1] - store i64 %155, i64* @ull, align 8 - load i8* @uc, align 1 ; :156 [#uses=1] - zext i8 %156 to i32 ; :157 [#uses=1] - trunc i32 %157 to i8 ; :158 [#uses=2] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 %158 ) ; :159 [#uses=1] - xor i8 %159, %158 ; :160 [#uses=1] - store i8 %160, i8* @sc, align 1 - load i8* @uc, align 1 ; :161 [#uses=1] - zext i8 %161 to i32 ; :162 [#uses=1] - trunc i32 %162 to i8 ; :163 [#uses=2] - call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 %163 ) ; :164 [#uses=1] - xor i8 %164, %163 ; :165 [#uses=1] - store i8 %165, i8* @uc, align 1 - load i8* @uc, align 1 ; :166 [#uses=1] - zext i8 %166 to i32 ; :167 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :168 [#uses=1] - trunc i32 %167 to i16 ; :169 [#uses=2] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %168, i16 %169 ) ; :170 [#uses=1] - xor i16 %170, %169 ; :171 [#uses=1] - store i16 %171, i16* @ss, align 2 - load i8* @uc, align 1 ; :172 [#uses=1] - zext i8 %172 to i32 ; :173 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :174 [#uses=1] - trunc i32 %173 to i16 ; :175 [#uses=2] - call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %174, i16 %175 ) ; :176 [#uses=1] - xor i16 %176, %175 ; :177 [#uses=1] - store i16 %177, i16* @us, align 2 - load i8* @uc, align 1 ; :178 [#uses=1] - zext i8 %178 to i32 ; :179 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :180 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %180, i32 %179 ) ; :181 [#uses=1] - xor i32 %181, %179 ; :182 [#uses=1] - store i32 %182, i32* @si, align 4 - load i8* @uc, align 1 ; :183 [#uses=1] - zext i8 %183 to i32 ; :184 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :185 [#uses=1] - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %185, i32 %184 ) ; :186 [#uses=1] - xor i32 %186, %184 ; :187 [#uses=1] - store i32 %187, i32* @ui, align 4 - load i8* @uc, align 1 ; :188 [#uses=1] - zext i8 %188 to i64 ; :189 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :190 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %190, i64 %189 ) ; :191 [#uses=1] - xor i64 %191, %189 ; :192 [#uses=1] - store i64 %192, i64* @sl, align 8 - load i8* @uc, align 1 ; :193 [#uses=1] - zext i8 %193 to i64 ; :194 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :195 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %195, i64 %194 ) ; :196 [#uses=1] - xor i64 %196, %194 ; :197 [#uses=1] - store i64 %197, i64* @ul, align 8 - load i8* @uc, align 1 ; :198 [#uses=1] - zext i8 %198 to i64 ; :199 [#uses=2] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :200 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %200, i64 %199 ) ; :201 [#uses=1] - xor i64 %201, %199 ; :202 [#uses=1] - store i64 %202, i64* @sll, align 8 - load i8* @uc, align 1 ; :203 [#uses=1] - zext i8 %203 to i64 ; :204 [#uses=2] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :205 [#uses=1] - call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %205, i64 %204 ) ; :206 [#uses=1] - xor i64 %206, %204 ; :207 [#uses=1] - store i64 %207, i64* @ull, align 8 - load i8* @uc, align 1 ; :208 [#uses=1] - zext i8 %208 to i32 ; :209 [#uses=1] - trunc i32 %209 to i8 ; :210 [#uses=2] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 %210 ) ; :211 [#uses=1] - and i8 %211, %210 ; :212 [#uses=1] - store i8 %212, i8* @sc, align 1 - load i8* @uc, align 1 ; :213 [#uses=1] - zext i8 %213 to i32 ; :214 [#uses=1] - trunc i32 %214 to i8 ; :215 [#uses=2] - call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 %215 ) ; :216 [#uses=1] - and i8 %216, %215 ; :217 [#uses=1] - store i8 %217, i8* @uc, align 1 - load i8* @uc, align 1 ; :218 [#uses=1] - zext i8 %218 to i32 ; :219 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :220 [#uses=1] - trunc i32 %219 to i16 ; :221 [#uses=2] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %220, i16 %221 ) ; :222 [#uses=1] - and i16 %222, %221 ; :223 [#uses=1] - store i16 %223, i16* @ss, align 2 - load i8* @uc, align 1 ; :224 [#uses=1] - zext i8 %224 to i32 ; :225 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :226 [#uses=1] - trunc i32 %225 to i16 ; :227 [#uses=2] - call i16 @llvm.atomic.load.and.i16.p0i16( i16* %226, i16 %227 ) ; :228 [#uses=1] - and i16 %228, %227 ; :229 [#uses=1] - store i16 %229, i16* @us, align 2 - load i8* @uc, align 1 ; :230 [#uses=1] - zext i8 %230 to i32 ; :231 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :232 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %232, i32 %231 ) ; :233 [#uses=1] - and i32 %233, %231 ; :234 [#uses=1] - store i32 %234, i32* @si, align 4 - load i8* @uc, align 1 ; :235 [#uses=1] - zext i8 %235 to i32 ; :236 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :237 [#uses=1] - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %237, i32 %236 ) ; :238 [#uses=1] - and i32 %238, %236 ; :239 [#uses=1] - store i32 %239, i32* @ui, align 4 - load i8* @uc, align 1 ; :240 [#uses=1] - zext i8 %240 to i64 ; :241 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :242 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %242, i64 %241 ) ; :243 [#uses=1] - and i64 %243, %241 ; :244 [#uses=1] - store i64 %244, i64* @sl, align 8 - load i8* @uc, align 1 ; :245 [#uses=1] - zext i8 %245 to i64 ; :246 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :247 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %247, i64 %246 ) ; :248 [#uses=1] - and i64 %248, %246 ; :249 [#uses=1] - store i64 %249, i64* @ul, align 8 - load i8* @uc, align 1 ; :250 [#uses=1] - zext i8 %250 to i64 ; :251 [#uses=2] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :252 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %252, i64 %251 ) ; :253 [#uses=1] - and i64 %253, %251 ; :254 [#uses=1] - store i64 %254, i64* @sll, align 8 - load i8* @uc, align 1 ; :255 [#uses=1] - zext i8 %255 to i64 ; :256 [#uses=2] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :257 [#uses=1] - call i64 @llvm.atomic.load.and.i64.p0i64( i64* %257, i64 %256 ) ; :258 [#uses=1] - and i64 %258, %256 ; :259 [#uses=1] - store i64 %259, i64* @ull, align 8 - load i8* @uc, align 1 ; :260 [#uses=1] - zext i8 %260 to i32 ; :261 [#uses=1] - trunc i32 %261 to i8 ; :262 [#uses=2] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 %262 ) ; :263 [#uses=1] - xor i8 %263, -1 ; :264 [#uses=1] - and i8 %264, %262 ; :265 [#uses=1] - store i8 %265, i8* @sc, align 1 - load i8* @uc, align 1 ; :266 [#uses=1] - zext i8 %266 to i32 ; :267 [#uses=1] - trunc i32 %267 to i8 ; :268 [#uses=2] - call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 %268 ) ; :269 [#uses=1] - xor i8 %269, -1 ; :270 [#uses=1] - and i8 %270, %268 ; :271 [#uses=1] - store i8 %271, i8* @uc, align 1 - load i8* @uc, align 1 ; :272 [#uses=1] - zext i8 %272 to i32 ; :273 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :274 [#uses=1] - trunc i32 %273 to i16 ; :275 [#uses=2] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %274, i16 %275 ) ; :276 [#uses=1] - xor i16 %276, -1 ; :277 [#uses=1] - and i16 %277, %275 ; :278 [#uses=1] - store i16 %278, i16* @ss, align 2 - load i8* @uc, align 1 ; :279 [#uses=1] - zext i8 %279 to i32 ; :280 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :281 [#uses=1] - trunc i32 %280 to i16 ; :282 [#uses=2] - call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %281, i16 %282 ) ; :283 [#uses=1] - xor i16 %283, -1 ; :284 [#uses=1] - and i16 %284, %282 ; :285 [#uses=1] - store i16 %285, i16* @us, align 2 - load i8* @uc, align 1 ; :286 [#uses=1] - zext i8 %286 to i32 ; :287 [#uses=2] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :288 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %288, i32 %287 ) ; :289 [#uses=1] - xor i32 %289, -1 ; :290 [#uses=1] - and i32 %290, %287 ; :291 [#uses=1] - store i32 %291, i32* @si, align 4 - load i8* @uc, align 1 ; :292 [#uses=1] - zext i8 %292 to i32 ; :293 [#uses=2] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :294 [#uses=1] - call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %294, i32 %293 ) ; :295 [#uses=1] - xor i32 %295, -1 ; :296 [#uses=1] - and i32 %296, %293 ; :297 [#uses=1] - store i32 %297, i32* @ui, align 4 - load i8* @uc, align 1 ; :298 [#uses=1] - zext i8 %298 to i64 ; :299 [#uses=2] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :300 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %300, i64 %299 ) ; :301 [#uses=1] - xor i64 %301, -1 ; :302 [#uses=1] - and i64 %302, %299 ; :303 [#uses=1] - store i64 %303, i64* @sl, align 8 - load i8* @uc, align 1 ; :304 [#uses=1] - zext i8 %304 to i64 ; :305 [#uses=2] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :306 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %306, i64 %305 ) ; :307 [#uses=1] - xor i64 %307, -1 ; :308 [#uses=1] - and i64 %308, %305 ; :309 [#uses=1] - store i64 %309, i64* @ul, align 8 - load i8* @uc, align 1 ; :310 [#uses=1] - zext i8 %310 to i64 ; :311 [#uses=2] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :312 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %312, i64 %311 ) ; :313 [#uses=1] - xor i64 %313, -1 ; :314 [#uses=1] - and i64 %314, %311 ; :315 [#uses=1] - store i64 %315, i64* @sll, align 8 - load i8* @uc, align 1 ; :316 [#uses=1] - zext i8 %316 to i64 ; :317 [#uses=2] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :318 [#uses=1] - call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %318, i64 %317 ) ; :319 [#uses=1] - xor i64 %319, -1 ; :320 [#uses=1] - and i64 %320, %317 ; :321 [#uses=1] - store i64 %321, i64* @ull, align 8 - br label %return + %0 = load i8* @uc, align 1 + %1 = zext i8 %0 to i32 + %2 = trunc i32 %1 to i8 + %3 = atomicrmw add i8* @sc, i8 %2 monotonic + %4 = add i8 %3, %2 + store i8 %4, i8* @sc, align 1 + %5 = load i8* @uc, align 1 + %6 = zext i8 %5 to i32 + %7 = trunc i32 %6 to i8 + %8 = atomicrmw add i8* @uc, i8 %7 monotonic + %9 = add i8 %8, %7 + store i8 %9, i8* @uc, align 1 + %10 = load i8* @uc, align 1 + %11 = zext i8 %10 to i32 + %12 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %13 = trunc i32 %11 to i16 + %14 = atomicrmw add i16* %12, i16 %13 monotonic + %15 = add i16 %14, %13 + store i16 %15, i16* @ss, align 2 + %16 = load i8* @uc, align 1 + %17 = zext i8 %16 to i32 + %18 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %19 = trunc i32 %17 to i16 + %20 = atomicrmw add i16* %18, i16 %19 monotonic + %21 = add i16 %20, %19 + store i16 %21, i16* @us, align 2 + %22 = load i8* @uc, align 1 + %23 = zext i8 %22 to i32 + %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %25 = atomicrmw add i32* %24, i32 %23 monotonic + %26 = add i32 %25, %23 + store i32 %26, i32* @si, align 4 + %27 = load i8* @uc, align 1 + %28 = zext i8 %27 to i32 + %29 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %30 = atomicrmw add i32* %29, i32 %28 monotonic + %31 = add i32 %30, %28 + store i32 %31, i32* @ui, align 4 + %32 = load i8* @uc, align 1 + %33 = zext i8 %32 to i64 + %34 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %35 = atomicrmw add i64* %34, i64 %33 monotonic + %36 = add i64 %35, %33 + store i64 %36, i64* @sl, align 8 + %37 = load i8* @uc, align 1 + %38 = zext i8 %37 to i64 + %39 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %40 = atomicrmw add i64* %39, i64 %38 monotonic + %41 = add i64 %40, %38 + store i64 %41, i64* @ul, align 8 + %42 = load i8* @uc, align 1 + %43 = zext i8 %42 to i64 + %44 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %45 = atomicrmw add i64* %44, i64 %43 monotonic + %46 = add i64 %45, %43 + store i64 %46, i64* @sll, align 8 + %47 = load i8* @uc, align 1 + %48 = zext i8 %47 to i64 + %49 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %50 = atomicrmw add i64* %49, i64 %48 monotonic + %51 = add i64 %50, %48 + store i64 %51, i64* @ull, align 8 + %52 = load i8* @uc, align 1 + %53 = zext i8 %52 to i32 + %54 = trunc i32 %53 to i8 + %55 = atomicrmw sub i8* @sc, i8 %54 monotonic + %56 = sub i8 %55, %54 + store i8 %56, i8* @sc, align 1 + %57 = load i8* @uc, align 1 + %58 = zext i8 %57 to i32 + %59 = trunc i32 %58 to i8 + %60 = atomicrmw sub i8* @uc, i8 %59 monotonic + %61 = sub i8 %60, %59 + store i8 %61, i8* @uc, align 1 + %62 = load i8* @uc, align 1 + %63 = zext i8 %62 to i32 + %64 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %65 = trunc i32 %63 to i16 + %66 = atomicrmw sub i16* %64, i16 %65 monotonic + %67 = sub i16 %66, %65 + store i16 %67, i16* @ss, align 2 + %68 = load i8* @uc, align 1 + %69 = zext i8 %68 to i32 + %70 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %71 = trunc i32 %69 to i16 + %72 = atomicrmw sub i16* %70, i16 %71 monotonic + %73 = sub i16 %72, %71 + store i16 %73, i16* @us, align 2 + %74 = load i8* @uc, align 1 + %75 = zext i8 %74 to i32 + %76 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %77 = atomicrmw sub i32* %76, i32 %75 monotonic + %78 = sub i32 %77, %75 + store i32 %78, i32* @si, align 4 + %79 = load i8* @uc, align 1 + %80 = zext i8 %79 to i32 + %81 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %82 = atomicrmw sub i32* %81, i32 %80 monotonic + %83 = sub i32 %82, %80 + store i32 %83, i32* @ui, align 4 + %84 = load i8* @uc, align 1 + %85 = zext i8 %84 to i64 + %86 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %87 = atomicrmw sub i64* %86, i64 %85 monotonic + %88 = sub i64 %87, %85 + store i64 %88, i64* @sl, align 8 + %89 = load i8* @uc, align 1 + %90 = zext i8 %89 to i64 + %91 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %92 = atomicrmw sub i64* %91, i64 %90 monotonic + %93 = sub i64 %92, %90 + store i64 %93, i64* @ul, align 8 + %94 = load i8* @uc, align 1 + %95 = zext i8 %94 to i64 + %96 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %97 = atomicrmw sub i64* %96, i64 %95 monotonic + %98 = sub i64 %97, %95 + store i64 %98, i64* @sll, align 8 + %99 = load i8* @uc, align 1 + %100 = zext i8 %99 to i64 + %101 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %102 = atomicrmw sub i64* %101, i64 %100 monotonic + %103 = sub i64 %102, %100 + store i64 %103, i64* @ull, align 8 + %104 = load i8* @uc, align 1 + %105 = zext i8 %104 to i32 + %106 = trunc i32 %105 to i8 + %107 = atomicrmw or i8* @sc, i8 %106 monotonic + %108 = or i8 %107, %106 + store i8 %108, i8* @sc, align 1 + %109 = load i8* @uc, align 1 + %110 = zext i8 %109 to i32 + %111 = trunc i32 %110 to i8 + %112 = atomicrmw or i8* @uc, i8 %111 monotonic + %113 = or i8 %112, %111 + store i8 %113, i8* @uc, align 1 + %114 = load i8* @uc, align 1 + %115 = zext i8 %114 to i32 + %116 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %117 = trunc i32 %115 to i16 + %118 = atomicrmw or i16* %116, i16 %117 monotonic + %119 = or i16 %118, %117 + store i16 %119, i16* @ss, align 2 + %120 = load i8* @uc, align 1 + %121 = zext i8 %120 to i32 + %122 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %123 = trunc i32 %121 to i16 + %124 = atomicrmw or i16* %122, i16 %123 monotonic + %125 = or i16 %124, %123 + store i16 %125, i16* @us, align 2 + %126 = load i8* @uc, align 1 + %127 = zext i8 %126 to i32 + %128 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %129 = atomicrmw or i32* %128, i32 %127 monotonic + %130 = or i32 %129, %127 + store i32 %130, i32* @si, align 4 + %131 = load i8* @uc, align 1 + %132 = zext i8 %131 to i32 + %133 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %134 = atomicrmw or i32* %133, i32 %132 monotonic + %135 = or i32 %134, %132 + store i32 %135, i32* @ui, align 4 + %136 = load i8* @uc, align 1 + %137 = zext i8 %136 to i64 + %138 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %139 = atomicrmw or i64* %138, i64 %137 monotonic + %140 = or i64 %139, %137 + store i64 %140, i64* @sl, align 8 + %141 = load i8* @uc, align 1 + %142 = zext i8 %141 to i64 + %143 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %144 = atomicrmw or i64* %143, i64 %142 monotonic + %145 = or i64 %144, %142 + store i64 %145, i64* @ul, align 8 + %146 = load i8* @uc, align 1 + %147 = zext i8 %146 to i64 + %148 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %149 = atomicrmw or i64* %148, i64 %147 monotonic + %150 = or i64 %149, %147 + store i64 %150, i64* @sll, align 8 + %151 = load i8* @uc, align 1 + %152 = zext i8 %151 to i64 + %153 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %154 = atomicrmw or i64* %153, i64 %152 monotonic + %155 = or i64 %154, %152 + store i64 %155, i64* @ull, align 8 + %156 = load i8* @uc, align 1 + %157 = zext i8 %156 to i32 + %158 = trunc i32 %157 to i8 + %159 = atomicrmw xor i8* @sc, i8 %158 monotonic + %160 = xor i8 %159, %158 + store i8 %160, i8* @sc, align 1 + %161 = load i8* @uc, align 1 + %162 = zext i8 %161 to i32 + %163 = trunc i32 %162 to i8 + %164 = atomicrmw xor i8* @uc, i8 %163 monotonic + %165 = xor i8 %164, %163 + store i8 %165, i8* @uc, align 1 + %166 = load i8* @uc, align 1 + %167 = zext i8 %166 to i32 + %168 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %169 = trunc i32 %167 to i16 + %170 = atomicrmw xor i16* %168, i16 %169 monotonic + %171 = xor i16 %170, %169 + store i16 %171, i16* @ss, align 2 + %172 = load i8* @uc, align 1 + %173 = zext i8 %172 to i32 + %174 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %175 = trunc i32 %173 to i16 + %176 = atomicrmw xor i16* %174, i16 %175 monotonic + %177 = xor i16 %176, %175 + store i16 %177, i16* @us, align 2 + %178 = load i8* @uc, align 1 + %179 = zext i8 %178 to i32 + %180 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %181 = atomicrmw xor i32* %180, i32 %179 monotonic + %182 = xor i32 %181, %179 + store i32 %182, i32* @si, align 4 + %183 = load i8* @uc, align 1 + %184 = zext i8 %183 to i32 + %185 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %186 = atomicrmw xor i32* %185, i32 %184 monotonic + %187 = xor i32 %186, %184 + store i32 %187, i32* @ui, align 4 + %188 = load i8* @uc, align 1 + %189 = zext i8 %188 to i64 + %190 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %191 = atomicrmw xor i64* %190, i64 %189 monotonic + %192 = xor i64 %191, %189 + store i64 %192, i64* @sl, align 8 + %193 = load i8* @uc, align 1 + %194 = zext i8 %193 to i64 + %195 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %196 = atomicrmw xor i64* %195, i64 %194 monotonic + %197 = xor i64 %196, %194 + store i64 %197, i64* @ul, align 8 + %198 = load i8* @uc, align 1 + %199 = zext i8 %198 to i64 + %200 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %201 = atomicrmw xor i64* %200, i64 %199 monotonic + %202 = xor i64 %201, %199 + store i64 %202, i64* @sll, align 8 + %203 = load i8* @uc, align 1 + %204 = zext i8 %203 to i64 + %205 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %206 = atomicrmw xor i64* %205, i64 %204 monotonic + %207 = xor i64 %206, %204 + store i64 %207, i64* @ull, align 8 + %208 = load i8* @uc, align 1 + %209 = zext i8 %208 to i32 + %210 = trunc i32 %209 to i8 + %211 = atomicrmw and i8* @sc, i8 %210 monotonic + %212 = and i8 %211, %210 + store i8 %212, i8* @sc, align 1 + %213 = load i8* @uc, align 1 + %214 = zext i8 %213 to i32 + %215 = trunc i32 %214 to i8 + %216 = atomicrmw and i8* @uc, i8 %215 monotonic + %217 = and i8 %216, %215 + store i8 %217, i8* @uc, align 1 + %218 = load i8* @uc, align 1 + %219 = zext i8 %218 to i32 + %220 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %221 = trunc i32 %219 to i16 + %222 = atomicrmw and i16* %220, i16 %221 monotonic + %223 = and i16 %222, %221 + store i16 %223, i16* @ss, align 2 + %224 = load i8* @uc, align 1 + %225 = zext i8 %224 to i32 + %226 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %227 = trunc i32 %225 to i16 + %228 = atomicrmw and i16* %226, i16 %227 monotonic + %229 = and i16 %228, %227 + store i16 %229, i16* @us, align 2 + %230 = load i8* @uc, align 1 + %231 = zext i8 %230 to i32 + %232 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %233 = atomicrmw and i32* %232, i32 %231 monotonic + %234 = and i32 %233, %231 + store i32 %234, i32* @si, align 4 + %235 = load i8* @uc, align 1 + %236 = zext i8 %235 to i32 + %237 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %238 = atomicrmw and i32* %237, i32 %236 monotonic + %239 = and i32 %238, %236 + store i32 %239, i32* @ui, align 4 + %240 = load i8* @uc, align 1 + %241 = zext i8 %240 to i64 + %242 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %243 = atomicrmw and i64* %242, i64 %241 monotonic + %244 = and i64 %243, %241 + store i64 %244, i64* @sl, align 8 + %245 = load i8* @uc, align 1 + %246 = zext i8 %245 to i64 + %247 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %248 = atomicrmw and i64* %247, i64 %246 monotonic + %249 = and i64 %248, %246 + store i64 %249, i64* @ul, align 8 + %250 = load i8* @uc, align 1 + %251 = zext i8 %250 to i64 + %252 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %253 = atomicrmw and i64* %252, i64 %251 monotonic + %254 = and i64 %253, %251 + store i64 %254, i64* @sll, align 8 + %255 = load i8* @uc, align 1 + %256 = zext i8 %255 to i64 + %257 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %258 = atomicrmw and i64* %257, i64 %256 monotonic + %259 = and i64 %258, %256 + store i64 %259, i64* @ull, align 8 + %260 = load i8* @uc, align 1 + %261 = zext i8 %260 to i32 + %262 = trunc i32 %261 to i8 + %263 = atomicrmw nand i8* @sc, i8 %262 monotonic + %264 = xor i8 %263, -1 + %265 = and i8 %264, %262 + store i8 %265, i8* @sc, align 1 + %266 = load i8* @uc, align 1 + %267 = zext i8 %266 to i32 + %268 = trunc i32 %267 to i8 + %269 = atomicrmw nand i8* @uc, i8 %268 monotonic + %270 = xor i8 %269, -1 + %271 = and i8 %270, %268 + store i8 %271, i8* @uc, align 1 + %272 = load i8* @uc, align 1 + %273 = zext i8 %272 to i32 + %274 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %275 = trunc i32 %273 to i16 + %276 = atomicrmw nand i16* %274, i16 %275 monotonic + %277 = xor i16 %276, -1 + %278 = and i16 %277, %275 + store i16 %278, i16* @ss, align 2 + %279 = load i8* @uc, align 1 + %280 = zext i8 %279 to i32 + %281 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %282 = trunc i32 %280 to i16 + %283 = atomicrmw nand i16* %281, i16 %282 monotonic + %284 = xor i16 %283, -1 + %285 = and i16 %284, %282 + store i16 %285, i16* @us, align 2 + %286 = load i8* @uc, align 1 + %287 = zext i8 %286 to i32 + %288 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %289 = atomicrmw nand i32* %288, i32 %287 monotonic + %290 = xor i32 %289, -1 + %291 = and i32 %290, %287 + store i32 %291, i32* @si, align 4 + %292 = load i8* @uc, align 1 + %293 = zext i8 %292 to i32 + %294 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %295 = atomicrmw nand i32* %294, i32 %293 monotonic + %296 = xor i32 %295, -1 + %297 = and i32 %296, %293 + store i32 %297, i32* @ui, align 4 + %298 = load i8* @uc, align 1 + %299 = zext i8 %298 to i64 + %300 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %301 = atomicrmw nand i64* %300, i64 %299 monotonic + %302 = xor i64 %301, -1 + %303 = and i64 %302, %299 + store i64 %303, i64* @sl, align 8 + %304 = load i8* @uc, align 1 + %305 = zext i8 %304 to i64 + %306 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %307 = atomicrmw nand i64* %306, i64 %305 monotonic + %308 = xor i64 %307, -1 + %309 = and i64 %308, %305 + store i64 %309, i64* @ul, align 8 + %310 = load i8* @uc, align 1 + %311 = zext i8 %310 to i64 + %312 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %313 = atomicrmw nand i64* %312, i64 %311 monotonic + %314 = xor i64 %313, -1 + %315 = and i64 %314, %311 + store i64 %315, i64* @sll, align 8 + %316 = load i8* @uc, align 1 + %317 = zext i8 %316 to i64 + %318 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %319 = atomicrmw nand i64* %318, i64 %317 monotonic + %320 = xor i64 %319, -1 + %321 = and i64 %320, %317 + store i64 %321, i64* @ull, align 8 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } define void @test_compare_and_swap() nounwind { entry: - load i8* @sc, align 1 ; :0 [#uses=1] - zext i8 %0 to i32 ; :1 [#uses=1] - load i8* @uc, align 1 ; :2 [#uses=1] - zext i8 %2 to i32 ; :3 [#uses=1] - trunc i32 %3 to i8 ; :4 [#uses=1] - trunc i32 %1 to i8 ; :5 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %4, i8 %5 ) ; :6 [#uses=1] - store i8 %6, i8* @sc, align 1 - load i8* @sc, align 1 ; :7 [#uses=1] - zext i8 %7 to i32 ; :8 [#uses=1] - load i8* @uc, align 1 ; :9 [#uses=1] - zext i8 %9 to i32 ; :10 [#uses=1] - trunc i32 %10 to i8 ; :11 [#uses=1] - trunc i32 %8 to i8 ; :12 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %11, i8 %12 ) ; :13 [#uses=1] - store i8 %13, i8* @uc, align 1 - load i8* @sc, align 1 ; :14 [#uses=1] - sext i8 %14 to i16 ; :15 [#uses=1] - zext i16 %15 to i32 ; :16 [#uses=1] - load i8* @uc, align 1 ; :17 [#uses=1] - zext i8 %17 to i32 ; :18 [#uses=1] - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :19 [#uses=1] - trunc i32 %18 to i16 ; :20 [#uses=1] - trunc i32 %16 to i16 ; :21 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %19, i16 %20, i16 %21 ) ; :22 [#uses=1] - store i16 %22, i16* @ss, align 2 - load i8* @sc, align 1 ; :23 [#uses=1] - sext i8 %23 to i16 ; :24 [#uses=1] - zext i16 %24 to i32 ; :25 [#uses=1] - load i8* @uc, align 1 ; :26 [#uses=1] - zext i8 %26 to i32 ; :27 [#uses=1] - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :28 [#uses=1] - trunc i32 %27 to i16 ; :29 [#uses=1] - trunc i32 %25 to i16 ; :30 [#uses=1] - call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %28, i16 %29, i16 %30 ) ; :31 [#uses=1] - store i16 %31, i16* @us, align 2 - load i8* @sc, align 1 ; :32 [#uses=1] - sext i8 %32 to i32 ; :33 [#uses=1] - load i8* @uc, align 1 ; :34 [#uses=1] - zext i8 %34 to i32 ; :35 [#uses=1] - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :36 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %36, i32 %35, i32 %33 ) ; :37 [#uses=1] - store i32 %37, i32* @si, align 4 - load i8* @sc, align 1 ; :38 [#uses=1] - sext i8 %38 to i32 ; :39 [#uses=1] - load i8* @uc, align 1 ; :40 [#uses=1] - zext i8 %40 to i32 ; :41 [#uses=1] - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :42 [#uses=1] - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %42, i32 %41, i32 %39 ) ; :43 [#uses=1] - store i32 %43, i32* @ui, align 4 - load i8* @sc, align 1 ; :44 [#uses=1] - sext i8 %44 to i64 ; :45 [#uses=1] - load i8* @uc, align 1 ; :46 [#uses=1] - zext i8 %46 to i64 ; :47 [#uses=1] - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :48 [#uses=1] - call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %48, i64 %47, i64 %45 ) ; :49 [#uses=1] - store i64 %49, i64* @sl, align 8 - load i8* @sc, align 1 ; :50 [#uses=1] - sext i8 %50 to i64 ; :51 [#uses=1] - load i8* @uc, align 1 ; :52 [#uses=1] - zext i8 %52 to i64 ; :53 [#uses=1] - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :54 [#uses=1] - call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %54, i64 %53, i64 %51 ) ; :55 [#uses=1] - store i64 %55, i64* @ul, align 8 - load i8* @sc, align 1 ; :56 [#uses=1] - sext i8 %56 to i64 ; :57 [#uses=1] - load i8* @uc, align 1 ; :58 [#uses=1] - zext i8 %58 to i64 ; :59 [#uses=1] - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :60 [#uses=1] - call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %60, i64 %59, i64 %57 ) ; :61 [#uses=1] - store i64 %61, i64* @sll, align 8 - load i8* @sc, align 1 ; :62 [#uses=1] - sext i8 %62 to i64 ; :63 [#uses=1] - load i8* @uc, align 1 ; :64 [#uses=1] - zext i8 %64 to i64 ; :65 [#uses=1] - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :66 [#uses=1] - call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %66, i64 %65, i64 %63 ) ; :67 [#uses=1] - store i64 %67, i64* @ull, align 8 - load i8* @sc, align 1 ; :68 [#uses=1] - zext i8 %68 to i32 ; :69 [#uses=1] - load i8* @uc, align 1 ; :70 [#uses=1] - zext i8 %70 to i32 ; :71 [#uses=1] - trunc i32 %71 to i8 ; :72 [#uses=2] - trunc i32 %69 to i8 ; :73 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %72, i8 %73 ) ; :74 [#uses=1] - icmp eq i8 %74, %72 ; :75 [#uses=1] - zext i1 %75 to i8 ; :76 [#uses=1] - zext i8 %76 to i32 ; :77 [#uses=1] - store i32 %77, i32* @ui, align 4 - load i8* @sc, align 1 ; :78 [#uses=1] - zext i8 %78 to i32 ; :79 [#uses=1] - load i8* @uc, align 1 ; :80 [#uses=1] - zext i8 %80 to i32 ; :81 [#uses=1] - trunc i32 %81 to i8 ; :82 [#uses=2] - trunc i32 %79 to i8 ; :83 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %82, i8 %83 ) ; :84 [#uses=1] - icmp eq i8 %84, %82 ; :85 [#uses=1] - zext i1 %85 to i8 ; :86 [#uses=1] - zext i8 %86 to i32 ; :87 [#uses=1] - store i32 %87, i32* @ui, align 4 - load i8* @sc, align 1 ; :88 [#uses=1] - sext i8 %88 to i16 ; :89 [#uses=1] - zext i16 %89 to i32 ; :90 [#uses=1] - load i8* @uc, align 1 ; :91 [#uses=1] - zext i8 %91 to i32 ; :92 [#uses=1] - trunc i32 %92 to i8 ; :93 [#uses=2] - trunc i32 %90 to i8 ; :94 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i16* @ss to i8*), i8 %93, i8 %94 ) ; :95 [#uses=1] - icmp eq i8 %95, %93 ; :96 [#uses=1] - zext i1 %96 to i8 ; :97 [#uses=1] - zext i8 %97 to i32 ; :98 [#uses=1] - store i32 %98, i32* @ui, align 4 - load i8* @sc, align 1 ; :99 [#uses=1] - sext i8 %99 to i16 ; :100 [#uses=1] - zext i16 %100 to i32 ; :101 [#uses=1] - load i8* @uc, align 1 ; :102 [#uses=1] - zext i8 %102 to i32 ; :103 [#uses=1] - trunc i32 %103 to i8 ; :104 [#uses=2] - trunc i32 %101 to i8 ; :105 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i16* @us to i8*), i8 %104, i8 %105 ) ; :106 [#uses=1] - icmp eq i8 %106, %104 ; :107 [#uses=1] - zext i1 %107 to i8 ; :108 [#uses=1] - zext i8 %108 to i32 ; :109 [#uses=1] - store i32 %109, i32* @ui, align 4 - load i8* @sc, align 1 ; :110 [#uses=1] - sext i8 %110 to i32 ; :111 [#uses=1] - load i8* @uc, align 1 ; :112 [#uses=1] - zext i8 %112 to i32 ; :113 [#uses=1] - trunc i32 %113 to i8 ; :114 [#uses=2] - trunc i32 %111 to i8 ; :115 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @si to i8*), i8 %114, i8 %115 ) ; :116 [#uses=1] - icmp eq i8 %116, %114 ; :117 [#uses=1] - zext i1 %117 to i8 ; :118 [#uses=1] - zext i8 %118 to i32 ; :119 [#uses=1] - store i32 %119, i32* @ui, align 4 - load i8* @sc, align 1 ; :120 [#uses=1] - sext i8 %120 to i32 ; :121 [#uses=1] - load i8* @uc, align 1 ; :122 [#uses=1] - zext i8 %122 to i32 ; :123 [#uses=1] - trunc i32 %123 to i8 ; :124 [#uses=2] - trunc i32 %121 to i8 ; :125 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @ui to i8*), i8 %124, i8 %125 ) ; :126 [#uses=1] - icmp eq i8 %126, %124 ; :127 [#uses=1] - zext i1 %127 to i8 ; :128 [#uses=1] - zext i8 %128 to i32 ; :129 [#uses=1] - store i32 %129, i32* @ui, align 4 - load i8* @sc, align 1 ; :130 [#uses=1] - sext i8 %130 to i64 ; :131 [#uses=1] - load i8* @uc, align 1 ; :132 [#uses=1] - zext i8 %132 to i64 ; :133 [#uses=1] - trunc i64 %133 to i8 ; :134 [#uses=2] - trunc i64 %131 to i8 ; :135 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i64* @sl to i8*), i8 %134, i8 %135 ) ; :136 [#uses=1] - icmp eq i8 %136, %134 ; :137 [#uses=1] - zext i1 %137 to i8 ; :138 [#uses=1] - zext i8 %138 to i32 ; :139 [#uses=1] - store i32 %139, i32* @ui, align 4 - load i8* @sc, align 1 ; :140 [#uses=1] - sext i8 %140 to i64 ; :141 [#uses=1] - load i8* @uc, align 1 ; :142 [#uses=1] - zext i8 %142 to i64 ; :143 [#uses=1] - trunc i64 %143 to i8 ; :144 [#uses=2] - trunc i64 %141 to i8 ; :145 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i64* @ul to i8*), i8 %144, i8 %145 ) ; :146 [#uses=1] - icmp eq i8 %146, %144 ; :147 [#uses=1] - zext i1 %147 to i8 ; :148 [#uses=1] - zext i8 %148 to i32 ; :149 [#uses=1] - store i32 %149, i32* @ui, align 4 - load i8* @sc, align 1 ; :150 [#uses=1] - sext i8 %150 to i64 ; :151 [#uses=1] - load i8* @uc, align 1 ; :152 [#uses=1] - zext i8 %152 to i64 ; :153 [#uses=1] - trunc i64 %153 to i8 ; :154 [#uses=2] - trunc i64 %151 to i8 ; :155 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i64* @sll to i8*), i8 %154, i8 %155 ) ; :156 [#uses=1] - icmp eq i8 %156, %154 ; :157 [#uses=1] - zext i1 %157 to i8 ; :158 [#uses=1] - zext i8 %158 to i32 ; :159 [#uses=1] - store i32 %159, i32* @ui, align 4 - load i8* @sc, align 1 ; :160 [#uses=1] - sext i8 %160 to i64 ; :161 [#uses=1] - load i8* @uc, align 1 ; :162 [#uses=1] - zext i8 %162 to i64 ; :163 [#uses=1] - trunc i64 %163 to i8 ; :164 [#uses=2] - trunc i64 %161 to i8 ; :165 [#uses=1] - call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i64* @ull to i8*), i8 %164, i8 %165 ) ; :166 [#uses=1] - icmp eq i8 %166, %164 ; :167 [#uses=1] - zext i1 %167 to i8 ; :168 [#uses=1] - zext i8 %168 to i32 ; :169 [#uses=1] - store i32 %169, i32* @ui, align 4 - br label %return + %0 = load i8* @sc, align 1 + %1 = zext i8 %0 to i32 + %2 = load i8* @uc, align 1 + %3 = zext i8 %2 to i32 + %4 = trunc i32 %3 to i8 + %5 = trunc i32 %1 to i8 + %6 = cmpxchg i8* @sc, i8 %4, i8 %5 monotonic + store i8 %6, i8* @sc, align 1 + %7 = load i8* @sc, align 1 + %8 = zext i8 %7 to i32 + %9 = load i8* @uc, align 1 + %10 = zext i8 %9 to i32 + %11 = trunc i32 %10 to i8 + %12 = trunc i32 %8 to i8 + %13 = cmpxchg i8* @uc, i8 %11, i8 %12 monotonic + store i8 %13, i8* @uc, align 1 + %14 = load i8* @sc, align 1 + %15 = sext i8 %14 to i16 + %16 = zext i16 %15 to i32 + %17 = load i8* @uc, align 1 + %18 = zext i8 %17 to i32 + %19 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %20 = trunc i32 %18 to i16 + %21 = trunc i32 %16 to i16 + %22 = cmpxchg i16* %19, i16 %20, i16 %21 monotonic + store i16 %22, i16* @ss, align 2 + %23 = load i8* @sc, align 1 + %24 = sext i8 %23 to i16 + %25 = zext i16 %24 to i32 + %26 = load i8* @uc, align 1 + %27 = zext i8 %26 to i32 + %28 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %29 = trunc i32 %27 to i16 + %30 = trunc i32 %25 to i16 + %31 = cmpxchg i16* %28, i16 %29, i16 %30 monotonic + store i16 %31, i16* @us, align 2 + %32 = load i8* @sc, align 1 + %33 = sext i8 %32 to i32 + %34 = load i8* @uc, align 1 + %35 = zext i8 %34 to i32 + %36 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %37 = cmpxchg i32* %36, i32 %35, i32 %33 monotonic + store i32 %37, i32* @si, align 4 + %38 = load i8* @sc, align 1 + %39 = sext i8 %38 to i32 + %40 = load i8* @uc, align 1 + %41 = zext i8 %40 to i32 + %42 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %43 = cmpxchg i32* %42, i32 %41, i32 %39 monotonic + store i32 %43, i32* @ui, align 4 + %44 = load i8* @sc, align 1 + %45 = sext i8 %44 to i64 + %46 = load i8* @uc, align 1 + %47 = zext i8 %46 to i64 + %48 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %49 = cmpxchg i64* %48, i64 %47, i64 %45 monotonic + store i64 %49, i64* @sl, align 8 + %50 = load i8* @sc, align 1 + %51 = sext i8 %50 to i64 + %52 = load i8* @uc, align 1 + %53 = zext i8 %52 to i64 + %54 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %55 = cmpxchg i64* %54, i64 %53, i64 %51 monotonic + store i64 %55, i64* @ul, align 8 + %56 = load i8* @sc, align 1 + %57 = sext i8 %56 to i64 + %58 = load i8* @uc, align 1 + %59 = zext i8 %58 to i64 + %60 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %61 = cmpxchg i64* %60, i64 %59, i64 %57 monotonic + store i64 %61, i64* @sll, align 8 + %62 = load i8* @sc, align 1 + %63 = sext i8 %62 to i64 + %64 = load i8* @uc, align 1 + %65 = zext i8 %64 to i64 + %66 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %67 = cmpxchg i64* %66, i64 %65, i64 %63 monotonic + store i64 %67, i64* @ull, align 8 + %68 = load i8* @sc, align 1 + %69 = zext i8 %68 to i32 + %70 = load i8* @uc, align 1 + %71 = zext i8 %70 to i32 + %72 = trunc i32 %71 to i8 + %73 = trunc i32 %69 to i8 + %74 = cmpxchg i8* @sc, i8 %72, i8 %73 monotonic + %75 = icmp eq i8 %74, %72 + %76 = zext i1 %75 to i8 + %77 = zext i8 %76 to i32 + store i32 %77, i32* @ui, align 4 + %78 = load i8* @sc, align 1 + %79 = zext i8 %78 to i32 + %80 = load i8* @uc, align 1 + %81 = zext i8 %80 to i32 + %82 = trunc i32 %81 to i8 + %83 = trunc i32 %79 to i8 + %84 = cmpxchg i8* @uc, i8 %82, i8 %83 monotonic + %85 = icmp eq i8 %84, %82 + %86 = zext i1 %85 to i8 + %87 = zext i8 %86 to i32 + store i32 %87, i32* @ui, align 4 + %88 = load i8* @sc, align 1 + %89 = sext i8 %88 to i16 + %90 = zext i16 %89 to i32 + %91 = load i8* @uc, align 1 + %92 = zext i8 %91 to i32 + %93 = trunc i32 %92 to i8 + %94 = trunc i32 %90 to i8 + %95 = cmpxchg i8* bitcast (i16* @ss to i8*), i8 %93, i8 %94 monotonic + %96 = icmp eq i8 %95, %93 + %97 = zext i1 %96 to i8 + %98 = zext i8 %97 to i32 + store i32 %98, i32* @ui, align 4 + %99 = load i8* @sc, align 1 + %100 = sext i8 %99 to i16 + %101 = zext i16 %100 to i32 + %102 = load i8* @uc, align 1 + %103 = zext i8 %102 to i32 + %104 = trunc i32 %103 to i8 + %105 = trunc i32 %101 to i8 + %106 = cmpxchg i8* bitcast (i16* @us to i8*), i8 %104, i8 %105 monotonic + %107 = icmp eq i8 %106, %104 + %108 = zext i1 %107 to i8 + %109 = zext i8 %108 to i32 + store i32 %109, i32* @ui, align 4 + %110 = load i8* @sc, align 1 + %111 = sext i8 %110 to i32 + %112 = load i8* @uc, align 1 + %113 = zext i8 %112 to i32 + %114 = trunc i32 %113 to i8 + %115 = trunc i32 %111 to i8 + %116 = cmpxchg i8* bitcast (i32* @si to i8*), i8 %114, i8 %115 monotonic + %117 = icmp eq i8 %116, %114 + %118 = zext i1 %117 to i8 + %119 = zext i8 %118 to i32 + store i32 %119, i32* @ui, align 4 + %120 = load i8* @sc, align 1 + %121 = sext i8 %120 to i32 + %122 = load i8* @uc, align 1 + %123 = zext i8 %122 to i32 + %124 = trunc i32 %123 to i8 + %125 = trunc i32 %121 to i8 + %126 = cmpxchg i8* bitcast (i32* @ui to i8*), i8 %124, i8 %125 monotonic + %127 = icmp eq i8 %126, %124 + %128 = zext i1 %127 to i8 + %129 = zext i8 %128 to i32 + store i32 %129, i32* @ui, align 4 + %130 = load i8* @sc, align 1 + %131 = sext i8 %130 to i64 + %132 = load i8* @uc, align 1 + %133 = zext i8 %132 to i64 + %134 = trunc i64 %133 to i8 + %135 = trunc i64 %131 to i8 + %136 = cmpxchg i8* bitcast (i64* @sl to i8*), i8 %134, i8 %135 monotonic + %137 = icmp eq i8 %136, %134 + %138 = zext i1 %137 to i8 + %139 = zext i8 %138 to i32 + store i32 %139, i32* @ui, align 4 + %140 = load i8* @sc, align 1 + %141 = sext i8 %140 to i64 + %142 = load i8* @uc, align 1 + %143 = zext i8 %142 to i64 + %144 = trunc i64 %143 to i8 + %145 = trunc i64 %141 to i8 + %146 = cmpxchg i8* bitcast (i64* @ul to i8*), i8 %144, i8 %145 monotonic + %147 = icmp eq i8 %146, %144 + %148 = zext i1 %147 to i8 + %149 = zext i8 %148 to i32 + store i32 %149, i32* @ui, align 4 + %150 = load i8* @sc, align 1 + %151 = sext i8 %150 to i64 + %152 = load i8* @uc, align 1 + %153 = zext i8 %152 to i64 + %154 = trunc i64 %153 to i8 + %155 = trunc i64 %151 to i8 + %156 = cmpxchg i8* bitcast (i64* @sll to i8*), i8 %154, i8 %155 monotonic + %157 = icmp eq i8 %156, %154 + %158 = zext i1 %157 to i8 + %159 = zext i8 %158 to i32 + store i32 %159, i32* @ui, align 4 + %160 = load i8* @sc, align 1 + %161 = sext i8 %160 to i64 + %162 = load i8* @uc, align 1 + %163 = zext i8 %162 to i64 + %164 = trunc i64 %163 to i8 + %165 = trunc i64 %161 to i8 + %166 = cmpxchg i8* bitcast (i64* @ull to i8*), i8 %164, i8 %165 monotonic + %167 = icmp eq i8 %166, %164 + %168 = zext i1 %167 to i8 + %169 = zext i8 %168 to i32 + store i32 %169, i32* @ui, align 4 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } -declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind - -declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind - -declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind - -declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64*, i64, i64) nounwind - define void @test_lock() nounwind { entry: - call i8 @llvm.atomic.swap.i8.p0i8( i8* @sc, i8 1 ) ; :0 [#uses=1] - store i8 %0, i8* @sc, align 1 - call i8 @llvm.atomic.swap.i8.p0i8( i8* @uc, i8 1 ) ; :1 [#uses=1] - store i8 %1, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :2 [#uses=1] - call i16 @llvm.atomic.swap.i16.p0i16( i16* %2, i16 1 ) ; :3 [#uses=1] - store i16 %3, i16* @ss, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :4 [#uses=1] - call i16 @llvm.atomic.swap.i16.p0i16( i16* %4, i16 1 ) ; :5 [#uses=1] - store i16 %5, i16* @us, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :6 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %6, i32 1 ) ; :7 [#uses=1] - store i32 %7, i32* @si, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :8 [#uses=1] - call i32 @llvm.atomic.swap.i32.p0i32( i32* %8, i32 1 ) ; :9 [#uses=1] - store i32 %9, i32* @ui, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :10 [#uses=1] - call i64 @llvm.atomic.swap.i64.p0i64( i64* %10, i64 1 ) ; :11 [#uses=1] - store i64 %11, i64* @sl, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :12 [#uses=1] - call i64 @llvm.atomic.swap.i64.p0i64( i64* %12, i64 1 ) ; :13 [#uses=1] - store i64 %13, i64* @ul, align 8 - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :14 [#uses=1] - call i64 @llvm.atomic.swap.i64.p0i64( i64* %14, i64 1 ) ; :15 [#uses=1] - store i64 %15, i64* @sll, align 8 - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :16 [#uses=1] - call i64 @llvm.atomic.swap.i64.p0i64( i64* %16, i64 1 ) ; :17 [#uses=1] - store i64 %17, i64* @ull, align 8 - call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true, i1 false ) - volatile store i8 0, i8* @sc, align 1 - volatile store i8 0, i8* @uc, align 1 - bitcast i8* bitcast (i16* @ss to i8*) to i16* ; :18 [#uses=1] - volatile store i16 0, i16* %18, align 2 - bitcast i8* bitcast (i16* @us to i8*) to i16* ; :19 [#uses=1] - volatile store i16 0, i16* %19, align 2 - bitcast i8* bitcast (i32* @si to i8*) to i32* ; :20 [#uses=1] - volatile store i32 0, i32* %20, align 4 - bitcast i8* bitcast (i32* @ui to i8*) to i32* ; :21 [#uses=1] - volatile store i32 0, i32* %21, align 4 - bitcast i8* bitcast (i64* @sl to i8*) to i64* ; :22 [#uses=1] - volatile store i64 0, i64* %22, align 8 - bitcast i8* bitcast (i64* @ul to i8*) to i64* ; :23 [#uses=1] - volatile store i64 0, i64* %23, align 8 - bitcast i8* bitcast (i64* @sll to i8*) to i64* ; :24 [#uses=1] - volatile store i64 0, i64* %24, align 8 - bitcast i8* bitcast (i64* @ull to i8*) to i64* ; :25 [#uses=1] - volatile store i64 0, i64* %25, align 8 - br label %return + %0 = atomicrmw xchg i8* @sc, i8 1 monotonic + store i8 %0, i8* @sc, align 1 + %1 = atomicrmw xchg i8* @uc, i8 1 monotonic + store i8 %1, i8* @uc, align 1 + %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + %3 = atomicrmw xchg i16* %2, i16 1 monotonic + store i16 %3, i16* @ss, align 2 + %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* + %5 = atomicrmw xchg i16* %4, i16 1 monotonic + store i16 %5, i16* @us, align 2 + %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* + %7 = atomicrmw xchg i32* %6, i32 1 monotonic + store i32 %7, i32* @si, align 4 + %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + %9 = atomicrmw xchg i32* %8, i32 1 monotonic + store i32 %9, i32* @ui, align 4 + %10 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + %11 = atomicrmw xchg i64* %10, i64 1 monotonic + store i64 %11, i64* @sl, align 8 + %12 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + %13 = atomicrmw xchg i64* %12, i64 1 monotonic + store i64 %13, i64* @ul, align 8 + %14 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + %15 = atomicrmw xchg i64* %14, i64 1 monotonic + store i64 %15, i64* @sll, align 8 + %16 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + %17 = atomicrmw xchg i64* %16, i64 1 monotonic + store i64 %17, i64* @ull, align 8 + fence seq_cst + store volatile i8 0, i8* @sc, align 1 + store volatile i8 0, i8* @uc, align 1 + %18 = bitcast i8* bitcast (i16* @ss to i8*) to i16* + store volatile i16 0, i16* %18, align 2 + %19 = bitcast i8* bitcast (i16* @us to i8*) to i16* + store volatile i16 0, i16* %19, align 2 + %20 = bitcast i8* bitcast (i32* @si to i8*) to i32* + store volatile i32 0, i32* %20, align 4 + %21 = bitcast i8* bitcast (i32* @ui to i8*) to i32* + store volatile i32 0, i32* %21, align 4 + %22 = bitcast i8* bitcast (i64* @sl to i8*) to i64* + store volatile i64 0, i64* %22, align 8 + %23 = bitcast i8* bitcast (i64* @ul to i8*) to i64* + store volatile i64 0, i64* %23, align 8 + %24 = bitcast i8* bitcast (i64* @sll to i8*) to i64* + store volatile i64 0, i64* %24, align 8 + %25 = bitcast i8* bitcast (i64* @ull to i8*) to i64* + store volatile i64 0, i64* %25, align 8 + br label %return -return: ; preds = %entry - ret void +return: ; preds = %entry + ret void } - -declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind - -declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind - -declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind - -declare i64 @llvm.atomic.swap.i64.p0i64(i64*, i64) nounwind - -declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind Modified: llvm/trunk/test/CodeGen/X86/atomic_op.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic_op.ll?rev=140585&r1=140584&r2=140585&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/atomic_op.ll (original) +++ llvm/trunk/test/CodeGen/X86/atomic_op.ll Mon Sep 26 19:17:29 2011 @@ -24,87 +24,87 @@ %tmp = load i32* %temp ; CHECK: lock ; CHECK: xaddl - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val1, i32 %tmp ) ; :0 [#uses=1] + %0 = atomicrmw add i32* %val1, i32 %tmp monotonic store i32 %0, i32* %old ; CHECK: lock ; CHECK: xaddl - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 30 ) ; :1 [#uses=1] + %1 = atomicrmw sub i32* %val2, i32 30 monotonic store i32 %1, i32* %old ; CHECK: lock ; CHECK: xaddl - call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val2, i32 1 ) ; :2 [#uses=1] + %2 = atomicrmw add i32* %val2, i32 1 monotonic store i32 %2, i32* %old ; CHECK: lock ; CHECK: xaddl - call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 1 ) ; :3 [#uses=1] + %3 = atomicrmw sub i32* %val2, i32 1 monotonic store i32 %3, i32* %old ; CHECK: andl ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.load.and.i32.p0i32( i32* %andt, i32 4080 ) ; :4 [#uses=1] + %4 = atomicrmw and i32* %andt, i32 4080 monotonic store i32 %4, i32* %old ; CHECK: orl ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.load.or.i32.p0i32( i32* %ort, i32 4080 ) ; :5 [#uses=1] + %5 = atomicrmw or i32* %ort, i32 4080 monotonic store i32 %5, i32* %old ; CHECK: xorl ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %xort, i32 4080 ) ; :6 [#uses=1] + %6 = atomicrmw xor i32* %xort, i32 4080 monotonic store i32 %6, i32* %old ; CHECK: cmov ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 16 ) ; :7 [#uses=1] + %7 = atomicrmw min i32* %val2, i32 16 monotonic store i32 %7, i32* %old %neg = sub i32 0, 1 ; [#uses=1] ; CHECK: cmov ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 %neg ) ; :8 [#uses=1] + %8 = atomicrmw min i32* %val2, i32 %neg monotonic store i32 %8, i32* %old ; CHECK: cmov ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 1 ) ; :9 [#uses=1] + %9 = atomicrmw max i32* %val2, i32 1 monotonic store i32 %9, i32* %old ; CHECK: cmov ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 0 ) ; :10 [#uses=1] + %10 = atomicrmw max i32* %val2, i32 0 monotonic store i32 %10, i32* %old ; CHECK: cmov ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %val2, i32 65535 ) ; :11 [#uses=1] + %11 = atomicrmw umax i32* %val2, i32 65535 monotonic store i32 %11, i32* %old ; CHECK: cmov ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %val2, i32 10 ) ; :12 [#uses=1] + %12 = atomicrmw umax i32* %val2, i32 10 monotonic store i32 %12, i32* %old ; CHECK: cmov ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %val2, i32 1 ) ; :13 [#uses=1] + %13 = atomicrmw umin i32* %val2, i32 1 monotonic store i32 %13, i32* %old ; CHECK: cmov ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %val2, i32 10 ) ; :14 [#uses=1] + %14 = atomicrmw umin i32* %val2, i32 10 monotonic store i32 %14, i32* %old ; CHECK: xchgl %{{.*}}, {{.*}}(%esp) - call i32 @llvm.atomic.swap.i32.p0i32( i32* %val2, i32 1976 ) ; :15 [#uses=1] + %15 = atomicrmw xchg i32* %val2, i32 1976 monotonic store i32 %15, i32* %old %neg1 = sub i32 0, 10 ; [#uses=1] ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %val2, i32 %neg1, i32 1 ) ; :16 [#uses=1] + %16 = cmpxchg i32* %val2, i32 %neg1, i32 1 monotonic store i32 %16, i32* %old ; CHECK: lock ; CHECK: cmpxchgl - call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %val2, i32 1976, i32 1 ) ; :17 [#uses=1] + %17 = cmpxchg i32* %val2, i32 1976, i32 1 monotonic store i32 %17, i32* %old ret void } @@ -114,30 +114,6 @@ ; CHECK: lock ; CHECK: cmpxchgl %{{.*}}, %gs:(%{{.*}}) - %0 = tail call i32 @llvm.atomic.cmp.swap.i32.p256i32(i32 addrspace(256)* %P, i32 0, i32 1) + %0 = cmpxchg i32 addrspace(256)* %P, i32 0, i32 1 monotonic ret void } - -declare i32 @llvm.atomic.cmp.swap.i32.p256i32(i32 addrspace(256)* nocapture, i32, i32) nounwind - -declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.min.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.max.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.umax.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.load.umin.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind - -declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind Modified: llvm/trunk/test/CodeGen/X86/barrier-sse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/barrier-sse.ll?rev=140585&r1=140584&r2=140585&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/barrier-sse.ll (original) +++ llvm/trunk/test/CodeGen/X86/barrier-sse.ll Mon Sep 26 19:17:29 2011 @@ -3,19 +3,9 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep mfence ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep MEMBARRIER - -declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1) - define void @test() { - call void @llvm.memory.barrier( i1 true, i1 true, i1 false, i1 false, i1 false) - call void @llvm.memory.barrier( i1 true, i1 false, i1 true, i1 false, i1 false) - call void @llvm.memory.barrier( i1 true, i1 false, i1 false, i1 true, i1 false) - - call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 false, i1 false) - call void @llvm.memory.barrier( i1 true, i1 true, i1 false, i1 true, i1 false) - call void @llvm.memory.barrier( i1 true, i1 false, i1 true, i1 true, i1 false) - - call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true , i1 false) - call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 false , i1 false) - ret void + fence acquire + fence release + fence acq_rel + ret void } Modified: llvm/trunk/test/CodeGen/X86/barrier.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/barrier.ll?rev=140585&r1=140584&r2=140585&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/barrier.ll (original) +++ llvm/trunk/test/CodeGen/X86/barrier.ll Mon Sep 26 19:17:29 2011 @@ -1,7 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=-sse2 | grep lock -declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1) define void @test() { - call void @llvm.memory.barrier( i1 true, i1 true, i1 false, i1 false, i1 false) + fence seq_cst ret void -} \ No newline at end of file +} Modified: llvm/trunk/test/CodeGen/X86/lfence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lfence.ll?rev=140585&r1=140584&r2=140585&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/lfence.ll (original) +++ llvm/trunk/test/CodeGen/X86/lfence.ll Mon Sep 26 19:17:29 2011 @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep lfence -declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1) +declare void @llvm.x86.sse2.lfence() nounwind define void @test() { - call void @llvm.memory.barrier( i1 true, i1 false, i1 false, i1 false, i1 true) - ret void + call void @llvm.x86.sse2.lfence() + ret void } Modified: llvm/trunk/test/CodeGen/X86/membarrier.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/membarrier.ll?rev=140585&r1=140584&r2=140585&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/membarrier.ll (original) +++ llvm/trunk/test/CodeGen/X86/membarrier.ll Mon Sep 26 19:17:29 2011 @@ -5,11 +5,8 @@ entry: %i = alloca i32, align 4 store i32 1, i32* %i, align 4 - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) - %0 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %i, i32 1) - call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + fence seq_cst + %0 = atomicrmw sub i32* %i, i32 1 monotonic + fence seq_cst ret i32 0 } - -declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind -declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind Modified: llvm/trunk/test/CodeGen/X86/mfence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mfence.ll?rev=140585&r1=140584&r2=140585&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/mfence.ll (original) +++ llvm/trunk/test/CodeGen/X86/mfence.ll Mon Sep 26 19:17:29 2011 @@ -2,19 +2,7 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep lfence ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mfence - -declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1) - define void @test() { - call void @llvm.memory.barrier( i1 true, i1 true, i1 false, i1 false, i1 true) - call void @llvm.memory.barrier( i1 true, i1 false, i1 true, i1 false, i1 true) - call void @llvm.memory.barrier( i1 true, i1 false, i1 false, i1 true, i1 true) - - call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 false, i1 true) - call void @llvm.memory.barrier( i1 true, i1 true, i1 false, i1 true, i1 true) - call void @llvm.memory.barrier( i1 true, i1 false, i1 true, i1 true, i1 true) - - call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true , i1 true) - call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 false , i1 true) - ret void + fence seq_cst + ret void } Removed: llvm/trunk/test/CodeGen/X86/nofence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/nofence.ll?rev=140584&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/nofence.ll (original) +++ llvm/trunk/test/CodeGen/X86/nofence.ll (removed) @@ -1,27 +0,0 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep fence - -declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1) - -define void @test() { - call void @llvm.memory.barrier( i1 true, i1 false, i1 false, i1 false, i1 false) - call void @llvm.memory.barrier( i1 false, i1 true, i1 false, i1 false, i1 false) - call void @llvm.memory.barrier( i1 false, i1 false, i1 true, i1 false, i1 false) - call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false) - - call void @llvm.memory.barrier( i1 true, i1 true, i1 false, i1 false, i1 false) - call void @llvm.memory.barrier( i1 true, i1 false, i1 true, i1 false, i1 false) - call void @llvm.memory.barrier( i1 true, i1 false, i1 false, i1 true, i1 false) - call void @llvm.memory.barrier( i1 false, i1 true, i1 true, i1 false, i1 false) - call void @llvm.memory.barrier( i1 false, i1 true, i1 false, i1 true, i1 false) - call void @llvm.memory.barrier( i1 false, i1 false, i1 true, i1 true, i1 false) - - call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 false, i1 false) - call void @llvm.memory.barrier( i1 true, i1 true, i1 false, i1 true, i1 false) - call void @llvm.memory.barrier( i1 true, i1 false, i1 true, i1 true, i1 false) - call void @llvm.memory.barrier( i1 false, i1 true, i1 true, i1 true, i1 false) - - - call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true , i1 false) - call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 false , i1 false) - ret void -} Modified: llvm/trunk/test/CodeGen/X86/sfence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sfence.ll?rev=140585&r1=140584&r2=140585&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sfence.ll (original) +++ llvm/trunk/test/CodeGen/X86/sfence.ll Mon Sep 26 19:17:29 2011 @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep sfence -declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1) +declare void @llvm.x86.sse.sfence() nounwind define void @test() { - call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true) - ret void + call void @llvm.x86.sse.sfence() + ret void } From atrick at apple.com Mon Sep 26 19:44:15 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 27 Sep 2011 00:44:15 -0000 Subject: [llvm-commits] [llvm] r140590 - /llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <20110927004415.289422A6C12C@llvm.org> Author: atrick Date: Mon Sep 26 19:44:14 2011 New Revision: 140590 URL: http://llvm.org/viewvc/llvm-project?rev=140590&view=rev Log: Disable LSR retry by default. Disabling aggressive LSR saves compilation time, and with the new indvars behavior usually improves performance. Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=140590&r1=140589&r2=140590&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Mon Sep 26 19:44:14 2011 @@ -70,12 +70,18 @@ #include "llvm/ADT/SetVector.h" #include "llvm/ADT/DenseSet.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/ValueHandle.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetLowering.h" #include using namespace llvm; +namespace llvm { +cl::opt EnableRetry( + "enable-lsr-retry", cl::Hidden, cl::desc("Enable LSR retry")); +} + namespace { /// RegSortData - This class holds data which is used to order reuse candidates. @@ -3309,6 +3315,9 @@ skip:; } + if (!EnableRetry && !AnySatisfiedReqRegs) + return; + // If none of the formulae had all of the required registers, relax the // constraint so that we don't exclude all formulae. if (!AnySatisfiedReqRegs) { @@ -3332,6 +3341,10 @@ // SolveRecurse does all the work. SolveRecurse(Solution, SolutionCost, Workspace, CurCost, CurRegs, VisitedRegs); + if (Solution.empty()) { + DEBUG(dbgs() << "\nNo Satisfactory Solution\n"); + return; + } // Ok, we've now made all our decisions. DEBUG(dbgs() << "\n" @@ -3811,6 +3824,9 @@ Types.clear(); RegUses.clear(); + if (Solution.empty()) + return; + #ifndef NDEBUG // Formulae should be legal. for (SmallVectorImpl::const_iterator I = Uses.begin(), From isanbard at gmail.com Mon Sep 26 19:59:32 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Sep 2011 00:59:32 -0000 Subject: [llvm-commits] [llvm] r140592 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnswitch.cpp test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll Message-ID: <20110927005932.16A472A6C12C@llvm.org> Author: void Date: Mon Sep 26 19:59:31 2011 New Revision: 140592 URL: http://llvm.org/viewvc/llvm-project?rev=140592&view=rev Log: Split the landing pad basic block with the correct function. Also merge the split landingpad instructions into a PHI node. PR11016 Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=140592&r1=140591&r2=140592&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Mon Sep 26 19:59:31 2011 @@ -561,10 +561,17 @@ BasicBlock *ExitBlock = ExitBlocks[i]; SmallVector Preds(pred_begin(ExitBlock), pred_end(ExitBlock)); + // Although SplitBlockPredecessors doesn't preserve loop-simplify in // general, if we call it on all predecessors of all exits then it does. - SplitBlockPredecessors(ExitBlock, Preds.data(), Preds.size(), - ".us-lcssa", this); + if (!ExitBlock->isLandingPad()) { + SplitBlockPredecessors(ExitBlock, Preds.data(), Preds.size(), + ".us-lcssa", this); + } else { + SmallVector NewBBs; + SplitLandingPadPredecessors(ExitBlock, Preds, ".us-lcssa", ".us-lcssa", + this, NewBBs); + } } } @@ -632,7 +639,7 @@ // as well. ParentLoop->addBasicBlockToLoop(NewBlocks[0], LI->getBase()); } - + for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i) { BasicBlock *NewExit = cast(VMap[ExitBlocks[i]]); // The new exit block should be in the same loop as the old one. @@ -653,6 +660,19 @@ if (It != VMap.end()) V = It->second; PN->addIncoming(V, NewExit); } + + if (LandingPadInst *LPad = NewExit->getLandingPadInst()) { + PN = PHINode::Create(LPad->getType(), 0, "", + ExitSucc->getFirstInsertionPt()); + + for (pred_iterator I = pred_begin(ExitSucc), E = pred_end(ExitSucc); + I != E; ++I) { + BasicBlock *BB = *I; + LandingPadInst *LPI = BB->getLandingPadInst(); + LPI->replaceAllUsesWith(PN); + PN->addIncoming(LPI, BB); + } + } } // Rewrite the code to refer to itself. Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll?rev=140592&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll (added) +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll Mon Sep 26 19:59:31 2011 @@ -0,0 +1,67 @@ +; RUN: opt < %s -scalarrepl-ssa -loop-unswitch -disable-output +; PR11016 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.7.2" + +%class.MyContainer.1.3.19.29 = type { [6 x %class.MyMemVarClass.0.2.18.28*] } +%class.MyMemVarClass.0.2.18.28 = type { i32 } + +define void @_ZN11MyContainer1fEi(%class.MyContainer.1.3.19.29* %this, i32 %doit) uwtable ssp align 2 { +entry: + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %inc1 = phi i32 [ %inc, %for.inc ], [ 0, %entry ] + %conv = sext i32 %inc1 to i64 + %cmp = icmp ult i64 %conv, 6 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + %tobool = icmp ne i32 %doit, 0 + br i1 %tobool, label %for.inc, label %if.then + +if.then: ; preds = %for.body + %idxprom = sext i32 %inc1 to i64 + %array_ = getelementptr inbounds %class.MyContainer.1.3.19.29* %this, i32 0, i32 0 + %arrayidx = getelementptr inbounds [6 x %class.MyMemVarClass.0.2.18.28*]* %array_, i32 0, i64 %idxprom + %tmp4 = load %class.MyMemVarClass.0.2.18.28** %arrayidx, align 8, !tbaa !0 + %isnull = icmp eq %class.MyMemVarClass.0.2.18.28* %tmp4, null + br i1 %isnull, label %for.inc, label %delete.notnull + +delete.notnull: ; preds = %if.then + invoke void @_ZN13MyMemVarClassD1Ev(%class.MyMemVarClass.0.2.18.28* %tmp4) + to label %invoke.cont unwind label %lpad + +invoke.cont: ; preds = %delete.notnull + %0 = bitcast %class.MyMemVarClass.0.2.18.28* %tmp4 to i8* + call void @_ZdlPv(i8* %0) nounwind + br label %for.inc + +lpad: ; preds = %delete.notnull + %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + %2 = extractvalue { i8*, i32 } %1, 0 + %3 = extractvalue { i8*, i32 } %1, 1 + %4 = bitcast %class.MyMemVarClass.0.2.18.28* %tmp4 to i8* + call void @_ZdlPv(i8* %4) nounwind + %lpad.val = insertvalue { i8*, i32 } undef, i8* %2, 0 + %lpad.val7 = insertvalue { i8*, i32 } %lpad.val, i32 %3, 1 + resume { i8*, i32 } %lpad.val7 + +for.inc: ; preds = %invoke.cont, %if.then, %for.body + %inc = add nsw i32 %inc1, 1 + br label %for.cond + +for.end: ; preds = %for.cond + ret void +} + +declare void @_ZN13MyMemVarClassD1Ev(%class.MyMemVarClass.0.2.18.28*) + +declare i32 @__gxx_personality_v0(...) + +declare void @_ZdlPv(i8*) nounwind + +!0 = metadata !{metadata !"any pointer", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} From justin.holewinski at gmail.com Mon Sep 26 20:04:47 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Tue, 27 Sep 2011 01:04:47 -0000 Subject: [llvm-commits] [llvm] r140593 - in /llvm/trunk: lib/Target/PTX/PTXInstrInfo.td test/CodeGen/PTX/20110926-sitofp.ll test/CodeGen/PTX/cvt.ll Message-ID: <20110927010447.30D9D2A6C12C@llvm.org> Author: jholewinski Date: Mon Sep 26 20:04:47 2011 New Revision: 140593 URL: http://llvm.org/viewvc/llvm-project?rev=140593&view=rev Log: PTX: Add support for sitofp in backend Added: llvm/trunk/test/CodeGen/PTX/20110926-sitofp.ll Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td llvm/trunk/test/CodeGen/PTX/cvt.ll Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=140593&r1=140592&r2=140593&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Mon Sep 26 20:04:47 2011 @@ -826,6 +826,19 @@ : InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a", [(set RegF32:$d, (fround RegF64:$a))]>; +def CVT_f32_s16 + : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.s16\t$d, $a", + [(set RegF32:$d, (sint_to_fp RegI16:$a))]>; + +def CVT_f32_s32 + : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.s32\t$d, $a", + [(set RegF32:$d, (sint_to_fp RegI32:$a))]>; + +def CVT_f32_s64 + : InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.s64\t$d, $a", + [(set RegF32:$d, (sint_to_fp RegI64:$a))]>; + + // Conversion to f64 def CVT_f64_pred @@ -849,6 +862,18 @@ : InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a", [(set RegF64:$d, (fextend RegF32:$a))]>; +def CVT_f64_s16 + : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.s16\t$d, $a", + [(set RegF64:$d, (sint_to_fp RegI16:$a))]>; + +def CVT_f64_s32 + : InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.s32\t$d, $a", + [(set RegF64:$d, (sint_to_fp RegI32:$a))]>; + +def CVT_f64_s64 + : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.s64\t$d, $a", + [(set RegF64:$d, (sint_to_fp RegI64:$a))]>; + // NOTE: These are temporarily here to help test some Clang-generated code. // We really need to properly introduce anyext and bitconvert into the back-end. // ANY_EXTEND Added: llvm/trunk/test/CodeGen/PTX/20110926-sitofp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/20110926-sitofp.ll?rev=140593&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PTX/20110926-sitofp.ll (added) +++ llvm/trunk/test/CodeGen/PTX/20110926-sitofp.ll Mon Sep 26 20:04:47 2011 @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=ptx32 | FileCheck %s + + at A = common global [1536 x [1536 x float]] zeroinitializer, align 4 + at B = common global [1536 x [1536 x float]] zeroinitializer, align 4 + +define internal ptx_device void @init_array(i32 %x, i32 %y) { + %arrayidx103 = getelementptr [1536 x [1536 x float]]* @A, i32 0, i32 %x, i32 %y + %arrayidx224 = getelementptr [1536 x [1536 x float]]* @B, i32 0, i32 %x, i32 %y + %mul5 = mul i32 %x, %y + %rem = srem i32 %mul5, 1024 + %add = add nsw i32 %rem, 1 +; CHECK: cvt.rn.f64.s32 %fd{{[0-9]+}}, %r{{[0-9]+}} + %conv = sitofp i32 %add to double + %div = fmul double %conv, 5.000000e-01 + %conv7 = fptrunc double %div to float + store float %conv7, float* %arrayidx103, align 4 + %rem14 = srem i32 %mul5, 1024 + %add15 = add nsw i32 %rem14, 1 + %conv16 = sitofp i32 %add15 to double + %div17 = fmul double %conv16, 5.000000e-01 + %conv18 = fptrunc double %div17 to float + store float %conv18, float* %arrayidx224, align 4 + ret void +} Modified: llvm/trunk/test/CodeGen/PTX/cvt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/cvt.ll?rev=140593&r1=140592&r2=140593&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/cvt.ll (original) +++ llvm/trunk/test/CodeGen/PTX/cvt.ll Mon Sep 26 20:04:47 2011 @@ -206,6 +206,27 @@ ret float %a } +define ptx_device float @cvt_f32_s16(i16 %x) { +; CHECK: cvt.rn.f32.s16 %ret{{[0-9]+}}, %rh{{[0-9]+}} +; CHECK: ret + %a = sitofp i16 %x to float + ret float %a +} + +define ptx_device float @cvt_f32_s32(i32 %x) { +; CHECK: cvt.rn.f32.s32 %ret{{[0-9]+}}, %r{{[0-9]+}} +; CHECK: ret + %a = sitofp i32 %x to float + ret float %a +} + +define ptx_device float @cvt_f32_s64(i64 %x) { +; CHECK: cvt.rn.f32.s64 %ret{{[0-9]+}}, %rd{{[0-9]+}} +; CHECK: ret + %a = sitofp i64 %x to float + ret float %a +} + ; f64 define ptx_device double @cvt_f64_preds(i1 %x) { @@ -242,3 +263,24 @@ %a = fpext float %x to double ret double %a } + +define ptx_device double @cvt_f64_s16(i16 %x) { +; CHECK: cvt.rn.f64.s16 %ret{{[0-9]+}}, %rh{{[0-9]+}} +; CHECK: ret + %a = sitofp i16 %x to double + ret double %a +} + +define ptx_device double @cvt_f64_s32(i32 %x) { +; CHECK: cvt.rn.f64.s32 %ret{{[0-9]+}}, %r{{[0-9]+}} +; CHECK: ret + %a = sitofp i32 %x to double + ret double %a +} + +define ptx_device double @cvt_f64_s64(i64 %x) { +; CHECK: cvt.rn.f64.s64 %ret{{[0-9]+}}, %rd{{[0-9]+}} +; CHECK: ret + %a = sitofp i64 %x to double + ret double %a +} From ahatanak at gmail.com Mon Sep 26 23:57:54 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 27 Sep 2011 04:57:54 -0000 Subject: [llvm-commits] [llvm] r140598 - /llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Message-ID: <20110927045754.5A8D82A6C12C@llvm.org> Author: ahatanak Date: Mon Sep 26 23:57:54 2011 New Revision: 140598 URL: http://llvm.org/viewvc/llvm-project?rev=140598&view=rev Log: Mark MipsPseudo isPseudo. Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=140598&r1=140597&r2=140598&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Mon Sep 26 23:57:54 2011 @@ -44,7 +44,9 @@ // Mips Pseudo Instructions Format class MipsPseudo pattern>: - MipsInst; + MipsInst { + let isPseudo = 1; +} //===----------------------------------------------------------------------===// // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> From baldrick at free.fr Tue Sep 27 03:28:38 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 27 Sep 2011 10:28:38 +0200 Subject: [llvm-commits] [llvm] r140463 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp In-Reply-To: <20110924183219.593FA2A6C12C@llvm.org> References: <20110924183219.593FA2A6C12C@llvm.org> Message-ID: <4E818936.8070808@free.fr> Hi Nadav, > [Vector-Select] Address one of the problems in 10902. > > When generating the trunc-store of i1's, we need to use the vector type and not > the scalar type. > > This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when > running with -promote-elements. I think this is wrong. Maybe wrong is too harsh :) It was decided that vectors would be stored bit-packed. This doesn't make any difference for vectors of i8, i32 etc. But it means that <4 x i1> will be stored the same as an i4, namely in 4 consecutive bits of one byte. Your patch will store <4 x i1> using 4 bytes. I'm not totally convinced that bit-packing is the right thing to do. But even if we were to go with your method there are other problems: things like the store size etc need to be consistent with what is actually done. The store size for <4 x i1> is (IIRC) 1 byte, but you are overwriting 4 bytes, so alias analysis (which uses the store size) is going to return wrong results. Also, the store size must never be larger than the type alloc size, so if you change the store size you will need to touch the alloc size too. However the alloc size needs to agree with sizeof in C, so you will have to fix clang as well (since it can produce these kinds of types IIRC). There are a bunch of places that assume that the store size is the size rounded up to the nearest byte, so these will have to be fixed too. And so on. Getting this right, having all parts of LLVM work correctly together, is a large project in itself. I doubt you want to go there. I think you should revert this patch. I'd rather have codegen fail with an assertion rather than silently produce wrong code. In fact it would be great if you added even more assertions! Ciao, Duncan. > > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=140463&r1=140462&r2=140463&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Sep 24 13:32:19 2011 > @@ -1180,6 +1180,10 @@ > // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. > unsigned NewWidth = SrcVT.getStoreSizeInBits(); > EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); > + if (SrcVT.isVector()) { > + NVT = EVT::getVectorVT(*DAG.getContext(), NVT, > + SrcVT.getVectorNumElements()); > + } > SDValue Ch; > > // The extra bits are guaranteed to be zero, since we stored them that > @@ -1521,7 +1525,12 @@ > // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) > EVT NVT = EVT::getIntegerVT(*DAG.getContext(), > StVT.getStoreSizeInBits()); > - Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); > + if (StVT.isVector()) { > + NVT = EVT::getVectorVT(*DAG.getContext(), NVT, > + StVT.getVectorNumElements()); > + } > + > + Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT.getScalarType()); > Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), > NVT, isVolatile, isNonTemporal, Alignment); > } else if (StWidth& (StWidth - 1)) { > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Tue Sep 27 05:37:28 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Sep 2011 10:37:28 -0000 Subject: [llvm-commits] [llvm] r140600 - /llvm/trunk/docs/ExceptionHandling.html Message-ID: <20110927103728.5AFA82A6C12C@llvm.org> Author: void Date: Tue Sep 27 05:37:28 2011 New Revision: 140600 URL: http://llvm.org/viewvc/llvm-project?rev=140600&view=rev Log: Remove some not-really-correct wording. Modified: llvm/trunk/docs/ExceptionHandling.html Modified: llvm/trunk/docs/ExceptionHandling.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ExceptionHandling.html?rev=140600&r1=140599&r2=140600&view=diff ============================================================================== --- llvm/trunk/docs/ExceptionHandling.html (original) +++ llvm/trunk/docs/ExceptionHandling.html Tue Sep 27 05:37:28 2011 @@ -261,7 +261,7 @@ and filter clauses. The exception is tested against the clauses sequentially from first to last. The selector value is a positive number if the exception matched a type info, a negative number if it matched a filter, - and zero if it matched to a cleanup. If nothing is matched, the behavior of + and zero if it matched a cleanup. If nothing is matched, the behavior of the program is undefined. If a type info matched, then the selector value is the index of the type info in the exception table, which can be obtained using the @@ -276,11 +276,6 @@ determine the index for a given type info. If the catch fails to match the selector then control is passed on to the next catch.

    -

    Note: Since the landing pad will not be used if there is no match in - the list of type info on the call to the landingpad instruction, - then neither the last catch nor catch all need to perform the check - against the selector.

    -

    Finally, the entry and exit of catch code is bracketed with calls to __cxa_begin_catch and __cxa_end_catch.

    From nadav.rotem at intel.com Tue Sep 27 05:48:29 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Tue, 27 Sep 2011 10:48:29 -0000 Subject: [llvm-commits] [llvm] r140601 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20110927104829.8307C2A6C12C@llvm.org> Author: nadav Date: Tue Sep 27 05:48:29 2011 New Revision: 140601 URL: http://llvm.org/viewvc/llvm-project?rev=140601&view=rev Log: Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8, while the decision is to bit-pack small values. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=140601&r1=140600&r2=140601&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Sep 27 05:48:29 2011 @@ -1180,10 +1180,6 @@ // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. unsigned NewWidth = SrcVT.getStoreSizeInBits(); EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); - if (SrcVT.isVector()) { - NVT = EVT::getVectorVT(*DAG.getContext(), NVT, - SrcVT.getVectorNumElements()); - } SDValue Ch; // The extra bits are guaranteed to be zero, since we stored them that @@ -1525,12 +1521,7 @@ // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits()); - if (StVT.isVector()) { - NVT = EVT::getVectorVT(*DAG.getContext(), NVT, - StVT.getVectorNumElements()); - } - - Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT.getScalarType()); + Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), NVT, isVolatile, isNonTemporal, Alignment); } else if (StWidth & (StWidth - 1)) { From nadav.rotem at intel.com Tue Sep 27 06:16:47 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Tue, 27 Sep 2011 11:16:47 -0000 Subject: [llvm-commits] [llvm] r140603 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <20110927111647.769C42A6C12C@llvm.org> Author: nadav Date: Tue Sep 27 06:16:47 2011 New Revision: 140603 URL: http://llvm.org/viewvc/llvm-project?rev=140603&view=rev Log: Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC. Add a new method: getAnyExtOrTrunc and use it to replace the manual check. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=140603&r1=140602&r2=140603&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Sep 27 06:16:47 2011 @@ -450,6 +450,10 @@ SDValue getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1, SDValue N2, const int *MaskElts); + /// getAnyExtOrTrunc - Convert Op, which must be of integer type, to the + /// integer type VT, by either any-extending or truncating it. + SDValue getAnyExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT); + /// getSExtOrTrunc - Convert Op, which must be of integer type, to the /// integer type VT, by either sign-extending or truncating it. SDValue getSExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=140603&r1=140602&r2=140603&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Sep 27 06:16:47 2011 @@ -504,14 +504,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); - // Convert to the expected type. EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); // Only use the result of getSetCCResultType if it is legal, // otherwise just use the promoted result type (NVT). - if (getTypeAction(SVT) != TargetLowering::TypeLegal) { - SVT = NVT; - } + if (!TLI.isTypeLegal(SVT)) + SVT = NVT; DebugLoc dl = N->getDebugLoc(); assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() && @@ -522,6 +520,7 @@ N->getOperand(1), N->getOperand(2)); assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); + // Convert to the expected type. return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); } @@ -2988,12 +2987,9 @@ V0->getValueType(0).getScalarType(), V0, V1); // EXTRACT_VECTOR_ELT can return types which are wider than the incoming - // element types (see PromoteIntRes_EXTRACT_VECTOR_ELT). If this is the case - // then we need to expand the outgoing value and not truncate it. - bool trunc = (N->getValueType(0).getSizeInBits() < - Ext.getValueType().getSizeInBits()); - return DAG.getNode(trunc ? ISD::TRUNCATE : ISD::ANY_EXTEND, - dl, N->getValueType(0), Ext); + // element types. If this is the case then we need to expand the outgoing + // value and not truncate it. + return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0)); } SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=140603&r1=140602&r2=140603&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep 27 06:16:47 2011 @@ -881,6 +881,12 @@ DbgInfo->clear(); } +SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) { + return VT.bitsGT(Op.getValueType()) ? + getNode(ISD::ANY_EXTEND, DL, VT, Op) : + getNode(ISD::TRUNCATE, DL, VT, Op); +} + SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) { return VT.bitsGT(Op.getValueType()) ? getNode(ISD::SIGN_EXTEND, DL, VT, Op) : From baldrick at free.fr Tue Sep 27 06:59:22 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 27 Sep 2011 13:59:22 +0200 Subject: [llvm-commits] [llvm] r140600 - /llvm/trunk/docs/ExceptionHandling.html In-Reply-To: <20110927103728.5AFA82A6C12C@llvm.org> References: <20110927103728.5AFA82A6C12C@llvm.org> Message-ID: <4E81BA9A.1090705@free.fr> Hi Bill, > --- llvm/trunk/docs/ExceptionHandling.html (original) > +++ llvm/trunk/docs/ExceptionHandling.html Tue Sep 27 05:37:28 2011 > @@ -261,7 +261,7 @@ > andfilter clauses. The exception is tested against the clauses > sequentially from first to last. The selector value is a positive number if > the exception matched a type info, a negative number if it matched a filter, > - and zero if it matched to a cleanup. If nothing is matched, the behavior of > + and zero if it matched a cleanup. If nothing is matched, the behavior of > the program isundefined. as I mentioned in a previous email the behaviour is not undefined at all. Ciao, Duncan. From baldrick at free.fr Tue Sep 27 11:43:19 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 27 Sep 2011 16:43:19 -0000 Subject: [llvm-commits] [llvm] r140606 - /llvm/trunk/lib/VMCore/Verifier.cpp Message-ID: <20110927164319.B12062A6C12C@llvm.org> Author: baldrick Date: Tue Sep 27 11:43:19 2011 New Revision: 140606 URL: http://llvm.org/viewvc/llvm-project?rev=140606&view=rev Log: Have the verifier check that all landingpad operands are constants. Modified: llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=140606&r1=140605&r2=140606&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Tue Sep 27 11:43:19 2011 @@ -1449,6 +1449,17 @@ "Personality function doesn't match others in function", &LPI); PersonalityFn = LPI.getPersonalityFn(); + // All operands must be constants. + Assert1(isa(PersonalityFn), "Personality function is not constant!", + &LPI); + for (unsigned i = 0, e = LPI.getNumClauses(); i < e; ++i) { + Value *Clause = LPI.getClause(i); + Assert1(isa(Clause), "Clause is not constant!", &LPI); + if (LPI.isFilter(i)) + Assert1(isa(Clause) || isa(Clause), + "Filter is not an array of constants!", &LPI); + } + visitInstruction(LPI); } From ahatanak at gmail.com Tue Sep 27 11:58:43 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 27 Sep 2011 16:58:43 -0000 Subject: [llvm-commits] [llvm] r140607 - /llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Message-ID: <20110927165843.E93442A6C12F@llvm.org> Author: ahatanak Date: Tue Sep 27 11:58:43 2011 New Revision: 140607 URL: http://llvm.org/viewvc/llvm-project?rev=140607&view=rev Log: Do not add the pass that restores $gp if target is Mips64. Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=140607&r1=140606&r2=140607&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Tue Sep 27 11:58:43 2011 @@ -96,7 +96,10 @@ bool MipsTargetMachine:: addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { - PM.add(createMipsEmitGPRestorePass(*this)); + // Do not restore $gp if target is Mips64. + // In N32/64, $gp is a callee-saved register. + if (!Subtarget.hasMips64()) + PM.add(createMipsEmitGPRestorePass(*this)); return true; } From ahatanak at gmail.com Tue Sep 27 12:15:27 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 27 Sep 2011 17:15:27 -0000 Subject: [llvm-commits] [llvm] r140609 - /llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Message-ID: <20110927171527.636262A6C12C@llvm.org> Author: ahatanak Date: Tue Sep 27 12:15:27 2011 New Revision: 140609 URL: http://llvm.org/viewvc/llvm-project?rev=140609&view=rev Log: Fix function MipsRegisterInfo::getRegisterNumbering. Return numbers of 64-bit registers. Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=140609&r1=140608&r2=140609&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Tue Sep 27 12:15:27 2011 @@ -51,39 +51,87 @@ getRegisterNumbering(unsigned RegEnum) { switch (RegEnum) { - case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0; - case Mips::AT : case Mips::F1 : return 1; - case Mips::V0 : case Mips::F2 : case Mips::D1 : return 2; - case Mips::V1 : case Mips::F3 : return 3; - case Mips::A0 : case Mips::F4 : case Mips::D2 : return 4; - case Mips::A1 : case Mips::F5 : return 5; - case Mips::A2 : case Mips::F6 : case Mips::D3 : return 6; - case Mips::A3 : case Mips::F7 : return 7; - case Mips::T0 : case Mips::F8 : case Mips::D4 : return 8; - case Mips::T1 : case Mips::F9 : return 9; - case Mips::T2 : case Mips::F10: case Mips::D5: return 10; - case Mips::T3 : case Mips::F11: return 11; - case Mips::T4 : case Mips::F12: case Mips::D6: return 12; - case Mips::T5 : case Mips::F13: return 13; - case Mips::T6 : case Mips::F14: case Mips::D7: return 14; - case Mips::T7 : case Mips::F15: return 15; - case Mips::S0 : case Mips::F16: case Mips::D8: return 16; - case Mips::S1 : case Mips::F17: return 17; - case Mips::S2 : case Mips::F18: case Mips::D9: return 18; - case Mips::S3 : case Mips::F19: return 19; - case Mips::S4 : case Mips::F20: case Mips::D10: return 20; - case Mips::S5 : case Mips::F21: return 21; - case Mips::S6 : case Mips::F22: case Mips::D11: return 22; - case Mips::S7 : case Mips::F23: return 23; - case Mips::T8 : case Mips::F24: case Mips::D12: return 24; - case Mips::T9 : case Mips::F25: return 25; - case Mips::K0 : case Mips::F26: case Mips::D13: return 26; - case Mips::K1 : case Mips::F27: return 27; - case Mips::GP : case Mips::F28: case Mips::D14: return 28; - case Mips::SP : case Mips::F29: return 29; - case Mips::FP : case Mips::F30: case Mips::D15: return 30; - case Mips::RA : case Mips::F31: return 31; - default: llvm_unreachable("Unknown register number!"); + case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64: + case Mips::D0: + return 0; + case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64: + return 1; + case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64: + case Mips::D1: + return 2; + case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64: + return 3; + case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64: + case Mips::D2: + return 4; + case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64: + return 5; + case Mips::A2: case Mips::A2_64: case Mips::F6: case Mips::D6_64: + case Mips::D3: + return 6; + case Mips::A3: case Mips::A3_64: case Mips::F7: case Mips::D7_64: + return 7; + case Mips::T0: case Mips::T0_64: case Mips::F8: case Mips::D8_64: + case Mips::D4: + return 8; + case Mips::T1: case Mips::T1_64: case Mips::F9: case Mips::D9_64: + return 9; + case Mips::T2: case Mips::T2_64: case Mips::F10: case Mips::D10_64: + case Mips::D5: + return 10; + case Mips::T3: case Mips::T3_64: case Mips::F11: case Mips::D11_64: + return 11; + case Mips::T4: case Mips::T4_64: case Mips::F12: case Mips::D12_64: + case Mips::D6: + return 12; + case Mips::T5: case Mips::T5_64: case Mips::F13: case Mips::D13_64: + return 13; + case Mips::T6: case Mips::T6_64: case Mips::F14: case Mips::D14_64: + case Mips::D7: + return 14; + case Mips::T7: case Mips::T7_64: case Mips::F15: case Mips::D15_64: + return 15; + case Mips::S0: case Mips::S0_64: case Mips::F16: case Mips::D16_64: + case Mips::D8: + return 16; + case Mips::S1: case Mips::S1_64: case Mips::F17: case Mips::D17_64: + return 17; + case Mips::S2: case Mips::S2_64: case Mips::F18: case Mips::D18_64: + case Mips::D9: + return 18; + case Mips::S3: case Mips::S3_64: case Mips::F19: case Mips::D19_64: + return 19; + case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64: + case Mips::D10: + return 20; + case Mips::S5: case Mips::S5_64: case Mips::F21: case Mips::D21_64: + return 21; + case Mips::S6: case Mips::S6_64: case Mips::F22: case Mips::D22_64: + case Mips::D11: + return 22; + case Mips::S7: case Mips::S7_64: case Mips::F23: case Mips::D23_64: + return 23; + case Mips::T8: case Mips::T8_64: case Mips::F24: case Mips::D24_64: + case Mips::D12: + return 24; + case Mips::T9: case Mips::T9_64: case Mips::F25: case Mips::D25_64: + return 25; + case Mips::K0: case Mips::K0_64: case Mips::F26: case Mips::D26_64: + case Mips::D13: + return 26; + case Mips::K1: case Mips::K1_64: case Mips::F27: case Mips::D27_64: + return 27; + case Mips::GP: case Mips::GP_64: case Mips::F28: case Mips::D28_64: + case Mips::D14: + return 28; + case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64: + return 29; + case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64: + case Mips::D15: + return 30; + case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64: + return 31; + default: llvm_unreachable("Unknown register number!"); } return 0; // Not reached } From stoklund at 2pi.dk Tue Sep 27 12:55:08 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 27 Sep 2011 17:55:08 -0000 Subject: [llvm-commits] [llvm] r140615 - /llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp Message-ID: <20110927175508.B90122A6C12C@llvm.org> Author: stoklund Date: Tue Sep 27 12:55:08 2011 New Revision: 140615 URL: http://llvm.org/viewvc/llvm-project?rev=140615&view=rev Log: Use existing function. Modified: llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp Modified: llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp?rev=140615&r1=140614&r2=140615&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp (original) +++ llvm/trunk/lib/Target/ARM/NEONMoveFix.cpp Tue Sep 27 12:55:08 2011 @@ -40,8 +40,6 @@ typedef DenseMap RegMap; bool InsertMoves(MachineBasicBlock &MBB); - - void TransferImpOps(MachineInstr &Old, MachineInstr &New); }; char NEONMoveFixPass::ID = 0; } @@ -51,16 +49,6 @@ (isA8 && (Domain & ARMII::DomainNEONA8)); } -/// Transfer implicit kill and def operands from Old to New. -void NEONMoveFixPass::TransferImpOps(MachineInstr &Old, MachineInstr &New) { - for (unsigned i = 0, e = Old.getNumOperands(); i != e; ++i) { - MachineOperand &MO = Old.getOperand(i); - if (!MO.isReg() || !MO.isImplicit()) - continue; - New.addOperand(MO); - } -} - bool NEONMoveFixPass::InsertMoves(MachineBasicBlock &MBB) { RegMap Defs; bool Modified = false; @@ -100,7 +88,7 @@ AddDefaultPred(BuildMI(MBB, *MI, MI->getDebugLoc(), TII->get(ARM::VORRd), DestReg) .addReg(SrcReg).addReg(SrcReg)); - TransferImpOps(*MI, *NewMI); + NewMI->copyImplicitOps(MI); MBB.erase(MI); MI = NewMI; From justin.holewinski at gmail.com Tue Sep 27 13:12:55 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Tue, 27 Sep 2011 18:12:55 -0000 Subject: [llvm-commits] [llvm] r140616 - in /llvm/trunk/lib/Target/PTX: PTXAsmPrinter.cpp PTXISelDAGToDAG.cpp PTXISelLowering.cpp PTXInstrLoadStore.td PTXMachineFunctionInfo.h PTXRegisterInfo.cpp Message-ID: <20110927181256.0C1572A6C12C@llvm.org> Author: jholewinski Date: Tue Sep 27 13:12:55 2011 New Revision: 140616 URL: http://llvm.org/viewvc/llvm-project?rev=140616&view=rev Log: PTX: Use external symbols to keep track of params and locals. This also fixes a couple of outstanding issues with frame objects occuring as instruction operands. Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140616&r1=140615&r2=140616&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Tue Sep 27 13:12:55 2011 @@ -66,10 +66,6 @@ void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, const char *Modifier = 0); - void printParamOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, - const char *Modifier = 0); - void printLocalOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, - const char *Modifier = 0); void printReturnOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, const char *Modifier = 0); void printPredicateOperand(const MachineInstr *MI, raw_ostream &O); @@ -415,6 +411,9 @@ case MachineOperand::MO_Register: OS << MFI->getRegisterName(MO.getReg()); break; + case MachineOperand::MO_ExternalSymbol: + OS << MO.getSymbolName(); + break; case MachineOperand::MO_FPImmediate: APInt constFP = MO.getFPImm()->getValueAPF().bitcastToAPInt(); bool isFloat = MO.getFPImm()->getType()->getTypeID() == Type::FloatTyID; @@ -451,29 +450,12 @@ printOperand(MI, opNum+1, OS); } -void PTXAsmPrinter::printParamOperand(const MachineInstr *MI, int opNum, - raw_ostream &OS, const char *Modifier) { - const PTXMachineFunctionInfo *MFI = MI->getParent()->getParent()-> - getInfo(); - OS << MFI->getParamManager().getParamName(MI->getOperand(opNum).getImm()); -} - void PTXAsmPrinter::printReturnOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, const char *Modifier) { //OS << RETURN_PREFIX << (int) MI->getOperand(opNum).getImm() + 1; OS << "__ret"; } -void PTXAsmPrinter::printLocalOperand(const MachineInstr *MI, int opNum, - raw_ostream &OS, const char *Modifier) { - OS << "__local" << MI->getOperand(opNum).getImm(); - - if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() != 0){ - OS << "+"; - printOperand(MI, opNum+1, OS); - } -} - void PTXAsmPrinter::EmitVariableDeclaration(const GlobalVariable *gv) { // Check to see if this is a special global used by LLVM, if so, emit it. if (EmitSpecialLLVMGlobal(gv)) @@ -702,7 +684,7 @@ } else { O << ", "; } - printParamOperand(MI, Index, O); + printOperand(MI, Index, O); Index++; } @@ -718,7 +700,7 @@ Index++; while (Index < MI->getNumOperands()) { - printParamOperand(MI, Index, O); + printOperand(MI, Index, O); if (Index < MI->getNumOperands()-1) { O << ", "; } Modified: llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp?rev=140616&r1=140615&r2=140616&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp Tue Sep 27 13:12:55 2011 @@ -12,7 +12,9 @@ //===----------------------------------------------------------------------===// #include "PTX.h" +#include "PTXMachineFunctionInfo.h" #include "PTXTargetMachine.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/DerivedTypes.h" #include "llvm/Support/Debug.h" @@ -180,20 +182,14 @@ SDNode *PTXDAGToDAGISel::SelectFrameIndex(SDNode *Node) { int FI = cast(Node)->getIndex(); //dbgs() << "Selecting FrameIndex at index " << FI << "\n"; - SDValue TFI = CurDAG->getTargetFrameIndex(FI, Node->getValueType(0)); + //SDValue TFI = CurDAG->getTargetFrameIndex(FI, Node->getValueType(0)); - //unsigned OpCode = PTX::LOAD_LOCAL_F32; + PTXMachineFunctionInfo *MFI = MF->getInfo(); - //for (SDNode::use_iterator i = Node->use_begin(), e = Node->use_end(); - // i != e; ++i) { - // SDNode *Use = *i; - // dbgs() << "USE: "; - // Use->dumpr(CurDAG); - //} - - return Node; - //return CurDAG->getMachineNode(OpCode, Node->getDebugLoc(), - // Node->getValueType(0), TFI); + SDValue FrameSymbol = CurDAG->getTargetExternalSymbol(MFI->getFrameSymbol(FI), + Node->getValueType(0)); + + return FrameSymbol.getNode(); } // Match memory operand of the form [reg+reg] Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=140616&r1=140615&r2=140616&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Tue Sep 27 13:12:55 2011 @@ -225,8 +225,11 @@ unsigned ParamSize = Ins[i].VT.getStoreSizeInBits(); unsigned Param = PM.addArgumentParam(ParamSize); + std::string ParamName = PM.getParamName(Param); + SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), + MVT::Other); SDValue ArgValue = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain, - DAG.getTargetConstant(Param, MVT::i32)); + ParamValue); InVals.push_back(ArgValue); } } @@ -319,9 +322,11 @@ if (Outs.size() == 1) { unsigned ParamSize = OutVals[0].getValueType().getSizeInBits(); unsigned Param = PM.addReturnParam(ParamSize); - SDValue ParamIndex = DAG.getTargetConstant(Param, MVT::i32); + std::string ParamName = PM.getParamName(Param); + SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), + MVT::Other); Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain, - ParamIndex, OutVals[0]); + ParamValue, OutVals[0]); } } else { for (unsigned i = 0, e = Outs.size(); i != e; ++i) { @@ -414,21 +419,25 @@ for (unsigned i = 0; i != OutVals.size(); ++i) { unsigned Size = OutVals[i].getValueType().getSizeInBits(); unsigned Param = PM.addLocalParam(Size); - SDValue Index = DAG.getTargetConstant(Param, MVT::i32); + std::string ParamName = PM.getParamName(Param); + SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), + MVT::Other); Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain, - Index, OutVals[i]); - Ops[i+Ins.size()+2] = Index; + ParamValue, OutVals[i]); + Ops[i+Ins.size()+2] = ParamValue; } - std::vector InParams; + std::vector InParams; // Generate list of .param variables to hold the return value(s). for (unsigned i = 0; i < Ins.size(); ++i) { unsigned Size = Ins[i].VT.getStoreSizeInBits(); unsigned Param = PM.addLocalParam(Size); - SDValue Index = DAG.getTargetConstant(Param, MVT::i32); - Ops[i+1] = Index; - InParams.push_back(Param); + std::string ParamName = PM.getParamName(Param); + SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), + MVT::Other); + Ops[i+1] = ParamValue; + InParams.push_back(ParamValue); } Ops[0] = Chain; @@ -438,8 +447,8 @@ // Create the LOAD_PARAM nodes that retrieve the function return value(s). for (unsigned i = 0; i < Ins.size(); ++i) { - SDValue Index = DAG.getTargetConstant(InParams[i], MVT::i32); - SDValue Load = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain, Index); + SDValue Load = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain, + InParams[i]); InVals.push_back(Load); } Modified: llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td?rev=140616&r1=140615&r2=140616&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrLoadStore.td Tue Sep 27 13:12:55 2011 @@ -88,12 +88,12 @@ let MIOperandInfo = (ops RegI64, i64imm); } def LOCALri32 : Operand { - let PrintMethod = "printLocalOperand"; - let MIOperandInfo = (ops RegI32, i32imm); + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops i32imm, i32imm); } def LOCALri64 : Operand { - let PrintMethod = "printLocalOperand"; - let MIOperandInfo = (ops RegI64, i64imm); + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops i64imm, i64imm); } def MEMii32 : Operand { let PrintMethod = "printMemOperand"; @@ -117,7 +117,7 @@ // Load/store .param space def PTXloadparam - : SDNode<"PTXISD::LOAD_PARAM", SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>, + : SDNode<"PTXISD::LOAD_PARAM", SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>, [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>; def PTXstoreparam : SDNode<"PTXISD::STORE_PARAM", SDTypeProfile<0, 2, [SDTCisVT<0, i32>]>, @@ -220,12 +220,12 @@ multiclass PTX_PARAM_LD_ST { let hasSideEffects = 1 in { - def LDpi : InstPTX<(outs RC:$d), (ins MEMpi:$a), + def LDpi : InstPTX<(outs RC:$d), (ins i32imm:$a), !strconcat("ld.param", !strconcat(typestr, "\t$d, [$a]")), - [(set RC:$d, (PTXloadparam timm:$a))]>; - def STpi : InstPTX<(outs), (ins MEMpi:$d, RC:$a), + [(set RC:$d, (PTXloadparam texternalsym:$a))]>; + def STpi : InstPTX<(outs), (ins i32imm:$d, RC:$a), !strconcat("st.param", !strconcat(typestr, "\t[$d], $a")), - [(PTXstoreparam timm:$d, RC:$a)]>; + [(PTXstoreparam texternalsym:$d, RC:$a)]>; } } Modified: llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h?rev=140616&r1=140615&r2=140616&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h (original) +++ llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h Tue Sep 27 13:12:55 2011 @@ -38,9 +38,11 @@ typedef std::vector RegisterList; typedef DenseMap RegisterMap; typedef DenseMap RegisterNameMap; + typedef DenseMap FrameMap; RegisterMap UsedRegs; RegisterNameMap RegNames; + FrameMap FrameSymbols; PTXParamManager ParamManager; @@ -141,6 +143,21 @@ return UsedRegs.lookup(TRC).size(); } + /// getFrameSymbol - Returns the symbol name for the given FrameIndex. + const char* getFrameSymbol(int FrameIndex) { + if (FrameSymbols.count(FrameIndex)) { + return FrameSymbols.lookup(FrameIndex).c_str(); + } else { + std::string Name = "__local"; + Name += utostr(FrameIndex); + // The whole point of caching this name is to ensure the pointer we pass + // to any getExternalSymbol() calls will remain valid for the lifetime of + // the back-end instance. This is to work around an issue in SelectionDAG + // where symbol names are expected to be life-long strings. + FrameSymbols[FrameIndex] = Name; + return FrameSymbols[FrameIndex].c_str(); + } + } }; // class PTXMachineFunctionInfo } // namespace llvm Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp?rev=140616&r1=140615&r2=140616&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp Tue Sep 27 13:12:55 2011 @@ -42,6 +42,8 @@ //unsigned Reg = MRI.createVirtualRegister(PTX::RegF32RegisterClass); + llvm_unreachable("FrameIndex should have been previously eliminated!"); + Index = 0; while (!MI.getOperand(Index).isFI()) { ++Index; @@ -63,7 +65,10 @@ //} //MI2->dump(); + //MachineOperand ESOp = MachineOperand::CreateES("__local__"); + // This frame index is post stack slot re-use assignments //MI.getOperand(Index).ChangeToRegister(Reg, false); MI.getOperand(Index).ChangeToImmediate(FrameIndex); + //MI.getOperand(Index) = ESOp; } From stpworld at narod.ru Tue Sep 27 13:32:53 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Tue, 27 Sep 2011 22:32:53 +0400 Subject: [llvm-commits] [LLVM, Switch case ranges] Cleanup patch before working on switch case ranges Message-ID: <4E8216D5.7000207@narod.ru> Hi, Please find attached the clean-up patch for the SwitchInst internals before working on switch case ranges (http://llvm.org/bugs/show_bug.cgi?id=1255). Patches for switch case ranges will follow. Regards, Stepan. -------------- next part -------------- A non-text attachment was scrubbed... Name: cr-cleanup.patch Type: text/x-patch Size: 9428 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110927/39c32594/attachment.bin From isanbard at gmail.com Tue Sep 27 13:44:01 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Sep 2011 18:44:01 -0000 Subject: [llvm-commits] [llvm] r140619 - /llvm/trunk/docs/Lexicon.html Message-ID: <20110927184401.C17412A6C12C@llvm.org> Author: void Date: Tue Sep 27 13:44:01 2011 New Revision: 140619 URL: http://llvm.org/viewvc/llvm-project?rev=140619&view=rev Log: Add FCA to the lexicon. Modified: llvm/trunk/docs/Lexicon.html Modified: llvm/trunk/docs/Lexicon.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Lexicon.html?rev=140619&r1=140618&r2=140619&view=diff ============================================================================== --- llvm/trunk/docs/Lexicon.html (original) +++ llvm/trunk/docs/Lexicon.html Tue Sep 27 13:44:01 2011 @@ -35,6 +35,10 @@ DSA DSE + - F - + + FCA + - G - GC @@ -137,6 +141,14 @@
    +

    - F -

    +
    +
    +
    FCA
    +
    First Class Aggregate
    +
    +
    +

    - G -

    From eli.friedman at gmail.com Tue Sep 27 13:55:32 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 27 Sep 2011 11:55:32 -0700 Subject: [llvm-commits] [LLVM, Switch case ranges] Cleanup patch before working on switch case ranges In-Reply-To: <4E8216D5.7000207@narod.ru> References: <4E8216D5.7000207@narod.ru> Message-ID: On Tue, Sep 27, 2011 at 11:32 AM, Stepan Dyatkovskiy wrote: > Hi, > > Please find attached the clean-up patch for the SwitchInst internals before > working on switch case ranges (http://llvm.org/bugs/show_bug.cgi?id=1255). > Patches for switch case ranges will follow. I'm not sure about the changes to lib/Target/CppBackend/CPPBackend.cpp... it looks like it ends up doing extra work. Probably not a big deal, though. + for (unsigned i = 1; i < NumCases; ++i) { + ConstantInt* CaseVal = SI.getCaseValue(i); + Constant* NewCaseVal = ConstantExpr::getSub(cast(CaseVal), + AddRHS); + assert(isa(NewCaseVal) && + "Result of expression should be constant"); Slightly strange indentation here. The rest of the changes look fine. -Eli From bigcheesegs at gmail.com Tue Sep 27 14:06:37 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 27 Sep 2011 19:06:37 -0000 Subject: [llvm-commits] [llvm] r140622 - in /llvm/trunk/test/Object: nm-trivial-object.test nm-trivial-object.test-broken objdump-trivial-object.test objdump-trivial-object.test-broken Message-ID: <20110927190637.ABD242A6C12C@llvm.org> Author: mspencer Date: Tue Sep 27 14:06:37 2011 New Revision: 140622 URL: http://llvm.org/viewvc/llvm-project?rev=140622&view=rev Log: Unbreak tests. Added: llvm/trunk/test/Object/nm-trivial-object.test - copied, changed from r140619, llvm/trunk/test/Object/nm-trivial-object.test-broken llvm/trunk/test/Object/objdump-trivial-object.test - copied, changed from r140619, llvm/trunk/test/Object/objdump-trivial-object.test-broken Removed: llvm/trunk/test/Object/nm-trivial-object.test-broken llvm/trunk/test/Object/objdump-trivial-object.test-broken Copied: llvm/trunk/test/Object/nm-trivial-object.test (from r140619, llvm/trunk/test/Object/nm-trivial-object.test-broken) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/nm-trivial-object.test?p2=llvm/trunk/test/Object/nm-trivial-object.test&p1=llvm/trunk/test/Object/nm-trivial-object.test-broken&r1=140619&r2=140622&rev=140622&view=diff ============================================================================== (empty) Removed: llvm/trunk/test/Object/nm-trivial-object.test-broken URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/nm-trivial-object.test-broken?rev=140621&view=auto ============================================================================== --- llvm/trunk/test/Object/nm-trivial-object.test-broken (original) +++ llvm/trunk/test/Object/nm-trivial-object.test-broken (removed) @@ -1,19 +0,0 @@ -RUN: llvm-nm %p/TestObjectFiles/trivial-object-test.coff-i386 \ -RUN: | FileCheck %s -check-prefix COFF -RUN: llvm-nm %p/TestObjectFiles/trivial-object-test.coff-x86-64 \ -RUN: | FileCheck %s -check-prefix COFF -RUN: llvm-nm %p/TestObjectFiles/trivial-object-test.elf-i386 \ -RUN: | FileCheck %s -check-prefix ELF -RUN: llvm-nm %p/TestObjectFiles/trivial-object-test.elf-x86-64 \ -RUN: | FileCheck %s -check-prefix ELF - -COFF: 00000000 d .data -COFF: 00000000 t .text -COFF: 00000000 d L{{_?}}.str -COFF: U {{_?}}SomeOtherFunction -COFF: 00000000 T {{_?}}main -COFF: U {{_?}}puts - -ELF: U SomeOtherFunction -ELF: 00000000 T main -ELF: U puts Copied: llvm/trunk/test/Object/objdump-trivial-object.test (from r140619, llvm/trunk/test/Object/objdump-trivial-object.test-broken) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/objdump-trivial-object.test?p2=llvm/trunk/test/Object/objdump-trivial-object.test&p1=llvm/trunk/test/Object/objdump-trivial-object.test-broken&r1=140619&r2=140622&rev=140622&view=diff ============================================================================== (empty) Removed: llvm/trunk/test/Object/objdump-trivial-object.test-broken URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/objdump-trivial-object.test-broken?rev=140621&view=auto ============================================================================== --- llvm/trunk/test/Object/objdump-trivial-object.test-broken (original) +++ llvm/trunk/test/Object/objdump-trivial-object.test-broken (removed) @@ -1,54 +0,0 @@ -RUN: llvm-objdump -d %p/TestObjectFiles/trivial-object-test.coff-i386 \ -RUN: | FileCheck %s -check-prefix COFF-i386 -RUN: llvm-objdump -d %p/TestObjectFiles/trivial-object-test.coff-x86-64 \ -RUN: | FileCheck %s -check-prefix COFF-x86-64 -RUN: llvm-objdump -d %p/TestObjectFiles/trivial-object-test.elf-i386 \ -RUN: | FileCheck %s -check-prefix ELF-i386 -RUN: llvm-objdump -d %p/TestObjectFiles/trivial-object-test.elf-x86-64 \ -RUN: | FileCheck %s -check-prefix ELF-x86-64 - -COFF-i386: file format COFF-i386 -COFF-i386: Disassembly of section .text: -COFF-i386: 0: 83 ec 0c subl $12, %esp -COFF-i386: 3: c7 44 24 08 00 00 00 00 movl $0, 8(%esp) -COFF-i386: b: c7 04 24 00 00 00 00 movl $0, (%esp) -COFF-i386: 12: e8 00 00 00 00 calll 0 -COFF-i386: 17: e8 00 00 00 00 calll 0 -COFF-i386: 1c: 8b 44 24 08 movl 8(%esp), %eax -COFF-i386: 20: 83 c4 0c addl $12, %esp -COFF-i386: 23: c3 ret - -COFF-x86-64: file format COFF-x86-64 -COFF-x86-64: Disassembly of section .text: -COFF-x86-64: 0: 48 83 ec 28 subq $40, %rsp -COFF-x86-64: 4: c7 44 24 24 00 00 00 00 movl $0, 36(%rsp) -COFF-x86-64: c: 48 8d 0d 00 00 00 00 leaq (%rip), %rcx -COFF-x86-64: 13: e8 00 00 00 00 callq 0 -COFF-x86-64: 18: e8 00 00 00 00 callq 0 -COFF-x86-64: 1d: 8b 44 24 24 movl 36(%rsp), %eax -COFF-x86-64: 21: 48 83 c4 28 addq $40, %rsp -COFF-x86-64: 25: c3 ret - - -ELF-i386: file format ELF32-i386 -ELF-i386: Disassembly of section .text: -ELF-i386: 0: 83 ec 0c subl $12, %esp -ELF-i386: 3: c7 44 24 08 00 00 00 00 movl $0, 8(%esp) -ELF-i386: b: c7 04 24 00 00 00 00 movl $0, (%esp) -ELF-i386: 12: e8 fc ff ff ff calll -4 -ELF-i386: 17: e8 fc ff ff ff calll -4 -ELF-i386: 1c: 8b 44 24 08 movl 8(%esp), %eax -ELF-i386: 20: 83 c4 0c addl $12, %esp -ELF-i386: 23: c3 ret - -ELF-x86-64: file format ELF64-x86-64 -ELF-x86-64: Disassembly of section .text: -ELF-x86-64: 0: 48 83 ec 08 subq $8, %rsp -ELF-x86-64: 4: c7 44 24 04 00 00 00 00 movl $0, 4(%rsp) -ELF-x86-64: c: bf 00 00 00 00 movl $0, %edi -ELF-x86-64: 11: e8 00 00 00 00 callq 0 -ELF-x86-64: 16: 30 c0 xorb %al, %al -ELF-x86-64: 18: e8 00 00 00 00 callq 0 -ELF-x86-64: 1d: 8b 44 24 04 movl 4(%rsp), %eax -ELF-x86-64: 21: 48 83 c4 08 addq $8, %rsp -ELF-x86-64: 25: c3 ret From justin.holewinski at gmail.com Tue Sep 27 14:25:50 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Tue, 27 Sep 2011 19:25:50 -0000 Subject: [llvm-commits] [llvm] r140624 - /llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Message-ID: <20110927192550.28C742A6C12C@llvm.org> Author: jholewinski Date: Tue Sep 27 14:25:49 2011 New Revision: 140624 URL: http://llvm.org/viewvc/llvm-project?rev=140624&view=rev Log: PTX: Fix case where printed alignment could be 0 Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140624&r1=140623&r2=140624&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Tue Sep 27 14:25:49 2011 @@ -480,7 +480,7 @@ unsigned alignment = gv->getAlignment(); if (alignment != 0) { decl += ".align "; - decl += utostr(Log2_32(gv->getAlignment())); + decl += utostr(std::max(1U, Log2_32(gv->getAlignment()))); decl += " "; } From baldrick at free.fr Tue Sep 27 14:34:22 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 27 Sep 2011 19:34:22 -0000 Subject: [llvm-commits] [llvm] r140625 - /llvm/trunk/lib/VMCore/Verifier.cpp Message-ID: <20110927193422.45E8C2A6C12C@llvm.org> Author: baldrick Date: Tue Sep 27 14:34:22 2011 New Revision: 140625 URL: http://llvm.org/viewvc/llvm-project?rev=140625&view=rev Log: Check that catch clauses have pointer type. Modified: llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=140625&r1=140624&r2=140625&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Tue Sep 27 14:34:22 2011 @@ -1455,9 +1455,14 @@ for (unsigned i = 0, e = LPI.getNumClauses(); i < e; ++i) { Value *Clause = LPI.getClause(i); Assert1(isa(Clause), "Clause is not constant!", &LPI); - if (LPI.isFilter(i)) + if (LPI.isCatch(i)) { + Assert1(isa(Clause->getType()), + "Catch operand does not have pointer type!", &LPI); + } else { + Assert1(LPI.isFilter(i), "Clause is neither catch nor filter!", &LPI); Assert1(isa(Clause) || isa(Clause), - "Filter is not an array of constants!", &LPI); + "Filter operand is not an array of constants!", &LPI); + } } visitInstruction(LPI); From bigcheesegs at gmail.com Tue Sep 27 14:36:56 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 27 Sep 2011 19:36:56 -0000 Subject: [llvm-commits] [llvm] r140626 - in /llvm/trunk: include/llvm/Object/Archive.h lib/Object/Archive.cpp lib/Object/Binary.cpp lib/Object/CMakeLists.txt Message-ID: <20110927193656.277E22A6C12C@llvm.org> Author: mspencer Date: Tue Sep 27 14:36:55 2011 New Revision: 140626 URL: http://llvm.org/viewvc/llvm-project?rev=140626&view=rev Log: Object: Add archive support. Added: llvm/trunk/include/llvm/Object/Archive.h llvm/trunk/lib/Object/Archive.cpp Modified: llvm/trunk/lib/Object/Binary.cpp llvm/trunk/lib/Object/CMakeLists.txt Added: llvm/trunk/include/llvm/Object/Archive.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/Archive.h?rev=140626&view=auto ============================================================================== --- llvm/trunk/include/llvm/Object/Archive.h (added) +++ llvm/trunk/include/llvm/Object/Archive.h Tue Sep 27 14:36:55 2011 @@ -0,0 +1,90 @@ +//===- Archive.h - ar archive file format -----------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the ar archive file format class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_OBJECT_ARCHIVE_H +#define LLVM_OBJECT_ARCHIVE_H + +#include "llvm/Object/Binary.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/DataTypes.h" + +namespace llvm { +namespace object { + +class Archive : public Binary { +public: + class Child { + Archive *Parent; + StringRef Data; + + public: + Child(Archive *p, StringRef d) : Parent(p), Data(d) {} + + bool operator ==(const Child &other) const { + return (Parent == other.Parent) && (Data.begin() == other.Data.begin()); + } + + Child getNext() const; + error_code getName(StringRef &Result) const; + int getLastModified() const; + int getUID() const; + int getGID() const; + int getAccessMode() const; + ///! Return the size of the archive member without the header or padding. + uint64_t getSize() const; + + MemoryBuffer *getBuffer() const; + error_code getAsBinary(OwningPtr &Result) const; + }; + + class child_iterator { + Child child; + public: + child_iterator(const Child &c) : child(c) {} + const Child* operator->() const { + return &child; + } + + bool operator==(const child_iterator &other) const { + return child == other.child; + } + + bool operator!=(const child_iterator &other) const { + return !(*this == other); + } + + child_iterator& operator++() { // Preincrement + child = child.getNext(); + return *this; + } + }; + + Archive(MemoryBuffer *source, error_code &ec); + + child_iterator begin_children(); + child_iterator end_children(); + + // Cast methods. + static inline bool classof(Archive const *v) { return true; } + static inline bool classof(Binary const *v) { + return v->getType() == Binary::isArchive; + } + +private: + child_iterator StringTable; +}; + +} +} + +#endif Added: llvm/trunk/lib/Object/Archive.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/Archive.cpp?rev=140626&view=auto ============================================================================== --- llvm/trunk/lib/Object/Archive.cpp (added) +++ llvm/trunk/lib/Object/Archive.cpp Tue Sep 27 14:36:55 2011 @@ -0,0 +1,172 @@ +//===- Archive.cpp - ar File Format implementation --------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the ArchiveObjectFile class. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Object/Archive.h" +#include "llvm/ADT/APInt.h" +#include "llvm/Support/MemoryBuffer.h" + +using namespace llvm; +using namespace object; + +namespace { +const StringRef Magic = "!\n"; + +struct ArchiveMemberHeader { + char Name[16]; + char LastModified[12]; + char UID[6]; + char GID[6]; + char AccessMode[8]; + char Size[10]; //< Size of data, not including header or padding. + char Terminator[2]; + + ///! Get the name without looking up long names. + StringRef getName() const { + char EndCond = Name[0] == '/' ? ' ' : '/'; + StringRef::size_type end = StringRef(Name, sizeof(Name)).find(EndCond); + if (end == StringRef::npos) + end = sizeof(Name); + assert(end <= sizeof(Name) && end > 0); + // Don't include the EndCond if there is one. + return StringRef(Name, end); + } + + uint64_t getSize() const { + APInt ret; + StringRef(Size, sizeof(Size)).getAsInteger(10, ret); + return ret.getZExtValue(); + } +}; + +const ArchiveMemberHeader *ToHeader(const char *base) { + return reinterpret_cast(base); +} +} + +Archive::Child Archive::Child::getNext() const { + size_t SpaceToSkip = sizeof(ArchiveMemberHeader) + + ToHeader(Data.data())->getSize(); + // If it's odd, add 1 to make it even. + if (SpaceToSkip & 1) + ++SpaceToSkip; + + const char *NextLoc = Data.data() + SpaceToSkip; + + // Check to see if this is past the end of the archive. + if (NextLoc >= Parent->Data->getBufferEnd()) + return Child(Parent, StringRef(0, 0)); + + size_t NextSize = sizeof(ArchiveMemberHeader) + + ToHeader(NextLoc)->getSize(); + + return Child(Parent, StringRef(NextLoc, NextSize)); +} + +error_code Archive::Child::getName(StringRef &Result) const { + StringRef name = ToHeader(Data.data())->getName(); + // Check if it's a special name. + if (name[0] == '/') { + if (name.size() == 1) { // Linker member. + Result = name; + return object_error::success; + } + if (name.size() == 2 && name[1] == '/') { // String table. + Result = name; + return object_error::success; + } + // It's a long name. + // Get the offset. + APInt offset; + name.substr(1).getAsInteger(10, offset); + const char *addr = Parent->StringTable->Data.begin() + + sizeof(ArchiveMemberHeader) + + offset.getZExtValue(); + // Verify it. + if (Parent->StringTable == Parent->end_children() + || addr < (Parent->StringTable->Data.begin() + + sizeof(ArchiveMemberHeader)) + || addr > (Parent->StringTable->Data.begin() + + sizeof(ArchiveMemberHeader) + + Parent->StringTable->getSize())) + return object_error::parse_failed; + Result = addr; + return object_error::success; + } + // It's a simple name. + if (name[name.size() - 1] == '/') + Result = name.substr(0, name.size() - 1); + else + Result = name; + return object_error::success; +} + +uint64_t Archive::Child::getSize() const { + return ToHeader(Data.data())->getSize(); +} + +MemoryBuffer *Archive::Child::getBuffer() const { + StringRef name; + if (getName(name)) return NULL; + return MemoryBuffer::getMemBuffer(Data.substr(sizeof(ArchiveMemberHeader), + getSize()), + name, + false); +} + +error_code Archive::Child::getAsBinary(OwningPtr &Result) const { + OwningPtr ret; + if (error_code ec = + createBinary(getBuffer(), ret)) + return ec; + Result.swap(ret); + return object_error::success; +} + +Archive::Archive(MemoryBuffer *source, error_code &ec) + : Binary(Binary::isArchive, source) + , StringTable(Child(this, StringRef(0, 0))) { + // Check for sufficient magic. + if (!source || source->getBufferSize() + < (8 + sizeof(ArchiveMemberHeader) + 2) // Smallest archive. + || StringRef(source->getBufferStart(), 8) != Magic) { + ec = object_error::invalid_file_type; + return; + } + + // Get the string table. It's the 3rd member. + child_iterator StrTable = begin_children(); + child_iterator e = end_children(); + for (int i = 0; StrTable != e && i < 2; ++StrTable, ++i); + + // Check to see if there were 3 members, or the 3rd member wasn't named "//". + StringRef name; + if (StrTable != e && !StrTable->getName(name) && name == "//") + StringTable = StrTable; + + ec = object_error::success; +} + +Archive::child_iterator Archive::begin_children() { + const char *Loc = Data->getBufferStart() + Magic.size(); + size_t Size = sizeof(ArchiveMemberHeader) + + ToHeader(Loc)->getSize(); + return Child(this, StringRef(Loc, Size)); +} + +Archive::child_iterator Archive::end_children() { + return Child(this, StringRef(0, 0)); +} + +namespace llvm { + +} // end namespace llvm Modified: llvm/trunk/lib/Object/Binary.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/Binary.cpp?rev=140626&r1=140625&r2=140626&view=diff ============================================================================== --- llvm/trunk/lib/Object/Binary.cpp (original) +++ llvm/trunk/lib/Object/Binary.cpp Tue Sep 27 14:36:55 2011 @@ -17,8 +17,9 @@ #include "llvm/Support/Path.h" // Include headers for createBinary. -#include "llvm/Object/ObjectFile.h" +#include "llvm/Object/Archive.h" #include "llvm/Object/COFF.h" +#include "llvm/Object/ObjectFile.h" using namespace llvm; using namespace object; @@ -50,6 +51,12 @@ static_cast(Source->getBufferSize())); error_code ec; switch (type) { + case sys::Archive_FileType: { + OwningPtr ret(new Archive(scopedSource.take(), ec)); + if (ec) return ec; + Result.swap(ret); + return object_error::success; + } case sys::ELF_Relocatable_FileType: case sys::ELF_Executable_FileType: case sys::ELF_SharedObject_FileType: Modified: llvm/trunk/lib/Object/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/CMakeLists.txt?rev=140626&r1=140625&r2=140626&view=diff ============================================================================== --- llvm/trunk/lib/Object/CMakeLists.txt (original) +++ llvm/trunk/lib/Object/CMakeLists.txt Tue Sep 27 14:36:55 2011 @@ -1,4 +1,5 @@ add_llvm_library(LLVMObject + Archive.cpp Binary.cpp COFFObjectFile.cpp ELFObjectFile.cpp From bigcheesegs at gmail.com Tue Sep 27 14:37:18 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 27 Sep 2011 19:37:18 -0000 Subject: [llvm-commits] [llvm] r140627 - in /llvm/trunk: test/Object/TestObjectFiles/archive-test.a-bitcode test/Object/TestObjectFiles/archive-test.a-coff-i386 test/Object/nm-archive.test tools/llvm-nm/llvm-nm.cpp Message-ID: <20110927193718.333882A6C12C@llvm.org> Author: mspencer Date: Tue Sep 27 14:37:18 2011 New Revision: 140627 URL: http://llvm.org/viewvc/llvm-project?rev=140627&view=rev Log: Add binary archive support to llvm-nm. Added: llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386 llvm/trunk/test/Object/nm-archive.test Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp Added: llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode?rev=140627&view=auto ============================================================================== Binary files llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode (added) and llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode Tue Sep 27 14:37:18 2011 differ Added: llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386 URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386?rev=140627&view=auto ============================================================================== Binary files llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386 (added) and llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386 Tue Sep 27 14:37:18 2011 differ Added: llvm/trunk/test/Object/nm-archive.test URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/nm-archive.test?rev=140627&view=auto ============================================================================== --- llvm/trunk/test/Object/nm-archive.test (added) +++ llvm/trunk/test/Object/nm-archive.test Tue Sep 27 14:37:18 2011 @@ -0,0 +1,17 @@ +RUN: llvm-nm %p/TestObjectFiles/archive-test.a-coff-i386 \ +RUN: | FileCheck %s -check-prefix COFF +RUN: llvm-nm %p/TestObjectFiles/archive-test.a-bitcode \ +RUN: | FileCheck %s -check-prefix BITCODE + + +COFF: trivial-object-test.coff-i386: +COFF-NEXT: 00000000 d .data +COFF-NEXT: 00000000 t .text +COFF-NEXT: 00000000 d L_.str +COFF-NEXT: U _SomeOtherFunction +COFF-NEXT: 00000000 T _main +COFF-NEXT: U _puts + +BITCODE: U SomeOtherFunction +BITCODE-NEXT: T main +BITCODE-NEXT: U puts Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=140627&r1=140626&r2=140627&view=diff ============================================================================== --- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original) +++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Tue Sep 27 14:37:18 2011 @@ -20,6 +20,7 @@ #include "llvm/Module.h" #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/Bitcode/Archive.h" +#include "llvm/Object/Archive.h" #include "llvm/Object/ObjectFile.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FileSystem.h" @@ -318,18 +319,34 @@ errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n"; } else if (aPath.isArchive()) { - std::string ErrMsg; - Archive* archive = Archive::OpenAndLoad(sys::Path(Filename), Context, - &ErrorMessage); - if (!archive) - errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n"; - std::vector Modules; - if (archive->getAllModules(Modules, &ErrorMessage)) { - errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n"; + OwningPtr arch; + if (error_code ec = object::createBinary(aPath.str(), arch)) { + errs() << ToolName << ": " << Filename << ": " << ec.message() << ".\n"; return; } - MultipleFiles = true; - std::for_each (Modules.begin(), Modules.end(), DumpSymbolNamesFromModule); + if (object::Archive *a = dyn_cast(arch.get())) { + for (object::Archive::child_iterator i = a->begin_children(), + e = a->end_children(); i != e; ++i) { + OwningPtr child; + if (error_code ec = i->getAsBinary(child)) { + // Try opening it as a bitcode file. + MemoryBuffer *buff = i->getBuffer(); + Module *Result = 0; + if (buff) + Result = ParseBitcodeFile(buff, Context, &ErrorMessage); + + if (Result) { + DumpSymbolNamesFromModule(Result); + delete Result; + } + continue; + } + if (object::ObjectFile *o = dyn_cast(child.get())) { + outs() << o->getFileName() << ":\n"; + DumpSymbolNamesFromObject(o); + } + } + } } else if (aPath.isObjectFile()) { OwningPtr obj; if (error_code ec = object::createBinary(aPath.str(), obj)) { From eli.friedman at gmail.com Tue Sep 27 15:01:10 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 27 Sep 2011 13:01:10 -0700 Subject: [llvm-commits] [llvm] r140624 - /llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp In-Reply-To: <20110927192550.28C742A6C12C@llvm.org> References: <20110927192550.28C742A6C12C@llvm.org> Message-ID: On Tue, Sep 27, 2011 at 12:25 PM, Justin Holewinski wrote: > Author: jholewinski > Date: Tue Sep 27 14:25:49 2011 > New Revision: 140624 > > URL: http://llvm.org/viewvc/llvm-project?rev=140624&view=rev > Log: > PTX: Fix case where printed alignment could be 0 > > Modified: > ? ?llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp > > Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140624&r1=140623&r2=140624&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Tue Sep 27 14:25:49 2011 > @@ -480,7 +480,7 @@ > ? unsigned alignment = gv->getAlignment(); > ? if (alignment != 0) { > ? ? decl += ".align "; > - ? ?decl += utostr(Log2_32(gv->getAlignment())); > + ? ?decl += utostr(std::max(1U, Log2_32(gv->getAlignment()))); > ? ? decl += " "; > ? } This looks wrong: you're making sure the alignment is at least 2 bytes?! -Eli From mcrosier at apple.com Tue Sep 27 15:01:41 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 27 Sep 2011 20:01:41 -0000 Subject: [llvm-commits] [llvm] r140629 - /llvm/trunk/lib/Support/SearchForAddressOfSpecialSymbol.cpp Message-ID: <20110927200142.016232A6C12C@llvm.org> Author: mcrosier Date: Tue Sep 27 15:01:41 2011 New Revision: 140629 URL: http://llvm.org/viewvc/llvm-project?rev=140629&view=rev Log: These symbols appear to be visible by SearchForAddressOfSymbol and no longer require special case handling. rdar://10117377 Modified: llvm/trunk/lib/Support/SearchForAddressOfSpecialSymbol.cpp Modified: llvm/trunk/lib/Support/SearchForAddressOfSpecialSymbol.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SearchForAddressOfSpecialSymbol.cpp?rev=140629&r1=140628&r2=140629&view=diff ============================================================================== --- llvm/trunk/lib/Support/SearchForAddressOfSpecialSymbol.cpp (original) +++ llvm/trunk/lib/Support/SearchForAddressOfSpecialSymbol.cpp Tue Sep 27 15:01:41 2011 @@ -28,21 +28,6 @@ #ifdef __APPLE__ { - EXPLICIT_SYMBOL(__ashldi3); - EXPLICIT_SYMBOL(__ashrdi3); - EXPLICIT_SYMBOL(__cmpdi2); - EXPLICIT_SYMBOL(__divdi3); - EXPLICIT_SYMBOL(__fixdfdi); - EXPLICIT_SYMBOL(__fixsfdi); - EXPLICIT_SYMBOL(__fixunsdfdi); - EXPLICIT_SYMBOL(__fixunssfdi); - EXPLICIT_SYMBOL(__floatdidf); - EXPLICIT_SYMBOL(__floatdisf); - EXPLICIT_SYMBOL(__lshrdi3); - EXPLICIT_SYMBOL(__moddi3); - EXPLICIT_SYMBOL(__udivdi3); - EXPLICIT_SYMBOL(__umoddi3); - // __eprintf is sometimes used for assert() handling on x86. // // FIXME: Currently disabled when using Clang, as we don't always have our From kledzik at apple.com Tue Sep 27 15:05:27 2011 From: kledzik at apple.com (Nick Kledzik) Date: Tue, 27 Sep 2011 20:05:27 -0000 Subject: [llvm-commits] [compiler-rt] r140630 - in /compiler-rt/trunk/make: AppleBI.mk platform/darwin_bni.mk Message-ID: <20110927200527.5DF952A6C12C@llvm.org> Author: kledzik Date: Tue Sep 27 15:05:27 2011 New Revision: 140630 URL: http://llvm.org/viewvc/llvm-project?rev=140630&view=rev Log: No armv4t slice of libcompiler_rt-static.a Modified: compiler-rt/trunk/make/AppleBI.mk compiler-rt/trunk/make/platform/darwin_bni.mk Modified: compiler-rt/trunk/make/AppleBI.mk URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/AppleBI.mk?rev=140630&r1=140629&r2=140630&view=diff ============================================================================== --- compiler-rt/trunk/make/AppleBI.mk (original) +++ compiler-rt/trunk/make/AppleBI.mk Tue Sep 27 15:05:27 2011 @@ -61,7 +61,7 @@ $(DYLIB_FLAGS) -Wl,-force_load,$^ -o $@ # Rule to make fat dylib -$(SYMROOT)/libcompiler_rt.dylib: $(foreach arch,$(RC_ARCHS), \ +$(SYMROOT)/libcompiler_rt.dylib: $(foreach arch,$(filter-out armv4t,$(RC_ARCHS)), \ $(OBJROOT)/libcompiler_rt-$(arch).dylib) $(call GetCNAVar,LIPO,Platform.darwin_bni,Release,) -create $^ -o $@ Modified: compiler-rt/trunk/make/platform/darwin_bni.mk URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/darwin_bni.mk?rev=140630&r1=140629&r2=140630&view=diff ============================================================================== --- compiler-rt/trunk/make/platform/darwin_bni.mk (original) +++ compiler-rt/trunk/make/platform/darwin_bni.mk Tue Sep 27 15:05:27 2011 @@ -67,6 +67,9 @@ muloti4 mulvti3 mulxc3 negti2 negvti2 parityti2 \ popcountti2 powixf2 subvti3 ucmpti2 udivmodti4 \ udivti3 umodti3 clear_cache enable_execute_stack + +FUNCTIONS.armv4t := $(FUNCTIONS) + FUNCTIONS.armv5 := $(FUNCTIONS) \ adddf3 addsf3 bswapdi2 bswapsi2 \ comparedf2 comparesf2 extendsfdf2 \ From isanbard at gmail.com Tue Sep 27 15:16:57 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Sep 2011 20:16:57 -0000 Subject: [llvm-commits] [llvm] r140631 - /llvm/trunk/docs/ExceptionHandling.html Message-ID: <20110927201657.EC9342A6C12C@llvm.org> Author: void Date: Tue Sep 27 15:16:57 2011 New Revision: 140631 URL: http://llvm.org/viewvc/llvm-project?rev=140631&view=rev Log: Remove incorrect passage. Modified: llvm/trunk/docs/ExceptionHandling.html Modified: llvm/trunk/docs/ExceptionHandling.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ExceptionHandling.html?rev=140631&r1=140630&r2=140631&view=diff ============================================================================== --- llvm/trunk/docs/ExceptionHandling.html (original) +++ llvm/trunk/docs/ExceptionHandling.html Tue Sep 27 15:16:57 2011 @@ -361,14 +361,10 @@

    The unwinder delegates the decision of whether to stop in a call frame to - that call frame's language-specific personality function. Not all personality - functions guarantee that they will stop to perform cleanups. For example, the - GNU C++ personality function doesn't do so unless the exception is actually - caught somewhere further up the stack. When using this personality to - implement EH for a language that guarantees that cleanups will always be run - (e.g. Ada), be sure to indicate a catch-all in the - landingpad instruction - rather than just cleanups.

    + that call frame's language-specific personality function. Not all unwinders + guarantee that they will stop to perform cleanups. For example, the GNU C++ + unwinder doesn't do so unless the exception is actually caught somewhere + further up the stack.

    In order for inlining to behave correctly, landing pads must be prepared to handle selector results that they did not originally advertise. Suppose that From benny.kra at googlemail.com Tue Sep 27 15:39:19 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 27 Sep 2011 20:39:19 -0000 Subject: [llvm-commits] [llvm] r140634 - in /llvm/trunk: lib/Analysis/ lib/Transforms/IPO/ lib/Transforms/InstCombine/ lib/Transforms/Scalar/ lib/Transforms/Utils/ test/Transforms/IndVarSimplify/ test/Transforms/InstCombine/ test/Transforms/LoopIdiom/ test/Transforms/LoopStrengthReduce/ test/Transforms/ScalarRepl/ test/Transforms/SimplifyLibCalls/ Message-ID: <20110927203919.B8EF02A6C12C@llvm.org> Author: d0k Date: Tue Sep 27 15:39:19 2011 New Revision: 140634 URL: http://llvm.org/viewvc/llvm-project?rev=140634&view=rev Log: Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit. If someone prefers %tmp42 to %42, run instnamer. Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp llvm/trunk/lib/Transforms/Scalar/GVN.cpp llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp llvm/trunk/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll llvm/trunk/test/Transforms/InstCombine/call.ll llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll llvm/trunk/test/Transforms/InstCombine/vector-casts.ll llvm/trunk/test/Transforms/LoopIdiom/basic.ll llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll llvm/trunk/test/Transforms/SimplifyLibCalls/pow-to-sqrt.ll Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Tue Sep 27 15:39:19 2011 @@ -163,7 +163,7 @@ } // If we haven't found this binop, insert it. - Instruction *BO = cast(Builder.CreateBinOp(Opcode, LHS, RHS, "tmp")); + Instruction *BO = cast(Builder.CreateBinOp(Opcode, LHS, RHS)); BO->setDebugLoc(SaveInsertPt->getDebugLoc()); rememberInstruction(BO); @@ -980,7 +980,7 @@ const SCEV *const StepArray[1] = { SE.getSCEV(StepV) }; IncV = expandAddToGEP(StepArray, StepArray+1, GEPPtrTy, IntTy, PN); if (IncV->getType() != PN->getType()) { - IncV = Builder.CreateBitCast(IncV, PN->getType(), "tmp"); + IncV = Builder.CreateBitCast(IncV, PN->getType()); rememberInstruction(IncV); } } else { @@ -1222,7 +1222,7 @@ Type *Ty = SE.getEffectiveSCEVType(S->getType()); Value *V = expandCodeFor(S->getOperand(), SE.getEffectiveSCEVType(S->getOperand()->getType())); - Value *I = Builder.CreateTrunc(V, Ty, "tmp"); + Value *I = Builder.CreateTrunc(V, Ty); rememberInstruction(I); return I; } @@ -1231,7 +1231,7 @@ Type *Ty = SE.getEffectiveSCEVType(S->getType()); Value *V = expandCodeFor(S->getOperand(), SE.getEffectiveSCEVType(S->getOperand()->getType())); - Value *I = Builder.CreateZExt(V, Ty, "tmp"); + Value *I = Builder.CreateZExt(V, Ty); rememberInstruction(I); return I; } @@ -1240,7 +1240,7 @@ Type *Ty = SE.getEffectiveSCEVType(S->getType()); Value *V = expandCodeFor(S->getOperand(), SE.getEffectiveSCEVType(S->getOperand()->getType())); - Value *I = Builder.CreateSExt(V, Ty, "tmp"); + Value *I = Builder.CreateSExt(V, Ty); rememberInstruction(I); return I; } @@ -1256,7 +1256,7 @@ LHS = InsertNoopCastOfTo(LHS, Ty); } Value *RHS = expandCodeFor(S->getOperand(i), Ty); - Value *ICmp = Builder.CreateICmpSGT(LHS, RHS, "tmp"); + Value *ICmp = Builder.CreateICmpSGT(LHS, RHS); rememberInstruction(ICmp); Value *Sel = Builder.CreateSelect(ICmp, LHS, RHS, "smax"); rememberInstruction(Sel); @@ -1280,7 +1280,7 @@ LHS = InsertNoopCastOfTo(LHS, Ty); } Value *RHS = expandCodeFor(S->getOperand(i), Ty); - Value *ICmp = Builder.CreateICmpUGT(LHS, RHS, "tmp"); + Value *ICmp = Builder.CreateICmpUGT(LHS, RHS); rememberInstruction(ICmp); Value *Sel = Builder.CreateSelect(ICmp, LHS, RHS, "umax"); rememberInstruction(Sel); Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Tue Sep 27 15:39:19 2011 @@ -1376,8 +1376,7 @@ for (unsigned i = 0, e = FieldGlobals.size(); i != e; ++i) { Value *GVVal = new LoadInst(FieldGlobals[i], "tmp", NullPtrBlock); Value *Cmp = new ICmpInst(*NullPtrBlock, ICmpInst::ICMP_NE, GVVal, - Constant::getNullValue(GVVal->getType()), - "tmp"); + Constant::getNullValue(GVVal->getType())); BasicBlock *FreeBlock = BasicBlock::Create(Cmp->getContext(), "free_it", OrigBB->getParent()); BasicBlock *NextBlock = BasicBlock::Create(Cmp->getContext(), "next", Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Tue Sep 27 15:39:19 2011 @@ -1197,7 +1197,7 @@ // an endless loop. By checking that A is non-constant we ensure that // we will never get to the loop. if (A == tmpOp0 && !isa(A)) // A&(A^B) -> A & ~B - return BinaryOperator::CreateAnd(A, Builder->CreateNot(B, "tmp")); + return BinaryOperator::CreateAnd(A, Builder->CreateNot(B)); } } @@ -2228,14 +2228,14 @@ if (A == Op1) // (B|A)^B == (A|B)^B std::swap(A, B); if (B == Op1) // (A|B)^B == A & ~B - return BinaryOperator::CreateAnd(A, Builder->CreateNot(Op1, "tmp")); + return BinaryOperator::CreateAnd(A, Builder->CreateNot(Op1)); } else if (match(Op0I, m_And(m_Value(A), m_Value(B))) && Op0I->hasOneUse()){ if (A == Op1) // (A&B)^A -> (B&A)^A std::swap(A, B); if (B == Op1 && // (B&A)^A == ~B & A !isa(Op1)) { // Canonical form is (B&C)^C - return BinaryOperator::CreateAnd(Builder->CreateNot(A, "tmp"), Op1); + return BinaryOperator::CreateAnd(Builder->CreateNot(A), Op1); } } } Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Tue Sep 27 15:39:19 2011 @@ -654,15 +654,13 @@ if (ExtractedElts[Idx] == 0) { ExtractedElts[Idx] = - Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1, - ConstantInt::get(Type::getInt32Ty(II->getContext()), - Idx&15, false), "tmp"); + Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1, + Builder->getInt32(Idx&15)); } // Insert this value into the result vector. Result = Builder->CreateInsertElement(Result, ExtractedElts[Idx], - ConstantInt::get(Type::getInt32Ty(II->getContext()), - i, false), "tmp"); + Builder->getInt32(i)); } return CastInst::Create(Instruction::BitCast, Result, CI.getType()); } @@ -1143,7 +1141,7 @@ } else { Instruction::CastOps opcode = CastInst::getCastOpcode(*AI, false, ParamTy, false); - Args.push_back(Builder->CreateCast(opcode, *AI, ParamTy, "tmp")); + Args.push_back(Builder->CreateCast(opcode, *AI, ParamTy)); } // Add any parameter attributes. @@ -1169,7 +1167,7 @@ // Must promote to pass through va_arg area! Instruction::CastOps opcode = CastInst::getCastOpcode(*AI, false, PTy, false); - Args.push_back(Builder->CreateCast(opcode, *AI, PTy, "tmp")); + Args.push_back(Builder->CreateCast(opcode, *AI, PTy)); } else { Args.push_back(*AI); } @@ -1213,7 +1211,7 @@ if (!NV->getType()->isVoidTy()) { Instruction::CastOps opcode = CastInst::getCastOpcode(NC, false, OldRetTy, false); - NV = NC = CastInst::Create(opcode, NC, OldRetTy, "tmp"); + NV = NC = CastInst::Create(opcode, NC, OldRetTy); NC->setDebugLoc(Caller->getDebugLoc()); // If this is an invoke instruction, we should insert it after the first Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp Tue Sep 27 15:39:19 2011 @@ -122,13 +122,13 @@ } else { Amt = ConstantInt::get(AI.getArraySize()->getType(), Scale); // Insert before the alloca, not before the cast. - Amt = AllocaBuilder.CreateMul(Amt, NumElements, "tmp"); + Amt = AllocaBuilder.CreateMul(Amt, NumElements); } if (uint64_t Offset = (AllocElTySize*ArrayOffset)/CastElTySize) { Value *Off = ConstantInt::get(AI.getArraySize()->getType(), Offset, true); - Amt = AllocaBuilder.CreateAdd(Amt, Off, "tmp"); + Amt = AllocaBuilder.CreateAdd(Amt, Off); } AllocaInst *New = AllocaBuilder.CreateAlloca(CastElTy, Amt); @@ -457,7 +457,7 @@ // Canonicalize trunc x to i1 -> (icmp ne (and x, 1), 0), likewise for vector. if (DestTy->getScalarSizeInBits() == 1) { Constant *One = ConstantInt::get(Src->getType(), 1); - Src = Builder->CreateAnd(Src, One, "tmp"); + Src = Builder->CreateAnd(Src, One); Value *Zero = Constant::getNullValue(Src->getType()); return new ICmpInst(ICmpInst::ICMP_NE, Src, Zero); } @@ -519,7 +519,7 @@ In->getType()->getScalarSizeInBits()-1); In = Builder->CreateLShr(In, Sh, In->getName()+".lobit"); if (In->getType() != CI.getType()) - In = Builder->CreateIntCast(In, CI.getType(), false/*ZExt*/, "tmp"); + In = Builder->CreateIntCast(In, CI.getType(), false/*ZExt*/); if (ICI->getPredicate() == ICmpInst::ICMP_SGT) { Constant *One = ConstantInt::get(In->getType(), 1); @@ -573,7 +573,7 @@ if ((Op1CV != 0) == isNE) { // Toggle the low bit. Constant *One = ConstantInt::get(In->getType(), 1); - In = Builder->CreateXor(In, One, "tmp"); + In = Builder->CreateXor(In, One); } if (CI.getType() == In->getType()) @@ -821,7 +821,7 @@ AndValue)); } if (SrcSize > DstSize) { - Value *Trunc = Builder->CreateTrunc(A, CI.getType(), "tmp"); + Value *Trunc = Builder->CreateTrunc(A, CI.getType()); APInt AndValue(APInt::getLowBitsSet(DstSize, MidSize)); return BinaryOperator::CreateAnd(Trunc, ConstantInt::get(Trunc->getType(), @@ -868,7 +868,7 @@ Value *TI0 = TI->getOperand(0); if (TI0->getType() == CI.getType()) { Constant *ZC = ConstantExpr::getZExt(C, CI.getType()); - Value *NewAnd = Builder->CreateAnd(TI0, ZC, "tmp"); + Value *NewAnd = Builder->CreateAnd(TI0, ZC); return BinaryOperator::CreateXor(NewAnd, ZC); } } @@ -901,7 +901,7 @@ Op0->getType()->getScalarSizeInBits()-1); Value *In = Builder->CreateAShr(Op0, Sh, Op0->getName()+".lobit"); if (In->getType() != CI.getType()) - In = Builder->CreateIntCast(In, CI.getType(), true/*SExt*/, "tmp"); + In = Builder->CreateIntCast(In, CI.getType(), true/*SExt*/); if (Pred == ICmpInst::ICMP_SGT) In = Builder->CreateNot(In, In->getName()+".not"); @@ -1307,13 +1307,13 @@ if (CI.getOperand(0)->getType()->getScalarSizeInBits() > TD->getPointerSizeInBits()) { Value *P = Builder->CreateTrunc(CI.getOperand(0), - TD->getIntPtrType(CI.getContext()), "tmp"); + TD->getIntPtrType(CI.getContext())); return new IntToPtrInst(P, CI.getType()); } if (CI.getOperand(0)->getType()->getScalarSizeInBits() < TD->getPointerSizeInBits()) { Value *P = Builder->CreateZExt(CI.getOperand(0), - TD->getIntPtrType(CI.getContext()), "tmp"); + TD->getIntPtrType(CI.getContext())); return new IntToPtrInst(P, CI.getType()); } } @@ -1382,14 +1382,12 @@ if (TD) { if (CI.getType()->getScalarSizeInBits() < TD->getPointerSizeInBits()) { Value *P = Builder->CreatePtrToInt(CI.getOperand(0), - TD->getIntPtrType(CI.getContext()), - "tmp"); + TD->getIntPtrType(CI.getContext())); return new TruncInst(P, CI.getType()); } if (CI.getType()->getScalarSizeInBits() > TD->getPointerSizeInBits()) { Value *P = Builder->CreatePtrToInt(CI.getOperand(0), - TD->getIntPtrType(CI.getContext()), - "tmp"); + TD->getIntPtrType(CI.getContext())); return new ZExtInst(P, CI.getType()); } } Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Tue Sep 27 15:39:19 2011 @@ -1186,10 +1186,10 @@ // Compute C << Y. Value *NS; if (Shift->getOpcode() == Instruction::LShr) { - NS = Builder->CreateShl(AndCST, Shift->getOperand(1), "tmp"); + NS = Builder->CreateShl(AndCST, Shift->getOperand(1)); } else { // Insert a logical shift. - NS = Builder->CreateLShr(AndCST, Shift->getOperand(1), "tmp"); + NS = Builder->CreateLShr(AndCST, Shift->getOperand(1)); } // Compute X & (C << Y). @@ -2484,7 +2484,7 @@ match(D, m_ConstantInt(C2)) && Op1->hasOneUse()) { Constant *NC = ConstantInt::get(I.getContext(), C1->getValue() ^ C2->getValue()); - Value *Xor = Builder->CreateXor(C, NC, "tmp"); + Value *Xor = Builder->CreateXor(C, NC); return new ICmpInst(I.getPredicate(), A, Xor); } @@ -2520,8 +2520,8 @@ } if (X) { // Build (X^Y) & Z - Op1 = Builder->CreateXor(X, Y, "tmp"); - Op1 = Builder->CreateAnd(Op1, Z, "tmp"); + Op1 = Builder->CreateXor(X, Y); + Op1 = Builder->CreateAnd(Op1, Z); I.setOperand(0, Op1); I.setOperand(1, Constant::getNullValue(Op1->getType())); return &I; Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Tue Sep 27 15:39:19 2011 @@ -38,7 +38,7 @@ m_Value(B))) && // The "1" can be any value known to be a power of 2. isPowerOfTwo(PowerOf2, IC.getTargetData())) { - A = IC.Builder->CreateSub(A, B, "tmp"); + A = IC.Builder->CreateSub(A, B); return IC.Builder->CreateShl(PowerOf2, A); } @@ -131,7 +131,7 @@ { Value *X; ConstantInt *C1; if (Op0->hasOneUse() && match(Op0, m_Add(m_Value(X), m_ConstantInt(C1)))) { - Value *Add = Builder->CreateMul(X, CI, "tmp"); + Value *Add = Builder->CreateMul(X, CI); return BinaryOperator::CreateAdd(Add, Builder->CreateMul(C1, CI)); } } @@ -244,7 +244,7 @@ if (BoolCast) { Value *V = Builder->CreateSub(Constant::getNullValue(I.getType()), - BoolCast, "tmp"); + BoolCast); return BinaryOperator::CreateAnd(V, OtherOp); } } @@ -466,8 +466,7 @@ { const APInt *CI; Value *N; if (match(Op1, m_Shl(m_Power2(CI), m_Value(N)))) { if (*CI != 1) - N = Builder->CreateAdd(N, ConstantInt::get(I.getType(), CI->logBase2()), - "tmp"); + N = Builder->CreateAdd(N, ConstantInt::get(I.getType(),CI->logBase2())); if (I.isExact()) return BinaryOperator::CreateExactLShr(Op0, N); return BinaryOperator::CreateLShr(Op0, N); @@ -630,7 +629,7 @@ // Turn A % (C << N), where C is 2^k, into A & ((C << N)-1) if (match(Op1, m_Shl(m_Power2(), m_Value()))) { Constant *N1 = Constant::getAllOnesValue(I.getType()); - Value *Add = Builder->CreateAdd(Op1, N1, "tmp"); + Value *Add = Builder->CreateAdd(Op1, N1); return BinaryOperator::CreateAnd(Op0, Add); } Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Tue Sep 27 15:39:19 2011 @@ -325,8 +325,7 @@ if ((RHSKnownOne & LHSKnownOne) == RHSKnownOne) { Constant *AndC = Constant::getIntegerValue(VTy, ~RHSKnownOne & DemandedMask); - Instruction *And = - BinaryOperator::CreateAnd(I->getOperand(0), AndC, "tmp"); + Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC); return InsertNewInstWith(And, *I); } } @@ -351,14 +350,12 @@ Constant *AndC = ConstantInt::get(I->getType(), NewMask & AndRHS->getValue()); - Instruction *NewAnd = - BinaryOperator::CreateAnd(I->getOperand(0), AndC, "tmp"); + Instruction *NewAnd = BinaryOperator::CreateAnd(I->getOperand(0), AndC); InsertNewInstWith(NewAnd, *I); Constant *XorC = ConstantInt::get(I->getType(), NewMask & XorRHS->getValue()); - Instruction *NewXor = - BinaryOperator::CreateXor(NewAnd, XorC, "tmp"); + Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC); return InsertNewInstWith(NewXor, *I); } Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Tue Sep 27 15:39:19 2011 @@ -822,7 +822,7 @@ DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrMode << " for " << *MemoryInst); if (SunkAddr->getType() != Addr->getType()) - SunkAddr = Builder.CreateBitCast(SunkAddr, Addr->getType(), "tmp"); + SunkAddr = Builder.CreateBitCast(SunkAddr, Addr->getType()); } else { DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for " << *MemoryInst); Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue Sep 27 15:39:19 2011 @@ -946,10 +946,9 @@ // Compute which bits of the stored value are being used by the load. Convert // to an integer type to start with. if (SrcVal->getType()->isPointerTy()) - SrcVal = Builder.CreatePtrToInt(SrcVal, TD.getIntPtrType(Ctx), "tmp"); + SrcVal = Builder.CreatePtrToInt(SrcVal, TD.getIntPtrType(Ctx)); if (!SrcVal->getType()->isIntegerTy()) - SrcVal = Builder.CreateBitCast(SrcVal, IntegerType::get(Ctx, StoreSize*8), - "tmp"); + SrcVal = Builder.CreateBitCast(SrcVal, IntegerType::get(Ctx, StoreSize*8)); // Shift the bits to the least significant depending on endianness. unsigned ShiftAmt; @@ -959,11 +958,10 @@ ShiftAmt = (StoreSize-LoadSize-Offset)*8; if (ShiftAmt) - SrcVal = Builder.CreateLShr(SrcVal, ShiftAmt, "tmp"); + SrcVal = Builder.CreateLShr(SrcVal, ShiftAmt); if (LoadSize != StoreSize) - SrcVal = Builder.CreateTrunc(SrcVal, IntegerType::get(Ctx, LoadSize*8), - "tmp"); + SrcVal = Builder.CreateTrunc(SrcVal, IntegerType::get(Ctx, LoadSize*8)); return CoerceAvailableValueToLoadType(SrcVal, LoadTy, InsertPt, TD); } Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Tue Sep 27 15:39:19 2011 @@ -492,7 +492,7 @@ Value *BranchVal = LIC; if (!isa(Val) || Val->getType() != Type::getInt1Ty(LIC->getContext())) - BranchVal = new ICmpInst(InsertPt, ICmpInst::ICMP_EQ, LIC, Val, "tmp"); + BranchVal = new ICmpInst(InsertPt, ICmpInst::ICMP_EQ, LIC, Val); else if (Val != ConstantInt::getTrue(Val->getContext())) // We want to enter the new loop when the condition is true. std::swap(TrueDest, FalseDest); Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Sep 27 15:39:19 2011 @@ -617,7 +617,7 @@ if (LoadInst *LI = dyn_cast(User)) { // The load is a bit extract from NewAI shifted right by Offset bits. - Value *LoadedVal = Builder.CreateLoad(NewAI, "tmp"); + Value *LoadedVal = Builder.CreateLoad(NewAI); Value *NewLoadVal = ConvertScalar_ExtractValue(LoadedVal, LI->getType(), Offset, Builder); LI->replaceAllUsesWith(NewLoadVal); @@ -822,7 +822,7 @@ // a shuffle vector. if (FromType->getPrimitiveSizeInBits() == ToType->getPrimitiveSizeInBits()) - return Builder.CreateBitCast(FromVal, ToType, "tmp"); + return Builder.CreateBitCast(FromVal, ToType); else return CreateShuffleVectorCast(FromVal, ToType, Builder); } @@ -838,14 +838,14 @@ LLVMContext &Context = FromVal->getContext(); Type *CastTy = VectorType::get(CastElementTy, NumCastVectorElements); - Value *Cast = Builder.CreateBitCast(FromVal, CastTy, "tmp"); + Value *Cast = Builder.CreateBitCast(FromVal, CastTy); unsigned EltSize = TD.getTypeAllocSizeInBits(CastElementTy); unsigned Elt = Offset/EltSize; assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); Value *Extract = Builder.CreateExtractElement(Cast, ConstantInt::get( - Type::getInt32Ty(Context), Elt), "tmp"); - return Builder.CreateBitCast(Extract, ToType, "tmp"); + Type::getInt32Ty(Context), Elt)); + return Builder.CreateBitCast(Extract, ToType); } // Otherwise it must be an element access. @@ -856,10 +856,9 @@ assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); } // Return the element extracted out of it. - Value *V = Builder.CreateExtractElement(FromVal, ConstantInt::get( - Type::getInt32Ty(FromVal->getContext()), Elt), "tmp"); + Value *V = Builder.CreateExtractElement(FromVal, Builder.getInt32(Elt)); if (V->getType() != ToType) - V = Builder.CreateBitCast(V, ToType, "tmp"); + V = Builder.CreateBitCast(V, ToType); return V; } @@ -872,7 +871,7 @@ Value *Elt = ConvertScalar_ExtractValue(FromVal, ST->getElementType(i), Offset+Layout.getElementOffsetInBits(i), Builder); - Res = Builder.CreateInsertValue(Res, Elt, i, "tmp"); + Res = Builder.CreateInsertValue(Res, Elt, i); } return Res; } @@ -883,7 +882,7 @@ for (unsigned i = 0, e = AT->getNumElements(); i != e; ++i) { Value *Elt = ConvertScalar_ExtractValue(FromVal, AT->getElementType(), Offset+i*EltSize, Builder); - Res = Builder.CreateInsertValue(Res, Elt, i, "tmp"); + Res = Builder.CreateInsertValue(Res, Elt, i); } return Res; } @@ -909,33 +908,31 @@ // only some bits are used. if (ShAmt > 0 && (unsigned)ShAmt < NTy->getBitWidth()) FromVal = Builder.CreateLShr(FromVal, - ConstantInt::get(FromVal->getType(), - ShAmt), "tmp"); + ConstantInt::get(FromVal->getType(), ShAmt)); else if (ShAmt < 0 && (unsigned)-ShAmt < NTy->getBitWidth()) FromVal = Builder.CreateShl(FromVal, - ConstantInt::get(FromVal->getType(), - -ShAmt), "tmp"); + ConstantInt::get(FromVal->getType(), -ShAmt)); // Finally, unconditionally truncate the integer to the right width. unsigned LIBitWidth = TD.getTypeSizeInBits(ToType); if (LIBitWidth < NTy->getBitWidth()) FromVal = Builder.CreateTrunc(FromVal, IntegerType::get(FromVal->getContext(), - LIBitWidth), "tmp"); + LIBitWidth)); else if (LIBitWidth > NTy->getBitWidth()) FromVal = Builder.CreateZExt(FromVal, IntegerType::get(FromVal->getContext(), - LIBitWidth), "tmp"); + LIBitWidth)); // If the result is an integer, this is a trunc or bitcast. if (ToType->isIntegerTy()) { // Should be done. } else if (ToType->isFloatingPointTy() || ToType->isVectorTy()) { // Just do a bitcast, we know the sizes match up. - FromVal = Builder.CreateBitCast(FromVal, ToType, "tmp"); + FromVal = Builder.CreateBitCast(FromVal, ToType); } else { // Otherwise must be a pointer. - FromVal = Builder.CreateIntToPtr(FromVal, ToType, "tmp"); + FromVal = Builder.CreateIntToPtr(FromVal, ToType); } assert(FromVal->getType() == ToType && "Didn't convert right?"); return FromVal; @@ -971,7 +968,7 @@ // a shuffle vector. if (VTy->getPrimitiveSizeInBits() == SV->getType()->getPrimitiveSizeInBits()) - return Builder.CreateBitCast(SV, AllocaType, "tmp"); + return Builder.CreateBitCast(SV, AllocaType); else return CreateShuffleVectorCast(SV, VTy, Builder); } @@ -984,36 +981,31 @@ ValSize); unsigned NumCastVectorElements = VecSize / ValSize; - LLVMContext &Context = SV->getContext(); - Type *OldCastTy = VectorType::get(CastElementTy, - NumCastVectorElements); - Value *OldCast = Builder.CreateBitCast(Old, OldCastTy, "tmp"); + Type *OldCastTy = VectorType::get(CastElementTy, NumCastVectorElements); + Value *OldCast = Builder.CreateBitCast(Old, OldCastTy); - Value *SVCast = Builder.CreateBitCast(SV, CastElementTy, "tmp"); + Value *SVCast = Builder.CreateBitCast(SV, CastElementTy); unsigned EltSize = TD.getTypeAllocSizeInBits(CastElementTy); unsigned Elt = Offset/EltSize; assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); Value *Insert = - Builder.CreateInsertElement(OldCast, SVCast, ConstantInt::get( - Type::getInt32Ty(Context), Elt), "tmp"); - return Builder.CreateBitCast(Insert, AllocaType, "tmp"); + Builder.CreateInsertElement(OldCast, SVCast, Builder.getInt32(Elt)); + return Builder.CreateBitCast(Insert, AllocaType); } // Must be an element insertion. assert(SV->getType() == VTy->getElementType()); uint64_t EltSize = TD.getTypeAllocSizeInBits(VTy->getElementType()); unsigned Elt = Offset/EltSize; - return Builder.CreateInsertElement(Old, SV, - ConstantInt::get(Type::getInt32Ty(SV->getContext()), Elt), - "tmp"); + return Builder.CreateInsertElement(Old, SV, Builder.getInt32(Elt)); } // If SV is a first-class aggregate value, insert each value recursively. if (StructType *ST = dyn_cast(SV->getType())) { const StructLayout &Layout = *TD.getStructLayout(ST); for (unsigned i = 0, e = ST->getNumElements(); i != e; ++i) { - Value *Elt = Builder.CreateExtractValue(SV, i, "tmp"); + Value *Elt = Builder.CreateExtractValue(SV, i); Old = ConvertScalar_InsertValue(Elt, Old, Offset+Layout.getElementOffsetInBits(i), Builder); @@ -1024,7 +1016,7 @@ if (ArrayType *AT = dyn_cast(SV->getType())) { uint64_t EltSize = TD.getTypeAllocSizeInBits(AT->getElementType()); for (unsigned i = 0, e = AT->getNumElements(); i != e; ++i) { - Value *Elt = Builder.CreateExtractValue(SV, i, "tmp"); + Value *Elt = Builder.CreateExtractValue(SV, i); Old = ConvertScalar_InsertValue(Elt, Old, Offset+i*EltSize, Builder); } return Old; @@ -1037,20 +1029,19 @@ unsigned SrcStoreWidth = TD.getTypeStoreSizeInBits(SV->getType()); unsigned DestStoreWidth = TD.getTypeStoreSizeInBits(AllocaType); if (SV->getType()->isFloatingPointTy() || SV->getType()->isVectorTy()) - SV = Builder.CreateBitCast(SV, - IntegerType::get(SV->getContext(),SrcWidth), "tmp"); + SV = Builder.CreateBitCast(SV, IntegerType::get(SV->getContext(),SrcWidth)); else if (SV->getType()->isPointerTy()) - SV = Builder.CreatePtrToInt(SV, TD.getIntPtrType(SV->getContext()), "tmp"); + SV = Builder.CreatePtrToInt(SV, TD.getIntPtrType(SV->getContext())); // Zero extend or truncate the value if needed. if (SV->getType() != AllocaType) { if (SV->getType()->getPrimitiveSizeInBits() < AllocaType->getPrimitiveSizeInBits()) - SV = Builder.CreateZExt(SV, AllocaType, "tmp"); + SV = Builder.CreateZExt(SV, AllocaType); else { // Truncation may be needed if storing more than the alloca can hold // (undefined behavior). - SV = Builder.CreateTrunc(SV, AllocaType, "tmp"); + SV = Builder.CreateTrunc(SV, AllocaType); SrcWidth = DestWidth; SrcStoreWidth = DestStoreWidth; } @@ -1073,12 +1064,10 @@ // only some bits in the structure are set. APInt Mask(APInt::getLowBitsSet(DestWidth, SrcWidth)); if (ShAmt > 0 && (unsigned)ShAmt < DestWidth) { - SV = Builder.CreateShl(SV, ConstantInt::get(SV->getType(), - ShAmt), "tmp"); + SV = Builder.CreateShl(SV, ConstantInt::get(SV->getType(), ShAmt)); Mask <<= ShAmt; } else if (ShAmt < 0 && (unsigned)-ShAmt < DestWidth) { - SV = Builder.CreateLShr(SV, ConstantInt::get(SV->getType(), - -ShAmt), "tmp"); + SV = Builder.CreateLShr(SV, ConstantInt::get(SV->getType(), -ShAmt)); Mask = Mask.lshr(-ShAmt); } Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Tue Sep 27 15:39:19 2011 @@ -874,8 +874,8 @@ Callee->getAttributes()); Value *FAbs = EmitUnaryFloatFnCall(Sqrt, "fabs", B, Callee->getAttributes()); - Value *FCmp = B.CreateFCmpOEQ(Op1, NegInf, "tmp"); - Value *Sel = B.CreateSelect(FCmp, Inf, FAbs, "tmp"); + Value *FCmp = B.CreateFCmpOEQ(Op1, NegInf); + Value *Sel = B.CreateSelect(FCmp, Inf, FAbs); return Sel; } @@ -908,10 +908,10 @@ Value *LdExpArg = 0; if (SIToFPInst *OpC = dyn_cast(Op)) { if (OpC->getOperand(0)->getType()->getPrimitiveSizeInBits() <= 32) - LdExpArg = B.CreateSExt(OpC->getOperand(0), B.getInt32Ty(), "tmp"); + LdExpArg = B.CreateSExt(OpC->getOperand(0), B.getInt32Ty()); } else if (UIToFPInst *OpC = dyn_cast(Op)) { if (OpC->getOperand(0)->getType()->getPrimitiveSizeInBits() < 32) - LdExpArg = B.CreateZExt(OpC->getOperand(0), B.getInt32Ty(), "tmp"); + LdExpArg = B.CreateZExt(OpC->getOperand(0), B.getInt32Ty()); } if (LdExpArg) { @@ -996,10 +996,10 @@ Value *F = Intrinsic::getDeclaration(Callee->getParent(), Intrinsic::cttz, ArgType); Value *V = B.CreateCall(F, Op, "cttz"); - V = B.CreateAdd(V, ConstantInt::get(V->getType(), 1), "tmp"); - V = B.CreateIntCast(V, B.getInt32Ty(), false, "tmp"); + V = B.CreateAdd(V, ConstantInt::get(V->getType(), 1)); + V = B.CreateIntCast(V, B.getInt32Ty(), false); - Value *Cond = B.CreateICmpNE(Op, Constant::getNullValue(ArgType), "tmp"); + Value *Cond = B.CreateICmpNE(Op, Constant::getNullValue(ArgType)); return B.CreateSelect(Cond, V, B.getInt32(0)); } }; Modified: llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp Tue Sep 27 15:39:19 2011 @@ -221,8 +221,7 @@ return; ICmpInst *ICmp = new ICmpInst(Rem, ICmpInst::ICMP_EQ, - Rem->getOperand(0), Rem->getOperand(1), - "tmp"); + Rem->getOperand(0), Rem->getOperand(1)); SelectInst *Sel = SelectInst::Create(ICmp, ConstantInt::get(Rem->getType(), 0), Modified: llvm/trunk/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll Tue Sep 27 15:39:19 2011 @@ -1,5 +1,5 @@ ; RUN: opt < %s -indvars -S -enable-iv-rewrite | FileCheck %s -; CHECK: %p.2.ip.1 = getelementptr [3 x [3 x double]]* %p, i64 2, i64 %tmp, i64 1 +; CHECK: %p.2.ip.1 = getelementptr [3 x [3 x double]]* %p, i64 2, i64 %0, i64 1 target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128-n:32:64" ; Indvars shouldn't expand this to Modified: llvm/trunk/test/Transforms/InstCombine/call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/call.ll?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/call.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/call.ll Tue Sep 27 15:39:19 2011 @@ -9,8 +9,8 @@ define void @test1(i32* %A) { call void bitcast (void (i8*)* @test1a to void (i32*)*)( i32* %A ) ret void -; CHECK: %tmp = bitcast i32* %A to i8* -; CHECK: call void @test1a(i8* %tmp) +; CHECK: %1 = bitcast i32* %A to i8* +; CHECK: call void @test1a(i8* %1) ; CHECK: ret void } @@ -24,8 +24,8 @@ define i32 @test2(i32 %A) { call void bitcast (void (i8)* @test2a to void (i32)*)( i32 %A ) ret i32 %A -; CHECK: %tmp = trunc i32 %A to i8 -; CHECK: call void @test2a(i8 %tmp) +; CHECK: %1 = trunc i32 %A to i8 +; CHECK: call void @test2a(i8 %1) ; CHECK: ret i32 %A } @@ -38,8 +38,8 @@ call void bitcast (void (i8, ...)* @test3a to void (i8, i8)*)( i8 %A, i8 %B ) ret void -; CHECK: %tmp = zext i8 %B to i32 -; CHECK: call void (i8, ...)* @test3a(i8 %A, i32 %tmp) +; CHECK: %1 = zext i8 %B to i32 +; CHECK: call void (i8, ...)* @test3a(i8 %A, i32 %1) ; CHECK: ret void } @@ -54,8 +54,8 @@ %X = call i32 bitcast (i8 ()* @test4a to i32 ()*)( ) ; [#uses=1] ret i32 %X ; CHECK: %X = call i8 @test4a() -; CHECK: %tmp = zext i8 %X to i32 -; CHECK: ret i32 %tmp +; CHECK: %1 = zext i8 %X to i32 +; CHECK: ret i32 %1 } Modified: llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll Tue Sep 27 15:39:19 2011 @@ -5,22 +5,22 @@ entry: ; CHECK: test1 ; CHECK: ptrtoint i32* %x to i64 - %tmp = ptrtoint i32* %x to i1 - ret i1 %tmp + %0 = ptrtoint i32* %x to i1 + ret i1 %0 } define i32* @test2(i128 %x) nounwind { entry: ; CHECK: test2 -; CHECK: inttoptr i64 %tmp1 to i32* - %tmp = inttoptr i128 %x to i32* - ret i32* %tmp +; CHECK: inttoptr i64 %0 to i32* + %0 = inttoptr i128 %x to i32* + ret i32* %0 } ; PR3574 ; CHECK: f0 -; CHECK: %tmp = zext i32 %a0 to i64 -; CHECK: ret i64 %tmp +; CHECK: %1 = zext i32 %a0 to i64 +; CHECK: ret i64 %1 define i64 @f0(i32 %a0) nounwind { %t0 = inttoptr i32 %a0 to i8* %t1 = ptrtoint i8* %t0 to i64 Modified: llvm/trunk/test/Transforms/InstCombine/vector-casts.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vector-casts.ll?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/vector-casts.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/vector-casts.ll Tue Sep 27 15:39:19 2011 @@ -7,7 +7,7 @@ ; CHECK: @test1 ; CHECK: and <2 x i64> %a, -; CHECK: icmp ne <2 x i64> %tmp, zeroinitializer +; CHECK: icmp ne <2 x i64> %1, zeroinitializer } ; The ashr turns into an lshr. Modified: llvm/trunk/test/Transforms/LoopIdiom/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopIdiom/basic.ll?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LoopIdiom/basic.ll (original) +++ llvm/trunk/test/Transforms/LoopIdiom/basic.ll Tue Sep 27 15:39:19 2011 @@ -62,8 +62,8 @@ ret void ; CHECK: @test2 ; CHECK: br i1 %cmp10, -; CHECK: %tmp = mul i64 %Size, 4 -; CHECK: call void @llvm.memset.p0i8.i64(i8* %Base1, i8 1, i64 %tmp, i32 4, i1 false) +; CHECK: %0 = mul i64 %Size, 4 +; CHECK: call void @llvm.memset.p0i8.i64(i8* %Base1, i8 1, i64 %0, i32 4, i1 false) ; CHECK-NOT: store } Modified: llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll (original) +++ llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll Tue Sep 27 15:39:19 2011 @@ -4,15 +4,15 @@ ; LSR should property handle the post-inc offset when folding the ; non-IV operand of an icmp into the IV. -; CHECK: %tmp2 = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast -; CHECK: %tmp3 = lshr i64 %tmp2, 1 -; CHECK: %tmp4 = mul i64 %tmp3, 2 +; CHECK: %5 = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast +; CHECK: %6 = lshr i64 %5, 1 +; CHECK: %7 = mul i64 %6, 2 ; CHECK: br label %for.body ; CHECK: for.body: -; CHECK: %lsr.iv5 = phi i64 [ %lsr.iv.next, %for.body ], [ %tmp4, %for.body.lr.ph ] -; CHECK: %lsr.iv.next = add i64 %lsr.iv5, -2 -; CHECK: %lsr.iv.next6 = inttoptr i64 %lsr.iv.next to i16* -; CHECK: %cmp27 = icmp eq i16* %lsr.iv.next6, null +; CHECK: %lsr.iv2 = phi i64 [ %lsr.iv.next, %for.body ], [ %7, %for.body.lr.ph ] +; CHECK: %lsr.iv.next = add i64 %lsr.iv2, -2 +; CHECK: %lsr.iv.next3 = inttoptr i64 %lsr.iv.next to i16* +; CHECK: %cmp27 = icmp eq i16* %lsr.iv.next3, null target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" Modified: llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Tue Sep 27 15:39:19 2011 @@ -110,7 +110,7 @@ ; CHECK-NOT: alloca ; CHECK: bitcast <4 x float> %x to <2 x double> ; CHECK-NEXT: extractelement <2 x double> -; CHECK-NEXT: bitcast double %tmp4 to <2 x float> +; CHECK-NEXT: bitcast double %2 to <2 x float> ; CHECK-NEXT: extractelement <4 x float> } @@ -125,7 +125,7 @@ ; CHECK: bitcast <4 x float> %x to <2 x double> ; CHECK-NEXT: bitcast <2 x float> %y to double ; CHECK-NEXT: insertelement <2 x double> -; CHECK-NEXT: bitcast <2 x double> %tmp2 to <4 x float> +; CHECK-NEXT: bitcast <2 x double> %3 to <4 x float> } define i256 @test9(<4 x i256> %x) { @@ -140,7 +140,7 @@ ; CHECK-NOT: alloca ; CHECK: bitcast <4 x i256> %x to <2 x i512> ; CHECK-NEXT: extractelement <2 x i512> -; CHECK-NEXT: bitcast i512 %tmp4 to <2 x i256> +; CHECK-NEXT: bitcast i512 %2 to <2 x i256> ; CHECK-NEXT: extractelement <4 x i256> } @@ -155,7 +155,7 @@ ; CHECK: bitcast <4 x i256> %x to <2 x i512> ; CHECK-NEXT: bitcast <2 x i256> %y to i512 ; CHECK-NEXT: insertelement <2 x i512> -; CHECK-NEXT: bitcast <2 x i512> %tmp2 to <4 x i256> +; CHECK-NEXT: bitcast <2 x i512> %3 to <4 x i256> } %union.v = type { <2 x i64> } @@ -245,7 +245,7 @@ ret void ; CHECK: @test15 ; CHECK-NOT: alloca -; CHECK: shufflevector <4 x i64> %tmpV2, <4 x i64> undef, <3 x i32> +; CHECK: shufflevector <4 x i64> %tmpV1, <4 x i64> undef, <3 x i32> } define <4 x float> @test16(<4 x float> %x, i64 %y0, i64 %y1) { Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/pow-to-sqrt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/pow-to-sqrt.ll?rev=140634&r1=140633&r2=140634&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyLibCalls/pow-to-sqrt.ll (original) +++ llvm/trunk/test/Transforms/SimplifyLibCalls/pow-to-sqrt.ll Tue Sep 27 15:39:19 2011 @@ -7,9 +7,9 @@ ; CHECK: define float @foo(float %x) nounwind { ; CHECK: %sqrtf = call float @sqrtf(float %x) nounwind readonly ; CHECK: %fabsf = call float @fabsf(float %sqrtf) nounwind readonly -; CHECK: %tmp = fcmp oeq float %x, 0xFFF0000000000000 -; CHECK: %tmp1 = select i1 %tmp, float 0x7FF0000000000000, float %fabsf -; CHECK: ret float %tmp1 +; CHECK: %1 = fcmp oeq float %x, 0xFFF0000000000000 +; CHECK: %retval = select i1 %1, float 0x7FF0000000000000, float %fabsf +; CHECK: ret float %retval define float @foo(float %x) nounwind { %retval = call float @powf(float %x, float 0.5) @@ -19,9 +19,9 @@ ; CHECK: define double @doo(double %x) nounwind { ; CHECK: %sqrt = call double @sqrt(double %x) nounwind readonly ; CHECK: %fabs = call double @fabs(double %sqrt) nounwind readonly -; CHECK: %tmp = fcmp oeq double %x, 0xFFF0000000000000 -; CHECK: %tmp1 = select i1 %tmp, double 0x7FF0000000000000, double %fabs -; CHECK: ret double %tmp1 +; CHECK: %1 = fcmp oeq double %x, 0xFFF0000000000000 +; CHECK: %retval = select i1 %1, double 0x7FF0000000000000, double %fabs +; CHECK: ret double %retval ; CHECK: } define double @doo(double %x) nounwind { From echristo at apple.com Tue Sep 27 15:43:01 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 27 Sep 2011 13:43:01 -0700 Subject: [llvm-commits] [llvm] r140634 - in /llvm/trunk: lib/Analysis/ lib/Transforms/IPO/ lib/Transforms/InstCombine/ lib/Transforms/Scalar/ lib/Transforms/Utils/ test/Transforms/IndVarSimplify/ test/Transforms/InstCombine/ test/Transforms/LoopIdiom/ test/Transforms/LoopStrengthReduce/ test/Transforms/ScalarRepl/ test/Transforms/SimplifyLibCalls/ In-Reply-To: <20110927203919.B8EF02A6C12C@llvm.org> References: <20110927203919.B8EF02A6C12C@llvm.org> Message-ID: <278A34CE-34C3-4714-BAB3-A927840BD6D1@apple.com> On Sep 27, 2011, at 1:39 PM, Benjamin Kramer wrote: > Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit. Awesome. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110927/a35c9c77/attachment.html From nlewycky at google.com Tue Sep 27 15:57:08 2011 From: nlewycky at google.com (Nick Lewycky) Date: Tue, 27 Sep 2011 13:57:08 -0700 Subject: [llvm-commits] [llvm] r139125 - in /llvm/trunk/lib/Target: ARM/ARM.td ARM/ARMInstrInfo.td ARM/ARMSubtarget.cpp ARM/ARMSubtarget.h ARM/MCTargetDesc/ARMMCTargetDesc.cpp X86/MCTargetDesc/X86MCTargetDesc.cpp X86/X86.td X86/X86InstrInfo.td X86/X86Subt Message-ID: On 14 September 2011 21:31, Nick Lewycky wrote: > Jim Grosbach wrote: > > > > On Sep 8, 2011, at 10:44 PM, Chris Lattner wrote: > > > >> > >> On Sep 6, 2011, at 10:05 AM, Jim Grosbach wrote: > >> > >>> Hi Nick, > >>> > >>> I have a few concerns about this that hopefully won't be too hard to > alleviate. On the more trite side, we generally try to keep the nomenclature > descriptive of purpose rather than of use. This patch names the sub-target > feature according to purpose (native client) and doesn't give any indication > of what it actually does. Is this really a sub-target feature at all? > Honestly, my general impression is that this is more accurately a target > platform in the triple akin to Linux or Darwin. For example, > thumbv7-unknown-nacl. Assuming so (and it looks like that is indeed how it's > specified?), why isn't querying the triple directly a-la > ARMSubtarget->isTargetDarwin(), sufficient? Lastly, speculating here as this > patch doesn't go into these details, but be very careful with alignment > changes in code sections, as the ARM backend is very sensitive to small > changes. Specifically, the constant island pass tracks instruction alignment > and relative distances as exactly as it can, and wil > l > > n! > >>> eed to be taught how to deal with these changes. > >> > >> I agree in principle, but I can see it go both ways. Note that 64-bit > support is also a "subtarget feature" which is also very odd, but > convenient. > > > > The key distinction is that 64-bit mode is orthogonal to the target and > NaCl is not. By definition, NaCl is a target OS like Darwin or Linux, as > that's where it shows up in the triple already. By making NaCl a true sub > target feature, we're duplicating information that already exists in the > triple. > > > >> That said, if "NaCL mode" is really just normal codegen plus a few > tweaks, it would be much better to add subtarget features for the tweaks, > and nacl mode could enable those tweaks. This respect is very different > than 64-bit support. > > > > Exactly. ARM does this sort of thing in the ARMSubtarget() constructor, > for example, by enabling/disabling certain features by default (reserving R9 > and use of movw/movt in v7) based on the target OS. > > > > I have no problem with there being an isTargetNaCl() accessor in the > ARMSubtarget/X86Subtarget classes. That part makes sense, and is akin to how > we have isTargetDarwin() already. It's only the implementation underneath > that which I object to. > > That makes sense to me. Thanks for the review! > > David, could you make the changes per Jim's review? > David? Ping? > Nick > > > > > -Jim > > > > > >>> > >>> On Sep 5, 2011, at 2:51 PM, Nick Lewycky wrote: > >>> > >>>> Author: nicholas > >>>> Date: Mon Sep 5 16:51:43 2011 > >>>> New Revision: 139125 > >>>> > >>>> URL: http://llvm.org/viewvc/llvm-project?rev=139125&view=rev > >>>> Log: > >>>> Add a new MC bit for NaCl (Native Client) mode. NaCl requires that > certain > >>>> instructions are more aligned than the CPU requires, and adds some > additional > >>>> directives, to follow in future patches. Patch by David Meyer! > >>>> > >>>> Modified: > >>>> llvm/trunk/lib/Target/ARM/ARM.td > >>>> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > >>>> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > >>>> llvm/trunk/lib/Target/ARM/ARMSubtarget.h > >>>> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > >>>> llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp > >>>> llvm/trunk/lib/Target/X86/X86.td > >>>> llvm/trunk/lib/Target/X86/X86InstrInfo.td > >>>> llvm/trunk/lib/Target/X86/X86Subtarget.cpp > >>>> llvm/trunk/lib/Target/X86/X86Subtarget.h > >>>> > >>>> Modified: llvm/trunk/lib/Target/ARM/ARM.td > >>>> URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=139125&r1=139124&r2=139125&view=diff > >>>> > ============================================================================== > >>>> --- llvm/trunk/lib/Target/ARM/ARM.td (original) > >>>> +++ llvm/trunk/lib/Target/ARM/ARM.td Mon Sep 5 16:51:43 2011 > >>>> @@ -23,6 +23,9 @@ > >>>> def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", > >>>> "Thumb mode">; > >>>> > >>>> +def ModeNaCl : SubtargetFeature<"nacl-mode", "InNaClMode", "true", > >>>> + "Native client mode">; > >>>> + > >>>> > //===----------------------------------------------------------------------===// > >>>> // ARM Subtarget features. > >>>> // > >>>> > >>>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > >>>> URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff > >>>> > ============================================================================== > >>>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) > >>>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep 5 16:51:43 2011 > >>>> @@ -209,6 +209,8 @@ > >>>> AssemblerPredicate<"!ModeThumb">; > >>>> def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; > >>>> def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; > >>>> +def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">, > >>>> + AssemblerPredicate<"ModeNaCl">; > >>>> > >>>> // FIXME: Eventually this will be just "hasV6T2Ops". > >>>> def UseMovt : Predicate<"Subtarget->useMovt()">; > >>>> > >>>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp > >>>> URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff > >>>> > ============================================================================== > >>>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) > >>>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Sep 5 16:51:43 > 2011 > >>>> @@ -53,6 +53,7 @@ > >>>> , HasVMLxForwarding(false) > >>>> , SlowFPBrcc(false) > >>>> , InThumbMode(false) > >>>> + , InNaClMode(false) > >>>> , HasThumb2(false) > >>>> , NoARM(false) > >>>> , PostRAScheduler(false) > >>>> > >>>> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h > >>>> URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=139125&r1=139124&r2=139125&view=diff > >>>> > ============================================================================== > >>>> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) > >>>> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Sep 5 16:51:43 2011 > >>>> @@ -70,6 +70,9 @@ > >>>> /// InThumbMode - True if compiling for Thumb, false for ARM. > >>>> bool InThumbMode; > >>>> > >>>> + /// InNaClMode - True if targeting Native Client > >>>> + bool InNaClMode; > >>>> + > >>>> /// HasThumb2 - True if Thumb2 instructions are supported. > >>>> bool HasThumb2; > >>>> > >>>> @@ -209,6 +212,9 @@ > >>>> const Triple&getTargetTriple() const { return TargetTriple; } > >>>> > >>>> bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } > >>>> + bool isTargetNaCl() const { > >>>> + return TargetTriple.getOS() == Triple::NativeClient; > >>>> + } > >>>> bool isTargetELF() const { return !isTargetDarwin(); } > >>>> > >>>> bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; } > >>>> > >>>> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > >>>> URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff > >>>> > ============================================================================== > >>>> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp > (original) > >>>> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Sep > 5 16:51:43 2011 > >>>> @@ -86,6 +86,14 @@ > >>>> ARMArchFeature += ",+thumb-mode"; > >>>> } > >>>> > >>>> + Triple TheTriple(TT); > >>>> + if (TheTriple.getOS() == Triple::NativeClient) { > >>>> + if (ARMArchFeature.empty()) > >>>> + ARMArchFeature = "+nacl-mode"; > >>>> + else > >>>> + ARMArchFeature += ",+nacl-mode"; > >>>> + } > >>>> + > >>>> return ARMArchFeature; > >>>> } > >>>> > >>>> > >>>> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp > >>>> URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=139125&r1=139124&r2=139125&view=diff > >>>> > ============================================================================== > >>>> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp > (original) > >>>> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Sep > 5 16:51:43 2011 > >>>> @@ -40,9 +40,16 @@ > >>>> > >>>> std::string X86_MC::ParseX86Triple(StringRef TT) { > >>>> Triple TheTriple(TT); > >>>> + std::string FS; > >>>> if (TheTriple.getArch() == Triple::x86_64) > >>>> - return "+64bit-mode"; > >>>> - return "-64bit-mode"; > >>>> + FS = "+64bit-mode"; > >>>> + else > >>>> + FS = "-64bit-mode"; > >>>> + if (TheTriple.getOS() == Triple::NativeClient) > >>>> + FS += ",+nacl-mode"; > >>>> + else > >>>> + FS += ",-nacl-mode"; > >>>> + return FS; > >>>> } > >>>> > >>>> /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 > values in the > >>>> > >>>> Modified: llvm/trunk/lib/Target/X86/X86.td > >>>> URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=139125&r1=139124&r2=139125&view=diff > >>>> > ============================================================================== > >>>> --- llvm/trunk/lib/Target/X86/X86.td (original) > >>>> +++ llvm/trunk/lib/Target/X86/X86.td Mon Sep 5 16:51:43 2011 > >>>> @@ -23,6 +23,9 @@ > >>>> def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", > >>>> "64-bit mode (x86_64)">; > >>>> > >>>> +def ModeNaCl : SubtargetFeature<"nacl-mode", "InNaClMode", "true", > >>>> + "Native Client mode">; > >>>> + > >>>> > //===----------------------------------------------------------------------===// > >>>> // X86 Subtarget features. > >>>> > //===----------------------------------------------------------------------===// > >>>> > >>>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td > >>>> URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=139125&r1=139124&r2=139125&view=diff > >>>> > ============================================================================== > >>>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) > >>>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep 5 16:51:43 2011 > >>>> @@ -482,6 +482,14 @@ > >>>> AssemblerPredicate<"Mode64Bit">; > >>>> def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; > >>>> def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; > >>>> +def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">, > >>>> + AssemblerPredicate<"ModeNaCl">; > >>>> +def IsNaCl32 : Predicate<"Subtarget->isTargetNaCl32()">, > >>>> + > AssemblerPredicate<"ModeNaCl,!Mode64Bit">; > >>>> +def IsNaCl64 : Predicate<"Subtarget->isTargetNaCl64()">, > >>>> + > AssemblerPredicate<"ModeNaCl,Mode64Bit">; > >>>> +def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">, > >>>> + AssemblerPredicate<"!ModeNaCl">; > >>>> def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; > >>>> def KernelCode : Predicate<"TM.getCodeModel() == > CodeModel::Kernel">; > >>>> def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small&&" > >>>> > >>>> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp > >>>> URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=139125&r1=139124&r2=139125&view=diff > >>>> > ============================================================================== > >>>> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) > >>>> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Sep 5 16:51:43 > 2011 > >>>> @@ -260,7 +260,8 @@ > >>>> // FIXME: this is a known good value for Yonah. How about others? > >>>> , MaxInlineSizeThreshold(128) > >>>> , TargetTriple(TT) > >>>> - , In64BitMode(is64Bit) { > >>>> + , In64BitMode(is64Bit) > >>>> + , InNaClMode(false) { > >>>> // Determine default and user specified characteristics > >>>> if (!FS.empty() || !CPU.empty()) { > >>>> std::string CPUName = CPU; > >>>> @@ -306,6 +307,11 @@ > >>>> if (In64BitMode) > >>>> ToggleFeature(X86::Mode64Bit); > >>>> > >>>> + if (isTargetNaCl()) { > >>>> + InNaClMode = true; > >>>> + ToggleFeature(X86::ModeNaCl); > >>>> + } > >>>> + > >>>> if (HasAVX) > >>>> X86SSELevel = NoMMXSSE; > >>>> > >>>> > >>>> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h > >>>> URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=139125&r1=139124&r2=139125&view=diff > >>>> > ============================================================================== > >>>> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original) > >>>> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Sep 5 16:51:43 2011 > >>>> @@ -119,6 +119,9 @@ > >>>> /// In64BitMode - True if compiling for 64-bit, false for 32-bit. > >>>> bool In64BitMode; > >>>> > >>>> + /// InNaClMode - True if compiling for Native Client target. > >>>> + bool InNaClMode; > >>>> + > >>>> public: > >>>> > >>>> /// This constructor initializes the data members to match that > >>>> @@ -190,6 +193,11 @@ > >>>> return !isTargetDarwin()&& !isTargetWindows()&& > !isTargetCygMing(); > >>>> } > >>>> bool isTargetLinux() const { return TargetTriple.getOS() == > Triple::Linux; } > >>>> + bool isTargetNaCl() const { > >>>> + return TargetTriple.getOS() == Triple::NativeClient; > >>>> + } > >>>> + bool isTargetNaCl32() const { return isTargetNaCl()&& !is64Bit(); > } > >>>> + bool isTargetNaCl64() const { return isTargetNaCl()&& is64Bit(); } > >>>> > >>>> bool isTargetWindows() const { return TargetTriple.getOS() == > Triple::Win32; } > >>>> bool isTargetMingw() const { return TargetTriple.getOS() == > Triple::MinGW32; } > >>>> > >>>> > >>>> _______________________________________________ > >>>> llvm-commits mailing list > >>>> llvm-commits at cs.uiuc.edu > >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > >>> > >>> > >>> _______________________________________________ > >>> llvm-commits mailing list > >>> llvm-commits at cs.uiuc.edu > >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > >> > > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110927/203347d9/attachment.html From grosbach at apple.com Tue Sep 27 15:59:33 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 27 Sep 2011 20:59:33 -0000 Subject: [llvm-commits] [llvm] r140636 - in /llvm/trunk: include/llvm/CodeGen/MachineConstantPool.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/ARM/ARMConstantPoolValue.cpp lib/Target/ARM/ARMConstantPoolValue.h Message-ID: <20110927205933.483D62A6C12C@llvm.org> Author: grosbach Date: Tue Sep 27 15:59:33 2011 New Revision: 140636 URL: http://llvm.org/viewvc/llvm-project?rev=140636&view=rev Log: Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId(). Naming conventions consistency. No functional change. Modified: llvm/trunk/include/llvm/CodeGen/MachineConstantPool.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h Modified: llvm/trunk/include/llvm/CodeGen/MachineConstantPool.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineConstantPool.h?rev=140636&r1=140635&r2=140636&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineConstantPool.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineConstantPool.h Tue Sep 27 15:59:33 2011 @@ -54,7 +54,7 @@ virtual int getExistingMachineCPValue(MachineConstantPool *CP, unsigned Alignment) = 0; - virtual void AddSelectionDAGCSEId(FoldingSetNodeID &ID) = 0; + virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID) = 0; /// print - Implement operator<< virtual void print(raw_ostream &O) const = 0; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=140636&r1=140635&r2=140636&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Sep 27 15:59:33 2011 @@ -403,7 +403,7 @@ ID.AddInteger(CP->getAlignment()); ID.AddInteger(CP->getOffset()); if (CP->isMachineConstantPoolEntry()) - CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); + CP->getMachineCPVal()->addSelectionDAGCSEId(ID); else ID.AddPointer(CP->getConstVal()); ID.AddInteger(CP->getTargetFlags()); @@ -1154,7 +1154,7 @@ AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); ID.AddInteger(Alignment); ID.AddInteger(Offset); - C->AddSelectionDAGCSEId(ID); + C->addSelectionDAGCSEId(ID); ID.AddInteger(TargetFlags); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) Modified: llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp?rev=140636&r1=140635&r2=140636&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp Tue Sep 27 15:59:33 2011 @@ -87,7 +87,7 @@ } void -ARMConstantPoolValue::AddSelectionDAGCSEId(FoldingSetNodeID &ID) { +ARMConstantPoolValue::addSelectionDAGCSEId(FoldingSetNodeID &ID) { ID.AddPointer(CVal); ID.AddPointer(S); ID.AddInteger(LabelId); Modified: llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h?rev=140636&r1=140635&r2=140636&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h Tue Sep 27 15:59:33 2011 @@ -101,7 +101,7 @@ virtual int getExistingMachineCPValue(MachineConstantPool *CP, unsigned Alignment); - virtual void AddSelectionDAGCSEId(FoldingSetNodeID &ID); + virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID); /// hasSameValue - Return true if this ARM constpool value /// can share the same constantpool entry as another ARM constpool value. From dpatel at apple.com Tue Sep 27 16:25:14 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 27 Sep 2011 14:25:14 -0700 Subject: [llvm-commits] [patch] ThreeStageLoopUnroll In-Reply-To: References: Message-ID: <36610B20-AAAC-4A37-88EF-DAE333CFA740@apple.com> Daniel, On Sep 23, 2011, at 11:07 AM, Daniel Nic?cio wrote: > This Patch improves the LoopUnroll Pass. > > First it identifies special cases where a three stage loop unrolling is desired. For example, if a loop updates an unaligned region of a bit array, it is desired that this pass generates a first loop that updates just some bits on the first word, a main loop that updates all intermediate words and a final loop that updates just some bits on the last word. This way, the main loop can be made canonical and further optimized. > > After splitting the loop into the three stage loops, it unrolls the main loop by a factor of 32, 64 or any other number that can generate further optimization opportunities. Hopefully, those optimizations will collapse the unrolled loop into a more efficient and smaller loop. > > This first version simply identifies loops that contain a "lshr X, 5" or "lshr X, 6" instruction and the result of that instruction is used to index an array. > > The heuristic to find loop candidates for this special unrolling can (and must) be further improved, since this special three stage unrolling is going to be very useful for vectorization passes and can also be used in other cases, like a memcopy and so on. > > The very purpose of this first patch is to get a feedback from the community on the idea of the three stage loop unrolling. Comments and Critics are very welcome. 1) Please don't update loop structure to keep track of a transformation specific data. It is best to let transformation pass handle isThreeStageUnrollCandidate (), getToBeThreeStageUnrolled() and setToBeThreeStageUnrolled() etc... 2) General llvm convention is to avoid + bool candidate = L->isThreeStageUnrollCandidate(L, LI); + if(candidate) { ?. and do + if (bool candidate = ? ) { + } if candidate is not used outside "if". 3) + static IRBuilder<> Builder(context); Please avoid using static variables. 4) I have not looked at your implementation in detail, but I'd refactor it properly instead of extending llvm::UnrollLoop() directly. Are you able to measure performance improvements using this transformation ? - Devang > The next step is going to make the code much more generic. > > Thanks > > Daniel Nicacio > > ps: I still have to come up with a simpler test case, it is in my TODO list ;) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dblaikie at gmail.com Tue Sep 27 16:48:21 2011 From: dblaikie at gmail.com (David Blaikie) Date: Tue, 27 Sep 2011 14:48:21 -0700 Subject: [llvm-commits] [patch] ThreeStageLoopUnroll In-Reply-To: <36610B20-AAAC-4A37-88EF-DAE333CFA740@apple.com> References: <36610B20-AAAC-4A37-88EF-DAE333CFA740@apple.com> Message-ID: > > 2) General llvm convention is to avoid > > + bool candidate = L->isThreeStageUnrollCandidate(L, LI); > + if(candidate) { > ?. > > and do > > + if (bool candidate = ? ) { > + } > > if candidate is not used outside "if". > At that point you might as well just write: if (L->isThreeStageUnrollCandidate(L, LI)) { } -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110927/dcc54e4f/attachment.html From dpatel at apple.com Tue Sep 27 16:55:19 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 27 Sep 2011 14:55:19 -0700 Subject: [llvm-commits] [patch] ThreeStageLoopUnroll In-Reply-To: References: <36610B20-AAAC-4A37-88EF-DAE333CFA740@apple.com> Message-ID: <72EBDCAC-85C1-48EC-91FA-500022E126F1@apple.com> On Sep 27, 2011, at 2:48 PM, David Blaikie wrote: > 2) General llvm convention is to avoid > > + bool candidate = L->isThreeStageUnrollCandidate(L, LI); > + if(candidate) { > ?. > > and do > > + if (bool candidate = ? ) { > + } > > if candidate is not used outside "if". > > At that point you might as well just write: > > if (L->isThreeStageUnrollCandidate(L, LI)) { > } Yes, if candidate is not used inside "if". - Devang -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110927/4c216873/attachment.html From geek4civic at gmail.com Tue Sep 27 16:54:50 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 27 Sep 2011 21:54:50 -0000 Subject: [llvm-commits] [llvm] r140641 - /llvm/trunk/test/CMakeLists.txt Message-ID: <20110927215450.57F7E2A6C12C@llvm.org> Author: chapuni Date: Tue Sep 27 16:54:50 2011 New Revision: 140641 URL: http://llvm.org/viewvc/llvm-project?rev=140641&view=rev Log: test/CMakeLists.txt: Depend on llvm-objdump. "make check" is expected to resolve test-dependent targets on CMake build. Modified: llvm/trunk/test/CMakeLists.txt Modified: llvm/trunk/test/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CMakeLists.txt?rev=140641&r1=140640&r2=140641&view=diff ============================================================================== --- llvm/trunk/test/CMakeLists.txt (original) +++ llvm/trunk/test/CMakeLists.txt Tue Sep 27 16:54:50 2011 @@ -114,7 +114,7 @@ UnitTests BugpointPasses LLVMHello llc lli llvm-ar llvm-as llvm-dis llvm-extract - llvm-ld llvm-link llvm-mc llvm-nm macho-dump opt + llvm-ld llvm-link llvm-mc llvm-nm llvm-objdump macho-dump opt FileCheck count not) set_target_properties(check.deps PROPERTIES FOLDER "Tests") From zwarich at apple.com Tue Sep 27 16:59:16 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Tue, 27 Sep 2011 21:59:16 -0000 Subject: [llvm-commits] [llvm] r140643 - /llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp Message-ID: <20110927215916.32C022A6C12C@llvm.org> Author: zwarich Date: Tue Sep 27 16:59:16 2011 New Revision: 140643 URL: http://llvm.org/viewvc/llvm-project?rev=140643&view=rev Log: Remove an invalid assert that is really just asserting when the scheduler emits a suboptimal schedule. Modified: llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp Modified: llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp?rev=140643&r1=140642&r2=140643&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp (original) +++ llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp Tue Sep 27 16:59:16 2011 @@ -213,7 +213,6 @@ freeUnits = freeUnit & (freeUnit - 1); } while (freeUnits); - assert(freeUnit && "No function unit available!"); if (IS->getReservationKind() == InstrStage::Required) RequiredScoreboard[cycle + i] |= freeUnit; else From grosbach at apple.com Tue Sep 27 17:02:40 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 27 Sep 2011 15:02:40 -0700 Subject: [llvm-commits] [llvm] r140634 - in /llvm/trunk: lib/Analysis/ lib/Transforms/IPO/ lib/Transforms/InstCombine/ lib/Transforms/Scalar/ lib/Transforms/Utils/ test/Transforms/IndVarSimplify/ test/Transforms/InstCombine/ test/Transforms/LoopIdiom/ test/Transforms/LoopStrengthReduce/ test/Transforms/ScalarRepl/ test/Transforms/SimplifyLibCalls/ In-Reply-To: <20110927203919.B8EF02A6C12C@llvm.org> References: <20110927203919.B8EF02A6C12C@llvm.org> Message-ID: Heh. That's a really nice cleanup. -j On Sep 27, 2011, at 1:39 PM, Benjamin Kramer wrote: > Author: d0k > Date: Tue Sep 27 15:39:19 2011 > New Revision: 140634 > > URL: http://llvm.org/viewvc/llvm-project?rev=140634&view=rev > Log: > Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit. > > If someone prefers %tmp42 to %42, run instnamer. > > Modified: > llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp > llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp > llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp > llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp > llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp > llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp > llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp > llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp > llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp > llvm/trunk/lib/Transforms/Scalar/GVN.cpp > llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp > llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp > llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp > llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp > llvm/trunk/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll > llvm/trunk/test/Transforms/InstCombine/call.ll > llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll > llvm/trunk/test/Transforms/InstCombine/vector-casts.ll > llvm/trunk/test/Transforms/LoopIdiom/basic.ll > llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll > llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll > llvm/trunk/test/Transforms/SimplifyLibCalls/pow-to-sqrt.ll > > Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) > +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Tue Sep 27 15:39:19 2011 > @@ -163,7 +163,7 @@ > } > > // If we haven't found this binop, insert it. > - Instruction *BO = cast(Builder.CreateBinOp(Opcode, LHS, RHS, "tmp")); > + Instruction *BO = cast(Builder.CreateBinOp(Opcode, LHS, RHS)); > BO->setDebugLoc(SaveInsertPt->getDebugLoc()); > rememberInstruction(BO); > > @@ -980,7 +980,7 @@ > const SCEV *const StepArray[1] = { SE.getSCEV(StepV) }; > IncV = expandAddToGEP(StepArray, StepArray+1, GEPPtrTy, IntTy, PN); > if (IncV->getType() != PN->getType()) { > - IncV = Builder.CreateBitCast(IncV, PN->getType(), "tmp"); > + IncV = Builder.CreateBitCast(IncV, PN->getType()); > rememberInstruction(IncV); > } > } else { > @@ -1222,7 +1222,7 @@ > Type *Ty = SE.getEffectiveSCEVType(S->getType()); > Value *V = expandCodeFor(S->getOperand(), > SE.getEffectiveSCEVType(S->getOperand()->getType())); > - Value *I = Builder.CreateTrunc(V, Ty, "tmp"); > + Value *I = Builder.CreateTrunc(V, Ty); > rememberInstruction(I); > return I; > } > @@ -1231,7 +1231,7 @@ > Type *Ty = SE.getEffectiveSCEVType(S->getType()); > Value *V = expandCodeFor(S->getOperand(), > SE.getEffectiveSCEVType(S->getOperand()->getType())); > - Value *I = Builder.CreateZExt(V, Ty, "tmp"); > + Value *I = Builder.CreateZExt(V, Ty); > rememberInstruction(I); > return I; > } > @@ -1240,7 +1240,7 @@ > Type *Ty = SE.getEffectiveSCEVType(S->getType()); > Value *V = expandCodeFor(S->getOperand(), > SE.getEffectiveSCEVType(S->getOperand()->getType())); > - Value *I = Builder.CreateSExt(V, Ty, "tmp"); > + Value *I = Builder.CreateSExt(V, Ty); > rememberInstruction(I); > return I; > } > @@ -1256,7 +1256,7 @@ > LHS = InsertNoopCastOfTo(LHS, Ty); > } > Value *RHS = expandCodeFor(S->getOperand(i), Ty); > - Value *ICmp = Builder.CreateICmpSGT(LHS, RHS, "tmp"); > + Value *ICmp = Builder.CreateICmpSGT(LHS, RHS); > rememberInstruction(ICmp); > Value *Sel = Builder.CreateSelect(ICmp, LHS, RHS, "smax"); > rememberInstruction(Sel); > @@ -1280,7 +1280,7 @@ > LHS = InsertNoopCastOfTo(LHS, Ty); > } > Value *RHS = expandCodeFor(S->getOperand(i), Ty); > - Value *ICmp = Builder.CreateICmpUGT(LHS, RHS, "tmp"); > + Value *ICmp = Builder.CreateICmpUGT(LHS, RHS); > rememberInstruction(ICmp); > Value *Sel = Builder.CreateSelect(ICmp, LHS, RHS, "umax"); > rememberInstruction(Sel); > > Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original) > +++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Tue Sep 27 15:39:19 2011 > @@ -1376,8 +1376,7 @@ > for (unsigned i = 0, e = FieldGlobals.size(); i != e; ++i) { > Value *GVVal = new LoadInst(FieldGlobals[i], "tmp", NullPtrBlock); > Value *Cmp = new ICmpInst(*NullPtrBlock, ICmpInst::ICMP_NE, GVVal, > - Constant::getNullValue(GVVal->getType()), > - "tmp"); > + Constant::getNullValue(GVVal->getType())); > BasicBlock *FreeBlock = BasicBlock::Create(Cmp->getContext(), "free_it", > OrigBB->getParent()); > BasicBlock *NextBlock = BasicBlock::Create(Cmp->getContext(), "next", > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Tue Sep 27 15:39:19 2011 > @@ -1197,7 +1197,7 @@ > // an endless loop. By checking that A is non-constant we ensure that > // we will never get to the loop. > if (A == tmpOp0 && !isa(A)) // A&(A^B) -> A & ~B > - return BinaryOperator::CreateAnd(A, Builder->CreateNot(B, "tmp")); > + return BinaryOperator::CreateAnd(A, Builder->CreateNot(B)); > } > } > > @@ -2228,14 +2228,14 @@ > if (A == Op1) // (B|A)^B == (A|B)^B > std::swap(A, B); > if (B == Op1) // (A|B)^B == A & ~B > - return BinaryOperator::CreateAnd(A, Builder->CreateNot(Op1, "tmp")); > + return BinaryOperator::CreateAnd(A, Builder->CreateNot(Op1)); > } else if (match(Op0I, m_And(m_Value(A), m_Value(B))) && > Op0I->hasOneUse()){ > if (A == Op1) // (A&B)^A -> (B&A)^A > std::swap(A, B); > if (B == Op1 && // (B&A)^A == ~B & A > !isa(Op1)) { // Canonical form is (B&C)^C > - return BinaryOperator::CreateAnd(Builder->CreateNot(A, "tmp"), Op1); > + return BinaryOperator::CreateAnd(Builder->CreateNot(A), Op1); > } > } > } > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Tue Sep 27 15:39:19 2011 > @@ -654,15 +654,13 @@ > > if (ExtractedElts[Idx] == 0) { > ExtractedElts[Idx] = > - Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1, > - ConstantInt::get(Type::getInt32Ty(II->getContext()), > - Idx&15, false), "tmp"); > + Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1, > + Builder->getInt32(Idx&15)); > } > > // Insert this value into the result vector. > Result = Builder->CreateInsertElement(Result, ExtractedElts[Idx], > - ConstantInt::get(Type::getInt32Ty(II->getContext()), > - i, false), "tmp"); > + Builder->getInt32(i)); > } > return CastInst::Create(Instruction::BitCast, Result, CI.getType()); > } > @@ -1143,7 +1141,7 @@ > } else { > Instruction::CastOps opcode = CastInst::getCastOpcode(*AI, > false, ParamTy, false); > - Args.push_back(Builder->CreateCast(opcode, *AI, ParamTy, "tmp")); > + Args.push_back(Builder->CreateCast(opcode, *AI, ParamTy)); > } > > // Add any parameter attributes. > @@ -1169,7 +1167,7 @@ > // Must promote to pass through va_arg area! > Instruction::CastOps opcode = > CastInst::getCastOpcode(*AI, false, PTy, false); > - Args.push_back(Builder->CreateCast(opcode, *AI, PTy, "tmp")); > + Args.push_back(Builder->CreateCast(opcode, *AI, PTy)); > } else { > Args.push_back(*AI); > } > @@ -1213,7 +1211,7 @@ > if (!NV->getType()->isVoidTy()) { > Instruction::CastOps opcode = > CastInst::getCastOpcode(NC, false, OldRetTy, false); > - NV = NC = CastInst::Create(opcode, NC, OldRetTy, "tmp"); > + NV = NC = CastInst::Create(opcode, NC, OldRetTy); > NC->setDebugLoc(Caller->getDebugLoc()); > > // If this is an invoke instruction, we should insert it after the first > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp Tue Sep 27 15:39:19 2011 > @@ -122,13 +122,13 @@ > } else { > Amt = ConstantInt::get(AI.getArraySize()->getType(), Scale); > // Insert before the alloca, not before the cast. > - Amt = AllocaBuilder.CreateMul(Amt, NumElements, "tmp"); > + Amt = AllocaBuilder.CreateMul(Amt, NumElements); > } > > if (uint64_t Offset = (AllocElTySize*ArrayOffset)/CastElTySize) { > Value *Off = ConstantInt::get(AI.getArraySize()->getType(), > Offset, true); > - Amt = AllocaBuilder.CreateAdd(Amt, Off, "tmp"); > + Amt = AllocaBuilder.CreateAdd(Amt, Off); > } > > AllocaInst *New = AllocaBuilder.CreateAlloca(CastElTy, Amt); > @@ -457,7 +457,7 @@ > // Canonicalize trunc x to i1 -> (icmp ne (and x, 1), 0), likewise for vector. > if (DestTy->getScalarSizeInBits() == 1) { > Constant *One = ConstantInt::get(Src->getType(), 1); > - Src = Builder->CreateAnd(Src, One, "tmp"); > + Src = Builder->CreateAnd(Src, One); > Value *Zero = Constant::getNullValue(Src->getType()); > return new ICmpInst(ICmpInst::ICMP_NE, Src, Zero); > } > @@ -519,7 +519,7 @@ > In->getType()->getScalarSizeInBits()-1); > In = Builder->CreateLShr(In, Sh, In->getName()+".lobit"); > if (In->getType() != CI.getType()) > - In = Builder->CreateIntCast(In, CI.getType(), false/*ZExt*/, "tmp"); > + In = Builder->CreateIntCast(In, CI.getType(), false/*ZExt*/); > > if (ICI->getPredicate() == ICmpInst::ICMP_SGT) { > Constant *One = ConstantInt::get(In->getType(), 1); > @@ -573,7 +573,7 @@ > > if ((Op1CV != 0) == isNE) { // Toggle the low bit. > Constant *One = ConstantInt::get(In->getType(), 1); > - In = Builder->CreateXor(In, One, "tmp"); > + In = Builder->CreateXor(In, One); > } > > if (CI.getType() == In->getType()) > @@ -821,7 +821,7 @@ > AndValue)); > } > if (SrcSize > DstSize) { > - Value *Trunc = Builder->CreateTrunc(A, CI.getType(), "tmp"); > + Value *Trunc = Builder->CreateTrunc(A, CI.getType()); > APInt AndValue(APInt::getLowBitsSet(DstSize, MidSize)); > return BinaryOperator::CreateAnd(Trunc, > ConstantInt::get(Trunc->getType(), > @@ -868,7 +868,7 @@ > Value *TI0 = TI->getOperand(0); > if (TI0->getType() == CI.getType()) { > Constant *ZC = ConstantExpr::getZExt(C, CI.getType()); > - Value *NewAnd = Builder->CreateAnd(TI0, ZC, "tmp"); > + Value *NewAnd = Builder->CreateAnd(TI0, ZC); > return BinaryOperator::CreateXor(NewAnd, ZC); > } > } > @@ -901,7 +901,7 @@ > Op0->getType()->getScalarSizeInBits()-1); > Value *In = Builder->CreateAShr(Op0, Sh, Op0->getName()+".lobit"); > if (In->getType() != CI.getType()) > - In = Builder->CreateIntCast(In, CI.getType(), true/*SExt*/, "tmp"); > + In = Builder->CreateIntCast(In, CI.getType(), true/*SExt*/); > > if (Pred == ICmpInst::ICMP_SGT) > In = Builder->CreateNot(In, In->getName()+".not"); > @@ -1307,13 +1307,13 @@ > if (CI.getOperand(0)->getType()->getScalarSizeInBits() > > TD->getPointerSizeInBits()) { > Value *P = Builder->CreateTrunc(CI.getOperand(0), > - TD->getIntPtrType(CI.getContext()), "tmp"); > + TD->getIntPtrType(CI.getContext())); > return new IntToPtrInst(P, CI.getType()); > } > if (CI.getOperand(0)->getType()->getScalarSizeInBits() < > TD->getPointerSizeInBits()) { > Value *P = Builder->CreateZExt(CI.getOperand(0), > - TD->getIntPtrType(CI.getContext()), "tmp"); > + TD->getIntPtrType(CI.getContext())); > return new IntToPtrInst(P, CI.getType()); > } > } > @@ -1382,14 +1382,12 @@ > if (TD) { > if (CI.getType()->getScalarSizeInBits() < TD->getPointerSizeInBits()) { > Value *P = Builder->CreatePtrToInt(CI.getOperand(0), > - TD->getIntPtrType(CI.getContext()), > - "tmp"); > + TD->getIntPtrType(CI.getContext())); > return new TruncInst(P, CI.getType()); > } > if (CI.getType()->getScalarSizeInBits() > TD->getPointerSizeInBits()) { > Value *P = Builder->CreatePtrToInt(CI.getOperand(0), > - TD->getIntPtrType(CI.getContext()), > - "tmp"); > + TD->getIntPtrType(CI.getContext())); > return new ZExtInst(P, CI.getType()); > } > } > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Tue Sep 27 15:39:19 2011 > @@ -1186,10 +1186,10 @@ > // Compute C << Y. > Value *NS; > if (Shift->getOpcode() == Instruction::LShr) { > - NS = Builder->CreateShl(AndCST, Shift->getOperand(1), "tmp"); > + NS = Builder->CreateShl(AndCST, Shift->getOperand(1)); > } else { > // Insert a logical shift. > - NS = Builder->CreateLShr(AndCST, Shift->getOperand(1), "tmp"); > + NS = Builder->CreateLShr(AndCST, Shift->getOperand(1)); > } > > // Compute X & (C << Y). > @@ -2484,7 +2484,7 @@ > match(D, m_ConstantInt(C2)) && Op1->hasOneUse()) { > Constant *NC = ConstantInt::get(I.getContext(), > C1->getValue() ^ C2->getValue()); > - Value *Xor = Builder->CreateXor(C, NC, "tmp"); > + Value *Xor = Builder->CreateXor(C, NC); > return new ICmpInst(I.getPredicate(), A, Xor); > } > > @@ -2520,8 +2520,8 @@ > } > > if (X) { // Build (X^Y) & Z > - Op1 = Builder->CreateXor(X, Y, "tmp"); > - Op1 = Builder->CreateAnd(Op1, Z, "tmp"); > + Op1 = Builder->CreateXor(X, Y); > + Op1 = Builder->CreateAnd(Op1, Z); > I.setOperand(0, Op1); > I.setOperand(1, Constant::getNullValue(Op1->getType())); > return &I; > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Tue Sep 27 15:39:19 2011 > @@ -38,7 +38,7 @@ > m_Value(B))) && > // The "1" can be any value known to be a power of 2. > isPowerOfTwo(PowerOf2, IC.getTargetData())) { > - A = IC.Builder->CreateSub(A, B, "tmp"); > + A = IC.Builder->CreateSub(A, B); > return IC.Builder->CreateShl(PowerOf2, A); > } > > @@ -131,7 +131,7 @@ > { Value *X; ConstantInt *C1; > if (Op0->hasOneUse() && > match(Op0, m_Add(m_Value(X), m_ConstantInt(C1)))) { > - Value *Add = Builder->CreateMul(X, CI, "tmp"); > + Value *Add = Builder->CreateMul(X, CI); > return BinaryOperator::CreateAdd(Add, Builder->CreateMul(C1, CI)); > } > } > @@ -244,7 +244,7 @@ > > if (BoolCast) { > Value *V = Builder->CreateSub(Constant::getNullValue(I.getType()), > - BoolCast, "tmp"); > + BoolCast); > return BinaryOperator::CreateAnd(V, OtherOp); > } > } > @@ -466,8 +466,7 @@ > { const APInt *CI; Value *N; > if (match(Op1, m_Shl(m_Power2(CI), m_Value(N)))) { > if (*CI != 1) > - N = Builder->CreateAdd(N, ConstantInt::get(I.getType(), CI->logBase2()), > - "tmp"); > + N = Builder->CreateAdd(N, ConstantInt::get(I.getType(),CI->logBase2())); > if (I.isExact()) > return BinaryOperator::CreateExactLShr(Op0, N); > return BinaryOperator::CreateLShr(Op0, N); > @@ -630,7 +629,7 @@ > // Turn A % (C << N), where C is 2^k, into A & ((C << N)-1) > if (match(Op1, m_Shl(m_Power2(), m_Value()))) { > Constant *N1 = Constant::getAllOnesValue(I.getType()); > - Value *Add = Builder->CreateAdd(Op1, N1, "tmp"); > + Value *Add = Builder->CreateAdd(Op1, N1); > return BinaryOperator::CreateAnd(Op0, Add); > } > > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Tue Sep 27 15:39:19 2011 > @@ -325,8 +325,7 @@ > if ((RHSKnownOne & LHSKnownOne) == RHSKnownOne) { > Constant *AndC = Constant::getIntegerValue(VTy, > ~RHSKnownOne & DemandedMask); > - Instruction *And = > - BinaryOperator::CreateAnd(I->getOperand(0), AndC, "tmp"); > + Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC); > return InsertNewInstWith(And, *I); > } > } > @@ -351,14 +350,12 @@ > > Constant *AndC = > ConstantInt::get(I->getType(), NewMask & AndRHS->getValue()); > - Instruction *NewAnd = > - BinaryOperator::CreateAnd(I->getOperand(0), AndC, "tmp"); > + Instruction *NewAnd = BinaryOperator::CreateAnd(I->getOperand(0), AndC); > InsertNewInstWith(NewAnd, *I); > > Constant *XorC = > ConstantInt::get(I->getType(), NewMask & XorRHS->getValue()); > - Instruction *NewXor = > - BinaryOperator::CreateXor(NewAnd, XorC, "tmp"); > + Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC); > return InsertNewInstWith(NewXor, *I); > } > > > Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Tue Sep 27 15:39:19 2011 > @@ -822,7 +822,7 @@ > DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrMode << " for " > << *MemoryInst); > if (SunkAddr->getType() != Addr->getType()) > - SunkAddr = Builder.CreateBitCast(SunkAddr, Addr->getType(), "tmp"); > + SunkAddr = Builder.CreateBitCast(SunkAddr, Addr->getType()); > } else { > DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for " > << *MemoryInst); > > Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue Sep 27 15:39:19 2011 > @@ -946,10 +946,9 @@ > // Compute which bits of the stored value are being used by the load. Convert > // to an integer type to start with. > if (SrcVal->getType()->isPointerTy()) > - SrcVal = Builder.CreatePtrToInt(SrcVal, TD.getIntPtrType(Ctx), "tmp"); > + SrcVal = Builder.CreatePtrToInt(SrcVal, TD.getIntPtrType(Ctx)); > if (!SrcVal->getType()->isIntegerTy()) > - SrcVal = Builder.CreateBitCast(SrcVal, IntegerType::get(Ctx, StoreSize*8), > - "tmp"); > + SrcVal = Builder.CreateBitCast(SrcVal, IntegerType::get(Ctx, StoreSize*8)); > > // Shift the bits to the least significant depending on endianness. > unsigned ShiftAmt; > @@ -959,11 +958,10 @@ > ShiftAmt = (StoreSize-LoadSize-Offset)*8; > > if (ShiftAmt) > - SrcVal = Builder.CreateLShr(SrcVal, ShiftAmt, "tmp"); > + SrcVal = Builder.CreateLShr(SrcVal, ShiftAmt); > > if (LoadSize != StoreSize) > - SrcVal = Builder.CreateTrunc(SrcVal, IntegerType::get(Ctx, LoadSize*8), > - "tmp"); > + SrcVal = Builder.CreateTrunc(SrcVal, IntegerType::get(Ctx, LoadSize*8)); > > return CoerceAvailableValueToLoadType(SrcVal, LoadTy, InsertPt, TD); > } > > Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Tue Sep 27 15:39:19 2011 > @@ -492,7 +492,7 @@ > Value *BranchVal = LIC; > if (!isa(Val) || > Val->getType() != Type::getInt1Ty(LIC->getContext())) > - BranchVal = new ICmpInst(InsertPt, ICmpInst::ICMP_EQ, LIC, Val, "tmp"); > + BranchVal = new ICmpInst(InsertPt, ICmpInst::ICMP_EQ, LIC, Val); > else if (Val != ConstantInt::getTrue(Val->getContext())) > // We want to enter the new loop when the condition is true. > std::swap(TrueDest, FalseDest); > > Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Sep 27 15:39:19 2011 > @@ -617,7 +617,7 @@ > > if (LoadInst *LI = dyn_cast(User)) { > // The load is a bit extract from NewAI shifted right by Offset bits. > - Value *LoadedVal = Builder.CreateLoad(NewAI, "tmp"); > + Value *LoadedVal = Builder.CreateLoad(NewAI); > Value *NewLoadVal > = ConvertScalar_ExtractValue(LoadedVal, LI->getType(), Offset, Builder); > LI->replaceAllUsesWith(NewLoadVal); > @@ -822,7 +822,7 @@ > // a shuffle vector. > if (FromType->getPrimitiveSizeInBits() == > ToType->getPrimitiveSizeInBits()) > - return Builder.CreateBitCast(FromVal, ToType, "tmp"); > + return Builder.CreateBitCast(FromVal, ToType); > else > return CreateShuffleVectorCast(FromVal, ToType, Builder); > } > @@ -838,14 +838,14 @@ > LLVMContext &Context = FromVal->getContext(); > Type *CastTy = VectorType::get(CastElementTy, > NumCastVectorElements); > - Value *Cast = Builder.CreateBitCast(FromVal, CastTy, "tmp"); > + Value *Cast = Builder.CreateBitCast(FromVal, CastTy); > > unsigned EltSize = TD.getTypeAllocSizeInBits(CastElementTy); > unsigned Elt = Offset/EltSize; > assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); > Value *Extract = Builder.CreateExtractElement(Cast, ConstantInt::get( > - Type::getInt32Ty(Context), Elt), "tmp"); > - return Builder.CreateBitCast(Extract, ToType, "tmp"); > + Type::getInt32Ty(Context), Elt)); > + return Builder.CreateBitCast(Extract, ToType); > } > > // Otherwise it must be an element access. > @@ -856,10 +856,9 @@ > assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); > } > // Return the element extracted out of it. > - Value *V = Builder.CreateExtractElement(FromVal, ConstantInt::get( > - Type::getInt32Ty(FromVal->getContext()), Elt), "tmp"); > + Value *V = Builder.CreateExtractElement(FromVal, Builder.getInt32(Elt)); > if (V->getType() != ToType) > - V = Builder.CreateBitCast(V, ToType, "tmp"); > + V = Builder.CreateBitCast(V, ToType); > return V; > } > > @@ -872,7 +871,7 @@ > Value *Elt = ConvertScalar_ExtractValue(FromVal, ST->getElementType(i), > Offset+Layout.getElementOffsetInBits(i), > Builder); > - Res = Builder.CreateInsertValue(Res, Elt, i, "tmp"); > + Res = Builder.CreateInsertValue(Res, Elt, i); > } > return Res; > } > @@ -883,7 +882,7 @@ > for (unsigned i = 0, e = AT->getNumElements(); i != e; ++i) { > Value *Elt = ConvertScalar_ExtractValue(FromVal, AT->getElementType(), > Offset+i*EltSize, Builder); > - Res = Builder.CreateInsertValue(Res, Elt, i, "tmp"); > + Res = Builder.CreateInsertValue(Res, Elt, i); > } > return Res; > } > @@ -909,33 +908,31 @@ > // only some bits are used. > if (ShAmt > 0 && (unsigned)ShAmt < NTy->getBitWidth()) > FromVal = Builder.CreateLShr(FromVal, > - ConstantInt::get(FromVal->getType(), > - ShAmt), "tmp"); > + ConstantInt::get(FromVal->getType(), ShAmt)); > else if (ShAmt < 0 && (unsigned)-ShAmt < NTy->getBitWidth()) > FromVal = Builder.CreateShl(FromVal, > - ConstantInt::get(FromVal->getType(), > - -ShAmt), "tmp"); > + ConstantInt::get(FromVal->getType(), -ShAmt)); > > // Finally, unconditionally truncate the integer to the right width. > unsigned LIBitWidth = TD.getTypeSizeInBits(ToType); > if (LIBitWidth < NTy->getBitWidth()) > FromVal = > Builder.CreateTrunc(FromVal, IntegerType::get(FromVal->getContext(), > - LIBitWidth), "tmp"); > + LIBitWidth)); > else if (LIBitWidth > NTy->getBitWidth()) > FromVal = > Builder.CreateZExt(FromVal, IntegerType::get(FromVal->getContext(), > - LIBitWidth), "tmp"); > + LIBitWidth)); > > // If the result is an integer, this is a trunc or bitcast. > if (ToType->isIntegerTy()) { > // Should be done. > } else if (ToType->isFloatingPointTy() || ToType->isVectorTy()) { > // Just do a bitcast, we know the sizes match up. > - FromVal = Builder.CreateBitCast(FromVal, ToType, "tmp"); > + FromVal = Builder.CreateBitCast(FromVal, ToType); > } else { > // Otherwise must be a pointer. > - FromVal = Builder.CreateIntToPtr(FromVal, ToType, "tmp"); > + FromVal = Builder.CreateIntToPtr(FromVal, ToType); > } > assert(FromVal->getType() == ToType && "Didn't convert right?"); > return FromVal; > @@ -971,7 +968,7 @@ > // a shuffle vector. > if (VTy->getPrimitiveSizeInBits() == > SV->getType()->getPrimitiveSizeInBits()) > - return Builder.CreateBitCast(SV, AllocaType, "tmp"); > + return Builder.CreateBitCast(SV, AllocaType); > else > return CreateShuffleVectorCast(SV, VTy, Builder); > } > @@ -984,36 +981,31 @@ > ValSize); > unsigned NumCastVectorElements = VecSize / ValSize; > > - LLVMContext &Context = SV->getContext(); > - Type *OldCastTy = VectorType::get(CastElementTy, > - NumCastVectorElements); > - Value *OldCast = Builder.CreateBitCast(Old, OldCastTy, "tmp"); > + Type *OldCastTy = VectorType::get(CastElementTy, NumCastVectorElements); > + Value *OldCast = Builder.CreateBitCast(Old, OldCastTy); > > - Value *SVCast = Builder.CreateBitCast(SV, CastElementTy, "tmp"); > + Value *SVCast = Builder.CreateBitCast(SV, CastElementTy); > > unsigned EltSize = TD.getTypeAllocSizeInBits(CastElementTy); > unsigned Elt = Offset/EltSize; > assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); > Value *Insert = > - Builder.CreateInsertElement(OldCast, SVCast, ConstantInt::get( > - Type::getInt32Ty(Context), Elt), "tmp"); > - return Builder.CreateBitCast(Insert, AllocaType, "tmp"); > + Builder.CreateInsertElement(OldCast, SVCast, Builder.getInt32(Elt)); > + return Builder.CreateBitCast(Insert, AllocaType); > } > > // Must be an element insertion. > assert(SV->getType() == VTy->getElementType()); > uint64_t EltSize = TD.getTypeAllocSizeInBits(VTy->getElementType()); > unsigned Elt = Offset/EltSize; > - return Builder.CreateInsertElement(Old, SV, > - ConstantInt::get(Type::getInt32Ty(SV->getContext()), Elt), > - "tmp"); > + return Builder.CreateInsertElement(Old, SV, Builder.getInt32(Elt)); > } > > // If SV is a first-class aggregate value, insert each value recursively. > if (StructType *ST = dyn_cast(SV->getType())) { > const StructLayout &Layout = *TD.getStructLayout(ST); > for (unsigned i = 0, e = ST->getNumElements(); i != e; ++i) { > - Value *Elt = Builder.CreateExtractValue(SV, i, "tmp"); > + Value *Elt = Builder.CreateExtractValue(SV, i); > Old = ConvertScalar_InsertValue(Elt, Old, > Offset+Layout.getElementOffsetInBits(i), > Builder); > @@ -1024,7 +1016,7 @@ > if (ArrayType *AT = dyn_cast(SV->getType())) { > uint64_t EltSize = TD.getTypeAllocSizeInBits(AT->getElementType()); > for (unsigned i = 0, e = AT->getNumElements(); i != e; ++i) { > - Value *Elt = Builder.CreateExtractValue(SV, i, "tmp"); > + Value *Elt = Builder.CreateExtractValue(SV, i); > Old = ConvertScalar_InsertValue(Elt, Old, Offset+i*EltSize, Builder); > } > return Old; > @@ -1037,20 +1029,19 @@ > unsigned SrcStoreWidth = TD.getTypeStoreSizeInBits(SV->getType()); > unsigned DestStoreWidth = TD.getTypeStoreSizeInBits(AllocaType); > if (SV->getType()->isFloatingPointTy() || SV->getType()->isVectorTy()) > - SV = Builder.CreateBitCast(SV, > - IntegerType::get(SV->getContext(),SrcWidth), "tmp"); > + SV = Builder.CreateBitCast(SV, IntegerType::get(SV->getContext(),SrcWidth)); > else if (SV->getType()->isPointerTy()) > - SV = Builder.CreatePtrToInt(SV, TD.getIntPtrType(SV->getContext()), "tmp"); > + SV = Builder.CreatePtrToInt(SV, TD.getIntPtrType(SV->getContext())); > > // Zero extend or truncate the value if needed. > if (SV->getType() != AllocaType) { > if (SV->getType()->getPrimitiveSizeInBits() < > AllocaType->getPrimitiveSizeInBits()) > - SV = Builder.CreateZExt(SV, AllocaType, "tmp"); > + SV = Builder.CreateZExt(SV, AllocaType); > else { > // Truncation may be needed if storing more than the alloca can hold > // (undefined behavior). > - SV = Builder.CreateTrunc(SV, AllocaType, "tmp"); > + SV = Builder.CreateTrunc(SV, AllocaType); > SrcWidth = DestWidth; > SrcStoreWidth = DestStoreWidth; > } > @@ -1073,12 +1064,10 @@ > // only some bits in the structure are set. > APInt Mask(APInt::getLowBitsSet(DestWidth, SrcWidth)); > if (ShAmt > 0 && (unsigned)ShAmt < DestWidth) { > - SV = Builder.CreateShl(SV, ConstantInt::get(SV->getType(), > - ShAmt), "tmp"); > + SV = Builder.CreateShl(SV, ConstantInt::get(SV->getType(), ShAmt)); > Mask <<= ShAmt; > } else if (ShAmt < 0 && (unsigned)-ShAmt < DestWidth) { > - SV = Builder.CreateLShr(SV, ConstantInt::get(SV->getType(), > - -ShAmt), "tmp"); > + SV = Builder.CreateLShr(SV, ConstantInt::get(SV->getType(), -ShAmt)); > Mask = Mask.lshr(-ShAmt); > } > > > Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Tue Sep 27 15:39:19 2011 > @@ -874,8 +874,8 @@ > Callee->getAttributes()); > Value *FAbs = EmitUnaryFloatFnCall(Sqrt, "fabs", B, > Callee->getAttributes()); > - Value *FCmp = B.CreateFCmpOEQ(Op1, NegInf, "tmp"); > - Value *Sel = B.CreateSelect(FCmp, Inf, FAbs, "tmp"); > + Value *FCmp = B.CreateFCmpOEQ(Op1, NegInf); > + Value *Sel = B.CreateSelect(FCmp, Inf, FAbs); > return Sel; > } > > @@ -908,10 +908,10 @@ > Value *LdExpArg = 0; > if (SIToFPInst *OpC = dyn_cast(Op)) { > if (OpC->getOperand(0)->getType()->getPrimitiveSizeInBits() <= 32) > - LdExpArg = B.CreateSExt(OpC->getOperand(0), B.getInt32Ty(), "tmp"); > + LdExpArg = B.CreateSExt(OpC->getOperand(0), B.getInt32Ty()); > } else if (UIToFPInst *OpC = dyn_cast(Op)) { > if (OpC->getOperand(0)->getType()->getPrimitiveSizeInBits() < 32) > - LdExpArg = B.CreateZExt(OpC->getOperand(0), B.getInt32Ty(), "tmp"); > + LdExpArg = B.CreateZExt(OpC->getOperand(0), B.getInt32Ty()); > } > > if (LdExpArg) { > @@ -996,10 +996,10 @@ > Value *F = Intrinsic::getDeclaration(Callee->getParent(), > Intrinsic::cttz, ArgType); > Value *V = B.CreateCall(F, Op, "cttz"); > - V = B.CreateAdd(V, ConstantInt::get(V->getType(), 1), "tmp"); > - V = B.CreateIntCast(V, B.getInt32Ty(), false, "tmp"); > + V = B.CreateAdd(V, ConstantInt::get(V->getType(), 1)); > + V = B.CreateIntCast(V, B.getInt32Ty(), false); > > - Value *Cond = B.CreateICmpNE(Op, Constant::getNullValue(ArgType), "tmp"); > + Value *Cond = B.CreateICmpNE(Op, Constant::getNullValue(ArgType)); > return B.CreateSelect(Cond, V, B.getInt32(0)); > } > }; > > Modified: llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp Tue Sep 27 15:39:19 2011 > @@ -221,8 +221,7 @@ > return; > > ICmpInst *ICmp = new ICmpInst(Rem, ICmpInst::ICMP_EQ, > - Rem->getOperand(0), Rem->getOperand(1), > - "tmp"); > + Rem->getOperand(0), Rem->getOperand(1)); > SelectInst *Sel = > SelectInst::Create(ICmp, > ConstantInt::get(Rem->getType(), 0), > > Modified: llvm/trunk/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll (original) > +++ llvm/trunk/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll Tue Sep 27 15:39:19 2011 > @@ -1,5 +1,5 @@ > ; RUN: opt < %s -indvars -S -enable-iv-rewrite | FileCheck %s > -; CHECK: %p.2.ip.1 = getelementptr [3 x [3 x double]]* %p, i64 2, i64 %tmp, i64 1 > +; CHECK: %p.2.ip.1 = getelementptr [3 x [3 x double]]* %p, i64 2, i64 %0, i64 1 > target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128-n:32:64" > > ; Indvars shouldn't expand this to > > Modified: llvm/trunk/test/Transforms/InstCombine/call.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/call.ll?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/InstCombine/call.ll (original) > +++ llvm/trunk/test/Transforms/InstCombine/call.ll Tue Sep 27 15:39:19 2011 > @@ -9,8 +9,8 @@ > define void @test1(i32* %A) { > call void bitcast (void (i8*)* @test1a to void (i32*)*)( i32* %A ) > ret void > -; CHECK: %tmp = bitcast i32* %A to i8* > -; CHECK: call void @test1a(i8* %tmp) > +; CHECK: %1 = bitcast i32* %A to i8* > +; CHECK: call void @test1a(i8* %1) > ; CHECK: ret void > } > > @@ -24,8 +24,8 @@ > define i32 @test2(i32 %A) { > call void bitcast (void (i8)* @test2a to void (i32)*)( i32 %A ) > ret i32 %A > -; CHECK: %tmp = trunc i32 %A to i8 > -; CHECK: call void @test2a(i8 %tmp) > +; CHECK: %1 = trunc i32 %A to i8 > +; CHECK: call void @test2a(i8 %1) > ; CHECK: ret i32 %A > } > > @@ -38,8 +38,8 @@ > call void bitcast (void (i8, ...)* @test3a to void (i8, i8)*)( i8 %A, i8 %B > ) > ret void > -; CHECK: %tmp = zext i8 %B to i32 > -; CHECK: call void (i8, ...)* @test3a(i8 %A, i32 %tmp) > +; CHECK: %1 = zext i8 %B to i32 > +; CHECK: call void (i8, ...)* @test3a(i8 %A, i32 %1) > ; CHECK: ret void > } > > @@ -54,8 +54,8 @@ > %X = call i32 bitcast (i8 ()* @test4a to i32 ()*)( ) ; [#uses=1] > ret i32 %X > ; CHECK: %X = call i8 @test4a() > -; CHECK: %tmp = zext i8 %X to i32 > -; CHECK: ret i32 %tmp > +; CHECK: %1 = zext i8 %X to i32 > +; CHECK: ret i32 %1 > } > > > > Modified: llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll (original) > +++ llvm/trunk/test/Transforms/InstCombine/ptr-int-cast.ll Tue Sep 27 15:39:19 2011 > @@ -5,22 +5,22 @@ > entry: > ; CHECK: test1 > ; CHECK: ptrtoint i32* %x to i64 > - %tmp = ptrtoint i32* %x to i1 > - ret i1 %tmp > + %0 = ptrtoint i32* %x to i1 > + ret i1 %0 > } > > define i32* @test2(i128 %x) nounwind { > entry: > ; CHECK: test2 > -; CHECK: inttoptr i64 %tmp1 to i32* > - %tmp = inttoptr i128 %x to i32* > - ret i32* %tmp > +; CHECK: inttoptr i64 %0 to i32* > + %0 = inttoptr i128 %x to i32* > + ret i32* %0 > } > > ; PR3574 > ; CHECK: f0 > -; CHECK: %tmp = zext i32 %a0 to i64 > -; CHECK: ret i64 %tmp > +; CHECK: %1 = zext i32 %a0 to i64 > +; CHECK: ret i64 %1 > define i64 @f0(i32 %a0) nounwind { > %t0 = inttoptr i32 %a0 to i8* > %t1 = ptrtoint i8* %t0 to i64 > > Modified: llvm/trunk/test/Transforms/InstCombine/vector-casts.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vector-casts.ll?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/InstCombine/vector-casts.ll (original) > +++ llvm/trunk/test/Transforms/InstCombine/vector-casts.ll Tue Sep 27 15:39:19 2011 > @@ -7,7 +7,7 @@ > > ; CHECK: @test1 > ; CHECK: and <2 x i64> %a, > -; CHECK: icmp ne <2 x i64> %tmp, zeroinitializer > +; CHECK: icmp ne <2 x i64> %1, zeroinitializer > } > > ; The ashr turns into an lshr. > > Modified: llvm/trunk/test/Transforms/LoopIdiom/basic.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopIdiom/basic.ll?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/LoopIdiom/basic.ll (original) > +++ llvm/trunk/test/Transforms/LoopIdiom/basic.ll Tue Sep 27 15:39:19 2011 > @@ -62,8 +62,8 @@ > ret void > ; CHECK: @test2 > ; CHECK: br i1 %cmp10, > -; CHECK: %tmp = mul i64 %Size, 4 > -; CHECK: call void @llvm.memset.p0i8.i64(i8* %Base1, i8 1, i64 %tmp, i32 4, i1 false) > +; CHECK: %0 = mul i64 %Size, 4 > +; CHECK: call void @llvm.memset.p0i8.i64(i8* %Base1, i8 1, i64 %0, i32 4, i1 false) > ; CHECK-NOT: store > } > > > Modified: llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll (original) > +++ llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll Tue Sep 27 15:39:19 2011 > @@ -4,15 +4,15 @@ > ; LSR should property handle the post-inc offset when folding the > ; non-IV operand of an icmp into the IV. > > -; CHECK: %tmp2 = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast > -; CHECK: %tmp3 = lshr i64 %tmp2, 1 > -; CHECK: %tmp4 = mul i64 %tmp3, 2 > +; CHECK: %5 = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast > +; CHECK: %6 = lshr i64 %5, 1 > +; CHECK: %7 = mul i64 %6, 2 > ; CHECK: br label %for.body > ; CHECK: for.body: > -; CHECK: %lsr.iv5 = phi i64 [ %lsr.iv.next, %for.body ], [ %tmp4, %for.body.lr.ph ] > -; CHECK: %lsr.iv.next = add i64 %lsr.iv5, -2 > -; CHECK: %lsr.iv.next6 = inttoptr i64 %lsr.iv.next to i16* > -; CHECK: %cmp27 = icmp eq i16* %lsr.iv.next6, null > +; CHECK: %lsr.iv2 = phi i64 [ %lsr.iv.next, %for.body ], [ %7, %for.body.lr.ph ] > +; CHECK: %lsr.iv.next = add i64 %lsr.iv2, -2 > +; CHECK: %lsr.iv.next3 = inttoptr i64 %lsr.iv.next to i16* > +; CHECK: %cmp27 = icmp eq i16* %lsr.iv.next3, null > > target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" > target triple = "x86_64-unknown-linux-gnu" > > Modified: llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll (original) > +++ llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Tue Sep 27 15:39:19 2011 > @@ -110,7 +110,7 @@ > ; CHECK-NOT: alloca > ; CHECK: bitcast <4 x float> %x to <2 x double> > ; CHECK-NEXT: extractelement <2 x double> > -; CHECK-NEXT: bitcast double %tmp4 to <2 x float> > +; CHECK-NEXT: bitcast double %2 to <2 x float> > ; CHECK-NEXT: extractelement <4 x float> > } > > @@ -125,7 +125,7 @@ > ; CHECK: bitcast <4 x float> %x to <2 x double> > ; CHECK-NEXT: bitcast <2 x float> %y to double > ; CHECK-NEXT: insertelement <2 x double> > -; CHECK-NEXT: bitcast <2 x double> %tmp2 to <4 x float> > +; CHECK-NEXT: bitcast <2 x double> %3 to <4 x float> > } > > define i256 @test9(<4 x i256> %x) { > @@ -140,7 +140,7 @@ > ; CHECK-NOT: alloca > ; CHECK: bitcast <4 x i256> %x to <2 x i512> > ; CHECK-NEXT: extractelement <2 x i512> > -; CHECK-NEXT: bitcast i512 %tmp4 to <2 x i256> > +; CHECK-NEXT: bitcast i512 %2 to <2 x i256> > ; CHECK-NEXT: extractelement <4 x i256> > } > > @@ -155,7 +155,7 @@ > ; CHECK: bitcast <4 x i256> %x to <2 x i512> > ; CHECK-NEXT: bitcast <2 x i256> %y to i512 > ; CHECK-NEXT: insertelement <2 x i512> > -; CHECK-NEXT: bitcast <2 x i512> %tmp2 to <4 x i256> > +; CHECK-NEXT: bitcast <2 x i512> %3 to <4 x i256> > } > > %union.v = type { <2 x i64> } > @@ -245,7 +245,7 @@ > ret void > ; CHECK: @test15 > ; CHECK-NOT: alloca > -; CHECK: shufflevector <4 x i64> %tmpV2, <4 x i64> undef, <3 x i32> > +; CHECK: shufflevector <4 x i64> %tmpV1, <4 x i64> undef, <3 x i32> > } > > define <4 x float> @test16(<4 x float> %x, i64 %y0, i64 %y1) { > > Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/pow-to-sqrt.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/pow-to-sqrt.ll?rev=140634&r1=140633&r2=140634&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/SimplifyLibCalls/pow-to-sqrt.ll (original) > +++ llvm/trunk/test/Transforms/SimplifyLibCalls/pow-to-sqrt.ll Tue Sep 27 15:39:19 2011 > @@ -7,9 +7,9 @@ > ; CHECK: define float @foo(float %x) nounwind { > ; CHECK: %sqrtf = call float @sqrtf(float %x) nounwind readonly > ; CHECK: %fabsf = call float @fabsf(float %sqrtf) nounwind readonly > -; CHECK: %tmp = fcmp oeq float %x, 0xFFF0000000000000 > -; CHECK: %tmp1 = select i1 %tmp, float 0x7FF0000000000000, float %fabsf > -; CHECK: ret float %tmp1 > +; CHECK: %1 = fcmp oeq float %x, 0xFFF0000000000000 > +; CHECK: %retval = select i1 %1, float 0x7FF0000000000000, float %fabsf > +; CHECK: ret float %retval > > define float @foo(float %x) nounwind { > %retval = call float @powf(float %x, float 0.5) > @@ -19,9 +19,9 @@ > ; CHECK: define double @doo(double %x) nounwind { > ; CHECK: %sqrt = call double @sqrt(double %x) nounwind readonly > ; CHECK: %fabs = call double @fabs(double %sqrt) nounwind readonly > -; CHECK: %tmp = fcmp oeq double %x, 0xFFF0000000000000 > -; CHECK: %tmp1 = select i1 %tmp, double 0x7FF0000000000000, double %fabs > -; CHECK: ret double %tmp1 > +; CHECK: %1 = fcmp oeq double %x, 0xFFF0000000000000 > +; CHECK: %retval = select i1 %1, double 0x7FF0000000000000, double %fabs > +; CHECK: ret double %retval > ; CHECK: } > > define double @doo(double %x) nounwind { > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ahatanak at gmail.com Tue Sep 27 17:01:01 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 27 Sep 2011 22:01:01 -0000 Subject: [llvm-commits] [llvm] r140644 - /llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Message-ID: <20110927220101.8A2AC2A6C12C@llvm.org> Author: ahatanak Date: Tue Sep 27 17:01:01 2011 New Revision: 140644 URL: http://llvm.org/viewvc/llvm-project?rev=140644&view=rev Log: Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside of the instruction definitions using Pat<>. Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=140644&r1=140643&r2=140644&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Tue Sep 27 17:01:01 2011 @@ -177,10 +177,12 @@ "ctc1\t$fs, $rt", []>; def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs), - "mfc1\t$rt, $fs", []>; + "mfc1\t$rt, $fs", + [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>; def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt), - "mtc1\t$rt, $fs", []>; + "mtc1\t$rt, $fs", + [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>; } def FMOV_S32 : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs), @@ -360,9 +362,6 @@ def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>; def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>; -def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>; -def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>; - let Predicates = [In32BitMode] in { def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>; def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>; From isanbard at gmail.com Tue Sep 27 17:14:12 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 27 Sep 2011 22:14:12 -0000 Subject: [llvm-commits] [llvm] r140646 - in /llvm/trunk/lib: CodeGen/LLVMTargetMachine.cpp Target/ARM/ARM.h Target/ARM/ARMSjLjLoweringPass.cpp Target/ARM/ARMTargetMachine.cpp Message-ID: <20110927221412.65F832A6C12C@llvm.org> Author: void Date: Tue Sep 27 17:14:12 2011 New Revision: 140646 URL: http://llvm.org/viewvc/llvm-project?rev=140646&view=rev Log: This is the start of the new SjLj EH preparation pass, which will replace the current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. Added: llvm/trunk/lib/Target/ARM/ARMSjLjLoweringPass.cpp Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/Target/ARM/ARM.h llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=140646&r1=140645&r2=140646&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Tue Sep 27 17:14:12 2011 @@ -45,6 +45,9 @@ bool EnableFastISel; } +static cl::opt DisableOldSjLjEH("disable-old-sjlj-eh", cl::Hidden, + cl::desc("Disable the old SjLj EH preparation pass")); + static cl::opt DisablePostRA("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc")); static cl::opt DisableBranchFold("disable-branch-fold", cl::Hidden, @@ -322,7 +325,8 @@ // removed from the parent invoke(s). This could happen when a landing // pad is shared by multiple invokes and is also a target of a normal // edge from elsewhere. - PM.add(createSjLjEHPass(getTargetLowering())); + if (!DisableOldSjLjEH) + PM.add(createSjLjEHPass(getTargetLowering())); // FALLTHROUGH case ExceptionHandling::DwarfCFI: case ExceptionHandling::ARM: Modified: llvm/trunk/lib/Target/ARM/ARM.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=140646&r1=140645&r2=140646&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.h (original) +++ llvm/trunk/lib/Target/ARM/ARM.h Tue Sep 27 17:14:12 2011 @@ -41,6 +41,7 @@ FunctionPass *createARMExpandPseudoPass(); FunctionPass *createARMGlobalMergePass(const TargetLowering* tli); FunctionPass *createARMConstantIslandPass(); +FunctionPass *createARMSjLjLoweringPass(); FunctionPass *createNEONMoveFixPass(); FunctionPass *createMLxExpansionPass(); FunctionPass *createThumb2ITBlockPass(); Added: llvm/trunk/lib/Target/ARM/ARMSjLjLoweringPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSjLjLoweringPass.cpp?rev=140646&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSjLjLoweringPass.cpp (added) +++ llvm/trunk/lib/Target/ARM/ARMSjLjLoweringPass.cpp Tue Sep 27 17:14:12 2011 @@ -0,0 +1,118 @@ +//===-- ARMSjLjLoweringPass.cpp - ARM SjLj Lowering Pass ------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains a pass that lowers the SjLj exception handling into +// machine instructions. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "arm-sjlj-lowering" +#include "ARM.h" +#include "llvm/Function.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/Target/TargetData.h" +#include "llvm/Target/TargetLowering.h" +#include "llvm/Support/CommandLine.h" +using namespace llvm; + +// Hidden options for the new EH stuff. +static cl::opt +EnableNewSjLjEHPrepare("enable-new-sjlj-eh", cl::Hidden, + cl::desc("Use the new SjLj EH preparation pass")); + +namespace { + +class ARMSjLjLowering : public MachineFunctionPass { + Type *FunctionCtxTy; + LLVMContext *Context; + + MachineFunction *MF; + const Function *Fn; + const TargetLowering *TLI; + const TargetInstrInfo *TII; + const TargetRegisterInfo *TRI; + + /// createFunctionContext - Create the function context on the stack. This + /// returns the nonnegative identifier representing it in the FrameInfo. + int createFunctionContext(); + +public: + static char ID; + ARMSjLjLowering() : MachineFunctionPass(ID) {} + + virtual bool runOnMachineFunction(MachineFunction &mf); + + virtual const char *getPassName() const { + return "ARM setjmp/longjmp exception handling lowering pass"; + } +}; + +char ARMSjLjLowering::ID = 0; + +} // end anonymous namespace + +FunctionPass *llvm::createARMSjLjLoweringPass() { + return new ARMSjLjLowering(); +} + +bool ARMSjLjLowering::runOnMachineFunction(MachineFunction &mf) { + if (!EnableNewSjLjEHPrepare) return false; + + MF = &mf; + Fn = MF->getFunction(); + Context = &Fn->getContext(); + TLI = MF->getTarget().getTargetLowering(); + TII = MF->getTarget().getInstrInfo(); + TRI = MF->getTarget().getRegisterInfo(); + + int FrameIdx = createFunctionContext(); (void)FrameIdx; + + return true; +} + +/// createFunctionContext - Create the function context on the stack. +int ARMSjLjLowering::createFunctionContext() { + // struct _Unwind_FunctionContext { + // // next function in stack of handlers. + // struct _Unwind_FunctionContext *prev; + // + // // set by calling function before registering to be the landing pad. + // uintptr_t resumeLocation; + // + // // set by personality handler to be parameters passed to landing pad + // // function. + // uintptr_t resumeParameters[4]; + // + // // set by calling function before registering + // __personality_routine personality; // arm offset=24 + // + // uintptr_t lsda // arm offset=28 + // + // // variable length array, contains registers to restore + // // 0 = r7, 1 = pc, 2 = sp + // void *jbuf[]; // 5 for GCC compatibility. + // }; + Type *VoidPtrTy = Type::getInt8PtrTy(*Context); + Type *Int32Ty = Type::getInt32Ty(*Context); + FunctionCtxTy = + StructType::get(VoidPtrTy, // prev + Int32Ty, // resumeLocation + ArrayType::get(Int32Ty, 4), // resumeParameters + VoidPtrTy, // personality + VoidPtrTy, // lsda + ArrayType::get(VoidPtrTy, 5), // jbuf + NULL); + + uint64_t TySize = TLI->getTargetData()->getTypeAllocSize(FunctionCtxTy); + unsigned Align = TLI->getTargetData()->getPrefTypeAlignment(FunctionCtxTy); + + return MF->getFrameInfo()->CreateStackObject(TySize, Align, false, false); +} Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=140646&r1=140645&r2=140646&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Tue Sep 27 17:14:12 2011 @@ -15,6 +15,7 @@ #include "ARM.h" #include "llvm/PassManager.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/TargetRegistry.h" @@ -107,7 +108,8 @@ PM.add(createARMLoadStoreOptimizationPass(true)); if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9()) PM.add(createMLxExpansionPass()); - + if (getMCAsmInfo()->getExceptionHandlingType() == ExceptionHandling::SjLj) + createARMSjLjLoweringPass(); return true; } From grosbach at apple.com Tue Sep 27 17:18:54 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 27 Sep 2011 22:18:54 -0000 Subject: [llvm-commits] [llvm] r140647 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s Message-ID: <20110927221854.942482A6C12C@llvm.org> Author: grosbach Date: Tue Sep 27 17:18:54 2011 New Revision: 140647 URL: http://llvm.org/viewvc/llvm-project?rev=140647&view=rev Log: ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. Add inst alias to handle these assembly forms. Add tests, too. rdar://10178799 Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=140647&r1=140646&r2=140647&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Sep 27 17:18:54 2011 @@ -3936,12 +3936,17 @@ (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm", (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; + def : t2InstAlias<"sxtb${p} $Rd, $Rm", (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; def : t2InstAlias<"sxtb16${p} $Rd, $Rm", (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; def : t2InstAlias<"sxth${p} $Rd, $Rm", (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; +def : t2InstAlias<"sxtb${p}.w $Rd, $Rm", + (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; +def : t2InstAlias<"sxth${p}.w $Rd, $Rm", + (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm", (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; @@ -3956,6 +3961,11 @@ def : t2InstAlias<"uxth${p} $Rd, $Rm", (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; +def : t2InstAlias<"uxtb${p}.w $Rd, $Rm", + (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; +def : t2InstAlias<"uxth${p}.w $Rd, $Rm", + (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; + // Extend instruction w/o the ".w" optional width specifier. def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot", (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=140647&r1=140646&r2=140647&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep 27 17:18:54 2011 @@ -2517,6 +2517,7 @@ ite ge sxtbge r2, r4 sxtblt r5, r1, ror #16 + sxtb.w r7, r8 @ CHECK: sxtb r5, r6 @ encoding: [0x75,0xb2] @ CHECK: sxtb.w r6, r9, ror #8 @ encoding: [0x4f,0xfa,0x99,0xf6] @@ -2524,6 +2525,7 @@ @ CHECK: ite ge @ encoding: [0xac,0xbf] @ CHECK: sxtbge r2, r4 @ encoding: [0x62,0xb2] @ CHECK: sxtblt.w r5, r1, ror #16 @ encoding: [0x4f,0xfa,0xa1,0xf5] +@ CHECK: sxtb.w r7, r8 @ encoding: [0x4f,0xfa,0x88,0xf7] @------------------------------------------------------------------------------ @@ -2553,6 +2555,7 @@ itt ne sxthne r3, r9 sxthne r2, r2, ror #16 + sxth.w r7, r8 @ CHECK: sxth r1, r6 @ encoding: [0x31,0xb2] @ CHECK: sxth.w r3, r8, ror #8 @ encoding: [0x0f,0xfa,0x98,0xf3] @@ -2560,6 +2563,7 @@ @ CHECK: itt ne @ encoding: [0x1c,0xbf] @ CHECK: sxthne.w r3, r9 @ encoding: [0x0f,0xfa,0x89,0xf3] @ CHECK: sxthne.w r2, r2, ror #16 @ encoding: [0x0f,0xfa,0xa2,0xf2] +@ CHECK: sxth.w r7, r8 @ encoding: [0x0f,0xfa,0x88,0xf7] @------------------------------------------------------------------------------ @@ -3016,6 +3020,7 @@ it cc uxtbcc r5, r1, ror #16 uxtb r8, r3, ror #24 + uxtb.w r7, r8 @ CHECK: it ge @ encoding: [0xa8,0xbf] @ CHECK: uxtbge r2, r4 @ encoding: [0xe2,0xb2] @@ -3024,6 +3029,7 @@ @ CHECK: it lo @ encoding: [0x38,0xbf] @ CHECK: uxtblo.w r5, r1, ror #16 @ encoding: [0x5f,0xfa,0xa1,0xf5] @ CHECK: uxtb.w r8, r3, ror #24 @ encoding: [0x5f,0xfa,0xb3,0xf8] +@ CHECK: uxtb.w r7, r8 @ encoding: [0x5f,0xfa,0x88,0xf7] @------------------------------------------------------------------------------ @@ -3056,6 +3062,7 @@ it le uxthle r2, r2, ror #16 uxth r9, r3, ror #24 + uxth.w r7, r8 @ CHECK: it ne @ encoding: [0x18,0xbf] @ CHECK: uxthne.w r3, r9 @ encoding: [0x1f,0xfa,0x89,0xf3] @@ -3064,7 +3071,7 @@ @ CHECK: it le @ encoding: [0xd8,0xbf] @ CHECK: uxthle.w r2, r2, ror #16 @ encoding: [0x1f,0xfa,0xa2,0xf2] @ CHECK: uxth.w r9, r3, ror #24 @ encoding: [0x1f,0xfa,0xb3,0xf9] - +@ CHECK: uxth.w r7, r8 @ encoding: [0x1f,0xfa,0x88,0xf7] @------------------------------------------------------------------------------ @ WFE/WFI/YIELD From stoklund at 2pi.dk Tue Sep 27 17:57:18 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 27 Sep 2011 22:57:18 -0000 Subject: [llvm-commits] [llvm] r140652 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/Target/X86/SSEDomainFix.cpp lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86InstrInfo.h Message-ID: <20110927225718.914352A6C12C@llvm.org> Author: stoklund Date: Tue Sep 27 17:57:18 2011 New Revision: 140652 URL: http://llvm.org/viewvc/llvm-project?rev=140652&view=rev Log: Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo. I am going to unify the SSEDomainFix and NEONMoveFix passes into a single target independent pass. They are essentially doing the same thing. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/Target/X86/SSEDomainFix.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=140652&r1=140651&r2=140652&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Sep 27 17:57:18 2011 @@ -687,6 +687,37 @@ return true; } + /// getExecutionDomain - Return the current execution domain and bit mask of + /// possible domains for instruction. + /// + /// Some micro-architectures have multiple execution domains, and multiple + /// opcodes that perform the same operation in different domains. For + /// example, the x86 architecture provides the por, orps, and orpd + /// instructions that all do the same thing. There is a latency penalty if a + /// register is written in one domain and read in another. + /// + /// This function returns a pair (domain, mask) containing the execution + /// domain of MI, and a bit mask of possible domains. The setExecutionDomain + /// function can be used to change the opcode to one of the domains in the + /// bit mask. Instructions whose execution domain can't be changed should + /// return a 0 mask. + /// + /// The execution domain numbers don't have any special meaning except domain + /// 0 is used for instructions that are not associated with any interesting + /// execution domain. + /// + virtual std::pair + getExecutionDomain(const MachineInstr *MI) const { + return std::make_pair(0, 0); + } + + /// setExecutionDomain - Change the opcode of MI to execute in Domain. + /// + /// The bit (1 << Domain) must be set in the mask returned from + /// getExecutionDomain(MI). + /// + virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {} + private: int CallFrameSetupOpcode, CallFrameDestroyOpcode; }; Modified: llvm/trunk/lib/Target/X86/SSEDomainFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp?rev=140652&r1=140651&r2=140652&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/SSEDomainFix.cpp (original) +++ llvm/trunk/lib/Target/X86/SSEDomainFix.cpp Tue Sep 27 17:57:18 2011 @@ -236,7 +236,7 @@ // Collapse all the instructions. while (!dv->Instrs.empty()) - TII->SetSSEDomain(dv->Instrs.pop_back_val(), domain); + TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain); dv->setSingleDomain(domain); // If there are multiple users, give them new, unique DomainValues. @@ -362,7 +362,7 @@ // If the collapsed operands force a single domain, propagate the collapse. if (isPowerOf2_32(available)) { unsigned domain = CountTrailingZeros_32(available); - TII->SetSSEDomain(mi, domain); + TII->setExecutionDomain(mi, domain); visitHardInstr(mi, domain); return; } @@ -473,7 +473,7 @@ MachineInstr *mi = I; if (mi->isDebugValue()) continue; ++Distance; - std::pair domp = TII->GetSSEDomain(mi); + std::pair domp = TII->getExecutionDomain(mi); if (domp.first) if (domp.second) visitSoftInstr(mi, domp.second); Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=140652&r1=140651&r2=140652&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Sep 27 17:57:18 2011 @@ -3355,13 +3355,13 @@ } std::pair -X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const { +X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const { uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; return std::make_pair(domain, domain && lookup(MI->getOpcode(), domain) ? 0xe : 0); } -void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const { +void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { assert(Domain>0 && Domain<4 && "Invalid execution domain"); uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; assert(dom && "Not an SSE instruction"); Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=140652&r1=140651&r2=140652&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Sep 27 17:57:18 2011 @@ -337,12 +337,10 @@ /// unsigned getGlobalBaseReg(MachineFunction *MF) const; - /// GetSSEDomain - Return the SSE execution domain of MI as the first element, - /// and a bitmask of possible arguments to SetSSEDomain ase the second. - std::pair GetSSEDomain(const MachineInstr *MI) const; + std::pair + getExecutionDomain(const MachineInstr *MI) const; - /// SetSSEDomain - Set the SSEDomain of MI. - void SetSSEDomain(MachineInstr *MI, unsigned Domain) const; + void setExecutionDomain(MachineInstr *MI, unsigned Domain) const; MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, From stoklund at 2pi.dk Tue Sep 27 17:57:21 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 27 Sep 2011 22:57:21 -0000 Subject: [llvm-commits] [llvm] r140653 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMBaseInstrInfo.h Message-ID: <20110927225721.B537F2A6C12C@llvm.org> Author: stoklund Date: Tue Sep 27 17:57:21 2011 New Revision: 140653 URL: http://llvm.org/viewvc/llvm-project?rev=140653&view=rev Log: Implement TII::get/setExecutionDomain() for ARM. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=140653&r1=140652&r2=140653&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Sep 27 17:57:21 2011 @@ -2720,3 +2720,56 @@ HasLane = Entry.HasLane; return true; } + +//===----------------------------------------------------------------------===// +// Execution domains. +//===----------------------------------------------------------------------===// +// +// Some instructions go down the NEON pipeline, some go down the VFP pipeline, +// and some can go down both. The vmov instructions go down the VFP pipeline, +// but they can be changed to vorr equivalents that are executed by the NEON +// pipeline. +// +// We use the following execution domain numbering: +// +// 0: Generic +// 1: VFP +// 2: NEON +// +// Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h +// +std::pair +ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { + // VMOVD is a VFP instruction, but can be changed to NEON if it isn't + // predicated. + if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) + return std::make_pair(1, 3); + + // No other instructions can be swizzled, so just determine their domain. + unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; + + if (Domain & ARMII::DomainNEON) + return std::make_pair(2, 0); + + // Certain instructions can go either way on Cortex-A8. + // Treat them as NEON instructions. + if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) + return std::make_pair(2, 0); + + if (Domain & ARMII::DomainVFP) + return std::make_pair(1, 0); + + return std::make_pair(0, 0); +} + +void +ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { + // We only know how to change VMOVD into VORR. + assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD"); + if (Domain != 2) + return; + + // Change to a VORRd which requires two identical use operands. + MI->setDesc(get(ARM::VORRd)); + MachineInstrBuilder(MI).addReg(MI->getOperand(1).getReg()); +} Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=140653&r1=140652&r2=140653&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Tue Sep 27 17:57:21 2011 @@ -210,6 +210,12 @@ int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const; + + /// VFP/NEON execution domains. + std::pair + getExecutionDomain(const MachineInstr *MI) const; + void setExecutionDomain(MachineInstr *MI, unsigned Domain) const; + private: int getVLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, From kremenek at apple.com Tue Sep 27 18:29:59 2011 From: kremenek at apple.com (Ted Kremenek) Date: Tue, 27 Sep 2011 23:29:59 -0000 Subject: [llvm-commits] [llvm] r140655 - in /llvm/trunk/lib/Target/ARM: CMakeLists.txt MCTargetDesc/CMakeLists.txt Message-ID: <20110927232959.BC96C2A6C12C@llvm.org> Author: kremenek Date: Tue Sep 27 18:29:59 2011 New Revision: 140655 URL: http://llvm.org/viewvc/llvm-project?rev=140655&view=rev Log: Unbreak CMake build. Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=140655&r1=140654&r2=140655&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Tue Sep 27 18:29:59 2011 @@ -36,13 +36,14 @@ ARMMCInstLower.cpp ARMRegisterInfo.cpp ARMSelectionDAGInfo.cpp + ARMSjLjLoweringPass.cpp ARMSubtarget.cpp ARMTargetMachine.cpp ARMTargetObjectFile.cpp MLxExpansionPass.cpp NEONMoveFix.cpp - Thumb1InstrInfo.cpp Thumb1FrameLowering.cpp + Thumb1InstrInfo.cpp Thumb1RegisterInfo.cpp Thumb2ITBlockPass.cpp Thumb2InstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt?rev=140655&r1=140654&r2=140655&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Tue Sep 27 18:29:59 2011 @@ -1,9 +1,9 @@ add_llvm_library(LLVMARMDesc ARMAsmBackend.cpp - ARMMCTargetDesc.cpp ARMMCAsmInfo.cpp ARMMCCodeEmitter.cpp ARMMCExpr.cpp + ARMMCTargetDesc.cpp ARMMachObjectWriter.cpp ) add_dependencies(LLVMARMDesc ARMCommonTableGen) From stoklund at 2pi.dk Tue Sep 27 18:50:46 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 27 Sep 2011 23:50:46 -0000 Subject: [llvm-commits] [llvm] r140659 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/Target/X86/SSEDomainFix.cpp lib/Target/X86/X86.h lib/Target/X86/X86TargetMachine.cpp test/CodeGen/X86/avx-load-store.ll test/CodeGen/X86/avx-splat.ll Message-ID: <20110927235046.8617E2A6C12C@llvm.org> Author: stoklund Date: Tue Sep 27 18:50:46 2011 New Revision: 140659 URL: http://llvm.org/viewvc/llvm-project?rev=140659&view=rev Log: Remove X86-dependent stuff from SSEDomainFix. This also enables domain swizzling for AVX code which required a few trivial test changes. The pass will be moved to lib/CodeGen shortly. Modified: llvm/trunk/include/llvm/CodeGen/Passes.h llvm/trunk/lib/Target/X86/SSEDomainFix.cpp llvm/trunk/lib/Target/X86/X86.h llvm/trunk/lib/Target/X86/X86TargetMachine.cpp llvm/trunk/test/CodeGen/X86/avx-load-store.ll llvm/trunk/test/CodeGen/X86/avx-splat.ll Modified: llvm/trunk/include/llvm/CodeGen/Passes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=140659&r1=140658&r2=140659&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/Passes.h (original) +++ llvm/trunk/include/llvm/CodeGen/Passes.h Tue Sep 27 18:50:46 2011 @@ -24,6 +24,7 @@ class MachineFunctionPass; class PassInfo; class TargetLowering; + class TargetRegisterClass; class raw_ostream; /// createUnreachableBlockEliminationPass - The LLVM code generator does not @@ -225,6 +226,14 @@ /// FunctionPass *createExpandISelPseudosPass(); + /// createExecutionDependencyFixPass - This pass fixes execution time + /// problems with dependent instructions, such as switching execution + /// domains to match. + /// + /// The pass will examine instructions using and defining registers in RC. + /// + FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC); + } // End llvm namespace #endif Modified: llvm/trunk/lib/Target/X86/SSEDomainFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp?rev=140659&r1=140658&r2=140659&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/SSEDomainFix.cpp (original) +++ llvm/trunk/lib/Target/X86/SSEDomainFix.cpp Tue Sep 27 18:50:46 2011 @@ -18,10 +18,12 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "sse-domain-fix" -#include "X86InstrInfo.h" +#define DEBUG_TYPE "execution-fix" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/ADT/DepthFirstIterator.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/Debug.h" @@ -97,25 +99,27 @@ }; } -static const unsigned NumRegs = 16; - namespace { class SSEDomainFixPass : public MachineFunctionPass { static char ID; SpecificBumpPtrAllocator Allocator; SmallVector Avail; + const TargetRegisterClass *const RC; MachineFunction *MF; - const X86InstrInfo *TII; + const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; MachineBasicBlock *MBB; + std::vector AliasMap; + const unsigned NumRegs; DomainValue **LiveRegs; typedef DenseMap LiveOutMap; LiveOutMap LiveOuts; unsigned Distance; public: - SSEDomainFixPass() : MachineFunctionPass(ID) {} + SSEDomainFixPass(const TargetRegisterClass *rc) + : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); @@ -154,10 +158,9 @@ /// Translate TRI register number to an index into our smaller tables of /// interesting registers. Return -1 for boring registers. -int SSEDomainFixPass::RegIndex(unsigned reg) { - assert(X86::XMM15 == X86::XMM0+NumRegs-1 && "Unexpected sort"); - reg -= X86::XMM0; - return reg < NumRegs ? (int) reg : -1; +int SSEDomainFixPass::RegIndex(unsigned Reg) { + assert(Reg < AliasMap.size() && "Invalid register"); + return AliasMap[Reg]; } DomainValue *SSEDomainFixPass::Alloc(int domain) { @@ -444,23 +447,33 @@ bool SSEDomainFixPass::runOnMachineFunction(MachineFunction &mf) { MF = &mf; - TII = static_cast(MF->getTarget().getInstrInfo()); + TII = MF->getTarget().getInstrInfo(); TRI = MF->getTarget().getRegisterInfo(); MBB = 0; LiveRegs = 0; Distance = 0; - assert(NumRegs == X86::VR128RegClass.getNumRegs() && "Bad regclass"); + assert(NumRegs == RC->getNumRegs() && "Bad regclass"); // If no XMM registers are used in the function, we can skip it completely. bool anyregs = false; - for (TargetRegisterClass::const_iterator I = X86::VR128RegClass.begin(), - E = X86::VR128RegClass.end(); I != E; ++I) + for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end(); + I != E; ++I) if (MF->getRegInfo().isPhysRegUsed(*I)) { anyregs = true; break; } if (!anyregs) return false; + // Initialize the AliasMap on the first use. + if (AliasMap.empty()) { + // Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC, + // or -1. + AliasMap.resize(TRI->getNumRegs(), -1); + for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i) + for (const unsigned *AI = TRI->getOverlaps(RC->getRegister(i)); *AI; ++AI) + AliasMap[*AI] = i; + } + MachineBasicBlock *Entry = MF->begin(); SmallPtrSet Visited; for (df_ext_iterator > @@ -501,6 +514,7 @@ return false; } -FunctionPass *llvm::createSSEDomainFixPass() { - return new SSEDomainFixPass(); +FunctionPass * +llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) { + return new SSEDomainFixPass(RC); } Modified: llvm/trunk/lib/Target/X86/X86.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=140659&r1=140658&r2=140659&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.h (original) +++ llvm/trunk/lib/Target/X86/X86.h Tue Sep 27 18:50:46 2011 @@ -44,10 +44,6 @@ /// FunctionPass *createX86FloatingPointStackifierPass(); -/// createSSEDomainFixPass - This pass twiddles SSE opcodes to prevent domain -/// crossings. -FunctionPass *createSSEDomainFixPass(); - /// createX86IssueVZeroUpperPass - This pass inserts AVX vzeroupper instructions /// before each call to avoid transition penalty between functions encoded with /// AVX and SSE. Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=140659&r1=140658&r2=140659&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Tue Sep 27 18:50:46 2011 @@ -133,7 +133,7 @@ bool ShouldPrint = false; if (OptLevel != CodeGenOpt::None && (Subtarget.hasSSE2() || Subtarget.hasAVX())) { - PM.add(createSSEDomainFixPass()); + PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass)); ShouldPrint = true; } Modified: llvm/trunk/test/CodeGen/X86/avx-load-store.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-load-store.ll?rev=140659&r1=140658&r2=140659&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-load-store.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-load-store.ll Tue Sep 27 18:50:46 2011 @@ -3,8 +3,8 @@ ; CHECK: vmovaps ; CHECK: vmovaps -; CHECK: vmovapd -; CHECK: vmovapd +; CHECK: vmovaps +; CHECK: vmovaps ; CHECK: vmovaps ; CHECK: vmovaps define void @test_256_load(double* nocapture %d, float* nocapture %f, <4 x i64>* nocapture %i) nounwind uwtable ssp { Modified: llvm/trunk/test/CodeGen/X86/avx-splat.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-splat.ll?rev=140659&r1=140658&r2=140659&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-splat.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-splat.ll Tue Sep 27 18:50:46 2011 @@ -47,7 +47,7 @@ ; shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> ; To: ; shuffle (vload ptr)), undef, <1, 1, 1, 1> -; CHECK: vmovaps +; CHECK: vmovdqa ; CHECK-NEXT: vinsertf128 $1 ; CHECK-NEXT: vpermilps $-1 define <8 x float> @funcE() nounwind { From stoklund at 2pi.dk Tue Sep 27 19:01:54 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 28 Sep 2011 00:01:54 -0000 Subject: [llvm-commits] [llvm] r140663 - in /llvm/trunk/lib: CodeGen/CMakeLists.txt CodeGen/ExecutionDepsFix.cpp Target/X86/CMakeLists.txt Target/X86/SSEDomainFix.cpp Message-ID: <20110928000154.5C9052A6C12C@llvm.org> Author: stoklund Date: Tue Sep 27 19:01:54 2011 New Revision: 140663 URL: http://llvm.org/viewvc/llvm-project?rev=140663&view=rev Log: Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix. I'll clean up the source in the next commit. Added: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp - copied, changed from r140661, llvm/trunk/lib/Target/X86/SSEDomainFix.cpp Removed: llvm/trunk/lib/Target/X86/SSEDomainFix.cpp Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt llvm/trunk/lib/Target/X86/CMakeLists.txt Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=140663&r1=140662&r2=140663&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Tue Sep 27 19:01:54 2011 @@ -13,6 +13,7 @@ EdgeBundles.cpp ELFCodeEmitter.cpp ELFWriter.cpp + ExecutionDepsFix.cpp ExpandISelPseudos.cpp ExpandPostRAPseudos.cpp GCMetadata.cpp Copied: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (from r140661, llvm/trunk/lib/Target/X86/SSEDomainFix.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?p2=llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp&p1=llvm/trunk/lib/Target/X86/SSEDomainFix.cpp&r1=140661&r2=140663&rev=140663&view=diff ============================================================================== (empty) Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=140663&r1=140662&r2=140663&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Tue Sep 27 19:01:54 2011 @@ -14,7 +14,6 @@ add_public_tablegen_target(X86CommonTableGen) set(sources - SSEDomainFix.cpp X86AsmPrinter.cpp X86COFFMachineModuleInfo.cpp X86CodeEmitter.cpp Removed: llvm/trunk/lib/Target/X86/SSEDomainFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/SSEDomainFix.cpp?rev=140662&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/SSEDomainFix.cpp (original) +++ llvm/trunk/lib/Target/X86/SSEDomainFix.cpp (removed) @@ -1,520 +0,0 @@ -//===- SSEDomainFix.cpp - Use proper int/float domain for SSE ---*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the SSEDomainFix pass. -// -// Some SSE instructions like mov, and, or, xor are available in different -// variants for different operand types. These variant instructions are -// equivalent, but on Nehalem and newer cpus there is extra latency -// transferring data between integer and floating point domains. -// -// This pass changes the variant instructions to minimize domain crossings. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "execution-fix" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/ADT/DepthFirstIterator.h" -#include "llvm/Support/Allocator.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" -using namespace llvm; - -/// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track -/// of execution domains. -/// -/// An open DomainValue represents a set of instructions that can still switch -/// execution domain. Multiple registers may refer to the same open -/// DomainValue - they will eventually be collapsed to the same execution -/// domain. -/// -/// A collapsed DomainValue represents a single register that has been forced -/// into one of more execution domains. There is a separate collapsed -/// DomainValue for each register, but it may contain multiple execution -/// domains. A register value is initially created in a single execution -/// domain, but if we were forced to pay the penalty of a domain crossing, we -/// keep track of the fact the the register is now available in multiple -/// domains. -namespace { -struct DomainValue { - // Basic reference counting. - unsigned Refs; - - // Bitmask of available domains. For an open DomainValue, it is the still - // possible domains for collapsing. For a collapsed DomainValue it is the - // domains where the register is available for free. - unsigned AvailableDomains; - - // Position of the last defining instruction. - unsigned Dist; - - // Twiddleable instructions using or defining these registers. - SmallVector Instrs; - - // A collapsed DomainValue has no instructions to twiddle - it simply keeps - // track of the domains where the registers are already available. - bool isCollapsed() const { return Instrs.empty(); } - - // Is domain available? - bool hasDomain(unsigned domain) const { - return AvailableDomains & (1u << domain); - } - - // Mark domain as available. - void addDomain(unsigned domain) { - AvailableDomains |= 1u << domain; - } - - // Restrict to a single domain available. - void setSingleDomain(unsigned domain) { - AvailableDomains = 1u << domain; - } - - // Return bitmask of domains that are available and in mask. - unsigned getCommonDomains(unsigned mask) const { - return AvailableDomains & mask; - } - - // First domain available. - unsigned getFirstDomain() const { - return CountTrailingZeros_32(AvailableDomains); - } - - DomainValue() { clear(); } - - void clear() { - Refs = AvailableDomains = Dist = 0; - Instrs.clear(); - } -}; -} - -namespace { -class SSEDomainFixPass : public MachineFunctionPass { - static char ID; - SpecificBumpPtrAllocator Allocator; - SmallVector Avail; - - const TargetRegisterClass *const RC; - MachineFunction *MF; - const TargetInstrInfo *TII; - const TargetRegisterInfo *TRI; - MachineBasicBlock *MBB; - std::vector AliasMap; - const unsigned NumRegs; - DomainValue **LiveRegs; - typedef DenseMap LiveOutMap; - LiveOutMap LiveOuts; - unsigned Distance; - -public: - SSEDomainFixPass(const TargetRegisterClass *rc) - : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} - - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesAll(); - MachineFunctionPass::getAnalysisUsage(AU); - } - - virtual bool runOnMachineFunction(MachineFunction &MF); - - virtual const char *getPassName() const { - return "SSE execution domain fixup"; - } - -private: - // Register mapping. - int RegIndex(unsigned Reg); - - // DomainValue allocation. - DomainValue *Alloc(int domain = -1); - void Recycle(DomainValue*); - - // LiveRegs manipulations. - void SetLiveReg(int rx, DomainValue *DV); - void Kill(int rx); - void Force(int rx, unsigned domain); - void Collapse(DomainValue *dv, unsigned domain); - bool Merge(DomainValue *A, DomainValue *B); - - void enterBasicBlock(); - void visitGenericInstr(MachineInstr*); - void visitSoftInstr(MachineInstr*, unsigned mask); - void visitHardInstr(MachineInstr*, unsigned domain); -}; -} - -char SSEDomainFixPass::ID = 0; - -/// Translate TRI register number to an index into our smaller tables of -/// interesting registers. Return -1 for boring registers. -int SSEDomainFixPass::RegIndex(unsigned Reg) { - assert(Reg < AliasMap.size() && "Invalid register"); - return AliasMap[Reg]; -} - -DomainValue *SSEDomainFixPass::Alloc(int domain) { - DomainValue *dv = Avail.empty() ? - new(Allocator.Allocate()) DomainValue : - Avail.pop_back_val(); - dv->Dist = Distance; - if (domain >= 0) - dv->addDomain(domain); - return dv; -} - -void SSEDomainFixPass::Recycle(DomainValue *dv) { - assert(dv && "Cannot recycle NULL"); - dv->clear(); - Avail.push_back(dv); -} - -/// Set LiveRegs[rx] = dv, updating reference counts. -void SSEDomainFixPass::SetLiveReg(int rx, DomainValue *dv) { - assert(unsigned(rx) < NumRegs && "Invalid index"); - if (!LiveRegs) { - LiveRegs = new DomainValue*[NumRegs]; - std::fill(LiveRegs, LiveRegs+NumRegs, (DomainValue*)0); - } - - if (LiveRegs[rx] == dv) - return; - if (LiveRegs[rx]) { - assert(LiveRegs[rx]->Refs && "Bad refcount"); - if (--LiveRegs[rx]->Refs == 0) Recycle(LiveRegs[rx]); - } - LiveRegs[rx] = dv; - if (dv) ++dv->Refs; -} - -// Kill register rx, recycle or collapse any DomainValue. -void SSEDomainFixPass::Kill(int rx) { - assert(unsigned(rx) < NumRegs && "Invalid index"); - if (!LiveRegs || !LiveRegs[rx]) return; - - // Before killing the last reference to an open DomainValue, collapse it to - // the first available domain. - if (LiveRegs[rx]->Refs == 1 && !LiveRegs[rx]->isCollapsed()) - Collapse(LiveRegs[rx], LiveRegs[rx]->getFirstDomain()); - else - SetLiveReg(rx, 0); -} - -/// Force register rx into domain. -void SSEDomainFixPass::Force(int rx, unsigned domain) { - assert(unsigned(rx) < NumRegs && "Invalid index"); - DomainValue *dv; - if (LiveRegs && (dv = LiveRegs[rx])) { - if (dv->isCollapsed()) - dv->addDomain(domain); - else if (dv->hasDomain(domain)) - Collapse(dv, domain); - else { - // This is an incompatible open DomainValue. Collapse it to whatever and force - // the new value into domain. This costs a domain crossing. - Collapse(dv, dv->getFirstDomain()); - assert(LiveRegs[rx] && "Not live after collapse?"); - LiveRegs[rx]->addDomain(domain); - } - } else { - // Set up basic collapsed DomainValue. - SetLiveReg(rx, Alloc(domain)); - } -} - -/// Collapse open DomainValue into given domain. If there are multiple -/// registers using dv, they each get a unique collapsed DomainValue. -void SSEDomainFixPass::Collapse(DomainValue *dv, unsigned domain) { - assert(dv->hasDomain(domain) && "Cannot collapse"); - - // Collapse all the instructions. - while (!dv->Instrs.empty()) - TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain); - dv->setSingleDomain(domain); - - // If there are multiple users, give them new, unique DomainValues. - if (LiveRegs && dv->Refs > 1) - for (unsigned rx = 0; rx != NumRegs; ++rx) - if (LiveRegs[rx] == dv) - SetLiveReg(rx, Alloc(domain)); -} - -/// Merge - All instructions and registers in B are moved to A, and B is -/// released. -bool SSEDomainFixPass::Merge(DomainValue *A, DomainValue *B) { - assert(!A->isCollapsed() && "Cannot merge into collapsed"); - assert(!B->isCollapsed() && "Cannot merge from collapsed"); - if (A == B) - return true; - // Restrict to the domains that A and B have in common. - unsigned common = A->getCommonDomains(B->AvailableDomains); - if (!common) - return false; - A->AvailableDomains = common; - A->Dist = std::max(A->Dist, B->Dist); - A->Instrs.append(B->Instrs.begin(), B->Instrs.end()); - for (unsigned rx = 0; rx != NumRegs; ++rx) - if (LiveRegs[rx] == B) - SetLiveReg(rx, A); - return true; -} - -void SSEDomainFixPass::enterBasicBlock() { - // Try to coalesce live-out registers from predecessors. - for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(), - e = MBB->livein_end(); i != e; ++i) { - int rx = RegIndex(*i); - if (rx < 0) continue; - for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(), - pe = MBB->pred_end(); pi != pe; ++pi) { - LiveOutMap::const_iterator fi = LiveOuts.find(*pi); - if (fi == LiveOuts.end()) continue; - DomainValue *pdv = fi->second[rx]; - if (!pdv) continue; - if (!LiveRegs || !LiveRegs[rx]) { - SetLiveReg(rx, pdv); - continue; - } - - // We have a live DomainValue from more than one predecessor. - if (LiveRegs[rx]->isCollapsed()) { - // We are already collapsed, but predecessor is not. Force him. - unsigned domain = LiveRegs[rx]->getFirstDomain(); - if (!pdv->isCollapsed() && pdv->hasDomain(domain)) - Collapse(pdv, domain); - continue; - } - - // Currently open, merge in predecessor. - if (!pdv->isCollapsed()) - Merge(LiveRegs[rx], pdv); - else - Force(rx, pdv->getFirstDomain()); - } - } -} - -// A hard instruction only works in one domain. All input registers will be -// forced into that domain. -void SSEDomainFixPass::visitHardInstr(MachineInstr *mi, unsigned domain) { - // Collapse all uses. - for (unsigned i = mi->getDesc().getNumDefs(), - e = mi->getDesc().getNumOperands(); i != e; ++i) { - MachineOperand &mo = mi->getOperand(i); - if (!mo.isReg()) continue; - int rx = RegIndex(mo.getReg()); - if (rx < 0) continue; - Force(rx, domain); - } - - // Kill all defs and force them. - for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { - MachineOperand &mo = mi->getOperand(i); - if (!mo.isReg()) continue; - int rx = RegIndex(mo.getReg()); - if (rx < 0) continue; - Kill(rx); - Force(rx, domain); - } -} - -// A soft instruction can be changed to work in other domains given by mask. -void SSEDomainFixPass::visitSoftInstr(MachineInstr *mi, unsigned mask) { - // Bitmask of available domains for this instruction after taking collapsed - // operands into account. - unsigned available = mask; - - // Scan the explicit use operands for incoming domains. - SmallVector used; - if (LiveRegs) - for (unsigned i = mi->getDesc().getNumDefs(), - e = mi->getDesc().getNumOperands(); i != e; ++i) { - MachineOperand &mo = mi->getOperand(i); - if (!mo.isReg()) continue; - int rx = RegIndex(mo.getReg()); - if (rx < 0) continue; - if (DomainValue *dv = LiveRegs[rx]) { - // Bitmask of domains that dv and available have in common. - unsigned common = dv->getCommonDomains(available); - // Is it possible to use this collapsed register for free? - if (dv->isCollapsed()) { - // Restrict available domains to the ones in common with the operand. - // If there are no common domains, we must pay the cross-domain - // penalty for this operand. - if (common) available = common; - } else if (common) - // Open DomainValue is compatible, save it for merging. - used.push_back(rx); - else - // Open DomainValue is not compatible with instruction. It is useless - // now. - Kill(rx); - } - } - - // If the collapsed operands force a single domain, propagate the collapse. - if (isPowerOf2_32(available)) { - unsigned domain = CountTrailingZeros_32(available); - TII->setExecutionDomain(mi, domain); - visitHardInstr(mi, domain); - return; - } - - // Kill off any remaining uses that don't match available, and build a list of - // incoming DomainValues that we want to merge. - SmallVector doms; - for (SmallVector::iterator i=used.begin(), e=used.end(); i!=e; ++i) { - int rx = *i; - DomainValue *dv = LiveRegs[rx]; - // This useless DomainValue could have been missed above. - if (!dv->getCommonDomains(available)) { - Kill(*i); - continue; - } - // sorted, uniqued insert. - bool inserted = false; - for (SmallVector::iterator i = doms.begin(), e = doms.end(); - i != e && !inserted; ++i) { - if (dv == *i) - inserted = true; - else if (dv->Dist < (*i)->Dist) { - inserted = true; - doms.insert(i, dv); - } - } - if (!inserted) - doms.push_back(dv); - } - - // doms are now sorted in order of appearance. Try to merge them all, giving - // priority to the latest ones. - DomainValue *dv = 0; - while (!doms.empty()) { - if (!dv) { - dv = doms.pop_back_val(); - continue; - } - - DomainValue *latest = doms.pop_back_val(); - if (Merge(dv, latest)) continue; - - // If latest didn't merge, it is useless now. Kill all registers using it. - for (SmallVector::iterator i=used.begin(), e=used.end(); i != e; ++i) - if (LiveRegs[*i] == latest) - Kill(*i); - } - - // dv is the DomainValue we are going to use for this instruction. - if (!dv) - dv = Alloc(); - dv->Dist = Distance; - dv->AvailableDomains = available; - dv->Instrs.push_back(mi); - - // Finally set all defs and non-collapsed uses to dv. - for (unsigned i = 0, e = mi->getDesc().getNumOperands(); i != e; ++i) { - MachineOperand &mo = mi->getOperand(i); - if (!mo.isReg()) continue; - int rx = RegIndex(mo.getReg()); - if (rx < 0) continue; - if (!LiveRegs || !LiveRegs[rx] || (mo.isDef() && LiveRegs[rx]!=dv)) { - Kill(rx); - SetLiveReg(rx, dv); - } - } -} - -void SSEDomainFixPass::visitGenericInstr(MachineInstr *mi) { - // Process explicit defs, kill any XMM registers redefined. - for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { - MachineOperand &mo = mi->getOperand(i); - if (!mo.isReg()) continue; - int rx = RegIndex(mo.getReg()); - if (rx < 0) continue; - Kill(rx); - } -} - -bool SSEDomainFixPass::runOnMachineFunction(MachineFunction &mf) { - MF = &mf; - TII = MF->getTarget().getInstrInfo(); - TRI = MF->getTarget().getRegisterInfo(); - MBB = 0; - LiveRegs = 0; - Distance = 0; - assert(NumRegs == RC->getNumRegs() && "Bad regclass"); - - // If no XMM registers are used in the function, we can skip it completely. - bool anyregs = false; - for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end(); - I != E; ++I) - if (MF->getRegInfo().isPhysRegUsed(*I)) { - anyregs = true; - break; - } - if (!anyregs) return false; - - // Initialize the AliasMap on the first use. - if (AliasMap.empty()) { - // Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC, - // or -1. - AliasMap.resize(TRI->getNumRegs(), -1); - for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i) - for (const unsigned *AI = TRI->getOverlaps(RC->getRegister(i)); *AI; ++AI) - AliasMap[*AI] = i; - } - - MachineBasicBlock *Entry = MF->begin(); - SmallPtrSet Visited; - for (df_ext_iterator > - DFI = df_ext_begin(Entry, Visited), DFE = df_ext_end(Entry, Visited); - DFI != DFE; ++DFI) { - MBB = *DFI; - enterBasicBlock(); - for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; - ++I) { - MachineInstr *mi = I; - if (mi->isDebugValue()) continue; - ++Distance; - std::pair domp = TII->getExecutionDomain(mi); - if (domp.first) - if (domp.second) - visitSoftInstr(mi, domp.second); - else - visitHardInstr(mi, domp.first); - else if (LiveRegs) - visitGenericInstr(mi); - } - - // Save live registers at end of MBB - used by enterBasicBlock(). - if (LiveRegs) - LiveOuts.insert(std::make_pair(MBB, LiveRegs)); - LiveRegs = 0; - } - - // Clear the LiveOuts vectors. Should we also collapse any remaining - // DomainValues? - for (LiveOutMap::const_iterator i = LiveOuts.begin(), e = LiveOuts.end(); - i != e; ++i) - delete[] i->second; - LiveOuts.clear(); - Avail.clear(); - Allocator.DestroyAll(); - - return false; -} - -FunctionPass * -llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) { - return new SSEDomainFixPass(RC); -} From stoklund at 2pi.dk Tue Sep 27 19:01:57 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 28 Sep 2011 00:01:57 -0000 Subject: [llvm-commits] [llvm] r140664 - /llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Message-ID: <20110928000157.08B882A6C12C@llvm.org> Author: stoklund Date: Tue Sep 27 19:01:56 2011 New Revision: 140664 URL: http://llvm.org/viewvc/llvm-project?rev=140664&view=rev Log: Rename class and clean up source. No functional change intended. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=140664&r1=140663&r2=140664&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Tue Sep 27 19:01:56 2011 @@ -1,4 +1,4 @@ -//===- SSEDomainFix.cpp - Use proper int/float domain for SSE ---*- C++ -*-===// +//===- ExecutionDepsFix.cpp - Fix execution dependecy issues ----*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,12 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the SSEDomainFix pass. +// This file contains the execution dependency fix pass. // -// Some SSE instructions like mov, and, or, xor are available in different +// Some X86 SSE instructions like mov, and, or, xor are available in different // variants for different operand types. These variant instructions are // equivalent, but on Nehalem and newer cpus there is extra latency -// transferring data between integer and floating point domains. +// transferring data between integer and floating point domains. ARM cores +// have similar issues when they are configured with both VFP and NEON +// pipelines. // // This pass changes the variant instructions to minimize domain crossings. // @@ -100,7 +102,7 @@ } namespace { -class SSEDomainFixPass : public MachineFunctionPass { +class ExeDepsFix : public MachineFunctionPass { static char ID; SpecificBumpPtrAllocator Allocator; SmallVector Avail; @@ -118,7 +120,7 @@ unsigned Distance; public: - SSEDomainFixPass(const TargetRegisterClass *rc) + ExeDepsFix(const TargetRegisterClass *rc) : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} virtual void getAnalysisUsage(AnalysisUsage &AU) const { @@ -154,16 +156,16 @@ }; } -char SSEDomainFixPass::ID = 0; +char ExeDepsFix::ID = 0; /// Translate TRI register number to an index into our smaller tables of /// interesting registers. Return -1 for boring registers. -int SSEDomainFixPass::RegIndex(unsigned Reg) { +int ExeDepsFix::RegIndex(unsigned Reg) { assert(Reg < AliasMap.size() && "Invalid register"); return AliasMap[Reg]; } -DomainValue *SSEDomainFixPass::Alloc(int domain) { +DomainValue *ExeDepsFix::Alloc(int domain) { DomainValue *dv = Avail.empty() ? new(Allocator.Allocate()) DomainValue : Avail.pop_back_val(); @@ -173,14 +175,14 @@ return dv; } -void SSEDomainFixPass::Recycle(DomainValue *dv) { +void ExeDepsFix::Recycle(DomainValue *dv) { assert(dv && "Cannot recycle NULL"); dv->clear(); Avail.push_back(dv); } /// Set LiveRegs[rx] = dv, updating reference counts. -void SSEDomainFixPass::SetLiveReg(int rx, DomainValue *dv) { +void ExeDepsFix::SetLiveReg(int rx, DomainValue *dv) { assert(unsigned(rx) < NumRegs && "Invalid index"); if (!LiveRegs) { LiveRegs = new DomainValue*[NumRegs]; @@ -198,7 +200,7 @@ } // Kill register rx, recycle or collapse any DomainValue. -void SSEDomainFixPass::Kill(int rx) { +void ExeDepsFix::Kill(int rx) { assert(unsigned(rx) < NumRegs && "Invalid index"); if (!LiveRegs || !LiveRegs[rx]) return; @@ -211,7 +213,7 @@ } /// Force register rx into domain. -void SSEDomainFixPass::Force(int rx, unsigned domain) { +void ExeDepsFix::Force(int rx, unsigned domain) { assert(unsigned(rx) < NumRegs && "Invalid index"); DomainValue *dv; if (LiveRegs && (dv = LiveRegs[rx])) { @@ -220,8 +222,8 @@ else if (dv->hasDomain(domain)) Collapse(dv, domain); else { - // This is an incompatible open DomainValue. Collapse it to whatever and force - // the new value into domain. This costs a domain crossing. + // This is an incompatible open DomainValue. Collapse it to whatever and + // force the new value into domain. This costs a domain crossing. Collapse(dv, dv->getFirstDomain()); assert(LiveRegs[rx] && "Not live after collapse?"); LiveRegs[rx]->addDomain(domain); @@ -234,7 +236,7 @@ /// Collapse open DomainValue into given domain. If there are multiple /// registers using dv, they each get a unique collapsed DomainValue. -void SSEDomainFixPass::Collapse(DomainValue *dv, unsigned domain) { +void ExeDepsFix::Collapse(DomainValue *dv, unsigned domain) { assert(dv->hasDomain(domain) && "Cannot collapse"); // Collapse all the instructions. @@ -251,7 +253,7 @@ /// Merge - All instructions and registers in B are moved to A, and B is /// released. -bool SSEDomainFixPass::Merge(DomainValue *A, DomainValue *B) { +bool ExeDepsFix::Merge(DomainValue *A, DomainValue *B) { assert(!A->isCollapsed() && "Cannot merge into collapsed"); assert(!B->isCollapsed() && "Cannot merge from collapsed"); if (A == B) @@ -269,7 +271,7 @@ return true; } -void SSEDomainFixPass::enterBasicBlock() { +void ExeDepsFix::enterBasicBlock() { // Try to coalesce live-out registers from predecessors. for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(), e = MBB->livein_end(); i != e; ++i) { @@ -306,7 +308,7 @@ // A hard instruction only works in one domain. All input registers will be // forced into that domain. -void SSEDomainFixPass::visitHardInstr(MachineInstr *mi, unsigned domain) { +void ExeDepsFix::visitHardInstr(MachineInstr *mi, unsigned domain) { // Collapse all uses. for (unsigned i = mi->getDesc().getNumDefs(), e = mi->getDesc().getNumOperands(); i != e; ++i) { @@ -329,7 +331,7 @@ } // A soft instruction can be changed to work in other domains given by mask. -void SSEDomainFixPass::visitSoftInstr(MachineInstr *mi, unsigned mask) { +void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) { // Bitmask of available domains for this instruction after taking collapsed // operands into account. unsigned available = mask; @@ -434,8 +436,8 @@ } } -void SSEDomainFixPass::visitGenericInstr(MachineInstr *mi) { - // Process explicit defs, kill any XMM registers redefined. +void ExeDepsFix::visitGenericInstr(MachineInstr *mi) { + // Process explicit defs, kill any relevant registers redefined. for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { MachineOperand &mo = mi->getOperand(i); if (!mo.isReg()) continue; @@ -445,7 +447,7 @@ } } -bool SSEDomainFixPass::runOnMachineFunction(MachineFunction &mf) { +bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) { MF = &mf; TII = MF->getTarget().getInstrInfo(); TRI = MF->getTarget().getRegisterInfo(); @@ -454,7 +456,8 @@ Distance = 0; assert(NumRegs == RC->getNumRegs() && "Bad regclass"); - // If no XMM registers are used in the function, we can skip it completely. + // If no relevant registers are used in the function, we can skip it + // completely. bool anyregs = false; for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end(); I != E; ++I) @@ -516,5 +519,5 @@ FunctionPass * llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) { - return new SSEDomainFixPass(RC); + return new ExeDepsFix(RC); } From geek4civic at gmail.com Tue Sep 27 19:12:48 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 28 Sep 2011 09:12:48 +0900 Subject: [llvm-commits] [llvm] r140616 - in /llvm/trunk/lib/Target/PTX: PTXAsmPrinter.cpp PTXISelDAGToDAG.cpp PTXISelLowering.cpp PTXInstrLoadStore.td PTXMachineFunctionInfo.h PTXRegisterInfo.cpp In-Reply-To: <20110927181256.0C1572A6C12C@llvm.org> References: <20110927181256.0C1572A6C12C@llvm.org> Message-ID: lJustin, > + ? ? ?std::string ParamName = PM.getParamName(Param); > + ? ? ?SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MVT::Other); ParamName.c_str() might be escaped, I guess. It causes undefined behavior on msvc. As dirty hack, to tweak them (4 points) as strdup(ParamName.c_str()), it could be suppressed. ...Takumi From eli.friedman at gmail.com Tue Sep 27 19:34:28 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 28 Sep 2011 00:34:28 -0000 Subject: [llvm-commits] [llvm] r140666 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/modref.ll Message-ID: <20110928003428.193FF2A6C12C@llvm.org> Author: efriedma Date: Tue Sep 27 19:34:27 2011 New Revision: 140666 URL: http://llvm.org/viewvc/llvm-project?rev=140666&view=rev Log: PR10628: Fix getModRefInfo so it queries the underlying alias() implementation correctly while checking nocapture calls. Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/test/Analysis/BasicAA/modref.ll Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=140666&r1=140665&r2=140666&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Sep 27 19:34:27 2011 @@ -714,7 +714,7 @@ // is impossible to alias the pointer we're checking. If not, we have to // assume that the call could touch the pointer, even though it doesn't // escape. - if (!isNoAlias(Location(cast(CI)), Loc)) { + if (!isNoAlias(Location(*CI), Location(Object))) { PassedAsArg = true; break; } Modified: llvm/trunk/test/Analysis/BasicAA/modref.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/modref.ll?rev=140666&r1=140665&r2=140666&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/modref.ll (original) +++ llvm/trunk/test/Analysis/BasicAA/modref.ll Tue Sep 27 19:34:27 2011 @@ -129,8 +129,23 @@ ; CHECK: ret } +; PR10628 +declare void @test7decl(i32* nocapture %x) +define i32 @test7() nounwind uwtable ssp { +entry: + %x = alloca i32, align 4 + store i32 0, i32* %x, align 4 + %add.ptr = getelementptr inbounds i32* %x, i64 1 + call void @test7decl(i32* %add.ptr) + %tmp = load i32* %x, align 4 + ret i32 %tmp +; CHECK: @test7( +; CHECK: store i32 0 +; CHECK: call void @test7decl +; CHECK: load i32* +} + declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind declare void @llvm.memset.p0i8.i8(i8* nocapture, i8, i8, i32, i1) nounwind declare void @llvm.memcpy.p0i8.p0i8.i8(i8* nocapture, i8* nocapture, i8, i32, i1) nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind - From pdox at google.com Tue Sep 27 20:36:23 2011 From: pdox at google.com (David Meyer) Date: Tue, 27 Sep 2011 18:36:23 -0700 Subject: [llvm-commits] [llvm] r139125 - in /llvm/trunk/lib/Target: ARM/ARM.td ARM/ARMInstrInfo.td ARM/ARMSubtarget.cpp ARM/ARMSubtarget.h ARM/MCTargetDesc/ARMMCTargetDesc.cpp X86/MCTargetDesc/X86MCTargetDesc.cpp X86/X86.td X86/X86InstrInfo.td X86/X86Subt In-Reply-To: References: Message-ID: Hello, I'm sorry, I did not see this thread earlier. The original reason for adding "NaClMode" was because we needed an AssemblerPredicate so that we could disable some MnemonicAlias's in the assembler for NaCl. Because NaCl on X86-64 implies 32-bit pointers, certain aliases no longer make sense. (like call -> callq) In retrospect, this is not terribly important. I think we can live without it. Attached is a patch to remove it. Let me know if it's ok to commit. - pdox -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110927/60cd9536/attachment-0001.html -------------- next part -------------- A non-text attachment was scrubbed... Name: naclmode.patch Type: text/x-patch Size: 6516 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110927/60cd9536/attachment-0001.bin From atrick at apple.com Tue Sep 27 20:35:36 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 28 Sep 2011 01:35:36 -0000 Subject: [llvm-commits] [llvm] r140670 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110928013536.96E4C2A6C12C@llvm.org> Author: atrick Date: Tue Sep 27 20:35:36 2011 New Revision: 140670 URL: http://llvm.org/viewvc/llvm-project?rev=140670&view=rev Log: indvars should hoist [sz]ext because licm is not rerun. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=140670&r1=140669&r2=140670&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Sep 27 20:35:36 2011 @@ -834,6 +834,9 @@ PHINode *CreateWideIV(SCEVExpander &Rewriter); protected: + Value *getExtend(Value *NarrowOper, Type *WideType, bool IsSigned, + Instruction *Use); + Instruction *CloneIVUser(NarrowIVDefUse DU); const SCEVAddRecExpr *GetWideRecurrence(Instruction *NarrowUse); @@ -846,8 +849,27 @@ }; } // anonymous namespace -static Value *getExtend( Value *NarrowOper, Type *WideType, - bool IsSigned, IRBuilder<> &Builder) { +/// isLoopInvariant - Perform a quick domtree based check for loop invariance +/// assuming that V is used within the loop. LoopInfo::isLoopInvariant() seems +/// gratuitous for this purpose. +static bool isLoopInvariant(Value *V, const Loop *L, const DominatorTree *DT) { + Instruction *Inst = dyn_cast(V); + if (!Inst) + return true; + + return DT->properlyDominates(Inst->getParent(), L->getHeader()); +} + +Value *WidenIV::getExtend(Value *NarrowOper, Type *WideType, bool IsSigned, + Instruction *Use) { + // Set the debug location and conservative insertion point. + IRBuilder<> Builder(Use); + // Hoist the insertion point into loop preheaders as far as possible. + for (const Loop *L = LI->getLoopFor(Use->getParent()); + L && L->getLoopPreheader() && isLoopInvariant(NarrowOper, L, DT); + L = L->getParentLoop()) + Builder.SetInsertPoint(L->getLoopPreheader()->getTerminator()); + return IsSigned ? Builder.CreateSExt(NarrowOper, WideType) : Builder.CreateZExt(NarrowOper, WideType); } @@ -872,22 +894,21 @@ case Instruction::AShr: DEBUG(dbgs() << "Cloning IVUser: " << *DU.NarrowUse << "\n"); - IRBuilder<> Builder(DU.NarrowUse); - // Replace NarrowDef operands with WideDef. Otherwise, we don't know // anything about the narrow operand yet so must insert a [sz]ext. It is // probably loop invariant and will be folded or hoisted. If it actually // comes from a widened IV, it should be removed during a future call to // WidenIVUse. Value *LHS = (DU.NarrowUse->getOperand(0) == DU.NarrowDef) ? DU.WideDef : - getExtend(DU.NarrowUse->getOperand(0), WideType, IsSigned, Builder); + getExtend(DU.NarrowUse->getOperand(0), WideType, IsSigned, DU.NarrowUse); Value *RHS = (DU.NarrowUse->getOperand(1) == DU.NarrowDef) ? DU.WideDef : - getExtend(DU.NarrowUse->getOperand(1), WideType, IsSigned, Builder); + getExtend(DU.NarrowUse->getOperand(1), WideType, IsSigned, DU.NarrowUse); BinaryOperator *NarrowBO = cast(DU.NarrowUse); BinaryOperator *WideBO = BinaryOperator::Create(NarrowBO->getOpcode(), LHS, RHS, NarrowBO->getName()); + IRBuilder<> Builder(DU.NarrowUse); Builder.Insert(WideBO); if (const OverflowingBinaryOperator *OBO = dyn_cast(NarrowBO)) { @@ -1391,17 +1412,6 @@ return Ty; } -/// isLoopInvariant - Perform a quick domtree based check for loop invariance -/// assuming that V is used within the loop. LoopInfo::isLoopInvariant() seems -/// gratuitous for this purpose. -static bool isLoopInvariant(Value *V, Loop *L, DominatorTree *DT) { - Instruction *Inst = dyn_cast(V); - if (!Inst) - return true; - - return DT->properlyDominates(Inst->getParent(), L->getHeader()); -} - /// getLoopPhiForCounter - Return the loop header phi IFF IncV adds a loop /// invariant value to the phi. static PHINode *getLoopPhiForCounter(Value *IncV, Loop *L, DominatorTree *DT) { From zwarich at apple.com Tue Sep 27 20:51:07 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Tue, 27 Sep 2011 18:51:07 -0700 Subject: [llvm-commits] [llvm] r140670 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp In-Reply-To: <20110928013536.96E4C2A6C12C@llvm.org> References: <20110928013536.96E4C2A6C12C@llvm.org> Message-ID: Test case? Cameron On Sep 27, 2011, at 6:35 PM, Andrew Trick wrote: > Author: atrick > Date: Tue Sep 27 20:35:36 2011 > New Revision: 140670 > > URL: http://llvm.org/viewvc/llvm-project?rev=140670&view=rev > Log: > indvars should hoist [sz]ext because licm is not rerun. > > Modified: > llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp > > Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=140670&r1=140669&r2=140670&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Sep 27 20:35:36 2011 > @@ -834,6 +834,9 @@ > PHINode *CreateWideIV(SCEVExpander &Rewriter); > > protected: > + Value *getExtend(Value *NarrowOper, Type *WideType, bool IsSigned, > + Instruction *Use); > + > Instruction *CloneIVUser(NarrowIVDefUse DU); > > const SCEVAddRecExpr *GetWideRecurrence(Instruction *NarrowUse); > @@ -846,8 +849,27 @@ > }; > } // anonymous namespace > > -static Value *getExtend( Value *NarrowOper, Type *WideType, > - bool IsSigned, IRBuilder<> &Builder) { > +/// isLoopInvariant - Perform a quick domtree based check for loop invariance > +/// assuming that V is used within the loop. LoopInfo::isLoopInvariant() seems > +/// gratuitous for this purpose. > +static bool isLoopInvariant(Value *V, const Loop *L, const DominatorTree *DT) { > + Instruction *Inst = dyn_cast(V); > + if (!Inst) > + return true; > + > + return DT->properlyDominates(Inst->getParent(), L->getHeader()); > +} > + > +Value *WidenIV::getExtend(Value *NarrowOper, Type *WideType, bool IsSigned, > + Instruction *Use) { > + // Set the debug location and conservative insertion point. > + IRBuilder<> Builder(Use); > + // Hoist the insertion point into loop preheaders as far as possible. > + for (const Loop *L = LI->getLoopFor(Use->getParent()); > + L && L->getLoopPreheader() && isLoopInvariant(NarrowOper, L, DT); > + L = L->getParentLoop()) > + Builder.SetInsertPoint(L->getLoopPreheader()->getTerminator()); > + > return IsSigned ? Builder.CreateSExt(NarrowOper, WideType) : > Builder.CreateZExt(NarrowOper, WideType); > } > @@ -872,22 +894,21 @@ > case Instruction::AShr: > DEBUG(dbgs() << "Cloning IVUser: " << *DU.NarrowUse << "\n"); > > - IRBuilder<> Builder(DU.NarrowUse); > - > // Replace NarrowDef operands with WideDef. Otherwise, we don't know > // anything about the narrow operand yet so must insert a [sz]ext. It is > // probably loop invariant and will be folded or hoisted. If it actually > // comes from a widened IV, it should be removed during a future call to > // WidenIVUse. > Value *LHS = (DU.NarrowUse->getOperand(0) == DU.NarrowDef) ? DU.WideDef : > - getExtend(DU.NarrowUse->getOperand(0), WideType, IsSigned, Builder); > + getExtend(DU.NarrowUse->getOperand(0), WideType, IsSigned, DU.NarrowUse); > Value *RHS = (DU.NarrowUse->getOperand(1) == DU.NarrowDef) ? DU.WideDef : > - getExtend(DU.NarrowUse->getOperand(1), WideType, IsSigned, Builder); > + getExtend(DU.NarrowUse->getOperand(1), WideType, IsSigned, DU.NarrowUse); > > BinaryOperator *NarrowBO = cast(DU.NarrowUse); > BinaryOperator *WideBO = BinaryOperator::Create(NarrowBO->getOpcode(), > LHS, RHS, > NarrowBO->getName()); > + IRBuilder<> Builder(DU.NarrowUse); > Builder.Insert(WideBO); > if (const OverflowingBinaryOperator *OBO = > dyn_cast(NarrowBO)) { > @@ -1391,17 +1412,6 @@ > return Ty; > } > > -/// isLoopInvariant - Perform a quick domtree based check for loop invariance > -/// assuming that V is used within the loop. LoopInfo::isLoopInvariant() seems > -/// gratuitous for this purpose. > -static bool isLoopInvariant(Value *V, Loop *L, DominatorTree *DT) { > - Instruction *Inst = dyn_cast(V); > - if (!Inst) > - return true; > - > - return DT->properlyDominates(Inst->getParent(), L->getHeader()); > -} > - > /// getLoopPhiForCounter - Return the loop header phi IFF IncV adds a loop > /// invariant value to the phi. > static PHINode *getLoopPhiForCounter(Value *IncV, Loop *L, DominatorTree *DT) { > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From atrick at apple.com Tue Sep 27 21:13:32 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 28 Sep 2011 02:13:32 -0000 Subject: [llvm-commits] [llvm] r140671 - /llvm/trunk/test/Transforms/IndVarSimplify/2011-09-27-hoistsext.ll Message-ID: <20110928021332.B095A2A6C12C@llvm.org> Author: atrick Date: Tue Sep 27 21:13:32 2011 New Revision: 140671 URL: http://llvm.org/viewvc/llvm-project?rev=140671&view=rev Log: Test case for r140670: indvars should hoist sext. Added: llvm/trunk/test/Transforms/IndVarSimplify/2011-09-27-hoistsext.ll Added: llvm/trunk/test/Transforms/IndVarSimplify/2011-09-27-hoistsext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2011-09-27-hoistsext.ll?rev=140671&view=auto ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/2011-09-27-hoistsext.ll (added) +++ llvm/trunk/test/Transforms/IndVarSimplify/2011-09-27-hoistsext.ll Tue Sep 27 21:13:32 2011 @@ -0,0 +1,28 @@ +; RUN: opt < %s -indvars -S | FileCheck %s +; Test indvars' ability to hoist new sext created by WidenIV. +; From ffbench. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +define internal double @fourn(double* %data, i32 %x, i32 %y, i32 %n) nounwind { +; CHECK: entry: +; CHECK: sext +; CHECK: sext +entry: + br label %for.body + +; CHECK: for.body: +; CHECK-NOT: sext +; CHECK: br +for.body: + %i2.115 = phi i32 [ 0, %entry ], [ %add249, %for.body ] + %add174 = add nsw i32 %i2.115, %x + %idxprom177 = sext i32 %add174 to i64 + %arrayidx179 = getelementptr inbounds double* %data, i64 %idxprom177 + %tmp180 = load double* %arrayidx179, align 8 + %add249 = add nsw i32 %i2.115, %y + %cmp168 = icmp sgt i32 %add249, %n + br i1 %cmp168, label %exit, label %for.body + +exit: + ret double %tmp180 +} From atrick at apple.com Tue Sep 27 21:15:40 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 27 Sep 2011 19:15:40 -0700 Subject: [llvm-commits] [llvm] r140670 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp In-Reply-To: References: <20110928013536.96E4C2A6C12C@llvm.org> Message-ID: <05B98E9A-65C9-4F95-ACB4-D0CC6BE8A337@apple.com> r140671 -Andy On Sep 27, 2011, at 6:51 PM, Cameron Zwarich wrote: > Test case? > > Cameron > > On Sep 27, 2011, at 6:35 PM, Andrew Trick wrote: > >> Author: atrick >> Date: Tue Sep 27 20:35:36 2011 >> New Revision: 140670 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=140670&view=rev >> Log: >> indvars should hoist [sz]ext because licm is not rerun. >> >> Modified: >> llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp >> >> Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=140670&r1=140669&r2=140670&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) >> +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Sep 27 20:35:36 2011 >> @@ -834,6 +834,9 @@ >> PHINode *CreateWideIV(SCEVExpander &Rewriter); >> >> protected: >> + Value *getExtend(Value *NarrowOper, Type *WideType, bool IsSigned, >> + Instruction *Use); >> + >> Instruction *CloneIVUser(NarrowIVDefUse DU); >> >> const SCEVAddRecExpr *GetWideRecurrence(Instruction *NarrowUse); >> @@ -846,8 +849,27 @@ >> }; >> } // anonymous namespace >> >> -static Value *getExtend( Value *NarrowOper, Type *WideType, >> - bool IsSigned, IRBuilder<> &Builder) { >> +/// isLoopInvariant - Perform a quick domtree based check for loop invariance >> +/// assuming that V is used within the loop. LoopInfo::isLoopInvariant() seems >> +/// gratuitous for this purpose. >> +static bool isLoopInvariant(Value *V, const Loop *L, const DominatorTree *DT) { >> + Instruction *Inst = dyn_cast(V); >> + if (!Inst) >> + return true; >> + >> + return DT->properlyDominates(Inst->getParent(), L->getHeader()); >> +} >> + >> +Value *WidenIV::getExtend(Value *NarrowOper, Type *WideType, bool IsSigned, >> + Instruction *Use) { >> + // Set the debug location and conservative insertion point. >> + IRBuilder<> Builder(Use); >> + // Hoist the insertion point into loop preheaders as far as possible. >> + for (const Loop *L = LI->getLoopFor(Use->getParent()); >> + L && L->getLoopPreheader() && isLoopInvariant(NarrowOper, L, DT); >> + L = L->getParentLoop()) >> + Builder.SetInsertPoint(L->getLoopPreheader()->getTerminator()); >> + >> return IsSigned ? Builder.CreateSExt(NarrowOper, WideType) : >> Builder.CreateZExt(NarrowOper, WideType); >> } >> @@ -872,22 +894,21 @@ >> case Instruction::AShr: >> DEBUG(dbgs() << "Cloning IVUser: " << *DU.NarrowUse << "\n"); >> >> - IRBuilder<> Builder(DU.NarrowUse); >> - >> // Replace NarrowDef operands with WideDef. Otherwise, we don't know >> // anything about the narrow operand yet so must insert a [sz]ext. It is >> // probably loop invariant and will be folded or hoisted. If it actually >> // comes from a widened IV, it should be removed during a future call to >> // WidenIVUse. >> Value *LHS = (DU.NarrowUse->getOperand(0) == DU.NarrowDef) ? DU.WideDef : >> - getExtend(DU.NarrowUse->getOperand(0), WideType, IsSigned, Builder); >> + getExtend(DU.NarrowUse->getOperand(0), WideType, IsSigned, DU.NarrowUse); >> Value *RHS = (DU.NarrowUse->getOperand(1) == DU.NarrowDef) ? DU.WideDef : >> - getExtend(DU.NarrowUse->getOperand(1), WideType, IsSigned, Builder); >> + getExtend(DU.NarrowUse->getOperand(1), WideType, IsSigned, DU.NarrowUse); >> >> BinaryOperator *NarrowBO = cast(DU.NarrowUse); >> BinaryOperator *WideBO = BinaryOperator::Create(NarrowBO->getOpcode(), >> LHS, RHS, >> NarrowBO->getName()); >> + IRBuilder<> Builder(DU.NarrowUse); >> Builder.Insert(WideBO); >> if (const OverflowingBinaryOperator *OBO = >> dyn_cast(NarrowBO)) { >> @@ -1391,17 +1412,6 @@ >> return Ty; >> } >> >> -/// isLoopInvariant - Perform a quick domtree based check for loop invariance >> -/// assuming that V is used within the loop. LoopInfo::isLoopInvariant() seems >> -/// gratuitous for this purpose. >> -static bool isLoopInvariant(Value *V, Loop *L, DominatorTree *DT) { >> - Instruction *Inst = dyn_cast(V); >> - if (!Inst) >> - return true; >> - >> - return DT->properlyDominates(Inst->getParent(), L->getHeader()); >> -} >> - >> /// getLoopPhiForCounter - Return the loop header phi IFF IncV adds a loop >> /// invariant value to the phi. >> static PHINode *getLoopPhiForCounter(Value *IncV, Loop *L, DominatorTree *DT) { >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Tue Sep 27 22:07:34 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 28 Sep 2011 03:07:34 -0000 Subject: [llvm-commits] [llvm] r140674 - /llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Message-ID: <20110928030735.042442A6C12C@llvm.org> Author: void Date: Tue Sep 27 22:07:34 2011 New Revision: 140674 URL: http://llvm.org/viewvc/llvm-project?rev=140674&view=rev Log: Don't conditionalize execution of the SjLj EH prepare pass. We may need an SjLj EH preparation pass for some call site information, at least in the short term. Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=140674&r1=140673&r2=140674&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Tue Sep 27 22:07:34 2011 @@ -45,9 +45,6 @@ bool EnableFastISel; } -static cl::opt DisableOldSjLjEH("disable-old-sjlj-eh", cl::Hidden, - cl::desc("Disable the old SjLj EH preparation pass")); - static cl::opt DisablePostRA("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc")); static cl::opt DisableBranchFold("disable-branch-fold", cl::Hidden, @@ -325,8 +322,7 @@ // removed from the parent invoke(s). This could happen when a landing // pad is shared by multiple invokes and is also a target of a normal // edge from elsewhere. - if (!DisableOldSjLjEH) - PM.add(createSjLjEHPass(getTargetLowering())); + PM.add(createSjLjEHPass(getTargetLowering())); // FALLTHROUGH case ExceptionHandling::DwarfCFI: case ExceptionHandling::ARM: From isanbard at gmail.com Tue Sep 27 22:14:06 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 28 Sep 2011 03:14:06 -0000 Subject: [llvm-commits] [llvm] r140675 - /llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Message-ID: <20110928031406.154DA2A6C12C@llvm.org> Author: void Date: Tue Sep 27 22:14:05 2011 New Revision: 140675 URL: http://llvm.org/viewvc/llvm-project?rev=140675&view=rev Log: In the new EH model, setup the function context and the call site info. The DWARF exception pass uses the call site information, which is set up here. A pre-RA pass is too late for it to use this information. So create and setup the function context here, and then insert the call site values here (and map the call sites for the DWARF EH pass). This is simpler than the original pass, and doesn't make the CFG lose its SSA-ness. It's a win-win-win-win-lose-win-win situation. Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=140675&r1=140674&r2=140675&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Tue Sep 27 22:14:05 2011 @@ -22,16 +22,22 @@ #include "llvm/Module.h" #include "llvm/Pass.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/Local.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/IRBuilder.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include using namespace llvm; +static cl::opt DisableOldSjLjEH("disable-old-sjlj-eh", cl::Hidden, + cl::desc("Disable the old SjLj EH preparation pass")); + STATISTIC(NumInvokes, "Number of invokes replaced"); STATISTIC(NumUnwinds, "Number of unwinds replaced"); STATISTIC(NumSpilled, "Number of registers live across unwind edges"); @@ -67,6 +73,9 @@ } private: + bool setupEntryBlockAndCallSites(Function &F); + void setupFunctionContext(Function &F, ArrayRef LPads); + void insertCallSiteStore(Instruction *I, int Number, Value *CallSite); void markInvokeCallSite(InvokeInst *II, int InvokeNo, Value *CallSite, SwitchInst *CatchSwitch); @@ -698,7 +707,178 @@ return true; } +/// setupFunctionContext - Allocate the function context on the stack and fill +/// it with all of the data that we know at this point. +void SjLjEHPass::setupFunctionContext(Function &F, + ArrayRef LPads) { + BasicBlock *EntryBB = F.begin(); + + // Create an alloca for the incoming jump buffer ptr and the new jump buffer + // that needs to be restored on all exits from the function. This is an alloca + // because the value needs to be added to the global context list. + unsigned Align = + TLI->getTargetData()->getPrefTypeAlignment(FunctionContextTy); + AllocaInst *FuncCtx = + new AllocaInst(FunctionContextTy, 0, Align, "fn_context", EntryBB->begin()); + + // Fill in the function context structure. + Value *Idxs[2]; + Type *Int32Ty = Type::getInt32Ty(F.getContext()); + Value *Zero = ConstantInt::get(Int32Ty, 0); + Value *One = ConstantInt::get(Int32Ty, 1); + + // Keep around a reference to the call_site field. + Idxs[0] = Zero; + Idxs[1] = One; + CallSite = GetElementPtrInst::Create(FuncCtx, Idxs, "call_site", + EntryBB->getTerminator()); + + // Reference the __data field. + Idxs[1] = ConstantInt::get(Int32Ty, 2); + Value *FCData = GetElementPtrInst::Create(FuncCtx, Idxs, "__data", + EntryBB->getTerminator()); + + // The exception value comes back in context->__data[0]. + Idxs[1] = Zero; + Value *ExceptionAddr = GetElementPtrInst::Create(FCData, Idxs, + "exception_gep", + EntryBB->getTerminator()); + + // The exception selector comes back in context->__data[1]. + Idxs[1] = One; + Value *SelectorAddr = GetElementPtrInst::Create(FCData, Idxs, + "exn_selector_gep", + EntryBB->getTerminator()); + + for (unsigned I = 0, E = LPads.size(); I != E; ++I) { + LandingPadInst *LPI = LPads[I]; + IRBuilder<> Builder(LPI->getParent()->getFirstInsertionPt()); + + Value *ExnVal = Builder.CreateLoad(ExceptionAddr, true, "exn_val"); + ExnVal = Builder.CreateIntToPtr(ExnVal, Type::getInt8PtrTy(F.getContext())); + Value *SelVal = Builder.CreateLoad(SelectorAddr, true, "exn_selector_val"); + + Type *LPadType = LPI->getType(); + Value *LPadVal = UndefValue::get(LPadType); + LPadVal = Builder.CreateInsertValue(LPadVal, ExnVal, 0, "lpad.val"); + LPadVal = Builder.CreateInsertValue(LPadVal, SelVal, 1, "lpad.val"); + + LPI->replaceAllUsesWith(LPadVal); + } + + // Personality function + Idxs[1] = ConstantInt::get(Int32Ty, 3); + if (!PersonalityFn) + PersonalityFn = LPads[0]->getPersonalityFn(); + Value *PersonalityFieldPtr = + GetElementPtrInst::Create(FuncCtx, Idxs, "pers_fn_gep", + EntryBB->getTerminator()); + new StoreInst(PersonalityFn, PersonalityFieldPtr, true, + EntryBB->getTerminator()); + + // LSDA address + Idxs[1] = ConstantInt::get(Int32Ty, 4); + Value *LSDAFieldPtr = + GetElementPtrInst::Create(FuncCtx, Idxs, "lsda_gep", + EntryBB->getTerminator()); + Value *LSDA = CallInst::Create(LSDAAddrFn, "lsda_addr", + EntryBB->getTerminator()); + new StoreInst(LSDA, LSDAFieldPtr, true, EntryBB->getTerminator()); + + // Get a reference to the jump buffer. + Idxs[1] = ConstantInt::get(Int32Ty, 5); + Value *JBufPtr = + GetElementPtrInst::Create(FuncCtx, Idxs, "jbuf_gep", + EntryBB->getTerminator()); + Idxs[1] = Zero; + Value *FramePtr = + GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_fp_gep", + EntryBB->getTerminator()); + + // Save the frame pointer. + Value *Val = CallInst::Create(FrameAddrFn, + ConstantInt::get(Int32Ty, 0), + "fp", + EntryBB->getTerminator()); + new StoreInst(Val, FramePtr, true, EntryBB->getTerminator()); + + // Save the stack pointer. + Idxs[1] = ConstantInt::get(Int32Ty, 2); + Value *StackPtr = + GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_sp_gep", + EntryBB->getTerminator()); + + Val = CallInst::Create(StackAddrFn, "sp", EntryBB->getTerminator()); + new StoreInst(Val, StackPtr, true, EntryBB->getTerminator()); + + // Call the setjmp instrinsic. It fills in the rest of the jmpbuf. + Value *SetjmpArg = + CastInst::Create(Instruction::BitCast, JBufPtr, + Type::getInt8PtrTy(F.getContext()), "", + EntryBB->getTerminator()); + Value *DispatchVal = CallInst::Create(BuiltinSetjmpFn, SetjmpArg, + "dispatch", + EntryBB->getTerminator()); + + // Add a call to dispatch_setup after the setjmp call. This is expanded to any + // target-specific setup that needs to be done. + CallInst::Create(DispatchSetupFn, DispatchVal, "", EntryBB->getTerminator()); +} + +/// setupEntryBlockAndCallSites - Setup the entry block by creating and filling +/// the function context and marking the call sites with the appropriate +/// values. These values are used by the DWARF EH emitter. +bool SjLjEHPass::setupEntryBlockAndCallSites(Function &F) { + SmallVector Invokes; + SmallVector LPads; + + // Look through the terminators of the basic blocks to find invokes. + for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) + if (InvokeInst *II = dyn_cast(BB->getTerminator())) { + Invokes.push_back(II); + LPads.push_back(II->getUnwindDest()->getLandingPadInst()); + } + + if (Invokes.empty()) return false; + + setupFunctionContext(F, LPads); + + // At this point, we are all set up, update the invoke instructions to mark + // their call_site values, and fill in the dispatch switch accordingly. + for (unsigned I = 0, E = Invokes.size(); I != E; ++I) { + insertCallSiteStore(Invokes[I], I + 1, CallSite); + + ConstantInt *CallSiteNum = + ConstantInt::get(Type::getInt32Ty(F.getContext()), I + 1); + + // Record the call site value for the back end so it stays associated with + // the invoke. + CallInst::Create(CallSiteFn, CallSiteNum, "", Invokes[I]); + } + + // Mark call instructions that aren't nounwind as no-action (call_site == + // -1). Skip the entry block, as prior to then, no function context has been + // created for this function and any unexpected exceptions thrown will go + // directly to the caller's context, which is what we want anyway, so no need + // to do anything here. + for (Function::iterator BB = F.begin(), E = F.end(); ++BB != E;) { + for (BasicBlock::iterator I = BB->begin(), end = BB->end(); I != end; ++I) + if (CallInst *CI = dyn_cast(I)) { + if (!CI->doesNotThrow()) + insertCallSiteStore(CI, -1, CallSite); + } else if (ResumeInst *RI = dyn_cast(I)) { + insertCallSiteStore(RI, -1, CallSite); + } + } + + return true; +} + bool SjLjEHPass::runOnFunction(Function &F) { - bool Res = insertSjLjEHSupport(F); + bool Res = false; + if (!DisableOldSjLjEH) + Res = insertSjLjEHSupport(F); + else + Res = setupEntryBlockAndCallSites(F); return Res; } From isanbard at gmail.com Tue Sep 27 22:36:43 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 28 Sep 2011 03:36:43 -0000 Subject: [llvm-commits] [llvm] r140676 - in /llvm/trunk: include/llvm/CodeGen/MachineFrameInfo.h include/llvm/Intrinsics.td lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SjLjEHPrepare.cpp Message-ID: <20110928033643.7051C2A6C12C@llvm.org> Author: void Date: Tue Sep 27 22:36:43 2011 New Revision: 140676 URL: http://llvm.org/viewvc/llvm-project?rev=140676&view=rev Log: Create and use an llvm.eh.sjlj.functioncontext intrinsic. This intrinsic is used to pass the index of the function context to the back-end for further processing. The back-end is in charge of filling in the rest of the entries. Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h llvm/trunk/include/llvm/Intrinsics.td llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h?rev=140676&r1=140675&r2=140676&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h Tue Sep 27 22:36:43 2011 @@ -174,6 +174,10 @@ /// StackProtectorIdx - The frame index for the stack protector. int StackProtectorIdx; + /// FunctionContextIdx - The frame index for the function context. Used for + /// SjLj exceptions. + int FunctionContextIdx; + /// MaxCallFrameSize - This contains the size of the largest call frame if the /// target uses frame setup/destroy pseudo instructions (as defined in the /// TargetFrameInfo class). This information is important for frame pointer @@ -220,6 +224,7 @@ AdjustsStack = false; HasCalls = false; StackProtectorIdx = -1; + FunctionContextIdx = -1; MaxCallFrameSize = 0; CSIValid = false; LocalFrameSize = 0; @@ -244,6 +249,11 @@ int getStackProtectorIndex() const { return StackProtectorIdx; } void setStackProtectorIndex(int I) { StackProtectorIdx = I; } + /// getFunctionContextIndex/setFunctionContextIndex - Return the index for the + /// function context object. This object is used for SjLj exceptions. + int getFunctionContextIndex() const { return FunctionContextIdx; } + void setFunctionContextIndex(int I) { FunctionContextIdx = I; } + /// isFrameAddressTaken - This method may be called any time after instruction /// selection is complete to determine if there is a call to /// \@llvm.frameaddress in this function. Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=140676&r1=140675&r2=140676&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Tue Sep 27 22:36:43 2011 @@ -322,12 +322,13 @@ def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>; let Properties = [IntrNoMem] in { - def int_eh_sjlj_lsda : Intrinsic<[llvm_ptr_ty]>; - def int_eh_sjlj_callsite: Intrinsic<[], [llvm_i32_ty]>; + def int_eh_sjlj_lsda : Intrinsic<[llvm_ptr_ty]>; + def int_eh_sjlj_callsite : Intrinsic<[], [llvm_i32_ty]>; + def int_eh_sjlj_functioncontext : Intrinsic<[], [llvm_ptr_ty]>; } def int_eh_sjlj_dispatch_setup : Intrinsic<[], [llvm_i32_ty]>; -def int_eh_sjlj_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>; -def int_eh_sjlj_longjmp : Intrinsic<[], [llvm_ptr_ty]>; +def int_eh_sjlj_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>; +def int_eh_sjlj_longjmp : Intrinsic<[], [llvm_ptr_ty]>; //===---------------- Generic Variable Attribute Intrinsics----------------===// // Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=140676&r1=140675&r2=140676&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Sep 27 22:36:43 2011 @@ -4754,6 +4754,14 @@ MMI.setCurrentCallSite(CI->getZExtValue()); return 0; } + case Intrinsic::eh_sjlj_functioncontext: { + // Get and store the index of the function context. + MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); + AllocaInst *FnCtx = cast(I.getArgOperand(0)); + int FI = FuncInfo.StaticAllocaMap[FnCtx]; + MFI->setFunctionContextIndex(FI); + return 0; + } case Intrinsic::eh_sjlj_setjmp: { setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), getValue(I.getArgOperand(0)))); Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=140676&r1=140675&r2=140676&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Tue Sep 27 22:36:43 2011 @@ -721,6 +721,12 @@ AllocaInst *FuncCtx = new AllocaInst(FunctionContextTy, 0, Align, "fn_context", EntryBB->begin()); + // Store a pointer to the function context so that the back-end will know + // where to look for it. + CallInst::Create(Intrinsic::getDeclaration(F.getParent(), + Intrinsic::eh_sjlj_functioncontext), + FuncCtx, "", EntryBB->getTerminator()); + // Fill in the function context structure. Value *Idxs[2]; Type *Int32Ty = Type::getInt32Ty(F.getContext()); From isanbard at gmail.com Tue Sep 27 22:47:11 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 28 Sep 2011 03:47:11 -0000 Subject: [llvm-commits] [llvm] r140677 - /llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Message-ID: <20110928034711.6E7042A6C12C@llvm.org> Author: void Date: Tue Sep 27 22:47:11 2011 New Revision: 140677 URL: http://llvm.org/viewvc/llvm-project?rev=140677&view=rev Log: Bitcast the alloca to an i8* to match the intrinsic's signature. Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=140677&r1=140676&r2=140677&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Tue Sep 27 22:47:11 2011 @@ -725,7 +725,10 @@ // where to look for it. CallInst::Create(Intrinsic::getDeclaration(F.getParent(), Intrinsic::eh_sjlj_functioncontext), - FuncCtx, "", EntryBB->getTerminator()); + CastInst::Create(Instruction::BitCast, FuncCtx, + Type::getInt8PtrTy(F.getContext()), "", + EntryBB->getTerminator()), + "", EntryBB->getTerminator()); // Fill in the function context structure. Value *Idxs[2]; From isanbard at gmail.com Tue Sep 27 22:52:41 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 28 Sep 2011 03:52:41 -0000 Subject: [llvm-commits] [llvm] r140678 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20110928035241.9FEA22A6C12C@llvm.org> Author: void Date: Tue Sep 27 22:52:41 2011 New Revision: 140678 URL: http://llvm.org/viewvc/llvm-project?rev=140678&view=rev Log: Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=140678&r1=140677&r2=140678&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Sep 27 22:52:41 2011 @@ -4757,7 +4757,8 @@ case Intrinsic::eh_sjlj_functioncontext: { // Get and store the index of the function context. MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); - AllocaInst *FnCtx = cast(I.getArgOperand(0)); + AllocaInst *FnCtx = + cast(I.getArgOperand(0)->stripPointerCasts()); int FI = FuncInfo.StaticAllocaMap[FnCtx]; MFI->setFunctionContextIndex(FI); return 0; From benny.kra at googlemail.com Tue Sep 27 23:08:02 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 28 Sep 2011 04:08:02 -0000 Subject: [llvm-commits] [llvm] r140679 - in /llvm/trunk/lib/Target/PTX: PTXISelLowering.cpp PTXParamManager.h Message-ID: <20110928040802.41C682A6C12C@llvm.org> Author: d0k Date: Tue Sep 27 23:08:02 2011 New Revision: 140679 URL: http://llvm.org/viewvc/llvm-project?rev=140679&view=rev Log: PTX: Pass param name strings per const reference. The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++) Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp llvm/trunk/lib/Target/PTX/PTXParamManager.h Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=140679&r1=140678&r2=140679&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Tue Sep 27 23:08:02 2011 @@ -225,7 +225,7 @@ unsigned ParamSize = Ins[i].VT.getStoreSizeInBits(); unsigned Param = PM.addArgumentParam(ParamSize); - std::string ParamName = PM.getParamName(Param); + const std::string &ParamName = PM.getParamName(Param); SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), MVT::Other); SDValue ArgValue = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain, @@ -322,7 +322,7 @@ if (Outs.size() == 1) { unsigned ParamSize = OutVals[0].getValueType().getSizeInBits(); unsigned Param = PM.addReturnParam(ParamSize); - std::string ParamName = PM.getParamName(Param); + const std::string &ParamName = PM.getParamName(Param); SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), MVT::Other); Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain, @@ -419,7 +419,7 @@ for (unsigned i = 0; i != OutVals.size(); ++i) { unsigned Size = OutVals[i].getValueType().getSizeInBits(); unsigned Param = PM.addLocalParam(Size); - std::string ParamName = PM.getParamName(Param); + const std::string &ParamName = PM.getParamName(Param); SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), MVT::Other); Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain, @@ -433,7 +433,7 @@ for (unsigned i = 0; i < Ins.size(); ++i) { unsigned Size = Ins[i].VT.getStoreSizeInBits(); unsigned Param = PM.addLocalParam(Size); - std::string ParamName = PM.getParamName(Param); + const std::string &ParamName = PM.getParamName(Param); SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), MVT::Other); Ops[i+1] = ParamValue; Modified: llvm/trunk/lib/Target/PTX/PTXParamManager.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXParamManager.h?rev=140679&r1=140678&r2=140679&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXParamManager.h (original) +++ llvm/trunk/lib/Target/PTX/PTXParamManager.h Tue Sep 27 23:08:02 2011 @@ -67,15 +67,15 @@ unsigned addLocalParam(unsigned Size); /// getParamName - Returns the name of the parameter as a string. - std::string getParamName(unsigned Param) const { + const std::string &getParamName(unsigned Param) const { assert(AllParams.count(Param) == 1 && "Param has not been defined!"); - return AllParams.lookup(Param).Name; + return AllParams.find(Param)->second.Name; } /// getParamSize - Returns the size of the parameter in bits. unsigned getParamSize(unsigned Param) const { assert(AllParams.count(Param) == 1 && "Param has not been defined!"); - return AllParams.lookup(Param).Size; + return AllParams.find(Param)->second.Size; } }; From benny.kra at googlemail.com Tue Sep 27 23:23:00 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 27 Sep 2011 21:23:00 -0700 Subject: [llvm-commits] [llvm] r140616 - in /llvm/trunk/lib/Target/PTX: PTXAsmPrinter.cpp PTXISelDAGToDAG.cpp PTXISelLowering.cpp PTXInstrLoadStore.td PTXMachineFunctionInfo.h PTXRegisterInfo.cpp In-Reply-To: References: <20110927181256.0C1572A6C12C@llvm.org> Message-ID: <9E9F7D7B-9288-4CD2-A744-38974C12CC18@googlemail.com> On 27.09.2011, at 17:12, NAKAMURA Takumi wrote: > lJustin, > >> + std::string ParamName = PM.getParamName(Param); >> + SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), >> + MVT::Other); > > ParamName.c_str() might be escaped, I guess. > It causes undefined behavior on msvc. > > As dirty hack, to tweak them (4 points) as strdup(ParamName.c_str()), > it could be suppressed. Fixed (without dirty hacks) in r140679. - Ben From benny.kra at googlemail.com Tue Sep 27 23:32:37 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 28 Sep 2011 04:32:37 -0000 Subject: [llvm-commits] [llvm] r140680 - /llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Message-ID: <20110928043237.250CD2A6C12C@llvm.org> Author: d0k Date: Tue Sep 27 23:32:36 2011 New Revision: 140680 URL: http://llvm.org/viewvc/llvm-project?rev=140680&view=rev Log: PTX: Simplify code. No functionality change. Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=140680&r1=140679&r2=140680&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Tue Sep 27 23:32:36 2011 @@ -399,19 +399,11 @@ Ops[0] = Chain; // Identify the callee function - if (GlobalAddressSDNode *G = dyn_cast(Callee)) { - const GlobalValue *GV = G->getGlobal(); - if (const Function *F = dyn_cast(GV)) { - assert(F->getCallingConv() == CallingConv::PTX_Device && - "PTX function calls must be to PTX device functions"); - Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy()); - Ops[Ins.size()+1] = Callee; - } else { - assert(false && "GlobalValue is not a function"); - } - } else { - assert(false && "Function must be a GlobalAddressSDNode"); - } + const GlobalValue *GV = cast(Callee)->getGlobal(); + assert(cast(GV)->getCallingConv() == CallingConv::PTX_Device && + "PTX function calls must be to PTX device functions"); + Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy()); + Ops[Ins.size()+1] = Callee; // Generate STORE_PARAM nodes for each function argument. In PTX, function // arguments are explicitly stored into .param variables and passed as From ahatanaka at mips.com Tue Sep 27 18:55:37 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Tue, 27 Sep 2011 23:55:37 -0000 Subject: [llvm-commits] [llvm] r140661 - /llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Message-ID: <20110927235537.2AEDF2A6C12C@llvm.org> Author: ahatanak Date: Tue Sep 27 18:55:37 2011 New Revision: 140661 URL: http://llvm.org/viewvc/llvm-project?rev=140661&view=rev Log: Remove MipsFPRound. Mips1 is no longer supported. Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=140661&r1=140660&r2=140661&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Tue Sep 27 18:55:37 2011 @@ -40,7 +40,6 @@ def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; -def MipsFPRound : SDNode<"MipsISD::FPRound", SDTFPRoundOp, [SDNPOptInGlue]>; def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, [SDNPHasChain, SDNPOptInGlue]>; def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; @@ -367,6 +366,3 @@ def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>; } -// MipsFPRound is only emitted for MipsI targets. -def : Pat<(f32 (MipsFPRound AFGR64:$src)), (CVTW_D32 AFGR64:$src)>; - From stpworld at narod.ru Wed Sep 28 02:03:24 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Wed, 28 Sep 2011 11:03:24 +0400 Subject: [llvm-commits] [LLVM, Switch case ranges] Cleanup patch before working on switch case ranges In-Reply-To: References: <4E8216D5.7000207@narod.ru> Message-ID: <4E82C6BC.2080709@narod.ru> > On Tue, Sep 27, 2011 at 11:32 AM, Stepan Dyatkovskiy wrote: >> Hi, >> >> Please find attached the clean-up patch for the SwitchInst internals before >> working on switch case ranges (http://llvm.org/bugs/show_bug.cgi?id=1255). >> Patches for switch case ranges will follow. > > I'm not sure about the changes to > lib/Target/CppBackend/CPPBackend.cpp... it looks like it ends up doing > extra work. void CppWriter::printInstruction has mixed implementation inside. For some instructions opNames array is used: const BranchInst* br = cast(I); Out << "BranchInst::Create(" ; if (br->getNumOperands() == 3) { Out << opNames[2] << ", " << opNames[1] << ", " << opNames[0] << ", "; } else if (br->getNumOperands() == 1) { Out << opNames[0] << ", "; } else { error("Branch with 2 operands?"); } But there are also instructions for which its own interface is used: const InvokeInst* inv = cast(I); // ... // some code here // ... Out << "InvokeInst *" << iName << " = InvokeInst::Create(" << getOpName(inv->getCalledFunction()) << ", " << getOpName(inv->getNormalDest()) << ", " << getOpName(inv->getUnwindDest()) << ", " << iName << "_params, \""; SwitchInst has unclear usage of operands array. Each even operand is a Case Value and it has ConstantInt type. And each odd operand is a case destination and it has BasicBlock type. So probably it is better to use SwitchInst interface here (like for InvokeInst)? > Probably not a big deal, though. > > + for (unsigned i = 1; i< NumCases; ++i) { > + ConstantInt* CaseVal = SI.getCaseValue(i); > + Constant* NewCaseVal = ConstantExpr::getSub(cast(CaseVal), > + AddRHS); > + assert(isa(NewCaseVal)&& > + "Result of expression should be constant"); > > Slightly strange indentation here. Did you mean something like this? + for (unsigned i = 1; i< NumCases; ++i) { + ConstantInt* CaseVal = SI.getCaseValue(i); + Constant* NewCaseVal = ConstantExpr::getSub(cast(CaseVal), + AddRHS); + assert(isa(NewCaseVal)&& + "Result of expression should be constant");> > The rest of the changes look fine. > > -Eli From eli.friedman at gmail.com Wed Sep 28 02:25:42 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 28 Sep 2011 00:25:42 -0700 Subject: [llvm-commits] [LLVM, Switch case ranges] Cleanup patch before working on switch case ranges In-Reply-To: <4E82C6BC.2080709@narod.ru> References: <4E8216D5.7000207@narod.ru> <4E82C6BC.2080709@narod.ru> Message-ID: On Wed, Sep 28, 2011 at 12:03 AM, Stepan Dyatkovskiy wrote: >> On Tue, Sep 27, 2011 at 11:32 AM, Stepan Dyatkovskiy >> ?wrote: >>> >>> Hi, >>> >>> Please find attached the clean-up patch for the SwitchInst internals >>> before >>> working on switch case ranges >>> (http://llvm.org/bugs/show_bug.cgi?id=1255). >>> Patches for switch case ranges will follow. >> >> I'm not sure about the changes to >> lib/Target/CppBackend/CPPBackend.cpp... it looks like it ends up doing >> extra work. > > void CppWriter::printInstruction has mixed implementation inside. For some > instructions opNames array is used: > > ? ?const BranchInst* br = cast(I); > ? ?Out << "BranchInst::Create(" ; > ? ?if (br->getNumOperands() == 3) { > ? ? ?Out << opNames[2] << ", " > ? ? ? ? ?<< opNames[1] << ", " > ? ? ? ? ?<< opNames[0] << ", "; > > ? ?} else if (br->getNumOperands() == 1) { > ? ? ?Out << opNames[0] << ", "; > ? ?} else { > ? ? ?error("Branch with 2 operands?"); > ? ?} > > But there are also instructions for which its own interface is used: > ?const InvokeInst* inv = cast(I); > ?// ... > ?// some code here > ?// ... > ?Out << "InvokeInst *" << iName << " = InvokeInst::Create(" > ? ? ? ?<< getOpName(inv->getCalledFunction()) << ", " > ? ? ? ?<< getOpName(inv->getNormalDest()) << ", " > ? ? ? ?<< getOpName(inv->getUnwindDest()) << ", " > ? ? ? ?<< iName << "_params, \""; > > SwitchInst has unclear usage of operands array. Each even operand is a Case > Value and it has ConstantInt type. And each odd operand is a case > destination and it has BasicBlock type. So probably it is better to use > SwitchInst interface here (like for InvokeInst)? Okay; this isn't really performance-sensitive code. >> Probably not a big deal, though. >> >> + ? ? ? ?for (unsigned i = 1; i< ?NumCases; ++i) { >> + ? ? ? ? ?ConstantInt* CaseVal = SI.getCaseValue(i); >> + ? ? ? ? ?Constant* NewCaseVal = >> ConstantExpr::getSub(cast(CaseVal), >> + ? ? ? ? ? ? ?AddRHS); >> + ? ? ? ? ?assert(isa(NewCaseVal)&& >> + ? ? ? ? ? ? ?"Result of expression should be constant"); >> >> Slightly strange indentation here. > > Did you mean something like this? > > + ? ? ? ?for (unsigned i = 1; i< ?NumCases; ++i) { > + ? ? ? ? ?ConstantInt* CaseVal = SI.getCaseValue(i); > + ? ? ? ? ?Constant* NewCaseVal = > ConstantExpr::getSub(cast(CaseVal), > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?AddRHS); > + ? ? ? ? ?assert(isa(NewCaseVal)&& > + ? ? ? ? ? ? ? ? "Result of expression should be constant");> Yes. -Eli From stpworld at narod.ru Wed Sep 28 03:22:02 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Wed, 28 Sep 2011 12:22:02 +0400 Subject: [llvm-commits] [LLVM, Switch case ranges] Cleanup patch before working on switch case ranges In-Reply-To: References: <4E8216D5.7000207@narod.ru> <4E82C6BC.2080709@narod.ru> Message-ID: <4E82D92A.8060102@narod.ru> Hi, Please find the fixed patch. Regards, Stepan. Eli Friedman wrote: > On Wed, Sep 28, 2011 at 12:03 AM, Stepan Dyatkovskiy wrote: >>> On Tue, Sep 27, 2011 at 11:32 AM, Stepan Dyatkovskiy >>> wrote: >>>> >>>> Hi, >>>> >>>> Please find attached the clean-up patch for the SwitchInst internals >>>> before >>>> working on switch case ranges >>>> (http://llvm.org/bugs/show_bug.cgi?id=1255). >>>> Patches for switch case ranges will follow. >>> >>> I'm not sure about the changes to >>> lib/Target/CppBackend/CPPBackend.cpp... it looks like it ends up doing >>> extra work. >> >> void CppWriter::printInstruction has mixed implementation inside. For some >> instructions opNames array is used: >> >> const BranchInst* br = cast(I); >> Out<< "BranchInst::Create(" ; >> if (br->getNumOperands() == 3) { >> Out<< opNames[2]<< "," >> << opNames[1]<< "," >> << opNames[0]<< ", "; >> >> } else if (br->getNumOperands() == 1) { >> Out<< opNames[0]<< ", "; >> } else { >> error("Branch with 2 operands?"); >> } >> >> But there are also instructions for which its own interface is used: >> const InvokeInst* inv = cast(I); >> // ... >> // some code here >> // ... >> Out<< "InvokeInst *"<< iName<< " = InvokeInst::Create(" >> << getOpName(inv->getCalledFunction())<< "," >> << getOpName(inv->getNormalDest())<< "," >> << getOpName(inv->getUnwindDest())<< "," >> << iName<< "_params, \""; >> >> SwitchInst has unclear usage of operands array. Each even operand is a Case >> Value and it has ConstantInt type. And each odd operand is a case >> destination and it has BasicBlock type. So probably it is better to use >> SwitchInst interface here (like for InvokeInst)? > > Okay; this isn't really performance-sensitive code. > >>> Probably not a big deal, though. >>> >>> + for (unsigned i = 1; i< NumCases; ++i) { >>> + ConstantInt* CaseVal = SI.getCaseValue(i); >>> + Constant* NewCaseVal = >>> ConstantExpr::getSub(cast(CaseVal), >>> + AddRHS); >>> + assert(isa(NewCaseVal)&& >>> + "Result of expression should be constant"); >>> >>> Slightly strange indentation here. >> >> Did you mean something like this? >> >> + for (unsigned i = 1; i< NumCases; ++i) { >> + ConstantInt* CaseVal = SI.getCaseValue(i); >> + Constant* NewCaseVal = >> ConstantExpr::getSub(cast(CaseVal), >> + AddRHS); >> + assert(isa(NewCaseVal)&& >> + "Result of expression should be constant");> > > Yes. > > -Eli -------------- next part -------------- A non-text attachment was scrubbed... Name: cr-cleanup.patch Type: text/x-patch Size: 9471 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110928/d22ab417/attachment.bin From baldrick at free.fr Wed Sep 28 04:13:03 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 28 Sep 2011 09:13:03 -0000 Subject: [llvm-commits] [llvm] r140686 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Message-ID: <20110928091303.2B4552A6C12E@llvm.org> Author: baldrick Date: Wed Sep 28 04:13:02 2011 New Revision: 140686 URL: http://llvm.org/viewvc/llvm-project?rev=140686&view=rev Log: A typeid of zero means a cleanup, not a catch. This case occurs when there is both a catch and a cleanup. Correct the comment. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=140686&r1=140685&r2=140686&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Wed Sep 28 04:13:02 2011 @@ -649,12 +649,14 @@ // Used by the runtime to match the type of the thrown exception to the // type of the catch clauses or the types in the exception specification. if (VerboseAsm) { - if (Action.ValueForTypeID >= 0) + if (Action.ValueForTypeID > 0) Asm->OutStreamer.AddComment(Twine(" Catch TypeInfo ") + llvm::itostr(Action.ValueForTypeID)); - else + else if (Action.ValueForTypeID < 0) Asm->OutStreamer.AddComment(Twine(" Filter TypeInfo ") + llvm::itostr(Action.ValueForTypeID)); + else + Asm->OutStreamer.AddComment(" Cleanup"); } Asm->EmitSLEB128(Action.ValueForTypeID); From geek4civic at gmail.com Wed Sep 28 04:23:56 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 28 Sep 2011 18:23:56 +0900 Subject: [llvm-commits] [llvm] r140616 - in /llvm/trunk/lib/Target/PTX: PTXAsmPrinter.cpp PTXISelDAGToDAG.cpp PTXISelLowering.cpp PTXInstrLoadStore.td PTXMachineFunctionInfo.h PTXRegisterInfo.cpp In-Reply-To: <9E9F7D7B-9288-4CD2-A744-38974C12CC18@googlemail.com> References: <20110927181256.0C1572A6C12C@llvm.org> <9E9F7D7B-9288-4CD2-A744-38974C12CC18@googlemail.com> Message-ID: > Fixed (without dirty hacks) in r140679. Thanks Benjamin! ...Takumi From gvenn.cfe.dev at gmail.com Wed Sep 28 05:53:56 2011 From: gvenn.cfe.dev at gmail.com (Garrison Venn) Date: Wed, 28 Sep 2011 10:53:56 -0000 Subject: [llvm-commits] [llvm] r140695 - /llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp Message-ID: <20110928105356.DAA772A6C12C@llvm.org> Author: gvenn Date: Wed Sep 28 05:53:56 2011 New Revision: 140695 URL: http://llvm.org/viewvc/llvm-project?rev=140695&view=rev Log: Changed comments on foreign C++ exceptions (generated with type info 7), handling with references to http://sourcery.mentor.com/public/cxx-abi/abi-eh.html (r 1.22). Modified: llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp Modified: llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp?rev=140695&r1=140694&r2=140695&view=diff ============================================================================== --- llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp (original) +++ llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp Wed Sep 28 05:53:56 2011 @@ -40,7 +40,8 @@ // // Cases -1 and 7 are caught by a C++ test harness where the validity of // of a C++ catch(...) clause catching a generated exception with a -// type info type of 7 is questionable. +// type info type of 7 is explained by: example in rules 1.6.4 in +// http://sourcery.mentor.com/public/cxx-abi/abi-eh.html (v1.22) // // This code uses code from the llvm compiler-rt project and the llvm // Kaleidoscope project. @@ -86,7 +87,7 @@ #endif // System C++ ABI unwind types from: -// http://refspecs.freestandards.org/abi-eh-1.21.html +// http://sourcery.mentor.com/public/cxx-abi/abi-eh.html (v1.22) extern "C" { @@ -1663,12 +1664,12 @@ exc.what()); } catch (...) { - // Catch all exceptions including our generated ones. I'm not sure - // why this latter functionality should work, as it seems that - // our exceptions should be foreign to C++ (the _Unwind_Exception:: - // exception_class should be different from the one used by C++), and - // therefore C++ should ignore the generated exceptions. - + // Catch all exceptions including our generated ones. This latter + // functionality works according to the example in rules 1.6.4 of + // http://sourcery.mentor.com/public/cxx-abi/abi-eh.html (v1.22), + // given that these will be exceptions foreign to C++ + // (the _Unwind_Exception::exception_class should be different from + // the one used by C++). fprintf(stderr, "\nrunExceptionThrow(...):In C++ catch all.\n"); } From dmalyshev at accesssoftek.com Wed Sep 28 06:19:31 2011 From: dmalyshev at accesssoftek.com (Danil Malyshev) Date: Wed, 28 Sep 2011 04:19:31 -0700 Subject: [llvm-commits] RuntimeDyld RelocationResolver Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE18055C55BB@mail.accesssoftek.com> ping ________________________________ From: Danil Malyshev Sent: Friday, September 23, 2011 7:14 PM To: 'llvm-commits at cs.uiuc.edu' Subject: RuntimeDyld RelocationResolver Hello everyone, Please find attached the patch for review. The patch adds a new RelocationResolver class which will get used later in the re-factored RuntimeDyLd. I'll send the patch for re-factored RuntimeDyLd once this one will pass the review. Regards, Danil -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110928/e5f0db4b/attachment.html From justin.holewinski at gmail.com Wed Sep 28 06:58:05 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Wed, 28 Sep 2011 07:58:05 -0400 Subject: [llvm-commits] [llvm] r140624 - /llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp In-Reply-To: References: <20110927192550.28C742A6C12C@llvm.org> Message-ID: On Tue, Sep 27, 2011 at 4:01 PM, Eli Friedman wrote: > On Tue, Sep 27, 2011 at 12:25 PM, Justin Holewinski > wrote: > > Author: jholewinski > > Date: Tue Sep 27 14:25:49 2011 > > New Revision: 140624 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=140624&view=rev > > Log: > > PTX: Fix case where printed alignment could be 0 > > > > Modified: > > llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp > > > > Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp > > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140624&r1=140623&r2=140624&view=diff > > > ============================================================================== > > --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) > > +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Tue Sep 27 14:25:49 2011 > > @@ -480,7 +480,7 @@ > > unsigned alignment = gv->getAlignment(); > > if (alignment != 0) { > > decl += ".align "; > > - decl += utostr(Log2_32(gv->getAlignment())); > > + decl += utostr(std::max(1U, Log2_32(gv->getAlignment()))); > > decl += " "; > > } > > This looks wrong: you're making sure the alignment is at least 2 bytes?! > No, this is making sure it is at least 1 byte. There were some cases where the Log2 function was returning 0. > > -Eli > -- Thanks, Justin Holewinski -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110928/d9f0c894/attachment.html From justin.holewinski at gmail.com Wed Sep 28 07:01:26 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Wed, 28 Sep 2011 08:01:26 -0400 Subject: [llvm-commits] [llvm] r140616 - in /llvm/trunk/lib/Target/PTX: PTXAsmPrinter.cpp PTXISelDAGToDAG.cpp PTXISelLowering.cpp PTXInstrLoadStore.td PTXMachineFunctionInfo.h PTXRegisterInfo.cpp In-Reply-To: References: <20110927181256.0C1572A6C12C@llvm.org> <9E9F7D7B-9288-4CD2-A744-38974C12CC18@googlemail.com> Message-ID: On Wed, Sep 28, 2011 at 5:23 AM, NAKAMURA Takumi wrote: > > Fixed (without dirty hacks) in r140679. > > Thanks Benjamin! ...Takumi > This isn't the first time I've been bit by SelectionDAG nodes not keeping internal copies of strings. What is the design rationale for this? Memory footprint? In other places, I have to make sure I hold on to dynamically-generated names that get passed to getTargetExternalSymbol(). -- Thanks, Justin Holewinski -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110928/5944ab00/attachment.html From proljc at gmail.com Wed Sep 28 08:54:23 2011 From: proljc at gmail.com (Liu) Date: Wed, 28 Sep 2011 21:54:23 +0800 Subject: [llvm-commits] [patch] Add MIPS64 instructions predicate defines Message-ID: Hi all I added MIPS64 instructions predicate defines. --Liu -------------- next part -------------- From 7799c37b61ac7a5af5580d94f138994f9fa5f4a2 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 28 Sep 2011 21:32:15 +0800 Subject: [PATCH] add mips64 insn predicate defs --- lib/Target/Mips/Mips64InstrInfo.td | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 5352230..dbf3821 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -10,3 +10,10 @@ // This file describes Mips64 instructions. // //===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Mips64 Instruction Predicate Definitions. +//===----------------------------------------------------------------------===// +def HasMips64 : Predicate<"Subtarget.hasMips64()">; +def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">; + -- 1.7.4.1 From james.molloy at arm.com Wed Sep 28 09:21:38 2011 From: james.molloy at arm.com (James Molloy) Date: Wed, 28 Sep 2011 14:21:38 -0000 Subject: [llvm-commits] [llvm] r140696 - in /llvm/trunk: lib/Target/ARM/ARM.td lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp test/MC/ARM/thumb2-mclass.s test/MC/Disassembler/ARM/thumb-MSR-MClass.txt test/MC/Disassembler/ARM/thumb-tests.txt Message-ID: <20110928142139.2636F2A6C12C@llvm.org> Author: jamesm Date: Wed Sep 28 09:21:38 2011 New Revision: 140696 URL: http://llvm.org/viewvc/llvm-project?rev=140696&view=rev Log: Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. Added: llvm/trunk/test/MC/ARM/thumb2-mclass.s (with props) llvm/trunk/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt (with props) Modified: llvm/trunk/lib/Target/ARM/ARM.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=140696&r1=140695&r2=140696&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Wed Sep 28 09:21:38 2011 @@ -94,6 +94,10 @@ def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", "Supports Multiprocessing extension">; +// M-series ISA? +def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true", + "Is microcontroller profile ('M' series)">; + // ARM ISAs. def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", "Support ARM v4T instructions">; @@ -185,7 +189,7 @@ // V6M Processors. def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM, - FeatureDB]>; + FeatureDB, FeatureMClass]>; // V6T2 Processors. def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops, @@ -208,14 +212,14 @@ // V7M Processors. def : ProcNoItin<"cortex-m3", [HasV7Ops, FeatureThumb2, FeatureNoARM, FeatureDB, - FeatureHWDiv]>; + FeatureHWDiv, FeatureMClass]>; // V7EM Processors. def : ProcNoItin<"cortex-m4", [HasV7Ops, FeatureThumb2, FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2, FeatureT2XtPk, FeatureVFP2, - FeatureVFPOnlySP]>; + FeatureVFPOnlySP, FeatureMClass]>; //===----------------------------------------------------------------------===// // Register File Description Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=140696&r1=140695&r2=140696&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Sep 28 09:21:38 2011 @@ -205,6 +205,10 @@ def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate<"ModeThumb,FeatureThumb2">; +def IsMClass : Predicate<"Subtarget->isMClass()">, + AssemblerPredicate<"FeatureMClass">; +def IsARClass : Predicate<"!Subtarget->isMClass()">, + AssemblerPredicate<"!FeatureMClass">; def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate<"!ModeThumb">; def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=140696&r1=140695&r2=140696&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep 28 09:21:38 2011 @@ -3540,30 +3540,55 @@ // Move between special register and ARM core register -- for disassembly only // // Move to ARM core register from Special Register -def t2MRS : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []> { + +// A/R class MRS. +// +// A/R class can only move from CPSR or SPSR. +def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []>, + Requires<[IsThumb2,IsARClass]> { bits<4> Rd; let Inst{31-12} = 0b11110011111011111000; let Inst{11-8} = Rd; let Inst{7-0} = 0b0000; } -def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS GPR:$Rd, pred:$p)>; +def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>; -def t2MRSsys:T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []> { +def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []>, + Requires<[IsThumb2,IsARClass]> { bits<4> Rd; let Inst{31-12} = 0b11110011111111111000; let Inst{11-8} = Rd; let Inst{7-0} = 0b0000; } +// M class MRS. +// +// This MRS has a mask field in bits 7-0 and can take more values than +// the A/R class (a full msr_mask). +def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary, + "mrs", "\t$Rd, $mask", []>, + Requires<[IsThumb2,IsMClass]> { + bits<4> Rd; + bits<8> mask; + let Inst{31-12} = 0b11110011111011111000; + let Inst{11-8} = Rd; + let Inst{19-16} = 0b1111; + let Inst{7-0} = mask; +} + + // Move from ARM core register to Special Register // +// A/R class MSR. +// // No need to have both system and application versions, the encodings are the // same and the assembly parser has no way to distinguish between them. The mask // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains // the mask with the fields to be accessed in the special register. -def t2MSR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn), - NoItinerary, "msr", "\t$mask, $Rn", []> { +def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn), + NoItinerary, "msr", "\t$mask, $Rn", []>, + Requires<[IsThumb2,IsARClass]> { bits<5> mask; bits<4> Rn; let Inst{31-21} = 0b11110011100; @@ -3574,6 +3599,22 @@ let Inst{7-0} = 0; } +// M class MSR. +// +// Move from ARM core register to Special Register +def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn), + NoItinerary, "msr", "\t$SYSm, $Rn", []>, + Requires<[IsThumb2,IsMClass]> { + bits<8> SYSm; + bits<4> Rn; + let Inst{31-21} = 0b11110011100; + let Inst{20} = 0b0; + let Inst{19-16} = Rn; + let Inst{15-12} = 0b1000; + let Inst{7-0} = SYSm; +} + + //===----------------------------------------------------------------------===// // Move between coprocessor and ARM core register // Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=140696&r1=140695&r2=140696&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Sep 28 09:21:38 2011 @@ -55,6 +55,7 @@ , InThumbMode(false) , InNaClMode(false) , HasThumb2(false) + , IsMClass(false) , NoARM(false) , PostRAScheduler(false) , IsR9Reserved(ReserveR9) Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=140696&r1=140695&r2=140696&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Sep 28 09:21:38 2011 @@ -76,6 +76,10 @@ /// HasThumb2 - True if Thumb2 instructions are supported. bool HasThumb2; + /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs - + /// v6m, v7m for example. + bool IsMClass; + /// NoARM - True if subtarget does not support ARM mode execution. bool NoARM; @@ -224,6 +228,8 @@ bool isThumb1Only() const { return InThumbMode && !HasThumb2; } bool isThumb2() const { return InThumbMode && HasThumb2; } bool hasThumb2() const { return HasThumb2; } + bool isMClass() const { return IsMClass; } + bool isARClass() const { return !IsMClass; } bool isR9Reserved() const { return IsR9Reserved; } Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=140696&r1=140695&r2=140696&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Sep 28 09:21:38 2011 @@ -114,10 +114,16 @@ bool hasV6Ops() const { return STI.getFeatureBits() & ARM::HasV6Ops; } + bool hasV7Ops() const { + return STI.getFeatureBits() & ARM::HasV7Ops; + } void SwitchMode() { unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); setAvailableFeatures(FB); } + bool isMClass() const { + return STI.getFeatureBits() & ARM::FeatureMClass; + } /// @name Auto-generated Match Functions /// { @@ -2076,6 +2082,37 @@ assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); StringRef Mask = Tok.getString(); + if (isMClass()) { + // See ARMv6-M 10.1.1 + unsigned FlagsVal = StringSwitch(Mask) + .Case("apsr", 0) + .Case("iapsr", 1) + .Case("eapsr", 2) + .Case("xpsr", 3) + .Case("ipsr", 5) + .Case("epsr", 6) + .Case("iepsr", 7) + .Case("msp", 8) + .Case("psp", 9) + .Case("primask", 16) + .Case("basepri", 17) + .Case("basepri_max", 18) + .Case("faultmask", 19) + .Case("control", 20) + .Default(~0U); + + if (FlagsVal == ~0U) + return MatchOperand_NoMatch; + + if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19) + // basepri, basepri_max and faultmask only valid for V7m. + return MatchOperand_NoMatch; + + Parser.Lex(); // Eat identifier token. + Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); + return MatchOperand_Success; + } + // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" size_t Start = 0, Next = Mask.find('_'); StringRef Flags = ""; Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=140696&r1=140695&r2=140696&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Sep 28 09:21:38 2011 @@ -621,6 +621,26 @@ unsigned SpecRegRBit = Op.getImm() >> 4; unsigned Mask = Op.getImm() & 0xf; + if (getAvailableFeatures() & ARM::FeatureMClass) { + switch (Op.getImm()) { + default: assert(0 && "Unexpected mask value!"); + case 0: O << "apsr"; return; + case 1: O << "iapsr"; return; + case 2: O << "eapsr"; return; + case 3: O << "xpsr"; return; + case 5: O << "ipsr"; return; + case 6: O << "epsr"; return; + case 7: O << "iepsr"; return; + case 8: O << "msp"; return; + case 9: O << "psp"; return; + case 16: O << "primask"; return; + case 17: O << "basepri"; return; + case 18: O << "basepri_max"; return; + case 19: O << "faultmask"; return; + case 20: O << "control"; return; + } + } + // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=140696&r1=140695&r2=140696&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Sep 28 09:21:38 2011 @@ -56,18 +56,21 @@ unsigned SubVer = TT[Idx]; if (SubVer >= '7' && SubVer <= '9') { if (Len >= Idx+2 && TT[Idx+1] == 'm') { - // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv - ARMArchFeature = "+v7,+noarm,+db,+hwdiv"; + // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass + ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass"; } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2, - // FeatureT2XtPk - ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk"; + // FeatureT2XtPk, FeatureMClass + ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass"; } else // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk"; } else if (SubVer == '6') { if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') ARMArchFeature = "+v6t2"; + else if (Len >= Idx+2 && TT[Idx+1] == 'm') + // v6m: FeatureNoARM, FeatureMClass + ARMArchFeature = "+v6t2,+noarm,+mclass"; else ARMArchFeature = "+v6"; } else if (SubVer == '5') { Added: llvm/trunk/test/MC/ARM/thumb2-mclass.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2-mclass.s?rev=140696&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/thumb2-mclass.s (added) +++ llvm/trunk/test/MC/ARM/thumb2-mclass.s Wed Sep 28 09:21:38 2011 @@ -0,0 +1,74 @@ +@ RUN: llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified + .globl _func + +@ Check that the assembler can handle the documented syntax from the ARM ARM. +@ These tests test instruction encodings specific to v7m & v7m (FeatureMClass). + + at ------------------------------------------------------------------------------ +@ MRS + at ------------------------------------------------------------------------------ + + mrs r0, apsr + mrs r0, iapsr + mrs r0, eapsr + mrs r0, xpsr + mrs r0, ipsr + mrs r0, epsr + mrs r0, iepsr + mrs r0, msp + mrs r0, psp + mrs r0, primask + mrs r0, basepri + mrs r0, basepri_max + mrs r0, faultmask + mrs r0, control + +@ CHECK: mrs r0, apsr @ encoding: [0xef,0xf3,0x00,0x80] +@ CHECK: mrs r0, iapsr @ encoding: [0xef,0xf3,0x01,0x80] +@ CHECK: mrs r0, eapsr @ encoding: [0xef,0xf3,0x02,0x80] +@ CHECK: mrs r0, xpsr @ encoding: [0xef,0xf3,0x03,0x80] +@ CHECK: mrs r0, ipsr @ encoding: [0xef,0xf3,0x05,0x80] +@ CHECK: mrs r0, epsr @ encoding: [0xef,0xf3,0x06,0x80] +@ CHECK: mrs r0, iepsr @ encoding: [0xef,0xf3,0x07,0x80] +@ CHECK: mrs r0, msp @ encoding: [0xef,0xf3,0x08,0x80] +@ CHECK: mrs r0, psp @ encoding: [0xef,0xf3,0x09,0x80] +@ CHECK: mrs r0, primask @ encoding: [0xef,0xf3,0x10,0x80] +@ CHECK: mrs r0, basepri @ encoding: [0xef,0xf3,0x11,0x80] +@ CHECK: mrs r0, basepri_max @ encoding: [0xef,0xf3,0x12,0x80] +@ CHECK: mrs r0, faultmask @ encoding: [0xef,0xf3,0x13,0x80] +@ CHECK: mrs r0, control @ encoding: [0xef,0xf3,0x14,0x80] + + at ------------------------------------------------------------------------------ +@ MSR + at ------------------------------------------------------------------------------ + + msr apsr, r0 + msr iapsr, r0 + msr eapsr, r0 + msr xpsr, r0 + msr ipsr, r0 + msr epsr, r0 + msr iepsr, r0 + msr msp, r0 + msr psp, r0 + msr primask, r0 + msr basepri, r0 + msr basepri_max, r0 + msr faultmask, r0 + msr control, r0 + +@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x80] +@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x80] +@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x80] +@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x80] +@ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x80] +@ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x80] +@ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x80] +@ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x80] +@ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x80] +@ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x80] +@ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x80] +@ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x80] +@ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x80] +@ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x80] Propchange: llvm/trunk/test/MC/ARM/thumb2-mclass.s ------------------------------------------------------------------------------ svn:eol-style = native Propchange: llvm/trunk/test/MC/ARM/thumb2-mclass.s ------------------------------------------------------------------------------ svn:keywords = Rev Date Author URL Id Added: llvm/trunk/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt?rev=140696&view=auto ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt (added) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt Wed Sep 28 09:21:38 2011 @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m3 | FileCheck %s + +# CHECK: msr primask, r0 +0x80 0xf3 0x10 0x80 + +# CHECK: mrs r0, primask +0xef 0xf3 0x10 0x80 Propchange: llvm/trunk/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt ------------------------------------------------------------------------------ svn:eol-style = native Propchange: llvm/trunk/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt ------------------------------------------------------------------------------ svn:keywords = Rev Date Author URL Id Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=140696&r1=140695&r2=140696&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Wed Sep 28 09:21:38 2011 @@ -295,3 +295,9 @@ # CHECK: pldw [r11, r12, lsl #2] 0x3b 0xf8 0x2c 0xf0 + +# CHECK: msr CPSR_fc, r0 +0x80 0xf3 0x00 0x89 + +# CHECK: mrs r0, apsr +0xef 0xf3 0x00 0x80 From justin.holewinski at gmail.com Wed Sep 28 09:32:06 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Wed, 28 Sep 2011 14:32:06 -0000 Subject: [llvm-commits] [llvm] r140698 - in /llvm/trunk/lib/Target/PTX: PTXAsmPrinter.cpp PTXAsmPrinter.h Message-ID: <20110928143206.D04502A6C12D@llvm.org> Author: jholewinski Date: Wed Sep 28 09:32:06 2011 New Revision: 140698 URL: http://llvm.org/viewvc/llvm-project?rev=140698&view=rev Log: PTX: MC-ize the PTX backend (patch 2 of N) Get rid of some of the no-longer-needed parts of PTXAsmPrinter. Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/PTXAsmPrinter.h Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140698&r1=140697&r2=140698&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Wed Sep 28 09:32:06 2011 @@ -136,6 +136,7 @@ { const PTXSubtarget& ST = TM.getSubtarget(); + // Emit the PTX .version and .target attributes OutStreamer.EmitRawText(Twine("\t.version " + ST.getPTXVersionString())); OutStreamer.EmitRawText(Twine("\t.target " + ST.getTargetString() + (ST.supportsDouble() ? "" @@ -169,13 +170,6 @@ EmitVariableDeclaration(i); } -bool PTXAsmPrinter::runOnMachineFunction(MachineFunction &MF) { - SetupMachineFunction(MF); - EmitFunctionDeclaration(); - EmitFunctionBody(); - return false; -} - void PTXAsmPrinter::EmitFunctionBodyStart() { OutStreamer.EmitRawText(Twine("{")); @@ -534,7 +528,7 @@ OutStreamer.AddBlankLine(); } -void PTXAsmPrinter::EmitFunctionDeclaration() { +void PTXAsmPrinter::EmitFunctionEntryLabel() { // The function label could have already been emitted if two symbols end up // conflicting due to asm renaming. Detect this and emit an error. if (!CurrentFnSym->isUndefined()) { Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.h?rev=140698&r1=140697&r2=140698&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.h (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.h Wed Sep 28 09:32:06 2011 @@ -34,12 +34,9 @@ bool doFinalization(Module &M); virtual void EmitStartOfAsmFile(Module &M); - - virtual bool runOnMachineFunction(MachineFunction &MF); - virtual void EmitFunctionBodyStart(); virtual void EmitFunctionBodyEnd(); - + virtual void EmitFunctionEntryLabel(); virtual void EmitInstruction(const MachineInstr *MI); void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); From justin.holewinski at gmail.com Wed Sep 28 09:32:04 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Wed, 28 Sep 2011 14:32:04 -0000 Subject: [llvm-commits] [llvm] r140697 - in /llvm/trunk: lib/Target/PTX/ lib/Target/PTX/InstPrinter/ lib/Target/PTX/MCTargetDesc/ test/CodeGen/PTX/ Message-ID: <20110928143204.77BA22A6C12C@llvm.org> Author: jholewinski Date: Wed Sep 28 09:32:04 2011 New Revision: 140697 URL: http://llvm.org/viewvc/llvm-project?rev=140697&view=rev Log: PTX: MC-ize the PTX back-end (patch 1 of N) Lay some groundwork for converting to MC-based asm printer. This is the first of probably many patches to bring the back-end back up-to-date with all of the recent MC changes. Added: llvm/trunk/lib/Target/PTX/InstPrinter/ llvm/trunk/lib/Target/PTX/InstPrinter/CMakeLists.txt llvm/trunk/lib/Target/PTX/InstPrinter/Makefile llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.h llvm/trunk/lib/Target/PTX/PTXAsmPrinter.h llvm/trunk/lib/Target/PTX/PTXMCInstLower.cpp Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt llvm/trunk/lib/Target/PTX/MCTargetDesc/CMakeLists.txt llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp llvm/trunk/lib/Target/PTX/Makefile llvm/trunk/lib/Target/PTX/PTX.h llvm/trunk/lib/Target/PTX/PTX.td llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp llvm/trunk/lib/Target/PTX/PTXInstrFormats.td llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h llvm/trunk/test/CodeGen/PTX/add.ll llvm/trunk/test/CodeGen/PTX/mov.ll llvm/trunk/test/CodeGen/PTX/mul.ll llvm/trunk/test/CodeGen/PTX/sub.ll Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Wed Sep 28 09:32:04 2011 @@ -14,6 +14,7 @@ PTXInstrInfo.cpp PTXFrameLowering.cpp PTXMCAsmStreamer.cpp + PTXMCInstLower.cpp PTXMFInfoExtract.cpp PTXParamManager.cpp PTXRegAlloc.cpp @@ -37,4 +38,6 @@ ) add_subdirectory(TargetInfo) +add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) + Added: llvm/trunk/lib/Target/PTX/InstPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/InstPrinter/CMakeLists.txt?rev=140697&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/InstPrinter/CMakeLists.txt (added) +++ llvm/trunk/lib/Target/PTX/InstPrinter/CMakeLists.txt Wed Sep 28 09:32:04 2011 @@ -0,0 +1,13 @@ +include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) + +add_llvm_library(LLVMPTXAsmPrinter + PTXInstPrinter.cpp + ) + +add_dependencies(LLVMPTXAsmPrinter PTXCommonTableGen) + +add_llvm_library_dependencies(LLVMPTXAsmPrinter + LLVMMC + LLVMSupport + ) + Added: llvm/trunk/lib/Target/PTX/InstPrinter/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/InstPrinter/Makefile?rev=140697&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/InstPrinter/Makefile (added) +++ llvm/trunk/lib/Target/PTX/InstPrinter/Makefile Wed Sep 28 09:32:04 2011 @@ -0,0 +1,16 @@ +##===- lib/Target/PTX/AsmPrinter/Makefile ------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## +LEVEL = ../../../.. +LIBRARYNAME = LLVMPTXAsmPrinter + +# Hack: we need to include 'main' ptx target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common + Added: llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp?rev=140697&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp (added) +++ llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp Wed Sep 28 09:32:04 2011 @@ -0,0 +1,149 @@ +//===-- PTXInstPrinter.cpp - Convert PTX MCInst to assembly syntax --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints a PTX MCInst to a .ptx file. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "asm-printer" +#include "PTXInstPrinter.h" +#include "PTXMachineFunctionInfo.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/Support/raw_ostream.h" +using namespace llvm; + +#define GET_INSTRUCTION_NAME +#include "PTXGenAsmWriter.inc" + +PTXInstPrinter::PTXInstPrinter(const MCAsmInfo &MAI, + const MCSubtargetInfo &STI) : + MCInstPrinter(MAI) { + // Initialize the set of available features. + setAvailableFeatures(STI.getFeatureBits()); +} + +StringRef PTXInstPrinter::getOpcodeName(unsigned Opcode) const { + return getInstructionName(Opcode); +} + +void PTXInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << getRegisterName(RegNo); +} + +void PTXInstPrinter::printInst(const MCInst *MI, raw_ostream &O, + StringRef Annot) { + printPredicate(MI, O); + switch (MI->getOpcode()) { + default: + printInstruction(MI, O); + break; + case PTX::CALL: + printCall(MI, O); + } + O << ";"; + printAnnotation(O, Annot); +} + +void PTXInstPrinter::printPredicate(const MCInst *MI, raw_ostream &O) { + // The last two operands are the predicate operands + int RegIndex; + int OpIndex; + + if (MI->getOpcode() == PTX::CALL) { + RegIndex = 0; + OpIndex = 1; + } else { + RegIndex = MI->getNumOperands()-2; + OpIndex = MI->getNumOperands()-1; + } + + int PredOp = MI->getOperand(OpIndex).getImm(); + if (PredOp != PTX::PRED_NONE) { + if (PredOp == PTX::PRED_NEGATE) { + O << '!'; + } else { + O << '@'; + } + printOperand(MI, RegIndex, O); + } +} + +void PTXInstPrinter::printCall(const MCInst *MI, raw_ostream &O) { + O << "\tcall.uni\t"; + // The first two operands are the predicate slot + unsigned Index = 2; + unsigned NumRets = MI->getOperand(Index++).getImm(); + for (unsigned i = 0; i < NumRets; ++i) { + if (i == 0) { + O << "("; + } else { + O << ", "; + } + printOperand(MI, Index++, O); + } + + if (NumRets > 0) { + O << "), "; + } + + O << *(MI->getOperand(Index++).getExpr()) << ", ("; + + unsigned NumArgs = MI->getOperand(Index++).getImm(); + for (unsigned i = 0; i < NumArgs; ++i) { + printOperand(MI, Index++, O); + if (i < NumArgs-1) { + O << ", "; + } + } + + O << ")"; +} + +void PTXInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + const MCOperand &Op = MI->getOperand(OpNo); + if (Op.isImm()) { + O << Op.getImm(); + } else if (Op.isFPImm()) { + double Imm = Op.getFPImm(); + APFloat FPImm(Imm); + APInt FPIntImm = FPImm.bitcastToAPInt(); + O << "0D"; + // PTX requires us to output the full 64 bits, even if the number is zero + if (FPIntImm.getZExtValue() > 0) { + O << FPIntImm.toString(16, false); + } else { + O << "0000000000000000"; + } + } else { + assert(Op.isExpr() && "unknown operand kind in printOperand"); + const MCExpr *Expr = Op.getExpr(); + if (const MCSymbolRefExpr *SymRefExpr = dyn_cast(Expr)) { + const MCSymbol &Sym = SymRefExpr->getSymbol(); + O << Sym.getName(); + } else { + O << *Op.getExpr(); + } + } +} + +void PTXInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + printOperand(MI, OpNo, O); + if (MI->getOperand(OpNo+1).isImm() && MI->getOperand(OpNo+1).getImm() == 0) + return; // don't print "+0" + O << "+"; + printOperand(MI, OpNo+1, O); +} + + Added: llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.h?rev=140697&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.h (added) +++ llvm/trunk/lib/Target/PTX/InstPrinter/PTXInstPrinter.h Wed Sep 28 09:32:04 2011 @@ -0,0 +1,46 @@ +//===-- PTXInstPrinter.h - Convert PTX MCInst to assembly syntax ----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints n PTX MCInst to a .ptx file. +// +//===----------------------------------------------------------------------===// + +#ifndef PTXINSTPRINTER_H +#define PTXINSTPRINTER_H + +#include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCSubtargetInfo.h" + +namespace llvm { + +class MCOperand; + +class PTXInstPrinter : public MCInstPrinter { +public: + PTXInstPrinter(const MCAsmInfo &MAI, const MCSubtargetInfo &STI); + + virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); + virtual StringRef getOpcodeName(unsigned Opcode) const; + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; + + static const char *getInstructionName(unsigned Opcode); + + // Autogenerated by tblgen. + void printInstruction(const MCInst *MI, raw_ostream &O); + static const char *getRegisterName(unsigned RegNo); + + void printPredicate(const MCInst *MI, raw_ostream &O); + void printCall(const MCInst *MI, raw_ostream &O); + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); +}; +} + +#endif + Modified: llvm/trunk/lib/Target/PTX/MCTargetDesc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/MCTargetDesc/CMakeLists.txt?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/MCTargetDesc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PTX/MCTargetDesc/CMakeLists.txt Wed Sep 28 09:32:04 2011 @@ -6,6 +6,7 @@ add_llvm_library_dependencies(LLVMPTXDesc LLVMMC LLVMPTXInfo + LLVMPTXAsmPrinter LLVMSupport ) Modified: llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp Wed Sep 28 09:32:04 2011 @@ -13,6 +13,7 @@ #include "PTXMCTargetDesc.h" #include "PTXMCAsmInfo.h" +#include "InstPrinter/PTXInstPrinter.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -57,6 +58,15 @@ return X; } +static MCInstPrinter *createPTXMCInstPrinter(const Target &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI, + const MCSubtargetInfo &STI) { + if (SyntaxVariant == 0) + return new PTXInstPrinter(MAI, STI); + return 0; +} + extern "C" void LLVMInitializePTXTargetMC() { // Register the MC asm info. RegisterMCAsmInfo X(ThePTX32Target); @@ -79,4 +89,8 @@ createPTXMCSubtargetInfo); TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target, createPTXMCSubtargetInfo); + + // Register the MCInstPrinter. + TargetRegistry::RegisterMCInstPrinter(ThePTX32Target, createPTXMCInstPrinter); + TargetRegistry::RegisterMCInstPrinter(ThePTX64Target, createPTXMCInstPrinter); } Modified: llvm/trunk/lib/Target/PTX/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/Makefile?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/Makefile (original) +++ llvm/trunk/lib/Target/PTX/Makefile Wed Sep 28 09:32:04 2011 @@ -18,6 +18,6 @@ PTXGenRegisterInfo.inc \ PTXGenSubtargetInfo.inc -DIRS = TargetInfo MCTargetDesc +DIRS = InstPrinter TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common Modified: llvm/trunk/lib/Target/PTX/PTX.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.h?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTX.h (original) +++ llvm/trunk/lib/Target/PTX/PTX.h Wed Sep 28 09:32:04 2011 @@ -19,6 +19,9 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { + class MachineInstr; + class MCInst; + class PTXAsmPrinter; class PTXTargetMachine; class FunctionPass; @@ -33,7 +36,8 @@ enum Predicate { PRED_NORMAL = 0, - PRED_NEGATE = 1 + PRED_NEGATE = 1, + PRED_NONE = 2 }; } // namespace PTX @@ -45,6 +49,9 @@ FunctionPass *createPTXRegisterAllocator(); + void LowerPTXMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, + PTXAsmPrinter &AP); + } // namespace llvm; #endif // PTX_H Modified: llvm/trunk/lib/Target/PTX/PTX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.td?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTX.td (original) +++ llvm/trunk/lib/Target/PTX/PTX.td Wed Sep 28 09:32:04 2011 @@ -122,9 +122,20 @@ def PTXInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// +// Assembly printer +//===----------------------------------------------------------------------===// +// PTX uses the MC printer for asm output, so make sure the TableGen +// AsmWriter bits get associated with the correct class. +def PTXAsmWriter : AsmWriter { + string AsmWriterClassName = "InstPrinter"; + bit isMCAsmWriter = 1; +} + +//===----------------------------------------------------------------------===// // Target Declaration //===----------------------------------------------------------------------===// def PTX : Target { let InstructionSet = PTXInstrInfo; + let AssemblyWriters = [PTXAsmWriter]; } Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Wed Sep 28 09:32:04 2011 @@ -15,6 +15,7 @@ #define DEBUG_TYPE "ptx-asm-printer" #include "PTX.h" +#include "PTXAsmPrinter.h" #include "PTXMachineFunctionInfo.h" #include "PTXParamManager.h" #include "PTXRegisterInfo.h" @@ -30,6 +31,8 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" @@ -44,49 +47,6 @@ using namespace llvm; -namespace { -class PTXAsmPrinter : public AsmPrinter { -public: - explicit PTXAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) - : AsmPrinter(TM, Streamer) {} - - const char *getPassName() const { return "PTX Assembly Printer"; } - - bool doFinalization(Module &M); - - virtual void EmitStartOfAsmFile(Module &M); - - virtual bool runOnMachineFunction(MachineFunction &MF); - - virtual void EmitFunctionBodyStart(); - virtual void EmitFunctionBodyEnd() { OutStreamer.EmitRawText(Twine("}")); } - - virtual void EmitInstruction(const MachineInstr *MI); - - void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); - void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, - const char *Modifier = 0); - void printReturnOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, - const char *Modifier = 0); - void printPredicateOperand(const MachineInstr *MI, raw_ostream &O); - - void printCall(const MachineInstr *MI, raw_ostream &O); - - unsigned GetOrCreateSourceID(StringRef FileName, - StringRef DirName); - - // autogen'd. - void printInstruction(const MachineInstr *MI, raw_ostream &OS); - static const char *getRegisterName(unsigned RegNo); - -private: - void EmitVariableDeclaration(const GlobalVariable *gv); - void EmitFunctionDeclaration(); - - StringMap SourceIdMap; -}; // class PTXAsmPrinter -} // namespace - static const char PARAM_PREFIX[] = "__param_"; static const char RETURN_PREFIX[] = "__ret_"; @@ -320,7 +280,12 @@ //} } +void PTXAsmPrinter::EmitFunctionBodyEnd() { + OutStreamer.EmitRawText(Twine("}")); +} + void PTXAsmPrinter::EmitInstruction(const MachineInstr *MI) { +#if 0 std::string str; str.reserve(64); @@ -388,6 +353,11 @@ StringRef strref = StringRef(str); OutStreamer.EmitRawText(strref); +#endif + + MCInst TmpInst; + LowerPTXMachineInstrToMCInst(MI, TmpInst, *this); + OutStreamer.EmitInstruction(TmpInst); } void PTXAsmPrinter::printOperand(const MachineInstr *MI, int opNum, @@ -737,10 +707,57 @@ return SrcId; } -#include "PTXGenAsmWriter.inc" +MCOperand PTXAsmPrinter::GetSymbolRef(const MachineOperand &MO, + const MCSymbol *Symbol) { + const MCExpr *Expr; + Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, OutContext); + return MCOperand::CreateExpr(Expr); +} + +bool PTXAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) { + const PTXMachineFunctionInfo *MFI = MF->getInfo(); + const MCExpr *Expr; + const char *RegSymbolName; + switch (MO.getType()) { + default: + llvm_unreachable("Unknown operand type"); + case MachineOperand::MO_Register: + // We create register operands as symbols, since the PTXInstPrinter class + // has no way to map virtual registers back to a name without some ugly + // hacks. + // FIXME: Figure out a better way to handle virtual register naming. + RegSymbolName = MFI->getRegisterName(MO.getReg()); + Expr = MCSymbolRefExpr::Create(RegSymbolName, MCSymbolRefExpr::VK_None, + OutContext); + MCOp = MCOperand::CreateExpr(Expr); + break; + case MachineOperand::MO_Immediate: + MCOp = MCOperand::CreateImm(MO.getImm()); + break; + case MachineOperand::MO_MachineBasicBlock: + MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( + MO.getMBB()->getSymbol(), OutContext)); + break; + case MachineOperand::MO_GlobalAddress: + MCOp = GetSymbolRef(MO, Mang->getSymbol(MO.getGlobal())); + break; + case MachineOperand::MO_ExternalSymbol: + MCOp = GetSymbolRef(MO, GetExternalSymbolSymbol(MO.getSymbolName())); + break; + case MachineOperand::MO_FPImmediate: + APFloat Val = MO.getFPImm()->getValueAPF(); + bool ignored; + Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored); + MCOp = MCOperand::CreateFPImm(Val.convertToDouble()); + break; + } + + return true; +} // Force static initialization. extern "C" void LLVMInitializePTXAsmPrinter() { RegisterAsmPrinter X(ThePTX32Target); RegisterAsmPrinter Y(ThePTX64Target); } + Added: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.h?rev=140697&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.h (added) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.h Wed Sep 28 09:32:04 2011 @@ -0,0 +1,73 @@ +//===-- PTXAsmPrinter.h - Print machine code to a PTX file ----------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// PTX Assembly printer class. +// +//===----------------------------------------------------------------------===// + +#ifndef PTXASMPRINTER_H +#define PTXASMPRINTER_H + +#include "PTX.h" +#include "PTXTargetMachine.h" +#include "llvm/ADT/StringMap.h" +#include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/Support/Compiler.h" + +namespace llvm { + +class MCOperand; + +class LLVM_LIBRARY_VISIBILITY PTXAsmPrinter : public AsmPrinter { +public: + explicit PTXAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer) {} + + const char *getPassName() const { return "PTX Assembly Printer"; } + + bool doFinalization(Module &M); + + virtual void EmitStartOfAsmFile(Module &M); + + virtual bool runOnMachineFunction(MachineFunction &MF); + + virtual void EmitFunctionBodyStart(); + virtual void EmitFunctionBodyEnd(); + + virtual void EmitInstruction(const MachineInstr *MI); + + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, + const char *Modifier = 0); + void printReturnOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, + const char *Modifier = 0); + void printPredicateOperand(const MachineInstr *MI, raw_ostream &O); + + void printCall(const MachineInstr *MI, raw_ostream &O); + + unsigned GetOrCreateSourceID(StringRef FileName, + StringRef DirName); + + MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol); + bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp); + + // autogen'd. + void printInstruction(const MachineInstr *MI, raw_ostream &OS); + static const char *getRegisterName(unsigned RegNo); + +private: + void EmitVariableDeclaration(const GlobalVariable *gv); + void EmitFunctionDeclaration(); + + StringMap SourceIdMap; +}; // class PTXAsmPrinter +} // namespace llvm + +#endif + Modified: llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp Wed Sep 28 09:32:04 2011 @@ -129,7 +129,7 @@ OpCode = PTX::READPARAMF64; SDValue Pred = CurDAG->getRegister(PTX::NoRegister, MVT::i1); - SDValue PredOp = CurDAG->getTargetConstant(PTX::PRED_NORMAL, MVT::i32); + SDValue PredOp = CurDAG->getTargetConstant(PTX::PRED_NONE, MVT::i32); DebugLoc dl = Node->getDebugLoc(); SDValue Ops[] = { Index, Pred, PredOp, Chain }; @@ -167,7 +167,7 @@ llvm_unreachable("Invalid type in SelectWRITEPARAM"); SDValue Pred = CurDAG->getRegister(PTX::NoRegister, MVT::i1); - SDValue PredOp = CurDAG->getTargetConstant(PTX::PRED_NORMAL, MVT::i32); + SDValue PredOp = CurDAG->getTargetConstant(PTX::PRED_NONE, MVT::i32); DebugLoc dl = Node->getDebugLoc(); SDValue Ops[] = { Value, Pred, PredOp, Chain }; Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Wed Sep 28 09:32:04 2011 @@ -393,8 +393,8 @@ "Calls are not handled for the target device"); std::vector Ops; - // The layout of the ops will be [Chain, Ins, Callee, Outs] - Ops.resize(Outs.size() + Ins.size() + 2); + // The layout of the ops will be [Chain, #Ins, Ins, Callee, #Outs, Outs] + Ops.resize(Outs.size() + Ins.size() + 4); Ops[0] = Chain; @@ -403,11 +403,12 @@ assert(cast(GV)->getCallingConv() == CallingConv::PTX_Device && "PTX function calls must be to PTX device functions"); Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy()); - Ops[Ins.size()+1] = Callee; + Ops[Ins.size()+2] = Callee; // Generate STORE_PARAM nodes for each function argument. In PTX, function // arguments are explicitly stored into .param variables and passed as // arguments. There is no register/stack-based calling convention in PTX. + Ops[Ins.size()+3] = DAG.getTargetConstant(OutVals.size(), MVT::i32); for (unsigned i = 0; i != OutVals.size(); ++i) { unsigned Size = OutVals[i].getValueType().getSizeInBits(); unsigned Param = PM.addLocalParam(Size); @@ -416,19 +417,20 @@ MVT::Other); Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, MVT::Other, Chain, ParamValue, OutVals[i]); - Ops[i+Ins.size()+2] = ParamValue; + Ops[i+Ins.size()+4] = ParamValue; } std::vector InParams; // Generate list of .param variables to hold the return value(s). + Ops[1] = DAG.getTargetConstant(Ins.size(), MVT::i32); for (unsigned i = 0; i < Ins.size(); ++i) { unsigned Size = Ins[i].VT.getStoreSizeInBits(); unsigned Param = PM.addLocalParam(Size); const std::string &ParamName = PM.getParamName(Param); SDValue ParamValue = DAG.getTargetExternalSymbol(ParamName.c_str(), MVT::Other); - Ops[i+1] = ParamValue; + Ops[i+2] = ParamValue; InParams.push_back(ParamValue); } Modified: llvm/trunk/lib/Target/PTX/PTXInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrFormats.td?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrFormats.td (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrFormats.td Wed Sep 28 09:32:04 2011 @@ -7,10 +7,10 @@ // //===----------------------------------------------------------------------===// -// PTX Predicate operand, default to (0, 0) = (zero-reg, always). +// PTX Predicate operand, default to (0, 0) = (zero-reg, none). // Leave PrintMethod empty; predicate printing is defined elsewhere. def pred : PredicateOperand; + (ops (i1 zero_reg), (i32 2))>; let Namespace = "PTX" in { class InstPTX pattern> Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Wed Sep 28 09:32:04 2011 @@ -167,7 +167,7 @@ return false; Pred.push_back(MO); - Pred.push_back(MachineOperand::CreateImm(PTX::PRED_NORMAL)); + Pred.push_back(MachineOperand::CreateImm(PTX::PRED_NONE)); return true; } @@ -283,7 +283,7 @@ BuildMI(&MBB, DL, get(PTX::BRAdp)) .addMBB(TBB).addReg(Cond[0].getReg()).addImm(Cond[1].getImm()); BuildMI(&MBB, DL, get(PTX::BRAd)) - .addMBB(FBB).addReg(PTX::NoRegister).addImm(PTX::PRED_NORMAL); + .addMBB(FBB).addReg(PTX::NoRegister).addImm(PTX::PRED_NONE); return 2; } else if (Cond.size()) { BuildMI(&MBB, DL, get(PTX::BRAdp)) @@ -291,7 +291,7 @@ return 1; } else { BuildMI(&MBB, DL, get(PTX::BRAd)) - .addMBB(TBB).addReg(PTX::NoRegister).addImm(PTX::PRED_NORMAL); + .addMBB(TBB).addReg(PTX::NoRegister).addImm(PTX::PRED_NONE); return 1; } } @@ -319,7 +319,7 @@ GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1) { SDValue predReg = DAG->getRegister(PTX::NoRegister, MVT::i1); - SDValue predOp = DAG->getTargetConstant(PTX::PRED_NORMAL, MVT::i32); + SDValue predOp = DAG->getTargetConstant(PTX::PRED_NONE, MVT::i32); SDValue ops[] = { Op1, predReg, predOp }; return DAG->getMachineNode(Opcode, dl, VT, ops, array_lengthof(ops)); } @@ -328,7 +328,7 @@ GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2) { SDValue predReg = DAG->getRegister(PTX::NoRegister, MVT::i1); - SDValue predOp = DAG->getTargetConstant(PTX::PRED_NORMAL, MVT::i32); + SDValue predOp = DAG->getTargetConstant(PTX::PRED_NONE, MVT::i32); SDValue ops[] = { Op1, Op2, predReg, predOp }; return DAG->getMachineNode(Opcode, dl, VT, ops, array_lengthof(ops)); } @@ -336,7 +336,7 @@ void PTXInstrInfo::AddDefaultPredicate(MachineInstr *MI) { if (MI->findFirstPredOperandIdx() == -1) { MI->addOperand(MachineOperand::CreateReg(PTX::NoRegister, /*IsDef=*/false)); - MI->addOperand(MachineOperand::CreateImm(PTX::PRED_NORMAL)); + MI->addOperand(MachineOperand::CreateImm(PTX::PRED_NONE)); } } Modified: llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp Wed Sep 28 09:32:04 2011 @@ -499,7 +499,7 @@ void PTXMCAsmStreamer::AddEncodingComment(const MCInst &Inst) {} void PTXMCAsmStreamer::EmitInstruction(const MCInst &Inst) { - assert(getCurrentSection() && "Cannot emit contents before setting section!"); +//assert(getCurrentSection() && "Cannot emit contents before setting section!"); // Show the encoding in a comment if we have a code emitter. if (Emitter) Added: llvm/trunk/lib/Target/PTX/PTXMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMCInstLower.cpp?rev=140697&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXMCInstLower.cpp (added) +++ llvm/trunk/lib/Target/PTX/PTXMCInstLower.cpp Wed Sep 28 09:32:04 2011 @@ -0,0 +1,33 @@ +//===-- PTXMCInstLower.cpp - Convert PTX MachineInstr to an MCInst --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains code to lower PTX MachineInstrs to their corresponding +// MCInst records. +// +//===----------------------------------------------------------------------===// + +#include "PTX.h" +#include "PTXAsmPrinter.h" +#include "llvm/Constants.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/Target/Mangler.h" + +void llvm::LowerPTXMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, + PTXAsmPrinter &AP) { + OutMI.setOpcode(MI->getOpcode()); + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + MCOperand MCOp; + if (AP.lowerOperand(MO, MCOp)) + OutMI.addOperand(MCOp); + } +} + Modified: llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h (original) +++ llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h Wed Sep 28 09:32:04 2011 @@ -128,9 +128,9 @@ /// getRegisterName - Returns the name of the specified virtual register. This /// name is used during PTX emission. - std::string getRegisterName(unsigned Reg) const { + const char *getRegisterName(unsigned Reg) const { if (RegNames.count(Reg)) - return RegNames.lookup(Reg); + return RegNames.find(Reg)->second.c_str(); else if (Reg == PTX::NoRegister) return "%noreg"; else Modified: llvm/trunk/test/CodeGen/PTX/add.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/add.ll?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/add.ll (original) +++ llvm/trunk/test/CodeGen/PTX/add.ll Wed Sep 28 09:32:04 2011 @@ -57,7 +57,7 @@ } define ptx_device float @t2_f32(float %x) { -; CHECK: add.rn.f32 %ret{{[0-9]+}}, %f{{[0-9]+}}, 0F3F800000; +; CHECK: add.rn.f32 %ret{{[0-9]+}}, %f{{[0-9]+}}, 0D3FF0000000000000; ; CHECK: ret; %z = fadd float %x, 1.0 ret float %z Modified: llvm/trunk/test/CodeGen/PTX/mov.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mov.ll?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/mov.ll (original) +++ llvm/trunk/test/CodeGen/PTX/mov.ll Wed Sep 28 09:32:04 2011 @@ -19,7 +19,7 @@ } define ptx_device float @t1_f32() { -; CHECK: mov.f32 %ret{{[0-9]+}}, 0F00000000; +; CHECK: mov.f32 %ret{{[0-9]+}}, 0D0000000000000000; ; CHECK: ret; ret float 0.0 } Modified: llvm/trunk/test/CodeGen/PTX/mul.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mul.ll?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/mul.ll (original) +++ llvm/trunk/test/CodeGen/PTX/mul.ll Wed Sep 28 09:32:04 2011 @@ -25,7 +25,7 @@ } define ptx_device float @t2_f32(float %x) { -; CHECK: mul.rn.f32 %ret{{[0-9]+}}, %f{{[0-9]+}}, 0F40A00000; +; CHECK: mul.rn.f32 %ret{{[0-9]+}}, %f{{[0-9]+}}, 0D4014000000000000; ; CHECK: ret; %z = fmul float %x, 5.0 ret float %z Modified: llvm/trunk/test/CodeGen/PTX/sub.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/sub.ll?rev=140697&r1=140696&r2=140697&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/sub.ll (original) +++ llvm/trunk/test/CodeGen/PTX/sub.ll Wed Sep 28 09:32:04 2011 @@ -57,7 +57,7 @@ } define ptx_device float @t2_f32(float %x) { -; CHECK: add.rn.f32 %ret{{[0-9]+}}, %f{{[0-9]+}}, 0FBF800000; +; CHECK: add.rn.f32 %ret{{[0-9]+}}, %f{{[0-9]+}}, 0DBFF0000000000000; ; CHECK: ret; %z = fsub float %x, 1.0 ret float %z From eli.friedman at gmail.com Wed Sep 28 11:25:25 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 28 Sep 2011 09:25:25 -0700 Subject: [llvm-commits] [llvm] r140624 - /llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp In-Reply-To: References: <20110927192550.28C742A6C12C@llvm.org> Message-ID: On Wed, Sep 28, 2011 at 4:58 AM, Justin Holewinski wrote: > On Tue, Sep 27, 2011 at 4:01 PM, Eli Friedman > wrote: >> >> On Tue, Sep 27, 2011 at 12:25 PM, Justin Holewinski >> wrote: >> > Author: jholewinski >> > Date: Tue Sep 27 14:25:49 2011 >> > New Revision: 140624 >> > >> > URL: http://llvm.org/viewvc/llvm-project?rev=140624&view=rev >> > Log: >> > PTX: Fix case where printed alignment could be 0 >> > >> > Modified: >> > ? ?llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp >> > >> > Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp >> > URL: >> > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140624&r1=140623&r2=140624&view=diff >> > >> > ============================================================================== >> > --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) >> > +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Tue Sep 27 14:25:49 2011 >> > @@ -480,7 +480,7 @@ >> > ? unsigned alignment = gv->getAlignment(); >> > ? if (alignment != 0) { >> > ? ? decl += ".align "; >> > - ? ?decl += utostr(Log2_32(gv->getAlignment())); >> > + ? ?decl += utostr(std::max(1U, Log2_32(gv->getAlignment()))); >> > ? ? decl += " "; >> > ? } >> >> This looks wrong: you're making sure the alignment is at least 2 bytes?! > > No, this is making sure it is at least 1 byte. There were some cases where > the Log2 function was returning 0. log2(1) == 0. log2(2) == 1. Hence, your patch enforces a minimum alignment of 2 bytes. -Eli From atrick at apple.com Wed Sep 28 12:02:54 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 28 Sep 2011 17:02:54 -0000 Subject: [llvm-commits] [llvm] r140701 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <20110928170254.A623A2A6C12C@llvm.org> Author: atrick Date: Wed Sep 28 12:02:54 2011 New Revision: 140701 URL: http://llvm.org/viewvc/llvm-project?rev=140701&view=rev Log: indvars: generalize SCEV getPreStartForSignExtend. Handle general Add expressions to avoid leaving around redundant 32-bit IVs. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=140701&r1=140700&r2=140701&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Sep 28 12:02:54 2011 @@ -1070,14 +1070,26 @@ // Check for a simple looking step prior to loop entry. const SCEVAddExpr *SA = dyn_cast(Start); - if (!SA || SA->getNumOperands() != 2 || SA->getOperand(0) != Step) + if (!SA) + return 0; + + // Create an AddExpr for "PreStart" after subtracting Step. Full SCEV + // subtraction is expensive. For this purpose, perform a quick and dirty + // difference, by checking for Step in the operand list. + SmallVector DiffOps; + for (SCEVAddExpr::op_iterator I = SA->op_begin(), E = SA->op_end(); + I != E; ++I) { + if (*I != Step) + DiffOps.push_back(*I); + } + if (DiffOps.size() == SA->getNumOperands()) return 0; // This is a postinc AR. Check for overflow on the preinc recurrence using the // same three conditions that getSignExtendedExpr checks. // 1. NSW flags on the step increment. - const SCEV *PreStart = SA->getOperand(1); + const SCEV *PreStart = SE->getAddExpr(DiffOps, SA->getNoWrapFlags()); const SCEVAddRecExpr *PreAR = dyn_cast( SE->getAddRecExpr(PreStart, Step, L, SCEV::FlagAnyWrap)); From ahatanaka at mips.com Wed Sep 28 12:50:27 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 28 Sep 2011 17:50:27 -0000 Subject: [llvm-commits] [llvm] r140703 - /llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Message-ID: <20110928175027.A86E52A6C12C@llvm.org> Author: ahatanak Date: Wed Sep 28 12:50:27 2011 New Revision: 140703 URL: http://llvm.org/viewvc/llvm-project?rev=140703&view=rev Log: Mips64 predicate definitions. Patch by Liu. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=140703&r1=140702&r2=140703&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Sep 28 12:50:27 2011 @@ -10,3 +10,10 @@ // This file describes Mips64 instructions. // //===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Mips64 Instruction Predicate Definitions. +//===----------------------------------------------------------------------===// +def HasMips64 : Predicate<"Subtarget.hasMips64()">; +def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">; + From ahatanak at gmail.com Wed Sep 28 12:53:18 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Wed, 28 Sep 2011 10:53:18 -0700 Subject: [llvm-commits] [patch] Add MIPS64 instructions predicate defines In-Reply-To: References: Message-ID: committed in r140703. Thank you. On Wed, Sep 28, 2011 at 6:54 AM, Liu wrote: > Hi all > > I added MIPS64 instructions predicate defines. > > --Liu > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From ahatanaka at mips.com Wed Sep 28 12:56:55 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 28 Sep 2011 17:56:55 -0000 Subject: [llvm-commits] [llvm] r140704 - /llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Message-ID: <20110928175655.426D32A6C12C@llvm.org> Author: ahatanak Date: Wed Sep 28 12:56:55 2011 New Revision: 140704 URL: http://llvm.org/viewvc/llvm-project?rev=140704&view=rev Log: Remove definitions of branch-on-FP-likely instructions. They are deprecated. Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=140704&r1=140703&r2=140704&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Wed Sep 28 12:56:55 2011 @@ -217,8 +217,6 @@ // They must be kept in synch. def MIPS_BRANCH_F : PatLeaf<(i32 0)>; def MIPS_BRANCH_T : PatLeaf<(i32 1)>; -def MIPS_BRANCH_FL : PatLeaf<(i32 2)>; -def MIPS_BRANCH_TL : PatLeaf<(i32 3)>; /// Floating Point Branch of False/True (Likely) let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in @@ -228,8 +226,6 @@ def BC1F : FBRANCH; def BC1T : FBRANCH; -def BC1FL : FBRANCH; -def BC1TL : FBRANCH; //===----------------------------------------------------------------------===// // Floating Point Flag Conditions From ahatanaka at mips.com Wed Sep 28 13:11:19 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 28 Sep 2011 18:11:19 -0000 Subject: [llvm-commits] [llvm] r140705 - /llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Message-ID: <20110928181119.CC3B02A6C12C@llvm.org> Author: ahatanak Date: Wed Sep 28 13:11:19 2011 New Revision: 140705 URL: http://llvm.org/viewvc/llvm-project?rev=140705&view=rev Log: Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit. Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=140705&r1=140704&r2=140705&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Wed Sep 28 13:11:19 2011 @@ -54,7 +54,8 @@ // Feature predicates. //===----------------------------------------------------------------------===// -def In32BitMode : Predicate<"!Subtarget.isFP64bit()">; +def IsFP64bit : Predicate<"Subtarget.isFP64bit()">; +def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">; def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">; def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">; @@ -78,7 +79,7 @@ !strconcat(asmstr, ".s\t$fd, $fs"), []>; def _D32 : FFR<0x11, funct, 0x1, (outs FGR32:$fd), (ins AFGR64:$fs), - !strconcat(asmstr, ".d\t$fd, $fs"), []>, Requires<[In32BitMode]>; + !strconcat(asmstr, ".d\t$fd, $fs"), []>, Requires<[NotFP64bit]>; } multiclass FFR1_2 funct, string asmstr, SDNode FOp> @@ -89,7 +90,7 @@ def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs), !strconcat(asmstr, ".d\t$fd, $fs"), - [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>; + [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[NotFP64bit]>; } class FFR1_3 funct, bits<5> fmt, RegisterClass RcSrc, @@ -109,7 +110,7 @@ (ins AFGR64:$fs, AFGR64:$ft), !strconcat(asmstr, ".d\t$fd, $fs, $ft"), [(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>, - Requires<[In32BitMode]>; + Requires<[NotFP64bit]>; } } @@ -258,7 +259,7 @@ def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc), "c.$cc.d\t$fs, $ft", [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>, - Requires<[In32BitMode]>; + Requires<[NotFP64bit]>; } @@ -276,7 +277,7 @@ def MOVZ_S : CondMovIntFP; def MOVN_S : CondMovIntFP; -let Predicates = [In32BitMode] in { +let Predicates = [NotFP64bit] in { def MOVZ_D : CondMovIntFP; def MOVN_D : CondMovIntFP; } @@ -284,7 +285,7 @@ defm : MovzPats; defm : MovnPats; -let Predicates = [In32BitMode] in { +let Predicates = [NotFP64bit] in { defm : MovzPats; defm : MovnPats; } @@ -309,7 +310,7 @@ def MOVT_S : CondMovFPFP; def MOVF_S : CondMovFPFP; -let Predicates = [In32BitMode] in { +let Predicates = [NotFP64bit] in { def MOVT_D : CondMovFPFP; def MOVF_D : CondMovFPFP; } @@ -357,7 +358,7 @@ def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>; def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>; -let Predicates = [In32BitMode] in { +let Predicates = [NotFP64bit] in { def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>; def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>; } From justin.holewinski at gmail.com Wed Sep 28 13:24:58 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Wed, 28 Sep 2011 18:24:58 -0000 Subject: [llvm-commits] [llvm] r140709 - /llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Message-ID: <20110928182458.5CC652A6C12C@llvm.org> Author: jholewinski Date: Wed Sep 28 13:24:58 2011 New Revision: 140709 URL: http://llvm.org/viewvc/llvm-project?rev=140709&view=rev Log: PTX: Fix alignment logic Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140709&r1=140708&r2=140709&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Wed Sep 28 13:24:58 2011 @@ -444,7 +444,7 @@ unsigned alignment = gv->getAlignment(); if (alignment != 0) { decl += ".align "; - decl += utostr(std::max(1U, Log2_32(gv->getAlignment()))); + decl += utostr(gv->getAlignment()); decl += " "; } From clattner at apple.com Wed Sep 28 13:27:04 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 28 Sep 2011 11:27:04 -0700 Subject: [llvm-commits] [patch] SystemZ Backend 80 columns. In-Reply-To: References: Message-ID: <3BB9DE9F-6208-4565-AEDF-6BFC5B87C8C2@apple.com> These patches all look fine, please commit them. If you don't have commit access, please make one large diff to make it easier to commit. Thanks! -Chris On Sep 23, 2011, at 6:02 AM, Liu wrote: > Hi all > > SystemZ Backend 80 columns. > > --Liu > <0001-SYSTEMZ-Backend-80-columns.patch>_______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From justin.holewinski at gmail.com Wed Sep 28 13:27:54 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Wed, 28 Sep 2011 14:27:54 -0400 Subject: [llvm-commits] [llvm] r140624 - /llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp In-Reply-To: References: <20110927192550.28C742A6C12C@llvm.org> Message-ID: On Wed, Sep 28, 2011 at 12:25 PM, Eli Friedman wrote: > On Wed, Sep 28, 2011 at 4:58 AM, Justin Holewinski > wrote: > > On Tue, Sep 27, 2011 at 4:01 PM, Eli Friedman > > wrote: > >> > >> On Tue, Sep 27, 2011 at 12:25 PM, Justin Holewinski > >> wrote: > >> > Author: jholewinski > >> > Date: Tue Sep 27 14:25:49 2011 > >> > New Revision: 140624 > >> > > >> > URL: http://llvm.org/viewvc/llvm-project?rev=140624&view=rev > >> > Log: > >> > PTX: Fix case where printed alignment could be 0 > >> > > >> > Modified: > >> > llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp > >> > > >> > Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp > >> > URL: > >> > > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=140624&r1=140623&r2=140624&view=diff > >> > > >> > > ============================================================================== > >> > --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) > >> > +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Tue Sep 27 14:25:49 > 2011 > >> > @@ -480,7 +480,7 @@ > >> > unsigned alignment = gv->getAlignment(); > >> > if (alignment != 0) { > >> > decl += ".align "; > >> > - decl += utostr(Log2_32(gv->getAlignment())); > >> > + decl += utostr(std::max(1U, Log2_32(gv->getAlignment()))); > >> > decl += " "; > >> > } > >> > >> This looks wrong: you're making sure the alignment is at least 2 bytes?! > > > > No, this is making sure it is at least 1 byte. There were some cases > where > > the Log2 function was returning 0. > > log2(1) == 0. log2(2) == 1. Hence, your patch enforces a minimum > alignment of 2 bytes. > Ah, I see the source of the confusion. I was actually fixing the wrong bug. :) The log shouldn't even be there, not sure when it made it in. Anyway, its fixed in r140709 now. > > -Eli > -- Thanks, Justin Holewinski -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110928/a7bf92ed/attachment.html From clattner at apple.com Wed Sep 28 13:28:52 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 28 Sep 2011 11:28:52 -0700 Subject: [llvm-commits] [llvm] r140332 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/haddsub.ll In-Reply-To: <4E7CB0E3.7010700@free.fr> References: <20110922201549.548402A6C12D@llvm.org> <451683E3-A32C-4905-A05A-364A33747D2F@apple.com> <4E7CB0E3.7010700@free.fr> Message-ID: <8DE35B46-A7D1-4112-84FA-78C7429371FE@apple.com> Thanks! So many minuses! :) -Chris On Sep 23, 2011, at 9:16 AM, Duncan Sands wrote: > Hi Chris, > >>> Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from >>> floating point add/sub of appropriate shuffle vectors. Does not >>> synthesize the 256 bit AVX versions because they work differently. >> >> Very cool Duncan. Would it make sense to legalize the intrinsics for these into the X86ISD nodes to avoid the duplicate patterns? > > good idea! I implemented this in commit 140383. > > Ciao, Duncan. From clattner at apple.com Wed Sep 28 13:32:22 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 28 Sep 2011 11:32:22 -0700 Subject: [llvm-commits] [llvm] r140548 - /llvm/trunk/lib/Target/PTX/PTXInstrInfo.td In-Reply-To: <20110926185725.0079D2A6C12C@llvm.org> References: <20110926185725.0079D2A6C12C@llvm.org> Message-ID: <8BAE362F-1046-4AC2-94FA-72879F9CECCE@apple.com> On Sep 26, 2011, at 11:57 AM, Justin Holewinski wrote: > Author: jholewinski > Date: Mon Sep 26 13:57:24 2011 > New Revision: 140548 > > URL: http://llvm.org/viewvc/llvm-project?rev=140548&view=rev > Log: > PTX: Implement ISD::ANY_EXTEND Hi Justin, Would it make more sense to define these as Pat<> patterns (which map to existing instructions) than as new instructions? -Chris > > Modified: > llvm/trunk/lib/Target/PTX/PTXInstrInfo.td > > Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=140548&r1=140547&r2=140548&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original) > +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Mon Sep 26 13:57:24 2011 > @@ -849,6 +849,18 @@ > : InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a", > [(set RegF64:$d, (fextend RegF32:$a))]>; > > +// NOTE: These are temporarily here to help test some Clang-generated code. > +// We really need to properly introduce anyext and bitconvert into the back-end. > +// ANY_EXTEND > +def ANY_EXTEND_I64_I32 > + : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a", > + [(set RegI64:$d, (anyext RegI32:$a))]>; > + > +// BITCAST > +def BITCAST_I32_F32 > + : InstPTX<(outs RegI32:$d), (ins RegF32:$a), "mov.b32\t$d, $a", > + [(set RegI32:$d, (bitconvert RegF32:$a))]>; > + > ///===- Control Flow Instructions -----------------------------------------===// > > let isBranch = 1, isTerminator = 1, isBarrier = 1 in { > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Wed Sep 28 13:50:00 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 28 Sep 2011 18:50:00 -0000 Subject: [llvm-commits] [llvm] r140712 - in /llvm/trunk/tools: Makefile llvm-cov/ llvm-cov/CMakeLists.txt llvm-cov/GCOVReader.cpp llvm-cov/GCOVReader.h llvm-cov/Makefile llvm-cov/llvm-cov.cpp Message-ID: <20110928185000.CBF0D2A6C12C@llvm.org> Author: dpatel Date: Wed Sep 28 13:50:00 2011 New Revision: 140712 URL: http://llvm.org/viewvc/llvm-project?rev=140712&view=rev Log: Introduce llvm-cov. Add llvm-cov skeleton. It has initial support to read coverage info generated by GCOVProfiling.cpp. Today, you can do prompt> clang a.c -ftest-coverage -fprofile-arcs -o a prompt> ./a prompt> llvm-cov -gcno a.gcno -gcda a.gcda a.c : #include "a.h" : : int main() { : int i = 0; : if (i) { 1: int j = 0; 1: j = 1; 1: } else { : int k = 1; : k = 2; : } 1: return 0; : } : : Added: llvm/trunk/tools/llvm-cov/ llvm/trunk/tools/llvm-cov/CMakeLists.txt llvm/trunk/tools/llvm-cov/GCOVReader.cpp llvm/trunk/tools/llvm-cov/GCOVReader.h llvm/trunk/tools/llvm-cov/Makefile llvm/trunk/tools/llvm-cov/llvm-cov.cpp Modified: llvm/trunk/tools/Makefile Modified: llvm/trunk/tools/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=140712&r1=140711&r2=140712&view=diff ============================================================================== --- llvm/trunk/tools/Makefile (original) +++ llvm/trunk/tools/Makefile Wed Sep 28 13:50:00 2011 @@ -26,7 +26,7 @@ lli llvm-extract llvm-mc \ bugpoint llvm-bcanalyzer llvm-stub \ llvm-diff macho-dump llvm-objdump \ - llvm-rtdyld llvm-dwarfdump + llvm-rtdyld llvm-dwarfdump llvm-cov # Let users override the set of tools to build from the command line. ifdef ONLY_TOOLS Added: llvm/trunk/tools/llvm-cov/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-cov/CMakeLists.txt?rev=140712&view=auto ============================================================================== --- llvm/trunk/tools/llvm-cov/CMakeLists.txt (added) +++ llvm/trunk/tools/llvm-cov/CMakeLists.txt Wed Sep 28 13:50:00 2011 @@ -0,0 +1,6 @@ +set(LLVM_LINK_COMPONENTS instrumentation ) + +add_llvm_tool(llvm-cov + GCOVReader.cpp + llvm-cov.cpp + ) Added: llvm/trunk/tools/llvm-cov/GCOVReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-cov/GCOVReader.cpp?rev=140712&view=auto ============================================================================== --- llvm/trunk/tools/llvm-cov/GCOVReader.cpp (added) +++ llvm/trunk/tools/llvm-cov/GCOVReader.cpp Wed Sep 28 13:50:00 2011 @@ -0,0 +1,276 @@ +//===- tools/llvm-cov/GCOVReader.cpp - LLVM coverage tool -----------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// GCOVReader implements the interface to read coverage files that use 'gcov' +// format. +// +// +//===----------------------------------------------------------------------===// + +#include "GCOVReader.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/OwningPtr.h" +#include "llvm/Support/MemoryObject.h" +#include "llvm/Support/system_error.h" +using namespace llvm; + +//===----------------------------------------------------------------------===// +// GCOVFile implementation. + +/// ~GCOVFile - Delete GCOVFile and its content. +GCOVFile::~GCOVFile() { + DeleteContainerPointers(Functions); +} + +/// read - Read GCOV buffer. +bool GCOVFile::read(GCOVBuffer &Buffer) { + Format = Buffer.readGCOVFormat(); + if (Format == InvalidGCOV) + return false; + + unsigned i = 0; + while(1) { + GCOVFunction *GFun = NULL; + if(Format == GCDA_402 || Format == GCDA_404) { + if (i < Functions.size()) + GFun = Functions[i]; + } else + GFun = new GCOVFunction(); + + if (GFun && GFun->read(Buffer, Format)) { + if(Format == GCNO_402 || Format == GCNO_404) + Functions.push_back(GFun); + } + else { + delete GFun; + break; + } + ++i; + } + return true; +} + +/// dump - Dump GCOVFile content on standard out for debugging purposes. +void GCOVFile::dump() { + for (SmallVector::iterator I = Functions.begin(), + E = Functions.end(); I != E; ++I) + (*I)->dump(); +} + +/// collectLineCounts - Collect line counts. This must be used after +/// reading .gcno and .gcda files. +void GCOVFile::collectLineCounts(FileInfo &FI) { + for (SmallVector::iterator I = Functions.begin(), + E = Functions.end(); I != E; ++I) + (*I)->collectLineCounts(FI); + FI.print(); +} + +//===----------------------------------------------------------------------===// +// GCOVFunction implementation. + +/// ~GCOVFunction - Delete GCOVFunction and its content. +GCOVFunction::~GCOVFunction() { + DeleteContainerPointers(Blocks); +} + +/// read - Read a aunction from the buffer. Return false if buffer cursor +/// does not point to a function tag. +bool GCOVFunction::read(GCOVBuffer &Buff, GCOVFormat Format) { + if (!Buff.readFunctionTag()) + return false; + + Buff.readInt(); // Function header length + Ident = Buff.readInt(); + Buff.readInt(); // Checksum #1 + if (Format != GCNO_402) + Buff.readInt(); // Checksum #2 + + Name = Buff.readString(); + if(Format == GCNO_402 || Format == GCNO_404) + Filename = Buff.readString(); + + if(Format == GCDA_402 || Format == GCDA_404) { + Buff.readArcTag(); + uint32_t Count = Buff.readInt() / 2; + for (unsigned i = 0, e = Count; i != e; ++i) { + Blocks[i]->addCount(Buff.readInt64()); + } + return true;; + } + + LineNumber = Buff.readInt(); + + // read blocks. + assert (Buff.readBlockTag() && "Block Tag not found!"); + uint32_t BlockCount = Buff.readInt(); + for (int i = 0, e = BlockCount; i != e; ++i) { + Buff.readInt(); // Block flags; + Blocks.push_back(new GCOVBlock(i)); + } + + // read edges. + while (Buff.readEdgeTag()) { + uint32_t EdgeCount = (Buff.readInt() - 1) / 2; + uint32_t BlockNo = Buff.readInt(); + assert (BlockNo < BlockCount && "Unexpected Block number!"); + for (int i = 0, e = EdgeCount; i != e; ++i) { + Blocks[BlockNo]->addEdge(Buff.readInt()); + Buff.readInt(); // Edge flag + } + } + + // read line table. + while (Buff.readLineTag()) { + uint32_t LineTableLength = Buff.readInt(); + uint32_t Size = Buff.getCursor() + LineTableLength*4; + uint32_t BlockNo = Buff.readInt(); + assert (BlockNo < BlockCount && "Unexpected Block number!"); + GCOVBlock *Block = Blocks[BlockNo]; + Buff.readInt(); // flag + while (Buff.getCursor() != (Size - 4)) { + StringRef Filename = Buff.readString(); + if (Buff.getCursor() == (Size - 4)) break; + while (uint32_t L = Buff.readInt()) + Block->addLine(Filename, L); + } + Buff.readInt(); // flag + } + return true; +} + +/// dump - Dump GCOVFunction content on standard out for debugging purposes. +void GCOVFunction::dump() { + outs() << "===== " << Name << " @ " << Filename << ":" << LineNumber << "\n"; + for (SmallVector::iterator I = Blocks.begin(), + E = Blocks.end(); I != E; ++I) + (*I)->dump(); +} + +/// collectLineCounts - Collect line counts. This must be used after +/// reading .gcno and .gcda files. +void GCOVFunction::collectLineCounts(FileInfo &FI) { + for (SmallVector::iterator I = Blocks.begin(), + E = Blocks.end(); I != E; ++I) + (*I)->collectLineCounts(FI); +} + +//===----------------------------------------------------------------------===// +// GCOVBlock implementation. + +/// ~GCOVBlock - Delete GCOVBlock and its content. +GCOVBlock::~GCOVBlock() { + Edges.clear(); + DeleteContainerSeconds(Lines); +} + +void GCOVBlock::addLine(StringRef Filename, uint32_t LineNo) { + GCOVLines *&LinesForFile = Lines[Filename]; + if (!LinesForFile) + LinesForFile = new GCOVLines(); + LinesForFile->add(LineNo); +} + +/// collectLineCounts - Collect line counts. This must be used after +/// reading .gcno and .gcda files. +void GCOVBlock::collectLineCounts(FileInfo &FI) { + for (StringMap::iterator I = Lines.begin(), + E = Lines.end(); I != E; ++I) + I->second->collectLineCounts(FI, I->first(), Counter); +} + +/// dump - Dump GCOVBlock content on standard out for debugging purposes. +void GCOVBlock::dump() { + outs() << "Block : " << Number << " Counter : " << Counter << "\n"; + if (!Edges.empty()) { + outs() << "\tEdges : "; + for (SmallVector::iterator I = Edges.begin(), E = Edges.end(); + I != E; ++I) + outs() << (*I) << ","; + outs() << "\n"; + } + if (!Lines.empty()) { + outs() << "\tLines : "; + for (StringMap::iterator LI = Lines.begin(), + LE = Lines.end(); LI != LE; ++LI) { + outs() << LI->first() << " -> "; + LI->second->dump(); + outs() << "\n"; + } + } +} + +//===----------------------------------------------------------------------===// +// GCOVLines implementation. + +/// collectLineCounts - Collect line counts. This must be used after +/// reading .gcno and .gcda files. +void GCOVLines::collectLineCounts(FileInfo &FI, StringRef Filename, + uint32_t Count) { + for (SmallVector::iterator I = Lines.begin(), + E = Lines.end(); I != E; ++I) + FI.addLineCount(Filename, *I, Count); +} + +/// dump - Dump GCOVLines content on standard out for debugging purposes. +void GCOVLines::dump() { + for (SmallVector::iterator I = Lines.begin(), + E = Lines.end(); I != E; ++I) + outs() << (*I) << ","; +} + +//===----------------------------------------------------------------------===// +// FileInfo implementation. + +/// addLineCount - Add line count for the given line number in a file. +void FileInfo::addLineCount(StringRef Filename, uint32_t Line, uint32_t Count) { + if (LineInfo.find(Filename) == LineInfo.end()) { + OwningPtr Buff; + if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename, Buff)) { + errs() << Filename << ": " << ec.message() << "\n"; + return; + } + StringRef AllLines = Buff.take()->getBuffer(); + LineCounts L(AllLines.count('\n')+2); + L[Line-1] = Count; + LineInfo[Filename] = L; + return; + } + LineCounts &L = LineInfo[Filename]; + L[Line-1] = Count; +} + +/// print - Print source files with collected line count information. +void FileInfo::print() { + for (StringMap::iterator I = LineInfo.begin(), E = LineInfo.end(); + I != E; ++I) { + StringRef Filename = I->first(); + outs() << Filename << "\n"; + LineCounts &L = LineInfo[Filename]; + OwningPtr Buff; + if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename, Buff)) { + errs() << Filename << ": " << ec.message() << "\n"; + return; + } + StringRef AllLines = Buff.take()->getBuffer(); + for (unsigned i = 0, e = L.size(); i != e; ++i) { + if (L[i]) + outs() << L[i] << ":\t"; + else + outs() << " :\t"; + std::pair P = AllLines.split('\n'); + if (AllLines != P.first) + outs() << P.first; + outs() << "\n"; + AllLines = P.second; + } + } +} + + Added: llvm/trunk/tools/llvm-cov/GCOVReader.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-cov/GCOVReader.h?rev=140712&view=auto ============================================================================== --- llvm/trunk/tools/llvm-cov/GCOVReader.h (added) +++ llvm/trunk/tools/llvm-cov/GCOVReader.h Wed Sep 28 13:50:00 2011 @@ -0,0 +1,225 @@ +//===-- tools/cov/GCOVReader.h - LLVM coverage tool -------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This header provides the interface to read coverage files that use 'gcov' +// format. +// +//===----------------------------------------------------------------------===// + +#ifndef GCOVREADER_H +#define GCOVREADER_H + +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringMap.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/raw_ostream.h" + +namespace llvm { + +class GCOVFunction; +class GCOVBlock; +class GCOVLines; +class FileInfo; + +enum GCOVFormat { + InvalidGCOV, + GCNO_402, + GCNO_404, + GCDA_402, + GCDA_404 +}; + +/// GCOVBuffer - A wrapper around MemoryBuffer to provid GCOV specific +/// read operations. +class GCOVBuffer { +public: + GCOVBuffer(MemoryBuffer *B) : Buffer(B), Cursor(0) {} + + /// readGCOVFormat - Read GCOV signature at the beginning of buffer. + enum GCOVFormat readGCOVFormat() { + StringRef Magic = Buffer->getBuffer().slice(0, 12); + Cursor = 12; + if (Magic == "oncg*404MVLL") + return GCNO_404; + else if (Magic == "oncg*204MVLL") + return GCNO_402; + else if (Magic == "adcg*404MVLL") + return GCDA_404; + else if (Magic == "adcg*204MVLL") + return GCDA_402; + + Cursor = 0; + return InvalidGCOV; + } + + /// readFunctionTag - If cursor points to a function tag then increment the + /// cursor and return true otherwise return false. + bool readFunctionTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4); + if (Tag.empty() || + Tag[0] != '\0' || Tag[1] != '\0' || + Tag[2] != '\0' || Tag[3] != '\1') { + return false; + } + Cursor += 4; + return true; + } + + /// readBlockTag - If cursor points to a block tag then increment the + /// cursor and return true otherwise return false. + bool readBlockTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4); + if (Tag.empty() || + Tag[0] != '\0' || Tag[1] != '\0' || + Tag[2] != '\x41' || Tag[3] != '\x01') { + return false; + } + Cursor += 4; + return true; + } + + /// readEdgeTag - If cursor points to an edge tag then increment the + /// cursor and return true otherwise return false. + bool readEdgeTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4); + if (Tag.empty() || + Tag[0] != '\0' || Tag[1] != '\0' || + Tag[2] != '\x43' || Tag[3] != '\x01') { + return false; + } + Cursor += 4; + return true; + } + + /// readLineTag - If cursor points to a line tag then increment the + /// cursor and return true otherwise return false. + bool readLineTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4); + if (Tag.empty() || + Tag[0] != '\0' || Tag[1] != '\0' || + Tag[2] != '\x45' || Tag[3] != '\x01') { + return false; + } + Cursor += 4; + return true; + } + + /// readArcTag - If cursor points to an gcda arc tag then increment the + /// cursor and return true otherwise return false. + bool readArcTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4); + if (Tag.empty() || + Tag[0] != '\0' || Tag[1] != '\0' || + Tag[2] != '\xa1' || Tag[3] != '\1') { + return false; + } + Cursor += 4; + return true; + } + + uint32_t readInt() { + uint32_t Result; + StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor+4); + assert (Str.empty() == false && "Unexpected memory buffer end!"); + Cursor += 4; + Result = *(uint32_t *)(Str.data()); + return Result; + } + + uint64_t readInt64() { + uint64_t Lo = readInt(); + uint64_t Hi = readInt(); + uint64_t Result = Lo | (Hi << 32); + return Result; + } + + StringRef readString() { + uint32_t Len = readInt() * 4; + StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor+Len); + Cursor += Len; + return Str; + } + + uint64_t getCursor() const { return Cursor; } +private: + MemoryBuffer *Buffer; + uint64_t Cursor; +}; + +/// GCOVFile - Collects file information. +class GCOVFile { +public: + GCOVFile() : Format(InvalidGCOV) {} + ~GCOVFile(); + bool read(GCOVBuffer &Buffer); + void dump(); + void collectLineCounts(FileInfo &FI); +private: + enum GCOVFormat Format; + SmallVector Functions; +}; + +/// GCOVFunction - Collects function information. +class GCOVFunction { +public: + GCOVFunction() : Ident(0), LineNumber(0) {} + ~GCOVFunction(); + bool read(GCOVBuffer &Buffer, GCOVFormat Format); + void dump(); + void collectLineCounts(FileInfo &FI); +private: + uint32_t Ident; + uint32_t LineNumber; + StringRef Name; + StringRef Filename; + SmallVector Blocks; +}; + +/// GCOVBlock - Collects block information. +class GCOVBlock { +public: + GCOVBlock(uint32_t N) : Number(N), Counter(0) {} + ~GCOVBlock(); + void addEdge(uint32_t N) { Edges.push_back(N); } + void addLine(StringRef Filename, uint32_t LineNo); + void addCount(uint64_t N) { Counter = N; } + void dump(); + void collectLineCounts(FileInfo &FI); +private: + uint32_t Number; + uint64_t Counter; + SmallVector Edges; + StringMap Lines; +}; + +/// GCOVLines - A wrapper around a vector of int to keep track of line nos. +class GCOVLines { +public: + ~GCOVLines() { Lines.clear(); } + void add(uint32_t N) { Lines.push_back(N); } + void collectLineCounts(FileInfo &FI, StringRef Filename, uint32_t Count); + void dump(); + +private: + SmallVector Lines; +}; + +typedef SmallVector LineCounts; +class FileInfo { +public: + void addLineCount(StringRef Filename, uint32_t Line, uint32_t Count); + void print(); +private: + StringMap LineInfo; +}; + + +} + +#endif Added: llvm/trunk/tools/llvm-cov/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-cov/Makefile?rev=140712&view=auto ============================================================================== --- llvm/trunk/tools/llvm-cov/Makefile (added) +++ llvm/trunk/tools/llvm-cov/Makefile Wed Sep 28 13:50:00 2011 @@ -0,0 +1,18 @@ +##===- tools/llvm-gcov/Makefile ----------------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../.. + +TOOLNAME = llvm-cov +LINK_COMPONENTS := instrumentation + +# This tool has no plugins, optimize startup time. +TOOL_NO_EXPORTS = 1 + +include $(LEVEL)/Makefile.common Added: llvm/trunk/tools/llvm-cov/llvm-cov.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-cov/llvm-cov.cpp?rev=140712&view=auto ============================================================================== --- llvm/trunk/tools/llvm-cov/llvm-cov.cpp (added) +++ llvm/trunk/tools/llvm-cov/llvm-cov.cpp Wed Sep 28 13:50:00 2011 @@ -0,0 +1,83 @@ +//===- tools/llvm-cov/llvm-cov.cpp - LLVM coverage tool -------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +// llvm-cov is a command line tools to analyze and report coverage information. +// +// +//===----------------------------------------------------------------------===// + +#include "GCOVReader.h" +#include "llvm/ADT/OwningPtr.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/ManagedStatic.h" +#include "llvm/Support/MemoryObject.h" +#include "llvm/Support/PrettyStackTrace.h" +#include "llvm/Support/Signals.h" +#include "llvm/Support/system_error.h" +using namespace llvm; + +static cl::opt +DumpGCOV("dump", cl::init(false), cl::desc("dump gcov file")); + +static cl::opt +InputGCNO("gcno", cl::desc(""), cl::init("")); + +static cl::opt +InputGCDA("gcda", cl::desc(""), cl::init("")); + + +//===----------------------------------------------------------------------===// +int main(int argc, char **argv) { + // Print a stack trace if we signal out. + sys::PrintStackTraceOnErrorSignal(); + PrettyStackTraceProgram X(argc, argv); + llvm_shutdown_obj Y; // Call llvm_shutdown() on exit. + + cl::ParseCommandLineOptions(argc, argv, "llvm cov\n"); + + + GCOVFile GF; + if (InputGCNO.empty()) + errs() << " " << argv[0] << ": No gcov input file!\n"; + + OwningPtr Buff; + if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputGCNO, Buff)) { + errs() << InputGCNO << ": " << ec.message() << "\n"; + return 1; + } + GCOVBuffer GB(Buff.take()); + + if (!GF.read(GB)) { + errs() << "Invalid .gcno File!\n"; + return 1; + } + + if (!InputGCDA.empty()) { + OwningPtr Buff2; + if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputGCDA, Buff2)) { + errs() << InputGCDA << ": " << ec.message() << "\n"; + return 1; + } + GCOVBuffer GB2(Buff2.take()); + + if (!GF.read(GB2)) { + errs() << "Invalid .gcda File!\n"; + return 1; + } + } + + + if (DumpGCOV) + GF.dump(); + + FileInfo FI; + GF.collectLineCounts(FI); + return 0; +} From echristo at apple.com Wed Sep 28 14:47:28 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 28 Sep 2011 19:47:28 -0000 Subject: [llvm-commits] [llvm] r140715 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20110928194728.E96B92A6C130@llvm.org> Author: echristo Date: Wed Sep 28 14:47:28 2011 New Revision: 140715 URL: http://llvm.org/viewvc/llvm-project?rev=140715&view=rev Log: Add a note on removing LLVMC. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=140715&r1=140714&r2=140715&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Wed Sep 28 14:47:28 2011 @@ -581,6 +581,8 @@ from the previous release.

      +
    • The LLVMC front end code was removed while separating + out language independence.
    • The LowerSetJmp pass wasn't used effectively by any target and has been removed.
    • The old TailDup pass was not used in the standard pipeline From isanbard at gmail.com Wed Sep 28 15:29:28 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 28 Sep 2011 20:29:28 -0000 Subject: [llvm-commits] [llvm] r140718 - /llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Message-ID: <20110928202928.7B5782A6C12C@llvm.org> Author: void Date: Wed Sep 28 15:29:28 2011 New Revision: 140718 URL: http://llvm.org/viewvc/llvm-project?rev=140718&view=rev Log: Ahem...actually *add* the ARMSjLjLowering pass to the pass manager. Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=140718&r1=140717&r2=140718&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Sep 28 15:29:28 2011 @@ -109,7 +109,7 @@ if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9()) PM.add(createMLxExpansionPass()); if (getMCAsmInfo()->getExceptionHandlingType() == ExceptionHandling::SjLj) - createARMSjLjLoweringPass(); + PM.add(createARMSjLjLoweringPass()); return true; } From isanbard at gmail.com Wed Sep 28 15:29:45 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 28 Sep 2011 20:29:45 -0000 Subject: [llvm-commits] [llvm] r140719 - /llvm/trunk/lib/Target/ARM/ARMSjLjLoweringPass.cpp Message-ID: <20110928202945.A3A982A6C12C@llvm.org> Author: void Date: Wed Sep 28 15:29:45 2011 New Revision: 140719 URL: http://llvm.org/viewvc/llvm-project?rev=140719&view=rev Log: Perform the lowering only if there are invokes. Modified: llvm/trunk/lib/Target/ARM/ARMSjLjLoweringPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMSjLjLoweringPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSjLjLoweringPass.cpp?rev=140719&r1=140718&r2=140719&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSjLjLoweringPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSjLjLoweringPass.cpp Wed Sep 28 15:29:45 2011 @@ -35,14 +35,14 @@ LLVMContext *Context; MachineFunction *MF; - const Function *Fn; + const Function *F; const TargetLowering *TLI; const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; - /// createFunctionContext - Create the function context on the stack. This - /// returns the nonnegative identifier representing it in the FrameInfo. - int createFunctionContext(); + /// setupFunctionContext - Setup the function context on the stack. Some of + /// the fields were set by the SjLj EH prepare pass. + int setupFunctionContext(); public: static char ID; @@ -67,19 +67,29 @@ if (!EnableNewSjLjEHPrepare) return false; MF = &mf; - Fn = MF->getFunction(); - Context = &Fn->getContext(); + F = MF->getFunction(); + Context = &F->getContext(); TLI = MF->getTarget().getTargetLowering(); TII = MF->getTarget().getInstrInfo(); TRI = MF->getTarget().getRegisterInfo(); - int FrameIdx = createFunctionContext(); (void)FrameIdx; + // Perform the lowering only if there are invokes. + bool HasInvokes = false; + for (Function::const_iterator BB = F->begin(), E = F->end(); BB != E; ++BB) + if (isa(BB->getTerminator())) { + HasInvokes = true; + break; + } + + if (!HasInvokes) return false; + + int FrameIdx = setupFunctionContext(); (void)FrameIdx; return true; } -/// createFunctionContext - Create the function context on the stack. -int ARMSjLjLowering::createFunctionContext() { +/// setupFunctionContext - Create the function context on the stack. +int ARMSjLjLowering::setupFunctionContext() { // struct _Unwind_FunctionContext { // // next function in stack of handlers. // struct _Unwind_FunctionContext *prev; From eli.friedman at gmail.com Wed Sep 28 15:41:50 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 28 Sep 2011 20:41:50 -0000 Subject: [llvm-commits] [llvm] r140720 - /llvm/trunk/unittests/Support/TypeBuilderTest.cpp Message-ID: <20110928204150.8DFA22A6C12C@llvm.org> Author: efriedma Date: Wed Sep 28 15:41:50 2011 New Revision: 140720 URL: http://llvm.org/viewvc/llvm-project?rev=140720&view=rev Log: NULL cannot be portably used as the last argument to a function with __attribute((sentinel)), even though it usually works. Use (void*)0 instead. PR11002. Modified: llvm/trunk/unittests/Support/TypeBuilderTest.cpp Modified: llvm/trunk/unittests/Support/TypeBuilderTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/TypeBuilderTest.cpp?rev=140720&r1=140719&r2=140720&view=diff ============================================================================== --- llvm/trunk/unittests/Support/TypeBuilderTest.cpp (original) +++ llvm/trunk/unittests/Support/TypeBuilderTest.cpp Wed Sep 28 15:41:50 2011 @@ -235,19 +235,19 @@ TypeBuilder::get(getGlobalContext()), TypeBuilder::get(getGlobalContext()), TypeBuilder::get(getGlobalContext()), - NULL)), + (void*)0)), (TypeBuilder::get(getGlobalContext()))); EXPECT_EQ(PointerType::getUnqual(StructType::get( TypeBuilder, false>::get(getGlobalContext()), TypeBuilder*, false>::get(getGlobalContext()), TypeBuilder*[], false>::get(getGlobalContext()), - NULL)), + (void*)0)), (TypeBuilder::get(getGlobalContext()))); EXPECT_EQ(PointerType::getUnqual(StructType::get( TypeBuilder, false>::get(getGlobalContext()), TypeBuilder*, false>::get(getGlobalContext()), TypeBuilder*[], false>::get(getGlobalContext()), - NULL)), + (void*)0)), (TypeBuilder::get(getGlobalContext()))); } From bigcheesegs at gmail.com Wed Sep 28 15:57:30 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 28 Sep 2011 20:57:30 -0000 Subject: [llvm-commits] [llvm] r140721 - in /llvm/trunk: include/llvm/Object/COFF.h include/llvm/Object/ObjectFile.h lib/Object/COFFObjectFile.cpp lib/Object/ELFObjectFile.cpp lib/Object/MachOObjectFile.cpp Message-ID: <20110928205730.480B42A6C12C@llvm.org> Author: mspencer Date: Wed Sep 28 15:57:30 2011 New Revision: 140721 URL: http://llvm.org/viewvc/llvm-project?rev=140721&view=rev Log: Object: Add isSection{Data,BSS}. Modified: llvm/trunk/include/llvm/Object/COFF.h llvm/trunk/include/llvm/Object/ObjectFile.h llvm/trunk/lib/Object/COFFObjectFile.cpp llvm/trunk/lib/Object/ELFObjectFile.cpp llvm/trunk/lib/Object/MachOObjectFile.cpp Modified: llvm/trunk/include/llvm/Object/COFF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=140721&r1=140720&r2=140721&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/COFF.h (original) +++ llvm/trunk/include/llvm/Object/COFF.h Wed Sep 28 15:57:30 2011 @@ -106,6 +106,8 @@ virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const; virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) const; virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const; + virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const; + virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const; virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Symb, bool &Result) const; Modified: llvm/trunk/include/llvm/Object/ObjectFile.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=140721&r1=140720&r2=140721&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/ObjectFile.h (original) +++ llvm/trunk/include/llvm/Object/ObjectFile.h Wed Sep 28 15:57:30 2011 @@ -131,6 +131,8 @@ // FIXME: Move to the normalization layer when it's created. error_code isText(bool &Result) const; + error_code isData(bool &Result) const; + error_code isBSS(bool &Result) const; error_code containsSymbol(SymbolRef S, bool &Result) const; }; @@ -179,6 +181,8 @@ virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const = 0; virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res)const=0; virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const = 0; + virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const = 0; + virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const = 0; virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Symb, bool &Result) const = 0; @@ -349,6 +353,14 @@ return OwningObject->isSectionText(SectionPimpl, Result); } +inline error_code SectionRef::isData(bool &Result) const { + return OwningObject->isSectionData(SectionPimpl, Result); +} + +inline error_code SectionRef::isBSS(bool &Result) const { + return OwningObject->isSectionBSS(SectionPimpl, Result); +} + inline error_code SectionRef::containsSymbol(SymbolRef S, bool &Result) const { return OwningObject->sectionContainsSymbol(SectionPimpl, S.SymbolPimpl, Result); Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=140721&r1=140720&r2=140721&view=diff ============================================================================== --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Wed Sep 28 15:57:30 2011 @@ -342,6 +342,20 @@ return object_error::success; } +error_code COFFObjectFile::isSectionData(DataRefImpl Sec, + bool &Result) const { + const coff_section *sec = toSec(Sec); + Result = sec->Characteristics & COFF::IMAGE_SCN_CNT_INITIALIZED_DATA; + return object_error::success; +} + +error_code COFFObjectFile::isSectionBSS(DataRefImpl Sec, + bool &Result) const { + const coff_section *sec = toSec(Sec); + Result = sec->Characteristics & COFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA; + return object_error::success; +} + error_code COFFObjectFile::sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Symb, bool &Result) const { Modified: llvm/trunk/lib/Object/ELFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ELFObjectFile.cpp?rev=140721&r1=140720&r2=140721&view=diff ============================================================================== --- llvm/trunk/lib/Object/ELFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/ELFObjectFile.cpp Wed Sep 28 15:57:30 2011 @@ -324,6 +324,8 @@ virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const; virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) const; virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const; + virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const; + virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const; virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Symb, bool &Result) const; @@ -676,6 +678,32 @@ template error_code ELFObjectFile + ::isSectionData(DataRefImpl Sec, + bool &Result) const { + const Elf_Shdr *sec = reinterpret_cast(Sec.p); + if (sec->sh_flags & (ELF::SHF_ALLOC | ELF::SHF_WRITE) + && sec->sh_type == ELF::SHT_PROGBITS) + Result = true; + else + Result = false; + return object_error::success; +} + +template +error_code ELFObjectFile + ::isSectionBSS(DataRefImpl Sec, + bool &Result) const { + const Elf_Shdr *sec = reinterpret_cast(Sec.p); + if (sec->sh_flags & (ELF::SHF_ALLOC | ELF::SHF_WRITE) + && sec->sh_type == ELF::SHT_NOBITS) + Result = true; + else + Result = false; + return object_error::success; +} + +template +error_code ELFObjectFile ::sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Symb, bool &Result) const { Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=140721&r1=140720&r2=140721&view=diff ============================================================================== --- llvm/trunk/lib/Object/MachOObjectFile.cpp (original) +++ llvm/trunk/lib/Object/MachOObjectFile.cpp Wed Sep 28 15:57:30 2011 @@ -63,6 +63,8 @@ virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const; virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) const; virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const; + virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const; + virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const; virtual error_code sectionContainsSymbol(DataRefImpl DRI, DataRefImpl S, bool &Result) const; @@ -480,6 +482,20 @@ return object_error::success; } +error_code MachOObjectFile::isSectionData(DataRefImpl DRI, + bool &Result) const { + // FIXME: Unimplemented. + Result = false; + return object_error::success; +} + +error_code MachOObjectFile::isSectionBSS(DataRefImpl DRI, + bool &Result) const { + // FIXME: Unimplemented. + Result = false; + return object_error::success; +} + error_code MachOObjectFile::sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Symb, bool &Result) const { From bigcheesegs at gmail.com Wed Sep 28 15:57:46 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 28 Sep 2011 20:57:46 -0000 Subject: [llvm-commits] [llvm] r140722 - in /llvm/trunk/tools: CMakeLists.txt Makefile llvm-size/ llvm-size/CMakeLists.txt llvm-size/Makefile llvm-size/llvm-size.cpp Message-ID: <20110928205747.028122A6C12C@llvm.org> Author: mspencer Date: Wed Sep 28 15:57:46 2011 New Revision: 140722 URL: http://llvm.org/viewvc/llvm-project?rev=140722&view=rev Log: Add llvm-size. Added: llvm/trunk/tools/llvm-size/ llvm/trunk/tools/llvm-size/CMakeLists.txt llvm/trunk/tools/llvm-size/Makefile llvm/trunk/tools/llvm-size/llvm-size.cpp Modified: llvm/trunk/tools/CMakeLists.txt llvm/trunk/tools/Makefile Modified: llvm/trunk/tools/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/CMakeLists.txt?rev=140722&r1=140721&r2=140722&view=diff ============================================================================== --- llvm/trunk/tools/CMakeLists.txt (original) +++ llvm/trunk/tools/CMakeLists.txt Wed Sep 28 15:57:46 2011 @@ -28,6 +28,7 @@ add_subdirectory(llvm-ranlib) add_subdirectory(llvm-ar) add_subdirectory(llvm-nm) +add_subdirectory(llvm-size) add_subdirectory(llvm-ld) add_subdirectory(llvm-prof) Modified: llvm/trunk/tools/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=140722&r1=140721&r2=140722&view=diff ============================================================================== --- llvm/trunk/tools/Makefile (original) +++ llvm/trunk/tools/Makefile Wed Sep 28 15:57:46 2011 @@ -26,7 +26,8 @@ lli llvm-extract llvm-mc \ bugpoint llvm-bcanalyzer llvm-stub \ llvm-diff macho-dump llvm-objdump \ - llvm-rtdyld llvm-dwarfdump llvm-cov + llvm-rtdyld llvm-dwarfdump llvm-cov \ + llvm-size # Let users override the set of tools to build from the command line. ifdef ONLY_TOOLS Added: llvm/trunk/tools/llvm-size/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-size/CMakeLists.txt?rev=140722&view=auto ============================================================================== --- llvm/trunk/tools/llvm-size/CMakeLists.txt (added) +++ llvm/trunk/tools/llvm-size/CMakeLists.txt Wed Sep 28 15:57:46 2011 @@ -0,0 +1,5 @@ +set(LLVM_LINK_COMPONENTS object) + +add_llvm_tool(llvm-size + llvm-size.cpp + ) Added: llvm/trunk/tools/llvm-size/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-size/Makefile?rev=140722&view=auto ============================================================================== --- llvm/trunk/tools/llvm-size/Makefile (added) +++ llvm/trunk/tools/llvm-size/Makefile Wed Sep 28 15:57:46 2011 @@ -0,0 +1,17 @@ +##===- tools/llvm-size/Makefile ----------------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## +LEVEL = ../.. + +TOOLNAME = llvm-size +LINK_COMPONENTS = object + +# This tool has no plugins, optimize startup time. +TOOL_NO_EXPORTS = 1 + +include $(LEVEL)/Makefile.common Added: llvm/trunk/tools/llvm-size/llvm-size.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-size/llvm-size.cpp?rev=140722&view=auto ============================================================================== --- llvm/trunk/tools/llvm-size/llvm-size.cpp (added) +++ llvm/trunk/tools/llvm-size/llvm-size.cpp Wed Sep 28 15:57:46 2011 @@ -0,0 +1,298 @@ +//===-- llvm-size.cpp - Print the size of each object section -------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This program is a utility that works like traditional Unix "size", +// that is, it prints out the size of each section, and the total size of all +// sections. +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/APInt.h" +#include "llvm/Object/Archive.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/Format.h" +#include "llvm/Support/ManagedStatic.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/PrettyStackTrace.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Support/Signals.h" +#include "llvm/Support/system_error.h" +#include +#include +using namespace llvm; +using namespace object; + +namespace { + enum OutputFormatTy {berkeley, sysv}; + cl::opt + OutputFormat("format", + cl::desc("Specify output format"), + cl::values(clEnumVal(sysv, "System V format"), + clEnumVal(berkeley, "Berkeley format"), + clEnumValEnd), + cl::init(berkeley)); + + cl::opt + OutputFormatShort(cl::desc("Specify output format"), + cl::values(clEnumValN(sysv, "A", "System V format"), + clEnumValN(berkeley, "B", "Berkeley format"), + clEnumValEnd), + cl::init(berkeley)); + + enum RadixTy {octal = 8, decimal = 10, hexadecimal = 16}; + cl::opt + Radix("-radix", + cl::desc("Print size in radix. Only 8, 10, and 16 are valid"), + cl::init(decimal)); + + cl::opt + RadixShort(cl::desc("Print size in radix:"), + cl::values(clEnumValN(octal, "o", "Print size in octal"), + clEnumValN(decimal, "d", "Print size in decimal"), + clEnumValN(hexadecimal, "x", "Print size in hexadecimal"), + clEnumValEnd), + cl::init(decimal)); + + cl::list + InputFilenames(cl::Positional, cl::desc(""), + cl::ZeroOrMore); + + std::string ToolName; +} + +static bool error(error_code ec) { + if (!ec) return false; + + outs() << ToolName << ": error reading file: " << ec.message() << ".\n"; + outs().flush(); + return true; +} + +static int getNumLengthAsString(uint64_t num) { + APInt conv(64, num); + SmallString<32> result; + conv.toString(result, unsigned int(Radix), false, true); + return result.size(); +} + +static void PrintObjectSectionSizes(ObjectFile *o) { + uint64_t total = 0; + std::string fmtbuf; + raw_string_ostream fmt(fmtbuf); + + const char *radix_fmt = 0; + switch (Radix) { + case octal: + radix_fmt = "llo"; + break; + case decimal: + radix_fmt = "llu"; + break; + case hexadecimal: + radix_fmt = "llx"; + break; + } + if (OutputFormat == sysv) { + // Run two passes over all sections. The first gets the lengths needed for + // formatting the output. The second actually does the output. + std::size_t max_name_len = strlen("section"); + int max_size_len = strlen("size"); + int max_addr_len = strlen("addr"); + error_code ec; + for (ObjectFile::section_iterator i = o->begin_sections(), + e = o->end_sections(); i != e; + i.increment(ec)) { + if (error(ec)) + return; + uint64_t size = 0; + if (error(i->getSize(size))) + return; + total += size; + + StringRef name; + uint64_t addr = 0; + if (error(i->getName(name))) return; + if (error(i->getAddress(addr))) return; + max_name_len = std::max(max_name_len, name.size()); + max_size_len = std::max(max_size_len, getNumLengthAsString(size)); + max_addr_len = std::max(max_addr_len, getNumLengthAsString(addr)); + } + + max_name_len += 2; + max_size_len += 2; + max_addr_len += 2; + + fmt << "%-" << max_name_len << "s " + << "%" << max_size_len << "s " + << "%" << max_addr_len << "s\n"; + + // Print header + outs() << format(fmt.str().c_str(), + static_cast("section"), + static_cast("size"), + static_cast("addr")); + fmtbuf.clear(); + + // Setup per section format. + fmt << "%-" << max_name_len << "s " + << "%#" << max_size_len << radix_fmt << " " + << "%#" << max_addr_len << radix_fmt << "\n"; + + // Print each section. + for (ObjectFile::section_iterator i = o->begin_sections(), + e = o->end_sections(); i != e; + i.increment(ec)) { + if (error(ec)) + return; + + StringRef name; + uint64_t size = 0; + uint64_t addr = 0; + if (error(i->getName(name))) return; + if (error(i->getSize(size))) return; + if (error(i->getAddress(addr))) return; + std::string namestr = name; + + outs() << format(fmt.str().c_str(), + namestr.c_str(), + size, + addr); + } + + // Print total. + fmtbuf.clear(); + fmt << "%-" << max_name_len << "s " + << "%#" << max_size_len << radix_fmt << "\n"; + outs() << format(fmt.str().c_str(), + static_cast("Total"), + total); + } else { + uint64_t total_text = 0; + uint64_t total_data = 0; + uint64_t total_bss = 0; + + error_code ec; + // Collect section data. + for (ObjectFile::section_iterator i = o->begin_sections(), + e = o->end_sections(); i != e; + i.increment(ec)) { + if (error(ec)) + return; + + uint64_t size = 0; + bool isText = false; + bool isData = false; + bool isBSS = false; + if (error(i->getSize(size))) return; + if (error(i->isText(isText))) return; + if (error(i->isData(isData))) return; + if (error(i->isBSS(isBSS))) return; + if (isText) + total_text += size; + else if (isData) + total_data += size; + else if (isBSS) + total_bss += size; + } + + total = total_text + total_data + total_bss; + + // Print result. + fmt << "%#7" << radix_fmt << " " + << "%#7" << radix_fmt << " " + << "%#7" << radix_fmt << " "; + outs() << format(fmt.str().c_str(), + total_text, + total_data, + total_bss); + fmtbuf.clear(); + fmt << "%7" << (Radix == octal ? "llo" : "llu") << " " + << "%7llx "; + outs() << format(fmt.str().c_str(), + total, + total); + } +} + +static void PrintFileSectionSizes(StringRef file) { + // If file is not stdin, check that it exists. + if (file != "-") { + bool exists; + if (sys::fs::exists(file, exists) || !exists) { + errs() << ToolName << ": '" << file << "': " << "No such file\n"; + return; + } + } + + OwningPtr binary; + if (error_code ec = createBinary(file, binary)) { + errs() << ToolName << ": " << file << ": " << ec.message() << ".\n"; + return; + } + + if (Archive *a = dyn_cast(binary.get())) { + for (object::Archive::child_iterator i = a->begin_children(), + e = a->end_children(); i != e; ++i) { + OwningPtr child; + if (error_code ec = i->getAsBinary(child)) { + errs() << ToolName << ": " << file << ": " << ec.message() << ".\n"; + continue; + } + if (ObjectFile *o = dyn_cast(child.get())) { + if (OutputFormat == sysv) + outs() << o->getFileName() << " (ex " << a->getFileName() + << "):\n"; + PrintObjectSectionSizes(o); + if (OutputFormat == berkeley) + outs() << o->getFileName() << " (ex " << a->getFileName() << ")\n"; + } + } + } else if (ObjectFile *o = dyn_cast(binary.get())) { + if (OutputFormat == sysv) + outs() << o->getFileName() << " :\n"; + PrintObjectSectionSizes(o); + if (OutputFormat == berkeley) + outs() << o->getFileName() << "\n"; + } else { + errs() << ToolName << ": " << file << ": " << "Unrecognized file type.\n"; + } + if (OutputFormat == sysv) + outs() << "\n"; +} + +int main(int argc, char **argv) { + // Print a stack trace if we signal out. + sys::PrintStackTraceOnErrorSignal(); + PrettyStackTraceProgram X(argc, argv); + + llvm_shutdown_obj Y; // Call llvm_shutdown() on exit. + cl::ParseCommandLineOptions(argc, argv, "llvm object size dumper\n"); + + ToolName = argv[0]; + if (OutputFormatShort.getNumOccurrences()) + OutputFormat = OutputFormatShort; + if (RadixShort.getNumOccurrences()) + Radix = int(RadixShort); + + if (InputFilenames.size() == 0) + InputFilenames.push_back("a.out"); + + if (OutputFormat == berkeley) + outs() << " text data bss " + << (Radix == int(octal) ? "oct" : "dec") + << " hex filename\n"; + + std::for_each(InputFilenames.begin(), InputFilenames.end(), + PrintFileSectionSizes); + + return 0; +} From eli.friedman at gmail.com Wed Sep 28 16:00:25 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 28 Sep 2011 21:00:25 -0000 Subject: [llvm-commits] [llvm] r140723 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/vec_compare-sse4.ll Message-ID: <20110928210025.A4E262A6C12C@llvm.org> Author: efriedma Date: Wed Sep 28 16:00:25 2011 New Revision: 140723 URL: http://llvm.org/viewvc/llvm-project?rev=140723&view=rev Log: PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them. Added: llvm/trunk/test/CodeGen/X86/vec_compare-sse4.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=140723&r1=140722&r2=140723&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 28 16:00:25 2011 @@ -8555,6 +8555,13 @@ if (Swap) std::swap(Op0, Op1); + // Check that the operation in question is available (most are plain SSE2, + // but PCMPGTQ and PCMPEQQ have different requirements). + if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42() && !Subtarget->hasAVX()) + return SDValue(); + if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41() && !Subtarget->hasAVX()) + return SDValue(); + // Since SSE has no unsigned integer comparisons, we need to flip the sign // bits of the inputs before performing those operations. if (FlipSigns) { Added: llvm/trunk/test/CodeGen/X86/vec_compare-sse4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_compare-sse4.ll?rev=140723&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_compare-sse4.ll (added) +++ llvm/trunk/test/CodeGen/X86/vec_compare-sse4.ll Wed Sep 28 16:00:25 2011 @@ -0,0 +1,35 @@ +; RUN: llc < %s -march=x86 -mattr=-sse3,+sse2 | FileCheck %s -check-prefix=SSE2 +; RUN: llc < %s -march=x86 -mattr=-sse42,+sse41 | FileCheck %s -check-prefix=SSE41 +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -check-prefix=SSE42 + +define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind { +; SSE42: test1: +; SSE42: pcmpgtq +; SSE42: ret +; SSE41: test1: +; SSE41-NOT: pcmpgtq +; SSE41: ret +; SSE2: test1: +; SSE2-NOT: pcmpgtq +; SSE2: ret + + %C = icmp sgt <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} + +define <2 x i64> @test2(<2 x i64> %A, <2 x i64> %B) nounwind { +; SSE42: test2: +; SSE42: pcmpeqq +; SSE42: ret +; SSE41: test2: +; SSE41: pcmpeqq +; SSE41: ret +; SSE2: test2: +; SSE2-NOT: pcmpeqq +; SSE2: ret + + %C = icmp eq <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} From bigcheesegs at gmail.com Wed Sep 28 16:24:44 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 28 Sep 2011 21:24:44 -0000 Subject: [llvm-commits] [llvm] r140726 - /llvm/trunk/tools/llvm-size/llvm-size.cpp Message-ID: <20110928212444.5875C2A6C12C@llvm.org> Author: mspencer Date: Wed Sep 28 16:24:44 2011 New Revision: 140726 URL: http://llvm.org/viewvc/llvm-project?rev=140726&view=rev Log: Fix cast. Modified: llvm/trunk/tools/llvm-size/llvm-size.cpp Modified: llvm/trunk/tools/llvm-size/llvm-size.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-size/llvm-size.cpp?rev=140726&r1=140725&r2=140726&view=diff ============================================================================== --- llvm/trunk/tools/llvm-size/llvm-size.cpp (original) +++ llvm/trunk/tools/llvm-size/llvm-size.cpp Wed Sep 28 16:24:44 2011 @@ -80,7 +80,7 @@ static int getNumLengthAsString(uint64_t num) { APInt conv(64, num); SmallString<32> result; - conv.toString(result, unsigned int(Radix), false, true); + conv.toString(result, static_cast(Radix), false, true); return result.size(); } From dblaikie at gmail.com Wed Sep 28 16:17:38 2011 From: dblaikie at gmail.com (David Blaikie) Date: Wed, 28 Sep 2011 14:17:38 -0700 Subject: [llvm-commits] [llvm] r140722 - in /llvm/trunk/tools: CMakeLists.txt Makefile llvm-size/ llvm-size/CMakeLists.txt llvm-size/Makefile llvm-size/llvm-size.cpp In-Reply-To: <20110928205747.028122A6C12C@llvm.org> References: <20110928205747.028122A6C12C@llvm.org> Message-ID: > > + conv.toString(result, unsigned int(Radix), false, true); > Is it just me, or is that causing a build break when building with ToT clang (admittedly my clang's not quite ToT, a few days old at best): llvm/tools/llvm-size/llvm-size.cpp:83:34: error: expected '(' for function-style cast or type construction conv.toString(result, unsigned int(Radix), false, true); ~~~~~~~~ ^ -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110928/84110768/attachment.html From clattner at apple.com Wed Sep 28 16:45:06 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 28 Sep 2011 14:45:06 -0700 Subject: [llvm-commits] [llvm] r140722 - in /llvm/trunk/tools: CMakeLists.txt Makefile llvm-size/ llvm-size/CMakeLists.txt llvm-size/Makefile llvm-size/llvm-size.cpp In-Reply-To: <20110928205747.028122A6C12C@llvm.org> References: <20110928205747.028122A6C12C@llvm.org> Message-ID: On Sep 28, 2011, at 1:57 PM, Michael J. Spencer wrote: > Author: mspencer > Date: Wed Sep 28 15:57:46 2011 > New Revision: 140722 > > URL: http://llvm.org/viewvc/llvm-project?rev=140722&view=rev > Log: > Add llvm-size. Cool. > +namespace { > + enum OutputFormatTy {berkeley, sysv}; > + cl::opt > + OutputFormat("format", Per the coding standards, please use 'static' instead of an anon namespace for data. > + if (OutputFormat == sysv) { > + // Run two passes over all sections. The first gets the lengths needed for > + // formatting the output. The second actually does the output. > + std::size_t max_name_len = strlen("section"); > + int max_size_len = strlen("size"); > + int max_addr_len = strlen("addr"); These (and the return value of getNumLengthAsString) should be unsigned. > // Setup per section format. > + fmt << "%-" << max_name_len << "s " > + << "%#" << max_size_len << radix_fmt << " " > + << "%#" << max_addr_len << radix_fmt << "\n"; This might be nicer with formatted_raw_ostream and the 'indent' method instead of building a format string. > +static void PrintFileSectionSizes(StringRef file) { > + // If file is not stdin, check that it exists. > + if (file != "-") { > + bool exists; > + if (sys::fs::exists(file, exists) || !exists) { > + errs() << ToolName << ": '" << file << "': " << "No such file\n"; > + return; > + } > + } > + > + OwningPtr binary; > + if (error_code ec = createBinary(file, binary)) { > + errs() << ToolName << ": " << file << ": " << ec.message() << ".\n"; > + return; > + } Please add doxygen comments to the functions, and comments to the code in general. > ++ > + ToolName = argv[0]; > + if (OutputFormatShort.getNumOccurrences()) > + OutputFormat = OutputFormatShort; > + if (RadixShort.getNumOccurrences()) > + Radix = int(RadixShort); 'Radix' should be a unsigned. -Chris From echristo at apple.com Wed Sep 28 16:45:02 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 28 Sep 2011 14:45:02 -0700 Subject: [llvm-commits] [llvm] r140722 - in /llvm/trunk/tools: CMakeLists.txt Makefile llvm-size/ llvm-size/CMakeLists.txt llvm-size/Makefile llvm-size/llvm-size.cpp In-Reply-To: References: <20110928205747.028122A6C12C@llvm.org> Message-ID: On Sep 28, 2011, at 2:17 PM, David Blaikie wrote: > + conv.toString(result, unsigned int(Radix), false, true); > > Is it just me, or is that causing a build break when building with ToT clang (admittedly my clang's not quite ToT, a few days old at best): > > llvm/tools/llvm-size/llvm-size.cpp:83:34: error: expected '(' for function-style cast or type construction > conv.toString(result, unsigned int(Radix), false, true); > ~~~~~~~~ ^ Already fixed. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110928/7968c5c4/attachment.html From isanbard at gmail.com Wed Sep 28 16:56:58 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 28 Sep 2011 21:56:58 -0000 Subject: [llvm-commits] [llvm] r140730 - /llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Message-ID: <20110928215659.4642E2A6C12E@llvm.org> Author: void Date: Wed Sep 28 16:56:53 2011 New Revision: 140730 URL: http://llvm.org/viewvc/llvm-project?rev=140730&view=rev Log: Have the SjLjEHPrepare pass do some more heavy lifting. Upon further review, most of the EH code should remain written at the IR level. The part which breaks SSA form is the dispatch table, so that part will be moved to the back-end. Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=140730&r1=140729&r2=140730&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Wed Sep 28 16:56:53 2011 @@ -58,6 +58,7 @@ Constant *ExceptionFn; Constant *CallSiteFn; Constant *DispatchSetupFn; + Constant *FuncCtxFn; Value *CallSite; DenseMap LPadSuccMap; public: @@ -74,7 +75,8 @@ private: bool setupEntryBlockAndCallSites(Function &F); - void setupFunctionContext(Function &F, ArrayRef LPads); + std::pair + setupFunctionContext(Function &F, ArrayRef LPads); void insertCallSiteStore(Instruction *I, int Number, Value *CallSite); void markInvokeCallSite(InvokeInst *II, int InvokeNo, Value *CallSite, @@ -125,6 +127,7 @@ CallSiteFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_callsite); DispatchSetupFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_dispatch_setup); + FuncCtxFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_functioncontext); PersonalityFn = 0; return true; @@ -709,8 +712,8 @@ /// setupFunctionContext - Allocate the function context on the stack and fill /// it with all of the data that we know at this point. -void SjLjEHPass::setupFunctionContext(Function &F, - ArrayRef LPads) { +std::pair SjLjEHPass:: +setupFunctionContext(Function &F, ArrayRef LPads) { BasicBlock *EntryBB = F.begin(); // Create an alloca for the incoming jump buffer ptr and the new jump buffer @@ -721,15 +724,6 @@ AllocaInst *FuncCtx = new AllocaInst(FunctionContextTy, 0, Align, "fn_context", EntryBB->begin()); - // Store a pointer to the function context so that the back-end will know - // where to look for it. - CallInst::Create(Intrinsic::getDeclaration(F.getParent(), - Intrinsic::eh_sjlj_functioncontext), - CastInst::Create(Instruction::BitCast, FuncCtx, - Type::getInt8PtrTy(F.getContext()), "", - EntryBB->getTerminator()), - "", EntryBB->getTerminator()); - // Fill in the function context structure. Value *Idxs[2]; Type *Int32Ty = Type::getInt32Ty(F.getContext()); @@ -811,33 +805,14 @@ EntryBB->getTerminator()); new StoreInst(Val, FramePtr, true, EntryBB->getTerminator()); - // Save the stack pointer. - Idxs[1] = ConstantInt::get(Int32Ty, 2); - Value *StackPtr = - GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_sp_gep", - EntryBB->getTerminator()); - - Val = CallInst::Create(StackAddrFn, "sp", EntryBB->getTerminator()); - new StoreInst(Val, StackPtr, true, EntryBB->getTerminator()); - - // Call the setjmp instrinsic. It fills in the rest of the jmpbuf. - Value *SetjmpArg = - CastInst::Create(Instruction::BitCast, JBufPtr, - Type::getInt8PtrTy(F.getContext()), "", - EntryBB->getTerminator()); - Value *DispatchVal = CallInst::Create(BuiltinSetjmpFn, SetjmpArg, - "dispatch", - EntryBB->getTerminator()); - - // Add a call to dispatch_setup after the setjmp call. This is expanded to any - // target-specific setup that needs to be done. - CallInst::Create(DispatchSetupFn, DispatchVal, "", EntryBB->getTerminator()); + return std::make_pair(FuncCtx, JBufPtr); } /// setupEntryBlockAndCallSites - Setup the entry block by creating and filling /// the function context and marking the call sites with the appropriate /// values. These values are used by the DWARF EH emitter. bool SjLjEHPass::setupEntryBlockAndCallSites(Function &F) { + SmallVector Returns; SmallVector Invokes; SmallVector LPads; @@ -846,11 +821,47 @@ if (InvokeInst *II = dyn_cast(BB->getTerminator())) { Invokes.push_back(II); LPads.push_back(II->getUnwindDest()->getLandingPadInst()); + } else if (ReturnInst *RI = dyn_cast(BB->getTerminator())) { + Returns.push_back(RI); } if (Invokes.empty()) return false; - setupFunctionContext(F, LPads); + std::pair FuncCtx = setupFunctionContext(F, LPads); + BasicBlock *EntryBB = F.begin(); + + // Save the stack pointer. + Type *Int32Ty = Type::getInt32Ty(F.getContext()); + Value *Idxs[2] = { + ConstantInt::get(Int32Ty, 0), ConstantInt::get(Int32Ty, 2) + }; + Value *StackPtr = + GetElementPtrInst::Create(FuncCtx.second, Idxs, "jbuf_sp_gep", + EntryBB->getTerminator()); + + Value *Val = CallInst::Create(StackAddrFn, "sp", EntryBB->getTerminator()); + new StoreInst(Val, StackPtr, true, EntryBB->getTerminator()); + + // Call the setjmp instrinsic. It fills in the rest of the jmpbuf. + Value *SetjmpArg = + CastInst::Create(Instruction::BitCast, FuncCtx.second, + Type::getInt8PtrTy(F.getContext()), "", + EntryBB->getTerminator()); + Value *DispatchVal = CallInst::Create(BuiltinSetjmpFn, SetjmpArg, + "dispatch", + EntryBB->getTerminator()); + + // Add a call to dispatch_setup after the setjmp call. This is expanded to any + // target-specific setup that needs to be done. + CallInst::Create(DispatchSetupFn, DispatchVal, "", EntryBB->getTerminator()); + + // Store a pointer to the function context so that the back-end will know + // where to look for it. + Value *FuncCtxArg = + CastInst::Create(Instruction::BitCast, FuncCtx.first, + Type::getInt8PtrTy(F.getContext()), "", + EntryBB->getTerminator()); + CallInst::Create(FuncCtxFn, FuncCtxArg, "", EntryBB->getTerminator()); // At this point, we are all set up, update the invoke instructions to mark // their call_site values, and fill in the dispatch switch accordingly. @@ -880,6 +891,16 @@ } } + // Register the function context and make sure it's known to not throw + CallInst *Register = CallInst::Create(RegisterFn, FuncCtx.first, "", + EntryBB->getTerminator()); + Register->setDoesNotThrow(); + + // Finally, for any returns from this function, if this function contains an + // invoke, add a call to unregister the function context. + for (unsigned I = 0, E = Returns.size(); I != E; ++I) + CallInst::Create(UnregisterFn, FuncCtx.first, "", Returns[I]); + return true; } From ahatanaka at mips.com Wed Sep 28 16:58:03 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Wed, 28 Sep 2011 21:58:03 -0000 Subject: [llvm-commits] [llvm] r140731 - in /llvm/trunk/lib/Target/Mips: MipsInstrFPU.td MipsInstrInfo.cpp Message-ID: <20110928215803.D4A282A6C12E@llvm.org> Author: ahatanak Date: Wed Sep 28 16:58:01 2011 New Revision: 140731 URL: http://llvm.org/viewvc/llvm-project?rev=140731&view=rev Log: Define classes for unary and binary FP instructions and use them to define multiclasses. Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=140731&r1=140730&r2=140731&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Wed Sep 28 16:58:01 2011 @@ -64,54 +64,62 @@ // // A set of multiclasses is used to address the register usage. // -// S32 - single precision in 16 32bit even fp registers +// S - single precision in 16 32bit even fp registers // single precision in 32 32bit fp registers in SingleOnly mode -// S64 - single precision in 32 64bit fp registers (In64BitMode) // D32 - double precision in 16 32bit even fp registers // D64 - double precision in 32 64bit fp registers (In64BitMode) // -// Only S32 and D32 are supported right now. +// Only S and D32 are supported right now. //===----------------------------------------------------------------------===// +// Unary instruction without pattern. +class FFR1 funct, bits<5> fmt, RegisterClass RCDst, + RegisterClass RCSrc, string asmstr>: + FFR<0x11, funct, fmt, (outs RCDst:$fd), (ins RCSrc:$fs), + !strconcat(asmstr, "\t$fd, $fs"), []> { + let ft = 0; +} + +// Unary instruction with pattern. +// All operands belong to the same register class. +class FFR1P funct, bits<5> fmt, RegisterClass RC, string asmstr, + SDNode FOp>: + FFR1 { + let Pattern = [(set RC:$fd, (FOp RC:$fs))]; +} + +// Binary instruction with pattern. +// All operands belong to the same register class. +class FFR2 funct, bits<5> fmt, RegisterClass RC, string asmstr, + SDNode FOp, bit isComm = 0>: + FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft), + !strconcat(asmstr, "\t$fd, $fs, $ft"), + [(set RC:$fd, (FOp RC:$fs, RC:$ft))]> { + let isCommutable = isComm; +} + +// Multiclasses. +// Unary instruction without pattern. multiclass FFR1_1 funct, string asmstr> { - def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs), - !strconcat(asmstr, ".s\t$fd, $fs"), []>; - - def _D32 : FFR<0x11, funct, 0x1, (outs FGR32:$fd), (ins AFGR64:$fs), - !strconcat(asmstr, ".d\t$fd, $fs"), []>, Requires<[NotFP64bit]>; + def _S : FFR1; + def _D32 : FFR1, Requires<[NotFP64bit]>; } +// Unary instruction with pattern. +// All operands belong to the same register class. multiclass FFR1_2 funct, string asmstr, SDNode FOp> { - def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs), - !strconcat(asmstr, ".s\t$fd, $fs"), - [(set FGR32:$fd, (FOp FGR32:$fs))]>; - - def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs), - !strconcat(asmstr, ".d\t$fd, $fs"), - [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[NotFP64bit]>; + def _S : FFR1P; + def _D32 : FFR1P, Requires<[NotFP64bit]>; } -class FFR1_3 funct, bits<5> fmt, RegisterClass RcSrc, - RegisterClass RcDst, string asmstr>: - FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs), - !strconcat(asmstr, "\t$fd, $fs"), []>; - - +// Binary instruction with pattern. +// All operands belong to the same register class. multiclass FFR1_4 funct, string asmstr, SDNode FOp, bit isComm = 0> { - let isCommutable = isComm in { - def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), - (ins FGR32:$fs, FGR32:$ft), - !strconcat(asmstr, ".s\t$fd, $fs, $ft"), - [(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>; - - def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), - (ins AFGR64:$fs, AFGR64:$ft), - !strconcat(asmstr, ".d\t$fd, $fs, $ft"), - [(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>, - Requires<[NotFP64bit]>; - } + def _S : FFR2; + def _D32 : FFR2, + Requires<[NotFP64bit]>; } //===----------------------------------------------------------------------===// @@ -130,37 +138,37 @@ defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>; /// Convert to Single Precison - def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">; + def CVTS_W32 : FFR1<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">; let Predicates = [IsNotSingleFloat] in { /// Ceil to long signed integer - def CEIL_LS : FFR1_3<0b001010, 0x0, FGR32, FGR32, "ceil.l">; - def CEIL_LD : FFR1_3<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">; + def CEIL_LS : FFR1<0b001010, 0x0, FGR32, FGR32, "ceil.l">; + def CEIL_LD : FFR1<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">; /// Round to long signed integer - def ROUND_LS : FFR1_3<0b001000, 0x0, FGR32, FGR32, "round.l">; - def ROUND_LD : FFR1_3<0b001000, 0x1, AFGR64, AFGR64, "round.l">; + def ROUND_LS : FFR1<0b001000, 0x0, FGR32, FGR32, "round.l">; + def ROUND_LD : FFR1<0b001000, 0x1, AFGR64, AFGR64, "round.l">; /// Floor to long signed integer - def FLOOR_LS : FFR1_3<0b001011, 0x0, FGR32, FGR32, "floor.l">; - def FLOOR_LD : FFR1_3<0b001011, 0x1, AFGR64, AFGR64, "floor.l">; + def FLOOR_LS : FFR1<0b001011, 0x0, FGR32, FGR32, "floor.l">; + def FLOOR_LD : FFR1<0b001011, 0x1, AFGR64, AFGR64, "floor.l">; /// Trunc to long signed integer - def TRUNC_LS : FFR1_3<0b001001, 0x0, FGR32, FGR32, "trunc.l">; - def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">; + def TRUNC_LS : FFR1<0b001001, 0x0, FGR32, FGR32, "trunc.l">; + def TRUNC_LD : FFR1<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">; /// Convert to long signed integer - def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">; - def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">; + def CVTL_S : FFR1<0b100101, 0x0, FGR32, FGR32, "cvt.l">; + def CVTL_D : FFR1<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">; /// Convert to Double Precison - def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">; - def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">; - def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">; + def CVTD_S : FFR1<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">; + def CVTD_W32 : FFR1<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">; + def CVTD_L32 : FFR1<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">; /// Convert to Single Precison - def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">; - def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">; + def CVTS_D32 : FFR1<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">; + def CVTS_L32 : FFR1<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">; } } @@ -185,7 +193,7 @@ [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>; } -def FMOV_S32 : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs), +def FMOV_S : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs), "mov.s\t$fd, $fs", []>; def FMOV_D32 : FFR<0x11, 0b000110, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs), "mov.d\t$fd, $fs", []>; @@ -252,7 +260,7 @@ /// Floating Point Compare let Defs=[FCR31] in { - def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc), + def FCMP_S : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc), "c.$cc.s\t$fs, $ft", [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>; @@ -350,16 +358,16 @@ }]>; def : Pat<(f32 fpimm0), (MTC1 ZERO)>; -def : Pat<(f32 fpimm0neg), (FNEG_S32 (MTC1 ZERO))>; +def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>; def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>; -def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>; +def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>; def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>; let Predicates = [NotFP64bit] in { def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>; - def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>; + def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S FGR32:$src)>; } Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=140731&r1=140730&r2=140731&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Wed Sep 28 16:58:01 2011 @@ -141,7 +141,7 @@ } if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) { - BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg) + BuildMI(MBB, I, DL, get(Mips::FMOV_S), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)); return; } From aaron at aaronballman.com Wed Sep 28 17:47:20 2011 From: aaron at aaronballman.com (Aaron Ballman) Date: Wed, 28 Sep 2011 17:47:20 -0500 Subject: [llvm-commits] [PATCH] Removed FIXME from Memory.inc on Windows In-Reply-To: References: Message-ID: Ping? ~Aaron On Mon, Sep 19, 2011 at 5:30 PM, Aaron Ballman wrote: > On Mon, Sep 19, 2011 at 4:31 AM, Anton Korobeynikov > wrote: >> Hi Aaron, >> >>> This patch addresses a FIXME in the Memory class on Windows. ?It now >>> supports allocating blocks of memory around the "NearBlock" parameter. >>> ?Additionally, it adds support for changing the protection for blocks >>> of virtual memory. >> Stuff looks generally ok for me, but I'd ask Takumi as well. >> Also, please split the patch into 2 parts, it definitely contains 2 >> unrelated blocks >> >> Thanks for working on this! > > My pleasure! ?I've split the changes into two separate diffs, and > attached them both. > > VProt.diff is the patch for supporting setting memory to be writable > or executable. > > NearBlock.diff is the patch which removes the FIXME for NearBlock support. > > Thanks! > > ~Aaron > From aaron at aaronballman.com Wed Sep 28 17:47:50 2011 From: aaron at aaronballman.com (Aaron Ballman) Date: Wed, 28 Sep 2011 17:47:50 -0500 Subject: [llvm-commits] [PATCH] Win64 Support for Crash Stack Crawls In-Reply-To: References: Message-ID: Ping? ~Aaron On Wed, Sep 21, 2011 at 6:06 PM, Aaron Ballman wrote: > This patch fixes a FIXME in Signals.inc for Win64. ?Now, it contains > support for 32- and 64-bit versions of the library. ?The StackWalk64 > API (and friends) were introduced in DebugHlp 5.1, which shipped with > Windows XP. ?However, I don't have an XP install handy to test > against, so I've not verified on the LCD platform. ?However, I have > tested it on Win7 64-bit with 32-bit and 64-bit versions of the > library. > > The majority of this patch involved working around MinGW. ?:-( ?It > doesn't have support for any of the 64-bit APIs or structures, so I > had to dynamically load them. ?All structures and function signatures > were pulled from the platform SDK. ?So this has been tested with VC++ > and MinGW both. > > ~Aaron > From evan.cheng at apple.com Wed Sep 28 18:16:34 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 28 Sep 2011 23:16:34 -0000 Subject: [llvm-commits] [llvm] r140733 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll Message-ID: <20110928231634.E16F72A6C12C@llvm.org> Author: evancheng Date: Wed Sep 28 18:16:31 2011 New Revision: 140733 URL: http://llvm.org/viewvc/llvm-project?rev=140733&view=rev Log: Tighten a ARM dag combine condition to avoid an identity transformation, which ends up introducing a cycle in the DAG. rdar://10196296 Added: llvm/trunk/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=140733&r1=140732&r2=140733&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Sep 28 18:16:31 2011 @@ -7344,7 +7344,7 @@ // movne r0, y /// FIXME: Turn this into a target neutral optimization? SDValue Res; - if (CC == ARMCC::NE && FalseVal == RHS) { + if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) { Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, N->getOperand(3), Cmp); } else if (CC == ARMCC::EQ && TrueVal == RHS) { Added: llvm/trunk/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll?rev=140733&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll Wed Sep 28 18:16:31 2011 @@ -0,0 +1,30 @@ +; RUN: llc -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 < %s + +; rdar://10196296 +; ARM target specific dag combine created a cycle in DAG. + +define void @t() nounwind ssp { + %1 = load i64* undef, align 4 + %2 = shl i32 5, 0 + %3 = zext i32 %2 to i64 + %4 = and i64 %1, %3 + %5 = lshr i64 %4, undef + switch i64 %5, label %8 [ + i64 0, label %9 + i64 1, label %6 + i64 4, label %9 + i64 5, label %7 + ] + +;