From nicholas at mxc.ca Mon Oct 3 00:15:00 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 03 Oct 2011 05:15:00 -0000
Subject: [llvm-commits] [llvm] r140980 - in /llvm/trunk:
lib/Analysis/ScalarEvolution.cpp
test/Analysis/ScalarEvolution/max-trip-count.ll
Message-ID: <20111003051500.B8CE62A6C12C@llvm.org>
Author: nicholas
Date: Mon Oct 3 00:14:59 2011
New Revision: 140980
URL: http://llvm.org/viewvc/llvm-project?rev=140980&view=rev
Log:
Revert r140979 due to reports of bootstrap failure.
Modified:
llvm/trunk/lib/Analysis/ScalarEvolution.cpp
llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll
Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=140980&r1=140979&r2=140980&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Oct 3 00:14:59 2011
@@ -5119,7 +5119,7 @@
// Compute the two solutions for the quadratic formula.
// The divisions must be performed as signed divisions.
APInt NegB(-B);
- APInt TwoA(A << 1);
+ APInt TwoA( A << 1 );
if (TwoA.isMinValue()) {
const SCEV *CNC = SE.getCouldNotCompute();
return std::make_pair(CNC, CNC);
@@ -5134,7 +5134,7 @@
return std::make_pair(SE.getConstant(Solution1),
SE.getConstant(Solution2));
- } // end APIntOps namespace
+ } // end APIntOps namespace
}
/// HowFarToZero - Return the number of times a backedge comparing the specified
@@ -5228,12 +5228,8 @@
// Handle unitary steps, which cannot wraparound.
// 1*N = -Start; -1*N = Start (mod 2^BW), so:
// N = Distance (as unsigned)
- if (StepC->getValue()->equalsInt(1) || StepC->getValue()->isAllOnesValue()) {
- ConstantRange CR = getUnsignedRange(Start);
- const SCEV *MaxBECount = getConstant(CountDown ? CR.getUnsignedMax()
- : ~CR.getUnsignedMin());
- return ExitLimit(Distance, MaxBECount);
- }
+ if (StepC->getValue()->equalsInt(1) || StepC->getValue()->isAllOnesValue())
+ return Distance;
// If the recurrence is known not to wraparound, unsigned divide computes the
// back edge count. We know that the value will either become zero (and thus
Modified: llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll?rev=140980&r1=140979&r2=140980&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll Mon Oct 3 00:14:59 2011
@@ -70,31 +70,3 @@
}
declare i32 @printf(i8*, ...)
-
-define void @test(i8* %a, i32 %n) nounwind {
-entry:
- %cmp1 = icmp sgt i32 %n, 0
- br i1 %cmp1, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph: ; preds = %entry
- %tmp = zext i32 %n to i64
- br label %for.body
-
-for.body: ; preds = %for.body, %for.body.lr.ph
- %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %for.body.lr.ph ]
- %arrayidx = getelementptr i8* %a, i64 %indvar
- store i8 0, i8* %arrayidx, align 1
- %indvar.next = add i64 %indvar, 1
- %exitcond = icmp ne i64 %indvar.next, %tmp
- br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
-
-for.cond.for.end_crit_edge: ; preds = %for.body
- br label %for.end
-
-for.end: ; preds = %for.cond.for.end_crit_edge, %entry
- ret void
-}
-
-; CHECK: Determining loop execution counts for: @test
-; CHECK-NEXT: backedge-taken count is
-; CHECK-NEXT: max backedge-taken count is -1
From edwintorok at gmail.com Mon Oct 3 01:41:46 2011
From: edwintorok at gmail.com (Torok Edwin)
Date: Mon, 03 Oct 2011 06:41:46 -0000
Subject: [llvm-commits] [llvm] r140991 - in /llvm/trunk:
bindings/ocaml/llvm/llvm.ml bindings/ocaml/llvm/llvm.mli
bindings/ocaml/llvm/llvm_ocaml.c test/Bindings/Ocaml/vmcore.ml
Message-ID: <20111003064149.69FAC2A6C12C@llvm.org>
Author: edwin
Date: Mon Oct 3 01:41:46 2011
New Revision: 140991
URL: http://llvm.org/viewvc/llvm-project?rev=140991&view=rev
Log:
attempt to fix ocaml bindings: landing pads
Modified:
llvm/trunk/bindings/ocaml/llvm/llvm.ml
llvm/trunk/bindings/ocaml/llvm/llvm.mli
llvm/trunk/bindings/ocaml/llvm/llvm_ocaml.c
llvm/trunk/test/Bindings/Ocaml/vmcore.ml
Modified: llvm/trunk/bindings/ocaml/llvm/llvm.ml
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/llvm/llvm.ml?rev=140991&r1=140990&r2=140991&view=diff
==============================================================================
--- llvm/trunk/bindings/ocaml/llvm/llvm.ml (original)
+++ llvm/trunk/bindings/ocaml/llvm/llvm.ml Mon Oct 3 01:41:46 2011
@@ -820,6 +820,9 @@
external build_invoke : llvalue -> llvalue array -> llbasicblock ->
llbasicblock -> string -> llbuilder -> llvalue
= "llvm_build_invoke_bc" "llvm_build_invoke_nat"
+external build_landingpad : lltype -> llvalue -> int -> string -> llbuilder ->
+ llvalue = "llvm_build_landingpad"
+external set_cleanup : llvalue -> bool -> unit = "llvm_set_cleanup"
external build_unreachable : llbuilder -> llvalue = "llvm_build_unreachable"
(*--... Arithmetic .........................................................--*)
Modified: llvm/trunk/bindings/ocaml/llvm/llvm.mli
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/llvm/llvm.mli?rev=140991&r1=140990&r2=140991&view=diff
==============================================================================
--- llvm/trunk/bindings/ocaml/llvm/llvm.mli (original)
+++ llvm/trunk/bindings/ocaml/llvm/llvm.mli Mon Oct 3 01:41:46 2011
@@ -339,7 +339,7 @@
See the method [llvm::FunctionType::get]. *)
val function_type : lltype -> lltype array -> lltype
-(** [va_arg_function_type ret_ty param_tys] is just like
+(** [var_arg_function_type ret_ty param_tys] is just like
[function_type ret_ty param_tys] except that it returns the function type
which also takes a variable number of arguments.
See the method [llvm::FunctionType::get]. *)
@@ -1615,6 +1615,16 @@
val build_invoke : llvalue -> llvalue array -> llbasicblock ->
llbasicblock -> string -> llbuilder -> llvalue
+(** [build_landingpad ty persfn numclauses name b] creates an
+ [landingpad]
+ instruction at the position specified by the instruction builder [b].
+ See the method [llvm::LLVMBuilder::CreateLandingPad]. *)
+val build_landingpad : lltype -> llvalue -> int -> string -> llbuilder ->
+ llvalue
+
+(** [set_cleanup lp] sets the cleanup flag in the [landingpad]instruction.
+ See the method [llvm::LandingPadInst::setCleanup]. *)
+val set_cleanup : llvalue -> bool -> unit
(** [build_unreachable b] creates an
[unreachable]
Modified: llvm/trunk/bindings/ocaml/llvm/llvm_ocaml.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/llvm/llvm_ocaml.c?rev=140991&r1=140990&r2=140991&view=diff
==============================================================================
--- llvm/trunk/bindings/ocaml/llvm/llvm_ocaml.c (original)
+++ llvm/trunk/bindings/ocaml/llvm/llvm_ocaml.c Mon Oct 3 01:41:46 2011
@@ -1212,6 +1212,19 @@
Args[4], Args[5]);
}
+CAMLprim LLVMValueRef llvm_build_landingpad(LLVMTypeRef Ty, LLVMValueRef PersFn,
+ value NumClauses, value Name,
+ value B) {
+ return LLVMBuildLandingPad(Builder_val(B), Ty, PersFn, Int_val(NumClauses),
+ String_val(Name));
+}
+
+CAMLprim value llvm_set_cleanup(LLVMValueRef LandingPadInst, value flag)
+{
+ LLVMSetCleanup(LandingPadInst, Bool_val(flag));
+ return Val_unit;
+}
+
/* llbuilder -> llvalue */
CAMLprim LLVMValueRef llvm_build_unreachable(value B) {
return LLVMBuildUnreachable(Builder_val(B));
Modified: llvm/trunk/test/Bindings/Ocaml/vmcore.ml
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bindings/Ocaml/vmcore.ml?rev=140991&r1=140990&r2=140991&view=diff
==============================================================================
--- llvm/trunk/test/Bindings/Ocaml/vmcore.ml (original)
+++ llvm/trunk/test/Bindings/Ocaml/vmcore.ml Mon Oct 3 01:41:46 2011
@@ -834,7 +834,17 @@
let bb00 = append_block context "Bb00" fn in
ignore (build_unreachable (builder_at_end context bb00));
-
+
+ let bblpad = append_block context "Bblpad" fn in
+ let rt = struct_type context [| pointer_type i8_type; i32_type |] in
+ let ft = var_arg_function_type i32_type [||] in
+ let personality = declare_function "__gxx_personality_v0" ft m in begin
+ let lp = build_landingpad rt personality 0 "lpad"
+ (builder_at_end context bblpad) in
+ set_cleanup lp true;
+ ignore (build_unreachable (builder_at_end context bblpad));
+ end;
+
group "ret"; begin
(* RUN: grep {ret.*P1} < %t.ll
*)
@@ -891,11 +901,11 @@
group "invoke"; begin
(* RUN: grep {build_invoke.*invoke.*P1.*P2} < %t.ll
- * RUN: grep {to.*Bb04.*unwind.*Bb00} < %t.ll
+ * RUN: grep {to.*Bb04.*unwind.*Bblpad} < %t.ll
*)
let bb04 = append_block context "Bb04" fn in
let b = builder_at_end context bb04 in
- ignore (build_invoke fn [| p1; p2 |] bb04 bb00 "build_invoke" b)
+ ignore (build_invoke fn [| p1; p2 |] bb04 bblpad "build_invoke" b)
end;
group "unreachable"; begin
From edwintorok at gmail.com Mon Oct 3 01:45:07 2011
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Mon, 03 Oct 2011 09:45:07 +0300
Subject: [llvm-commits] fixing the OCaml bindings for 3.0
In-Reply-To: <553D8D40-6AD8-4794-B645-FE89535F4E74@apple.com>
References: <4E870429.4000006@gmail.com> <4E888C95.7090108@gmail.com>
<553D8D40-6AD8-4794-B645-FE89535F4E74@apple.com>
Message-ID: <4E8959F3.2070509@gmail.com>
On 10/03/2011 01:28 AM, Cameron Zwarich wrote:
> On Oct 2, 2011, at 9:08 AM, T?r?k Edwin wrote:
>
>> On 10/01/2011 03:14 PM, T?r?k Edwin wrote:
>>> Hi,
>>>
>>> I noticed that currently the OCaml bindings don't pass the testsuite.
>>> First problem is due to exception handling changes: invoke must point to a basic block with a landingpad,
>>> otherwise verifier rejects it.
>>>
>>> Attach patch tries to address that by exposing LLVMBuildLandingPad, and calling it: the verifier passes now.
>>> There are still many grep failures left though, I'll probably go through these in the next days and try to figure what is wrong.
>>>
>>> Some help would be appreciated, there are currently 158 grep failures (even after applying this patch), see log.gz.
>>
>> Looks like I misinterpreted the output from lit: it shows all greps regardless if they failed or not.
>> There was really only one failure, attached patch makes all Bindings/Ocaml tests pass!
>>
>> OK to commit?
>
> I don't have experience with the Ocaml bindings, but it looks good to me.
>
Thanks, committed.
--Edwin
From nicholas at mxc.ca Mon Oct 3 02:10:46 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 03 Oct 2011 07:10:46 -0000
Subject: [llvm-commits] [llvm] r140992 - in /llvm/trunk:
lib/Analysis/ScalarEvolution.cpp
test/Analysis/ScalarEvolution/max-trip-count.ll
Message-ID: <20111003071046.6E0E02A6C12C@llvm.org>
Author: nicholas
Date: Mon Oct 3 02:10:45 2011
New Revision: 140992
URL: http://llvm.org/viewvc/llvm-project?rev=140992&view=rev
Log:
Reapply r140979 with fix! We never did get a testcase, but careful review of the
logic by David Meyer revealed this bug.
Modified:
llvm/trunk/lib/Analysis/ScalarEvolution.cpp
llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll
Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=140992&r1=140991&r2=140992&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Oct 3 02:10:45 2011
@@ -5119,7 +5119,7 @@
// Compute the two solutions for the quadratic formula.
// The divisions must be performed as signed divisions.
APInt NegB(-B);
- APInt TwoA( A << 1 );
+ APInt TwoA(A << 1);
if (TwoA.isMinValue()) {
const SCEV *CNC = SE.getCouldNotCompute();
return std::make_pair(CNC, CNC);
@@ -5134,7 +5134,7 @@
return std::make_pair(SE.getConstant(Solution1),
SE.getConstant(Solution2));
- } // end APIntOps namespace
+ } // end APIntOps namespace
}
/// HowFarToZero - Return the number of times a backedge comparing the specified
@@ -5228,8 +5228,19 @@
// Handle unitary steps, which cannot wraparound.
// 1*N = -Start; -1*N = Start (mod 2^BW), so:
// N = Distance (as unsigned)
- if (StepC->getValue()->equalsInt(1) || StepC->getValue()->isAllOnesValue())
- return Distance;
+ if (StepC->getValue()->equalsInt(1) || StepC->getValue()->isAllOnesValue()) {
+ ConstantRange CR = getUnsignedRange(Start);
+ const SCEV *MaxBECount;
+ if (!CountDown && CR.getUnsignedMin().isMinValue())
+ // When counting up, the worst starting value is 1, not 0.
+ MaxBECount = CR.getUnsignedMax().isMinValue()
+ ? getConstant(APInt::getMinValue(CR.getBitWidth()))
+ : getConstant(APInt::getMaxValue(CR.getBitWidth()));
+ else
+ MaxBECount = getConstant(CountDown ? CR.getUnsignedMax()
+ : -CR.getUnsignedMin());
+ return ExitLimit(Distance, MaxBECount);
+ }
// If the recurrence is known not to wraparound, unsigned divide computes the
// back edge count. We know that the value will either become zero (and thus
Modified: llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll?rev=140992&r1=140991&r2=140992&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/max-trip-count.ll Mon Oct 3 02:10:45 2011
@@ -70,3 +70,31 @@
}
declare i32 @printf(i8*, ...)
+
+define void @test(i8* %a, i32 %n) nounwind {
+entry:
+ %cmp1 = icmp sgt i32 %n, 0
+ br i1 %cmp1, label %for.body.lr.ph, label %for.end
+
+for.body.lr.ph: ; preds = %entry
+ %tmp = zext i32 %n to i64
+ br label %for.body
+
+for.body: ; preds = %for.body, %for.body.lr.ph
+ %indvar = phi i64 [ %indvar.next, %for.body ], [ 0, %for.body.lr.ph ]
+ %arrayidx = getelementptr i8* %a, i64 %indvar
+ store i8 0, i8* %arrayidx, align 1
+ %indvar.next = add i64 %indvar, 1
+ %exitcond = icmp ne i64 %indvar.next, %tmp
+ br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
+
+for.cond.for.end_crit_edge: ; preds = %for.body
+ br label %for.end
+
+for.end: ; preds = %for.cond.for.end_crit_edge, %entry
+ ret void
+}
+
+; CHECK: Determining loop execution counts for: @test
+; CHECK-NEXT: backedge-taken count is
+; CHECK-NEXT: max backedge-taken count is -1
From craig.topper at gmail.com Mon Oct 3 02:51:10 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Mon, 03 Oct 2011 07:51:10 -0000
Subject: [llvm-commits] [llvm] r140993 -
/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
Message-ID: <20111003075115.2D8D8312800A@llvm.org>
Author: ctopper
Date: Mon Oct 3 02:51:09 2011
New Revision: 140993
URL: http://llvm.org/viewvc/llvm-project?rev=140993&view=rev
Log:
Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode.
Modified:
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c?rev=140993&r1=140992&r2=140993&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c Mon Oct 3 02:51:09 2011
@@ -406,12 +406,14 @@
consumeByte(insn, &insn->vexPrefix[2]);
/* We simulate the REX prefix for simplicity's sake */
-
- insn->rexPrefix = 0x40
- | (wFromVEX3of3(insn->vexPrefix[2]) << 3)
- | (rFromVEX2of3(insn->vexPrefix[1]) << 2)
- | (xFromVEX2of3(insn->vexPrefix[1]) << 1)
- | (bFromVEX2of3(insn->vexPrefix[1]) << 0);
+
+ if (insn->mode == MODE_64BIT) {
+ insn->rexPrefix = 0x40
+ | (wFromVEX3of3(insn->vexPrefix[2]) << 3)
+ | (rFromVEX2of3(insn->vexPrefix[1]) << 2)
+ | (xFromVEX2of3(insn->vexPrefix[1]) << 1)
+ | (bFromVEX2of3(insn->vexPrefix[1]) << 0);
+ }
switch (ppFromVEX3of3(insn->vexPrefix[2]))
{
@@ -444,8 +446,10 @@
insn->vexPrefix[0] = byte;
consumeByte(insn, &insn->vexPrefix[1]);
- insn->rexPrefix = 0x40
- | (rFromVEX2of2(insn->vexPrefix[1]) << 2);
+ if (insn->mode == MODE_64BIT) {
+ insn->rexPrefix = 0x40
+ | (rFromVEX2of2(insn->vexPrefix[1]) << 2);
+ }
switch (ppFromVEX2of2(insn->vexPrefix[1]))
{
@@ -763,7 +767,7 @@
break;
}
- if (wFromVEX3of3(insn->vexPrefix[2]))
+ if (insn->mode == MODE_64BIT && wFromVEX3of3(insn->vexPrefix[2]))
attrMask |= ATTR_REXW;
if (lFromVEX3of3(insn->vexPrefix[2]))
attrMask |= ATTR_VEXL;
From craig.topper at gmail.com Mon Oct 3 02:53:59 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Mon, 03 Oct 2011 07:53:59 -0000
Subject: [llvm-commits] [llvm] r140994 -
/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
Message-ID: <20111003075359.69AB0312800A@llvm.org>
Author: ctopper
Date: Mon Oct 3 02:53:59 2011
New Revision: 140994
URL: http://llvm.org/viewvc/llvm-project?rev=140994&view=rev
Log:
Test updates that were supposed to go with r140993.
Modified:
llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=140994&r1=140993&r2=140994&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Mon Oct 3 02:53:59 2011
@@ -102,13 +102,13 @@
# CHECK: movw $47416, -66(%ebp)
0x66 0xc7 0x45 0xbe 0x38 0xb9
-# CHECK: vaddpd %ymm13, %ymm1, %ymm0
+# CHECK: vaddpd %ymm5, %ymm1, %ymm0
0xc4 0xc1 0x75 0x58 0xc5
# CHECK: vaddps %ymm3, %ymm1, %ymm0
0xc5 0xf4 0x58 0xc3
-# CHECK: vandpd %ymm13, %ymm1, %ymm0
+# CHECK: vandpd %ymm5, %ymm1, %ymm0
0xc4 0xc1 0x75 0x54 0xc5
# CHECK: vandps %ymm3, %ymm1, %ymm0
@@ -129,8 +129,8 @@
# CHECK: vcvtsd2si %xmm0, %eax
0xc5 0xfb 0x2d 0xc0
-# CHECK: vcvtsd2si %xmm0, %rax
-0xc4 0xe1 0xfb 0x2d 0xc0
+# CHECK: vcvtsd2si %xmm0, %eax
+0xc4 0xe1 0x7b 0x2d 0xc0
# CHECK: vmaskmovpd %xmm0, %xmm1, (%eax)
0xc4 0xe2 0x71 0x2f 0x00
From craig.topper at gmail.com Mon Oct 3 03:14:31 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Mon, 03 Oct 2011 08:14:31 -0000
Subject: [llvm-commits] [llvm] r140997 - in /llvm/trunk:
lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
test/MC/Disassembler/X86/simple-tests.txt
test/MC/Disassembler/X86/x86-32.txt
Message-ID: <20111003081431.E9F8D312800A@llvm.org>
Author: ctopper
Date: Mon Oct 3 03:14:29 2011
New Revision: 140997
URL: http://llvm.org/viewvc/llvm-project?rev=140997&view=rev
Log:
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
Modified:
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c?rev=140997&r1=140996&r2=140997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c Mon Oct 3 03:14:29 2011
@@ -1491,6 +1491,9 @@
else
return -1;
+ if (insn->mode != MODE_64BIT)
+ insn->vvvv &= 0x7;
+
return 0;
}
Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=140997&r1=140996&r2=140997&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Mon Oct 3 03:14:29 2011
@@ -365,3 +365,6 @@
# CHECK: testq $0, %rax
0x48 0xa9 0x00 0x00 0x00 0x00
+
+# CHECK: vaddps %xmm3, %xmm15, %xmm0
+0xc4 0xe1 0x00 0x58 0xc3
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=140997&r1=140996&r2=140997&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Mon Oct 3 03:14:29 2011
@@ -384,3 +384,6 @@
# CHECK: movl %eax, 0
0xa3 0x00 0x00 0x00 0x00
+
+# CHECK: vaddps %xmm3, %xmm7, %xmm0
+0xc4 0xe1 0x00 0x58 0xc3
From edwintorok at gmail.com Mon Oct 3 08:38:59 2011
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Mon, 03 Oct 2011 16:38:59 +0300
Subject: [llvm-commits] Fix opcodes in C bindings
Message-ID: <4E89BAF3.2040905@gmail.com>
Hi,
LLVMOpcode is out of sync with getOpcode() right now (was ok in 2.9 AFAICT).
Attached patch introduces a function to map between Instruction::* opcodes and the opcodes declared in llvm-c/Core.h.
It does that by using the macros in Instruction.def, so that it will always be up-to-date as internal opcodes change.
When a new opcode is introduced you'll get a compile error in Core.cpp and will have to add it to llvm-c/Core.h
as well (at the end of the other opcodes). This way the C API opcodes can't get out-of-sync.
The 2nd patch adds an LLVMGetInstructionOpcode to the C API, to allow it to inspect, not just create instructions.
Best regards,
--Edwin
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From rafael.espindola at gmail.com Mon Oct 3 09:45:38 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Mon, 03 Oct 2011 14:45:38 -0000
Subject: [llvm-commits] [llvm] r141001 - in /llvm/trunk: docs/LangRef.html
include/llvm/Attributes.h lib/AsmParser/LLLexer.cpp
lib/AsmParser/LLParser.cpp lib/AsmParser/LLToken.h
lib/Target/CppBackend/CPPBackend.cpp lib/VMCore/Attributes.cpp
test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
test/Transforms/TailCallElim/setjmp.ll
Message-ID: <20111003144541.503492A6C12C@llvm.org>
Author: rafael
Date: Mon Oct 3 09:45:37 2011
New Revision: 141001
URL: http://llvm.org/viewvc/llvm-project?rev=141001&view=rev
Log:
Add the returns_twice attribute to LLVM.
Modified:
llvm/trunk/docs/LangRef.html
llvm/trunk/include/llvm/Attributes.h
llvm/trunk/lib/AsmParser/LLLexer.cpp
llvm/trunk/lib/AsmParser/LLParser.cpp
llvm/trunk/lib/AsmParser/LLToken.h
llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
llvm/trunk/lib/VMCore/Attributes.cpp
llvm/trunk/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
llvm/trunk/test/Transforms/TailCallElim/setjmp.ll
Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=141001&r1=141000&r2=141001&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Mon Oct 3 09:45:37 2011
@@ -1262,6 +1262,11 @@
the ELF x86-64 abi, but it can be disabled for some compilation
units.
+ returns_twice
+ This attribute indicates that this function can return
+ twice. The C setjmp is an example of such a function.
+ The compiler disables some optimizations (like tail calls) in the caller of
+ these functions.
Modified: llvm/trunk/include/llvm/Attributes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Attributes.h?rev=141001&r1=141000&r2=141001&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Attributes.h (original)
+++ llvm/trunk/include/llvm/Attributes.h Mon Oct 3 09:45:37 2011
@@ -65,8 +65,7 @@
///of alignment with +1 bias
///0 means unaligned (different from
///alignstack(1))
-const Attributes Hotpatch = 1<<29; ///< Function should have special
- ///'hotpatch' sequence in prologue
+const Attributes ReturnsTwice = 1<<29; ///< Function can return twice
const Attributes UWTable = 1<<30; ///< Function must be in a unwind
///table
const Attributes NonLazyBind = 1U<<31; ///< Function is called early and/or
@@ -93,7 +92,7 @@
const Attributes FunctionOnly = NoReturn | NoUnwind | ReadNone | ReadOnly |
NoInline | AlwaysInline | OptimizeForSize | StackProtect | StackProtectReq |
NoRedZone | NoImplicitFloat | Naked | InlineHint | StackAlignment |
- Hotpatch | UWTable | NonLazyBind;
+ UWTable | NonLazyBind | ReturnsTwice;
/// @brief Parameter attributes that do not apply to vararg call arguments.
const Attributes VarArgsIncompatible = StructRet;
Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=141001&r1=141000&r2=141001&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Mon Oct 3 09:45:37 2011
@@ -558,6 +558,7 @@
KEYWORD(readnone);
KEYWORD(readonly);
KEYWORD(uwtable);
+ KEYWORD(returns_twice);
KEYWORD(inlinehint);
KEYWORD(noinline);
Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=141001&r1=141000&r2=141001&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Oct 3 09:45:37 2011
@@ -911,6 +911,7 @@
case lltok::kw_noreturn: Attrs |= Attribute::NoReturn; break;
case lltok::kw_nounwind: Attrs |= Attribute::NoUnwind; break;
case lltok::kw_uwtable: Attrs |= Attribute::UWTable; break;
+ case lltok::kw_returns_twice: Attrs |= Attribute::ReturnsTwice; break;
case lltok::kw_noinline: Attrs |= Attribute::NoInline; break;
case lltok::kw_readnone: Attrs |= Attribute::ReadNone; break;
case lltok::kw_readonly: Attrs |= Attribute::ReadOnly; break;
@@ -922,7 +923,6 @@
case lltok::kw_noredzone: Attrs |= Attribute::NoRedZone; break;
case lltok::kw_noimplicitfloat: Attrs |= Attribute::NoImplicitFloat; break;
case lltok::kw_naked: Attrs |= Attribute::Naked; break;
- case lltok::kw_hotpatch: Attrs |= Attribute::Hotpatch; break;
case lltok::kw_nonlazybind: Attrs |= Attribute::NonLazyBind; break;
case lltok::kw_alignstack: {
Modified: llvm/trunk/lib/AsmParser/LLToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=141001&r1=141000&r2=141001&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLToken.h (original)
+++ llvm/trunk/lib/AsmParser/LLToken.h Mon Oct 3 09:45:37 2011
@@ -90,6 +90,7 @@
kw_readnone,
kw_readonly,
kw_uwtable,
+ kw_returns_twice,
kw_inlinehint,
kw_noinline,
Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=141001&r1=141000&r2=141001&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Oct 3 09:45:37 2011
@@ -470,7 +470,7 @@
HANDLE_ATTR(NoImplicitFloat);
HANDLE_ATTR(Naked);
HANDLE_ATTR(InlineHint);
- HANDLE_ATTR(Hotpatch);
+ HANDLE_ATTR(ReturnsTwice);
HANDLE_ATTR(UWTable);
HANDLE_ATTR(NonLazyBind);
#undef HANDLE_ATTR
Modified: llvm/trunk/lib/VMCore/Attributes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Attributes.cpp?rev=141001&r1=141000&r2=141001&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Attributes.cpp (original)
+++ llvm/trunk/lib/VMCore/Attributes.cpp Mon Oct 3 09:45:37 2011
@@ -38,6 +38,8 @@
Result += "nounwind ";
if (Attrs & Attribute::UWTable)
Result += "uwtable ";
+ if (Attrs & Attribute::ReturnsTwice)
+ Result += "returns_twice ";
if (Attrs & Attribute::InReg)
Result += "inreg ";
if (Attrs & Attribute::NoAlias)
@@ -72,8 +74,6 @@
Result += "noimplicitfloat ";
if (Attrs & Attribute::Naked)
Result += "naked ";
- if (Attrs & Attribute::Hotpatch)
- Result += "hotpatch ";
if (Attrs & Attribute::NonLazyBind)
Result += "nonlazybind ";
if (Attrs & Attribute::StackAlignment) {
Modified: llvm/trunk/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll?rev=141001&r1=141000&r2=141001&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll (original)
+++ llvm/trunk/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll Mon Oct 3 09:45:37 2011
@@ -42,6 +42,6 @@
ret i32 %retval8
}
-declare i32 @_setjmp(%struct.__jmp_buf_tag*)
+declare i32 @_setjmp(%struct.__jmp_buf_tag*) returns_twice
declare void @g()
Modified: llvm/trunk/test/Transforms/TailCallElim/setjmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailCallElim/setjmp.ll?rev=141001&r1=141000&r2=141001&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/TailCallElim/setjmp.ll (original)
+++ llvm/trunk/test/Transforms/TailCallElim/setjmp.ll Mon Oct 3 09:45:37 2011
@@ -11,6 +11,6 @@
ret void
}
-declare i32 @setjmp(i32*)
+declare i32 @setjmp(i32*) returns_twice
declare void @bar()
From edwintorok at gmail.com Mon Oct 3 10:04:13 2011
From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=)
Date: Mon, 03 Oct 2011 18:04:13 +0300
Subject: [llvm-commits] [llvm] r141001 - in /llvm/trunk:
docs/LangRef.html include/llvm/Attributes.h lib/AsmParser/LLLexer.cpp
lib/AsmParser/LLParser.cpp lib/AsmParser/LLToken.h
lib/Target/CppBackend/CPPBackend.cpp lib/VMCore/Attributes.cpp
test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
test/Transforms/TailCallElim/setjmp.ll
In-Reply-To: <20111003144541.503492A6C12C@llvm.org>
References: <20111003144541.503492A6C12C@llvm.org>
Message-ID: <4E89CEED.6010207@gmail.com>
On 10/03/2011 05:45 PM, Rafael Espindola wrote:
> Author: rafael
> Date: Mon Oct 3 09:45:37 2011
> New Revision: 141001
>
> URL: http://llvm.org/viewvc/llvm-project?rev=141001&view=rev
> Log:
> Add the returns_twice attribute to LLVM.
>
> Modified:
> llvm/trunk/docs/LangRef.html
> llvm/trunk/include/llvm/Attributes.h
> llvm/trunk/lib/AsmParser/LLLexer.cpp
> llvm/trunk/lib/AsmParser/LLParser.cpp
> llvm/trunk/lib/AsmParser/LLToken.h
> llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
> llvm/trunk/lib/VMCore/Attributes.cpp
> llvm/trunk/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
> llvm/trunk/test/Transforms/TailCallElim/setjmp.ll
>
> Modified: llvm/trunk/docs/LangRef.html
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=141001&r1=141000&r2=141001&view=diff
> ==============================================================================
> --- llvm/trunk/docs/LangRef.html (original)
> +++ llvm/trunk/docs/LangRef.html Mon Oct 3 09:45:37 2011
> @@ -1262,6 +1262,11 @@
> the ELF x86-64 abi, but it can be disabled for some compilation
> units.
>
> + returns_twice
> + This attribute indicates that this function can return
> + twice. The C setjmp is an example of such a function.
> + The compiler disables some optimizations (like tail calls) in the caller of
> + these functions.
>
>
>
>
> Modified: llvm/trunk/include/llvm/Attributes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Attributes.h?rev=141001&r1=141000&r2=141001&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Attributes.h (original)
> +++ llvm/trunk/include/llvm/Attributes.h Mon Oct 3 09:45:37 2011
> @@ -65,8 +65,7 @@
> ///of alignment with +1 bias
> ///0 means unaligned (different from
> ///alignstack(1))
> -const Attributes Hotpatch = 1<<29; ///< Function should have special
> - ///'hotpatch' sequence in prologue
> +const Attributes ReturnsTwice = 1<<29; ///< Function can return twice
LangRef still refers to the hotpatch attribute, if you intend to drop it
you should probably remove it from there as well.
Did we run out of bits for attributes?
Best regards,
--Edwin
From echristo at apple.com Mon Oct 3 10:44:54 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 03 Oct 2011 08:44:54 -0700
Subject: [llvm-commits] [llvm] r140924 - in /llvm/trunk/lib/Target/ARM:
ARMBaseRegisterInfo.cpp ARMFrameLowering.cpp Thumb1FrameLowering.cpp
In-Reply-To: <20111001020318.A290E2A6C12C@llvm.org>
References: <20111001020318.A290E2A6C12C@llvm.org>
Message-ID:
On Sep 30, 2011, at 7:03 PM, Chad Rosier wrote:
> Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
> useful if an optimization assumes the stack has been realigned. Credit to
> Eli for his assistance.
> rdar://10043857
Testcase?
-eric
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From echristo at apple.com Mon Oct 3 10:49:20 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 03 Oct 2011 15:49:20 -0000
Subject: [llvm-commits] [llvm] r141005 -
/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
Message-ID: <20111003154920.A04F22A6C12D@llvm.org>
Author: echristo
Date: Mon Oct 3 10:49:20 2011
New Revision: 141005
URL: http://llvm.org/viewvc/llvm-project?rev=141005&view=rev
Log:
Whitespace.
Modified:
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=141005&r1=141004&r2=141005&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Mon Oct 3 10:49:20 2011
@@ -1236,7 +1236,7 @@
return VariableDie;
}
- // Check if variable is described by a DBG_VALUE instruction.
+ // Check if variable is described by a DBG_VALUE instruction.
if (const MachineInstr *DVInsn = DV->getMInsn()) {
bool updated = false;
if (DVInsn->getNumOperands() == 3) {
From echristo at apple.com Mon Oct 3 10:49:16 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 03 Oct 2011 15:49:16 -0000
Subject: [llvm-commits] [llvm] r141004 -
/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20111003154917.E17422A6C12C@llvm.org>
Author: echristo
Date: Mon Oct 3 10:49:16 2011
New Revision: 141004
URL: http://llvm.org/viewvc/llvm-project?rev=141004&view=rev
Log:
Typo.
Modified:
llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=141004&r1=141003&r2=141004&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Oct 3 10:49:16 2011
@@ -386,7 +386,7 @@
TheCU->constructVariableDIE(ArgDV, Scope->isAbstractScope()))
Children.push_back(Arg);
- // Collect lexical scope childrens first.
+ // Collect lexical scope children first.
const SmallVector &Variables = ScopeVariables.lookup(Scope);
for (unsigned i = 0, N = Variables.size(); i < N; ++i)
if (DIE *Variable =
From echristo at apple.com Mon Oct 3 11:40:47 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 03 Oct 2011 09:40:47 -0700
Subject: [llvm-commits] [llvm] r140924 - in /llvm/trunk/lib/Target/ARM:
ARMBaseRegisterInfo.cpp ARMFrameLowering.cpp Thumb1FrameLowering.cpp
In-Reply-To:
References: <20111001020318.A290E2A6C12C@llvm.org>
Message-ID: <12BB28DC-68E0-4577-A6A1-9332A6021CF7@apple.com>
On Oct 3, 2011, at 8:44 AM, Eric Christopher wrote:
>
> On Sep 30, 2011, at 7:03 PM, Chad Rosier wrote:
>
>> Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
>> useful if an optimization assumes the stack has been realigned. Credit to
>> Eli for his assistance.
>> rdar://10043857
>
> Testcase?
Nevermind, I saw you pulled it back out. Might want a test case when you recommit though :)
-eric
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From mcrosier at apple.com Mon Oct 3 11:43:35 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Mon, 03 Oct 2011 09:43:35 -0700
Subject: [llvm-commits] [llvm] r140924 - in /llvm/trunk/lib/Target/ARM:
ARMBaseRegisterInfo.cpp ARMFrameLowering.cpp Thumb1FrameLowering.cpp
In-Reply-To: <12BB28DC-68E0-4577-A6A1-9332A6021CF7@apple.com>
References: <20111001020318.A290E2A6C12C@llvm.org>
<12BB28DC-68E0-4577-A6A1-9332A6021CF7@apple.com>
Message-ID:
On Oct 3, 2011, at 9:40 AM, Eric Christopher wrote:
>
> On Oct 3, 2011, at 8:44 AM, Eric Christopher wrote:
>
>>
>> On Sep 30, 2011, at 7:03 PM, Chad Rosier wrote:
>>
>>> Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
>>> useful if an optimization assumes the stack has been realigned. Credit to
>>> Eli for his assistance.
>>> rdar://10043857
>>
>> Testcase?
>
> Nevermind, I saw you pulled it back out. Might want a test case when you recommit though :)
I will make sure to include one.
Chad
> -eric
>
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From stoklund at 2pi.dk Mon Oct 3 11:50:42 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 03 Oct 2011 09:50:42 -0700
Subject: [llvm-commits] patch: chrec * chrec = chrec.
In-Reply-To: <4E88F8E3.3050506@mxc.ca>
References: <4E88F8E3.3050506@mxc.ca>
Message-ID: <7AD2AE23-DD82-4D4E-A75B-FCB290144F4D@2pi.dk>
On Oct 2, 2011, at 4:50 PM, Nick Lewycky wrote:
> This patch is a follow-up to r139133 which corrected SCEV's getMulExpr when given two chrec arguments. Here I extend it to correctly multiply chrecs of any length.
Hi Nick,
I can't really comment on the SCEV stuff, but
+static unsigned Choose(unsigned n, unsigned k, bool &Overflow) {
+ // This method can overflow internally even if the final result would fit.
+
+ if (n == 0) return 1;
+ if (k >= n) return 1;
+
+ if (k > n/2)
+ k = n-k;
+
+ unsigned r = 1;
+ for (unsigned i = 1; i <= k; ++i) {
+ r = umul_ov(r, n-(i-1), Overflow);
+ r /= i;
+ }
+ return r;
+}
Please add a comment that this function is computing a binomial coefficient, and how it does it.
In particular, it wasn't immediately clear to me that the division never truncates.
Are binomial coefficients defined for k > n? If so, shouldn't the value be 0?
+ const SCEV *CoeffTerm = getConstant(Ty, Coeff1*Coeff2);
Can this multiplication overflow?
Finally, your x,y,z loop is O(N^4) in the number of SCEV operands. I don't know if this is a problem in practice.
The Choose() calls in that loop are computing the same intermediate results over and over. You could get an O(N^3) computation by reusing those binomials.
/jakob
From craig.topper at gmail.com Mon Oct 3 12:28:24 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Mon, 03 Oct 2011 17:28:24 -0000
Subject: [llvm-commits] [llvm] r141007 - in /llvm/trunk:
lib/Target/X86/X86.td lib/Target/X86/X86InstrInfo.td
lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86Subtarget.cpp
lib/Target/X86/X86Subtarget.h test/MC/Disassembler/X86/simple-tests.txt
test/MC/Disassembler/X86/x86-32.txt
Message-ID: <20111003172825.485C52A6C12C@llvm.org>
Author: ctopper
Date: Mon Oct 3 12:28:23 2011
New Revision: 141007
URL: http://llvm.org/viewvc/llvm-project?rev=141007&view=rev
Log:
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
Modified:
llvm/trunk/lib/Target/X86/X86.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86Subtarget.cpp
llvm/trunk/lib/Target/X86/X86Subtarget.h
llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=141007&r1=141006&r2=141007&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Mon Oct 3 12:28:23 2011
@@ -96,6 +96,10 @@
"Allow unaligned memory operands on vector/SIMD instructions">;
def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
"Enable AES instructions">;
+def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
+ "Support MOVBE instruction">;
+def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
+ "Support RDRAND instruction">;
//===----------------------------------------------------------------------===//
// X86 processors supported.
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=141007&r1=141006&r2=141007&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Oct 3 12:28:23 2011
@@ -473,6 +473,8 @@
def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
+def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
+def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
@@ -1297,6 +1299,36 @@
"arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
//===----------------------------------------------------------------------===//
+// MOVBE Instructions
+//
+let Predicates = [HasMOVBE] in {
+ def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
+ "movbe{w}\t{$src, $dst|$dst, $src}", []>, OpSize, T8;
+ def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
+ "movbe{l}\t{$src, $dst|$dst, $src}", []>, T8;
+ def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
+ "movbe{q}\t{$src, $dst|$dst, $src}", []>, T8;
+ def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
+ "movbe{w}\t{$src, $dst|$dst, $src}", []>, OpSize, T8;
+ def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
+ "movbe{l}\t{$src, $dst|$dst, $src}", []>, T8;
+ def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
+ "movbe{q}\t{$src, $dst|$dst, $src}", []>, T8;
+}
+
+//===----------------------------------------------------------------------===//
+// RDRAND Instruction
+//
+let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
+ def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
+ "rdrand{w}\t$dst", []>, OpSize, TB;
+ def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
+ "rdrand{l}\t$dst", []>, TB;
+ def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
+ "rdrand{q}\t$dst", []>, TB;
+}
+
+//===----------------------------------------------------------------------===//
// Subsystems.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=141007&r1=141006&r2=141007&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Oct 3 12:28:23 2011
@@ -6748,4 +6748,3 @@
def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
[(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
}
-
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=141007&r1=141006&r2=141007&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Oct 3 12:28:23 2011
@@ -203,8 +203,10 @@
HasCLMUL = IsIntel && ((ECX >> 1) & 0x1); ToggleFeature(X86::FeatureCLMUL);
HasFMA3 = IsIntel && ((ECX >> 12) & 0x1); ToggleFeature(X86::FeatureFMA3);
+ HasMOVBE = IsIntel && ((ECX >> 22) & 0x1); ToggleFeature(X86::FeatureMOVBE);
HasPOPCNT = IsIntel && ((ECX >> 23) & 0x1); ToggleFeature(X86::FeaturePOPCNT);
HasAES = IsIntel && ((ECX >> 25) & 0x1); ToggleFeature(X86::FeatureAES);
+ HasRDRAND = IsIntel && ((ECX >> 30) & 0x1); ToggleFeature(X86::FeatureRDRAND);
HasCmpxchg16b = ((ECX >> 13) & 0x1); ToggleFeature(X86::FeatureCMPXCHG16B);
if (IsIntel || IsAMD) {
@@ -254,6 +256,8 @@
, HasCLMUL(false)
, HasFMA3(false)
, HasFMA4(false)
+ , HasMOVBE(false)
+ , HasRDRAND(false)
, IsBTMemSlow(false)
, IsUAMemFast(false)
, HasVectorUAMem(false)
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=141007&r1=141006&r2=141007&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Oct 3 12:28:23 2011
@@ -90,6 +90,12 @@
/// HasFMA4 - Target has 4-operand fused multiply-add
bool HasFMA4;
+ /// HasMOVBE - True if the processor has the MOVBE instruction;
+ bool HasMOVBE;
+
+ /// HasRDRAND - True if the processor has the RDRAND instruction;
+ bool HasRDRAND;
+
/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
bool IsBTMemSlow;
@@ -172,6 +178,8 @@
bool hasCLMUL() const { return HasCLMUL; }
bool hasFMA3() const { return HasFMA3; }
bool hasFMA4() const { return HasFMA4; }
+ bool hasMOVBE() const { return HasMOVBE; }
+ bool hasRDRAND() const { return HasRDRAND; }
bool isBTMemSlow() const { return IsBTMemSlow; }
bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
bool hasVectorUAMem() const { return HasVectorUAMem; }
Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=141007&r1=141006&r2=141007&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Mon Oct 3 12:28:23 2011
@@ -368,3 +368,30 @@
# CHECK: vaddps %xmm3, %xmm15, %xmm0
0xc4 0xe1 0x00 0x58 0xc3
+
+# CHECK: movbel (%rax), %eax
+0x0f 0x38 0xf0 0x00
+
+# CHECK: movbel %eax, (%rax)
+0x0f 0x38 0xf1 0x00
+
+# CHECK: movbew (%rax), %ax
+0x66 0x0f 0x38 0xf0 0x00
+
+# CHECK: movbew %ax, (%rax)
+0x66 0x0f 0x38 0xf1 0x00
+
+# CHECK: movbeq (%rax), %rax
+0x48 0x0f 0x38 0xf0 0x00
+
+# CHECK: movbeq %rax, (%rax)
+0x48 0x0f 0x38 0xf1 0x00
+
+# CHECK: rdrandw %ax
+0x66 0x0f 0xc7 0xf0
+
+# CHECK: rdrandl %eax
+0x0f 0xc7 0xf0
+
+# CHECK: rdrandq %rax
+0x48 0x0f 0xc7 0xf0
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=141007&r1=141006&r2=141007&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Mon Oct 3 12:28:23 2011
@@ -387,3 +387,21 @@
# CHECK: vaddps %xmm3, %xmm7, %xmm0
0xc4 0xe1 0x00 0x58 0xc3
+
+# CHECK: movbel (%eax), %eax
+0x0f 0x38 0xf0 0x00
+
+# CHECK: movbel %eax, (%eax)
+0x0f 0x38 0xf1 0x00
+
+# CHECK: movbew (%eax), %ax
+0x66 0x0f 0x38 0xf0 0x00
+
+# CHECK: movbew %ax, (%eax)
+0x66 0x0f 0x38 0xf1 0x00
+
+# CHECK: rdrandw %ax
+0x66 0x0f 0xc7 0xf0
+
+# CHECK: rdrandl %eax
+0x0f 0xc7 0xf0
From clattner at apple.com Mon Oct 3 12:52:00 2011
From: clattner at apple.com (Chris Lattner)
Date: Mon, 03 Oct 2011 10:52:00 -0700
Subject: [llvm-commits] [llvm] r140951 - in /llvm/trunk: ./
include/llvm/TableGen/ lib/ lib/TableGen/ utils/TableGen/
In-Reply-To: <20111001164115.E37E82A6C12C@llvm.org>
References: <20111001164115.E37E82A6C12C@llvm.org>
Message-ID:
On Oct 1, 2011, at 9:41 AM, Peter Collingbourne wrote:
> Author: pcc
> Date: Sat Oct 1 11:41:13 2011
> New Revision: 140951
>
> URL: http://llvm.org/viewvc/llvm-project?rev=140951&view=rev
> Log:
> Move TableGen's parser and entry point into a library
>
> This is the first step towards splitting LLVM and Clang's tblgen executables.
Hi Peter,
Thanks for working on this. Doing this right is going to require some work though:
1. All of the 'main' code and the top-level cl::opt's should be in utils/tablegen, not in TableGen/Main.h
2. The tablegen headers (like the rest of it :) are a mess, they are not split properly between public and private headers.
3. The tblgen code uses RTTI and EH, which none of the rest of the LLVM libraries do.
So long as RTTI and EH don't invade tools other than the utils/TableGen executable, I'm ok with continuing to forget about #3, but #1 and #2 are pretty important.
Are you committed to fixing these problems as follow-ons? What direction are you going here?
-Chris
From grosbach at apple.com Mon Oct 3 12:59:31 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 03 Oct 2011 17:59:31 -0000
Subject: [llvm-commits] [llvm] r141010 -
/llvm/trunk/test/MC/ARM/neon-mov-encoding.s
Message-ID: <20111003175931.E6DD22A6C12C@llvm.org>
Author: grosbach
Date: Mon Oct 3 12:59:31 2011
New Revision: 141010
URL: http://llvm.org/viewvc/llvm-project?rev=141010&view=rev
Log:
Tidy up a bit. Formatting.
Modified:
llvm/trunk/test/MC/ARM/neon-mov-encoding.s
Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.s?rev=141010&r1=141009&r2=141010&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-mov-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-mov-encoding.s Mon Oct 3 12:59:31 2011
@@ -1,117 +1,131 @@
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
@ XFAIL: *
-@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2]
- vmov.i8 d16, #0x8
-@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2]
+ vmov.i8 d16, #0x8
vmov.i16 d16, #0x10
-@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2]
vmov.i16 d16, #0x1000
-@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2]
vmov.i32 d16, #0x20
-@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2]
vmov.i32 d16, #0x2000
-@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2]
vmov.i32 d16, #0x200000
-@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2]
vmov.i32 d16, #0x20000000
-@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2]
vmov.i32 d16, #0x20FF
-@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2]
vmov.i32 d16, #0x20FFFF
-@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3]
vmov.i64 d16, #0xFF0000FF0000FFFF
-@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2]
- vmov.i8 q8, #0x8
-@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2]
+
+@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2]
+@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2]
+@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2]
+@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2]
+@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2]
+@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2]
+@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2]
+@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2]
+@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2]
+@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3]
+
+
+
+ vmov.i8 q8, #0x8
vmov.i16 q8, #0x10
-@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2]
vmov.i16 q8, #0x1000
-@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2]
vmov.i32 q8, #0x20
-@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2]
vmov.i32 q8, #0x2000
-@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2]
vmov.i32 q8, #0x200000
-@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2]
vmov.i32 q8, #0x20000000
-@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2]
vmov.i32 q8, #0x20FF
-@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2]
vmov.i32 q8, #0x20FFFF
-@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3]
vmov.i64 q8, #0xFF0000FF0000FFFF
-@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2]
+
+@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2]
+@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2]
+@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2]
+@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2]
+@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2]
+@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2]
+@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2]
+@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2]
+@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2]
+@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3]
+
vmvn.i16 d16, #0x10
-@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2]
vmvn.i16 d16, #0x1000
-@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2]
vmvn.i32 d16, #0x20
-@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2]
vmvn.i32 d16, #0x2000
-@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2]
vmvn.i32 d16, #0x200000
-@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2]
vmvn.i32 d16, #0x20000000
-@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2]
vmvn.i32 d16, #0x20FF
-@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2]
vmvn.i32 d16, #0x20FFFF
-@ CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf2]
+
+@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2]
+@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2]
+@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2]
+@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2]
+@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2]
+@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2]
+@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2]
+@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2]
+
vmovl.s8 q8, d16
-@ CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf2]
vmovl.s16 q8, d16
-@ CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf2]
vmovl.s32 q8, d16
-@ CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf3]
vmovl.u8 q8, d16
-@ CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf3]
vmovl.u16 q8, d16
-@ CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf3]
vmovl.u32 q8, d16
-@ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3]
+
+@ CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf2]
+@ CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf2]
+@ CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf2]
+@ CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf3]
+@ CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf3]
+@ CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf3]
+
+
vmovn.i16 d16, q8
-@ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3]
vmovn.i32 d16, q8
-@ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3]
vmovn.i64 d16, q8
-@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xf3]
vqmovn.s16 d16, q8
-@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xf3]
vqmovn.s32 d16, q8
-@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xf3]
vqmovn.s64 d16, q8
-@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xf3]
vqmovn.u16 d16, q8
-@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xf3]
vqmovn.u32 d16, q8
-@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xf3]
vqmovn.u64 d16, q8
-@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xf3]
vqmovun.s16 d16, q8
-@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3]
vqmovun.s32 d16, q8
-@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3]
vqmovun.s64 d16, q8
-@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee]
- vmov.s8 r0, d16[1]
-@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee]
+
+@ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3]
+@ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3]
+@ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3]
+@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xf3]
+@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xf3]
+@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xf3]
+@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xf3]
+@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xf3]
+@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xf3]
+@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xf3]
+@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3]
+@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3]
+
+ vmov.s8 r0, d16[1]
vmov.s16 r0, d16[1]
-@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee]
- vmov.u8 r0, d16[1]
-@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee]
+ vmov.u8 r0, d16[1]
vmov.u16 r0, d16[1]
-@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee]
- vmov.32 r0, d16[1]
-@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee]
+ vmov.32 r0, d16[1]
vmov.8 d16[1], r1
-@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee]
vmov.16 d16[1], r1
-@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee]
vmov.32 d16[1], r1
-@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee]
vmov.8 d18[1], r1
-@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee]
vmov.16 d18[1], r1
-@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee]
vmov.32 d18[1], r1
+
+@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee]
+@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee]
+@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee]
+@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee]
+@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee]
+@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee]
+@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee]
+@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee]
+@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee]
+@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee]
+@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee]
From cdavis at mymail.mines.edu Mon Oct 3 13:22:54 2011
From: cdavis at mymail.mines.edu (Charles Davis)
Date: Mon, 3 Oct 2011 12:22:54 -0600
Subject: [llvm-commits] [llvm] r141001 - in /llvm/trunk:
docs/LangRef.html include/llvm/Attributes.h
lib/AsmParser/LLLexer.cpp lib/AsmParser/LLParser.cpp
lib/AsmParser/LLToken.h lib/Target/CppBackend/CPPBackend.cpp
lib/VMCore/Attributes.cpp
test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
test/Transforms/TailCallElim/setjmp.ll
In-Reply-To: <4E89CEED.6010207@gmail.com>
References: <20111003144541.503492A6C12C@llvm.org> <4E89CEED.6010207@gmail.com>
Message-ID: <30C532CC-0907-4DAB-8D06-2D826955D2E7@mymail.mines.edu>
On Oct 3, 2011, at 9:04 AM, T?r?k Edwin wrote:
> Did we run out of bits for attributes?
Yes, we did (cf. thread "Function attribute size limit" on LLVMdev).
>
> Best regards,
> --Edwin
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
From apazos at codeaurora.org Mon Oct 3 13:31:24 2011
From: apazos at codeaurora.org (Ana Pazos)
Date: Mon, 3 Oct 2011 11:31:24 -0700
Subject: [llvm-commits] LLVM patch to optimize integer ABS idiom for ARM
target
In-Reply-To:
References: <000b01cc7408$25f9a5a0$71ecf0e0$@org>
<000f01cc74d5$b9edd790$2dc986b0$@org>
<659E20BB-A99D-43CD-BE21-D5AC8C71834F@apple.com>
<000001cc7d7a$328a7a80$979f6f80$@org>
<94F98DFD-CEA6-41E1-84EB-FAC72B292492@apple.com>
<016e01cc7ec9$6c4550b0$44cff210$@org>
Message-ID: <006601cc81fa$a7d59020$f780b060$@org>
Attached is the updated iabs.ll test patch for ARM and Thumb to match the new codegen.
Thanks!
Ana.
From: Evan Cheng [mailto:evan.cheng at apple.com]
Sent: Friday, September 30, 2011 9:44 PM
To: Ana Pazos
Cc: llvm-commits at cs.uiuc.edu; rajav at codeaurora.org; apazos at codeaurora.org
Subject: Re: [llvm-commits] LLVM patch to optimize integer ABS idiom for ARM target
The patch looks fine to me. But please update the failing tests to match the new codegen. Feel free to get it committed after the update.
Evan
On Sep 29, 2011, at 10:01 AM, Ana Pazos wrote:
Hi folks,
Find attached the updated patch that optimizes integer ABS idiom for the ARM target.
Let me know what you think.
Thank you!
Ana.
From: Evan Cheng [mailto:evan.cheng at apple.com]
Sent: Wednesday, September 28, 2011 5:20 PM
To: Ana Pazos
Cc: 'Eli Friedman'; rajav at codeaurora.org
Subject: Re: [llvm-commits] LLVM patch to optimize integer ABS idiom for ARM target
Hi Ana,
The patch looks much cleaner. There are some minor stylistic issues though:
+ BuildMI(*SinkBB, SinkBB->begin(), dl,
+ TII->get(ARM::PHI), ABSDstReg)
+ .addReg(NewRsbDstReg).addMBB(RSBBB)
+ .addReg(NewMovDstReg).addMBB(BB);
Indentation.
+ if (DisableARMIntABS){
+ return NULL;
+ }
Please make sure there is a space before '{'. Also note in general LLVM code doesn't use { } for single statement if - else clauses.
Please send the patch to llvm-commits for larger audience. Thanks.
Evan
On Sep 27, 2011, at 6:01 PM, Ana Pazos wrote:
Hello Evan,
I have updated the patch following your comments 1-4 and suggestions 1-2.
I have defined separate ARM ABS and t2ABS nodes and have moved the lowering of these nodes (to movs + rsbmi machine instructions) to pre-RA scheduling time.
The updated patch only modifies ARM target-dependent files.
The "bonuses" features imply changes to LLVM target-independent code which I am not able to address right away.
I have also rerun the llvm/test and llvm/projects/test-suite tests and the results are attached.
Please let me know what you think and if further changes are needed.
Note:
- The DAGCombiner lowers SELECT_CC as ASR/ADD/XOR instruction BEFORE each target has a chance to choose its preferred idiom.
The code change in ARMISelDAGToDAG.cpp is to convert ASR/ADD/XOR representing integer ABS into an ARM ABS/t2ABS node.
This was done to avoid changing LLVM target-independent code.
- ABS nodes take a source operand and a destination operand (V1 = ABS V0).
The comparison against 0 and the predicated computation of the absolute value are implicit in the node.
That is why the ABS nodes are declared as defining CPSR.
Thanks a lot!
Ana.
From: Evan Cheng [mailto:evan.cheng at apple.com]
Sent: Sunday, September 18, 2011 11:22 AM
To: Ana Pazos
Cc: rajav at codeaurora.org
Subject: Re: [llvm-commits] LLVM patch to optimize integer ABS idiom for ARM target
On Sep 16, 2011, at 6:04 PM, Ana Pazos wrote:
Hi Evan,
Thanks for the great feedback.
I think I can immediately improve the patch by addressing your points 1-4 and suggestions 1-2 and deliver these changes soon.
The ?bonuses? suggestions imply changes to LLVM target-independent code which I might not be able to address right away.
Would this plan be ok with you?
Yes. Thanks.
Please see my comments below.
Talk to you again soon!
Thanks a lot,
Ana.
From: Evan Cheng [mailto:evan.cheng at apple.com]
Sent: Friday, September 16, 2011 11:32 AM
To: Ana Pazos
Cc: Commit Messages and Patches for LLVM
Subject: Re: [llvm-commits] LLVM patch to optimize integer ABS idiom for ARM target
Hi Ana,
Thanks for working on this. It does look like an important peephole optimization. Unfortunately I think this patch has some problems.
1. The instruction selection pattern is looking for a very specific case. Does it still work if the source is not a function argument? For example, if it's the return value of a function call, or a result of a computation, I don't think it will work with this patch.
[apazos] Yes, it still works if the source is not a function argument. Maybe the test case confused you.
The ASR/ADD/XOR pattern that implements integer ABS is searched for in the DAG and can happen in any place in the function code.
Once it is found, it is replaced with the pseudoABS node using as source operand the ADD instruction first source operand (which is the same as SRA instruction first source operand).
Later when pseudoABS node is lowered, it becomes movs/conditional rsbmi using as source and destination register the pseudoABS instruction destination register.
So there is nothing in the patch that restricts the operand to be ?r0?.
Ok. I'm just concerned about looking for specific patterns could be fragile which is why I suggest adding a ABS isel opcode.
2. MOVrs and RSBccri are not needed. You can expand into MOVr with the optional def set to CPSR and a RSBri with the predicate operand filled in.
[apazos] Probably my inexperience with *.td file definitions. I will find out how to use the existing MOVr and RSBri instruction definitions.
Ok.
3. We want to avoid pseudo instructions that expands into multiple instructions. As you have noticed, this messes up scheduling. Probably the right solution is to expand the instructions at pre-RA scheduling time.
[apazos] I understand why you want to avoid pseudo instructions that expand into multiple instructions. It was my concern too.
I have a version of the patch that implements the optimization at pre-RA scheduling time.
For that, I had to add a PHI node in the DAG (to be able to add the conditional execution path that computes RSB).
The problem with this alternative solution is that LLVM decided to spill both input operands to the PHI nodes, and the final code was very inefficient.
I was not using the latest LLVM source code. I will try this solution again with the LLVM svn tip. Will let you know if I see the problem again.
Ok.
4. It's a bad idea to have a single instruction that's used for both ARM and Thumb2 mode.
[apazos] There is nothing special we need to do handle Thumb2 mode.
I built EEMBC benchmarks in Thumb2 mode and the ABS optimization worked just fine.
Note that in Thumb2 mode conditional execution is implemented with IT instructions.
There is no need to explicitly write IT instructions though.
The assembler/code emitter inserts it for you where necessary changing the pattern movs rsbmi into movs itmi rsbmi.
So I am not sure we need t2ABSri type of node.
You still need pseudo nodes for ARM and Thumb2. We do not allow two modes to share an opcode.
My suggestion:
1. ISel should match to an instruction (say ABS, t2ABSri) that's marked with usesCustomInserter = 1.
2. Add support to lower ABS to MOVr and RSBri with optional def and predicate operands filled in. Please do the same for the Thumb2 variant.
[apazos] I think I understood what you meant. Let me give it a try.
Bonuses:
1. Is this sufficient to generate the best code sequence? e.g.
movs r0, r0
rsbmi r0, r0, #0
This is the best if r0 is a function input. But how about?
add r0, r1
movs r0, r0
rsbmi r0, r0, #0
Shouldn't we copy propagate the movs?
adds r0, r1
rsbmi r0, r0, #0
One possibility is the scheduler custom expansion code look for the instruction that defines the source and tack the optional def on that instruction. Any other ideas?
2. How to make the instruction selection code match more cases? My suggestion is to add a new target independent opcode ABS. For targets where this node is legal, i.e. ARM, dag combine can form this instruction rather than the sra + sub sequence. This way, you can write a simple pattern to match the instruction instead of C++ selection code.
[apazos] So instead of ARM/Thumb-specific DAG nodes create a new target independent ABS DAG node?
SELECT_CC DAG nodes that represent integer ABS patterns are transformed into target independent ABS DAG nodes.
And then ARM/Thumb target lowers it as movs/rsbmi and the other targets lower it as sra + add + xor sequence.
No, other targets will not generate ABS dag nodes since it will not be legal.
The problem with this solution is that it will imply changes to target-independent LLVM code.
In my current solution I strived to not change any target-independent LLVM code.
I believe this is a less fragile solution.
[apazos] Let me give more thought to the 2 bonuses suggestions above.
[apazos] But immediately I can address the other points.
Ok. Thanks.
Evan
Evan
On Sep 15, 2011, at 5:32 PM, Ana Pazos wrote:
Hello,
I worked on an LLVM patch to optimize integer ABS idiom for the ARM target and would like to submit it to your review.
I experimented with EEMBC benchmarks, in particular MPEG encoding, and noted integer ABS computation happens frequently. Significant speed up was achieved with the optimized idiom for ARM (20% for MPEG encoding).
Patch details:
LLVM lowers SELECT_CC nodes that represent an integer ABS pattern into ASR/ADD/XOR instructions.
It is possible to create an optimized machine idiom for integer ABS on ARM formed by MOVs/RSBmi predicated instructions.
This patch modifies ARM-specific files to implement the above optimized machine idiom for integer ABS.
Generation of the optimized integer ABS idiom is turned on by default. To turn this feature off set -disable-arm-int-abs feature flag.
abspatch.diff
Changes to ARM-specific files to implement optimized integer ABS idiom.
abstestpatch.diff
ARM/iabs.ll and Thumb/iabs.ll tests check for the non-optimized integer ABS idiom (ASR/ADD/XOR).
When applying abspatch.diff these tests fail. So patched the tests to set -disable-arm-int-abs flag to prevent the compiler from generating optimized integer ABS pattern and allow the non-optimized idiom to be checked.
iabsopt.ll
Similar to ARM/iabs.ll and Thumb/iabs.ll tests except that it checks for the optimized integer ABS idiom and checks for all possible test conditions.
failures.txt
Failure report and explanation from running llvm/test and projects/test-suite on ARM.
I noted failures running llvm/test (svn version 139318) and projects/test-suite (svn revision 139319) on ARM. Are these failures expected?
Thank you,
Ana.
_______________________________________________
llvm-commits mailing list
llvm-commits at cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
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From bob.wilson at apple.com Mon Oct 3 13:48:17 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 03 Oct 2011 18:48:17 -0000
Subject: [llvm-commits] [llvm] r141013 - /llvm/trunk/utils/buildit/build_llvm
Message-ID: <20111003184817.6C32C2A6C12C@llvm.org>
Author: bwilson
Date: Mon Oct 3 13:48:16 2011
New Revision: 141013
URL: http://llvm.org/viewvc/llvm-project?rev=141013&view=rev
Log:
Find the strip tool that works with the specified SDKROOT. rdar://10165908
Modified:
llvm/trunk/utils/buildit/build_llvm
Modified: llvm/trunk/utils/buildit/build_llvm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=141013&r1=141012&r2=141013&view=diff
==============================================================================
--- llvm/trunk/utils/buildit/build_llvm (original)
+++ llvm/trunk/utils/buildit/build_llvm Mon Oct 3 13:48:16 2011
@@ -201,14 +201,20 @@
echo "#define LLVM_VERSION ${RC_ProjectSourceVersion}" > $DEST_DIR$DEST_ROOT/include/llvm/Version.h
echo "#define LLVM_MINOR_VERSION ${RC_ProjectSourceSubversion}" >> $DEST_DIR$DEST_ROOT/include/llvm/Version.h
+# Find the right version of strip to use.
+STRIP=strip
+if [ -n "$SDKROOT" ]; then
+ STRIP=`xcrun -sdk $SDKROOT -find strip`
+fi
+
if [ "x$LLVM_DEBUG" != "x1" ]; then
# Strip local symbols from llvm libraries.
#
# Use '-l' to strip i386 modules. N.B. that flag doesn't work with kext or
# PPC objects!
- strip -Sl $DEST_DIR$DEST_ROOT/lib/*.[oa]
+ $STRIP -Sl $DEST_DIR$DEST_ROOT/lib/*.[oa]
for f in `ls $DEST_DIR$DEST_ROOT/lib/*.so`; do
- strip -Sxl $f
+ $STRIP -Sxl $f
done
fi
@@ -297,7 +303,7 @@
# Use '-l' to strip i386 modules. N.B. that flag doesn't work with kext or
# PPC objects!
- strip -arch all -Sl $DT_HOME/lib/libLTO.dylib
+ $STRIP -arch all -Sl $DT_HOME/lib/libLTO.dylib
if [ "x$DISABLE_USR_LINKS" == "x" ]; then
# Add a symlink in /usr/lib for B&I.
@@ -327,7 +333,7 @@
# PPC objects!
find $DEST_DIR -perm -0111 -type f \
! \( -name '*.la' -o -name gccas -o -name gccld -o -name llvm-config \) \
- -print | xargs -n 1 -P ${SYSCTL} strip -arch all -Sl
+ -print | xargs -n 1 -P ${SYSCTL} $STRIP -arch all -Sl
chgrp -h -R wheel $DEST_DIR
chgrp -R wheel $DEST_DIR
From dnicacios at gmail.com Mon Oct 3 14:23:34 2011
From: dnicacios at gmail.com (=?ISO-8859-1?Q?Daniel_Nic=E1cio?=)
Date: Mon, 3 Oct 2011 12:23:34 -0700
Subject: [llvm-commits] [patch] ThreeStageLoopUnroll
In-Reply-To: <72EBDCAC-85C1-48EC-91FA-500022E126F1@apple.com>
References:
<36610B20-AAAC-4A37-88EF-DAE333CFA740@apple.com>
<72EBDCAC-85C1-48EC-91FA-500022E126F1@apple.com>
Message-ID:
Thanks for the reply guys, I will fix what you pointed out. And I will work
on it to improve it further.
On Tue, Sep 27, 2011 at 2:55 PM, Devang Patel wrote:
>
> On Sep 27, 2011, at 2:48 PM, David Blaikie wrote:
>
> 2) General llvm convention is to avoid
>>
>> + bool candidate = L->isThreeStageUnrollCandidate(L, LI);
>> + if(candidate) {
>> ?.
>>
>> and do
>>
>> + if (bool candidate = ? ) {
>> + }
>>
>> if candidate is not used outside "if".
>>
>
> At that point you might as well just write:
>
> if (L->isThreeStageUnrollCandidate(L, LI)) {
> }
>
>
> Yes, if candidate is not used inside "if".
> -
> Devang
>
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From ahatanaka at mips.com Mon Oct 3 14:28:50 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Mon, 03 Oct 2011 19:28:50 -0000
Subject: [llvm-commits] [llvm] r141015 - in /llvm/trunk/lib/Target/Mips:
Mips64InstrInfo.td MipsInstrInfo.td
Message-ID: <20111003192850.402DB2A6C12C@llvm.org>
Author: ahatanak
Date: Mon Oct 3 14:28:44 2011
New Revision: 141015
URL: http://llvm.org/viewvc/llvm-project?rev=141015&view=rev
Log:
Add definitions of instructions which move values between 64-bit integer
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=141015&r1=141014&r2=141015&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Oct 3 14:28:44 2011
@@ -90,6 +90,19 @@
let shamt = _shamt;
}
+// Move from Hi/Lo
+let shamt = 0 in {
+let rs = 0, rt = 0 in
+class MoveFromLOHI64 func, string instr_asm>:
+ FR<0x00, func, (outs CPU64Regs:$dst), (ins),
+ !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
+
+let rt = 0, rd = 0 in
+class MoveToLOHI64 func, string instr_asm>:
+ FR<0x00, func, (outs), (ins CPU64Regs:$src),
+ !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
+}
+
//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//
@@ -126,6 +139,16 @@
def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>;
}
+let Defs = [HI64] in
+ def MTHI64 : MoveToLOHI64<0x11, "mthi">;
+let Defs = [LO64] in
+ def MTLO64 : MoveToLOHI64<0x13, "mtlo">;
+
+let Uses = [HI64] in
+ def MFHI64 : MoveFromLOHI64<0x10, "mfhi">;
+let Uses = [LO64] in
+ def MFLO64 : MoveFromLOHI64<0x12, "mflo">;
+
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=141015&r1=141014&r2=141015&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Oct 3 14:28:44 2011
@@ -359,13 +359,17 @@
}
// Move from Hi/Lo
+let shamt = 0 in {
+let rs = 0, rt = 0 in
class MoveFromLOHI func, string instr_asm>:
FR<0x00, func, (outs CPURegs:$dst), (ins),
!strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
+let rt = 0, rd = 0 in
class MoveToLOHI func, string instr_asm>:
FR<0x00, func, (outs), (ins CPURegs:$src),
!strconcat(instr_asm, "\t$src"), [], IIHiLo>;
+}
class EffectiveAddress :
FI<0x09, (outs CPURegs:$dst), (ins mem_ea:$addr),
From ahatanaka at mips.com Mon Oct 3 15:01:11 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Mon, 03 Oct 2011 20:01:11 -0000
Subject: [llvm-commits] [llvm] r141017 - in /llvm/trunk:
lib/Target/Mips/Mips64InstrInfo.td lib/Target/Mips/MipsISelDAGToDAG.cpp
test/CodeGen/Mips/mips64instrs.ll
Message-ID: <20111003200111.E32702A6C12C@llvm.org>
Author: ahatanak
Date: Mon Oct 3 15:01:11 2011
New Revision: 141017
URL: http://llvm.org/viewvc/llvm-project?rev=141017&view=rev
Log:
Add support for 64-bit integer multiply instructions.
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=141017&r1=141016&r2=141017&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Oct 3 15:01:11 2011
@@ -90,6 +90,14 @@
let shamt = _shamt;
}
+// Mul, Div
+let Defs = [HI64, LO64] in {
+ let isCommutable = 1 in
+ class Mul64 func, string instr_asm, InstrItinClass itin>:
+ FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
+ !strconcat(instr_asm, "\t$a, $b"), [], itin>;
+}
+
// Move from Hi/Lo
let shamt = 0 in {
let rs = 0, rt = 0 in
@@ -139,6 +147,10 @@
def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>;
}
+/// Multiply and Divide Instructions.
+def DMULT : Mul64<0x1c, "dmult", IIImul>;
+def DMULTu : Mul64<0x1d, "dmultu", IIImul>;
+
let Defs = [HI64] in
def MTHI64 : MoveToLOHI64<0x11, "mthi">;
let Defs = [LO64] in
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=141017&r1=141016&r2=141017&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Mon Oct 3 15:01:11 2011
@@ -237,6 +237,8 @@
/// Mul with two results
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI: {
+ assert(Node->getValueType(0) != MVT::i64 &&
+ "64-bit multiplication with two results not handled.");
SDValue Op1 = Node->getOperand(0);
SDValue Op2 = Node->getOperand(1);
@@ -262,21 +264,29 @@
/// Special Muls
case ISD::MUL:
- if (Subtarget.hasMips32())
+ // Mips32 has a 32-bit three operand mul instruction.
+ if (Subtarget.hasMips32() && Node->getValueType(0) == MVT::i32)
break;
case ISD::MULHS:
case ISD::MULHU: {
+ assert((Opcode == ISD::MUL || Node->getValueType(0) != MVT::i64) &&
+ "64-bit MULH* not handled.");
+ EVT Ty = Node->getValueType(0);
SDValue MulOp1 = Node->getOperand(0);
SDValue MulOp2 = Node->getOperand(1);
- unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
+ unsigned MulOp = (Opcode == ISD::MULHU ?
+ Mips::MULTu :
+ (Ty == MVT::i32 ? Mips::MULT : Mips::DMULT));
SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
MVT::Glue, MulOp1, MulOp2);
SDValue InFlag = SDValue(MulNode, 0);
- if (Opcode == ISD::MUL)
- return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
+ if (Opcode == ISD::MUL) {
+ unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64);
+ return CurDAG->getMachineNode(Opc, dl, Ty, InFlag);
+ }
else
return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
}
Modified: llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64instrs.ll?rev=141017&r1=141016&r2=141017&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64instrs.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64instrs.ll Mon Oct 3 15:01:11 2011
@@ -70,3 +70,16 @@
ret i64 %xor
}
+define i64 @f12(i64 %a, i64 %b) nounwind readnone {
+entry:
+; CHECK: mult
+ %mul = mul nsw i64 %b, %a
+ ret i64 %mul
+}
+
+define i64 @f13(i64 %a, i64 %b) nounwind readnone {
+entry:
+; CHECK: mult
+ %mul = mul i64 %b, %a
+ ret i64 %mul
+}
From nlewycky at google.com Mon Oct 3 15:03:29 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Mon, 3 Oct 2011 13:03:29 -0700
Subject: [llvm-commits] patch: chrec * chrec = chrec.
In-Reply-To: <7AD2AE23-DD82-4D4E-A75B-FCB290144F4D@2pi.dk>
References: <4E88F8E3.3050506@mxc.ca>
<7AD2AE23-DD82-4D4E-A75B-FCB290144F4D@2pi.dk>
Message-ID:
On 3 October 2011 09:50, Jakob Stoklund Olesen wrote:
>
> On Oct 2, 2011, at 4:50 PM, Nick Lewycky wrote:
>
> > This patch is a follow-up to r139133 which corrected SCEV's getMulExpr
> when given two chrec arguments. Here I extend it to correctly multiply
> chrecs of any length.
>
> Hi Nick,
>
> I can't really comment on the SCEV stuff, but
>
> +static unsigned Choose(unsigned n, unsigned k, bool &Overflow) {
> + // This method can overflow internally even if the final result would
> fit.
> +
> + if (n == 0) return 1;
> + if (k >= n) return 1;
> +
> + if (k > n/2)
> + k = n-k;
> +
> + unsigned r = 1;
> + for (unsigned i = 1; i <= k; ++i) {
> + r = umul_ov(r, n-(i-1), Overflow);
> + r /= i;
> + }
> + return r;
> +}
>
> Please add a comment that this function is computing a binomial
> coefficient, and how it does it.
>
Sure. I was relying on the reader understanding "n choose k".
In particular, it wasn't immediately clear to me that the division never
> truncates.
>
> Are binomial coefficients defined for k > n? If so, shouldn't the value be
> 0?
>
Yes, k > n should be zero.
> + const SCEV *CoeffTerm = getConstant(Ty,
> Coeff1*Coeff2);
>
> Can this multiplication overflow?
>
Oh good point. I spent all this time thinking about what if Ty is an i3 and
Coeff1*Coeff2 doesn't fit there, but not the case where Ty is larger than
unsigned. The most straight-forward thing to do is reuse umul_ov.
Finally, your x,y,z loop is O(N^4) in the number of SCEV operands. I don't
> know if this is a problem in practice.
>
> The Choose() calls in that loop are computing the same intermediate results
> over and over. You could get an O(N^3) computation by reusing those
> binomials.
>
Both true, but not yet observed to be problems in practice. One alternative
approach would be to allocate a binomial-coefficient scratch space and then
use the recursive algorithm. I was really hoping to avoid putting more
complex implementation for Choose into this patch, there's enough gnarly
math in there as it is.
Nick
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From stoklund at 2pi.dk Mon Oct 3 15:20:36 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 03 Oct 2011 13:20:36 -0700
Subject: [llvm-commits] patch: chrec * chrec = chrec.
In-Reply-To:
References: <4E88F8E3.3050506@mxc.ca>
<7AD2AE23-DD82-4D4E-A75B-FCB290144F4D@2pi.dk>
Message-ID:
On Oct 3, 2011, at 1:03 PM, Nick Lewycky wrote:
> On 3 October 2011 09:50, Jakob Stoklund Olesen wrote:
>
> + const SCEV *CoeffTerm = getConstant(Ty, Coeff1*Coeff2);
>
> Can this multiplication overflow?
>
> Oh good point. I spent all this time thinking about what if Ty is an i3 and Coeff1*Coeff2 doesn't fit there, but not the case where Ty is larger than unsigned. The most straight-forward thing to do is reuse umul_ov.
Or just promote to 64-bit. ScalarEvolution::getConstant() already takes a uint64_t.
>
> Finally, your x,y,z loop is O(N^4) in the number of SCEV operands. I don't know if this is a problem in practice.
>
> The Choose() calls in that loop are computing the same intermediate results over and over. You could get an O(N^3) computation by reusing those binomials.
>
> Both true, but not yet observed to be problems in practice. One alternative approach would be to allocate a binomial-coefficient scratch space and then use the recursive algorithm. I was really hoping to avoid putting more complex implementation for Choose into this patch, there's enough gnarly math in there as it is.
Fair enough.
/jakob
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From ahatanaka at mips.com Mon Oct 3 15:38:09 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Mon, 03 Oct 2011 20:38:09 -0000
Subject: [llvm-commits] [llvm] r141019 -
/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
Message-ID: <20111003203809.4EF552A6C12C@llvm.org>
Author: ahatanak
Date: Mon Oct 3 15:38:08 2011
New Revision: 141019
URL: http://llvm.org/viewvc/llvm-project?rev=141019&view=rev
Log:
Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer
registers.
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=141019&r1=141018&r2=141019&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Oct 3 15:38:08 2011
@@ -94,70 +94,63 @@
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
- bool DestCPU = Mips::CPURegsRegClass.contains(DestReg);
- bool SrcCPU = Mips::CPURegsRegClass.contains(SrcReg);
+ unsigned Opc = 0, ZeroReg = 0;
- // CPU-CPU is the most common.
- if (DestCPU && SrcCPU) {
- BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
-
- // Copy to CPU from other registers.
- if (DestCPU) {
- if (Mips::CCRRegClass.contains(SrcReg))
- BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
+ if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
+ if (Mips::CPURegsRegClass.contains(SrcReg))
+ Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
+ else if (Mips::CCRRegClass.contains(SrcReg))
+ Opc = Mips::CFC1;
else if (Mips::FGR32RegClass.contains(SrcReg))
- BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
+ Opc = Mips::MFC1;
else if (SrcReg == Mips::HI)
- BuildMI(MBB, I, DL, get(Mips::MFHI), DestReg);
+ Opc = Mips::MFHI, SrcReg = 0;
else if (SrcReg == Mips::LO)
- BuildMI(MBB, I, DL, get(Mips::MFLO), DestReg);
- else
- llvm_unreachable("Copy to CPU from invalid register");
- return;
+ Opc = Mips::MFLO, SrcReg = 0;
}
-
- // Copy to other registers from CPU.
- if (SrcCPU) {
+ else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
if (Mips::CCRRegClass.contains(DestReg))
- BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
+ Opc = Mips::CTC1;
else if (Mips::FGR32RegClass.contains(DestReg))
- BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
+ Opc = Mips::MTC1;
else if (DestReg == Mips::HI)
- BuildMI(MBB, I, DL, get(Mips::MTHI))
- .addReg(SrcReg, getKillRegState(KillSrc));
+ Opc = Mips::MTHI, DestReg = 0;
else if (DestReg == Mips::LO)
- BuildMI(MBB, I, DL, get(Mips::MTLO))
- .addReg(SrcReg, getKillRegState(KillSrc));
- else
- llvm_unreachable("Copy from CPU to invalid register");
- return;
+ Opc = Mips::MTLO, DestReg = 0;
}
-
- if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) {
- BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
+ else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
+ Opc = Mips::FMOV_S32;
+ else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
+ Opc = Mips::FMOV_D32;
+ else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
+ Opc = Mips::MOVCCRToCCR;
+ else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
+ if (Mips::CPU64RegsRegClass.contains(SrcReg))
+ Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
+ else if (SrcReg == Mips::HI64)
+ Opc = Mips::MFHI64, SrcReg = 0;
+ else if (SrcReg == Mips::LO64)
+ Opc = Mips::MFLO64, SrcReg = 0;
+ }
+ else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
+ if (DestReg == Mips::HI64)
+ Opc = Mips::MTHI64, DestReg = 0;
+ else if (DestReg == Mips::LO64)
+ Opc = Mips::MTLO64, DestReg = 0;
}
- if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) {
- BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
+ assert(Opc && "Cannot copy registers");
- if (Mips::CCRRegClass.contains(DestReg, SrcReg)) {
- BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
- llvm_unreachable("Cannot copy registers");
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
+
+ if (DestReg)
+ MIB.addReg(DestReg, RegState::Define);
+
+ if (ZeroReg)
+ MIB.addReg(ZeroReg);
+
+ if (SrcReg)
+ MIB.addReg(SrcReg, getKillRegState(KillSrc));
}
void MipsInstrInfo::
From joerg at britannica.bec.de Mon Oct 3 15:51:57 2011
From: joerg at britannica.bec.de (Joerg Sonnenberger)
Date: Mon, 3 Oct 2011 22:51:57 +0200
Subject: [llvm-commits] patch: chrec * chrec = chrec.
In-Reply-To: <4E88F8E3.3050506@mxc.ca>
References: <4E88F8E3.3050506@mxc.ca>
Message-ID: <20111003205157.GA10434@britannica.bec.de>
On Sun, Oct 02, 2011 at 04:50:59PM -0700, Nick Lewycky wrote:
> Index: lib/Analysis/ScalarEvolution.cpp
> ===================================================================
> --- lib/Analysis/ScalarEvolution.cpp (revision 140963)
> +++ lib/Analysis/ScalarEvolution.cpp (working copy)
> @@ -1812,6 +1812,29 @@
> return S;
> }
>
> +static unsigned umul_ov(unsigned i, unsigned j, bool &Overflow) {
> + unsigned k = i*j;
> + if (j > 1 && k / j != i) Overflow = true;
> + return k;
> +}
> +
> +static unsigned Choose(unsigned n, unsigned k, bool &Overflow) {
> + // This method can overflow internally even if the final result would fit.
> +
> + if (n == 0) return 1;
> + if (k >= n) return 1;
> +
> + if (k > n/2)
> + k = n-k;
> +
> + unsigned r = 1;
> + for (unsigned i = 1; i <= k; ++i) {
> + r = umul_ov(r, n-(i-1), Overflow);
> + r /= i;
> + }
> + return r;
> +}
> +
What exactly is the desired behavior in case of overflow?
E.g. do you want to get C(n,k) % (UINTMAX + 1)? In that case, your
formula doesn't compute correct results.
Joerg
From grosbach at apple.com Mon Oct 3 15:52:00 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 03 Oct 2011 20:52:00 -0000
Subject: [llvm-commits] [llvm] r141020 -
/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
Message-ID: <20111003205200.751D02A6C12C@llvm.org>
Author: grosbach
Date: Mon Oct 3 15:51:59 2011
New Revision: 141020
URL: http://llvm.org/viewvc/llvm-project?rev=141020&view=rev
Log:
Thumb2 ADD/SUB can take SP as a destination register.
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=141020&r1=141019&r2=141020&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Oct 3 15:51:59 2011
@@ -639,9 +639,9 @@
// in particular for taking the address of a local.
let isReMaterializable = 1 in {
def ri : T2sTwoRegImm<
- (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
- opc, ".w\t$Rd, $Rn, $imm",
- [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
+ (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
+ opc, ".w\t$Rd, $Rn, $imm",
+ [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24} = 1;
@@ -651,9 +651,9 @@
}
// 12-bit imm
def ri12 : T2I<
- (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
+ (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
!strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
- [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
+ [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
@@ -669,9 +669,9 @@
let Inst{7-0} = imm{7-0};
}
// register
- def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
- opc, ".w\t$Rd, $Rn, $Rm",
- [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
+ def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
+ IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
+ [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
let isCommutable = Commutable;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
@@ -683,9 +683,9 @@
}
// shifted register
def rs : T2sTwoRegShiftedReg<
- (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
+ (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
- [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
+ [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24} = 1;
@@ -3848,24 +3848,24 @@
// Aliases for ADD without the ".w" optional width specifier.
def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
- (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+ (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
- (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
+ (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
- (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
+ (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
- (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
+ (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
pred:$p, cc_out:$s)>;
// Aliases for SUB without the ".w" optional width specifier.
def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
- (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+ (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
- (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
+ (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
- (t2SUBrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
+ (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
- (t2SUBrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
+ (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
pred:$p, cc_out:$s)>;
// Alias for compares without the ".w" optional width specifier.
From grosbach at apple.com Mon Oct 3 15:58:08 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 03 Oct 2011 20:58:08 -0000
Subject: [llvm-commits] [llvm] r141022 -
/llvm/trunk/test/MC/ARM/thumb-diagnostics.s
Message-ID: <20111003205808.BE5722A6C12C@llvm.org>
Author: grosbach
Date: Mon Oct 3 15:58:08 2011
New Revision: 141022
URL: http://llvm.org/viewvc/llvm-project?rev=141022&view=rev
Log:
Update test for 141010.
Modified:
llvm/trunk/test/MC/ARM/thumb-diagnostics.s
Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=141022&r1=141021&r2=141022&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Mon Oct 3 15:58:08 2011
@@ -131,7 +131,7 @@
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: add sp, #3
@ CHECK-ERRORS: ^
-@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
@ CHECK-ERRORS: add sp, sp, #512
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
From dpatel at apple.com Mon Oct 3 15:59:18 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 03 Oct 2011 20:59:18 -0000
Subject: [llvm-commits] [llvm] r141023 - in /llvm/trunk:
include/llvm-c/Core.h lib/VMCore/Core.cpp
Message-ID: <20111003205918.5DBAE2A6C12C@llvm.org>
Author: dpatel
Date: Mon Oct 3 15:59:18 2011
New Revision: 141023
URL: http://llvm.org/viewvc/llvm-project?rev=141023&view=rev
Log:
Add C api for Instruction->eraseFromParent().
Modified:
llvm/trunk/include/llvm-c/Core.h
llvm/trunk/lib/VMCore/Core.cpp
Modified: llvm/trunk/include/llvm-c/Core.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=141023&r1=141022&r2=141023&view=diff
==============================================================================
--- llvm/trunk/include/llvm-c/Core.h (original)
+++ llvm/trunk/include/llvm-c/Core.h Mon Oct 3 15:59:18 2011
@@ -776,6 +776,7 @@
LLVMBasicBlockRef LLVMGetInstructionParent(LLVMValueRef Inst);
LLVMValueRef LLVMGetNextInstruction(LLVMValueRef Inst);
LLVMValueRef LLVMGetPreviousInstruction(LLVMValueRef Inst);
+void LLVMInstructionEraseFromParent(LLVMValueRef Inst);
/* Operations on call sites */
void LLVMSetInstructionCallConv(LLVMValueRef Instr, unsigned CC);
Modified: llvm/trunk/lib/VMCore/Core.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=141023&r1=141022&r2=141023&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Core.cpp (original)
+++ llvm/trunk/lib/VMCore/Core.cpp Mon Oct 3 15:59:18 2011
@@ -1508,6 +1508,10 @@
return wrap(--I);
}
+void LLVMInstructionEraseFromParent(LLVMValueRef Inst) {
+ unwrap(Inst)->eraseFromParent();
+}
+
/*--.. Call and invoke instructions ........................................--*/
unsigned LLVMGetInstructionCallConv(LLVMValueRef Instr) {
From ahatanaka at mips.com Mon Oct 3 16:06:13 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Mon, 03 Oct 2011 21:06:13 -0000
Subject: [llvm-commits] [llvm] r141024 - in /llvm/trunk:
lib/Target/Mips/Mips64InstrInfo.td lib/Target/Mips/MipsISelLowering.cpp
lib/Target/Mips/MipsInstrInfo.td test/CodeGen/Mips/mips64instrs.ll
Message-ID: <20111003210613.966DD2A6C12C@llvm.org>
Author: ahatanak
Date: Mon Oct 3 16:06:13 2011
New Revision: 141024
URL: http://llvm.org/viewvc/llvm-project?rev=141024&view=rev
Log:
Add support for 64-bit divide instructions.
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=141024&r1=141023&r2=141024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Oct 3 16:06:13 2011
@@ -96,6 +96,11 @@
class Mul64 func, string instr_asm, InstrItinClass itin>:
FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
!strconcat(instr_asm, "\t$a, $b"), [], itin>;
+
+ class Div64 func, string instr_asm, InstrItinClass itin>:
+ FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
+ !strconcat(instr_asm, "\t$$zero, $a, $b"),
+ [(op CPU64Regs:$a, CPU64Regs:$b)], itin>;
}
// Move from Hi/Lo
@@ -150,6 +155,8 @@
/// Multiply and Divide Instructions.
def DMULT : Mul64<0x1c, "dmult", IIImul>;
def DMULTu : Mul64<0x1d, "dmultu", IIImul>;
+def DSDIV : Div64;
+def DUDIV : Div64;
let Defs = [HI64] in
def MTHI64 : MoveToLOHI64<0x11, "mthi">;
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=141024&r1=141023&r2=141024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Oct 3 16:06:13 2011
@@ -138,6 +138,10 @@
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UDIV, MVT::i32, Expand);
setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SDIV, MVT::i64, Expand);
+ setOperationAction(ISD::SREM, MVT::i64, Expand);
+ setOperationAction(ISD::UDIV, MVT::i64, Expand);
+ setOperationAction(ISD::UREM, MVT::i64, Expand);
// Operations not directly supported by Mips.
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
@@ -413,6 +417,9 @@
if (DCI.isBeforeLegalizeOps())
return SDValue();
+ EVT Ty = N->getValueType(0);
+ unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
+ unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
MipsISD::DivRemU;
DebugLoc dl = N->getDebugLoc();
@@ -424,7 +431,7 @@
// insert MFLO
if (N->hasAnyUseOfValue(0)) {
- SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32,
+ SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
InGlue);
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
InChain = CopyFromLo.getValue(1);
@@ -434,7 +441,7 @@
// insert MFHI
if (N->hasAnyUseOfValue(1)) {
SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
- Mips::HI, MVT::i32, InGlue);
+ HI, Ty, InGlue);
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=141024&r1=141023&r2=141024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Oct 3 16:06:13 2011
@@ -34,7 +34,7 @@
SDTCisSameAs<1, 2>,
SDTCisSameAs<2, 3>]>;
def SDT_MipsDivRem : SDTypeProfile<0, 2,
- [SDTCisVT<0, i32>,
+ [SDTCisInt<0>,
SDTCisSameAs<0, 1>]>;
def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
Modified: llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64instrs.ll?rev=141024&r1=141023&r2=141024&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64instrs.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64instrs.ll Mon Oct 3 16:06:13 2011
@@ -83,3 +83,36 @@
%mul = mul i64 %b, %a
ret i64 %mul
}
+
+define i64 @f14(i64 %a, i64 %b) nounwind readnone {
+entry:
+; CHECK: ddiv $zero
+; CHECK: mflo
+ %div = sdiv i64 %a, %b
+ ret i64 %div
+}
+
+define i64 @f15(i64 %a, i64 %b) nounwind readnone {
+entry:
+; CHECK: ddivu $zero
+; CHECK: mflo
+ %div = udiv i64 %a, %b
+ ret i64 %div
+}
+
+define i64 @f16(i64 %a, i64 %b) nounwind readnone {
+entry:
+; CHECK: ddiv $zero
+; CHECK: mfhi
+ %rem = srem i64 %a, %b
+ ret i64 %rem
+}
+
+define i64 @f17(i64 %a, i64 %b) nounwind readnone {
+entry:
+; CHECK: ddivu $zero
+; CHECK: mfhi
+ %rem = urem i64 %a, %b
+ ret i64 %rem
+}
+
From nlewycky at google.com Mon Oct 3 16:10:45 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Mon, 3 Oct 2011 14:10:45 -0700
Subject: [llvm-commits] patch: chrec * chrec = chrec.
In-Reply-To: <20111003205157.GA10434@britannica.bec.de>
References: <4E88F8E3.3050506@mxc.ca>
<20111003205157.GA10434@britannica.bec.de>
Message-ID:
On 3 October 2011 13:51, Joerg Sonnenberger wrote:
> On Sun, Oct 02, 2011 at 04:50:59PM -0700, Nick Lewycky wrote:
> > Index: lib/Analysis/ScalarEvolution.cpp
> > ===================================================================
> > --- lib/Analysis/ScalarEvolution.cpp (revision 140963)
> > +++ lib/Analysis/ScalarEvolution.cpp (working copy)
> > @@ -1812,6 +1812,29 @@
> > return S;
> > }
> >
> > +static unsigned umul_ov(unsigned i, unsigned j, bool &Overflow) {
> > + unsigned k = i*j;
> > + if (j > 1 && k / j != i) Overflow = true;
> > + return k;
> > +}
> > +
> > +static unsigned Choose(unsigned n, unsigned k, bool &Overflow) {
> > + // This method can overflow internally even if the final result would
> fit.
> > +
> > + if (n == 0) return 1;
> > + if (k >= n) return 1;
> > +
> > + if (k > n/2)
> > + k = n-k;
> > +
> > + unsigned r = 1;
> > + for (unsigned i = 1; i <= k; ++i) {
> > + r = umul_ov(r, n-(i-1), Overflow);
> > + r /= i;
> > + }
> > + return r;
> > +}
> > +
>
> What exactly is the desired behavior in case of overflow?
> E.g. do you want to get C(n,k) % (UINTMAX + 1)? In that case, your
> formula doesn't compute correct results.
>
In overflow the return value is garbage and Overflow is set. This method
deserves a comment.
Nick
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From grosbach at apple.com Mon Oct 3 16:12:43 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 03 Oct 2011 21:12:43 -0000
Subject: [llvm-commits] [llvm] r141025 - in /llvm/trunk:
lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrVFP.td
lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/simple-fp-encoding.s
Message-ID: <20111003211243.8AF782A6C12C@llvm.org>
Author: grosbach
Date: Mon Oct 3 16:12:43 2011
New Revision: 141025
URL: http://llvm.org/viewvc/llvm-project?rev=141025&view=rev
Log:
ARM assembly parsing and encoding for VMRS/FMSTAT.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/simple-fp-encoding.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=141025&r1=141024&r2=141025&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Oct 3 16:12:43 2011
@@ -227,6 +227,10 @@
: InstAlias, Requires<[IsThumb]>;
class t2InstAlias
: InstAlias, Requires<[IsThumb2]>;
+class VFP2InstAlias
+ : InstAlias, Requires<[HasVFP2]>;
+class VFP3InstAlias
+ : InstAlias, Requires<[HasVFP3]>;
//===----------------------------------------------------------------------===//
// ARM Instruction templates.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=141025&r1=141024&r2=141025&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Oct 3 16:12:43 2011
@@ -1148,3 +1148,10 @@
let Inst{3-0} = imm{3-0};
}
}
+
+//===----------------------------------------------------------------------===//
+// Assembler aliases.
+//
+
+def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
+
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=141025&r1=141024&r2=141025&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Oct 3 16:12:43 2011
@@ -3046,6 +3046,7 @@
Error(Parser.getTok().getLoc(), "unexpected token in operand");
return true;
case AsmToken::Identifier: {
+ // If this is VMRS, check for the apsr_nzcv operand.
if (!tryParseRegisterWithWriteBack(Operands))
return false;
int Res = tryParseShiftRegister(Operands);
@@ -3053,6 +3054,12 @@
return false;
else if (Res == -1) // irrecoverable error
return true;
+ if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
+ S = Parser.getTok().getLoc();
+ Parser.Lex();
+ Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
+ return false;
+ }
// Fall though for the Identifier case that is not a register or a
// special name.
Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=141025&r1=141024&r2=141025&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Mon Oct 3 16:12:43 2011
@@ -114,8 +114,10 @@
@ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]
vnmls.f32 s1, s2, s0
-@ FIXME: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
-@ vmrs apsr_nzcv, fpscr
+@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
+@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
+ vmrs apsr_nzcv, fpscr
+ fmstat
@ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
vnegne.f64 d16, d16
From isanbard at gmail.com Mon Oct 3 16:15:28 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 03 Oct 2011 21:15:28 -0000
Subject: [llvm-commits] [llvm] r141026 -
/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
Message-ID: <20111003211528.C1E702A6C12C@llvm.org>
Author: void
Date: Mon Oct 3 16:15:28 2011
New Revision: 141026
URL: http://llvm.org/viewvc/llvm-project?rev=141026&view=rev
Log:
Move the grabbing of the jump buffer into the caller function, eliminating the need for returning a std::pair.
Modified:
llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=141026&r1=141025&r2=141026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Mon Oct 3 16:15:28 2011
@@ -75,8 +75,7 @@
private:
bool setupEntryBlockAndCallSites(Function &F);
- std::pair
- setupFunctionContext(Function &F, ArrayRef LPads);
+ Value *setupFunctionContext(Function &F, ArrayRef LPads);
void insertCallSiteStore(Instruction *I, int Number, Value *CallSite);
void markInvokeCallSite(InvokeInst *II, int InvokeNo, Value *CallSite,
@@ -712,7 +711,7 @@
/// setupFunctionContext - Allocate the function context on the stack and fill
/// it with all of the data that we know at this point.
-std::pair SjLjEHPass::
+Value *SjLjEHPass::
setupFunctionContext(Function &F, ArrayRef LPads) {
BasicBlock *EntryBB = F.begin();
@@ -788,24 +787,7 @@
EntryBB->getTerminator());
new StoreInst(LSDA, LSDAFieldPtr, true, EntryBB->getTerminator());
- // Get a reference to the jump buffer.
- Idxs[1] = ConstantInt::get(Int32Ty, 5);
- Value *JBufPtr =
- GetElementPtrInst::Create(FuncCtx, Idxs, "jbuf_gep",
- EntryBB->getTerminator());
- Idxs[1] = Zero;
- Value *FramePtr =
- GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_fp_gep",
- EntryBB->getTerminator());
-
- // Save the frame pointer.
- Value *Val = CallInst::Create(FrameAddrFn,
- ConstantInt::get(Int32Ty, 0),
- "fp",
- EntryBB->getTerminator());
- new StoreInst(Val, FramePtr, true, EntryBB->getTerminator());
-
- return std::make_pair(FuncCtx, JBufPtr);
+ return FuncCtx;
}
/// setupEntryBlockAndCallSites - Setup the entry block by creating and filling
@@ -827,24 +809,44 @@
if (Invokes.empty()) return false;
- std::pair FuncCtx = setupFunctionContext(F, LPads);
+ Value *FuncCtx = setupFunctionContext(F, LPads);
BasicBlock *EntryBB = F.begin();
-
- // Save the stack pointer.
Type *Int32Ty = Type::getInt32Ty(F.getContext());
+
Value *Idxs[2] = {
- ConstantInt::get(Int32Ty, 0), ConstantInt::get(Int32Ty, 2)
+ ConstantInt::get(Int32Ty, 0), 0
};
+
+ // Get a reference to the jump buffer.
+ Idxs[1] = ConstantInt::get(Int32Ty, 5);
+ Value *JBufPtr =
+ GetElementPtrInst::Create(FuncCtx, Idxs, "jbuf_gep",
+ EntryBB->getTerminator());
+
+ // Save the frame pointer.
+ Idxs[1] = ConstantInt::get(Int32Ty, 0);
+ Value *FramePtr =
+ GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_fp_gep",
+ EntryBB->getTerminator());
+
+ Value *Val = CallInst::Create(FrameAddrFn,
+ ConstantInt::get(Int32Ty, 0),
+ "fp",
+ EntryBB->getTerminator());
+ new StoreInst(Val, FramePtr, true, EntryBB->getTerminator());
+
+ // Save the stack pointer.
+ Idxs[1] = ConstantInt::get(Int32Ty, 2);
Value *StackPtr =
- GetElementPtrInst::Create(FuncCtx.second, Idxs, "jbuf_sp_gep",
+ GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_sp_gep",
EntryBB->getTerminator());
- Value *Val = CallInst::Create(StackAddrFn, "sp", EntryBB->getTerminator());
+ Val = CallInst::Create(StackAddrFn, "sp", EntryBB->getTerminator());
new StoreInst(Val, StackPtr, true, EntryBB->getTerminator());
// Call the setjmp instrinsic. It fills in the rest of the jmpbuf.
Value *SetjmpArg =
- CastInst::Create(Instruction::BitCast, FuncCtx.second,
+ CastInst::Create(Instruction::BitCast, JBufPtr,
Type::getInt8PtrTy(F.getContext()), "",
EntryBB->getTerminator());
Value *DispatchVal = CallInst::Create(BuiltinSetjmpFn, SetjmpArg,
@@ -858,7 +860,7 @@
// Store a pointer to the function context so that the back-end will know
// where to look for it.
Value *FuncCtxArg =
- CastInst::Create(Instruction::BitCast, FuncCtx.first,
+ CastInst::Create(Instruction::BitCast, FuncCtx,
Type::getInt8PtrTy(F.getContext()), "",
EntryBB->getTerminator());
CallInst::Create(FuncCtxFn, FuncCtxArg, "", EntryBB->getTerminator());
@@ -892,14 +894,14 @@
}
// Register the function context and make sure it's known to not throw
- CallInst *Register = CallInst::Create(RegisterFn, FuncCtx.first, "",
+ CallInst *Register = CallInst::Create(RegisterFn, FuncCtx, "",
EntryBB->getTerminator());
Register->setDoesNotThrow();
// Finally, for any returns from this function, if this function contains an
// invoke, add a call to unregister the function context.
for (unsigned I = 0, E = Returns.size(); I != E; ++I)
- CallInst::Create(UnregisterFn, FuncCtx.first, "", Returns[I]);
+ CallInst::Create(UnregisterFn, FuncCtx, "", Returns[I]);
return true;
}
From ahatanaka at mips.com Mon Oct 3 16:16:53 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Mon, 03 Oct 2011 21:16:53 -0000
Subject: [llvm-commits] [llvm] r141028 - in /llvm/trunk:
lib/Target/Mips/Mips64InstrInfo.td test/CodeGen/Mips/mips64instrs.ll
Message-ID: <20111003211653.ED1F32A6C12C@llvm.org>
Author: ahatanak
Date: Mon Oct 3 16:16:50 2011
New Revision: 141028
URL: http://llvm.org/viewvc/llvm-project?rev=141028&view=rev
Log:
Add support for 64-bit count leading ones and zeros instructions.
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=141028&r1=141027&r2=141028&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Oct 3 16:16:50 2011
@@ -116,6 +116,15 @@
!strconcat(instr_asm, "\t$src"), [], IIHiLo>;
}
+// Count Leading Ones/Zeros in Word
+class CountLeading64 func, string instr_asm, list pattern>:
+ FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
+ !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
+ Requires<[HasBitCount]> {
+ let shamt = 0;
+ let rt = rd;
+}
+
//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//
@@ -168,6 +177,12 @@
let Uses = [LO64] in
def MFLO64 : MoveFromLOHI64<0x12, "mflo">;
+/// Count Leading
+def DCLZ : CountLeading64<0x24, "dclz",
+ [(set CPU64Regs:$dst, (ctlz CPU64Regs:$src))]>;
+def DCLO : CountLeading64<0x25, "dclo",
+ [(set CPU64Regs:$dst, (ctlz (not CPU64Regs:$src)))]>;
+
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64instrs.ll?rev=141028&r1=141027&r2=141028&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64instrs.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64instrs.ll Mon Oct 3 16:16:50 2011
@@ -116,3 +116,20 @@
ret i64 %rem
}
+declare i64 @llvm.ctlz.i64(i64) nounwind readnone
+
+; CHECK: dclz $2, $4
+define i64 @f18(i64 %X) nounwind readnone {
+entry:
+ %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X)
+ ret i64 %tmp1
+}
+
+; CHECK: dclo $2, $4
+define i64 @f19(i64 %X) nounwind readnone {
+entry:
+ %neg = xor i64 %X, -1
+ %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg)
+ ret i64 %tmp1
+}
+
From ahatanaka at mips.com Mon Oct 3 16:23:18 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Mon, 03 Oct 2011 21:23:18 -0000
Subject: [llvm-commits] [llvm] r141029 - in /llvm/trunk:
lib/Target/Mips/Mips64InstrInfo.td test/CodeGen/Mips/mips64instrs.ll
Message-ID: <20111003212319.188E62A6C12C@llvm.org>
Author: ahatanak
Date: Mon Oct 3 16:23:18 2011
New Revision: 141029
URL: http://llvm.org/viewvc/llvm-project?rev=141029&view=rev
Log:
Add support for 64-bit logical NOR.
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=141029&r1=141028&r2=141029&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Oct 3 16:23:18 2011
@@ -72,6 +72,12 @@
!strconcat(instr_asm, "\t$dst, $b, $c"),
[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, immZExt16:$c))], IIAlu>;
+let isCommutable = 1 in
+class LogicNOR64 op, bits<6> func, string instr_asm>:
+ FR;
+
// Shifts
class LogicR_shift_rotate_imm64 func, bits<5> _rs, string instr_asm,
SDNode OpNode, PatFrag PF>:
@@ -141,6 +147,7 @@
def DAND : LogicR64<0x24, "and", and>;
def DOR : LogicR64<0x25, "or", or>;
def DXOR : LogicR64<0x26, "xor", xor>;
+def DNOR : LogicNOR64<0x00, 0x27, "nor">;
/// Shift Instructions
def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>;
Modified: llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64instrs.ll?rev=141029&r1=141028&r2=141029&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64instrs.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64instrs.ll Mon Oct 3 16:23:18 2011
@@ -133,3 +133,11 @@
ret i64 %tmp1
}
+define i64 @f20(i64 %a, i64 %b) nounwind readnone {
+entry:
+; CHECK: nor
+ %or = or i64 %b, %a
+ %neg = xor i64 %or, -1
+ ret i64 %neg
+}
+
From ahatanaka at mips.com Mon Oct 3 16:24:30 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Mon, 03 Oct 2011 21:24:30 -0000
Subject: [llvm-commits] [llvm] r141030 -
/llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
Message-ID: <20111003212430.5DCEA2A6C12C@llvm.org>
Author: ahatanak
Date: Mon Oct 3 16:24:30 2011
New Revision: 141030
URL: http://llvm.org/viewvc/llvm-project?rev=141030&view=rev
Log:
Move CHECK after entry label.
Modified:
llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
Modified: llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64instrs.ll?rev=141030&r1=141029&r2=141030&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64instrs.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64instrs.ll Mon Oct 3 16:24:30 2011
@@ -118,16 +118,16 @@
declare i64 @llvm.ctlz.i64(i64) nounwind readnone
-; CHECK: dclz $2, $4
define i64 @f18(i64 %X) nounwind readnone {
entry:
+; CHECK: dclz $2, $4
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X)
ret i64 %tmp1
}
-; CHECK: dclo $2, $4
define i64 @f19(i64 %X) nounwind readnone {
entry:
+; CHECK: dclo $2, $4
%neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg)
ret i64 %tmp1
From isanbard at gmail.com Mon Oct 3 16:25:38 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 03 Oct 2011 21:25:38 -0000
Subject: [llvm-commits] [llvm] r141031 - in /llvm/trunk/lib/Target/ARM:
ARMISelLowering.cpp ARMISelLowering.h
Message-ID: <20111003212538.E1C222A6C12C@llvm.org>
Author: void
Date: Mon Oct 3 16:25:38 2011
New Revision: 141031
URL: http://llvm.org/viewvc/llvm-project?rev=141031&view=rev
Log:
Check-pointing the new SjLj EH lowering.
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=141031&r1=141030&r2=141031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Oct 3 16:25:38 2011
@@ -5482,6 +5482,80 @@
return BB;
}
+MachineBasicBlock *ARMTargetLowering::
+EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
+ const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+ DebugLoc dl = MI->getDebugLoc();
+ MachineFunction *MF = MBB->getParent();
+ MachineRegisterInfo *MRI = &MF->getRegInfo();
+ MachineConstantPool *MCP = MF->getConstantPool();
+ ARMFunctionInfo *AFI = MF->getInfo();
+ const Function *F = MF->getFunction();
+ MachineFrameInfo *MFI = MF->getFrameInfo();
+ MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
+ int FI = MFI->getFunctionContextIndex();
+ MachineBasicBlock *Last = &MF->back();
+ MF->insert(MF->end(), DispatchBB);
+ MF->RenumberBlocks(Last);
+
+ // Shove the dispatch's address into the return slot in the function context.
+ DispatchBB->setIsLandingPad();
+ MBB->addSuccessor(DispatchBB);
+
+ BuildMI(DispatchBB, dl, TII->get(ARM::TRAP));
+
+ bool isThumb = Subtarget->isThumb();
+ unsigned PCLabelId = AFI->createPICLabelUId();
+ unsigned PCAdj = isThumb ? 4 : 8;
+ ARMConstantPoolValue *CPV =
+ ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
+ unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
+
+ const TargetRegisterClass *TRC =
+ isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
+
+ MachineMemOperand *CPMMO =
+ MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
+ MachineMemOperand::MOLoad, 4, 4);
+
+ MachineMemOperand *FIMMO =
+ MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
+ MachineMemOperand::MOStore, 4, 4);
+
+ // Load the address of the dispatch MBB into the jump buffer.
+ if (isThumb) {
+ unsigned NewVReg = MRI->createVirtualRegister(TRC);
+ BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci_pic), NewVReg)
+ .addConstantPoolIndex(CPI)
+ .addImm(1)
+ .addMemOperand(CPMMO);
+ AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRspi))
+ .addReg(NewVReg, RegState::Kill)
+ .addFrameIndex(FI)
+ .addImm(36) // &jbuf[1] :: pc
+ .addMemOperand(FIMMO));
+ } else {
+ unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
+ AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
+ .addConstantPoolIndex(CPI)
+ .addImm(0)
+ .addMemOperand(CPMMO));
+ unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
+ AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
+ .addReg(NewVReg1, RegState::Kill)
+ .addImm(1));
+ AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
+ .addReg(NewVReg2, RegState::Kill)
+ .addFrameIndex(FI)
+ .addImm(36) // &jbuf[1] :: pc
+ .addMemOperand(FIMMO));
+ }
+
+ MI->eraseFromParent(); // The instruction is gone now.
+
+ return MBB;
+}
+
static
MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=141031&r1=141030&r2=141031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Oct 3 16:25:38 2011
@@ -512,6 +512,9 @@
bool signExtend,
ARMCC::CondCodes Cond) const;
+ MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
+ MachineBasicBlock *MBB) const;
+
bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
};
From nicholas at mxc.ca Mon Oct 3 16:30:08 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 03 Oct 2011 21:30:08 -0000
Subject: [llvm-commits] [llvm] r141032 - /llvm/trunk/lib/Support/APFloat.cpp
Message-ID: <20111003213008.B23272A6C12C@llvm.org>
Author: nicholas
Date: Mon Oct 3 16:30:08 2011
New Revision: 141032
URL: http://llvm.org/viewvc/llvm-project?rev=141032&view=rev
Log:
Fix typo in comments.
Modified:
llvm/trunk/lib/Support/APFloat.cpp
Modified: llvm/trunk/lib/Support/APFloat.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APFloat.cpp?rev=141032&r1=141031&r2=141032&view=diff
==============================================================================
--- llvm/trunk/lib/Support/APFloat.cpp (original)
+++ llvm/trunk/lib/Support/APFloat.cpp Mon Oct 3 16:30:08 2011
@@ -1192,7 +1192,7 @@
if (omsb) {
/* OMSB is numbered from 1. We want to place it in the integer
- bit numbered PRECISON if possible, with a compensating change in
+ bit numbered PRECISION if possible, with a compensating change in
the exponent. */
exponentChange = omsb - semantics->precision;
@@ -2125,7 +2125,7 @@
dstCount = partCount();
precision = semantics->precision;
- /* We want the most significant PRECISON bits of SRC. There may not
+ /* We want the most significant PRECISION bits of SRC. There may not
be that many; extract what we can. */
if (precision <= omsb) {
exponent = omsb - 1;
From evan.cheng at apple.com Mon Oct 3 17:19:05 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 03 Oct 2011 15:19:05 -0700
Subject: [llvm-commits] [llvm] r140863 - in /llvm/trunk:
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
test/CodeGen/ARM/fast-isel.ll test/CodeGen/ARM/hidden-vis-2.ll
test/CodeGen/ARM/hidden-vis-3.ll test/CodeGen/ARM/tail-opts.ll
test/CodeGen/Thumb2/machine-licm.ll
In-Reply-To: <20110930174137.A91E42A6C12C@llvm.org>
References: <20110930174137.A91E42A6C12C@llvm.org>
Message-ID:
Since you are making this change, can you fix x86_64 as well?
Evan
On Sep 30, 2011, at 10:41 AM, Jim Grosbach wrote:
> Author: grosbach
> Date: Fri Sep 30 12:41:35 2011
> New Revision: 140863
>
> URL: http://llvm.org/viewvc/llvm-project?rev=140863&view=rev
> Log:
> ARM Darwin default relocation model is PIC.
>
> This matches clang, so default options in llc and friends are now closer to
> clang's defaults.
>
> Modified:
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> llvm/trunk/test/CodeGen/ARM/fast-isel.ll
> llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll
> llvm/trunk/test/CodeGen/ARM/hidden-vis-3.ll
> llvm/trunk/test/CodeGen/ARM/tail-opts.ll
> llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=140863&r1=140862&r2=140863&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Fri Sep 30 12:41:35 2011
> @@ -139,8 +139,11 @@
> static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
> CodeModel::Model CM) {
> MCCodeGenInfo *X = new MCCodeGenInfo();
> - if (RM == Reloc::Default)
> - RM = Reloc::DynamicNoPIC;
> + if (RM == Reloc::Default) {
> + Triple TheTriple(TT);
> + // Default relocation model on Darwin is PIC, not DynamicNoPIC.
> + RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
> + }
> X->InitMCCodeGenInfo(RM, CM);
> return X;
> }
>
> Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=140863&r1=140862&r2=140863&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Fri Sep 30 12:41:35 2011
> @@ -1,5 +1,5 @@
> -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
> -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
> +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
> +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
>
> ; Very basic fast-isel functionality.
> define i32 @add(i32 %a, i32 %b) nounwind {
>
> Modified: llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll?rev=140863&r1=140862&r2=140863&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll Fri Sep 30 12:41:35 2011
> @@ -1,4 +1,4 @@
> -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
> +; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=arm-apple-darwin | FileCheck %s
>
> @x = weak hidden global i32 0 ; [#uses=1]
>
>
> Modified: llvm/trunk/test/CodeGen/ARM/hidden-vis-3.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hidden-vis-3.ll?rev=140863&r1=140862&r2=140863&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/hidden-vis-3.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/hidden-vis-3.ll Fri Sep 30 12:41:35 2011
> @@ -1,4 +1,4 @@
> -; RUN: llc < %s -mtriple=arm-apple-darwin9 | FileCheck %s
> +; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=arm-apple-darwin9 | FileCheck %s
>
> @x = external hidden global i32 ; [#uses=1]
> @y = extern_weak hidden global i32 ; [#uses=1]
>
> Modified: llvm/trunk/test/CodeGen/ARM/tail-opts.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/tail-opts.ll?rev=140863&r1=140862&r2=140863&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/tail-opts.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/tail-opts.ll Fri Sep 30 12:41:35 2011
> @@ -1,4 +1,4 @@
> -; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 -asm-verbose=false | FileCheck %s
> +; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic -mcpu=cortex-a8 -asm-verbose=false | FileCheck %s
>
> declare void @bar(i32)
> declare void @car(i32)
>
> Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=140863&r1=140862&r2=140863&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original)
> +++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Fri Sep 30 12:41:35 2011
> @@ -1,4 +1,4 @@
> -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-fp-elim | FileCheck %s
> +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=dynamic-no-pic -disable-fp-elim | FileCheck %s
> ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC
> ; rdar://7353541
> ; rdar://7354376
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
From evan.cheng at apple.com Mon Oct 3 17:25:30 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 03 Oct 2011 15:25:30 -0700
Subject: [llvm-commits] [patch] Add the returns_twice attribute
In-Reply-To: <4E84F46A.9070206@gmail.com>
References: <4E84F46A.9070206@gmail.com>
Message-ID: <6638C20A-2346-49A1-B604-45C0FE854CC4@apple.com>
See Function::callsFunctionThatReturnsTwice(). If you are adding this attribute, then should add the attribute to these special functions (e.g. setjmp)? Then callsFunctionThatReturnsTwice() can go away.
Evan
On Sep 29, 2011, at 3:42 PM, Rafael ?vila de Esp?ndola wrote:
> The attached patch reuses the hotpatch attribute (which Charles Davis
> says is unused) to create the returs_twice attribute. This will be used
> to implement the C attribute with the same name.
>
> It is needed by valgrind, since it has its own setjmp like function.
>
> See PR11038 for more information.
>
> Is it OK?
>
> Cheers,
> Rafael
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
From grosbach at apple.com Mon Oct 3 17:30:25 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 03 Oct 2011 22:30:25 -0000
Subject: [llvm-commits] [llvm] r141038 - in /llvm/trunk:
lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/simple-fp-encoding.s
Message-ID: <20111003223025.91C582A6C12C@llvm.org>
Author: grosbach
Date: Mon Oct 3 17:30:24 2011
New Revision: 141038
URL: http://llvm.org/viewvc/llvm-project?rev=141038&view=rev
Log:
ARM parsing/encoding for VCMP/VCMPE.
Modified:
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/simple-fp-encoding.s
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=141038&r1=141037&r2=141038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Oct 3 17:30:24 2011
@@ -3582,6 +3582,17 @@
delete Op;
}
}
+ // VCMP{E} does the same thing, but with a different operand count.
+ if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
+ static_cast(Operands[4])->isImm()) {
+ ARMOperand *Op = static_cast(Operands[4]);
+ const MCConstantExpr *CE = dyn_cast(Op->getImm());
+ if (CE && CE->getValue() == 0) {
+ Operands.erase(Operands.begin() + 4);
+ Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
+ delete Op;
+ }
+ }
// Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
// end. Convert it to a token here.
if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=141038&r1=141037&r2=141038&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Mon Oct 3 17:30:24 2011
@@ -36,11 +36,11 @@
@ CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
vcmpe.f32 s1, s0
-@ FIXME: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
-@ vcmpe.f64 d16, #0
+@ CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
+ vcmpe.f64 d16, #0
-@ FIXME: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
-@ vcmpe.f32 s0, #0
+@ CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
+ vcmpe.f32 s0, #0
@ CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee]
vabs.f64 d16, d16
From isanbard at gmail.com Mon Oct 3 17:42:40 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 03 Oct 2011 22:42:40 -0000
Subject: [llvm-commits] [llvm] r141040 -
/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
Message-ID: <20111003224240.B4E062A6C12C@llvm.org>
Author: void
Date: Mon Oct 3 17:42:40 2011
New Revision: 141040
URL: http://llvm.org/viewvc/llvm-project?rev=141040&view=rev
Log:
Don't carry over the dispatchsetup hack from the old system.
Modified:
llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=141040&r1=141039&r2=141040&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Mon Oct 3 17:42:40 2011
@@ -849,13 +849,7 @@
CastInst::Create(Instruction::BitCast, JBufPtr,
Type::getInt8PtrTy(F.getContext()), "",
EntryBB->getTerminator());
- Value *DispatchVal = CallInst::Create(BuiltinSetjmpFn, SetjmpArg,
- "dispatch",
- EntryBB->getTerminator());
-
- // Add a call to dispatch_setup after the setjmp call. This is expanded to any
- // target-specific setup that needs to be done.
- CallInst::Create(DispatchSetupFn, DispatchVal, "", EntryBB->getTerminator());
+ CallInst::Create(BuiltinSetjmpFn, SetjmpArg, "", EntryBB->getTerminator());
// Store a pointer to the function context so that the back-end will know
// where to look for it.
From isanbard at gmail.com Mon Oct 3 17:44:15 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 03 Oct 2011 22:44:15 -0000
Subject: [llvm-commits] [llvm] r141042 -
/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20111003224415.AC7442A6C12C@llvm.org>
Author: void
Date: Mon Oct 3 17:44:15 2011
New Revision: 141042
URL: http://llvm.org/viewvc/llvm-project?rev=141042&view=rev
Log:
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=141042&r1=141041&r2=141042&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Oct 3 17:44:15 2011
@@ -5505,8 +5505,9 @@
BuildMI(DispatchBB, dl, TII->get(ARM::TRAP));
bool isThumb = Subtarget->isThumb();
+ bool isThumb2 = Subtarget->isThumb2();
unsigned PCLabelId = AFI->createPICLabelUId();
- unsigned PCAdj = isThumb ? 4 : 8;
+ unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
ARMConstantPoolValue *CPV =
ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
@@ -5523,18 +5524,48 @@
MachineMemOperand::MOStore, 4, 4);
// Load the address of the dispatch MBB into the jump buffer.
- if (isThumb) {
- unsigned NewVReg = MRI->createVirtualRegister(TRC);
- BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci_pic), NewVReg)
- .addConstantPoolIndex(CPI)
- .addImm(1)
- .addMemOperand(CPMMO);
- AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRspi))
- .addReg(NewVReg, RegState::Kill)
+ if (isThumb2) {
+ unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
+ AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
+ .addConstantPoolIndex(CPI)
+ .addMemOperand(CPMMO));
+ unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
+ BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
+ .addReg(NewVReg1, RegState::Kill)
+ .addImm(PCLabelId);
+ AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
+ .addReg(NewVReg2, RegState::Kill)
.addFrameIndex(FI)
.addImm(36) // &jbuf[1] :: pc
.addMemOperand(FIMMO));
+ } else if (isThumb) {
+ // Incoming value: jbuf
+ // ldr.n r1, LCPI1_4
+ // add r1, pc
+ // add r2, sp, #48 ; &jbuf[1]
+ // str r1, [r2]
+ unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
+ AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
+ .addConstantPoolIndex(CPI)
+ .addMemOperand(CPMMO));
+ unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
+ BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
+ .addReg(NewVReg1)
+ .addImm(PCLabelId);
+ unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
+ AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg3)
+ .addFrameIndex(FI)
+ .addImm(36)); // &jbuf[1] :: pc
+ AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
+ .addReg(NewVReg2, RegState::Kill)
+ .addReg(NewVReg3, RegState::Kill)
+ .addImm(0)
+ .addMemOperand(FIMMO));
} else {
+ // Incoming value: jbuf
+ // ldr r1, LCPI1_1
+ // add r1, pc, r1
+ // str r1, [$jbuf, #+4] ; &jbuf[1]
unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
.addConstantPoolIndex(CPI)
@@ -5543,7 +5574,7 @@
unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
.addReg(NewVReg1, RegState::Kill)
- .addImm(1));
+ .addImm(PCLabelId));
AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
.addReg(NewVReg2, RegState::Kill)
.addFrameIndex(FI)
From grosbach at apple.com Mon Oct 3 17:48:13 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 03 Oct 2011 15:48:13 -0700
Subject: [llvm-commits] [llvm] r140863 - in /llvm/trunk:
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
test/CodeGen/ARM/fast-isel.ll test/CodeGen/ARM/hidden-vis-2.ll
test/CodeGen/ARM/hidden-vis-3.ll test/CodeGen/ARM/tail-opts.ll
test/CodeGen/Thumb2/machine-licm.ll
In-Reply-To:
References: <20110930174137.A91E42A6C12C@llvm.org>
Message-ID: <64B540EC-DBFF-4E2F-8798-F0329460766B@apple.com>
It looks like x86_64 is already supposed to default to PIC. Are you seeing examples where that's not working?
-Jim
On Oct 3, 2011, at 3:19 PM, Evan Cheng wrote:
> Since you are making this change, can you fix x86_64 as well?
>
> Evan
>
> On Sep 30, 2011, at 10:41 AM, Jim Grosbach wrote:
>
>> Author: grosbach
>> Date: Fri Sep 30 12:41:35 2011
>> New Revision: 140863
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=140863&view=rev
>> Log:
>> ARM Darwin default relocation model is PIC.
>>
>> This matches clang, so default options in llc and friends are now closer to
>> clang's defaults.
>>
>> Modified:
>> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
>> llvm/trunk/test/CodeGen/ARM/fast-isel.ll
>> llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll
>> llvm/trunk/test/CodeGen/ARM/hidden-vis-3.ll
>> llvm/trunk/test/CodeGen/ARM/tail-opts.ll
>> llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
>>
>> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=140863&r1=140862&r2=140863&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Fri Sep 30 12:41:35 2011
>> @@ -139,8 +139,11 @@
>> static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
>> CodeModel::Model CM) {
>> MCCodeGenInfo *X = new MCCodeGenInfo();
>> - if (RM == Reloc::Default)
>> - RM = Reloc::DynamicNoPIC;
>> + if (RM == Reloc::Default) {
>> + Triple TheTriple(TT);
>> + // Default relocation model on Darwin is PIC, not DynamicNoPIC.
>> + RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
>> + }
>> X->InitMCCodeGenInfo(RM, CM);
>> return X;
>> }
>>
>> Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=140863&r1=140862&r2=140863&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Fri Sep 30 12:41:35 2011
>> @@ -1,5 +1,5 @@
>> -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
>> -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
>> +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
>> +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
>>
>> ; Very basic fast-isel functionality.
>> define i32 @add(i32 %a, i32 %b) nounwind {
>>
>> Modified: llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll?rev=140863&r1=140862&r2=140863&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/hidden-vis-2.ll Fri Sep 30 12:41:35 2011
>> @@ -1,4 +1,4 @@
>> -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
>> +; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=arm-apple-darwin | FileCheck %s
>>
>> @x = weak hidden global i32 0 ; [#uses=1]
>>
>>
>> Modified: llvm/trunk/test/CodeGen/ARM/hidden-vis-3.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hidden-vis-3.ll?rev=140863&r1=140862&r2=140863&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/hidden-vis-3.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/hidden-vis-3.ll Fri Sep 30 12:41:35 2011
>> @@ -1,4 +1,4 @@
>> -; RUN: llc < %s -mtriple=arm-apple-darwin9 | FileCheck %s
>> +; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=arm-apple-darwin9 | FileCheck %s
>>
>> @x = external hidden global i32 ; [#uses=1]
>> @y = extern_weak hidden global i32 ; [#uses=1]
>>
>> Modified: llvm/trunk/test/CodeGen/ARM/tail-opts.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/tail-opts.ll?rev=140863&r1=140862&r2=140863&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/tail-opts.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/tail-opts.ll Fri Sep 30 12:41:35 2011
>> @@ -1,4 +1,4 @@
>> -; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 -asm-verbose=false | FileCheck %s
>> +; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic -mcpu=cortex-a8 -asm-verbose=false | FileCheck %s
>>
>> declare void @bar(i32)
>> declare void @car(i32)
>>
>> Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=140863&r1=140862&r2=140863&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original)
>> +++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Fri Sep 30 12:41:35 2011
>> @@ -1,4 +1,4 @@
>> -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-fp-elim | FileCheck %s
>> +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=dynamic-no-pic -disable-fp-elim | FileCheck %s
>> ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC
>> ; rdar://7353541
>> ; rdar://7354376
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
From atrick at apple.com Mon Oct 3 17:57:09 2011
From: atrick at apple.com (Andrew Trick)
Date: Mon, 03 Oct 2011 15:57:09 -0700
Subject: [llvm-commits] patch: chrec * chrec = chrec.
In-Reply-To: <4E88F8E3.3050506@mxc.ca>
References: <4E88F8E3.3050506@mxc.ca>
Message-ID:
On Oct 2, 2011, at 4:50 PM, Nick Lewycky wrote:
> This patch is a follow-up to r139133 which corrected SCEV's getMulExpr when given two chrec arguments. Here I extend it to correctly multiply chrecs of any length.
>
> The meat of this patch is a pure blob of illegible math. If you want to do a hard review, I would suggest:
> - trying to derive the formula I used in the comment to calculate the terms of the new chrec
> - proving to yourself a coefficient that doesn't fit can safely be truncated
>
> If you want to do an easier review, I would suggest running it over code. This will fire in 447.dealII for example.
>
> I know that other work is going on in the loop optimizer right now which I don't want to interfere with, so please let me know when wouldn't be a bad time to land this.
>
> Nick
>
Nick,
I don't have a problem with you landing this whenever you can. As long as I don't have to vouch for correctness of the math. More comments would help in this regard. Not being a math major, it wasn't obvious to me that you're computing binomial coefficients here.
The reference to a benchmark is quite helpful, and the unit tests give me a good feeling. I'm aware of the problem with verifying SCEV equivalence. I would love to an equivalence checker that can run in assert mode, but it's pretty low on my todo list now.
-Andy
From grosbach at apple.com Mon Oct 3 18:03:27 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 03 Oct 2011 23:03:27 -0000
Subject: [llvm-commits] [llvm] r141043 -
/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
Message-ID: <20111003230328.1768A2A6C12C@llvm.org>
Author: grosbach
Date: Mon Oct 3 18:03:26 2011
New Revision: 141043
URL: http://llvm.org/viewvc/llvm-project?rev=141043&view=rev
Log:
Tidy up. 80 columns.
Modified:
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h?rev=141043&r1=141042&r2=141043&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h Mon Oct 3 18:03:26 2011
@@ -637,7 +637,7 @@
/// floating-point value, then return -1.
static inline int getFP64Imm(const APInt &Imm) {
uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
- int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
+ int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
// We can handle 4 bits of mantissa.
From joerg at britannica.bec.de Mon Oct 3 18:27:26 2011
From: joerg at britannica.bec.de (Joerg Sonnenberger)
Date: Tue, 4 Oct 2011 01:27:26 +0200
Subject: [llvm-commits] patch: chrec * chrec = chrec.
In-Reply-To:
References: <4E88F8E3.3050506@mxc.ca>
<20111003205157.GA10434@britannica.bec.de>
Message-ID: <20111003232726.GA13292@britannica.bec.de>
On Mon, Oct 03, 2011 at 02:10:45PM -0700, Nick Lewycky wrote:
> On 3 October 2011 13:51, Joerg Sonnenberger wrote:
> > What exactly is the desired behavior in case of overflow?
> > E.g. do you want to get C(n,k) % (UINTMAX + 1)? In that case, your
> > formula doesn't compute correct results.
> >
>
> In overflow the return value is garbage and Overflow is set. This method
> deserves a comment.
>From IRC: since n is supposed to be small, it might be better to just
check for n <= 34 and consider it as overflow otherwise. Essentially,
that's the largest number for which C(2n,n) < 2**32. In theory, it would
be possible to compute C(n,k) in the finite field by eliminating the
factors 2 in the divisor and implementing the division using the
multiplicative inverse at the end. That's quite a bit more work though.
Joerg
From grosbach at apple.com Mon Oct 3 18:38:41 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 03 Oct 2011 23:38:41 -0000
Subject: [llvm-commits] [llvm] r141046 - in /llvm/trunk:
lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
test/MC/ARM/simple-fp-encoding.s
Message-ID: <20111003233841.929B42A6C12C@llvm.org>
Author: grosbach
Date: Mon Oct 3 18:38:36 2011
New Revision: 141046
URL: http://llvm.org/viewvc/llvm-project?rev=141046&view=rev
Log:
ARM assembly parsing and encoding for VMOV immediate.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/simple-fp-encoding.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=141046&r1=141045&r2=141046&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Oct 3 18:38:36 2011
@@ -31,6 +31,12 @@
// Operand Definitions.
//
+// 8-bit floating-point immediate encodings.
+def FPImmOperand : AsmOperandClass {
+ let Name = "FPImm";
+ let ParserMethod = "parseFPImm";
+}
+
def vfp_f32imm : Operand,
PatLeaf<(f32 fpimm), [{
return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
@@ -40,6 +46,7 @@
return CurDAG->getTargetConstant(enc, MVT::i32);
}]>> {
let PrintMethod = "printFPImmOperand";
+ let ParserMatchClass = FPImmOperand;
}
def vfp_f64imm : Operand,
@@ -51,6 +58,7 @@
return CurDAG->getTargetConstant(enc, MVT::i32);
}]>> {
let PrintMethod = "printFPImmOperand";
+ let ParserMatchClass = FPImmOperand;
}
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=141046&r1=141045&r2=141046&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Oct 3 18:38:36 2011
@@ -158,6 +158,7 @@
OperandMatchResultTy parseBitfield(SmallVectorImpl&);
OperandMatchResultTy parsePostIdxReg(SmallVectorImpl&);
OperandMatchResultTy parseAM3Offset(SmallVectorImpl&);
+ OperandMatchResultTy parseFPImm(SmallVectorImpl&);
// Asm Match Converter Methods
bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
@@ -247,6 +248,7 @@
CoprocNum,
CoprocReg,
Immediate,
+ FPImmediate,
MemBarrierOpt,
Memory,
PostIndexRegister,
@@ -305,6 +307,10 @@
const MCExpr *Val;
} Imm;
+ struct {
+ unsigned Val; // encoded 8-bit representation
+ } FPImm;
+
/// Combined record for all forms of ARM address expressions.
struct {
unsigned BaseRegNum;
@@ -380,6 +386,9 @@
case Immediate:
Imm = o.Imm;
break;
+ case FPImmediate:
+ FPImm = o.FPImm;
+ break;
case MemBarrierOpt:
MBOpt = o.MBOpt;
break;
@@ -449,6 +458,11 @@
return Imm.Val;
}
+ unsigned getFPImm() const {
+ assert(Kind == FPImmediate && "Invalid access!");
+ return FPImm.Val;
+ }
+
ARM_MB::MemBOpt getMemBarrierOpt() const {
assert(Kind == MemBarrierOpt && "Invalid access!");
return MBOpt.Val;
@@ -471,6 +485,7 @@
bool isITMask() const { return Kind == ITCondMask; }
bool isITCondCode() const { return Kind == CondCode; }
bool isImm() const { return Kind == Immediate; }
+ bool isFPImm() const { return Kind == FPImmediate; }
bool isImm8s4() const {
if (Kind != Immediate)
return false;
@@ -952,6 +967,11 @@
addExpr(Inst, getImm());
}
+ void addFPImmOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::CreateImm(getFPImm()));
+ }
+
void addImm8s4Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// FIXME: We really want to scale the value here, but the LDRD/STRD
@@ -1467,6 +1487,14 @@
return Op;
}
+ static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
+ ARMOperand *Op = new ARMOperand(FPImmediate);
+ Op->FPImm.Val = Val;
+ Op->StartLoc = S;
+ Op->EndLoc = S;
+ return Op;
+ }
+
static ARMOperand *CreateMem(unsigned BaseRegNum,
const MCConstantExpr *OffsetImm,
unsigned OffsetRegNum,
@@ -1529,6 +1557,10 @@
void ARMOperand::print(raw_ostream &OS) const {
switch (Kind) {
+ case FPImmediate:
+ OS << "";
+ break;
case CondCode:
OS << "";
break;
@@ -3024,6 +3056,50 @@
return false;
}
+/// parseFPImm - A floating point immediate expression operand.
+ARMAsmParser::OperandMatchResultTy ARMAsmParser::
+parseFPImm(SmallVectorImpl &Operands) {
+ SMLoc S = Parser.getTok().getLoc();
+
+ if (Parser.getTok().isNot(AsmToken::Hash))
+ return MatchOperand_NoMatch;
+ Parser.Lex(); // Eat the '#'.
+
+ // Handle negation, as that still comes through as a separate token.
+ bool isNegative = false;
+ if (Parser.getTok().is(AsmToken::Minus)) {
+ isNegative = true;
+ Parser.Lex();
+ }
+ const AsmToken &Tok = Parser.getTok();
+ if (Tok.is(AsmToken::Real)) {
+ APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
+ uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
+ // If we had a '-' in front, toggle the sign bit.
+ IntVal ^= (uint64_t)isNegative << 63;
+ int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
+ Parser.Lex(); // Eat the token.
+ if (Val == -1) {
+ TokError("floating point value out of range");
+ return MatchOperand_ParseFail;
+ }
+ Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
+ return MatchOperand_Success;
+ }
+ if (Tok.is(AsmToken::Integer)) {
+ int64_t Val = Tok.getIntVal();
+ Parser.Lex(); // Eat the token.
+ if (Val > 255 || Val < 0) {
+ TokError("encoded floating point value out of range");
+ return MatchOperand_ParseFail;
+ }
+ Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
+ return MatchOperand_Success;
+ }
+
+ TokError("invalid floating point immediate");
+ return MatchOperand_ParseFail;
+}
/// Parse a arm instruction operand. For now this parses the operand regardless
/// of the mnemonic.
bool ARMAsmParser::parseOperand(SmallVectorImpl &Operands,
Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=141046&r1=141045&r2=141046&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Mon Oct 3 18:38:36 2011
@@ -141,11 +141,15 @@
@ CHECK: vmsr fpsid, r0 @ encoding: [0x10,0x0a,0xe0,0xee]
vmsr fpsid, r0
-@ FIXME: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee]
-@ vmov.f64 d16, #3.000000e+00
-
-@ FIXME: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee]
-@ vmov.f32 s0, #3.000000e+00
+ vmov.f64 d16, #3.000000e+00
+ vmov.f32 s0, #3.000000e+00
+ vmov.f64 d16, #-3.000000e+00
+ vmov.f32 s0, #-3.000000e+00
+
+@ CHECK: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee]
+@ CHECK: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee]
+@ CHECK: vmov.f64 d16, #-3.000000e+00 @ encoding: [0x08,0x0b,0xf8,0xee]
+@ CHECK: vmov.f32 s0, #-3.000000e+00 @ encoding: [0x08,0x0a,0xb8,0xee]
@ CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee]
@ CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee]
From grosbach at apple.com Mon Oct 3 18:40:13 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 03 Oct 2011 23:40:13 -0000
Subject: [llvm-commits] [llvm] r141047 -
/llvm/trunk/test/MC/ARM/simple-encoding.ll
Message-ID: <20111003234013.7FD5D2A6C12C@llvm.org>
Author: grosbach
Date: Mon Oct 3 18:40:13 2011
New Revision: 141047
URL: http://llvm.org/viewvc/llvm-project?rev=141047&view=rev
Log:
Tidy up. These tests are covered in the .s file tests now.
Removed:
llvm/trunk/test/MC/ARM/simple-encoding.ll
Removed: llvm/trunk/test/MC/ARM/simple-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-encoding.ll?rev=141046&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/simple-encoding.ll (removed)
@@ -1,236 +0,0 @@
-;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding -disable-cgp-branch-opts -join-physregs < %s | FileCheck %s
-
-
-;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
-; should run on .s source files rather than using llc to generate the
-; assembly. There's also a large number of instruction encodings the
-; compiler never generates, so we need the integrated assembler to be
-; able to test those at all.
-
-declare void @llvm.trap() nounwind
-declare i32 @llvm.ctlz.i32(i32)
-
-define i32 @foo(i32 %a, i32 %b) {
-; CHECK: foo
-; CHECK: trap @ encoding: [0xfe,0xde,0xff,0xe7]
-; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
-
- tail call void @llvm.trap()
- ret i32 undef
-}
-
-define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2
-; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0]
-; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
- %add = add nsw i32 %b, %a
- ret i32 %add
-}
-
-
-define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3
-; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0]
-; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
- %mul = shl i32 %b, 3
- %add = add nsw i32 %mul, %a
- ret i32 %add
-}
-
-define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4
-; CHECK: add r0, r0, #4064 @ encoding: [0xfe,0x0e,0x80,0xe2]
-; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
- %add = add nsw i32 %a, 4064
- ret i32 %add
-}
-
-define i32 @f5(i32 %a, i32 %b, i32 %c) {
-; CHECK: f5
-; CHECK: cmp r0, r1 @ encoding: [0x01,0x00,0x50,0xe1]
-; CHECK: mov r0, r2 @ encoding: [0x02,0x00,0xa0,0xe1]
-; CHECK: movgt r0, r1 @ encoding: [0x01,0x00,0xa0,0xc1]
- %cmp = icmp sgt i32 %a, %b
- %retval.0 = select i1 %cmp, i32 %b, i32 %c
- ret i32 %retval.0
-}
-
-define i64 @f6(i64 %a, i64 %b, i64 %c) {
-; CHECK: f6
-; CHECK: adds r0, r2, r0 @ encoding: [0x00,0x00,0x92,0xe0]
-; CHECK: adc r1, r3, r1 @ encoding: [0x01,0x10,0xa3,0xe0]
- %add = add nsw i64 %b, %a
- ret i64 %add
-}
-
-define i32 @f7(i32 %a, i32 %b) {
-; CHECK: f7
-; CHECK: uxtab r0, r0, r1 @ encoding: [0x71,0x00,0xe0,0xe6]
- %and = and i32 %b, 255
- %add = add i32 %and, %a
- ret i32 %add
-}
-
-define i32 @f8(i32 %a) {
-; CHECK: f8
-; CHECK: movt r0, #42405 @ encoding: [0xa5,0x05,0x4a,0xe3]
- %and = and i32 %a, 65535
- %or = or i32 %and, -1515913216
- ret i32 %or
-}
-
-define i32 @f9() {
-; CHECK: f9
-; CHECK: movw r0, #42405 @ encoding: [0xa5,0x05,0x0a,0xe3]
- ret i32 42405
-}
-
-define i64 @f10(i64 %a) {
-; CHECK: f10
-; CHECK: asrs r1, r1, #1 @ encoding: [0xc1,0x10,0xb0,0xe1]
-; CHECK: rrx r0, r0 @ encoding: [0x60,0x00,0xa0,0xe1]
- %shr = ashr i64 %a, 1
- ret i64 %shr
-}
-
-define i32 @f11([1 x i32] %A.coerce0, [1 x i32] %B.coerce0) {
-; CHECK: f11
-; CHECK: ubfx r1, r1, #8, #5 @ encoding: [0x51,0x14,0xe4,0xe7]
-; CHECK: sbfx r0, r0, #13, #7 @ encoding: [0xd0,0x06,0xa6,0xe7]
- %tmp1 = extractvalue [1 x i32] %A.coerce0, 0
- %tmp2 = extractvalue [1 x i32] %B.coerce0, 0
- %tmp3 = shl i32 %tmp1, 12
- %bf.val.sext = ashr i32 %tmp3, 25
- %tmp4 = lshr i32 %tmp2, 8
- %bf.clear2 = and i32 %tmp4, 31
- %mul = mul nsw i32 %bf.val.sext, %bf.clear2
- ret i32 %mul
-}
-
-define i32 @f12(i32 %a) {
-; CHECK: f12:
-; CHECK: bfc r0, #4, #20 @ encoding: [0x1f,0x02,0xd7,0xe7]
- %tmp = and i32 %a, 4278190095
- ret i32 %tmp
-}
-
-define i64 @f13() {
-; CHECK: f13:
-; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3]
-; CHECK: mvn r1, #-2147483648 @ encoding: [0x02,0x11,0xe0,0xe3]
- ret i64 9223372036854775807
-}
-
-define i32 @f14(i32 %x, i32 %y) {
-; CHECK: f14:
-; CHECK: smmul r0, r1, r0 @ encoding: [0x11,0xf0,0x50,0xe7]
- %tmp = sext i32 %x to i64
- %tmp1 = sext i32 %y to i64
- %tmp2 = mul i64 %tmp1, %tmp
- %tmp3 = lshr i64 %tmp2, 32
- %tmp3.upgrd.1 = trunc i64 %tmp3 to i32
- ret i32 %tmp3.upgrd.1
-}
-
-define i32 @f15(i32 %x, i32 %y) {
-; CHECK: f15:
-; CHECK: umull r1, r0, r1, r0 @ encoding: [0x91,0x10,0x80,0xe0]
- %tmp = zext i32 %x to i64
- %tmp1 = zext i32 %y to i64
- %tmp2 = mul i64 %tmp1, %tmp
- %tmp3 = lshr i64 %tmp2, 32
- %tmp3.upgrd.2 = trunc i64 %tmp3 to i32
- ret i32 %tmp3.upgrd.2
-}
-
-define i32 @f16(i16 %x, i32 %y) {
-; CHECK: f16:
-; CHECK: smulbt r0, r0, r1 @ encoding: [0xc0,0x01,0x60,0xe1]
- %tmp1 = add i16 %x, 2
- %tmp2 = sext i16 %tmp1 to i32
- %tmp3 = ashr i32 %y, 16
- %tmp4 = mul i32 %tmp2, %tmp3
- ret i32 %tmp4
-}
-
-define i32 @f17(i32 %x, i32 %y) {
-; CHECK: f17:
-; CHECK: smultt r0, r1, r0 @ encoding: [0xe1,0x00,0x60,0xe1]
- %tmp1 = ashr i32 %x, 16
- %tmp3 = ashr i32 %y, 16
- %tmp4 = mul i32 %tmp3, %tmp1
- ret i32 %tmp4
-}
-
-define i32 @f18(i32 %a, i16 %x, i32 %y) {
-; CHECK: f18:
-; CHECK: smlabt r0, r1, r2, r0 @ encoding: [0xc1,0x02,0x00,0xe1]
- %tmp = sext i16 %x to i32
- %tmp2 = ashr i32 %y, 16
- %tmp3 = mul i32 %tmp2, %tmp
- %tmp5 = add i32 %tmp3, %a
- ret i32 %tmp5
-}
-
-define i32 @f19(i32 %x) {
-; CHECK: f19
-; CHECK: clz r0, r0 @ encoding: [0x10,0x0f,0x6f,0xe1]
- %tmp.1 = call i32 @llvm.ctlz.i32( i32 %x )
- ret i32 %tmp.1
-}
-
-define i32 @f20(i32 %X) {
-; CHECK: f20
-; CHECK: rev16 r0, r0 @ encoding: [0xb0,0x0f,0xbf,0xe6]
- %tmp1 = lshr i32 %X, 8
- %X15 = bitcast i32 %X to i32
- %tmp4 = shl i32 %X15, 8
- %tmp2 = and i32 %tmp1, 16711680
- %tmp5 = and i32 %tmp4, -16777216
- %tmp9 = and i32 %tmp1, 255
- %tmp13 = and i32 %tmp4, 65280
- %tmp6 = or i32 %tmp5, %tmp2
- %tmp10 = or i32 %tmp6, %tmp13
- %tmp14 = or i32 %tmp10, %tmp9
- ret i32 %tmp14
-}
-
-define i32 @f21(i32 %X) {
-; CHECK: f21
-; CHECK: revsh r0, r0 @ encoding: [0xb0,0x0f,0xff,0xe6]
- %tmp1 = lshr i32 %X, 8
- %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
- %tmp3 = trunc i32 %X to i16
- %tmp2 = and i16 %tmp1.upgrd.1, 255
- %tmp4 = shl i16 %tmp3, 8
- %tmp5 = or i16 %tmp2, %tmp4
- %tmp5.upgrd.2 = sext i16 %tmp5 to i32
- ret i32 %tmp5.upgrd.2
-}
-
-define i32 @f22(i32 %X, i32 %Y) {
-; CHECK: f22
-; CHECK: pkhtb r0, r0, r1, asr #22 @ encoding: [0x51,0x0b,0x80,0xe6]
- %tmp1 = and i32 %X, -65536
- %tmp2 = lshr i32 %Y, 22
- %tmp3 = or i32 %tmp2, %tmp1
- ret i32 %tmp3
-}
-
-define i32 @f23(i32 %X, i32 %Y) {
-; CHECK: f23
-; CHECK: pkhbt r0, r0, r1, lsl #18 @ encoding: [0x11,0x09,0x80,0xe6]
- %tmp1 = and i32 %X, 65535
- %tmp2 = shl i32 %Y, 18
- %tmp3 = or i32 %tmp1, %tmp2
- ret i32 %tmp3
-}
-
-define void @f24(i32 %a) {
-; CHECK: f24
-; CHECK: cmp r0, #65536 @ encoding: [0x01,0x08,0x50,0xe3]
- %b = icmp ugt i32 %a, 65536
- br i1 %b, label %r, label %r
-r:
- ret void
-}
From peter at pcc.me.uk Mon Oct 3 18:48:49 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Tue, 4 Oct 2011 00:48:49 +0100
Subject: [llvm-commits] [llvm] r140951 - in /llvm/trunk: ./
include/llvm/TableGen/ lib/ lib/TableGen/ utils/TableGen/
In-Reply-To:
References: <20111001164115.E37E82A6C12C@llvm.org>
Message-ID: <20111003234849.GA27357@pcc.me.uk>
Hi Chris,
> What direction are you going here?
My intention is to move the Clang tblgen backends into the Clang
source tree by building the tblgen parser out into a library that
can be used to create tblgen-like tools, and creating LLVM and Clang
utilities which contain their respective backends and which are clients
of that library. I'm trying to achieve this incrementally, by first
creating a TableGen library containing the parser and most of 'main'.
Currently tblgen is the only client, but I hope to replace this with
llvm-tblgen and clang-tblgen utilities.
> Are you committed to fixing these problems as follow-ons?
To address these issues:
> 1. All of the 'main' code and the top-level cl::opt's should be in utils/tablegen, not in TableGen/Main.h
Since llvm-tblgen and clang-tblgen would share most of the
implementation of their 'main' functions, I think it makes sense to
also put most of that code in the library. The TableGenAction class
allows for tools to provide the relevant part of 'main' that calls
out to their backends.
I have noticed that this change is causing problems for shared library
users [1], and I apologise for not anticipating this. I think that as
a single-purpose library, TableGen does not belong in the shared library,
so the most logical way to resolve this problem is to exclude it from
the shared library.
> 2. The tablegen headers (like the rest of it :) are a mess, they are not split properly between public and private headers.
I think that to begin with, the TableGen public interface should
provide the bare minimum to allow clients to write their own
tblgen-like tools. To this end, the public interface consists of
the backend base class, the TableGenAction base class, the Record
data structure definitions and the 'TableGenMain' function. I believe
that I've largely achieved this split with the current set of header
files in include/llvm/TableGen.
> 3. The tblgen code uses RTTI and EH, which none of the rest of the LLVM libraries do.
>
> So long as RTTI and EH don't invade tools other than the utils/TableGen executable, I'm ok with continuing to forget about #3, but #1 and #2 are pretty important.
I'm not addressing this problem. The TableGen library and its clients
will be built with RTTI and EH.
Thanks,
--
Peter
[1] http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-October/043687.html
From bigcheesegs at gmail.com Mon Oct 3 19:02:38 2011
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Mon, 3 Oct 2011 17:02:38 -0700
Subject: [llvm-commits] [llvm] r139314 - in /llvm/trunk:
include/llvm/Object/COFF.h include/llvm/Object/ObjectFile.h
lib/Object/COFFObjectFile.cpp lib/Object/ELFObjectFile.cpp
lib/Object/MachOObjectFile.cpp
In-Reply-To: <20110908205217.935612A6C12C@llvm.org>
References: <20110908205217.935612A6C12C@llvm.org>
Message-ID:
On Thu, Sep 8, 2011 at 1:52 PM, Benjamin Kramer
wrote:
> Author: d0k
> Date: Thu Sep ?8 15:52:17 2011
> New Revision: 139314
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139314&view=rev
> Log:
> Add support for relocations to ObjectFile.
>
> Patch by Danil Malyshev!
>
> Modified:
> ? ?llvm/trunk/include/llvm/Object/COFF.h
> ? ?llvm/trunk/include/llvm/Object/ObjectFile.h
> ? ?llvm/trunk/lib/Object/COFFObjectFile.cpp
> ? ?llvm/trunk/lib/Object/ELFObjectFile.cpp
> ? ?llvm/trunk/lib/Object/MachOObjectFile.cpp
>
> Modified: llvm/trunk/include/llvm/Object/COFF.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=139314&r1=139313&r2=139314&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Object/COFF.h (original)
> +++ llvm/trunk/include/llvm/Object/COFF.h Thu Sep ?8 15:52:17 2011
> @@ -67,6 +67,12 @@
> ? support::ulittle32_t Characteristics;
> ?};
>
> +struct coff_relocation {
> + ?support::ulittle32_t VirtualAddress;
> + ?support::ulittle32_t SymbolTableIndex;
> + ?support::ulittle16_t Type;
> +};
> +
> ?class COFFObjectFile : public ObjectFile {
> ?private:
> ? const coff_file_header *Header;
> @@ -81,6 +87,7 @@
>
> ? const coff_symbol ? ? ?*toSymb(DataRefImpl Symb) const;
> ? const coff_section ? ? *toSec(DataRefImpl Sec) const;
> + ?const coff_relocation ?*toRel(DataRefImpl Rel) const;
>
> ?protected:
> ? virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
> @@ -99,12 +106,24 @@
> ? virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Symb,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool &Result) const;
>
> + ?virtual error_code getRelocationNext(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? RelocationRef &Res) const;
> + ?virtual error_code getRelocationAddress(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t &Res) const;
> + ?virtual error_code getRelocationSymbol(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SymbolRef &Res) const;
> + ?virtual error_code getRelocationType(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint32_t &Res) const;
> + ?virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int64_t &Res) const;
> ?public:
> ? COFFObjectFile(MemoryBuffer *Object, error_code &ec);
> ? virtual symbol_iterator begin_symbols() const;
> ? virtual symbol_iterator end_symbols() const;
> ? virtual section_iterator begin_sections() const;
> ? virtual section_iterator end_sections() const;
> + ?virtual relocation_iterator begin_relocations() const;
> + ?virtual relocation_iterator end_relocations() const;
>
> ? virtual uint8_t getBytesInAddress() const;
> ? virtual StringRef getFileFormatName() const;
>
> Modified: llvm/trunk/include/llvm/Object/ObjectFile.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=139314&r1=139313&r2=139314&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Object/ObjectFile.h (original)
> +++ llvm/trunk/include/llvm/Object/ObjectFile.h Thu Sep ?8 15:52:17 2011
> @@ -39,22 +39,6 @@
> ? return std::memcmp(&a, &b, sizeof(DataRefImpl)) == 0;
> ?}
>
> -class RelocationRef {
> - ?DataRefImpl RelocationPimpl;
> - ?const ObjectFile *OwningObject;
> -
> -public:
> - ?RelocationRef() : OwningObject(NULL) {
> - ? ?std::memset(&RelocationPimpl, 0, sizeof(RelocationPimpl));
> - ?}
> -
> - ?RelocationRef(DataRefImpl RelocationP, const ObjectFile *Owner);
> -
> - ?bool operator==(const RelocationRef &Other) const;
> -
> - ?error_code getNext(RelocationRef &Result);
> -};
> -
> ?/// SymbolRef - This is a value type class that represents a single symbol in
> ?/// the list of symbols in the object file.
> ?class SymbolRef {
> @@ -86,6 +70,29 @@
> ? error_code isInternal(bool &Result) const;
> ?};
>
> +/// RelocationRef - This is a value type class that represents a single
> +/// relocation in the list of relocations in the object file.
> +class RelocationRef {
> + ?DataRefImpl RelocationPimpl;
> + ?const ObjectFile *OwningObject;
> +
> +public:
> + ?RelocationRef() : OwningObject(NULL) {
> + ? ?std::memset(&RelocationPimpl, 0, sizeof(RelocationPimpl));
> + ?}
> +
> + ?RelocationRef(DataRefImpl RelocationP, const ObjectFile *Owner);
> +
> + ?bool operator==(const RelocationRef &Other) const;
> +
> + ?error_code getNext(RelocationRef &Result) const;
> +
> + ?error_code getAddress(uint64_t &Result) const;
> + ?error_code getSymbol(SymbolRef &Result) const;
> + ?error_code getType(uint32_t &Result) const;
> + ?error_code getAdditionalInfo(int64_t &Result) const;
> +};
> +
> ?/// SectionRef - This is a value type class that represents a single section in
> ?/// the list of sections in the object file.
> ?class SectionRef {
> @@ -160,6 +167,19 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool &Result) const = 0;
>
>
> + ?// Same as above for RelocationRef.
> + ?friend class RelocationRef;
> + ?virtual error_code getRelocationNext(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? RelocationRef &Res) const = 0;
> + ?virtual error_code getRelocationAddress(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t &Res) const =0;
> + ?virtual error_code getRelocationSymbol(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SymbolRef &Res) const = 0;
> + ?virtual error_code getRelocationType(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint32_t &Res) const = 0;
> + ?virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int64_t &Res) const = 0;
> +
> ?public:
> ? template
> ? class content_iterator {
> @@ -196,6 +216,7 @@
>
> ? typedef content_iterator symbol_iterator;
> ? typedef content_iterator section_iterator;
> + ?typedef content_iterator relocation_iterator;
>
> ? virtual symbol_iterator begin_symbols() const = 0;
> ? virtual symbol_iterator end_symbols() const = 0;
> @@ -203,6 +224,9 @@
> ? virtual section_iterator begin_sections() const = 0;
> ? virtual section_iterator end_sections() const = 0;
>
> + ?virtual relocation_iterator begin_relocations() const = 0;
> + ?virtual relocation_iterator end_relocations() const = 0;
> +
> ? /// @brief The number of bytes used to represent an address in this object
> ? /// ? ? ? ?file format.
> ? virtual uint8_t getBytesInAddress() const = 0;
> @@ -302,6 +326,37 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Result);
> ?}
>
> +
> +/// RelocationRef
> +inline RelocationRef::RelocationRef(DataRefImpl RelocationP,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const ObjectFile *Owner)
> + ?: RelocationPimpl(RelocationP)
> + ?, OwningObject(Owner) {}
> +
> +inline bool RelocationRef::operator==(const RelocationRef &Other) const {
> + ?return RelocationPimpl == Other.RelocationPimpl;
> +}
> +
> +inline error_code RelocationRef::getNext(RelocationRef &Result) const {
> + ?return OwningObject->getRelocationNext(RelocationPimpl, Result);
> +}
> +
> +inline error_code RelocationRef::getAddress(uint64_t &Result) const {
> + ?return OwningObject->getRelocationAddress(RelocationPimpl, Result);
> +}
> +
> +inline error_code RelocationRef::getSymbol(SymbolRef &Result) const {
> + ?return OwningObject->getRelocationSymbol(RelocationPimpl, Result);
> +}
> +
> +inline error_code RelocationRef::getType(uint32_t &Result) const {
> + ?return OwningObject->getRelocationType(RelocationPimpl, Result);
> +}
> +
> +inline error_code RelocationRef::getAdditionalInfo(int64_t &Result) const {
> + ?return OwningObject->getRelocationAdditionalInfo(RelocationPimpl, Result);
> +}
> +
> ?} // end namespace object
> ?} // end namespace llvm
>
>
> Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=139314&r1=139313&r2=139314&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original)
> +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Thu Sep ?8 15:52:17 2011
> @@ -327,7 +327,7 @@
> ? Header = reinterpret_cast(base() + HeaderStart);
> ? if (!checkAddr(Data, ec, uintptr_t(Header), sizeof(coff_file_header)))
> ? ? return;
> -
> +
> ? SectionTable =
> ? ? reinterpret_cast( base()
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + HeaderStart
> @@ -360,7 +360,7 @@
> ? ? ec = object_error::parse_failed;
> ? ? return;
> ? }
> -
> +
> ? ec = object_error::success;
> ?}
>
> @@ -445,6 +445,77 @@
> ? return object_error::success;
> ?}
>
> +const coff_relocation *COFFObjectFile::toRel(DataRefImpl Rel) const {
> + ?assert(Rel.d.b < Header->NumberOfSections && "Section index out of range!");
> + ?const coff_section *Sect;
> + ?getSection(Rel.d.b, Sect);
> + ?assert(Rel.d.a < Sect->NumberOfRelocations && "Relocation index out of range!");
> + ?return
> + ? ?reinterpret_cast(base() +
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Sect->PointerToRelocations) +
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Rel.d.a;
> +}
> +error_code COFFObjectFile::getRelocationNext(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? RelocationRef &Res) const {
> + ?const coff_section *Sect = NULL;
> + ?if (error_code ec = getSection(Rel.d.b, Sect))
> + ? ?return ec;
> + ?if (++Rel.d.a >= Sect->NumberOfRelocations) {
> + ? ?Rel.d.a = 0;
> + ? ?while (++Rel.d.b < Header->NumberOfSections) {
> + ? ? ?const coff_section *Sect;
> + ? ? ?getSection(Rel.d.b, Sect);
> + ? ? ?if (Sect->NumberOfRelocations > 0)
> + ? ? ? ?break;
> + ? ?}
> + ?}
> + ?Res = RelocationRef(Rel, this);
> + ?return object_error::success;
> +}
> +error_code COFFObjectFile::getRelocationAddress(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t &Res) const {
> + ?const coff_section *Sect;
> + ?if (error_code ec = getSection(Rel.d.b, Sect))
> + ? ?return ec;
> + ?const coff_relocation* R = toRel(Rel);
> + ?Res = reinterpret_cast(base() +
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Sect->PointerToRawData +
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?R->VirtualAddress);
> + ?return object_error::success;
> +}
> +error_code COFFObjectFile::getRelocationSymbol(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SymbolRef &Res) const {
> + ?const coff_relocation* R = toRel(Rel);
> + ?DataRefImpl Symb;
> + ?Symb.p = reinterpret_cast(SymbolTable + R->SymbolTableIndex);
> + ?Res = SymbolRef(Symb, this);
> + ?return object_error::success;
> +}
> +error_code COFFObjectFile::getRelocationType(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint32_t &Res) const {
> + ?const coff_relocation* R = toRel(Rel);
> + ?Res = R->Type;
> + ?return object_error::success;
> +}
> +error_code COFFObjectFile::getRelocationAdditionalInfo(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int64_t &Res) const {
> + ?Res = 0;
> + ?return object_error::success;
> +}
> +ObjectFile::relocation_iterator COFFObjectFile::begin_relocations() const {
> + ?DataRefImpl ret;
> + ?ret.d.a = 0;
> + ?ret.d.b = 1;
> + ?return relocation_iterator(RelocationRef(ret, this));
> +}
> +ObjectFile::relocation_iterator COFFObjectFile::end_relocations() const {
> + ?DataRefImpl ret;
> + ?ret.d.a = 0;
> + ?ret.d.b = Header->NumberOfSections;
> + ?return relocation_iterator(RelocationRef(ret, this));
> +}
> +
> +
> ?namespace llvm {
>
> ? ObjectFile *ObjectFile::createCOFFObjectFile(MemoryBuffer *Object) {
>
> Modified: llvm/trunk/lib/Object/ELFObjectFile.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ELFObjectFile.cpp?rev=139314&r1=139313&r2=139314&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Object/ELFObjectFile.cpp (original)
> +++ llvm/trunk/lib/Object/ELFObjectFile.cpp Thu Sep ?8 15:52:17 2011
> @@ -14,6 +14,7 @@
> ?#include "llvm/ADT/SmallVector.h"
> ?#include "llvm/ADT/StringSwitch.h"
> ?#include "llvm/ADT/Triple.h"
> +#include "llvm/ADT/DenseMap.h"
> ?#include "llvm/Object/ObjectFile.h"
> ?#include "llvm/Support/ELF.h"
> ?#include "llvm/Support/Endian.h"
> @@ -176,12 +177,89 @@
> ?}
>
> ?namespace {
> +template
> +struct Elf_Rel_Base;
> +
> +template
> +struct Elf_Rel_Base {
> + ?LLVM_ELF_IMPORT_TYPES(target_endianness, false)
> + ?Elf_Addr ? ? ?r_offset; // Location (file byte offset, or program virtual addr)
> + ?Elf_Word ? ? ?r_info; ?// Symbol table index and type of relocation to apply
> +};
> +
> +template
> +struct Elf_Rel_Base {
> + ?LLVM_ELF_IMPORT_TYPES(target_endianness, true)
> + ?Elf_Addr ? ? ?r_offset; // Location (file byte offset, or program virtual addr)
> + ?Elf_Xword ? ? r_info; ? // Symbol table index and type of relocation to apply
> +};
> +
> +template
> +struct Elf_Rel_Base {
> + ?LLVM_ELF_IMPORT_TYPES(target_endianness, false)
> + ?Elf_Addr ? ? ?r_offset; // Location (file byte offset, or program virtual addr)
> + ?Elf_Word ? ? ?r_info; ? // Symbol table index and type of relocation to apply
> + ?Elf_Sword ? ? r_addend; // Compute value for relocatable field by adding this
> +};
> +
> +template
> +struct Elf_Rel_Base {
> + ?LLVM_ELF_IMPORT_TYPES(target_endianness, true)
> + ?Elf_Addr ? ? ?r_offset; // Location (file byte offset, or program virtual addr)
> + ?Elf_Xword ? ? r_info; ? // Symbol table index and type of relocation to apply
> + ?Elf_Sxword ? ?r_addend; // Compute value for relocatable field by adding this.
> +};
> +
> +template
> +struct Elf_Rel_Impl;
> +
> +template
> +struct Elf_Rel_Impl
> + ? ? ? : Elf_Rel_Base {
> + ?using Elf_Rel_Base::r_info;
> + ?LLVM_ELF_IMPORT_TYPES(target_endianness, true)
> +
> + ?// These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TYPE,
> + ?// and ELF64_R_INFO macros defined in the ELF specification:
> + ?uint64_t getSymbol() const { return (r_info >> 32); }
> + ?unsigned char getType() const {
> + ? ?return (unsigned char) (r_info & 0xffffffffL);
> + ?}
> + ?void setSymbol(uint64_t s) { setSymbolAndType(s, getType()); }
> + ?void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }
> + ?void setSymbolAndType(uint64_t s, unsigned char t) {
> + ? ?r_info = (s << 32) + (t&0xffffffffL);
> + ?}
> +};
> +
> +template
> +struct Elf_Rel_Impl
> + ? ? ? : Elf_Rel_Base {
> + ?using Elf_Rel_Base::r_info;
> + ?LLVM_ELF_IMPORT_TYPES(target_endianness, false)
> +
> + ?// These accessors and mutators correspond to the ELF32_R_SYM, ELF32_R_TYPE,
> + ?// and ELF32_R_INFO macros defined in the ELF specification:
> + ?uint32_t getSymbol() const { return (r_info >> 8); }
> + ?unsigned char getType() const { return (unsigned char) (r_info & 0x0ff); }
> + ?void setSymbol(uint32_t s) { setSymbolAndType(s, getType()); }
> + ?void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }
> + ?void setSymbolAndType(uint32_t s, unsigned char t) {
> + ? ?r_info = (s << 8) + t;
> + ?}
> +};
> +
> +}
> +
> +namespace {
> ?template
> ?class ELFObjectFile : public ObjectFile {
> ? LLVM_ELF_IMPORT_TYPES(target_endianness, is64Bits)
>
> ? typedef Elf_Shdr_Impl Elf_Shdr;
> ? typedef Elf_Sym_Impl Elf_Sym;
> + ?typedef Elf_Rel_Impl Elf_Rel;
> + ?typedef Elf_Rel_Impl Elf_Rela;
>
> ? struct Elf_Ehdr {
> ? ? unsigned char e_ident[ELF::EI_NIDENT]; // ELF Identification bytes
> @@ -206,18 +284,26 @@
> ? ? unsigned char getDataEncoding() const { return e_ident[ELF::EI_DATA]; }
> ? };
>
> - ?typedef SmallVector SymbolTableSections_t;
> + ?typedef SmallVector Sections_t;
> + ?typedef DenseMap IndexMap_t;
>
> ? const Elf_Ehdr *Header;
> ? const Elf_Shdr *SectionHeaderTable;
> ? const Elf_Shdr *dot_shstrtab_sec; // Section header string table.
> ? const Elf_Shdr *dot_strtab_sec; ? // Symbol header string table.
> - ?SymbolTableSections_t SymbolTableSections;
> + ?Sections_t SymbolTableSections;
> + ?IndexMap_t SymbolTableSectionsIndexMap;
> + ?Sections_t RelocationTableSections;
>
> ? void ? ? ? ? ? ?validateSymbol(DataRefImpl Symb) const;
> + ?bool ? ? ? ? ? ?isRelocationHasAddend(DataRefImpl Rel) const;
> + ?template
> + ?const T ? ? ? ?*getEntry(DataRefImpl Entry, Sections_t Sections) const;
> ? const Elf_Sym ?*getSymbol(DataRefImpl Symb) const;
> ? const Elf_Shdr *getSection(DataRefImpl index) const;
> ? const Elf_Shdr *getSection(uint16_t index) const;
> + ?const Elf_Rel ?*getRel(DataRefImpl Rel) const;
> + ?const Elf_Rela *getRela(DataRefImpl Rela) const;
> ? const char ? ? *getString(uint16_t section, uint32_t offset) const;
> ? const char ? ? *getString(const Elf_Shdr *section, uint32_t offset) const;
>
> @@ -238,12 +324,25 @@
> ? virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Symb,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool &Result) const;
>
> + ?virtual error_code getRelocationNext(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? RelocationRef &Res) const;
> + ?virtual error_code getRelocationAddress(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t &Res) const;
> + ?virtual error_code getRelocationSymbol(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SymbolRef &Res) const;
> + ?virtual error_code getRelocationType(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint32_t &Res) const;
> + ?virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int64_t &Res) const;
> +
> ?public:
> ? ELFObjectFile(MemoryBuffer *Object, error_code &ec);
> ? virtual symbol_iterator begin_symbols() const;
> ? virtual symbol_iterator end_symbols() const;
> ? virtual section_iterator begin_sections() const;
> ? virtual section_iterator end_sections() const;
> + ?virtual relocation_iterator begin_relocations() const;
> + ?virtual relocation_iterator end_relocations() const;
>
> ? virtual uint8_t getBytesInAddress() const;
> ? virtual StringRef getFileFormatName() const;
> @@ -416,7 +515,8 @@
> ? ? ? return ec;
> ? ? Result = StringSwitch(name)
> ? ? ? .StartsWith(".debug", 'N')
> - ? ? ?.StartsWith(".note", 'n');
> + ? ? ?.StartsWith(".note", 'n')
> + ? ? ?.Default('?');
> ? ? return object_error::success;
> ? }
>
> @@ -507,6 +607,121 @@
> ? return object_error::success;
> ?}
>
> +// Relocations
> +template
> +error_code ELFObjectFile
> + ? ? ? ? ? ? ? ? ? ? ? ?::getRelocationNext(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?RelocationRef &Result) const {
> + ?const Elf_Shdr *RelocationTableSection = RelocationTableSections[Rel.d.b];
> +
> + ?// Check to see if we are at the end of this relocation table.
> + ?if (++Rel.d.a >= RelocationTableSection->getEntityCount()) {
> + ? ?// We are at the end. If there are other relocation tables, jump to them.
> + ? ?Rel.d.a = 0;
> + ? ?// Otherwise return the terminator.
> + ? ?if (++Rel.d.b >= SymbolTableSections.size()) {
> + ? ? ?Rel.d.a = std::numeric_limits::max();
> + ? ? ?Rel.d.b = std::numeric_limits::max();
> + ? ?}
> + ?}
> +
> + ?Result = RelocationRef(Rel, this);
> + ?return object_error::success;
> +}
> +
> +template
> +error_code ELFObjectFile
> + ? ? ? ? ? ? ? ? ? ? ? ?::getRelocationSymbol(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SymbolRef &Result) const {
> + ?uint32_t symbolIdx;
> + ?const Elf_Shdr *sec = RelocationTableSections[Rel.d.b];
> + ?switch (sec->sh_type) {
> + ? ?default :
> + ? ? ?report_fatal_error("Invalid section type in Rel!");
> + ? ?case ELF::SHT_REL : {
> + ? ? ?symbolIdx = getRel(Rel)->getSymbol();
> + ? ? ?break;
> + ? ?}
> + ? ?case ELF::SHT_RELA : {
> + ? ? ?symbolIdx = getRela(Rel)->getSymbol();
> + ? ? ?break;
> + ? ?}
> + ?}
> + ?DataRefImpl SymbolData;
> + ?IndexMap_t::const_iterator it = SymbolTableSectionsIndexMap.find(sec->sh_link);
> + ?if (it == SymbolTableSectionsIndexMap.end())
> + ? ?report_fatal_error("Relocation symbol table not found!");
> + ?SymbolData.d.a = symbolIdx;
> + ?SymbolData.d.b = it->second;
> + ?Result = SymbolRef(SymbolData, this);
> + ?return object_error::success;
> +}
> +
> +template
> +error_code ELFObjectFile
> + ? ? ? ? ? ? ? ? ? ? ? ?::getRelocationAddress(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t &Result) const {
> + ?uint64_t offset;
> + ?const Elf_Shdr *sec = RelocationTableSections[Rel.d.b];
> + ?switch (sec->sh_type) {
> + ? ?default :
> + ? ? ?report_fatal_error("Invalid section type in Rel!");
> + ? ?case ELF::SHT_REL : {
> + ? ? ?offset = getRel(Rel)->r_offset;
> + ? ? ?break;
> + ? ?}
> + ? ?case ELF::SHT_RELA : {
> + ? ? ?offset = getRela(Rel)->r_offset;
> + ? ? ?break;
> + ? ?}
> + ?}
> +
> + ?const Elf_Shdr *secAddr = getSection(sec->sh_info);
> + ?Result = offset + reinterpret_cast(base() + secAddr->sh_offset);
> + ?return object_error::success;
> +}
> +
> +template
> +error_code ELFObjectFile
> + ? ? ? ? ? ? ? ? ? ? ? ?::getRelocationType(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint32_t &Result) const {
> + ?const Elf_Shdr *sec = RelocationTableSections[Rel.d.b];
> + ?switch (sec->sh_type) {
> + ? ?default :
> + ? ? ?report_fatal_error("Invalid section type in Rel!");
> + ? ?case ELF::SHT_REL : {
> + ? ? ?Result = getRel(Rel)->getType();
> + ? ? ?break;
> + ? ?}
> + ? ?case ELF::SHT_RELA : {
> + ? ? ?Result = getRela(Rel)->getType();
> + ? ? ?break;
> + ? ?}
> + ?}
> + ?return object_error::success;
> +}
> +
> +template
> +error_code ELFObjectFile
> + ? ? ? ? ? ? ? ? ? ? ? ?::getRelocationAdditionalInfo(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int64_t &Result) const {
> + ?const Elf_Shdr *sec = RelocationTableSections[Rel.d.b];
> + ?switch (sec->sh_type) {
> + ? ?default :
> + ? ? ?report_fatal_error("Invalid section type in Rel!");
> + ? ?case ELF::SHT_REL : {
> + ? ? ?Result = 0;
> + ? ? ?return object_error::success;
> + ? ?}
> + ? ?case ELF::SHT_RELA : {
> + ? ? ?Result = getRela(Rel)->r_addend;
> + ? ? ?return object_error::success;
> + ? ?}
> + ?}
> +}
> +
> +
> +
> ?template
> ?ELFObjectFile::ELFObjectFile(MemoryBuffer *Object
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? , error_code &ec)
> @@ -529,13 +744,17 @@
>
>
> ? // To find the symbol tables we walk the section table to find SHT_STMTAB.
> - ?for (const char *i = reinterpret_cast(SectionHeaderTable),
> - ? ? ? ? ? ? ? ? ?*e = i + Header->e_shnum * Header->e_shentsize;
> - ? ? ? ? ? ? ? ? ? i != e; i += Header->e_shentsize) {
> - ? ?const Elf_Shdr *sh = reinterpret_cast(i);
> + ?const Elf_Shdr* sh =
> + ? ? ? ? ? ? ? ? ? ?reinterpret_cast(SectionHeaderTable);
> + ?for (unsigned i = 0; i < Header->e_shnum; ++i) {
> ? ? if (sh->sh_type == ELF::SHT_SYMTAB) {
> + ? ? ?SymbolTableSectionsIndexMap[i] = SymbolTableSections.size();
> ? ? ? SymbolTableSections.push_back(sh);
> ? ? }
> + ? ?if (sh->sh_type == ELF::SHT_REL || sh->sh_type == ELF::SHT_RELA) {
> + ? ? ?RelocationTableSections.push_back(sh);
> + ? ?}
> + ? ?++sh;
> ? }
>
> ? // Get string table sections.
> @@ -615,6 +834,31 @@
> ?}
>
> ?template
> +ObjectFile::relocation_iterator ELFObjectFile
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ::begin_relocations() const {
> + ?DataRefImpl RelData;
> + ?memset(&RelData, 0, sizeof(RelData));
> + ?if (RelocationTableSections.size() == 0) {
> + ? ?RelData.d.a = std::numeric_limits::max();
> + ? ?RelData.d.b = std::numeric_limits::max();
> + ?} else {
> + ? ?RelData.d.a = 0;
> + ? ?RelData.d.b = 0;
> + ?}
> + ?return relocation_iterator(RelocationRef(RelData, this));
> +}
> +
> +template
> +ObjectFile::relocation_iterator ELFObjectFile
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ::end_relocations() const {
> + ?DataRefImpl RelData;
> + ?memset(&RelData, 0, sizeof(RelData));
> + ?RelData.d.a = std::numeric_limits::max();
> + ?RelData.d.b = std::numeric_limits::max();
> + ?return relocation_iterator(RelocationRef(RelData, this));
> +}
> +
> +template
> ?uint8_t ELFObjectFile::getBytesInAddress() const {
> ? return is64Bits ? 8 : 4;
> ?}
> @@ -629,6 +873,8 @@
> ? ? ? return "ELF32-i386";
> ? ? case ELF::EM_X86_64:
> ? ? ? return "ELF32-x86-64";
> + ? ?case ELF::EM_ARM:
> + ? ? ?return "ELF32-arm";
> ? ? default:
> ? ? ? return "ELF32-unknown";
> ? ? }
> @@ -654,19 +900,41 @@
> ? ? return Triple::x86;
> ? case ELF::EM_X86_64:
> ? ? return Triple::x86_64;
> + ?case ELF::EM_ARM:
> + ? ?return Triple::arm;
> ? default:
> ? ? return Triple::UnknownArch;
> ? }
> ?}
>
> ?template
> -const typename ELFObjectFile::Elf_Sym *
> -ELFObjectFile::getSymbol(DataRefImpl Symb) const {
> - ?const Elf_Shdr *sec = SymbolTableSections[Symb.d.b];
> - ?return reinterpret_cast(
> +template
> +inline const T *
> +ELFObjectFile::getEntry(DataRefImpl Entry,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Sections_t Sections) const {
> + ?const Elf_Shdr *sec = Sections[Entry.d.b];
> + ?return reinterpret_cast(
> ? ? ? ? ? ?base()
> ? ? ? ? ? ?+ sec->sh_offset
> - ? ? ? ? ? + (Symb.d.a * sec->sh_entsize));
> + ? ? ? ? ? + (Entry.d.a * sec->sh_entsize));
> +}
> +
> +template
> +const typename ELFObjectFile::Elf_Sym *
> +ELFObjectFile::getSymbol(DataRefImpl Symb) const {
> + ?return getEntry(Symb, SymbolTableSections);
> +}
> +
> +template
> +const typename ELFObjectFile::Elf_Rel *
> +ELFObjectFile::getRel(DataRefImpl Rel) const {
> + ?return getEntry(Rel, RelocationTableSections);
> +}
> +
> +template
> +const typename ELFObjectFile::Elf_Rela *
> +ELFObjectFile::getRela(DataRefImpl Rela) const {
> + ?return getEntry(Rela, RelocationTableSections);
> ?}
>
> ?template
>
> Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=139314&r1=139313&r2=139314&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
> +++ llvm/trunk/lib/Object/MachOObjectFile.cpp Thu Sep ?8 15:52:17 2011
> @@ -18,6 +18,7 @@
> ?#include "llvm/Object/ObjectFile.h"
> ?#include "llvm/Support/MemoryBuffer.h"
> ?#include "llvm/Support/MachO.h"
> +#include "llvm/ADT/SmallVector.h"
>
> ?#include
> ?#include
> @@ -32,15 +33,14 @@
>
> ?class MachOObjectFile : public ObjectFile {
> ?public:
> - ?MachOObjectFile(MemoryBuffer *Object, MachOObject *MOO, error_code &ec)
> - ? ?: ObjectFile(Binary::isMachO, Object, ec),
> - ? ? ?MachOObj(MOO),
> - ? ? ?RegisteredStringTable(std::numeric_limits::max()) {}
> + ?MachOObjectFile(MemoryBuffer *Object, MachOObject *MOO, error_code &ec);
>
> ? virtual symbol_iterator begin_symbols() const;
> ? virtual symbol_iterator end_symbols() const;
> ? virtual section_iterator begin_sections() const;
> ? virtual section_iterator end_sections() const;
> + ?virtual relocation_iterator begin_relocations() const;
> + ?virtual relocation_iterator end_relocations() const;
>
> ? virtual uint8_t getBytesInAddress() const;
> ? virtual StringRef getFileFormatName() const;
> @@ -63,9 +63,22 @@
> ? virtual error_code sectionContainsSymbol(DataRefImpl DRI, DataRefImpl S,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool &Result) const;
>
> + ?virtual error_code getRelocationNext(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? RelocationRef &Res) const;
> + ?virtual error_code getRelocationAddress(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint64_t &Res) const;
> + ?virtual error_code getRelocationSymbol(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SymbolRef &Res) const;
> + ?virtual error_code getRelocationType(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint32_t &Res) const;
> + ?virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int64_t &Res) const;
> ?private:
> ? MachOObject *MachOObj;
> ? mutable uint32_t RegisteredStringTable;
> + ?typedef SmallVector SectionList;
> + ?SectionList Sections;
> +
>
> ? void moveToNextSection(DataRefImpl &DRI) const;
> ? void getSymbolTableEntry(DataRefImpl DRI,
> @@ -76,8 +89,35 @@
> ? void getSection(DataRefImpl DRI, InMemoryStruct &Res) const;
> ? void getSection64(DataRefImpl DRI,
> ? ? ? ? ? ? ? ? ? ? InMemoryStruct &Res) const;
> + ?void getRelocation(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? InMemoryStruct &Res) const;
> ?};
>
> +MachOObjectFile::MachOObjectFile(MemoryBuffer *Object, MachOObject *MOO,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? error_code &ec)
> + ? ?: ObjectFile(Binary::isMachO, Object, ec),
> + ? ? ?MachOObj(MOO),
> + ? ? ?RegisteredStringTable(std::numeric_limits::max()) {
> + ?DataRefImpl DRI;
> + ?DRI.d.a = DRI.d.b = 0;
> + ?moveToNextSection(DRI);
> + ?uint32_t LoadCommandCount = MachOObj->getHeader().NumLoadCommands;
> + ?while (DRI.d.a < LoadCommandCount) {
> + ? ?Sections.push_back(DRI);
> + ? ?uint64_t Addr;
> + ? ?uint64_t Size;
> + ? ?StringRef Name;
> + ? ?getSectionAddress(DRI, Addr);
> + ? ?getSectionSize(DRI, Size);
> + ? ?getSectionName(DRI, Name);
> + ? ?InMemoryStruct Sect;
> + ? ?getSection(DRI, Sect);
> + ? ?DRI.d.b++;
> + ? ?moveToNextSection(DRI);
> + ?}
> +}
> +
> +
> ?ObjectFile *ObjectFile::createMachOObjectFile(MemoryBuffer *Buffer) {
> ? error_code ec;
> ? std::string Err;
> @@ -414,6 +454,125 @@
> ? return section_iterator(SectionRef(DRI, this));
> ?}
>
> +/*===-- Relocations -------------------------------------------------------===*/
> +
> +void MachOObjectFile::
> +getRelocation(DataRefImpl Rel,
> + ? ? ? ? ? ? ?InMemoryStruct &Res) const {
> + ?uint32_t relOffset;
> + ?if (MachOObj->is64Bit()) {
> + ? ?InMemoryStruct Sect;
> + ? ?getSection64(Sections[Rel.d.b], Sect);
> + ? ?relOffset = Sect->RelocationTableOffset;
> + ?} else {
> + ? ?InMemoryStruct Sect;
> + ? ?getSection(Sections[Rel.d.b], Sect);
> + ? ?relOffset = Sect->RelocationTableOffset;
> + ?}
> + ?MachOObj->ReadRelocationEntry(relOffset, Rel.d.a, Res);
> +}
> +error_code MachOObjectFile::getRelocationNext(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?RelocationRef &Res) const {
> + ?++Rel.d.a;
> + ?while (Rel.d.b < Sections.size()) {
> + ? ?unsigned relocationCount;
> + ? ?if (MachOObj->is64Bit()) {
> + ? ? ?InMemoryStruct Sect;
> + ? ? ?getSection64(Sections[Rel.d.b], Sect);
> + ? ? ?relocationCount = Sect->NumRelocationTableEntries;
> + ? ?} else {
> + ? ? ?InMemoryStruct Sect;
> + ? ? ?getSection(Sections[Rel.d.b], Sect);
> + ? ? ?relocationCount = Sect->NumRelocationTableEntries;
> + ? ?}
> + ? ?if (Rel.d.a < relocationCount)
> + ? ? ?break;
> +
> + ? ?Rel.d.a = 0;
> + ? ?++Rel.d.b;
> + ?}
> + ?Res = RelocationRef(Rel, this);
> + ?return object_error::success;
> +}
> +error_code MachOObjectFile::getRelocationAddress(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? uint64_t &Res) const {
> + ?const uint8_t* sectAddress = base();
> + ?if (MachOObj->is64Bit()) {
> + ? ?InMemoryStruct Sect;
> + ? ?getSection64(Sections[Rel.d.b], Sect);
> + ? ?sectAddress += Sect->Offset;
> + ?} else {
> + ? ?InMemoryStruct Sect;
> + ? ?getSection(Sections[Rel.d.b], Sect);
> + ? ?sectAddress += Sect->Offset;
> + ?}
> + ?InMemoryStruct RE;
> + ?getRelocation(Rel, RE);
> + ?Res = reinterpret_cast(sectAddress + RE->Word0);
> + ?return object_error::success;
> +}
> +error_code MachOObjectFile::getRelocationSymbol(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?SymbolRef &Res) const {
> + ?InMemoryStruct RE;
> + ?getRelocation(Rel, RE);
> + ?uint32_t SymbolIdx = RE->Word1 & 0xffffff;
> + ?bool isExtern = (RE->Word1 >> 27) & 1;
> +
> + ?DataRefImpl Sym;
> + ?Sym.d.a = Sym.d.b = 0;
> + ?moveToNextSymbol(Sym);
> + ?uint32_t NumLoadCommands = MachOObj->getHeader().NumLoadCommands;
> + ?if (isExtern) {
> + ? ?for (unsigned i = 0; i < SymbolIdx; i++) {
> + ? ? ?Sym.d.b++;
> + ? ? ?moveToNextSymbol(Sym);
> + ? ? ?assert(Sym.d.a < NumLoadCommands &&
> + ? ? ? ? ? ? "Relocation symbol index out of range!");
> + ? ?}
> + ?}
> + ?Res = SymbolRef(Sym, this);
> + ?return object_error::success;
> +}
> +error_code MachOObjectFile::getRelocationType(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?uint32_t &Res) const {
> + ?InMemoryStruct RE;
> + ?getRelocation(Rel, RE);
> + ?Res = RE->Word1;
> + ?return object_error::success;
> +}
> +error_code MachOObjectFile::getRelocationAdditionalInfo(DataRefImpl Rel,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int64_t &Res) const {
> + ?InMemoryStruct RE;
> + ?getRelocation(Rel, RE);
> + ?bool isExtern = (RE->Word1 >> 27) & 1;
> + ?Res = 0;
> + ?if (!isExtern) {
> + ? ?const uint8_t* sectAddress = base();
> + ? ?if (MachOObj->is64Bit()) {
> + ? ? ?InMemoryStruct Sect;
> + ? ? ?getSection64(Sections[Rel.d.b], Sect);
> + ? ? ?sectAddress += Sect->Offset;
> + ? ?} else {
> + ? ? ?InMemoryStruct Sect;
> + ? ? ?getSection(Sections[Rel.d.b], Sect);
> + ? ? ?sectAddress += Sect->Offset;
> + ? ?}
> + ? ?Res = reinterpret_cast(sectAddress);
> + ?}
> + ?return object_error::success;
> +}
> +ObjectFile::relocation_iterator MachOObjectFile::begin_relocations() const {
> + ?DataRefImpl ret;
> + ?ret.d.a = ret.d.b = 0;
> + ?return relocation_iterator(RelocationRef(ret, this));
> +}
> +ObjectFile::relocation_iterator MachOObjectFile::end_relocations() const {
> + ?DataRefImpl ret;
> + ?ret.d.a = 0;
> + ?ret.d.b = Sections.size();
> + ?return relocation_iterator(RelocationRef(ret, this));
> +}
> +
> ?/*===-- Miscellaneous -----------------------------------------------------===*/
>
> ?uint8_t MachOObjectFile::getBytesInAddress() const {
Is it alright with you if I change the relocation API to provide
relocations per section instead of per object file? All currently
supported file formats do this internally, and most tools access
relocations in this manner. Also, your implementation of getAddress
returns the memory address the relocation targets on the system as a
uintptr_t, which seems very odd to me.
- Michael Spencer
From atrick at apple.com Mon Oct 3 19:07:03 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 04 Oct 2011 00:07:03 -0000
Subject: [llvm-commits] [llvm] r141049 -
/llvm/trunk/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll
Message-ID: <20111004000703.F11752A6C12C@llvm.org>
Author: atrick
Date: Mon Oct 3 19:07:02 2011
New Revision: 141049
URL: http://llvm.org/viewvc/llvm-project?rev=141049&view=rev
Log:
Unit test for r140919, loop unroll heuristics.
Added:
llvm/trunk/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll
Added: llvm/trunk/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll?rev=141049&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll (added)
+++ llvm/trunk/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll Mon Oct 3 19:07:02 2011
@@ -0,0 +1,36 @@
+; RUN: opt < %s -S -loop-unroll -unroll-threshold=150 | FileCheck %s
+;
+; Verify that trunc i64 to i32 is considered free by loop unrolling
+; heuristics when i32 is a native type.
+; This should result in full unrolling this loop with size=7, TC=19.
+; If the trunc were not free we would have 8*19=152 > 150.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+
+; Check that for.body was unrolled 19 times.
+; CHECK: @test
+; CHECK: %0 = load
+; CHECK: %conv = sext i8 %0 to i32
+; CHECK: %add.1 = add nsw i32 %conv.1, %conv
+; CHECK: %add.18 = add nsw i32 %conv.18, %add.17
+; CHECK: ret i32 %add.18
+define i32 @test(i8* %arr) nounwind uwtable readnone {
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+ %sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ]
+ %arrayidx = getelementptr inbounds i8* %arr, i64 %indvars.iv
+ %0 = load i8* %arrayidx, align 1
+ %conv = sext i8 %0 to i32
+ %add = add nsw i32 %conv, %sum.02
+ %indvars.iv.next = add i64 %indvars.iv, 1
+ %lftr.wideiv1 = trunc i64 %indvars.iv.next to i32
+ %exitcond2 = icmp eq i32 %lftr.wideiv1, 19
+ br i1 %exitcond2, label %for.end, label %for.body
+
+for.end: ; preds = %for.body
+ %add.lcssa = phi i32 [ %add, %for.body ]
+ ret i32 %add.lcssa
+}
From isanbard at gmail.com Mon Oct 3 19:16:48 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 04 Oct 2011 00:16:48 -0000
Subject: [llvm-commits] [llvm] r141050 -
/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
Message-ID: <20111004001648.CC1802A6C12C@llvm.org>
Author: void
Date: Mon Oct 3 19:16:40 2011
New Revision: 141050
URL: http://llvm.org/viewvc/llvm-project?rev=141050&view=rev
Log:
Generic cleanup.
Modified:
llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=141050&r1=141049&r2=141050&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Mon Oct 3 19:16:40 2011
@@ -638,7 +638,7 @@
Type::getInt8PtrTy(F.getContext()), "",
EntryBB->getTerminator());
Value *DispatchVal = CallInst::Create(BuiltinSetjmpFn, SetjmpArg,
- "dispatch",
+ "",
EntryBB->getTerminator());
// Add a call to dispatch_setup after the setjmp call. This is expanded to any
@@ -780,9 +780,8 @@
// LSDA address
Idxs[1] = ConstantInt::get(Int32Ty, 4);
- Value *LSDAFieldPtr =
- GetElementPtrInst::Create(FuncCtx, Idxs, "lsda_gep",
- EntryBB->getTerminator());
+ Value *LSDAFieldPtr = GetElementPtrInst::Create(FuncCtx, Idxs, "lsda_gep",
+ EntryBB->getTerminator());
Value *LSDA = CallInst::Create(LSDAAddrFn, "lsda_addr",
EntryBB->getTerminator());
new StoreInst(LSDA, LSDAFieldPtr, true, EntryBB->getTerminator());
@@ -819,15 +818,13 @@
// Get a reference to the jump buffer.
Idxs[1] = ConstantInt::get(Int32Ty, 5);
- Value *JBufPtr =
- GetElementPtrInst::Create(FuncCtx, Idxs, "jbuf_gep",
- EntryBB->getTerminator());
+ Value *JBufPtr = GetElementPtrInst::Create(FuncCtx, Idxs, "jbuf_gep",
+ EntryBB->getTerminator());
// Save the frame pointer.
Idxs[1] = ConstantInt::get(Int32Ty, 0);
- Value *FramePtr =
- GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_fp_gep",
- EntryBB->getTerminator());
+ Value *FramePtr = GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_fp_gep",
+ EntryBB->getTerminator());
Value *Val = CallInst::Create(FrameAddrFn,
ConstantInt::get(Int32Ty, 0),
@@ -837,26 +834,23 @@
// Save the stack pointer.
Idxs[1] = ConstantInt::get(Int32Ty, 2);
- Value *StackPtr =
- GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_sp_gep",
- EntryBB->getTerminator());
+ Value *StackPtr = GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_sp_gep",
+ EntryBB->getTerminator());
Val = CallInst::Create(StackAddrFn, "sp", EntryBB->getTerminator());
new StoreInst(Val, StackPtr, true, EntryBB->getTerminator());
// Call the setjmp instrinsic. It fills in the rest of the jmpbuf.
- Value *SetjmpArg =
- CastInst::Create(Instruction::BitCast, JBufPtr,
- Type::getInt8PtrTy(F.getContext()), "",
- EntryBB->getTerminator());
+ Value *SetjmpArg = CastInst::Create(Instruction::BitCast, JBufPtr,
+ Type::getInt8PtrTy(F.getContext()), "",
+ EntryBB->getTerminator());
CallInst::Create(BuiltinSetjmpFn, SetjmpArg, "", EntryBB->getTerminator());
// Store a pointer to the function context so that the back-end will know
// where to look for it.
- Value *FuncCtxArg =
- CastInst::Create(Instruction::BitCast, FuncCtx,
- Type::getInt8PtrTy(F.getContext()), "",
- EntryBB->getTerminator());
+ Value *FuncCtxArg = CastInst::Create(Instruction::BitCast, FuncCtx,
+ Type::getInt8PtrTy(F.getContext()), "",
+ EntryBB->getTerminator());
CallInst::Create(FuncCtxFn, FuncCtxArg, "", EntryBB->getTerminator());
// At this point, we are all set up, update the invoke instructions to mark
@@ -877,7 +871,7 @@
// created for this function and any unexpected exceptions thrown will go
// directly to the caller's context, which is what we want anyway, so no need
// to do anything here.
- for (Function::iterator BB = F.begin(), E = F.end(); ++BB != E;) {
+ for (Function::iterator BB = F.begin(), E = F.end(); ++BB != E;)
for (BasicBlock::iterator I = BB->begin(), end = BB->end(); I != end; ++I)
if (CallInst *CI = dyn_cast(I)) {
if (!CI->doesNotThrow())
@@ -885,7 +879,6 @@
} else if (ResumeInst *RI = dyn_cast(I)) {
insertCallSiteStore(RI, -1, CallSite);
}
- }
// Register the function context and make sure it's known to not throw
CallInst *Register = CallInst::Create(RegisterFn, FuncCtx, "",
From peter at pcc.me.uk Mon Oct 3 19:30:35 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Tue, 04 Oct 2011 00:30:35 -0000
Subject: [llvm-commits] [llvm] r141052 -
/llvm/trunk/tools/llvm-shlib/Makefile
Message-ID: <20111004003035.C393B2A6C12C@llvm.org>
Author: pcc
Date: Mon Oct 3 19:30:34 2011
New Revision: 141052
URL: http://llvm.org/viewvc/llvm-project?rev=141052&view=rev
Log:
Exclude libLLVMTableGen.a from the shared library
Unbreaks tools for --enable-shared build.
Modified:
llvm/trunk/tools/llvm-shlib/Makefile
Modified: llvm/trunk/tools/llvm-shlib/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-shlib/Makefile?rev=141052&r1=141051&r2=141052&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-shlib/Makefile (original)
+++ llvm/trunk/tools/llvm-shlib/Makefile Mon Oct 3 19:30:34 2011
@@ -30,10 +30,11 @@
include $(LEVEL)/Makefile.common
# Include all archives in libLLVM.(so|dylib) except the ones that have
-# their own dynamic libraries.
+# their own dynamic libraries and TableGen.
Archives := $(wildcard $(LibDir)/libLLVM*.a)
SharedLibraries := $(wildcard $(LibDir)/libLLVM*$(SHLIBEXT))
-IncludeInLibLlvm := $(filter-out $(basename $(SharedLibraries)).a, $(Archives))
+ExcludeFromLibLlvm := $(basename $(SharedLibraries)).a %/libLLVMTableGen.a
+IncludeInLibLlvm := $(filter-out $(ExcludeFromLibLlvm), $(Archives))
LLVMLibsOptions := $(IncludeInLibLlvm:$(LibDir)/lib%.a=-l%)
LLVMLibsPaths := $(IncludeInLibLlvm)
From rafael.espindola at gmail.com Mon Oct 3 21:51:02 2011
From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=)
Date: Mon, 3 Oct 2011 22:51:02 -0400
Subject: [llvm-commits] [patch] Add the returns_twice attribute
In-Reply-To: <6638C20A-2346-49A1-B604-45C0FE854CC4@apple.com>
References: <4E84F46A.9070206@gmail.com>
<6638C20A-2346-49A1-B604-45C0FE854CC4@apple.com>
Message-ID:
2011/10/3 Evan Cheng :
> See Function::callsFunctionThatReturnsTwice(). If you are adding this attribute, then should add the attribute to these special functions (e.g. setjmp)? Then callsFunctionThatReturnsTwice() can go away.
Well, it will check if the function calls another function with this
attribute. I hope the next patches done this week (see
llvm.org/pr11038).
> Evan
>
Cheers,
Rafael
From rafael.espindola at gmail.com Mon Oct 3 22:08:44 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 04 Oct 2011 03:08:44 -0000
Subject: [llvm-commits] [llvm] r141057 - in /llvm/trunk: docs/LangRef.html
lib/AsmParser/LLLexer.cpp lib/AsmParser/LLToken.h utils/llvm.grm
Message-ID: <20111004030846.644012A6C12C@llvm.org>
Author: rafael
Date: Mon Oct 3 22:08:43 2011
New Revision: 141057
URL: http://llvm.org/viewvc/llvm-project?rev=141057&view=rev
Log:
Remove last references to hotpatch.
Modified:
llvm/trunk/docs/LangRef.html
llvm/trunk/lib/AsmParser/LLLexer.cpp
llvm/trunk/lib/AsmParser/LLToken.h
llvm/trunk/utils/llvm.grm
Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=141057&r1=141056&r2=141057&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Mon Oct 3 22:08:43 2011
@@ -1163,14 +1163,6 @@
function into callers whenever possible, ignoring any active inlining size
threshold for this caller.
- hotpatch
- This attribute indicates that the function should be 'hotpatchable',
- meaning the function can be patched and/or hooked even while it is
- loaded into memory. On x86, the function prologue will be preceded
- by six bytes of padding and will begin with a two-byte instruction.
- Most of the functions in the Windows system DLLs in Windows XP SP2 or
- higher were compiled in this fashion.
-
nonlazybind
This attribute suppresses lazy symbol binding for the function. This
may make calls to the function faster, at the cost of extra program
Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=141057&r1=141056&r2=141057&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Mon Oct 3 22:08:43 2011
@@ -569,7 +569,6 @@
KEYWORD(noredzone);
KEYWORD(noimplicitfloat);
KEYWORD(naked);
- KEYWORD(hotpatch);
KEYWORD(nonlazybind);
KEYWORD(type);
Modified: llvm/trunk/lib/AsmParser/LLToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=141057&r1=141056&r2=141057&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLToken.h (original)
+++ llvm/trunk/lib/AsmParser/LLToken.h Mon Oct 3 22:08:43 2011
@@ -101,7 +101,6 @@
kw_noredzone,
kw_noimplicitfloat,
kw_naked,
- kw_hotpatch,
kw_nonlazybind,
kw_type,
Modified: llvm/trunk/utils/llvm.grm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm.grm?rev=141057&r1=141056&r2=141057&view=diff
==============================================================================
--- llvm/trunk/utils/llvm.grm (original)
+++ llvm/trunk/utils/llvm.grm Mon Oct 3 22:08:43 2011
@@ -172,7 +172,7 @@
| optsize
| ssp
| sspreq
- | hotpatch
+ | returns_twice
| nonlazybind
;
From atrick at apple.com Mon Oct 3 22:34:50 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 04 Oct 2011 03:34:50 -0000
Subject: [llvm-commits] [llvm] r141058 - in /llvm/trunk:
include/llvm/Transforms/Utils/BasicBlockUtils.h
lib/Transforms/Utils/BreakCriticalEdges.cpp
Message-ID: <20111004033452.D336F2A6C12C@llvm.org>
Author: atrick
Date: Mon Oct 3 22:34:49 2011
New Revision: 141058
URL: http://llvm.org/viewvc/llvm-project?rev=141058&view=rev
Log:
whitespace
Modified:
llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h
llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
Modified: llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h?rev=141058&r1=141057&r2=141058&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h (original)
+++ llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h Mon Oct 3 22:34:49 2011
@@ -31,8 +31,8 @@
/// DeleteDeadBlock - Delete the specified block, which must have no
/// predecessors.
void DeleteDeadBlock(BasicBlock *BB);
-
-
+
+
/// FoldSingleEntryPHINodes - We know that BB has one predecessor. If there are
/// any single-entry PHI nodes in it, fold them away. This handles the case
/// when all entries to the PHI nodes in a block are guaranteed equal, such as
@@ -75,7 +75,7 @@
/// The output is added to Result, as pairs of edge info.
void FindFunctionBackedges(const Function &F,
SmallVectorImpl > &Result);
-
+
/// GetSuccessorNumber - Search for the specified successor of basic block BB
/// and return its position in the terminator instruction's list of
@@ -97,10 +97,10 @@
/// was split, null otherwise.
///
/// If MergeIdenticalEdges is true (not the default), *all* edges from TI to the
-/// specified successor will be merged into the same critical edge block.
-/// This is most commonly interesting with switch instructions, which may
+/// specified successor will be merged into the same critical edge block.
+/// This is most commonly interesting with switch instructions, which may
/// have many edges to any one destination. This ensures that all edges to that
-/// dest go to one block instead of each going to a different block, but isn't
+/// dest go to one block instead of each going to a different block, but isn't
/// the standard definition of a "critical edge".
///
/// It is invalid to call this function on a critical edge that starts at an
@@ -147,8 +147,8 @@
}
}
-/// SplitEdge - Split the edge connecting specified block. Pass P must
-/// not be NULL.
+/// SplitEdge - Split the edge connecting specified block. Pass P must
+/// not be NULL.
BasicBlock *SplitEdge(BasicBlock *From, BasicBlock *To, Pass *P);
/// SplitBlock - Split the specified block at the specified instruction - every
@@ -157,7 +157,7 @@
/// the loop info is updated.
///
BasicBlock *SplitBlock(BasicBlock *Old, Instruction *SplitPt, Pass *P);
-
+
/// SplitBlockPredecessors - This method transforms BB by introducing a new
/// basic block into the function, and moving some of the predecessors of BB to
/// be predecessors of the new block. The new predecessors are indicated by the
@@ -180,13 +180,13 @@
/// block gets the remaining predecessors of OrigBB. The landingpad instruction
/// OrigBB is clone into both of the new basic blocks. The new blocks are given
/// the suffixes 'Suffix1' and 'Suffix2', and are returned in the NewBBs vector.
-///
+///
/// This currently updates the LLVM IR, AliasAnalysis, DominatorTree,
/// DominanceFrontier, LoopInfo, and LCCSA but no other analyses. In particular,
/// it does not preserve LoopSimplify (because it's complicated to handle the
/// case where one of the edges being split is an exit of a loop with other
/// exits).
-///
+///
void SplitLandingPadPredecessors(BasicBlock *OrigBB,ArrayRef Preds,
const char *Suffix, const char *Suffix2,
Pass *P, SmallVectorImpl &NewBBs);
@@ -199,7 +199,7 @@
ReturnInst *FoldReturnIntoUncondBranch(ReturnInst *RI, BasicBlock *BB,
BasicBlock *Pred);
-/// GetFirstDebugLocInBasicBlock - Return first valid DebugLoc entry in a
+/// GetFirstDebugLocInBasicBlock - Return first valid DebugLoc entry in a
/// given basic block.
DebugLoc GetFirstDebugLocInBasicBlock(const BasicBlock *BB);
Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=141058&r1=141057&r2=141058&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Mon Oct 3 22:34:49 2011
@@ -102,7 +102,7 @@
++I; // Skip one edge due to the incoming arc from TI.
if (!AllowIdenticalEdges)
return I != E;
-
+
// If AllowIdenticalEdges is true, then we allow this edge to be considered
// non-critical iff all preds come from TI's block.
while (I != E) {
@@ -155,10 +155,10 @@
/// This returns the new block if the edge was split, null otherwise.
///
/// If MergeIdenticalEdges is true (not the default), *all* edges from TI to the
-/// specified successor will be merged into the same critical edge block.
-/// This is most commonly interesting with switch instructions, which may
+/// specified successor will be merged into the same critical edge block.
+/// This is most commonly interesting with switch instructions, which may
/// have many edges to any one destination. This ensures that all edges to that
-/// dest go to one block instead of each going to a different block, but isn't
+/// dest go to one block instead of each going to a different block, but isn't
/// the standard definition of a "critical edge".
///
/// It is invalid to call this function on a critical edge that starts at an
@@ -169,10 +169,10 @@
BasicBlock *llvm::SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum,
Pass *P, bool MergeIdenticalEdges) {
if (!isCriticalEdge(TI, SuccNum, MergeIdenticalEdges)) return 0;
-
+
assert(!isa(TI) &&
"Cannot split critical edge from IndirectBrInst");
-
+
BasicBlock *TIBB = TI->getParent();
BasicBlock *DestBB = TI->getSuccessor(SuccNum);
@@ -194,7 +194,7 @@
Function &F = *TIBB->getParent();
Function::iterator FBBI = TIBB;
F.getBasicBlockList().insert(++FBBI, NewBB);
-
+
// If there are any PHI nodes in DestBB, we need to update them so that they
// merge incoming values from NewBB instead of from TIBB.
{
@@ -211,35 +211,35 @@
// happens because the BB list of PHI nodes are usually in the same
// order.
if (PN->getIncomingBlock(BBIdx) != TIBB)
- BBIdx = PN->getBasicBlockIndex(TIBB);
+ BBIdx = PN->getBasicBlockIndex(TIBB);
PN->setIncomingBlock(BBIdx, NewBB);
}
}
-
+
// If there are any other edges from TIBB to DestBB, update those to go
// through the split block, making those edges non-critical as well (and
// reducing the number of phi entries in the DestBB if relevant).
if (MergeIdenticalEdges) {
for (unsigned i = SuccNum+1, e = TI->getNumSuccessors(); i != e; ++i) {
if (TI->getSuccessor(i) != DestBB) continue;
-
+
// Remove an entry for TIBB from DestBB phi nodes.
DestBB->removePredecessor(TIBB);
-
+
// We found another edge to DestBB, go to NewBB instead.
TI->setSuccessor(i, NewBB);
}
}
-
-
+
+
// If we don't have a pass object, we can't update anything...
if (P == 0) return NewBB;
-
+
DominatorTree *DT = P->getAnalysisIfAvailable();
LoopInfo *LI = P->getAnalysisIfAvailable();
ProfileInfo *PI = P->getAnalysisIfAvailable();
-
+
// If we have nothing to update, just return.
if (DT == 0 && LI == 0 && PI == 0)
return NewBB;
@@ -267,7 +267,7 @@
}
bool NewBBDominatesDestBB = true;
-
+
// Should we update DominatorTree information?
if (DT) {
DomTreeNode *TINode = DT->getNode(TIBB);
@@ -278,7 +278,7 @@
if (TINode) { // Don't break unreachable code!
DomTreeNode *NewBBNode = DT->addNewBlock(NewBB, TIBB);
DomTreeNode *DestBBNode = 0;
-
+
// If NewBBDominatesDestBB hasn't been computed yet, do so with DT.
if (!OtherPreds.empty()) {
DestBBNode = DT->getNode(DestBB);
@@ -289,7 +289,7 @@
}
OtherPreds.clear();
}
-
+
// If NewBBDominatesDestBB, then NewBB dominates DestBB, otherwise it
// doesn't dominate anything.
if (NewBBDominatesDestBB) {
From atrick at apple.com Mon Oct 3 22:50:45 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 04 Oct 2011 03:50:45 -0000
Subject: [llvm-commits] [llvm] r141059 - in /llvm/trunk:
include/llvm/Transforms/Utils/BasicBlockUtils.h
lib/Transforms/Scalar/LoopStrengthReduce.cpp
lib/Transforms/Utils/BreakCriticalEdges.cpp
test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
Message-ID: <20111004035045.F07DD2A6C12C@llvm.org>
Author: atrick
Date: Mon Oct 3 22:50:44 2011
New Revision: 141059
URL: http://llvm.org/viewvc/llvm-project?rev=141059&view=rev
Log:
LSR should avoid redundant edge splitting.
This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes LSR is not splitting edges "nicely"
Added:
llvm/trunk/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
Modified:
llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h
llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
Modified: llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h?rev=141059&r1=141058&r2=141059&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h (original)
+++ llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h Mon Oct 3 22:50:44 2011
@@ -109,7 +109,8 @@
/// to.
///
BasicBlock *SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum,
- Pass *P = 0, bool MergeIdenticalEdges = false);
+ Pass *P = 0, bool MergeIdenticalEdges = false,
+ bool DontDeleteUselessPHIs = false);
inline BasicBlock *SplitCriticalEdge(BasicBlock *BB, succ_iterator SI,
Pass *P = 0) {
@@ -136,13 +137,15 @@
/// described above.
inline BasicBlock *SplitCriticalEdge(BasicBlock *Src, BasicBlock *Dst,
Pass *P = 0,
- bool MergeIdenticalEdges = false) {
+ bool MergeIdenticalEdges = false,
+ bool DontDeleteUselessPHIs = false) {
TerminatorInst *TI = Src->getTerminator();
unsigned i = 0;
while (1) {
assert(i != TI->getNumSuccessors() && "Edge doesn't exist!");
if (TI->getSuccessor(i) == Dst)
- return SplitCriticalEdge(TI, i, P, MergeIdenticalEdges);
+ return SplitCriticalEdge(TI, i, P, MergeIdenticalEdges,
+ DontDeleteUselessPHIs);
++i;
}
}
Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=141059&r1=141058&r2=141059&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Mon Oct 3 22:50:44 2011
@@ -3677,7 +3677,9 @@
// Split the critical edge.
BasicBlock *NewBB = 0;
if (!Parent->isLandingPad()) {
- NewBB = SplitCriticalEdge(BB, Parent, P);
+ NewBB = SplitCriticalEdge(BB, Parent, P,
+ /*MergeIdenticalEdges=*/true,
+ /*DontDeleteUselessPhis=*/true);
} else {
SmallVector NewBBs;
SplitLandingPadPredecessors(Parent, BB, "", "", P, NewBBs);
Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=141059&r1=141058&r2=141059&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Mon Oct 3 22:50:44 2011
@@ -167,7 +167,8 @@
/// to.
///
BasicBlock *llvm::SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum,
- Pass *P, bool MergeIdenticalEdges) {
+ Pass *P, bool MergeIdenticalEdges,
+ bool DontDeleteUselessPhis) {
if (!isCriticalEdge(TI, SuccNum, MergeIdenticalEdges)) return 0;
assert(!isa(TI) &&
@@ -224,7 +225,7 @@
if (TI->getSuccessor(i) != DestBB) continue;
// Remove an entry for TIBB from DestBB phi nodes.
- DestBB->removePredecessor(TIBB);
+ DestBB->removePredecessor(TIBB, DontDeleteUselessPhis);
// We found another edge to DestBB, go to NewBB instead.
TI->setSuccessor(i, NewBB);
Added: llvm/trunk/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll?rev=141059&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll (added)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll Mon Oct 3 22:50:44 2011
@@ -0,0 +1,43 @@
+; RUN: opt -loop-reduce -S < %s | FileCheck %s
+;
+; Test LSR's use of SplitCriticalEdge during phi rewriting.
+; Verify that identical edges are merged. rdar://problem/6453893
+
+target triple = "x86-apple-darwin"
+
+; CHECK: @test
+; CHECK: bb89:
+; CHECK: phi i8* [ %lsr.iv.next1, %bbA.bb89_crit_edge ], [ %lsr.iv.next1, %bbB.bb89_crit_edge ]{{$}}
+
+define i8* @test() {
+entry:
+ br label %loop
+
+loop:
+ %rec = phi i32 [ %next, %loop ], [ 0, %entry ]
+ %next = add i32 %rec, 1
+ %tmp75 = getelementptr i8* null, i32 %next
+ br i1 false, label %loop, label %loopexit
+
+loopexit:
+ br i1 false, label %bbA, label %bbB
+
+bbA:
+ switch i32 0, label %bb89 [
+ i32 47, label %bb89
+ i32 58, label %bb89
+ ]
+
+bbB:
+ switch i8 0, label %bb89 [
+ i8 47, label %bb89
+ i8 58, label %bb89
+ ]
+
+bb89:
+ %tmp75phi = phi i8* [ %tmp75, %bbA ], [ %tmp75, %bbA ], [ %tmp75, %bbA ], [ %tmp75, %bbB ], [ %tmp75, %bbB ], [ %tmp75, %bbB ]
+ br label %exit
+
+exit:
+ ret i8* %tmp75phi
+}
From nicholas at mxc.ca Tue Oct 4 01:23:06 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 03 Oct 2011 23:23:06 -0700
Subject: [llvm-commits] patch: chrec * chrec = chrec.
In-Reply-To: <20111003232726.GA13292@britannica.bec.de>
References: <4E88F8E3.3050506@mxc.ca> <20111003205157.GA10434@britannica.bec.de>
<20111003232726.GA13292@britannica.bec.de>
Message-ID: <4E8AA64A.9040505@mxc.ca>
Joerg Sonnenberger wrote:
> On Mon, Oct 03, 2011 at 02:10:45PM -0700, Nick Lewycky wrote:
>> On 3 October 2011 13:51, Joerg Sonnenberger wrote:
>>> What exactly is the desired behavior in case of overflow?
>>> E.g. do you want to get C(n,k) % (UINTMAX + 1)? In that case, your
>>> formula doesn't compute correct results.
>>>
>>
>> In overflow the return value is garbage and Overflow is set. This method
>> deserves a comment.
>
>> From IRC: since n is supposed to be small, it might be better to just
> check for n<= 34 and consider it as overflow otherwise. Essentially,
> that's the largest number for which C(2n,n)< 2**32. In theory, it would
> be possible to compute C(n,k) in the finite field by eliminating the
> factors 2 in the divisor and implementing the division using the
> multiplicative inverse at the end. That's quite a bit more work though.
I tried the simple trick of pulling out 2's before the multiple/divide
in Choose() and that only helped a little; in all the cases I could
find, the actually loop optimization being performed was guaranteed to
overflow on some other Choose(n, k) computation it would do later.
It's not clear to me how using multiplicative inverses helps? Can I take
each term in the denominator (the terms in k!) and take the inverse of
each, and just turn them all into multiplies?
For now I'm planning to go ahead with the implementation of Choose()
as-is, then we can change it in subsequent patches.
Nick
From craig.topper at gmail.com Tue Oct 4 01:30:56 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Tue, 04 Oct 2011 06:30:56 -0000
Subject: [llvm-commits] [llvm] r141065 - in /llvm/trunk:
lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
lib/Target/X86/MCTargetDesc/X86BaseInfo.h lib/Target/X86/X86InstrFormats.td
lib/Target/X86/X86InstrSSE.td test/MC/Disassembler/X86/simple-tests.txt
test/MC/Disassembler/X86/x86-32.txt
utils/TableGen/X86DisassemblerTables.cpp
utils/TableGen/X86DisassemblerTables.h
utils/TableGen/X86RecognizableInstr.cpp
utils/TableGen/X86RecognizableInstr.h
Message-ID: <20111004063056.6B762312800A@llvm.org>
Author: ctopper
Date: Tue Oct 4 01:30:42 2011
New Revision: 141065
URL: http://llvm.org/viewvc/llvm-project?rev=141065&view=rev
Log:
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
Modified:
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
llvm/trunk/lib/Target/X86/X86InstrFormats.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
llvm/trunk/utils/TableGen/X86DisassemblerTables.h
llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
llvm/trunk/utils/TableGen/X86RecognizableInstr.h
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c?rev=141065&r1=141064&r2=141065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c Tue Oct 4 01:30:42 2011
@@ -767,8 +767,6 @@
break;
}
- if (insn->mode == MODE_64BIT && wFromVEX3of3(insn->vexPrefix[2]))
- attrMask |= ATTR_REXW;
if (lFromVEX3of3(insn->vexPrefix[2]))
attrMask |= ATTR_VEXL;
}
@@ -793,23 +791,55 @@
}
}
else {
- if (insn->rexPrefix & 0x08)
- attrMask |= ATTR_REXW;
-
if (isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation))
attrMask |= ATTR_OPSIZE;
else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation))
attrMask |= ATTR_XS;
else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation))
attrMask |= ATTR_XD;
-
}
+ if (insn->rexPrefix & 0x08)
+ attrMask |= ATTR_REXW;
+
if (getIDWithAttrMask(&instructionID, insn, attrMask))
return -1;
/* The following clauses compensate for limitations of the tables. */
+ if ((attrMask & ATTR_VEXL) && (attrMask & ATTR_REXW)) {
+ /*
+ * Some VEX instructions ignore the L-bit, but use the W-bit. Normally L-bit
+ * has precedence since there are no L-bit with W-bit entries in the tables.
+ * So if the L-bit isn't significant we should use the W-bit instead.
+ */
+
+ const struct InstructionSpecifier *spec;
+ uint16_t instructionIDWithWBit;
+ const struct InstructionSpecifier *specWithWBit;
+
+ spec = specifierForUID(instructionID);
+
+ if (getIDWithAttrMask(&instructionIDWithWBit,
+ insn,
+ (attrMask & (~ATTR_VEXL)) | ATTR_REXW)) {
+ insn->instructionID = instructionID;
+ insn->spec = spec;
+ return 0;
+ }
+
+ specWithWBit = specifierForUID(instructionIDWithWBit);
+
+ if (instructionID != instructionIDWithWBit) {
+ insn->instructionID = instructionIDWithWBit;
+ insn->spec = specWithWBit;
+ } else {
+ insn->instructionID = instructionID;
+ insn->spec = spec;
+ }
+ return 0;
+ }
+
if ((attrMask & ATTR_XD) && (attrMask & ATTR_REXW)) {
/*
* Although for SSE instructions it is usually necessary to treat REX.W+F2
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h?rev=141065&r1=141064&r2=141065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h Tue Oct 4 01:30:42 2011
@@ -107,7 +107,7 @@
ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\
- ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XS prefix")\
+ ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\
ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize")
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h?rev=141065&r1=141064&r2=141065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h Tue Oct 4 01:30:42 2011
@@ -398,13 +398,17 @@
/// field marked when using a f256 memory references.
VEX_L = 1U << 4,
+ // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX
+ // prefix. Usually used for scalar instructions. Needed by disassembler.
+ VEX_LIG = 1U << 5,
+
/// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
/// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
/// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
/// storing a classifier in the imm8 field. To simplify our implementation,
/// we handle this by storeing the classifier in the opcode field and using
/// this flag to indicate that the encoder should do the wacky 3DNow! thing.
- Has3DNow0F0FOpcode = 1U << 5
+ Has3DNow0F0FOpcode = 1U << 6
};
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=141065&r1=141064&r2=141065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Tue Oct 4 01:30:42 2011
@@ -113,6 +113,7 @@
class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
class VEX_L { bit hasVEX_L = 1; }
+class VEX_LIG { bit ignoresVEX_L = 1; }
class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
class X86Inst opcod, Format f, ImmType i, dag outs, dag ins,
@@ -150,6 +151,7 @@
bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
// to be encoded in a immediate field?
bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
+ bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
// TSFlags layout should be kept in sync with X86InstrInfo.h.
@@ -169,7 +171,8 @@
let TSFlags{35} = hasVEX_4VPrefix;
let TSFlags{36} = hasVEX_i8ImmReg;
let TSFlags{37} = hasVEX_L;
- let TSFlags{38} = has3DNow0F0FOpcode;
+ let TSFlags{38} = ignoresVEX_L;
+ let TSFlags{39} = has3DNow0F0FOpcode;
}
class PseudoI pattern>
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=141065&r1=141064&r2=141065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Oct 4 01:30:42 2011
@@ -342,34 +342,38 @@
// AVX
def VMOVSSrr : sse12_move_rr, XS, VEX_4V;
+ "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
+ VEX_LIG;
def VMOVSDrr : sse12_move_rr, XD, VEX_4V;
+ "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
+ VEX_LIG;
// For the disassembler
let isCodeGenOnly = 1 in {
def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
(ins VR128:$src1, FR32:$src2),
"movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
- XS, VEX_4V;
+ XS, VEX_4V, VEX_LIG;
def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
(ins VR128:$src1, FR64:$src2),
"movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
- XD, VEX_4V;
+ XD, VEX_4V, VEX_LIG;
}
let canFoldAsLoad = 1, isReMaterializable = 1 in {
- def VMOVSSrm : sse12_move_rm, XS, VEX;
+ def VMOVSSrm : sse12_move_rm, XS, VEX,
+ VEX_LIG;
let AddedComplexity = 20 in
- def VMOVSDrm : sse12_move_rm, XD, VEX;
+ def VMOVSDrm : sse12_move_rm, XD, VEX,
+ VEX_LIG;
}
def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
"movss\t{$src, $dst|$dst, $src}",
- [(store FR32:$src, addr:$dst)]>, XS, VEX;
+ [(store FR32:$src, addr:$dst)]>, XS, VEX, VEX_LIG;
def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
"movsd\t{$src, $dst|$dst, $src}",
- [(store FR64:$src, addr:$dst)]>, XD, VEX;
+ [(store FR64:$src, addr:$dst)]>, XD, VEX, VEX_LIG;
// SSE1 & 2
let Constraints = "$src1 = $dst" in {
@@ -1344,30 +1348,32 @@
}
defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
- "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
+ "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
+ VEX_LIG;
defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
"cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
- VEX_W;
+ VEX_W, VEX_LIG;
defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
- "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
+ "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX,
+ VEX_LIG;
defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
"cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
- VEX, VEX_W;
+ VEX, VEX_W, VEX_LIG;
// The assembler can recognize rr 64-bit instructions by seeing a rxx
// register, but the same isn't true when only using memory operands,
// provide other assembly "l" and "q" forms to address this explicitly
// where appropriate to do so.
defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
- VEX_4V;
+ VEX_4V, VEX_LIG;
defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
- VEX_4V, VEX_W;
+ VEX_4V, VEX_W, VEX_LIG;
defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
- VEX_4V;
+ VEX_4V, VEX_LIG;
defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
- VEX_4V;
+ VEX_4V, VEX_LIG;
defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
- VEX_4V, VEX_W;
+ VEX_4V, VEX_W, VEX_LIG;
let Predicates = [HasAVX] in {
def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
@@ -1447,9 +1453,10 @@
// intructions that only match with the intrinsic form, why create duplicates
// to let them be recognized by the assembler?
defm VCVTSD2SI : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
- "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
+ "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_LIG;
defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
- "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
+ "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W,
+ VEX_LIG;
defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
f128mem, load, "cvtsd2si{l}">, XD;
@@ -1509,10 +1516,11 @@
let Pattern = [] in {
defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
- "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
+ "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS,
+ VEX, VEX_LIG;
defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
"cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
- VEX_W;
+ VEX_W, VEX_LIG;
defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
"cvtdq2ps\t{$src, $dst|$dst, $src}",
SSEPackedSingle>, TB, VEX;
@@ -1559,12 +1567,12 @@
def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
(ins FR64:$src1, FR64:$src2),
"cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
- VEX_4V;
+ VEX_4V, VEX_LIG;
let mayLoad = 1 in
def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
(ins FR64:$src1, f64mem:$src2),
"vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
+ []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
Requires<[HasAVX]>;
@@ -1589,12 +1597,12 @@
def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
(ins FR32:$src1, FR32:$src2),
"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- []>, XS, Requires<[HasAVX]>, VEX_4V;
+ []>, XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
let mayLoad = 1 in
def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
(ins FR32:$src1, f32mem:$src2),
"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
+ []>, XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
let Predicates = [HasAVX] in {
def : Pat<(f64 (fextend FR32:$src)),
@@ -1986,11 +1994,11 @@
defm VCMPSS : sse12_cmp_scalar,
- XS, VEX_4V;
+ XS, VEX_4V, VEX_LIG;
defm VCMPSD : sse12_cmp_scalar,
- XD, VEX_4V;
+ XD, VEX_4V, VEX_LIG;
let Constraints = "$src1 = $dst" in {
defm CMPSS : sse12_cmp_scalar, TB, VEX;
+ "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
- "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
+ "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
+ VEX_LIG;
let Pattern = [] in {
defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
- "comiss", SSEPackedSingle>, TB, VEX;
+ "comiss", SSEPackedSingle>, TB, VEX,
+ VEX_LIG;
defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
- "comisd", SSEPackedDouble>, TB, OpSize, VEX;
+ "comisd", SSEPackedDouble>, TB, OpSize, VEX,
+ VEX_LIG;
}
defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
@@ -2744,32 +2755,32 @@
// Binary Arithmetic instructions
defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
- basic_sse12_fp_binop_s_int<0x58, "add", 0>,
- basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
+ basic_sse12_fp_binop_s_int<0x58, "add", 0>, VEX_4V, VEX_LIG;
+defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
- basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
- basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
+ basic_sse12_fp_binop_s_int<0x59, "mul", 0>, VEX_4V, VEX_LIG;
+defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
let isCommutable = 0 in {
defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
- basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
- basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
+ basic_sse12_fp_binop_s_int<0x5C, "sub", 0>, VEX_4V, VEX_LIG;
+ defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
- basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
- basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
+ basic_sse12_fp_binop_s_int<0x5E, "div", 0>, VEX_4V, VEX_LIG;
+ defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
- basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
- basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
+ basic_sse12_fp_binop_s_int<0x5F, "max", 0>, VEX_4V, VEX_LIG;
+ defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
- basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
- basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
+ basic_sse12_fp_binop_s_int<0x5D, "min", 0>, VEX_4V, VEX_LIG;
+ defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
basic_sse12_fp_binop_p_y_int<0x5D, "min">,
basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
@@ -2967,7 +2978,7 @@
let Predicates = [HasAVX] in {
// Square root.
defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
- sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
+ sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
@@ -2981,13 +2992,13 @@
// Reciprocal approximations. Note that these typically require refinement
// in order to obtain suitable precision.
- defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
+ defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
- defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
+ defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
@@ -5612,14 +5623,14 @@
int_x86_avx_round_pd_256>, VEX;
defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
int_x86_sse41_round_ss,
- int_x86_sse41_round_sd, 0>, VEX_4V;
+ int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
// Instructions for the assembler
defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
VEX;
defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
VEX;
- defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
+ defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V, VEX_LIG;
}
defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=141065&r1=141064&r2=141065&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Tue Oct 4 01:30:42 2011
@@ -395,3 +395,30 @@
# CHECK: rdrandq %rax
0x48 0x0f 0xc7 0xf0
+
+# CHECK: vroundss $0, %xmm0, %xmm0, %xmm0
+0xc4 0xe3 0x7d 0x0a 0xc0 0x00
+
+# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0
+0xc4 0xe3 0x7d 0x0b 0xc0 0x00
+
+# CHECK: vcvtsd2si %xmm0, %eax
+0xc4 0xe1 0x7f 0x2d 0xc0
+
+# CHECK: vcvtsd2si %xmm0, %rax
+0xc4 0xe1 0xff 0x2d 0xc0
+
+# CHECK: vucomisd %xmm1, %xmm0
+0xc5 0xfd 0x2e 0xc1
+
+# CHECK: vucomiss %xmm1, %xmm0
+0xc5 0xfc 0x2e 0xc1
+
+# CHECK: vcomisd %xmm1, %xmm0
+0xc5 0xfd 0x2f 0xc1
+
+# CHECK: vcomiss %xmm1, %xmm0
+0xc5 0xfc 0x2f 0xc1
+
+# CHECK: vaddss %xmm1, %xmm0, %xmm0
+0xc5 0xfe 0x58 0xc1
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=141065&r1=141064&r2=141065&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Tue Oct 4 01:30:42 2011
@@ -405,3 +405,30 @@
# CHECK: rdrandl %eax
0x0f 0xc7 0xf0
+
+# CHECK: vroundss $0, %xmm0, %xmm0, %xmm0
+0xc4 0xe3 0x7d 0x0a 0xc0 0x00
+
+# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0
+0xc4 0xe3 0x7d 0x0b 0xc0 0x00
+
+# CHECK: vcvtsd2si %xmm0, %eax
+0xc4 0xe1 0x7f 0x2d 0xc0
+
+# CHECK: vcvtsd2si %xmm0, %eax
+0xc4 0xe1 0xff 0x2d 0xc0
+
+# CHECK: vucomisd %xmm1, %xmm0
+0xc5 0xfd 0x2e 0xc1
+
+# CHECK: vucomiss %xmm1, %xmm0
+0xc5 0xfc 0x2e 0xc1
+
+# CHECK: vcomisd %xmm1, %xmm0
+0xc5 0xfd 0x2f 0xc1
+
+# CHECK: vcomiss %xmm1, %xmm0
+0xc5 0xfc 0x2f 0xc1
+
+# CHECK: vaddss %xmm1, %xmm0, %xmm0
+0xc5 0xfe 0x58 0xc1
Modified: llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp?rev=141065&r1=141064&r2=141065&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp (original)
+++ llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp Tue Oct 4 01:30:42 2011
@@ -32,7 +32,8 @@
/// @param parent - The class that may be the superset
/// @return - True if child is a subset of parent, false otherwise.
static inline bool inheritsFrom(InstructionContext child,
- InstructionContext parent) {
+ InstructionContext parent,
+ bool VEX_LIG = false) {
if (child == parent)
return true;
@@ -68,33 +69,29 @@
case IC_64BIT_XD_OPSIZE:
return false;
case IC_64BIT_REXW_XD:
- return false;
case IC_64BIT_REXW_XS:
- return false;
case IC_64BIT_REXW_OPSIZE:
return false;
case IC_VEX:
- return inheritsFrom(child, IC_VEX_W);
+ return inheritsFrom(child, IC_VEX_W) ||
+ (VEX_LIG && inheritsFrom(child, IC_VEX_L));
case IC_VEX_XS:
- return inheritsFrom(child, IC_VEX_W_XS);
+ return inheritsFrom(child, IC_VEX_W_XS) ||
+ (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
case IC_VEX_XD:
- return inheritsFrom(child, IC_VEX_W_XD);
+ return inheritsFrom(child, IC_VEX_W_XD) ||
+ (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
case IC_VEX_OPSIZE:
- return inheritsFrom(child, IC_VEX_W_OPSIZE);
+ return inheritsFrom(child, IC_VEX_W_OPSIZE) ||
+ (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
case IC_VEX_W:
- return false;
case IC_VEX_W_XS:
- return false;
case IC_VEX_W_XD:
- return false;
case IC_VEX_W_OPSIZE:
return false;
case IC_VEX_L:
- return false;
case IC_VEX_L_XS:
- return false;
case IC_VEX_L_XD:
- return false;
case IC_VEX_L_OPSIZE:
return false;
default:
@@ -651,7 +648,8 @@
uint8_t opcode,
const ModRMFilter &filter,
InstrUID uid,
- bool is32bit) {
+ bool is32bit,
+ bool ignoresVEX_L) {
unsigned index;
ContextDecision &decision = *Tables[type];
@@ -661,7 +659,7 @@
continue;
if (inheritsFrom((InstructionContext)index,
- InstructionSpecifiers[uid].insnContext))
+ InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],
filter,
uid,
Modified: llvm/trunk/utils/TableGen/X86DisassemblerTables.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86DisassemblerTables.h?rev=141065&r1=141064&r2=141065&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86DisassemblerTables.h (original)
+++ llvm/trunk/utils/TableGen/X86DisassemblerTables.h Tue Oct 4 01:30:42 2011
@@ -261,12 +261,14 @@
/// correspond to the desired instruction.
/// @param uid - The unique ID of the instruction.
/// @param is32bit - Instructon is only 32-bit
+ /// @param ignoresVEX_L - Instruction ignores VEX.L
void setTableFields(OpcodeType type,
InstructionContext insnContext,
uint8_t opcode,
const ModRMFilter &filter,
InstrUID uid,
- bool is32bit);
+ bool is32bit,
+ bool ignoresVEX_L);
/// specForUID - Returns the instruction specifier for a given unique
/// instruction ID. Used when resolving collisions.
Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=141065&r1=141064&r2=141065&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Tue Oct 4 01:30:42 2011
@@ -217,6 +217,7 @@
HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
+ IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
@@ -284,7 +285,9 @@
InstructionContext insnContext;
if (HasVEX_4VPrefix || HasVEXPrefix) {
- if (HasOpSizePrefix && HasVEX_LPrefix)
+ if (HasVEX_LPrefix && HasVEX_WPrefix)
+ llvm_unreachable("Don't support VEX.L and VEX.W together");
+ else if (HasOpSizePrefix && HasVEX_LPrefix)
insnContext = IC_VEX_L_OPSIZE;
else if (HasOpSizePrefix && HasVEX_WPrefix)
insnContext = IC_VEX_W_OPSIZE;
@@ -957,7 +960,7 @@
insnContext(),
currentOpcode,
*filter,
- UID, Is32Bit);
+ UID, Is32Bit, IgnoresVEX_L);
Spec->modifierType = MODIFIER_OPCODE;
Spec->modifierBase = opcodeToSet;
@@ -967,14 +970,14 @@
insnContext(),
opcodeToSet,
*filter,
- UID, Is32Bit);
+ UID, Is32Bit, IgnoresVEX_L);
}
} else {
tables.setTableFields(opcodeType,
insnContext(),
opcodeToSet,
*filter,
- UID, Is32Bit);
+ UID, Is32Bit, IgnoresVEX_L);
Spec->modifierType = MODIFIER_NONE;
Spec->modifierBase = opcodeToSet;
Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.h?rev=141065&r1=141064&r2=141065&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.h (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.h Tue Oct 4 01:30:42 2011
@@ -60,6 +60,8 @@
bool HasVEX_WPrefix;
/// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
bool HasVEX_LPrefix;
+ // The ignoreVEX_L field from the record
+ bool IgnoresVEX_L;
/// The hasLockPrefix field from the record
bool HasLockPrefix;
/// The isCodeGenOnly filed from the record
From nicholas at mxc.ca Tue Oct 4 01:51:27 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 04 Oct 2011 06:51:27 -0000
Subject: [llvm-commits] [llvm] r141066 - in /llvm/trunk:
include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp
unittests/Analysis/ScalarEvolutionTest.cpp
Message-ID: <20111004065128.2B4BB312800A@llvm.org>
Author: nicholas
Date: Tue Oct 4 01:51:26 2011
New Revision: 141066
URL: http://llvm.org/viewvc/llvm-project?rev=141066&view=rev
Log:
The product of two chrec's can always be represented as a chrec.
Modified:
llvm/trunk/include/llvm/Analysis/ScalarEvolution.h
llvm/trunk/lib/Analysis/ScalarEvolution.cpp
llvm/trunk/unittests/Analysis/ScalarEvolutionTest.cpp
Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=141066&r1=141065&r2=141066&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original)
+++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Tue Oct 4 01:51:26 2011
@@ -588,6 +588,14 @@
Ops.push_back(RHS);
return getMulExpr(Ops, Flags);
}
+ const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
+ SCEV::NoWrapFlags Flags = SCEV::FlagAnyWrap) {
+ SmallVector Ops;
+ Ops.push_back(Op0);
+ Ops.push_back(Op1);
+ Ops.push_back(Op2);
+ return getMulExpr(Ops, Flags);
+ }
const SCEV *getUDivExpr(const SCEV *LHS, const SCEV *RHS);
const SCEV *getAddRecExpr(const SCEV *Start, const SCEV *Step,
const Loop *L, SCEV::NoWrapFlags Flags);
Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=141066&r1=141065&r2=141066&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Oct 4 01:51:26 2011
@@ -1812,6 +1812,38 @@
return S;
}
+static uint64_t umul_ov(uint64_t i, uint64_t j, bool &Overflow) {
+ uint64_t k = i*j;
+ if (j > 1 && k / j != i) Overflow = true;
+ return k;
+}
+
+/// Compute the result of "n choose k", the binomial coefficient. If an
+/// intermediate computation overflows, Overflow will be set and the return will
+/// be garbage. Overflow is not cleared on absense of overflow.
+static uint64_t Choose(uint64_t n, uint64_t k, bool &Overflow) {
+ // We use the multiplicative formula:
+ // n(n-1)(n-2)...(n-(k-1)) / k(k-1)(k-2)...1 .
+ // At each iteration, we take the n-th term of the numeral and divide by the
+ // (k-n)th term of the denominator. This division will always produce an
+ // integral result, and helps reduce the chance of overflow in the
+ // intermediate computations. However, we can still overflow even when the
+ // final result would fit.
+
+ if (n == 0 || n == k) return 1;
+ if (k > n) return 0;
+
+ if (k > n/2)
+ k = n-k;
+
+ uint64_t r = 1;
+ for (uint64_t i = 1; i <= k; ++i) {
+ r = umul_ov(r, n-(i-1), Overflow);
+ r /= i;
+ }
+ return r;
+}
+
/// getMulExpr - Get a canonical multiply expression, or something simpler if
/// possible.
const SCEV *ScalarEvolution::getMulExpr(SmallVectorImpl &Ops,
@@ -1987,53 +2019,61 @@
for (unsigned OtherIdx = Idx+1;
OtherIdx < Ops.size() && isa(Ops[OtherIdx]);
++OtherIdx) {
- bool Retry = false;
if (AddRecLoop == cast(Ops[OtherIdx])->getLoop()) {
- // {A,+,B} * {C,+,D} --> {A*C,+,A*D + B*C + B*D,+,2*B*D}
+ // {A1,+,A2,+,...,+,An} * {B1,+,B2,+,...,+,Bn}
+ // = {x=1 in [ sum y=x..2x [ sum z=max(y-x, y-n)..min(x,n) [
+ // choose(x, 2x)*choose(2x-y, x-z)*A_{y-z}*B_z
+ // ]]],+,...up to x=2n}.
+ // Note that the arguments to choose() are always integers with values
+ // known at compile time, never SCEV objects.
//
- // {A,+,B} * {C,+,D} = A+It*B * C+It*D = A*C + (A*D + B*C)*It + B*D*It^2
- // Given an equation of the form x + y*It + z*It^2 (above), we want to
- // express it in terms of {X,+,Y,+,Z}.
- // {X,+,Y,+,Z} = X + Y*It + Z*(It^2 - It)/2.
- // Rearranging, X = x, Y = y+z, Z = 2z.
- //
- // x = A*C, y = (A*D + B*C), z = B*D.
- // Therefore X = A*C, Y = A*D + B*C + B*D and Z = 2*B*D.
+ // The implementation avoids pointless extra computations when the two
+ // addrec's are of different length (mathematically, it's equivalent to
+ // an infinite stream of zeros on the right).
+ bool OpsModified = false;
for (; OtherIdx != Ops.size() && isa(Ops[OtherIdx]);
++OtherIdx)
if (const SCEVAddRecExpr *OtherAddRec =
dyn_cast(Ops[OtherIdx]))
if (OtherAddRec->getLoop() == AddRecLoop) {
- const SCEV *A = AddRec->getStart();
- const SCEV *B = AddRec->getStepRecurrence(*this);
- const SCEV *C = OtherAddRec->getStart();
- const SCEV *D = OtherAddRec->getStepRecurrence(*this);
- const SCEV *NewStart = getMulExpr(A, C);
- const SCEV *BD = getMulExpr(B, D);
- const SCEV *NewStep = getAddExpr(getMulExpr(A, D),
- getMulExpr(B, C), BD);
- const SCEV *NewSecondOrderStep =
- getMulExpr(BD, getConstant(BD->getType(), 2));
-
- // This can happen when AddRec or OtherAddRec have >3 operands.
- // TODO: support these add-recs.
- if (isLoopInvariant(NewStart, AddRecLoop) &&
- isLoopInvariant(NewStep, AddRecLoop) &&
- isLoopInvariant(NewSecondOrderStep, AddRecLoop)) {
- SmallVector AddRecOps;
- AddRecOps.push_back(NewStart);
- AddRecOps.push_back(NewStep);
- AddRecOps.push_back(NewSecondOrderStep);
+ bool Overflow = false;
+ Type *Ty = AddRec->getType();
+ bool LargerThan64Bits = getTypeSizeInBits(Ty) > 64;
+ SmallVector AddRecOps;
+ for (int x = 0, xe = AddRec->getNumOperands() +
+ OtherAddRec->getNumOperands() - 1;
+ x != xe && !Overflow; ++x) {
+ const SCEV *Term = getConstant(Ty, 0);
+ for (int y = x, ye = 2*x+1; y != ye && !Overflow; ++y) {
+ uint64_t Coeff1 = Choose(x, 2*x - y, Overflow);
+ for (int z = std::max(y-x, y-(int)AddRec->getNumOperands()+1),
+ ze = std::min(x+1, (int)OtherAddRec->getNumOperands());
+ z < ze && !Overflow; ++z) {
+ uint64_t Coeff2 = Choose(2*x - y, x-z, Overflow);
+ uint64_t Coeff;
+ if (LargerThan64Bits)
+ Coeff = umul_ov(Coeff1, Coeff2, Overflow);
+ else
+ Coeff = Coeff1*Coeff2;
+ const SCEV *CoeffTerm = getConstant(Ty, Coeff);
+ const SCEV *Term1 = AddRec->getOperand(y-z);
+ const SCEV *Term2 = OtherAddRec->getOperand(z);
+ Term = getAddExpr(Term, getMulExpr(CoeffTerm, Term1,Term2));
+ }
+ }
+ AddRecOps.push_back(Term);
+ }
+ if (!Overflow) {
const SCEV *NewAddRec = getAddRecExpr(AddRecOps,
AddRec->getLoop(),
SCEV::FlagAnyWrap);
if (Ops.size() == 2) return NewAddRec;
Ops[Idx] = AddRec = cast(NewAddRec);
Ops.erase(Ops.begin() + OtherIdx); --OtherIdx;
- Retry = true;
+ OpsModified = true;
}
}
- if (Retry)
+ if (OpsModified)
return getMulExpr(Ops);
}
}
Modified: llvm/trunk/unittests/Analysis/ScalarEvolutionTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Analysis/ScalarEvolutionTest.cpp?rev=141066&r1=141065&r2=141066&view=diff
==============================================================================
--- llvm/trunk/unittests/Analysis/ScalarEvolutionTest.cpp (original)
+++ llvm/trunk/unittests/Analysis/ScalarEvolutionTest.cpp Tue Oct 4 01:51:26 2011
@@ -8,20 +8,35 @@
//===----------------------------------------------------------------------===//
#include
+#include
#include