Architecture	OS	compiler
x86-32	Mac OS 10.5	gcc 4.0.1
x86-32	Linux	gcc 4.2.X, gcc 4.3.X
x86-32	FreeBSD	gcc 4.2.X
x86-32	mingw	gcc 3.4.5
x86-64	Mac OS 10.5	gcc 4.0.1
x86-64	Linux	gcc 4.2.X, gcc 4.3.X
x86-64	FreeBSD	gcc 4.2.X
Architecture	OS	compiler
x86-32	Mac OS 10.5	gcc 4.0.1
x86-32	Linux	gcc 4.2.X, gcc 4.3.X
x86-32	FreeBSD	gcc 4.2.X
x86-32	mingw	gcc 3.4.5
x86-64	Mac OS 10.5	gcc 4.0.1
x86-64	Linux	gcc 4.2.X, gcc 4.3.X
x86-64	FreeBSD	gcc 4.2.X

Architecture	OS	llvm-gcc baseline	clang baseline	tests
x86-32	Linux	last release	last release	llvm dejagnu, clang tests, test-suite (including spec)
x86-32	FreeBSD	none	last release	llvm dejagnu, clang tests, test-suite
x86-32	mingw	last release	none	QT
x86-64	Mac OS 10.X	last release	last release	llvm dejagnu, clang tests, test-suite (including spec)
x86-64	Linux	last release	last release	llvm dejagnu, clang tests, test-suite (including spec)
x86-64	FreeBSD	none	last release	llvm dejagnu, clang tests, test-suite
Architecture	OS	clang baseline	tests
x86-32	Linux	last release	llvm dejagnu, clang tests, test-suite (including spec)
x86-32	FreeBSD	last release	llvm dejagnu, clang tests, test-suite
x86-32	mingw	none	QT
x86-64	Mac OS 10.X	last release	llvm dejagnu, clang tests, test-suite (including spec)
x86-64	Linux	last release	llvm dejagnu, clang tests, test-suite (including spec)
x86-64	FreeBSD	last release	llvm dejagnu, clang tests, test-suite

The LLVM demo page must be updated to use the new release. This consists of - using the new llvm-gcc binary and building LLVM.

+ using the new clang binary and building LLVM.

Update the LLVM Website

@@ -574,8 +529,8 @@

Create a new subdirectory X.Y in the releases directory.

Commit the llvm, test-suite, llvm-gcc source, - clang source, clang binaries, and llvm-gcc +

Commit the llvm, test-suite, clang source, + clang binaries, dragonegg source, and dragonegg binaries in this new directory.

Copy and commit the llvm/docs and LICENSE.txt files From zwarich at apple.com Mon Oct 17 15:31:39 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Mon, 17 Oct 2011 13:31:39 -0700 Subject: [llvm-commits] [llvm] r142111 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td In-Reply-To: <397F0F35-8800-464E-A35F-0739331CA355@googlemail.com> References: <20111016063810.67296312800A@llvm.org> <397F0F35-8800-464E-A35F-0739331CA355@googlemail.com> Message-ID: On Oct 16, 2011, at 2:32 AM, Benjamin Kramer wrote: > On 16.10.2011, at 08:38, Cameron Zwarich wrote: > >> Author: zwarich >> Date: Sun Oct 16 01:38:10 2011 >> New Revision: 142111 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=142111&view=rev >> Log: >> Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads. >> These missing flags show up as errors when running -verify-coalescing on >> test-suite. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=142111&r1=142110&r2=142111&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Sun Oct 16 01:38:10 2011 >> @@ -1321,6 +1321,8 @@ >> IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>; >> >> // Indexed stores >> + >> +let mayStore = 1, neverHasSideEffects = 1 in { >> def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb), >> (ins rGPR:$Rt, t2addrmode_imm8:$addr), >> AddrModeT2_i8, IndexModePre, IIC_iStore_iu, >> @@ -1397,7 +1399,7 @@ >> [(set GPRnopc:$Rn_wb, >> (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>; >> } >> - >> +} // mayStore = 1, neverHasSideEffects = 1 > > Hi Cameron, > > now I get warnings from tblgen: > > Warning: mayStore flag explicitly set on instruction 't2STRB_POST' but flag already inferred from pattern. > Warning: neverHasSideEffects set on instruction 't2STRB_POST' which already has a pattern > Warning: mayStore flag explicitly set on instruction 't2STRB_preidx' but flag already inferred from pattern. > Warning: neverHasSideEffects set on instruction 't2STRB_preidx' which already has a pattern > Warning: mayStore flag explicitly set on instruction 't2STRH_POST' but flag already inferred from pattern. > Warning: neverHasSideEffects set on instruction 't2STRH_POST' which already has a pattern > Warning: mayStore flag explicitly set on instruction 't2STRH_preidx' but flag already inferred from pattern. > Warning: neverHasSideEffects set on instruction 't2STRH_preidx' which already has a pattern > Warning: mayStore flag explicitly set on instruction 't2STR_POST' but flag already inferred from pattern. > Warning: neverHasSideEffects set on instruction 't2STR_POST' which already has a pattern > Warning: mayStore flag explicitly set on instruction 't2STR_preidx' but flag already inferred from pattern. > Warning: neverHasSideEffects set on instruction 't2STR_preidx' which already has a pattern I'll try to fix this in TableGen itself rather than mucking with the file to silence it. Cameron From isanbard at gmail.com Mon Oct 17 15:37:20 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 20:37:20 -0000 Subject: [llvm-commits] [llvm] r142245 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20111017203720.82E65312800A@llvm.org> Author: void Date: Mon Oct 17 15:37:20 2011 New Revision: 142245 URL: http://llvm.org/viewvc/llvm-project?rev=142245&view=rev Log: Add a call to EmitSjLjDispatchBlock. Once the intrinsics are marked as having a custom inserter, it will call this method to emit the dispatch table into the machine function. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142245&r1=142244&r2=142245&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Oct 17 15:37:20 2011 @@ -6223,6 +6223,14 @@ return BB; } + case ARM::Int_eh_sjlj_setjmp: + case ARM::Int_eh_sjlj_setjmp_nofp: + case ARM::tInt_eh_sjlj_setjmp: + case ARM::t2Int_eh_sjlj_setjmp: + case ARM::t2Int_eh_sjlj_setjmp_nofp: + EmitSjLjDispatchBlock(MI, BB); + return BB; + case ARM::ABS: case ARM::t2ABS: { // To insert an ABS instruction, we have to insert the From nadav.rotem at intel.com Mon Oct 17 15:37:43 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Mon, 17 Oct 2011 22:37:43 +0200 Subject: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ In-Reply-To: <84BE87AB-7185-4CF6-B0F4-D242762AA4A0@mac.com> References: <20111016203133.CC4E13128018@llvm.org> <1B579157-F0E8-45FB-A8E8-3D520ED36FC0@mac.com> <84BE87AB-7185-4CF6-B0F4-D242762AA4A0@mac.com> Message-ID: <6594DDFF12B03D4E89690887C248699402A2C887C6@hasmsx504.ger.corp.intel.com> Hi Owen, Thanks for looking at this. I restored the CHECKs and added some documentation. Let me explain the recent changes to the type-legalizer and how it affects the ARM backend. Previously the type-legalizer changed <2 x i16> into <4 x i16>. Currently, the type legalizer attempts to widen each element first. So <2 x i16> is promoted to <2 x i32>. Generally, this is a good change for ARM because it maps better to the sparse vector architectures (not to mention that it enables the use of NEON masks using vectors of i1's). Usually, the common types are better supported on vector architectures. Let me point out another example. Consider the following operation MUL v4i8; On x86, the llvm codegen would promote it to v16i8, only to discover that there is no v16i8 multiplication operation, and scalarize the operation to 16 scalar multiplications. So, as this example shows, promoting elements is beneficial in many cases. The new type-legalization generates new code sequences. For example: trunc store and anyext loads. I implemented fast load/store sequences for x86. Other targets also need to optimize the new sequences. I opened a bug report on this PR11158. Thanks, Nadav From: Owen Anderson [mailto:resistor at mac.com] Sent: Monday, October 17, 2011 19:42 To: Rotem, Nadav Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ On Oct 17, 2011, at 10:29 AM, Owen Anderson wrote: Nadav, On Oct 16, 2011, at 1:31 PM, Nadav Rotem wrote: Author: nadav Date: Sun Oct 16 15:31:33 2011 New Revision: 142152 ... Modified: llvm/trunk/test/CodeGen/ARM/vrev.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=142152&r1=142151&r2=142152&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrev.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vrev.ll Sun Oct 16 15:31:33 2011 @@ -150,9 +150,6 @@ ; vrev <4 x i16> should use VREV32 and not VREV64 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { -; CHECK: test_vrev64: -; CHECK: vext.16 -; CHECK: vrev32.16 entry: %0 = bitcast <4 x i16>* %source to <8 x i16>* %tmp2 = load <8 x i16>* %0, align 4 You've removed all the CHECK lines from this test, essentially disabling it. Please make sure it still works and add back correct CHECK lines. To follow up on my own post, it does not still work. The new generated code is MUCH worse than what is being checked for, involve extra stores rather than a shuffle instruction. Please fix this or re-disable this patch until it can be fixed. --Owen --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/e568e67e/attachment-0001.html From nadav.rotem at intel.com Mon Oct 17 15:41:41 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Mon, 17 Oct 2011 22:41:41 +0200 Subject: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ In-Reply-To: <4E9BFF45.2040609@nokia.com> References: <20111016203133.CC4E13128018@llvm.org> <4E9BFF45.2040609@nokia.com> Message-ID: <6594DDFF12B03D4E89690887C248699402A2C887C8@hasmsx504.ger.corp.intel.com> Kalle, You can disable this feature by setting the llc flag '-promote-elements=false'. I noticed that the SPU backend does not implement the vector SHL operation properly which makes SIGN_EXTEND_INREG very inefficient. Any chance that you fix this ? Thanks, Nadav -----Original Message----- From: Kalle Raiskila [mailto:kalle.raiskila at nokia.com] Sent: Monday, October 17, 2011 12:11 To: Rotem, Nadav Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ On 16/10/11 23:31, ext Nadav Rotem wrote: > Author: nadav > Date: Sun Oct 16 15:31:33 2011 > New Revision: 142152 > > URL: http://llvm.org/viewvc/llvm-project?rev=142152&view=rev > Log: > Enable element promotion type legalization by deafault. > Changed tests which assumed that vectors are legalized by widening them. How does one disable this per instruction/vectortype/backend? Because e.g. the runtime of this: > define %vec @test_add(%vec %param) > { > -;CHECK: a {{\$.}}, $3, $3 > +;CHECK: shufb > +;CHECK: addx > %1 = add %vec %param, %param > ;CHECK: bi $lr > ret %vec %1 > @@ -17,21 +18,14 @@ increased from 2 to 12 cycles when %vec is <2 x i32> thanks, kalle --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From benny.kra at googlemail.com Mon Oct 17 15:49:40 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 17 Oct 2011 20:49:40 -0000 Subject: [llvm-commits] [llvm] r142247 - /llvm/trunk/lib/Support/StringRef.cpp Message-ID: <20111017204940.E97A02A6C12C@llvm.org> Author: d0k Date: Mon Oct 17 15:49:40 2011 New Revision: 142247 URL: http://llvm.org/viewvc/llvm-project?rev=142247&view=rev Log: Fix handling of the From parameter in StringRef::find. Enable bounds checking to catch this kind of bug earlier. Modified: llvm/trunk/lib/Support/StringRef.cpp Modified: llvm/trunk/lib/Support/StringRef.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/StringRef.cpp?rev=142247&r1=142246&r2=142247&view=diff ============================================================================== --- llvm/trunk/lib/Support/StringRef.cpp (original) +++ llvm/trunk/lib/Support/StringRef.cpp Mon Oct 17 15:49:40 2011 @@ -153,19 +153,22 @@ return npos; } + if (From >= Length) + return npos; + // Build the bad char heuristic table, with uint8_t to reduce cache thrashing. uint8_t BadCharSkip[256]; std::memset(BadCharSkip, N, 256); for (unsigned i = 0; i != N-1; ++i) BadCharSkip[(uint8_t)Str[i]] = N-1-i; - unsigned Len = Length, Pos = min(From, Length); + unsigned Len = Length-From, Pos = From; while (Len >= N) { if (substr(Pos, N).equals(Str)) // See if this is the correct substring. return Pos; // Otherwise skip the appropriate number of bytes. - uint8_t Skip = BadCharSkip[(uint8_t)Data[Pos+N-1]]; + uint8_t Skip = BadCharSkip[(uint8_t)(*this)[Pos+N-1]]; Len -= Skip; Pos += Skip; } From dpatel at apple.com Mon Oct 17 16:00:00 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 17 Oct 2011 14:00:00 -0700 Subject: [llvm-commits] new .file directive In-Reply-To: References:

Message-ID: <7D66141B-90F9-4A28-9A3E-CB167D285975@apple.com> On Oct 14, 2011, at 7:10 PM, Nick Lewycky wrote: > > Please review! > > Index: lib/CodeGen/AsmPrinter/DwarfDebug.cpp > =================================================================== > --- lib/CodeGen/AsmPrinter/DwarfDebug.cpp (revision 142035) > +++ lib/CodeGen/AsmPrinter/DwarfDebug.cpp (working copy) > @@ -442,23 +442,21 @@ > if (FileName.empty()) > return GetOrCreateSourceID("", StringRef()); > > - // MCStream expects full path name as filename. > - if (!DirName.empty() && !sys::path::is_absolute(FileName)) { > - SmallString<128> FullPathName = DirName; > - sys::path::append(FullPathName, FileName); > - // Here FullPathName will be copied into StringMap by GetOrCreateSourceID. > - return GetOrCreateSourceID(StringRef(FullPathName), StringRef()); > - } > + unsigned SrcId = SourceIdMap.size()+1; > + std::pair SourceName = > + std::make_pair(FileName, DirName); > + std::pair, unsigned> Entry = > + make_pair(SourceName, SrcId); > > - StringMapEntry &Entry = SourceIdMap.GetOrCreateValue(FileName); > - if (Entry.getValue()) > - return Entry.getValue(); > + std::map, unsigned>::iterator I; > + bool NewlyInserted; > + tie(I, NewlyInserted) = SourceIdMap.insert(Entry); > + if (!NewlyInserted) > + return I->second; > > - unsigned SrcId = SourceIdMap.size(); > - Entry.setValue(SrcId); > - > // Print out a .file directive to specify files for .loc directives. > - Asm->OutStreamer.EmitDwarfFileDirective(SrcId, Entry.getKey()); > + Asm->OutStreamer.EmitDwarfFileDirective(SrcId, Entry.first.second, > + Entry.first.first); > > return SrcId; > } > Index: lib/CodeGen/AsmPrinter/DwarfDebug.h > =================================================================== > --- lib/CodeGen/AsmPrinter/DwarfDebug.h (revision 142035) > +++ lib/CodeGen/AsmPrinter/DwarfDebug.h (working copy) > @@ -26,6 +26,7 @@ > #include "llvm/ADT/UniqueVector.h" > #include "llvm/Support/Allocator.h" > #include "llvm/Support/DebugLoc.h" > +#include > > namespace llvm { > > @@ -207,9 +208,9 @@ > /// > std::vector Abbreviations; > > - /// SourceIdMap - Source id map, i.e. pair of directory id and source file > - /// id mapped to a unique id. > - StringMap SourceIdMap; > + /// SourceIdMap - Source id map, i.e. pair of source filename and directory > + /// mapped to a unique id. > + std::map, unsigned> SourceIdMap; > > /// StringPool - A String->Symbol mapping of strings used by indirect > /// references. Why do you need this change in DwarfDebug ? Why can't MCAsmStreamer split file and directly ? - Devang -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/54a76e32/attachment.html From grosbach at apple.com Mon Oct 17 16:00:11 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 17 Oct 2011 21:00:11 -0000 Subject: [llvm-commits] [llvm] r142248 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20111017210011.AECAD2A6C12C@llvm.org> Author: grosbach Date: Mon Oct 17 16:00:11 2011 New Revision: 142248 URL: http://llvm.org/viewvc/llvm-project?rev=142248&view=rev Log: Tidy up organization. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142248&r1=142247&r2=142248&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 17 16:00:11 2011 @@ -15,6 +15,10 @@ //===----------------------------------------------------------------------===// // NEON-specific Operands. //===----------------------------------------------------------------------===// +def nModImm : Operand { + let PrintMethod = "printNEONModImmOperand"; +} + def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; } def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; } def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; } @@ -164,14 +168,6 @@ }]>; //===----------------------------------------------------------------------===// -// NEON operand definitions -//===----------------------------------------------------------------------===// - -def nModImm : Operand { - let PrintMethod = "printNEONModImmOperand"; -} - -//===----------------------------------------------------------------------===// // NEON load / store instructions //===----------------------------------------------------------------------===// From benny.kra at googlemail.com Mon Oct 17 16:18:03 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 17 Oct 2011 21:18:03 -0000 Subject: [llvm-commits] [llvm] r142253 - /llvm/trunk/include/llvm/MC/MCInst.h Message-ID: <20111017211803.28B5F2A6C12C@llvm.org> Author: d0k Date: Mon Oct 17 16:18:03 2011 New Revision: 142253 URL: http://llvm.org/viewvc/llvm-project?rev=142253&view=rev Log: MCOperand is pod-like. Modified: llvm/trunk/include/llvm/MC/MCInst.h Modified: llvm/trunk/include/llvm/MC/MCInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=142253&r1=142252&r2=142253&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInst.h (original) +++ llvm/trunk/include/llvm/MC/MCInst.h Mon Oct 17 16:18:03 2011 @@ -123,6 +123,7 @@ void dump() const; }; +template <> struct isPodLike { static const bool value = true; }; /// MCInst - Instances of this class represent a single low-level machine /// instruction. From zwarich at apple.com Mon Oct 17 16:20:14 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Mon, 17 Oct 2011 21:20:14 -0000 Subject: [llvm-commits] [llvm] r142254 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20111017212014.2FCBB312800A@llvm.org> Author: zwarich Date: Mon Oct 17 16:20:13 2011 New Revision: 142254 URL: http://llvm.org/viewvc/llvm-project?rev=142254&view=rev Log: Pseudoinstructions should not be less constrained than the instruction they are lowered to. This fixes a lot of verifier failures on the test suite. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=142254&r1=142253&r2=142254&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Oct 17 16:20:13 2011 @@ -614,19 +614,19 @@ PatFrag opnode, bit Commutable = 0> { // shifted imm def ri : T2sTwoRegImm< - (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii, + (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii, opc, ".w\t$Rd, $Rn, $imm", - [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]>; + [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>; // register def rr : T2sThreeReg< - (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir, + (outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), iir, opc, ".w\t$Rd, $Rn, $Rm", - [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]>; + [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, rGPR:$Rm))]>; // shifted register def rs : T2sTwoRegShiftedReg< - (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis, + (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis, opc, ".w\t$Rd, $Rn, $ShiftedRm", - [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]>; + [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>; } } From isanbard at gmail.com Mon Oct 17 16:20:24 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 21:20:24 -0000 Subject: [llvm-commits] [llvm] r142256 - in /llvm/trunk: lib/Transforms/InstCombine/InstructionCombining.cpp test/Transforms/InstCombine/LandingPadClauses.ll Message-ID: <20111017212024.62C7B2A6C12C@llvm.org> Author: void Date: Mon Oct 17 16:20:24 2011 New Revision: 142256 URL: http://llvm.org/viewvc/llvm-project?rev=142256&view=rev Log: Add support for the Objective-C personality function to the instruction combining of the landingpad instruction. The ObjC personality function acts almost identically to the C++ personality function. In particular, it uses "null" as a "catch-all" value. Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp llvm/trunk/test/Transforms/InstCombine/LandingPadClauses.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=142256&r1=142255&r2=142256&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Oct 17 16:20:24 2011 @@ -1414,7 +1414,8 @@ enum Personality_Type { Unknown_Personality, GNU_Ada_Personality, - GNU_CXX_Personality + GNU_CXX_Personality, + GNU_ObjC_Personality }; /// RecognizePersonality - See if the given exception handling personality @@ -1426,7 +1427,8 @@ return Unknown_Personality; return StringSwitch(F->getName()) .Case("__gnat_eh_personality", GNU_Ada_Personality) - .Case("__gxx_personality_v0", GNU_CXX_Personality) + .Case("__gxx_personality_v0", GNU_CXX_Personality) + .Case("__objc_personality_v0", GNU_ObjC_Personality) .Default(Unknown_Personality); } @@ -1440,6 +1442,7 @@ // match foreign exceptions (or didn't, before gcc-4.7). return false; case GNU_CXX_Personality: + case GNU_ObjC_Personality: return TypeInfo->isNullValue(); } llvm_unreachable("Unknown personality!"); Modified: llvm/trunk/test/Transforms/InstCombine/LandingPadClauses.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/LandingPadClauses.ll?rev=142256&r1=142255&r2=142256&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/LandingPadClauses.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/LandingPadClauses.ll Mon Oct 17 16:20:24 2011 @@ -6,6 +6,7 @@ declare i32 @generic_personality(i32, i64, i8*, i8*) declare i32 @__gxx_personality_v0(i32, i64, i8*, i8*) +declare i32 @__objc_personality_v0(i32, i64, i8*, i8*) declare void @bar() @@ -179,3 +180,54 @@ ; CHECK-NEXT: null ; CHECK-NEXT: unreachable } + +define void @foo_objc() { +; CHECK: @foo_objc + invoke void @bar() + to label %cont.a unwind label %lpad.a +cont.a: + invoke void @bar() + to label %cont.b unwind label %lpad.b +cont.b: + invoke void @bar() + to label %cont.c unwind label %lpad.c +cont.c: + invoke void @bar() + to label %cont.d unwind label %lpad.d +cont.d: + ret void + +lpad.a: + %a = landingpad { i8*, i32 } personality i32 (i32, i64, i8*, i8*)* @__objc_personality_v0 + catch i32* null + catch i32* @T1 + unreachable +; CHECK: %a = landingpad +; CHECK-NEXT: null +; CHECK-NEXT: unreachable + +lpad.b: + %b = landingpad { i8*, i32 } personality i32 (i32, i64, i8*, i8*)* @__objc_personality_v0 + filter [1 x i32*] zeroinitializer + unreachable +; CHECK: %b = landingpad +; CHECK-NEXT: cleanup +; CHECK-NEXT: unreachable + +lpad.c: + %c = landingpad { i8*, i32 } personality i32 (i32, i64, i8*, i8*)* @__objc_personality_v0 + filter [2 x i32*] [i32* @T1, i32* null] + unreachable +; CHECK: %c = landingpad +; CHECK-NEXT: cleanup +; CHECK-NEXT: unreachable + +lpad.d: + %d = landingpad { i8*, i32 } personality i32 (i32, i64, i8*, i8*)* @__objc_personality_v0 + cleanup + catch i32* null + unreachable +; CHECK: %d = landingpad +; CHECK-NEXT: null +; CHECK-NEXT: unreachable +} From resistor at mac.com Mon Oct 17 16:21:44 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 17 Oct 2011 21:21:44 -0000 Subject: [llvm-commits] [llvm] r142257 - /llvm/trunk/include/llvm/MC/MCInstrAnalysis.h Message-ID: <20111017212144.366F7312800A@llvm.org> Author: resistor Date: Mon Oct 17 16:21:44 2011 New Revision: 142257 URL: http://llvm.org/viewvc/llvm-project?rev=142257&view=rev Log: Use the correct predicate for determining if a branch is conditional or not. Modified: llvm/trunk/include/llvm/MC/MCInstrAnalysis.h Modified: llvm/trunk/include/llvm/MC/MCInstrAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrAnalysis.h?rev=142257&r1=142256&r2=142257&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInstrAnalysis.h (original) +++ llvm/trunk/include/llvm/MC/MCInstrAnalysis.h Mon Oct 17 16:21:44 2011 @@ -33,7 +33,7 @@ } virtual bool isConditionalBranch(const MCInst &Inst) const { - return Info->get(Inst.getOpcode()).isBranch(); + return Info->get(Inst.getOpcode()).isConditionalBranch(); } virtual bool isUnconditionalBranch(const MCInst &Inst) const { From nlewycky at google.com Mon Oct 17 16:33:33 2011 From: nlewycky at google.com (Nick Lewycky) Date: Mon, 17 Oct 2011 14:33:33 -0700 Subject: [llvm-commits] new .file directive In-Reply-To: <7D66141B-90F9-4A28-9A3E-CB167D285975@apple.com> References:

<7D66141B-90F9-4A28-9A3E-CB167D285975@apple.com> Message-ID: On 17 October 2011 14:00, Devang Patel wrote: > > On Oct 14, 2011, at 7:10 PM, Nick Lewycky wrote: > > >> Please review! >> > > > Index: lib/CodeGen/AsmPrinter/DwarfDebug.cpp > =================================================================== > --- lib/CodeGen/AsmPrinter/DwarfDebug.cpp (revision 142035) > +++ lib/CodeGen/AsmPrinter/DwarfDebug.cpp (working copy) > @@ -442,23 +442,21 @@ > if (FileName.empty()) > return GetOrCreateSourceID("", StringRef()); > > - // MCStream expects full path name as filename. > - if (!DirName.empty() && !sys::path::is_absolute(FileName)) { > - SmallString<128> FullPathName = DirName; > - sys::path::append(FullPathName, FileName); > - // Here FullPathName will be copied into StringMap by > GetOrCreateSourceID. > - return GetOrCreateSourceID(StringRef(FullPathName), StringRef()); > - } > + unsigned SrcId = SourceIdMap.size()+1; > + std::pair SourceName = > + std::make_pair(FileName, DirName); > + std::pair, unsigned> Entry = > + make_pair(SourceName, SrcId); > > - StringMapEntry &Entry = > SourceIdMap.GetOrCreateValue(FileName); > - if (Entry.getValue()) > - return Entry.getValue(); > + std::map, unsigned>::iterator I; > + bool NewlyInserted; > + tie(I, NewlyInserted) = SourceIdMap.insert(Entry); > + if (!NewlyInserted) > + return I->second; > > - unsigned SrcId = SourceIdMap.size(); > - Entry.setValue(SrcId); > - > // Print out a .file directive to specify files for .loc directives. > - Asm->OutStreamer.EmitDwarfFileDirective(SrcId, Entry.getKey()); > + Asm->OutStreamer.EmitDwarfFileDirective(SrcId, Entry.first.second, > + Entry.first.first); > > return SrcId; > } > Index: lib/CodeGen/AsmPrinter/DwarfDebug.h > =================================================================== > --- lib/CodeGen/AsmPrinter/DwarfDebug.h (revision 142035) > +++ lib/CodeGen/AsmPrinter/DwarfDebug.h (working copy) > @@ -26,6 +26,7 @@ > #include "llvm/ADT/UniqueVector.h" > #include "llvm/Support/Allocator.h" > #include "llvm/Support/DebugLoc.h" > +#include > > namespace llvm { > > @@ -207,9 +208,9 @@ > /// > std::vector Abbreviations; > > - /// SourceIdMap - Source id map, i.e. pair of directory id and source > file > - /// id mapped to a unique id. > - StringMap SourceIdMap; > + /// SourceIdMap - Source id map, i.e. pair of source filename and > directory > + /// mapped to a unique id. > + std::map, unsigned> SourceIdMap; > > /// StringPool - A String->Symbol mapping of strings used by indirect > /// references. > > > Why do you need this change in DwarfDebug ? Why can't MCAsmStreamer split > file and directly ? > It can, but that's missing the point :) Clang emits separate file and directory, the .bc has the separate file and directory, we currently join them again here so that the asm stream can split them again. I'm removing that extra join+split pair. Going forward, the split could produce different results. I want to encode "clang -isystem foo/bar" + "#include " into directory entry: foo/bar file entry: x/y.h and there's no way that the resplitting could know that as opposed to "foo" + "bar/x/y.h" and "foo/bar/x" + "y.h". Also, this more closely represents what really goes into the debug info, there's a dir entry with the dirname and a file entry which has the filename and the dir entry number. Nick -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/94993a68/attachment.html From isanbard at gmail.com Mon Oct 17 16:32:56 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 21:32:56 -0000 Subject: [llvm-commits] [llvm] r142258 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20111017213256.AB5922A6C12C@llvm.org> Author: void Date: Mon Oct 17 16:32:56 2011 New Revision: 142258 URL: http://llvm.org/viewvc/llvm-project?rev=142258&view=rev Log: Don't renumber the blocks here. This could cause problems later on if another pass renumbers the blocks again. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142258&r1=142257&r2=142258&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Oct 17 16:32:56 2011 @@ -5741,12 +5741,10 @@ MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock(); DispatchBB->addSuccessor(DispContBB); - // Insert and renumber MBBs. - MachineBasicBlock *Last = &MF->back(); + // Insert and MBBs. MF->insert(MF->end(), DispatchBB); MF->insert(MF->end(), DispContBB); MF->insert(MF->end(), TrapBB); - MF->RenumberBlocks(Last); // Insert code into the entry block that creates and registers the function // context. From benny.kra at googlemail.com Mon Oct 17 16:33:26 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 17 Oct 2011 21:33:26 -0000 Subject: [llvm-commits] [llvm] r142259 - in /llvm/trunk/lib: Target/Blackfin/BlackfinIntrinsicInfo.cpp Target/MBlaze/MBlazeIntrinsicInfo.cpp VMCore/Function.cpp Message-ID: <20111017213326.B7A27312800A@llvm.org> Author: d0k Date: Mon Oct 17 16:33:26 2011 New Revision: 142259 URL: http://llvm.org/viewvc/llvm-project?rev=142259&view=rev Log: Use a SmallVector for intrinsic argument types. Modified: llvm/trunk/lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp llvm/trunk/lib/VMCore/Function.cpp Modified: llvm/trunk/lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp?rev=142259&r1=142258&r2=142259&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp Mon Oct 17 16:33:26 2011 @@ -83,7 +83,7 @@ static FunctionType *getType(LLVMContext &Context, unsigned id) { Type *ResultTy = NULL; - std::vector ArgTys; + SmallVector ArgTys; bool IsVarArg = false; #define GET_INTRINSIC_GENERATOR Modified: llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp?rev=142259&r1=142258&r2=142259&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp Mon Oct 17 16:33:26 2011 @@ -92,7 +92,7 @@ static FunctionType *getType(LLVMContext &Context, unsigned id) { Type *ResultTy = NULL; - std::vector ArgTys; + SmallVector ArgTys; bool IsVarArg = false; #define GET_INTRINSIC_GENERATOR Modified: llvm/trunk/lib/VMCore/Function.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=142259&r1=142258&r2=142259&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Function.cpp (original) +++ llvm/trunk/lib/VMCore/Function.cpp Mon Oct 17 16:33:26 2011 @@ -359,7 +359,7 @@ FunctionType *Intrinsic::getType(LLVMContext &Context, ID id, ArrayRef Tys) { Type *ResultTy = NULL; - std::vector ArgTys; + SmallVector ArgTys; bool IsVarArg = false; #define GET_INTRINSIC_GENERATOR From resistor at mac.com Mon Oct 17 16:37:03 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 17 Oct 2011 21:37:03 -0000 Subject: [llvm-commits] [llvm] r142261 - /llvm/trunk/include/llvm/Object/MachO.h Message-ID: <20111017213703.4EC58312800A@llvm.org> Author: resistor Date: Mon Oct 17 16:37:03 2011 New Revision: 142261 URL: http://llvm.org/viewvc/llvm-project?rev=142261&view=rev Log: Add an accessor to get the underlying MachO representation. Modified: llvm/trunk/include/llvm/Object/MachO.h Modified: llvm/trunk/include/llvm/Object/MachO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachO.h?rev=142261&r1=142260&r2=142261&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/MachO.h (original) +++ llvm/trunk/include/llvm/Object/MachO.h Mon Oct 17 16:37:03 2011 @@ -38,6 +38,8 @@ virtual StringRef getFileFormatName() const; virtual unsigned getArch() const; + MachOObject *getObject() { return MachOObj; } + protected: virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const; virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const; From resistor at mac.com Mon Oct 17 16:37:35 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 17 Oct 2011 21:37:35 -0000 Subject: [llvm-commits] [llvm] r142263 - /llvm/trunk/tools/llvm-objdump/MachODump.cpp Message-ID: <20111017213735.A2CE8312800A@llvm.org> Author: resistor Date: Mon Oct 17 16:37:35 2011 New Revision: 142263 URL: http://llvm.org/viewvc/llvm-project?rev=142263&view=rev Log: Rewrite most of MachODump to work through the generic libObject interfaces rather than accessing the MachO internals directly. Modified: llvm/trunk/tools/llvm-objdump/MachODump.cpp Modified: llvm/trunk/tools/llvm-objdump/MachODump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/MachODump.cpp?rev=142263&r1=142262&r2=142263&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/MachODump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/MachODump.cpp Mon Oct 17 16:37:35 2011 @@ -14,7 +14,7 @@ #include "llvm-objdump.h" #include "MCFunction.h" #include "llvm/Support/MachO.h" -#include "llvm/Object/MachOObject.h" +#include "llvm/Object/MachO.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/Triple.h" #include "llvm/ADT/STLExtras.h" @@ -85,57 +85,43 @@ return 0; } -struct Section { - char Name[16]; - uint64_t Address; - uint64_t Size; - uint32_t Offset; - uint32_t NumRelocs; - uint64_t RelocTableOffset; -}; - -struct Symbol { - uint64_t Value; - uint32_t StringIndex; - uint8_t SectionIndex; - bool operator<(const Symbol &RHS) const { return Value < RHS.Value; } +struct SymbolSorter { + bool operator()(const SymbolRef &A, const SymbolRef &B) { + SymbolRef::Type AType, BType; + A.getType(AType); + B.getType(BType); + + uint64_t AAddr, BAddr; + if (AType != SymbolRef::ST_Function) + AAddr = 0; + else + A.getAddress(AAddr); + if (BType != SymbolRef::ST_Function) + BAddr = 0; + else + B.getAddress(BAddr); + return AAddr < BAddr; + } }; -template -static Section copySection(const T &Sect) { - Section S; - memcpy(S.Name, Sect->Name, 16); - S.Address = Sect->Address; - S.Size = Sect->Size; - S.Offset = Sect->Offset; - S.NumRelocs = Sect->NumRelocationTableEntries; - S.RelocTableOffset = Sect->RelocationTableOffset; - return S; -} - -template -static Symbol copySymbol(const T &STE) { - Symbol S; - S.StringIndex = STE->StringIndex; - S.SectionIndex = STE->SectionIndex; - S.Value = STE->Value; - return S; -} - // Print additional information about an address, if available. -static void DumpAddress(uint64_t Address, ArrayRef

Sections, +static void DumpAddress(uint64_t Address, ArrayRef Sections, MachOObject *MachOObj, raw_ostream &OS) { for (unsigned i = 0; i != Sections.size(); ++i) { - uint64_t addr = Address-Sections[i].Address; - if (Sections[i].Address <= Address && - Sections[i].Address + Sections[i].Size > Address) { - StringRef bytes = MachOObj->getData(Sections[i].Offset, - Sections[i].Size); + uint64_t SectAddr = 0, SectSize = 0; + Sections[i].getAddress(SectAddr); + Sections[i].getSize(SectSize); + uint64_t addr = SectAddr; + if (SectAddr <= Address && + SectAddr + SectSize > Address) { + StringRef bytes, name; + Sections[i].getContents(bytes); + Sections[i].getName(name); // Print constant strings. - if (!strcmp(Sections[i].Name, "__cstring")) + if (!name.compare("__cstring")) OS << '"' << bytes.substr(addr, bytes.find('\0', addr)) << '"'; // Print constant CFStrings. - if (!strcmp(Sections[i].Name, "__cfstring")) + if (!name.compare("__cfstring")) OS << "@\"" << bytes.substr(addr, bytes.find('\0', addr)) << '"'; } } @@ -212,59 +198,34 @@ } static void getSectionsAndSymbols(const macho::Header &Header, - MachOObject *MachOObj, + MachOObjectFile *MachOObj, InMemoryStruct *SymtabLC, - std::vector

&Sections, - std::vector &Symbols, + std::vector &Sections, + std::vector &Symbols, SmallVectorImpl &FoundFns) { - // Make a list of all symbols in the object file. - for (unsigned i = 0; i != Header.NumLoadCommands; ++i) { - const MachOObject::LoadCommandInfo &LCI = MachOObj->getLoadCommandInfo(i); - if (LCI.Command.Type == macho::LCT_Segment) { - InMemoryStruct SegmentLC; - MachOObj->ReadSegmentLoadCommand(LCI, SegmentLC); - - // Store the sections in this segment. - for (unsigned SectNum = 0; SectNum != SegmentLC->NumSections; ++SectNum) { - InMemoryStruct Sect; - MachOObj->ReadSection(LCI, SectNum, Sect); - Sections.push_back(copySection(Sect)); + error_code ec; + for (symbol_iterator SI = MachOObj->begin_symbols(), + SE = MachOObj->end_symbols(); SI != SE; SI.increment(ec)) + Symbols.push_back(*SI); + + for (section_iterator SI = MachOObj->begin_sections(), + SE = MachOObj->end_sections(); SI != SE; SI.increment(ec)) { + SectionRef SR = *SI; + StringRef SectName; + SR.getName(SectName); + Sections.push_back(*SI); + } - } - } else if (LCI.Command.Type == macho::LCT_Segment64) { - InMemoryStruct Segment64LC; - MachOObj->ReadSegment64LoadCommand(LCI, Segment64LC); - - // Store the sections in this segment. - for (unsigned SectNum = 0; SectNum != Segment64LC->NumSections; - ++SectNum) { - InMemoryStruct Sect64; - MachOObj->ReadSection64(LCI, SectNum, Sect64); - Sections.push_back(copySection(Sect64)); - } - } else if (LCI.Command.Type == macho::LCT_FunctionStarts) { + for (unsigned i = 0; i != Header.NumLoadCommands; ++i) { + const MachOObject::LoadCommandInfo &LCI = + MachOObj->getObject()->getLoadCommandInfo(i); + if (LCI.Command.Type == macho::LCT_FunctionStarts) { // We found a function starts segment, parse the addresses for later // consumption. InMemoryStruct LLC; - MachOObj->ReadLinkeditDataLoadCommand(LCI, LLC); + MachOObj->getObject()->ReadLinkeditDataLoadCommand(LCI, LLC); - MachOObj->ReadULEB128s(LLC->DataOffset, FoundFns); - } - } - // Store the symbols. - if (SymtabLC) { - for (unsigned i = 0; i != (*SymtabLC)->NumSymbolTableEntries; ++i) { - if (MachOObj->is64Bit()) { - InMemoryStruct STE; - MachOObj->ReadSymbol64TableEntry((*SymtabLC)->SymbolTableOffset, i, - STE); - Symbols.push_back(copySymbol(STE)); - } else { - InMemoryStruct STE; - MachOObj->ReadSymbolTableEntry((*SymtabLC)->SymbolTableOffset, i, - STE); - Symbols.push_back(copySymbol(STE)); - } + MachOObj->getObject()->ReadULEB128s(LLC->DataOffset, FoundFns); } } } @@ -277,9 +238,11 @@ return; } - OwningPtr MachOObj(MachOObject::LoadFromBuffer(Buff.take())); + OwningPtr MachOOF(static_cast( + ObjectFile::createMachOObjectFile(Buff.take()))); + MachOObject *MachOObj = MachOOF->getObject(); - const Target *TheTarget = GetTarget(MachOObj.get()); + const Target *TheTarget = GetTarget(MachOObj); if (!TheTarget) { // GetTarget prints out stuff. return; @@ -322,17 +285,17 @@ MachOObj->ReadSymtabLoadCommand(*SymtabLCI, SymtabLC); MachOObj->RegisterStringTable(*SymtabLC); - std::vector

Sections; - std::vector Symbols; + std::vector Sections; + std::vector Symbols; SmallVector FoundFns; - getSectionsAndSymbols(Header, MachOObj.get(), &SymtabLC, Sections, Symbols, + getSectionsAndSymbols(Header, MachOOF.get(), &SymtabLC, Sections, Symbols, FoundFns); // Make a copy of the unsorted symbol list. FIXME: duplication - std::vector UnsortedSymbols(Symbols); + std::vector UnsortedSymbols(Symbols); // Sort the symbols by address, just in case they didn't come in that way. - array_pod_sort(Symbols.begin(), Symbols.end()); + std::sort(Symbols.begin(), Symbols.end(), SymbolSorter()); #ifndef NDEBUG raw_ostream &DebugOut = DebugFlag ? dbgs() : nulls(); @@ -343,12 +306,12 @@ StringRef DebugAbbrevSection, DebugInfoSection, DebugArangesSection, DebugLineSection, DebugStrSection; OwningPtr diContext; - OwningPtr DSYMObj; - MachOObject *DbgInfoObj = MachOObj.get(); + OwningPtr DSYMObj; + MachOObject *DbgInfoObj = MachOObj; // Try to find debug info and set up the DIContext for it. if (UseDbg) { - ArrayRef

DebugSections = Sections; - std::vector

DSYMSections; + ArrayRef DebugSections = Sections; + std::vector DSYMSections; // A separate DSym file path was specified, parse it as a macho file, // get the sections and supply it to the section name parsing machinery. @@ -358,34 +321,33 @@ errs() << "llvm-objdump: " << Filename << ": " << ec.message() << '\n'; return; } - DSYMObj.reset(MachOObject::LoadFromBuffer(Buf.take())); - const macho::Header &Header = DSYMObj->getHeader(); + DSYMObj.reset(static_cast( + ObjectFile::createMachOObjectFile(Buf.take()))); + const macho::Header &Header = DSYMObj->getObject()->getHeader(); - std::vector Symbols; + std::vector Symbols; SmallVector FoundFns; getSectionsAndSymbols(Header, DSYMObj.get(), 0, DSYMSections, Symbols, FoundFns); DebugSections = DSYMSections; - DbgInfoObj = DSYMObj.get(); + DbgInfoObj = DSYMObj.get()->getObject(); } // Find the named debug info sections. for (unsigned SectIdx = 0; SectIdx != DebugSections.size(); SectIdx++) { - if (!strcmp(DebugSections[SectIdx].Name, "__debug_abbrev")) - DebugAbbrevSection = DbgInfoObj->getData(DebugSections[SectIdx].Offset, - DebugSections[SectIdx].Size); - else if (!strcmp(DebugSections[SectIdx].Name, "__debug_info")) - DebugInfoSection = DbgInfoObj->getData(DebugSections[SectIdx].Offset, - DebugSections[SectIdx].Size); - else if (!strcmp(DebugSections[SectIdx].Name, "__debug_aranges")) - DebugArangesSection = DbgInfoObj->getData(DebugSections[SectIdx].Offset, - DebugSections[SectIdx].Size); - else if (!strcmp(DebugSections[SectIdx].Name, "__debug_line")) - DebugLineSection = DbgInfoObj->getData(DebugSections[SectIdx].Offset, - DebugSections[SectIdx].Size); - else if (!strcmp(DebugSections[SectIdx].Name, "__debug_str")) - DebugStrSection = DbgInfoObj->getData(DebugSections[SectIdx].Offset, - DebugSections[SectIdx].Size); + StringRef SectName; + if (!DebugSections[SectIdx].getName(SectName)) { + if (SectName.equals("__DWARF,__debug_abbrev")) + DebugSections[SectIdx].getContents(DebugAbbrevSection); + else if (SectName.equals("__DWARF,__debug_info")) + DebugSections[SectIdx].getContents(DebugInfoSection); + else if (SectName.equals("__DWARF,__debug_aranges")) + DebugSections[SectIdx].getContents(DebugArangesSection); + else if (SectName.equals("__DWARF,__debug_line")) + DebugSections[SectIdx].getContents(DebugLineSection); + else if (SectName.equals("__DWARF,__debug_str")) + DebugSections[SectIdx].getContents(DebugStrSection); + } } // Setup the DIContext. @@ -401,68 +363,111 @@ FunctionListTy Functions; for (unsigned SectIdx = 0; SectIdx != Sections.size(); SectIdx++) { - if (strcmp(Sections[SectIdx].Name, "__text")) + StringRef SectName; + if (Sections[SectIdx].getName(SectName) || + SectName.compare("__TEXT,__text")) continue; // Skip non-text sections // Insert the functions from the function starts segment into our map. - uint64_t VMAddr = Sections[SectIdx].Address - Sections[SectIdx].Offset; - for (unsigned i = 0, e = FoundFns.size(); i != e; ++i) - FunctionMap.insert(std::make_pair(FoundFns[i]+VMAddr, (MCFunction*)0)); + uint64_t VMAddr; + Sections[SectIdx].getAddress(VMAddr); + for (unsigned i = 0, e = FoundFns.size(); i != e; ++i) { + StringRef SectBegin; + Sections[SectIdx].getContents(SectBegin); + uint64_t Offset = (uint64_t)SectBegin.data(); + FunctionMap.insert(std::make_pair(VMAddr + FoundFns[i]-Offset, + (MCFunction*)0)); + } - StringRef Bytes = MachOObj->getData(Sections[SectIdx].Offset, - Sections[SectIdx].Size); + StringRef Bytes; + Sections[SectIdx].getContents(Bytes); StringRefMemoryObject memoryObject(Bytes); bool symbolTableWorked = false; // Parse relocations. std::vector > Relocs; - for (unsigned j = 0; j != Sections[SectIdx].NumRelocs; ++j) { - InMemoryStruct RE; - MachOObj->ReadRelocationEntry(Sections[SectIdx].RelocTableOffset, j, RE); - Relocs.push_back(std::make_pair(RE->Word0, RE->Word1 & 0xffffff)); + error_code ec; + for (relocation_iterator RI = Sections[SectIdx].begin_relocations(), + RE = Sections[SectIdx].end_relocations(); RI != RE; RI.increment(ec)) { + uint64_t RelocOffset, SectionAddress; + RI->getAddress(RelocOffset); + Sections[SectIdx].getAddress(SectionAddress); + RelocOffset -= SectionAddress; + + uint32_t RelocInfo; + RI->getType(RelocInfo); + + Relocs.push_back(std::make_pair(RelocOffset, RelocInfo)); } array_pod_sort(Relocs.begin(), Relocs.end()); // Disassemble symbol by symbol. for (unsigned SymIdx = 0; SymIdx != Symbols.size(); SymIdx++) { + StringRef SymName; + Symbols[SymIdx].getName(SymName); + + SymbolRef::Type ST; + Symbols[SymIdx].getType(ST); + if (ST != SymbolRef::ST_Function) + continue; + // Make sure the symbol is defined in this section. - if ((unsigned)Symbols[SymIdx].SectionIndex - 1 != SectIdx) + bool containsSym = false; + Sections[SectIdx].containsSymbol(Symbols[SymIdx], containsSym); + if (!containsSym) continue; // Start at the address of the symbol relative to the section's address. - uint64_t Start = Symbols[SymIdx].Value - Sections[SectIdx].Address; + uint64_t Start = 0; + Symbols[SymIdx].getOffset(Start); + // Stop disassembling either at the beginning of the next symbol or at // the end of the section. - uint64_t End = (SymIdx+1 == Symbols.size() || - Symbols[SymIdx].SectionIndex != Symbols[SymIdx+1].SectionIndex) ? - Sections[SectIdx].Size : - Symbols[SymIdx+1].Value - Sections[SectIdx].Address; - uint64_t Size; + bool containsNextSym = true; + uint64_t NextSym = 0; + uint64_t NextSymIdx = SymIdx+1; + while (Symbols.size() > NextSymIdx) { + SymbolRef::Type NextSymType; + Symbols[NextSymIdx].getType(NextSymType); + if (NextSymType == SymbolRef::ST_Function) { + Sections[SectIdx].containsSymbol(Symbols[NextSymIdx], + containsNextSym); + Symbols[NextSymIdx].getOffset(NextSym); + break; + } + ++NextSymIdx; + } - if (Start >= End) - continue; + uint64_t SectSize; + Sections[SectIdx].getSize(SectSize); + uint64_t End = containsNextSym ? NextSym : SectSize; + uint64_t Size; symbolTableWorked = true; if (!CFG) { // Normal disassembly, print addresses, bytes and mnemonic form. - outs() << MachOObj->getStringAtIndex(Symbols[SymIdx].StringIndex) - << ":\n"; + StringRef SymName; + Symbols[SymIdx].getName(SymName); + + outs() << SymName << ":\n"; DILineInfo lastLine; for (uint64_t Index = Start; Index < End; Index += Size) { MCInst Inst; if (DisAsm->getInstruction(Inst, Size, memoryObject, Index, DebugOut, nulls())) { - outs() << format("%8llx:\t", Sections[SectIdx].Address + Index); + uint64_t SectAddress = 0; + Sections[SectIdx].getAddress(SectAddress); + outs() << format("%8llx:\t", SectAddress + Index); + DumpBytes(StringRef(Bytes.data() + Index, Size)); IP->printInst(&Inst, outs(), ""); // Print debug info. if (diContext) { DILineInfo dli = - diContext->getLineInfoForAddress(Sections[SectIdx].Address + - Index); + diContext->getLineInfoForAddress(SectAddress + Index); // Print valid line info if it changed. if (dli != lastLine && dli.getLine() != 0) outs() << "\t## " << dli.getFileName() << ':' @@ -478,20 +483,24 @@ } } else { // Create CFG and use it for disassembly. + StringRef SymName; + Symbols[SymIdx].getName(SymName); createMCFunctionAndSaveCalls( - MachOObj->getStringAtIndex(Symbols[SymIdx].StringIndex), - DisAsm.get(), memoryObject, Start, End, InstrAnalysis.get(), - Start, DebugOut, FunctionMap, Functions); + SymName, DisAsm.get(), memoryObject, Start, End, + InstrAnalysis.get(), Start, DebugOut, FunctionMap, Functions); } } if (CFG) { if (!symbolTableWorked) { // Reading the symbol table didn't work, create a big __TEXT symbol. + uint64_t SectSize = 0, SectAddress = 0; + Sections[SectIdx].getSize(SectSize); + Sections[SectIdx].getAddress(SectAddress); createMCFunctionAndSaveCalls("__TEXT", DisAsm.get(), memoryObject, - 0, Sections[SectIdx].Size, + 0, SectSize, InstrAnalysis.get(), - Sections[SectIdx].Offset, DebugOut, + SectAddress, DebugOut, FunctionMap, Functions); } for (std::map::iterator mi = FunctionMap.begin(), @@ -499,11 +508,14 @@ if (mi->second == 0) { // Create functions for the remaining callees we have gathered, // but we didn't find a name for them. + uint64_t SectSize = 0; + Sections[SectIdx].getSize(SectSize); + SmallVector Calls; MCFunction f = MCFunction::createFunctionFromMC("unknown", DisAsm.get(), memoryObject, mi->first, - Sections[SectIdx].Size, + SectSize, InstrAnalysis.get(), DebugOut, Calls); Functions.push_back(f); @@ -535,13 +547,17 @@ break; } + uint64_t SectSize = 0, SectAddress; + Sections[SectIdx].getSize(SectSize); + Sections[SectIdx].getAddress(SectAddress); + // No predecessors, this is a data block. Print as .byte directives. if (!hasPreds) { - uint64_t End = llvm::next(fi) == fe ? Sections[SectIdx].Size : + uint64_t End = llvm::next(fi) == fe ? SectSize : llvm::next(fi)->first; outs() << "# " << End-fi->first << " bytes of data:\n"; for (unsigned pos = fi->first; pos != End; ++pos) { - outs() << format("%8x:\t", Sections[SectIdx].Address + pos); + outs() << format("%8x:\t", SectAddress + pos); DumpBytes(StringRef(Bytes.data() + pos, 1)); outs() << format("\t.byte 0x%02x\n", (uint8_t)Bytes[pos]); } @@ -558,13 +574,12 @@ const MCDecodedInst &Inst = fi->second.getInsts()[ii]; // If there's a symbol at this address, print its name. - if (FunctionMap.find(Sections[SectIdx].Address + Inst.Address) != + if (FunctionMap.find(SectAddress + Inst.Address) != FunctionMap.end()) - outs() << FunctionMap[Sections[SectIdx].Address + Inst.Address]-> - getName() << ":\n"; + outs() << FunctionMap[SectAddress + Inst.Address]-> getName() + << ":\n"; - outs() << format("%8llx:\t", Sections[SectIdx].Address + - Inst.Address); + outs() << format("%8llx:\t", SectAddress + Inst.Address); DumpBytes(StringRef(Bytes.data() + Inst.Address, Inst.Size)); if (fi->second.contains(fi->first)) // Indent simple loops. @@ -575,15 +590,15 @@ // Look for relocations inside this instructions, if there is one // print its target and additional information if available. for (unsigned j = 0; j != Relocs.size(); ++j) - if (Relocs[j].first >= Sections[SectIdx].Address + Inst.Address && - Relocs[j].first < Sections[SectIdx].Address + Inst.Address + - Inst.Size) { - outs() << "\t# " - << MachOObj->getStringAtIndex( - UnsortedSymbols[Relocs[j].second].StringIndex) - << ' '; - DumpAddress(UnsortedSymbols[Relocs[j].second].Value, Sections, - MachOObj.get(), outs()); + if (Relocs[j].first >= SectAddress + Inst.Address && + Relocs[j].first < SectAddress + Inst.Address + Inst.Size) { + StringRef SymName; + uint64_t Addr; + UnsortedSymbols[Relocs[j].second].getName(SymName); + UnsortedSymbols[Relocs[j].second].getAddress(Addr); + + outs() << "\t# " << SymName << ' '; + DumpAddress(Addr, Sections, MachOObj, outs()); } // If this instructions contains an address, see if we can evaluate @@ -592,13 +607,12 @@ Inst.Address, Inst.Size); if (targ != -1ULL) - DumpAddress(targ, Sections, MachOObj.get(), outs()); + DumpAddress(targ, Sections, MachOObj, outs()); // Print debug info. if (diContext) { DILineInfo dli = - diContext->getLineInfoForAddress(Sections[SectIdx].Address + - Inst.Address); + diContext->getLineInfoForAddress(SectAddress + Inst.Address); // Print valid line info if it changed. if (dli != lastLine && dli.getLine() != 0) outs() << "\t## " << dli.getFileName() << ':' From isanbard at gmail.com Mon Oct 17 16:38:49 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 21:38:49 -0000 Subject: [llvm-commits] [dragonegg] r142268 - /dragonegg/tags/ Message-ID: <20111017213849.3FCE1312800A@llvm.org> Author: void Date: Mon Oct 17 16:38:49 2011 New Revision: 142268 URL: http://llvm.org/viewvc/llvm-project?rev=142268&view=rev Log: Create tags directory Added: dragonegg/tags/ From isanbard at gmail.com Mon Oct 17 16:40:48 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 21:40:48 -0000 Subject: [llvm-commits] [dragonegg] r142270 - /dragonegg/tags/RELEASE_30/ Message-ID: <20111017214048.17ECF312800A@llvm.org> Author: void Date: Mon Oct 17 16:40:47 2011 New Revision: 142270 URL: http://llvm.org/viewvc/llvm-project?rev=142270&view=rev Log: Creating release directory for 30. Added: dragonegg/tags/RELEASE_30/ From isanbard at gmail.com Mon Oct 17 16:40:53 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 21:40:53 -0000 Subject: [llvm-commits] [dragonegg] r142271 - /dragonegg/tags/RELEASE_30/rc1/ Message-ID: <20111017214053.E0548312800A@llvm.org> Author: void Date: Mon Oct 17 16:40:53 2011 New Revision: 142271 URL: http://llvm.org/viewvc/llvm-project?rev=142271&view=rev Log: Creating release candidate 1 from release_30 branch Added: dragonegg/tags/RELEASE_30/rc1/ - copied from r142270, dragonegg/branches/release_30/ From isanbard at gmail.com Mon Oct 17 16:40:56 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 21:40:56 -0000 Subject: [llvm-commits] [test-suite] r142272 - /test-suite/tags/RELEASE_30/ Message-ID: <20111017214057.0E2122A6C12C@llvm.org> Author: void Date: Mon Oct 17 16:40:56 2011 New Revision: 142272 URL: http://llvm.org/viewvc/llvm-project?rev=142272&view=rev Log: Creating release directory for 30. Added: test-suite/tags/RELEASE_30/ From isanbard at gmail.com Mon Oct 17 16:41:02 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 21:41:02 -0000 Subject: [llvm-commits] [test-suite] r142273 - /test-suite/tags/RELEASE_30/rc1/ Message-ID: <20111017214102.C1FE72A6C12C@llvm.org> Author: void Date: Mon Oct 17 16:41:02 2011 New Revision: 142273 URL: http://llvm.org/viewvc/llvm-project?rev=142273&view=rev Log: Creating release candidate 1 from release_30 branch Added: test-suite/tags/RELEASE_30/rc1/ - copied from r142272, test-suite/branches/release_30/ From isanbard at gmail.com Mon Oct 17 16:41:05 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 21:41:05 -0000 Subject: [llvm-commits] [compiler-rt] r142274 - /compiler-rt/tags/RELEASE_30/ Message-ID: <20111017214105.E01E42A6C12C@llvm.org> Author: void Date: Mon Oct 17 16:41:05 2011 New Revision: 142274 URL: http://llvm.org/viewvc/llvm-project?rev=142274&view=rev Log: Creating release directory for 30. Added: compiler-rt/tags/RELEASE_30/ From isanbard at gmail.com Mon Oct 17 16:41:11 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 21:41:11 -0000 Subject: [llvm-commits] [compiler-rt] r142275 - /compiler-rt/tags/RELEASE_30/rc1/ Message-ID: <20111017214111.8B532312800A@llvm.org> Author: void Date: Mon Oct 17 16:41:11 2011 New Revision: 142275 URL: http://llvm.org/viewvc/llvm-project?rev=142275&view=rev Log: Creating release candidate 1 from release_30 branch Added: compiler-rt/tags/RELEASE_30/rc1/ - copied from r142274, compiler-rt/branches/release_30/ From jabbey at arxan.com Mon Oct 17 16:44:05 2011 From: jabbey at arxan.com (Joe Abbey) Date: Mon, 17 Oct 2011 16:44:05 -0500 Subject: [llvm-commits] Removing additional warnings Message-ID: This resolves the last couple warnings: MipsISelLowering.cpp:791:12: warning: variable ?dl? set but not used [-Wunused-but-set-variable] ARMISelDAGToDAG.cpp:2319:12: warning: variable ?DL? set but not used [-Wunused-but-set-variable] as well as some warnings when tbl-genning thumb2 Cheers, Joe Abbey Software Architect Arxan Technologies, Inc. 1305 Cumberland Ave, Ste 215 West Lafayette, IN 47906 jabbey at arxan.com www.arxan.com -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/bb511230/attachment.html -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: llvm_warning_free.txt Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/bb511230/attachment.txt From isanbard at gmail.com Mon Oct 17 16:42:29 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 21:42:29 -0000 Subject: [llvm-commits] [llvm] r142280 - /llvm/trunk/utils/release/tag.sh Message-ID: <20111017214230.05E562A6C12C@llvm.org> Author: void Date: Mon Oct 17 16:42:29 2011 New Revision: 142280 URL: http://llvm.org/viewvc/llvm-project?rev=142280&view=rev Log: Add message to svn mkdir command. Modified: llvm/trunk/utils/release/tag.sh Modified: llvm/trunk/utils/release/tag.sh URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/tag.sh?rev=142280&r1=142279&r2=142280&view=diff ============================================================================== --- llvm/trunk/utils/release/tag.sh (original) +++ llvm/trunk/utils/release/tag.sh Mon Oct 17 16:42:29 2011 @@ -43,7 +43,7 @@ set -x for proj in llvm cfe dragonegg test-suite compiler-rt libcxx libcxxabi ; do if ! svn ls $base_url/$proj/tags/RELEASE_$release > /dev/null 2>&1 ; then - svn mkdir $base_url/$proj/tags/RELEASE_$release + svn mkdir -m "Creating release directory for release_$release." $base_url/$proj/tags/RELEASE_$release fi if ! svn ls $base_url/$proj/tags/RELEASE_$release/rc$rc > /dev/null 2>&1 ; then svn copy -m "Creating release candidate $rc from release_$release branch" \ From dpatel at apple.com Mon Oct 17 16:45:56 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 17 Oct 2011 14:45:56 -0700 Subject: [llvm-commits] new .file directive In-Reply-To: References:

<7D66141B-90F9-4A28-9A3E-CB167D285975@apple.com> Message-ID: On Oct 17, 2011, at 2:33 PM, Nick Lewycky wrote: > It can, but that's missing the point :) Clang emits separate file and directory, the .bc has the separate file and directory, we currently join them again here so that the asm stream can split them again. I'm removing that extra join+split pair. > > Going forward, the split could produce different results. I want to encode "clang -isystem foo/bar" + "#include " into > directory entry: foo/bar > file entry: x/y.h > and there's no way that the resplitting could know that as opposed to "foo" + "bar/x/y.h" and "foo/bar/x" + "y.h". > > Also, this more closely represents what really goes into the debug info, there's a dir entry with the dirname and a file entry which has the filename and the dir entry number. makes sense! - Devang -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/081169e9/attachment.html From isanbard at gmail.com Mon Oct 17 16:45:07 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 21:45:07 -0000 Subject: [llvm-commits] [llvm] r142282 - /llvm/trunk/utils/release/test-release.sh Message-ID: <20111017214508.1191B2A6C12C@llvm.org> Author: void Date: Mon Oct 17 16:45:07 2011 New Revision: 142282 URL: http://llvm.org/viewvc/llvm-project?rev=142282&view=rev Log: Forgot to add the project name to the 'svn ls' command. Modified: llvm/trunk/utils/release/test-release.sh Modified: llvm/trunk/utils/release/test-release.sh URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/test-release.sh?rev=142282&r1=142281&r2=142282&view=diff ============================================================================== --- llvm/trunk/utils/release/test-release.sh (original) +++ llvm/trunk/utils/release/test-release.sh Mon Oct 17 16:45:07 2011 @@ -163,7 +163,7 @@ for proj in $projects ; do echo "# Validating $proj SVN URL" - if ! svn ls $Base_url/tags/RELEASE_$Release_no_dot/rc$RC > /dev/null 2>&1 ; then + if ! svn ls $Base_url/$proj/tags/RELEASE_$Release_no_dot/rc$RC > /dev/null 2>&1 ; then echo "llvm $Release release candidate $RC doesn't exist!" exit 1 fi From resistor at mac.com Mon Oct 17 16:53:26 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 17 Oct 2011 14:53:26 -0700 Subject: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ In-Reply-To: <6594DDFF12B03D4E89690887C248699402A2C887C6@hasmsx504.ger.corp.intel.com> References: <20111016203133.CC4E13128018@llvm.org> <1B579157-F0E8-45FB-A8E8-3D520ED36FC0@mac.com> <84BE87AB-7185-4CF6-B0F4-D242762AA4A0@mac.com> <6594DDFF12B03D4E89690887C248699402A2C887C6@hasmsx504.ger.corp.intel.com> Message-ID: <32320A16-378C-4390-A51B-241396859284@mac.com> Nadav, On Oct 17, 2011, at 1:37 PM, Rotem, Nadav wrote: > The new type-legalization generates new code sequences. For example: trunc store and anyext loads. I implemented fast load/store sequences for x86. Other targets also need to optimize the new sequences. I opened a bug report on this PR11158. Unfortunately, that PR does not cover the issue exposed in the testcase I pointed out, which is a real, significant performance issue with this approach. Take a look at this snippet: define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { entry: %0 = bitcast <4 x i16>* %source to <8 x i16>* %tmp2 = load <8 x i16>* %0, align 4 %tmp3 = extractelement <8 x i16> %tmp2, i32 6 %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0 %tmp9 = extractelement <8 x i16> %tmp2, i32 5 %tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1 store <2 x i16> %tmp11, <2 x i16>* %dst, align 4 ret void } In NEON, vectors of i16 are legal, but i16 is not. The correct code generation sequence was to collapse all of the insert/extract vectors into a shuffle, at which point there are longer illegal types present. With your change, we promote all the vectors to vector of i32, at which point we can no longer match the desired shuffle instruction, in addition to having to emit a (possibly inefficient) vector trunc_store. Even if we do add an efficient trunc_store lowering to ARM backend, it will still be unable to match the efficient shuffle because we have obfuscated the code by promoting rather than collapsing it to a shuffle. That collapse to a shuffle is what the test that removed was checking for. --Owen -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/61a5061c/attachment.html From lhames at gmail.com Mon Oct 17 16:54:43 2011 From: lhames at gmail.com (Lang Hames) Date: Mon, 17 Oct 2011 21:54:43 -0000 Subject: [llvm-commits] [llvm] r142286 - /llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll Message-ID: <20111017215443.9FFF6312800A@llvm.org> Author: lhames Date: Mon Oct 17 16:54:43 2011 New Revision: 142286 URL: http://llvm.org/viewvc/llvm-project?rev=142286&view=rev Log: Fixed quoting on default data layout option. Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll?rev=142286&r1=142285&r2=142286&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll (original) +++ llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll Mon Oct 17 16:54:43 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -default-data-layout="e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" -simplify-libcalls -S | FileCheck %s +; RUN: opt < %s "-default-data-layout=e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" -simplify-libcalls -S | FileCheck %s @.str1 = private constant [11 x i8] c"(){};[]&|:\00", align 4 ; check that simplify libcalls will not replace a call with one calling From zwarich at apple.com Mon Oct 17 16:54:46 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Mon, 17 Oct 2011 21:54:46 -0000 Subject: [llvm-commits] [llvm] r142287 - /llvm/trunk/lib/CodeGen/OptimizePHIs.cpp Message-ID: <20111017215446.625CD312800A@llvm.org> Author: zwarich Date: Mon Oct 17 16:54:46 2011 New Revision: 142287 URL: http://llvm.org/viewvc/llvm-project?rev=142287&view=rev Log: When deleting a phi cycle after looking through copies, constrain the register to match its final use. With this change, all of test-suite compiles for Thumb2 with -verify-coalescing enabled. Modified: llvm/trunk/lib/CodeGen/OptimizePHIs.cpp Modified: llvm/trunk/lib/CodeGen/OptimizePHIs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/OptimizePHIs.cpp?rev=142287&r1=142286&r2=142287&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/OptimizePHIs.cpp (original) +++ llvm/trunk/lib/CodeGen/OptimizePHIs.cpp Mon Oct 17 16:54:46 2011 @@ -165,7 +165,11 @@ InstrSet PHIsInCycle; if (IsSingleValuePHICycle(MI, SingleValReg, PHIsInCycle) && SingleValReg != 0) { - MRI->replaceRegWith(MI->getOperand(0).getReg(), SingleValReg); + unsigned OldReg = MI->getOperand(0).getReg(); + if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) + continue; + + MRI->replaceRegWith(OldReg, SingleValReg); MI->eraseFromParent(); ++NumPHICycles; Changed = true; From eli.friedman at gmail.com Mon Oct 17 17:03:44 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 17 Oct 2011 15:03:44 -0700 Subject: [llvm-commits] [llvm] r142286 - /llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll In-Reply-To: <20111017215443.9FFF6312800A@llvm.org> References: <20111017215443.9FFF6312800A@llvm.org> Message-ID: On Mon, Oct 17, 2011 at 2:54 PM, Lang Hames wrote: > Author: lhames > Date: Mon Oct 17 16:54:43 2011 > New Revision: 142286 > > URL: http://llvm.org/viewvc/llvm-project?rev=142286&view=rev > Log: > Fixed quoting on default data layout option. > > Modified: > ? ?llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll > > Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll?rev=142286&r1=142285&r2=142286&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll (original) > +++ llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll Mon Oct 17 16:54:43 2011 > @@ -1,4 +1,4 @@ > -; RUN: opt < %s -default-data-layout="e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" -simplify-libcalls -S | FileCheck %s > +; RUN: opt < %s "-default-data-layout=e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" -simplify-libcalls -S | FileCheck %s Either way works, AFAIK. -Eli From nlewycky at google.com Mon Oct 17 17:06:45 2011 From: nlewycky at google.com (Nick Lewycky) Date: Mon, 17 Oct 2011 15:06:45 -0700 Subject: [llvm-commits] PATCH: Add pass printing and a basic sanity test for BlockFrequencyInfo analysis In-Reply-To: References:

Message-ID: diff --git a/lib/Analysis/BlockFrequencyInfo.cpp b/lib/Analysis/BlockFrequencyInfo.cpp index ee89915..9e05065 100644 --- a/lib/Analysis/BlockFrequencyInfo.cpp +++ b/lib/Analysis/BlockFrequencyInfo.cpp @@ -49,6 +49,10 @@ bool BlockFrequencyInfo::runOnFunction(Function &F) { return false; } +void BlockFrequencyInfo::print(raw_ostream &O, const Module * /*M*/) const { Just const const Module* will do. + if (BFI) BFI->print(O); +} + +; Loop backedges are weighted, and their bodies represented as having a greater +; frequency. Please re-english. :) Please commit once you've fixed those. Nick On 16 October 2011 23:30, Chandler Carruth wrote: > (Sent to the wrong address for Jakub it seems...) > > > On Sun, Oct 16, 2011 at 11:25 PM, Chandler Carruth wrote: > >> Hello, >> >> So it turns out that BranchProbabilityInfo and BlockFrequencyInfo aren't >> rigged up to __builtin_expect at all. I think no one realized because we >> have essentially no test coverage for these analysis passes. See >> http://llvm.org/PR2577 >> >> This patch adds test coverage for BlockFrequencyInfo which is the easiest >> to test, and essentially a good way to strictly cover BranchProbabilityInfo. >> Subsequent patches to add the remaining features to actually use >> __builtin_expect will follow with tests based on this. >> -Chandler >> > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/eeabb18f/attachment.html From lhames at gmail.com Mon Oct 17 17:05:35 2011 From: lhames at gmail.com (Lang Hames) Date: Mon, 17 Oct 2011 22:05:35 -0000 Subject: [llvm-commits] [llvm] r142288 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/AsmParser/LLParser.cpp lib/Target/TargetData.cpp Message-ID: <20111017220535.2A343312800A@llvm.org> Author: lhames Date: Mon Oct 17 17:05:34 2011 New Revision: 142288 URL: http://llvm.org/viewvc/llvm-project?rev=142288&view=rev Log: Validate target data layout strings. Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion. Modified: llvm/trunk/include/llvm/Target/TargetData.h llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/Target/TargetData.cpp Modified: llvm/trunk/include/llvm/Target/TargetData.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetData.h?rev=142288&r1=142287&r2=142288&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetData.h (original) +++ llvm/trunk/include/llvm/Target/TargetData.h Mon Oct 17 17:05:34 2011 @@ -44,7 +44,7 @@ AGGREGATE_ALIGN = 'a', ///< Aggregate alignment STACK_ALIGN = 's' ///< Stack objects alignment }; - + /// Target alignment element. /// /// Stores the alignment data associated with a given alignment type (pointer, @@ -80,7 +80,7 @@ unsigned StackNaturalAlign; ///< Stack natural alignment SmallVector LegalIntWidths; ///< Legal Integers. - + /// Alignments- Where the primitive type alignment data is stored. /// /// @sa init(). @@ -88,7 +88,7 @@ /// pointers vs. 64-bit pointers by extending TargetAlignment, but for now, /// we don't. SmallVector Alignments; - + /// InvalidAlignmentElem - This member is a signal that a requested alignment /// type and bit width were not found in the SmallVector. static const TargetAlignElem InvalidAlignmentElem; @@ -112,19 +112,30 @@ return &align != &InvalidAlignmentElem; } + /// Initialise a TargetData object with default values, ensure that the + /// target data pass is registered. + void init(); + public: /// Default ctor. /// /// @note This has to exist, because this is a pass, but it should never be /// used. TargetData(); - + /// Constructs a TargetData from a specification string. See init(). explicit TargetData(StringRef TargetDescription) : ImmutablePass(ID) { - init(TargetDescription); + std::string errMsg = parseSpecifier(TargetDescription, this); + assert(errMsg == "" && "Invalid target data layout string."); + (void)errMsg; } + /// Parses a target data specification string. Returns an error message + /// if the string is malformed, or the empty string on success. Optionally + /// initialises a TargetData object if passed a non-null pointer. + static std::string parseSpecifier(StringRef TargetDescription, TargetData* td = 0); + /// Initialize target data from properties stored in the module. explicit TargetData(const Module *M); @@ -141,9 +152,6 @@ ~TargetData(); // Not virtual, do not subclass this class - //! Parse a target data layout string and initialize TargetData alignments. - void init(StringRef TargetDescription); - /// Target endianness... bool isLittleEndian() const { return LittleEndian; } bool isBigEndian() const { return !LittleEndian; } @@ -152,7 +160,7 @@ /// TargetData. This representation is in the same format accepted by the /// string constructor above. std::string getStringRepresentation() const; - + /// isLegalInteger - This function returns true if the specified type is /// known to be a native integer type supported by the CPU. For example, /// i64 is not native on most 32-bit CPUs and i37 is not native on any known @@ -166,7 +174,7 @@ return true; return false; } - + bool isIllegalInteger(unsigned Width) const { return !isLegalInteger(Width); } @@ -251,11 +259,11 @@ /// getABITypeAlignment - Return the minimum ABI-required alignment for the /// specified type. unsigned getABITypeAlignment(Type *Ty) const; - + /// getABIIntegerTypeAlignment - Return the minimum ABI-required alignment for /// an integer type of the specified bitwidth. unsigned getABIIntegerTypeAlignment(unsigned BitWidth) const; - + /// getCallFrameTypeAlignment - Return the minimum ABI-required alignment /// for the specified type when it is part of a call frame. @@ -305,7 +313,7 @@ assert((Alignment & (Alignment-1)) == 0 && "Alignment must be power of 2!"); return (Val + (Alignment-1)) & ~UIntTy(Alignment-1); } - + static char ID; // Pass identification, replacement for typeid }; Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=142288&r1=142287&r2=142288&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Oct 17 17:05:34 2011 @@ -24,6 +24,7 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetData.h" using namespace llvm; static std::string getTypeString(Type *T) { @@ -260,9 +261,14 @@ return false; case lltok::kw_datalayout: Lex.Lex(); + LocTy SpecifierLoc = Lex.getLoc(); if (ParseToken(lltok::equal, "expected '=' after target datalayout") || ParseStringConstant(Str)) return true; + std::string errMsg = TargetData::parseSpecifier(Str); + if (errMsg != "") { + return Error(SpecifierLoc, errMsg); + } M->setDataLayout(Str); return false; } Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=142288&r1=142287&r2=142288&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Mon Oct 17 17:05:34 2011 @@ -125,15 +125,15 @@ //===----------------------------------------------------------------------===// /// getInt - Get an integer ignoring errors. -static unsigned getInt(StringRef R) { - unsigned Result = 0; +static int getInt(StringRef R) { + int Result = 0; R.getAsInteger(10, Result); return Result; } -void TargetData::init(StringRef Desc) { +void TargetData::init() { initializeTargetDataPass(*PassRegistry::getPassRegistry()); - + LayoutMap = 0; LittleEndian = false; PointerMemSize = 8; @@ -152,6 +152,12 @@ setAlignment(VECTOR_ALIGN, 8, 8, 64); // v2i32, v1i64, ... setAlignment(VECTOR_ALIGN, 16, 16, 128); // v16i8, v8i16, v4i32, ... setAlignment(AGGREGATE_ALIGN, 0, 8, 0); // struct +} + +std::string TargetData::parseSpecifier(StringRef Desc, TargetData *td) { + + if (td) + td->init(); while (!Desc.empty()) { std::pair Split = Desc.split('-'); @@ -169,28 +175,54 @@ switch (Specifier[0]) { case 'E': - LittleEndian = false; + if (td) + td->LittleEndian = false; break; case 'e': - LittleEndian = true; + if (td) + td->LittleEndian = true; break; - case 'p': + case 'p': { + // Pointer size. Split = Token.split(':'); - PointerMemSize = getInt(Split.first) / 8; + int PointerMemSizeBits = getInt(Split.first); + if (PointerMemSizeBits < 0 || PointerMemSizeBits % 8 != 0) + return "invalid pointer size, must be a positive 8-bit multiple"; + if (td) + td->PointerMemSize = PointerMemSizeBits / 8; + + // Pointer ABI alignment. Split = Split.second.split(':'); - PointerABIAlign = getInt(Split.first) / 8; + int PointerABIAlignBits = getInt(Split.first); + if (PointerABIAlignBits < 0 || PointerABIAlignBits % 8 != 0) { + return "invalid pointer ABI alignment, " + "must be a positive 8-bit multiple"; + } + if (td) + td->PointerABIAlign = PointerABIAlignBits / 8; + + // Pointer preferred alignment. Split = Split.second.split(':'); - PointerPrefAlign = getInt(Split.first) / 8; - if (PointerPrefAlign == 0) - PointerPrefAlign = PointerABIAlign; + int PointerPrefAlignBits = getInt(Split.first); + if (PointerPrefAlignBits < 0 || PointerPrefAlignBits % 8 != 0) { + return "invalid pointer preferred alignment, " + "must be a positive 8-bit multiple"; + } + if (td) { + td->PointerPrefAlign = PointerPrefAlignBits / 8; + if (td->PointerPrefAlign == 0) + td->PointerPrefAlign = td->PointerABIAlign; + } break; + } case 'i': case 'v': case 'f': case 'a': case 's': { AlignTypeEnum AlignType; - switch (Specifier[0]) { + char field = Specifier[0]; + switch (field) { default: case 'i': AlignType = INTEGER_ALIGN; break; case 'v': AlignType = VECTOR_ALIGN; break; @@ -198,37 +230,66 @@ case 'a': AlignType = AGGREGATE_ALIGN; break; case 's': AlignType = STACK_ALIGN; break; } - unsigned Size = getInt(Specifier.substr(1)); + int Size = getInt(Specifier.substr(1)); + if (Size < 0) { + return std::string("invalid ") + field + "-size field, " + "must be positive"; + } + Split = Token.split(':'); - unsigned ABIAlign = getInt(Split.first) / 8; + int ABIAlignBits = getInt(Split.first); + if (ABIAlignBits < 0 || ABIAlignBits % 8 != 0) { + return std::string("invalid ") + field +"-abi-alignment field, " + "must be a positive 8-bit multiple"; + } + unsigned ABIAlign = ABIAlignBits / 8; Split = Split.second.split(':'); - unsigned PrefAlign = getInt(Split.first) / 8; + + int PrefAlignBits = getInt(Split.first); + if (PrefAlignBits < 0 || PrefAlignBits % 8 != 0) { + return std::string("invalid ") + field +"-preferred-alignment field, " + "must be a positive 8-bit multiple"; + } + unsigned PrefAlign = PrefAlignBits / 8; if (PrefAlign == 0) PrefAlign = ABIAlign; - setAlignment(AlignType, ABIAlign, PrefAlign, Size); + + if (td) + td->setAlignment(AlignType, ABIAlign, PrefAlign, Size); break; } case 'n': // Native integer types. Specifier = Specifier.substr(1); do { - if (unsigned Width = getInt(Specifier)) - LegalIntWidths.push_back(Width); + int Width = getInt(Specifier); + if (Width <= 0) { + return std::string("invalid native integer size \'") + Specifier.str() + + "\', must be a positive integer."; + } + if (td && Width != 0) + td->LegalIntWidths.push_back(Width); Split = Token.split(':'); Specifier = Split.first; Token = Split.second; } while (!Specifier.empty() || !Token.empty()); break; - case 'S': // Stack natural alignment. - StackNaturalAlign = getInt(Specifier.substr(1)); - StackNaturalAlign /= 8; - // FIXME: Should we really be truncating these alingments and - // sizes silently? + case 'S': { // Stack natural alignment. + int StackNaturalAlignBits = getInt(Specifier.substr(1)); + if (StackNaturalAlignBits < 0 || StackNaturalAlignBits % 8 != 0) { + return "invalid natural stack alignment (S-field), " + "must be a positive 8-bit multiple"; + } + if (td) + td->StackNaturalAlign = StackNaturalAlignBits / 8; break; + } default: break; } } + + return ""; } /// Default ctor. @@ -242,7 +303,9 @@ TargetData::TargetData(const Module *M) : ImmutablePass(ID) { - init(M->getDataLayout()); + std::string errMsg = parseSpecifier(M->getDataLayout(), this); + assert(errMsg == "" && "Module M has malformed target data layout string."); + (void)errMsg; } void From lhames at apple.com Mon Oct 17 17:14:35 2011 From: lhames at apple.com (Lang Hames) Date: Mon, 17 Oct 2011 15:14:35 -0700 Subject: [llvm-commits] [llvm] r142286 - /llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll In-Reply-To: <20111017215443.9FFF6312800A@llvm.org> References: <20111017215443.9FFF6312800A@llvm.org> Message-ID: Not quite. Apparently the shell lines in the lit suite are tcl, which doesn't honor the embedded quote. This led to the trailing quote being passed through in the target data layout string. The parser used to swallow this silently, treating the resulting 'n32"' as zero and discard it. The new verifier barfed on it though (as it should). - Lang. On Oct 17, 2011, at 2:54 PM, Lang Hames wrote: > Author: lhames > Date: Mon Oct 17 16:54:43 2011 > New Revision: 142286 > > URL: http://llvm.org/viewvc/llvm-project?rev=142286&view=rev > Log: > Fixed quoting on default data layout option. > > Modified: > llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll > > Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll?rev=142286&r1=142285&r2=142286&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll (original) > +++ llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll Mon Oct 17 16:54:43 2011 > @@ -1,4 +1,4 @@ > -; RUN: opt < %s -default-data-layout="e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" -simplify-libcalls -S | FileCheck %s > +; RUN: opt < %s "-default-data-layout=e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" -simplify-libcalls -S | FileCheck %s > @.str1 = private constant [11 x i8] c"(){};[]&|:\00", align 4 > > ; check that simplify libcalls will not replace a call with one calling > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From rafael.espindola at gmail.com Mon Oct 17 17:26:24 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Mon, 17 Oct 2011 18:26:24 -0400 Subject: [llvm-commits] [llvm] r142288 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/AsmParser/LLParser.cpp lib/Target/TargetData.cpp In-Reply-To: <20111017220535.2A343312800A@llvm.org> References: <20111017220535.2A343312800A@llvm.org> Message-ID: <4E9CAB90.3010102@gmail.com> looks like this broke the build: Linking CXX executable ../../bin/llvm-as ../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)' clang-3: error: linker command failed with exit code 1 (use -v to see invocation) Cheers, Rafael From grosbach at apple.com Mon Oct 17 17:26:03 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 17 Oct 2011 22:26:03 -0000 Subject: [llvm-commits] [llvm] r142293 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-mov-encoding.s test/MC/ARM/neont2-mov-encoding.s utils/TableGen/EDEmitter.cpp Message-ID: <20111017222603.CABA2312800A@llvm.org> Author: grosbach Date: Mon Oct 17 17:26:03 2011 New Revision: 142293 URL: http://llvm.org/viewvc/llvm-project?rev=142293&view=rev Log: ARM NEON "vmov.i8" immediate assembly parsing and encoding. NEON immediates are "interesting". Start of the work to handle parsing them in an 'as' compatible manner. Getting the matcher to play nicely with these and the floating point immediates from VFP is an extra fun wrinkle. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/neon-mov-encoding.s llvm/trunk/test/MC/ARM/neont2-mov-encoding.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142293&r1=142292&r2=142293&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 17 17:26:03 2011 @@ -19,6 +19,12 @@ let PrintMethod = "printNEONModImmOperand"; } +def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; } +def nImmSplatI8 : Operand { + let PrintMethod = "printNEONModImmOperand"; + let ParserMatchClass = nImmSplatI8AsmOperand; +} + def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; } def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; } def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; } @@ -4314,11 +4320,11 @@ let isReMaterializable = 1 in { def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmSplatI8:$SIMM), IIC_VMOVImm, "vmov", "i8", "$Vd, $SIMM", "", [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>; def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmSplatI8:$SIMM), IIC_VMOVImm, "vmov", "i8", "$Vd, $SIMM", "", [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=142293&r1=142292&r2=142293&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Oct 17 17:26:03 2011 @@ -898,6 +898,7 @@ bool isMSRMask() const { return Kind == k_MSRMask; } bool isProcIFlags() const { return Kind == k_ProcIFlags; } + // NEON operands. bool isVectorIndex8() const { if (Kind != k_VectorIndex) return false; return VectorIndex.Val < 8; @@ -911,7 +912,18 @@ return VectorIndex.Val < 2; } - + bool isNEONi8splat() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + // Must be a constant. + if (!CE) return false; + int64_t Value = CE->getValue(); + // i8 value splatted across 8 bytes. The immediate is just the 8 byte + // value. +// return ((Value << 8) | (Value & 0xff)) == Value; + return Value >= 0 && Value < 256; + } void addExpr(MCInst &Inst, const MCExpr *Expr) const { // Add as immediates when possible. Null MCExpr = 0. @@ -1435,6 +1447,14 @@ Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); } + void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + // The immediate encodes the type of constant as well as the value. + // Mask in that this is an i8 splat. + const MCConstantExpr *CE = dyn_cast(getImm()); + Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); + } + virtual void print(raw_ostream &OS) const; static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { @@ -3330,6 +3350,22 @@ if (Parser.getTok().isNot(AsmToken::Hash)) return MatchOperand_NoMatch; + + // Disambiguate the VMOV forms that can accept an FP immediate. + // vmov.f32 , #imm + // vmov.f64 , #imm + // vmov.f32 , #imm @ vector f32x2 + // vmov.f32 , #imm @ vector f32x4 + // + // There are also the NEON VMOV instructions which expect an + // integer constant. Make sure we don't try to parse an FPImm + // for these: + // vmov.i{8|16|32|64} , #imm + ARMOperand *TyOp = static_cast(Operands[2]); + if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && + TyOp->getToken() != ".f64")) + return MatchOperand_NoMatch; + Parser.Lex(); // Eat the '#'. // Handle negation, as that still comes through as a separate token. Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.s?rev=142293&r1=142292&r2=142293&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mov-encoding.s Mon Oct 17 17:26:03 2011 @@ -1,69 +1,68 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * vmov.i8 d16, #0x8 - vmov.i16 d16, #0x10 - vmov.i16 d16, #0x1000 - vmov.i32 d16, #0x20 - vmov.i32 d16, #0x2000 - vmov.i32 d16, #0x200000 - vmov.i32 d16, #0x20000000 - vmov.i32 d16, #0x20FF - vmov.i32 d16, #0x20FFFF - vmov.i64 d16, #0xFF0000FF0000FFFF +@ vmov.i16 d16, #0x10 +@ vmov.i16 d16, #0x1000 +@ vmov.i32 d16, #0x20 +@ vmov.i32 d16, #0x2000 +@ vmov.i32 d16, #0x200000 +@ vmov.i32 d16, #0x20000000 +@ vmov.i32 d16, #0x20FF +@ vmov.i32 d16, #0x20FFFF +@ vmov.i64 d16, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] -@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] -@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2] -@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2] -@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] -@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] -@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] -@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] -@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] -@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] +@ FIXME: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] +@ FIXME: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2] +@ FIXME: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2] +@ FIXME: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] +@ FIXME: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] +@ FIXME: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] +@ FIXME: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] +@ FIXME: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] +@ FIXME: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] vmov.i8 q8, #0x8 - vmov.i16 q8, #0x10 - vmov.i16 q8, #0x1000 - vmov.i32 q8, #0x20 - vmov.i32 q8, #0x2000 - vmov.i32 q8, #0x200000 - vmov.i32 q8, #0x20000000 - vmov.i32 q8, #0x20FF - vmov.i32 q8, #0x20FFFF - vmov.i64 q8, #0xFF0000FF0000FFFF +@ vmov.i16 q8, #0x10 +@ vmov.i16 q8, #0x1000 +@ vmov.i32 q8, #0x20 +@ vmov.i32 q8, #0x2000 +@ vmov.i32 q8, #0x200000 +@ vmov.i32 q8, #0x20000000 +@ vmov.i32 q8, #0x20FF +@ vmov.i32 q8, #0x20FFFF +@ vmov.i64 q8, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2] -@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] -@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2] -@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2] -@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] -@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] -@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] -@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] -@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] -@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] - - vmvn.i16 d16, #0x10 - vmvn.i16 d16, #0x1000 - vmvn.i32 d16, #0x20 - vmvn.i32 d16, #0x2000 - vmvn.i32 d16, #0x200000 - vmvn.i32 d16, #0x20000000 - vmvn.i32 d16, #0x20FF - vmvn.i32 d16, #0x20FFFF - -@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2] -@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2] -@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2] -@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] -@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] -@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] -@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] -@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] +@ FIXME: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] +@ FIXME: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2] +@ FIXME: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2] +@ FIXME: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] +@ FIXME: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] +@ FIXME: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] +@ FIXME: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] +@ FIXME: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] +@ FIXME: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] + +@ vmvn.i16 d16, #0x10 +@ vmvn.i16 d16, #0x1000 +@ vmvn.i32 d16, #0x20 +@ vmvn.i32 d16, #0x2000 +@ vmvn.i32 d16, #0x200000 +@ vmvn.i32 d16, #0x20000000 +@ vmvn.i32 d16, #0x20FF +@ vmvn.i32 d16, #0x20FFFF + +@ FIXME: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2] +@ FIXME: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2] +@ FIXME: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2] +@ FIXME: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] +@ FIXME: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] +@ FIXME: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] +@ FIXME: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] +@ FIXME: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] vmovl.s8 q8, d16 vmovl.s16 q8, d16 @@ -106,26 +105,26 @@ @ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3] @ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3] - vmov.s8 r0, d16[1] - vmov.s16 r0, d16[1] - vmov.u8 r0, d16[1] - vmov.u16 r0, d16[1] - vmov.32 r0, d16[1] - vmov.8 d16[1], r1 - vmov.16 d16[1], r1 - vmov.32 d16[1], r1 - vmov.8 d18[1], r1 - vmov.16 d18[1], r1 - vmov.32 d18[1], r1 - -@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] -@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] -@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] -@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] -@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] -@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] -@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] -@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] -@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] -@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] -@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] +@ vmov.s8 r0, d16[1] +@ vmov.s16 r0, d16[1] +@ vmov.u8 r0, d16[1] +@ vmov.u16 r0, d16[1] +@ vmov.32 r0, d16[1] +@ vmov.8 d16[1], r1 +@ vmov.16 d16[1], r1 +@ vmov.32 d16[1], r1 +@ vmov.8 d18[1], r1 +@ vmov.16 d18[1], r1 +@ vmov.32 d18[1], r1 + +@ FIXME: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] +@ FIXME: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] +@ FIXME: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] +@ FIXME: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] +@ FIXME: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] +@ FIXME: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] +@ FIXME: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] +@ FIXME: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] +@ FIXME: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] +@ FIXME: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] +@ FIXME: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] Modified: llvm/trunk/test/MC/ARM/neont2-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mov-encoding.s?rev=142293&r1=142292&r2=142293&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mov-encoding.s Mon Oct 17 17:26:03 2011 @@ -1,119 +1,131 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * .code 16 -@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xef] vmov.i8 d16, #0x8 -@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xef] - vmov.i16 d16, #0x10 -@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xef] - vmov.i16 d16, #0x1000 -@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xef] - vmov.i32 d16, #0x20 -@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xef] - vmov.i32 d16, #0x2000 -@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xef] - vmov.i32 d16, #0x200000 -@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xef] - vmov.i32 d16, #0x20000000 -@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xef] - vmov.i32 d16, #0x20FF -@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xef] - vmov.i32 d16, #0x20FFFF -@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xff] - vmov.i64 d16, #0xFF0000FF0000FFFF -@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xef] +@ vmov.i16 d16, #0x10 +@ vmov.i16 d16, #0x1000 +@ vmov.i32 d16, #0x20 +@ vmov.i32 d16, #0x2000 +@ vmov.i32 d16, #0x200000 +@ vmov.i32 d16, #0x20000000 +@ vmov.i32 d16, #0x20FF +@ vmov.i32 d16, #0x20FFFF +@ vmov.i64 d16, #0xFF0000FF0000FFFF + +@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0xc0,0xef,0x18,0x0e] +@ FIXME: vmov.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x10,0x08] +@ FIXME: vmov.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x10,0x0a] +@ FIXME: vmov.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x10,0x00] +@ FIXME: vmov.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x10,0x02] +@ FIXME: vmov.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x10,0x04] +@ FIXME: vmov.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x10,0x06] +@ FIXME: vmov.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x10,0x0c] +@ FIXME: vmov.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x10,0x0d] +@ FIXME: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x33,0x0e] + + vmov.i8 q8, #0x8 -@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xef] - vmov.i16 q8, #0x10 -@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xef] - vmov.i16 q8, #0x1000 -@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xef] - vmov.i32 q8, #0x20 -@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xef] - vmov.i32 q8, #0x2000 -@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xef] - vmov.i32 q8, #0x200000 -@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xef] - vmov.i32 q8, #0x20000000 -@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xef] - vmov.i32 q8, #0x20FF -@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xef] - vmov.i32 q8, #0x20FFFF -@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xff] - vmov.i64 q8, #0xFF0000FF0000FFFF -@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xef] - vmvn.i16 d16, #0x10 -@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xef] - vmvn.i16 d16, #0x1000 -@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xef] - vmvn.i32 d16, #0x20 -@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xef] - vmvn.i32 d16, #0x2000 -@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xef] - vmvn.i32 d16, #0x200000 -@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xef] - vmvn.i32 d16, #0x20000000 -@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xef] - vmvn.i32 d16, #0x20FF -@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xef] - vmvn.i32 d16, #0x20FFFF -@ CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xef] +@ vmov.i16 q8, #0x10 +@ vmov.i16 q8, #0x1000 +@ vmov.i32 q8, #0x20 +@ vmov.i32 q8, #0x2000 +@ vmov.i32 q8, #0x200000 +@ vmov.i32 q8, #0x20000000 +@ vmov.i32 q8, #0x20FF +@ vmov.i32 q8, #0x20FFFF +@ vmov.i64 q8, #0xFF0000FF0000FFFF + +@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0xc0,0xef,0x58,0x0e] +@ FIXME: vmov.i16 q8, #0x10 @ encoding: [0xc1,0xef,0x50,0x08] +@ FIXME: vmov.i16 q8, #0x1000 @ encoding: [0xc1,0xef,0x50,0x0a] +@ FIXME: vmov.i32 q8, #0x20 @ encoding: [0xc2,0xef,0x50,0x00] +@ FIXME: vmov.i32 q8, #0x2000 @ encoding: [0xc2,0xef,0x50,0x02] +@ FIXME: vmov.i32 q8, #0x200000 @ encoding: [0xc2,0xef,0x50,0x04] +@ FIXME: vmov.i32 q8, #0x20000000 @ encoding: [0xc2,0xef,0x50,0x06] +@ FIXME: vmov.i32 q8, #0x20FF @ encoding: [0xc2,0xef,0x50,0x0c] +@ FIXME: vmov.i32 q8, #0x20FFFF @ encoding: [0xc2,0xef,0x50,0x0d] +@ FIXME: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x73,0x0e] + + +@ vmvn.i16 d16, #0x10 +@ vmvn.i16 d16, #0x1000 +@ vmvn.i32 d16, #0x20 +@ vmvn.i32 d16, #0x2000 +@ vmvn.i32 d16, #0x200000 +@ vmvn.i32 d16, #0x20000000 +@ vmvn.i32 d16, #0x20FF +@ vmvn.i32 d16, #0x20FFFF + +@ FIXME: vmvn.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x30,0x08] +@ FIXME: vmvn.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x30,0x0a] +@ FIXME: vmvn.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x30,0x00] +@ FIXME: vmvn.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x30,0x02] +@ FIXME: vmvn.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x30,0x04] +@ FIXME: vmvn.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x30,0x06] +@ FIXME: vmvn.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x30,0x0c] +@ FIXME: vmvn.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x30,0x0d] + + vmovl.s8 q8, d16 -@ CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xef] vmovl.s16 q8, d16 -@ CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xef] vmovl.s32 q8, d16 -@ CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xff] vmovl.u8 q8, d16 -@ CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xff] vmovl.u16 q8, d16 -@ CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xff] vmovl.u32 q8, d16 -@ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xff] vmovn.i16 d16, q8 -@ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xff] vmovn.i32 d16, q8 -@ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xff] vmovn.i64 d16, q8 -@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xff] vqmovn.s16 d16, q8 -@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xff] vqmovn.s32 d16, q8 -@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xff] vqmovn.s64 d16, q8 -@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xff] vqmovn.u16 d16, q8 -@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xff] vqmovn.u32 d16, q8 -@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xff] vqmovn.u64 d16, q8 -@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xff] vqmovun.s16 d16, q8 -@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xff] vqmovun.s32 d16, q8 -@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xff] vqmovun.s64 d16, q8 -@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] - vmov.s8 r0, d16[1] -@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] - vmov.s16 r0, d16[1] -@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] - vmov.u8 r0, d16[1] -@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] - vmov.u16 r0, d16[1] -@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] - vmov.32 r0, d16[1] -@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] - vmov.8 d16[1], r1 -@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] - vmov.16 d16[1], r1 -@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] - vmov.32 d16[1], r1 -@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] - vmov.8 d18[1], r1 -@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] - vmov.16 d18[1], r1 -@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] - vmov.32 d18[1], r1 + +@ CHECK: vmovl.s8 q8, d16 @ encoding: [0xc8,0xef,0x30,0x0a] +@ CHECK: vmovl.s16 q8, d16 @ encoding: [0xd0,0xef,0x30,0x0a] +@ CHECK: vmovl.s32 q8, d16 @ encoding: [0xe0,0xef,0x30,0x0a] +@ CHECK: vmovl.u8 q8, d16 @ encoding: [0xc8,0xff,0x30,0x0a] +@ CHECK: vmovl.u16 q8, d16 @ encoding: [0xd0,0xff,0x30,0x0a] +@ CHECK: vmovl.u32 q8, d16 @ encoding: [0xe0,0xff,0x30,0x0a] +@ CHECK: vmovn.i16 d16, q8 @ encoding: [0xf2,0xff,0x20,0x02] +@ CHECK: vmovn.i32 d16, q8 @ encoding: [0xf6,0xff,0x20,0x02] +@ CHECK: vmovn.i64 d16, q8 @ encoding: [0xfa,0xff,0x20,0x02] +@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xf2,0xff,0xa0,0x02] +@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xf6,0xff,0xa0,0x02] +@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xfa,0xff,0xa0,0x02] +@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xf2,0xff,0xe0,0x02] +@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xf6,0xff,0xe0,0x02] +@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xfa,0xff,0xe0,0x02] +@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0xf2,0xff,0x60,0x02] +@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0xf6,0xff,0x60,0x02] +@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0xfa,0xff,0x60,0x02] + + +@ vmov.s8 r0, d16[1] +@ vmov.s16 r0, d16[1] +@ vmov.u8 r0, d16[1] +@ vmov.u16 r0, d16[1] +@ vmov.32 r0, d16[1] +@ vmov.8 d16[1], r1 +@ vmov.16 d16[1], r1 +@ vmov.32 d16[1], r1 +@ vmov.8 d18[1], r1 +@ vmov.16 d18[1], r1 +@ vmov.32 d18[1], r1 + +@ FIXME: vmov.s8 r0, d16[1] @ encoding: [0x50,0xee,0xb0,0x0b] +@ FIXME: vmov.s16 r0, d16[1] @ encoding: [0x10,0xee,0xf0,0x0b] +@ FIXME: vmov.u8 r0, d16[1] @ encoding: [0xd0,0xee,0xb0,0x0b] +@ FIXME: vmov.u16 r0, d16[1] @ encoding: [0x90,0xee,0xf0,0x0b] +@ FIXME: vmov.32 r0, d16[1] @ encoding: [0x30,0xee,0x90,0x0b] +@ FIXME: vmov.8 d16[1], r1 @ encoding: [0x40,0xee,0xb0,0x1b] +@ FIXME: vmov.16 d16[1], r1 @ encoding: [0x00,0xee,0xf0,0x1b] +@ FIXME: vmov.32 d16[1], r1 @ encoding: [0x20,0xee,0x90,0x1b] +@ FIXME: vmov.8 d18[1], r1 @ encoding: [0x42,0xee,0xb0,0x1b] +@ FIXME: vmov.16 d18[1], r1 @ encoding: [0x02,0xee,0xf0,0x1b] +@ FIXME: vmov.32 d18[1], r1 @ encoding: [0x22,0xee,0x90,0x1b] Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=142293&r1=142292&r2=142293&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Oct 17 17:26:03 2011 @@ -597,6 +597,7 @@ IMM("imm1_16"); IMM("imm1_32"); IMM("nModImm"); + IMM("nImmSplatI8"); IMM("imm0_7"); IMM("imm0_15"); IMM("imm0_255"); From isanbard at gmail.com Mon Oct 17 17:26:23 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Oct 2011 22:26:23 -0000 Subject: [llvm-commits] [llvm] r142294 - in /llvm/trunk/lib: CodeGen/SjLjEHPrepare.cpp Target/ARM/ARMInstrInfo.td Target/ARM/ARMInstrThumb.td Target/ARM/ARMInstrThumb2.td Message-ID: <20111017222623.F25072A6C12C@llvm.org> Author: void Date: Mon Oct 17 17:26:23 2011 New Revision: 142294 URL: http://llvm.org/viewvc/llvm-project?rev=142294&view=rev Log: Now Igor, throw the switch...give my creation life! Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the SjLj dispatch table in IR, where it frequently violates serveral assumptions -- in particular assumptions made by the landingpad instruction about what can branch to a landing pad and what cannot. Performing this in the back-end allows us to violate these assumptions without the IR getting angry at us. It also allows us to perform a small optimization. We can shove the address of the dispatch's basic block into the function context and not have to add code around the setjmp to check for the return value and jump to the dispatch. Neat, huh? Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=142294&r1=142293&r2=142294&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Mon Oct 17 17:26:23 2011 @@ -36,6 +36,7 @@ using namespace llvm; static cl::opt DisableOldSjLjEH("disable-old-sjlj-eh", cl::Hidden, + cl::init(true), cl::desc("Disable the old SjLj EH preparation pass")); STATISTIC(NumInvokes, "Number of invokes replaced"); Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=142294&r1=142293&r2=142294&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Oct 17 17:26:23 2011 @@ -4635,7 +4635,8 @@ // no encoding information is necessary. let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, - QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in { + QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1, + usesCustomInserter = 1 in { def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), NoItinerary, [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=142294&r1=142293&r2=142294&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Oct 17 17:26:23 2011 @@ -1259,7 +1259,8 @@ // preserve all of the callee-saved resgisters, which is exactly what we want. // $val is a scratch register for our use. let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], - hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in + hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, + usesCustomInserter = 1 in def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), AddrModeNone, 0, NoItinerary, "","", [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=142294&r1=142293&r2=142294&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Oct 17 17:26:23 2011 @@ -3088,7 +3088,8 @@ let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], - hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in { + hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, + usesCustomInserter = 1 in { def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), AddrModeNone, 0, NoItinerary, "", "", [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, @@ -3097,7 +3098,8 @@ let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], - hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in { + hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, + usesCustomInserter = 1 in { def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), AddrModeNone, 0, NoItinerary, "", "", [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, From dpatel at apple.com Mon Oct 17 17:30:34 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 17 Oct 2011 22:30:34 -0000 Subject: [llvm-commits] [llvm] r142295 - /llvm/trunk/lib/Analysis/DebugInfo.cpp Message-ID: <20111017223035.01A56312800A@llvm.org> Author: dpatel Date: Mon Oct 17 17:30:34 2011 New Revision: 142295 URL: http://llvm.org/viewvc/llvm-project?rev=142295&view=rev Log: Update DebugInfoFinder to match recent debug info encoding changes. Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=142295&r1=142294&r2=142295&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Mon Oct 17 17:30:34 2011 @@ -927,9 +927,30 @@ /// processModule - Process entire module and collect debug info. void DebugInfoFinder::processModule(Module &M) { - if (NamedMDNode *CU_Nodes = M.getNamedMetadata("llvm.dbg.cu")) - for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) - addCompileUnit(DICompileUnit(CU_Nodes->getOperand(i))); + if (NamedMDNode *CU_Nodes = M.getNamedMetadata("llvm.dbg.cu")) { + for (unsigned i = 0, e = CU_Nodes->getNumOperands(); i != e; ++i) { + DICompileUnit CU(CU_Nodes->getOperand(i)); + addCompileUnit(CU); + if (CU.getVersion() > LLVMDebugVersion10) { + DIArray GVs = CU.getGlobalVariables(); + for (unsigned i = 0, e = GVs.getNumElements(); i != e; ++i) { + DIGlobalVariable DIG(GVs.getElement(i)); + if (addGlobalVariable(DIG)) + processType(DIG.getType()); + } + DIArray SPs = CU.getSubprograms(); + for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i) + processSubprogram(DISubprogram(SPs.getElement(i))); + DIArray EnumTypes = CU.getEnumTypes(); + for (unsigned i = 0, e = EnumTypes.getNumElements(); i != e; ++i) + processType(DIType(EnumTypes.getElement(i))); + DIArray RetainedTypes = CU.getRetainedTypes(); + for (unsigned i = 0, e = RetainedTypes.getNumElements(); i != e; ++i) + processType(DIType(RetainedTypes.getElement(i))); + return; + } + } + } for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) for (Function::iterator FI = (*I).begin(), FE = (*I).end(); FI != FE; ++FI) From rafael.espindola at gmail.com Mon Oct 17 17:37:51 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 17 Oct 2011 22:37:51 -0000 Subject: [llvm-commits] [llvm] r142296 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/AsmParser/LLParser.cpp lib/Target/TargetData.cpp Message-ID: <20111017223751.F0FE2312800A@llvm.org> Author: rafael Date: Mon Oct 17 17:37:51 2011 New Revision: 142296 URL: http://llvm.org/viewvc/llvm-project?rev=142296&view=rev Log: 142288 broke the build: Linking CXX executable ../../bin/llvm-as ../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)' clang-3: error: linker command failed with exit code 1 (use -v to see invocation) Revert "Validate target data layout strings." This reverts commit 599d2d4c25d3aee63a21d9c67a88cd43bd971b7e. Modified: llvm/trunk/include/llvm/Target/TargetData.h llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/Target/TargetData.cpp Modified: llvm/trunk/include/llvm/Target/TargetData.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetData.h?rev=142296&r1=142295&r2=142296&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetData.h (original) +++ llvm/trunk/include/llvm/Target/TargetData.h Mon Oct 17 17:37:51 2011 @@ -44,7 +44,7 @@ AGGREGATE_ALIGN = 'a', ///< Aggregate alignment STACK_ALIGN = 's' ///< Stack objects alignment }; - + /// Target alignment element. /// /// Stores the alignment data associated with a given alignment type (pointer, @@ -80,7 +80,7 @@ unsigned StackNaturalAlign; ///< Stack natural alignment SmallVector LegalIntWidths; ///< Legal Integers. - + /// Alignments- Where the primitive type alignment data is stored. /// /// @sa init(). @@ -88,7 +88,7 @@ /// pointers vs. 64-bit pointers by extending TargetAlignment, but for now, /// we don't. SmallVector Alignments; - + /// InvalidAlignmentElem - This member is a signal that a requested alignment /// type and bit width were not found in the SmallVector. static const TargetAlignElem InvalidAlignmentElem; @@ -112,30 +112,19 @@ return &align != &InvalidAlignmentElem; } - /// Initialise a TargetData object with default values, ensure that the - /// target data pass is registered. - void init(); - public: /// Default ctor. /// /// @note This has to exist, because this is a pass, but it should never be /// used. TargetData(); - + /// Constructs a TargetData from a specification string. See init(). explicit TargetData(StringRef TargetDescription) : ImmutablePass(ID) { - std::string errMsg = parseSpecifier(TargetDescription, this); - assert(errMsg == "" && "Invalid target data layout string."); - (void)errMsg; + init(TargetDescription); } - /// Parses a target data specification string. Returns an error message - /// if the string is malformed, or the empty string on success. Optionally - /// initialises a TargetData object if passed a non-null pointer. - static std::string parseSpecifier(StringRef TargetDescription, TargetData* td = 0); - /// Initialize target data from properties stored in the module. explicit TargetData(const Module *M); @@ -152,6 +141,9 @@ ~TargetData(); // Not virtual, do not subclass this class + //! Parse a target data layout string and initialize TargetData alignments. + void init(StringRef TargetDescription); + /// Target endianness... bool isLittleEndian() const { return LittleEndian; } bool isBigEndian() const { return !LittleEndian; } @@ -160,7 +152,7 @@ /// TargetData. This representation is in the same format accepted by the /// string constructor above. std::string getStringRepresentation() const; - + /// isLegalInteger - This function returns true if the specified type is /// known to be a native integer type supported by the CPU. For example, /// i64 is not native on most 32-bit CPUs and i37 is not native on any known @@ -174,7 +166,7 @@ return true; return false; } - + bool isIllegalInteger(unsigned Width) const { return !isLegalInteger(Width); } @@ -259,11 +251,11 @@ /// getABITypeAlignment - Return the minimum ABI-required alignment for the /// specified type. unsigned getABITypeAlignment(Type *Ty) const; - + /// getABIIntegerTypeAlignment - Return the minimum ABI-required alignment for /// an integer type of the specified bitwidth. unsigned getABIIntegerTypeAlignment(unsigned BitWidth) const; - + /// getCallFrameTypeAlignment - Return the minimum ABI-required alignment /// for the specified type when it is part of a call frame. @@ -313,7 +305,7 @@ assert((Alignment & (Alignment-1)) == 0 && "Alignment must be power of 2!"); return (Val + (Alignment-1)) & ~UIntTy(Alignment-1); } - + static char ID; // Pass identification, replacement for typeid }; Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=142296&r1=142295&r2=142296&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Oct 17 17:37:51 2011 @@ -24,7 +24,6 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetData.h" using namespace llvm; static std::string getTypeString(Type *T) { @@ -261,14 +260,9 @@ return false; case lltok::kw_datalayout: Lex.Lex(); - LocTy SpecifierLoc = Lex.getLoc(); if (ParseToken(lltok::equal, "expected '=' after target datalayout") || ParseStringConstant(Str)) return true; - std::string errMsg = TargetData::parseSpecifier(Str); - if (errMsg != "") { - return Error(SpecifierLoc, errMsg); - } M->setDataLayout(Str); return false; } Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=142296&r1=142295&r2=142296&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Mon Oct 17 17:37:51 2011 @@ -125,15 +125,15 @@ //===----------------------------------------------------------------------===// /// getInt - Get an integer ignoring errors. -static int getInt(StringRef R) { - int Result = 0; +static unsigned getInt(StringRef R) { + unsigned Result = 0; R.getAsInteger(10, Result); return Result; } -void TargetData::init() { +void TargetData::init(StringRef Desc) { initializeTargetDataPass(*PassRegistry::getPassRegistry()); - + LayoutMap = 0; LittleEndian = false; PointerMemSize = 8; @@ -152,12 +152,6 @@ setAlignment(VECTOR_ALIGN, 8, 8, 64); // v2i32, v1i64, ... setAlignment(VECTOR_ALIGN, 16, 16, 128); // v16i8, v8i16, v4i32, ... setAlignment(AGGREGATE_ALIGN, 0, 8, 0); // struct -} - -std::string TargetData::parseSpecifier(StringRef Desc, TargetData *td) { - - if (td) - td->init(); while (!Desc.empty()) { std::pair Split = Desc.split('-'); @@ -175,54 +169,28 @@ switch (Specifier[0]) { case 'E': - if (td) - td->LittleEndian = false; + LittleEndian = false; break; case 'e': - if (td) - td->LittleEndian = true; + LittleEndian = true; break; - case 'p': { - // Pointer size. + case 'p': Split = Token.split(':'); - int PointerMemSizeBits = getInt(Split.first); - if (PointerMemSizeBits < 0 || PointerMemSizeBits % 8 != 0) - return "invalid pointer size, must be a positive 8-bit multiple"; - if (td) - td->PointerMemSize = PointerMemSizeBits / 8; - - // Pointer ABI alignment. + PointerMemSize = getInt(Split.first) / 8; Split = Split.second.split(':'); - int PointerABIAlignBits = getInt(Split.first); - if (PointerABIAlignBits < 0 || PointerABIAlignBits % 8 != 0) { - return "invalid pointer ABI alignment, " - "must be a positive 8-bit multiple"; - } - if (td) - td->PointerABIAlign = PointerABIAlignBits / 8; - - // Pointer preferred alignment. + PointerABIAlign = getInt(Split.first) / 8; Split = Split.second.split(':'); - int PointerPrefAlignBits = getInt(Split.first); - if (PointerPrefAlignBits < 0 || PointerPrefAlignBits % 8 != 0) { - return "invalid pointer preferred alignment, " - "must be a positive 8-bit multiple"; - } - if (td) { - td->PointerPrefAlign = PointerPrefAlignBits / 8; - if (td->PointerPrefAlign == 0) - td->PointerPrefAlign = td->PointerABIAlign; - } + PointerPrefAlign = getInt(Split.first) / 8; + if (PointerPrefAlign == 0) + PointerPrefAlign = PointerABIAlign; break; - } case 'i': case 'v': case 'f': case 'a': case 's': { AlignTypeEnum AlignType; - char field = Specifier[0]; - switch (field) { + switch (Specifier[0]) { default: case 'i': AlignType = INTEGER_ALIGN; break; case 'v': AlignType = VECTOR_ALIGN; break; @@ -230,66 +198,37 @@ case 'a': AlignType = AGGREGATE_ALIGN; break; case 's': AlignType = STACK_ALIGN; break; } - int Size = getInt(Specifier.substr(1)); - if (Size < 0) { - return std::string("invalid ") + field + "-size field, " - "must be positive"; - } - + unsigned Size = getInt(Specifier.substr(1)); Split = Token.split(':'); - int ABIAlignBits = getInt(Split.first); - if (ABIAlignBits < 0 || ABIAlignBits % 8 != 0) { - return std::string("invalid ") + field +"-abi-alignment field, " - "must be a positive 8-bit multiple"; - } - unsigned ABIAlign = ABIAlignBits / 8; + unsigned ABIAlign = getInt(Split.first) / 8; Split = Split.second.split(':'); - - int PrefAlignBits = getInt(Split.first); - if (PrefAlignBits < 0 || PrefAlignBits % 8 != 0) { - return std::string("invalid ") + field +"-preferred-alignment field, " - "must be a positive 8-bit multiple"; - } - unsigned PrefAlign = PrefAlignBits / 8; + unsigned PrefAlign = getInt(Split.first) / 8; if (PrefAlign == 0) PrefAlign = ABIAlign; - - if (td) - td->setAlignment(AlignType, ABIAlign, PrefAlign, Size); + setAlignment(AlignType, ABIAlign, PrefAlign, Size); break; } case 'n': // Native integer types. Specifier = Specifier.substr(1); do { - int Width = getInt(Specifier); - if (Width <= 0) { - return std::string("invalid native integer size \'") + Specifier.str() + - "\', must be a positive integer."; - } - if (td && Width != 0) - td->LegalIntWidths.push_back(Width); + if (unsigned Width = getInt(Specifier)) + LegalIntWidths.push_back(Width); Split = Token.split(':'); Specifier = Split.first; Token = Split.second; } while (!Specifier.empty() || !Token.empty()); break; - case 'S': { // Stack natural alignment. - int StackNaturalAlignBits = getInt(Specifier.substr(1)); - if (StackNaturalAlignBits < 0 || StackNaturalAlignBits % 8 != 0) { - return "invalid natural stack alignment (S-field), " - "must be a positive 8-bit multiple"; - } - if (td) - td->StackNaturalAlign = StackNaturalAlignBits / 8; + case 'S': // Stack natural alignment. + StackNaturalAlign = getInt(Specifier.substr(1)); + StackNaturalAlign /= 8; + // FIXME: Should we really be truncating these alingments and + // sizes silently? break; - } default: break; } } - - return ""; } /// Default ctor. @@ -303,9 +242,7 @@ TargetData::TargetData(const Module *M) : ImmutablePass(ID) { - std::string errMsg = parseSpecifier(M->getDataLayout(), this); - assert(errMsg == "" && "Module M has malformed target data layout string."); - (void)errMsg; + init(M->getDataLayout()); } void From grosbach at apple.com Mon Oct 17 17:41:42 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 17 Oct 2011 22:41:42 -0000 Subject: [llvm-commits] [llvm] r142297 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20111017224142.41450312800A@llvm.org> Author: grosbach Date: Mon Oct 17 17:41:42 2011 New Revision: 142297 URL: http://llvm.org/viewvc/llvm-project?rev=142297&view=rev Log: Tidy up. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=142297&r1=142296&r2=142297&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Oct 17 17:41:42 2011 @@ -921,7 +921,6 @@ int64_t Value = CE->getValue(); // i8 value splatted across 8 bytes. The immediate is just the 8 byte // value. -// return ((Value << 8) | (Value & 0xff)) == Value; return Value >= 0 && Value < 256; } From lhames at apple.com Mon Oct 17 17:50:31 2011 From: lhames at apple.com (Lang Hames) Date: Mon, 17 Oct 2011 15:50:31 -0700 Subject: [llvm-commits] [llvm] r142288 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/AsmParser/LLParser.cpp lib/Target/TargetData.cpp In-Reply-To: <4E9CAB90.3010102@gmail.com> References: <20111017220535.2A343312800A@llvm.org> <4E9CAB90.3010102@gmail.com> Message-ID: <66274180-07B4-49B2-85ED-35DEA2484412@apple.com> The function in question is in the patch. Guess it's a CMake issue. I'm looking into it now. - Lang. On Oct 17, 2011, at 3:26 PM, Rafael ?vila de Esp?ndola wrote: > looks like this broke the build: > > > Linking CXX executable ../../bin/llvm-as > ../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function > llvm::LLParser::ParseTargetDefinition(): error: undefined reference to > 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)' > clang-3: error: linker command failed with exit code 1 (use -v to see > invocation) > > Cheers, > Rafael > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From Xiaoyi.Guo at amd.com Mon Oct 17 17:51:55 2011 From: Xiaoyi.Guo at amd.com (Guo, Xiaoyi) Date: Mon, 17 Oct 2011 17:51:55 -0500 Subject: [llvm-commits] InstCombine patch to improve combining of nested ShuffleVectorInst's In-Reply-To: References: <27F465BDABE6954AABB2A4E3599BDAC702AD1527D4@sausexmbp02.amd.com> <27F465BDABE6954AABB2A4E3599BDAC702AD15286F@sausexmbp02.amd.com> <27F465BDABE6954AABB2A4E3599BDAC702AD152898@sausexmbp02.amd.com> Message-ID: <27F465BDABE6954AABB2A4E3599BDAC702AD31B52C@sausexmbp02.amd.com> Ping? -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Eli Friedman Sent: Tuesday, October 11, 2011 4:34 PM To: Guo, Xiaoyi Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] InstCombine patch to improve combining of nested ShuffleVectorInst's On Tue, Oct 11, 2011 at 4:16 PM, Guo, Xiaoyi wrote: > From the comment in the original code I understood that we want to be very conservative when doing the shuffle transformations. So I also tried to be careful and only do the transformation if no new mask is created, so the net effect is just removing some instructions, which I think should be as safe as the original code. Oh, I missed that part. Now I follow what you're doing. :) The concept is fine; I want to look over the mask transform logic a bit more closely before committing, though. -Eli > > Xiaoyi > > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu > [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Eli Friedman > Sent: Tuesday, October 11, 2011 4:10 PM > To: Guo, Xiaoyi > Cc: llvm-commits at cs.uiuc.edu > Subject: Re: [llvm-commits] InstCombine patch to improve combining of > nested ShuffleVectorInst's > > On Tue, Oct 11, 2011 at 3:54 PM, Guo, Xiaoyi wrote: >> Sorry. Try again... > > We intentionally don't do generalized shuffle transformations in instcombine at the moment because, at least at the time the shufflevector instruction was introduced, we didn't really trust the quality of the shuffle-matching code in the backends for shuffles which don't have an obvious single-instruction mapping. ?I'm not sure that situation has improved... > > -Eli > >> -----Original Message----- >> From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] >> Sent: Tuesday, October 11, 2011 3:06 PM >> To: Guo, Xiaoyi >> Cc: llvm-commits at cs.uiuc.edu >> Subject: Re: [llvm-commits] InstCombine patch to improve combining of >> nested ShuffleVectorInst's >> >> The attached patch only contain testcases! You probably missed >> something! :) >> >> On Tue, Oct 11, 2011 at 6:58 PM, Guo, Xiaoyi wrote: >>> The attached patch is to improve InstCombine to handle more cases of >>> nested ShuffleVectorInst's. New test cases are added to vec_shuffle.ll. >>> >>> >>> >>> It would be much appreciated if someone can review it and if ok help >>> to commit it. >>> >>> >>> >>> Thanks, >>> >>> Xiaoyi >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> >> >> >> >> -- >> Bruno Cardoso Lopes >> http://www.brunocardoso.cc >> >> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Mon Oct 17 17:53:25 2011 From: gohman at apple.com (Dan Gohman) Date: Mon, 17 Oct 2011 22:53:25 -0000 Subject: [llvm-commits] [llvm] r142298 - in /llvm/trunk: lib/Transforms/Scalar/ObjCARC.cpp test/Transforms/ObjCARC/retain-block-alloca.ll Message-ID: <20111017225325.B3C4A2A6C12C@llvm.org> Author: djg Date: Mon Oct 17 17:53:25 2011 New Revision: 142298 URL: http://llvm.org/viewvc/llvm-project?rev=142298&view=rev Log: Teach the ARC optimizer about the !clang.arc.copy_on_escape metadata tag on objc_retainBlock calls, which indicates that they may be optimized away. rdar://10211286. Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp llvm/trunk/test/Transforms/ObjCARC/retain-block-alloca.ll Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp?rev=142298&r1=142297&r2=142298&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Mon Oct 17 17:53:25 2011 @@ -1154,6 +1154,10 @@ /// opposed to objc_retain calls). bool IsRetainBlock; + /// CopyOnEscape - True if this the Calls are objc_retainBlock calls + /// which all have the !clang.arc.copy_on_escape metadata. + bool CopyOnEscape; + /// IsTailCallRelease - True of the objc_release calls are all marked /// with the "tail" keyword. bool IsTailCallRelease; @@ -1176,8 +1180,8 @@ SmallPtrSet ReverseInsertPts; RRInfo() : - KnownSafe(false), IsRetainBlock(false), IsTailCallRelease(false), - Partial(false), + KnownSafe(false), IsRetainBlock(false), CopyOnEscape(false), + IsTailCallRelease(false), Partial(false), ReleaseMetadata(0) {} void clear(); @@ -1187,6 +1191,7 @@ void RRInfo::clear() { KnownSafe = false; IsRetainBlock = false; + CopyOnEscape = false; IsTailCallRelease = false; Partial = false; ReleaseMetadata = 0; @@ -1294,6 +1299,7 @@ if (RRI.ReleaseMetadata != Other.RRI.ReleaseMetadata) RRI.ReleaseMetadata = 0; + RRI.CopyOnEscape = RRI.CopyOnEscape && Other.RRI.CopyOnEscape; RRI.KnownSafe = RRI.KnownSafe && Other.RRI.KnownSafe; RRI.IsTailCallRelease = RRI.IsTailCallRelease && Other.RRI.IsTailCallRelease; RRI.Calls.insert(Other.RRI.Calls.begin(), Other.RRI.Calls.end()); @@ -1482,6 +1488,10 @@ /// metadata. unsigned ImpreciseReleaseMDKind; + /// CopyOnEscape - The Metadata Kind for clang.arc.copy_on_escape + /// metadata. + unsigned CopyOnEscapeMDKind; + Constant *getRetainRVCallee(Module *M); Constant *getAutoreleaseRVCallee(Module *M); Constant *getReleaseCallee(Module *M); @@ -2360,9 +2370,12 @@ S.SetAtLeastOneRefCount(); S.DecrementNestCount(); - // An objc_retainBlock call with just a use still needs to be kept, - // because it may be copying a block from the stack to the heap. - if (Class == IC_RetainBlock && S.GetSeq() == S_Use) + // An non-copy-on-escape objc_retainBlock call with just a use still + // needs to be kept, because it may be copying a block from the stack + // to the heap. + if (Class == IC_RetainBlock && + !Inst->getMetadata(CopyOnEscapeMDKind) && + S.GetSeq() == S_Use) S.SetSeq(S_CanRelease); switch (S.GetSeq()) { @@ -2377,6 +2390,8 @@ // better to let it remain as the first instruction after a call. if (Class != IC_RetainRV) { S.RRI.IsRetainBlock = Class == IC_RetainBlock; + if (S.RRI.IsRetainBlock) + S.RRI.CopyOnEscape = !!Inst->getMetadata(CopyOnEscapeMDKind); Retains[Inst] = S.RRI; } S.ClearSequenceProgress(); @@ -2527,6 +2542,8 @@ S.SetSeq(S_Retain); S.RRI.clear(); S.RRI.IsRetainBlock = Class == IC_RetainBlock; + if (S.RRI.IsRetainBlock) + S.RRI.CopyOnEscape = !!Inst->getMetadata(CopyOnEscapeMDKind); // Don't check S.IsKnownIncremented() here because it's not // sufficient. S.RRI.KnownSafe = S.IsKnownNested(); @@ -2618,10 +2635,11 @@ S.SetSeq(S_Use); break; case S_Retain: - // An objc_retainBlock call may be responsible for copying the block - // data from the stack to the heap. Model this by moving it straight - // from S_Retain to S_Use. + // A non-copy-on-scape objc_retainBlock call may be responsible for + // copying the block data from the stack to the heap. Model this by + // moving it straight from S_Retain to S_Use. if (S.RRI.IsRetainBlock && + !S.RRI.CopyOnEscape && CanUse(Inst, Ptr, PA, Class)) { assert(S.RRI.ReverseInsertPts.empty()); S.RRI.ReverseInsertPts.insert(Inst); @@ -2713,6 +2731,9 @@ getRetainBlockCallee(M) : getRetainCallee(M), MyArg, "", InsertPt); Call->setDoesNotThrow(); + if (RetainsToMove.CopyOnEscape) + Call->setMetadata(CopyOnEscapeMDKind, + MDNode::get(M->getContext(), ArrayRef())); if (!RetainsToMove.IsRetainBlock) Call->setTailCall(); } @@ -2792,10 +2813,11 @@ // regardless of what possible decrements or uses lie between them. bool KnownSafe = isa(Arg); - // Same for stack storage, unless this is an objc_retainBlock call, - // which is responsible for copying the block data from the stack to - // the heap. - if (!I->second.IsRetainBlock && isa(Arg)) + // Same for stack storage, unless this is a non-copy-on-escape + // objc_retainBlock call, which is responsible for copying the block data + // from the stack to the heap. + if ((!I->second.IsRetainBlock || I->second.CopyOnEscape) && + isa(Arg)) KnownSafe = true; // A constant pointer can't be pointing to an object on the heap. It may @@ -2905,6 +2927,7 @@ // Merge the IsRetainBlock values. if (FirstRetain) { RetainsToMove.IsRetainBlock = NewReleaseRetainRRI.IsRetainBlock; + RetainsToMove.CopyOnEscape = NewReleaseRetainRRI.CopyOnEscape; FirstRetain = false; } else if (ReleasesToMove.IsRetainBlock != NewReleaseRetainRRI.IsRetainBlock) @@ -2912,6 +2935,9 @@ // objc_retain and the other uses objc_retainBlock. goto next_retain; + // Merge the CopyOnEscape values. + RetainsToMove.CopyOnEscape &= NewReleaseRetainRRI.CopyOnEscape; + // Collect the optimal insertion points. if (!KnownSafe) for (SmallPtrSet::const_iterator @@ -3265,6 +3291,8 @@ // Identify the imprecise release metadata kind. ImpreciseReleaseMDKind = M.getContext().getMDKindID("clang.imprecise_release"); + CopyOnEscapeMDKind = + M.getContext().getMDKindID("clang.arc.copy_on_escape"); // Intuitively, objc_retain and others are nocapture, however in practice // they are not, because they return their argument value. And objc_release Modified: llvm/trunk/test/Transforms/ObjCARC/retain-block-alloca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ObjCARC/retain-block-alloca.ll?rev=142298&r1=142297&r2=142298&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ObjCARC/retain-block-alloca.ll (original) +++ llvm/trunk/test/Transforms/ObjCARC/retain-block-alloca.ll Mon Oct 17 17:53:25 2011 @@ -1,11 +1,6 @@ ; RUN: opt -S -objc-arc < %s | FileCheck %s ; rdar://10209613 -; CHECK: define void @test -; CHECK: %3 = call i8* @objc_retainBlock(i8* %2) nounwind -; CHECK: @objc_msgSend -; CHECK-NEXT: @objc_release(i8* %3) - %0 = type opaque %struct.__block_descriptor = type { i64, i64 } @@ -13,6 +8,10 @@ @__block_descriptor_tmp = external hidden constant { i64, i64, i8*, i8*, i8*, i8* } @"\01L_OBJC_SELECTOR_REFERENCES_" = external hidden global i8*, section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip" +; CHECK: define void @test( +; CHECK: %3 = call i8* @objc_retainBlock(i8* %2) nounwind +; CHECK: @objc_msgSend +; CHECK-NEXT: @objc_release(i8* %3) define void @test(%0* %array) uwtable { entry: %block = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, align 8 @@ -41,6 +40,43 @@ ret void } +; Same as test, but the objc_retainBlock has a clang.arc.copy_on_escape +; tag so it's safe to delete. + +; CHECK: define void @test_with_COE( +; CHECK-NOT: @objc_retainBlock +; CHECK: @objc_msgSend +; CHECK: @objc_release +; CHECK-NOT: @objc_release +; CHECK: } +define void @test_with_COE(%0* %array) uwtable { +entry: + %block = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>, align 8 + %0 = bitcast %0* %array to i8* + %1 = tail call i8* @objc_retain(i8* %0) nounwind + %block.isa = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, i64 0, i32 0 + store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** %block.isa, align 8 + %block.flags = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, i64 0, i32 1 + store i32 1107296256, i32* %block.flags, align 8 + %block.reserved = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, i64 0, i32 2 + store i32 0, i32* %block.reserved, align 4 + %block.invoke = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, i64 0, i32 3 + store i8* bitcast (void (i8*)* @__test_block_invoke_0 to i8*), i8** %block.invoke, align 8 + %block.descriptor = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, i64 0, i32 4 + store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8*, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** %block.descriptor, align 8 + %block.captured = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block, i64 0, i32 5 + store %0* %array, %0** %block.captured, align 8 + %2 = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %0* }>* %block to i8* + %3 = call i8* @objc_retainBlock(i8* %2) nounwind, !clang.arc.copy_on_escape !0 + %tmp2 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8 + call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i8*)*)(i8* %0, i8* %tmp2, i8* %3) + call void @objc_release(i8* %3) nounwind + %strongdestroy = load %0** %block.captured, align 8 + %4 = bitcast %0* %strongdestroy to i8* + call void @objc_release(i8* %4) nounwind, !clang.imprecise_release !0 + ret void +} + declare i8* @objc_retain(i8*) declare void @__test_block_invoke_0(i8* nocapture) uwtable From jabbey at arxan.com Mon Oct 17 17:56:15 2011 From: jabbey at arxan.com (Joe Abbey) Date: Mon, 17 Oct 2011 17:56:15 -0500 Subject: [llvm-commits] Removing additional warnings In-Reply-To: References: Message-ID: Updated after Bill's Dr. Frankenstein maneuver. Joe Abbey Software Architect Arxan Technologies, Inc. 1305 Cumberland Ave, Ste 215 West Lafayette, IN 47906 jabbey at arxan.com www.arxan.com On Oct 17, 2011, at 5:44 PM, Joe Abbey wrote: This resolves the last couple warnings: MipsISelLowering.cpp:791:12: warning: variable ?dl? set but not used [-Wunused-but-set-variable] ARMISelDAGToDAG.cpp:2319:12: warning: variable ?DL? set but not used [-Wunused-but-set-variable] as well as some warnings when tbl-genning thumb2 Cheers, Joe Abbey Software Architect Arxan Technologies, Inc. 1305 Cumberland Ave, Ste 215 West Lafayette, IN 47906 jabbey at arxan.com www.arxan.com _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/fb9575f0/attachment.html -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: llvm_warning_free_updated.txt Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/fb9575f0/attachment.txt From mcrosier at apple.com Mon Oct 17 17:54:23 2011 From: mcrosier at apple.com (Chad Rosier) Date: Mon, 17 Oct 2011 22:54:23 -0000 Subject: [llvm-commits] [llvm] r142299 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20111017225423.9EA3B2A6C12C@llvm.org> Author: mcrosier Date: Mon Oct 17 17:54:23 2011 New Revision: 142299 URL: http://llvm.org/viewvc/llvm-project?rev=142299&view=rev Log: Add a few FIXME comments. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=142299&r1=142298&r2=142299&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Oct 17 17:54:23 2011 @@ -1743,6 +1743,7 @@ CCValAssign &VA = ValLocs[0]; // Don't bother handling odd stuff for now. + // FIXME: Should be able to handle i1, i8, and/or i16 return types. if (VA.getLocInfo() != CCValAssign::Full) return false; // Only handle register returns for now. @@ -1934,6 +1935,7 @@ Type *ArgTy = (*i)->getType(); MVT ArgVT; + // FIXME: Should be able to handle i1, i8, and/or i16 parameters. if (!isTypeLegal(ArgTy, ArgVT)) return false; unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); From nicholas at mxc.ca Mon Oct 17 18:05:28 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 17 Oct 2011 23:05:28 -0000 Subject: [llvm-commits] [llvm] r142300 - in /llvm/trunk: include/llvm/MC/ include/llvm/Support/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCParser/ lib/Target/ lib/Target/PTX/ test/CodeGen/X86/ test/MC/AsmParser/ tools/llc/ tools/llvm-mc/ Message-ID: <20111017230529.111262A6C12C@llvm.org> Author: nicholas Date: Mon Oct 17 18:05:28 2011 New Revision: 142300 URL: http://llvm.org/viewvc/llvm-project?rev=142300&view=rev Log: Add support for a new extension to the .file directive: .file filenumber "directory" "filename" This removes one join+split of the directory+filename in MC internals. Because bitcode files have independent fields for directory and filenames in debug info, this patch may change the .o files written by existing .bc files. Modified: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/include/llvm/Support/TargetRegistry.h llvm/trunk/include/llvm/Target/TargetMachine.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/lib/MC/MCLoggingStreamer.cpp llvm/trunk/lib/MC/MCNullStreamer.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCPureStreamer.cpp llvm/trunk/lib/MC/MCStreamer.cpp llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp llvm/trunk/lib/Target/TargetMachine.cpp llvm/trunk/test/CodeGen/X86/dbg-file-name.ll llvm/trunk/test/MC/AsmParser/directive_file.s llvm/trunk/tools/llc/llc.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Mon Oct 17 18:05:28 2011 @@ -204,7 +204,8 @@ /// @{ /// GetDwarfFile - creates an entry in the dwarf file and directory tables. - unsigned GetDwarfFile(StringRef FileName, unsigned FileNumber); + unsigned GetDwarfFile(StringRef Directory, StringRef FileName, + unsigned FileNumber); bool isValidDwarfFileNumber(unsigned FileNumber); Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Mon Oct 17 18:05:28 2011 @@ -505,7 +505,8 @@ /// EmitDwarfFileDirective - Associate a filename with a specified logical /// file number. This implements the DWARF2 '.file 4 "foo.c"' assembler /// directive. - virtual bool EmitDwarfFileDirective(unsigned FileNo,StringRef Filename); + virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Directory, + StringRef Filename); /// EmitDwarfLocDirective - This implements the DWARF2 // '.loc fileno lineno ...' assembler directive. @@ -613,6 +614,7 @@ bool isVerboseAsm, bool useLoc, bool useCFI, + bool useDwarfDirectory, MCInstPrinter *InstPrint = 0, MCCodeEmitter *CE = 0, MCAsmBackend *TAB = 0, Modified: llvm/trunk/include/llvm/Support/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetRegistry.h?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Support/TargetRegistry.h Mon Oct 17 18:05:28 2011 @@ -50,6 +50,7 @@ MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, bool isVerboseAsm, bool useLoc, bool useCFI, + bool useDwarfDirectory, MCInstPrinter *InstPrint, MCCodeEmitter *CE, MCAsmBackend *TAB, @@ -116,6 +117,7 @@ bool isVerboseAsm, bool useLoc, bool useCFI, + bool useDwarfDirectory, MCInstPrinter *InstPrint, MCCodeEmitter *CE, MCAsmBackend *TAB, @@ -426,13 +428,14 @@ bool isVerboseAsm, bool useLoc, bool useCFI, + bool useDwarfDirectory, MCInstPrinter *InstPrint, MCCodeEmitter *CE, MCAsmBackend *TAB, bool ShowInst) const { // AsmStreamerCtorFn is default to llvm::createAsmStreamer return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc, useCFI, - InstPrint, CE, TAB, ShowInst); + useDwarfDirectory, InstPrint, CE, TAB, ShowInst); } /// @} Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Oct 17 18:05:28 2011 @@ -101,6 +101,7 @@ unsigned MCSaveTempLabels : 1; unsigned MCUseLoc : 1; unsigned MCUseCFI : 1; + unsigned MCUseDwarfDirectory : 1; public: virtual ~TargetMachine(); @@ -196,6 +197,14 @@ /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives. void setMCUseCFI(bool Value) { MCUseCFI = Value; } + /// hasMCUseDwarfDirectory - Check whether we should use .file directives with + /// explicit directories. + bool hasMCUseDwarfDirectory() const { return MCUseDwarfDirectory; } + + /// setMCUseDwarfDirectory - Set whether all we should use .file directives + /// with explicit directories. + void setMCUseDwarfDirectory(bool Value) { MCUseDwarfDirectory = Value; } + /// getRelocationModel - Returns the code generation relocation model. The /// choices are static, PIC, and dynamic-no-pic, and target default. Reloc::Model getRelocationModel() const; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Oct 17 18:05:28 2011 @@ -442,23 +442,21 @@ if (FileName.empty()) return GetOrCreateSourceID("", StringRef()); - // MCStream expects full path name as filename. - if (!DirName.empty() && !sys::path::is_absolute(FileName)) { - SmallString<128> FullPathName = DirName; - sys::path::append(FullPathName, FileName); - // Here FullPathName will be copied into StringMap by GetOrCreateSourceID. - return GetOrCreateSourceID(StringRef(FullPathName), StringRef()); - } - - StringMapEntry &Entry = SourceIdMap.GetOrCreateValue(FileName); - if (Entry.getValue()) - return Entry.getValue(); - - unsigned SrcId = SourceIdMap.size(); - Entry.setValue(SrcId); + unsigned SrcId = SourceIdMap.size()+1; + std::pair SourceName = + std::make_pair(FileName, DirName); + std::pair, unsigned> Entry = + make_pair(SourceName, SrcId); + + std::map, unsigned>::iterator I; + bool NewlyInserted; + tie(I, NewlyInserted) = SourceIdMap.insert(Entry); + if (!NewlyInserted) + return I->second; // Print out a .file directive to specify files for .loc directives. - Asm->OutStreamer.EmitDwarfFileDirective(SrcId, Entry.getKey()); + Asm->OutStreamer.EmitDwarfFileDirective(SrcId, Entry.first.second, + Entry.first.first); return SrcId; } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Oct 17 18:05:28 2011 @@ -26,6 +26,7 @@ #include "llvm/ADT/UniqueVector.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/DebugLoc.h" +#include namespace llvm { @@ -207,9 +208,9 @@ /// std::vector Abbreviations; - /// SourceIdMap - Source id map, i.e. pair of directory id and source file - /// id mapped to a unique id. - StringMap SourceIdMap; + /// SourceIdMap - Source id map, i.e. pair of source filename and directory + /// mapped to a unique id. + std::map, unsigned> SourceIdMap; /// StringPool - A String->Symbol mapping of strings used by indirect /// references. Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Mon Oct 17 18:05:28 2011 @@ -159,6 +159,7 @@ getVerboseAsm(), hasMCUseLoc(), hasMCUseCFI(), + hasMCUseDwarfDirectory(), InstPrinter, MCE, MAB, ShowMCInst); Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Mon Oct 17 18:05:28 2011 @@ -29,6 +29,7 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Support/Format.h" #include "llvm/Support/FormattedStream.h" +#include "llvm/Support/PathV2.h" #include using namespace llvm; @@ -50,6 +51,7 @@ unsigned ShowInst : 1; unsigned UseLoc : 1; unsigned UseCFI : 1; + unsigned UseDwarfDirectory : 1; enum EHSymbolFlags { EHGlobal = 1, EHWeakDefinition = 1 << 1, @@ -63,13 +65,15 @@ public: MCAsmStreamer(MCContext &Context, formatted_raw_ostream &os, bool isVerboseAsm, bool useLoc, bool useCFI, + bool useDwarfDirectory, MCInstPrinter *printer, MCCodeEmitter *emitter, MCAsmBackend *asmbackend, bool showInst) : MCStreamer(Context), OS(os), MAI(Context.getAsmInfo()), InstPrinter(printer), Emitter(emitter), AsmBackend(asmbackend), CommentStream(CommentToEmit), IsVerboseAsm(isVerboseAsm), - ShowInst(showInst), UseLoc(useLoc), UseCFI(useCFI) { + ShowInst(showInst), UseLoc(useLoc), UseCFI(useCFI), + UseDwarfDirectory(useDwarfDirectory) { if (InstPrinter && IsVerboseAsm) InstPrinter->setCommentStream(CommentStream); } @@ -196,7 +200,8 @@ unsigned char Value = 0); virtual void EmitFileDirective(StringRef Filename); - virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Filename); + virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Directory, + StringRef Filename); virtual void EmitDwarfLocDirective(unsigned FileNo, unsigned Line, unsigned Column, unsigned Flags, unsigned Isa, unsigned Discriminator, @@ -748,13 +753,27 @@ EmitEOL(); } -bool MCAsmStreamer::EmitDwarfFileDirective(unsigned FileNo, StringRef Filename){ +bool MCAsmStreamer::EmitDwarfFileDirective(unsigned FileNo, StringRef Directory, + StringRef Filename) { + if (!UseDwarfDirectory && !Directory.empty()) { + if (sys::path::is_absolute(Filename)) + return EmitDwarfFileDirective(FileNo, "", Filename); + + SmallString<128> FullPathName = Directory; + sys::path::append(FullPathName, Filename); + return EmitDwarfFileDirective(FileNo, "", FullPathName); + } + if (UseLoc) { OS << "\t.file\t" << FileNo << ' '; + if (!Directory.empty()) { + PrintQuotedString(Directory, OS); + OS << ' '; + } PrintQuotedString(Filename, OS); EmitEOL(); } - return this->MCStreamer::EmitDwarfFileDirective(FileNo, Filename); + return this->MCStreamer::EmitDwarfFileDirective(FileNo, Directory, Filename); } void MCAsmStreamer::EmitDwarfLocDirective(unsigned FileNo, unsigned Line, @@ -1271,9 +1290,9 @@ MCStreamer *llvm::createAsmStreamer(MCContext &Context, formatted_raw_ostream &OS, bool isVerboseAsm, bool useLoc, - bool useCFI, MCInstPrinter *IP, - MCCodeEmitter *CE, MCAsmBackend *MAB, - bool ShowInst) { + bool useCFI, bool useDwarfDirectory, + MCInstPrinter *IP, MCCodeEmitter *CE, + MCAsmBackend *MAB, bool ShowInst) { return new MCAsmStreamer(Context, OS, isVerboseAsm, useLoc, useCFI, - IP, CE, MAB, ShowInst); + useDwarfDirectory, IP, CE, MAB, ShowInst); } Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Mon Oct 17 18:05:28 2011 @@ -248,7 +248,8 @@ /// directory tables. If the file number has already been allocated it is an /// error and zero is returned and the client reports the error, else the /// allocated file number is returned. The file numbers may be in any order. -unsigned MCContext::GetDwarfFile(StringRef FileName, unsigned FileNumber) { +unsigned MCContext::GetDwarfFile(StringRef Directory, StringRef FileName, + unsigned FileNumber) { // TODO: a FileNumber of zero says to use the next available file number. // Note: in GenericAsmParser::ParseDirectiveFile() FileNumber was checked // to not be less than one. This needs to be change to be not less than zero. @@ -266,19 +267,21 @@ // Get the new MCDwarfFile slot for this FileNumber. MCDwarfFile *&File = MCDwarfFiles[FileNumber]; - // Separate the directory part from the basename of the FileName. - std::pair Slash = FileName.rsplit('/'); + if (Directory.empty()) { + // Separate the directory part from the basename of the FileName. + std::pair Slash = FileName.rsplit('/'); + Directory = Slash.second; + if (!Directory.empty()) + FileName = Slash.first; + } // Find or make a entry in the MCDwarfDirs vector for this Directory. - StringRef Name; - unsigned DirIndex; // Capture directory name. - if (Slash.second.empty()) { - Name = Slash.first; - DirIndex = 0; // For FileNames with no directories a DirIndex of 0 is used. + unsigned DirIndex; + if (Directory.empty()) { + // For FileNames with no directories a DirIndex of 0 is used. + DirIndex = 0; } else { - StringRef Directory = Slash.first; - Name = Slash.second; DirIndex = 0; for (unsigned End = MCDwarfDirs.size(); DirIndex < End; DirIndex++) { if (Directory == MCDwarfDirs[DirIndex]) @@ -291,16 +294,16 @@ } // The DirIndex is one based, as DirIndex of 0 is used for FileNames with // no directories. MCDwarfDirs[] is unlike MCDwarfFiles[] in that the - // directory names are stored at MCDwarfDirs[DirIndex-1] where FileNames are - // stored at MCDwarfFiles[FileNumber].Name . + // directory names are stored at MCDwarfDirs[DirIndex-1] where FileNames + // are stored at MCDwarfFiles[FileNumber].Name . DirIndex++; } // Now make the MCDwarfFile entry and place it in the slot in the MCDwarfFiles // vector. - char *Buf = static_cast(Allocate(Name.size())); - memcpy(Buf, Name.data(), Name.size()); - File = new (*this) MCDwarfFile(StringRef(Buf, Name.size()), DirIndex); + char *Buf = static_cast(Allocate(FileName.size())); + memcpy(Buf, FileName.data(), FileName.size()); + File = new (*this) MCDwarfFile(StringRef(Buf, FileName.size()), DirIndex); // return the allocated FileNumber. return FileNumber; Modified: llvm/trunk/lib/MC/MCLoggingStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCLoggingStreamer.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCLoggingStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCLoggingStreamer.cpp Mon Oct 17 18:05:28 2011 @@ -208,10 +208,12 @@ return Child->EmitFileDirective(Filename); } - virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Filename) { + virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Directory, + StringRef Filename) { LogCall("EmitDwarfFileDirective", - "FileNo:" + Twine(FileNo) + " Filename:" + Filename); - return Child->EmitDwarfFileDirective(FileNo, Filename); + "FileNo:" + Twine(FileNo) + " Directory:" + Directory + + " Filename:" + Filename); + return Child->EmitDwarfFileDirective(FileNo, Directory, Filename); } virtual void EmitDwarfLocDirective(unsigned FileNo, unsigned Line, Modified: llvm/trunk/lib/MC/MCNullStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCNullStreamer.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCNullStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCNullStreamer.cpp Mon Oct 17 18:05:28 2011 @@ -83,7 +83,8 @@ unsigned char Value = 0) {} virtual void EmitFileDirective(StringRef Filename) {} - virtual bool EmitDwarfFileDirective(unsigned FileNo,StringRef Filename) { + virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Directory, + StringRef Filename) { return false; } virtual void EmitDwarfLocDirective(unsigned FileNo, unsigned Line, Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Oct 17 18:05:28 2011 @@ -2303,7 +2303,8 @@ } /// ParseDirectiveFile -/// ::= .file [number] string +/// ::= .file [number] filename +/// ::= .file number directory filename bool GenericAsmParser::ParseDirectiveFile(StringRef, SMLoc DirectiveLoc) { // FIXME: I'm not sure what this is. int64_t FileNumber = -1; @@ -2319,17 +2320,31 @@ if (getLexer().isNot(AsmToken::String)) return TokError("unexpected token in '.file' directive"); - StringRef Filename = getTok().getString(); - Filename = Filename.substr(1, Filename.size()-2); + // Usually the directory and filename together, otherwise just the directory. + StringRef Path = getTok().getString(); + Path = Path.substr(1, Path.size()-2); Lex(); + StringRef Directory; + StringRef Filename; + if (getLexer().is(AsmToken::String)) { + if (FileNumber == -1) + return TokError("explicit path specified, but no file number"); + Filename = getTok().getString(); + Filename = Filename.substr(1, Filename.size()-2); + Directory = Path; + Lex(); + } else { + Filename = Path; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.file' directive"); if (FileNumber == -1) getStreamer().EmitFileDirective(Filename); else { - if (getStreamer().EmitDwarfFileDirective(FileNumber, Filename)) + if (getStreamer().EmitDwarfFileDirective(FileNumber, Directory, Filename)) Error(FileNumberLoc, "file number already allocated"); } Modified: llvm/trunk/lib/MC/MCPureStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCPureStreamer.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCPureStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCPureStreamer.cpp Mon Oct 17 18:05:28 2011 @@ -93,7 +93,8 @@ virtual void EmitFileDirective(StringRef Filename) { report_fatal_error("unsupported directive in pure streamer"); } - virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Filename) { + virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Directory, + StringRef Filename) { report_fatal_error("unsupported directive in pure streamer"); return false; } Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Mon Oct 17 18:05:28 2011 @@ -142,8 +142,9 @@ } bool MCStreamer::EmitDwarfFileDirective(unsigned FileNo, + StringRef Directory, StringRef Filename) { - return getContext().GetDwarfFile(Filename, FileNo) == 0; + return getContext().GetDwarfFile(Directory, Filename, FileNo) == 0; } void MCStreamer::EmitDwarfLocDirective(unsigned FileNo, unsigned Line, Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Mon Oct 17 18:05:28 2011 @@ -535,7 +535,7 @@ Entry.setValue(SrcId); // Print out a .file directive to specify files for .loc directives. - OutStreamer.EmitDwarfFileDirective(SrcId, Entry.getKey()); + OutStreamer.EmitDwarfFileDirective(SrcId, "", Entry.getKey()); return SrcId; } @@ -594,4 +594,3 @@ RegisterAsmPrinter X(ThePTX32Target); RegisterAsmPrinter Y(ThePTX64Target); } - Modified: llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXMCAsmStreamer.cpp Mon Oct 17 18:05:28 2011 @@ -22,6 +22,7 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Support/Format.h" #include "llvm/Support/FormattedStream.h" +#include "llvm/Support/PathV2.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -165,7 +166,8 @@ unsigned char Value = 0); virtual void EmitFileDirective(StringRef Filename); - virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Filename); + virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Directory, + StringRef Filename); virtual void EmitInstruction(const MCInst &Inst); @@ -489,11 +491,20 @@ // FIXME: should we inherit from MCAsmStreamer? bool PTXMCAsmStreamer::EmitDwarfFileDirective(unsigned FileNo, - StringRef Filename){ + StringRef Directory, + StringRef Filename) { + if (!Directory.empty()) { + if (sys::path::is_absolute(Filename)) + return EmitDwarfFileDirective(FileNo, "", Filename); + SmallString<128> FullPathName = Directory; + sys::path::append(FullPathName, Filename); + return EmitDwarfFileDirective(FileNo, "", FullPathName); + } + OS << "\t.file\t" << FileNo << ' '; PrintQuotedString(Filename, OS); EmitEOL(); - return this->MCStreamer::EmitDwarfFileDirective(FileNo, Filename); + return this->MCStreamer::EmitDwarfFileDirective(FileNo, Directory, Filename); } void PTXMCAsmStreamer::AddEncodingComment(const MCInst &Inst) {} @@ -535,6 +546,7 @@ MCStreamer *createPTXAsmStreamer(MCContext &Context, formatted_raw_ostream &OS, bool isVerboseAsm, bool useLoc, bool useCFI, + bool useDwarfDirectory, MCInstPrinter *IP, MCCodeEmitter *CE, MCAsmBackend *MAB, bool ShowInst) { Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Mon Oct 17 18:05:28 2011 @@ -46,7 +46,7 @@ namespace llvm { MCStreamer *createPTXAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, bool isVerboseAsm, bool useLoc, - bool useCFI, + bool useCFI, bool useDwarfDirectory, MCInstPrinter *InstPrint, MCCodeEmitter *CE, MCAsmBackend *MAB, @@ -157,6 +157,7 @@ true, /* verbose asm */ hasMCUseLoc(), hasMCUseCFI(), + hasMCUseDwarfDirectory(), InstPrinter, MCE, MAB, false /* show MC encoding */); Modified: llvm/trunk/lib/Target/TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/TargetMachine.cpp Mon Oct 17 18:05:28 2011 @@ -197,7 +197,8 @@ MCNoExecStack(false), MCSaveTempLabels(false), MCUseLoc(true), - MCUseCFI(true) { + MCUseCFI(true), + MCUseDwarfDirectory(true) { // Typically it will be subtargets that will adjust FloatABIType from Default // to Soft or Hard. if (UseSoftFloat) Modified: llvm/trunk/test/CodeGen/X86/dbg-file-name.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-file-name.ll?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-file-name.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-file-name.ll Mon Oct 17 18:05:28 2011 @@ -1,7 +1,7 @@ ; RUN: llc -mtriple x86_64-apple-darwin10.0.0 < %s | FileCheck %s ; Radar 8884898 -; CHECK: file 1 "/Users/manav/one/two{{/|\\\\}}simple.c" +; CHECK: file 1 "/Users/manav/one/two" "simple.c" declare i32 @printf(i8*, ...) nounwind Modified: llvm/trunk/test/MC/AsmParser/directive_file.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_file.s?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_file.s (original) +++ llvm/trunk/test/MC/AsmParser/directive_file.s Mon Oct 17 18:05:28 2011 @@ -2,7 +2,8 @@ .file "hello" .file 1 "world" + .file 2 "directory" "file" # CHECK: .file "hello" # CHECK: .file 1 "world" - +# CHECK: .file 2 "directory" "file" Modified: llvm/trunk/tools/llc/llc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/tools/llc/llc.cpp (original) +++ llvm/trunk/tools/llc/llc.cpp Mon Oct 17 18:05:28 2011 @@ -133,6 +133,9 @@ cl::opt DisableCFI("disable-cfi", cl::Hidden, cl::desc("Do not use .cfi_* directives")); +cl::opt DisableDwarfDirectory("disable-dwarf-directory", cl::Hidden, + cl::desc("Do not use file directives with an explicit directory.")); + static cl::opt DisableRedZone("disable-red-zone", cl::desc("Do not emit code that uses the red zone."), @@ -316,6 +319,9 @@ if (DisableCFI) Target.setMCUseCFI(false); + if (DisableDwarfDirectory) + Target.setMCUseDwarfDirectory(false); + // Disable .loc support for older OS X versions. if (TheTriple.isMacOSX() && TheTriple.isMacOSXVersionLT(10, 6)) Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=142300&r1=142299&r2=142300&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Mon Oct 17 18:05:28 2011 @@ -409,8 +409,10 @@ } Str.reset(TheTarget->createAsmStreamer(Ctx, FOS, /*asmverbose*/true, /*useLoc*/ true, - /*useCFI*/ true, IP, CE, MAB, - ShowInst)); + /*useCFI*/ true, + /*useDwarfDirectory*/ true, + IP, CE, MAB, ShowInst)); + } else if (FileType == OFT_Null) { Str.reset(createNullStreamer(Ctx)); } else { @@ -515,4 +517,3 @@ return 0; } - From grosbach at apple.com Mon Oct 17 18:09:09 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 17 Oct 2011 23:09:09 -0000 Subject: [llvm-commits] [llvm] r142303 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neont2-mov-encoding.s utils/TableGen/EDEmitter.cpp Message-ID: <20111017230910.102F12A6C12C@llvm.org> Author: grosbach Date: Mon Oct 17 18:09:09 2011 New Revision: 142303 URL: http://llvm.org/viewvc/llvm-project?rev=142303&view=rev Log: ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/neont2-mov-encoding.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142303&r1=142302&r2=142303&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 17 18:09:09 2011 @@ -24,6 +24,11 @@ let PrintMethod = "printNEONModImmOperand"; let ParserMatchClass = nImmSplatI8AsmOperand; } +def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; } +def nImmSplatI16 : Operand { + let PrintMethod = "printNEONModImmOperand"; + let ParserMatchClass = nImmSplatI16AsmOperand; +} def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; } def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; } @@ -3743,7 +3748,7 @@ v4i32, v4i32, or, 1>; def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1, - (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), + (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src), IIC_VMOVImm, "vorr", "i16", "$Vd, $SIMM", "$src = $Vd", [(set DPR:$Vd, @@ -3761,7 +3766,7 @@ } def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1, - (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), + (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src), IIC_VMOVImm, "vorr", "i16", "$Vd, $SIMM", "$src = $Vd", [(set QPR:$Vd, @@ -3792,7 +3797,7 @@ (vnotq QPR:$Vm))))]>; def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1, - (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), + (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src), IIC_VMOVImm, "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", [(set DPR:$Vd, @@ -3810,7 +3815,7 @@ } def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1, - (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), + (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src), IIC_VMOVImm, "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", [(set QPR:$Vd, @@ -3844,14 +3849,14 @@ let isReMaterializable = 1 in { def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmSplatI16:$SIMM), IIC_VMOVImm, "vmvn", "i16", "$Vd, $SIMM", "", [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> { let Inst{9} = SIMM{9}; } def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmSplatI16:$SIMM), IIC_VMOVImm, "vmvn", "i16", "$Vd, $SIMM", "", [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> { let Inst{9} = SIMM{9}; @@ -4329,14 +4334,14 @@ [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>; def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmSplatI16:$SIMM), IIC_VMOVImm, "vmov", "i16", "$Vd, $SIMM", "", [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> { let Inst{9} = SIMM{9}; } def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmSplatI16:$SIMM), IIC_VMOVImm, "vmov", "i16", "$Vd, $SIMM", "", [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> { let Inst{9} = SIMM{9}; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=142303&r1=142302&r2=142303&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Oct 17 18:09:09 2011 @@ -924,6 +924,17 @@ return Value >= 0 && Value < 256; } + bool isNEONi16splat() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + // Must be a constant. + if (!CE) return false; + int64_t Value = CE->getValue(); + // i16 value in the range [0,255] or [0x0100, 0xff00] + return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); + } + void addExpr(MCInst &Inst, const MCExpr *Expr) const { // Add as immediates when possible. Null MCExpr = 0. if (Expr == 0) @@ -1454,6 +1465,18 @@ Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); } + void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + // The immediate encodes the type of constant as well as the value. + const MCConstantExpr *CE = dyn_cast(getImm()); + unsigned Value = CE->getValue(); + if (Value >= 256) + Value = (Value >> 8) | 0xa00; + else + Value |= 0x800; + Inst.addOperand(MCOperand::CreateImm(Value)); + } + virtual void print(raw_ostream &OS) const; static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { Modified: llvm/trunk/test/MC/ARM/neont2-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mov-encoding.s?rev=142303&r1=142302&r2=142303&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mov-encoding.s Mon Oct 17 18:09:09 2011 @@ -3,8 +3,8 @@ .code 16 vmov.i8 d16, #0x8 -@ vmov.i16 d16, #0x10 -@ vmov.i16 d16, #0x1000 + vmov.i16 d16, #0x10 + vmov.i16 d16, #0x1000 @ vmov.i32 d16, #0x20 @ vmov.i32 d16, #0x2000 @ vmov.i32 d16, #0x200000 @@ -14,8 +14,8 @@ @ vmov.i64 d16, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 d16, #0x8 @ encoding: [0xc0,0xef,0x18,0x0e] -@ FIXME: vmov.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x10,0x08] -@ FIXME: vmov.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x10,0x0a] +@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x10,0x08] +@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x10,0x0a] @ FIXME: vmov.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x10,0x00] @ FIXME: vmov.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x10,0x02] @ FIXME: vmov.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x10,0x04] @@ -26,8 +26,8 @@ vmov.i8 q8, #0x8 -@ vmov.i16 q8, #0x10 -@ vmov.i16 q8, #0x1000 + vmov.i16 q8, #0x10 + vmov.i16 q8, #0x1000 @ vmov.i32 q8, #0x20 @ vmov.i32 q8, #0x2000 @ vmov.i32 q8, #0x200000 @@ -37,8 +37,8 @@ @ vmov.i64 q8, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 q8, #0x8 @ encoding: [0xc0,0xef,0x58,0x0e] -@ FIXME: vmov.i16 q8, #0x10 @ encoding: [0xc1,0xef,0x50,0x08] -@ FIXME: vmov.i16 q8, #0x1000 @ encoding: [0xc1,0xef,0x50,0x0a] +@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0xc1,0xef,0x50,0x08] +@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0xc1,0xef,0x50,0x0a] @ FIXME: vmov.i32 q8, #0x20 @ encoding: [0xc2,0xef,0x50,0x00] @ FIXME: vmov.i32 q8, #0x2000 @ encoding: [0xc2,0xef,0x50,0x02] @ FIXME: vmov.i32 q8, #0x200000 @ encoding: [0xc2,0xef,0x50,0x04] @@ -48,8 +48,8 @@ @ FIXME: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x73,0x0e] -@ vmvn.i16 d16, #0x10 -@ vmvn.i16 d16, #0x1000 + vmvn.i16 d16, #0x10 + vmvn.i16 d16, #0x1000 @ vmvn.i32 d16, #0x20 @ vmvn.i32 d16, #0x2000 @ vmvn.i32 d16, #0x200000 @@ -57,8 +57,8 @@ @ vmvn.i32 d16, #0x20FF @ vmvn.i32 d16, #0x20FFFF -@ FIXME: vmvn.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x30,0x08] -@ FIXME: vmvn.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x30,0x0a] +@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x30,0x08] +@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x30,0x0a] @ FIXME: vmvn.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x30,0x00] @ FIXME: vmvn.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x30,0x02] @ FIXME: vmvn.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x30,0x04] Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=142303&r1=142302&r2=142303&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Oct 17 18:09:09 2011 @@ -598,6 +598,7 @@ IMM("imm1_32"); IMM("nModImm"); IMM("nImmSplatI8"); + IMM("nImmSplatI16"); IMM("imm0_7"); IMM("imm0_15"); IMM("imm0_255"); From stoklund at 2pi.dk Mon Oct 17 18:16:56 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 17 Oct 2011 16:16:56 -0700 Subject: [llvm-commits] [llvm] r142286 - /llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll In-Reply-To: References: <20111017215443.9FFF6312800A@llvm.org> Message-ID: <618CE4EC-5CD1-435D-8AF8-534FEDDA6DF7@2pi.dk> On Oct 17, 2011, at 3:14 PM, Lang Hames wrote: > Not quite. Apparently the shell lines in the lit suite are tcl, which doesn't honor the embedded quote. This led to the trailing quote being passed through in the target data layout string. The parser used to swallow this silently, treating the resulting 'n32"' as zero and discard it. The new verifier barfed on it though (as it should). Does it also catch test/Other/constant-fold-gep.ll? /jakob From rafael.espindola at gmail.com Mon Oct 17 18:17:03 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Mon, 17 Oct 2011 19:17:03 -0400 Subject: [llvm-commits] [llvm] r142288 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/AsmParser/LLParser.cpp lib/Target/TargetData.cpp In-Reply-To: <4E9CAB90.3010102@gmail.com> References: <20111017220535.2A343312800A@llvm.org> <4E9CAB90.3010102@gmail.com> Message-ID: <4E9CB76F.4060709@gmail.com> On 10/17/2011 06:26 PM, Rafael ?vila de Esp?ndola wrote: > looks like this broke the build: > > > Linking CXX executable ../../bin/llvm-as > ../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function > llvm::LLParser::ParseTargetDefinition(): error: undefined reference to > 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)' > clang-3: error: linker command failed with exit code 1 (use -v to see > invocation) It looks like all that was missing was the attached patch. Chandler, is it OK with the original patch? > Cheers, > Rafael Cheers, Rafael -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: t.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/d2e02a74/attachment.pl From lhames at gmail.com Mon Oct 17 18:24:48 2011 From: lhames at gmail.com (Lang Hames) Date: Mon, 17 Oct 2011 23:24:48 -0000 Subject: [llvm-commits] [llvm] r142306 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/AsmParser/CMakeLists.txt lib/AsmParser/LLParser.cpp lib/Target/TargetData.cpp Message-ID: <20111017232448.3EF853524001@llvm.org> Author: lhames Date: Mon Oct 17 18:24:48 2011 New Revision: 142306 URL: http://llvm.org/viewvc/llvm-project?rev=142306&view=rev Log: Re-applying the target data layout verification patch from r142288, plus appropriate CMake dependencies. Thanks to Raphael Espindola for tracking down the CMake issues. Modified: llvm/trunk/include/llvm/Target/TargetData.h llvm/trunk/lib/AsmParser/CMakeLists.txt llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/Target/TargetData.cpp Modified: llvm/trunk/include/llvm/Target/TargetData.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetData.h?rev=142306&r1=142305&r2=142306&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetData.h (original) +++ llvm/trunk/include/llvm/Target/TargetData.h Mon Oct 17 18:24:48 2011 @@ -44,7 +44,7 @@ AGGREGATE_ALIGN = 'a', ///< Aggregate alignment STACK_ALIGN = 's' ///< Stack objects alignment }; - + /// Target alignment element. /// /// Stores the alignment data associated with a given alignment type (pointer, @@ -80,7 +80,7 @@ unsigned StackNaturalAlign; ///< Stack natural alignment SmallVector LegalIntWidths; ///< Legal Integers. - + /// Alignments- Where the primitive type alignment data is stored. /// /// @sa init(). @@ -88,7 +88,7 @@ /// pointers vs. 64-bit pointers by extending TargetAlignment, but for now, /// we don't. SmallVector Alignments; - + /// InvalidAlignmentElem - This member is a signal that a requested alignment /// type and bit width were not found in the SmallVector. static const TargetAlignElem InvalidAlignmentElem; @@ -112,19 +112,30 @@ return &align != &InvalidAlignmentElem; } + /// Initialise a TargetData object with default values, ensure that the + /// target data pass is registered. + void init(); + public: /// Default ctor. /// /// @note This has to exist, because this is a pass, but it should never be /// used. TargetData(); - + /// Constructs a TargetData from a specification string. See init(). explicit TargetData(StringRef TargetDescription) : ImmutablePass(ID) { - init(TargetDescription); + std::string errMsg = parseSpecifier(TargetDescription, this); + assert(errMsg == "" && "Invalid target data layout string."); + (void)errMsg; } + /// Parses a target data specification string. Returns an error message + /// if the string is malformed, or the empty string on success. Optionally + /// initialises a TargetData object if passed a non-null pointer. + static std::string parseSpecifier(StringRef TargetDescription, TargetData* td = 0); + /// Initialize target data from properties stored in the module. explicit TargetData(const Module *M); @@ -141,9 +152,6 @@ ~TargetData(); // Not virtual, do not subclass this class - //! Parse a target data layout string and initialize TargetData alignments. - void init(StringRef TargetDescription); - /// Target endianness... bool isLittleEndian() const { return LittleEndian; } bool isBigEndian() const { return !LittleEndian; } @@ -152,7 +160,7 @@ /// TargetData. This representation is in the same format accepted by the /// string constructor above. std::string getStringRepresentation() const; - + /// isLegalInteger - This function returns true if the specified type is /// known to be a native integer type supported by the CPU. For example, /// i64 is not native on most 32-bit CPUs and i37 is not native on any known @@ -166,7 +174,7 @@ return true; return false; } - + bool isIllegalInteger(unsigned Width) const { return !isLegalInteger(Width); } @@ -251,11 +259,11 @@ /// getABITypeAlignment - Return the minimum ABI-required alignment for the /// specified type. unsigned getABITypeAlignment(Type *Ty) const; - + /// getABIIntegerTypeAlignment - Return the minimum ABI-required alignment for /// an integer type of the specified bitwidth. unsigned getABIIntegerTypeAlignment(unsigned BitWidth) const; - + /// getCallFrameTypeAlignment - Return the minimum ABI-required alignment /// for the specified type when it is part of a call frame. @@ -305,7 +313,7 @@ assert((Alignment & (Alignment-1)) == 0 && "Alignment must be power of 2!"); return (Val + (Alignment-1)) & ~UIntTy(Alignment-1); } - + static char ID; // Pass identification, replacement for typeid }; Modified: llvm/trunk/lib/AsmParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/CMakeLists.txt?rev=142306&r1=142305&r2=142306&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/CMakeLists.txt (original) +++ llvm/trunk/lib/AsmParser/CMakeLists.txt Mon Oct 17 18:24:48 2011 @@ -8,4 +8,5 @@ add_llvm_library_dependencies(LLVMAsmParser LLVMCore LLVMSupport + LLVMTarget ) Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=142306&r1=142305&r2=142306&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Oct 17 18:24:48 2011 @@ -24,6 +24,7 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetData.h" using namespace llvm; static std::string getTypeString(Type *T) { @@ -260,9 +261,14 @@ return false; case lltok::kw_datalayout: Lex.Lex(); + LocTy SpecifierLoc = Lex.getLoc(); if (ParseToken(lltok::equal, "expected '=' after target datalayout") || ParseStringConstant(Str)) return true; + std::string errMsg = TargetData::parseSpecifier(Str); + if (errMsg != "") { + return Error(SpecifierLoc, errMsg); + } M->setDataLayout(Str); return false; } Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=142306&r1=142305&r2=142306&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Mon Oct 17 18:24:48 2011 @@ -125,15 +125,15 @@ //===----------------------------------------------------------------------===// /// getInt - Get an integer ignoring errors. -static unsigned getInt(StringRef R) { - unsigned Result = 0; +static int getInt(StringRef R) { + int Result = 0; R.getAsInteger(10, Result); return Result; } -void TargetData::init(StringRef Desc) { +void TargetData::init() { initializeTargetDataPass(*PassRegistry::getPassRegistry()); - + LayoutMap = 0; LittleEndian = false; PointerMemSize = 8; @@ -152,6 +152,12 @@ setAlignment(VECTOR_ALIGN, 8, 8, 64); // v2i32, v1i64, ... setAlignment(VECTOR_ALIGN, 16, 16, 128); // v16i8, v8i16, v4i32, ... setAlignment(AGGREGATE_ALIGN, 0, 8, 0); // struct +} + +std::string TargetData::parseSpecifier(StringRef Desc, TargetData *td) { + + if (td) + td->init(); while (!Desc.empty()) { std::pair Split = Desc.split('-'); @@ -169,28 +175,54 @@ switch (Specifier[0]) { case 'E': - LittleEndian = false; + if (td) + td->LittleEndian = false; break; case 'e': - LittleEndian = true; + if (td) + td->LittleEndian = true; break; - case 'p': + case 'p': { + // Pointer size. Split = Token.split(':'); - PointerMemSize = getInt(Split.first) / 8; + int PointerMemSizeBits = getInt(Split.first); + if (PointerMemSizeBits < 0 || PointerMemSizeBits % 8 != 0) + return "invalid pointer size, must be a positive 8-bit multiple"; + if (td) + td->PointerMemSize = PointerMemSizeBits / 8; + + // Pointer ABI alignment. Split = Split.second.split(':'); - PointerABIAlign = getInt(Split.first) / 8; + int PointerABIAlignBits = getInt(Split.first); + if (PointerABIAlignBits < 0 || PointerABIAlignBits % 8 != 0) { + return "invalid pointer ABI alignment, " + "must be a positive 8-bit multiple"; + } + if (td) + td->PointerABIAlign = PointerABIAlignBits / 8; + + // Pointer preferred alignment. Split = Split.second.split(':'); - PointerPrefAlign = getInt(Split.first) / 8; - if (PointerPrefAlign == 0) - PointerPrefAlign = PointerABIAlign; + int PointerPrefAlignBits = getInt(Split.first); + if (PointerPrefAlignBits < 0 || PointerPrefAlignBits % 8 != 0) { + return "invalid pointer preferred alignment, " + "must be a positive 8-bit multiple"; + } + if (td) { + td->PointerPrefAlign = PointerPrefAlignBits / 8; + if (td->PointerPrefAlign == 0) + td->PointerPrefAlign = td->PointerABIAlign; + } break; + } case 'i': case 'v': case 'f': case 'a': case 's': { AlignTypeEnum AlignType; - switch (Specifier[0]) { + char field = Specifier[0]; + switch (field) { default: case 'i': AlignType = INTEGER_ALIGN; break; case 'v': AlignType = VECTOR_ALIGN; break; @@ -198,37 +230,66 @@ case 'a': AlignType = AGGREGATE_ALIGN; break; case 's': AlignType = STACK_ALIGN; break; } - unsigned Size = getInt(Specifier.substr(1)); + int Size = getInt(Specifier.substr(1)); + if (Size < 0) { + return std::string("invalid ") + field + "-size field, " + "must be positive"; + } + Split = Token.split(':'); - unsigned ABIAlign = getInt(Split.first) / 8; + int ABIAlignBits = getInt(Split.first); + if (ABIAlignBits < 0 || ABIAlignBits % 8 != 0) { + return std::string("invalid ") + field +"-abi-alignment field, " + "must be a positive 8-bit multiple"; + } + unsigned ABIAlign = ABIAlignBits / 8; Split = Split.second.split(':'); - unsigned PrefAlign = getInt(Split.first) / 8; + + int PrefAlignBits = getInt(Split.first); + if (PrefAlignBits < 0 || PrefAlignBits % 8 != 0) { + return std::string("invalid ") + field +"-preferred-alignment field, " + "must be a positive 8-bit multiple"; + } + unsigned PrefAlign = PrefAlignBits / 8; if (PrefAlign == 0) PrefAlign = ABIAlign; - setAlignment(AlignType, ABIAlign, PrefAlign, Size); + + if (td) + td->setAlignment(AlignType, ABIAlign, PrefAlign, Size); break; } case 'n': // Native integer types. Specifier = Specifier.substr(1); do { - if (unsigned Width = getInt(Specifier)) - LegalIntWidths.push_back(Width); + int Width = getInt(Specifier); + if (Width <= 0) { + return std::string("invalid native integer size \'") + Specifier.str() + + "\', must be a positive integer."; + } + if (td && Width != 0) + td->LegalIntWidths.push_back(Width); Split = Token.split(':'); Specifier = Split.first; Token = Split.second; } while (!Specifier.empty() || !Token.empty()); break; - case 'S': // Stack natural alignment. - StackNaturalAlign = getInt(Specifier.substr(1)); - StackNaturalAlign /= 8; - // FIXME: Should we really be truncating these alingments and - // sizes silently? + case 'S': { // Stack natural alignment. + int StackNaturalAlignBits = getInt(Specifier.substr(1)); + if (StackNaturalAlignBits < 0 || StackNaturalAlignBits % 8 != 0) { + return "invalid natural stack alignment (S-field), " + "must be a positive 8-bit multiple"; + } + if (td) + td->StackNaturalAlign = StackNaturalAlignBits / 8; break; + } default: break; } } + + return ""; } /// Default ctor. @@ -242,7 +303,9 @@ TargetData::TargetData(const Module *M) : ImmutablePass(ID) { - init(M->getDataLayout()); + std::string errMsg = parseSpecifier(M->getDataLayout(), this); + assert(errMsg == "" && "Module M has malformed target data layout string."); + (void)errMsg; } void From nicholas at mxc.ca Mon Oct 17 18:27:36 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 17 Oct 2011 23:27:36 -0000 Subject: [llvm-commits] [llvm] r142307 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20111017232736.3AE362A6C12C@llvm.org> Author: nicholas Date: Mon Oct 17 18:27:36 2011 New Revision: 142307 URL: http://llvm.org/viewvc/llvm-project?rev=142307&view=rev Log: Minor style cleanup, no functionality change. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=142307&r1=142306&r2=142307&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Oct 17 18:27:36 2011 @@ -481,7 +481,7 @@ NewCU->addUInt(Die, dwarf::DW_AT_entry_pc, dwarf::DW_FORM_addr, 0); // DW_AT_stmt_list is a offset of line number information for this // compile unit in debug_line section. - if(Asm->MAI->doesDwarfRequireRelocationForSectionOffset()) + if (Asm->MAI->doesDwarfRequireRelocationForSectionOffset()) NewCU->addLabel(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, Asm->GetTempSymbol("section_line")); else @@ -497,8 +497,7 @@ NewCU->addString(Die, dwarf::DW_AT_APPLE_flags, dwarf::DW_FORM_string, Flags); - unsigned RVer = DIUnit.getRunTimeVersion(); - if (RVer) + if (unsigned RVer = DIUnit.getRunTimeVersion()) NewCU->addUInt(Die, dwarf::DW_AT_APPLE_major_runtime_vers, dwarf::DW_FORM_data1, RVer); From chandlerc at google.com Mon Oct 17 18:30:10 2011 From: chandlerc at google.com (Chandler Carruth) Date: Mon, 17 Oct 2011 16:30:10 -0700 Subject: [llvm-commits] [llvm] r142288 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/AsmParser/LLParser.cpp lib/Target/TargetData.cpp In-Reply-To: <4E9CB76F.4060709@gmail.com> References: <20111017220535.2A343312800A@llvm.org> <4E9CAB90.3010102@gmail.com> <4E9CB76F.4060709@gmail.com> Message-ID: On Mon, Oct 17, 2011 at 4:17 PM, Rafael ?vila de Esp?ndola < rafael.espindola at gmail.com> wrote: > On 10/17/2011 06:26 PM, Rafael ?vila de Esp?ndola wrote: > >> looks like this broke the build: >> >> >> Linking CXX executable ../../bin/llvm-as >> ../../lib/libLLVMAsmParser.a(**LLParser.cpp.o):/home/** >> espindola/llvm/llvm/lib/**AsmParser/LLParser.cpp:**function >> llvm::LLParser::**ParseTargetDefinition(): error: undefined reference to >> 'llvm::TargetData::**parseSpecifier(llvm::**StringRef, >> llvm::TargetData*)' >> clang-3: error: linker command failed with exit code 1 (use -v to see >> invocation) >> > > It looks like all that was missing was the attached patch. > > Chandler, is it OK with the original patch? As discussed in IRC, yes this is sufficient for the link command to succeed, but it feels completely wrong for the LL parsing to depend on the target library. I think this is a more fundamental layering issue. Currently AsmParser only depends on Support and Core, and that seems reasonable. I don't think something not in the VMCore should be required in order to parse the IR. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/019d9811/attachment.html From bigcheesegs at gmail.com Mon Oct 17 18:37:43 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 17 Oct 2011 23:37:43 -0000 Subject: [llvm-commits] [llvm] r142309 - /llvm/trunk/include/llvm/Object/ObjectFile.h Message-ID: <20111017233743.E40C23524001@llvm.org> Author: mspencer Date: Mon Oct 17 18:37:43 2011 New Revision: 142309 URL: http://llvm.org/viewvc/llvm-project?rev=142309&view=rev Log: 80-col. Modified: llvm/trunk/include/llvm/Object/ObjectFile.h Modified: llvm/trunk/include/llvm/Object/ObjectFile.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=142309&r1=142308&r2=142309&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/ObjectFile.h (original) +++ llvm/trunk/include/llvm/Object/ObjectFile.h Mon Oct 17 18:37:43 2011 @@ -229,10 +229,12 @@ virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) const =0; virtual error_code getSymbolOffset(DataRefImpl Symb, uint64_t &Res) const =0; virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const = 0; + virtual error_code getSymbolType(DataRefImpl Symb, + SymbolRef::Type &Res) const = 0; virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const = 0; virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const = 0; virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const = 0; - virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const = 0; + // Same as above for SectionRef. friend class SectionRef; From grosbach at apple.com Mon Oct 17 18:50:19 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 17 Oct 2011 23:50:19 -0000 Subject: [llvm-commits] [llvm] r142313 - /llvm/trunk/test/MC/ARM/neon-mov-encoding.s Message-ID: <20111017235019.2F7CD2A6C12C@llvm.org> Author: grosbach Date: Mon Oct 17 18:50:19 2011 New Revision: 142313 URL: http://llvm.org/viewvc/llvm-project?rev=142313&view=rev Log: Enable a few more NEON immediate tests. Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.s Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.s?rev=142313&r1=142312&r2=142313&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mov-encoding.s Mon Oct 17 18:50:19 2011 @@ -1,8 +1,8 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s vmov.i8 d16, #0x8 -@ vmov.i16 d16, #0x10 -@ vmov.i16 d16, #0x1000 + vmov.i16 d16, #0x10 + vmov.i16 d16, #0x1000 @ vmov.i32 d16, #0x20 @ vmov.i32 d16, #0x2000 @ vmov.i32 d16, #0x200000 @@ -12,8 +12,8 @@ @ vmov.i64 d16, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] -@ FIXME: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] -@ FIXME: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2] +@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] +@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2] @ FIXME: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2] @ FIXME: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] @ FIXME: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] @@ -25,8 +25,8 @@ vmov.i8 q8, #0x8 -@ vmov.i16 q8, #0x10 -@ vmov.i16 q8, #0x1000 + vmov.i16 q8, #0x10 + vmov.i16 q8, #0x1000 @ vmov.i32 q8, #0x20 @ vmov.i32 q8, #0x2000 @ vmov.i32 q8, #0x200000 @@ -36,8 +36,8 @@ @ vmov.i64 q8, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2] -@ FIXME: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] -@ FIXME: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2] +@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] +@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2] @ FIXME: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2] @ FIXME: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] @ FIXME: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] @@ -46,8 +46,8 @@ @ FIXME: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] @ FIXME: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] -@ vmvn.i16 d16, #0x10 -@ vmvn.i16 d16, #0x1000 + vmvn.i16 d16, #0x10 + vmvn.i16 d16, #0x1000 @ vmvn.i32 d16, #0x20 @ vmvn.i32 d16, #0x2000 @ vmvn.i32 d16, #0x200000 @@ -55,8 +55,8 @@ @ vmvn.i32 d16, #0x20FF @ vmvn.i32 d16, #0x20FFFF -@ FIXME: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2] -@ FIXME: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2] +@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2] +@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2] @ FIXME: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2] @ FIXME: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] @ FIXME: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] From bigcheesegs at gmail.com Mon Oct 17 18:53:37 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 17 Oct 2011 23:53:37 -0000 Subject: [llvm-commits] [llvm] r142314 - in /llvm/trunk: include/llvm/Object/COFF.h include/llvm/Object/MachO.h lib/Object/ELFObjectFile.cpp Message-ID: <20111017235337.36FCD3524001@llvm.org> Author: mspencer Date: Mon Oct 17 18:53:37 2011 New Revision: 142314 URL: http://llvm.org/viewvc/llvm-project?rev=142314&view=rev Log: Object: Implement casting for concrete classes. Modified: llvm/trunk/include/llvm/Object/COFF.h llvm/trunk/include/llvm/Object/MachO.h llvm/trunk/lib/Object/ELFObjectFile.cpp Modified: llvm/trunk/include/llvm/Object/COFF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=142314&r1=142313&r2=142314&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/COFF.h (original) +++ llvm/trunk/include/llvm/Object/COFF.h Mon Oct 17 18:53:37 2011 @@ -141,6 +141,12 @@ virtual uint8_t getBytesInAddress() const; virtual StringRef getFileFormatName() const; virtual unsigned getArch() const; + + + static inline bool classof(const Binary *v) { + return v->getType() == isCOFF; + } + static inline bool classof(const COFFObjectFile *v) { return true; } }; } Modified: llvm/trunk/include/llvm/Object/MachO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachO.h?rev=142314&r1=142313&r2=142314&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/MachO.h (original) +++ llvm/trunk/include/llvm/Object/MachO.h Mon Oct 17 18:53:37 2011 @@ -40,6 +40,11 @@ MachOObject *getObject() { return MachOObj; } + static inline bool classof(const Binary *v) { + return v->getType() == isMachO; + } + static inline bool classof(const MachOObjectFile *v) { return true; } + protected: virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const; virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const; Modified: llvm/trunk/lib/Object/ELFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ELFObjectFile.cpp?rev=142314&r1=142313&r2=142314&view=diff ============================================================================== --- llvm/trunk/lib/Object/ELFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/ELFObjectFile.cpp Mon Oct 17 18:53:37 2011 @@ -377,6 +377,11 @@ uint64_t getStringTableIndex() const; ELF::Elf64_Word getSymbolTableIndex(const Elf_Sym *symb) const; const Elf_Shdr *getSection(const Elf_Sym *symb) const; + + static inline bool classof(const Binary *v) { + return v->getType() == isELF; + } + static inline bool classof(const ELFObjectFile *v) { return true; } }; } // end namespace From bigcheesegs at gmail.com Mon Oct 17 18:53:56 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 17 Oct 2011 23:53:56 -0000 Subject: [llvm-commits] [llvm] r142315 - in /llvm/trunk: include/llvm/Object/COFF.h lib/Object/COFFObjectFile.cpp Message-ID: <20111017235356.AE20F2A6C12C@llvm.org> Author: mspencer Date: Mon Oct 17 18:53:56 2011 New Revision: 142315 URL: http://llvm.org/viewvc/llvm-project?rev=142315&view=rev Log: Object/COFF: Expose more data in the public API. Modified: llvm/trunk/include/llvm/Object/COFF.h llvm/trunk/lib/Object/COFFObjectFile.cpp Modified: llvm/trunk/include/llvm/Object/COFF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=142315&r1=142314&r2=142315&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/COFF.h (original) +++ llvm/trunk/include/llvm/Object/COFF.h Mon Oct 17 18:53:56 2011 @@ -73,6 +73,16 @@ support::ulittle16_t Type; }; +struct coff_aux_section_definition { + support::ulittle32_t Length; + support::ulittle16_t NumberOfRelocations; + support::ulittle16_t NumberOfLinenumbers; + support::ulittle32_t CheckSum; + support::ulittle16_t Number; + support::ulittle8_t Selection; + char Unused[3]; +}; + class COFFObjectFile : public ObjectFile { private: const coff_file_header *Header; @@ -81,11 +91,7 @@ const char *StringTable; uint32_t StringTableSize; - error_code getSection(int32_t index, - const coff_section *&Res) const; error_code getString(uint32_t offset, StringRef &Res) const; - error_code getSymbol(uint32_t index, - const coff_symbol *&Res) const; const coff_symbol *toSymb(DataRefImpl Symb) const; const coff_section *toSec(DataRefImpl Sec) const; @@ -142,6 +148,17 @@ virtual StringRef getFileFormatName() const; virtual unsigned getArch() const; + error_code getHeader(const coff_file_header *&Res) const; + error_code getSection(int32_t index, const coff_section *&Res) const; + error_code getSymbol(uint32_t index, const coff_symbol *&Res) const; + template + error_code getAuxSymbol(uint32_t index, const T *&Res) const { + const coff_symbol *s; + error_code ec = getSymbol(index, s); + Res = reinterpret_cast(s); + return ec; + } + error_code getSymbolName(const coff_symbol *symbol, StringRef &Res) const; static inline bool classof(const Binary *v) { return v->getType() == isCOFF; Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=142315&r1=142314&r2=142315&view=diff ============================================================================== --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Mon Oct 17 18:53:56 2011 @@ -98,21 +98,7 @@ error_code COFFObjectFile::getSymbolName(DataRefImpl Symb, StringRef &Result) const { const coff_symbol *symb = toSymb(Symb); - // Check for string table entry. First 4 bytes are 0. - if (symb->Name.Offset.Zeroes == 0) { - uint32_t Offset = symb->Name.Offset.Offset; - if (error_code ec = getString(Offset, Result)) - return ec; - return object_error::success; - } - - if (symb->Name.ShortName[7] == 0) - // Null terminated, let ::strlen figure out the length. - Result = StringRef(symb->Name.ShortName); - else - // Not null terminated, use all 8 bytes. - Result = StringRef(symb->Name.ShortName, 8); - return object_error::success; + return getSymbolName(symb, Result); } error_code COFFObjectFile::getSymbolOffset(DataRefImpl Symb, @@ -525,6 +511,11 @@ } } +error_code COFFObjectFile::getHeader(const coff_file_header *&Res) const { + Res = Header; + return object_error::success; +} + error_code COFFObjectFile::getSection(int32_t index, const coff_section *&Result) const { // Check for special index values. @@ -553,13 +544,32 @@ error_code COFFObjectFile::getSymbol(uint32_t index, const coff_symbol *&Result) const { - if (index > 0 && index < Header->NumberOfSymbols) + if (index >= 0 && index < Header->NumberOfSymbols) Result = SymbolTable + index; else return object_error::parse_failed; return object_error::success; } +error_code COFFObjectFile::getSymbolName(const coff_symbol *symbol, + StringRef &Res) const { + // Check for string table entry. First 4 bytes are 0. + if (symbol->Name.Offset.Zeroes == 0) { + uint32_t Offset = symbol->Name.Offset.Offset; + if (error_code ec = getString(Offset, Res)) + return ec; + return object_error::success; + } + + if (symbol->Name.ShortName[7] == 0) + // Null terminated, let ::strlen figure out the length. + Res = StringRef(symbol->Name.ShortName); + else + // Not null terminated, use all 8 bytes. + Res = StringRef(symbol->Name.ShortName, 8); + return object_error::success; +} + const coff_relocation *COFFObjectFile::toRel(DataRefImpl Rel) const { return reinterpret_cast(Rel.p); } From bigcheesegs at gmail.com Mon Oct 17 18:54:23 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 17 Oct 2011 23:54:23 -0000 Subject: [llvm-commits] [llvm] r142316 - in /llvm/trunk: include/llvm/Object/COFF.h include/llvm/Object/MachO.h include/llvm/Object/ObjectFile.h include/llvm/Support/MachO.h lib/Object/COFFObjectFile.cpp lib/Object/ELFObjectFile.cpp lib/Object/MachOObjectFile.cpp Message-ID: <20111017235423.31DF83524001@llvm.org> Author: mspencer Date: Mon Oct 17 18:54:22 2011 New Revision: 142316 URL: http://llvm.org/viewvc/llvm-project?rev=142316&view=rev Log: Object: Add isSymbolWeak. Modified: llvm/trunk/include/llvm/Object/COFF.h llvm/trunk/include/llvm/Object/MachO.h llvm/trunk/include/llvm/Object/ObjectFile.h llvm/trunk/include/llvm/Support/MachO.h llvm/trunk/lib/Object/COFFObjectFile.cpp llvm/trunk/lib/Object/ELFObjectFile.cpp llvm/trunk/lib/Object/MachOObjectFile.cpp Modified: llvm/trunk/include/llvm/Object/COFF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=142316&r1=142315&r2=142316&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/COFF.h (original) +++ llvm/trunk/include/llvm/Object/COFF.h Mon Oct 17 18:54:22 2011 @@ -106,6 +106,7 @@ virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const; virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const; virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const; + virtual error_code isSymbolWeak(DataRefImpl Symb, bool &Res) const; virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const; virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const; Modified: llvm/trunk/include/llvm/Object/MachO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachO.h?rev=142316&r1=142315&r2=142316&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/MachO.h (original) +++ llvm/trunk/include/llvm/Object/MachO.h Mon Oct 17 18:54:22 2011 @@ -54,6 +54,7 @@ virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const; virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const; virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const; + virtual error_code isSymbolWeak(DataRefImpl Symb, bool &Res) const; virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const; virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const; Modified: llvm/trunk/include/llvm/Object/ObjectFile.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=142316&r1=142315&r2=142316&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/ObjectFile.h (original) +++ llvm/trunk/include/llvm/Object/ObjectFile.h Mon Oct 17 18:54:22 2011 @@ -121,6 +121,9 @@ /// such as library functions error_code isGlobal(bool &Result) const; + /// Returns true for weak symbols. + error_code isWeak(bool &Result) const; + DataRefImpl getRawDataRefImpl() const; }; typedef content_iterator symbol_iterator; @@ -234,7 +237,7 @@ virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const = 0; virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const = 0; virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const = 0; - + virtual error_code isSymbolWeak(DataRefImpl Symb, bool &Res) const = 0; // Same as above for SectionRef. friend class SectionRef; @@ -345,6 +348,10 @@ return OwningObject->isSymbolGlobal(SymbolPimpl, Result); } +inline error_code SymbolRef::isWeak(bool &Result) const { + return OwningObject->isSymbolWeak(SymbolPimpl, Result); +} + inline error_code SymbolRef::getType(SymbolRef::Type &Result) const { return OwningObject->getSymbolType(SymbolPimpl, Result); } Modified: llvm/trunk/include/llvm/Support/MachO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/MachO.h?rev=142316&r1=142315&r2=142316&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/MachO.h (original) +++ llvm/trunk/include/llvm/Support/MachO.h Mon Oct 17 18:54:22 2011 @@ -240,6 +240,9 @@ NListSectionNoSection = 0u, // NO_SECT NListSectionMaxSection = 0xffu, // MAX_SECT + NListDescWeakRef = 0x40u, + NListDescWeakDef = 0x80u, + // Constant values for the "n_type" field in llvm::MachO::nlist and // llvm::MachO::nlist_64 when "(n_type & NlistMaskStab) != 0" StabGlobalSymbol = 0x20u, // N_GSYM Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=142316&r1=142315&r2=142316&view=diff ============================================================================== --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Mon Oct 17 18:54:22 2011 @@ -168,6 +168,13 @@ return object_error::success; } +error_code COFFObjectFile::isSymbolWeak(DataRefImpl Symb, + bool &Result) const { + const coff_symbol *symb = toSymb(Symb); + Result = (symb->StorageClass == COFF::IMAGE_SYM_CLASS_WEAK_EXTERNAL); + return object_error::success; +} + error_code COFFObjectFile::getSymbolSize(DataRefImpl Symb, uint64_t &Result) const { // FIXME: Return the correct size. This requires looking at all the symbols Modified: llvm/trunk/lib/Object/ELFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ELFObjectFile.cpp?rev=142316&r1=142315&r2=142316&view=diff ============================================================================== --- llvm/trunk/lib/Object/ELFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/ELFObjectFile.cpp Mon Oct 17 18:54:22 2011 @@ -331,6 +331,7 @@ virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const; virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const; virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const; + virtual error_code isSymbolWeak(DataRefImpl Symb, bool &Res) const; virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const; virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const; @@ -643,6 +644,17 @@ template error_code ELFObjectFile + ::isSymbolWeak(DataRefImpl Symb, + bool &Result) const { + validateSymbol(Symb); + const Elf_Sym *symb = getSymbol(Symb); + + Result = symb->getBinding() == ELF::STB_WEAK; + return object_error::success; +} + +template +error_code ELFObjectFile ::isSymbolInternal(DataRefImpl Symb, bool &Result) const { validateSymbol(Symb); Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=142316&r1=142315&r2=142316&view=diff ============================================================================== --- llvm/trunk/lib/Object/MachOObjectFile.cpp (original) +++ llvm/trunk/lib/Object/MachOObjectFile.cpp Mon Oct 17 18:54:22 2011 @@ -228,6 +228,20 @@ return object_error::success; } +error_code MachOObjectFile::isSymbolWeak(DataRefImpl Symb, bool &Res) const { + + if (MachOObj->is64Bit()) { + InMemoryStruct Entry; + getSymbol64TableEntry(Symb, Entry); + Res = Entry->Flags & (MachO::NListDescWeakRef | MachO::NListDescWeakDef); + } else { + InMemoryStruct Entry; + getSymbolTableEntry(Symb, Entry); + Res = Entry->Flags & (MachO::NListDescWeakRef | MachO::NListDescWeakDef); + } + return object_error::success; +} + error_code MachOObjectFile::getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const { uint8_t n_type; From bigcheesegs at gmail.com Mon Oct 17 18:54:47 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 17 Oct 2011 23:54:47 -0000 Subject: [llvm-commits] [llvm] r142317 - in /llvm/trunk: include/llvm/Object/COFF.h include/llvm/Object/MachO.h include/llvm/Object/ObjectFile.h lib/Object/COFFObjectFile.cpp lib/Object/ELFObjectFile.cpp lib/Object/MachOObjectFile.cpp Message-ID: <20111017235447.27A252A6C12C@llvm.org> Author: mspencer Date: Mon Oct 17 18:54:46 2011 New Revision: 142317 URL: http://llvm.org/viewvc/llvm-project?rev=142317&view=rev Log: Object: Add isSymbolAbsolute and getSymbolSection. Modified: llvm/trunk/include/llvm/Object/COFF.h llvm/trunk/include/llvm/Object/MachO.h llvm/trunk/include/llvm/Object/ObjectFile.h llvm/trunk/lib/Object/COFFObjectFile.cpp llvm/trunk/lib/Object/ELFObjectFile.cpp llvm/trunk/lib/Object/MachOObjectFile.cpp Modified: llvm/trunk/include/llvm/Object/COFF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=142317&r1=142316&r2=142317&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/COFF.h (original) +++ llvm/trunk/include/llvm/Object/COFF.h Mon Oct 17 18:54:46 2011 @@ -108,6 +108,9 @@ virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const; virtual error_code isSymbolWeak(DataRefImpl Symb, bool &Res) const; virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const; + virtual error_code isSymbolAbsolute(DataRefImpl Symb, bool &Res) const; + virtual error_code getSymbolSection(DataRefImpl Symb, + section_iterator &Res) const; virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const; virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const; Modified: llvm/trunk/include/llvm/Object/MachO.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachO.h?rev=142317&r1=142316&r2=142317&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/MachO.h (original) +++ llvm/trunk/include/llvm/Object/MachO.h Mon Oct 17 18:54:46 2011 @@ -56,6 +56,9 @@ virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const; virtual error_code isSymbolWeak(DataRefImpl Symb, bool &Res) const; virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const; + virtual error_code isSymbolAbsolute(DataRefImpl Symb, bool &Res) const; + virtual error_code getSymbolSection(DataRefImpl Symb, + section_iterator &Res) const; virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const; virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const; Modified: llvm/trunk/include/llvm/Object/ObjectFile.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=142317&r1=142316&r2=142317&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/ObjectFile.h (original) +++ llvm/trunk/include/llvm/Object/ObjectFile.h Mon Oct 17 18:54:46 2011 @@ -78,55 +78,7 @@ return std::memcmp(&a, &b, sizeof(DataRefImpl)) == 0; } -/// SymbolRef - This is a value type class that represents a single symbol in -/// the list of symbols in the object file. -class SymbolRef { - friend class SectionRef; - DataRefImpl SymbolPimpl; - const ObjectFile *OwningObject; - -public: - SymbolRef() : OwningObject(NULL) { - std::memset(&SymbolPimpl, 0, sizeof(SymbolPimpl)); - } - - enum Type { - ST_Function, - ST_Data, - ST_External, // Defined in another object file - ST_Other - }; - - SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner); - - bool operator==(const SymbolRef &Other) const; - - error_code getNext(SymbolRef &Result) const; - - error_code getName(StringRef &Result) const; - error_code getAddress(uint64_t &Result) const; - error_code getOffset(uint64_t &Result) const; - error_code getSize(uint64_t &Result) const; - error_code getType(SymbolRef::Type &Result) const; - - /// Returns the ascii char that should be displayed in a symbol table dump via - /// nm for this symbol. - error_code getNMTypeChar(char &Result) const; - - /// Returns true for symbols that are internal to the object file format such - /// as section symbols. - error_code isInternal(bool &Result) const; - - /// Returns true for symbols that can be used in another objects, - /// such as library functions - error_code isGlobal(bool &Result) const; - - /// Returns true for weak symbols. - error_code isWeak(bool &Result) const; - - DataRefImpl getRawDataRefImpl() const; -}; -typedef content_iterator symbol_iterator; +class SymbolRef; /// RelocationRef - This is a value type class that represents a single /// relocation in the list of relocations in the object file. @@ -201,6 +153,63 @@ }; typedef content_iterator section_iterator; +/// SymbolRef - This is a value type class that represents a single symbol in +/// the list of symbols in the object file. +class SymbolRef { + friend class SectionRef; + DataRefImpl SymbolPimpl; + const ObjectFile *OwningObject; + +public: + SymbolRef() : OwningObject(NULL) { + std::memset(&SymbolPimpl, 0, sizeof(SymbolPimpl)); + } + + enum Type { + ST_Function, + ST_Data, + ST_External, // Defined in another object file + ST_Other + }; + + SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner); + + bool operator==(const SymbolRef &Other) const; + + error_code getNext(SymbolRef &Result) const; + + error_code getName(StringRef &Result) const; + error_code getAddress(uint64_t &Result) const; + error_code getOffset(uint64_t &Result) const; + error_code getSize(uint64_t &Result) const; + error_code getType(SymbolRef::Type &Result) const; + + /// Returns the ascii char that should be displayed in a symbol table dump via + /// nm for this symbol. + error_code getNMTypeChar(char &Result) const; + + /// Returns true for symbols that are internal to the object file format such + /// as section symbols. + error_code isInternal(bool &Result) const; + + /// Returns true for symbols that can be used in another objects, + /// such as library functions + error_code isGlobal(bool &Result) const; + + /// Returns true for weak symbols. + error_code isWeak(bool &Result) const; + + /// @brief Return true for absolute symbols. + error_code isAbsolute(bool &Result) const; + + /// @brief Get section this symbol is defined in reference to. Result is + /// end_sections() if it is undefined or is an absolute symbol. + error_code getSection(section_iterator &Result) const; + + DataRefImpl getRawDataRefImpl() const; +}; +typedef content_iterator symbol_iterator; + const uint64_t UnknownAddressOrSize = ~0ULL; /// ObjectFile - This class is the base class for all object file types. @@ -238,6 +247,9 @@ virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const = 0; virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const = 0; virtual error_code isSymbolWeak(DataRefImpl Symb, bool &Res) const = 0; + virtual error_code isSymbolAbsolute(DataRefImpl Symb, bool &Res) const = 0; + virtual error_code getSymbolSection(DataRefImpl Symb, + section_iterator &Res) const = 0; // Same as above for SectionRef. friend class SectionRef; @@ -352,6 +364,14 @@ return OwningObject->isSymbolWeak(SymbolPimpl, Result); } +inline error_code SymbolRef::isAbsolute(bool &Result) const { + return OwningObject->isSymbolAbsolute(SymbolPimpl, Result); +} + +inline error_code SymbolRef::getSection(section_iterator &Result) const { + return OwningObject->getSymbolSection(SymbolPimpl, Result); +} + inline error_code SymbolRef::getType(SymbolRef::Type &Result) const { return OwningObject->getSymbolType(SymbolPimpl, Result); } Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=142317&r1=142316&r2=142317&view=diff ============================================================================== --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Mon Oct 17 18:54:46 2011 @@ -268,6 +268,28 @@ return object_error::success; } +error_code COFFObjectFile::isSymbolAbsolute(DataRefImpl Symb, + bool &Result) const { + const coff_symbol *symb = toSymb(Symb); + Result = symb->SectionNumber == COFF::IMAGE_SYM_ABSOLUTE; + return object_error::success; +} + +error_code COFFObjectFile::getSymbolSection(DataRefImpl Symb, + section_iterator &Result) const { + const coff_symbol *symb = toSymb(Symb); + if (symb->SectionNumber <= COFF::IMAGE_SYM_UNDEFINED) + Result = end_sections(); + else { + const coff_section *sec; + if (error_code ec = getSection(symb->SectionNumber, sec)) return ec; + DataRefImpl Sec; + Sec.p = reinterpret_cast(sec); + Result = section_iterator(SectionRef(Sec, this)); + } + return object_error::success; +} + error_code COFFObjectFile::getSectionNext(DataRefImpl Sec, SectionRef &Result) const { const coff_section *sec = toSec(Sec); Modified: llvm/trunk/lib/Object/ELFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ELFObjectFile.cpp?rev=142317&r1=142316&r2=142317&view=diff ============================================================================== --- llvm/trunk/lib/Object/ELFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/ELFObjectFile.cpp Mon Oct 17 18:54:46 2011 @@ -333,6 +333,9 @@ virtual error_code isSymbolGlobal(DataRefImpl Symb, bool &Res) const; virtual error_code isSymbolWeak(DataRefImpl Symb, bool &Res) const; virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const; + virtual error_code isSymbolAbsolute(DataRefImpl Symb, bool &Res) const; + virtual error_code getSymbolSection(DataRefImpl Symb, + section_iterator &Res) const; virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const; virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const; @@ -655,6 +658,32 @@ template error_code ELFObjectFile + ::isSymbolAbsolute(DataRefImpl Symb, bool &Res) const { + validateSymbol(Symb); + const Elf_Sym *symb = getSymbol(Symb); + Res = symb->st_shndx == ELF::SHN_ABS; + return object_error::success; +} + +template +error_code ELFObjectFile + ::getSymbolSection(DataRefImpl Symb, + section_iterator &Res) const { + validateSymbol(Symb); + const Elf_Sym *symb = getSymbol(Symb); + const Elf_Shdr *sec = getSection(symb); + if (!sec) + Res = end_sections(); + else { + DataRefImpl Sec; + Sec.p = reinterpret_cast(sec); + Res = section_iterator(SectionRef(Sec, this)); + } + return object_error::success; +} + +template +error_code ELFObjectFile ::isSymbolInternal(DataRefImpl Symb, bool &Result) const { validateSymbol(Symb); Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=142317&r1=142316&r2=142317&view=diff ============================================================================== --- llvm/trunk/lib/Object/MachOObjectFile.cpp (original) +++ llvm/trunk/lib/Object/MachOObjectFile.cpp Mon Oct 17 18:54:46 2011 @@ -242,6 +242,43 @@ return object_error::success; } +error_code MachOObjectFile::isSymbolAbsolute(DataRefImpl Symb, bool &Res) const{ + uint8_t n_type; + if (MachOObj->is64Bit()) { + InMemoryStruct Entry; + getSymbol64TableEntry(Symb, Entry); + n_type = Entry->Type; + } else { + InMemoryStruct Entry; + getSymbolTableEntry(Symb, Entry); + n_type = Entry->Type; + } + + Res = (n_type & MachO::NlistMaskType) == MachO::NListTypeAbsolute; + return object_error::success; +} + +error_code MachOObjectFile::getSymbolSection(DataRefImpl Symb, + section_iterator &Res) const { + uint8_t index; + if (MachOObj->is64Bit()) { + InMemoryStruct Entry; + getSymbol64TableEntry(Symb, Entry); + index = Entry->SectionIndex; + } else { + InMemoryStruct Entry; + getSymbolTableEntry(Symb, Entry); + index = Entry->SectionIndex; + } + + if (index == 0) + Res = end_sections(); + else + Res = section_iterator(SectionRef(Sections[index], this)); + + return object_error::success; +} + error_code MachOObjectFile::getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const { uint8_t n_type; From bigcheesegs at gmail.com Mon Oct 17 18:55:06 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 17 Oct 2011 23:55:06 -0000 Subject: [llvm-commits] [llvm] r142318 - in /llvm/trunk: include/llvm/Object/ObjectFile.h lib/Object/ELFObjectFile.cpp Message-ID: <20111017235506.4C3F22A6C12C@llvm.org> Author: mspencer Date: Mon Oct 17 18:55:06 2011 New Revision: 142318 URL: http://llvm.org/viewvc/llvm-project?rev=142318&view=rev Log: Object: Add some types to SymbolRef::Type. Some of these can be true at the same time and there are a lot to add, so this should be turned into a bitfield. Some of the other accessors should probably be folded into this. Modified: llvm/trunk/include/llvm/Object/ObjectFile.h llvm/trunk/lib/Object/ELFObjectFile.cpp Modified: llvm/trunk/include/llvm/Object/ObjectFile.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=142318&r1=142317&r2=142318&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/ObjectFile.h (original) +++ llvm/trunk/include/llvm/Object/ObjectFile.h Mon Oct 17 18:55:06 2011 @@ -166,9 +166,11 @@ } enum Type { - ST_Function, ST_Data, + ST_Debug, ST_External, // Defined in another object file + ST_File, + ST_Function, ST_Other }; Modified: llvm/trunk/lib/Object/ELFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ELFObjectFile.cpp?rev=142318&r1=142317&r2=142318&view=diff ============================================================================== --- llvm/trunk/lib/Object/ELFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/ELFObjectFile.cpp Mon Oct 17 18:55:06 2011 @@ -621,6 +621,12 @@ } switch (symb->getType()) { + case ELF::STT_SECTION: + Result = SymbolRef::ST_Debug; + break; + case ELF::STT_FILE: + Result = SymbolRef::ST_File; + break; case ELF::STT_FUNC: Result = SymbolRef::ST_Function; break; From bigcheesegs at gmail.com Mon Oct 17 18:55:22 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 17 Oct 2011 23:55:22 -0000 Subject: [llvm-commits] [llvm] r142319 - in /llvm/trunk: test/Object/objdump-symbol-table.test tools/llvm-objdump/llvm-objdump.cpp Message-ID: <20111017235522.B2CAB2A6C12C@llvm.org> Author: mspencer Date: Mon Oct 17 18:55:22 2011 New Revision: 142319 URL: http://llvm.org/viewvc/llvm-project?rev=142319&view=rev Log: llvm-objdump: Add static symbol table dumping. Modified: llvm/trunk/test/Object/objdump-symbol-table.test llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Modified: llvm/trunk/test/Object/objdump-symbol-table.test URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/objdump-symbol-table.test?rev=142319&r1=142318&r2=142319&view=diff ============================================================================== --- llvm/trunk/test/Object/objdump-symbol-table.test (original) +++ llvm/trunk/test/Object/objdump-symbol-table.test Mon Oct 17 18:55:22 2011 @@ -3,9 +3,7 @@ RUN: llvm-objdump -t %p/TestObjectFiles/trivial-object-test.elf-i386 \ RUN: | FileCheck %s -check-prefix ELF-i386 -XFAIL: * - -COFF-i386: trivial-object-test.coff-i386: file format pe-i386 +COFF-i386: trivial-object-test.coff-i386: file format COFF-i386: SYMBOL TABLE: COFF-i386: [ 0](sec 1)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x00000000 .text COFF-i386: AUX scnlen 0x24 nreloc 3 nlnno 0 checksum 0x0 assoc 1 comdat 0 @@ -16,7 +14,7 @@ COFF-i386: [ 6](sec 0)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000000 _puts COFF-i386: [ 7](sec 0)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000000 _SomeOtherFunction -ELF-i386: trivial-object-test.elf-i386: file format elf32-i386 +ELF-i386: trivial-object-test.elf-i386: file format ELF-i386: SYMBOL TABLE: ELF-i386: 00000000 l df *ABS* 00000000 trivial-object-test.s ELF-i386: 00000000 l d .text 00000000 .text Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=142319&r1=142318&r2=142319&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Mon Oct 17 18:55:22 2011 @@ -16,6 +16,7 @@ #include "llvm-objdump.h" #include "MCFunction.h" #include "llvm/Object/Archive.h" +#include "llvm/Object/COFF.h" #include "llvm/Object/ObjectFile.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/StringExtras.h" @@ -65,6 +66,9 @@ SectionContents("s", cl::desc("Display the content of each section")); static cl::opt +SymbolTable("t", cl::desc("Display the symbol table")); + +static cl::opt MachO("macho", cl::desc("Use MachO specific object file parser")); static cl::alias MachOm("m", cl::desc("Alias for --macho"), cl::aliasopt(MachO)); @@ -411,6 +415,113 @@ } } +static void PrintCOFFSymbolTable(const COFFObjectFile *coff) { + const coff_file_header *header; + if (error(coff->getHeader(header))) return; + int aux_count = 0; + const coff_symbol *symbol = 0; + for (int i = 0, e = header->NumberOfSymbols; i != e; ++i) { + if (aux_count--) { + // Figure out which type of aux this is. + if (symbol->StorageClass == COFF::IMAGE_SYM_CLASS_STATIC + && symbol->Value == 0) { // Section definition. + const coff_aux_section_definition *asd; + if (error(coff->getAuxSymbol(i, asd))) + return; + outs() << "AUX " + << format("scnlen 0x%x nreloc %d nlnno %d checksum 0x%x " + , asd->Length + , asd->NumberOfRelocations + , asd->NumberOfLinenumbers + , asd->CheckSum) + << format("assoc %d comdat %d\n", asd->Number, asd->Selection); + } else { + outs() << "AUX Unknown\n"; + } + } else { + StringRef name; + if (error(coff->getSymbol(i, symbol))) return; + if (error(coff->getSymbolName(symbol, name))) return; + outs() << "[" << format("%2d", i) << "]" + << "(sec " << format("%2d", int16_t(symbol->SectionNumber)) << ")" + << "(fl 0x" << format("%02x", symbol->Type.BaseType) << ")" + << "(ty " << format("%3x", symbol->Type) << ")" + << "(scl " << format("%3x", symbol->StorageClass) << ") " + << "(nx " << unsigned(symbol->NumberOfAuxSymbols) << ") " + << "0x" << format("%08x", symbol->Value) << " " + << name << "\n"; + aux_count = symbol->NumberOfAuxSymbols; + } + } +} + +static void PrintSymbolTable(const ObjectFile *o) { + outs() << "SYMBOL TABLE:\n"; + + if (const COFFObjectFile *coff = dyn_cast(o)) + PrintCOFFSymbolTable(coff); + else { + error_code ec; + for (symbol_iterator si = o->begin_symbols(), + se = o->end_symbols(); si != se; si.increment(ec)) { + if (error(ec)) return; + StringRef Name; + uint64_t Offset; + bool Global; + SymbolRef::Type Type; + bool Weak; + bool Absolute; + uint64_t Size; + section_iterator Section = o->end_sections(); + if (error(si->getName(Name))) continue; + if (error(si->getOffset(Offset))) continue; + if (error(si->isGlobal(Global))) continue; + if (error(si->getType(Type))) continue; + if (error(si->isWeak(Weak))) continue; + if (error(si->isAbsolute(Absolute))) continue; + if (error(si->getSize(Size))) continue; + if (error(si->getSection(Section))) continue; + + if (Offset == UnknownAddressOrSize) + Offset = 0; + char GlobLoc = ' '; + if (Type != SymbolRef::ST_External) + GlobLoc = Global ? 'g' : 'l'; + char Debug = (Type == SymbolRef::ST_Debug || Type == SymbolRef::ST_File) + ? 'd' : ' '; + char FileFunc = ' '; + if (Type == SymbolRef::ST_File) + FileFunc = 'f'; + else if (Type == SymbolRef::ST_Function) + FileFunc = 'F'; + + outs() << format("%08x", Offset) << " " + << GlobLoc // Local -> 'l', Global -> 'g', Neither -> ' ' + << (Weak ? 'w' : ' ') // Weak? + << ' ' // Constructor. Not supported yet. + << ' ' // Warning. Not supported yet. + << ' ' // Indirect reference to another symbol. + << Debug // Debugging (d) or dynamic (D) symbol. + << FileFunc // Name of function (F), file (f) or object (O). + << ' '; + if (Absolute) + outs() << "*ABS*"; + else if (Section == o->end_sections()) + outs() << "*UND*"; + else { + StringRef SectionName; + if (error(Section->getName(SectionName))) + SectionName = ""; + outs() << SectionName; + } + outs() << '\t' + << format("%08x ", Size) + << Name + << '\n'; + } + } +} + static void DumpObject(const ObjectFile *o) { outs() << '\n'; outs() << o->getFileName() @@ -424,6 +535,8 @@ PrintSectionHeaders(o); if (SectionContents) PrintSectionContents(o); + if (SymbolTable) + PrintSymbolTable(o); } /// @brief Dump each object file in \a a; @@ -494,7 +607,11 @@ if (InputFilenames.size() == 0) InputFilenames.push_back("a.out"); - if (!Disassemble && !Relocations && !SectionHeaders && !SectionContents) { + if (!Disassemble + && !Relocations + && !SectionHeaders + && !SectionContents + && !SymbolTable) { cl::PrintHelpMessage(); return 2; } From bigcheesegs at gmail.com Mon Oct 17 19:17:04 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 18 Oct 2011 00:17:04 -0000 Subject: [llvm-commits] [llvm] r142320 - in /llvm/trunk: test/Object/objdump-symbol-table.test tools/llvm-objdump/llvm-objdump.cpp Message-ID: <20111018001704.8587C2A6C12C@llvm.org> Author: mspencer Date: Mon Oct 17 19:17:04 2011 New Revision: 142320 URL: http://llvm.org/viewvc/llvm-project?rev=142320&view=rev Log: Revert "llvm-objdump: Add static symbol table dumping." This reverts commit 0c30d4e4f5f9110c5a67bd0ca84444dc58697596. Modified: llvm/trunk/test/Object/objdump-symbol-table.test llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Modified: llvm/trunk/test/Object/objdump-symbol-table.test URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/objdump-symbol-table.test?rev=142320&r1=142319&r2=142320&view=diff ============================================================================== --- llvm/trunk/test/Object/objdump-symbol-table.test (original) +++ llvm/trunk/test/Object/objdump-symbol-table.test Mon Oct 17 19:17:04 2011 @@ -3,7 +3,9 @@ RUN: llvm-objdump -t %p/TestObjectFiles/trivial-object-test.elf-i386 \ RUN: | FileCheck %s -check-prefix ELF-i386 -COFF-i386: trivial-object-test.coff-i386: file format +XFAIL: * + +COFF-i386: trivial-object-test.coff-i386: file format pe-i386 COFF-i386: SYMBOL TABLE: COFF-i386: [ 0](sec 1)(fl 0x00)(ty 0)(scl 3) (nx 1) 0x00000000 .text COFF-i386: AUX scnlen 0x24 nreloc 3 nlnno 0 checksum 0x0 assoc 1 comdat 0 @@ -14,7 +16,7 @@ COFF-i386: [ 6](sec 0)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000000 _puts COFF-i386: [ 7](sec 0)(fl 0x00)(ty 0)(scl 2) (nx 0) 0x00000000 _SomeOtherFunction -ELF-i386: trivial-object-test.elf-i386: file format +ELF-i386: trivial-object-test.elf-i386: file format elf32-i386 ELF-i386: SYMBOL TABLE: ELF-i386: 00000000 l df *ABS* 00000000 trivial-object-test.s ELF-i386: 00000000 l d .text 00000000 .text Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=142320&r1=142319&r2=142320&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Mon Oct 17 19:17:04 2011 @@ -16,7 +16,6 @@ #include "llvm-objdump.h" #include "MCFunction.h" #include "llvm/Object/Archive.h" -#include "llvm/Object/COFF.h" #include "llvm/Object/ObjectFile.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/StringExtras.h" @@ -66,9 +65,6 @@ SectionContents("s", cl::desc("Display the content of each section")); static cl::opt -SymbolTable("t", cl::desc("Display the symbol table")); - -static cl::opt MachO("macho", cl::desc("Use MachO specific object file parser")); static cl::alias MachOm("m", cl::desc("Alias for --macho"), cl::aliasopt(MachO)); @@ -415,113 +411,6 @@ } } -static void PrintCOFFSymbolTable(const COFFObjectFile *coff) { - const coff_file_header *header; - if (error(coff->getHeader(header))) return; - int aux_count = 0; - const coff_symbol *symbol = 0; - for (int i = 0, e = header->NumberOfSymbols; i != e; ++i) { - if (aux_count--) { - // Figure out which type of aux this is. - if (symbol->StorageClass == COFF::IMAGE_SYM_CLASS_STATIC - && symbol->Value == 0) { // Section definition. - const coff_aux_section_definition *asd; - if (error(coff->getAuxSymbol(i, asd))) - return; - outs() << "AUX " - << format("scnlen 0x%x nreloc %d nlnno %d checksum 0x%x " - , asd->Length - , asd->NumberOfRelocations - , asd->NumberOfLinenumbers - , asd->CheckSum) - << format("assoc %d comdat %d\n", asd->Number, asd->Selection); - } else { - outs() << "AUX Unknown\n"; - } - } else { - StringRef name; - if (error(coff->getSymbol(i, symbol))) return; - if (error(coff->getSymbolName(symbol, name))) return; - outs() << "[" << format("%2d", i) << "]" - << "(sec " << format("%2d", int16_t(symbol->SectionNumber)) << ")" - << "(fl 0x" << format("%02x", symbol->Type.BaseType) << ")" - << "(ty " << format("%3x", symbol->Type) << ")" - << "(scl " << format("%3x", symbol->StorageClass) << ") " - << "(nx " << unsigned(symbol->NumberOfAuxSymbols) << ") " - << "0x" << format("%08x", symbol->Value) << " " - << name << "\n"; - aux_count = symbol->NumberOfAuxSymbols; - } - } -} - -static void PrintSymbolTable(const ObjectFile *o) { - outs() << "SYMBOL TABLE:\n"; - - if (const COFFObjectFile *coff = dyn_cast(o)) - PrintCOFFSymbolTable(coff); - else { - error_code ec; - for (symbol_iterator si = o->begin_symbols(), - se = o->end_symbols(); si != se; si.increment(ec)) { - if (error(ec)) return; - StringRef Name; - uint64_t Offset; - bool Global; - SymbolRef::Type Type; - bool Weak; - bool Absolute; - uint64_t Size; - section_iterator Section = o->end_sections(); - if (error(si->getName(Name))) continue; - if (error(si->getOffset(Offset))) continue; - if (error(si->isGlobal(Global))) continue; - if (error(si->getType(Type))) continue; - if (error(si->isWeak(Weak))) continue; - if (error(si->isAbsolute(Absolute))) continue; - if (error(si->getSize(Size))) continue; - if (error(si->getSection(Section))) continue; - - if (Offset == UnknownAddressOrSize) - Offset = 0; - char GlobLoc = ' '; - if (Type != SymbolRef::ST_External) - GlobLoc = Global ? 'g' : 'l'; - char Debug = (Type == SymbolRef::ST_Debug || Type == SymbolRef::ST_File) - ? 'd' : ' '; - char FileFunc = ' '; - if (Type == SymbolRef::ST_File) - FileFunc = 'f'; - else if (Type == SymbolRef::ST_Function) - FileFunc = 'F'; - - outs() << format("%08x", Offset) << " " - << GlobLoc // Local -> 'l', Global -> 'g', Neither -> ' ' - << (Weak ? 'w' : ' ') // Weak? - << ' ' // Constructor. Not supported yet. - << ' ' // Warning. Not supported yet. - << ' ' // Indirect reference to another symbol. - << Debug // Debugging (d) or dynamic (D) symbol. - << FileFunc // Name of function (F), file (f) or object (O). - << ' '; - if (Absolute) - outs() << "*ABS*"; - else if (Section == o->end_sections()) - outs() << "*UND*"; - else { - StringRef SectionName; - if (error(Section->getName(SectionName))) - SectionName = ""; - outs() << SectionName; - } - outs() << '\t' - << format("%08x ", Size) - << Name - << '\n'; - } - } -} - static void DumpObject(const ObjectFile *o) { outs() << '\n'; outs() << o->getFileName() @@ -535,8 +424,6 @@ PrintSectionHeaders(o); if (SectionContents) PrintSectionContents(o); - if (SymbolTable) - PrintSymbolTable(o); } /// @brief Dump each object file in \a a; @@ -607,11 +494,7 @@ if (InputFilenames.size() == 0) InputFilenames.push_back("a.out"); - if (!Disassemble - && !Relocations - && !SectionHeaders - && !SectionContents - && !SymbolTable) { + if (!Disassemble && !Relocations && !SectionHeaders && !SectionContents) { cl::PrintHelpMessage(); return 2; } From grosbach at apple.com Mon Oct 17 19:22:00 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 18 Oct 2011 00:22:00 -0000 Subject: [llvm-commits] [llvm] r142321 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-mov-encoding.s test/MC/ARM/neont2-mov-encoding.s utils/TableGen/EDEmitter.cpp Message-ID: <20111018002200.7774C3524001@llvm.org> Author: grosbach Date: Mon Oct 17 19:22:00 2011 New Revision: 142321 URL: http://llvm.org/viewvc/llvm-project?rev=142321&view=rev Log: ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/neon-mov-encoding.s llvm/trunk/test/MC/ARM/neont2-mov-encoding.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142321&r1=142320&r2=142321&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 17 19:22:00 2011 @@ -29,6 +29,16 @@ let PrintMethod = "printNEONModImmOperand"; let ParserMatchClass = nImmSplatI16AsmOperand; } +def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; } +def nImmSplatI32 : Operand { + let PrintMethod = "printNEONModImmOperand"; + let ParserMatchClass = nImmSplatI32AsmOperand; +} +def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; } +def nImmVMOVI32 : Operand { + let PrintMethod = "printNEONModImmOperand"; + let ParserMatchClass = nImmVMOVI32AsmOperand; +} def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; } def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; } @@ -3757,7 +3767,7 @@ } def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1, - (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), + (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src), IIC_VMOVImm, "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", [(set DPR:$Vd, @@ -3775,7 +3785,7 @@ } def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1, - (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), + (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src), IIC_VMOVImm, "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", [(set QPR:$Vd, @@ -3806,7 +3816,7 @@ } def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1, - (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src), + (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src), IIC_VMOVImm, "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", [(set DPR:$Vd, @@ -3824,7 +3834,7 @@ } def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1, - (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src), + (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src), IIC_VMOVImm, "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", [(set QPR:$Vd, @@ -3863,14 +3873,14 @@ } def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, "vmvn", "i32", "$Vd, $SIMM", "", [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> { let Inst{11-8} = SIMM{11-8}; } def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, "vmvn", "i32", "$Vd, $SIMM", "", [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> { let Inst{11-8} = SIMM{11-8}; @@ -4348,14 +4358,14 @@ } def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, "vmov", "i32", "$Vd, $SIMM", "", [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> { let Inst{11-8} = SIMM{11-8}; } def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, "vmov", "i32", "$Vd, $SIMM", "", [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> { let Inst{11-8} = SIMM{11-8}; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=142321&r1=142320&r2=142321&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Oct 17 19:22:00 2011 @@ -935,6 +935,37 @@ return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); } + bool isNEONi32splat() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + // Must be a constant. + if (!CE) return false; + int64_t Value = CE->getValue(); + // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. + return (Value >= 0 && Value < 256) || + (Value >= 0x0100 && Value <= 0xff00) || + (Value >= 0x010000 && Value <= 0xff0000) || + (Value >= 0x01000000 && Value <= 0xff000000); + } + + bool isNEONi32vmov() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + // Must be a constant. + if (!CE) return false; + int64_t Value = CE->getValue(); + // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, + // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. + return (Value >= 0 && Value < 256) || + (Value >= 0x0100 && Value <= 0xff00) || + (Value >= 0x010000 && Value <= 0xff0000) || + (Value >= 0x01000000 && Value <= 0xff000000) || + (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || + (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); + } + void addExpr(MCInst &Inst, const MCExpr *Expr) const { // Add as immediates when possible. Null MCExpr = 0. if (Expr == 0) @@ -1477,6 +1508,34 @@ Inst.addOperand(MCOperand::CreateImm(Value)); } + void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + // The immediate encodes the type of constant as well as the value. + const MCConstantExpr *CE = dyn_cast(getImm()); + unsigned Value = CE->getValue(); + if (Value >= 256 && Value <= 0xff00) + Value = (Value >> 8) | 0x200; + else if (Value > 0xffff && Value <= 0xff0000) + Value = (Value >> 16) | 0x400; + else if (Value > 0xffffff) + Value = (Value >> 24) | 0x600; + Inst.addOperand(MCOperand::CreateImm(Value)); + } + + void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + // The immediate encodes the type of constant as well as the value. + const MCConstantExpr *CE = dyn_cast(getImm()); + unsigned Value = CE->getValue(); + if (Value >= 256 && Value <= 0xffff) + Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); + else if (Value > 0xffff && Value <= 0xffffff) + Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); + else if (Value > 0xffffff) + Value = (Value >> 24) | 0x600; + Inst.addOperand(MCOperand::CreateImm(Value)); + } + virtual void print(raw_ostream &OS) const; static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.s?rev=142321&r1=142320&r2=142321&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mov-encoding.s Mon Oct 17 19:22:00 2011 @@ -3,23 +3,23 @@ vmov.i8 d16, #0x8 vmov.i16 d16, #0x10 vmov.i16 d16, #0x1000 -@ vmov.i32 d16, #0x20 -@ vmov.i32 d16, #0x2000 -@ vmov.i32 d16, #0x200000 -@ vmov.i32 d16, #0x20000000 -@ vmov.i32 d16, #0x20FF -@ vmov.i32 d16, #0x20FFFF + vmov.i32 d16, #0x20 + vmov.i32 d16, #0x2000 + vmov.i32 d16, #0x200000 + vmov.i32 d16, #0x20000000 + vmov.i32 d16, #0x20FF + vmov.i32 d16, #0x20FFFF @ vmov.i64 d16, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] @ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] @ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2] -@ FIXME: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2] -@ FIXME: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] -@ FIXME: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] -@ FIXME: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] -@ FIXME: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] -@ FIXME: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] @ FIXME: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] @@ -27,42 +27,42 @@ vmov.i8 q8, #0x8 vmov.i16 q8, #0x10 vmov.i16 q8, #0x1000 -@ vmov.i32 q8, #0x20 -@ vmov.i32 q8, #0x2000 -@ vmov.i32 q8, #0x200000 -@ vmov.i32 q8, #0x20000000 -@ vmov.i32 q8, #0x20FF -@ vmov.i32 q8, #0x20FFFF + vmov.i32 q8, #0x20 + vmov.i32 q8, #0x2000 + vmov.i32 q8, #0x200000 + vmov.i32 q8, #0x20000000 + vmov.i32 q8, #0x20FF + vmov.i32 q8, #0x20FFFF @ vmov.i64 q8, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2] @ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] @ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2] -@ FIXME: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2] -@ FIXME: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] -@ FIXME: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] -@ FIXME: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] -@ FIXME: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] -@ FIXME: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] @ FIXME: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] vmvn.i16 d16, #0x10 vmvn.i16 d16, #0x1000 -@ vmvn.i32 d16, #0x20 -@ vmvn.i32 d16, #0x2000 -@ vmvn.i32 d16, #0x200000 -@ vmvn.i32 d16, #0x20000000 -@ vmvn.i32 d16, #0x20FF -@ vmvn.i32 d16, #0x20FFFF + vmvn.i32 d16, #0x20 + vmvn.i32 d16, #0x2000 + vmvn.i32 d16, #0x200000 + vmvn.i32 d16, #0x20000000 + vmvn.i32 d16, #0x20FF + vmvn.i32 d16, #0x20FFFF @ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2] @ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2] -@ FIXME: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2] -@ FIXME: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] -@ FIXME: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] -@ FIXME: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] -@ FIXME: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] -@ FIXME: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] vmovl.s8 q8, d16 vmovl.s16 q8, d16 Modified: llvm/trunk/test/MC/ARM/neont2-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mov-encoding.s?rev=142321&r1=142320&r2=142321&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mov-encoding.s Mon Oct 17 19:22:00 2011 @@ -5,66 +5,66 @@ vmov.i8 d16, #0x8 vmov.i16 d16, #0x10 vmov.i16 d16, #0x1000 -@ vmov.i32 d16, #0x20 -@ vmov.i32 d16, #0x2000 -@ vmov.i32 d16, #0x200000 -@ vmov.i32 d16, #0x20000000 -@ vmov.i32 d16, #0x20FF -@ vmov.i32 d16, #0x20FFFF + vmov.i32 d16, #0x20 + vmov.i32 d16, #0x2000 + vmov.i32 d16, #0x200000 + vmov.i32 d16, #0x20000000 + vmov.i32 d16, #0x20FF + vmov.i32 d16, #0x20FFFF @ vmov.i64 d16, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 d16, #0x8 @ encoding: [0xc0,0xef,0x18,0x0e] @ CHECK: vmov.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x10,0x08] @ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x10,0x0a] -@ FIXME: vmov.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x10,0x00] -@ FIXME: vmov.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x10,0x02] -@ FIXME: vmov.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x10,0x04] -@ FIXME: vmov.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x10,0x06] -@ FIXME: vmov.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x10,0x0c] -@ FIXME: vmov.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x10,0x0d] +@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x10,0x00] +@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x10,0x02] +@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x10,0x04] +@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x10,0x06] +@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x10,0x0c] +@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x10,0x0d] @ FIXME: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x33,0x0e] vmov.i8 q8, #0x8 vmov.i16 q8, #0x10 vmov.i16 q8, #0x1000 -@ vmov.i32 q8, #0x20 -@ vmov.i32 q8, #0x2000 -@ vmov.i32 q8, #0x200000 -@ vmov.i32 q8, #0x20000000 -@ vmov.i32 q8, #0x20FF -@ vmov.i32 q8, #0x20FFFF + vmov.i32 q8, #0x20 + vmov.i32 q8, #0x2000 + vmov.i32 q8, #0x200000 + vmov.i32 q8, #0x20000000 + vmov.i32 q8, #0x20FF + vmov.i32 q8, #0x20FFFF @ vmov.i64 q8, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 q8, #0x8 @ encoding: [0xc0,0xef,0x58,0x0e] @ CHECK: vmov.i16 q8, #0x10 @ encoding: [0xc1,0xef,0x50,0x08] @ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0xc1,0xef,0x50,0x0a] -@ FIXME: vmov.i32 q8, #0x20 @ encoding: [0xc2,0xef,0x50,0x00] -@ FIXME: vmov.i32 q8, #0x2000 @ encoding: [0xc2,0xef,0x50,0x02] -@ FIXME: vmov.i32 q8, #0x200000 @ encoding: [0xc2,0xef,0x50,0x04] -@ FIXME: vmov.i32 q8, #0x20000000 @ encoding: [0xc2,0xef,0x50,0x06] -@ FIXME: vmov.i32 q8, #0x20FF @ encoding: [0xc2,0xef,0x50,0x0c] -@ FIXME: vmov.i32 q8, #0x20FFFF @ encoding: [0xc2,0xef,0x50,0x0d] +@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0xc2,0xef,0x50,0x00] +@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0xc2,0xef,0x50,0x02] +@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0xc2,0xef,0x50,0x04] +@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0xc2,0xef,0x50,0x06] +@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0xc2,0xef,0x50,0x0c] +@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0xc2,0xef,0x50,0x0d] @ FIXME: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x73,0x0e] vmvn.i16 d16, #0x10 vmvn.i16 d16, #0x1000 -@ vmvn.i32 d16, #0x20 -@ vmvn.i32 d16, #0x2000 -@ vmvn.i32 d16, #0x200000 -@ vmvn.i32 d16, #0x20000000 -@ vmvn.i32 d16, #0x20FF -@ vmvn.i32 d16, #0x20FFFF + vmvn.i32 d16, #0x20 + vmvn.i32 d16, #0x2000 + vmvn.i32 d16, #0x200000 + vmvn.i32 d16, #0x20000000 + vmvn.i32 d16, #0x20FF + vmvn.i32 d16, #0x20FFFF @ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x30,0x08] @ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0xc1,0xef,0x30,0x0a] -@ FIXME: vmvn.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x30,0x00] -@ FIXME: vmvn.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x30,0x02] -@ FIXME: vmvn.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x30,0x04] -@ FIXME: vmvn.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x30,0x06] -@ FIXME: vmvn.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x30,0x0c] -@ FIXME: vmvn.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x30,0x0d] +@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0xc2,0xef,0x30,0x00] +@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x30,0x02] +@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x30,0x04] +@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x30,0x06] +@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x30,0x0c] +@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x30,0x0d] vmovl.s8 q8, d16 Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=142321&r1=142320&r2=142321&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Oct 17 19:22:00 2011 @@ -599,6 +599,8 @@ IMM("nModImm"); IMM("nImmSplatI8"); IMM("nImmSplatI16"); + IMM("nImmSplatI32"); + IMM("nImmVMOVI32"); IMM("imm0_7"); IMM("imm0_15"); IMM("imm0_255"); From lhames at gmail.com Mon Oct 17 19:23:49 2011 From: lhames at gmail.com (Lang Hames) Date: Tue, 18 Oct 2011 00:23:49 -0000 Subject: [llvm-commits] [llvm] r142323 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/AsmParser/CMakeLists.txt lib/AsmParser/LLParser.cpp lib/Target/TargetData.cpp Message-ID: <20111018002349.8EEEB2A6C12C@llvm.org> Author: lhames Date: Mon Oct 17 19:23:49 2011 New Revision: 142323 URL: http://llvm.org/viewvc/llvm-project?rev=142323&view=rev Log: Backing out patch. Will refactor to remove the AsmParser dependency on Target. Modified: llvm/trunk/include/llvm/Target/TargetData.h llvm/trunk/lib/AsmParser/CMakeLists.txt llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/Target/TargetData.cpp Modified: llvm/trunk/include/llvm/Target/TargetData.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetData.h?rev=142323&r1=142322&r2=142323&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetData.h (original) +++ llvm/trunk/include/llvm/Target/TargetData.h Mon Oct 17 19:23:49 2011 @@ -44,7 +44,7 @@ AGGREGATE_ALIGN = 'a', ///< Aggregate alignment STACK_ALIGN = 's' ///< Stack objects alignment }; - + /// Target alignment element. /// /// Stores the alignment data associated with a given alignment type (pointer, @@ -80,7 +80,7 @@ unsigned StackNaturalAlign; ///< Stack natural alignment SmallVector LegalIntWidths; ///< Legal Integers. - + /// Alignments- Where the primitive type alignment data is stored. /// /// @sa init(). @@ -88,7 +88,7 @@ /// pointers vs. 64-bit pointers by extending TargetAlignment, but for now, /// we don't. SmallVector Alignments; - + /// InvalidAlignmentElem - This member is a signal that a requested alignment /// type and bit width were not found in the SmallVector. static const TargetAlignElem InvalidAlignmentElem; @@ -112,30 +112,19 @@ return &align != &InvalidAlignmentElem; } - /// Initialise a TargetData object with default values, ensure that the - /// target data pass is registered. - void init(); - public: /// Default ctor. /// /// @note This has to exist, because this is a pass, but it should never be /// used. TargetData(); - + /// Constructs a TargetData from a specification string. See init(). explicit TargetData(StringRef TargetDescription) : ImmutablePass(ID) { - std::string errMsg = parseSpecifier(TargetDescription, this); - assert(errMsg == "" && "Invalid target data layout string."); - (void)errMsg; + init(TargetDescription); } - /// Parses a target data specification string. Returns an error message - /// if the string is malformed, or the empty string on success. Optionally - /// initialises a TargetData object if passed a non-null pointer. - static std::string parseSpecifier(StringRef TargetDescription, TargetData* td = 0); - /// Initialize target data from properties stored in the module. explicit TargetData(const Module *M); @@ -152,6 +141,9 @@ ~TargetData(); // Not virtual, do not subclass this class + //! Parse a target data layout string and initialize TargetData alignments. + void init(StringRef TargetDescription); + /// Target endianness... bool isLittleEndian() const { return LittleEndian; } bool isBigEndian() const { return !LittleEndian; } @@ -160,7 +152,7 @@ /// TargetData. This representation is in the same format accepted by the /// string constructor above. std::string getStringRepresentation() const; - + /// isLegalInteger - This function returns true if the specified type is /// known to be a native integer type supported by the CPU. For example, /// i64 is not native on most 32-bit CPUs and i37 is not native on any known @@ -174,7 +166,7 @@ return true; return false; } - + bool isIllegalInteger(unsigned Width) const { return !isLegalInteger(Width); } @@ -259,11 +251,11 @@ /// getABITypeAlignment - Return the minimum ABI-required alignment for the /// specified type. unsigned getABITypeAlignment(Type *Ty) const; - + /// getABIIntegerTypeAlignment - Return the minimum ABI-required alignment for /// an integer type of the specified bitwidth. unsigned getABIIntegerTypeAlignment(unsigned BitWidth) const; - + /// getCallFrameTypeAlignment - Return the minimum ABI-required alignment /// for the specified type when it is part of a call frame. @@ -313,7 +305,7 @@ assert((Alignment & (Alignment-1)) == 0 && "Alignment must be power of 2!"); return (Val + (Alignment-1)) & ~UIntTy(Alignment-1); } - + static char ID; // Pass identification, replacement for typeid }; Modified: llvm/trunk/lib/AsmParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/CMakeLists.txt?rev=142323&r1=142322&r2=142323&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/CMakeLists.txt (original) +++ llvm/trunk/lib/AsmParser/CMakeLists.txt Mon Oct 17 19:23:49 2011 @@ -8,5 +8,4 @@ add_llvm_library_dependencies(LLVMAsmParser LLVMCore LLVMSupport - LLVMTarget ) Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=142323&r1=142322&r2=142323&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Mon Oct 17 19:23:49 2011 @@ -24,7 +24,6 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetData.h" using namespace llvm; static std::string getTypeString(Type *T) { @@ -261,14 +260,9 @@ return false; case lltok::kw_datalayout: Lex.Lex(); - LocTy SpecifierLoc = Lex.getLoc(); if (ParseToken(lltok::equal, "expected '=' after target datalayout") || ParseStringConstant(Str)) return true; - std::string errMsg = TargetData::parseSpecifier(Str); - if (errMsg != "") { - return Error(SpecifierLoc, errMsg); - } M->setDataLayout(Str); return false; } Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=142323&r1=142322&r2=142323&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Mon Oct 17 19:23:49 2011 @@ -125,15 +125,15 @@ //===----------------------------------------------------------------------===// /// getInt - Get an integer ignoring errors. -static int getInt(StringRef R) { - int Result = 0; +static unsigned getInt(StringRef R) { + unsigned Result = 0; R.getAsInteger(10, Result); return Result; } -void TargetData::init() { +void TargetData::init(StringRef Desc) { initializeTargetDataPass(*PassRegistry::getPassRegistry()); - + LayoutMap = 0; LittleEndian = false; PointerMemSize = 8; @@ -152,12 +152,6 @@ setAlignment(VECTOR_ALIGN, 8, 8, 64); // v2i32, v1i64, ... setAlignment(VECTOR_ALIGN, 16, 16, 128); // v16i8, v8i16, v4i32, ... setAlignment(AGGREGATE_ALIGN, 0, 8, 0); // struct -} - -std::string TargetData::parseSpecifier(StringRef Desc, TargetData *td) { - - if (td) - td->init(); while (!Desc.empty()) { std::pair Split = Desc.split('-'); @@ -175,54 +169,28 @@ switch (Specifier[0]) { case 'E': - if (td) - td->LittleEndian = false; + LittleEndian = false; break; case 'e': - if (td) - td->LittleEndian = true; + LittleEndian = true; break; - case 'p': { - // Pointer size. + case 'p': Split = Token.split(':'); - int PointerMemSizeBits = getInt(Split.first); - if (PointerMemSizeBits < 0 || PointerMemSizeBits % 8 != 0) - return "invalid pointer size, must be a positive 8-bit multiple"; - if (td) - td->PointerMemSize = PointerMemSizeBits / 8; - - // Pointer ABI alignment. + PointerMemSize = getInt(Split.first) / 8; Split = Split.second.split(':'); - int PointerABIAlignBits = getInt(Split.first); - if (PointerABIAlignBits < 0 || PointerABIAlignBits % 8 != 0) { - return "invalid pointer ABI alignment, " - "must be a positive 8-bit multiple"; - } - if (td) - td->PointerABIAlign = PointerABIAlignBits / 8; - - // Pointer preferred alignment. + PointerABIAlign = getInt(Split.first) / 8; Split = Split.second.split(':'); - int PointerPrefAlignBits = getInt(Split.first); - if (PointerPrefAlignBits < 0 || PointerPrefAlignBits % 8 != 0) { - return "invalid pointer preferred alignment, " - "must be a positive 8-bit multiple"; - } - if (td) { - td->PointerPrefAlign = PointerPrefAlignBits / 8; - if (td->PointerPrefAlign == 0) - td->PointerPrefAlign = td->PointerABIAlign; - } + PointerPrefAlign = getInt(Split.first) / 8; + if (PointerPrefAlign == 0) + PointerPrefAlign = PointerABIAlign; break; - } case 'i': case 'v': case 'f': case 'a': case 's': { AlignTypeEnum AlignType; - char field = Specifier[0]; - switch (field) { + switch (Specifier[0]) { default: case 'i': AlignType = INTEGER_ALIGN; break; case 'v': AlignType = VECTOR_ALIGN; break; @@ -230,66 +198,37 @@ case 'a': AlignType = AGGREGATE_ALIGN; break; case 's': AlignType = STACK_ALIGN; break; } - int Size = getInt(Specifier.substr(1)); - if (Size < 0) { - return std::string("invalid ") + field + "-size field, " - "must be positive"; - } - + unsigned Size = getInt(Specifier.substr(1)); Split = Token.split(':'); - int ABIAlignBits = getInt(Split.first); - if (ABIAlignBits < 0 || ABIAlignBits % 8 != 0) { - return std::string("invalid ") + field +"-abi-alignment field, " - "must be a positive 8-bit multiple"; - } - unsigned ABIAlign = ABIAlignBits / 8; + unsigned ABIAlign = getInt(Split.first) / 8; Split = Split.second.split(':'); - - int PrefAlignBits = getInt(Split.first); - if (PrefAlignBits < 0 || PrefAlignBits % 8 != 0) { - return std::string("invalid ") + field +"-preferred-alignment field, " - "must be a positive 8-bit multiple"; - } - unsigned PrefAlign = PrefAlignBits / 8; + unsigned PrefAlign = getInt(Split.first) / 8; if (PrefAlign == 0) PrefAlign = ABIAlign; - - if (td) - td->setAlignment(AlignType, ABIAlign, PrefAlign, Size); + setAlignment(AlignType, ABIAlign, PrefAlign, Size); break; } case 'n': // Native integer types. Specifier = Specifier.substr(1); do { - int Width = getInt(Specifier); - if (Width <= 0) { - return std::string("invalid native integer size \'") + Specifier.str() + - "\', must be a positive integer."; - } - if (td && Width != 0) - td->LegalIntWidths.push_back(Width); + if (unsigned Width = getInt(Specifier)) + LegalIntWidths.push_back(Width); Split = Token.split(':'); Specifier = Split.first; Token = Split.second; } while (!Specifier.empty() || !Token.empty()); break; - case 'S': { // Stack natural alignment. - int StackNaturalAlignBits = getInt(Specifier.substr(1)); - if (StackNaturalAlignBits < 0 || StackNaturalAlignBits % 8 != 0) { - return "invalid natural stack alignment (S-field), " - "must be a positive 8-bit multiple"; - } - if (td) - td->StackNaturalAlign = StackNaturalAlignBits / 8; + case 'S': // Stack natural alignment. + StackNaturalAlign = getInt(Specifier.substr(1)); + StackNaturalAlign /= 8; + // FIXME: Should we really be truncating these alingments and + // sizes silently? break; - } default: break; } } - - return ""; } /// Default ctor. @@ -303,9 +242,7 @@ TargetData::TargetData(const Module *M) : ImmutablePass(ID) { - std::string errMsg = parseSpecifier(M->getDataLayout(), this); - assert(errMsg == "" && "Module M has malformed target data layout string."); - (void)errMsg; + init(M->getDataLayout()); } void From cdavis at mymail.mines.edu Mon Oct 17 19:37:19 2011 From: cdavis at mymail.mines.edu (Charles Davis) Date: Mon, 17 Oct 2011 18:37:19 -0600 Subject: [llvm-commits] [PATCH] Fix compiling source files in subdirectories with autoconf Message-ID: <8963C7C2-E230-4BB3-B0EC-F0ABB529E95A@mymail.mines.edu> Hi, This patch fixes an issue with source files located in subdirectories (relative to the Makefile referencing them). The build system was not creating those directories in the build tree, which caused compiling the sources to fail. This patch fixes that. I encountered this getting the LLDB Host library and LLDB debug server to compile from Makefiles. OK to commit? Chip -------------- next part -------------- A non-text attachment was scrubbed... Name: source-subdir-fix.patch Type: application/octet-stream Size: 12984 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/6633d539/attachment.obj -------------- next part -------------- From lhames at apple.com Mon Oct 17 19:26:57 2011 From: lhames at apple.com (Lang Hames) Date: Mon, 17 Oct 2011 17:26:57 -0700 Subject: [llvm-commits] [llvm] r142288 - in /llvm/trunk: include/llvm/Target/TargetData.h lib/AsmParser/LLParser.cpp lib/Target/TargetData.cpp In-Reply-To: References: <20111017220535.2A343312800A@llvm.org> <4E9CAB90.3010102@gmail.com> <4E9CB76F.4060709@gmail.com> Message-ID: Hey Chandler, Backed out in r142323. Will recommit when I find a home for this parser that doesn't require this dependency. Cheers, Lang. On Oct 17, 2011, at 4:30 PM, Chandler Carruth wrote: > On Mon, Oct 17, 2011 at 4:17 PM, Rafael ?vila de Esp?ndola wrote: > On 10/17/2011 06:26 PM, Rafael ?vila de Esp?ndola wrote: > looks like this broke the build: > > > Linking CXX executable ../../bin/llvm-as > ../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function > llvm::LLParser::ParseTargetDefinition(): error: undefined reference to > 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)' > clang-3: error: linker command failed with exit code 1 (use -v to see > invocation) > > It looks like all that was missing was the attached patch. > > Chandler, is it OK with the original patch? > > As discussed in IRC, yes this is sufficient for the link command to succeed, but it feels completely wrong for the LL parsing to depend on the target library. I think this is a more fundamental layering issue. Currently AsmParser only depends on Support and Core, and that seems reasonable. I don't think something not in the VMCore should be required in order to parse the IR. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/74848a69/attachment.html From xuzhongxing at foxmail.com Mon Oct 17 20:48:02 2011 From: xuzhongxing at foxmail.com (=?ISO-8859-1?B?WHUgWmhvbmd4aW5n?=) Date: Tue, 18 Oct 2011 09:48:02 +0800 Subject: [llvm-commits] [llvm] r142315 - in /llvm/trunk:include/llvm/Object/COFF.h lib/Object/COFFObjectFile.cpp Message-ID: @@ -553,13 +544,32 @@ error_code COFFObjectFile::getSymbol(uint32_t index, const coff_symbol *&Result) const { - if (index > 0 && index < Header->NumberOfSymbols) + if (index >= 0 && index < Header->NumberOfSymbols) Hi Michael, index is unsigned. It's always >= 0. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111018/bdb1790d/attachment.html From eli.friedman at gmail.com Mon Oct 17 21:48:07 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 17 Oct 2011 19:48:07 -0700 Subject: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ In-Reply-To: <20111016203133.CC4E13128018@llvm.org> References: <20111016203133.CC4E13128018@llvm.org> Message-ID: On Sun, Oct 16, 2011 at 1:31 PM, Nadav Rotem wrote: > Author: nadav > Date: Sun Oct 16 15:31:33 2011 > New Revision: 142152 > > URL: http://llvm.org/viewvc/llvm-project?rev=142152&view=rev > Log: > Enable element promotion type legalization by deafault. > Changed tests which assumed that vectors are legalized by widening them. This change appears to be causing a miscompile for http://llvm.org/viewvc/llvm-project/clang-tests/trunk/gcc-4_2-testsuite/src/gcc.c-torture/execute/pr23135.c?view=markup . Please take a look. -Eli > > Modified: > ? ?llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp > ? ?llvm/trunk/test/CodeGen/ARM/vrev.ll > ? ?llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll > ? ?llvm/trunk/test/CodeGen/CellSPU/shuffles.ll > ? ?llvm/trunk/test/CodeGen/CellSPU/v2i32.ll > ? ?llvm/trunk/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll > ? ?llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll > ? ?llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll > ? ?llvm/trunk/test/CodeGen/X86/mmx-pinsrw.ll > ? ?llvm/trunk/test/CodeGen/X86/mmx-vzmovl-2.ll > ? ?llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll > ? ?llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll > ? ?llvm/trunk/test/CodeGen/X86/vsplit-and.ll > ? ?llvm/trunk/test/CodeGen/X86/widen_arith-1.ll > ? ?llvm/trunk/test/CodeGen/X86/widen_arith-2.ll > ? ?llvm/trunk/test/CodeGen/X86/widen_arith-3.ll > ? ?llvm/trunk/test/CodeGen/X86/widen_cast-1.ll > ? ?llvm/trunk/test/CodeGen/X86/widen_cast-4.ll > ? ?llvm/trunk/test/CodeGen/X86/widen_conv-1.ll > ? ?llvm/trunk/test/CodeGen/X86/widen_conv-4.ll > ? ?llvm/trunk/test/CodeGen/X86/widen_load-0.ll > ? ?llvm/trunk/test/CodeGen/X86/widen_load-2.ll > ? ?llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll > ? ?llvm/trunk/test/CodeGen/X86/x86-shifts.ll > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sun Oct 16 15:31:33 2011 > @@ -36,7 +36,7 @@ > ?/// - the promotion of vector elements. This feature is disabled by default > ?/// and only enabled using this flag. > ?static cl::opt > -AllowPromoteIntElem("promote-elements", cl::Hidden, > +AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true), > ? cl::desc("Allow promotion of integer vector element types")); > > ?namespace llvm { > > Modified: llvm/trunk/test/CodeGen/ARM/vrev.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/vrev.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/vrev.ll Sun Oct 16 15:31:33 2011 > @@ -150,9 +150,6 @@ > > ?; vrev <4 x i16> should use VREV32 and not VREV64 > ?define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { > -; CHECK: test_vrev64: > -; CHECK: vext.16 > -; CHECK: vrev32.16 > ?entry: > ? %0 = bitcast <4 x i16>* %source to <8 x i16>* > ? %tmp2 = load <8 x i16>* %0, align 4 > > Modified: llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll (original) > +++ llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll Sun Oct 16 15:31:33 2011 > @@ -1,12 +1,12 @@ > ?; RUN: llc < %s -march=cellspu > %t1.s > ?; RUN: grep {shlh ? ? ?} ?%t1.s | count 10 > ?; RUN: grep {shlhi ? ? } ?%t1.s | count 3 > -; RUN: grep {shl ? ? ? } ?%t1.s | count 11 > +; RUN: grep {shl ? ? ? } ?%t1.s | count 10 > ?; RUN: grep {shli ? ? ?} ?%t1.s | count 3 > ?; RUN: grep {xshw ? ? ?} ?%t1.s | count 5 > -; RUN: grep {and ? ? ? } ?%t1.s | count 14 > -; RUN: grep {andi ? ? ?} ?%t1.s | count 2 > -; RUN: grep {rotmi ? ? } ?%t1.s | count 2 > +; RUN: grep {and ? ? ? } ?%t1.s | count 15 > +; RUN: grep {andi ? ? ?} ?%t1.s | count 4 > +; RUN: grep {rotmi ? ? } ?%t1.s | count 4 > ?; RUN: grep {rotqmbyi ?} ?%t1.s | count 1 > ?; RUN: grep {rotqmbii ?} ?%t1.s | count 2 > ?; RUN: grep {rotqmby ? } ?%t1.s | count 1 > > Modified: llvm/trunk/test/CodeGen/CellSPU/shuffles.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/shuffles.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/CellSPU/shuffles.ll (original) > +++ llvm/trunk/test/CodeGen/CellSPU/shuffles.ll Sun Oct 16 15:31:33 2011 > @@ -1,12 +1,14 @@ > ?; RUN: llc -O1 ?--march=cellspu < %s | FileCheck %s > > +;CHECK: shuffle > ?define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) { > ? ; CHECK: cwd {{\$.}}, 0($sp) > ? ; CHECK: shufb {{\$., \$4, \$3, \$.}} > ? %val= shufflevector <4 x float> %param1, <4 x float> %param2, <4 x i32> > ? ret <4 x float> %val > ?} > - > + > +;CHECK: splat > ?define <4 x float> @splat(float %param1) { > ? ; CHECK: lqa > ? ; CHECK: shufb $3 > @@ -16,6 +18,7 @@ > ? ret <4 x float> %val > ?} > > +;CHECK: test_insert > ?define void @test_insert( <2 x float>* %ptr, float %val1, float %val2 ) { > ? %sl2_17_tmp1 = insertelement <2 x float> zeroinitializer, float %val1, i32 0 > ?;CHECK: ? ? ? ?lqa ? ? $6, > @@ -31,6 +34,7 @@ > ? ret void > ?} > > +;CHECK: test_insert_1 > ?define <4 x float> ?@test_insert_1(<4 x float> %vparam, float %eltparam) { > ?;CHECK: cwd ? ? $5, 4($sp) > ?;CHECK: shufb ? $3, $4, $3, $5 > @@ -39,6 +43,7 @@ > ? ret <4 x float> %rv > ?} > > +;CHECK: test_v2i32 > ?define <2 x i32> @test_v2i32(<4 x i32>%vec) > ?{ > ?;CHECK: rotqbyi $3, $3, 4 > @@ -49,17 +54,14 @@ > > ?define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec) > ?{ > -;CHECK: rotqbyi $3, $3, 8 > -;CHECK: bi $lr > ? %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, > ? ? ? ? <4 x i32> > ? ret <4 x i32> %rv > ?} > > +;CHECK: test_v4i32_rot4 > ?define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec) > ?{ > -;CHECK: rotqbyi $3, $3, 4 > -;CHECK: bi $lr > ? %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, > ? ? ? ? <4 x i32> > ? ret <4 x i32> %rv > > Modified: llvm/trunk/test/CodeGen/CellSPU/v2i32.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/v2i32.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/CellSPU/v2i32.ll (original) > +++ llvm/trunk/test/CodeGen/CellSPU/v2i32.ll Sun Oct 16 15:31:33 2011 > @@ -9,7 +9,8 @@ > > ?define %vec @test_add(%vec %param) > ?{ > -;CHECK: a {{\$.}}, $3, $3 > +;CHECK: shufb > +;CHECK: addx > ? %1 = add %vec %param, %param > ?;CHECK: bi $lr > ? ret %vec %1 > @@ -17,21 +18,14 @@ > > ?define %vec @test_sub(%vec %param) > ?{ > -;CHECK: sf {{\$.}}, $4, $3 > ? %1 = sub %vec %param, > - > ?;CHECK: bi $lr > ? ret %vec %1 > ?} > > ?define %vec @test_mul(%vec %param) > ?{ > -;CHECK: mpyu > -;CHECK: mpyh > -;CHECK: a {{\$., \$., \$.}} > -;CHECK: a {{\$., \$., \$.}} > ? %1 = mul %vec %param, %param > - > ?;CHECK: bi $lr > ? ret %vec %1 > ?} > @@ -56,22 +50,12 @@ > > ?define void @test_store( %vec %val, %vec* %ptr) > ?{ > -;CHECK: stqd $3, 0(${{.}}) > -;CHECK: bi $lr > ? store %vec %val, %vec* %ptr > ? ret void > ?} > > -;Alignment of <2 x i32> is not *directly* defined in the ABI > -;It probably is safe to interpret it as an array, thus having 8 byte > -;alignment (according to ABI). This tests that the size of > -;[2 x <2 x i32>] is 16 bytes, i.e. there is no padding between the > -;two arrays > ?define <2 x i32>* @test_alignment( [2 x <2 x i32>]* %ptr) > ?{ > -; CHECK-NOT: ? ai ? ? ?$3, $3, 16 > -; CHECK: ? ? ? ai ? ? ?$3, $3, 8 > -; CHECK: ? ? ? bi ? ? ?$lr > ? ?%rv = getelementptr [2 x <2 x i32>]* %ptr, i32 0, i32 1 > ? ?ret <2 x i32>* %rv > ?} > > Modified: llvm/trunk/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll Sun Oct 16 15:31:33 2011 > @@ -1,5 +1,5 @@ > -; RUN: llc < %s -march=x86 -mattr=+sse2 -mattr=+mmx | grep unpcklpd > -; RUN: llc < %s -march=x86 -mattr=+sse2 -mattr=+mmx | grep unpckhpd > +; RUN: llc < %s -march=x86 -mattr=+sse2 -mattr=+mmx | not grep unpcklpd > +; RUN: llc < %s -march=x86 -mattr=+sse2 -mattr=+mmx | not grep unpckhpd > ?; RUN: llc < %s -march=x86 -mattr=+sse2 | grep cvttpd2pi | count 1 > ?; RUN: llc < %s -march=x86 -mattr=+sse2 | grep cvtpi2pd | count 1 > ?; originally from PR2687, but things don't work that way any more. > > Modified: llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll Sun Oct 16 15:31:33 2011 > @@ -1,6 +1,6 @@ > ?; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 > %t1 > ?; RUN: grep movzwl %t1 | count 2 > -; RUN: grep movzbl %t1 | count 2 > +; RUN: grep movzbl %t1 | count 1 > ?; RUN: grep movd %t1 | count 4 > > ?define <4 x i16> @a(i32* %x1) nounwind { > > Modified: llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll Sun Oct 16 15:31:33 2011 > @@ -1,32 +1,35 @@ > ?; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s > ?; There are no MMX operations here, so we use XMM or i64. > > +; CHECK: ti8 > ?define void @ti8(double %a, double %b) nounwind { > ?entry: > ? ? ? ? %tmp1 = bitcast double %a to <8 x i8> > ? ? ? ? %tmp2 = bitcast double %b to <8 x i8> > ? ? ? ? %tmp3 = add <8 x i8> %tmp1, %tmp2 > -; CHECK: ?paddb %xmm1, %xmm0 > +; CHECK: ?paddw > ? ? ? ? store <8 x i8> %tmp3, <8 x i8>* null > ? ? ? ? ret void > ?} > > +; CHECK: ti16 > ?define void @ti16(double %a, double %b) nounwind { > ?entry: > ? ? ? ? %tmp1 = bitcast double %a to <4 x i16> > ? ? ? ? %tmp2 = bitcast double %b to <4 x i16> > ? ? ? ? %tmp3 = add <4 x i16> %tmp1, %tmp2 > -; CHECK: ?paddw %xmm1, %xmm0 > +; CHECK: ?paddd > ? ? ? ? store <4 x i16> %tmp3, <4 x i16>* null > ? ? ? ? ret void > ?} > > +; CHECK: ti32 > ?define void @ti32(double %a, double %b) nounwind { > ?entry: > ? ? ? ? %tmp1 = bitcast double %a to <2 x i32> > ? ? ? ? %tmp2 = bitcast double %b to <2 x i32> > ? ? ? ? %tmp3 = add <2 x i32> %tmp1, %tmp2 > -; CHECK: ?paddd %xmm1, %xmm0 > +; CHECK: ?paddq > ? ? ? ? store <2 x i32> %tmp3, <2 x i32>* null > ? ? ? ? ret void > ?} > @@ -55,6 +58,7 @@ > ? ? ? ? ret void > ?} > > +; CHECK: ti16a > ?define void @ti16a(double %a, double %b) nounwind { > ?entry: > ? ? ? ? %tmp1 = bitcast double %a to x86_mmx > @@ -66,6 +70,7 @@ > ? ? ? ? ret void > ?} > > +; CHECK: ti32a > ?define void @ti32a(double %a, double %b) nounwind { > ?entry: > ? ? ? ? %tmp1 = bitcast double %a to x86_mmx > @@ -77,6 +82,7 @@ > ? ? ? ? ret void > ?} > > +; CHECK: ti64a > ?define void @ti64a(double %a, double %b) nounwind { > ?entry: > ? ? ? ? %tmp1 = bitcast double %a to x86_mmx > > Modified: llvm/trunk/test/CodeGen/X86/mmx-pinsrw.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-pinsrw.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/mmx-pinsrw.ll (original) > +++ llvm/trunk/test/CodeGen/X86/mmx-pinsrw.ll Sun Oct 16 15:31:33 2011 > @@ -1,4 +1,4 @@ > -; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | grep pinsrw | count 1 > +; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | grep pinsr > ?; PR2562 > > ?external global i16 ? ? ? ? ? ?; :0 [#uses=1] > > Modified: llvm/trunk/test/CodeGen/X86/mmx-vzmovl-2.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-vzmovl-2.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/mmx-vzmovl-2.ll (original) > +++ llvm/trunk/test/CodeGen/X86/mmx-vzmovl-2.ll Sun Oct 16 15:31:33 2011 > @@ -1,6 +1,5 @@ > -; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | grep pxor > -; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | grep punpckldq > - > +; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | grep pxor | count 1 > +; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | grep punpcklqdq | count 1 > ? ? ? ?%struct.vS1024 = type { [8 x <4 x i32>] } > ? ? ? ?%struct.vS512 = type { [4 x <4 x i32>] } > > > Modified: llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll (original) > +++ llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll Sun Oct 16 15:31:33 2011 > @@ -3,9 +3,10 @@ > ?; Verify when widening a divide/remainder operation, we only generate a > ?; divide/rem per element since divide/remainder can trap. > > +; CHECK: vectorDiv > ?define void @vectorDiv (<2 x i32> addrspace(1)* %nsource, <2 x i32> addrspace(1)* %dsource, <2 x i32> addrspace(1)* %qdest) nounwind { > -; CHECK: idivl > -; CHECK: idivl > +; CHECK: idivq > +; CHECK: idivq > ?; CHECK-NOT: idivl > ?; CHECK: ret > ?entry: > @@ -32,6 +33,7 @@ > ? ret void > ?} > > +; CHECK: test_char_div > ?define <3 x i8> @test_char_div(<3 x i8> %num, <3 x i8> %div) { > ?; CHECK: idivb > ?; CHECK: idivb > @@ -42,6 +44,7 @@ > ? ret <3 x i8> ?%div.r > ?} > > +; CHECK: test_char_div > ?define <3 x i8> @test_uchar_div(<3 x i8> %num, <3 x i8> %div) { > ?; CHECK: divb > ?; CHECK: divb > @@ -52,6 +55,7 @@ > ? ret <3 x i8> ?%div.r > ?} > > +; CHECK: test_short_div > ?define <5 x i16> @test_short_div(<5 x i16> %num, <5 x i16> %div) { > ?; CHECK: idivw > ?; CHECK: idivw > @@ -64,17 +68,19 @@ > ? ret <5 x i16> ?%div.r > ?} > > +; CHECK: test_ushort_div > ?define <4 x i16> @test_ushort_div(<4 x i16> %num, <4 x i16> %div) { > -; CHECK: divw > -; CHECK: divw > -; CHECK: divw > -; CHECK: divw > -; CHECK-NOT: divw > +; CHECK: divl > +; CHECK: divl > +; CHECK: divl > +; CHECK: divl > +; CHECK-NOT: divl > ?; CHECK: ret > ? %div.r = udiv <4 x i16> %num, %div > ? ret <4 x i16> ?%div.r > ?} > > +; CHECK: test_uint_div > ?define <3 x i32> @test_uint_div(<3 x i32> %num, <3 x i32> %div) { > ?; CHECK: divl > ?; CHECK: divl > @@ -85,6 +91,7 @@ > ? ret <3 x i32> ?%div.r > ?} > > +; CHECK: test_long_div > ?define <3 x i64> @test_long_div(<3 x i64> %num, <3 x i64> %div) { > ?; CHECK: idivq > ?; CHECK: idivq > @@ -95,6 +102,7 @@ > ? ret <3 x i64> ?%div.r > ?} > > +; CHECK: test_ulong_div > ?define <3 x i64> @test_ulong_div(<3 x i64> %num, <3 x i64> %div) { > ?; CHECK: divq > ?; CHECK: divq > @@ -105,18 +113,19 @@ > ? ret <3 x i64> ?%div.r > ?} > > - > +; CHECK: test_char_rem > ?define <4 x i8> @test_char_rem(<4 x i8> %num, <4 x i8> %rem) { > -; CHECK: idivb > -; CHECK: idivb > -; CHECK: idivb > -; CHECK: idivb > -; CHECK-NOT: idivb > +; CHECK: idivl > +; CHECK: idivl > +; CHECK: idivl > +; CHECK: idivl > +; CHECK-NOT: idivl > ?; CHECK: ret > ? %rem.r = srem <4 x i8> %num, %rem > ? ret <4 x i8> ?%rem.r > ?} > > +; CHECK: test_short_rem > ?define <5 x i16> @test_short_rem(<5 x i16> %num, <5 x i16> %rem) { > ?; CHECK: idivw > ?; CHECK: idivw > @@ -129,6 +138,7 @@ > ? ret <5 x i16> ?%rem.r > ?} > > +; CHECK: test_uint_rem > ?define <4 x i32> @test_uint_rem(<4 x i32> %num, <4 x i32> %rem) { > ?; CHECK: idivl > ?; CHECK: idivl > @@ -141,6 +151,7 @@ > ?} > > > +; CHECK: test_ulong_rem > ?define <5 x i64> @test_ulong_rem(<5 x i64> %num, <5 x i64> %rem) { > ?; CHECK: divq > ?; CHECK: divq > @@ -153,6 +164,7 @@ > ? ret <5 x i64> ?%rem.r > ?} > > +; CHECK: test_int_div > ?define void @test_int_div(<3 x i32>* %dest, <3 x i32>* %old, i32 %n) { > ?; CHECK: idivl > ?; CHECK: idivl > > Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll (original) > +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll Sun Oct 16 15:31:33 2011 > @@ -26,10 +26,10 @@ > > ?define void @t02(<8 x i32>* %source, <2 x i32>* %dest) nounwind noinline { > ?entry: > -; CHECK: movaps ?32({{%rdi|%rcx}}), %xmm0 > -; CHECK-NEXT: movaps ?48({{%rdi|%rcx}}), %xmm1 > -; CHECK-NEXT: movss ? %xmm1, %xmm0 > -; CHECK-NEXT: movq ? ?%xmm0, ({{%rsi|%rdx}}) > +; CHECK: movl ?36({{%rdi|%rcx}}) > +; CHECK-NEXT: movl ?48({{%rdi|%rcx}}) > +; CHECK: punpcklqdq > +; CHECK: movq ? ?%xmm0, ({{%rsi|%rdx}}) > ? %0 = bitcast <8 x i32>* %source to <4 x i32>* > ? %arrayidx = getelementptr inbounds <4 x i32>* %0, i64 3 > ? %tmp2 = load <4 x i32>* %arrayidx, align 16 > > Modified: llvm/trunk/test/CodeGen/X86/vsplit-and.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vsplit-and.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/vsplit-and.ll (original) > +++ llvm/trunk/test/CodeGen/X86/vsplit-and.ll Sun Oct 16 15:31:33 2011 > @@ -2,7 +2,7 @@ > > > ?define void @t(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind readonly { > -; CHECK: andb > +; CHECK: pandn > ? %cmp1 = icmp ne <2 x i64> %src1, zeroinitializer > ? %cmp2 = icmp ne <2 x i64> %src2, zeroinitializer > ? %t1 = and <2 x i1> %cmp1, %cmp2 > @@ -12,7 +12,7 @@ > ?} > > ?define void @t2(<3 x i64>* %dst, <3 x i64> %src1, <3 x i64> %src2) nounwind readonly { > -; CHECK: andb > +; CHECK-NOT: pandn > ? %cmp1 = icmp ne <3 x i64> %src1, zeroinitializer > ? %cmp2 = icmp ne <3 x i64> %src2, zeroinitializer > ? %t1 = and <3 x i1> %cmp1, %cmp2 > > Modified: llvm/trunk/test/CodeGen/X86/widen_arith-1.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-1.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_arith-1.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_arith-1.ll Sun Oct 16 15:31:33 2011 > @@ -1,12 +1,10 @@ > ?; RUN: llc < %s -march=x86 -mattr=+sse42 | ?FileCheck %s > > -; Widen a v3i8 to v16i8 to use a vector add > - > ?define void @update(<3 x i8>* %dst, <3 x i8>* %src, i32 %n) nounwind { > ?entry: > ?; CHECK-NOT: pextrw > -; CHECK: paddb > -; CHECK: pextrb > +; CHECK: add > + > ? ? ? ?%dst.addr = alloca <3 x i8>* ? ? ? ? ? ?; <<3 x i8>**> [#uses=2] > ? ? ? ?%src.addr = alloca <3 x i8>* ? ? ? ? ? ?; <<3 x i8>**> [#uses=2] > ? ? ? ?%n.addr = alloca i32 ? ? ? ? ? ?; [#uses=2] > > Modified: llvm/trunk/test/CodeGen/X86/widen_arith-2.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-2.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_arith-2.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_arith-2.ll Sun Oct 16 15:31:33 2011 > @@ -1,5 +1,5 @@ > ?; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s > -; CHECK: paddb > +; CHECK: padd > ?; CHECK: pand > > ?; widen v8i8 to v16i8 (checks even power of 2 widening with add & and) > > Modified: llvm/trunk/test/CodeGen/X86/widen_arith-3.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-3.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_arith-3.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_arith-3.ll Sun Oct 16 15:31:33 2011 > @@ -1,7 +1,8 @@ > ?; RUN: llc < %s -march=x86 -mattr=+sse42 -post-RA-scheduler=true | FileCheck %s > -; CHECK: paddw > -; CHECK: pextrw > -; CHECK: movd > +; CHECK: incw > +; CHECK: incl > +; CHECK: incl > +; CHECK: addl > > ?; Widen a v3i16 to v8i16 to do a vector add > > > Modified: llvm/trunk/test/CodeGen/X86/widen_cast-1.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_cast-1.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_cast-1.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_cast-1.ll Sun Oct 16 15:31:33 2011 > @@ -1,5 +1,5 @@ > ?; RUN: llc -march=x86 -mattr=+sse42 < %s | FileCheck %s > -; CHECK: paddw > +; CHECK: paddd > ?; CHECK: pextrd > ?; CHECK: movd > > > Modified: llvm/trunk/test/CodeGen/X86/widen_cast-4.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_cast-4.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_cast-4.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_cast-4.ll Sun Oct 16 15:31:33 2011 > @@ -1,16 +1,6 @@ > ?; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > - > -; v8i8 that is widen to v16i8 then split > -; FIXME: This is widen to v16i8 and split to 16 and we then rebuild the vector. > -; Unfortunately, we don't split the store so we don't get the code we want. > +; CHECK: psraw > +; CHECK: psraw > > ?define void @update(i64* %dst_i, i64* %src_i, i32 %n) nounwind { > ?entry: > > Modified: llvm/trunk/test/CodeGen/X86/widen_conv-1.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_conv-1.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_conv-1.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_conv-1.ll Sun Oct 16 15:31:33 2011 > @@ -1,6 +1,5 @@ > ?; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s > -; CHECK: pshufd > -; CHECK: paddd > +; CHECK: paddq > > ?; truncate v2i64 to v2i32 > > > Modified: llvm/trunk/test/CodeGen/X86/widen_conv-4.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_conv-4.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_conv-4.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_conv-4.ll Sun Oct 16 15:31:33 2011 > @@ -1,5 +1,5 @@ > ?; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s > -; CHECK: cvtsi2ss > +; CHECK-NOT: cvtsi2ss > > ?; unsigned to float v7i16 to v7f32 > > > Modified: llvm/trunk/test/CodeGen/X86/widen_load-0.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_load-0.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_load-0.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_load-0.ll Sun Oct 16 15:31:33 2011 > @@ -4,15 +4,15 @@ > > ?; Both loads should happen before either store. > > -; CHECK: movl ?(%rdi), %[[R1:...]] > -; CHECK: movl ?(%rsi), %[[R2:...]] > -; CHECK: movl ?%[[R2]], (%rdi) > -; CHECK: movl ?%[[R1]], (%rsi) > +; CHECK: movd ?(%rsi), {{.*}} > +; CHECK: movd ?(%rdi), {{.*}} > +; CHECK: movd ?{{.*}}, (%rdi) > +; CHECK: movd ?{{.*}}, (%rsi) > > -; WIN64: movl ?(%rcx), %[[R1:...]] > -; WIN64: movl ?(%rdx), %[[R2:...]] > -; WIN64: movl ?%[[R2]], (%rcx) > -; WIN64: movl ?%[[R1]], (%rdx) > +; WIN64: movd ?(%rdx), {{.*}} > +; WIN64: movd ?(%rcx), {{.*}} > +; WIN64: movd ?{{.*}}, (%rcx) > +; WIN64: movd ?{{.*}}, (%rdx) > > ?define void @short2_int_swap(<2 x i16>* nocapture %b, i32* nocapture %c) nounwind { > ?entry: > > Modified: llvm/trunk/test/CodeGen/X86/widen_load-2.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_load-2.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_load-2.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_load-2.ll Sun Oct 16 15:31:33 2011 > @@ -4,6 +4,7 @@ > ?; > > ?%i32vec3 = type <3 x i32> > +; CHECK: add3i32 > ?define void @add3i32(%i32vec3* ?sret %ret, %i32vec3* %ap, %i32vec3* %bp) ?{ > ?; CHECK: movdqa > ?; CHECK: paddd > @@ -16,6 +17,7 @@ > ? ? ? ?ret void > ?} > > +; CHECK: add3i32_2 > ?define void @add3i32_2(%i32vec3* ?sret %ret, %i32vec3* %ap, %i32vec3* %bp) ?{ > ?; CHECK: movq > ?; CHECK: pinsrd > @@ -32,6 +34,7 @@ > ?} > > ?%i32vec7 = type <7 x i32> > +; CHECK: add7i32 > ?define void @add7i32(%i32vec7* ?sret %ret, %i32vec7* %ap, %i32vec7* %bp) ?{ > ?; CHECK: movdqa > ?; CHECK: movdqa > @@ -47,6 +50,7 @@ > ? ? ? ?ret void > ?} > > +; CHECK: add12i32 > ?%i32vec12 = type <12 x i32> > ?define void @add12i32(%i32vec12* ?sret %ret, %i32vec12* %ap, %i32vec12* %bp) ?{ > ?; CHECK: movdqa > @@ -66,12 +70,14 @@ > ?} > > > +; CHECK: add3i16 > ?%i16vec3 = type <3 x i16> > ?define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind { > -; CHECK: movdqa > -; CHECK: paddw > -; CHECK: movd > -; CHECK: pextrw > +; CHECK: add3i16 > +; CHECK: addl > +; CHECK: addl > +; CHECK: addl > +; CHECK: ret > ? ? ? ?%a = load %i16vec3* %ap, align 16 > ? ? ? ?%b = load %i16vec3* %bp, align 16 > ? ? ? ?%x = add %i16vec3 %a, %b > @@ -79,10 +85,11 @@ > ? ? ? ?ret void > ?} > > +; CHECK: add4i16 > ?%i16vec4 = type <4 x i16> > ?define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind { > -; CHECK: movdqa > -; CHECK: paddw > +; CHECK: add4i16 > +; CHECK: paddd > ?; CHECK: movq > ? ? ? ?%a = load %i16vec4* %ap, align 16 > ? ? ? ?%b = load %i16vec4* %bp, align 16 > @@ -91,6 +98,7 @@ > ? ? ? ?ret void > ?} > > +; CHECK: add12i16 > ?%i16vec12 = type <12 x i16> > ?define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind { > ?; CHECK: movdqa > @@ -106,6 +114,7 @@ > ? ? ? ?ret void > ?} > > +; CHECK: add18i16 > ?%i16vec18 = type <18 x i16> > ?define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind { > ?; CHECK: movdqa > @@ -125,12 +134,13 @@ > ?} > > > +; CHECK: add3i8 > ?%i8vec3 = type <3 x i8> > ?define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind { > -; CHECK: movdqa > -; CHECK: paddb > -; CHECK: pextrb > -; CHECK: movb > +; CHECK: addb > +; CHECK: addb > +; CHECK: addb > +; CHECK: ret > ? ? ? ?%a = load %i8vec3* %ap, align 16 > ? ? ? ?%b = load %i8vec3* %bp, align 16 > ? ? ? ?%x = add %i8vec3 %a, %b > @@ -138,6 +148,7 @@ > ? ? ? ?ret void > ?} > > +; CHECK: add31i8: > ?%i8vec31 = type <31 x i8> > ?define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind { > ?; CHECK: movdqa > @@ -147,6 +158,7 @@ > ?; CHECK: movq > ?; CHECK: pextrb > ?; CHECK: pextrw > +; CHECK: ret > ? ? ? ?%a = load %i8vec31* %ap, align 16 > ? ? ? ?%b = load %i8vec31* %bp, align 16 > ? ? ? ?%x = add %i8vec31 %a, %b > @@ -155,9 +167,10 @@ > ?} > > > +; CHECK: rot > ?%i8vec3pack = type { <3 x i8>, i8 } > ?define %i8vec3pack ?@rot() nounwind { > -; CHECK: shrb > +; CHECK: shrl > ?entry: > ? %X = alloca %i8vec3pack, align 4 > ? %rot = alloca %i8vec3pack, align 4 > > Modified: llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll Sun Oct 16 15:31:33 2011 > @@ -50,7 +50,7 @@ > ?; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS > ?define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone { > ?; CHECK: shuf4: > -; CHECK: punpckldq > +; CHECK-NOT: punpckldq > ? %vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> > ? ret <8 x i8> %vshuf > ?} > > Modified: llvm/trunk/test/CodeGen/X86/x86-shifts.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-shifts.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/x86-shifts.ll (original) > +++ llvm/trunk/test/CodeGen/X86/x86-shifts.ll Sun Oct 16 15:31:33 2011 > @@ -124,7 +124,7 @@ > ?define <2 x i32> @shl2_other(<2 x i32> %A) nounwind { > ?entry: > ?; CHECK: shl2_other > -; CHECK-not: ? ? ?psllq > +; CHECK: psllq > ? %B = shl <2 x i32> %A, ?< i32 2, i32 2> > ? %C = shl <2 x i32> %A, ?< i32 9, i32 9> > ? %K = xor <2 x i32> %B, %C > @@ -134,7 +134,7 @@ > ?define <2 x i32> @shr2_other(<2 x i32> %A) nounwind { > ?entry: > ?; CHECK: shr2_other > -; CHECK-NOT: ? ? ?psrlq > +; CHECK: psrlq > ? %B = lshr <2 x i32> %A, ?< i32 8, i32 8> > ? %C = lshr <2 x i32> %A, ?< i32 1, i32 1> > ? %K = xor <2 x i32> %B, %C > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From jabbey at arxan.com Mon Oct 17 22:04:54 2011 From: jabbey at arxan.com (Joe Abbey) Date: Mon, 17 Oct 2011 22:04:54 -0500 Subject: [llvm-commits] Removing additional warnings In-Reply-To: References:

Message-ID: <779C31AF-E36E-4670-A0E4-F8B5565B78DA@arxan.com> Ping? I'd commit it myself as obvious, but I'd need commit access. :-) Thanks! Joe Abbey Software Architect Arxan Technologies, Inc. 1305 Cumberland Ave, Ste 215 West Lafayette, IN 47906 jabbey at arxan.com www.arxan.com On Oct 17, 2011, at 6:56 PM, Joe Abbey wrote: Updated after Bill's Dr. Frankenstein maneuver. Joe Abbey Software Architect Arxan Technologies, Inc. 1305 Cumberland Ave, Ste 215 West Lafayette, IN 47906 jabbey at arxan.com www.arxan.com On Oct 17, 2011, at 5:44 PM, Joe Abbey wrote: This resolves the last couple warnings: MipsISelLowering.cpp:791:12: warning: variable ?dl? set but not used [-Wunused-but-set-variable] ARMISelDAGToDAG.cpp:2319:12: warning: variable ?DL? set but not used [-Wunused-but-set-variable] as well as some warnings when tbl-genning thumb2 Cheers, Joe Abbey Software Architect Arxan Technologies, Inc. 1305 Cumberland Ave, Ste 215 West Lafayette, IN 47906 jabbey at arxan.com www.arxan.com _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/52c41458/attachment.html From eli.friedman at gmail.com Mon Oct 17 22:17:35 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 18 Oct 2011 03:17:35 -0000 Subject: [llvm-commits] [llvm] r142332 - in /llvm/trunk/lib/Target: ARM/ARMISelDAGToDAG.cpp ARM/ARMInstrThumb2.td Mips/MipsISelLowering.cpp Message-ID: <20111018031735.285103524001@llvm.org> Author: efriedma Date: Mon Oct 17 22:17:34 2011 New Revision: 142332 URL: http://llvm.org/viewvc/llvm-project?rev=142332&view=rev Log: Fix misc warnings. Patch by Joe Abbey. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=142332&r1=142331&r2=142332&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Oct 17 22:17:34 2011 @@ -2316,7 +2316,6 @@ SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){ SDValue XORSrc0 = N->getOperand(0); SDValue XORSrc1 = N->getOperand(1); - DebugLoc DL = N->getDebugLoc(); EVT VT = N->getValueType(0); if (DisableARMIntABS) Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=142332&r1=142331&r2=142332&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Oct 17 22:17:34 2011 @@ -1345,6 +1345,7 @@ "$addr.base = $Rn_wb, at earlyclobber $Rn_wb", []> { let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8"; } +} // mayStore = 1, neverHasSideEffects = 1 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb), (ins rGPR:$Rt, addr_offset_none:$Rn, @@ -1399,7 +1400,6 @@ [(set GPRnopc:$Rn_wb, (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>; } -} // mayStore = 1, neverHasSideEffects = 1 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly // only. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=142332&r1=142331&r2=142332&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Oct 17 22:17:34 2011 @@ -788,8 +788,6 @@ MachineBasicBlock * MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { - DebugLoc dl = MI->getDebugLoc(); - switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); From eli.friedman at gmail.com Mon Oct 17 22:19:45 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 17 Oct 2011 20:19:45 -0700 Subject: [llvm-commits] Removing additional warnings In-Reply-To: <779C31AF-E36E-4670-A0E4-F8B5565B78DA@arxan.com> References:

<779C31AF-E36E-4670-A0E4-F8B5565B78DA@arxan.com> Message-ID: r142332. -Eli On Mon, Oct 17, 2011 at 8:04 PM, Joe Abbey wrote: > Ping? > I'd commit it myself as obvious, but I'd need commit access. :-) > Thanks! > Joe Abbey > Software Architect > Arxan Technologies, Inc. > 1305 Cumberland Ave, Ste 215 > West Lafayette, IN 47906 > jabbey at arxan.com > www.arxan.com > On Oct 17, 2011, at 6:56 PM, Joe Abbey wrote: > > Updated after Bill's Dr. Frankenstein maneuver. > > Joe Abbey > Software Architect > Arxan Technologies, Inc. > 1305 Cumberland Ave, Ste 215 > West Lafayette, IN 47906 > jabbey at arxan.com > www.arxan.com > On Oct 17, 2011, at 5:44 PM, Joe Abbey wrote: > > This resolves the last couple warnings: > > MipsISelLowering.cpp:791:12: warning: variable ?dl? set but not used > [-Wunused-but-set-variable] > ARMISelDAGToDAG.cpp:2319:12: warning: variable ?DL? set but not used > [-Wunused-but-set-variable] > > as well as some warnings when tbl-genning thumb2 > > Cheers, > Joe Abbey > Software Architect > Arxan Technologies, Inc. > 1305 Cumberland Ave, Ste 215 > West Lafayette, IN 47906 > jabbey at arxan.com > www.arxan.com > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From hfinkel at anl.gov Mon Oct 17 22:51:57 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 18 Oct 2011 03:51:57 -0000 Subject: [llvm-commits] [llvm] r142334 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20111018035157.553622A6C12C@llvm.org> Author: hfinkel Date: Mon Oct 17 22:51:57 2011 New Revision: 142334 URL: http://llvm.org/viewvc/llvm-project?rev=142334&view=rev Log: Fix comment to refer to correct instruction Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=142334&r1=142333&r2=142334&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Oct 17 22:51:57 2011 @@ -2686,7 +2686,7 @@ } void SelectionDAGBuilder::visitFPExt(const User &I){ - // FPTrunc is never a no-op cast, no need to check + // FPExt is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); From jabbey at arxan.com Mon Oct 17 22:56:40 2011 From: jabbey at arxan.com (Joe Abbey) Date: Mon, 17 Oct 2011 22:56:40 -0500 Subject: [llvm-commits] [llvm] r142315 - in /llvm/trunk: include/llvm/Object/COFF.h lib/Object/COFFObjectFile.cpp In-Reply-To: <20111017235356.AE20F2A6C12C@llvm.org> References: <20111017235356.AE20F2A6C12C@llvm.org> Message-ID: Michael, index will never be < 0, since it is uint32_t. Perhaps remove the check index >= 0? Granted, storage class and section number values can be "negative", but I don't think indexes will be. Unless as you've coded an index is produced >= NumberOfSymbols. error_code COFFObjectFile::getSymbol(uint32_t index, const coff_symbol *&Result) const { if (index < Header->NumberOfSymbols) Result = SymbolTable + index; else return object_error::parse_failed; return object_error::success; } Cheers, Joe Abbey Software Architect Arxan Technologies, Inc. 1305 Cumberland Ave, Ste 215 West Lafayette, IN 47906 jabbey at arxan.com www.arxan.com On Oct 17, 2011, at 7:53 PM, Michael J. Spencer wrote: > Author: mspencer > Date: Mon Oct 17 18:53:56 2011 > New Revision: 142315 > > URL: http://llvm.org/viewvc/llvm-project?rev=142315&view=rev > Log: > Object/COFF: Expose more data in the public API. > > Modified: > llvm/trunk/include/llvm/Object/COFF.h > llvm/trunk/lib/Object/COFFObjectFile.cpp > > Modified: llvm/trunk/include/llvm/Object/COFF.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=142315&r1=142314&r2=142315&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Object/COFF.h (original) > +++ llvm/trunk/include/llvm/Object/COFF.h Mon Oct 17 18:53:56 2011 > @@ -73,6 +73,16 @@ > support::ulittle16_t Type; > }; > > +struct coff_aux_section_definition { > + support::ulittle32_t Length; > + support::ulittle16_t NumberOfRelocations; > + support::ulittle16_t NumberOfLinenumbers; > + support::ulittle32_t CheckSum; > + support::ulittle16_t Number; > + support::ulittle8_t Selection; > + char Unused[3]; > +}; > + > class COFFObjectFile : public ObjectFile { > private: > const coff_file_header *Header; > @@ -81,11 +91,7 @@ > const char *StringTable; > uint32_t StringTableSize; > > - error_code getSection(int32_t index, > - const coff_section *&Res) const; > error_code getString(uint32_t offset, StringRef &Res) const; > - error_code getSymbol(uint32_t index, > - const coff_symbol *&Res) const; > > const coff_symbol *toSymb(DataRefImpl Symb) const; > const coff_section *toSec(DataRefImpl Sec) const; > @@ -142,6 +148,17 @@ > virtual StringRef getFileFormatName() const; > virtual unsigned getArch() const; > > + error_code getHeader(const coff_file_header *&Res) const; > + error_code getSection(int32_t index, const coff_section *&Res) const; > + error_code getSymbol(uint32_t index, const coff_symbol *&Res) const; > + template > + error_code getAuxSymbol(uint32_t index, const T *&Res) const { > + const coff_symbol *s; > + error_code ec = getSymbol(index, s); > + Res = reinterpret_cast(s); > + return ec; > + } > + error_code getSymbolName(const coff_symbol *symbol, StringRef &Res) const; > > static inline bool classof(const Binary *v) { > return v->getType() == isCOFF; > > Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=142315&r1=142314&r2=142315&view=diff > ============================================================================== > --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) > +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Mon Oct 17 18:53:56 2011 > @@ -98,21 +98,7 @@ > error_code COFFObjectFile::getSymbolName(DataRefImpl Symb, > StringRef &Result) const { > const coff_symbol *symb = toSymb(Symb); > - // Check for string table entry. First 4 bytes are 0. > - if (symb->Name.Offset.Zeroes == 0) { > - uint32_t Offset = symb->Name.Offset.Offset; > - if (error_code ec = getString(Offset, Result)) > - return ec; > - return object_error::success; > - } > - > - if (symb->Name.ShortName[7] == 0) > - // Null terminated, let ::strlen figure out the length. > - Result = StringRef(symb->Name.ShortName); > - else > - // Not null terminated, use all 8 bytes. > - Result = StringRef(symb->Name.ShortName, 8); > - return object_error::success; > + return getSymbolName(symb, Result); > } > > error_code COFFObjectFile::getSymbolOffset(DataRefImpl Symb, > @@ -525,6 +511,11 @@ > } > } > > +error_code COFFObjectFile::getHeader(const coff_file_header *&Res) const { > + Res = Header; > + return object_error::success; > +} > + > error_code COFFObjectFile::getSection(int32_t index, > const coff_section *&Result) const { > // Check for special index values. > @@ -553,13 +544,32 @@ > > error_code COFFObjectFile::getSymbol(uint32_t index, > const coff_symbol *&Result) const { > - if (index > 0 && index < Header->NumberOfSymbols) > + if (index >= 0 && index < Header->NumberOfSymbols) > Result = SymbolTable + index; > else > return object_error::parse_failed; > return object_error::success; > } > > +error_code COFFObjectFile::getSymbolName(const coff_symbol *symbol, > + StringRef &Res) const { > + // Check for string table entry. First 4 bytes are 0. > + if (symbol->Name.Offset.Zeroes == 0) { > + uint32_t Offset = symbol->Name.Offset.Offset; > + if (error_code ec = getString(Offset, Res)) > + return ec; > + return object_error::success; > + } > + > + if (symbol->Name.ShortName[7] == 0) > + // Null terminated, let ::strlen figure out the length. > + Res = StringRef(symbol->Name.ShortName); > + else > + // Not null terminated, use all 8 bytes. > + Res = StringRef(symbol->Name.ShortName, 8); > + return object_error::success; > +} > + > const coff_relocation *COFFObjectFile::toRel(DataRefImpl Rel) const { > return reinterpret_cast(Rel.p); > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gkistanova at gmail.com Mon Oct 17 16:05:37 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 17 Oct 2011 21:05:37 -0000 Subject: [llvm-commits] [zorg] r142251 - in /zorg/trunk/buildbot/osuosl/master/config: builders.py slaves.py status.py Message-ID: <20111017210537.1C1B52A6C12C@llvm.org> Author: gkistanova Date: Mon Oct 17 16:05:36 2011 New Revision: 142251 URL: http://llvm.org/viewvc/llvm-project?rev=142251&view=rev Log: Cosmetic. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py zorg/trunk/buildbot/osuosl/master/config/slaves.py zorg/trunk/buildbot/osuosl/master/config/status.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=142251&r1=142250&r2=142251&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Oct 17 16:05:36 2011 @@ -34,7 +34,7 @@ return [ # {'name': "llvm-i686-linux", # 'slavenames': ["dunbar1"], -# 'builddir': "llvm-i686", +# 'builddir': "llvm-i686", # 'factory': LLVMBuilder.getLLVMBuildFactory("i686-pc-linux-gnu", jobs=2, enable_shared=True)}, {'name': "llvm-x86_64-linux", 'slavenames': ["gcc14"], @@ -63,7 +63,7 @@ valgrindSuppressions='utils/valgrind/x86_64-pc-linux-gnu.supp')}, {'name': "llvm-i686-debian", 'slavenames': ["gcc15"], - 'builddir': "llvm-i686-debian", + 'builddir': "llvm-i686-debian", 'factory': LLVMBuilder.getLLVMBuildFactory("i686-pc-linux-gnu")}, {'name': "llvm-x86_64-ubuntu", 'slavenames':["arxan_davinci"], @@ -342,7 +342,7 @@ stage1_config='Release+Asserts', stage2_config='Release+Asserts'), 'category' : 'clang'}, - + # Clang cross builders. {'name': "clang-x86_64-darwin10-self-mingw32", 'slavenames':["kistanova1"], @@ -352,7 +352,7 @@ '--host=i686-pc-mingw32', '--target=i686-pc-mingw32']), 'category' : 'clang'}, - + {'name' : "clang-x86_64-darwin10-cross-mingw32", 'slavenames' :["kistanova1"], 'builddir' :"clang-x86_64-darwin10-cross-mingw32", @@ -464,7 +464,7 @@ 'description' : 'install llvm-gcc', 'haltOnFailure' : True },]), 'category' : 'llvm-gcc' }, - + {'name' : "llvm-gcc-build-x86_64-darwin10-x-mingw32-x-armeabi", 'slavenames': [ "kistanova1" ], 'builddir' : "llvm-gcc-build-x86_64-darwin10-x-mingw32-x-armeabi", @@ -485,7 +485,7 @@ 'haltOnFailure' : True }, {'name' : 'copy_cross_tools', 'description' : 'copy cross_tools', - 'haltOnFailure' : True }, + 'haltOnFailure' : True }, {'name' : 'configure_llvm_1', 'description' : 'configure llvm (stage 1)', 'haltOnFailure' : True }, @@ -495,7 +495,7 @@ 'haltOnFailure' : True }, {'name' : 'test_llvm_1', 'description' : 'test llvm (stage 1)', - 'haltOnFailure' : False }, + 'haltOnFailure' : False }, {'name' : 'configure_llvmgcc_1', 'description' : 'configure llvm-gcc (stage 1)', 'haltOnFailure' : True }, @@ -510,35 +510,35 @@ 'haltOnFailure' : True }, {'name' : 'make_llvm_2', 'description' : 'make llvm (stage 2)', - 'extra_args' : ['-j8'], + 'extra_args' : ['-j8'], 'haltOnFailure' : True }, {'name' : 'configure_llvmgcc_2', 'description' : 'configure llvm-gcc (stage 2)', 'haltOnFailure' : True }, {'name' : 'make_llvmgcc_2', 'description' : 'make llvm-gcc (stage 2)', - 'extra_args' : ['-j8'], + 'extra_args' : ['-j8'], 'haltOnFailure' : True }, {'name' : 'install_llvmgcc_2', 'description' : 'install llvm-gcc (stage 2)', - 'haltOnFailure' : True }, + 'haltOnFailure' : True }, {'name' : 'configure_llvm_3', 'description' : 'configure llvm (stage 3)', 'haltOnFailure' : True }, {'name' : 'make_llvm_3', 'description' : 'make llvm (stage 3)', - 'extra_args' : ['-j8'], + 'extra_args' : ['-j8'], 'haltOnFailure' : True }, {'name' : 'configure_llvmgcc_3', 'description' : 'configure llvm-gcc (stage 3)', 'haltOnFailure' : True }, {'name' : 'make_llvmgcc_3', 'description' : 'make llvm-gcc (stage 3)', - 'extra_args' : ['-j8'], + 'extra_args' : ['-j8'], 'haltOnFailure' : True }, {'name' : 'install_llvmgcc_3', 'description' : 'install llvm-gcc (stage 3)', - 'haltOnFailure' : True },]), + 'haltOnFailure' : True },]), 'category' : 'llvm-gcc' }, @@ -794,7 +794,7 @@ for b in _get_clang_builders(): b['category'] = 'clang' yield b - + for b in _get_polly_builders(): b['category'] = 'polly' yield b Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=142251&r1=142250&r2=142251&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Mon Oct 17 16:05:36 2011 @@ -59,7 +59,7 @@ create_slave("kistanova5", properties={'jobs' : 1}, max_builds=1), # Ubuntu pandaboard cortex-a9 - create_slave("kistanova6", properties={'jobs' : 2}, max_builds=1), + create_slave("kistanova6", properties={'jobs' : 2}, max_builds=1), # FreeBSD 8.2 X86_64 create_slave("kistanova7", properties={'jobs' : 2}, max_builds=1), @@ -77,87 +77,87 @@ # GCC Compile Farm Slaves, see http://gcc.gnu.org/wiki/CompileFarm # gcc10 2TB 2x12x1.5 GHz AMD Opteron Magny-Cours / 64 GB RAM / Supermicro AS-1022G-BTF / Debian x86-64 - create_slave("gcc10", properties={'jobs' : 12}, max_builds=1), + create_slave("gcc10", properties={'jobs' : 12}, max_builds=1), # gcc11 580G 2x 2x2.0 GHz AMD Opteron 2212 / 4GB RAM / Dell SC1345 / Debian x86-64 - create_slave("gcc11", properties={'jobs' : 2}, max_builds=1), + create_slave("gcc11", properties={'jobs' : 2}, max_builds=1), # gcc12 580G 2x 2x2.0 GHz AMD Opteron 2212 / 4GB RAM / Dell SC1345 / Debian x86-64 - create_slave("gcc12", properties={'jobs' : 2}, max_builds=1), + create_slave("gcc12", properties={'jobs' : 2}, max_builds=1), # gcc13 580G 2x2x2.0 GHz AMD Opteron 2212 / 4GB RAM / Dell SC1345 / Debian x86-64 - create_slave("gcc13", properties={'jobs' : 2}, max_builds=1), + create_slave("gcc13", properties={'jobs' : 2}, max_builds=1), # gcc14 750G 2x4x3.0 GHz Intel Xeon X5450 / 16GB RAM / Dell Poweredge 1950 / Debian x86-64 - create_slave("gcc14", properties={'jobs' : 4}, max_builds=1), + create_slave("gcc14", properties={'jobs' : 4}, max_builds=1), # gcc15 160G 1x2x2.8 GHz Intel Xeon 2.8 (Paxville DP) / 1 GB RAM / Dell SC1425 / Debian x86-64 - create_slave("gcc15", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc15", properties={'jobs' : 1}, max_builds=1), # gcc16 580G 2x4x2.2 GHz AMD Opteron 8354 (Barcelona B3) / 16 GB RAM / Debian x86-64 - create_slave("gcc16", properties={'jobs' : 4}, max_builds=1), + create_slave("gcc16", properties={'jobs' : 4}, max_builds=1), # gcc17 580G 2x4x2.2 GHz AMD Opteron 8354 (Barcelona B3) / 16 GB RAM / Debian x86-64 - create_slave("gcc17", properties={'jobs' : 4}, max_builds=1), + create_slave("gcc17", properties={'jobs' : 4}, max_builds=1), # gcc20 1TB 2x6x2.93 GHz Intel Dual Xeon X5670 2.93 GHz 12 cores 24 threads / 24 GB RAM / Debian amd64 - create_slave("gcc20", properties={'jobs' : 12}, max_builds=1), + create_slave("gcc20", properties={'jobs' : 12}, max_builds=1), # gcc30 17G 0.4 GHz Alpha EV56 / 2GB RAM / AlphaServer 1200 5/400 => offline, to relocate - create_slave("gcc30", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc30", properties={'jobs' : 1}, max_builds=1), # gcc31 51G 2x0.4 GHz TI UltraSparc II (BlackBird) / 2 GB RAM / Sun Enterprise 250 => offline, to relocate - create_slave("gcc31", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc31", properties={'jobs' : 1}, max_builds=1), # gcc33 19033 1TB 0.8 GHz Freescale i.MX515 / 512 MB RAM / Efika MX Client Dev Board / Ubuntu armv7l - create_slave("gcc33", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc33", properties={'jobs' : 1}, max_builds=1), # gcc34 19034 1TB 0.8 GHz Freescale i.MX515 / 512 MB RAM / Efika MX Client Dev Board / Ubuntu armv7l - create_slave("gcc34", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc34", properties={'jobs' : 1}, max_builds=1), # gcc35 19035 1TB 0.8 GHz Freescale i.MX515 (ARM Cortex-A8) / 512 MB RAM / Efika MX Client Dev Board / Debian armel - create_slave("gcc35", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc35", properties={'jobs' : 1}, max_builds=1), # gcc36 19036 1TB 0.8 GHz Freescale i.MX515 (ARM Cortex-A8) / 512 MB RAM / Efika MX Client Dev Board / Debian armel (?) create_slave("gcc36", properties={'jobs' : 1}, max_builds=1), # gcc37 19037 1TB 0.8 GHz Freescale i.MX515 / 512 MB RAM / Efika MX Client Dev Board / Ubuntu armv7l - create_slave("gcc37", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc37", properties={'jobs' : 1}, max_builds=1), # gcc38 1TB 3.2 GHz IBM Cell BE / 256 MB RAM / Sony Playstation 3 / Debian powerpc - create_slave("gcc38", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc38", properties={'jobs' : 1}, max_builds=1), # gcc40 160G 1.8 GHz IBM PowerPC 970 (G5) / 512 MB RAM / Apple PowerMac G5 / Debian powerpc - create_slave("gcc40", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc40", properties={'jobs' : 1}, max_builds=1), # gcc42 9092 160G 0.8 GHz ICT Loongson 2F / 512 MB RAM / Lemote Fuloong 6004 Linux mini PC / Debian mipsel - create_slave("gcc42", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc42", properties={'jobs' : 1}, max_builds=1), # gcc43 9093 60G 1.4 GHz Powerpc G4 7447A / 1GB RAM / Apple Mac Mini - create_slave("gcc43", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc43", properties={'jobs' : 1}, max_builds=1), # gcc45 19045 1TB 4x3.0 GHz AMD Athlon II X4 640 / 4 GB RAM / Debian i386 - create_slave("gcc45", properties={'jobs' : 2}, max_builds=1), + create_slave("gcc45", properties={'jobs' : 2}, max_builds=1), # gcc46 250G 1.66 GHz Intel Atom D510 2 cores 4 threads / 4 GB RAM / Debian amd64 - create_slave("gcc46", properties={'jobs' : 2}, max_builds=1), + create_slave("gcc46", properties={'jobs' : 2}, max_builds=1), # gcc47 250G 1.66 GHz Intel Atom D510 2 cores 4 threads / 4 GB RAM / Debian amd64 - create_slave("gcc47", properties={'jobs' : 2}, max_builds=1), + create_slave("gcc47", properties={'jobs' : 2}, max_builds=1), # gcc50 9080 250G 0.6 GHz ARM XScale-80219 / 512 MB RAM / Thecus N2100 NAS - create_slave("gcc50", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc50", properties={'jobs' : 1}, max_builds=1), # gcc51 9081 60G 0.8 GHz ICT Loongson 2F / 1 GB RAM / Lemote YeeLoong 8089 notebook / Debian mipsel - create_slave("gcc51", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc51", properties={'jobs' : 1}, max_builds=1), # gcc52 9082 1TB 0.8 GHz ICT Loongson 2F / 512 MB RAM / Gdium Liberty 1000 notebook / Mandriva 2009.1 mipsel - create_slave("gcc52", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc52", properties={'jobs' : 1}, max_builds=1), # gcc53 9083 80G 2x1.25 GHz PowerPC 7455 G4 / 1.5 GB RAM / PowerMac G4 dual processor - create_slave("gcc53", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc53", properties={'jobs' : 1}, max_builds=1), # gcc54 36G 0.5 GHz TI UltraSparc IIe (Hummingbird) / 1.5 GB RAM / Sun Netra T1 200 / Debian sparc - create_slave("gcc54", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc54", properties={'jobs' : 1}, max_builds=1), # gcc55 9085 250G 1.2 GHz Marvell Kirkwood 88F6281 (Feroceon) / 512 MB RAM / Marvell SheevaPlug / Ubuntu armel - create_slave("gcc55", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc55", properties={'jobs' : 1}, max_builds=1), # gcc56 9086 320G 1.2 GHz Marvell Kirkwood 88F6281 (Feroceon) / 512 MB RAM / Marvell SheevaPlug / Ubuntu armel - create_slave("gcc56", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc56", properties={'jobs' : 1}, max_builds=1), # gcc57 9087 320G 1.2 GHz Marvell Kirkwood 88F6281 (Feroceon) / 512 MB RAM / Marvell SheevaPlug / Ubuntu armel - create_slave("gcc57", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc57", properties={'jobs' : 1}, max_builds=1), # gcc60 9200 72G 2x1.3 GHz Intel Itanium 2 (Madison) / 6 GB RAM / HP zx6000 / Debian ia64 - create_slave("gcc60", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc60", properties={'jobs' : 1}, max_builds=1), # gcc61 9201 36G 2x0.55 GHz HP PA-8600 / 3.5 GB RAM / HP 9000/785/J6000 / Debian hppa - create_slave("gcc61", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc61", properties={'jobs' : 1}, max_builds=1), # gcc62 9202 36G 6x0.4 GHz TI UltraSparc II (BlackBird) / 5 GB RAM / Sun Enterprise 4500 / Debian sparc - create_slave("gcc62", properties={'jobs' : 3}, max_builds=1), + create_slave("gcc62", properties={'jobs' : 3}, max_builds=1), # gcc63 9203 72G 8x4x1 GHz Sun UltraSparc T1 (Niagara) / 8 GB RAM / Sun Fire T1000 / Debian sparc - create_slave("gcc63", properties={'jobs' : 16}, max_builds=1), + create_slave("gcc63", properties={'jobs' : 16}, max_builds=1), # gcc64 9204 72G 1 GHz Sun UltraSPARC-IIIi / 1 GB RAM / Sun V210 / OpenBSD 4.6 sparc64 - create_slave("gcc64", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc64", properties={'jobs' : 1}, max_builds=1), # gcc70 160G 2x3.2 GHz Intel Xeon 3.2E (Irwindale) / 3 GB RAM / Dell Poweredge SC1425 / NetBSD amd64 - create_slave("gcc70", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc70", properties={'jobs' : 1}, max_builds=1), # gcc100 1TB 2x2.6 GHz AMD Opteron 252 / 1GB RAM running Debian x86_64 - create_slave("gcc100", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc100", properties={'jobs' : 1}, max_builds=1), # gcc101 1TB 2x2.6 GHz AMD Opteron 252 / 1GB RAM running FreeBSD 8 x86_64 - create_slave("gcc101", properties={'jobs' : 1}, max_builds=1), + create_slave("gcc101", properties={'jobs' : 1}, max_builds=1), # gcc200 8010 80G 4x0.4 GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 - create_slave("gcc200", properties={'jobs' : 2}, max_builds=1), + create_slave("gcc200", properties={'jobs' : 2}, max_builds=1), # gcc201 8011 80G 4x0.4 GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 - create_slave("gcc201", properties={'jobs' : 2}, max_builds=1), + create_slave("gcc201", properties={'jobs' : 2}, max_builds=1), # Debian x86_64, 2 x 6-core Opteron 2.6 GHz create_slave("osu7", properties={'jobs' : 6}, max_builds=4), Modified: zorg/trunk/buildbot/osuosl/master/config/status.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/status.py?rev=142251&r1=142250&r2=142251&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/status.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/status.py Mon Oct 17 16:05:36 2011 @@ -6,7 +6,7 @@ import config from zorg.buildbot.util.ConfigEmailLookup import ConfigEmailLookup -from zorg.buildbot.util.InformativeMailNotifier import InformativeMailNotifier +from zorg.buildbot.util.InformativeMailNotifier import InformativeMailNotifier # Returns a list of Status Targets. The results of each build will be # pushed to these targets. buildbot/status/*.py has a variety to choose from, @@ -19,12 +19,12 @@ authz_cfg=authz.Authz( # change any of these to True to enable; see the manual for more # options - gracefulShutdown = False, - forceBuild = True, # use this to test your slave once it is set up - forceAllBuilds = False, - pingBuilder = True, - stopBuild = True, - stopAllBuilds = False, + gracefulShutdown = False, + forceBuild = True, # use this to test your slave once it is set up + forceAllBuilds = False, + pingBuilder = True, + stopBuild = True, + stopAllBuilds = False, cancelPendingBuild = True, ) From nick.sumner at gmail.com Mon Oct 17 14:53:33 2011 From: nick.sumner at gmail.com (Nick Sumner) Date: Mon, 17 Oct 2011 15:53:33 -0400 Subject: [llvm-commits] Patch to support projects using C++0x mode Message-ID: C++0x mode in GCC requires that destructors be accessible by children in the class hierarchy. This is true even if the destructors in both a parent and its child are deleted. The attached patch fixes deleted destructor visibility for Operators to allow GCC to build LLVM projects that use C++0x mode. It simply makes deleted parent destructors protected instead of private. -- Nick Sumner -------------- next part -------------- A non-text attachment was scrubbed... Name: destructorAccess.diff Type: text/x-patch Size: 957 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111017/0b143dd5/attachment.bin From bigcheesegs at gmail.com Mon Oct 17 23:29:02 2011 From: bigcheesegs at gmail.com (Michael Spencer) Date: Mon, 17 Oct 2011 21:29:02 -0700 Subject: [llvm-commits] [llvm] r142315 - in /llvm/trunk:include/llvm/Object/COFF.h lib/Object/COFFObjectFile.cpp In-Reply-To: References: Message-ID: On Mon, Oct 17, 2011 at 6:48 PM, Xu Zhongxing wrote: > > @@ -553,13 +544,32 @@ > > ?error_code COFFObjectFile::getSymbol(uint32_t index, > ????????????????????????????????????? const coff_symbol *&Result) const { > -? if (index > 0 && index < Header->NumberOfSymbols) > +? if (index >= 0 && index < Header->NumberOfSymbols) > Hi Michael, index is unsigned. It's always >= 0. Thanks, didn't notice that while changing. The >= 0 was intended to handle the -1 and -2 cases. The COFF standard doesn't specify if the field is signed or unsigned, however, the tools seem to indicate that it is unsigned, and only -1 and -2 have special meanings. - Michael Spencer From dgregor at apple.com Mon Oct 17 23:33:28 2011 From: dgregor at apple.com (Douglas Gregor) Date: Mon, 17 Oct 2011 21:33:28 -0700 Subject: [llvm-commits] Patch to support projects using C++0x mode In-Reply-To: References: Message-ID: On Oct 17, 2011, at 12:53 PM, Nick Sumner wrote: > C++0x mode in GCC requires that destructors be accessible by children > in the class hierarchy. This is true even if the destructors in both a > parent and its child are deleted. This sounds like a GCC bug. Which version of GCC is this? Have you reported it as a bug there? > The attached patch fixes deleted destructor visibility for Operators > to allow GCC to build LLVM projects that use C++0x mode. It simply > makes deleted parent destructors protected instead of private. Please add comments indicating that this is a workaround for compiler bugs in GCC, rather than some deliberate attempt to make the destructors accessible to subclasses. - Doug From jabbey at arxan.com Mon Oct 17 23:44:37 2011 From: jabbey at arxan.com (Joe Abbey) Date: Tue, 18 Oct 2011 04:44:37 -0000 Subject: [llvm-commits] [llvm] r142336 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20111018044437.2B68C2A6C12C@llvm.org> Author: jabbey Date: Mon Oct 17 23:44:36 2011 New Revision: 142336 URL: http://llvm.org/viewvc/llvm-project?rev=142336&view=rev Log: Commit test, capitalizing store... keep it simple. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=142336&r1=142335&r2=142336&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Oct 17 23:44:36 2011 @@ -2145,7 +2145,7 @@ } //===----------------------------------------------------------------------===// -// Load / store Instructions. +// Load / Store Instructions. // // Load From mcrosier at apple.com Tue Oct 18 00:28:00 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 18 Oct 2011 05:28:00 -0000 Subject: [llvm-commits] [llvm] r142337 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMFrameLowering.cpp lib/Target/ARM/Thumb1FrameLowering.cpp test/CodeGen/ARM/thumb1-dynrealign.ll Message-ID: <20111018052800.70B9A2A6C12C@llvm.org> Author: mcrosier Date: Tue Oct 18 00:28:00 2011 New Revision: 142337 URL: http://llvm.org/viewvc/llvm-project?rev=142337&view=rev Log: Add support for dynamic stack realignment when in thumb1 mode. rdar://10288916 Added: llvm/trunk/test/CodeGen/ARM/thumb1-dynrealign.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=142337&r1=142336&r2=142337&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Oct 18 00:28:00 2011 @@ -626,13 +626,10 @@ bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - const ARMFunctionInfo *AFI = MF.getInfo(); // We can't realign the stack if: // 1. Dynamic stack realignment is explicitly disabled, - // 2. This is a Thumb1 function (it's not useful, so we don't bother), or - // 3. There are VLAs in the function and the base pointer is disabled. - return (RealignStack && !AFI->isThumb1OnlyFunction() && - (!MFI->hasVarSizedObjects() || EnableBasePointer)); + // 2. There are VLAs in the function and the base pointer is disabled. + return (RealignStack && (!MFI->hasVarSizedObjects() || EnableBasePointer)); } bool ARMBaseRegisterInfo:: Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=142337&r1=142336&r2=142337&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Tue Oct 18 00:28:00 2011 @@ -881,10 +881,12 @@ // for sure what the stack size will be, but for this, an estimate is good // enough. If there anything changes it, it'll be a spill, which implies // we've used all the registers and so R4 is already used, so not marking - // it here will be OK. + // it here will be OK. Also spill R4 if Thumb1 function requires stack + // realignment. // FIXME: It will be better just to find spare register here. unsigned StackSize = estimateStackSize(MF); - if (MFI->hasVarSizedObjects() || StackSize > 508) + if (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF) || + StackSize > 508) MF.getRegInfo().setPhysRegUsed(ARM::R4); } Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=142337&r1=142336&r2=142337&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Tue Oct 18 00:28:00 2011 @@ -155,10 +155,32 @@ AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); AFI->setDPRCalleeSavedAreaSize(DPRCSSize); - // Thumb1 does not currently support dynamic stack realignment. Report a - // fatal error rather then silently generate bad code. - if (RegInfo->needsStackRealignment(MF)) - report_fatal_error("Dynamic stack realignment not supported for thumb1."); + // If we need dynamic stack realignment, do it here. Be paranoid and make + // sure if we also have VLAs, we have a base pointer for frame access. + if (RegInfo->needsStackRealignment(MF)) { + // We cannot use sp as source/dest register here, thus we're emitting the + // following sequence: + // mov r4, sp + // lsrs r4, r4, Log2MaxAlign + // lsls r4, r4, Log2MaxAlign + // mov sp, r4 + unsigned MaxAlign = MFI->getMaxAlignment(); + unsigned Log2MaxAlign = Log2_32(MaxAlign); + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) + .addReg(ARM::SP, RegState::Kill)); + AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), + ARM::R4)) + .addReg(ARM::R4, RegState::Kill) + .addImm(Log2MaxAlign)); + AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), + ARM::R4)) + .addReg(ARM::R4, RegState::Kill) + .addImm(Log2MaxAlign)); + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) + .addReg(ARM::R4, RegState::Kill)); + + AFI->setShouldRestoreSPFromFP(true); + } // If we need a base pointer, set it up here. It's whatever the value // of the stack pointer is at this point. Any variable size objects Added: llvm/trunk/test/CodeGen/ARM/thumb1-dynrealign.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb1-dynrealign.ll?rev=142337&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/thumb1-dynrealign.ll (added) +++ llvm/trunk/test/CodeGen/ARM/thumb1-dynrealign.ll Tue Oct 18 00:28:00 2011 @@ -0,0 +1,40 @@ +; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s + +; Normal load from SP +define void @SP(i32 %i) nounwind uwtable ssp { +entry: +; CHECK: @SP +; CHECK: push {r7, lr} +; CHECK-NEXT: mov r7, sp +; CHECK-NEXT: sub sp, #4 +; CHECK-NEXT: mov r1, sp +; CHECK-NEXT: str r0, [r1] +; CHECK-NEXT: mov r0, sp +; CHECK-NEXT: blx _SP_ +; CHECK-NEXT: add sp, #4 +; CHECK-NEXT: pop {r7, pc} + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + call void @SP_(i32* %i.addr) + ret void +} + +declare void @SP_(i32*) + +; Dynamic stack realignment +define void @FP(double %a) nounwind uwtable ssp { +entry: +; CHECK: mov r4, sp +; CHECK-NEXT: lsrs r4, r4, #3 +; CHECK-NEXT: lsls r4, r4, #3 +; CHECK-NEXT: mov sp, r4 +; Restore from FP +; CHECK: subs r4, r7, #4 +; CHECK: mov sp, r4 + %a.addr = alloca double, align 8 + store double %a, double* %a.addr, align 8 + call void @FP_(double* %a.addr) + ret void +} + +declare void @FP_(double*) From pdox at google.com Tue Oct 18 00:29:23 2011 From: pdox at google.com (David Meyer) Date: Tue, 18 Oct 2011 05:29:23 -0000 Subject: [llvm-commits] [llvm] r142338 - in /llvm/trunk/lib/Target: ARM/ARM.td ARM/ARMInstrInfo.td ARM/ARMSubtarget.cpp ARM/ARMSubtarget.h ARM/MCTargetDesc/ARMMCTargetDesc.cpp X86/MCTargetDesc/X86MCTargetDesc.cpp X86/X86.td X86/X86InstrInfo.td X86/X86Subtarget.cpp X86/X86Subtarget.h Message-ID: <20111018052923.E3BB13524001@llvm.org> Author: pdox Date: Tue Oct 18 00:29:23 2011 New Revision: 142338 URL: http://llvm.org/viewvc/llvm-project?rev=142338&view=rev Log: Remove NaClMode Modified: llvm/trunk/lib/Target/ARM/ARM.td llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp llvm/trunk/lib/Target/X86/X86.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86Subtarget.cpp llvm/trunk/lib/Target/X86/X86Subtarget.h Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=142338&r1=142337&r2=142338&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Tue Oct 18 00:29:23 2011 @@ -23,9 +23,6 @@ def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", "Thumb mode">; -def ModeNaCl : SubtargetFeature<"nacl-mode", "InNaClMode", "true", - "Native client mode">; - //===----------------------------------------------------------------------===// // ARM Subtarget features. // Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=142338&r1=142337&r2=142338&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Oct 18 00:29:23 2011 @@ -213,8 +213,7 @@ AssemblerPredicate<"!ModeThumb">; def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; -def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">, - AssemblerPredicate<"ModeNaCl">; +def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; // FIXME: Eventually this will be just "hasV6T2Ops". def UseMovt : Predicate<"Subtarget->useMovt()">; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=142338&r1=142337&r2=142338&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Tue Oct 18 00:29:23 2011 @@ -53,7 +53,6 @@ , HasVMLxForwarding(false) , SlowFPBrcc(false) , InThumbMode(false) - , InNaClMode(false) , HasThumb2(false) , IsMClass(false) , NoARM(false) Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=142338&r1=142337&r2=142338&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Oct 18 00:29:23 2011 @@ -70,9 +70,6 @@ /// InThumbMode - True if compiling for Thumb, false for ARM. bool InThumbMode; - /// InNaClMode - True if targeting Native Client - bool InNaClMode; - /// HasThumb2 - True if Thumb2 instructions are supported. bool HasThumb2; Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=142338&r1=142337&r2=142338&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Tue Oct 18 00:29:23 2011 @@ -89,14 +89,6 @@ ARMArchFeature += ",+thumb-mode"; } - Triple TheTriple(TT); - if (TheTriple.getOS() == Triple::NativeClient) { - if (ARMArchFeature.empty()) - ARMArchFeature = "+nacl-mode"; - else - ARMArchFeature += ",+nacl-mode"; - } - return ARMArchFeature; } Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=142338&r1=142337&r2=142338&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Tue Oct 18 00:29:23 2011 @@ -45,10 +45,6 @@ FS = "+64bit-mode"; else FS = "-64bit-mode"; - if (TheTriple.getOS() == Triple::NativeClient) - FS += ",+nacl-mode"; - else - FS += ",-nacl-mode"; return FS; } Modified: llvm/trunk/lib/Target/X86/X86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=142338&r1=142337&r2=142338&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.td (original) +++ llvm/trunk/lib/Target/X86/X86.td Tue Oct 18 00:29:23 2011 @@ -23,9 +23,6 @@ def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", "64-bit mode (x86_64)">; -def ModeNaCl : SubtargetFeature<"nacl-mode", "InNaClMode", "true", - "Native Client mode">; - //===----------------------------------------------------------------------===// // X86 Subtarget features. //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=142338&r1=142337&r2=142338&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Oct 18 00:29:23 2011 @@ -490,14 +490,8 @@ AssemblerPredicate<"Mode64Bit">; def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; -def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">, - AssemblerPredicate<"ModeNaCl">; -def IsNaCl32 : Predicate<"Subtarget->isTargetNaCl32()">, - AssemblerPredicate<"ModeNaCl,!Mode64Bit">; -def IsNaCl64 : Predicate<"Subtarget->isTargetNaCl64()">, - AssemblerPredicate<"ModeNaCl,Mode64Bit">; -def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">, - AssemblerPredicate<"!ModeNaCl">; +def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; +def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=142338&r1=142337&r2=142338&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Tue Oct 18 00:29:23 2011 @@ -321,8 +321,7 @@ // FIXME: this is a known good value for Yonah. How about others? , MaxInlineSizeThreshold(128) , TargetTriple(TT) - , In64BitMode(is64Bit) - , InNaClMode(false) { + , In64BitMode(is64Bit) { // Determine default and user specified characteristics if (!FS.empty() || !CPU.empty()) { std::string CPUName = CPU; @@ -368,11 +367,6 @@ if (In64BitMode) ToggleFeature(X86::Mode64Bit); - if (isTargetNaCl()) { - InNaClMode = true; - ToggleFeature(X86::ModeNaCl); - } - if (HasAVX) X86SSELevel = NoMMXSSE; Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=142338&r1=142337&r2=142338&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Tue Oct 18 00:29:23 2011 @@ -137,9 +137,6 @@ /// In64BitMode - True if compiling for 64-bit, false for 32-bit. bool In64BitMode; - /// InNaClMode - True if compiling for Native Client target. - bool InNaClMode; - public: /// This constructor initializes the data members to match that From pdox at google.com Tue Oct 18 00:32:37 2011 From: pdox at google.com (David Meyer) Date: Mon, 17 Oct 2011 22:32:37 -0700 Subject: [llvm-commits] [llvm] r139125 - in /llvm/trunk/lib/Target: ARM/ARM.td ARM/ARMInstrInfo.td ARM/ARMSubtarget.cpp ARM/ARMSubtarget.h ARM/MCTargetDesc/ARMMCTargetDesc.cpp X86/MCTargetDesc/X86MCTargetDesc.cpp X86/X86.td X86/X86InstrInfo.td X86/X86Subt In-Reply-To: <4A95B243-6A22-4C87-8954-AEAD7C76FFFC@apple.com> References: <5507F0AA-C4AA-4E4C-AAEB-E29BA56F2FE9@apple.com> <64F54B0A-8C73-481D-BE71-3BE9C52B6562@apple.com> <1B395F83-791E-42CE-9A72-1FBC9230EC19@apple.com>

<4A95B243-6A22-4C87-8954-AEAD7C76FFFC@apple.com> Message-ID: Committed r142338 From nick.sumner at gmail.com Tue Oct 18 01:22:21 2011 From: nick.sumner at gmail.com (Nick Sumner) Date: Tue, 18 Oct 2011 02:22:21 -0400 Subject: [llvm-commits] Patch to support projects using C++0x mode In-Reply-To: References:

Message-ID: Sorry, looks like this was already fixed in a better way by r131062. On 10/18/11, Douglas Gregor wrote: > > On Oct 17, 2011, at 12:53 PM, Nick Sumner wrote: > >> C++0x mode in GCC requires that destructors be accessible by children >> in the class hierarchy. This is true even if the destructors in both a >> parent and its child are deleted. > > This sounds like a GCC bug. Which version of GCC is this? Have you reported > it as a bug there? > >> The attached patch fixes deleted destructor visibility for Operators >> to allow GCC to build LLVM projects that use C++0x mode. It simply >> makes deleted parent destructors protected instead of private. > > Please add comments indicating that this is a workaround for compiler bugs > in GCC, rather than some deliberate attempt to make the destructors > accessible to subclasses. > > - Doug > -- Nick Sumner From nadav.rotem at intel.com Tue Oct 18 02:37:05 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Tue, 18 Oct 2011 09:37:05 +0200 Subject: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ In-Reply-To: <32320A16-378C-4390-A51B-241396859284@mac.com> References: <20111016203133.CC4E13128018@llvm.org> <1B579157-F0E8-45FB-A8E8-3D520ED36FC0@mac.com> <84BE87AB-7185-4CF6-B0F4-D242762AA4A0@mac.com> <6594DDFF12B03D4E89690887C248699402A2C887C6@hasmsx504.ger.corp.intel.com> <32320A16-378C-4390-A51B-241396859284@mac.com> Message-ID: <6594DDFF12B03D4E89690887C248699402A2C888AA@hasmsx504.ger.corp.intel.com> Owen, I discussed the legalization of <2 x i16> stores on ARM with Anton. As you mentioned, i16 is illegal on ARM and it is not possible to scalarize the store in the Legalizer. This was the main reason for moving the legalization of vector memory ops into LegalizeVectorOps. I agree that in some cases promoting the elements in the vector is less efficient than widening the number of elements. However, generally ?promotion? is a better strategy. I am mostly interested in code-generation of auto-vectorized IR. What workloads are you mostly interested in ? Maybe we can discuss the needed optimizations for these workloads. I benchmarked x86 programs (w/ SSE and AVX), but ARM and other SIMD processors should be similar. Thanks, Nadav From: Owen Anderson [mailto:resistor at mac.com] Sent: Monday, October 17, 2011 23:53 To: Rotem, Nadav Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ Nadav, On Oct 17, 2011, at 1:37 PM, Rotem, Nadav wrote:? The new type-legalization generates new code sequences. For example: trunc store and anyext loads. ?I implemented fast load/store sequences ?for x86. ?Other targets also need to optimize the new sequences. ?I opened a bug report on this PR11158. Unfortunately, that PR does not cover the issue exposed in the testcase I pointed out, which is a real, significant performance issue with this approach. ?Take a look at this snippet: define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { entry: ? %0 = bitcast <4 x i16>* %source to <8 x i16>* ? %tmp2 = load <8 x i16>* %0, align 4 ? %tmp3 = extractelement <8 x i16> %tmp2, i32 6 ? %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0 ? %tmp9 = extractelement <8 x i16> %tmp2, i32 5 ? %tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1 ? store <2 x i16> %tmp11, <2 x i16>* %dst, align 4 ? ret void } In NEON, vectors of i16 are legal, but i16 is not. ?The correct code generation sequence was to collapse all of the insert/extract vectors into a shuffle, at which point there are longer illegal types present. ?With your change, we promote all the vectors to vector of i32, at which point we can no longer match the desired shuffle instruction, in addition to having to emit a (possibly inefficient) vector trunc_store. ?Even if we do add an efficient trunc_store lowering to ARM backend, it will still be unable to match the efficient shuffle because we have obfuscated the code by promoting rather than collapsing it to a shuffle. That collapse to a shuffle is what the test that removed was checking for. --Owen --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From isanbard at gmail.com Tue Oct 18 02:40:22 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 18 Oct 2011 07:40:22 -0000 Subject: [llvm-commits] [llvm] r142341 - /llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h Message-ID: <20111018074022.5DF7E312800A@llvm.org> Author: void Date: Tue Oct 18 02:40:22 2011 New Revision: 142341 URL: http://llvm.org/viewvc/llvm-project?rev=142341&view=rev Log: Coding style cleanups. No functionality change. Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h?rev=142341&r1=142340&r2=142341&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h (original) +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h Tue Oct 18 02:40:22 2011 @@ -1,7 +1,4 @@ -#ifndef LLVM_Mips_MipsFIXUPKINDS_H -#define LLVM_Mips_MipsFIXUPKINDS_H - -//===-- Mips/MipsFixupKinds.h - Mips Specific Fixup Entries --------*- C++ -*-===// +//===-- Mips/MipsFixupKinds.h - Mips Specific Fixup Entries -----*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -10,6 +7,8 @@ // //===----------------------------------------------------------------------===// +#ifndef LLVM_Mips_MipsFIXUPKINDS_H +#define LLVM_Mips_MipsFIXUPKINDS_H #include "llvm/MC/MCFixup.h" @@ -83,8 +82,8 @@ LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; -} // namespace llvm } // namespace Mips +} // namespace llvm -#endif /* LLVM_Mips_MipsFIXUPKINDS_H */ +#endif // LLVM_Mips_MipsFIXUPKINDS_H From geek4civic at gmail.com Tue Oct 18 02:48:23 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 18 Oct 2011 16:48:23 +0900 Subject: [llvm-commits] [PATCH] test/lit.cfg: Enable the feature 'asserts' to check output of llc -version. Message-ID: llc knows whether he is compiled with -DNDEBUG. | Optimized build with assertions. --- test/lit.cfg | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-test-lit.cfg-Enable-the-feature-asserts-to-check.patch.txt Type: text/x-patch Size: 580 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111018/823c1ec3/attachment.bin From baldrick at free.fr Tue Oct 18 03:02:35 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 18 Oct 2011 10:02:35 +0200 Subject: [llvm-commits] [llvm] r142300 - in /llvm/trunk: include/llvm/MC/ include/llvm/Support/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCParser/ lib/Target/ lib/Target/PTX/ test/CodeGen/X86/ test/MC/AsmParser/ tools/llc/ tools/llvm-mc/ In-Reply-To: <20111017230529.111262A6C12C@llvm.org> References: <20111017230529.111262A6C12C@llvm.org> Message-ID: <4E9D329B.7070808@free.fr> Hi Nick, > Add support for a new extension to the .file directive: > > .file filenumber "directory" "filename" > > This removes one join+split of the directory+filename in MC internals. Because > bitcode files have independent fields for directory and filenames in debug info, > this patch may change the .o files written by existing .bc files. I think this broke the dragonegg buildbots. The assembler complains with messages like this: cc2Q7AFZ.s:6: Error: junk at end of line, first unrecognized character is `"' The line in question is .file 1 "/home/baldrick/osuosl/slave/dragonegg-i386-linux/dragonegg/utils" "TargetInfo.cpp" Ciao, Duncan. From mcrosier at apple.com Tue Oct 18 03:08:41 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 18 Oct 2011 01:08:41 -0700 Subject: [llvm-commits] [llvm] r142191 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp In-Reply-To: <20111017161810.1CEAA312800A@llvm.org> References: <20111017161810.1CEAA312800A@llvm.org> Message-ID: On Oct 17, 2011, at 9:18 AM, Benjamin Kramer wrote: > Author: d0k > Date: Mon Oct 17 11:18:09 2011 > New Revision: 142191 > > URL: http://llvm.org/viewvc/llvm-project?rev=142191&view=rev > Log: > Pick low-hanging MatchEntry shrinkage fruit. > > Shaves 200k off Release-Asserts clang binaries on i386. Nice! :) -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111018/ef98ee7d/attachment.html From baldrick at free.fr Tue Oct 18 03:12:47 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 18 Oct 2011 10:12:47 +0200 Subject: [llvm-commits] [PATCH] Fix compiling source files in subdirectories with autoconf In-Reply-To: <8963C7C2-E230-4BB3-B0EC-F0ABB529E95A@mymail.mines.edu> References: <8963C7C2-E230-4BB3-B0EC-F0ABB529E95A@mymail.mines.edu> Message-ID: <4E9D34FF.6040001@free.fr> Hi Charles, > This patch fixes an issue with source files located in subdirectories (relative to the Makefile referencing them). The build system was not creating those directories in the build tree, which caused compiling the sources to fail. This patch fixes that. I encountered this getting the LLDB Host library and LLDB debug server to compile from Makefiles. your patch has a bunch of changes to lib/Target/X86 in it. I presume that was an accident? Ciao, Duncan. From geek4civic at gmail.com Tue Oct 18 03:22:40 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 18 Oct 2011 17:22:40 +0900 Subject: [llvm-commits] [PATCH] test/lit.cfg: Enable the feature 'asserts' to check output of llc -version. In-Reply-To: References: Message-ID: Oh no, I missed fixup patch. -if re.match(r'with assertions', llc_cmd.stdout.read()): +if re.search(r'with assertions', llc_cmd.stdout.read()): FYI, on cmake build, there are build configurations "Release" "Debug" "MinSizeRel" "RelWithDebInfo". All of them are applicable on Linux and mingw. ...Takumi From baldrick at free.fr Tue Oct 18 03:22:14 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 18 Oct 2011 08:22:14 -0000 Subject: [llvm-commits] [dragonegg] r142343 - /dragonegg/trunk/src/Backend.cpp Message-ID: <20111018082214.AFAFA3128034@llvm.org> Author: baldrick Date: Tue Oct 18 03:22:14 2011 New Revision: 142343 URL: http://llvm.org/viewvc/llvm-project?rev=142343&view=rev Log: No need to explicitly enable vector select support: it is now the default. Modified: dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=142343&r1=142342&r2=142343&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Tue Oct 18 03:22:14 2011 @@ -340,8 +340,6 @@ if (flag_split_stack) Args.push_back("--segmented-stacks"); #endif - // Enable the experimental vector type legalization by element promotion code. - Args.push_back("--promote-elements"); // If there are options that should be passed through to the LLVM backend // directly from the command line, do so now. This is mainly for debugging From baldrick at free.fr Tue Oct 18 03:25:20 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 18 Oct 2011 08:25:20 -0000 Subject: [llvm-commits] [dragonegg] r142344 - /dragonegg/trunk/src/Backend.cpp Message-ID: <20111018082520.925843128034@llvm.org> Author: baldrick Date: Tue Oct 18 03:25:20 2011 New Revision: 142344 URL: http://llvm.org/viewvc/llvm-project?rev=142344&view=rev Log: Try to fix the dragonegg buildbots by disabling this new feature (file directives with an explicit directory), which is not yet supported by binutils. Modified: dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=142344&r1=142343&r2=142344&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Tue Oct 18 03:25:20 2011 @@ -340,6 +340,9 @@ if (flag_split_stack) Args.push_back("--segmented-stacks"); #endif + // Binutils does not yet support this construct. FIXME: Once GCC learns to + // detect support for this, condition this on what GCC detected. + Args.push_back("--disable-dwarf-directory"); // If there are options that should be passed through to the LLVM backend // directly from the command line, do so now. This is mainly for debugging From baldrick at free.fr Tue Oct 18 03:33:42 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 18 Oct 2011 10:33:42 +0200 Subject: [llvm-commits] [llvm] r142300 - in /llvm/trunk: include/llvm/MC/ include/llvm/Support/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/ lib/MC/MCParser/ lib/Target/ lib/Target/PTX/ test/CodeGen/X86/ test/MC/AsmParser/ tools/llc/ tools/llvm-mc/ In-Reply-To: <4E9D329B.7070808@free.fr> References: <20111017230529.111262A6C12C@llvm.org> <4E9D329B.7070808@free.fr> Message-ID: <4E9D39E6.9090901@free.fr> Hi Nick, for the moment I've disabled this feature in dragonegg, which should fix the dragonegg buildbots. Ciao, Duncan. >> Add support for a new extension to the .file directive: >> >> .file filenumber "directory" "filename" >> >> This removes one join+split of the directory+filename in MC internals. Because >> bitcode files have independent fields for directory and filenames in debug info, >> this patch may change the .o files written by existing .bc files. > > I think this broke the dragonegg buildbots. The assembler complains with > messages like this: > > cc2Q7AFZ.s:6: Error: junk at end of line, first unrecognized character is `"' > > The line in question is > > .file 1 > "/home/baldrick/osuosl/slave/dragonegg-i386-linux/dragonegg/utils" "TargetInfo.cpp" > > Ciao, Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Tue Oct 18 04:11:57 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 18 Oct 2011 09:11:57 -0000 Subject: [llvm-commits] [dragonegg] r142346 - /dragonegg/trunk/src/Backend.cpp Message-ID: <20111018091157.4E9333128034@llvm.org> Author: baldrick Date: Tue Oct 18 04:11:57 2011 New Revision: 142346 URL: http://llvm.org/viewvc/llvm-project?rev=142346&view=rev Log: Directly set the MC flag rather than pushing a command line argument. Modified: dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=142346&r1=142345&r2=142346&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Tue Oct 18 04:11:57 2011 @@ -340,9 +340,6 @@ if (flag_split_stack) Args.push_back("--segmented-stacks"); #endif - // Binutils does not yet support this construct. FIXME: Once GCC learns to - // detect support for this, condition this on what GCC detected. - Args.push_back("--disable-dwarf-directory"); // If there are options that should be passed through to the LLVM backend // directly from the command line, do so now. This is mainly for debugging @@ -438,8 +435,12 @@ TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr, RelocModel, CMModel); - TheTarget->setMCUseCFI(flag_dwarf2_cfi_asm); assert(TheTarget->getTargetData()->isBigEndian() == BYTES_BIG_ENDIAN); + TheTarget->setMCUseCFI(flag_dwarf2_cfi_asm); + // Binutils does not yet support the use of file directives with an explicit + // directory. FIXME: Once GCC learns to detect support for this, condition + // on what GCC detected. + TheTarget->setMCUseDwarfDirectory(false); } /// CreateModule - Create and initialize a module to output LLVM IR to. From baldrick at free.fr Tue Oct 18 04:20:04 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 18 Oct 2011 09:20:04 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r142347 - /llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Message-ID: <20111018092004.D137C3128034@llvm.org> Author: baldrick Date: Tue Oct 18 04:20:04 2011 New Revision: 142347 URL: http://llvm.org/viewvc/llvm-project?rev=142347&view=rev Log: Hook up the returns_twice attribute to GCC's ECF_RETURNS_TWICE. Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=142347&r1=142346&r2=142347&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Tue Oct 18 04:20:04 2011 @@ -901,6 +901,10 @@ if (flags & ECF_NOTHROW) FnAttributes |= Attribute::NoUnwind; + // Check for 'returnstwice' function attribute. + if (flags & ECF_RETURNS_TWICE) + FnAttributes |= Attribute::ReturnsTwice; + // Check for 'readnone' function attribute. // Both PURE and CONST will be set if the user applied // __attribute__((const)) to a function the compiler From nadav.rotem at intel.com Tue Oct 18 04:21:32 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Tue, 18 Oct 2011 11:21:32 +0200 Subject: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ In-Reply-To: References: <20111016203133.CC4E13128018@llvm.org> Message-ID: <6594DDFF12B03D4E89690887C248699402A2C88958@hasmsx504.ger.corp.intel.com> Hi Eli, Thanks for letting me know about this. I am now able to reproduce this problem locally. Hope to fix this soon. Nadav -----Original Message----- From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Tuesday, October 18, 2011 04:48 To: Rotem, Nadav Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ On Sun, Oct 16, 2011 at 1:31 PM, Nadav Rotem wrote: > Author: nadav > Date: Sun Oct 16 15:31:33 2011 > New Revision: 142152 > > URL: http://llvm.org/viewvc/llvm-project?rev=142152&view=rev > Log: > Enable element promotion type legalization by deafault. > Changed tests which assumed that vectors are legalized by widening them. This change appears to be causing a miscompile for http://llvm.org/viewvc/llvm-project/clang-tests/trunk/gcc-4_2-testsuite/src/gcc.c-torture/execute/pr23135.c?view=markup . Please take a look. -Eli > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp > llvm/trunk/test/CodeGen/ARM/vrev.ll > llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll > llvm/trunk/test/CodeGen/CellSPU/shuffles.ll > llvm/trunk/test/CodeGen/CellSPU/v2i32.ll > llvm/trunk/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll > llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll > llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll > llvm/trunk/test/CodeGen/X86/mmx-pinsrw.ll > llvm/trunk/test/CodeGen/X86/mmx-vzmovl-2.ll > llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll > llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll > llvm/trunk/test/CodeGen/X86/vsplit-and.ll > llvm/trunk/test/CodeGen/X86/widen_arith-1.ll > llvm/trunk/test/CodeGen/X86/widen_arith-2.ll > llvm/trunk/test/CodeGen/X86/widen_arith-3.ll > llvm/trunk/test/CodeGen/X86/widen_cast-1.ll > llvm/trunk/test/CodeGen/X86/widen_cast-4.ll > llvm/trunk/test/CodeGen/X86/widen_conv-1.ll > llvm/trunk/test/CodeGen/X86/widen_conv-4.ll > llvm/trunk/test/CodeGen/X86/widen_load-0.ll > llvm/trunk/test/CodeGen/X86/widen_load-2.ll > llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll > llvm/trunk/test/CodeGen/X86/x86-shifts.ll > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sun Oct 16 15:31:33 2011 > @@ -36,7 +36,7 @@ > /// - the promotion of vector elements. This feature is disabled by default > /// and only enabled using this flag. > static cl::opt > -AllowPromoteIntElem("promote-elements", cl::Hidden, > +AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true), > cl::desc("Allow promotion of integer vector element types")); > > namespace llvm { > > Modified: llvm/trunk/test/CodeGen/ARM/vrev.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/vrev.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/vrev.ll Sun Oct 16 15:31:33 2011 > @@ -150,9 +150,6 @@ > > ; vrev <4 x i16> should use VREV32 and not VREV64 > define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { > -; CHECK: test_vrev64: > -; CHECK: vext.16 > -; CHECK: vrev32.16 > entry: > %0 = bitcast <4 x i16>* %source to <8 x i16>* > %tmp2 = load <8 x i16>* %0, align 4 > > Modified: llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll (original) > +++ llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll Sun Oct 16 15:31:33 2011 > @@ -1,12 +1,12 @@ > ; RUN: llc < %s -march=cellspu > %t1.s > ; RUN: grep {shlh } %t1.s | count 10 > ; RUN: grep {shlhi } %t1.s | count 3 > -; RUN: grep {shl } %t1.s | count 11 > +; RUN: grep {shl } %t1.s | count 10 > ; RUN: grep {shli } %t1.s | count 3 > ; RUN: grep {xshw } %t1.s | count 5 > -; RUN: grep {and } %t1.s | count 14 > -; RUN: grep {andi } %t1.s | count 2 > -; RUN: grep {rotmi } %t1.s | count 2 > +; RUN: grep {and } %t1.s | count 15 > +; RUN: grep {andi } %t1.s | count 4 > +; RUN: grep {rotmi } %t1.s | count 4 > ; RUN: grep {rotqmbyi } %t1.s | count 1 > ; RUN: grep {rotqmbii } %t1.s | count 2 > ; RUN: grep {rotqmby } %t1.s | count 1 > > Modified: llvm/trunk/test/CodeGen/CellSPU/shuffles.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/shuffles.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/CellSPU/shuffles.ll (original) > +++ llvm/trunk/test/CodeGen/CellSPU/shuffles.ll Sun Oct 16 15:31:33 2011 > @@ -1,12 +1,14 @@ > ; RUN: llc -O1 --march=cellspu < %s | FileCheck %s > > +;CHECK: shuffle > define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) { > ; CHECK: cwd {{\$.}}, 0($sp) > ; CHECK: shufb {{\$., \$4, \$3, \$.}} > %val= shufflevector <4 x float> %param1, <4 x float> %param2, <4 x i32> > ret <4 x float> %val > } > - > + > +;CHECK: splat > define <4 x float> @splat(float %param1) { > ; CHECK: lqa > ; CHECK: shufb $3 > @@ -16,6 +18,7 @@ > ret <4 x float> %val > } > > +;CHECK: test_insert > define void @test_insert( <2 x float>* %ptr, float %val1, float %val2 ) { > %sl2_17_tmp1 = insertelement <2 x float> zeroinitializer, float %val1, i32 0 > ;CHECK: lqa $6, > @@ -31,6 +34,7 @@ > ret void > } > > +;CHECK: test_insert_1 > define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) { > ;CHECK: cwd $5, 4($sp) > ;CHECK: shufb $3, $4, $3, $5 > @@ -39,6 +43,7 @@ > ret <4 x float> %rv > } > > +;CHECK: test_v2i32 > define <2 x i32> @test_v2i32(<4 x i32>%vec) > { > ;CHECK: rotqbyi $3, $3, 4 > @@ -49,17 +54,14 @@ > > define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec) > { > -;CHECK: rotqbyi $3, $3, 8 > -;CHECK: bi $lr > %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, > <4 x i32> > ret <4 x i32> %rv > } > > +;CHECK: test_v4i32_rot4 > define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec) > { > -;CHECK: rotqbyi $3, $3, 4 > -;CHECK: bi $lr > %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, > <4 x i32> > ret <4 x i32> %rv > > Modified: llvm/trunk/test/CodeGen/CellSPU/v2i32.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/v2i32.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/CellSPU/v2i32.ll (original) > +++ llvm/trunk/test/CodeGen/CellSPU/v2i32.ll Sun Oct 16 15:31:33 2011 > @@ -9,7 +9,8 @@ > > define %vec @test_add(%vec %param) > { > -;CHECK: a {{\$.}}, $3, $3 > +;CHECK: shufb > +;CHECK: addx > %1 = add %vec %param, %param > ;CHECK: bi $lr > ret %vec %1 > @@ -17,21 +18,14 @@ > > define %vec @test_sub(%vec %param) > { > -;CHECK: sf {{\$.}}, $4, $3 > %1 = sub %vec %param, > - > ;CHECK: bi $lr > ret %vec %1 > } > > define %vec @test_mul(%vec %param) > { > -;CHECK: mpyu > -;CHECK: mpyh > -;CHECK: a {{\$., \$., \$.}} > -;CHECK: a {{\$., \$., \$.}} > %1 = mul %vec %param, %param > - > ;CHECK: bi $lr > ret %vec %1 > } > @@ -56,22 +50,12 @@ > > define void @test_store( %vec %val, %vec* %ptr) > { > -;CHECK: stqd $3, 0(${{.}}) > -;CHECK: bi $lr > store %vec %val, %vec* %ptr > ret void > } > > -;Alignment of <2 x i32> is not *directly* defined in the ABI > -;It probably is safe to interpret it as an array, thus having 8 byte > -;alignment (according to ABI). This tests that the size of > -;[2 x <2 x i32>] is 16 bytes, i.e. there is no padding between the > -;two arrays > define <2 x i32>* @test_alignment( [2 x <2 x i32>]* %ptr) > { > -; CHECK-NOT: ai $3, $3, 16 > -; CHECK: ai $3, $3, 8 > -; CHECK: bi $lr > %rv = getelementptr [2 x <2 x i32>]* %ptr, i32 0, i32 1 > ret <2 x i32>* %rv > } > > Modified: llvm/trunk/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll Sun Oct 16 15:31:33 2011 > @@ -1,5 +1,5 @@ > -; RUN: llc < %s -march=x86 -mattr=+sse2 -mattr=+mmx | grep unpcklpd > -; RUN: llc < %s -march=x86 -mattr=+sse2 -mattr=+mmx | grep unpckhpd > +; RUN: llc < %s -march=x86 -mattr=+sse2 -mattr=+mmx | not grep unpcklpd > +; RUN: llc < %s -march=x86 -mattr=+sse2 -mattr=+mmx | not grep unpckhpd > ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep cvttpd2pi | count 1 > ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep cvtpi2pd | count 1 > ; originally from PR2687, but things don't work that way any more. > > Modified: llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll Sun Oct 16 15:31:33 2011 > @@ -1,6 +1,6 @@ > ; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 > %t1 > ; RUN: grep movzwl %t1 | count 2 > -; RUN: grep movzbl %t1 | count 2 > +; RUN: grep movzbl %t1 | count 1 > ; RUN: grep movd %t1 | count 4 > > define <4 x i16> @a(i32* %x1) nounwind { > > Modified: llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll Sun Oct 16 15:31:33 2011 > @@ -1,32 +1,35 @@ > ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s > ; There are no MMX operations here, so we use XMM or i64. > > +; CHECK: ti8 > define void @ti8(double %a, double %b) nounwind { > entry: > %tmp1 = bitcast double %a to <8 x i8> > %tmp2 = bitcast double %b to <8 x i8> > %tmp3 = add <8 x i8> %tmp1, %tmp2 > -; CHECK: paddb %xmm1, %xmm0 > +; CHECK: paddw > store <8 x i8> %tmp3, <8 x i8>* null > ret void > } > > +; CHECK: ti16 > define void @ti16(double %a, double %b) nounwind { > entry: > %tmp1 = bitcast double %a to <4 x i16> > %tmp2 = bitcast double %b to <4 x i16> > %tmp3 = add <4 x i16> %tmp1, %tmp2 > -; CHECK: paddw %xmm1, %xmm0 > +; CHECK: paddd > store <4 x i16> %tmp3, <4 x i16>* null > ret void > } > > +; CHECK: ti32 > define void @ti32(double %a, double %b) nounwind { > entry: > %tmp1 = bitcast double %a to <2 x i32> > %tmp2 = bitcast double %b to <2 x i32> > %tmp3 = add <2 x i32> %tmp1, %tmp2 > -; CHECK: paddd %xmm1, %xmm0 > +; CHECK: paddq > store <2 x i32> %tmp3, <2 x i32>* null > ret void > } > @@ -55,6 +58,7 @@ > ret void > } > > +; CHECK: ti16a > define void @ti16a(double %a, double %b) nounwind { > entry: > %tmp1 = bitcast double %a to x86_mmx > @@ -66,6 +70,7 @@ > ret void > } > > +; CHECK: ti32a > define void @ti32a(double %a, double %b) nounwind { > entry: > %tmp1 = bitcast double %a to x86_mmx > @@ -77,6 +82,7 @@ > ret void > } > > +; CHECK: ti64a > define void @ti64a(double %a, double %b) nounwind { > entry: > %tmp1 = bitcast double %a to x86_mmx > > Modified: llvm/trunk/test/CodeGen/X86/mmx-pinsrw.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-pinsrw.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/mmx-pinsrw.ll (original) > +++ llvm/trunk/test/CodeGen/X86/mmx-pinsrw.ll Sun Oct 16 15:31:33 2011 > @@ -1,4 +1,4 @@ > -; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | grep pinsrw | count 1 > +; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | grep pinsr > ; PR2562 > > external global i16 ; :0 [#uses=1] > > Modified: llvm/trunk/test/CodeGen/X86/mmx-vzmovl-2.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-vzmovl-2.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/mmx-vzmovl-2.ll (original) > +++ llvm/trunk/test/CodeGen/X86/mmx-vzmovl-2.ll Sun Oct 16 15:31:33 2011 > @@ -1,6 +1,5 @@ > -; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | grep pxor > -; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | grep punpckldq > - > +; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | grep pxor | count 1 > +; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | grep punpcklqdq | count 1 > %struct.vS1024 = type { [8 x <4 x i32>] } > %struct.vS512 = type { [4 x <4 x i32>] } > > > Modified: llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll (original) > +++ llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll Sun Oct 16 15:31:33 2011 > @@ -3,9 +3,10 @@ > ; Verify when widening a divide/remainder operation, we only generate a > ; divide/rem per element since divide/remainder can trap. > > +; CHECK: vectorDiv > define void @vectorDiv (<2 x i32> addrspace(1)* %nsource, <2 x i32> addrspace(1)* %dsource, <2 x i32> addrspace(1)* %qdest) nounwind { > -; CHECK: idivl > -; CHECK: idivl > +; CHECK: idivq > +; CHECK: idivq > ; CHECK-NOT: idivl > ; CHECK: ret > entry: > @@ -32,6 +33,7 @@ > ret void > } > > +; CHECK: test_char_div > define <3 x i8> @test_char_div(<3 x i8> %num, <3 x i8> %div) { > ; CHECK: idivb > ; CHECK: idivb > @@ -42,6 +44,7 @@ > ret <3 x i8> %div.r > } > > +; CHECK: test_char_div > define <3 x i8> @test_uchar_div(<3 x i8> %num, <3 x i8> %div) { > ; CHECK: divb > ; CHECK: divb > @@ -52,6 +55,7 @@ > ret <3 x i8> %div.r > } > > +; CHECK: test_short_div > define <5 x i16> @test_short_div(<5 x i16> %num, <5 x i16> %div) { > ; CHECK: idivw > ; CHECK: idivw > @@ -64,17 +68,19 @@ > ret <5 x i16> %div.r > } > > +; CHECK: test_ushort_div > define <4 x i16> @test_ushort_div(<4 x i16> %num, <4 x i16> %div) { > -; CHECK: divw > -; CHECK: divw > -; CHECK: divw > -; CHECK: divw > -; CHECK-NOT: divw > +; CHECK: divl > +; CHECK: divl > +; CHECK: divl > +; CHECK: divl > +; CHECK-NOT: divl > ; CHECK: ret > %div.r = udiv <4 x i16> %num, %div > ret <4 x i16> %div.r > } > > +; CHECK: test_uint_div > define <3 x i32> @test_uint_div(<3 x i32> %num, <3 x i32> %div) { > ; CHECK: divl > ; CHECK: divl > @@ -85,6 +91,7 @@ > ret <3 x i32> %div.r > } > > +; CHECK: test_long_div > define <3 x i64> @test_long_div(<3 x i64> %num, <3 x i64> %div) { > ; CHECK: idivq > ; CHECK: idivq > @@ -95,6 +102,7 @@ > ret <3 x i64> %div.r > } > > +; CHECK: test_ulong_div > define <3 x i64> @test_ulong_div(<3 x i64> %num, <3 x i64> %div) { > ; CHECK: divq > ; CHECK: divq > @@ -105,18 +113,19 @@ > ret <3 x i64> %div.r > } > > - > +; CHECK: test_char_rem > define <4 x i8> @test_char_rem(<4 x i8> %num, <4 x i8> %rem) { > -; CHECK: idivb > -; CHECK: idivb > -; CHECK: idivb > -; CHECK: idivb > -; CHECK-NOT: idivb > +; CHECK: idivl > +; CHECK: idivl > +; CHECK: idivl > +; CHECK: idivl > +; CHECK-NOT: idivl > ; CHECK: ret > %rem.r = srem <4 x i8> %num, %rem > ret <4 x i8> %rem.r > } > > +; CHECK: test_short_rem > define <5 x i16> @test_short_rem(<5 x i16> %num, <5 x i16> %rem) { > ; CHECK: idivw > ; CHECK: idivw > @@ -129,6 +138,7 @@ > ret <5 x i16> %rem.r > } > > +; CHECK: test_uint_rem > define <4 x i32> @test_uint_rem(<4 x i32> %num, <4 x i32> %rem) { > ; CHECK: idivl > ; CHECK: idivl > @@ -141,6 +151,7 @@ > } > > > +; CHECK: test_ulong_rem > define <5 x i64> @test_ulong_rem(<5 x i64> %num, <5 x i64> %rem) { > ; CHECK: divq > ; CHECK: divq > @@ -153,6 +164,7 @@ > ret <5 x i64> %rem.r > } > > +; CHECK: test_int_div > define void @test_int_div(<3 x i32>* %dest, <3 x i32>* %old, i32 %n) { > ; CHECK: idivl > ; CHECK: idivl > > Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll (original) > +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll Sun Oct 16 15:31:33 2011 > @@ -26,10 +26,10 @@ > > define void @t02(<8 x i32>* %source, <2 x i32>* %dest) nounwind noinline { > entry: > -; CHECK: movaps 32({{%rdi|%rcx}}), %xmm0 > -; CHECK-NEXT: movaps 48({{%rdi|%rcx}}), %xmm1 > -; CHECK-NEXT: movss %xmm1, %xmm0 > -; CHECK-NEXT: movq %xmm0, ({{%rsi|%rdx}}) > +; CHECK: movl 36({{%rdi|%rcx}}) > +; CHECK-NEXT: movl 48({{%rdi|%rcx}}) > +; CHECK: punpcklqdq > +; CHECK: movq %xmm0, ({{%rsi|%rdx}}) > %0 = bitcast <8 x i32>* %source to <4 x i32>* > %arrayidx = getelementptr inbounds <4 x i32>* %0, i64 3 > %tmp2 = load <4 x i32>* %arrayidx, align 16 > > Modified: llvm/trunk/test/CodeGen/X86/vsplit-and.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vsplit-and.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/vsplit-and.ll (original) > +++ llvm/trunk/test/CodeGen/X86/vsplit-and.ll Sun Oct 16 15:31:33 2011 > @@ -2,7 +2,7 @@ > > > define void @t(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind readonly { > -; CHECK: andb > +; CHECK: pandn > %cmp1 = icmp ne <2 x i64> %src1, zeroinitializer > %cmp2 = icmp ne <2 x i64> %src2, zeroinitializer > %t1 = and <2 x i1> %cmp1, %cmp2 > @@ -12,7 +12,7 @@ > } > > define void @t2(<3 x i64>* %dst, <3 x i64> %src1, <3 x i64> %src2) nounwind readonly { > -; CHECK: andb > +; CHECK-NOT: pandn > %cmp1 = icmp ne <3 x i64> %src1, zeroinitializer > %cmp2 = icmp ne <3 x i64> %src2, zeroinitializer > %t1 = and <3 x i1> %cmp1, %cmp2 > > Modified: llvm/trunk/test/CodeGen/X86/widen_arith-1.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-1.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_arith-1.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_arith-1.ll Sun Oct 16 15:31:33 2011 > @@ -1,12 +1,10 @@ > ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s > > -; Widen a v3i8 to v16i8 to use a vector add > - > define void @update(<3 x i8>* %dst, <3 x i8>* %src, i32 %n) nounwind { > entry: > ; CHECK-NOT: pextrw > -; CHECK: paddb > -; CHECK: pextrb > +; CHECK: add > + > %dst.addr = alloca <3 x i8>* ; <<3 x i8>**> [#uses=2] > %src.addr = alloca <3 x i8>* ; <<3 x i8>**> [#uses=2] > %n.addr = alloca i32 ; [#uses=2] > > Modified: llvm/trunk/test/CodeGen/X86/widen_arith-2.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-2.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_arith-2.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_arith-2.ll Sun Oct 16 15:31:33 2011 > @@ -1,5 +1,5 @@ > ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s > -; CHECK: paddb > +; CHECK: padd > ; CHECK: pand > > ; widen v8i8 to v16i8 (checks even power of 2 widening with add & and) > > Modified: llvm/trunk/test/CodeGen/X86/widen_arith-3.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-3.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_arith-3.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_arith-3.ll Sun Oct 16 15:31:33 2011 > @@ -1,7 +1,8 @@ > ; RUN: llc < %s -march=x86 -mattr=+sse42 -post-RA-scheduler=true | FileCheck %s > -; CHECK: paddw > -; CHECK: pextrw > -; CHECK: movd > +; CHECK: incw > +; CHECK: incl > +; CHECK: incl > +; CHECK: addl > > ; Widen a v3i16 to v8i16 to do a vector add > > > Modified: llvm/trunk/test/CodeGen/X86/widen_cast-1.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_cast-1.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_cast-1.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_cast-1.ll Sun Oct 16 15:31:33 2011 > @@ -1,5 +1,5 @@ > ; RUN: llc -march=x86 -mattr=+sse42 < %s | FileCheck %s > -; CHECK: paddw > +; CHECK: paddd > ; CHECK: pextrd > ; CHECK: movd > > > Modified: llvm/trunk/test/CodeGen/X86/widen_cast-4.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_cast-4.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_cast-4.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_cast-4.ll Sun Oct 16 15:31:33 2011 > @@ -1,16 +1,6 @@ > ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > -; CHECK: sarb > - > -; v8i8 that is widen to v16i8 then split > -; FIXME: This is widen to v16i8 and split to 16 and we then rebuild the vector. > -; Unfortunately, we don't split the store so we don't get the code we want. > +; CHECK: psraw > +; CHECK: psraw > > define void @update(i64* %dst_i, i64* %src_i, i32 %n) nounwind { > entry: > > Modified: llvm/trunk/test/CodeGen/X86/widen_conv-1.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_conv-1.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_conv-1.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_conv-1.ll Sun Oct 16 15:31:33 2011 > @@ -1,6 +1,5 @@ > ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s > -; CHECK: pshufd > -; CHECK: paddd > +; CHECK: paddq > > ; truncate v2i64 to v2i32 > > > Modified: llvm/trunk/test/CodeGen/X86/widen_conv-4.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_conv-4.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_conv-4.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_conv-4.ll Sun Oct 16 15:31:33 2011 > @@ -1,5 +1,5 @@ > ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s > -; CHECK: cvtsi2ss > +; CHECK-NOT: cvtsi2ss > > ; unsigned to float v7i16 to v7f32 > > > Modified: llvm/trunk/test/CodeGen/X86/widen_load-0.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_load-0.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_load-0.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_load-0.ll Sun Oct 16 15:31:33 2011 > @@ -4,15 +4,15 @@ > > ; Both loads should happen before either store. > > -; CHECK: movl (%rdi), %[[R1:...]] > -; CHECK: movl (%rsi), %[[R2:...]] > -; CHECK: movl %[[R2]], (%rdi) > -; CHECK: movl %[[R1]], (%rsi) > +; CHECK: movd (%rsi), {{.*}} > +; CHECK: movd (%rdi), {{.*}} > +; CHECK: movd {{.*}}, (%rdi) > +; CHECK: movd {{.*}}, (%rsi) > > -; WIN64: movl (%rcx), %[[R1:...]] > -; WIN64: movl (%rdx), %[[R2:...]] > -; WIN64: movl %[[R2]], (%rcx) > -; WIN64: movl %[[R1]], (%rdx) > +; WIN64: movd (%rdx), {{.*}} > +; WIN64: movd (%rcx), {{.*}} > +; WIN64: movd {{.*}}, (%rcx) > +; WIN64: movd {{.*}}, (%rdx) > > define void @short2_int_swap(<2 x i16>* nocapture %b, i32* nocapture %c) nounwind { > entry: > > Modified: llvm/trunk/test/CodeGen/X86/widen_load-2.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_load-2.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_load-2.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_load-2.ll Sun Oct 16 15:31:33 2011 > @@ -4,6 +4,7 @@ > ; > > %i32vec3 = type <3 x i32> > +; CHECK: add3i32 > define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { > ; CHECK: movdqa > ; CHECK: paddd > @@ -16,6 +17,7 @@ > ret void > } > > +; CHECK: add3i32_2 > define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { > ; CHECK: movq > ; CHECK: pinsrd > @@ -32,6 +34,7 @@ > } > > %i32vec7 = type <7 x i32> > +; CHECK: add7i32 > define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) { > ; CHECK: movdqa > ; CHECK: movdqa > @@ -47,6 +50,7 @@ > ret void > } > > +; CHECK: add12i32 > %i32vec12 = type <12 x i32> > define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) { > ; CHECK: movdqa > @@ -66,12 +70,14 @@ > } > > > +; CHECK: add3i16 > %i16vec3 = type <3 x i16> > define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind { > -; CHECK: movdqa > -; CHECK: paddw > -; CHECK: movd > -; CHECK: pextrw > +; CHECK: add3i16 > +; CHECK: addl > +; CHECK: addl > +; CHECK: addl > +; CHECK: ret > %a = load %i16vec3* %ap, align 16 > %b = load %i16vec3* %bp, align 16 > %x = add %i16vec3 %a, %b > @@ -79,10 +85,11 @@ > ret void > } > > +; CHECK: add4i16 > %i16vec4 = type <4 x i16> > define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind { > -; CHECK: movdqa > -; CHECK: paddw > +; CHECK: add4i16 > +; CHECK: paddd > ; CHECK: movq > %a = load %i16vec4* %ap, align 16 > %b = load %i16vec4* %bp, align 16 > @@ -91,6 +98,7 @@ > ret void > } > > +; CHECK: add12i16 > %i16vec12 = type <12 x i16> > define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind { > ; CHECK: movdqa > @@ -106,6 +114,7 @@ > ret void > } > > +; CHECK: add18i16 > %i16vec18 = type <18 x i16> > define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind { > ; CHECK: movdqa > @@ -125,12 +134,13 @@ > } > > > +; CHECK: add3i8 > %i8vec3 = type <3 x i8> > define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind { > -; CHECK: movdqa > -; CHECK: paddb > -; CHECK: pextrb > -; CHECK: movb > +; CHECK: addb > +; CHECK: addb > +; CHECK: addb > +; CHECK: ret > %a = load %i8vec3* %ap, align 16 > %b = load %i8vec3* %bp, align 16 > %x = add %i8vec3 %a, %b > @@ -138,6 +148,7 @@ > ret void > } > > +; CHECK: add31i8: > %i8vec31 = type <31 x i8> > define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind { > ; CHECK: movdqa > @@ -147,6 +158,7 @@ > ; CHECK: movq > ; CHECK: pextrb > ; CHECK: pextrw > +; CHECK: ret > %a = load %i8vec31* %ap, align 16 > %b = load %i8vec31* %bp, align 16 > %x = add %i8vec31 %a, %b > @@ -155,9 +167,10 @@ > } > > > +; CHECK: rot > %i8vec3pack = type { <3 x i8>, i8 } > define %i8vec3pack @rot() nounwind { > -; CHECK: shrb > +; CHECK: shrl > entry: > %X = alloca %i8vec3pack, align 4 > %rot = alloca %i8vec3pack, align 4 > > Modified: llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll (original) > +++ llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll Sun Oct 16 15:31:33 2011 > @@ -50,7 +50,7 @@ > ; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS > define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone { > ; CHECK: shuf4: > -; CHECK: punpckldq > +; CHECK-NOT: punpckldq > %vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> > ret <8 x i8> %vshuf > } > > Modified: llvm/trunk/test/CodeGen/X86/x86-shifts.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-shifts.ll?rev=142152&r1=142151&r2=142152&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/x86-shifts.ll (original) > +++ llvm/trunk/test/CodeGen/X86/x86-shifts.ll Sun Oct 16 15:31:33 2011 > @@ -124,7 +124,7 @@ > define <2 x i32> @shl2_other(<2 x i32> %A) nounwind { > entry: > ; CHECK: shl2_other > -; CHECK-not: psllq > +; CHECK: psllq > %B = shl <2 x i32> %A, < i32 2, i32 2> > %C = shl <2 x i32> %A, < i32 9, i32 9> > %K = xor <2 x i32> %B, %C > @@ -134,7 +134,7 @@ > define <2 x i32> @shr2_other(<2 x i32> %A) nounwind { > entry: > ; CHECK: shr2_other > -; CHECK-NOT: psrlq > +; CHECK: psrlq > %B = lshr <2 x i32> %A, < i32 8, i32 8> > %C = lshr <2 x i32> %A, < i32 1, i32 1> > %K = xor <2 x i32> %B, %C > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From anton at korobeynikov.info Tue Oct 18 07:19:19 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Tue, 18 Oct 2011 16:19:19 +0400 Subject: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ In-Reply-To: <6594DDFF12B03D4E89690887C248699402A2C888AA@hasmsx504.ger.corp.intel.com> References: <20111016203133.CC4E13128018@llvm.org> <1B579157-F0E8-45FB-A8E8-3D520ED36FC0@mac.com> <84BE87AB-7185-4CF6-B0F4-D242762AA4A0@mac.com> <6594DDFF12B03D4E89690887C248699402A2C887C6@hasmsx504.ger.corp.intel.com> <32320A16-378C-4390-A51B-241396859284@mac.com> <6594DDFF12B03D4E89690887C248699402A2C888AA@hasmsx504.ger.corp.intel.com> Message-ID: Hi Nadav, > I discussed the legalization of <2 x i16> stores on ARM with Anton. As you mentioned, i16 is illegal on ARM and it is not possible to scalarize the store in the Legalizer. > This was the main reason for moving the legalization of vector memory ops into LegalizeVectorOps. Well, this is completely different story. Your question was about trunc-stores, but here it seems to prevent important codegen sequence. > I agree that in some cases promoting the elements in the vector is less efficient than widening the number of elements. ?However, generally ?promotion? is a better strategy. ?I am mostly interested in code-generation of auto-vectorized IR. ?What workloads are you mostly interested in ? Maybe we can discuss the needed optimizations for these workloads. On NEON you can do pretty efficient vector manipulations via shuffles (e.g. any shuffle of 4 elements can be codegen'ed in 5 or less instructions, usually 2-3). This is really important for ARM. In the meantime I'd suggest you adding target-specific "vector select strategy" flag, so target can choose how to deal with all the stuff and make sure your code is disabled for e.g. ARM and CellSPU. --- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From baldrick at free.fr Tue Oct 18 07:44:00 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 18 Oct 2011 12:44:00 -0000 Subject: [llvm-commits] [llvm] r142350 - in /llvm/trunk/lib: CodeGen/SelectionDAG/LegalizeVectorOps.cpp CodeGen/SelectionDAG/SelectionDAG.cpp CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Target/ARM/ARMISelLowering.cpp Target/X86/X86FrameLowering.cpp Target/X86/X86ISelLowering.cpp Message-ID: <20111018124400.BB56C3128034@llvm.org> Author: baldrick Date: Tue Oct 18 07:44:00 2011 New Revision: 142350 URL: http://llvm.org/viewvc/llvm-project?rev=142350&view=rev Log: Fix a bunch of unused variable warnings when doing a release build with gcc-4.6. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=142350&r1=142349&r2=142350&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Tue Oct 18 07:44:00 2011 @@ -384,7 +384,6 @@ // Implement VSELECT in terms of XOR, AND, OR // on platforms which do not support blend natively. EVT VT = Op.getOperand(0).getValueType(); - EVT OVT = Op.getOperand(1).getValueType(); DebugLoc DL = Op.getDebugLoc(); SDValue Mask = Op.getOperand(0); @@ -398,7 +397,8 @@ !TLI.isOperationLegalOrCustom(ISD::OR, VT)) return DAG.UnrollVectorOp(Op.getNode()); - assert(VT.getSizeInBits() == OVT.getSizeInBits() && "Invalid mask size"); + assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits() + && "Invalid mask size"); // Bitcast the operands to be the same type as the mask. // This is needed when we select between FP types because // the mask is a vector of integers. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=142350&r1=142349&r2=142350&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Oct 18 07:44:00 2011 @@ -2800,6 +2800,7 @@ EVT.getVectorNumElements() == VT.getVectorNumElements()) && "Vector element counts must match in FP_ROUND_INREG"); assert(EVT.bitsLE(VT) && "Not rounding down!"); + (void)EVT; if (cast(N2)->getVT() == VT) return N1; // Not actually rounding. break; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=142350&r1=142349&r2=142350&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Oct 18 07:44:00 2011 @@ -2474,7 +2474,7 @@ size_t numCmps = Clusterify(Cases, SI); DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() << ". Total compares: " << numCmps << '\n'); - numCmps = 0; + (void)numCmps; // Get the Value to be switched on and default basic blocks, which will be // inserted into CaseBlock records, representing basic blocks in the binary Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142350&r1=142349&r2=142350&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Oct 18 07:44:00 2011 @@ -4902,9 +4902,9 @@ static void ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl& Results, SelectionDAG &DAG, unsigned NewOp) { - EVT T = Node->getValueType(0); DebugLoc dl = Node->getDebugLoc(); - assert (T == MVT::i64 && "Only know how to expand i64 atomics"); + assert (Node->getValueType(0) == MVT::i64 && + "Only know how to expand i64 atomics"); SmallVector Ops; Ops.push_back(Node->getOperand(0)); // Chain Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=142350&r1=142349&r2=142350&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Tue Oct 18 07:44:00 2011 @@ -1113,9 +1113,7 @@ // Skip the saved EBP. Offset += RI->getSlotSize(); } else { - unsigned Align = MFI->getObjectAlignment(FI); - assert((-(Offset + StackSize)) % Align == 0); - Align = 0; + assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0); return Offset + StackSize; } // FIXME: Support tail calls @@ -1267,7 +1265,7 @@ true); assert(FrameIdx == MFI->getObjectIndexBegin() && "Slot for EBP register must be last in order to be found!"); - FrameIdx = 0; + (void)FrameIdx; } } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=142350&r1=142349&r2=142350&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Oct 18 07:44:00 2011 @@ -1753,6 +1753,7 @@ // places. assert(VA.getValNo() != LastVal && "Don't support value assigned to multiple locs yet"); + (void)LastVal; LastVal = VA.getValNo(); if (VA.isRegLoc()) { @@ -10476,9 +10477,9 @@ void X86TargetLowering:: ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl&Results, SelectionDAG &DAG, unsigned NewOp) const { - EVT T = Node->getValueType(0); DebugLoc dl = Node->getDebugLoc(); - assert (T == MVT::i64 && "Only know how to expand i64 atomics"); + assert (Node->getValueType(0) == MVT::i64 && + "Only know how to expand i64 atomics"); SDValue Chain = Node->getOperand(0); SDValue In1 = Node->getOperand(1); From baldrick at free.fr Tue Oct 18 07:45:46 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 18 Oct 2011 12:45:46 -0000 Subject: [llvm-commits] [dragonegg] r142351 - /dragonegg/trunk/src/Types.cpp Message-ID: <20111018124546.D4CAC3128034@llvm.org> Author: baldrick Date: Tue Oct 18 07:45:46 2011 New Revision: 142351 URL: http://llvm.org/viewvc/llvm-project?rev=142351&view=rev Log: Silence an unused parameter warning when doing a release build with gcc-4.6. Modified: dragonegg/trunk/src/Types.cpp Modified: dragonegg/trunk/src/Types.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Types.cpp?rev=142351&r1=142350&r2=142351&view=diff ============================================================================== --- dragonegg/trunk/src/Types.cpp (original) +++ dragonegg/trunk/src/Types.cpp Tue Oct 18 07:45:46 2011 @@ -388,6 +388,7 @@ } #endif + (void)type; return Ty; } From justin.holewinski at gmail.com Tue Oct 18 08:39:20 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Tue, 18 Oct 2011 13:39:20 -0000 Subject: [llvm-commits] [llvm] r142352 - in /llvm/trunk: lib/Target/PTX/PTXInstrInfo.td test/CodeGen/PTX/mad-disabling.ll Message-ID: <20111018133920.DD3693128034@llvm.org> Author: jholewinski Date: Tue Oct 18 08:39:20 2011 New Revision: 142352 URL: http://llvm.org/viewvc/llvm-project?rev=142352&view=rev Log: PTX: Fix disabling of MAD instruction selection Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td llvm/trunk/test/CodeGen/PTX/mad-disabling.ll Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=142352&r1=142351&r2=142352&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Tue Oct 18 08:39:20 2011 @@ -885,19 +885,26 @@ // FMUL+FADD def : Pat<(f32 (fadd (fmul RegF32:$a, RegF32:$b), RegF32:$c)), - (FMADrrr32 RndDefault, RegF32:$a, RegF32:$b, RegF32:$c)>; + (FMADrrr32 RndDefault, RegF32:$a, RegF32:$b, RegF32:$c)>, + Requires<[SupportsFMA]>; def : Pat<(f32 (fadd (fmul RegF32:$a, RegF32:$b), fpimm:$c)), - (FMADrri32 RndDefault, RegF32:$a, RegF32:$b, fpimm:$c)>; + (FMADrri32 RndDefault, RegF32:$a, RegF32:$b, fpimm:$c)>, + Requires<[SupportsFMA]>; def : Pat<(f32 (fadd (fmul RegF32:$a, fpimm:$b), fpimm:$c)), - (FMADrrr32 RndDefault, RegF32:$a, fpimm:$b, fpimm:$c)>; + (FMADrrr32 RndDefault, RegF32:$a, fpimm:$b, fpimm:$c)>, + Requires<[SupportsFMA]>; def : Pat<(f32 (fadd (fmul RegF32:$a, RegF32:$b), fpimm:$c)), - (FMADrri32 RndDefault, RegF32:$a, RegF32:$b, fpimm:$c)>; + (FMADrri32 RndDefault, RegF32:$a, RegF32:$b, fpimm:$c)>, + Requires<[SupportsFMA]>; def : Pat<(f64 (fadd (fmul RegF64:$a, RegF64:$b), RegF64:$c)), - (FMADrrr64 RndDefault, RegF64:$a, RegF64:$b, RegF64:$c)>; + (FMADrrr64 RndDefault, RegF64:$a, RegF64:$b, RegF64:$c)>, + Requires<[SupportsFMA]>; def : Pat<(f64 (fadd (fmul RegF64:$a, RegF64:$b), fpimm:$c)), - (FMADrri64 RndDefault, RegF64:$a, RegF64:$b, fpimm:$c)>; + (FMADrri64 RndDefault, RegF64:$a, RegF64:$b, fpimm:$c)>, + Requires<[SupportsFMA]>; def : Pat<(f64 (fadd (fmul RegF64:$a, fpimm:$b), fpimm:$c)), - (FMADrri64 RndDefault, RegF64:$a, fpimm:$b, fpimm:$c)>; + (FMADrri64 RndDefault, RegF64:$a, fpimm:$b, fpimm:$c)>, + Requires<[SupportsFMA]>; // FNEG def : Pat<(f32 (fneg RegF32:$a)), (FNEGrr32 RndDefault, RegF32:$a)>; Modified: llvm/trunk/test/CodeGen/PTX/mad-disabling.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mad-disabling.ll?rev=142352&r1=142351&r2=142352&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PTX/mad-disabling.ll (original) +++ llvm/trunk/test/CodeGen/PTX/mad-disabling.ll Tue Oct 18 08:39:20 2011 @@ -1,8 +1,13 @@ -; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20 | grep "mad" -; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20,+no-fma | grep -v "mad" +; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20 | FileCheck %s -check-prefix=FMA +; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20,+no-fma | FileCheck %s -check-prefix=MUL +; RUN: llc < %s -march=ptx64 -mattr=+ptx20,+sm20 | FileCheck %s -check-prefix=FMA +; RUN: llc < %s -march=ptx64 -mattr=+ptx20,+sm20,+no-fma | FileCheck %s -check-prefix=MUL define ptx_device float @test_mul_add_f(float %x, float %y, float %z) { entry: +; FMA: mad.rn.f32 +; MUL: mul.rn.f32 +; MUL: add.rn.f32 %a = fmul float %x, %y %b = fadd float %a, %z ret float %b @@ -10,6 +15,9 @@ define ptx_device double @test_mul_add_d(double %x, double %y, double %z) { entry: +; FMA: mad.rn.f64 +; MUL: mul.rn.f64 +; MUL: add.rn.f64 %a = fmul double %x, %y %b = fadd double %a, %z ret double %b From justin.holewinski at gmail.com Tue Oct 18 08:47:28 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Tue, 18 Oct 2011 09:47:28 -0400 Subject: [llvm-commits] [LLVM3.0] Patch to fix FMA instruction selection Message-ID: Attached is a patch to fix the disabling of multiply-add instructions in the PTX back-end. This bug was discovered by Dan Bailey, and fixes an issue that is present in the LLVM 3.0 branch. Can this be committed to the LLVM 3.0 release branch? The fix has already been applied to LLVM ToT in r142352. -- Thanks, Justin Holewinski -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111018/ad2d00d5/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-core_606.patch Type: text/x-patch Size: 3268 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111018/ad2d00d5/attachment.bin From grosbach at apple.com Tue Oct 18 11:18:11 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 18 Oct 2011 16:18:11 -0000 Subject: [llvm-commits] [llvm] r142356 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-mov-encoding.s test/MC/ARM/neont2-mov-encoding.s utils/TableGen/EDEmitter.cpp Message-ID: <20111018161811.F2E3F3128034@llvm.org> Author: grosbach Date: Tue Oct 18 11:18:11 2011 New Revision: 142356 URL: http://llvm.org/viewvc/llvm-project?rev=142356&view=rev Log: ARM assembly parsing and encoding for VMOV.i64. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/neon-mov-encoding.s llvm/trunk/test/MC/ARM/neont2-mov-encoding.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142356&r1=142355&r2=142356&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 18 11:18:11 2011 @@ -39,6 +39,11 @@ let PrintMethod = "printNEONModImmOperand"; let ParserMatchClass = nImmVMOVI32AsmOperand; } +def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; } +def nImmSplatI64 : Operand { + let PrintMethod = "printNEONModImmOperand"; + let ParserMatchClass = nImmSplatI64AsmOperand; +} def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; } def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; } @@ -4372,11 +4377,11 @@ } def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmSplatI64:$SIMM), IIC_VMOVImm, "vmov", "i64", "$Vd, $SIMM", "", [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>; def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd), - (ins nModImm:$SIMM), IIC_VMOVImm, + (ins nImmSplatI64:$SIMM), IIC_VMOVImm, "vmov", "i64", "$Vd, $SIMM", "", [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>; } // isReMaterializable Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=142356&r1=142355&r2=142356&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Oct 18 11:18:11 2011 @@ -966,6 +966,19 @@ (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); } + bool isNEONi64splat() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + // Must be a constant. + if (!CE) return false; + uint64_t Value = CE->getValue(); + // i64 value with each byte being either 0 or 0xff. + for (unsigned i = 0; i < 8; ++i) + if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; + return true; + } + void addExpr(MCInst &Inst, const MCExpr *Expr) const { // Add as immediates when possible. Null MCExpr = 0. if (Expr == 0) @@ -1536,6 +1549,18 @@ Inst.addOperand(MCOperand::CreateImm(Value)); } + void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + // The immediate encodes the type of constant as well as the value. + const MCConstantExpr *CE = dyn_cast(getImm()); + uint64_t Value = CE->getValue(); + unsigned Imm = 0; + for (unsigned i = 0; i < 8; ++i, Value >>= 8) { + Imm |= (Value & 1) << i; + } + Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); + } + virtual void print(raw_ostream &OS) const; static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.s?rev=142356&r1=142355&r2=142356&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mov-encoding.s Tue Oct 18 11:18:11 2011 @@ -9,7 +9,7 @@ vmov.i32 d16, #0x20000000 vmov.i32 d16, #0x20FF vmov.i32 d16, #0x20FFFF -@ vmov.i64 d16, #0xFF0000FF0000FFFF + vmov.i64 d16, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] @ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] @@ -20,7 +20,7 @@ @ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] @ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] @ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] -@ FIXME: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] +@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] @@ -33,7 +33,7 @@ vmov.i32 q8, #0x20000000 vmov.i32 q8, #0x20FF vmov.i32 q8, #0x20FFFF -@ vmov.i64 q8, #0xFF0000FF0000FFFF + vmov.i64 q8, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2] @ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] @@ -44,7 +44,7 @@ @ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] @ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] @ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] -@ FIXME: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] +@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] vmvn.i16 d16, #0x10 vmvn.i16 d16, #0x1000 Modified: llvm/trunk/test/MC/ARM/neont2-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mov-encoding.s?rev=142356&r1=142355&r2=142356&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mov-encoding.s Tue Oct 18 11:18:11 2011 @@ -11,7 +11,7 @@ vmov.i32 d16, #0x20000000 vmov.i32 d16, #0x20FF vmov.i32 d16, #0x20FFFF -@ vmov.i64 d16, #0xFF0000FF0000FFFF + vmov.i64 d16, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 d16, #0x8 @ encoding: [0xc0,0xef,0x18,0x0e] @ CHECK: vmov.i16 d16, #0x10 @ encoding: [0xc1,0xef,0x10,0x08] @@ -22,7 +22,7 @@ @ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x10,0x06] @ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x10,0x0c] @ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x10,0x0d] -@ FIXME: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x33,0x0e] +@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x33,0x0e] vmov.i8 q8, #0x8 @@ -34,7 +34,7 @@ vmov.i32 q8, #0x20000000 vmov.i32 q8, #0x20FF vmov.i32 q8, #0x20FFFF -@ vmov.i64 q8, #0xFF0000FF0000FFFF + vmov.i64 q8, #0xFF0000FF0000FFFF @ CHECK: vmov.i8 q8, #0x8 @ encoding: [0xc0,0xef,0x58,0x0e] @ CHECK: vmov.i16 q8, #0x10 @ encoding: [0xc1,0xef,0x50,0x08] @@ -45,7 +45,7 @@ @ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0xc2,0xef,0x50,0x06] @ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0xc2,0xef,0x50,0x0c] @ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0xc2,0xef,0x50,0x0d] -@ FIXME: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x73,0x0e] +@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x73,0x0e] vmvn.i16 d16, #0x10 Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=142356&r1=142355&r2=142356&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Oct 18 11:18:11 2011 @@ -600,6 +600,7 @@ IMM("nImmSplatI8"); IMM("nImmSplatI16"); IMM("nImmSplatI32"); + IMM("nImmSplatI64"); IMM("nImmVMOVI32"); IMM("imm0_7"); IMM("imm0_15"); From grosbach at apple.com Tue Oct 18 11:24:57 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 18 Oct 2011 09:24:57 -0700 Subject: [llvm-commits] [llvm] r142337 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMFrameLowering.cpp lib/Target/ARM/Thumb1FrameLowering.cpp test/CodeGen/ARM/thumb1-dynrealign.ll In-Reply-To: <20111018052800.70B9A2A6C12C@llvm.org> References: <20111018052800.70B9A2A6C12C@llvm.org> Message-ID: Nice! -j On Oct 17, 2011, at 10:28 PM, Chad Rosier wrote: > Author: mcrosier > Date: Tue Oct 18 00:28:00 2011 > New Revision: 142337 > > URL: http://llvm.org/viewvc/llvm-project?rev=142337&view=rev > Log: > Add support for dynamic stack realignment when in thumb1 mode. > rdar://10288916 > > Added: > llvm/trunk/test/CodeGen/ARM/thumb1-dynrealign.ll > Modified: > llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp > llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp > llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=142337&r1=142336&r2=142337&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Oct 18 00:28:00 2011 > @@ -626,13 +626,10 @@ > > bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { > const MachineFrameInfo *MFI = MF.getFrameInfo(); > - const ARMFunctionInfo *AFI = MF.getInfo(); > // We can't realign the stack if: > // 1. Dynamic stack realignment is explicitly disabled, > - // 2. This is a Thumb1 function (it's not useful, so we don't bother), or > - // 3. There are VLAs in the function and the base pointer is disabled. > - return (RealignStack && !AFI->isThumb1OnlyFunction() && > - (!MFI->hasVarSizedObjects() || EnableBasePointer)); > + // 2. There are VLAs in the function and the base pointer is disabled. > + return (RealignStack && (!MFI->hasVarSizedObjects() || EnableBasePointer)); > } > > bool ARMBaseRegisterInfo:: > > Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=142337&r1=142336&r2=142337&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Tue Oct 18 00:28:00 2011 > @@ -881,10 +881,12 @@ > // for sure what the stack size will be, but for this, an estimate is good > // enough. If there anything changes it, it'll be a spill, which implies > // we've used all the registers and so R4 is already used, so not marking > - // it here will be OK. > + // it here will be OK. Also spill R4 if Thumb1 function requires stack > + // realignment. > // FIXME: It will be better just to find spare register here. > unsigned StackSize = estimateStackSize(MF); > - if (MFI->hasVarSizedObjects() || StackSize > 508) > + if (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF) || > + StackSize > 508) > MF.getRegInfo().setPhysRegUsed(ARM::R4); > } > > > Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=142337&r1=142336&r2=142337&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original) > +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Tue Oct 18 00:28:00 2011 > @@ -155,10 +155,32 @@ > AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); > AFI->setDPRCalleeSavedAreaSize(DPRCSSize); > > - // Thumb1 does not currently support dynamic stack realignment. Report a > - // fatal error rather then silently generate bad code. > - if (RegInfo->needsStackRealignment(MF)) > - report_fatal_error("Dynamic stack realignment not supported for thumb1."); > + // If we need dynamic stack realignment, do it here. Be paranoid and make > + // sure if we also have VLAs, we have a base pointer for frame access. > + if (RegInfo->needsStackRealignment(MF)) { > + // We cannot use sp as source/dest register here, thus we're emitting the > + // following sequence: > + // mov r4, sp > + // lsrs r4, r4, Log2MaxAlign > + // lsls r4, r4, Log2MaxAlign > + // mov sp, r4 > + unsigned MaxAlign = MFI->getMaxAlignment(); > + unsigned Log2MaxAlign = Log2_32(MaxAlign); > + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) > + .addReg(ARM::SP, RegState::Kill)); > + AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), > + ARM::R4)) > + .addReg(ARM::R4, RegState::Kill) > + .addImm(Log2MaxAlign)); > + AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), > + ARM::R4)) > + .addReg(ARM::R4, RegState::Kill) > + .addImm(Log2MaxAlign)); > + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) > + .addReg(ARM::R4, RegState::Kill)); > + > + AFI->setShouldRestoreSPFromFP(true); > + } > > // If we need a base pointer, set it up here. It's whatever the value > // of the stack pointer is at this point. Any variable size objects > > Added: llvm/trunk/test/CodeGen/ARM/thumb1-dynrealign.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb1-dynrealign.ll?rev=142337&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/thumb1-dynrealign.ll (added) > +++ llvm/trunk/test/CodeGen/ARM/thumb1-dynrealign.ll Tue Oct 18 00:28:00 2011 > @@ -0,0 +1,40 @@ > +; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s > + > +; Normal load from SP > +define void @SP(i32 %i) nounwind uwtable ssp { > +entry: > +; CHECK: @SP > +; CHECK: push {r7, lr} > +; CHECK-NEXT: mov r7, sp > +; CHECK-NEXT: sub sp, #4 > +; CHECK-NEXT: mov r1, sp > +; CHECK-NEXT: str r0, [r1] > +; CHECK-NEXT: mov r0, sp > +; CHECK-NEXT: blx _SP_ > +; CHECK-NEXT: add sp, #4 > +; CHECK-NEXT: pop {r7, pc} > + %i.addr = alloca i32, align 4 > + store i32 %i, i32* %i.addr, align 4 > + call void @SP_(i32* %i.addr) > + ret void > +} > + > +declare void @SP_(i32*) > + > +; Dynamic stack realignment > +define void @FP(double %a) nounwind uwtable ssp { > +entry: > +; CHECK: mov r4, sp > +; CHECK-NEXT: lsrs r4, r4, #3 > +; CHECK-NEXT: lsls r4, r4, #3 > +; CHECK-NEXT: mov sp, r4 > +; Restore from FP > +; CHECK: subs r4, r7, #4 > +; CHECK: mov sp, r4 > + %a.addr = alloca double, align 8 > + store double %a, double* %a.addr, align 8 > + call void @FP_(double* %a.addr) > + ret void > +} > + > +declare void @FP_(double*) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From cdavis at mymail.mines.edu Tue Oct 18 11:36:44 2011 From: cdavis at mymail.mines.edu (Charles Davis) Date: Tue, 18 Oct 2011 10:36:44 -0600 Subject: [llvm-commits] [PATCH] Fix compiling source files in subdirectories with autoconf In-Reply-To: <4E9D34FF.6040001@free.fr> References: <8963C7C2-E230-4BB3-B0EC-F0ABB529E95A@mymail.mines.edu> <4E9D34FF.6040001@free.fr> Message-ID: <0B972CF2-93FD-485E-80D1-2E9386D8D8E3@mymail.mines.edu> On Oct 18, 2011, at 2:12 AM, Duncan Sands wrote: > Hi Charles, > >> This patch fixes an issue with source files located in subdirectories (relative to the Makefile referencing them). The build system was not creating those directories in the build tree, which caused compiling the sources to fail. This patch fixes that. I encountered this getting the LLDB Host library and LLDB debug server to compile from Makefiles. > > your patch has a bunch of changes to lib/Target/X86 in it. I presume > that was an accident? Yeah. Here's a fixed patch. Chip -------------- next part -------------- A non-text attachment was scrubbed... Name: source-subdir-fix.patch Type: application/octet-stream Size: 9919 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111018/ec80b27f/attachment-0001.obj From david_dean at apple.com Tue Oct 18 11:36:28 2011 From: david_dean at apple.com (David Dean) Date: Tue, 18 Oct 2011 16:36:28 -0000 Subject: [llvm-commits] [zorg] r142358 - /zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Message-ID: <20111018163628.7B5A53128034@llvm.org> Author: ddean Date: Tue Oct 18 11:36:28 2011 New Revision: 142358 URL: http://llvm.org/viewvc/llvm-project?rev=142358&view=rev Log: Add additional logging to gcc test suites Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=142358&r1=142357&r2=142358&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Tue Oct 18 11:36:28 2011 @@ -362,7 +362,8 @@ command=["make", "-k", "check-%s" % lang] + make_vars, description="gcc-4_2-testsuite (%s)" % lang, workdir='clang-tests/gcc-4_2-testsuite', - logfiles={ 'dg.sum' : 'obj/%s/%s.sum' % (lang, lang) }, + logfiles={ 'dg.sum' : 'obj/%s/%s.sum' % (lang, lang), + '%s.log' % lang : 'obj/%s/%s.log' % (lang, lang)}, ignore=gcc_dg_ignores.get(lang, []))) def addClangGDBTests(f, ignores={}, install_prefix="%(builddir)s/llvm.install"): From resistor at mac.com Tue Oct 18 11:51:48 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 18 Oct 2011 09:51:48 -0700 Subject: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ In-Reply-To: References: <20111016203133.CC4E13128018@llvm.org> <1B579157-F0E8-45FB-A8E8-3D520ED36FC0@mac.com> <84BE87AB-7185-4CF6-B0F4-D242762AA4A0@mac.com> <6594DDFF12B03D4E89690887C248699402A2C887C6@hasmsx504.ger.corp.intel.com> <32320A16-378C-4390-A51B-241396859284@mac.com> <6594DDFF12B03D4E89690887C248699402A2C888AA@hasmsx504.ger.corp.intel.com> Message-ID: <3B17D92A-B302-4439-9A05-7DABE3AAF8BB@mac.com> On Oct 18, 2011, at 5:19 AM, Anton Korobeynikov wrote: > Hi Nadav, > >> I discussed the legalization of <2 x i16> stores on ARM with Anton. As you mentioned, i16 is illegal on ARM and it is not possible to scalarize the store in the Legalizer. >> This was the main reason for moving the legalization of vector memory ops into LegalizeVectorOps. > Well, this is completely different story. Your question was about > trunc-stores, but here it seems to prevent important codegen sequence. > >> I agree that in some cases promoting the elements in the vector is less efficient than widening the number of elements. However, generally ?promotion? is a better strategy. I am mostly interested in code-generation of auto-vectorized IR. What workloads are you mostly interested in ? Maybe we can discuss the needed optimizations for these workloads. > On NEON you can do pretty efficient vector manipulations via shuffles > (e.g. any shuffle of 4 elements can be codegen'ed in 5 or less > instructions, usually 2-3). This is really important for ARM. > > In the meantime I'd suggest you adding target-specific "vector select > strategy" flag, so target can choose how to deal with all the stuff > and make sure your code is disabled for e.g. ARM and CellSPU. I had an extended discussion with Dan about this yesterday, and we came to two conclusions: 1) The particular testcase in question is really weird, and probably isn't a great representative of code we care about. As long as we don't generate something completely braindead for it, we're OK with it being regressed if this is an overall win. 2) Determining a policy for vector-widening vs. element-widening is really, really hard, and also context dependent. In this particular case, we want to widen the vector because a later immutable use (the store) is expressed in terms of i16's. However, it's easy to imagine other circumstances where the later use would prefer the element-widening approach. --Owen From dpatel at apple.com Tue Oct 18 12:03:46 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 18 Oct 2011 17:03:46 -0000 Subject: [llvm-commits] [test-suite] r142362 - in /test-suite/trunk: TEST.dbgopt.Makefile TEST.dbgopt.report Message-ID: <20111018170346.BBED63128034@llvm.org> Author: dpatel Date: Tue Oct 18 12:03:46 2011 New Revision: 142362 URL: http://llvm.org/viewvc/llvm-project?rev=142362&view=rev Log: Add report description for dbgopt. Added: test-suite/trunk/TEST.dbgopt.report Modified: test-suite/trunk/TEST.dbgopt.Makefile Modified: test-suite/trunk/TEST.dbgopt.Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.dbgopt.Makefile?rev=142362&r1=142361&r2=142362&view=diff ============================================================================== --- test-suite/trunk/TEST.dbgopt.Makefile (original) +++ test-suite/trunk/TEST.dbgopt.Makefile Tue Oct 18 12:03:46 2011 @@ -22,10 +22,15 @@ -S ${PROJ_SRC_DIR}/$*.c -o Output/$*.first.s -$(LLVMCC) $(CPPFLAGS) $(CFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -Os \ -fno-verbose-asm -S ${PROJ_SRC_DIR}/$*.c -o Output/$*.second.s + echo "---------------------------------------------------------------" \ + > Output/$*.dbgopt.report.txt; \ + echo ">>> ========= '$*' Program" >> Output/$*.dbgopt.report.txt; \ + echo "---------------------------------------------------------------\n"\ + >> Output/$*.dbgopt.report.txt; @-if diff Output/$*.first.s Output/$*.second.s > $@; then \ - echo "--------- TEST-PASS: $*" > Output/$*.dbgopt.report.txt; \ + echo "TEST: PASS" >> Output/$*.dbgopt.report.txt; \ else \ - echo "--------- TEST-FAIL: $*" > Output/$*.dbgopt.report.txt; \ + echo "TEST: FAIL" >> Output/$*.dbgopt.report.txt; \ fi Output/%.s: %.cpp Output/.dir $(INCLUDES) @@ -34,10 +39,15 @@ -S ${PROJ_SRC_DIR}/$*.cpp -o Output/$*.first.s -$(LLVMCC) $(CPPFLAGS) $(CFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -Os -S \ -fno-verbose-asm ${PROJ_SRC_DIR}/$*.cpp -o Output/$*.second.s + echo "---------------------------------------------------------------" \ + > Output/$*.dbgopt.report.txt; \ + echo ">>> ========= '$*' Program" >> Output/$*.dbgopt.report.txt; \ + echo "---------------------------------------------------------------\n"\ + >> Output/$*.dbgopt.report.txt; @-if diff Output/$*.first.s Output/$*.second.s > $@; then \ - echo "--------- TEST-PASS: $*" > Output/$*.dbgopt.report.txt; \ + echo "TEST: PASS" >> Output/$*.dbgopt.report.txt; \ else \ - echo "--------- TEST-FAIL: $*" > Output/$*.dbgopt.report.txt; \ + echo "TEST: FAIL" >> Output/$*.dbgopt.report.txt; \ fi Output/%.s: %.cc Output/.dir $(INCLUDES) @@ -46,10 +56,15 @@ -S ${PROJ_SRC_DIR}/$*.cc -o Output/$*.first.s -$(LLVMCC) $(CPPFLAGS) $(CFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -Os -S \ -fno-verbose-asm ${PROJ_SRC_DIR}/$*.cc -o Output/$*.second.s + echo "---------------------------------------------------------------" \ + > Output/$*.dbgopt.report.txt; \ + echo ">>> ========= '$*' Program" >> Output/$*.dbgopt.report.txt; \ + echo "---------------------------------------------------------------\n"\ + >> Output/$*.dbgopt.report.txt; @-if diff Output/$*.first.s Output/$*.second.s > $@; then \ - echo "--------- TEST-PASS: $*" > Output/$*.dbgopt.report.txt; \ + echo "TEST: PASS" >> Output/$*.dbgopt.report.txt; \ else \ - echo "--------- TEST-FAIL: $*" > Output/$*.dbgopt.report.txt; \ + echo "TEST: FAIL" >> Output/$*.dbgopt.report.txt; \ fi Output/%.s: %.m Output/.dir $(INCLUDES) @@ -58,10 +73,15 @@ -S ${PROJ_SRC_DIR}/$*.m -o Output/$*.first.s -$(LLVMCC) $(CFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -Os -S \ -fno-verbose-asm ${PROJ_SRC_DIR}/$*.m -o Output/$*.second.s + echo "---------------------------------------------------------------" \ + > Output/$*.dbgopt.report.txt; \ + echo ">>> ========= '$*' Program" >> Output/$*.dbgopt.report.txt; \ + echo "---------------------------------------------------------------\n"\ + >> Output/$*.dbgopt.report.txt; @-if diff Output/$*.first.s Output/$*.second.s > $@; then \ - echo "--------- TEST-PASS: $*" > Output/$*.dbgopt.report.txt; \ + echo "TEST: PASS" >> Output/$*.dbgopt.report.txt; \ else \ - echo "--------- TEST-FAIL: $*" > Output/$*.dbgopt.report.txt; \ + echo "TEST: FAIL" >> Output/$*.dbgopt.report.txt; \ fi Output/%.s: %.mm Output/.dir $(INCLUDES) @@ -70,10 +90,15 @@ -S ${PROJ_SRC_DIR}/$*.mm -o Output/$*.first.s -$(LLVMCC) $(CPPFLAGS) $(CFLAGS) $(LOPTFLAGS) $(X_TARGET_FLAGS) -Os -S \ -fno-verbose-asm ${PROJ_SRC_DIR}/$*.mm -o Output/$*.second.s + echo "---------------------------------------------------------------" \ + > Output/$*.dbgopt.report.txt; \ + echo ">>> ========= '$*' Program" >> Output/$*.dbgopt.report.txt; \ + echo "---------------------------------------------------------------\n"\ + >> Output/$*.dbgopt.report.txt; @-if diff Output/$*.first.s Output/$*.second.s > $@; then \ - echo "--------- TEST-PASS: $*" > Output/$*.dbgopt.report.txt; \ + echo "TEST: PASS" >> Output/$*.dbgopt.report.txt; \ else \ - echo "--------- TEST-FAIL: $*" > Output/$*.dbgopt.report.txt; \ + echo "TEST: FAIL" >> Output/$*.dbgopt.report.txt; \ fi Asms := $(sort $(addsuffix .s, $(notdir $(basename $(Source))))) Added: test-suite/trunk/TEST.dbgopt.report URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.dbgopt.report?rev=142362&view=auto ============================================================================== --- test-suite/trunk/TEST.dbgopt.report (added) +++ test-suite/trunk/TEST.dbgopt.report Tue Oct 18 12:03:46 2011 @@ -0,0 +1,16 @@ +##=== TEST.dbgopt.report - Report description for dbgopt -------*- perl -*-===## +# +# This file defines a report to be generated for TEST=dbgopt tests. +# +##===----------------------------------------------------------------------===## + + +# These are the columns for the report. The first entry is the header for the +# column, the second is the regex to use to match the value. Empty list create +# separators, and closures may be put in for custom processing. +( +# Name + ["Program" , '\'([^\']+)\' Program'], + [], + ["Result" , 'TEST: (PASS|FAIL)'] +); From grosbach at apple.com Tue Oct 18 12:09:36 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 18 Oct 2011 17:09:36 -0000 Subject: [llvm-commits] [llvm] r142363 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20111018170936.25EBB3128034@llvm.org> Author: grosbach Date: Tue Oct 18 12:09:35 2011 New Revision: 142363 URL: http://llvm.org/viewvc/llvm-project?rev=142363&view=rev Log: Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=142363&r1=142362&r2=142363&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Oct 18 12:09:35 2011 @@ -1695,6 +1695,8 @@ let Inst{14-12} = 0b000; let Inst{7-4} = 0b0000; } +def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm, + pred:$p, zero_reg)>; def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm, pred:$p, CPSR)>; def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm, From grosbach at apple.com Tue Oct 18 12:16:30 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 18 Oct 2011 17:16:30 -0000 Subject: [llvm-commits] [llvm] r142365 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20111018171630.C28153128034@llvm.org> Author: grosbach Date: Tue Oct 18 12:16:30 2011 New Revision: 142365 URL: http://llvm.org/viewvc/llvm-project?rev=142365&view=rev Log: ARM vqdmlal assembly parsing for the lane index operand. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142365&r1=142364&r2=142365&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 18 12:16:30 2011 @@ -2265,9 +2265,9 @@ ValueType ResTy, ValueType OpTy, Intrinsic IntOp> : N3VLane16 Author: grosbach Date: Tue Oct 18 12:22:53 2011 New Revision: 142367 URL: http://llvm.org/viewvc/llvm-project?rev=142367&view=rev Log: Tidy up formatting. Modified: llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s Modified: llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s?rev=142367&r1=142366&r2=142367&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s Tue Oct 18 12:22:53 2011 @@ -1,66 +1,82 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] vmla.i8 d16, d18, d17 -@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] vmla.i16 d16, d18, d17 -@ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf2] vmla.i32 d16, d18, d17 -@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2] vmla.f32 d16, d18, d17 -@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf2] vmla.i8 q9, q8, q10 -@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf2] vmla.i16 q9, q8, q10 -@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2] vmla.i32 q9, q8, q10 -@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2] vmla.f32 q9, q8, q10 -@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf2] + +@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] +@ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf2] +@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2] +@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf2] +@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf2] +@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2] +@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2] + + vmlal.s8 q8, d19, d18 -@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf2] vmlal.s16 q8, d19, d18 -@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf2] vmlal.s32 q8, d19, d18 -@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf3] vmlal.u8 q8, d19, d18 -@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf3] vmlal.u16 q8, d19, d18 -@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf3] vmlal.u32 q8, d19, d18 -@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xf2] + +@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf2] +@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf2] +@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf2] +@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf3] +@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf3] +@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf3] + + vqdmlal.s16 q8, d19, d18 -@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xf2] vqdmlal.s32 q8, d19, d18 -@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3] + +@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xf2] +@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xf2] + + vmls.i8 d16, d18, d17 -@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3] vmls.i16 d16, d18, d17 -@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3] vmls.i32 d16, d18, d17 -@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xf2] vmls.f32 d16, d18, d17 -@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf3] vmls.i8 q9, q8, q10 -@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf3] vmls.i16 q9, q8, q10 -@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3] vmls.i32 q9, q8, q10 -@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xf2] vmls.f32 q9, q8, q10 -@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf2] + +@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3] +@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3] +@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3] +@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xf2] +@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf3] +@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf3] +@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3] +@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xf2] + + vmlsl.s8 q8, d19, d18 -@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf2] vmlsl.s16 q8, d19, d18 -@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf2] vmlsl.s32 q8, d19, d18 -@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf3] vmlsl.u8 q8, d19, d18 -@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf3] vmlsl.u16 q8, d19, d18 -@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf3] vmlsl.u32 q8, d19, d18 -@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2] + +@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf2] +@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf2] +@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf2] +@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf3] +@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf3] +@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf3] + + vqdmlsl.s16 q8, d19, d18 -@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2] vqdmlsl.s32 q8, d19, d18 + +@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2] +@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2] From grosbach at apple.com Tue Oct 18 12:23:34 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 18 Oct 2011 17:23:34 -0000 Subject: [llvm-commits] [llvm] r142368 - in /llvm/trunk/test/MC/ARM: neon-mul-accum-encoding.s neont2-mul-accum-encoding.s Message-ID: <20111018172334.931B73128034@llvm.org> Author: grosbach Date: Tue Oct 18 12:23:34 2011 New Revision: 142368 URL: http://llvm.org/viewvc/llvm-project?rev=142368&view=rev Log: Tests for 142365. Modified: llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Modified: llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s?rev=142368&r1=142367&r2=142368&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.s Tue Oct 18 12:23:34 2011 @@ -36,9 +36,17 @@ vqdmlal.s16 q8, d19, d18 vqdmlal.s32 q8, d19, d18 + vqdmlal.s16 q11, d11, d7[0] + vqdmlal.s16 q11, d11, d7[1] + vqdmlal.s16 q11, d11, d7[2] + vqdmlal.s16 q11, d11, d7[3] @ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xf2] @ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xf2] +@ CHECK: vqdmlal.s16 q11, d11, d7[0] @ encoding: [0x47,0x63,0xdb,0xf2] +@ CHECK: vqdmlal.s16 q11, d11, d7[1] @ encoding: [0x4f,0x63,0xdb,0xf2] +@ CHECK: vqdmlal.s16 q11, d11, d7[2] @ encoding: [0x67,0x63,0xdb,0xf2] +@ CHECK: vqdmlal.s16 q11, d11, d7[3] @ encoding: [0x6f,0x63,0xdb,0xf2] vmls.i8 d16, d18, d17 Modified: llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s?rev=142368&r1=142367&r2=142368&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Tue Oct 18 12:23:34 2011 @@ -38,9 +38,17 @@ vqdmlal.s16 q8, d19, d18 vqdmlal.s32 q8, d19, d18 + vqdmlal.s16 q11, d11, d7[0] + vqdmlal.s16 q11, d11, d7[1] + vqdmlal.s16 q11, d11, d7[2] + vqdmlal.s16 q11, d11, d7[3] @ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x09] @ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x09] +@ CHECK: vqdmlal.s16 q11, d11, d7[0] @ encoding: [0xdb,0xef,0x47,0x63] +@ CHECK: vqdmlal.s16 q11, d11, d7[1] @ encoding: [0xdb,0xef,0x4f,0x63] +@ CHECK: vqdmlal.s16 q11, d11, d7[2] @ encoding: [0xdb,0xef,0x67,0x63] +@ CHECK: vqdmlal.s16 q11, d11, d7[3] @ encoding: [0xdb,0xef,0x6f,0x63] vmls.i8 d16, d18, d17 From isanbard at gmail.com Tue Oct 18 12:27:12 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 18 Oct 2011 17:27:12 -0000 Subject: [llvm-commits] [llvm] r142369 - /llvm/trunk/utils/release/test-release.sh Message-ID: <20111018172712.EFB733524005@llvm.org> Author: void Date: Tue Oct 18 12:27:12 2011 New Revision: 142369 URL: http://llvm.org/viewvc/llvm-project?rev=142369&view=rev Log: Don't exit just because some early commands fail. Use the -k flag when running the checks. Modified: llvm/trunk/utils/release/test-release.sh Modified: llvm/trunk/utils/release/test-release.sh URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/test-release.sh?rev=142369&r1=142368&r2=142369&view=diff ============================================================================== --- llvm/trunk/utils/release/test-release.sh (original) +++ llvm/trunk/utils/release/test-release.sh Tue Oct 18 12:27:12 2011 @@ -12,8 +12,6 @@ # #===------------------------------------------------------------------------===# -set -e # Exit if any command fails - projects="llvm cfe dragonegg test-suite" # Base SVN URL for the sources. @@ -265,13 +263,15 @@ ObjDir="$3" cd $ObjDir - make check-all \ + make -k check-all \ 2>&1 | tee $LogDir/llvm.check-Phase$Phase-$Flavor.log - make unittests \ + make -k unittests \ 2>&1 | tee $LogDir/llvm.unittests-Phase$Phase-$Flavor.log cd $BuildDir } +set -e # Exit if any command fails + if [ "$do_checkout" = "yes" ]; then export_sources fi @@ -368,6 +368,8 @@ done ) 2>&1 | tee $LogDir/testing.$Release-rc$RC.log +set +e + # Woo hoo! echo "### Testing Finished ###" echo "### Logs: $LogDir" From bob.wilson at apple.com Tue Oct 18 12:34:47 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 18 Oct 2011 17:34:47 -0000 Subject: [llvm-commits] [llvm] r142370 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/ARM/vector-DAGCombine.ll Message-ID: <20111018173447.E45C23524002@llvm.org> Author: bwilson Date: Tue Oct 18 12:34:47 2011 New Revision: 142370 URL: http://llvm.org/viewvc/llvm-project?rev=142370&view=rev Log: Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS. svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands with illegal types, even before type legalization. For this testcase, that led to one BUILD_VECTOR with i16 operands and another with promoted i32 operands, which triggered the assertion. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=142370&r1=142369&r2=142370&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Oct 18 12:34:47 2011 @@ -7261,8 +7261,19 @@ } EVT VT = LHSOp.getValueType(); - assert(RHSOp.getValueType() == VT && - "SimplifyVBinOp with different BUILD_VECTOR element types"); + EVT RVT = RHSOp.getValueType(); + if (RVT != VT) { + // Integer BUILD_VECTOR operands may have types larger than the element + // size (e.g., when the element type is not legal). Prior to type + // legalization, the types may not match between the two BUILD_VECTORS. + // Truncate one of the operands to make them match. + if (RVT.getSizeInBits() > VT.getSizeInBits()) { + RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); + } else { + LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); + VT = RVT; + } + } SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, LHSOp, RHSOp); if (FoldOp.getOpcode() != ISD::UNDEF && Modified: llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll?rev=142370&r1=142369&r2=142370&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll Tue Oct 18 12:34:47 2011 @@ -123,3 +123,13 @@ ret void } +; The following test was hitting an assertion in the DAG combiner when +; constant folding the multiply because the "sext undef" was translated to +; a BUILD_VECTOR with i32 0 operands, which did not match the i16 operands +; of the other BUILD_VECTOR. +define i16 @foldBuildVectors() { + %1 = sext <8 x i8> undef to <8 x i16> + %2 = mul <8 x i16> %1, + %3 = extractelement <8 x i16> %2, i32 0 + ret i16 %3 +} From bob.wilson at apple.com Tue Oct 18 12:34:51 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 18 Oct 2011 17:34:51 -0000 Subject: [llvm-commits] [llvm] r142371 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vmul.ll Message-ID: <20111018173451.C65DA3524002@llvm.org> Author: bwilson Date: Tue Oct 18 12:34:51 2011 New Revision: 142371 URL: http://llvm.org/viewvc/llvm-project?rev=142371&view=rev Log: Fix incorrect check for sign-extended constant BUILD_VECTOR. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/test/CodeGen/ARM/vmul.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142371&r1=142370&r2=142371&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Oct 18 12:34:51 2011 @@ -4527,7 +4527,7 @@ unsigned HalfSize = EltSize / 2; if (isSigned) { int64_t SExtVal = C->getSExtValue(); - if ((SExtVal >> HalfSize) != (SExtVal >> EltSize)) + if (SExtVal != SExtVal << (64 - HalfSize) >> (64 - HalfSize)) return false; } else { if ((C->getZExtValue() >> HalfSize) != 0) Modified: llvm/trunk/test/CodeGen/ARM/vmul.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmul.ll?rev=142371&r1=142370&r2=142371&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmul.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vmul.ll Tue Oct 18 12:34:51 2011 @@ -514,3 +514,14 @@ store <8 x i8> %10, <8 x i8>* %11, align 8 ret void } + +; If one operand has a zero-extend and the other a sign-extend, vmull +; cannot be used. +define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) { +; CHECK: vmullWithInconsistentExtensions +; CHECK-NOT: vmull.s8 + %1 = sext <8 x i8> %vec to <8 x i16> + %2 = mul <8 x i16> %1, + %3 = extractelement <8 x i16> %2, i32 0 + ret i16 %3 +} From resistor at mac.com Tue Oct 18 12:50:23 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 18 Oct 2011 17:50:23 -0000 Subject: [llvm-commits] [llvm] r142377 - in /llvm/trunk/test/MC/ARM: neont2-mul-accum-encoding.s neont2-mul-encoding.s Message-ID: <20111018175023.151983128034@llvm.org> Author: resistor Date: Tue Oct 18 12:50:22 2011 New Revision: 142377 URL: http://llvm.org/viewvc/llvm-project?rev=142377&view=rev Log: Add several FIXME cases for ARM encodings. Modified: llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Modified: llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s?rev=142377&r1=142376&r2=142377&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Tue Oct 18 12:50:22 2011 @@ -90,3 +90,8 @@ @ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x0b] @ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x0b] + +@ vmla.i32 q12, q8, d3[0] +@ FIXME: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80] +@ vmlal.s32 q0, d5, d10[0] +@ FIXME: vmlal.s32 q0, d5, d10[0] @ encoding: [0xa5,0xef,0x4a,0x02] Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-encoding.s?rev=142377&r1=142376&r2=142377&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Tue Oct 18 12:50:22 2011 @@ -56,3 +56,12 @@ vqdmull.s16 q8, d16, d17 @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d] vqdmull.s32 q8, d16, d17 + +@ FIXME: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80] +@ vmla.i32 q12, q8, d3[0] +@ FIXME: vqdmulh.s16 d11, d2, d3[0] @ encoding: [0x92,0xef,0x43,0xbc] +@ vqdmulh.s16 d11, d2, d3[0] +@ FIXME: vmul.i16 d18, d8, d0[3] @ encoding: [0xd8,0xef,0x68,0x28] +@ vmul.i16 d18, d8, d0[3] + + From bruno.cardoso at gmail.com Tue Oct 18 12:50:36 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 18 Oct 2011 17:50:36 -0000 Subject: [llvm-commits] [llvm] r142378 - in /llvm/trunk/lib/Target/Mips: CMakeLists.txt Makefile MipsCodeEmitter.cpp MipsCondMov.td MipsInstrFPU.td MipsInstrFormats.td MipsInstrInfo.td Message-ID: <20111018175036.41BDB3128034@llvm.org> Author: bruno Date: Tue Oct 18 12:50:36 2011 New Revision: 142378 URL: http://llvm.org/viewvc/llvm-project?rev=142378&view=rev Log: Final patch that completes old JIT support for Mips: -Fix binary codes and rename operands in .td files so that automatically generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct encoding for instructions. -Define new class FMem for instructions that access memory. -Define new class FFRGPR for instructions that move data between GPR and FPU general and control registers. -Define custom encoder methods for memory operands, and also for size operands of ext and ins instructions. -Only static relocation model is currently implemented. Patch by Sasa Stankovic Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt llvm/trunk/lib/Target/Mips/Makefile llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp llvm/trunk/lib/Target/Mips/MipsCondMov.td llvm/trunk/lib/Target/Mips/MipsInstrFPU.td llvm/trunk/lib/Target/Mips/MipsInstrFormats.td llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=142378&r1=142377&r2=142378&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Tue Oct 18 12:50:36 2011 @@ -2,6 +2,7 @@ llvm_tablegen(MipsGenRegisterInfo.inc -gen-register-info) llvm_tablegen(MipsGenInstrInfo.inc -gen-instr-info) +llvm_tablegen(MipsGenCodeEmitter.inc -gen-emitter) llvm_tablegen(MipsGenAsmWriter.inc -gen-asm-writer) llvm_tablegen(MipsGenDAGISel.inc -gen-dag-isel) llvm_tablegen(MipsGenCallingConv.inc -gen-callingconv) Modified: llvm/trunk/lib/Target/Mips/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Makefile?rev=142378&r1=142377&r2=142378&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Makefile (original) +++ llvm/trunk/lib/Target/Mips/Makefile Tue Oct 18 12:50:36 2011 @@ -13,7 +13,7 @@ # Make sure that tblgen is run, first thing. BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \ - MipsGenAsmWriter.inc \ + MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ MipsGenSubtargetInfo.inc Modified: llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp?rev=142378&r1=142377&r2=142378&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp Tue Oct 18 12:50:36 2011 @@ -105,6 +105,9 @@ unsigned getRelocation(const MachineInstr &MI, const MachineOperand &MO) const; + unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const; + unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const; + unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const; }; } @@ -153,6 +156,28 @@ return Mips::reloc_mips_lo; } +unsigned MipsCodeEmitter::getMemEncoding(const MachineInstr &MI, + unsigned OpNo) const { + // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. + assert(MI.getOperand(OpNo).isReg()); + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16; + return + (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits; +} + +unsigned MipsCodeEmitter::getSizeExtEncoding(const MachineInstr &MI, + unsigned OpNo) const { + // size is encoded as size-1. + return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; +} + +unsigned MipsCodeEmitter::getSizeInsEncoding(const MachineInstr &MI, + unsigned OpNo) const { + // size is encoded as pos+size-1. + return getMachineOpValue(MI, MI.getOperand(OpNo-1)) + + getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; +} + /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI, @@ -238,8 +263,4 @@ return new MipsCodeEmitter(TM, JCE); } -unsigned MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const { - // this function will be automatically generated by the CodeEmitterGenerator - // using TableGen - return 0; -} +#include "MipsGenCodeEmitter.inc" Modified: llvm/trunk/lib/Target/Mips/MipsCondMov.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCondMov.td?rev=142378&r1=142377&r2=142378&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsCondMov.td (original) +++ llvm/trunk/lib/Target/Mips/MipsCondMov.td Tue Oct 18 12:50:36 2011 @@ -16,6 +16,8 @@ bits<6> func, string instr_asm> : FFR<0x11, func, fmt, (outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F), !strconcat(instr_asm, "\t$fd, $fs, $rt"), []> { + bits<5> rt; + let ft = rt; let Constraints = "$F = $fd"; } @@ -116,8 +118,8 @@ def MOVT_I64 : CondMovFPInt, Requires<[HasMips64]>; -def MOVF_I : CondMovFPInt; -def MOVF_I64 : CondMovFPInt, +def MOVF_I : CondMovFPInt; +def MOVF_I64 : CondMovFPInt, Requires<[HasMips64]>; def MOVT_S : CondMovFPFP; Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=142378&r1=142377&r2=142378&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Tue Oct 18 12:50:36 2011 @@ -76,14 +76,16 @@ // FP load. class FPLoad op, string opstr, PatFrag FOp, RegisterClass RC, Operand MemOpnd>: - FFI; + FMem; // FP store. class FPStore op, string opstr, PatFrag FOp, RegisterClass RC, Operand MemOpnd>: - FFI; + FMem; // Instructions that convert an FP value to 32-bit fixed point. multiclass FFR1_W_M funct, string opstr> { @@ -158,22 +160,28 @@ // stores, and moves between floating-point and integer registers. // When defining instructions, we reference all 32-bit registers, // regardless of register aliasing. -let fd = 0 in { - /// Move Control Registers From/To CPU Registers - def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins CCR:$fs), + +class FFRGPR _fmt, dag outs, dag ins, string asmstr, list pattern>: + FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> { + bits<5> rt; + let ft = rt; + let fd = 0; +} + +/// Move Control Registers From/To CPU Registers +def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs), "cfc1\t$rt, $fs", []>; - def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs), - "ctc1\t$fs, $rt", []>; +def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt), + "ctc1\t$rt, $fs", []>; - def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs), +def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs), "mfc1\t$rt, $fs", [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>; - def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt), +def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt), "mtc1\t$rt, $fs", [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>; -} def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>; def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>, @@ -203,7 +211,7 @@ } /// Floating-point Aritmetic -defm FADD : FFR2P_M<0x10, "add", fadd, 1>; +defm FADD : FFR2P_M<0x00, "add", fadd, 1>; defm FDIV : FFR2P_M<0x03, "div", fdiv>; defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>; defm FSUB : FFR2P_M<0x01, "sub", fsub>; @@ -218,12 +226,16 @@ /// Floating Point Branch of False/True (Likely) let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in - class FBRANCH : FFI<0x11, (outs), - (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"), - [(MipsFPBrcond op, bb:$dst)]>; + class FBRANCH nd, bits<1> tf, PatLeaf op, string asmstr> : + FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"), + [(MipsFPBrcond op, bb:$dst)]> { + let Inst{20-18} = 0; + let Inst{17} = nd; + let Inst{16} = tf; +} -def BC1F : FBRANCH; -def BC1T : FBRANCH; +def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">; +def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">; //===----------------------------------------------------------------------===// // Floating Point Flag Conditions @@ -249,11 +261,11 @@ /// Floating Point Compare let Defs=[FCR31] in { - def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc), + def FCMP_S32 : FCC<0x10, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc), "c.$cc.s\t$fs, $ft", [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>; - def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc), + def FCMP_D32 : FCC<0x11, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc), "c.$cc.d\t$fs, $ft", [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>, Requires<[NotFP64bit]>; Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=142378&r1=142377&r2=142378&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Tue Oct 18 12:50:36 2011 @@ -21,30 +21,55 @@ // //===----------------------------------------------------------------------===// +// Format specifies the encoding used by the instruction. This is part of the +// ad-hoc solution used to emit machine instruction encodings by our machine +// code emitter. +class Format val> { + bits<4> Value = val; +} + +def Pseudo : Format<0>; +def FrmR : Format<1>; +def FrmI : Format<2>; +def FrmJ : Format<3>; +def FrmFR : Format<4>; +def FrmFI : Format<5>; +def FrmOther : Format<6>; // Instruction w/ a custom format + // Generic Mips Format class MipsInst pattern, - InstrItinClass itin>: Instruction + InstrItinClass itin, Format f>: Instruction { field bits<32> Inst; + Format Form = f; let Namespace = "Mips"; - bits<6> opcode; + bits<6> Opcode = 0; - // Top 5 bits are the 'opcode' field - let Inst{31-26} = opcode; + // Top 6 bits are the 'opcode' field + let Inst{31-26} = Opcode; - dag OutOperandList = outs; - dag InOperandList = ins; + let OutOperandList = outs; + let InOperandList = ins; let AsmString = asmstr; let Pattern = pattern; let Itinerary = itin; + + // + // Attributes specific to Mips instructions... + // + bits<4> FormBits = Form.Value; + + // TSFlags layout should be kept in sync with MipsInstrInfo.h. + let TSFlags{3-0} = FormBits; } // Mips Pseudo Instructions Format class MipsPseudo pattern>: - MipsInst { + MipsInst { + let isCodeGenOnly = 1; let isPseudo = 1; } @@ -54,7 +79,7 @@ class FR op, bits<6> _funct, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst + MipsInst { bits<5> rd; bits<5> rs; @@ -62,7 +87,7 @@ bits<5> shamt; bits<6> funct; - let opcode = op; + let Opcode = op; let funct = _funct; let Inst{25-21} = rs; @@ -77,13 +102,13 @@ //===----------------------------------------------------------------------===// class FI op, dag outs, dag ins, string asmstr, list pattern, - InstrItinClass itin>: MipsInst + InstrItinClass itin>: MipsInst { bits<5> rt; bits<5> rs; bits<16> imm16; - let opcode = op; + let Opcode = op; let Inst{25-21} = rs; let Inst{20-16} = rt; @@ -92,13 +117,13 @@ class CBranchBase op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst + MipsInst { bits<5> rs; bits<5> rt; bits<16> imm16; - let opcode = op; + let Opcode = op; let Inst{25-21} = rs; let Inst{20-16} = rt; @@ -110,11 +135,11 @@ //===----------------------------------------------------------------------===// class FJ op, dag outs, dag ins, string asmstr, list pattern, - InstrItinClass itin>: MipsInst + InstrItinClass itin>: MipsInst { bits<26> addr; - let opcode = op; + let Opcode = op; let Inst{25-0} = addr; } @@ -138,7 +163,7 @@ class FFR op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins, string asmstr, list pattern> : - MipsInst + MipsInst { bits<5> fd; bits<5> fs; @@ -146,7 +171,7 @@ bits<5> fmt; bits<6> funct; - let opcode = op; + let Opcode = op; let funct = _funct; let fmt = _fmt; @@ -162,13 +187,13 @@ //===----------------------------------------------------------------------===// class FFI op, dag outs, dag ins, string asmstr, list pattern>: - MipsInst + MipsInst { bits<5> ft; bits<5> base; bits<16> imm16; - let opcode = op; + let Opcode = op; let Inst{25-21} = base; let Inst{20-16} = ft; @@ -180,14 +205,14 @@ //===----------------------------------------------------------------------===// class FCC _fmt, dag outs, dag ins, string asmstr, list pattern> : - MipsInst + MipsInst { bits<5> fs; bits<5> ft; bits<4> cc; bits<5> fmt; - let opcode = 0x11; + let Opcode = 0x11; let fmt = _fmt; let Inst{25-21} = fmt; @@ -201,14 +226,14 @@ class FCMOV _tf, dag outs, dag ins, string asmstr, list pattern> : - MipsInst + MipsInst { bits<5> rd; bits<5> rs; bits<3> cc; bits<1> tf; - let opcode = 0; + let Opcode = 0; let tf = _tf; let Inst{25-21} = rs; @@ -222,7 +247,7 @@ class FFCMOV _fmt, bits<1> _tf, dag outs, dag ins, string asmstr, list pattern> : - MipsInst + MipsInst { bits<5> fd; bits<5> fs; @@ -230,7 +255,7 @@ bits<5> fmt; bits<1> tf; - let opcode = 17; + let Opcode = 17; let fmt = _fmt; let tf = _tf; Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=142378&r1=142377&r2=142378&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Oct 18 12:50:36 2011 @@ -153,6 +153,7 @@ def mem : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops CPURegs, simm16); + let EncoderMethod = "getMemEncoding"; } def mem64 : Operand { @@ -163,6 +164,17 @@ def mem_ea : Operand { let PrintMethod = "printMemOperandEA"; let MIOperandInfo = (ops CPURegs, simm16); + let EncoderMethod = "getMemEncoding"; +} + +// size operand of ext instruction +def size_ext : Operand { + let EncoderMethod = "getSizeExtEncoding"; +} + +// size operand of ins instruction +def size_ins : Operand { + let EncoderMethod = "getSizeInsEncoding"; } // Transformation Function - get the lower 16 bits. @@ -269,14 +281,14 @@ // Arithmetic and logical instructions with 2 register operands. class ArithLogicI op, string instr_asm, SDNode OpNode, Operand Od, PatLeaf imm_type, RegisterClass RC> : - FI; + FI; class ArithOverflowI op, string instr_asm, SDNode OpNode, Operand Od, PatLeaf imm_type, RegisterClass RC> : - FI; + FI; // Arithmetic Multiply ADD/SUB let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in @@ -323,16 +335,23 @@ // Load Upper Imediate class LoadUpper op, string instr_asm>: - FI { + FI { let rs = 0; } +class FMem op, dag outs, dag ins, string asmstr, list pattern, + InstrItinClass itin>: FFI { + bits<21> addr; + let Inst{25-21} = addr{20-16}; + let Inst{15-0} = addr{15-0}; +} + // Memory Load/Store let canFoldAsLoad = 1 in class LoadM op, string instr_asm, PatFrag OpNode, RegisterClass RC, Operand MemOpnd, bit Pseudo>: - FI { let isPseudo = Pseudo; @@ -340,7 +359,7 @@ class StoreM op, string instr_asm, PatFrag OpNode, RegisterClass RC, Operand MemOpnd, bit Pseudo>: - FI { let isPseudo = Pseudo; @@ -384,9 +403,9 @@ // Conditional Branch class CBranch op, string instr_asm, PatFrag cond_op, RegisterClass RC>: - CBranchBase { + CBranchBase { let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 1; @@ -394,9 +413,9 @@ class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, RegisterClass RC>: - CBranchBase { + CBranchBase { let rt = _rt; let isBranch = 1; let isTerminator = 1; @@ -415,9 +434,9 @@ class SetCC_I op, string instr_asm, PatFrag cond_op, Operand Od, PatLeaf imm_type, RegisterClass RC>: - FI; // Unconditional branch @@ -454,10 +473,8 @@ } class BranchLink: - FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops), - !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch> { - let rt = 0; - } + FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$imm16, variable_ops), + !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>; } // Mul, Div @@ -509,7 +526,7 @@ } class EffectiveAddress : - FI<0x09, (outs CPURegs:$rt), (ins mem_ea:$addr), + FMem<0x09, (outs CPURegs:$rt), (ins mem_ea:$addr), instr_asm, [(set CPURegs:$rt, addr:$addr)], IIAlu>; // Count Leading Ones/Zeros in Word @@ -533,7 +550,7 @@ // Sign Extend in Register. class SignExtInReg sa, string instr_asm, ValueType vt>: - FR<0x3f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt), + FR<0x1f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt), !strconcat(instr_asm, "\t$rd, $rt"), [(set CPURegs:$rd, (sext_inreg CPURegs:$rt, vt))], NoItinerary> { let rs = 0; @@ -711,20 +728,22 @@ let hasSideEffects = 1 in def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype", - [(MipsSync imm:$stype)], NoItinerary> + [(MipsSync imm:$stype)], NoItinerary, FrmOther> { - let opcode = 0; + bits<5> stype; + let Opcode = 0; let Inst{25-11} = 0; + let Inst{10-6} = stype; let Inst{5-0} = 15; } /// Load-linked, Store-conditional let mayLoad = 1 in - def LL : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr), - "ll\t$dst, $addr", [], IILoad>; -let mayStore = 1, Constraints = "$src = $dst" in - def SC : FI<0x38, (outs CPURegs:$dst), (ins CPURegs:$src, mem:$addr), - "sc\t$src, $addr", [], IIStore>; + def LL : FMem<0x30, (outs CPURegs:$rt), (ins mem:$addr), + "ll\t$rt, $addr", [], IILoad>; +let mayStore = 1, Constraints = "$rt = $dst" in + def SC : FMem<0x38, (outs CPURegs:$dst), (ins CPURegs:$rt, mem:$addr), + "sc\t$rt, $addr", [], IIStore>; /// Jump and Branch Instructions def J : JumpFJ<0x02, "j">; @@ -736,15 +755,17 @@ def BNE : CBranch<0x05, "bne", setne, CPURegs>; def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>; -def BLEZ : CBranchZero<0x07, 0, "blez", setle, CPURegs>; +def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>; def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>; -def BGEZAL : BranchLink<"bgezal">; -def BLTZAL : BranchLink<"bltzal">; +let rt=0x11 in + def BGEZAL : BranchLink<"bgezal">; +let rt=0x10 in + def BLTZAL : BranchLink<"bltzal">; let isReturn=1, isTerminator=1, hasDelaySlot=1, - isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in - def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target), + isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in + def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target), "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>; /// Multiply and Divide Instructions. @@ -799,14 +820,14 @@ def RDHWR : ReadHardware; def EXT : ExtIns<0, "ext", (outs CPURegs:$rt), - (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz), + (ins CPURegs:$rs, uimm16:$pos, size_ext:$sz), [(set CPURegs:$rt, (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$sz))], NoItinerary>; let Constraints = "$src = $rt" in def INS : ExtIns<4, "ins", (outs CPURegs:$rt), - (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz, CPURegs:$src), + (ins CPURegs:$rs, uimm16:$pos, size_ins:$sz, CPURegs:$src), [(set CPURegs:$rt, (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$sz, CPURegs:$src))], From nadav.rotem at intel.com Tue Oct 18 12:56:14 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Tue, 18 Oct 2011 19:56:14 +0200 Subject: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ In-Reply-To: <3B17D92A-B302-4439-9A05-7DABE3AAF8BB@mac.com> References: <20111016203133.CC4E13128018@llvm.org> <1B579157-F0E8-45FB-A8E8-3D520ED36FC0@mac.com> <84BE87AB-7185-4CF6-B0F4-D242762AA4A0@mac.com> <6594DDFF12B03D4E89690887C248699402A2C887C6@hasmsx504.ger.corp.intel.com> <32320A16-378C-4390-A51B-241396859284@mac.com> <6594DDFF12B03D4E89690887C248699402A2C888AA@hasmsx504.ger.corp.intel.com> <3B17D92A-B302-4439-9A05-7DABE3AAF8BB@mac.com> Message-ID: <6594DDFF12B03D4E89690887C248699402A2C88BCE@hasmsx504.ger.corp.intel.com> Owen, Currently the LLVM type-legalizer is not context aware. I think that in one of the bug-reports, Duncan mentioned a general plan to unify the type-legalizer and the operation legalizer. This will allow us to make context-aware legalization decisions. Maybe we can discuss this in the next dev-meeting. Thank you again for looking at this. Nadav -----Original Message----- From: Owen Anderson [mailto:resistor at mac.com] Sent: Tuesday, October 18, 2011 18:52 To: Anton Korobeynikov Cc: Rotem, Nadav; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/ On Oct 18, 2011, at 5:19 AM, Anton Korobeynikov wrote: > Hi Nadav, > >> I discussed the legalization of <2 x i16> stores on ARM with Anton. As you mentioned, i16 is illegal on ARM and it is not possible to scalarize the store in the Legalizer. >> This was the main reason for moving the legalization of vector memory ops into LegalizeVectorOps. > Well, this is completely different story. Your question was about > trunc-stores, but here it seems to prevent important codegen sequence. > >> I agree that in some cases promoting the elements in the vector is less efficient than widening the number of elements. However, generally 'promotion' is a better strategy. I am mostly interested in code-generation of auto-vectorized IR. What workloads are you mostly interested in ? Maybe we can discuss the needed optimizations for these workloads. > On NEON you can do pretty efficient vector manipulations via shuffles > (e.g. any shuffle of 4 elements can be codegen'ed in 5 or less > instructions, usually 2-3). This is really important for ARM. > > In the meantime I'd suggest you adding target-specific "vector select > strategy" flag, so target can choose how to deal with all the stuff > and make sure your code is disabled for e.g. ARM and CellSPU. I had an extended discussion with Dan about this yesterday, and we came to two conclusions: 1) The particular testcase in question is really weird, and probably isn't a great representative of code we care about. As long as we don't generate something completely braindead for it, we're OK with it being regressed if this is an overall win. 2) Determining a policy for vector-widening vs. element-widening is really, really hard, and also context dependent. In this particular case, we want to widen the vector because a later immutable use (the store) is expressed in terms of i16's. However, it's easy to imagine other circumstances where the later use would prefer the element-widening approach. --Owen --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From resistor at mac.com Tue Oct 18 12:57:31 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 18 Oct 2011 17:57:31 -0000 Subject: [llvm-commits] [llvm] r142379 - /llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Message-ID: <20111018175731.93F353128034@llvm.org> Author: resistor Date: Tue Oct 18 12:57:31 2011 New Revision: 142379 URL: http://llvm.org/viewvc/llvm-project?rev=142379&view=rev Log: Add a few more testcases. Modified: llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Modified: llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s?rev=142379&r1=142378&r2=142379&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Tue Oct 18 12:57:31 2011 @@ -95,3 +95,8 @@ @ FIXME: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80] @ vmlal.s32 q0, d5, d10[0] @ FIXME: vmlal.s32 q0, d5, d10[0] @ encoding: [0xa5,0xef,0x4a,0x02] +@ vmls.i16 q4, q12, d6[2] +@ FIXME: vmls.i16 q4, q12, d6[2] @ encoding: [0x98,0xff,0xe6,0x94] +@ vmlsl.u16 q11, d25, d1[3] +@ FIXME: vmlsl.u16 q11, d25, d1[3] @ encoding: [0xd9,0xff,0xe9,0x66] + From grosbach at apple.com Tue Oct 18 13:01:09 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 18 Oct 2011 18:01:09 -0000 Subject: [llvm-commits] [llvm] r142380 - /llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Message-ID: <20111018180109.860523128034@llvm.org> Author: grosbach Date: Tue Oct 18 13:01:09 2011 New Revision: 142380 URL: http://llvm.org/viewvc/llvm-project?rev=142380&view=rev Log: Tidy up. Modified: llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Modified: llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s?rev=142380&r1=142379&r2=142380&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Tue Oct 18 13:01:09 2011 @@ -10,6 +10,7 @@ vmla.i16 q9, q8, q10 vmla.i32 q9, q8, q10 vmla.f32 q9, q8, q10 +@ vmla.i32 q12, q8, d3[0] @ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0x42,0xef,0xa1,0x09] @ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0x52,0xef,0xa1,0x09] @@ -19,6 +20,7 @@ @ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0x50,0xef,0xe4,0x29] @ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0x60,0xef,0xe4,0x29] @ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0x40,0xef,0xf4,0x2d] +@ FIXME: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80] vmlal.s8 q8, d19, d18 @@ -27,6 +29,7 @@ vmlal.u8 q8, d19, d18 vmlal.u16 q8, d19, d18 vmlal.u32 q8, d19, d18 +@ vmlal.s32 q0, d5, d10[0] @ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xc3,0xef,0xa2,0x08] @ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x08] @@ -34,6 +37,7 @@ @ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xc3,0xff,0xa2,0x08] @ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xd3,0xff,0xa2,0x08] @ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xe3,0xff,0xa2,0x08] +@ FIXME: vmlal.s32 q0, d5, d10[0] @ encoding: [0xa5,0xef,0x4a,0x02] vqdmlal.s16 q8, d19, d18 @@ -59,6 +63,7 @@ vmls.i16 q9, q8, q10 vmls.i32 q9, q8, q10 vmls.f32 q9, q8, q10 +@ vmls.i16 q4, q12, d6[2] @ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0x42,0xff,0xa1,0x09] @ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0x52,0xff,0xa1,0x09] @@ -68,6 +73,7 @@ @ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0x50,0xff,0xe4,0x29] @ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0x60,0xff,0xe4,0x29] @ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0x60,0xef,0xf4,0x2d] +@ FIXME: vmls.i16 q4, q12, d6[2] @ encoding: [0x98,0xff,0xe6,0x94] vmlsl.s8 q8, d19, d18 @@ -76,6 +82,7 @@ vmlsl.u8 q8, d19, d18 vmlsl.u16 q8, d19, d18 vmlsl.u32 q8, d19, d18 +@ vmlsl.u16 q11, d25, d1[3] @ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xc3,0xef,0xa2,0x0a] @ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x0a] @@ -83,6 +90,7 @@ @ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xc3,0xff,0xa2,0x0a] @ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xd3,0xff,0xa2,0x0a] @ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xe3,0xff,0xa2,0x0a] +@ FIXME: vmlsl.u16 q11, d25, d1[3] @ encoding: [0xd9,0xff,0xe9,0x66] vqdmlsl.s16 q8, d19, d18 @@ -90,13 +98,3 @@ @ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x0b] @ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x0b] - -@ vmla.i32 q12, q8, d3[0] -@ FIXME: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80] -@ vmlal.s32 q0, d5, d10[0] -@ FIXME: vmlal.s32 q0, d5, d10[0] @ encoding: [0xa5,0xef,0x4a,0x02] -@ vmls.i16 q4, q12, d6[2] -@ FIXME: vmls.i16 q4, q12, d6[2] @ encoding: [0x98,0xff,0xe6,0x94] -@ vmlsl.u16 q11, d25, d1[3] -@ FIXME: vmlsl.u16 q11, d25, d1[3] @ encoding: [0xd9,0xff,0xe9,0x66] - From grosbach at apple.com Tue Oct 18 13:01:52 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 18 Oct 2011 18:01:52 -0000 Subject: [llvm-commits] [llvm] r142381 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neont2-mul-encoding.s Message-ID: <20111018180152.670723128034@llvm.org> Author: grosbach Date: Tue Oct 18 13:01:52 2011 New Revision: 142381 URL: http://llvm.org/viewvc/llvm-project?rev=142381&view=rev Log: ARM vmul assembly parsing for the lane index operand. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142381&r1=142380&r2=142381&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 18 13:01:52 2011 @@ -1936,8 +1936,8 @@ InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp> : N3VLane32<0, 1, op21_20, op11_8, 1, 0, - (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane), - NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "", + (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), + NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", [(set (Ty DPR:$Vd), (Ty (ShOp (Ty DPR:$Vn), (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> { @@ -1946,8 +1946,8 @@ class N3VDSL16 op21_20, bits<4> op11_8, string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp> : N3VLane16<0, 1, op21_20, op11_8, 1, 0, - (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane), - NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","", + (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), + NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","", [(set (Ty DPR:$Vd), (Ty (ShOp (Ty DPR:$Vn), (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> { Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-encoding.s?rev=142381&r1=142380&r2=142381&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Tue Oct 18 13:01:52 2011 @@ -22,6 +22,10 @@ vmul.p8 d16, d16, d17 @ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x09] vmul.p8 q8, q8, q9 + + vmul.i16 d18, d8, d0[3] +@ CHECK: vmul.i16 d18, d8, d0[3] @ encoding: [0xd8,0xef,0x68,0x28] + @ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x0b] vqdmulh.s16 d16, d16, d17 @ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x0b] @@ -57,11 +61,7 @@ @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d] vqdmull.s32 q8, d16, d17 +@ vmla.i32 q12, q8, d3[0] +@ vqdmulh.s16 d11, d2, d3[0] @ FIXME: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80] -@ vmla.i32 q12, q8, d3[0] @ FIXME: vqdmulh.s16 d11, d2, d3[0] @ encoding: [0x92,0xef,0x43,0xbc] -@ vqdmulh.s16 d11, d2, d3[0] -@ FIXME: vmul.i16 d18, d8, d0[3] @ encoding: [0xd8,0xef,0x68,0x28] -@ vmul.i16 d18, d8, d0[3] - - From grosbach at apple.com Tue Oct 18 13:05:16 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 18 Oct 2011 18:05:16 -0000 Subject: [llvm-commits] [llvm] r142382 - /llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Message-ID: <20111018180517.029F23128034@llvm.org> Author: grosbach Date: Tue Oct 18 13:05:16 2011 New Revision: 142382 URL: http://llvm.org/viewvc/llvm-project?rev=142382&view=rev Log: Tidy up formatting. Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-encoding.s?rev=142382&r1=142381&r2=142382&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Tue Oct 18 13:05:16 2011 @@ -2,66 +2,77 @@ .code 16 -@ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x09] vmul.i8 d16, d16, d17 -@ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0x50,0xef,0xb1,0x09] vmul.i16 d16, d16, d17 -@ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x09] vmul.i32 d16, d16, d17 -@ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x0d] vmul.f32 d16, d16, d17 -@ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x09] vmul.i8 q8, q8, q9 -@ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0x50,0xef,0xf2,0x09] vmul.i16 q8, q8, q9 -@ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x09] vmul.i32 q8, q8, q9 -@ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x0d] vmul.f32 q8, q8, q9 -@ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x09] vmul.p8 d16, d16, d17 -@ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x09] vmul.p8 q8, q8, q9 - vmul.i16 d18, d8, d0[3] -@ CHECK: vmul.i16 d18, d8, d0[3] @ encoding: [0xd8,0xef,0x68,0x28] -@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x0b] +@ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x09] +@ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0x50,0xef,0xb1,0x09] +@ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x09] +@ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x0d] +@ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x09] +@ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0x50,0xef,0xf2,0x09] +@ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x09] +@ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x0d] +@ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0x40,0xff,0xb1,0x09] +@ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x09] +@ CHECK: vmul.i16 d18, d8, d0[3] @ encoding: [0xd8,0xef,0x68,0x28] + + vqdmulh.s16 d16, d16, d17 -@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x0b] vqdmulh.s32 d16, d16, d17 -@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x0b] vqdmulh.s16 q8, q8, q9 -@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x0b] vqdmulh.s32 q8, q8, q9 -@ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b] +@ vqdmulh.s16 d11, d2, d3[0] + +@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x0b] +@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x0b] +@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x0b] +@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x0b] +@ FIXME: vqdmulh.s16 d11, d2, d3[0] @ encoding: [0x92,0xef,0x43,0xbc] + + vqrdmulh.s16 d16, d16, d17 -@ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b] vqrdmulh.s32 d16, d16, d17 -@ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b] vqrdmulh.s16 q8, q8, q9 -@ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b] vqrdmulh.s32 q8, q8, q9 -@ CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xc0,0xef,0xa1,0x0c] + +@ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b] +@ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b] +@ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b] +@ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b] + + vmull.s8 q8, d16, d17 -@ CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0c] vmull.s16 q8, d16, d17 -@ CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0c] vmull.s32 q8, d16, d17 -@ CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xc0,0xff,0xa1,0x0c] vmull.u8 q8, d16, d17 -@ CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xd0,0xff,0xa1,0x0c] vmull.u16 q8, d16, d17 -@ CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xe0,0xff,0xa1,0x0c] vmull.u32 q8, d16, d17 -@ CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xc0,0xef,0xa1,0x0e] vmull.p8 q8, d16, d17 -@ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d] + +@ CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xc0,0xef,0xa1,0x0c] +@ CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0c] +@ CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0c] +@ CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xc0,0xff,0xa1,0x0c] +@ CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xd0,0xff,0xa1,0x0c] +@ CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xe0,0xff,0xa1,0x0c] +@ CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xc0,0xef,0xa1,0x0e] + + vqdmull.s16 q8, d16, d17 -@ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d] vqdmull.s32 q8, d16, d17 +@ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d] +@ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d] + @ vmla.i32 q12, q8, d3[0] -@ vqdmulh.s16 d11, d2, d3[0] -@ FIXME: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80] -@ FIXME: vqdmulh.s16 d11, d2, d3[0] @ encoding: [0x92,0xef,0x43,0xbc] +@ FIXME: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80] From grosbach at apple.com Tue Oct 18 13:05:50 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 18 Oct 2011 18:05:50 -0000 Subject: [llvm-commits] [llvm] r142383 - /llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Message-ID: <20111018180550.982653128034@llvm.org> Author: grosbach Date: Tue Oct 18 13:05:50 2011 New Revision: 142383 URL: http://llvm.org/viewvc/llvm-project?rev=142383&view=rev Log: Remove duplicate test. Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-encoding.s?rev=142383&r1=142382&r2=142383&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mul-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Tue Oct 18 13:05:50 2011 @@ -73,6 +73,3 @@ @ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d] @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d] - -@ vmla.i32 q12, q8, d3[0] -@ FIXME: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80] From eli.friedman at gmail.com Tue Oct 18 13:08:46 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 18 Oct 2011 11:08:46 -0700 Subject: [llvm-commits] [llvm] r142371 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vmul.ll In-Reply-To: <20111018173451.C65DA3524002@llvm.org> References: <20111018173451.C65DA3524002@llvm.org> Message-ID: On Tue, Oct 18, 2011 at 10:34 AM, Bob Wilson wrote: > Author: bwilson > Date: Tue Oct 18 12:34:51 2011 > New Revision: 142371 > > URL: http://llvm.org/viewvc/llvm-project?rev=142371&view=rev > Log: > Fix incorrect check for sign-extended constant BUILD_VECTOR. >

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