From nicholas at mxc.ca  Mon Oct 24 00:51:01 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 24 Oct 2011 05:51:01 -0000
Subject: [llvm-commits] [llvm] r142788 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20111024055101.8CBF93524006@llvm.org>

Author: nicholas
Date: Mon Oct 24 00:51:01 2011
New Revision: 142788

URL: http://llvm.org/viewvc/llvm-project?rev=142788&view=rev
Log:
PHI nodes not in the loop header aren't part of the loop iteration initial
state. Furthermore, they might not have two operands. This fixes the underlying
issue behind the crashes introduced in r142781.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=142788&r1=142787&r2=142788&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Oct 24 00:51:01 2011
@@ -4856,7 +4856,7 @@
     for (DenseMap<Instruction *, Constant *>::const_iterator
            I = CurrentIterVals.begin(), E = CurrentIterVals.end(); I != E; ++I){
       PHINode *PHI = dyn_cast<PHINode>(I->first);
-      if (!PHI || PHI == PN) continue;
+      if (!PHI || PHI == PN || PHI->getParent() != Header) continue;
       Constant *&NextPHI = NextIterVals[PHI];
       if (NextPHI) continue;    // Already computed!
 



From chandlerc at gmail.com  Mon Oct 24 00:55:59 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 24 Oct 2011 05:55:59 -0000
Subject: [llvm-commits] [llvm] r142789 -
	/llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
Message-ID: <20111024055559.25FF93524006@llvm.org>

Author: chandlerc
Date: Mon Oct 24 00:55:58 2011
New Revision: 142789

URL: http://llvm.org/viewvc/llvm-project?rev=142789&view=rev
Log:
Doxygen-ify the comments on the public interface for BPI. Also, move the
two more subtle routines to the bottom and expand on their cautionary
comments a bit. No functionality or actual interface change here.

Modified:
    llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h

Modified: llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h?rev=142789&r1=142788&r2=142789&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h Mon Oct 24 00:55:58 2011
@@ -23,6 +23,15 @@
 class LoopInfo;
 class raw_ostream;
 
+/// \brief Analysis pass providing branch probability information.
+///
+/// This is a function analysis pass which provides information on the relative
+/// probabilities of each "edge" in the function's CFG where such an edge is
+/// defined by a pair of basic blocks. The probability for a given block and
+/// a successor block are always relative to the probabilities of the other
+/// successor blocks. Another way of looking at it is that the probabilities
+/// for a given block B and each of its successors should sum to exactly
+/// one (100%).
 class BranchProbabilityInfo : public FunctionPass {
 public:
   static char ID;
@@ -35,32 +44,52 @@
   bool runOnFunction(Function &F);
   void print(raw_ostream &OS, const Module *M = 0) const;
 
-  // Returned value is between 1 and UINT32_MAX. Look at
-  // BranchProbabilityInfo.cpp for details.
-  uint32_t getEdgeWeight(const BasicBlock *Src, const BasicBlock *Dst) const;
-
-  // Look at BranchProbabilityInfo.cpp for details. Use it with caution!
-  void setEdgeWeight(const BasicBlock *Src, const BasicBlock *Dst,
-                     uint32_t Weight);
+  /// \brief Get an edge's probability, relative to other out-edges of the Src.
+  ///
+  /// This routine provides access to the fractional probability between zero
+  /// (0%) and one (100%) of this edge executing, relative to other edges
+  /// leaving the 'Src' block. The returned probability is never zero, and can
+  /// only be one if the source block has only one successor.
+  BranchProbability getEdgeProbability(const BasicBlock *Src,
+                                       const BasicBlock *Dst) const;
 
-  // A 'Hot' edge is an edge which probability is >= 80%.
+  /// \brief Test if an edge is hot relative to other out-edges of the Src.
+  ///
+  /// Check whether this edge out of the source block is 'hot'. We define hot
+  /// as having a relative probability >= 80%.
   bool isEdgeHot(const BasicBlock *Src, const BasicBlock *Dst) const;
 
-  // Return a hot successor for the block BB or null if there isn't one.
+  /// \brief Retrieve the hot successor of a block if one exists.
+  ///
+  /// Given a basic block, look through its successors and if one exists for
+  /// which \see isEdgeHot would return true, return that successor block.
   BasicBlock *getHotSucc(BasicBlock *BB) const;
 
-  // Return a probability as a fraction between 0 (0% probability) and
-  // 1 (100% probability), however the value is never equal to 0, and can be 1
-  // only iff SRC block has only one successor.
-  BranchProbability getEdgeProbability(const BasicBlock *Src,
-                                       const BasicBlock *Dst) const;
-
-  // Print value between 0 (0% probability) and 1 (100% probability),
-  // however the value is never equal to 0, and can be 1 only iff SRC block
-  // has only one successor.
+  /// \brief Print an edge's probability.
+  ///
+  /// Retrieves an edge's probability similarly to \see getEdgeProbability, but
+  /// then prints that probability to the provided stream. That stream is then
+  /// returned.
   raw_ostream &printEdgeProbability(raw_ostream &OS, const BasicBlock *Src,
                                     const BasicBlock *Dst) const;
 
+  /// \brief Get the raw edge weight calculated for the block pair.
+  ///
+  /// This returns the raw edge weight. It is guaranteed to fall between 1 and
+  /// UINT32_MAX. Note that the raw edge weight is not meaningful in isolation.
+  /// This interface should be very carefully, and primarily by routines that
+  /// are updating the analysis by later calling setEdgeWeight.
+  uint32_t getEdgeWeight(const BasicBlock *Src, const BasicBlock *Dst) const;
+
+  /// \brief Set the raw edge weight for the block pair.
+  ///
+  /// This allows a pass to explicitly set the edge weight for a block. It can
+  /// be used when updating the CFG to update and preserve the branch
+  /// probability information. Read the implementation of how these edge
+  /// weights are calculated carefully before using!
+  void setEdgeWeight(const BasicBlock *Src, const BasicBlock *Dst,
+                     uint32_t Weight);
+
 private:
   typedef std::pair<const BasicBlock *, const BasicBlock *> Edge;
 



From rdivacky at freebsd.org  Mon Oct 24 01:50:08 2011
From: rdivacky at freebsd.org (Roman Divacky)
Date: Mon, 24 Oct 2011 08:50:08 +0200
Subject: [llvm-commits] [llvm] r142743 - in /llvm/trunk:
	lib/CodeGen/MachineBlockPlacement.cpp
	test/CodeGen/X86/block-placement.ll
In-Reply-To: <CAGCO0Kijo0HaTYBwTQum_4SbceAH1L2j56ejePW1EQSRqQ9rug@mail.gmail.com>
References: <20111023091845.40B6F3524006@llvm.org>
	<20111023105635.GA92259@freebsd.org>
	<CAGCO0Kijo0HaTYBwTQum_4SbceAH1L2j56ejePW1EQSRqQ9rug@mail.gmail.com>
Message-ID: <20111024065008.GA19273@freebsd.org>

On Sun, Oct 23, 2011 at 12:36:17PM -0700, Chandler Carruth wrote:
> On Sun, Oct 23, 2011 at 3:56 AM, Roman Divacky <rdivacky at freebsd.org> wrote:
> 
> > I enabled your MachineBlockPlacement pass by default and ran perlbench.
> >
> > Your pass gets perl from 94% (of gcc4.2.1 compiled one performance) to 96%.
> > Great work!
> >
> 
> That's actually rather surprising. The probabilities we're basing any of
> this on are quite broken. But hey, I'm glad it's improving things. What
> hardware? How stable were the numbers?

The numbers are very stable. The cpu in question was 

CPU: Intel(R) Core(TM)2 Duo CPU     E8500  @ 3.16GHz


roman

From nicholas at mxc.ca  Mon Oct 24 01:57:06 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 24 Oct 2011 06:57:06 -0000
Subject: [llvm-commits] [llvm] r142790 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
Message-ID: <20111024065706.388E53524006@llvm.org>

Author: nicholas
Date: Mon Oct 24 01:57:05 2011
New Revision: 142790

URL: http://llvm.org/viewvc/llvm-project?rev=142790&view=rev
Log:
Reapply r142781 with fix. Original message:

  Enhance SCEV's brute force loop analysis to handle multiple PHI nodes in the
  loop header when computing the trip count.

  With this, we now constant evaluate:
    struct ListNode { const struct ListNode *next; int i; };
    static const struct ListNode node1 = {0, 1};
    static const struct ListNode node2 = {&node1, 2};
    static const struct ListNode node3 = {&node2, 3};
    int test() {
      int sum = 0;
      for (const struct ListNode *n = &node3; n != 0; n = n->next)
        sum += n->i;
      return sum;
    }

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Analysis/ScalarEvolution/load.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=142790&r1=142789&r2=142790&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Oct 24 01:57:05 2011
@@ -4882,29 +4882,33 @@
   // That's the only form we support here.
   if (PN->getNumIncomingValues() != 2) return getCouldNotCompute();
 
+  DenseMap<Instruction *, Constant *> CurrentIterVals;
+  BasicBlock *Header = L->getHeader();
+  assert(PN->getParent() == Header && "Can't evaluate PHI not in loop header!");
+
   // One entry must be a constant (coming in from outside of the loop), and the
   // second must be derived from the same PHI.
   bool SecondIsBackedge = L->contains(PN->getIncomingBlock(1));
-  Constant *StartCST =
-    dyn_cast<Constant>(PN->getIncomingValue(!SecondIsBackedge));
-  if (StartCST == 0) return getCouldNotCompute();  // Must be a constant.
-
-  Value *BEValue = PN->getIncomingValue(SecondIsBackedge);
-  if (getConstantEvolvingPHI(BEValue, L) != PN &&
-      !isa<Constant>(BEValue))
-    return getCouldNotCompute();  // Not derived from same PHI.
+  PHINode *PHI = 0;
+  for (BasicBlock::iterator I = Header->begin();
+       (PHI = dyn_cast<PHINode>(I)); ++I) {
+    Constant *StartCST =
+      dyn_cast<Constant>(PHI->getIncomingValue(!SecondIsBackedge));
+    if (StartCST == 0) continue;
+    CurrentIterVals[PHI] = StartCST;
+  }
+  if (!CurrentIterVals.count(PN))
+    return getCouldNotCompute();
 
   // Okay, we find a PHI node that defines the trip count of this loop.  Execute
   // the loop symbolically to determine when the condition gets a value of
   // "ExitWhen".
-  unsigned IterationNum = 0;
-  unsigned MaxIterations = MaxBruteForceIterations;   // Limit analysis.
-  for (Constant *PHIVal = StartCST;
-       IterationNum != MaxIterations; ++IterationNum) {
-    DenseMap<Instruction *, Constant *> PHIValMap;
-    PHIValMap[PN] = PHIVal;
+
+  unsigned MaxIterations = MaxBruteForceIterations;   // Limit analysis.  
+  for (unsigned IterationNum = 0; IterationNum != MaxIterations;++IterationNum){
     ConstantInt *CondVal =
-      dyn_cast_or_null<ConstantInt>(EvaluateExpression(Cond, L, PHIValMap, TD));
+      dyn_cast_or_null<ConstantInt>(EvaluateExpression(Cond, L,
+                                                       CurrentIterVals, TD));
 
     // Couldn't symbolically evaluate.
     if (!CondVal) return getCouldNotCompute();
@@ -4914,11 +4918,19 @@
       return getConstant(Type::getInt32Ty(getContext()), IterationNum);
     }
 
-    // Compute the value of the PHI node for the next iteration.
-    Constant *NextPHI = EvaluateExpression(BEValue, L, PHIValMap, TD);
-    if (NextPHI == 0 || NextPHI == PHIVal)
-      return getCouldNotCompute();// Couldn't evaluate or not making progress...
-    PHIVal = NextPHI;
+    // Update all the PHI nodes for the next iteration.
+    DenseMap<Instruction *, Constant *> NextIterVals;
+    for (DenseMap<Instruction *, Constant *>::const_iterator
+           I = CurrentIterVals.begin(), E = CurrentIterVals.end(); I != E; ++I){
+      PHINode *PHI = dyn_cast<PHINode>(I->first);
+      if (!PHI || PHI->getParent() != Header) continue;
+      Constant *&NextPHI = NextIterVals[PHI];
+      if (NextPHI) continue;    // Already computed!
+
+      Value *BEValue = PHI->getIncomingValue(SecondIsBackedge);
+      NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
+    }
+    CurrentIterVals.swap(NextIterVals);
   }
 
   // Too many iterations were needed to evaluate.

Modified: llvm/trunk/test/Analysis/ScalarEvolution/load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/load.ll?rev=142790&r1=142789&r2=142790&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/load.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/load.ll Mon Oct 24 01:57:05 2011
@@ -1,5 +1,4 @@
 ; RUN: opt -analyze -scalar-evolution < %s 2>&1 | FileCheck %s
-; PR11034
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
 target triple = "i386-pc-linux-gnu"
@@ -7,6 +6,7 @@
 @arr1 = internal unnamed_addr constant [50 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50], align 4
 @arr2 = internal unnamed_addr constant [50 x i32] [i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0], align 4
 
+; PR11034
 define i32 @test1() nounwind readnone {
 ; CHECK: test1
 entry:
@@ -31,3 +31,35 @@
 for.end:                                          ; preds = %for.body
   ret i32 %add2
 }
+
+
+%struct.ListNode = type { %struct.ListNode*, i32 }
+
+ at node5 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node4 to %struct.ListNode*), i32 4, [4 x i8] undef }, align 8
+ at node4 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node3 to %struct.ListNode*), i32 3, [4 x i8] undef }, align 8
+ at node3 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node2 to %struct.ListNode*), i32 2, [4 x i8] undef }, align 8
+ at node2 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node1 to %struct.ListNode*), i32 1, [4 x i8] undef }, align 8
+ at node1 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* null, i32 0, [4 x i8] undef }, align 8
+
+define i32 @test2() nounwind uwtable readonly {
+; CHECK: test2
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ]
+; CHECK: -->  %sum.02{{ *}}Exits: 10
+  %n.01 = phi %struct.ListNode* [ bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node5 to %struct.ListNode*), %entry ], [ %1, %for.body ]
+; CHECK: -->  %n.01{{ *}}Exits: @node1
+  %i = getelementptr inbounds %struct.ListNode* %n.01, i64 0, i32 1
+  %0 = load i32* %i, align 4
+  %add = add nsw i32 %0, %sum.02
+  %next = getelementptr inbounds %struct.ListNode* %n.01, i64 0, i32 0
+  %1 = load %struct.ListNode** %next, align 8
+; CHECK: -->  %1{{ *}}Exits: 0
+  %cmp = icmp eq %struct.ListNode* %1, null
+  br i1 %cmp, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret i32 %add
+}



From stpworld at narod.ru  Mon Oct 24 02:32:49 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Mon, 24 Oct 2011 11:32:49 +0400
Subject: [llvm-commits] [LLVM, llvm-nm,
 arm] Fix for nm-trivial-object.test and for nm-archive.test
In-Reply-To: <CACXTSinHzMOEUhDi2nJ17ZFs54zwX5WuNbpQgh+Qrw=scVTeow@mail.gmail.com>
References: <4EA1BF05.7030307@narod.ru>
	<CACXTSinHzMOEUhDi2nJ17ZFs54zwX5WuNbpQgh+Qrw=scVTeow@mail.gmail.com>
Message-ID: <4EA514A1.3020109@narod.ru>

Hi,
Yes, you right. Sorry, I actually mean clang-native-arm-cortex-a9:
http://lab.llvm.org:8011/builders/clang-native-arm-cortex-a9/builds/155

Regards,
Stepan.

Michael Spencer wrote:
> On Fri, Oct 21, 2011 at 11:50 AM, Stepan Dyatkovskiy<stpworld at narod.ru>  wrote:
>> Hi all,
>> Please find the patch for review that fixes nm-trivial-object.test and
>> nm-archive.test for arm architecture.
>>
>> Regards,
>> Stepan
>
> These tests are currently passing on the llvm-arm-linux buildbot.
> Where are you encountering the failure?
>
> This does, however, show that the code is currently wrong. It's trying
> to print a uint64_t as an unsigned. The code needs to use the address
> size from the object file to print either 8 byte or 4 byte addresses
> and sizes using the correct format string.
>
> Thanks for bringing this up!
>
> - Michael Spencer


From baldrick at free.fr  Mon Oct 24 03:29:56 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 24 Oct 2011 10:29:56 +0200
Subject: [llvm-commits] [PATCH][docs/CommandGuide] Reveal there is a
 "-help-hidden" option for opt command
In-Reply-To: <20111023100324.GA3546@cs.nctu.edu.tw>
References: <20111023100324.GA3546@cs.nctu.edu.tw>
Message-ID: <4EA52204.6090903@free.fr>

Hi chenwj,

>    I think it's a good idea to tell people there is a "-help-hidden"
> which shows more available options for `opt` command. For example,
> people might need to control how inline is done by `opt` but don't
> know there is "-inline-threshold" option which only appears with
> "-help-hidden" (see the link below).

I think it would be best to make -inline-threshold not be hidden.  I suspect
there are a bunch of hidden options that shouldn't be hidden, and a bunch of
not hidden options that should be hidden.  I think you shouldn't hesitate to
send patches that change the hidden flag.

Ciao, Duncan.

From geek4civic at gmail.com  Mon Oct 24 05:02:59 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Mon, 24 Oct 2011 10:02:59 -0000
Subject: [llvm-commits] [llvm] r142791 - /llvm/trunk/.gitignore
Message-ID: <20111024100300.0A32B3128018@llvm.org>

Author: chapuni
Date: Mon Oct 24 05:02:59 2011
New Revision: 142791

URL: http://llvm.org/viewvc/llvm-project?rev=142791&view=rev
Log:
Test commit

Modified:
    llvm/trunk/.gitignore

Modified: llvm/trunk/.gitignore
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/.gitignore?rev=142791&r1=142790&r2=142791&view=diff
==============================================================================
--- llvm/trunk/.gitignore (original)
+++ llvm/trunk/.gitignore Mon Oct 24 05:02:59 2011
@@ -38,3 +38,4 @@
 !projects/Makefile
 # Clang, which is tracked independently.
 tools/clang
+



From geek4civic at gmail.com  Mon Oct 24 05:03:25 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Mon, 24 Oct 2011 10:03:25 -0000
Subject: [llvm-commits] [llvm] r142792 - /llvm/trunk/.gitignore
Message-ID: <20111024100326.059F73128018@llvm.org>

Author: chapuni
Date: Mon Oct 24 05:03:25 2011
New Revision: 142792

URL: http://llvm.org/viewvc/llvm-project?rev=142792&view=rev
Log:
Revert "Test commit"

Modified:
    llvm/trunk/.gitignore

Modified: llvm/trunk/.gitignore
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/.gitignore?rev=142792&r1=142791&r2=142792&view=diff
==============================================================================
--- llvm/trunk/.gitignore (original)
+++ llvm/trunk/.gitignore Mon Oct 24 05:03:25 2011
@@ -38,4 +38,3 @@
 !projects/Makefile
 # Clang, which is tracked independently.
 tools/clang
-



From chandlerc at gmail.com  Mon Oct 24 07:01:08 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 24 Oct 2011 12:01:08 -0000
Subject: [llvm-commits] [llvm] r142793 - in /llvm/trunk:
 include/llvm/Analysis/BranchProbabilityInfo.h
 lib/Analysis/BranchProbabilityInfo.cpp
 test/Analysis/BranchProbabilityInfo/noreturn.ll
Message-ID: <20111024120109.0457F312800A@llvm.org>

Author: chandlerc
Date: Mon Oct 24 07:01:08 2011
New Revision: 142793

URL: http://llvm.org/viewvc/llvm-project?rev=142793&view=rev
Log:
Remove return heuristics from the static branch probabilities, and
introduce no-return or unreachable heuristics.

The return heuristics from the Ball and Larus paper don't work well in
practice as they pessimize early return paths. The only good hitrate
return heuristics are those for:
 - NULL return
 - Constant return
 - negative integer return

Only the last of these three can possibly require significant code for
the returning block, and even the last is fairly rare and usually also
a constant. As a consequence, even for the cold return paths, there is
little code on that return path, and so little code density to be gained
by sinking it. The places where sinking these blocks is valuable (inner
loops) will already be weighted appropriately as the edge is a loop-exit
branch.

All of this aside, early returns are nearly as common as all three of
these return categories, and should actually be predicted as taken!
Rather than muddy the waters of the static predictions, just remain
silent on returns and let the CFG itself dictate any layout or other
issues.

However, the return heuristic was flagging one very important case:
unreachable. Unfortunately it still gave a 1/4 chance of the
branch-to-unreachable occuring. It also didn't do a rigorous job of
finding those blocks which post-dominate an unreachable block.

This patch builds a more powerful analysis that should flag all branches
to blocks known to then reach unreachable. It also has better worst-case
runtime complexity by not looping through successors for each block. The
previous code would perform an N^2 walk in the event of a single entry
block branching to N successors with a switch where each successor falls
through to the next and they finally fall through to a return.

Test case added for noreturn heuristics. Also doxygen comments improved
along the way.

Added:
    llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll
Modified:
    llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
    llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp

Modified: llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h?rev=142793&r1=142792&r2=142793&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h Mon Oct 24 07:01:08 2011
@@ -17,6 +17,7 @@
 #include "llvm/InitializePasses.h"
 #include "llvm/Pass.h"
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/Support/BranchProbability.h"
 
 namespace llvm {
@@ -109,11 +110,14 @@
   /// \brief Track the last function we run over for printing.
   Function *LastF;
 
+  /// \brief Track the set of blocks directly succeeded by a returning block.
+  SmallPtrSet<BasicBlock *, 16> PostDominatedByUnreachable;
+
   /// \brief Get sum of the block successors' weights.
   uint32_t getSumForBlock(const BasicBlock *BB) const;
 
+  bool calcUnreachableHeuristics(BasicBlock *BB);
   bool calcMetadataWeights(BasicBlock *BB);
-  bool calcReturnHeuristics(BasicBlock *BB);
   bool calcPointerHeuristics(BasicBlock *BB);
   bool calcLoopBranchHeuristics(BasicBlock *BB);
   bool calcZeroHeuristics(BasicBlock *BB);

Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=142793&r1=142792&r2=142793&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Mon Oct 24 07:01:08 2011
@@ -18,6 +18,7 @@
 #include "llvm/Metadata.h"
 #include "llvm/Analysis/BranchProbabilityInfo.h"
 #include "llvm/Analysis/LoopInfo.h"
+#include "llvm/ADT/PostOrderIterator.h"
 #include "llvm/Support/CFG.h"
 #include "llvm/Support/Debug.h"
 
@@ -54,8 +55,18 @@
 static const uint32_t LBH_TAKEN_WEIGHT = 124;
 static const uint32_t LBH_NONTAKEN_WEIGHT = 4;
 
-static const uint32_t RH_TAKEN_WEIGHT = 24;
-static const uint32_t RH_NONTAKEN_WEIGHT = 8;
+/// \brief Unreachable-terminating branch taken weight.
+///
+/// This is the weight for a branch being taken to a block that terminates
+/// (eventually) in unreachable. These are predicted as unlikely as possible.
+static const uint32_t UR_TAKEN_WEIGHT = 1;
+
+/// \brief Unreachable-terminating branch not-taken weight.
+///
+/// This is the weight for a branch not being taken toward a block that
+/// terminates (eventually) in unreachable. Such a branch is essentially never
+/// taken.
+static const uint32_t UR_NONTAKEN_WEIGHT = 1023;
 
 static const uint32_t PH_TAKEN_WEIGHT = 20;
 static const uint32_t PH_NONTAKEN_WEIGHT = 12;
@@ -73,38 +84,62 @@
 // Minimum weight of an edge. Please note, that weight is NEVER 0.
 static const uint32_t MIN_WEIGHT = 1;
 
-// Return TRUE if BB leads directly to a Return Instruction.
-static bool isReturningBlock(BasicBlock *BB) {
-  SmallPtrSet<BasicBlock *, 8> Visited;
-
-  while (true) {
-    TerminatorInst *TI = BB->getTerminator();
-    if (isa<ReturnInst>(TI))
-      return true;
+static uint32_t getMaxWeightFor(BasicBlock *BB) {
+  return UINT32_MAX / BB->getTerminator()->getNumSuccessors();
+}
 
-    if (TI->getNumSuccessors() > 1)
-      break;
 
-    // It is unreachable block which we can consider as a return instruction.
-    if (TI->getNumSuccessors() == 0)
-      return true;
+/// \brief Calculate edge weights for successors lead to unreachable.
+///
+/// Predict that a successor which leads necessarily to an
+/// unreachable-terminated block as extremely unlikely.
+bool BranchProbabilityInfo::calcUnreachableHeuristics(BasicBlock *BB) {
+  TerminatorInst *TI = BB->getTerminator();
+  if (TI->getNumSuccessors() == 0) {
+    if (isa<UnreachableInst>(TI))
+      PostDominatedByUnreachable.insert(BB);
+    return false;
+  }
 
-    Visited.insert(BB);
-    BB = TI->getSuccessor(0);
+  SmallPtrSet<BasicBlock *, 4> UnreachableEdges;
+  SmallPtrSet<BasicBlock *, 4> ReachableEdges;
 
-    // Stop if cycle is detected.
-    if (Visited.count(BB))
-      return false;
+  for (succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) {
+    if (PostDominatedByUnreachable.count(*I))
+      UnreachableEdges.insert(*I);
+    else
+      ReachableEdges.insert(*I);
   }
 
-  return false;
-}
+  // If all successors are in the set of blocks post-dominated by unreachable,
+  // this block is too.
+  if (UnreachableEdges.size() == TI->getNumSuccessors())
+    PostDominatedByUnreachable.insert(BB);
+
+  // Skip probabilities if this block has a single successor or if all were
+  // reachable.
+  if (TI->getNumSuccessors() == 1 || UnreachableEdges.empty())
+    return false;
+
+  uint32_t UnreachableWeight =
+    std::max(UR_TAKEN_WEIGHT / UnreachableEdges.size(), MIN_WEIGHT);
+  for (SmallPtrSet<BasicBlock *, 4>::iterator I = UnreachableEdges.begin(),
+                                              E = UnreachableEdges.end();
+       I != E; ++I)
+    setEdgeWeight(BB, *I, UnreachableWeight);
+
+  if (ReachableEdges.empty())
+    return true;
+  uint32_t ReachableWeight =
+    std::max(UR_NONTAKEN_WEIGHT / ReachableEdges.size(), NORMAL_WEIGHT);
+  for (SmallPtrSet<BasicBlock *, 4>::iterator I = ReachableEdges.begin(),
+                                              E = ReachableEdges.end();
+       I != E; ++I)
+    setEdgeWeight(BB, *I, ReachableWeight);
 
-static uint32_t getMaxWeightFor(BasicBlock *BB) {
-  return UINT32_MAX / BB->getTerminator()->getNumSuccessors();
+  return true;
 }
 
-
 // Propagate existing explicit probabilities from either profile data or
 // 'expect' intrinsic processing.
 bool BranchProbabilityInfo::calcMetadataWeights(BasicBlock *BB) {
@@ -143,46 +178,6 @@
   return true;
 }
 
-// Calculate Edge Weights using "Return Heuristics". Predict a successor which
-// leads directly to Return Instruction will not be taken.
-bool BranchProbabilityInfo::calcReturnHeuristics(BasicBlock *BB){
-  if (BB->getTerminator()->getNumSuccessors() == 1)
-    return false;
-
-  SmallPtrSet<BasicBlock *, 4> ReturningEdges;
-  SmallPtrSet<BasicBlock *, 4> StayEdges;
-
-  for (succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) {
-    BasicBlock *Succ = *I;
-    if (isReturningBlock(Succ))
-      ReturningEdges.insert(Succ);
-    else
-      StayEdges.insert(Succ);
-  }
-
-  if (uint32_t numStayEdges = StayEdges.size()) {
-    uint32_t stayWeight = RH_TAKEN_WEIGHT / numStayEdges;
-    if (stayWeight < NORMAL_WEIGHT)
-      stayWeight = NORMAL_WEIGHT;
-
-    for (SmallPtrSet<BasicBlock *, 4>::iterator I = StayEdges.begin(),
-         E = StayEdges.end(); I != E; ++I)
-      setEdgeWeight(BB, *I, stayWeight);
-  }
-
-  if (uint32_t numRetEdges = ReturningEdges.size()) {
-    uint32_t retWeight = RH_NONTAKEN_WEIGHT / numRetEdges;
-    if (retWeight < MIN_WEIGHT)
-      retWeight = MIN_WEIGHT;
-    for (SmallPtrSet<BasicBlock *, 4>::iterator I = ReturningEdges.begin(),
-         E = ReturningEdges.end(); I != E; ++I) {
-      setEdgeWeight(BB, *I, retWeight);
-    }
-  }
-
-  return ReturningEdges.size() > 0;
-}
-
 // Calculate Edge Weights using "Pointer Heuristics". Predict a comparsion
 // between two pointer or pointer and NULL will fail.
 bool BranchProbabilityInfo::calcPointerHeuristics(BasicBlock *BB) {
@@ -390,20 +385,28 @@
 bool BranchProbabilityInfo::runOnFunction(Function &F) {
   LastF = &F; // Store the last function we ran on for printing.
   LI = &getAnalysis<LoopInfo>();
+  assert(PostDominatedByUnreachable.empty());
 
-  for (Function::iterator I = F.begin(), E = F.end(); I != E; ++I) {
-    if (calcMetadataWeights(I))
+  // Walk the basic blocks in post-order so that we can build up state about
+  // the successors of a block iteratively.
+  for (po_iterator<BasicBlock *> I = po_begin(&F.getEntryBlock()),
+                                 E = po_end(&F.getEntryBlock());
+       I != E; ++I) {
+    DEBUG(dbgs() << "Computing probabilities for " << I->getName() << "\n");
+    if (calcUnreachableHeuristics(*I))
       continue;
-    if (calcLoopBranchHeuristics(I))
+    if (calcMetadataWeights(*I))
       continue;
-    if (calcReturnHeuristics(I))
+    if (calcLoopBranchHeuristics(*I))
       continue;
-    if (calcPointerHeuristics(I))
+    if (calcPointerHeuristics(*I))
       continue;
-    if (calcZeroHeuristics(I))
+    if (calcZeroHeuristics(*I))
       continue;
-    calcFloatingPointHeuristics(I);
+    calcFloatingPointHeuristics(*I);
   }
+
+  PostDominatedByUnreachable.clear();
   return false;
 }
 

Added: llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll?rev=142793&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll (added)
+++ llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll Mon Oct 24 07:01:08 2011
@@ -0,0 +1,79 @@
+; Test the static branch probability heuristics for no-return functions.
+; RUN: opt < %s -analyze -branch-prob | FileCheck %s
+
+declare void @abort() noreturn
+
+define i32 @test1(i32 %a, i32 %b) {
+; CHECK: Printing analysis {{.*}} for function 'test1'
+entry:
+  %cond = icmp eq i32 %a, 42
+  br i1 %cond, label %exit, label %abort
+; CHECK: edge entry -> exit probability is 1023 / 1024
+; CHECK: edge entry -> abort probability is 1 / 1024
+
+abort:
+  call void @abort() noreturn
+  unreachable
+
+exit:
+  ret i32 %b
+}
+
+define i32 @test2(i32 %a, i32 %b) {
+; CHECK: Printing analysis {{.*}} for function 'test2'
+entry:
+  switch i32 %a, label %exit [i32 1, label %case_a
+                              i32 2, label %case_b
+                              i32 3, label %case_c
+                              i32 4, label %case_d]
+; CHECK: edge entry -> exit probability is 1023 / 1027
+; CHECK: edge entry -> case_a probability is 1 / 1027
+; CHECK: edge entry -> case_b probability is 1 / 1027
+; CHECK: edge entry -> case_c probability is 1 / 1027
+; CHECK: edge entry -> case_d probability is 1 / 1027
+
+case_a:
+  br label %case_b
+
+case_b:
+  br label %case_c
+
+case_c:
+  br label %case_d
+
+case_d:
+  call void @abort() noreturn
+  unreachable
+
+exit:
+  ret i32 %b
+}
+
+define i32 @test3(i32 %a, i32 %b) {
+; CHECK: Printing analysis {{.*}} for function 'test3'
+; Make sure we unify across multiple conditional branches.
+entry:
+  %cond1 = icmp eq i32 %a, 42
+  br i1 %cond1, label %exit, label %dom
+; CHECK: edge entry -> exit probability is 1023 / 1024
+; CHECK: edge entry -> dom probability is 1 / 1024
+
+dom:
+  %cond2 = icmp ult i32 %a, 42
+  br i1 %cond2, label %idom1, label %idom2
+; CHECK: edge dom -> idom1 probability is 1 / 2
+; CHECK: edge dom -> idom2 probability is 1 / 2
+
+idom1:
+  br label %abort
+
+idom2:
+  br label %abort
+
+abort:
+  call void @abort() noreturn
+  unreachable
+
+exit:
+  ret i32 %b
+}



From baldrick at free.fr  Mon Oct 24 08:31:03 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 24 Oct 2011 15:31:03 +0200
Subject: [llvm-commits] [PATCH][docs/CommandGuide] Reveal there is a
 "-help-hidden" option for opt command
In-Reply-To: <20111024091211.GA37465@cs.nctu.edu.tw>
References: <20111023100324.GA3546@cs.nctu.edu.tw> <4EA52204.6090903@free.fr>
	<20111024091211.GA37465@cs.nctu.edu.tw>
Message-ID: <4EA56897.8030205@free.fr>

>> I think it would be best to make -inline-threshold not be hidden.  I suspect
>> there are a bunch of hidden options that shouldn't be hidden, and a bunch of
>> not hidden options that should be hidden.  I think you shouldn't hesitate to
>> send patches that change the hidden flag.
>
>    Should we discuss which options should be hidden or not hidden on
> LLVMdev mailing list? I want to collect developers' comment on this.

These seem like candidates:

-disable-output
-inline-threshold
-inlinehint-threshold
-unroll-threshold

That said, these risk encouraging people to fiddle with thresholds rather than
reporting bugs about inlining (or whatever) not doing a good job automatically.

Ciao, Duncan.

From benny.kra at googlemail.com  Mon Oct 24 08:50:56 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 24 Oct 2011 13:50:56 -0000
Subject: [llvm-commits] [llvm] r142794 - in /llvm/trunk:
 include/llvm/Support/BranchProbability.h
 unittests/Support/BlockFrequencyTest.cpp
Message-ID: <20111024135056.313A8312800A@llvm.org>

Author: d0k
Date: Mon Oct 24 08:50:56 2011
New Revision: 142794

URL: http://llvm.org/viewvc/llvm-project?rev=142794&view=rev
Log:
Implement comparison operators for BranchProbability in a way that can't overflow INT64_MAX.

Add a test case for the edge case that triggers this. Thanks to Chandler for bringing this to my attention.

Modified:
    llvm/trunk/include/llvm/Support/BranchProbability.h
    llvm/trunk/unittests/Support/BlockFrequencyTest.cpp

Modified: llvm/trunk/include/llvm/Support/BranchProbability.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/BranchProbability.h?rev=142794&r1=142793&r2=142794&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/BranchProbability.h (original)
+++ llvm/trunk/include/llvm/Support/BranchProbability.h Mon Oct 24 08:50:56 2011
@@ -29,10 +29,6 @@
   // Denominator
   uint32_t D;
 
-  int64_t compare(BranchProbability RHS) const {
-    return (uint64_t)N * RHS.D - (uint64_t)D * RHS.N;
-  }
-
 public:
   BranchProbability(uint32_t n, uint32_t d) : N(n), D(d) {
     assert(d > 0 && "Denomiator cannot be 0!");
@@ -54,12 +50,24 @@
 
   void dump() const;
 
-  bool operator==(BranchProbability RHS) const { return compare(RHS) == 0; }
-  bool operator!=(BranchProbability RHS) const { return compare(RHS) != 0; }
-  bool operator< (BranchProbability RHS) const { return compare(RHS) <  0; }
-  bool operator> (BranchProbability RHS) const { return compare(RHS) >  0; }
-  bool operator<=(BranchProbability RHS) const { return compare(RHS) <= 0; }
-  bool operator>=(BranchProbability RHS) const { return compare(RHS) >= 0; }
+  bool operator==(BranchProbability RHS) const {
+    return (uint64_t)N * RHS.D == (uint64_t)D * RHS.N;
+  }
+  bool operator!=(BranchProbability RHS) const {
+    return !(*this == RHS);
+  }
+  bool operator<(BranchProbability RHS) const {
+    return (uint64_t)N * RHS.D < (uint64_t)D * RHS.N;
+  }
+  bool operator>(BranchProbability RHS) const {
+    return RHS < *this;
+  }
+  bool operator<=(BranchProbability RHS) const {
+    return (uint64_t)N * RHS.D <= (uint64_t)D * RHS.N;
+  }
+  bool operator>=(BranchProbability RHS) const {
+    return RHS <= *this;
+  }
 };
 
 raw_ostream &operator<<(raw_ostream &OS, const BranchProbability &Prob);

Modified: llvm/trunk/unittests/Support/BlockFrequencyTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/BlockFrequencyTest.cpp?rev=142794&r1=142793&r2=142794&view=diff
==============================================================================
--- llvm/trunk/unittests/Support/BlockFrequencyTest.cpp (original)
+++ llvm/trunk/unittests/Support/BlockFrequencyTest.cpp Mon Oct 24 08:50:56 2011
@@ -71,6 +71,15 @@
   EXPECT_TRUE(B > C);
   EXPECT_FALSE(B <= C);
   EXPECT_TRUE(B >= C);
+
+  BranchProbability BigZero(0, UINT32_MAX);
+  BranchProbability BigOne(UINT32_MAX, UINT32_MAX);
+  EXPECT_FALSE(BigZero == BigOne);
+  EXPECT_TRUE(BigZero != BigOne);
+  EXPECT_TRUE(BigZero < BigOne);
+  EXPECT_FALSE(BigZero > BigOne);
+  EXPECT_TRUE(BigZero <= BigOne);
+  EXPECT_FALSE(BigZero >= BigOne);
 }
 
 }



From benny.kra at googlemail.com  Mon Oct 24 08:57:57 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 24 Oct 2011 15:57:57 +0200
Subject: [llvm-commits] [llvm] r142751 - in /llvm/trunk:
	include/llvm/Support/BranchProbability.h
	lib/Analysis/BranchProbabilityInfo.cpp
	lib/Support/BranchProbability.cpp
	unittests/Support/BlockFrequencyTest.cpp
In-Reply-To: <CAGCO0KgR72YaG3=20AHcvuUCD5a5uHpXAvttnZROuxeFs7C78A@mail.gmail.com>
References: <20111023111914.98F8D3524006@llvm.org>
	<CAGCO0KgR72YaG3=20AHcvuUCD5a5uHpXAvttnZROuxeFs7C78A@mail.gmail.com>
Message-ID: <1ED8602D-45A1-4455-81B8-C9C2416D8C8F@googlemail.com>


On 23.10.2011, at 21:35, Chandler Carruth wrote:

> After some discussion on IRC...
> 
> On Sun, Oct 23, 2011 at 4:19 AM, Benjamin Kramer <benny.kra at googlemail.com> wrote:
> +  int64_t compare(BranchProbability RHS) const {
> +    return (uint64_t)N * RHS.D - (uint64_t)D * RHS.N;
> +  }
> 
> It would be good to comment here that the result of the LHS of the subtract can't be larger than INT64_MAX without the RHS being large enough to reduce it because N <= D. It might also be nice to just assert that fact.
>  
> --- llvm/trunk/unittests/Support/BlockFrequencyTest.cpp (original)
> +++ llvm/trunk/unittests/Support/BlockFrequencyTest.cpp Sun Oct 23 06:19:14 2011
> @@ -53,4 +53,24 @@
>   EXPECT_EQ(Freq.getFrequency(), UINT64_MAX);
>  }
> 
> +TEST(BlockFrequencyTest, ProbabilityCompare) {
> +  BranchProbability A(4, 5);
> +  BranchProbability B(4U << 29, 5U << 29);
> 
> Maybe add a test case that compares B against a RHS with a similarly large denominator value to ensure that overflow of INT64_MAX is indeed brought back down in the computation? In particular the interesting one to my mind is (UINT32_MAX, UINT32_MAX) vs. (1, UINT32_MAX).

I could come up with a case where the subtraction gives wrong results. UINT32_MAX/UINT32_MAX is bigger than 0/UINT32_MAX but UINT32_MAX*UINT32_MAX - UINT32_MAX*0 is still negative. Fixed in r142794.

Thanks for reviewing this!
- Ben

From rdivacky at freebsd.org  Mon Oct 24 11:09:44 2011
From: rdivacky at freebsd.org (Roman Divacky)
Date: Mon, 24 Oct 2011 18:09:44 +0200
Subject: [llvm-commits] [llvm] r142793 - in /llvm/trunk:
	include/llvm/Analysis/BranchProbabilityInfo.h
	lib/Analysis/BranchProbabilityInfo.cpp
	test/Analysis/BranchProbabilityInfo/noreturn.ll
In-Reply-To: <20111024120109.0457F312800A@llvm.org>
References: <20111024120109.0457F312800A@llvm.org>
Message-ID: <20111024160944.GA84963@freebsd.org>

This brings mixed results. It speeds most of the perlbench subbenchmarks
a little but slows down a few by A LOT (ie. 20%). The overall result
is +/- nothing (I saw 96% -> 95% in my vs gcc benchmark but that's probably
noise). Both before and after this commit it performs 1% better than without
the block placement.

You can see the detailed results here:


          http://lev.vlakno.cz/~rdivacky/perlbench-clang-block-placement.html


The lab1 is vanilla clang, lab2 is r142793 with the block placement enabled
and lab3 is 142793 with block placement enabled but with r142793 reverted
(ie. llvm before this commit)

The loop/* tests seems to have taken a big hit.

On Mon, Oct 24, 2011 at 12:01:08PM -0000, Chandler Carruth wrote:
> Author: chandlerc
> Date: Mon Oct 24 07:01:08 2011
> New Revision: 142793
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=142793&view=rev
> Log:
> Remove return heuristics from the static branch probabilities, and
> introduce no-return or unreachable heuristics.
> 
> The return heuristics from the Ball and Larus paper don't work well in
> practice as they pessimize early return paths. The only good hitrate
> return heuristics are those for:
>  - NULL return
>  - Constant return
>  - negative integer return
> 
> Only the last of these three can possibly require significant code for
> the returning block, and even the last is fairly rare and usually also
> a constant. As a consequence, even for the cold return paths, there is
> little code on that return path, and so little code density to be gained
> by sinking it. The places where sinking these blocks is valuable (inner
> loops) will already be weighted appropriately as the edge is a loop-exit
> branch.
> 
> All of this aside, early returns are nearly as common as all three of
> these return categories, and should actually be predicted as taken!
> Rather than muddy the waters of the static predictions, just remain
> silent on returns and let the CFG itself dictate any layout or other
> issues.
> 
> However, the return heuristic was flagging one very important case:
> unreachable. Unfortunately it still gave a 1/4 chance of the
> branch-to-unreachable occuring. It also didn't do a rigorous job of
> finding those blocks which post-dominate an unreachable block.
> 
> This patch builds a more powerful analysis that should flag all branches
> to blocks known to then reach unreachable. It also has better worst-case
> runtime complexity by not looping through successors for each block. The
> previous code would perform an N^2 walk in the event of a single entry
> block branching to N successors with a switch where each successor falls
> through to the next and they finally fall through to a return.
> 
> Test case added for noreturn heuristics. Also doxygen comments improved
> along the way.
> 
> Added:
>     llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll
> Modified:
>     llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
>     llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
> 
> Modified: llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h?rev=142793&r1=142792&r2=142793&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h (original)
> +++ llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h Mon Oct 24 07:01:08 2011
> @@ -17,6 +17,7 @@
>  #include "llvm/InitializePasses.h"
>  #include "llvm/Pass.h"
>  #include "llvm/ADT/DenseMap.h"
> +#include "llvm/ADT/SmallPtrSet.h"
>  #include "llvm/Support/BranchProbability.h"
>  
>  namespace llvm {
> @@ -109,11 +110,14 @@
>    /// \brief Track the last function we run over for printing.
>    Function *LastF;
>  
> +  /// \brief Track the set of blocks directly succeeded by a returning block.
> +  SmallPtrSet<BasicBlock *, 16> PostDominatedByUnreachable;
> +
>    /// \brief Get sum of the block successors' weights.
>    uint32_t getSumForBlock(const BasicBlock *BB) const;
>  
> +  bool calcUnreachableHeuristics(BasicBlock *BB);
>    bool calcMetadataWeights(BasicBlock *BB);
> -  bool calcReturnHeuristics(BasicBlock *BB);
>    bool calcPointerHeuristics(BasicBlock *BB);
>    bool calcLoopBranchHeuristics(BasicBlock *BB);
>    bool calcZeroHeuristics(BasicBlock *BB);
> 
> Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=142793&r1=142792&r2=142793&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original)
> +++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Mon Oct 24 07:01:08 2011
> @@ -18,6 +18,7 @@
>  #include "llvm/Metadata.h"
>  #include "llvm/Analysis/BranchProbabilityInfo.h"
>  #include "llvm/Analysis/LoopInfo.h"
> +#include "llvm/ADT/PostOrderIterator.h"
>  #include "llvm/Support/CFG.h"
>  #include "llvm/Support/Debug.h"
>  
> @@ -54,8 +55,18 @@
>  static const uint32_t LBH_TAKEN_WEIGHT = 124;
>  static const uint32_t LBH_NONTAKEN_WEIGHT = 4;
>  
> -static const uint32_t RH_TAKEN_WEIGHT = 24;
> -static const uint32_t RH_NONTAKEN_WEIGHT = 8;
> +/// \brief Unreachable-terminating branch taken weight.
> +///
> +/// This is the weight for a branch being taken to a block that terminates
> +/// (eventually) in unreachable. These are predicted as unlikely as possible.
> +static const uint32_t UR_TAKEN_WEIGHT = 1;
> +
> +/// \brief Unreachable-terminating branch not-taken weight.
> +///
> +/// This is the weight for a branch not being taken toward a block that
> +/// terminates (eventually) in unreachable. Such a branch is essentially never
> +/// taken.
> +static const uint32_t UR_NONTAKEN_WEIGHT = 1023;
>  
>  static const uint32_t PH_TAKEN_WEIGHT = 20;
>  static const uint32_t PH_NONTAKEN_WEIGHT = 12;
> @@ -73,38 +84,62 @@
>  // Minimum weight of an edge. Please note, that weight is NEVER 0.
>  static const uint32_t MIN_WEIGHT = 1;
>  
> -// Return TRUE if BB leads directly to a Return Instruction.
> -static bool isReturningBlock(BasicBlock *BB) {
> -  SmallPtrSet<BasicBlock *, 8> Visited;
> -
> -  while (true) {
> -    TerminatorInst *TI = BB->getTerminator();
> -    if (isa<ReturnInst>(TI))
> -      return true;
> +static uint32_t getMaxWeightFor(BasicBlock *BB) {
> +  return UINT32_MAX / BB->getTerminator()->getNumSuccessors();
> +}
>  
> -    if (TI->getNumSuccessors() > 1)
> -      break;
>  
> -    // It is unreachable block which we can consider as a return instruction.
> -    if (TI->getNumSuccessors() == 0)
> -      return true;
> +/// \brief Calculate edge weights for successors lead to unreachable.
> +///
> +/// Predict that a successor which leads necessarily to an
> +/// unreachable-terminated block as extremely unlikely.
> +bool BranchProbabilityInfo::calcUnreachableHeuristics(BasicBlock *BB) {
> +  TerminatorInst *TI = BB->getTerminator();
> +  if (TI->getNumSuccessors() == 0) {
> +    if (isa<UnreachableInst>(TI))
> +      PostDominatedByUnreachable.insert(BB);
> +    return false;
> +  }
>  
> -    Visited.insert(BB);
> -    BB = TI->getSuccessor(0);
> +  SmallPtrSet<BasicBlock *, 4> UnreachableEdges;
> +  SmallPtrSet<BasicBlock *, 4> ReachableEdges;
>  
> -    // Stop if cycle is detected.
> -    if (Visited.count(BB))
> -      return false;
> +  for (succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) {
> +    if (PostDominatedByUnreachable.count(*I))
> +      UnreachableEdges.insert(*I);
> +    else
> +      ReachableEdges.insert(*I);
>    }
>  
> -  return false;
> -}
> +  // If all successors are in the set of blocks post-dominated by unreachable,
> +  // this block is too.
> +  if (UnreachableEdges.size() == TI->getNumSuccessors())
> +    PostDominatedByUnreachable.insert(BB);
> +
> +  // Skip probabilities if this block has a single successor or if all were
> +  // reachable.
> +  if (TI->getNumSuccessors() == 1 || UnreachableEdges.empty())
> +    return false;
> +
> +  uint32_t UnreachableWeight =
> +    std::max(UR_TAKEN_WEIGHT / UnreachableEdges.size(), MIN_WEIGHT);
> +  for (SmallPtrSet<BasicBlock *, 4>::iterator I = UnreachableEdges.begin(),
> +                                              E = UnreachableEdges.end();
> +       I != E; ++I)
> +    setEdgeWeight(BB, *I, UnreachableWeight);
> +
> +  if (ReachableEdges.empty())
> +    return true;
> +  uint32_t ReachableWeight =
> +    std::max(UR_NONTAKEN_WEIGHT / ReachableEdges.size(), NORMAL_WEIGHT);
> +  for (SmallPtrSet<BasicBlock *, 4>::iterator I = ReachableEdges.begin(),
> +                                              E = ReachableEdges.end();
> +       I != E; ++I)
> +    setEdgeWeight(BB, *I, ReachableWeight);
>  
> -static uint32_t getMaxWeightFor(BasicBlock *BB) {
> -  return UINT32_MAX / BB->getTerminator()->getNumSuccessors();
> +  return true;
>  }
>  
> -
>  // Propagate existing explicit probabilities from either profile data or
>  // 'expect' intrinsic processing.
>  bool BranchProbabilityInfo::calcMetadataWeights(BasicBlock *BB) {
> @@ -143,46 +178,6 @@
>    return true;
>  }
>  
> -// Calculate Edge Weights using "Return Heuristics". Predict a successor which
> -// leads directly to Return Instruction will not be taken.
> -bool BranchProbabilityInfo::calcReturnHeuristics(BasicBlock *BB){
> -  if (BB->getTerminator()->getNumSuccessors() == 1)
> -    return false;
> -
> -  SmallPtrSet<BasicBlock *, 4> ReturningEdges;
> -  SmallPtrSet<BasicBlock *, 4> StayEdges;
> -
> -  for (succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) {
> -    BasicBlock *Succ = *I;
> -    if (isReturningBlock(Succ))
> -      ReturningEdges.insert(Succ);
> -    else
> -      StayEdges.insert(Succ);
> -  }
> -
> -  if (uint32_t numStayEdges = StayEdges.size()) {
> -    uint32_t stayWeight = RH_TAKEN_WEIGHT / numStayEdges;
> -    if (stayWeight < NORMAL_WEIGHT)
> -      stayWeight = NORMAL_WEIGHT;
> -
> -    for (SmallPtrSet<BasicBlock *, 4>::iterator I = StayEdges.begin(),
> -         E = StayEdges.end(); I != E; ++I)
> -      setEdgeWeight(BB, *I, stayWeight);
> -  }
> -
> -  if (uint32_t numRetEdges = ReturningEdges.size()) {
> -    uint32_t retWeight = RH_NONTAKEN_WEIGHT / numRetEdges;
> -    if (retWeight < MIN_WEIGHT)
> -      retWeight = MIN_WEIGHT;
> -    for (SmallPtrSet<BasicBlock *, 4>::iterator I = ReturningEdges.begin(),
> -         E = ReturningEdges.end(); I != E; ++I) {
> -      setEdgeWeight(BB, *I, retWeight);
> -    }
> -  }
> -
> -  return ReturningEdges.size() > 0;
> -}
> -
>  // Calculate Edge Weights using "Pointer Heuristics". Predict a comparsion
>  // between two pointer or pointer and NULL will fail.
>  bool BranchProbabilityInfo::calcPointerHeuristics(BasicBlock *BB) {
> @@ -390,20 +385,28 @@
>  bool BranchProbabilityInfo::runOnFunction(Function &F) {
>    LastF = &F; // Store the last function we ran on for printing.
>    LI = &getAnalysis<LoopInfo>();
> +  assert(PostDominatedByUnreachable.empty());
>  
> -  for (Function::iterator I = F.begin(), E = F.end(); I != E; ++I) {
> -    if (calcMetadataWeights(I))
> +  // Walk the basic blocks in post-order so that we can build up state about
> +  // the successors of a block iteratively.
> +  for (po_iterator<BasicBlock *> I = po_begin(&F.getEntryBlock()),
> +                                 E = po_end(&F.getEntryBlock());
> +       I != E; ++I) {
> +    DEBUG(dbgs() << "Computing probabilities for " << I->getName() << "\n");
> +    if (calcUnreachableHeuristics(*I))
>        continue;
> -    if (calcLoopBranchHeuristics(I))
> +    if (calcMetadataWeights(*I))
>        continue;
> -    if (calcReturnHeuristics(I))
> +    if (calcLoopBranchHeuristics(*I))
>        continue;
> -    if (calcPointerHeuristics(I))
> +    if (calcPointerHeuristics(*I))
>        continue;
> -    if (calcZeroHeuristics(I))
> +    if (calcZeroHeuristics(*I))
>        continue;
> -    calcFloatingPointHeuristics(I);
> +    calcFloatingPointHeuristics(*I);
>    }
> +
> +  PostDominatedByUnreachable.clear();
>    return false;
>  }
>  
> 
> Added: llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll?rev=142793&view=auto
> ==============================================================================
> --- llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll (added)
> +++ llvm/trunk/test/Analysis/BranchProbabilityInfo/noreturn.ll Mon Oct 24 07:01:08 2011
> @@ -0,0 +1,79 @@
> +; Test the static branch probability heuristics for no-return functions.
> +; RUN: opt < %s -analyze -branch-prob | FileCheck %s
> +
> +declare void @abort() noreturn
> +
> +define i32 @test1(i32 %a, i32 %b) {
> +; CHECK: Printing analysis {{.*}} for function 'test1'
> +entry:
> +  %cond = icmp eq i32 %a, 42
> +  br i1 %cond, label %exit, label %abort
> +; CHECK: edge entry -> exit probability is 1023 / 1024
> +; CHECK: edge entry -> abort probability is 1 / 1024
> +
> +abort:
> +  call void @abort() noreturn
> +  unreachable
> +
> +exit:
> +  ret i32 %b
> +}
> +
> +define i32 @test2(i32 %a, i32 %b) {
> +; CHECK: Printing analysis {{.*}} for function 'test2'
> +entry:
> +  switch i32 %a, label %exit [i32 1, label %case_a
> +                              i32 2, label %case_b
> +                              i32 3, label %case_c
> +                              i32 4, label %case_d]
> +; CHECK: edge entry -> exit probability is 1023 / 1027
> +; CHECK: edge entry -> case_a probability is 1 / 1027
> +; CHECK: edge entry -> case_b probability is 1 / 1027
> +; CHECK: edge entry -> case_c probability is 1 / 1027
> +; CHECK: edge entry -> case_d probability is 1 / 1027
> +
> +case_a:
> +  br label %case_b
> +
> +case_b:
> +  br label %case_c
> +
> +case_c:
> +  br label %case_d
> +
> +case_d:
> +  call void @abort() noreturn
> +  unreachable
> +
> +exit:
> +  ret i32 %b
> +}
> +
> +define i32 @test3(i32 %a, i32 %b) {
> +; CHECK: Printing analysis {{.*}} for function 'test3'
> +; Make sure we unify across multiple conditional branches.
> +entry:
> +  %cond1 = icmp eq i32 %a, 42
> +  br i1 %cond1, label %exit, label %dom
> +; CHECK: edge entry -> exit probability is 1023 / 1024
> +; CHECK: edge entry -> dom probability is 1 / 1024
> +
> +dom:
> +  %cond2 = icmp ult i32 %a, 42
> +  br i1 %cond2, label %idom1, label %idom2
> +; CHECK: edge dom -> idom1 probability is 1 / 2
> +; CHECK: edge dom -> idom2 probability is 1 / 2
> +
> +idom1:
> +  br label %abort
> +
> +idom2:
> +  br label %abort
> +
> +abort:
> +  call void @abort() noreturn
> +  unreachable
> +
> +exit:
> +  ret i32 %b
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

From chandlerc at gmail.com  Mon Oct 24 11:51:55 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 24 Oct 2011 16:51:55 -0000
Subject: [llvm-commits] [llvm] r142799 -
	/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
Message-ID: <20111024165155.83F02312800A@llvm.org>

Author: chandlerc
Date: Mon Oct 24 11:51:55 2011
New Revision: 142799

URL: http://llvm.org/viewvc/llvm-project?rev=142799&view=rev
Log:
Sink an otherwise unused variable's initializer into the asserts that
used it. Fixes an unused variable warning from GCC on release builds.

Modified:
    llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp

Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=142799&r1=142798&r2=142799&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Mon Oct 24 11:51:55 2011
@@ -395,9 +395,8 @@
 
 void MachineBlockPlacement::placeChainsTopologically(MachineFunction &F) {
   MachineBasicBlock *EntryB = &F.front();
-  BlockChain *EntryChain = BlockToChain[EntryB];
-  assert(EntryChain && "Missing chain for entry block");
-  assert(*EntryChain->begin() == EntryB &&
+  assert(BlockToChain[EntryB] && "Missing chain for entry block");
+  assert(*BlockToChain[EntryB]->begin() == EntryB &&
          "Entry block is not the head of the entry block chain");
 
   // Walk the blocks in RPO, and insert each block for a chain in order the



From isanbard at gmail.com  Mon Oct 24 12:12:36 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 24 Oct 2011 17:12:36 -0000
Subject: [llvm-commits] [llvm] r142800 -
	/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
Message-ID: <20111024171236.6998F312800A@llvm.org>

Author: void
Date: Mon Oct 24 12:12:36 2011
New Revision: 142800

URL: http://llvm.org/viewvc/llvm-project?rev=142800&view=rev
Log:
Cleanup. Get rid of the old SjLj EH lowering code. No functionality change.

Modified:
    llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=142800&r1=142799&r2=142800&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Mon Oct 24 12:12:36 2011
@@ -30,17 +30,13 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/IRBuilder.h"
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include <set>
 using namespace llvm;
 
-static cl::opt<bool> DisableOldSjLjEH("disable-old-sjlj-eh", cl::Hidden,
-                                      cl::init(true),
-    cl::desc("Disable the old SjLj EH preparation pass"));
-
 STATISTIC(NumInvokes, "Number of invokes replaced");
-STATISTIC(NumUnwinds, "Number of unwinds replaced");
 STATISTIC(NumSpilled, "Number of registers live across unwind edges");
 
 namespace {
@@ -52,16 +48,12 @@
     Constant *BuiltinSetjmpFn;
     Constant *FrameAddrFn;
     Constant *StackAddrFn;
-    Constant *StackRestoreFn;
     Constant *LSDAAddrFn;
     Value *PersonalityFn;
-    Constant *SelectorFn;
-    Constant *ExceptionFn;
     Constant *CallSiteFn;
     Constant *DispatchSetupFn;
     Constant *FuncCtxFn;
     Value *CallSite;
-    DenseMap<InvokeInst*, BasicBlock*> LPadSuccMap;
   public:
     static char ID; // Pass identification, replacement for typeid
     explicit SjLjEHPass(const TargetLowering *tli = NULL)
@@ -79,13 +71,7 @@
     Value *setupFunctionContext(Function &F, ArrayRef<LandingPadInst*> LPads);
     void lowerIncomingArguments(Function &F);
     void lowerAcrossUnwindEdges(Function &F, ArrayRef<InvokeInst*> Invokes);
-
     void insertCallSiteStore(Instruction *I, int Number, Value *CallSite);
-    void markInvokeCallSite(InvokeInst *II, int InvokeNo, Value *CallSite,
-                            SwitchInst *CatchSwitch);
-    void splitLiveRangesAcrossInvokes(SmallVector<InvokeInst*,16> &Invokes);
-    void splitLandingPad(InvokeInst *II);
-    bool insertSjLjEHSupport(Function &F);
   };
 } // end anonymous namespace
 
@@ -121,11 +107,8 @@
                           (Type *)0);
   FrameAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::frameaddress);
   StackAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::stacksave);
-  StackRestoreFn = Intrinsic::getDeclaration(&M, Intrinsic::stackrestore);
   BuiltinSetjmpFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_setjmp);
   LSDAAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_lsda);
-  SelectorFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_selector);
-  ExceptionFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_exception);
   CallSiteFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_callsite);
   DispatchSetupFn
     = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_dispatch_setup);
@@ -145,572 +128,16 @@
   new StoreInst(CallSiteNoC, CallSite, true, I);  // volatile
 }
 
-/// splitLandingPad - Split a landing pad. This takes considerable care because
-/// of PHIs and other nasties. The problem is that the jump table needs to jump
-/// to the landing pad block. However, the landing pad block can be jumped to
-/// only by an invoke instruction. So we clone the landingpad instruction into
-/// its own basic block, have the invoke jump to there. The landingpad
-/// instruction's basic block's successor is now the target for the jump table.
-///
-/// But because of PHI nodes, we need to create another basic block for the jump
-/// table to jump to. This is definitely a hack, because the values for the PHI
-/// nodes may not be defined on the edge from the jump table. But that's okay,
-/// because the jump table is simply a construct to mimic what is happening in
-/// the CFG. So the values are mysteriously there, even though there is no value
-/// for the PHI from the jump table's edge (hence calling this a hack).
-void SjLjEHPass::splitLandingPad(InvokeInst *II) {
-  SmallVector<BasicBlock*, 2> NewBBs;
-  SplitLandingPadPredecessors(II->getUnwindDest(), II->getParent(),
-                              ".1", ".2", this, NewBBs);
-
-  // Create an empty block so that the jump table has something to jump to
-  // which doesn't have any PHI nodes.
-  BasicBlock *LPad = NewBBs[0];
-  BasicBlock *Succ = *succ_begin(LPad);
-  BasicBlock *JumpTo = BasicBlock::Create(II->getContext(), "jt.land",
-                                          LPad->getParent(), Succ);
-  LPad->getTerminator()->eraseFromParent();
-  BranchInst::Create(JumpTo, LPad);
-  BranchInst::Create(Succ, JumpTo);
-  LPadSuccMap[II] = JumpTo;
-
-  for (BasicBlock::iterator I = Succ->begin(); isa<PHINode>(I); ++I) {
-    PHINode *PN = cast<PHINode>(I);
-    Value *Val = PN->removeIncomingValue(LPad, false);
-    PN->addIncoming(Val, JumpTo);
-  }
-}
-
-/// markInvokeCallSite - Insert code to mark the call_site for this invoke
-void SjLjEHPass::markInvokeCallSite(InvokeInst *II, int InvokeNo,
-                                    Value *CallSite,
-                                    SwitchInst *CatchSwitch) {
-  ConstantInt *CallSiteNoC= ConstantInt::get(Type::getInt32Ty(II->getContext()),
-                                              InvokeNo);
-  // The runtime comes back to the dispatcher with the call_site - 1 in
-  // the context. Odd, but there it is.
-  ConstantInt *SwitchValC = ConstantInt::get(Type::getInt32Ty(II->getContext()),
-                                             InvokeNo - 1);
-
-  // If the unwind edge has phi nodes, split the edge.
-  if (isa<PHINode>(II->getUnwindDest()->begin())) {
-    // FIXME: New EH - This if-condition will be always true in the new scheme.
-    if (II->getUnwindDest()->isLandingPad())
-      splitLandingPad(II);
-    else
-      SplitCriticalEdge(II, 1, this);
-
-    // If there are any phi nodes left, they must have a single predecessor.
-    while (PHINode *PN = dyn_cast<PHINode>(II->getUnwindDest()->begin())) {
-      PN->replaceAllUsesWith(PN->getIncomingValue(0));
-      PN->eraseFromParent();
-    }
-  }
-
-  // Insert the store of the call site value
-  insertCallSiteStore(II, InvokeNo, CallSite);
-
-  // Record the call site value for the back end so it stays associated with
-  // the invoke.
-  CallInst::Create(CallSiteFn, CallSiteNoC, "", II);
-
-  // Add a switch case to our unwind block.
-  if (BasicBlock *SuccBB = LPadSuccMap[II]) {
-    CatchSwitch->addCase(SwitchValC, SuccBB);
-  } else {
-    CatchSwitch->addCase(SwitchValC, II->getUnwindDest());
-  }
-
-  // We still want this to look like an invoke so we emit the LSDA properly,
-  // so we don't transform the invoke into a call here.
-}
-
 /// MarkBlocksLiveIn - Insert BB and all of its predescessors into LiveBBs until
 /// we reach blocks we've already seen.
-static void MarkBlocksLiveIn(BasicBlock *BB, std::set<BasicBlock*> &LiveBBs) {
-  if (!LiveBBs.insert(BB).second) return; // already been here.
+static void MarkBlocksLiveIn(BasicBlock *BB,
+                             SmallPtrSet<BasicBlock*, 64> &LiveBBs) {
+  if (!LiveBBs.insert(BB)) return; // already been here.
 
   for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
     MarkBlocksLiveIn(*PI, LiveBBs);
 }
 
-/// splitLiveRangesAcrossInvokes - Each value that is live across an unwind edge
-/// we spill into a stack location, guaranteeing that there is nothing live
-/// across the unwind edge.  This process also splits all critical edges
-/// coming out of invoke's.
-/// FIXME: Move this function to a common utility file (Local.cpp?) so
-/// both SjLj and LowerInvoke can use it.
-void SjLjEHPass::
-splitLiveRangesAcrossInvokes(SmallVector<InvokeInst*,16> &Invokes) {
-  // First step, split all critical edges from invoke instructions.
-  for (unsigned i = 0, e = Invokes.size(); i != e; ++i) {
-    InvokeInst *II = Invokes[i];
-    SplitCriticalEdge(II, 0, this);
-
-    // FIXME: New EH - This if-condition will be always true in the new scheme.
-    if (II->getUnwindDest()->isLandingPad())
-      splitLandingPad(II);
-    else
-      SplitCriticalEdge(II, 1, this);
-
-    assert(!isa<PHINode>(II->getNormalDest()) &&
-           !isa<PHINode>(II->getUnwindDest()) &&
-           "Critical edge splitting left single entry phi nodes?");
-  }
-
-  Function *F = Invokes.back()->getParent()->getParent();
-
-  // To avoid having to handle incoming arguments specially, we lower each arg
-  // to a copy instruction in the entry block.  This ensures that the argument
-  // value itself cannot be live across the entry block.
-  BasicBlock::iterator AfterAllocaInsertPt = F->begin()->begin();
-  while (isa<AllocaInst>(AfterAllocaInsertPt) &&
-        isa<ConstantInt>(cast<AllocaInst>(AfterAllocaInsertPt)->getArraySize()))
-    ++AfterAllocaInsertPt;
-  for (Function::arg_iterator AI = F->arg_begin(), E = F->arg_end();
-       AI != E; ++AI) {
-    Type *Ty = AI->getType();
-    // Aggregate types can't be cast, but are legal argument types, so we have
-    // to handle them differently. We use an extract/insert pair as a
-    // lightweight method to achieve the same goal.
-    if (isa<StructType>(Ty) || isa<ArrayType>(Ty) || isa<VectorType>(Ty)) {
-      Instruction *EI = ExtractValueInst::Create(AI, 0, "",AfterAllocaInsertPt);
-      Instruction *NI = InsertValueInst::Create(AI, EI, 0);
-      NI->insertAfter(EI);
-      AI->replaceAllUsesWith(NI);
-      // Set the operand of the instructions back to the AllocaInst.
-      EI->setOperand(0, AI);
-      NI->setOperand(0, AI);
-    } else {
-      // This is always a no-op cast because we're casting AI to AI->getType()
-      // so src and destination types are identical. BitCast is the only
-      // possibility.
-      CastInst *NC = new BitCastInst(
-        AI, AI->getType(), AI->getName()+".tmp", AfterAllocaInsertPt);
-      AI->replaceAllUsesWith(NC);
-      // Set the operand of the cast instruction back to the AllocaInst.
-      // Normally it's forbidden to replace a CastInst's operand because it
-      // could cause the opcode to reflect an illegal conversion. However,
-      // we're replacing it here with the same value it was constructed with.
-      // We do this because the above replaceAllUsesWith() clobbered the
-      // operand, but we want this one to remain.
-      NC->setOperand(0, AI);
-    }
-  }
-
-  // Finally, scan the code looking for instructions with bad live ranges.
-  for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB)
-    for (BasicBlock::iterator II = BB->begin(), E = BB->end(); II != E; ++II) {
-      // Ignore obvious cases we don't have to handle.  In particular, most
-      // instructions either have no uses or only have a single use inside the
-      // current block.  Ignore them quickly.
-      Instruction *Inst = II;
-      if (Inst->use_empty()) continue;
-      if (Inst->hasOneUse() &&
-          cast<Instruction>(Inst->use_back())->getParent() == BB &&
-          !isa<PHINode>(Inst->use_back())) continue;
-
-      // If this is an alloca in the entry block, it's not a real register
-      // value.
-      if (AllocaInst *AI = dyn_cast<AllocaInst>(Inst))
-        if (isa<ConstantInt>(AI->getArraySize()) && BB == F->begin())
-          continue;
-
-      // Avoid iterator invalidation by copying users to a temporary vector.
-      SmallVector<Instruction*,16> Users;
-      for (Value::use_iterator UI = Inst->use_begin(), E = Inst->use_end();
-           UI != E; ++UI) {
-        Instruction *User = cast<Instruction>(*UI);
-        if (User->getParent() != BB || isa<PHINode>(User))
-          Users.push_back(User);
-      }
-
-      // Find all of the blocks that this value is live in.
-      std::set<BasicBlock*> LiveBBs;
-      LiveBBs.insert(Inst->getParent());
-      while (!Users.empty()) {
-        Instruction *U = Users.back();
-        Users.pop_back();
-
-        if (!isa<PHINode>(U)) {
-          MarkBlocksLiveIn(U->getParent(), LiveBBs);
-        } else {
-          // Uses for a PHI node occur in their predecessor block.
-          PHINode *PN = cast<PHINode>(U);
-          for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
-            if (PN->getIncomingValue(i) == Inst)
-              MarkBlocksLiveIn(PN->getIncomingBlock(i), LiveBBs);
-        }
-      }
-
-      // Now that we know all of the blocks that this thing is live in, see if
-      // it includes any of the unwind locations.
-      bool NeedsSpill = false;
-      for (unsigned i = 0, e = Invokes.size(); i != e; ++i) {
-        BasicBlock *UnwindBlock = Invokes[i]->getUnwindDest();
-        if (UnwindBlock != BB && LiveBBs.count(UnwindBlock))
-          NeedsSpill = true;
-      }
-
-      // If we decided we need a spill, do it.
-      // FIXME: Spilling this way is overkill, as it forces all uses of
-      // the value to be reloaded from the stack slot, even those that aren't
-      // in the unwind blocks. We should be more selective.
-      if (NeedsSpill) {
-        ++NumSpilled;
-        DemoteRegToStack(*Inst, true);
-      }
-    }
-}
-
-/// CreateLandingPadLoad - Load the exception handling values and insert them
-/// into a structure.
-static Instruction *CreateLandingPadLoad(Function &F, Value *ExnAddr,
-                                         Value *SelAddr,
-                                         BasicBlock::iterator InsertPt) {
-  Value *Exn = new LoadInst(ExnAddr, "exn", false,
-                            InsertPt);
-  Type *Ty = Type::getInt8PtrTy(F.getContext());
-  Exn = CastInst::Create(Instruction::IntToPtr, Exn, Ty, "", InsertPt);
-  Value *Sel = new LoadInst(SelAddr, "sel", false, InsertPt);
-
-  Ty = StructType::get(Exn->getType(), Sel->getType(), NULL);
-  InsertValueInst *LPadVal = InsertValueInst::Create(llvm::UndefValue::get(Ty),
-                                                     Exn, 0,
-                                                     "lpad.val", InsertPt);
-  return InsertValueInst::Create(LPadVal, Sel, 1, "lpad.val", InsertPt);
-}
-
-/// ReplaceLandingPadVal - Replace the landingpad instruction's value with a
-/// load from the stored values (via CreateLandingPadLoad). This looks through
-/// PHI nodes, and removes them if they are dead.
-static void ReplaceLandingPadVal(Function &F, Instruction *Inst, Value *ExnAddr,
-                                 Value *SelAddr) {
-  if (Inst->use_empty()) return;
-
-  while (!Inst->use_empty()) {
-    Instruction *I = cast<Instruction>(Inst->use_back());
-
-    if (PHINode *PN = dyn_cast<PHINode>(I)) {
-      ReplaceLandingPadVal(F, PN, ExnAddr, SelAddr);
-      if (PN->use_empty()) PN->eraseFromParent();
-      continue;
-    }
-
-    I->replaceUsesOfWith(Inst, CreateLandingPadLoad(F, ExnAddr, SelAddr, I));
-  }
-}
-
-bool SjLjEHPass::insertSjLjEHSupport(Function &F) {
-  SmallVector<ReturnInst*,16> Returns;
-  SmallVector<UnwindInst*,16> Unwinds;
-  SmallVector<InvokeInst*,16> Invokes;
-
-  // Look through the terminators of the basic blocks to find invokes, returns
-  // and unwinds.
-  for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
-    if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator())) {
-      // Remember all return instructions in case we insert an invoke into this
-      // function.
-      Returns.push_back(RI);
-    } else if (InvokeInst *II = dyn_cast<InvokeInst>(BB->getTerminator())) {
-      Invokes.push_back(II);
-    } else if (UnwindInst *UI = dyn_cast<UnwindInst>(BB->getTerminator())) {
-      Unwinds.push_back(UI);
-    }
-  }
-
-  NumInvokes += Invokes.size();
-  NumUnwinds += Unwinds.size();
-
-  // If we don't have any invokes, there's nothing to do.
-  if (Invokes.empty()) return false;
-
-  // Find the eh.selector.*, eh.exception and alloca calls.
-  //
-  // Remember any allocas() that aren't in the entry block, as the
-  // jmpbuf saved SP will need to be updated for them.
-  //
-  // We'll use the first eh.selector to determine the right personality
-  // function to use. For SJLJ, we always use the same personality for the
-  // whole function, not on a per-selector basis.
-  // FIXME: That's a bit ugly. Better way?
-  SmallVector<CallInst*,16> EH_Selectors;
-  SmallVector<CallInst*,16> EH_Exceptions;
-  SmallVector<Instruction*,16> JmpbufUpdatePoints;
-
-  for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
-    // Note: Skip the entry block since there's nothing there that interests
-    // us. eh.selector and eh.exception shouldn't ever be there, and we
-    // want to disregard any allocas that are there.
-    // 
-    // FIXME: This is awkward. The new EH scheme won't need to skip the entry
-    //        block.
-    if (BB == F.begin()) {
-      if (InvokeInst *II = dyn_cast<InvokeInst>(F.begin()->getTerminator())) {
-        // FIXME: This will be always non-NULL in the new EH.
-        if (LandingPadInst *LPI = II->getUnwindDest()->getLandingPadInst())
-          if (!PersonalityFn) PersonalityFn = LPI->getPersonalityFn();
-      }
-
-      continue;
-    }
-
-    for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
-      if (CallInst *CI = dyn_cast<CallInst>(I)) {
-        if (CI->getCalledFunction() == SelectorFn) {
-          if (!PersonalityFn) PersonalityFn = CI->getArgOperand(1);
-          EH_Selectors.push_back(CI);
-        } else if (CI->getCalledFunction() == ExceptionFn) {
-          EH_Exceptions.push_back(CI);
-        } else if (CI->getCalledFunction() == StackRestoreFn) {
-          JmpbufUpdatePoints.push_back(CI);
-        }
-      } else if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
-        JmpbufUpdatePoints.push_back(AI);
-      } else if (InvokeInst *II = dyn_cast<InvokeInst>(I)) {
-        // FIXME: This will be always non-NULL in the new EH.
-        if (LandingPadInst *LPI = II->getUnwindDest()->getLandingPadInst())
-          if (!PersonalityFn) PersonalityFn = LPI->getPersonalityFn();
-      }
-    }
-  }
-
-  // If we don't have any eh.selector calls, we can't determine the personality
-  // function. Without a personality function, we can't process exceptions.
-  if (!PersonalityFn) return false;
-
-  // We have invokes, so we need to add register/unregister calls to get this
-  // function onto the global unwind stack.
-  //
-  // First thing we need to do is scan the whole function for values that are
-  // live across unwind edges.  Each value that is live across an unwind edge we
-  // spill into a stack location, guaranteeing that there is nothing live across
-  // the unwind edge.  This process also splits all critical edges coming out of
-  // invoke's.
-  splitLiveRangesAcrossInvokes(Invokes);
-
-
-  SmallVector<LandingPadInst*, 16> LandingPads;
-  for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
-    if (InvokeInst *II = dyn_cast<InvokeInst>(BB->getTerminator()))
-      // FIXME: This will be always non-NULL in the new EH.
-      if (LandingPadInst *LPI = II->getUnwindDest()->getLandingPadInst())
-        LandingPads.push_back(LPI);
-  }
-
-
-  BasicBlock *EntryBB = F.begin();
-  // Create an alloca for the incoming jump buffer ptr and the new jump buffer
-  // that needs to be restored on all exits from the function.  This is an
-  // alloca because the value needs to be added to the global context list.
-  unsigned Align = 4; // FIXME: Should be a TLI check?
-  AllocaInst *FunctionContext =
-    new AllocaInst(FunctionContextTy, 0, Align,
-                   "fcn_context", F.begin()->begin());
-
-  Value *Idxs[2];
-  Type *Int32Ty = Type::getInt32Ty(F.getContext());
-  Value *Zero = ConstantInt::get(Int32Ty, 0);
-  // We need to also keep around a reference to the call_site field
-  Idxs[0] = Zero;
-  Idxs[1] = ConstantInt::get(Int32Ty, 1);
-  CallSite = GetElementPtrInst::Create(FunctionContext, Idxs, "call_site",
-                                       EntryBB->getTerminator());
-
-  // The exception selector comes back in context->data[1]
-  Idxs[1] = ConstantInt::get(Int32Ty, 2);
-  Value *FCData = GetElementPtrInst::Create(FunctionContext, Idxs, "fc_data",
-                                            EntryBB->getTerminator());
-  Idxs[1] = ConstantInt::get(Int32Ty, 1);
-  Value *SelectorAddr = GetElementPtrInst::Create(FCData, Idxs,
-                                                  "exc_selector_gep",
-                                                  EntryBB->getTerminator());
-  // The exception value comes back in context->data[0]
-  Idxs[1] = Zero;
-  Value *ExceptionAddr = GetElementPtrInst::Create(FCData, Idxs,
-                                                   "exception_gep",
-                                                   EntryBB->getTerminator());
-
-  // The result of the eh.selector call will be replaced with a a reference to
-  // the selector value returned in the function context. We leave the selector
-  // itself so the EH analysis later can use it.
-  for (int i = 0, e = EH_Selectors.size(); i < e; ++i) {
-    CallInst *I = EH_Selectors[i];
-    Value *SelectorVal = new LoadInst(SelectorAddr, "select_val", true, I);
-    I->replaceAllUsesWith(SelectorVal);
-  }
-
-  // eh.exception calls are replaced with references to the proper location in
-  // the context. Unlike eh.selector, the eh.exception calls are removed
-  // entirely.
-  for (int i = 0, e = EH_Exceptions.size(); i < e; ++i) {
-    CallInst *I = EH_Exceptions[i];
-    // Possible for there to be duplicates, so check to make sure the
-    // instruction hasn't already been removed.
-    if (!I->getParent()) continue;
-    Value *Val = new LoadInst(ExceptionAddr, "exception", true, I);
-    Type *Ty = Type::getInt8PtrTy(F.getContext());
-    Val = CastInst::Create(Instruction::IntToPtr, Val, Ty, "", I);
-
-    I->replaceAllUsesWith(Val);
-    I->eraseFromParent();
-  }
-
-  for (unsigned i = 0, e = LandingPads.size(); i != e; ++i)
-    ReplaceLandingPadVal(F, LandingPads[i], ExceptionAddr, SelectorAddr);
-
-  // The entry block changes to have the eh.sjlj.setjmp, with a conditional
-  // branch to a dispatch block for non-zero returns. If we return normally,
-  // we're not handling an exception and just register the function context and
-  // continue.
-
-  // Create the dispatch block.  The dispatch block is basically a big switch
-  // statement that goes to all of the invoke landing pads.
-  BasicBlock *DispatchBlock =
-    BasicBlock::Create(F.getContext(), "eh.sjlj.setjmp.catch", &F);
-
-  // Insert a load of the callsite in the dispatch block, and a switch on its
-  // value. By default, we issue a trap statement.
-  BasicBlock *TrapBlock =
-    BasicBlock::Create(F.getContext(), "trapbb", &F);
-  CallInst::Create(Intrinsic::getDeclaration(F.getParent(), Intrinsic::trap),
-                   "", TrapBlock);
-  new UnreachableInst(F.getContext(), TrapBlock);
-
-  Value *DispatchLoad = new LoadInst(CallSite, "invoke.num", true,
-                                     DispatchBlock);
-  SwitchInst *DispatchSwitch =
-    SwitchInst::Create(DispatchLoad, TrapBlock, Invokes.size(),
-                       DispatchBlock);
-  // Split the entry block to insert the conditional branch for the setjmp.
-  BasicBlock *ContBlock = EntryBB->splitBasicBlock(EntryBB->getTerminator(),
-                                                   "eh.sjlj.setjmp.cont");
-
-  // Populate the Function Context
-  //   1. LSDA address
-  //   2. Personality function address
-  //   3. jmpbuf (save SP, FP and call eh.sjlj.setjmp)
-
-  // LSDA address
-  Idxs[0] = Zero;
-  Idxs[1] = ConstantInt::get(Int32Ty, 4);
-  Value *LSDAFieldPtr =
-    GetElementPtrInst::Create(FunctionContext, Idxs, "lsda_gep",
-                              EntryBB->getTerminator());
-  Value *LSDA = CallInst::Create(LSDAAddrFn, "lsda_addr",
-                                 EntryBB->getTerminator());
-  new StoreInst(LSDA, LSDAFieldPtr, true, EntryBB->getTerminator());
-
-  Idxs[1] = ConstantInt::get(Int32Ty, 3);
-  Value *PersonalityFieldPtr =
-    GetElementPtrInst::Create(FunctionContext, Idxs, "lsda_gep",
-                              EntryBB->getTerminator());
-  new StoreInst(PersonalityFn, PersonalityFieldPtr, true,
-                EntryBB->getTerminator());
-
-  // Save the frame pointer.
-  Idxs[1] = ConstantInt::get(Int32Ty, 5);
-  Value *JBufPtr
-    = GetElementPtrInst::Create(FunctionContext, Idxs, "jbuf_gep",
-                                EntryBB->getTerminator());
-  Idxs[1] = ConstantInt::get(Int32Ty, 0);
-  Value *FramePtr =
-    GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_fp_gep",
-                              EntryBB->getTerminator());
-
-  Value *Val = CallInst::Create(FrameAddrFn,
-                                ConstantInt::get(Int32Ty, 0),
-                                "fp",
-                                EntryBB->getTerminator());
-  new StoreInst(Val, FramePtr, true, EntryBB->getTerminator());
-
-  // Save the stack pointer.
-  Idxs[1] = ConstantInt::get(Int32Ty, 2);
-  Value *StackPtr =
-    GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_sp_gep",
-                              EntryBB->getTerminator());
-
-  Val = CallInst::Create(StackAddrFn, "sp", EntryBB->getTerminator());
-  new StoreInst(Val, StackPtr, true, EntryBB->getTerminator());
-
-  // Call the setjmp instrinsic. It fills in the rest of the jmpbuf.
-  Value *SetjmpArg =
-    CastInst::Create(Instruction::BitCast, JBufPtr,
-                     Type::getInt8PtrTy(F.getContext()), "",
-                     EntryBB->getTerminator());
-  Value *DispatchVal = CallInst::Create(BuiltinSetjmpFn, SetjmpArg,
-                                        "",
-                                        EntryBB->getTerminator());
-
-  // Add a call to dispatch_setup after the setjmp call. This is expanded to any
-  // target-specific setup that needs to be done.
-  CallInst::Create(DispatchSetupFn, DispatchVal, "", EntryBB->getTerminator());
-
-  // check the return value of the setjmp. non-zero goes to dispatcher.
-  Value *IsNormal = new ICmpInst(EntryBB->getTerminator(),
-                                 ICmpInst::ICMP_EQ, DispatchVal, Zero,
-                                 "notunwind");
-  // Nuke the uncond branch.
-  EntryBB->getTerminator()->eraseFromParent();
-
-  // Put in a new condbranch in its place.
-  BranchInst::Create(ContBlock, DispatchBlock, IsNormal, EntryBB);
-
-  // Register the function context and make sure it's known to not throw
-  CallInst *Register =
-    CallInst::Create(RegisterFn, FunctionContext, "",
-                     ContBlock->getTerminator());
-  Register->setDoesNotThrow();
-
-  // At this point, we are all set up, update the invoke instructions to mark
-  // their call_site values, and fill in the dispatch switch accordingly.
-  for (unsigned i = 0, e = Invokes.size(); i != e; ++i)
-    markInvokeCallSite(Invokes[i], i+1, CallSite, DispatchSwitch);
-
-  // Mark call instructions that aren't nounwind as no-action (call_site ==
-  // -1). Skip the entry block, as prior to then, no function context has been
-  // created for this function and any unexpected exceptions thrown will go
-  // directly to the caller's context, which is what we want anyway, so no need
-  // to do anything here.
-  for (Function::iterator BB = F.begin(), E = F.end(); ++BB != E;) {
-    for (BasicBlock::iterator I = BB->begin(), end = BB->end(); I != end; ++I)
-      if (CallInst *CI = dyn_cast<CallInst>(I)) {
-        // Ignore calls to the EH builtins (eh.selector, eh.exception)
-        Constant *Callee = CI->getCalledFunction();
-        if (Callee != SelectorFn && Callee != ExceptionFn
-            && !CI->doesNotThrow())
-          insertCallSiteStore(CI, -1, CallSite);
-      } else if (ResumeInst *RI = dyn_cast<ResumeInst>(I)) {
-        insertCallSiteStore(RI, -1, CallSite);
-      }
-  }
-
-  // Replace all unwinds with a branch to the unwind handler.
-  // ??? Should this ever happen with sjlj exceptions?
-  for (unsigned i = 0, e = Unwinds.size(); i != e; ++i) {
-    BranchInst::Create(TrapBlock, Unwinds[i]);
-    Unwinds[i]->eraseFromParent();
-  }
-
-  // Following any allocas not in the entry block, update the saved SP in the
-  // jmpbuf to the new value.
-  for (unsigned i = 0, e = JmpbufUpdatePoints.size(); i != e; ++i) {
-    Instruction *AI = JmpbufUpdatePoints[i];
-    Instruction *StackAddr = CallInst::Create(StackAddrFn, "sp");
-    StackAddr->insertAfter(AI);
-    Instruction *StoreStackAddr = new StoreInst(StackAddr, StackPtr, true);
-    StoreStackAddr->insertAfter(StackAddr);
-  }
-
-  // Finally, for any returns from this function, if this function contains an
-  // invoke, add a call to unregister the function context.
-  for (unsigned i = 0, e = Returns.size(); i != e; ++i)
-    CallInst::Create(UnregisterFn, FunctionContext, "", Returns[i]);
-
-  return true;
-}
-
 /// setupFunctionContext - Allocate the function context on the stack and fill
 /// it with all of the data that we know at this point.
 Value *SjLjEHPass::
@@ -871,7 +298,7 @@
       }
 
       // Find all of the blocks that this value is live in.
-      std::set<BasicBlock*> LiveBBs;
+      SmallPtrSet<BasicBlock*, 64> LiveBBs;
       LiveBBs.insert(Inst->getParent());
       while (!Users.empty()) {
         Instruction *U = Users.back();
@@ -895,6 +322,7 @@
         BasicBlock *UnwindBlock = Invokes[i]->getUnwindDest();
         if (UnwindBlock != BB && LiveBBs.count(UnwindBlock)) {
           NeedsSpill = true;
+          break;
         }
       }
 
@@ -903,8 +331,8 @@
       // the value to be reloaded from the stack slot, even those that aren't
       // in the unwind blocks. We should be more selective.
       if (NeedsSpill) {
-        ++NumSpilled;
         DemoteRegToStack(*Inst, true);
+        ++NumSpilled;
       }
     }
   }
@@ -950,6 +378,8 @@
 
   if (Invokes.empty()) return false;
 
+  NumInvokes += Invokes.size();
+
   lowerIncomingArguments(F);
   lowerAcrossUnwindEdges(F, Invokes);
 
@@ -1039,10 +469,6 @@
 }
 
 bool SjLjEHPass::runOnFunction(Function &F) {
-  bool Res = false;
-  if (!DisableOldSjLjEH)
-    Res = insertSjLjEHSupport(F);
-  else
-    Res = setupEntryBlockAndCallSites(F);
+  bool Res = setupEntryBlockAndCallSites(F);
   return Res;
 }



From grosbach at apple.com  Mon Oct 24 12:16:24 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 24 Oct 2011 17:16:24 -0000
Subject: [llvm-commits] [llvm] r142801 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
Message-ID: <20111024171624.9182E312800A@llvm.org>

Author: grosbach
Date: Mon Oct 24 12:16:24 2011
New Revision: 142801

URL: http://llvm.org/viewvc/llvm-project?rev=142801&view=rev
Log:
Thumb2 LDM instructions can target PC. Make sure to encode it.

PR11220

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=142801&r1=142800&r2=142801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Oct 24 12:16:24 2011
@@ -1543,8 +1543,7 @@
     let Inst{21}    = 0;        // No writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
   def IA_UPD :
     T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@@ -1559,8 +1558,7 @@
     let Inst{21}    = 1;        // Writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
   def DB :
     T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@@ -1575,8 +1573,7 @@
     let Inst{21}    = 0;        // No writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
   def DB_UPD :
     T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@@ -1591,8 +1588,7 @@
     let Inst{21}    = 1;        // Writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
 }
 



From benny.kra at googlemail.com  Mon Oct 24 12:24:05 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 24 Oct 2011 17:24:05 -0000
Subject: [llvm-commits] [llvm] r142804 - /llvm/trunk/test/TableGen/Paste.td
Message-ID: <20111024172405.EA2BD312800A@llvm.org>

Author: d0k
Date: Mon Oct 24 12:24:05 2011
New Revision: 142804

URL: http://llvm.org/viewvc/llvm-project?rev=142804&view=rev
Log:
XFAIL test on leak checkers.

Modified:
    llvm/trunk/test/TableGen/Paste.td

Modified: llvm/trunk/test/TableGen/Paste.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/Paste.td?rev=142804&r1=142803&r2=142804&view=diff
==============================================================================
--- llvm/trunk/test/TableGen/Paste.td (original)
+++ llvm/trunk/test/TableGen/Paste.td Mon Oct 24 12:24:05 2011
@@ -1,4 +1,5 @@
 // RUN: llvm-tblgen %s | FileCheck %s
+// XFAIL: vg_leak
 
 class Instr<int i> {
   int index = i;



From dblaikie at gmail.com  Mon Oct 24 12:26:26 2011
From: dblaikie at gmail.com (David Blaikie)
Date: Mon, 24 Oct 2011 10:26:26 -0700
Subject: [llvm-commits] [llvm] r142793 - in /llvm/trunk:
 include/llvm/Analysis/BranchProbabilityInfo.h
 lib/Analysis/BranchProbabilityInfo.cpp
 test/Analysis/BranchProbabilityInfo/noreturn.ll
In-Reply-To: <20111024120109.0457F312800A@llvm.org>
References: <20111024120109.0457F312800A@llvm.org>
Message-ID: <CAENS6EsW61+XsQn88SVxtM__ob+asmZ16a3ipRX9PjvdpBCB1g@mail.gmail.com>

> However, the return heuristic was flagging one very important case:
> unreachable. Unfortunately it still gave a 1/4 chance of the
> branch-to-unreachable occuring. It also didn't do a rigorous job of
> finding those blocks which post-dominate an unreachable block.

When does this actually come up? When I was experimenting with some
opt issues a few weeks ago I found unreachable blocks were being
stripped out very early (in the SimplifyCFG pass), though I expect
other passes could possibly introduce new ones later on.

- David

From grosbach at apple.com  Mon Oct 24 12:26:26 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 24 Oct 2011 17:26:26 -0000
Subject: [llvm-commits] [llvm] r142806 -
	/llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll
Message-ID: <20111024172626.9334A312800A@llvm.org>

Author: grosbach
Date: Mon Oct 24 12:26:26 2011
New Revision: 142806

URL: http://llvm.org/viewvc/llvm-project?rev=142806&view=rev
Log:
Update test for r142801.

Modified:
    llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll

Modified: llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll?rev=142806&r1=142805&r2=142806&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll (original)
+++ llvm/trunk/test/MC/ARM/elf-thumbfunc-reloc.ll Mon Oct 24 12:26:26 2011
@@ -22,7 +22,7 @@
 
 
 ; make sure that bl 0 <foo> (fff7feff) is correctly encoded
-; CHECK: '_section_data', '704700bf 2de90048 fff7feff bde80008'
+; CHECK: '_section_data', '704700bf 2de90048 fff7feff bde80088'
 
 ;  Offset     Info    Type            Sym.Value  Sym. Name
 ; 00000008  0000070a R_ARM_THM_CALL    00000001   foo



From chandlerc at gmail.com  Mon Oct 24 12:32:44 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 24 Oct 2011 10:32:44 -0700
Subject: [llvm-commits] [llvm] r142793 - in /llvm/trunk:
 include/llvm/Analysis/BranchProbabilityInfo.h
 lib/Analysis/BranchProbabilityInfo.cpp
 test/Analysis/BranchProbabilityInfo/noreturn.ll
In-Reply-To: <CAENS6EsW61+XsQn88SVxtM__ob+asmZ16a3ipRX9PjvdpBCB1g@mail.gmail.com>
References: <20111024120109.0457F312800A@llvm.org>
	<CAENS6EsW61+XsQn88SVxtM__ob+asmZ16a3ipRX9PjvdpBCB1g@mail.gmail.com>
Message-ID: <CAGCO0KgyDxeZENgi_rkjqOPW4pbEavdhxKDGkJGbjZV0N-OJMg@mail.gmail.com>

On Mon, Oct 24, 2011 at 10:26 AM, David Blaikie <dblaikie at gmail.com> wrote:

> > However, the return heuristic was flagging one very important case:
> > unreachable. Unfortunately it still gave a 1/4 chance of the
> > branch-to-unreachable occuring. It also didn't do a rigorous job of
> > finding those blocks which post-dominate an unreachable block.
>
> When does this actually come up? When I was experimenting with some
> opt issues a few weeks ago I found unreachable blocks were being
> stripped out very early (in the SimplifyCFG pass), though I expect
> other passes could possibly introduce new ones later on.


After a call to a noreturn function, such as 'abort' or other
process-termination function.
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From gohman at apple.com  Mon Oct 24 12:45:03 2011
From: gohman at apple.com (Dan Gohman)
Date: Mon, 24 Oct 2011 17:45:03 -0000
Subject: [llvm-commits] [llvm] r142810 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ test/CodeGen/Alpha/ test/CodeGen/MBlaze/
 test/CodeGen/Mips/ test/CodeGen/PTX/ test/CodeGen/PowerPC/
Message-ID: <20111024174503.282D2312800A@llvm.org>

Author: djg
Date: Mon Oct 24 12:45:02 2011
New Revision: 142810

URL: http://llvm.org/viewvc/llvm-project?rev=142810&view=rev
Log:
Change the default scheduler from Latency to ILP, since Latency
is going away.

Removed:
    llvm/trunk/test/CodeGen/Mips/fpcmp.ll
    llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll
    llvm/trunk/test/CodeGen/MBlaze/cc.ll
    llvm/trunk/test/CodeGen/MBlaze/div.ll
    llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll
    llvm/trunk/test/CodeGen/Mips/cmov.ll
    llvm/trunk/test/CodeGen/Mips/eh.ll
    llvm/trunk/test/CodeGen/Mips/fcopysign.ll
    llvm/trunk/test/CodeGen/Mips/i64arg.ll
    llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
    llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
    llvm/trunk/test/CodeGen/Mips/unalignedload.ll
    llvm/trunk/test/CodeGen/PTX/cvt.ll
    llvm/trunk/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
    llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll
    llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Oct 24 12:45:02 2011
@@ -610,7 +610,7 @@
   ExceptionSelectorRegister = 0;
   BooleanContents = UndefinedBooleanContent;
   BooleanVectorContents = UndefinedBooleanContent;
-  SchedPreferenceInfo = Sched::Latency;
+  SchedPreferenceInfo = Sched::ILP;
   JumpBufSize = 0;
   JumpBufAlignment = 0;
   MinFunctionAlignment = 0;

Modified: llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll (original)
+++ llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll Mon Oct 24 12:45:02 2011
@@ -5,7 +5,7 @@
 	ret i64 %tmp431
 }
 
-; CHECK: sll $16,33,$0
-; CHECK-NEXT: sll $16,32,$1
-; CHECK-NEXT: addq $0,$1,$0
+; CHECK: sll $16,32,$0
+; CHECK-NEXT: sll $16,33,$1
+; CHECK-NEXT: addq $1,$0,$0
 

Modified: llvm/trunk/test/CodeGen/MBlaze/cc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/cc.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/cc.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/cc.ll Mon Oct 24 12:45:02 2011
@@ -222,8 +222,8 @@
 
     %tmp.12 = call i32 @params8_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
                                          i32 6, i32 7, i32 8)
-    ; CHECK:        {{swi? .*, r1, 28}}
     ; CHECK:        {{swi? .*, r1, 32}}
+    ; CHECK:        {{swi? .*, r1, 28}}
     ; CHECK:        {{.* r5, .*, .*}}
     ; CHECK:        {{.* r6, .*, .*}}
     ; CHECK:        {{.* r7, .*, .*}}
@@ -235,9 +235,9 @@
 
     %tmp.13 = call i32 @params9_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
                                          i32 6, i32 7, i32 8, i32 9)
-    ; CHECK:        {{swi? .*, r1, 28}}
-    ; CHECK:        {{swi? .*, r1, 32}}
     ; CHECK:        {{swi? .*, r1, 36}}
+    ; CHECK:        {{swi? .*, r1, 32}}
+    ; CHECK:        {{swi? .*, r1, 28}}
     ; CHECK:        {{.* r5, .*, .*}}
     ; CHECK:        {{.* r6, .*, .*}}
     ; CHECK:        {{.* r7, .*, .*}}
@@ -249,10 +249,10 @@
 
     %tmp.14 = call i32 @params10_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
                                           i32 6, i32 7, i32 8, i32 9, i32 10)
-    ; CHECK:        {{swi? .*, r1, 28}}
-    ; CHECK:        {{swi? .*, r1, 32}}
-    ; CHECK:        {{swi? .*, r1, 36}}
     ; CHECK:        {{swi? .*, r1, 40}}
+    ; CHECK:        {{swi? .*, r1, 36}}
+    ; CHECK:        {{swi? .*, r1, 32}}
+    ; CHECK:        {{swi? .*, r1, 28}}
     ; CHECK:        {{.* r5, .*, .*}}
     ; CHECK:        {{.* r6, .*, .*}}
     ; CHECK:        {{.* r7, .*, .*}}

Modified: llvm/trunk/test/CodeGen/MBlaze/div.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/div.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/div.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/div.ll Mon Oct 24 12:45:02 2011
@@ -13,14 +13,14 @@
     ; FUN-NOT:    idiv
     ; FUN:        brlid
     ; DIV-NOT:    brlid
-    ; DIV:        idivu
+    ; DIV:        idiv
 
     %tmp.2 = sdiv i8 %a, %b
     ; FUN-NOT:    idiv
     ; FUN:        brlid
     ; DIV-NOT:    brlid
-    ; DIV-NOT:    idivu
-    ; DIV:        idiv
+    ; DIV-NOT:    idiv
+    ; DIV:        idivu
 
     %tmp.3 = add i8 %tmp.1, %tmp.2
     ret i8 %tmp.3
@@ -36,14 +36,14 @@
     ; FUN-NOT:    idiv
     ; FUN:        brlid
     ; DIV-NOT:    brlid
-    ; DIV:        idivu
+    ; DIV:        idiv
 
     %tmp.2 = sdiv i16 %a, %b
     ; FUN-NOT:    idiv
     ; FUN:        brlid
     ; DIV-NOT:    brlid
-    ; DIV-NOT:    idivu
-    ; DIV:        idiv
+    ; DIV-NOT:    idiv
+    ; DIV:        idivu
 
     %tmp.3 = add i16 %tmp.1, %tmp.2
     ret i16 %tmp.3
@@ -59,14 +59,14 @@
     ; FUN-NOT:    idiv
     ; FUN:        brlid
     ; DIV-NOT:    brlid
-    ; DIV:        idivu
+    ; DIV:        idiv
 
     %tmp.2 = sdiv i32 %a, %b
     ; FUN-NOT:    idiv
     ; FUN:        brlid
     ; DIV-NOT:    brlid
-    ; DIV-NOT:    idivu
-    ; DIV:        idiv
+    ; DIV-NOT:    idiv
+    ; DIV:        idivu
 
     %tmp.3 = add i32 %tmp.1, %tmp.2
     ret i32 %tmp.3

Modified: llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll Mon Oct 24 12:45:02 2011
@@ -6,8 +6,8 @@
   volatile store i32 2, i32* %x, align 4
   %0 = volatile load i32* %x, align 4             ; <i32> [#uses=1]
 ; CHECK: lui $3, %hi($JTI0_0)
-; CHECK: sll $2, $2, 2
 ; CHECK: addiu $3, $3, %lo($JTI0_0)
+; CHECK: sll $2, $2, 2
   switch i32 %0, label %bb4 [
     i32 0, label %bb5
     i32 1, label %bb1

Modified: llvm/trunk/test/CodeGen/Mips/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cmov.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cmov.ll Mon Oct 24 12:45:02 2011
@@ -4,8 +4,8 @@
 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
 @i3 = common global i32* null, align 4
 
-; CHECK:  addiu ${{[0-9]+}}, $gp, %got(i1)
 ; CHECK:  lw  ${{[0-9]+}}, %got(i3)($gp)
+; CHECK:  addiu ${{[0-9]+}}, $gp, %got(i1)
 define i32* @cmov1(i32 %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0
@@ -18,8 +18,8 @@
 @d = global i32 0, align 4
 
 ; CHECK: cmov2:
-; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c)
 ; CHECK: addiu $[[R1:[0-9]+]], $gp, %got(d)
+; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c)
 ; CHECK: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
 define i32 @cmov2(i32 %s) nounwind readonly {
 entry:

Modified: llvm/trunk/test/CodeGen/Mips/eh.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/eh.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/eh.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/eh.ll Mon Oct 24 12:45:02 2011
@@ -10,15 +10,11 @@
 ; CHECK-EL:  .cfi_def_cfa_offset
 ; CHECK-EL:  sdc1 $f20
 ; CHECK-EL:  sw  $ra
-; CHECK-EL:  sw  $17
-; CHECK-EL:  sw  $16
 ; CHECK-EL:  .cfi_offset 52, -8
 ; CHECK-EL:  .cfi_offset 53, -4
 ; CHECK-EB:  .cfi_offset 53, -8
 ; CHECK-EB:  .cfi_offset 52, -4
 ; CHECK-EL:  .cfi_offset 31, -12
-; CHECK-EL:  .cfi_offset 17, -16
-; CHECK-EL:  .cfi_offset 16, -20
 ; CHECK-EL:  .cprestore 
 
   %exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind

Modified: llvm/trunk/test/CodeGen/Mips/fcopysign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcopysign.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fcopysign.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fcopysign.ll Mon Oct 24 12:45:02 2011
@@ -4,27 +4,27 @@
 define double @func0(double %d0, double %d1) nounwind readnone {
 entry:
 ; CHECK-EL: func0:
-; CHECK-EL: lui $[[T0:[0-9]+]], 32767
 ; CHECK-EL: lui $[[T1:[0-9]+]], 32768
-; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f13
-; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
-; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f15
 ; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
-; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
-; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
-; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12
+; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f15
+; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]]
+; CHECK-EL: lui $[[T0:[0-9]+]], 32767
+; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f13
+; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI1]], $[[MSK0]]
 ; CHECK-EL: or  $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
+; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12
 ; CHECK-EL: mtc1 $[[LO0]], $f0
 ; CHECK-EL: mtc1 $[[OR]], $f1
 ;
-; CHECK-EB: lui $[[T0:[0-9]+]], 32767
 ; CHECK-EB: lui $[[T1:[0-9]+]], 32768
-; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12
-; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
-; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14
 ; CHECK-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0
-; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
+; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14
 ; CHECK-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
+; CHECK-EB: lui $[[T0:[0-9]+]], 32767
+; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12
+; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
 ; CHECK-EB: or  $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
 ; CHECK-EB: mfc1 $[[LO0:[0-9]+]], $f13
 ; CHECK-EB: mtc1 $[[OR]], $f0
@@ -38,14 +38,14 @@
 define float @func1(float %f0, float %f1) nounwind readnone {
 entry:
 ; CHECK-EL: func1:
-; CHECK-EL: lui $[[T0:[0-9]+]], 32767
 ; CHECK-EL: lui $[[T1:[0-9]+]], 32768
-; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12
-; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
-; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14
 ; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
-; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
+; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14
 ; CHECK-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
+; CHECK-EL: lui $[[T0:[0-9]+]], 32767
+; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
+; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12
+; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
 ; CHECK-EL: or  $[[T4:[0-9]+]], $[[T2]], $[[T3]]
 ; CHECK-EL: mtc1 $[[T4]], $f0
   %call = tail call float @copysignf(float %f0, float %f1) nounwind readnone

Removed: llvm/trunk/test/CodeGen/Mips/fpcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fpcmp.ll?rev=142809&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fpcmp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fpcmp.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS32
-
- at g1 = external global i32
-
-define i32 @f(float %f0, float %f1) nounwind {
-entry:
-; CHECK-MIPS32: c.olt.s
-; CHECK-MIPS32: movt
-; CHECK-MIPS32: c.olt.s
-; CHECK-MIPS32: movt
-  %cmp = fcmp olt float %f0, %f1
-  %conv = zext i1 %cmp to i32
-  %tmp2 = load i32* @g1, align 4
-  %add = add nsw i32 %tmp2, %conv
-  store i32 %add, i32* @g1, align 4
-  %cond = select i1 %cmp, i32 10, i32 20
-  ret i32 %cond
-}

Modified: llvm/trunk/test/CodeGen/Mips/i64arg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/i64arg.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/i64arg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/i64arg.ll Mon Oct 24 12:45:02 2011
@@ -4,21 +4,21 @@
 entry:
 ; CHECK: addu $[[R1:[0-9]+]], $zero, $5
 ; CHECK: addu $[[R0:[0-9]+]], $zero, $4
-; CHECK: lw  $25, %call16(ff1)
 ; CHECK: ori $6, ${{[0-9]+}}, 3855
 ; CHECK: ori $7, ${{[0-9]+}}, 22136
+; CHECK: lw  $25, %call16(ff1)
 ; CHECK: jalr
   tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
 ; CHECK: lw $25, %call16(ff2)
-; CHECK: lw $[[R2:[0-9]+]], 88($sp)
-; CHECK: lw $[[R3:[0-9]+]], 92($sp)
+; CHECK: lw $[[R2:[0-9]+]], 80($sp)
+; CHECK: lw $[[R3:[0-9]+]], 84($sp)
 ; CHECK: addu $4, $zero, $[[R2]]
 ; CHECK: addu $5, $zero, $[[R3]]
 ; CHECK: jalr $25
   tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
   %sub = add nsw i32 %i, -1
-; CHECK: sw $[[R0]], 24($sp)
 ; CHECK: sw $[[R1]], 28($sp)
+; CHECK: sw $[[R0]], 24($sp)
 ; CHECK: lw $25, %call16(ff3)
 ; CHECK: addu $6, $zero, $[[R2]]
 ; CHECK: addu $7, $zero, $[[R3]]

Modified: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll Mon Oct 24 12:45:02 2011
@@ -8,10 +8,10 @@
 ; CHECK: #APP
 ; CHECK: sw $4, 0($[[T0]])
 ; CHECK: #NO_APP
-; CHECK: lw  $[[T1:[0-9]+]], %got(g1)($gp)
 ; CHECK: #APP
 ; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]])
 ; CHECK: #NO_APP
+; CHECK: lw  $[[T1:[0-9]+]], %got(g1)($gp)
 ; CHECK: sw  $[[T3]], 0($[[T1]])
 
   %l1 = alloca i32, align 4

Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Mon Oct 24 12:45:02 2011
@@ -12,20 +12,20 @@
 entry:
 ; CHECK: lw  $[[R1:[0-9]+]], %got(f1.s1)($gp)
 ; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
-; CHECK: lw  $[[R2:[0-9]+]], 8($[[R0]])
-; CHECK: lw  $[[R7:[0-9]+]], 12($[[R0]])
-; CHECK: lw  $[[R3:[0-9]+]], 16($[[R0]])
-; CHECK: lw  $[[R4:[0-9]+]], 20($[[R0]])
-; CHECK: lw  $[[R5:[0-9]+]], 24($[[R0]])
 ; CHECK: lw  $[[R6:[0-9]+]], 28($[[R0]])
-; CHECK: sw  $[[R2]], 16($sp)
-; CHECK: sw  $[[R7]], 20($sp)
-; CHECK: sw  $[[R3]], 24($sp)
-; CHECK: sw  $[[R4]], 28($sp)
-; CHECK: sw  $[[R5]], 32($sp)
+; CHECK: lw  $[[R5:[0-9]+]], 24($[[R0]])
+; CHECK: lw  $[[R4:[0-9]+]], 20($[[R0]])
+; CHECK: lw  $[[R3:[0-9]+]], 16($[[R0]])
+; CHECK: lw  $[[R7:[0-9]+]], 12($[[R0]])
+; CHECK: lw  $[[R2:[0-9]+]], 8($[[R0]])
 ; CHECK: sw  $[[R6]], 36($sp)
-; CHECK: lw  $6, %lo(f1.s1)($[[R1]])
+; CHECK: sw  $[[R5]], 32($sp)
+; CHECK: sw  $[[R4]], 28($sp)
+; CHECK: sw  $[[R3]], 24($sp)
+; CHECK: sw  $[[R7]], 20($sp)
+; CHECK: sw  $[[R2]], 16($sp)
 ; CHECK: lw  $7, 4($[[R0]])
+; CHECK: lw  $6, %lo(f1.s1)($[[R1]])
   %agg.tmp10 = alloca %struct.S3, align 4
   call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
   call void @callee2(%struct.S2* byval @f1.s2) nounwind
@@ -44,20 +44,20 @@
 define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
 entry:
 ; CHECK: addiu $sp, $sp, -56
-; CHECK: sw  $6, 64($sp)
 ; CHECK: sw  $7, 68($sp)
+; CHECK: sw  $6, 64($sp)
+; CHECK: lw  $4, 88($sp)
 ; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp)
+; CHECK: lw  $[[R3:[0-9]+]], 72($sp)
+; CHECK: lw  $[[R4:[0-9]+]], 76($sp)
 ; CHECK: lw  $[[R2:[0-9]+]], 68($sp)
 ; CHECK: lh  $[[R1:[0-9]+]], 66($sp)
 ; CHECK: lb  $[[R0:[0-9]+]], 64($sp)
-; CHECK: lw  $[[R3:[0-9]+]], 72($sp)
-; CHECK: lw  $[[R4:[0-9]+]], 76($sp)
-; CHECK: lw  $4, 88($sp)
-; CHECK: sw  $[[R3]], 16($sp)
-; CHECK: sw  $[[R4]], 20($sp)
-; CHECK: sw  $[[R2]], 24($sp)
-; CHECK: sw  $[[R1]], 28($sp)
 ; CHECK: sw  $[[R0]], 32($sp)
+; CHECK: sw  $[[R1]], 28($sp)
+; CHECK: sw  $[[R2]], 24($sp)
+; CHECK: sw  $[[R4]], 20($sp)
+; CHECK: sw  $[[R3]], 16($sp)
 ; CHECK: mfc1 $6, $f[[F0]]
 
   %i2 = getelementptr inbounds %struct.S1* %s1, i32 0, i32 5
@@ -81,12 +81,12 @@
 define void @f3(%struct.S2* nocapture byval %s2) nounwind {
 entry:
 ; CHECK: addiu $sp, $sp, -56
-; CHECK: sw  $4, 56($sp)
-; CHECK: sw  $5, 60($sp)
-; CHECK: sw  $6, 64($sp)
 ; CHECK: sw  $7, 68($sp)
-; CHECK: lw  $[[R0:[0-9]+]], 68($sp)
+; CHECK: sw  $6, 64($sp)
+; CHECK: sw  $5, 60($sp)
+; CHECK: sw  $4, 56($sp)
 ; CHECK: lw  $4, 56($sp)
+; CHECK: lw  $[[R0:[0-9]+]], 68($sp)
 ; CHECK: sw  $[[R0]], 24($sp)
 
   %arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0
@@ -100,14 +100,14 @@
 define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
 entry:
 ; CHECK: addiu $sp, $sp, -56
-; CHECK: sw  $5, 60($sp)
-; CHECK: sw  $6, 64($sp)
 ; CHECK: sw  $7, 68($sp)
+; CHECK: sw  $6, 64($sp)
+; CHECK: sw  $5, 60($sp)
+; CHECK: lw  $4, 68($sp)
 ; CHECK: lw  $[[R1:[0-9]+]], 88($sp)
 ; CHECK: lb  $[[R0:[0-9]+]], 60($sp)
-; CHECK: lw  $4, 68($sp)
-; CHECK: sw  $[[R1]], 24($sp)
 ; CHECK: sw  $[[R0]], 32($sp)
+; CHECK: sw  $[[R1]], 24($sp)
 
   %i = getelementptr inbounds %struct.S1* %s1, i32 0, i32 2
   %tmp = load i32* %i, align 4, !tbaa !0

Modified: llvm/trunk/test/CodeGen/Mips/unalignedload.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/unalignedload.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/unalignedload.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/unalignedload.ll Mon Oct 24 12:45:02 2011
@@ -9,27 +9,27 @@
 
 define void @foo1() nounwind {
 entry:
-; CHECK-EL: lw  $25, %call16(foo2)
 ; CHECK-EL: ulhu  $4, 2
+; CHECK-EL: lw  $25, %call16(foo2)
 ; CHECK-EL: lw  $[[R0:[0-9]+]], %got(s4)
 ; CHECK-EL: lbu $[[R1:[0-9]+]], 6($[[R0]])
-; CHECK-EL: ulhu  $[[R2:[0-9]+]], 4($[[R0]])
 ; CHECK-EL: sll $[[R3:[0-9]+]], $[[R1]], 16
+; CHECK-EL: ulhu  $[[R2:[0-9]+]], 4($[[R0]])
+; CHECK-EL: or  $5, $[[R2]], $[[R3]]
 ; CHECK-EL: ulw $4, 0($[[R0]])
 ; CHECK-EL: lw  $25, %call16(foo4)
-; CHECK-EL: or  $5, $[[R2]], $[[R3]]
 
 ; CHECK-EB: ulhu  $[[R0:[0-9]+]], 2
-; CHECK-EB: lw  $25, %call16(foo2)
 ; CHECK-EB: sll $4, $[[R0]], 16
+; CHECK-EB: lw  $25, %call16(foo2)
 ; CHECK-EB: lw  $[[R1:[0-9]+]], %got(s4)
-; CHECK-EB: ulhu  $[[R2:[0-9]+]], 4($[[R1]])
 ; CHECK-EB: lbu $[[R3:[0-9]+]], 6($[[R1]])
-; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16
 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R3]], 8
+; CHECK-EB: ulhu  $[[R2:[0-9]+]], 4($[[R1]])
+; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16
+; CHECK-EB: or  $5, $[[R4]], $[[R5]]
 ; CHECK-EB: ulw $4, 0($[[R1]])
 ; CHECK-EB: lw  $25, %call16(foo4)
-; CHECK-EB: or  $5, $[[R4]], $[[R5]]
 
   tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2* @s2, i32 0, i32 1)) nounwind
   tail call void @foo4(%struct.S4* byval @s4) nounwind

Modified: llvm/trunk/test/CodeGen/PTX/cvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/cvt.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/cvt.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/cvt.ll Mon Oct 24 12:45:02 2011
@@ -172,9 +172,9 @@
 ; f32
 
 define ptx_device float @cvt_f32_preds(i1 %x) {
-; CHECK: mov.b32 %f0, 1065353216;
-; CHECK: mov.b32 %f1, 0;
-; CHECK: selp.f32 %ret{{[0-9]+}}, %f0, %f1, %p{{[0-9]+}};
+; CHECK: mov.b32 %f0, 0;
+; CHECK: mov.b32 %f1, 1065353216;
+; CHECK: selp.f32 %ret{{[0-9]+}}, %f1, %f0, %p{{[0-9]+}};
 ; CHECK: ret;
 	%a = uitofp i1 %x to float
 	ret float %a
@@ -232,9 +232,9 @@
 ; f64
 
 define ptx_device double @cvt_f64_preds(i1 %x) {
-; CHECK: mov.b64 %fd0, 4575657221408423936;
-; CHECK: mov.b64 %fd1, 0;
-; CHECK: selp.f64 %ret{{[0-9]+}}, %fd0, %fd1, %p{{[0-9]+}};
+; CHECK: mov.b64 %fd0, 0;
+; CHECK: mov.b64 %fd1, 4575657221408423936;
+; CHECK: selp.f64 %ret{{[0-9]+}}, %fd1, %fd0, %p{{[0-9]+}};
 ; CHECK: ret;
 	%a = uitofp i1 %x to double
 	ret double %a

Removed: llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll?rev=142809&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll (removed)
@@ -1,23 +0,0 @@
-; RUN: llc < %s -march=ppc32 -combiner-alias-analysis | grep f5
-
-target datalayout = "E-p:32:32"
-target triple = "powerpc-apple-darwin8.2.0"
-        %struct.Point = type { double, double, double }
-
-define void @offset(%struct.Point* %pt, double %x, double %y, double %z) {
-entry:
-        %tmp = getelementptr %struct.Point* %pt, i32 0, i32 0           ; <double*> [#uses=2]
-        %tmp.upgrd.1 = load double* %tmp                ; <double> [#uses=1]
-        %tmp2 = fadd double %tmp.upgrd.1, %x             ; <double> [#uses=1]
-        store double %tmp2, double* %tmp
-        %tmp6 = getelementptr %struct.Point* %pt, i32 0, i32 1          ; <double*> [#uses=2]
-        %tmp7 = load double* %tmp6              ; <double> [#uses=1]
-        %tmp9 = fadd double %tmp7, %y            ; <double> [#uses=1]
-        store double %tmp9, double* %tmp6
-        %tmp13 = getelementptr %struct.Point* %pt, i32 0, i32 2         ; <double*> [#uses=2]
-        %tmp14 = load double* %tmp13            ; <double> [#uses=1]
-        %tmp16 = fadd double %tmp14, %z          ; <double> [#uses=1]
-        store double %tmp16, double* %tmp13
-        ret void
-}
-

Modified: llvm/trunk/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll Mon Oct 24 12:45:02 2011
@@ -1,9 +1,9 @@
 ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \
-; RUN:   grep {stw r3, 32751}
+; RUN:   grep {stw r4, 32751}
 ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
-; RUN:   grep {stw r3, 32751}
+; RUN:   grep {stw r4, 32751}
 ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
-; RUN:   grep {std r3, 9024}
+; RUN:   grep {std r4, 9024}
 
 define void @test() nounwind {
 	store i32 0, i32* inttoptr (i64 48725999 to i32*)

Modified: llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll Mon Oct 24 12:45:02 2011
@@ -47,8 +47,8 @@
 
 L1:                                               ; preds = %L2, %bb2
   %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ]  ; <i32> [#uses=1]
-; PIC: addis r[[R0:[0-9]+]], r{{[0-9]+}}, ha16(Ltmp0-L0$pb)
 ; PIC: li r[[R1:[0-9]+]], lo16(Ltmp0-L0$pb)
+; PIC: addis r[[R0:[0-9]+]], r{{[0-9]+}}, ha16(Ltmp0-L0$pb)
 ; PIC: add r[[R2:[0-9]+]], r[[R0]], r[[R1]]
 ; PIC: stw r[[R2]]
 ; STATIC: li r[[R0:[0-9]+]], lo16(Ltmp0)

Modified: llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll?rev=142810&r1=142809&r2=142810&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll Mon Oct 24 12:45:02 2011
@@ -12,156 +12,151 @@
 define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
  entry:
   %x = va_arg %struct.__va_list_tag* %ap, i64; Get from r5,r6
-; CHECK:      lbz 4, 0(3)
-; CHECK-NEXT: lwz 5, 4(3)
-; CHECK-NEXT: rlwinm 6, 4, 0, 31, 31
-; CHECK-NEXT: cmplwi 0, 6, 0
-; CHECK-NEXT: addi 6, 4, 1
+; CHECK: lbz 4, 0(3)
+; CHECK-NEXT: rlwinm 5, 4, 0, 31, 31
+; CHECK-NEXT: cmplwi 0, 5, 0
+; CHECK-NEXT: addi 5, 4, 1
 ; CHECK-NEXT: stw 3, -4(1)
-; CHECK-NEXT: stw 6, -8(1)
+; CHECK-NEXT: stw 5, -8(1)
 ; CHECK-NEXT: stw 4, -12(1)
-; CHECK-NEXT: stw 5, -16(1)
 ; CHECK-NEXT: bne 0, .LBB0_2
 ; CHECK-NEXT: # BB#1:                                 # %entry
 ; CHECK-NEXT: lwz 3, -12(1)
 ; CHECK-NEXT: stw 3, -8(1)
 ; CHECK-NEXT: .LBB0_2:                                # %entry
 ; CHECK-NEXT: lwz 3, -8(1)
-; CHECK-NEXT: lwz 4, -4(1)
-; CHECK-NEXT: lwz 5, 8(4)
-; CHECK-NEXT: slwi 6, 3, 2
-; CHECK-NEXT: addi 7, 3, 2
+; CHECK-NEXT: slwi 4, 3, 2
+; CHECK-NEXT: lwz 5, -4(1)
+; CHECK-NEXT: lwz 6, 4(5)
+; CHECK-NEXT: lwz 7, 8(5)
+; CHECK-NEXT: add 4, 7, 4
 ; CHECK-NEXT: cmpwi 0, 3, 8
-; CHECK-NEXT: lwz 3, -16(1)
-; CHECK-NEXT: addi 8, 3, 4
-; CHECK-NEXT: add 5, 5, 6
 ; CHECK-NEXT: mfcr 0                          # cr0
-; CHECK-NEXT: stw 0, -20(1)
-; CHECK-NEXT: stw 5, -24(1)
-; CHECK-NEXT: stw 3, -28(1)
-; CHECK-NEXT: stw 7, -32(1)
-; CHECK-NEXT: stw 8, -36(1)
+; CHECK-NEXT: stw 0, -16(1)
+; CHECK-NEXT: stw 3, -20(1)
+; CHECK-NEXT: stw 4, -24(1)
+; CHECK-NEXT: stw 6, -28(1)
 ; CHECK-NEXT: blt 0, .LBB0_4
 ; CHECK-NEXT: # BB#3:                                 # %entry
-; CHECK-NEXT: lwz 3, -36(1)
-; CHECK-NEXT: stw 3, -28(1)
-; CHECK-NEXT: .LBB0_4:                                # %entry
 ; CHECK-NEXT: lwz 3, -28(1)
-; CHECK-NEXT: lwz 4, -32(1)
-; CHECK-NEXT: lwz 5, -4(1)
-; CHECK-NEXT: stb 4, 0(5)
-; CHECK-NEXT: lwz 4, -24(1)
-; CHECK-NEXT: lwz 0, -20(1)
+; CHECK-NEXT: stw 3, -24(1)
+; CHECK-NEXT: .LBB0_4:                                # %entry
+; CHECK-NEXT: lwz 3, -24(1)
+; CHECK-NEXT: lwz 4, -28(1)
+; CHECK-NEXT: addi 5, 4, 4
+; CHECK-NEXT: lwz 0, -16(1)
 ; CHECK-NEXT: mtcrf 128, 0
+; CHECK-NEXT: stw 4, -32(1)
+; CHECK-NEXT: stw 5, -36(1)
 ; CHECK-NEXT: stw 3, -40(1)
-; CHECK-NEXT: stw 4, -44(1)
 ; CHECK-NEXT: blt 0, .LBB0_6
 ; CHECK-NEXT: # BB#5:                                 # %entry
-; CHECK-NEXT: lwz 3, -16(1)
-; CHECK-NEXT: stw 3, -44(1)
+; CHECK-NEXT: lwz 3, -36(1)
+; CHECK-NEXT: stw 3, -32(1)
 ; CHECK-NEXT: .LBB0_6:                                # %entry
-; CHECK-NEXT: lwz 3, -44(1)
-; CHECK-NEXT: lwz 4, -40(1)
-; CHECK-NEXT: lwz 5, -4(1)
-; CHECK-NEXT: stw 4, 4(5)
+; CHECK-NEXT: lwz 3, -32(1)
+; CHECK-NEXT: lwz 4, -20(1)
+; CHECK-NEXT: addi 5, 4, 2
+; CHECK-NEXT: lwz 6, -4(1)
+; CHECK-NEXT: stb 5, 0(6)
+; CHECK-NEXT: stw 3, 4(6)
   store i64 %x, i64* @var1, align 8
-; CHECK-NEXT: lis 4, var1 at ha
-; CHECK-NEXT: lwz 6, 4(3)
-; CHECK-NEXT: lwz 3, 0(3)
-; CHECK-NEXT: la 7, var1 at l(4)
-; CHECK-NEXT: stw 3, var1 at l(4)
-; CHECK-NEXT: stw 6, 4(7)
+; CHECK-NEXT: lwz 3, -40(1)
+; CHECK-NEXT: lwz 5, 0(3)
+; CHECK-NEXT: lwz 7, 4(3)
+; CHECK-NEXT: lis 8, var1 at ha
+; CHECK-NEXT: la 9, var1 at l(8)
+; CHECK-NEXT: stw 7, 4(9)
+; CHECK-NEXT: stw 5, var1 at l(8)
   %y = va_arg %struct.__va_list_tag* %ap, double; From f1
-; CHECK-NEXT: lbz 3, 1(5)
-; CHECK-NEXT: lwz 4, 4(5)
-; CHECK-NEXT: lwz 6, 8(5)
-; CHECK-NEXT: slwi 7, 3, 3
-; CHECK-NEXT: add 6, 6, 7
-; CHECK-NEXT: addi 7, 3, 1
-; CHECK-NEXT: cmpwi 0, 3, 8
-; CHECK-NEXT: addi 3, 4, 8
-; CHECK-NEXT: addi 6, 6, 32
-; CHECK-NEXT: mr 8, 4
+; CHECK-NEXT: lbz 5, 1(6)
+; CHECK-NEXT: lwz 7, 4(6)
+; CHECK-NEXT: lwz 8, 8(6)
+; CHECK-NEXT: slwi 9, 5, 3
+; CHECK-NEXT: add 8, 8, 9
+; CHECK-NEXT: cmpwi 0, 5, 8
+; CHECK-NEXT: addi 9, 7, 8
+; CHECK-NEXT: mr 10, 7
+; CHECK-NEXT: stw 9, -44(1)
+; CHECK-NEXT: stw 7, -48(1)
 ; CHECK-NEXT: mfcr 0                          # cr0
-; CHECK-NEXT: stw 0, -48(1)
-; CHECK-NEXT: stw 4, -52(1)
-; CHECK-NEXT: stw 6, -56(1)
-; CHECK-NEXT: stw 7, -60(1)
-; CHECK-NEXT: stw 3, -64(1)
-; CHECK-NEXT: stw 8, -68(1)
+; CHECK-NEXT: stw 0, -52(1)
+; CHECK-NEXT: stw 5, -56(1)
+; CHECK-NEXT: stw 10, -60(1)
+; CHECK-NEXT: stw 8, -64(1)
 ; CHECK-NEXT: blt 0, .LBB0_8
 ; CHECK-NEXT: # BB#7:                                 # %entry
-; CHECK-NEXT: lwz 3, -64(1)
-; CHECK-NEXT: stw 3, -68(1)
+; CHECK-NEXT: lwz 3, -44(1)
+; CHECK-NEXT: stw 3, -60(1)
 ; CHECK-NEXT: .LBB0_8:                                # %entry
-; CHECK-NEXT: lwz 3, -68(1)
-; CHECK-NEXT: lwz 4, -60(1)
-; CHECK-NEXT: lwz 5, -4(1)
-; CHECK-NEXT: stb 4, 1(5)
-; CHECK-NEXT: lwz 4, -56(1)
-; CHECK-NEXT: lwz 0, -48(1)
+; CHECK-NEXT: lwz 3, -60(1)
+; CHECK-NEXT: lwz 4, -64(1)
+; CHECK-NEXT: addi 4, 4, 32
+; CHECK-NEXT: lwz 0, -52(1)
 ; CHECK-NEXT: mtcrf 128, 0
-; CHECK-NEXT: stw 4, -72(1)
-; CHECK-NEXT: stw 3, -76(1)
+; CHECK-NEXT: stw 4, -68(1)
+; CHECK-NEXT: stw 3, -72(1)
 ; CHECK-NEXT: blt 0, .LBB0_10
 ; CHECK-NEXT: # BB#9:                                 # %entry
-; CHECK-NEXT: lwz 3, -52(1)
-; CHECK-NEXT: stw 3, -72(1)
+; CHECK-NEXT: lwz 3, -48(1)
+; CHECK-NEXT: stw 3, -68(1)
 ; CHECK-NEXT: .LBB0_10:                               # %entry
-; CHECK-NEXT: lwz 3, -72(1)
-; CHECK-NEXT: lwz 4, -76(1)
-; CHECK-NEXT: lwz 5, -4(1)
-; CHECK-NEXT: stw 4, 4(5)
+; CHECK-NEXT: lwz 3, -68(1)
+; CHECK-NEXT: lwz 4, -56(1)
+; CHECK-NEXT: addi 5, 4, 1
+; CHECK-NEXT: lwz 6, -4(1)
+; CHECK-NEXT: stb 5, 1(6)
+; CHECK-NEXT: lwz 5, -72(1)
+; CHECK-NEXT: stw 5, 4(6)
 ; CHECK-NEXT: lfd 0, 0(3)
   store double %y, double* @var2, align 8
 ; CHECK-NEXT: lis 3, var2 at ha
 ; CHECK-NEXT: stfd 0, var2 at l(3)
   %z = va_arg %struct.__va_list_tag* %ap, i32; From r7
-; CHECK-NEXT: lbz 3, 0(5)
-; CHECK-NEXT: lwz 4, 4(5)
-; CHECK-NEXT: lwz 6, 8(5)
-; CHECK-NEXT: slwi 7, 3, 2
-; CHECK-NEXT: addi 8, 3, 1
+; CHECK-NEXT: lbz 3, 0(6)
+; CHECK-NEXT: lwz 5, 4(6)
+; CHECK-NEXT: lwz 7, 8(6)
+; CHECK-NEXT: slwi 8, 3, 2
+; CHECK-NEXT: add 7, 7, 8
 ; CHECK-NEXT: cmpwi 0, 3, 8
-; CHECK-NEXT: addi 3, 4, 4
-; CHECK-NEXT: add 6, 6, 7
-; CHECK-NEXT: mr 7, 4
-; CHECK-NEXT: stw 6, -80(1)
+; CHECK-NEXT: addi 8, 5, 4
+; CHECK-NEXT: mr 9, 5
+; CHECK-NEXT: stw 3, -76(1)
+; CHECK-NEXT: stw 7, -80(1)
 ; CHECK-NEXT: stw 8, -84(1)
-; CHECK-NEXT: stw 3, -88(1)
-; CHECK-NEXT: stw 4, -92(1)
-; CHECK-NEXT: stw 7, -96(1)
+; CHECK-NEXT: stw 5, -88(1)
+; CHECK-NEXT: stw 9, -92(1)
 ; CHECK-NEXT: mfcr 0                          # cr0
-; CHECK-NEXT: stw 0, -100(1)
+; CHECK-NEXT: stw 0, -96(1)
 ; CHECK-NEXT: blt 0, .LBB0_12
 ; CHECK-NEXT: # BB#11:                                # %entry
-; CHECK-NEXT: lwz 3, -88(1)
-; CHECK-NEXT: stw 3, -96(1)
+; CHECK-NEXT: lwz 3, -84(1)
+; CHECK-NEXT: stw 3, -92(1)
 ; CHECK-NEXT: .LBB0_12:                               # %entry
-; CHECK-NEXT: lwz 3, -96(1)
-; CHECK-NEXT: lwz 4, -84(1)
-; CHECK-NEXT: lwz 5, -4(1)
-; CHECK-NEXT: stb 4, 0(5)
+; CHECK-NEXT: lwz 3, -92(1)
 ; CHECK-NEXT: lwz 4, -80(1)
-; CHECK-NEXT: lwz 0, -100(1)
+; CHECK-NEXT: lwz 0, -96(1)
 ; CHECK-NEXT: mtcrf 128, 0
+; CHECK-NEXT: stw 3, -100(1)
 ; CHECK-NEXT: stw 4, -104(1)
-; CHECK-NEXT: stw 3, -108(1)
 ; CHECK-NEXT: blt 0, .LBB0_14
 ; CHECK-NEXT: # BB#13:                                # %entry
-; CHECK-NEXT: lwz 3, -92(1)
+; CHECK-NEXT: lwz 3, -88(1)
 ; CHECK-NEXT: stw 3, -104(1)
 ; CHECK-NEXT: .LBB0_14:                               # %entry
 ; CHECK-NEXT: lwz 3, -104(1)
-; CHECK-NEXT: lwz 4, -108(1)
-; CHECK-NEXT: lwz 5, -4(1)
-; CHECK-NEXT: stw 4, 4(5)
+; CHECK-NEXT: lwz 4, -76(1)
+; CHECK-NEXT: addi 5, 4, 1
+; CHECK-NEXT: lwz 6, -4(1)
+; CHECK-NEXT: stb 5, 0(6)
+; CHECK-NEXT: lwz 5, -100(1)
+; CHECK-NEXT: stw 5, 4(6)
 ; CHECK-NEXT: lwz 3, 0(3)
   store i32 %z, i32* @var3, align 4
-; CHECK-NEXT: lis 4, var3 at ha
-; CHECK-NEXT: stw 3, var3 at l(4)
+; CHECK-NEXT: lis 5, var3 at ha
+; CHECK-NEXT: stw 3, var3 at l(5)
   ret void
-; CHECK-NEXT: stw 5, -112(1)
-; CHECK-NEXT: blr
+; CHECK-NEXT: stw 6, -108(1)
+; CHECK-NEXT: blr 
 }
 



From gohman at apple.com  Mon Oct 24 12:53:16 2011
From: gohman at apple.com (Dan Gohman)
Date: Mon, 24 Oct 2011 17:53:16 -0000
Subject: [llvm-commits] [llvm] r142811 - in /llvm/trunk:
 lib/Target/MSP430/MSP430ISelLowering.cpp test/CodeGen/MSP430/Inst16mm.ll
 test/CodeGen/MSP430/indirectbr2.ll
Message-ID: <20111024175316.EB688312800A@llvm.org>

Author: djg
Date: Mon Oct 24 12:53:16 2011
New Revision: 142811

URL: http://llvm.org/viewvc/llvm-project?rev=142811&view=rev
Log:
Remove the explicit request for "Latency" scheduling from MSP430,
as the Latency scheduler is going away.

Modified:
    llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
    llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll
    llvm/trunk/test/CodeGen/MSP430/indirectbr2.ll

Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=142811&r1=142810&r2=142811&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Mon Oct 24 12:53:16 2011
@@ -80,7 +80,6 @@
   setStackPointerRegisterToSaveRestore(MSP430::SPW);
   setBooleanContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
-  setSchedulingPreference(Sched::Latency);
 
   // We have post-incremented loads / stores.
   setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);

Modified: llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll?rev=142811&r1=142810&r2=142811&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll Mon Oct 24 12:53:16 2011
@@ -64,6 +64,6 @@
  %0 = load i16* %retval                          ; <i16> [#uses=1]
  ret i16 %0
 ; CHECK: mov2:
-; CHECK:	mov.w	0(r1), 4(r1)
 ; CHECK:	mov.w	2(r1), 6(r1)
+; CHECK:	mov.w	0(r1), 4(r1)
 }

Modified: llvm/trunk/test/CodeGen/MSP430/indirectbr2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/indirectbr2.ll?rev=142811&r1=142810&r2=142811&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MSP430/indirectbr2.ll (original)
+++ llvm/trunk/test/CodeGen/MSP430/indirectbr2.ll Mon Oct 24 12:53:16 2011
@@ -5,7 +5,7 @@
 entry:
   %tmp1 = getelementptr inbounds [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1]
   %gotovar.4.0 = load i8** %tmp1, align 4        ; <i8*> [#uses=1]
-; CHECK: mov.w   .LC.0.2070(r15), pc
+; CHECK: mov.w   .LC.0.2070(r12), pc
   indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
 
 L5:                                               ; preds = %bb2



From gohman at apple.com  Mon Oct 24 12:55:11 2011
From: gohman at apple.com (Dan Gohman)
Date: Mon, 24 Oct 2011 17:55:11 -0000
Subject: [llvm-commits] [llvm] r142813 - in /llvm/trunk/lib:
 CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Target/ARM/ARMISelLowering.cpp
Message-ID: <20111024175511.5B296312800A@llvm.org>

Author: djg
Date: Mon Oct 24 12:55:11 2011
New Revision: 142813

URL: http://llvm.org/viewvc/llvm-project?rev=142813&view=rev
Log:
Change this overloaded use of Sched::Latency to be an overloaded
use of Sched::ILP instead, as Sched::Latency is going away.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=142813&r1=142812&r2=142813&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Oct 24 12:55:11 2011
@@ -2100,9 +2100,9 @@
   int LHeight = (int)left->getHeight() + LPenalty;
   int RHeight = (int)right->getHeight() + RPenalty;
 
-  bool LStall = (!checkPref || left->SchedulingPref == Sched::Latency) &&
+  bool LStall = (!checkPref || left->SchedulingPref == Sched::ILP) &&
     BUHasStall(left, LHeight, SPQ);
-  bool RStall = (!checkPref || right->SchedulingPref == Sched::Latency) &&
+  bool RStall = (!checkPref || right->SchedulingPref == Sched::ILP) &&
     BUHasStall(right, RHeight, SPQ);
 
   // If scheduling one of the node will cause a pipeline stall, delay it.
@@ -2124,8 +2124,8 @@
 
   // If either node is scheduling for latency, sort them by height/depth
   // and latency.
-  if (!checkPref || (left->SchedulingPref == Sched::Latency ||
-                     right->SchedulingPref == Sched::Latency)) {
+  if (!checkPref || (left->SchedulingPref == Sched::ILP ||
+                     right->SchedulingPref == Sched::ILP)) {
     if (DisableSchedCycles) {
       if (LHeight != RHeight) {
         DEBUG(++FactorCount[FactHeight]);

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142813&r1=142812&r2=142813&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Oct 24 12:55:11 2011
@@ -986,7 +986,7 @@
     if (VT == MVT::Glue || VT == MVT::Other)
       continue;
     if (VT.isFloatingPoint() || VT.isVector())
-      return Sched::Latency;
+      return Sched::ILP;
   }
 
   if (!N->isMachineOpcode())
@@ -1001,7 +1001,7 @@
     return Sched::RegPressure;
   if (!Itins->isEmpty() &&
       Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
-    return Sched::Latency;
+    return Sched::ILP;
 
   return Sched::RegPressure;
 }



From gohman at apple.com  Mon Oct 24 12:58:28 2011
From: gohman at apple.com (Dan Gohman)
Date: Mon, 24 Oct 2011 10:58:28 -0700
Subject: [llvm-commits] [llvm] r142810 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ test/CodeGen/Alpha/ test/CodeGen/MBlaze/
 test/CodeGen/Mips/ test/CodeGen/PTX/ test/CodeGen/PowerPC/
In-Reply-To: <2A04634E-D076-4C2A-B9C2-B3E393315679@apple.com>
References: <20111024174503.282D2312800A@llvm.org>
	<2A04634E-D076-4C2A-B9C2-B3E393315679@apple.com>
Message-ID: <ABCEBAE9-83DC-4AF8-8A3B-B21C6B9A720E@apple.com>


On Oct 24, 2011, at 10:57 AM, Evan Cheng wrote:

> 
> On Oct 24, 2011, at 10:45 AM, Dan Gohman wrote:
> 
>> Author: djg
>> Date: Mon Oct 24 12:45:02 2011
>> New Revision: 142810
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=142810&view=rev
>> Log:
>> Change the default scheduler from Latency to ILP, since Latency
>> is going away.
> 
> By "latency", you meant top down latency scheduler, right? The bottom-up one is being used by ARM, etc.

Right. In the source, the top-down scheduler is just called "Latency".

Dan


From gohman at apple.com  Mon Oct 24 12:56:48 2011
From: gohman at apple.com (Dan Gohman)
Date: Mon, 24 Oct 2011 17:56:48 -0000
Subject: [llvm-commits] [llvm] r142815 - in /llvm/trunk:
 include/llvm/Target/TargetMachine.h
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <20111024175649.02FD2312800A@llvm.org>

Author: djg
Date: Mon Oct 24 12:56:48 2011
New Revision: 142815

URL: http://llvm.org/viewvc/llvm-project?rev=142815&view=rev
Log:
Delete the Latency scheduling preference.

Modified:
    llvm/trunk/include/llvm/Target/TargetMachine.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=142815&r1=142814&r2=142815&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Oct 24 12:56:48 2011
@@ -56,7 +56,6 @@
 namespace Sched {
   enum Preference {
     None,             // No preference
-    Latency,          // Scheduling for shortest total latency.
     RegPressure,      // Scheduling for lowest register pressure.
     Hybrid,           // Scheduling for both latency and register pressure.
     ILP               // Scheduling for ILP in low register pressure mode.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=142815&r1=142814&r2=142815&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Oct 24 12:56:48 2011
@@ -144,8 +144,6 @@
 
     if (OptLevel == CodeGenOpt::None)
       return createSourceListDAGScheduler(IS, OptLevel);
-    if (TLI.getSchedulingPreference() == Sched::Latency)
-      return createTDListDAGScheduler(IS, OptLevel);
     if (TLI.getSchedulingPreference() == Sched::RegPressure)
       return createBURRListDAGScheduler(IS, OptLevel);
     if (TLI.getSchedulingPreference() == Sched::Hybrid)



From evan.cheng at apple.com  Mon Oct 24 12:57:07 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 24 Oct 2011 10:57:07 -0700
Subject: [llvm-commits] [llvm] r142810 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ test/CodeGen/Alpha/ test/CodeGen/MBlaze/
 test/CodeGen/Mips/ test/CodeGen/PTX/ test/CodeGen/PowerPC/
In-Reply-To: <20111024174503.282D2312800A@llvm.org>
References: <20111024174503.282D2312800A@llvm.org>
Message-ID: <2A04634E-D076-4C2A-B9C2-B3E393315679@apple.com>


On Oct 24, 2011, at 10:45 AM, Dan Gohman wrote:

> Author: djg
> Date: Mon Oct 24 12:45:02 2011
> New Revision: 142810
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=142810&view=rev
> Log:
> Change the default scheduler from Latency to ILP, since Latency
> is going away.

By "latency", you meant top down latency scheduler, right? The bottom-up one is being used by ARM, etc.

Evan

> 
> Removed:
>    llvm/trunk/test/CodeGen/Mips/fpcmp.ll
>    llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>    llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll
>    llvm/trunk/test/CodeGen/MBlaze/cc.ll
>    llvm/trunk/test/CodeGen/MBlaze/div.ll
>    llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll
>    llvm/trunk/test/CodeGen/Mips/cmov.ll
>    llvm/trunk/test/CodeGen/Mips/eh.ll
>    llvm/trunk/test/CodeGen/Mips/fcopysign.ll
>    llvm/trunk/test/CodeGen/Mips/i64arg.ll
>    llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
>    llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
>    llvm/trunk/test/CodeGen/Mips/unalignedload.ll
>    llvm/trunk/test/CodeGen/PTX/cvt.ll
>    llvm/trunk/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
>    llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll
>    llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Oct 24 12:45:02 2011
> @@ -610,7 +610,7 @@
>   ExceptionSelectorRegister = 0;
>   BooleanContents = UndefinedBooleanContent;
>   BooleanVectorContents = UndefinedBooleanContent;
> -  SchedPreferenceInfo = Sched::Latency;
> +  SchedPreferenceInfo = Sched::ILP;
>   JumpBufSize = 0;
>   JumpBufAlignment = 0;
>   MinFunctionAlignment = 0;
> 
> Modified: llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll (original)
> +++ llvm/trunk/test/CodeGen/Alpha/2010-08-01-mulreduce64.ll Mon Oct 24 12:45:02 2011
> @@ -5,7 +5,7 @@
> 	ret i64 %tmp431
> }
> 
> -; CHECK: sll $16,33,$0
> -; CHECK-NEXT: sll $16,32,$1
> -; CHECK-NEXT: addq $0,$1,$0
> +; CHECK: sll $16,32,$0
> +; CHECK-NEXT: sll $16,33,$1
> +; CHECK-NEXT: addq $1,$0,$0
> 
> 
> Modified: llvm/trunk/test/CodeGen/MBlaze/cc.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/cc.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MBlaze/cc.ll (original)
> +++ llvm/trunk/test/CodeGen/MBlaze/cc.ll Mon Oct 24 12:45:02 2011
> @@ -222,8 +222,8 @@
> 
>     %tmp.12 = call i32 @params8_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
>                                          i32 6, i32 7, i32 8)
> -    ; CHECK:        {{swi? .*, r1, 28}}
>     ; CHECK:        {{swi? .*, r1, 32}}
> +    ; CHECK:        {{swi? .*, r1, 28}}
>     ; CHECK:        {{.* r5, .*, .*}}
>     ; CHECK:        {{.* r6, .*, .*}}
>     ; CHECK:        {{.* r7, .*, .*}}
> @@ -235,9 +235,9 @@
> 
>     %tmp.13 = call i32 @params9_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
>                                          i32 6, i32 7, i32 8, i32 9)
> -    ; CHECK:        {{swi? .*, r1, 28}}
> -    ; CHECK:        {{swi? .*, r1, 32}}
>     ; CHECK:        {{swi? .*, r1, 36}}
> +    ; CHECK:        {{swi? .*, r1, 32}}
> +    ; CHECK:        {{swi? .*, r1, 28}}
>     ; CHECK:        {{.* r5, .*, .*}}
>     ; CHECK:        {{.* r6, .*, .*}}
>     ; CHECK:        {{.* r7, .*, .*}}
> @@ -249,10 +249,10 @@
> 
>     %tmp.14 = call i32 @params10_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
>                                           i32 6, i32 7, i32 8, i32 9, i32 10)
> -    ; CHECK:        {{swi? .*, r1, 28}}
> -    ; CHECK:        {{swi? .*, r1, 32}}
> -    ; CHECK:        {{swi? .*, r1, 36}}
>     ; CHECK:        {{swi? .*, r1, 40}}
> +    ; CHECK:        {{swi? .*, r1, 36}}
> +    ; CHECK:        {{swi? .*, r1, 32}}
> +    ; CHECK:        {{swi? .*, r1, 28}}
>     ; CHECK:        {{.* r5, .*, .*}}
>     ; CHECK:        {{.* r6, .*, .*}}
>     ; CHECK:        {{.* r7, .*, .*}}
> 
> Modified: llvm/trunk/test/CodeGen/MBlaze/div.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/div.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MBlaze/div.ll (original)
> +++ llvm/trunk/test/CodeGen/MBlaze/div.ll Mon Oct 24 12:45:02 2011
> @@ -13,14 +13,14 @@
>     ; FUN-NOT:    idiv
>     ; FUN:        brlid
>     ; DIV-NOT:    brlid
> -    ; DIV:        idivu
> +    ; DIV:        idiv
> 
>     %tmp.2 = sdiv i8 %a, %b
>     ; FUN-NOT:    idiv
>     ; FUN:        brlid
>     ; DIV-NOT:    brlid
> -    ; DIV-NOT:    idivu
> -    ; DIV:        idiv
> +    ; DIV-NOT:    idiv
> +    ; DIV:        idivu
> 
>     %tmp.3 = add i8 %tmp.1, %tmp.2
>     ret i8 %tmp.3
> @@ -36,14 +36,14 @@
>     ; FUN-NOT:    idiv
>     ; FUN:        brlid
>     ; DIV-NOT:    brlid
> -    ; DIV:        idivu
> +    ; DIV:        idiv
> 
>     %tmp.2 = sdiv i16 %a, %b
>     ; FUN-NOT:    idiv
>     ; FUN:        brlid
>     ; DIV-NOT:    brlid
> -    ; DIV-NOT:    idivu
> -    ; DIV:        idiv
> +    ; DIV-NOT:    idiv
> +    ; DIV:        idivu
> 
>     %tmp.3 = add i16 %tmp.1, %tmp.2
>     ret i16 %tmp.3
> @@ -59,14 +59,14 @@
>     ; FUN-NOT:    idiv
>     ; FUN:        brlid
>     ; DIV-NOT:    brlid
> -    ; DIV:        idivu
> +    ; DIV:        idiv
> 
>     %tmp.2 = sdiv i32 %a, %b
>     ; FUN-NOT:    idiv
>     ; FUN:        brlid
>     ; DIV-NOT:    brlid
> -    ; DIV-NOT:    idivu
> -    ; DIV:        idiv
> +    ; DIV-NOT:    idiv
> +    ; DIV:        idivu
> 
>     %tmp.3 = add i32 %tmp.1, %tmp.2
>     ret i32 %tmp.3
> 
> Modified: llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll Mon Oct 24 12:45:02 2011
> @@ -6,8 +6,8 @@
>   volatile store i32 2, i32* %x, align 4
>   %0 = volatile load i32* %x, align 4             ; <i32> [#uses=1]
> ; CHECK: lui $3, %hi($JTI0_0)
> -; CHECK: sll $2, $2, 2
> ; CHECK: addiu $3, $3, %lo($JTI0_0)
> +; CHECK: sll $2, $2, 2
>   switch i32 %0, label %bb4 [
>     i32 0, label %bb5
>     i32 1, label %bb1
> 
> Modified: llvm/trunk/test/CodeGen/Mips/cmov.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cmov.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/cmov.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/cmov.ll Mon Oct 24 12:45:02 2011
> @@ -4,8 +4,8 @@
> @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
> @i3 = common global i32* null, align 4
> 
> -; CHECK:  addiu ${{[0-9]+}}, $gp, %got(i1)
> ; CHECK:  lw  ${{[0-9]+}}, %got(i3)($gp)
> +; CHECK:  addiu ${{[0-9]+}}, $gp, %got(i1)
> define i32* @cmov1(i32 %s) nounwind readonly {
> entry:
>   %tobool = icmp ne i32 %s, 0
> @@ -18,8 +18,8 @@
> @d = global i32 0, align 4
> 
> ; CHECK: cmov2:
> -; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c)
> ; CHECK: addiu $[[R1:[0-9]+]], $gp, %got(d)
> +; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c)
> ; CHECK: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
> define i32 @cmov2(i32 %s) nounwind readonly {
> entry:
> 
> Modified: llvm/trunk/test/CodeGen/Mips/eh.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/eh.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/eh.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/eh.ll Mon Oct 24 12:45:02 2011
> @@ -10,15 +10,11 @@
> ; CHECK-EL:  .cfi_def_cfa_offset
> ; CHECK-EL:  sdc1 $f20
> ; CHECK-EL:  sw  $ra
> -; CHECK-EL:  sw  $17
> -; CHECK-EL:  sw  $16
> ; CHECK-EL:  .cfi_offset 52, -8
> ; CHECK-EL:  .cfi_offset 53, -4
> ; CHECK-EB:  .cfi_offset 53, -8
> ; CHECK-EB:  .cfi_offset 52, -4
> ; CHECK-EL:  .cfi_offset 31, -12
> -; CHECK-EL:  .cfi_offset 17, -16
> -; CHECK-EL:  .cfi_offset 16, -20
> ; CHECK-EL:  .cprestore 
> 
>   %exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind
> 
> Modified: llvm/trunk/test/CodeGen/Mips/fcopysign.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcopysign.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/fcopysign.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/fcopysign.ll Mon Oct 24 12:45:02 2011
> @@ -4,27 +4,27 @@
> define double @func0(double %d0, double %d1) nounwind readnone {
> entry:
> ; CHECK-EL: func0:
> -; CHECK-EL: lui $[[T0:[0-9]+]], 32767
> ; CHECK-EL: lui $[[T1:[0-9]+]], 32768
> -; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f13
> -; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
> -; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f15
> ; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
> -; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
> -; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
> -; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12
> +; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f15
> +; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]]
> +; CHECK-EL: lui $[[T0:[0-9]+]], 32767
> +; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
> +; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f13
> +; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI1]], $[[MSK0]]
> ; CHECK-EL: or  $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
> +; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12
> ; CHECK-EL: mtc1 $[[LO0]], $f0
> ; CHECK-EL: mtc1 $[[OR]], $f1
> ;
> -; CHECK-EB: lui $[[T0:[0-9]+]], 32767
> ; CHECK-EB: lui $[[T1:[0-9]+]], 32768
> -; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12
> -; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
> -; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14
> ; CHECK-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0
> -; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
> +; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14
> ; CHECK-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
> +; CHECK-EB: lui $[[T0:[0-9]+]], 32767
> +; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
> +; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12
> +; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
> ; CHECK-EB: or  $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
> ; CHECK-EB: mfc1 $[[LO0:[0-9]+]], $f13
> ; CHECK-EB: mtc1 $[[OR]], $f0
> @@ -38,14 +38,14 @@
> define float @func1(float %f0, float %f1) nounwind readnone {
> entry:
> ; CHECK-EL: func1:
> -; CHECK-EL: lui $[[T0:[0-9]+]], 32767
> ; CHECK-EL: lui $[[T1:[0-9]+]], 32768
> -; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12
> -; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
> -; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14
> ; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
> -; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
> +; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14
> ; CHECK-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
> +; CHECK-EL: lui $[[T0:[0-9]+]], 32767
> +; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
> +; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12
> +; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
> ; CHECK-EL: or  $[[T4:[0-9]+]], $[[T2]], $[[T3]]
> ; CHECK-EL: mtc1 $[[T4]], $f0
>   %call = tail call float @copysignf(float %f0, float %f1) nounwind readnone
> 
> Removed: llvm/trunk/test/CodeGen/Mips/fpcmp.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fpcmp.ll?rev=142809&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/fpcmp.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/fpcmp.ll (removed)
> @@ -1,18 +0,0 @@
> -; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS32
> -
> - at g1 = external global i32
> -
> -define i32 @f(float %f0, float %f1) nounwind {
> -entry:
> -; CHECK-MIPS32: c.olt.s
> -; CHECK-MIPS32: movt
> -; CHECK-MIPS32: c.olt.s
> -; CHECK-MIPS32: movt
> -  %cmp = fcmp olt float %f0, %f1
> -  %conv = zext i1 %cmp to i32
> -  %tmp2 = load i32* @g1, align 4
> -  %add = add nsw i32 %tmp2, %conv
> -  store i32 %add, i32* @g1, align 4
> -  %cond = select i1 %cmp, i32 10, i32 20
> -  ret i32 %cond
> -}
> 
> Modified: llvm/trunk/test/CodeGen/Mips/i64arg.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/i64arg.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/i64arg.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/i64arg.ll Mon Oct 24 12:45:02 2011
> @@ -4,21 +4,21 @@
> entry:
> ; CHECK: addu $[[R1:[0-9]+]], $zero, $5
> ; CHECK: addu $[[R0:[0-9]+]], $zero, $4
> -; CHECK: lw  $25, %call16(ff1)
> ; CHECK: ori $6, ${{[0-9]+}}, 3855
> ; CHECK: ori $7, ${{[0-9]+}}, 22136
> +; CHECK: lw  $25, %call16(ff1)
> ; CHECK: jalr
>   tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
> ; CHECK: lw $25, %call16(ff2)
> -; CHECK: lw $[[R2:[0-9]+]], 88($sp)
> -; CHECK: lw $[[R3:[0-9]+]], 92($sp)
> +; CHECK: lw $[[R2:[0-9]+]], 80($sp)
> +; CHECK: lw $[[R3:[0-9]+]], 84($sp)
> ; CHECK: addu $4, $zero, $[[R2]]
> ; CHECK: addu $5, $zero, $[[R3]]
> ; CHECK: jalr $25
>   tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
>   %sub = add nsw i32 %i, -1
> -; CHECK: sw $[[R0]], 24($sp)
> ; CHECK: sw $[[R1]], 28($sp)
> +; CHECK: sw $[[R0]], 24($sp)
> ; CHECK: lw $25, %call16(ff3)
> ; CHECK: addu $6, $zero, $[[R2]]
> ; CHECK: addu $7, $zero, $[[R3]]
> 
> Modified: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll Mon Oct 24 12:45:02 2011
> @@ -8,10 +8,10 @@
> ; CHECK: #APP
> ; CHECK: sw $4, 0($[[T0]])
> ; CHECK: #NO_APP
> -; CHECK: lw  $[[T1:[0-9]+]], %got(g1)($gp)
> ; CHECK: #APP
> ; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]])
> ; CHECK: #NO_APP
> +; CHECK: lw  $[[T1:[0-9]+]], %got(g1)($gp)
> ; CHECK: sw  $[[T3]], 0($[[T1]])
> 
>   %l1 = alloca i32, align 4
> 
> Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Mon Oct 24 12:45:02 2011
> @@ -12,20 +12,20 @@
> entry:
> ; CHECK: lw  $[[R1:[0-9]+]], %got(f1.s1)($gp)
> ; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
> -; CHECK: lw  $[[R2:[0-9]+]], 8($[[R0]])
> -; CHECK: lw  $[[R7:[0-9]+]], 12($[[R0]])
> -; CHECK: lw  $[[R3:[0-9]+]], 16($[[R0]])
> -; CHECK: lw  $[[R4:[0-9]+]], 20($[[R0]])
> -; CHECK: lw  $[[R5:[0-9]+]], 24($[[R0]])
> ; CHECK: lw  $[[R6:[0-9]+]], 28($[[R0]])
> -; CHECK: sw  $[[R2]], 16($sp)
> -; CHECK: sw  $[[R7]], 20($sp)
> -; CHECK: sw  $[[R3]], 24($sp)
> -; CHECK: sw  $[[R4]], 28($sp)
> -; CHECK: sw  $[[R5]], 32($sp)
> +; CHECK: lw  $[[R5:[0-9]+]], 24($[[R0]])
> +; CHECK: lw  $[[R4:[0-9]+]], 20($[[R0]])
> +; CHECK: lw  $[[R3:[0-9]+]], 16($[[R0]])
> +; CHECK: lw  $[[R7:[0-9]+]], 12($[[R0]])
> +; CHECK: lw  $[[R2:[0-9]+]], 8($[[R0]])
> ; CHECK: sw  $[[R6]], 36($sp)
> -; CHECK: lw  $6, %lo(f1.s1)($[[R1]])
> +; CHECK: sw  $[[R5]], 32($sp)
> +; CHECK: sw  $[[R4]], 28($sp)
> +; CHECK: sw  $[[R3]], 24($sp)
> +; CHECK: sw  $[[R7]], 20($sp)
> +; CHECK: sw  $[[R2]], 16($sp)
> ; CHECK: lw  $7, 4($[[R0]])
> +; CHECK: lw  $6, %lo(f1.s1)($[[R1]])
>   %agg.tmp10 = alloca %struct.S3, align 4
>   call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
>   call void @callee2(%struct.S2* byval @f1.s2) nounwind
> @@ -44,20 +44,20 @@
> define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
> entry:
> ; CHECK: addiu $sp, $sp, -56
> -; CHECK: sw  $6, 64($sp)
> ; CHECK: sw  $7, 68($sp)
> +; CHECK: sw  $6, 64($sp)
> +; CHECK: lw  $4, 88($sp)
> ; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp)
> +; CHECK: lw  $[[R3:[0-9]+]], 72($sp)
> +; CHECK: lw  $[[R4:[0-9]+]], 76($sp)
> ; CHECK: lw  $[[R2:[0-9]+]], 68($sp)
> ; CHECK: lh  $[[R1:[0-9]+]], 66($sp)
> ; CHECK: lb  $[[R0:[0-9]+]], 64($sp)
> -; CHECK: lw  $[[R3:[0-9]+]], 72($sp)
> -; CHECK: lw  $[[R4:[0-9]+]], 76($sp)
> -; CHECK: lw  $4, 88($sp)
> -; CHECK: sw  $[[R3]], 16($sp)
> -; CHECK: sw  $[[R4]], 20($sp)
> -; CHECK: sw  $[[R2]], 24($sp)
> -; CHECK: sw  $[[R1]], 28($sp)
> ; CHECK: sw  $[[R0]], 32($sp)
> +; CHECK: sw  $[[R1]], 28($sp)
> +; CHECK: sw  $[[R2]], 24($sp)
> +; CHECK: sw  $[[R4]], 20($sp)
> +; CHECK: sw  $[[R3]], 16($sp)
> ; CHECK: mfc1 $6, $f[[F0]]
> 
>   %i2 = getelementptr inbounds %struct.S1* %s1, i32 0, i32 5
> @@ -81,12 +81,12 @@
> define void @f3(%struct.S2* nocapture byval %s2) nounwind {
> entry:
> ; CHECK: addiu $sp, $sp, -56
> -; CHECK: sw  $4, 56($sp)
> -; CHECK: sw  $5, 60($sp)
> -; CHECK: sw  $6, 64($sp)
> ; CHECK: sw  $7, 68($sp)
> -; CHECK: lw  $[[R0:[0-9]+]], 68($sp)
> +; CHECK: sw  $6, 64($sp)
> +; CHECK: sw  $5, 60($sp)
> +; CHECK: sw  $4, 56($sp)
> ; CHECK: lw  $4, 56($sp)
> +; CHECK: lw  $[[R0:[0-9]+]], 68($sp)
> ; CHECK: sw  $[[R0]], 24($sp)
> 
>   %arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0
> @@ -100,14 +100,14 @@
> define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
> entry:
> ; CHECK: addiu $sp, $sp, -56
> -; CHECK: sw  $5, 60($sp)
> -; CHECK: sw  $6, 64($sp)
> ; CHECK: sw  $7, 68($sp)
> +; CHECK: sw  $6, 64($sp)
> +; CHECK: sw  $5, 60($sp)
> +; CHECK: lw  $4, 68($sp)
> ; CHECK: lw  $[[R1:[0-9]+]], 88($sp)
> ; CHECK: lb  $[[R0:[0-9]+]], 60($sp)
> -; CHECK: lw  $4, 68($sp)
> -; CHECK: sw  $[[R1]], 24($sp)
> ; CHECK: sw  $[[R0]], 32($sp)
> +; CHECK: sw  $[[R1]], 24($sp)
> 
>   %i = getelementptr inbounds %struct.S1* %s1, i32 0, i32 2
>   %tmp = load i32* %i, align 4, !tbaa !0
> 
> Modified: llvm/trunk/test/CodeGen/Mips/unalignedload.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/unalignedload.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/unalignedload.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/unalignedload.ll Mon Oct 24 12:45:02 2011
> @@ -9,27 +9,27 @@
> 
> define void @foo1() nounwind {
> entry:
> -; CHECK-EL: lw  $25, %call16(foo2)
> ; CHECK-EL: ulhu  $4, 2
> +; CHECK-EL: lw  $25, %call16(foo2)
> ; CHECK-EL: lw  $[[R0:[0-9]+]], %got(s4)
> ; CHECK-EL: lbu $[[R1:[0-9]+]], 6($[[R0]])
> -; CHECK-EL: ulhu  $[[R2:[0-9]+]], 4($[[R0]])
> ; CHECK-EL: sll $[[R3:[0-9]+]], $[[R1]], 16
> +; CHECK-EL: ulhu  $[[R2:[0-9]+]], 4($[[R0]])
> +; CHECK-EL: or  $5, $[[R2]], $[[R3]]
> ; CHECK-EL: ulw $4, 0($[[R0]])
> ; CHECK-EL: lw  $25, %call16(foo4)
> -; CHECK-EL: or  $5, $[[R2]], $[[R3]]
> 
> ; CHECK-EB: ulhu  $[[R0:[0-9]+]], 2
> -; CHECK-EB: lw  $25, %call16(foo2)
> ; CHECK-EB: sll $4, $[[R0]], 16
> +; CHECK-EB: lw  $25, %call16(foo2)
> ; CHECK-EB: lw  $[[R1:[0-9]+]], %got(s4)
> -; CHECK-EB: ulhu  $[[R2:[0-9]+]], 4($[[R1]])
> ; CHECK-EB: lbu $[[R3:[0-9]+]], 6($[[R1]])
> -; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16
> ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R3]], 8
> +; CHECK-EB: ulhu  $[[R2:[0-9]+]], 4($[[R1]])
> +; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16
> +; CHECK-EB: or  $5, $[[R4]], $[[R5]]
> ; CHECK-EB: ulw $4, 0($[[R1]])
> ; CHECK-EB: lw  $25, %call16(foo4)
> -; CHECK-EB: or  $5, $[[R4]], $[[R5]]
> 
>   tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2* @s2, i32 0, i32 1)) nounwind
>   tail call void @foo4(%struct.S4* byval @s4) nounwind
> 
> Modified: llvm/trunk/test/CodeGen/PTX/cvt.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/cvt.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PTX/cvt.ll (original)
> +++ llvm/trunk/test/CodeGen/PTX/cvt.ll Mon Oct 24 12:45:02 2011
> @@ -172,9 +172,9 @@
> ; f32
> 
> define ptx_device float @cvt_f32_preds(i1 %x) {
> -; CHECK: mov.b32 %f0, 1065353216;
> -; CHECK: mov.b32 %f1, 0;
> -; CHECK: selp.f32 %ret{{[0-9]+}}, %f0, %f1, %p{{[0-9]+}};
> +; CHECK: mov.b32 %f0, 0;
> +; CHECK: mov.b32 %f1, 1065353216;
> +; CHECK: selp.f32 %ret{{[0-9]+}}, %f1, %f0, %p{{[0-9]+}};
> ; CHECK: ret;
> 	%a = uitofp i1 %x to float
> 	ret float %a
> @@ -232,9 +232,9 @@
> ; f64
> 
> define ptx_device double @cvt_f64_preds(i1 %x) {
> -; CHECK: mov.b64 %fd0, 4575657221408423936;
> -; CHECK: mov.b64 %fd1, 0;
> -; CHECK: selp.f64 %ret{{[0-9]+}}, %fd0, %fd1, %p{{[0-9]+}};
> +; CHECK: mov.b64 %fd0, 0;
> +; CHECK: mov.b64 %fd1, 4575657221408423936;
> +; CHECK: selp.f64 %ret{{[0-9]+}}, %fd1, %fd0, %p{{[0-9]+}};
> ; CHECK: ret;
> 	%a = uitofp i1 %x to double
> 	ret double %a
> 
> Removed: llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll?rev=142809&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll (removed)
> @@ -1,23 +0,0 @@
> -; RUN: llc < %s -march=ppc32 -combiner-alias-analysis | grep f5
> -
> -target datalayout = "E-p:32:32"
> -target triple = "powerpc-apple-darwin8.2.0"
> -        %struct.Point = type { double, double, double }
> -
> -define void @offset(%struct.Point* %pt, double %x, double %y, double %z) {
> -entry:
> -        %tmp = getelementptr %struct.Point* %pt, i32 0, i32 0           ; <double*> [#uses=2]
> -        %tmp.upgrd.1 = load double* %tmp                ; <double> [#uses=1]
> -        %tmp2 = fadd double %tmp.upgrd.1, %x             ; <double> [#uses=1]
> -        store double %tmp2, double* %tmp
> -        %tmp6 = getelementptr %struct.Point* %pt, i32 0, i32 1          ; <double*> [#uses=2]
> -        %tmp7 = load double* %tmp6              ; <double> [#uses=1]
> -        %tmp9 = fadd double %tmp7, %y            ; <double> [#uses=1]
> -        store double %tmp9, double* %tmp6
> -        %tmp13 = getelementptr %struct.Point* %pt, i32 0, i32 2         ; <double*> [#uses=2]
> -        %tmp14 = load double* %tmp13            ; <double> [#uses=1]
> -        %tmp16 = fadd double %tmp14, %z          ; <double> [#uses=1]
> -        store double %tmp16, double* %tmp13
> -        ret void
> -}
> -
> 
> Modified: llvm/trunk/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll Mon Oct 24 12:45:02 2011
> @@ -1,9 +1,9 @@
> ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \
> -; RUN:   grep {stw r3, 32751}
> +; RUN:   grep {stw r4, 32751}
> ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
> -; RUN:   grep {stw r3, 32751}
> +; RUN:   grep {stw r4, 32751}
> ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
> -; RUN:   grep {std r3, 9024}
> +; RUN:   grep {std r4, 9024}
> 
> define void @test() nounwind {
> 	store i32 0, i32* inttoptr (i64 48725999 to i32*)
> 
> Modified: llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll Mon Oct 24 12:45:02 2011
> @@ -47,8 +47,8 @@
> 
> L1:                                               ; preds = %L2, %bb2
>   %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ]  ; <i32> [#uses=1]
> -; PIC: addis r[[R0:[0-9]+]], r{{[0-9]+}}, ha16(Ltmp0-L0$pb)
> ; PIC: li r[[R1:[0-9]+]], lo16(Ltmp0-L0$pb)
> +; PIC: addis r[[R0:[0-9]+]], r{{[0-9]+}}, ha16(Ltmp0-L0$pb)
> ; PIC: add r[[R2:[0-9]+]], r[[R0]], r[[R1]]
> ; PIC: stw r[[R2]]
> ; STATIC: li r[[R0:[0-9]+]], lo16(Ltmp0)
> 
> Modified: llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll?rev=142810&r1=142809&r2=142810&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll Mon Oct 24 12:45:02 2011
> @@ -12,156 +12,151 @@
> define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
>  entry:
>   %x = va_arg %struct.__va_list_tag* %ap, i64; Get from r5,r6
> -; CHECK:      lbz 4, 0(3)
> -; CHECK-NEXT: lwz 5, 4(3)
> -; CHECK-NEXT: rlwinm 6, 4, 0, 31, 31
> -; CHECK-NEXT: cmplwi 0, 6, 0
> -; CHECK-NEXT: addi 6, 4, 1
> +; CHECK: lbz 4, 0(3)
> +; CHECK-NEXT: rlwinm 5, 4, 0, 31, 31
> +; CHECK-NEXT: cmplwi 0, 5, 0
> +; CHECK-NEXT: addi 5, 4, 1
> ; CHECK-NEXT: stw 3, -4(1)
> -; CHECK-NEXT: stw 6, -8(1)
> +; CHECK-NEXT: stw 5, -8(1)
> ; CHECK-NEXT: stw 4, -12(1)
> -; CHECK-NEXT: stw 5, -16(1)
> ; CHECK-NEXT: bne 0, .LBB0_2
> ; CHECK-NEXT: # BB#1:                                 # %entry
> ; CHECK-NEXT: lwz 3, -12(1)
> ; CHECK-NEXT: stw 3, -8(1)
> ; CHECK-NEXT: .LBB0_2:                                # %entry
> ; CHECK-NEXT: lwz 3, -8(1)
> -; CHECK-NEXT: lwz 4, -4(1)
> -; CHECK-NEXT: lwz 5, 8(4)
> -; CHECK-NEXT: slwi 6, 3, 2
> -; CHECK-NEXT: addi 7, 3, 2
> +; CHECK-NEXT: slwi 4, 3, 2
> +; CHECK-NEXT: lwz 5, -4(1)
> +; CHECK-NEXT: lwz 6, 4(5)
> +; CHECK-NEXT: lwz 7, 8(5)
> +; CHECK-NEXT: add 4, 7, 4
> ; CHECK-NEXT: cmpwi 0, 3, 8
> -; CHECK-NEXT: lwz 3, -16(1)
> -; CHECK-NEXT: addi 8, 3, 4
> -; CHECK-NEXT: add 5, 5, 6
> ; CHECK-NEXT: mfcr 0                          # cr0
> -; CHECK-NEXT: stw 0, -20(1)
> -; CHECK-NEXT: stw 5, -24(1)
> -; CHECK-NEXT: stw 3, -28(1)
> -; CHECK-NEXT: stw 7, -32(1)
> -; CHECK-NEXT: stw 8, -36(1)
> +; CHECK-NEXT: stw 0, -16(1)
> +; CHECK-NEXT: stw 3, -20(1)
> +; CHECK-NEXT: stw 4, -24(1)
> +; CHECK-NEXT: stw 6, -28(1)
> ; CHECK-NEXT: blt 0, .LBB0_4
> ; CHECK-NEXT: # BB#3:                                 # %entry
> -; CHECK-NEXT: lwz 3, -36(1)
> -; CHECK-NEXT: stw 3, -28(1)
> -; CHECK-NEXT: .LBB0_4:                                # %entry
> ; CHECK-NEXT: lwz 3, -28(1)
> -; CHECK-NEXT: lwz 4, -32(1)
> -; CHECK-NEXT: lwz 5, -4(1)
> -; CHECK-NEXT: stb 4, 0(5)
> -; CHECK-NEXT: lwz 4, -24(1)
> -; CHECK-NEXT: lwz 0, -20(1)
> +; CHECK-NEXT: stw 3, -24(1)
> +; CHECK-NEXT: .LBB0_4:                                # %entry
> +; CHECK-NEXT: lwz 3, -24(1)
> +; CHECK-NEXT: lwz 4, -28(1)
> +; CHECK-NEXT: addi 5, 4, 4
> +; CHECK-NEXT: lwz 0, -16(1)
> ; CHECK-NEXT: mtcrf 128, 0
> +; CHECK-NEXT: stw 4, -32(1)
> +; CHECK-NEXT: stw 5, -36(1)
> ; CHECK-NEXT: stw 3, -40(1)
> -; CHECK-NEXT: stw 4, -44(1)
> ; CHECK-NEXT: blt 0, .LBB0_6
> ; CHECK-NEXT: # BB#5:                                 # %entry
> -; CHECK-NEXT: lwz 3, -16(1)
> -; CHECK-NEXT: stw 3, -44(1)
> +; CHECK-NEXT: lwz 3, -36(1)
> +; CHECK-NEXT: stw 3, -32(1)
> ; CHECK-NEXT: .LBB0_6:                                # %entry
> -; CHECK-NEXT: lwz 3, -44(1)
> -; CHECK-NEXT: lwz 4, -40(1)
> -; CHECK-NEXT: lwz 5, -4(1)
> -; CHECK-NEXT: stw 4, 4(5)
> +; CHECK-NEXT: lwz 3, -32(1)
> +; CHECK-NEXT: lwz 4, -20(1)
> +; CHECK-NEXT: addi 5, 4, 2
> +; CHECK-NEXT: lwz 6, -4(1)
> +; CHECK-NEXT: stb 5, 0(6)
> +; CHECK-NEXT: stw 3, 4(6)
>   store i64 %x, i64* @var1, align 8
> -; CHECK-NEXT: lis 4, var1 at ha
> -; CHECK-NEXT: lwz 6, 4(3)
> -; CHECK-NEXT: lwz 3, 0(3)
> -; CHECK-NEXT: la 7, var1 at l(4)
> -; CHECK-NEXT: stw 3, var1 at l(4)
> -; CHECK-NEXT: stw 6, 4(7)
> +; CHECK-NEXT: lwz 3, -40(1)
> +; CHECK-NEXT: lwz 5, 0(3)
> +; CHECK-NEXT: lwz 7, 4(3)
> +; CHECK-NEXT: lis 8, var1 at ha
> +; CHECK-NEXT: la 9, var1 at l(8)
> +; CHECK-NEXT: stw 7, 4(9)
> +; CHECK-NEXT: stw 5, var1 at l(8)
>   %y = va_arg %struct.__va_list_tag* %ap, double; From f1
> -; CHECK-NEXT: lbz 3, 1(5)
> -; CHECK-NEXT: lwz 4, 4(5)
> -; CHECK-NEXT: lwz 6, 8(5)
> -; CHECK-NEXT: slwi 7, 3, 3
> -; CHECK-NEXT: add 6, 6, 7
> -; CHECK-NEXT: addi 7, 3, 1
> -; CHECK-NEXT: cmpwi 0, 3, 8
> -; CHECK-NEXT: addi 3, 4, 8
> -; CHECK-NEXT: addi 6, 6, 32
> -; CHECK-NEXT: mr 8, 4
> +; CHECK-NEXT: lbz 5, 1(6)
> +; CHECK-NEXT: lwz 7, 4(6)
> +; CHECK-NEXT: lwz 8, 8(6)
> +; CHECK-NEXT: slwi 9, 5, 3
> +; CHECK-NEXT: add 8, 8, 9
> +; CHECK-NEXT: cmpwi 0, 5, 8
> +; CHECK-NEXT: addi 9, 7, 8
> +; CHECK-NEXT: mr 10, 7
> +; CHECK-NEXT: stw 9, -44(1)
> +; CHECK-NEXT: stw 7, -48(1)
> ; CHECK-NEXT: mfcr 0                          # cr0
> -; CHECK-NEXT: stw 0, -48(1)
> -; CHECK-NEXT: stw 4, -52(1)
> -; CHECK-NEXT: stw 6, -56(1)
> -; CHECK-NEXT: stw 7, -60(1)
> -; CHECK-NEXT: stw 3, -64(1)
> -; CHECK-NEXT: stw 8, -68(1)
> +; CHECK-NEXT: stw 0, -52(1)
> +; CHECK-NEXT: stw 5, -56(1)
> +; CHECK-NEXT: stw 10, -60(1)
> +; CHECK-NEXT: stw 8, -64(1)
> ; CHECK-NEXT: blt 0, .LBB0_8
> ; CHECK-NEXT: # BB#7:                                 # %entry
> -; CHECK-NEXT: lwz 3, -64(1)
> -; CHECK-NEXT: stw 3, -68(1)
> +; CHECK-NEXT: lwz 3, -44(1)
> +; CHECK-NEXT: stw 3, -60(1)
> ; CHECK-NEXT: .LBB0_8:                                # %entry
> -; CHECK-NEXT: lwz 3, -68(1)
> -; CHECK-NEXT: lwz 4, -60(1)
> -; CHECK-NEXT: lwz 5, -4(1)
> -; CHECK-NEXT: stb 4, 1(5)
> -; CHECK-NEXT: lwz 4, -56(1)
> -; CHECK-NEXT: lwz 0, -48(1)
> +; CHECK-NEXT: lwz 3, -60(1)
> +; CHECK-NEXT: lwz 4, -64(1)
> +; CHECK-NEXT: addi 4, 4, 32
> +; CHECK-NEXT: lwz 0, -52(1)
> ; CHECK-NEXT: mtcrf 128, 0
> -; CHECK-NEXT: stw 4, -72(1)
> -; CHECK-NEXT: stw 3, -76(1)
> +; CHECK-NEXT: stw 4, -68(1)
> +; CHECK-NEXT: stw 3, -72(1)
> ; CHECK-NEXT: blt 0, .LBB0_10
> ; CHECK-NEXT: # BB#9:                                 # %entry
> -; CHECK-NEXT: lwz 3, -52(1)
> -; CHECK-NEXT: stw 3, -72(1)
> +; CHECK-NEXT: lwz 3, -48(1)
> +; CHECK-NEXT: stw 3, -68(1)
> ; CHECK-NEXT: .LBB0_10:                               # %entry
> -; CHECK-NEXT: lwz 3, -72(1)
> -; CHECK-NEXT: lwz 4, -76(1)
> -; CHECK-NEXT: lwz 5, -4(1)
> -; CHECK-NEXT: stw 4, 4(5)
> +; CHECK-NEXT: lwz 3, -68(1)
> +; CHECK-NEXT: lwz 4, -56(1)
> +; CHECK-NEXT: addi 5, 4, 1
> +; CHECK-NEXT: lwz 6, -4(1)
> +; CHECK-NEXT: stb 5, 1(6)
> +; CHECK-NEXT: lwz 5, -72(1)
> +; CHECK-NEXT: stw 5, 4(6)
> ; CHECK-NEXT: lfd 0, 0(3)
>   store double %y, double* @var2, align 8
> ; CHECK-NEXT: lis 3, var2 at ha
> ; CHECK-NEXT: stfd 0, var2 at l(3)
>   %z = va_arg %struct.__va_list_tag* %ap, i32; From r7
> -; CHECK-NEXT: lbz 3, 0(5)
> -; CHECK-NEXT: lwz 4, 4(5)
> -; CHECK-NEXT: lwz 6, 8(5)
> -; CHECK-NEXT: slwi 7, 3, 2
> -; CHECK-NEXT: addi 8, 3, 1
> +; CHECK-NEXT: lbz 3, 0(6)
> +; CHECK-NEXT: lwz 5, 4(6)
> +; CHECK-NEXT: lwz 7, 8(6)
> +; CHECK-NEXT: slwi 8, 3, 2
> +; CHECK-NEXT: add 7, 7, 8
> ; CHECK-NEXT: cmpwi 0, 3, 8
> -; CHECK-NEXT: addi 3, 4, 4
> -; CHECK-NEXT: add 6, 6, 7
> -; CHECK-NEXT: mr 7, 4
> -; CHECK-NEXT: stw 6, -80(1)
> +; CHECK-NEXT: addi 8, 5, 4
> +; CHECK-NEXT: mr 9, 5
> +; CHECK-NEXT: stw 3, -76(1)
> +; CHECK-NEXT: stw 7, -80(1)
> ; CHECK-NEXT: stw 8, -84(1)
> -; CHECK-NEXT: stw 3, -88(1)
> -; CHECK-NEXT: stw 4, -92(1)
> -; CHECK-NEXT: stw 7, -96(1)
> +; CHECK-NEXT: stw 5, -88(1)
> +; CHECK-NEXT: stw 9, -92(1)
> ; CHECK-NEXT: mfcr 0                          # cr0
> -; CHECK-NEXT: stw 0, -100(1)
> +; CHECK-NEXT: stw 0, -96(1)
> ; CHECK-NEXT: blt 0, .LBB0_12
> ; CHECK-NEXT: # BB#11:                                # %entry
> -; CHECK-NEXT: lwz 3, -88(1)
> -; CHECK-NEXT: stw 3, -96(1)
> +; CHECK-NEXT: lwz 3, -84(1)
> +; CHECK-NEXT: stw 3, -92(1)
> ; CHECK-NEXT: .LBB0_12:                               # %entry
> -; CHECK-NEXT: lwz 3, -96(1)
> -; CHECK-NEXT: lwz 4, -84(1)
> -; CHECK-NEXT: lwz 5, -4(1)
> -; CHECK-NEXT: stb 4, 0(5)
> +; CHECK-NEXT: lwz 3, -92(1)
> ; CHECK-NEXT: lwz 4, -80(1)
> -; CHECK-NEXT: lwz 0, -100(1)
> +; CHECK-NEXT: lwz 0, -96(1)
> ; CHECK-NEXT: mtcrf 128, 0
> +; CHECK-NEXT: stw 3, -100(1)
> ; CHECK-NEXT: stw 4, -104(1)
> -; CHECK-NEXT: stw 3, -108(1)
> ; CHECK-NEXT: blt 0, .LBB0_14
> ; CHECK-NEXT: # BB#13:                                # %entry
> -; CHECK-NEXT: lwz 3, -92(1)
> +; CHECK-NEXT: lwz 3, -88(1)
> ; CHECK-NEXT: stw 3, -104(1)
> ; CHECK-NEXT: .LBB0_14:                               # %entry
> ; CHECK-NEXT: lwz 3, -104(1)
> -; CHECK-NEXT: lwz 4, -108(1)
> -; CHECK-NEXT: lwz 5, -4(1)
> -; CHECK-NEXT: stw 4, 4(5)
> +; CHECK-NEXT: lwz 4, -76(1)
> +; CHECK-NEXT: addi 5, 4, 1
> +; CHECK-NEXT: lwz 6, -4(1)
> +; CHECK-NEXT: stb 5, 0(6)
> +; CHECK-NEXT: lwz 5, -100(1)
> +; CHECK-NEXT: stw 5, 4(6)
> ; CHECK-NEXT: lwz 3, 0(3)
>   store i32 %z, i32* @var3, align 4
> -; CHECK-NEXT: lis 4, var3 at ha
> -; CHECK-NEXT: stw 3, var3 at l(4)
> +; CHECK-NEXT: lis 5, var3 at ha
> +; CHECK-NEXT: stw 3, var3 at l(5)
>   ret void
> -; CHECK-NEXT: stw 5, -112(1)
> -; CHECK-NEXT: blr
> +; CHECK-NEXT: stw 6, -108(1)
> +; CHECK-NEXT: blr 
> }
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From gohman at apple.com  Mon Oct 24 13:01:06 2011
From: gohman at apple.com (Dan Gohman)
Date: Mon, 24 Oct 2011 18:01:06 -0000
Subject: [llvm-commits] [llvm] r142816 - in /llvm/trunk:
 include/llvm/CodeGen/LinkAllCodegenComponents.h
 include/llvm/CodeGen/SchedulerRegistry.h
 lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Message-ID: <20111024180106.ED702312800A@llvm.org>

Author: djg
Date: Mon Oct 24 13:01:06 2011
New Revision: 142816

URL: http://llvm.org/viewvc/llvm-project?rev=142816&view=rev
Log:
Delete the top-down "Latency" scheduler. Top-down scheduling doesn't handle
physreg dependencies, and upcoming codegen changes will require proper
physreg dependence handling.

Removed:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
Modified:
    llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
    llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h

Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=142816&r1=142815&r2=142816&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Mon Oct 24 13:01:06 2011
@@ -45,7 +45,6 @@
       (void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
       (void) llvm::createSourceListDAGScheduler(NULL,llvm::CodeGenOpt::Default);
       (void) llvm::createHybridListDAGScheduler(NULL,llvm::CodeGenOpt::Default);
-      (void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
       (void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);
       (void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);
 

Modified: llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h?rev=142816&r1=142815&r2=142816&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SchedulerRegistry.h Mon Oct 24 13:01:06 2011
@@ -86,10 +86,6 @@
 /// to reduce register pressure.
 ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
                                               CodeGenOpt::Level);
-/// createTDListDAGScheduler - This creates a top-down list scheduler with
-/// a hazard recognizer.
-ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
-                                             CodeGenOpt::Level OptLevel);
 
 /// createFastDAGScheduler - This creates a "fast" scheduler.
 ///

Removed: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=142815&view=auto
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (removed)
@@ -1,265 +0,0 @@
-//===---- ScheduleDAGList.cpp - Implement a list scheduler for isel DAG ---===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This implements a top-down list scheduler, using standard algorithms.
-// The basic approach uses a priority queue of available nodes to schedule.
-// One at a time, nodes are taken from the priority queue (thus in priority
-// order), checked for legality to schedule, and emitted if legal.
-//
-// Nodes may not be legal to schedule either due to structural hazards (e.g.
-// pipeline or resource constraints) or because an input to the instruction has
-// not completed execution.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "pre-RA-sched"
-#include "ScheduleDAGSDNodes.h"
-#include "llvm/CodeGen/LatencyPriorityQueue.h"
-#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
-#include "llvm/CodeGen/SchedulerRegistry.h"
-#include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/ADT/Statistic.h"
-#include <climits>
-using namespace llvm;
-
-STATISTIC(NumNoops , "Number of noops inserted");
-STATISTIC(NumStalls, "Number of pipeline stalls");
-
-static RegisterScheduler
-  tdListDAGScheduler("list-td", "Top-down list scheduler",
-                     createTDListDAGScheduler);
-
-namespace {
-//===----------------------------------------------------------------------===//
-/// ScheduleDAGList - The actual list scheduler implementation.  This supports
-/// top-down scheduling.
-///
-class ScheduleDAGList : public ScheduleDAGSDNodes {
-private:
-  /// AvailableQueue - The priority queue to use for the available SUnits.
-  ///
-  SchedulingPriorityQueue *AvailableQueue;
-
-  /// PendingQueue - This contains all of the instructions whose operands have
-  /// been issued, but their results are not ready yet (due to the latency of
-  /// the operation).  Once the operands become available, the instruction is
-  /// added to the AvailableQueue.
-  std::vector<SUnit*> PendingQueue;
-
-  /// HazardRec - The hazard recognizer to use.
-  ScheduleHazardRecognizer *HazardRec;
-
-public:
-  ScheduleDAGList(MachineFunction &mf,
-                  SchedulingPriorityQueue *availqueue)
-    : ScheduleDAGSDNodes(mf), AvailableQueue(availqueue) {
-
-    const TargetMachine &tm = mf.getTarget();
-    HazardRec = tm.getInstrInfo()->CreateTargetHazardRecognizer(&tm, this);
-  }
-
-  ~ScheduleDAGList() {
-    delete HazardRec;
-    delete AvailableQueue;
-  }
-
-  void Schedule();
-
-private:
-  void ReleaseSucc(SUnit *SU, const SDep &D);
-  void ReleaseSuccessors(SUnit *SU);
-  void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
-  void ListScheduleTopDown();
-};
-}  // end anonymous namespace
-
-/// Schedule - Schedule the DAG using list scheduling.
-void ScheduleDAGList::Schedule() {
-  DEBUG(dbgs() << "********** List Scheduling **********\n");
-
-  // Build the scheduling graph.
-  BuildSchedGraph(NULL);
-
-  AvailableQueue->initNodes(SUnits);
-
-  ListScheduleTopDown();
-
-  AvailableQueue->releaseState();
-}
-
-//===----------------------------------------------------------------------===//
-//  Top-Down Scheduling
-//===----------------------------------------------------------------------===//
-
-/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
-/// the PendingQueue if the count reaches zero. Also update its cycle bound.
-void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) {
-  SUnit *SuccSU = D.getSUnit();
-
-#ifndef NDEBUG
-  if (SuccSU->NumPredsLeft == 0) {
-    dbgs() << "*** Scheduling failed! ***\n";
-    SuccSU->dump(this);
-    dbgs() << " has been released too many times!\n";
-    llvm_unreachable(0);
-  }
-#endif
-  --SuccSU->NumPredsLeft;
-
-  SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
-
-  // If all the node's predecessors are scheduled, this node is ready
-  // to be scheduled. Ignore the special ExitSU node.
-  if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
-    PendingQueue.push_back(SuccSU);
-}
-
-void ScheduleDAGList::ReleaseSuccessors(SUnit *SU) {
-  // Top down: release successors.
-  for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
-       I != E; ++I) {
-    assert(!I->isAssignedRegDep() &&
-           "The list-td scheduler doesn't yet support physreg dependencies!");
-
-    ReleaseSucc(SU, *I);
-  }
-}
-
-/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
-/// count of its successors. If a successor pending count is zero, add it to
-/// the Available queue.
-void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
-  DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
-  DEBUG(SU->dump(this));
-
-  Sequence.push_back(SU);
-  assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
-  SU->setDepthToAtLeast(CurCycle);
-
-  ReleaseSuccessors(SU);
-  SU->isScheduled = true;
-  AvailableQueue->ScheduledNode(SU);
-}
-
-/// ListScheduleTopDown - The main loop of list scheduling for top-down
-/// schedulers.
-void ScheduleDAGList::ListScheduleTopDown() {
-  unsigned CurCycle = 0;
-
-  // Release any successors of the special Entry node.
-  ReleaseSuccessors(&EntrySU);
-
-  // All leaves to Available queue.
-  for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
-    // It is available if it has no predecessors.
-    if (SUnits[i].Preds.empty()) {
-      AvailableQueue->push(&SUnits[i]);
-      SUnits[i].isAvailable = true;
-    }
-  }
-
-  // While Available queue is not empty, grab the node with the highest
-  // priority. If it is not ready put it back.  Schedule the node.
-  std::vector<SUnit*> NotReady;
-  Sequence.reserve(SUnits.size());
-  while (!AvailableQueue->empty() || !PendingQueue.empty()) {
-    // Check to see if any of the pending instructions are ready to issue.  If
-    // so, add them to the available queue.
-    for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
-      if (PendingQueue[i]->getDepth() == CurCycle) {
-        AvailableQueue->push(PendingQueue[i]);
-        PendingQueue[i]->isAvailable = true;
-        PendingQueue[i] = PendingQueue.back();
-        PendingQueue.pop_back();
-        --i; --e;
-      } else {
-        assert(PendingQueue[i]->getDepth() > CurCycle && "Negative latency?");
-      }
-    }
-
-    // If there are no instructions available, don't try to issue anything, and
-    // don't advance the hazard recognizer.
-    if (AvailableQueue->empty()) {
-      ++CurCycle;
-      continue;
-    }
-
-    SUnit *FoundSUnit = 0;
-
-    bool HasNoopHazards = false;
-    while (!AvailableQueue->empty()) {
-      SUnit *CurSUnit = AvailableQueue->pop();
-
-      ScheduleHazardRecognizer::HazardType HT =
-        HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
-      if (HT == ScheduleHazardRecognizer::NoHazard) {
-        FoundSUnit = CurSUnit;
-        break;
-      }
-
-      // Remember if this is a noop hazard.
-      HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
-
-      NotReady.push_back(CurSUnit);
-    }
-
-    // Add the nodes that aren't ready back onto the available list.
-    if (!NotReady.empty()) {
-      AvailableQueue->push_all(NotReady);
-      NotReady.clear();
-    }
-
-    // If we found a node to schedule, do it now.
-    if (FoundSUnit) {
-      ScheduleNodeTopDown(FoundSUnit, CurCycle);
-      HazardRec->EmitInstruction(FoundSUnit);
-
-      // If this is a pseudo-op node, we don't want to increment the current
-      // cycle.
-      if (FoundSUnit->Latency)  // Don't increment CurCycle for pseudo-ops!
-        ++CurCycle;
-    } else if (!HasNoopHazards) {
-      // Otherwise, we have a pipeline stall, but no other problem, just advance
-      // the current cycle and try again.
-      DEBUG(dbgs() << "*** Advancing cycle, no work to do\n");
-      HazardRec->AdvanceCycle();
-      ++NumStalls;
-      ++CurCycle;
-    } else {
-      // Otherwise, we have no instructions to issue and we have instructions
-      // that will fault if we don't do this right.  This is the case for
-      // processors without pipeline interlocks and other cases.
-      DEBUG(dbgs() << "*** Emitting noop\n");
-      HazardRec->EmitNoop();
-      Sequence.push_back(0);   // NULL here means noop
-      ++NumNoops;
-      ++CurCycle;
-    }
-  }
-
-#ifndef NDEBUG
-  VerifySchedule(/*isBottomUp=*/false);
-#endif
-}
-
-//===----------------------------------------------------------------------===//
-//                         Public Constructor Functions
-//===----------------------------------------------------------------------===//
-
-/// createTDListDAGScheduler - This creates a top-down list scheduler.
-ScheduleDAGSDNodes *
-llvm::createTDListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
-  return new ScheduleDAGList(*IS->MF, new LatencyPriorityQueue());
-}



From resistor at mac.com  Mon Oct 24 13:04:29 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 24 Oct 2011 18:04:29 -0000
Subject: [llvm-commits] [llvm] r142817 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/neont2.txt
Message-ID: <20111024180429.6A91D312800A@llvm.org>

Author: resistor
Date: Mon Oct 24 13:04:29 2011
New Revision: 142817

URL: http://llvm.org/viewvc/llvm-project?rev=142817&view=rev
Log:
Fix a NEON disassembly case that was broken in the recent refactorings.  As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/neont2.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=142817&r1=142816&r2=142817&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Oct 24 13:04:29 2011
@@ -1974,12 +1974,6 @@
       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
         return MCDisassembler::Fail;
       break;
-    case ARM::VLD2b8:
-    case ARM::VLD2b16:
-    case ARM::VLD2b32:
-    case ARM::VLD2b8_UPD:
-    case ARM::VLD2b16_UPD:
-    case ARM::VLD2b32_UPD:
     case ARM::VLD3q8:
     case ARM::VLD3q16:
     case ARM::VLD3q32:

Modified: llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neont2.txt?rev=142817&r1=142816&r2=142817&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neont2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neont2.txt Mon Oct 24 13:04:29 2011
@@ -1584,3 +1584,7 @@
 # CHECK: vst4.16	{d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
 0xc0 0xf9 0x4f 0x1b
 # CHECK: vst4.32	{d17[0], d19[0], d21[0], d23[0]}, [r0]
+
+0x63 0xf9 0x37 0xc9
+# CHECK: vld2.8	{d28, d29}, [r3, :256], r7
+



From dgregor at apple.com  Mon Oct 24 13:09:23 2011
From: dgregor at apple.com (Douglas Gregor)
Date: Mon, 24 Oct 2011 18:09:23 -0000
Subject: [llvm-commits] [llvm] r142821 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt
Message-ID: <20111024180923.4C350312800A@llvm.org>

Author: dgregor
Date: Mon Oct 24 13:09:23 2011
New Revision: 142821

URL: http://llvm.org/viewvc/llvm-project?rev=142821&view=rev
Log:
Unbreak CMake build

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt?rev=142821&r1=142820&r2=142821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt Mon Oct 24 13:09:23 2011
@@ -17,6 +17,7 @@
   SelectionDAG.cpp
   SelectionDAGBuilder.cpp
   SelectionDAGISel.cpp
+  SelectionDAGList.cpp
   SelectionDAGPrinter.cpp
   TargetLowering.cpp
   TargetSelectionDAGInfo.cpp



From dgregor at apple.com  Mon Oct 24 13:10:52 2011
From: dgregor at apple.com (Douglas Gregor)
Date: Mon, 24 Oct 2011 18:10:52 -0000
Subject: [llvm-commits] [llvm] r142822 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt
Message-ID: <20111024181052.69833312800A@llvm.org>

Author: dgregor
Date: Mon Oct 24 13:10:52 2011
New Revision: 142822

URL: http://llvm.org/viewvc/llvm-project?rev=142822&view=rev
Log:
Really unbreak CMake build

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt?rev=142822&r1=142821&r2=142822&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt Mon Oct 24 13:10:52 2011
@@ -11,13 +11,11 @@
   LegalizeVectorOps.cpp
   LegalizeVectorTypes.cpp
   ScheduleDAGFast.cpp
-  ScheduleDAGList.cpp
-  ScheduleDAGRRList.cpp
+ ScheduleDAGRRList.cpp
   ScheduleDAGSDNodes.cpp
   SelectionDAG.cpp
   SelectionDAGBuilder.cpp
   SelectionDAGISel.cpp
-  SelectionDAGList.cpp
   SelectionDAGPrinter.cpp
   TargetLowering.cpp
   TargetSelectionDAGInfo.cpp



From dblaikie at gmail.com  Mon Oct 24 13:14:59 2011
From: dblaikie at gmail.com (David Blaikie)
Date: Mon, 24 Oct 2011 11:14:59 -0700
Subject: [llvm-commits] [llvm] r142731 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
In-Reply-To: <20111022195820.621CC2A6C12C@llvm.org>
References: <20111022195820.621CC2A6C12C@llvm.org>
Message-ID: <CAENS6EvZqx4aO9Z7D6k4Y+x_6EMDL8X0T9MivyLsoQHqrctjRg@mail.gmail.com>

> Make SCEV's brute force analysis stronger in two ways. Firstly, we should be
> able to constant fold load instructions where the argument is a constant.
> Second, we should be able to watch multiple PHI nodes through the loop; this
> patch only supports PHIs in loop headers, more can be done here.
>
> With this patch, we now constant evaluate:
> ?static const int arr[] = {1, 2, 3, 4, 5};
> ?int test() {
> ? ?int sum = 0;
> ? ?for (int i = 0; i < 5; ++i) sum += arr[i];
> ? ?return sum;
> ?}

[I'll test this myself this evening, but I thought this might be worth
asking/discussing]

What happens if you invoke UB in this code by, say, iterating past the
end of the array? Does SCEV act on this in any way, such as replacing
the whole block with unreachable? Would it be possible to produce a
diagnostic of some kind? (I realize once LLVM's doing codegen it's a
bit late for front ends, but I don't know if there are any hooks for
such functionality)

- David


From nlewycky at google.com  Mon Oct 24 13:29:04 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Mon, 24 Oct 2011 11:29:04 -0700
Subject: [llvm-commits] [llvm] r142731 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
In-Reply-To: <4EA42164.8040509@free.fr>
References: <20111022195820.621CC2A6C12C@llvm.org> <4EA42164.8040509@free.fr>
Message-ID: <CADbEz-iYBk6zegG3rc19n7KdJjNPc5fTkocvrQjDeCuKBpDkMw@mail.gmail.com>

On 23 October 2011 07:15, Duncan Sands <baldrick at free.fr> wrote:

> Hi Nick,
>
> > -  if (const CmpInst *CI = dyn_cast<CmpInst>(I))
> > +  if (CmpInst *CI = dyn_cast<CmpInst>(I))
> >       return ConstantFoldCompareInstOperands(CI->getPredicate(),
> Operands[0],
> >                                              Operands[1], TD);
> > +  if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
> > +    if (!LI->isVolatile())
> > +      return ConstantFoldLoadFromConstPtr(Operands[0], TD);
> > +  }
> >     return ConstantFoldInstOperands(I->getOpcode(), I->getType(),
> Operands, TD);
>
> maybe you could use instsimplify here?  It does constant folding and more
> besides.  It can break LCSSA form, so y so,
> check out the loop transform users of instsimplify to seou may need to
> check for that (ife how).


As far as I can see, LCSSA isn't documented and I don't understand it well
enough to know whether I'm preserving it or breaking it etc. I know it
involves creating 1-operand PHI nodes in strategic places and that's about
it.

Are there cases where InstructionSimplify will return a Constant that the
constant folder won't? This code is entirely based off of a mapping to
Constant*, so instsimplify won't help without more refactoring.

That refactoring would be scary because while we can represent the arbitrary
values, we'll find ourselves effectively unrolling the loop as we build up a
larger and larger SCEV expression. I'd like to leave unrolling to the
unrolling pass.

Nick

> @@ -4993,7 +5109,10 @@
> >             if (const CmpInst *CI = dyn_cast<CmpInst>(I))
> >               C = ConstantFoldCompareInstOperands(CI->getPredicate(),
> >                                                   Operands[0],
> Operands[1], TD);
> > -          else
> > +          else if (const LoadInst *LI = dyn_cast<LoadInst>(I)) {
> > +            if (!LI->isVolatile())
> > +              C = ConstantFoldLoadFromConstPtr(Operands[0], TD);
> > +          } else
> >               C = ConstantFoldInstOperands(I->getOpcode(), I->getType(),
> >                                            Operands, TD);
> >             if (!C) return V;
>
> Likewise.
>
> Ciao, Duncan.
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From dberlin at dberlin.org  Mon Oct 24 13:35:36 2011
From: dberlin at dberlin.org (Daniel Berlin)
Date: Mon, 24 Oct 2011 14:35:36 -0400
Subject: [llvm-commits] [llvm] r142731 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
In-Reply-To: <CADbEz-iYBk6zegG3rc19n7KdJjNPc5fTkocvrQjDeCuKBpDkMw@mail.gmail.com>
References: <20111022195820.621CC2A6C12C@llvm.org> <4EA42164.8040509@free.fr>
	<CADbEz-iYBk6zegG3rc19n7KdJjNPc5fTkocvrQjDeCuKBpDkMw@mail.gmail.com>
Message-ID: <CAF4BwTU8t-k=v=rJXVGxPtWJkTS7eaGie49OYEwsa_vVe+5vaw@mail.gmail.com>

On Mon, Oct 24, 2011 at 2:29 PM, Nick Lewycky <nlewycky at google.com> wrote:
> On 23 October 2011 07:15, Duncan Sands <baldrick at free.fr> wrote:
>>
>> Hi Nick,
>>
>> > - ?if (const CmpInst *CI = dyn_cast<CmpInst>(I))
>> > + ?if (CmpInst *CI = dyn_cast<CmpInst>(I))
>> > ? ? ? return ConstantFoldCompareInstOperands(CI->getPredicate(),
>> > Operands[0],
>> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Operands[1], TD);
>> > + ?if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
>> > + ? ?if (!LI->isVolatile())
>> > + ? ? ?return ConstantFoldLoadFromConstPtr(Operands[0], TD);
>> > + ?}
>> > ? ? return ConstantFoldInstOperands(I->getOpcode(), I->getType(),
>> > Operands, TD);
>>
>> maybe you could use instsimplify here? ?It does constant folding and more
>> besides. ?It can break LCSSA form, so y so,
>> check out the loop transform users of instsimplify to seou may need to
>> check for that (ife how).
>
> As far as I can see, LCSSA isn't documented and I don't understand it well
> enough to know whether I'm preserving it or breaking it etc. I know it
> involves creating 1-operand PHI nodes in strategic places and that's about
> it.
I'll paraphrase what i helped write for the GCC web page on this:
Loop closed SSA is simple:

No SSA name defined inside a loop is used outside of it.
In order to make this true, phi nodes are created at loop exits for
names defined inside the loop, but used later outside the loop.

The reason for doing this are three fold
1. A lot of optimizations are interested in exactly these values (For
example, these are exactly the values you may be able to replace with
new constant expressions)
2. IV analysis can talk about a name and you don't have to worry about
which loop they are talking about, it's always a single loop
3. it makes loop opts easier, because the set of nodes you have to
modify is contained quite nicely (otherwise, any loop opt that needs
to update uses may have to update nodes all throughout the function)


From eli.friedman at gmail.com  Mon Oct 24 13:43:12 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 24 Oct 2011 11:43:12 -0700
Subject: [llvm-commits] [llvm] r142731 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
In-Reply-To: <CADbEz-iYBk6zegG3rc19n7KdJjNPc5fTkocvrQjDeCuKBpDkMw@mail.gmail.com>
References: <20111022195820.621CC2A6C12C@llvm.org> <4EA42164.8040509@free.fr>
	<CADbEz-iYBk6zegG3rc19n7KdJjNPc5fTkocvrQjDeCuKBpDkMw@mail.gmail.com>
Message-ID: <CAJdarcGpRyZ3wpvwP4QDG-Dok24niPvEw2DG+nb1NGG-cQ3k4A@mail.gmail.com>

On Mon, Oct 24, 2011 at 11:29 AM, Nick Lewycky <nlewycky at google.com> wrote:
> On 23 October 2011 07:15, Duncan Sands <baldrick at free.fr> wrote:
>>
>> Hi Nick,
>>
>> > - ?if (const CmpInst *CI = dyn_cast<CmpInst>(I))
>> > + ?if (CmpInst *CI = dyn_cast<CmpInst>(I))
>> > ? ? ? return ConstantFoldCompareInstOperands(CI->getPredicate(),
>> > Operands[0],
>> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Operands[1], TD);
>> > + ?if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
>> > + ? ?if (!LI->isVolatile())
>> > + ? ? ?return ConstantFoldLoadFromConstPtr(Operands[0], TD);
>> > + ?}
>> > ? ? return ConstantFoldInstOperands(I->getOpcode(), I->getType(),
>> > Operands, TD);
>>
>> maybe you could use instsimplify here? ?It does constant folding and more
>> besides. ?It can break LCSSA form, so y so,
>> check out the loop transform users of instsimplify to seou may need to
>> check for that (ife how).
>
> As far as I can see, LCSSA isn't documented and I don't understand it well
> enough to know whether I'm preserving it or breaking it etc. I know it
> involves creating 1-operand PHI nodes in strategic places and that's about
> it.

>From LCSSA.cpp:

// This pass transforms loops by placing phi nodes at the end of the loops for
// all values that are live across the loop boundary.  For example, it turns
// the left into the right code:
//
// for (...)                for (...)
//   if (c)                   if (c)
//     X1 = ...                 X1 = ...
//   else                     else
//     X2 = ...                 X2 = ...
//   X3 = phi(X1, X2)         X3 = phi(X1, X2)
// ... = X3 + 4             X4 = phi(X3)
//                          ... = X4 + 4
//
// This is still valid LLVM; the extra phi nodes are purely redundant, and will
// be trivially eliminated by InstCombine.  The major benefit of this
// transformation is that it makes many other loop optimizations, such as
// LoopUnswitching, simpler.

> Are there cases where InstructionSimplify will return a Constant that the
> constant folder won't? This code is entirely based off of a mapping to
> Constant*, so instsimplify won't help without more refactoring.
> That refactoring would be scary because while we can represent the arbitrary
> values, we'll find ourselves effectively unrolling the loop as we build up a
> larger and larger SCEV expression. I'd like to leave unrolling to the
> unrolling pass.

Well, sure, you don't want to SCEV an expression if the representation
isn't useful... that said, it seems like you only care that the
returned value is loop-invariant.

-Eli


From eli.friedman at gmail.com  Mon Oct 24 14:07:19 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 24 Oct 2011 12:07:19 -0700
Subject: [llvm-commits] [llvm] r142731 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
In-Reply-To: <20111022195820.621CC2A6C12C@llvm.org>
References: <20111022195820.621CC2A6C12C@llvm.org>
Message-ID: <CAJdarcG8a1TdptrY+6HtFNdGwbaAt7TZQz3bPx-FMV23YRXPbw@mail.gmail.com>

On Sat, Oct 22, 2011 at 12:58 PM, Nick Lewycky <nicholas at mxc.ca> wrote:
> Author: nicholas
> Date: Sat Oct 22 14:58:20 2011
> New Revision: 142731
>
> URL: http://llvm.org/viewvc/llvm-project?rev=142731&view=rev
> Log:
> Make SCEV's brute force analysis stronger in two ways. Firstly, we should be
> able to constant fold load instructions where the argument is a constant.
> Second, we should be able to watch multiple PHI nodes through the loop; this
> patch only supports PHIs in loop headers, more can be done here.
>
> With this patch, we now constant evaluate:
> ?static const int arr[] = {1, 2, 3, 4, 5};
> ?int test() {
> ? ?int sum = 0;
> ? ?for (int i = 0; i < 5; ++i) sum += arr[i];
> ? ?return sum;
> ?}

This commit is causing a miscompile on
gcc.c-torture/execute/20030105-1.c (and possibly a couple other
tests).

-Eli

> Added:
> ? ?llvm/trunk/test/Analysis/ScalarEvolution/load.ll
> Modified:
> ? ?llvm/trunk/lib/Analysis/ScalarEvolution.cpp
>
> Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=142731&r1=142730&r2=142731&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
> +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Sat Oct 22 14:58:20 2011
> @@ -4658,7 +4658,8 @@
> ?/// specified type, assuming that all operands were constants.
> ?static bool CanConstantFold(const Instruction *I) {
> ? if (isa<BinaryOperator>(I) || isa<CmpInst>(I) ||
> - ? ? ?isa<SelectInst>(I) || isa<CastInst>(I) || isa<GetElementPtrInst>(I))
> + ? ? ?isa<SelectInst>(I) || isa<CastInst>(I) || isa<GetElementPtrInst>(I) ||
> + ? ? ?isa<LoadInst>(I))
> ? ? return true;
>
> ? if (const CallInst *CI = dyn_cast<CallInst>(I))
> @@ -4751,13 +4752,19 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const TargetData *TD) {
> ? // Convenient constant check, but redundant for recursive calls.
> ? if (Constant *C = dyn_cast<Constant>(V)) return C;
> + ?Instruction *I = dyn_cast<Instruction>(V);
> + ?if (!I) return 0;
>
> - ?Instruction *I = cast<Instruction>(V);
> ? if (Constant *C = Vals.lookup(I)) return C;
>
> - ?assert(!isa<PHINode>(I) && "loop header phis should be mapped to constant");
> - ?assert(canConstantEvolve(I, L) && "cannot evaluate expression in this loop");
> - ?(void)L;
> + ?// An instruction inside the loop depends on a value outside the loop that we
> + ?// weren't given a mapping for, or a value such as a call inside the loop.
> + ?if (!canConstantEvolve(I, L)) return 0;
> +
> + ?// An unmapped PHI can be due to a branch or another loop inside this loop,
> + ?// or due to this not being the initial iteration through a loop where we
> + ?// couldn't compute the evolution of this particular PHI last time.
> + ?if (isa<PHINode>(I)) return 0;
>
> ? std::vector<Constant*> Operands(I->getNumOperands());
>
> @@ -4774,9 +4781,13 @@
> ? ? Operands[i] = C;
> ? }
>
> - ?if (const CmpInst *CI = dyn_cast<CmpInst>(I))
> + ?if (CmpInst *CI = dyn_cast<CmpInst>(I))
> ? ? return ConstantFoldCompareInstOperands(CI->getPredicate(), Operands[0],
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Operands[1], TD);
> + ?if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
> + ? ?if (!LI->isVolatile())
> + ? ? ?return ConstantFoldLoadFromConstPtr(Operands[0], TD);
> + ?}
> ? return ConstantFoldInstOperands(I->getOpcode(), I->getType(), Operands, TD);
> ?}
>
> @@ -4798,23 +4809,26 @@
>
> ? Constant *&RetVal = ConstantEvolutionLoopExitValue[PN];
>
> - ?// FIXME: Nick's fix for PR11034 will seed constants for multiple header phis.
> ? DenseMap<Instruction *, Constant *> CurrentIterVals;
> + ?BasicBlock *Header = L->getHeader();
> + ?assert(PN->getParent() == Header && "Can't evaluate PHI not in loop header!");
>
> ? // Since the loop is canonicalized, the PHI node must have two entries. ?One
> ? // entry must be a constant (coming in from outside of the loop), and the
> ? // second must be derived from the same PHI.
> ? bool SecondIsBackedge = L->contains(PN->getIncomingBlock(1));
> - ?Constant *StartCST =
> - ? ?dyn_cast<Constant>(PN->getIncomingValue(!SecondIsBackedge));
> - ?if (StartCST == 0)
> - ? ?return RetVal = 0; ?// Must be a constant.
> - ?CurrentIterVals[PN] = StartCST;
> + ?PHINode *PHI = 0;
> + ?for (BasicBlock::iterator I = Header->begin();
> + ? ? ? (PHI = dyn_cast<PHINode>(I)); ++I) {
> + ? ?Constant *StartCST =
> + ? ? ?dyn_cast<Constant>(PHI->getIncomingValue(!SecondIsBackedge));
> + ? ?if (StartCST == 0) continue;
> + ? ?CurrentIterVals[PHI] = StartCST;
> + ?}
> + ?if (!CurrentIterVals.count(PN))
> + ? ?return RetVal = 0;
>
> ? Value *BEValue = PN->getIncomingValue(SecondIsBackedge);
> - ?if (getConstantEvolvingPHI(BEValue, L) != PN &&
> - ? ? ?!isa<Constant>(BEValue))
> - ? ?return RetVal = 0; ?// Not derived from same PHI.
>
> ? // Execute the loop symbolically to determine the exit value.
> ? if (BEs.getActiveBits() >= 32)
> @@ -4826,15 +4840,29 @@
> ? ? if (IterationNum == NumIterations)
> ? ? ? return RetVal = CurrentIterVals[PN]; ?// Got exit value!
>
> - ? ?// Compute the value of the PHI node for the next iteration.
> + ? ?// Compute the value of the PHIs for the next iteration.
> ? ? // EvaluateExpression adds non-phi values to the CurrentIterVals map.
> + ? ?DenseMap<Instruction *, Constant *> NextIterVals;
> ? ? Constant *NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
> ? ? if (NextPHI == CurrentIterVals[PN])
> ? ? ? return RetVal = NextPHI; ?// Stopped evolving!
> ? ? if (NextPHI == 0)
> ? ? ? return 0; ? ? ? ?// Couldn't evaluate!
> - ? ?DenseMap<Instruction *, Constant *> NextIterVals;
> ? ? NextIterVals[PN] = NextPHI;
> +
> + ? ?// Also evaluate the other PHI nodes. ?However, we don't get to stop if we
> + ? ?// cease to be able to evaluate one of them or if they stop evolving,
> + ? ?// because that doesn't necessarily prevent us from computing PN.
> + ? ?for (DenseMap<Instruction *, Constant *>::const_iterator
> + ? ? ? ? ? I = CurrentIterVals.begin(), E = CurrentIterVals.end(); I != E; ++I){
> + ? ? ?PHINode *PHI = dyn_cast<PHINode>(I->first);
> + ? ? ?if (!PHI || PHI == PN) continue;
> + ? ? ?Constant *&NextPHI = NextIterVals[PHI];
> + ? ? ?if (NextPHI) continue; ? ?// Already computed!
> +
> + ? ? ?Value *BEValue = PHI->getIncomingValue(SecondIsBackedge);
> + ? ? ?NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
> + ? ?}
> ? ? CurrentIterVals.swap(NextIterVals);
> ? }
> ?}
> @@ -4844,9 +4872,9 @@
> ?/// try to evaluate a few iterations of the loop until we get the exit
> ?/// condition gets a value of ExitWhen (true or false). ?If we cannot
> ?/// evaluate the trip count of the loop, return getCouldNotCompute().
> -const SCEV * ScalarEvolution::ComputeExitCountExhaustively(const Loop *L,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Value *Cond,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool ExitWhen) {
> +const SCEV *ScalarEvolution::ComputeExitCountExhaustively(const Loop *L,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Value *Cond,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool ExitWhen) {
> ? PHINode *PN = getConstantEvolvingPHI(Cond, L);
> ? if (PN == 0) return getCouldNotCompute();
>
> @@ -4921,6 +4949,98 @@
> ? return C;
> ?}
>
> +/// This builds up a Constant using the ConstantExpr interface. ?That way, we
> +/// will return Constants for objects which aren't represented by a
> +/// SCEVConstant, because SCEVConstant is restricted to ConstantInt.
> +/// Returns NULL if the SCEV isn't representable as a Constant.
> +static Constant *BuildConstantFromSCEV(const SCEV *V) {
> + ?switch (V->getSCEVType()) {
> + ? ?default: ?// TODO: smax, umax.
> + ? ?case scCouldNotCompute:
> + ? ?case scAddRecExpr:
> + ? ? ?break;
> + ? ?case scConstant:
> + ? ? ?return cast<SCEVConstant>(V)->getValue();
> + ? ?case scUnknown:
> + ? ? ?return dyn_cast<Constant>(cast<SCEVUnknown>(V)->getValue());
> + ? ?case scSignExtend: {
> + ? ? ?const SCEVSignExtendExpr *SS = cast<SCEVSignExtendExpr>(V);
> + ? ? ?if (Constant *CastOp = BuildConstantFromSCEV(SS->getOperand()))
> + ? ? ? ?return ConstantExpr::getSExt(CastOp, SS->getType());
> + ? ? ?break;
> + ? ?}
> + ? ?case scZeroExtend: {
> + ? ? ?const SCEVZeroExtendExpr *SZ = cast<SCEVZeroExtendExpr>(V);
> + ? ? ?if (Constant *CastOp = BuildConstantFromSCEV(SZ->getOperand()))
> + ? ? ? ?return ConstantExpr::getZExt(CastOp, SZ->getType());
> + ? ? ?break;
> + ? ?}
> + ? ?case scTruncate: {
> + ? ? ?const SCEVTruncateExpr *ST = cast<SCEVTruncateExpr>(V);
> + ? ? ?if (Constant *CastOp = BuildConstantFromSCEV(ST->getOperand()))
> + ? ? ? ?return ConstantExpr::getTrunc(CastOp, ST->getType());
> + ? ? ?break;
> + ? ?}
> + ? ?case scAddExpr: {
> + ? ? ?const SCEVAddExpr *SA = cast<SCEVAddExpr>(V);
> + ? ? ?if (Constant *C = BuildConstantFromSCEV(SA->getOperand(0))) {
> + ? ? ? ?if (C->getType()->isPointerTy())
> + ? ? ? ? ?C = ConstantExpr::getBitCast(C, Type::getInt8PtrTy(C->getContext()));
> + ? ? ? ?for (unsigned i = 1, e = SA->getNumOperands(); i != e; ++i) {
> + ? ? ? ? ?Constant *C2 = BuildConstantFromSCEV(SA->getOperand(i));
> + ? ? ? ? ?if (!C2) return 0;
> +
> + ? ? ? ? ?// First pointer!
> + ? ? ? ? ?if (!C->getType()->isPointerTy() && C2->getType()->isPointerTy()) {
> + ? ? ? ? ? ?std::swap(C, C2);
> + ? ? ? ? ? ?// The offsets have been converted to bytes. ?We can add bytes to an
> + ? ? ? ? ? ?// i8* by GEP with the byte count in the first index.
> + ? ? ? ? ? ?C = ConstantExpr::getBitCast(C,Type::getInt8PtrTy(C->getContext()));
> + ? ? ? ? ?}
> +
> + ? ? ? ? ?// Don't bother trying to sum two pointers. We probably can't
> + ? ? ? ? ?// statically compute a load that results from it anyway.
> + ? ? ? ? ?if (C2->getType()->isPointerTy())
> + ? ? ? ? ? ?return 0;
> +
> + ? ? ? ? ?if (C->getType()->isPointerTy()) {
> + ? ? ? ? ? ?if (cast<PointerType>(C->getType())->getElementType()->isStructTy())
> + ? ? ? ? ? ? ?C2 = ConstantExpr::getIntegerCast(
> + ? ? ? ? ? ? ? ? ?C2, Type::getInt32Ty(C->getContext()), true);
> + ? ? ? ? ? ?C = ConstantExpr::getGetElementPtr(C, C2);
> + ? ? ? ? ?} else
> + ? ? ? ? ? ?C = ConstantExpr::getAdd(C, C2);
> + ? ? ? ?}
> + ? ? ? ?return C;
> + ? ? ?}
> + ? ? ?break;
> + ? ?}
> + ? ?case scMulExpr: {
> + ? ? ?const SCEVMulExpr *SM = cast<SCEVMulExpr>(V);
> + ? ? ?if (Constant *C = BuildConstantFromSCEV(SM->getOperand(0))) {
> + ? ? ? ?// Don't bother with pointers at all.
> + ? ? ? ?if (C->getType()->isPointerTy()) return 0;
> + ? ? ? ?for (unsigned i = 1, e = SM->getNumOperands(); i != e; ++i) {
> + ? ? ? ? ?Constant *C2 = BuildConstantFromSCEV(SM->getOperand(i));
> + ? ? ? ? ?if (!C2 || C2->getType()->isPointerTy()) return 0;
> + ? ? ? ? ?C = ConstantExpr::getMul(C, C2);
> + ? ? ? ?}
> + ? ? ? ?return C;
> + ? ? ?}
> + ? ? ?break;
> + ? ?}
> + ? ?case scUDivExpr: {
> + ? ? ?const SCEVUDivExpr *SU = cast<SCEVUDivExpr>(V);
> + ? ? ?if (Constant *LHS = BuildConstantFromSCEV(SU->getLHS()))
> + ? ? ? ?if (Constant *RHS = BuildConstantFromSCEV(SU->getRHS()))
> + ? ? ? ? ?if (LHS->getType() == RHS->getType())
> + ? ? ? ? ? ?return ConstantExpr::getUDiv(LHS, RHS);
> + ? ? ?break;
> + ? ?}
> + ?}
> + ?return 0;
> +}
> +
> ?const SCEV *ScalarEvolution::computeSCEVAtScope(const SCEV *V, const Loop *L) {
> ? if (isa<SCEVConstant>(V)) return V;
>
> @@ -4973,11 +5093,7 @@
> ? ? ? ? ? const SCEV *OpV = getSCEVAtScope(OrigV, L);
> ? ? ? ? ? MadeImprovement |= OrigV != OpV;
>
> - ? ? ? ? ?Constant *C = 0;
> - ? ? ? ? ?if (const SCEVConstant *SC = dyn_cast<SCEVConstant>(OpV))
> - ? ? ? ? ? ?C = SC->getValue();
> - ? ? ? ? ?if (const SCEVUnknown *SU = dyn_cast<SCEVUnknown>(OpV))
> - ? ? ? ? ? ?C = dyn_cast<Constant>(SU->getValue());
> + ? ? ? ? ?Constant *C = BuildConstantFromSCEV(OpV);
> ? ? ? ? ? if (!C) return V;
> ? ? ? ? ? if (C->getType() != Op->getType())
> ? ? ? ? ? ? C = ConstantExpr::getCast(CastInst::getCastOpcode(C, false,
> @@ -4993,7 +5109,10 @@
> ? ? ? ? ? if (const CmpInst *CI = dyn_cast<CmpInst>(I))
> ? ? ? ? ? ? C = ConstantFoldCompareInstOperands(CI->getPredicate(),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Operands[0], Operands[1], TD);
> - ? ? ? ? ?else
> + ? ? ? ? ?else if (const LoadInst *LI = dyn_cast<LoadInst>(I)) {
> + ? ? ? ? ? ?if (!LI->isVolatile())
> + ? ? ? ? ? ? ?C = ConstantFoldLoadFromConstPtr(Operands[0], TD);
> + ? ? ? ? ?} else
> ? ? ? ? ? ? C = ConstantFoldInstOperands(I->getOpcode(), I->getType(),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Operands, TD);
> ? ? ? ? ? if (!C) return V;
>
> Added: llvm/trunk/test/Analysis/ScalarEvolution/load.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/load.ll?rev=142731&view=auto
> ==============================================================================
> --- llvm/trunk/test/Analysis/ScalarEvolution/load.ll (added)
> +++ llvm/trunk/test/Analysis/ScalarEvolution/load.ll Sat Oct 22 14:58:20 2011
> @@ -0,0 +1,33 @@
> +; RUN: opt -analyze -scalar-evolution < %s 2>&1 | FileCheck %s
> +; PR11034
> +
> +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
> +target triple = "i386-pc-linux-gnu"
> +
> + at arr1 = internal unnamed_addr constant [50 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50], align 4
> + at arr2 = internal unnamed_addr constant [50 x i32] [i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0], align 4
> +
> +define i32 @test1() nounwind readnone {
> +; CHECK: test1
> +entry:
> + ?br label %for.body
> +
> +for.body: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ; preds = %entry, %for.body
> + ?%sum.04 = phi i32 [ 0, %entry ], [ %add2, %for.body ]
> +; CHECK: --> ?%sum.04{{ *}}Exits: 2450
> + ?%i.03 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
> + ?%arrayidx = getelementptr inbounds [50 x i32]* @arr1, i32 0, i32 %i.03
> + ?%0 = load i32* %arrayidx, align 4
> +; CHECK: --> ?%0{{ *}}Exits: 50
> + ?%arrayidx1 = getelementptr inbounds [50 x i32]* @arr2, i32 0, i32 %i.03
> + ?%1 = load i32* %arrayidx1, align 4
> +; CHECK: --> ?%1{{ *}}Exits: 0
> + ?%add = add i32 %0, %sum.04
> + ?%add2 = add i32 %add, %1
> + ?%inc = add nsw i32 %i.03, 1
> + ?%cmp = icmp eq i32 %inc, 50
> + ?br i1 %cmp, label %for.end, label %for.body
> +
> +for.end: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?; preds = %for.body
> + ?ret i32 %add2
> +}
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From stpworld at narod.ru  Mon Oct 24 14:36:49 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Mon, 24 Oct 2011 23:36:49 +0400
Subject: [llvm-commits] [LLVM, llvm-nm,
 arm] Fix for nm-trivial-object.test and for nm-archive.test
In-Reply-To: <4EA514A1.3020109@narod.ru>
References: <4EA1BF05.7030307@narod.ru>
	<CACXTSinHzMOEUhDi2nJ17ZFs54zwX5WuNbpQgh+Qrw=scVTeow@mail.gmail.com>
	<4EA514A1.3020109@narod.ru>
Message-ID: <4EA5BE51.7040105@narod.ru>

Hi all. Please find the reworked patch in attachment.

Regards,
Stepan.

Stepan Dyatkovskiy wrote:
> Hi,
> Yes, you right. Sorry, I actually mean clang-native-arm-cortex-a9:
> http://lab.llvm.org:8011/builders/clang-native-arm-cortex-a9/builds/155
>
> Regards,
> Stepan.
>
> Michael Spencer wrote:
>> On Fri, Oct 21, 2011 at 11:50 AM, Stepan Dyatkovskiy<stpworld at narod.ru>   wrote:
>>> Hi all,
>>> Please find the patch for review that fixes nm-trivial-object.test and
>>> nm-archive.test for arm architecture.
>>>
>>> Regards,
>>> Stepan
>>
>> These tests are currently passing on the llvm-arm-linux buildbot.
>> Where are you encountering the failure?
>>
>> This does, however, show that the code is currently wrong. It's trying
>> to print a uint64_t as an unsigned. The code needs to use the address
>> size from the object file to print either 8 byte or 4 byte addresses
>> and sizes using the correct format string.
>>
>> Thanks for bringing this up!
>>
>> - Michael Spencer
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From respindola at mozilla.com  Mon Oct 24 15:02:27 2011
From: respindola at mozilla.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Mon, 24 Oct 2011 16:02:27 -0400
Subject: [llvm-commits] [patch][pr11202] Handle BB with address taken being
 deleted from codegen
Message-ID: <4EA5C453.5050203@mozilla.com>

We currently handle the following cases when removing a BB that has its 
address taken

* An IL pass is deleting it, and no references to it were emitted so 
far. In this case replaceAllUsesWith takes care of everything.
* An IL pass is deleting it, but a reference to it was already emitted. 
When emitting the reference we created a CallbackVH, so now we get 
notified about the deleting and remember to produce a dummy label for it .

The case we are not handling in this bug is a BB that is referenced from 
another function or global variable being remove by a codegen pass. 
There are two problems

* replaceAllUsesWith will not work once we are in Codegen, so we will 
need to use dummy labels for both cases.
* MachineBasicBlock are not Values, so we cannot use CallbackVH.

What this patch does is add a method to MMI that Codegen can use to 
record that a MBB is being deleted. This is handled almost the same way 
we handle and IL BB being deleted, but we have to keep the hash table 
entry since the IL level BB will not be delete and can still be in use.

Cheers,
Rafael
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From daniel at zuster.org  Mon Oct 24 15:15:10 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 24 Oct 2011 13:15:10 -0700
Subject: [llvm-commits] [llvm] r142456 - in /llvm/trunk/projects/sample:
 ./ autoconf/ autoconf/m4/
In-Reply-To: <4EA085D8.9000300@illinois.edu>
References: <20111018231048.C544A3128034@llvm.org>
	<CA+Ov9+kZ_x_LFyN0BXq49y2c9ZaWw2jOwkSBe-Nz_Qz_X=f6+Q@mail.gmail.com>
	<CAEU8z68Q8FtaZNP4B8ML26v+fC1w7T+2oVnYjuie8=YGw5KWaw@mail.gmail.com>
	<4EA085D8.9000300@illinois.edu>
Message-ID: <CAEU8z68A+WxOQ+Rd21W0mjaebEJv+o_XAzeaQWRoH96kbqc4fQ@mail.gmail.com>

On Thu, Oct 20, 2011 at 1:34 PM, John Criswell <criswell at illinois.edu> wrote:
> On 10/20/11 2:52 PM, Daniel Dunbar wrote:
>>
>> On Tue, Oct 18, 2011 at 11:11 PM, Anton Korobeynikov
>> <anton at korobeynikov.info> ?wrote:

<snip>
>
> It seems that both LLVM projects and LLVM itself have a lot of overlap in
> what their build systems need to do (compiling code, creating linked
> libraries, getting the compile flags right to find LLVM header files, etc.).
> ?Perhaps this is the code duplication issue to which Anton refers.

For the most part, you just described "software projects" in general.
Yes, software needs to be built and linked. That doesn't mean that the
primary LLVM project is the right place to design some kind of general
configure/make solution for the world.

I am fine supplying something for users to easily get started with,
but I hate having my hands tied when it comes to working on the LLVM
build because we coupled supplying a solution for users with our build
system.

In general, I think LLVM as a project and LLVM as a set of libraries
have very different problems that make it unlikely they have the same
requirements for a build system:
(a) LLVM is huge, and like many huge projects, has lots of problems
and complexity due to that. Few projects that use LLVM will be
anywhere close it LLVM's size.
(b) LLVM's design for flexible use as a client library has all kinds
of complexity, almost none of which our clients have use for (unless
they themselves are also trying to build as an interconnected set of
libraries -- highly unlikely).
(c) LLVM is a compiler infrastructure, and has associated important
interesting use cases for a build system (self-hosting,
cross-compiling). Clients not building compilers will be unlikely to
care as much about these things.
(d) LLVM is supposed to be highly portable. Clients may or may not
want this, but those who don't aren't likely to care as much about
properly modeling various configuration checks, etc.

>>
>> For example, realistic projects using LLVM would be much better served
>> by having a configuration that is pre-setup to support targeting
>> different versions of LLVM. This is incredibly useful and something we
>> hacked together in KLEE, but would make more sense to be part of the
>> standard template. Obviously, however, that kind of code has no
>> relevance to LLVM TOT.
>
> Trying to have a single code base support multiple versions of LLVM seems
> painful and, for analysis passes especially, nearly futile (it seems that
> analysis passes have to use the internal LLVM API directly, which is as
> fluid as water between releases). ?I'm actually not interested in that
> feature. ?Is anyone else?

Yes, it is painful, and yes it is very important to some projects. It
is incredibly useful for a number of reasons:
(a) allows testing vs newer versions of LLVM risk free,
(b) important for research projects (like KLEE) where different users
end up having more software built on top of the code and are focused
on their research, not tracking LLVM. Different groups can easily be
at different points in a publication cycle, one group may want a new
LLVM, the other may want as much stability as possible.

> Having said all that, perhaps the old projects system was over-engineered,
> and that over-engineering is flooding over into the current line of
> thinking. ?IIRC, the only reason why the Projects system was so complicated
> was because we wanted to let LLVM projects place their source trees and
> object there whereever they wanted. ?If we take that feature away and
> require that all projects be checked out into llvm/projects, then all a
> project needs to do to use LLVM's build system is to set the LEVEL variable
> appropriately and include Makefile.common, correct? ?The LLVM build system
> loses the cruft, and projects can still use the LLVM build system. ?Projects
> can still have configure scripts and specialized build rules for things not
> handled by LLVM's configure script and Makefiles.
>
> This would eliminate cruft *and* prevent code duplication all in a single
> step.

I don't think you understand what I want to do. I want to be able to
change the LLVM build infrastructure without having to worry about it
breaking some piece of compatibility in external projects.
autoconf/make are just a terrible system to treat as "API". I don't
think any system that tries to reuse the LLVM build setup for an
external project is a good idea.

>From my perspective, aside from the historical reasons, there are very
few *pro* reasons to share the build system:

(a) code duplication is not an issue. Very little of the complexity of
the LLVM autoconf/Make system should actually end up being duplicated
in the sample project. It is just done that way currently no because
there is no way to know what users are depending on (see terrible
system to treat as "API"). Conversely, most of the code to deal with
external projects can be eliminated from the LLVM makefiles once the
dependency is broken.

(b) code improvement (ensuring projects benefit from incremental
development) is not really an issue. We rarely improve the build
system, upcoming improvements are much more likely to only be
interesting to the LLVM project, and it is incredibly hard to make
changes without breaking the "API". Since the solution was supposed to
be a "quick start" one, this is not a good tradeoff.

(c) differing requirements: as enumerated above, I feel like LLVM the
project and LLVM as a library have very different use cases.

(d) inactive development. Even if duplication were an issue, in
practice the build system in its current form changes very little, so
the duplication causes little practical harm.

(e) Finally, I don't think LLVM's build system is that great. It would
be one thing if we had an amazing, very well architected, nicely
documented, super fast setup that we really felt other people would
benefit from. I don't think this is the case, the current setup is OK
and workable for LLVM but I don't think it is so good that other
projects should really use it as an example to follow.

My feelings based on the arguments above is that the current setup is
holding us back from making useful improvements for the LLVM project
and its developers, in exchange for very little in return.

 - Daniel

> If people want to place their source and object trees any place they want,
> then they can go through the hassle of building their on build system. ?That
> seems like a fair tradeoff.
>
> Thoughts?
>
> -- John T.
>
>>
>> ?- Daniel
>>
>>> --
>>> With best regards, Anton Korobeynikov
>>> Faculty of Mathematics and Mechanics, Saint Petersburg State University
>>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>


From resistor at mac.com  Mon Oct 24 15:19:18 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 24 Oct 2011 20:19:18 -0000
Subject: [llvm-commits] [llvm] r142840 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20111024201918.3971E312800A@llvm.org>

Author: resistor
Date: Mon Oct 24 15:19:18 2011
New Revision: 142840

URL: http://llvm.org/viewvc/llvm-project?rev=142840&view=rev
Log:
Stub out some of the MachO relocation decoding hooks.

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=142840&r1=142839&r2=142840&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Mon Oct 24 15:19:18 2011
@@ -641,6 +641,8 @@
 }
 error_code MachOObjectFile::getRelocationTypeName(DataRefImpl Rel,
                                           SmallVectorImpl<char> &Result) const {
+  StringRef res = "Unknown";
+  Result.append(res.begin(), res.end());
   return object_error::success;
 }
 error_code MachOObjectFile::getRelocationAdditionalInfo(DataRefImpl Rel,
@@ -666,6 +668,8 @@
 }
 error_code MachOObjectFile::getRelocationValueString(DataRefImpl Rel,
                                           SmallVectorImpl<char> &Result) const {
+  StringRef res = "Unknown";
+  Result.append(res.begin(), res.end());
   return object_error::success;
 }
 



From eli.friedman at gmail.com  Mon Oct 24 15:24:21 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 24 Oct 2011 20:24:21 -0000
Subject: [llvm-commits] [llvm] r142841 -
	/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
Message-ID: <20111024202421.8B328312800A@llvm.org>

Author: efriedma
Date: Mon Oct 24 15:24:21 2011
New Revision: 142841

URL: http://llvm.org/viewvc/llvm-project?rev=142841&view=rev
Log:
Add support to the old JIT for acquire/release loads and stores on x86.  PR11207.


Modified:
    llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp

Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=142841&r1=142840&r2=142841&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Mon Oct 24 15:24:21 2011
@@ -589,6 +589,13 @@
   }
 }
 
+static const MCInstrDesc *UpdateOp(MachineInstr &MI, const X86InstrInfo *II,
+                                   unsigned Opcode) {
+  const MCInstrDesc *Desc = &II->get(Opcode);
+  MI.setDesc(*Desc);
+  return Desc;
+}
+
 template<class CodeEmitter>
 void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
                                            const MCInstrDesc *Desc) {
@@ -596,15 +603,23 @@
   
   // If this is a pseudo instruction, lower it.
   switch (Desc->getOpcode()) {
-  case X86::ADD16rr_DB:   Desc = &II->get(X86::OR16rr); MI.setDesc(*Desc);break;
-  case X86::ADD32rr_DB:   Desc = &II->get(X86::OR32rr); MI.setDesc(*Desc);break;
-  case X86::ADD64rr_DB:   Desc = &II->get(X86::OR64rr); MI.setDesc(*Desc);break;
-  case X86::ADD16ri_DB:   Desc = &II->get(X86::OR16ri); MI.setDesc(*Desc);break;
-  case X86::ADD32ri_DB:   Desc = &II->get(X86::OR32ri); MI.setDesc(*Desc);break;
-  case X86::ADD64ri32_DB:Desc = &II->get(X86::OR64ri32);MI.setDesc(*Desc);break;
-  case X86::ADD16ri8_DB:  Desc = &II->get(X86::OR16ri8);MI.setDesc(*Desc);break;
-  case X86::ADD32ri8_DB:  Desc = &II->get(X86::OR32ri8);MI.setDesc(*Desc);break;
-  case X86::ADD64ri8_DB:  Desc = &II->get(X86::OR64ri8);MI.setDesc(*Desc);break;
+  case X86::ADD16rr_DB:      Desc = UpdateOp(MI, II, X86::OR16rr); break;
+  case X86::ADD32rr_DB:      Desc = UpdateOp(MI, II, X86::OR32rr); break;
+  case X86::ADD64rr_DB:      Desc = UpdateOp(MI, II, X86::OR64rr); break;
+  case X86::ADD16ri_DB:      Desc = UpdateOp(MI, II, X86::OR16ri); break;
+  case X86::ADD32ri_DB:      Desc = UpdateOp(MI, II, X86::OR32ri); break;
+  case X86::ADD64ri32_DB:    Desc = UpdateOp(MI, II, X86::OR64ri32); break;
+  case X86::ADD16ri8_DB:     Desc = UpdateOp(MI, II, X86::OR16ri8); break;
+  case X86::ADD32ri8_DB:     Desc = UpdateOp(MI, II, X86::OR32ri8); break;
+  case X86::ADD64ri8_DB:     Desc = UpdateOp(MI, II, X86::OR64ri8); break;
+  case X86::ACQUIRE_MOV8rm:  Desc = UpdateOp(MI, II, X86::MOV8rm); break;
+  case X86::ACQUIRE_MOV16rm: Desc = UpdateOp(MI, II, X86::MOV16rm); break;
+  case X86::ACQUIRE_MOV32rm: Desc = UpdateOp(MI, II, X86::MOV32rm); break;
+  case X86::ACQUIRE_MOV64rm: Desc = UpdateOp(MI, II, X86::MOV64rm); break;
+  case X86::RELEASE_MOV8mr:  Desc = UpdateOp(MI, II, X86::MOV8mr); break;
+  case X86::RELEASE_MOV16mr: Desc = UpdateOp(MI, II, X86::MOV16mr); break;
+  case X86::RELEASE_MOV32mr: Desc = UpdateOp(MI, II, X86::MOV32mr); break;
+  case X86::RELEASE_MOV64mr: Desc = UpdateOp(MI, II, X86::MOV64mr); break;
   }
   
 



From eli.friedman at gmail.com  Mon Oct 24 15:43:17 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 24 Oct 2011 13:43:17 -0700
Subject: [llvm-commits] [llvm] r142841 -
	/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
In-Reply-To: <20111024202421.8B328312800A@llvm.org>
References: <20111024202421.8B328312800A@llvm.org>
Message-ID: <CAJdarcE-Kz1abJSyOpVaKsheop4J4a77bUZ-LS6Zv2hxExNwcg@mail.gmail.com>

On Mon, Oct 24, 2011 at 1:24 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> Author: efriedma
> Date: Mon Oct 24 15:24:21 2011
> New Revision: 142841
>
> URL: http://llvm.org/viewvc/llvm-project?rev=142841&view=rev
> Log:
> Add support to the old JIT for acquire/release loads and stores on x86. ?PR11207.

Evan, is this okay for 3.0?

-Eli

> Modified:
> ? ?llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=142841&r1=142840&r2=142841&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Mon Oct 24 15:24:21 2011
> @@ -589,6 +589,13 @@
> ? }
> ?}
>
> +static const MCInstrDesc *UpdateOp(MachineInstr &MI, const X86InstrInfo *II,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned Opcode) {
> + ?const MCInstrDesc *Desc = &II->get(Opcode);
> + ?MI.setDesc(*Desc);
> + ?return Desc;
> +}
> +
> ?template<class CodeEmitter>
> ?void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCInstrDesc *Desc) {
> @@ -596,15 +603,23 @@
>
> ? // If this is a pseudo instruction, lower it.
> ? switch (Desc->getOpcode()) {
> - ?case X86::ADD16rr_DB: ? Desc = &II->get(X86::OR16rr); MI.setDesc(*Desc);break;
> - ?case X86::ADD32rr_DB: ? Desc = &II->get(X86::OR32rr); MI.setDesc(*Desc);break;
> - ?case X86::ADD64rr_DB: ? Desc = &II->get(X86::OR64rr); MI.setDesc(*Desc);break;
> - ?case X86::ADD16ri_DB: ? Desc = &II->get(X86::OR16ri); MI.setDesc(*Desc);break;
> - ?case X86::ADD32ri_DB: ? Desc = &II->get(X86::OR32ri); MI.setDesc(*Desc);break;
> - ?case X86::ADD64ri32_DB:Desc = &II->get(X86::OR64ri32);MI.setDesc(*Desc);break;
> - ?case X86::ADD16ri8_DB: ?Desc = &II->get(X86::OR16ri8);MI.setDesc(*Desc);break;
> - ?case X86::ADD32ri8_DB: ?Desc = &II->get(X86::OR32ri8);MI.setDesc(*Desc);break;
> - ?case X86::ADD64ri8_DB: ?Desc = &II->get(X86::OR64ri8);MI.setDesc(*Desc);break;
> + ?case X86::ADD16rr_DB: ? ? ?Desc = UpdateOp(MI, II, X86::OR16rr); break;
> + ?case X86::ADD32rr_DB: ? ? ?Desc = UpdateOp(MI, II, X86::OR32rr); break;
> + ?case X86::ADD64rr_DB: ? ? ?Desc = UpdateOp(MI, II, X86::OR64rr); break;
> + ?case X86::ADD16ri_DB: ? ? ?Desc = UpdateOp(MI, II, X86::OR16ri); break;
> + ?case X86::ADD32ri_DB: ? ? ?Desc = UpdateOp(MI, II, X86::OR32ri); break;
> + ?case X86::ADD64ri32_DB: ? ?Desc = UpdateOp(MI, II, X86::OR64ri32); break;
> + ?case X86::ADD16ri8_DB: ? ? Desc = UpdateOp(MI, II, X86::OR16ri8); break;
> + ?case X86::ADD32ri8_DB: ? ? Desc = UpdateOp(MI, II, X86::OR32ri8); break;
> + ?case X86::ADD64ri8_DB: ? ? Desc = UpdateOp(MI, II, X86::OR64ri8); break;
> + ?case X86::ACQUIRE_MOV8rm: ?Desc = UpdateOp(MI, II, X86::MOV8rm); break;
> + ?case X86::ACQUIRE_MOV16rm: Desc = UpdateOp(MI, II, X86::MOV16rm); break;
> + ?case X86::ACQUIRE_MOV32rm: Desc = UpdateOp(MI, II, X86::MOV32rm); break;
> + ?case X86::ACQUIRE_MOV64rm: Desc = UpdateOp(MI, II, X86::MOV64rm); break;
> + ?case X86::RELEASE_MOV8mr: ?Desc = UpdateOp(MI, II, X86::MOV8mr); break;
> + ?case X86::RELEASE_MOV16mr: Desc = UpdateOp(MI, II, X86::MOV16mr); break;
> + ?case X86::RELEASE_MOV32mr: Desc = UpdateOp(MI, II, X86::MOV32mr); break;
> + ?case X86::RELEASE_MOV64mr: Desc = UpdateOp(MI, II, X86::MOV64mr); break;
> ? }
>
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From eli.friedman at gmail.com  Mon Oct 24 15:44:16 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 24 Oct 2011 13:44:16 -0700
Subject: [llvm-commits] [llvm] r142841 -
	/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
In-Reply-To: <CAJdarcE-Kz1abJSyOpVaKsheop4J4a77bUZ-LS6Zv2hxExNwcg@mail.gmail.com>
References: <20111024202421.8B328312800A@llvm.org>
	<CAJdarcE-Kz1abJSyOpVaKsheop4J4a77bUZ-LS6Zv2hxExNwcg@mail.gmail.com>
Message-ID: <CAJdarcGXxpOGwMhpT3T0L9d_yf8X-XzFxg46ZyD_4T08_GVRZg@mail.gmail.com>

On Mon, Oct 24, 2011 at 1:43 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Mon, Oct 24, 2011 at 1:24 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
>> Author: efriedma
>> Date: Mon Oct 24 15:24:21 2011
>> New Revision: 142841
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=142841&view=rev
>> Log:
>> Add support to the old JIT for acquire/release loads and stores on x86. ?PR11207.
>
> Evan, is this okay for 3.0?

Nevermind; Bill already pulled it in.

-Eli


From nicholas at mxc.ca  Mon Oct 24 16:02:39 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 24 Oct 2011 21:02:39 -0000
Subject: [llvm-commits] [llvm] r142843 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp
 test/Analysis/ScalarEvolution/trip-count11.ll
Message-ID: <20111024210239.2B4F4312800A@llvm.org>

Author: nicholas
Date: Mon Oct 24 16:02:38 2011
New Revision: 142843

URL: http://llvm.org/viewvc/llvm-project?rev=142843&view=rev
Log:
Now that we look at all the header PHIs, we need to consider all the header PHIs
when deciding that the loop has stopped evolving. Fixes miscompile in the gcc
torture testsuite!

Added:
    llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll
Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=142843&r1=142842&r2=142843&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Oct 24 16:02:38 2011
@@ -4844,12 +4844,12 @@
     // EvaluateExpression adds non-phi values to the CurrentIterVals map.
     DenseMap<Instruction *, Constant *> NextIterVals;
     Constant *NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
-    if (NextPHI == CurrentIterVals[PN])
-      return RetVal = NextPHI;  // Stopped evolving!
     if (NextPHI == 0)
       return 0;        // Couldn't evaluate!
     NextIterVals[PN] = NextPHI;
 
+    bool StoppedEvolving = NextPHI == CurrentIterVals[PN];
+
     // Also evaluate the other PHI nodes.  However, we don't get to stop if we
     // cease to be able to evaluate one of them or if they stop evolving,
     // because that doesn't necessarily prevent us from computing PN.
@@ -4858,11 +4858,19 @@
       PHINode *PHI = dyn_cast<PHINode>(I->first);
       if (!PHI || PHI == PN || PHI->getParent() != Header) continue;
       Constant *&NextPHI = NextIterVals[PHI];
-      if (NextPHI) continue;    // Already computed!
-
-      Value *BEValue = PHI->getIncomingValue(SecondIsBackedge);
-      NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
+      if (!NextPHI) {   // Not already computed.
+        Value *BEValue = PHI->getIncomingValue(SecondIsBackedge);
+        NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
+      }
+      if (NextPHI != I->second)
+        StoppedEvolving = false;
     }
+
+    // If all entries in CurrentIterVals == NextIterVals then we can stop
+    // iterating, the loop can't continue to change.
+    if (StoppedEvolving)
+      return RetVal = CurrentIterVals[PN];
+
     CurrentIterVals.swap(NextIterVals);
   }
 }

Added: llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll?rev=142843&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll (added)
+++ llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll Mon Oct 24 16:02:38 2011
@@ -0,0 +1,29 @@
+; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+ at foo.a = internal constant [8 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7], align 16
+
+define i32 @foo() nounwind uwtable noinline {
+entry:
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
+; CHECK: --> %sum.0 Exits: 28
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
+  %cmp = icmp ult i32 %i.0, 8
+  br i1 %cmp, label %for.inc, label %for.end
+
+for.inc:                                          ; preds = %for.cond
+  %idxprom = sext i32 %i.0 to i64
+  %arrayidx = getelementptr inbounds [8 x i32]* @foo.a, i64 0, i64 %idxprom
+  %0 = load i32* %arrayidx, align 4
+  %add = add nsw i32 %sum.0, %0
+  %inc = add nsw i32 %i.0, 1
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  ret i32 %sum.0
+}



From nlewycky at google.com  Mon Oct 24 16:05:55 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Mon, 24 Oct 2011 14:05:55 -0700
Subject: [llvm-commits] [llvm] r142731 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
In-Reply-To: <CAJdarcG8a1TdptrY+6HtFNdGwbaAt7TZQz3bPx-FMV23YRXPbw@mail.gmail.com>
References: <20111022195820.621CC2A6C12C@llvm.org>
	<CAJdarcG8a1TdptrY+6HtFNdGwbaAt7TZQz3bPx-FMV23YRXPbw@mail.gmail.com>
Message-ID: <CADbEz-gDXrh9+XQPL3T9nv4uEGN84NKZsCHsZ5Trf2zKPgxsWw@mail.gmail.com>

On 24 October 2011 12:07, Eli Friedman <eli.friedman at gmail.com> wrote:

> On Sat, Oct 22, 2011 at 12:58 PM, Nick Lewycky <nicholas at mxc.ca> wrote:
> > Author: nicholas
> > Date: Sat Oct 22 14:58:20 2011
> > New Revision: 142731
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=142731&view=rev
> > Log:
> > Make SCEV's brute force analysis stronger in two ways. Firstly, we should
> be
> > able to constant fold load instructions where the argument is a constant.
> > Second, we should be able to watch multiple PHI nodes through the loop;
> this
> > patch only supports PHIs in loop headers, more can be done here.
> >
> > With this patch, we now constant evaluate:
> >  static const int arr[] = {1, 2, 3, 4, 5};
> >  int test() {
> >    int sum = 0;
> >    for (int i = 0; i < 5; ++i) sum += arr[i];
> >    return sum;
> >  }
>
> This commit is causing a miscompile on
> gcc.c-torture/execute/20030105-1.c (and possibly a couple other
> tests).


Thanks Eli! Fixed in r142843.

Nick
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From clattner at apple.com  Mon Oct 24 16:17:08 2011
From: clattner at apple.com (Chris Lattner)
Date: Mon, 24 Oct 2011 14:17:08 -0700
Subject: [llvm-commits] [PATCH][docs/CommandGuide] Reveal there is a
 "-help-hidden" option for opt command
In-Reply-To: <4EA56897.8030205@free.fr>
References: <20111023100324.GA3546@cs.nctu.edu.tw> <4EA52204.6090903@free.fr>
	<20111024091211.GA37465@cs.nctu.edu.tw> <4EA56897.8030205@free.fr>
Message-ID: <73F28AFD-15DB-48A5-AFEB-30F0B1F35F98@apple.com>


On Oct 24, 2011, at 6:31 AM, Duncan Sands wrote:

>>> I think it would be best to make -inline-threshold not be hidden.  I suspect
>>> there are a bunch of hidden options that shouldn't be hidden, and a bunch of
>>> not hidden options that should be hidden.  I think you shouldn't hesitate to
>>> send patches that change the hidden flag.
>> 
>>   Should we discuss which options should be hidden or not hidden on
>> LLVMdev mailing list? I want to collect developers' comment on this.
> 
> These seem like candidates:
> 
> -disable-output
> -inline-threshold
> -inlinehint-threshold
> -unroll-threshold
> 
> That said, these risk encouraging people to fiddle with thresholds rather than
> reporting bugs about inlining (or whatever) not doing a good job automatically.

I'd be fine with exposing these out through (e.g.) opt.  However, the "units" are subject to change in the future, which is why they aren't public "knobs".  They certainly shouldn't be exposed out through clang or otherwise to end-users of the compiler.

-Chris

From resistor at mac.com  Mon Oct 24 16:44:00 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 24 Oct 2011 21:44:00 -0000
Subject: [llvm-commits] [llvm] r142852 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20111024214400.4B97C312800A@llvm.org>

Author: resistor
Date: Mon Oct 24 16:44:00 2011
New Revision: 142852

URL: http://llvm.org/viewvc/llvm-project?rev=142852&view=rev
Log:
Get relocation parsing/dumping to a mostly-working state for MachO files.

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=142852&r1=142851&r2=142852&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Mon Oct 24 16:44:00 2011
@@ -16,6 +16,7 @@
 #include "llvm/Object/MachO.h"
 #include "llvm/Object/MachOFormat.h"
 #include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/raw_ostream.h"
 
 #include <cctype>
 #include <cstring>
@@ -596,15 +597,15 @@
 }
 error_code MachOObjectFile::getRelocationAddress(DataRefImpl Rel,
                                                  uint64_t &Res) const {
-  const uint8_t* sectAddress = base();
+  const uint8_t* sectAddress = 0;
   if (MachOObj->is64Bit()) {
     InMemoryStruct<macho::Section64> Sect;
     getSection64(Sections[Rel.d.b], Sect);
-    sectAddress += Sect->Offset;
+    sectAddress += Sect->Address;
   } else {
     InMemoryStruct<macho::Section> Sect;
     getSection(Sections[Rel.d.b], Sect);
-    sectAddress += Sect->Offset;
+    sectAddress += Sect->Address;
   }
   InMemoryStruct<macho::RelocationEntry> RE;
   getRelocation(Rel, RE);
@@ -641,7 +642,88 @@
 }
 error_code MachOObjectFile::getRelocationTypeName(DataRefImpl Rel,
                                           SmallVectorImpl<char> &Result) const {
-  StringRef res = "Unknown";
+  // TODO: Support scattered relocations.
+  StringRef res;
+  InMemoryStruct<macho::RelocationEntry> RE;
+  getRelocation(Rel, RE);
+  unsigned r_type = (RE->Word1 >> 28) & 0xF;
+
+  unsigned Arch = getArch();
+  switch (Arch) {
+    case Triple::x86: {
+      const char* Table[] =  {
+        "GENERIC_RELOC_VANILLA",
+        "GENERIC_RELOC_PAIR",
+        "GENERIC_RELOC_SECTDIFF",
+        "GENERIC_RELOC_LOCAL_SECTDIFF",
+        "GENERIC_RELOC_PB_LA_PTR" };
+
+      if (r_type > 4)
+        res = "Unknown";
+      else
+        res = Table[r_type];
+      break;
+    }
+    case Triple::x86_64: {
+      const char* Table[] =  {
+        "X86_64_RELOC_BRANCH",
+        "X86_64_RELOC_GOT_LOAD",
+        "X86_64_RELOC_GOT",
+        "X86_64_RELOC_SIGNED",
+        "X86_64_RELOC_UNSIGNED",
+        "X86_64_RELOC_SUBTRACTOR" };
+
+      if (r_type > 5)
+        res = "Unknown";
+      else
+        res = Table[r_type];
+      break;
+    }
+    case Triple::arm: {
+      const char* Table[] =  {
+        "ARM_RELOC_VANILLA",
+        "ARM_RELOC_PAIR",
+        "ARM_RELOC_SECTDIFF",
+        "ARM_RELOC_LOCAL_SECTDIFF",
+        "ARM_RELOC_PB_LA_PTR",
+        "ARM_RELOC_BR24",
+        "ARM_THUMB_RELOC_BR22",
+        "ARM_THUMB_32BIT_BRANCH",
+        "ARM_RELOC_HALF",
+        "ARM_RELOC_HALF_SECTDIFF" };
+
+      if (r_type > 9)
+        res = "Unknown";
+      else
+        res = Table[r_type];
+      break;
+    }
+    case Triple::ppc: {
+      const char* Table[] =  {
+        "PPC_RELOC_VANILLA",
+        "PPC_RELOC_PAIR",
+        "PPC_RELOC_BR14",
+        "PPC_RELOC_BR24",
+        "PPC_RELOC_HI16",
+        "PPC_RELOC_LO16",
+        "PPC_RELOC_HA16",
+        "PPC_RELOC_LO14",
+        "PPC_RELOC_SECTDIFF",
+        "PPC_RELOC_PB_LA_PTR",
+        "PPC_RELOC_HI16_SECTDIFF",
+        "PPC_RELOC_LO16_SECTDIFF",
+        "PPC_RELOC_HA16_SECTDIFF",
+        "PPC_RELOC_JBSR",
+        "PPC_RELOC_LO14_SECTDIFF",
+        "PPC_RELOC_LOCAL_SECTDIFF" };
+
+      res = Table[r_type];
+      break;
+    }
+    case Triple::UnknownArch:
+      res = "Unknown";
+      break;
+  }
   Result.append(res.begin(), res.end());
   return object_error::success;
 }
@@ -668,8 +750,47 @@
 }
 error_code MachOObjectFile::getRelocationValueString(DataRefImpl Rel,
                                           SmallVectorImpl<char> &Result) const {
-  StringRef res = "Unknown";
-  Result.append(res.begin(), res.end());
+  InMemoryStruct<macho::RelocationEntry> RE;
+  getRelocation(Rel, RE);
+
+  std::string fmtbuf;
+  raw_string_ostream fmt(fmtbuf);
+
+  bool isExtern = (RE->Word1 >> 27) & 1;
+  if (isExtern) {
+    uint32_t Val = (RE->Word1 & 0xFFFFFF);
+    symbol_iterator SI = begin_symbols();
+
+    error_code ec;
+    while (Val--) {
+      SI.increment(ec);
+      if (ec) report_fatal_error(ec.message());
+    }
+
+    StringRef SymName;
+    if ((ec = SI->getName(SymName)))
+      report_fatal_error(ec.message());
+
+    fmt << SymName;
+  } else {
+    uint32_t Val = (RE->Word1 & 0xFFFFFF);
+    section_iterator SI = begin_sections();
+
+    error_code ec;
+    while (Val--) {
+      SI.increment(ec);
+      if (ec) report_fatal_error(ec.message());
+    }
+
+    StringRef SectName;
+    if ((ec = SI->getName(SectName)))
+      report_fatal_error(ec.message());
+
+    fmt << SectName;
+  }
+
+  fmt.flush();
+  Result.append(fmtbuf.begin(), fmtbuf.end());
   return object_error::success;
 }
 



From grosbach at apple.com  Mon Oct 24 16:45:13 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 24 Oct 2011 21:45:13 -0000
Subject: [llvm-commits] [llvm] r142853 - in /llvm/trunk/lib/Target/ARM:
 ARMBaseInstrInfo.cpp ARMExpandPseudoInsts.cpp ARMISelDAGToDAG.cpp
 ARMInstrNEON.td Disassembler/ARMDisassembler.cpp
Message-ID: <20111024214513.A6B09312800A@llvm.org>

Author: grosbach
Date: Mon Oct 24 16:45:13 2011
New Revision: 142853

URL: http://llvm.org/viewvc/llvm-project?rev=142853&view=rev
Log:
ARM refactor am6offset usage for VLD1.

Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.


Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=142853&r1=142852&r2=142853&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Oct 24 16:45:13 2011
@@ -2401,10 +2401,14 @@
     case ARM::VLD1q16:
     case ARM::VLD1q32:
     case ARM::VLD1q64:
-    case ARM::VLD1q8_UPD:
-    case ARM::VLD1q16_UPD:
-    case ARM::VLD1q32_UPD:
-    case ARM::VLD1q64_UPD:
+    case ARM::VLD1q8wb_fixed:
+    case ARM::VLD1q16wb_fixed:
+    case ARM::VLD1q32wb_fixed:
+    case ARM::VLD1q64wb_fixed:
+    case ARM::VLD1q8wb_register:
+    case ARM::VLD1q16wb_register:
+    case ARM::VLD1q32wb_register:
+    case ARM::VLD1q64wb_register:
     case ARM::VLD2d8:
     case ARM::VLD2d16:
     case ARM::VLD2d32:
@@ -2562,10 +2566,14 @@
     case ARM::VLD1q16Pseudo:
     case ARM::VLD1q32Pseudo:
     case ARM::VLD1q64Pseudo:
-    case ARM::VLD1q8Pseudo_UPD:
-    case ARM::VLD1q16Pseudo_UPD:
-    case ARM::VLD1q32Pseudo_UPD:
-    case ARM::VLD1q64Pseudo_UPD:
+    case ARM::VLD1q8PseudoWB_register:
+    case ARM::VLD1q16PseudoWB_register:
+    case ARM::VLD1q32PseudoWB_register:
+    case ARM::VLD1q64PseudoWB_register:
+    case ARM::VLD1q8PseudoWB_fixed:
+    case ARM::VLD1q16PseudoWB_fixed:
+    case ARM::VLD1q32PseudoWB_fixed:
+    case ARM::VLD1q64PseudoWB_fixed:
     case ARM::VLD2d8Pseudo:
     case ARM::VLD2d16Pseudo:
     case ARM::VLD2d32Pseudo:

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=142853&r1=142852&r2=142853&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Oct 24 16:45:13 2011
@@ -102,7 +102,7 @@
     unsigned PseudoOpc;
     unsigned RealOpc;
     bool IsLoad;
-    bool HasWriteBack;
+    bool HasWritebackOperand;
     NEONRegSpacing RegSpacing;
     unsigned char NumRegs; // D registers loaded or stored
     unsigned char RegElts; // elements per D register; used for lane ops
@@ -148,13 +148,17 @@
 { ARM::VLD1d64TPseudo_UPD,  ARM::VLD1d64T_UPD, true,  true,  SingleSpc,  3, 1 ,false},
 
 { ARM::VLD1q16Pseudo,       ARM::VLD1q16,      true,  false, SingleSpc,  2, 4 ,false},
-{ ARM::VLD1q16Pseudo_UPD,   ARM::VLD1q16_UPD,  true,  true,  SingleSpc,  2, 4 ,false},
+{ ARM::VLD1q16PseudoWB_fixed, ARM::VLD1q16wb_fixed,true,false,SingleSpc, 2, 4 ,false},
+{ ARM::VLD1q16PseudoWB_register, ARM::VLD1q16wb_register, true, true, SingleSpc, 2, 4 ,false},
 { ARM::VLD1q32Pseudo,       ARM::VLD1q32,      true,  false, SingleSpc,  2, 2 ,false},
-{ ARM::VLD1q32Pseudo_UPD,   ARM::VLD1q32_UPD,  true,  true,  SingleSpc,  2, 2 ,false},
+{ ARM::VLD1q32PseudoWB_fixed, ARM::VLD1q32wb_fixed,true,false,SingleSpc, 2, 2 ,false},
+{ ARM::VLD1q32PseudoWB_register, ARM::VLD1q32wb_register, true, true, SingleSpc, 2, 2 ,false},
 { ARM::VLD1q64Pseudo,       ARM::VLD1q64,      true,  false, SingleSpc,  2, 1 ,false},
-{ ARM::VLD1q64Pseudo_UPD,   ARM::VLD1q64_UPD,  true,  true,  SingleSpc,  2, 1 ,false},
+{ ARM::VLD1q64PseudoWB_fixed, ARM::VLD1q64wb_fixed,true,false,SingleSpc, 2, 2 ,false},
+{ ARM::VLD1q64PseudoWB_register, ARM::VLD1q64wb_register, true, true, SingleSpc, 2, 1 ,false},
 { ARM::VLD1q8Pseudo,        ARM::VLD1q8,       true,  false, SingleSpc,  2, 8 ,false},
-{ ARM::VLD1q8Pseudo_UPD,    ARM::VLD1q8_UPD,   true,  true,  SingleSpc,  2, 8 ,false},
+{ ARM::VLD1q8PseudoWB_fixed, ARM::VLD1q8wb_fixed,true,false, SingleSpc,  2, 8 ,false},
+{ ARM::VLD1q8PseudoWB_register, ARM::VLD1q8wb_register,true,true,SingleSpc,2,8,false},
 
 { ARM::VLD2DUPd16Pseudo,     ARM::VLD2DUPd16,     true, false, SingleSpc, 2, 4,true},
 { ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true,  SingleSpc, 2, 4,true},
@@ -436,14 +440,14 @@
   if (NumRegs > 3 && TableEntry->copyAllListRegs)
     MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
 
-  if (TableEntry->HasWriteBack)
+  if (TableEntry->HasWritebackOperand)
     MIB.addOperand(MI.getOperand(OpIdx++));
 
   // Copy the addrmode6 operands.
   MIB.addOperand(MI.getOperand(OpIdx++));
   MIB.addOperand(MI.getOperand(OpIdx++));
   // Copy the am6offset operand.
-  if (TableEntry->HasWriteBack)
+  if (TableEntry->HasWritebackOperand)
     MIB.addOperand(MI.getOperand(OpIdx++));
 
   // For an instruction writing double-spaced subregs, the pseudo instruction
@@ -488,14 +492,14 @@
   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
                                     TII->get(TableEntry->RealOpc));
   unsigned OpIdx = 0;
-  if (TableEntry->HasWriteBack)
+  if (TableEntry->HasWritebackOperand)
     MIB.addOperand(MI.getOperand(OpIdx++));
 
   // Copy the addrmode6 operands.
   MIB.addOperand(MI.getOperand(OpIdx++));
   MIB.addOperand(MI.getOperand(OpIdx++));
   // Copy the am6offset operand.
-  if (TableEntry->HasWriteBack)
+  if (TableEntry->HasWritebackOperand)
     MIB.addOperand(MI.getOperand(OpIdx++));
 
   bool SrcIsKill = MI.getOperand(OpIdx).isKill();
@@ -565,14 +569,14 @@
       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
   }
 
-  if (TableEntry->HasWriteBack)
+  if (TableEntry->HasWritebackOperand)
     MIB.addOperand(MI.getOperand(OpIdx++));
 
   // Copy the addrmode6 operands.
   MIB.addOperand(MI.getOperand(OpIdx++));
   MIB.addOperand(MI.getOperand(OpIdx++));
   // Copy the am6offset operand.
-  if (TableEntry->HasWriteBack)
+  if (TableEntry->HasWritebackOperand)
     MIB.addOperand(MI.getOperand(OpIdx++));
 
   // Grab the super-register source.
@@ -1068,10 +1072,14 @@
     case ARM::VLD1q16Pseudo:
     case ARM::VLD1q32Pseudo:
     case ARM::VLD1q64Pseudo:
-    case ARM::VLD1q8Pseudo_UPD:
-    case ARM::VLD1q16Pseudo_UPD:
-    case ARM::VLD1q32Pseudo_UPD:
-    case ARM::VLD1q64Pseudo_UPD:
+    case ARM::VLD1q8PseudoWB_register:
+    case ARM::VLD1q16PseudoWB_register:
+    case ARM::VLD1q32PseudoWB_register:
+    case ARM::VLD1q64PseudoWB_register:
+    case ARM::VLD1q8PseudoWB_fixed:
+    case ARM::VLD1q16PseudoWB_fixed:
+    case ARM::VLD1q32PseudoWB_fixed:
+    case ARM::VLD1q64PseudoWB_fixed:
     case ARM::VLD2d8Pseudo:
     case ARM::VLD2d16Pseudo:
     case ARM::VLD2d32Pseudo:

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=142853&r1=142852&r2=142853&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Oct 24 16:45:13 2011
@@ -1549,6 +1549,23 @@
   return CurDAG->getTargetConstant(Alignment, MVT::i32);
 }
 
+// Get the register stride update opcode of a VLD/VST instruction that
+// is otherwise equivalent to the given fixed stride updating instruction.
+static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
+  switch (Opc) {
+  default: break;
+  case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
+  case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
+  case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
+  case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
+  case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
+  case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
+  case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
+  case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
+  }
+  return Opc; // If not one we handle, return it unchanged.
+}
+
 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
                                    unsigned *DOpcodes, unsigned *QOpcodes0,
                                    unsigned *QOpcodes1) {
@@ -1612,7 +1629,14 @@
     Ops.push_back(Align);
     if (isUpdating) {
       SDValue Inc = N->getOperand(AddrOpIdx + 1);
-      Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
+      // FIXME: VLD1 fixed increment doesn't need Reg0. Remove the reg0
+      // case entirely when the rest are updated to that form, too.
+      // Do that before committing this change. Likewise, the opcode
+      // update call will become unconditional.
+      if (NumVecs == 1 && !isa<ConstantSDNode>(Inc.getNode()))
+        Opc = getVLDSTRegisterUpdateOpcode(Opc);
+      if (NumVecs != 1 || !isa<ConstantSDNode>(Inc.getNode()))
+        Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
     }
     Ops.push_back(Pred);
     Ops.push_back(Reg0);
@@ -2750,16 +2774,18 @@
   }
 
   case ARMISD::VLD1_UPD: {
-    unsigned DOpcodes[] = { ARM::VLD1d8_UPD, ARM::VLD1d16_UPD,
-                            ARM::VLD1d32_UPD, ARM::VLD1d64_UPD };
-    unsigned QOpcodes[] = { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q16Pseudo_UPD,
-                            ARM::VLD1q32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
+    unsigned DOpcodes[] = { ARM::VLD1d8wb_fixed, ARM::VLD1d16wb_fixed,
+                            ARM::VLD1d32wb_fixed, ARM::VLD1d64wb_fixed };
+    unsigned QOpcodes[] = { ARM::VLD1q8PseudoWB_fixed,
+                            ARM::VLD1q16PseudoWB_fixed,
+                            ARM::VLD1q32PseudoWB_fixed,
+                            ARM::VLD1q64PseudoWB_fixed };
     return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
   }
 
   case ARMISD::VLD2_UPD: {
     unsigned DOpcodes[] = { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d16Pseudo_UPD,
-                            ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
+                            ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
     unsigned QOpcodes[] = { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q16Pseudo_UPD,
                             ARM::VLD2q32Pseudo_UPD };
     return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
@@ -2767,7 +2793,7 @@
 
   case ARMISD::VLD3_UPD: {
     unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
-                            ARM::VLD3d32Pseudo_UPD, ARM::VLD1d64TPseudo_UPD };
+                            ARM::VLD3d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
     unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
                              ARM::VLD3q16Pseudo_UPD,
                              ARM::VLD3q32Pseudo_UPD };
@@ -2779,7 +2805,7 @@
 
   case ARMISD::VLD4_UPD: {
     unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
-                            ARM::VLD4d32Pseudo_UPD, ARM::VLD1d64QPseudo_UPD };
+                            ARM::VLD4d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
     unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
                              ARM::VLD4q16Pseudo_UPD,
                              ARM::VLD4q32Pseudo_UPD };

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142853&r1=142852&r2=142853&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 24 16:45:13 2011
@@ -259,6 +259,14 @@
   : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
                 (ins addrmode6:$addr, am6offset:$offset), itin,
                 "$addr.addr = $wb">;
+class VLDQWBfixedPseudo<InstrItinClass itin>
+  : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
+                (ins addrmode6:$addr), itin,
+                "$addr.addr = $wb">;
+class VLDQWBregisterPseudo<InstrItinClass itin>
+  : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
+                (ins addrmode6:$addr, rGPR:$offset), itin,
+                "$addr.addr = $wb">;
 class VLDQQPseudo<InstrItinClass itin>
   : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
 class VLDQQWBPseudo<InstrItinClass itin>
@@ -309,37 +317,58 @@
 def  VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
 
 // ...with address register writeback:
-class VLD1DWB<bits<4> op7_4, string Dt>
-  : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
-          (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
-          "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
-          "$Rn.addr = $wb", []> {
-  let Inst{4} = Rn{4};
-  let DecoderMethod = "DecodeVLDInstruction";
+multiclass VLD1DWB<bits<4> op7_4, string Dt> {
+  def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
+                     (ins addrmode6:$Rn), IIC_VLD1u,
+                     "vld1", Dt, "$Vd, $Rn!",
+                     "$Rn.addr = $wb", []> {
+    let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
+    let Inst{4} = Rn{4};
+    let DecoderMethod = "DecodeVLDInstruction";
+  }
+  def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
+                        (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
+                        "vld1", Dt, "$Vd, $Rn, $Rm",
+                        "$Rn.addr = $wb", []> {
+    let Inst{4} = Rn{4};
+    let DecoderMethod = "DecodeVLDInstruction";
+  }
 }
-class VLD1QWB<bits<4> op7_4, string Dt>
-  : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
-          (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
-          "vld1", Dt, "$Vd, $Rn$Rm",
-          "$Rn.addr = $wb", []> {
-  let Inst{5-4} = Rn{5-4};
-  let DecoderMethod = "DecodeVLDInstruction";
+multiclass VLD1QWB<bits<4> op7_4, string Dt> {
+  def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
+                    (ins addrmode6:$Rn), IIC_VLD1x2u,
+                     "vld1", Dt, "$Vd, $Rn!",
+                     "$Rn.addr = $wb", []> {
+    let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
+    let Inst{5-4} = Rn{5-4};
+    let DecoderMethod = "DecodeVLDInstruction";
+  }
+  def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
+                        (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
+                        "vld1", Dt, "$Vd, $Rn, $Rm",
+                        "$Rn.addr = $wb", []> {
+    let Inst{5-4} = Rn{5-4};
+    let DecoderMethod = "DecodeVLDInstruction";
+  }
 }
 
-def VLD1d8_UPD  : VLD1DWB<{0,0,0,?}, "8">;
-def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
-def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
-def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
-
-def VLD1q8_UPD  : VLD1QWB<{0,0,?,?}, "8">;
-def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
-def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
-def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
-
-def VLD1q8Pseudo_UPD  : VLDQWBPseudo<IIC_VLD1x2u>;
-def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
-def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
-def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
+defm VLD1d8wb  : VLD1DWB<{0,0,0,?}, "8">;
+defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
+defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
+defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
+defm VLD1q8wb  : VLD1QWB<{0,0,?,?}, "8">;
+defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
+defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
+defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
+
+def VLD1q8PseudoWB_fixed  : VLDQWBfixedPseudo<IIC_VLD1x2u>;
+def VLD1q16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
+def VLD1q32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
+def VLD1q64PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
+def VLD1q8PseudoWB_register  : VLDQWBregisterPseudo<IIC_VLD1x2u>;
+def VLD1q16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
+def VLD1q32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
+def VLD1q64PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
 
 // ...with 3 registers
 class VLD1D3<bits<4> op7_4, string Dt>

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=142853&r1=142852&r2=142853&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Oct 24 16:45:13 2011
@@ -2054,14 +2054,22 @@
 
   // Writeback operand
   switch (Inst.getOpcode()) {
-    case ARM::VLD1d8_UPD:
-    case ARM::VLD1d16_UPD:
-    case ARM::VLD1d32_UPD:
-    case ARM::VLD1d64_UPD:
-    case ARM::VLD1q8_UPD:
-    case ARM::VLD1q16_UPD:
-    case ARM::VLD1q32_UPD:
-    case ARM::VLD1q64_UPD:
+    case ARM::VLD1d8wb_fixed:
+    case ARM::VLD1d16wb_fixed:
+    case ARM::VLD1d32wb_fixed:
+    case ARM::VLD1d64wb_fixed:
+    case ARM::VLD1d8wb_register:
+    case ARM::VLD1d16wb_register:
+    case ARM::VLD1d32wb_register:
+    case ARM::VLD1d64wb_register:
+    case ARM::VLD1q8wb_fixed:
+    case ARM::VLD1q16wb_fixed:
+    case ARM::VLD1q32wb_fixed:
+    case ARM::VLD1q64wb_fixed:
+    case ARM::VLD1q8wb_register:
+    case ARM::VLD1q16wb_register:
+    case ARM::VLD1q32wb_register:
+    case ARM::VLD1q64wb_register:
     case ARM::VLD1d8T_UPD:
     case ARM::VLD1d16T_UPD:
     case ARM::VLD1d32T_UPD:
@@ -2103,11 +2111,42 @@
     return MCDisassembler::Fail;
 
   // AddrMode6 Offset (register)
-  if (Rm == 0xD)
-    Inst.addOperand(MCOperand::CreateReg(0));
-  else if (Rm != 0xF) {
-    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+  switch (Inst.getOpcode()) {
+  default:
+    // The below have been updated to have explicit am6offset split
+    // between fixed and register offset. For those instructions not
+    // yet updated, we need to add an additional reg0 operand for the
+    // fixed variant.
+    //
+    // The fixed offset encodes as Rm == 0xd, so we check for that.
+    if (Rm == 0xd) {
+      Inst.addOperand(MCOperand::CreateReg(0));
+      break;
+    }
+    // Fall through to handle the register offset variant.
+  case ARM::VLD1d8wb_fixed:
+  case ARM::VLD1d16wb_fixed:
+  case ARM::VLD1d32wb_fixed:
+  case ARM::VLD1d64wb_fixed:
+  case ARM::VLD1d8wb_register:
+  case ARM::VLD1d16wb_register:
+  case ARM::VLD1d32wb_register:
+  case ARM::VLD1d64wb_register:
+  case ARM::VLD1q8wb_fixed:
+  case ARM::VLD1q16wb_fixed:
+  case ARM::VLD1q32wb_fixed:
+  case ARM::VLD1q64wb_fixed:
+  case ARM::VLD1q8wb_register:
+  case ARM::VLD1q16wb_register:
+  case ARM::VLD1q32wb_register:
+  case ARM::VLD1q64wb_register:
+    // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
+    // variant encodes Rm == 0xf. Anything else is a register offset post-
+    // increment and we need to add the register operand to the instruction.
+    if (Rm != 0xD && Rm != 0xF &&
+        !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
       return MCDisassembler::Fail;
+    break;
   }
 
   return S;



From mcrosier at apple.com  Mon Oct 24 16:56:50 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Mon, 24 Oct 2011 21:56:50 -0000
Subject: [llvm-commits] [llvm] r142856 - /llvm/trunk/utils/show-diagnostics
Message-ID: <20111024215650.79E83312800A@llvm.org>

Author: mcrosier
Date: Mon Oct 24 16:56:50 2011
New Revision: 142856

URL: http://llvm.org/viewvc/llvm-project?rev=142856&view=rev
Log:
Add options to enable each individual level for the show-diagnostics tool.
rdar://9683410

Modified:
    llvm/trunk/utils/show-diagnostics

Modified: llvm/trunk/utils/show-diagnostics
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/show-diagnostics?rev=142856&r1=142855&r2=142856&view=diff
==============================================================================
--- llvm/trunk/utils/show-diagnostics (original)
+++ llvm/trunk/utils/show-diagnostics Mon Oct 24 16:56:50 2011
@@ -5,15 +5,40 @@
 def main():
     from optparse import OptionParser, OptionGroup
     parser = OptionParser("""\
-usage: %prog [options] <path>
+Usage: %prog [options] <path>
 
 Utility for dumping Clang-style logged diagnostics.\
 """)
+    parser.add_option("-a", "--all", action="store_true", dest="all", 
+                      default=False, help="dump all messages.")
+    parser.add_option("-e", "--error", action="store_true", dest="error", 
+                      default=False, help="dump 'error' messages.")
+    parser.add_option("-f", "--fatal", action="store_true", dest="fatal", 
+                      default=False, help="dump 'fatal error' messages.")
+    parser.add_option("-i", "--ignored", action="store_true", dest="ignored", 
+                      default=False, help="dump 'ignored' messages.")
+    parser.add_option("-n", "--note", action="store_true", dest="note", 
+                      default=False, help="dump 'note' messages.")
+    parser.add_option("-w", "--warning", action="store_true", dest="warning", 
+                      default=False, help="dump 'warning' messages.")
     (opts, args) = parser.parse_args()
 
     if len(args) != 1:
         parser.error("invalid number of arguments")
 
+    levels = {'error': False, 'fatal error': False, 'ignored': False,
+              'note': False, 'warning': False}
+    if opts.error:
+        levels['error'] = True
+    if opts.fatal:
+        levels['fatal error'] = True
+    if opts.ignored:
+        levels['ignored'] = True
+    if opts.note:
+        levels['note'] = True
+    if opts.warning:
+        levels['warning'] = True
+
     path, = args
 
     # Read the diagnostics log.
@@ -44,9 +69,10 @@
         file = file_diags.get('main-file')
         print "*** %s ***" % file
         for d in file_diags.get('diagnostics', ()):
-            print "%s:%s:%s: %s: %s" % (
-                d.get('filename'), d.get('line'), d.get('column'),
-                d.get('level'), d.get('message'))
+            if levels[d.get('level')] or opts.all:
+                print " %s:%s:%s: %s: %s" % (
+                    d.get('filename'), d.get('line'), d.get('column'),
+                    d.get('level'), d.get('message'))
 
 if __name__ == "__main__":
     main()



From grosbach at apple.com  Mon Oct 24 17:16:59 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 24 Oct 2011 22:16:59 -0000
Subject: [llvm-commits] [llvm] r142861 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/neon-vld-encoding.s
Message-ID: <20111024221659.28B6E312800A@llvm.org>

Author: grosbach
Date: Mon Oct 24 17:16:58 2011
New Revision: 142861

URL: http://llvm.org/viewvc/llvm-project?rev=142861&view=rev
Log:
ARM assembly parsing and encoding for VLD1 w/ writeback.

One and two length register list variants.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/neon-vld-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142861&r1=142860&r2=142861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 24 17:16:58 2011
@@ -325,6 +325,7 @@
     let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
     let Inst{4} = Rn{4};
     let DecoderMethod = "DecodeVLDInstruction";
+    let AsmMatchConverter = "cvtVLDwbFixed";
   }
   def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
                         (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
@@ -332,6 +333,7 @@
                         "$Rn.addr = $wb", []> {
     let Inst{4} = Rn{4};
     let DecoderMethod = "DecodeVLDInstruction";
+    let AsmMatchConverter = "cvtVLDwbRegister";
   }
 }
 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
@@ -342,6 +344,7 @@
     let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
     let Inst{5-4} = Rn{5-4};
     let DecoderMethod = "DecodeVLDInstruction";
+    let AsmMatchConverter = "cvtVLDwbFixed";
   }
   def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
                         (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
@@ -349,6 +352,7 @@
                         "$Rn.addr = $wb", []> {
     let Inst{5-4} = Rn{5-4};
     let DecoderMethod = "DecodeVLDInstruction";
+    let AsmMatchConverter = "cvtVLDwbRegister";
   }
 }
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=142861&r1=142860&r2=142861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Oct 24 17:16:58 2011
@@ -198,6 +198,10 @@
                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
   bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
                         const SmallVectorImpl<MCParsedAsmOperand*> &);
+  bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
+                     const SmallVectorImpl<MCParsedAsmOperand*> &);
+  bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
+                        const SmallVectorImpl<MCParsedAsmOperand*> &);
 
   bool validateInstruction(MCInst &Inst,
                            const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
@@ -3326,6 +3330,36 @@
   return true;
 }
 
+bool ARMAsmParser::
+cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
+              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  // Vd
+  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
+  // Create a writeback register dummy placeholder.
+  Inst.addOperand(MCOperand::CreateImm(0));
+  // Vn
+  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
+  // pred
+  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
+  return true;
+}
+
+bool ARMAsmParser::
+cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
+                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  // Vd
+  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
+  // Create a writeback register dummy placeholder.
+  Inst.addOperand(MCOperand::CreateImm(0));
+  // Vn
+  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
+  // Vm
+  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
+  // pred
+  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
+  return true;
+}
+
 /// Parse an ARM memory expression, return false if successful else return true
 /// or an error.  The first token must be a '[' when called.
 bool ARMAsmParser::

Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=142861&r1=142860&r2=142861&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Mon Oct 24 17:16:58 2011
@@ -17,22 +17,58 @@
 	vld1.32 {d5, d6, d7, d8}, [r3]
 	vld1.64 {d6, d7, d8, d9}, [r3, :64]
 
-@ CHECK: vld1.8	{d16}, [r0, :64]        @ encoding: [0x1f,0x07,0x60,0xf4]
-@ CHECK: vld1.16	{d16}, [r0]     @ encoding: [0x4f,0x07,0x60,0xf4]
-@ CHECK: vld1.32	{d16}, [r0]     @ encoding: [0x8f,0x07,0x60,0xf4]
-@ CHECK: vld1.64	{d16}, [r0]     @ encoding: [0xcf,0x07,0x60,0xf4]
-@ CHECK: vld1.8	{d16, d17}, [r0, :64]   @ encoding: [0x1f,0x0a,0x60,0xf4]
-@ CHECK: vld1.16	{d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4]
-@ CHECK: vld1.32	{d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf4]
-@ CHECK: vld1.64	{d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4]
-@ CHECK: vld1.8	{d1, d2, d3}, [r3]      @ encoding: [0x0f,0x16,0x23,0xf4]
+	vld1.8	{d16}, [r0, :64]!
+	vld1.16	{d16}, [r0]!
+	vld1.32	{d16}, [r0]!
+	vld1.64	{d16}, [r0]!
+	vld1.8	{d16, d17}, [r0, :64]!
+	vld1.16	{d16, d17}, [r0, :128]!
+	vld1.32	{d16, d17}, [r0]!
+	vld1.64	{d16, d17}, [r0]!
+
+	vld1.8	{d16}, [r0, :64], r5
+	vld1.16	{d16}, [r0], r5
+	vld1.32	{d16}, [r0], r5
+	vld1.64	{d16}, [r0], r5
+	vld1.8	{d16, d17}, [r0, :64], r5
+	vld1.16	{d16, d17}, [r0, :128], r5
+	vld1.32	{d16, d17}, [r0], r5
+	vld1.64	{d16, d17}, [r0], r5
+
+@ CHECK: vld1.8 {d16}, [r0, :64]        @ encoding: [0x1f,0x07,0x60,0xf4]
+@ CHECK: vld1.16 {d16}, [r0]            @ encoding: [0x4f,0x07,0x60,0xf4]
+@ CHECK: vld1.32 {d16}, [r0]            @ encoding: [0x8f,0x07,0x60,0xf4]
+@ CHECK: vld1.64 {d16}, [r0]            @ encoding: [0xcf,0x07,0x60,0xf4]
+@ CHECK: vld1.8 {d16, d17}, [r0, :64]   @ encoding: [0x1f,0x0a,0x60,0xf4]
+@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4]
+@ CHECK: vld1.32 {d16, d17}, [r0]       @ encoding: [0x8f,0x0a,0x60,0xf4]
+@ CHECK: vld1.64 {d16, d17}, [r0]       @ encoding: [0xcf,0x0a,0x60,0xf4]
+@ CHECK: vld1.8 {d1, d2, d3}, [r3]      @ encoding: [0x0f,0x16,0x23,0xf4]
 @ CHECK: vld1.16 {d4, d5, d6}, [r3, :64] @ encoding: [0x5f,0x46,0x23,0xf4]
-@ CHECK: vld1.32 {d5, d6, d7}, [r3]      @ encoding: [0x8f,0x56,0x23,0xf4]
+@ CHECK: vld1.32 {d5, d6, d7}, [r3]     @ encoding: [0x8f,0x56,0x23,0xf4]
 @ CHECK: vld1.64 {d6, d7, d8}, [r3, :64] @ encoding: [0xdf,0x66,0x23,0xf4]
-@ CHECK: vld1.8	{d1, d2, d3, d4}, [r3]  @ encoding: [0x0f,0x12,0x23,0xf4]
+@ CHECK: vld1.8 {d1, d2, d3, d4}, [r3]  @ encoding: [0x0f,0x12,0x23,0xf4]
 @ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64] @ encoding: [0x5f,0x42,0x23,0xf4]
 @ CHECK: vld1.32 {d5, d6, d7, d8}, [r3]  @ encoding: [0x8f,0x52,0x23,0xf4]
 @ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64] @ encoding: [0xdf,0x62,0x23,0xf4]
+@ CHECK: vld1.8	{d16}, [r0, :64]!       @ encoding: [0x1d,0x07,0x60,0xf4]
+
+@ CHECK: vld1.16 {d16}, [r0]!           @ encoding: [0x4d,0x07,0x60,0xf4]
+@ CHECK: vld1.32 {d16}, [r0]!           @ encoding: [0x8d,0x07,0x60,0xf4]
+@ CHECK: vld1.64 {d16}, [r0]!           @ encoding: [0xcd,0x07,0x60,0xf4]
+@ CHECK: vld1.8 {d16, d17}, [r0, :64]!  @ encoding: [0x1d,0x0a,0x60,0xf4]
+@ CHECK: vld1.16 {d16, d17}, [r0, :128]! @ encoding: [0x6d,0x0a,0x60,0xf4]
+@ CHECK: vld1.32 {d16, d17}, [r0]!      @ encoding: [0x8d,0x0a,0x60,0xf4]
+@ CHECK: vld1.64 {d16, d17}, [r0]!      @ encoding: [0xcd,0x0a,0x60,0xf4]
+
+@ CHECK: vld1.8 {d16}, [r0, :64], r5    @ encoding: [0x15,0x07,0x60,0xf4]
+@ CHECK: vld1.16 {d16}, [r0], r5        @ encoding: [0x45,0x07,0x60,0xf4]
+@ CHECK: vld1.32 {d16}, [r0], r5        @ encoding: [0x85,0x07,0x60,0xf4]
+@ CHECK: vld1.64 {d16}, [r0], r5        @ encoding: [0xc5,0x07,0x60,0xf4]
+@ CHECK: vld1.8 {d16, d17}, [r0, :64], r5 @ encoding: [0x15,0x0a,0x60,0xf4]
+@ CHECK: vld1.16 {d16, d17}, [r0, :128], r5 @ encoding: [0x65,0x0a,0x60,0xf4]
+@ CHECK: vld1.32 {d16, d17}, [r0], r5   @ encoding: [0x85,0x0a,0x60,0xf4]
+@ CHECK: vld1.64 {d16, d17}, [r0], r5   @ encoding: [0xc5,0x0a,0x60,0xf4]
 
 
 	vld2.8	{d16, d17}, [r0, :64]



From evan.cheng at apple.com  Mon Oct 24 18:01:03 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 24 Oct 2011 23:01:03 -0000
Subject: [llvm-commits] [llvm] r142867 -
	/llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp
Message-ID: <20111024230103.708FA312800A@llvm.org>

Author: evancheng
Date: Mon Oct 24 18:01:03 2011
New Revision: 142867

URL: http://llvm.org/viewvc/llvm-project?rev=142867&view=rev
Log:
ARMConstantPoolMBB::print should print BB number.

Modified:
    llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp?rev=142867&r1=142866&r2=142867&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp Mon Oct 24 18:01:03 2011
@@ -315,5 +315,6 @@
 }
 
 void ARMConstantPoolMBB::print(raw_ostream &O) const {
+  O << "BB#" << MBB->getNumber();
   ARMConstantPoolValue::print(O);
 }



From isanbard at gmail.com  Mon Oct 24 18:05:43 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 24 Oct 2011 23:05:43 -0000
Subject: [llvm-commits] [llvm] r142869 - in /llvm/trunk:
 lib/CodeGen/TargetLoweringObjectFileImpl.cpp
 test/CodeGen/ARM/gv-stubs-crash.ll
Message-ID: <20111024230543.5F950312800A@llvm.org>

Author: void
Date: Mon Oct 24 18:05:43 2011
New Revision: 142869

URL: http://llvm.org/viewvc/llvm-project?rev=142869&view=rev
Log:
Check the visibility of the global variable before placing it into the stubs
table. A hidden variable could potentially end up in both lists.
<rdar://problem/10336715>

Added:
    llvm/trunk/test/CodeGen/ARM/gv-stubs-crash.ll
Modified:
    llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp

Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=142869&r1=142868&r2=142869&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Mon Oct 24 18:05:43 2011
@@ -506,7 +506,9 @@
     // Add information about the stub reference to MachOMMI so that the stub
     // gets emitted by the asmprinter.
     MCSymbol *SSym = getContext().GetOrCreateSymbol(Name.str());
-    MachineModuleInfoImpl::StubValueTy &StubSym = MachOMMI.getGVStubEntry(SSym);
+    MachineModuleInfoImpl::StubValueTy &StubSym =
+      GV->hasHiddenVisibility() ? MachOMMI.getHiddenGVStubEntry(SSym) :
+                                  MachOMMI.getGVStubEntry(SSym);
     if (StubSym.getPointer() == 0) {
       MCSymbol *Sym = Mang->getSymbol(GV);
       StubSym = MachineModuleInfoImpl::StubValueTy(Sym, !GV->hasLocalLinkage());
@@ -534,7 +536,9 @@
   // Add information about the stub reference to MachOMMI so that the stub
   // gets emitted by the asmprinter.
   MCSymbol *SSym = getContext().GetOrCreateSymbol(Name.str());
-  MachineModuleInfoImpl::StubValueTy &StubSym = MachOMMI.getGVStubEntry(SSym);
+  MachineModuleInfoImpl::StubValueTy &StubSym =
+      GV->hasHiddenVisibility() ? MachOMMI.getHiddenGVStubEntry(SSym) :
+                                  MachOMMI.getGVStubEntry(SSym);
   if (StubSym.getPointer() == 0) {
     MCSymbol *Sym = Mang->getSymbol(GV);
     StubSym = MachineModuleInfoImpl::StubValueTy(Sym, !GV->hasLocalLinkage());

Added: llvm/trunk/test/CodeGen/ARM/gv-stubs-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/gv-stubs-crash.ll?rev=142869&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/gv-stubs-crash.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/gv-stubs-crash.ll Mon Oct 24 18:05:43 2011
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=pic
+; <rdar://problem/10336715>
+
+ at Exn = external hidden unnamed_addr constant { i8*, i8* }
+
+define hidden void @func(i32* %this, i32* %e) optsize align 2 {
+  %e.ld = load i32* %e, align 4
+  %inv = invoke zeroext i1 @func2(i32* %this, i32 %e.ld) optsize
+          to label %ret unwind label %lpad
+
+ret:
+  ret void
+
+lpad:
+  %lp = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*)
+          catch i8* bitcast ({ i8*, i8* }* @Exn to i8*)
+  br label %.loopexit4
+
+.loopexit4:
+  %exn = call i8* @__cxa_allocate_exception(i32 8) nounwind
+  call void @__cxa_throw(i8* %exn, i8* bitcast ({ i8*, i8* }* @Exn to i8*), i8* bitcast (void (i32*)* @dtor to i8*)) noreturn
+  unreachable
+
+resume:
+  resume { i8*, i32 } %lp
+}
+
+declare hidden zeroext i1 @func2(i32*, i32) optsize align 2
+
+declare i8* @__cxa_allocate_exception(i32)
+
+declare i32 @__gxx_personality_sj0(...)
+
+declare void @dtor(i32*) optsize
+
+declare void @__cxa_throw(i8*, i8*, i8*)



From eli.friedman at gmail.com  Mon Oct 24 18:08:53 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 24 Oct 2011 23:08:53 -0000
Subject: [llvm-commits] [llvm] r142871 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vstlane.ll
Message-ID: <20111024230853.26297312800A@llvm.org>

Author: efriedma
Date: Mon Oct 24 18:08:52 2011
New Revision: 142871

URL: http://llvm.org/viewvc/llvm-project?rev=142871&view=rev
Log:
Don't crash on variable insertelement on ARM.  PR10258.


Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/vstlane.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142871&r1=142870&r2=142871&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Oct 24 18:08:52 2011
@@ -108,6 +108,7 @@
   EVT ElemTy = VT.getVectorElementType();
   if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
     setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
+  setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
   setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
   if (ElemTy != MVT::i32) {
     setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
@@ -4453,6 +4454,15 @@
   return SDValue();
 }
 
+static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
+  // INSERT_VECTOR_ELT is legal only for immediate indexes.
+  SDValue Lane = Op.getOperand(2);
+  if (!isa<ConstantSDNode>(Lane))
+    return SDValue();
+
+  return Op;
+}
+
 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
   // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
   SDValue Lane = Op.getOperand(1);
@@ -4975,6 +4985,7 @@
   case ISD::SETCC:         return LowerVSETCC(Op, DAG);
   case ISD::BUILD_VECTOR:  return LowerBUILD_VECTOR(Op, DAG, Subtarget);
   case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
+  case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
   case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
   case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
   case ISD::FLT_ROUNDS_:   return LowerFLT_ROUNDS_(Op, DAG);

Modified: llvm/trunk/test/CodeGen/ARM/vstlane.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vstlane.ll?rev=142871&r1=142870&r2=142871&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vstlane.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vstlane.ll Mon Oct 24 18:08:52 2011
@@ -358,6 +358,13 @@
 	ret void
 }
 
+; Make sure this doesn't crash; PR10258
+define <8 x i16> @variable_insertelement(<8 x i16> %a, i16 %b, i32 %c) nounwind readnone {
+;CHECK: variable_insertelement:
+    %r = insertelement <8 x i16> %a, i16 %b, i32 %c
+    ret <8 x i16> %r
+}
+
 declare void @llvm.arm.neon.vst4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind
 declare void @llvm.arm.neon.vst4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
 declare void @llvm.arm.neon.vst4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind



From resistor at mac.com  Mon Oct 24 18:20:07 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 24 Oct 2011 23:20:07 -0000
Subject: [llvm-commits] [llvm] r142875 - in /llvm/trunk:
 include/llvm/Object/MachO.h lib/Object/MachOObjectFile.cpp
Message-ID: <20111024232007.48CFF312800A@llvm.org>

Author: resistor
Date: Mon Oct 24 18:20:07 2011
New Revision: 142875

URL: http://llvm.org/viewvc/llvm-project?rev=142875&view=rev
Log:
More fixes and improvements to MachO relocation pretty-printing, particular for x86 and x86_64 relocations with addends.

Modified:
    llvm/trunk/include/llvm/Object/MachO.h
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/include/llvm/Object/MachO.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachO.h?rev=142875&r1=142874&r2=142875&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/MachO.h (original)
+++ llvm/trunk/include/llvm/Object/MachO.h Mon Oct 24 18:20:07 2011
@@ -108,6 +108,8 @@
   void getRelocation(DataRefImpl Rel,
                      InMemoryStruct<macho::RelocationEntry> &Res) const;
   std::size_t getSectionIndex(DataRefImpl Sec) const;
+
+  error_code getRelocationTargetName(uint32_t Idx, StringRef &S) const;
 };
 
 }

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=142875&r1=142874&r2=142875&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Mon Oct 24 18:20:07 2011
@@ -666,14 +666,18 @@
     }
     case Triple::x86_64: {
       const char* Table[] =  {
+        "X86_64_RELOC_UNSIGNED",
+        "X86_64_RELOC_SIGNED",
         "X86_64_RELOC_BRANCH",
         "X86_64_RELOC_GOT_LOAD",
         "X86_64_RELOC_GOT",
-        "X86_64_RELOC_SIGNED",
-        "X86_64_RELOC_UNSIGNED",
-        "X86_64_RELOC_SUBTRACTOR" };
+        "X86_64_RELOC_SUBTRACTOR",
+        "X86_64_RELOC_SIGNED_1",
+        "X86_64_RELOC_SIGNED_2",
+        "X86_64_RELOC_SIGNED_4",
+        "X86_64_RELOC_TLV" };
 
-      if (r_type > 5)
+      if (r_type > 9)
         res = "Unknown";
       else
         res = Table[r_type];
@@ -748,46 +752,138 @@
   }
   return object_error::success;
 }
+
+// Helper to advance a section or symbol iterator multiple increments at a time.
+template<class T>
+error_code advance(T &it, size_t Val) {
+  error_code ec;
+  while (Val--) {
+    it.increment(ec);
+  }
+  return ec;
+}
+
+template<class T>
+void advanceTo(T &it, size_t Val) {
+  if (error_code ec = advance(it, Val))
+    report_fatal_error(ec.message());
+}
+
+error_code
+MachOObjectFile::getRelocationTargetName(uint32_t Idx, StringRef &S) const {
+  bool isExtern = (Idx >> 27) & 1;
+  uint32_t Val = Idx & 0xFFFFFF;
+  error_code ec;
+
+  if (isExtern) {
+    symbol_iterator SI = begin_symbols();
+    advanceTo(SI, Val);
+    ec = SI->getName(S);
+  } else {
+    section_iterator SI = begin_sections();
+    advanceTo(SI, Val);
+    ec = SI->getName(S);
+  }
+
+  return ec;
+}
+
 error_code MachOObjectFile::getRelocationValueString(DataRefImpl Rel,
                                           SmallVectorImpl<char> &Result) const {
   InMemoryStruct<macho::RelocationEntry> RE;
   getRelocation(Rel, RE);
 
-  std::string fmtbuf;
-  raw_string_ostream fmt(fmtbuf);
+  std::string addend;
+  raw_string_ostream addend_fmt(addend);
 
-  bool isExtern = (RE->Word1 >> 27) & 1;
-  if (isExtern) {
-    uint32_t Val = (RE->Word1 & 0xFFFFFF);
-    symbol_iterator SI = begin_symbols();
+  bool isPCRel = (RE->Word1 >> 25) & 1;
+  unsigned Type = (RE->Word1 >> 28) & 0xF;
 
-    error_code ec;
-    while (Val--) {
-      SI.increment(ec);
-      if (ec) report_fatal_error(ec.message());
+  // Determine any addends that should be displayed with the relocation.
+  // These require decoding the relocation type, which is triple-specific.
+  unsigned Arch = getArch();
+
+  // X86_64 has entirely custom relocation types.
+  if (Arch == Triple::x86_64) {
+    switch (Type) {
+      case 5: { // X86_64_RELOC_SUBTRACTOR
+        RelocationRef NextReloc;
+        if (error_code ec = getRelocationNext(Rel, NextReloc))
+          report_fatal_error(ec.message());
+
+        uint32_t SucessorType;
+        if (error_code ec = NextReloc.getType(SucessorType))
+          report_fatal_error(ec.message());
+
+        // X86_64_SUBTRACTOR must be followed by a relocation of type
+        // X86_64_RELOC_UNSIGNED.
+        unsigned RType = (SucessorType >> 28) & 0xF;
+        if (RType != 0)
+          report_fatal_error("Expected X86_64_RELOC_UNSIGNED after "
+                             "X86_64_RELOC_SUBTRACTOR.");
+
+        StringRef Name;
+        if (error_code ec = getRelocationTargetName(SucessorType, Name))
+          report_fatal_error(ec.message());
+
+        addend_fmt << "-" << Name;
+      }
+      case 6: // X86_64_RELOC_SIGNED1
+        addend_fmt << "-1";
+        break;
+      case 7: // X86_64_RELOC_SIGNED2
+        addend_fmt << "-2";
+        break;
+      case 8: // X86_64_RELOC_SIGNED4
+        addend_fmt << "-4";
+        break;
     }
+  }
 
-    StringRef SymName;
-    if ((ec = SI->getName(SymName)))
-      report_fatal_error(ec.message());
+  // X86 and ARM share some relocation types in common.
+  if (Arch == Triple::x86 || Arch == Triple::arm) {
+    switch (Type) {
+      case 1: // GENERIC_RELOC_PAIR - prints no info
+        return object_error::success;
+      case 2:   // GENERIC_RELOC_SECTDIFF
+      case 4: { // GENERIC_RELOC_LOCAL_SECTDIFF
+        RelocationRef NextReloc;
+        if (error_code ec = getRelocationNext(Rel, NextReloc))
+          report_fatal_error(ec.message());
+
+        uint32_t SucessorType;
+        if (error_code ec = NextReloc.getType(SucessorType))
+          report_fatal_error(ec.message());
+
+        // X86 sect diff's must be followed by a relocation of type
+        // GENERIC_RELOC_PAIR.
+        unsigned RType = (SucessorType >> 28) & 0xF;
+        if (RType != 1)
+          report_fatal_error("Expected GENERIC_RELOC_PAIR after "
+                             "GENERIC_RELOC_SECTDIFF or "
+                             "GENERIC_RELOC_LOCAL_SECTDIFF.");
+
+        StringRef Name;
+        if (error_code ec = getRelocationTargetName(SucessorType, Name))
+          report_fatal_error(ec.message());
 
-    fmt << SymName;
-  } else {
-    uint32_t Val = (RE->Word1 & 0xFFFFFF);
-    section_iterator SI = begin_sections();
+        addend_fmt << "-" << Name;
 
-    error_code ec;
-    while (Val--) {
-      SI.increment(ec);
-      if (ec) report_fatal_error(ec.message());
+      }
     }
+  }
 
-    StringRef SectName;
-    if ((ec = SI->getName(SectName)))
-      report_fatal_error(ec.message());
+  addend_fmt.flush();
 
-    fmt << SectName;
-  }
+  std::string fmtbuf;
+  raw_string_ostream fmt(fmtbuf);
+
+  StringRef Name;
+  if (error_code ec = getRelocationTargetName(RE->Word1, Name))
+    report_fatal_error(ec.message());
+
+  fmt << Name << addend;
+  if (isPCRel) fmt << "-P";
 
   fmt.flush();
   Result.append(fmtbuf.begin(), fmtbuf.end());



From grosbach at apple.com  Mon Oct 24 18:26:05 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 24 Oct 2011 23:26:05 -0000
Subject: [llvm-commits] [llvm] r142876 - in /llvm/trunk:
 lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMExpandPseudoInsts.cpp
 lib/Target/ARM/ARMInstrNEON.td
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/ARM/neon-vld-encoding.s
Message-ID: <20111024232605.9D666312800A@llvm.org>

Author: grosbach
Date: Mon Oct 24 18:26:05 2011
New Revision: 142876

URL: http://llvm.org/viewvc/llvm-project?rev=142876&view=rev
Log:
ARM assembly parsing and encoding for VLD1 w/ writeback.

Three entry register list variation.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/ARM/neon-vld-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=142876&r1=142875&r2=142876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Oct 24 18:26:05 2011
@@ -2428,7 +2428,8 @@
     case ARM::VLD3d8_UPD:
     case ARM::VLD3d16_UPD:
     case ARM::VLD3d32_UPD:
-    case ARM::VLD1d64T_UPD:
+    case ARM::VLD1d64Twb_fixed:
+    case ARM::VLD1d64Twb_register:
     case ARM::VLD3q8_UPD:
     case ARM::VLD3q16_UPD:
     case ARM::VLD3q32_UPD:
@@ -2593,7 +2594,6 @@
     case ARM::VLD3d8Pseudo_UPD:
     case ARM::VLD3d16Pseudo_UPD:
     case ARM::VLD3d32Pseudo_UPD:
-    case ARM::VLD1d64TPseudo_UPD:
     case ARM::VLD3q8Pseudo_UPD:
     case ARM::VLD3q16Pseudo_UPD:
     case ARM::VLD3q32Pseudo_UPD:

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=142876&r1=142875&r2=142876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Oct 24 18:26:05 2011
@@ -145,8 +145,6 @@
 { ARM::VLD1d64QPseudo,      ARM::VLD1d64Q,     true,  false, SingleSpc,  4, 1 ,false},
 { ARM::VLD1d64QPseudo_UPD,  ARM::VLD1d64Q_UPD, true,  true,  SingleSpc,  4, 1 ,false},
 { ARM::VLD1d64TPseudo,      ARM::VLD1d64T,     true,  false, SingleSpc,  3, 1 ,false},
-{ ARM::VLD1d64TPseudo_UPD,  ARM::VLD1d64T_UPD, true,  true,  SingleSpc,  3, 1 ,false},
-
 { ARM::VLD1q16Pseudo,       ARM::VLD1q16,      true,  false, SingleSpc,  2, 4 ,false},
 { ARM::VLD1q16PseudoWB_fixed, ARM::VLD1q16wb_fixed,true,false,SingleSpc, 2, 4 ,false},
 { ARM::VLD1q16PseudoWB_register, ARM::VLD1q16wb_register, true, true, SingleSpc, 2, 4 ,false},
@@ -1099,7 +1097,6 @@
     case ARM::VLD3d8Pseudo_UPD:
     case ARM::VLD3d16Pseudo_UPD:
     case ARM::VLD3d32Pseudo_UPD:
-    case ARM::VLD1d64TPseudo_UPD:
     case ARM::VLD3q8Pseudo_UPD:
     case ARM::VLD3q16Pseudo_UPD:
     case ARM::VLD3q32Pseudo_UPD:

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142876&r1=142875&r2=142876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 24 18:26:05 2011
@@ -383,12 +383,24 @@
   let Inst{4} = Rn{4};
   let DecoderMethod = "DecodeVLDInstruction";
 }
-class VLD1D3WB<bits<4> op7_4, string Dt>
-  : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
-          (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
-          "$Vd, $Rn$Rm", "$Rn.addr = $wb", []> {
-  let Inst{4} = Rn{4};
-  let DecoderMethod = "DecodeVLDInstruction";
+multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
+  def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
+                    (ins addrmode6:$Rn), IIC_VLD1x2u,
+                     "vld1", Dt, "$Vd, $Rn!",
+                     "$Rn.addr = $wb", []> {
+    let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
+    let Inst{5-4} = Rn{5-4};
+    let DecoderMethod = "DecodeVLDInstruction";
+    let AsmMatchConverter = "cvtVLDwbFixed";
+  }
+  def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
+                        (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
+                        "vld1", Dt, "$Vd, $Rn, $Rm",
+                        "$Rn.addr = $wb", []> {
+    let Inst{5-4} = Rn{5-4};
+    let DecoderMethod = "DecodeVLDInstruction";
+    let AsmMatchConverter = "cvtVLDwbRegister";
+  }
 }
 
 def VLD1d8T      : VLD1D3<{0,0,0,?}, "8">;
@@ -396,13 +408,12 @@
 def VLD1d32T     : VLD1D3<{1,0,0,?}, "32">;
 def VLD1d64T     : VLD1D3<{1,1,0,?}, "64">;
 
-def VLD1d8T_UPD  : VLD1D3WB<{0,0,0,?}, "8">;
-def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
-def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
-def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
+defm VLD1d8Twb  : VLD1D3WB<{0,0,0,?}, "8">;
+defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
+defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
+defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
 
-def VLD1d64TPseudo     : VLDQQPseudo<IIC_VLD1x3>;
-def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
+def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
 
 // ...with 4 registers
 class VLD1D4<bits<4> op7_4, string Dt>

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=142876&r1=142875&r2=142876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Oct 24 18:26:05 2011
@@ -2070,10 +2070,14 @@
     case ARM::VLD1q16wb_register:
     case ARM::VLD1q32wb_register:
     case ARM::VLD1q64wb_register:
-    case ARM::VLD1d8T_UPD:
-    case ARM::VLD1d16T_UPD:
-    case ARM::VLD1d32T_UPD:
-    case ARM::VLD1d64T_UPD:
+    case ARM::VLD1d8Twb_fixed:
+    case ARM::VLD1d8Twb_register:
+    case ARM::VLD1d16Twb_fixed:
+    case ARM::VLD1d16Twb_register:
+    case ARM::VLD1d32Twb_fixed:
+    case ARM::VLD1d32Twb_register:
+    case ARM::VLD1d64Twb_fixed:
+    case ARM::VLD1d64Twb_register:
     case ARM::VLD1d8Q_UPD:
     case ARM::VLD1d16Q_UPD:
     case ARM::VLD1d32Q_UPD:

Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=142876&r1=142875&r2=142876&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Mon Oct 24 18:26:05 2011
@@ -35,6 +35,16 @@
 	vld1.32	{d16, d17}, [r0], r5
 	vld1.64	{d16, d17}, [r0], r5
 
+	vld1.8 {d1, d2, d3}, [r3]!
+	vld1.16 {d4, d5, d6}, [r3, :64]!
+	vld1.32 {d5, d6, d7}, [r3]!
+	vld1.64 {d6, d7, d8}, [r3, :64]!
+
+	vld1.8 {d1, d2, d3}, [r3], r6
+	vld1.16 {d4, d5, d6}, [r3, :64], r6
+	vld1.32 {d5, d6, d7}, [r3], r6
+	vld1.64 {d6, d7, d8}, [r3, :64], r6
+
 @ CHECK: vld1.8 {d16}, [r0, :64]        @ encoding: [0x1f,0x07,0x60,0xf4]
 @ CHECK: vld1.16 {d16}, [r0]            @ encoding: [0x4f,0x07,0x60,0xf4]
 @ CHECK: vld1.32 {d16}, [r0]            @ encoding: [0x8f,0x07,0x60,0xf4]
@@ -70,6 +80,16 @@
 @ CHECK: vld1.32 {d16, d17}, [r0], r5   @ encoding: [0x85,0x0a,0x60,0xf4]
 @ CHECK: vld1.64 {d16, d17}, [r0], r5   @ encoding: [0xc5,0x0a,0x60,0xf4]
 
+@ CHECK: vld1.8	{d1, d2, d3}, [r3]!     @ encoding: [0x0d,0x16,0x23,0xf4]
+@ CHECK: vld1.16 {d4, d5, d6}, [r3, :64]! @ encoding: [0x5d,0x46,0x23,0xf4]
+@ CHECK: vld1.32 {d5, d6, d7}, [r3]!     @ encoding: [0x8d,0x56,0x23,0xf4]
+@ CHECK: vld1.64 {d6, d7, d8}, [r3, :64]! @ encoding: [0xdd,0x66,0x23,0xf4]
+
+@ CHECK: vld1.8	{d1, d2, d3}, [r3], r6  @ encoding: [0x06,0x16,0x23,0xf4]
+@ CHECK: vld1.16 {d4, d5, d6}, [r3, :64], r6 @ encoding: [0x56,0x46,0x23,0xf4]
+@ CHECK: vld1.32 {d5, d6, d7}, [r3], r6  @ encoding: [0x86,0x56,0x23,0xf4]
+@ CHECK: vld1.64 {d6, d7, d8}, [r3, :64], r6 @ encoding: [0xd6,0x66,0x23,0xf4]
+
 
 	vld2.8	{d16, d17}, [r0, :64]
 	vld2.16	{d16, d17}, [r0, :128]



From grosbach at apple.com  Mon Oct 24 18:40:47 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 24 Oct 2011 23:40:47 -0000
Subject: [llvm-commits] [llvm] r142877 - in /llvm/trunk/lib/Target/ARM:
 ARMBaseInstrInfo.cpp ARMExpandPseudoInsts.cpp ARMInstrNEON.td
Message-ID: <20111024234047.2AFBD312800A@llvm.org>

Author: grosbach
Date: Mon Oct 24 18:40:46 2011
New Revision: 142877

URL: http://llvm.org/viewvc/llvm-project?rev=142877&view=rev
Log:
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=142877&r1=142876&r2=142877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Oct 24 18:40:46 2011
@@ -2610,7 +2610,6 @@
     case ARM::VLD4d8Pseudo_UPD:
     case ARM::VLD4d16Pseudo_UPD:
     case ARM::VLD4d32Pseudo_UPD:
-    case ARM::VLD1d64QPseudo_UPD:
     case ARM::VLD4q8Pseudo_UPD:
     case ARM::VLD4q16Pseudo_UPD:
     case ARM::VLD4q32Pseudo_UPD:

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=142877&r1=142876&r2=142877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Oct 24 18:40:46 2011
@@ -143,7 +143,6 @@
 { ARM::VLD1LNq8Pseudo_UPD,  ARM::VLD1LNd8_UPD,  true, true,  EvenDblSpc, 1, 8 ,true},
 
 { ARM::VLD1d64QPseudo,      ARM::VLD1d64Q,     true,  false, SingleSpc,  4, 1 ,false},
-{ ARM::VLD1d64QPseudo_UPD,  ARM::VLD1d64Q_UPD, true,  true,  SingleSpc,  4, 1 ,false},
 { ARM::VLD1d64TPseudo,      ARM::VLD1d64T,     true,  false, SingleSpc,  3, 1 ,false},
 { ARM::VLD1q16Pseudo,       ARM::VLD1q16,      true,  false, SingleSpc,  2, 4 ,false},
 { ARM::VLD1q16PseudoWB_fixed, ARM::VLD1q16wb_fixed,true,false,SingleSpc, 2, 4 ,false},
@@ -1113,7 +1112,6 @@
     case ARM::VLD4d8Pseudo_UPD:
     case ARM::VLD4d16Pseudo_UPD:
     case ARM::VLD4d32Pseudo_UPD:
-    case ARM::VLD1d64QPseudo_UPD:
     case ARM::VLD4q8Pseudo_UPD:
     case ARM::VLD4q16Pseudo_UPD:
     case ARM::VLD4q32Pseudo_UPD:

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142877&r1=142876&r2=142877&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 24 18:40:46 2011
@@ -444,7 +444,6 @@
 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
 
 def VLD1d64QPseudo     : VLDQQPseudo<IIC_VLD1x4>;
-def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
 
 //   VLD2     : Vector Load (multiple 2-element structures)
 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>



From gohman at apple.com  Mon Oct 24 18:48:32 2011
From: gohman at apple.com (Dan Gohman)
Date: Mon, 24 Oct 2011 23:48:32 -0000
Subject: [llvm-commits] [llvm] r142878 - in /llvm/trunk: CMakeLists.txt
 autoconf/configure.ac configure docs/CodeGenerator.html
 docs/ReleaseNotes.html include/llvm/ADT/Triple.h
 include/llvm/CodeGen/SelectionDAGISel.h lib/Support/Triple.cpp
 lib/Target/SystemZ/ projects/sample/autoconf/configure.ac
 projects/sample/configure test/CodeGen/SystemZ/
 utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
 utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
Message-ID: <20111024234832.C162E312800A@llvm.org>

Author: djg
Date: Mon Oct 24 18:48:32 2011
New Revision: 142878

URL: http://llvm.org/viewvc/llvm-project?rev=142878&view=rev
Log:
Remove the SystemZ backend.

Removed:
    llvm/trunk/lib/Target/SystemZ/
    llvm/trunk/test/CodeGen/SystemZ/
Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/configure
    llvm/trunk/docs/CodeGenerator.html
    llvm/trunk/docs/ReleaseNotes.html
    llvm/trunk/include/llvm/ADT/Triple.h
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
    llvm/trunk/lib/Support/Triple.cpp
    llvm/trunk/projects/sample/autoconf/configure.ac
    llvm/trunk/projects/sample/configure
    llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
    llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Mon Oct 24 18:48:32 2011
@@ -76,7 +76,6 @@
   PowerPC
   PTX
   Sparc
-  SystemZ
   X86
   XCore
   )

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Mon Oct 24 18:48:32 2011
@@ -357,7 +357,6 @@
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
   msp430-*)               llvm_cv_target_arch="MSP430" ;;
-  s390x-*)                llvm_cv_target_arch="SystemZ" ;;
   bfin-*)                 llvm_cv_target_arch="Blackfin" ;;
   mblaze-*)               llvm_cv_target_arch="MBlaze" ;;
   ptx-*)                  llvm_cv_target_arch="PTX" ;;
@@ -494,7 +493,6 @@
     Mips)        AC_SUBST(TARGET_HAS_JIT,1) ;;
     XCore)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     MSP430)      AC_SUBST(TARGET_HAS_JIT,0) ;;
-    SystemZ)     AC_SUBST(TARGET_HAS_JIT,0) ;;
     Blackfin)    AC_SUBST(TARGET_HAS_JIT,0) ;;
     MBlaze)      AC_SUBST(TARGET_HAS_JIT,0) ;;
     PTX)         AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -608,13 +606,13 @@
 AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
     [Build specific host targets: all or target1,target2,... Valid targets are:
      host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu,
-     xcore, msp430, systemz, blackfin, ptx, cbe, and cpp (default=all)]),,
+     xcore, msp430, blackfin, ptx, cbe, and cpp (default=all)]),,
     enableval=all)
 if test "$enableval" = host-only ; then
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 SystemZ Blackfin CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 Blackfin CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -627,7 +625,6 @@
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
         xcore)    TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
         msp430)   TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-        systemz)  TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
         blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
         cbe)      TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
         cpp)      TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
@@ -645,7 +642,6 @@
             CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
             XCore)       TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
             MSP430)      TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-            s390x)       TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
             Blackfin)    TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
             PTX)         TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
             *)       AC_MSG_ERROR([Can not set target to build]) ;;

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Mon Oct 24 18:48:32 2011
@@ -1416,7 +1416,7 @@
   --enable-targets        Build specific host targets: all or
                           target1,target2,... Valid targets are: host, x86,
                           x86_64, sparc, powerpc, alpha, arm, mips, spu,
-                          xcore, msp430, systemz, blackfin, ptx, cbe, and cpp
+                          xcore, msp430, blackfin, ptx, cbe, and cpp
                           (default=all)
   --enable-cbe-printf-a   Enable C Backend output with hex floating point via
                           %a (default is YES)
@@ -3880,7 +3880,6 @@
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
   msp430-*)               llvm_cv_target_arch="MSP430" ;;
-  s390x-*)                llvm_cv_target_arch="SystemZ" ;;
   bfin-*)                 llvm_cv_target_arch="Blackfin" ;;
   mblaze-*)               llvm_cv_target_arch="MBlaze" ;;
   ptx-*)                  llvm_cv_target_arch="PTX" ;;
@@ -5085,8 +5084,6 @@
  ;;
     MSP430)      TARGET_HAS_JIT=0
  ;;
-    SystemZ)     TARGET_HAS_JIT=0
- ;;
     Blackfin)    TARGET_HAS_JIT=0
  ;;
     MBlaze)      TARGET_HAS_JIT=0
@@ -5277,7 +5274,7 @@
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 SystemZ Blackfin CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 Blackfin CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5290,7 +5287,6 @@
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
         xcore)    TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
         msp430)   TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-        systemz)  TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
         blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
         cbe)      TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
         cpp)      TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
@@ -5308,7 +5304,6 @@
             CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
             XCore)       TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
             MSP430)      TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-            s390x)       TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
             Blackfin)    TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
             PTX)         TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
             *)       { { echo "$as_me:$LINENO: error: Can not set target to build" >&5

Modified: llvm/trunk/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/docs/CodeGenerator.html (original)
+++ llvm/trunk/docs/CodeGenerator.html Mon Oct 24 18:48:32 2011
@@ -2217,7 +2217,6 @@
     <th>PTX</th>
     <th>PowerPC</th>
     <th>Sparc</th>
-    <th>SystemZ</th>
     <th>X86</th>
     <th>XCore</th>
   </tr>
@@ -2234,7 +2233,6 @@
   <td class="no"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="yes"></td> <!-- Sparc -->
-  <td class="unknown"></td> <!-- SystemZ -->
   <td class="yes"></td> <!-- X86 -->
   <td class="unknown"></td> <!-- XCore -->
 </tr>
@@ -2251,7 +2249,6 @@
   <td class="no"></td> <!-- PTX -->
   <td class="no"></td> <!-- PowerPC -->
   <td class="no"></td> <!-- Sparc -->
-  <td class="no"></td> <!-- SystemZ -->
   <td class="yes"></td> <!-- X86 -->
   <td class="no"></td> <!-- XCore -->
 </tr>
@@ -2268,7 +2265,6 @@
   <td class="no"></td> <!-- PTX -->
   <td class="no"></td> <!-- PowerPC -->
   <td class="no"></td> <!-- Sparc -->
-  <td class="no"></td> <!-- SystemZ -->
   <td class="yes"></td> <!-- X86 -->
   <td class="no"></td> <!-- XCore -->
 </tr>
@@ -2285,7 +2281,6 @@
   <td class="unknown"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="unknown"></td> <!-- Sparc -->
-  <td class="unknown"></td> <!-- SystemZ -->
   <td class="yes"></td> <!-- X86 -->
   <td class="unknown"></td> <!-- XCore -->
 </tr>
@@ -2302,7 +2297,6 @@
   <td class="unknown"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="unknown"></td> <!-- Sparc -->
-  <td class="unknown"></td> <!-- SystemZ -->
   <td class="yes"></td> <!-- X86 -->
   <td class="unknown"></td> <!-- XCore -->
 </tr>
@@ -2319,7 +2313,6 @@
   <td class="no"></td> <!-- PTX -->
   <td class="no"></td> <!-- PowerPC -->
   <td class="no"></td> <!-- Sparc -->
-  <td class="no"></td> <!-- SystemZ -->
   <td class="yes"></td> <!-- X86 -->
   <td class="no"></td> <!-- XCore -->
 </tr>
@@ -2336,7 +2329,6 @@
   <td class="unknown"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="unknown"></td> <!-- Sparc -->
-  <td class="unknown"></td> <!-- SystemZ -->
   <td class="yes"></td> <!-- X86 -->
   <td class="unknown"></td> <!-- XCore -->
 </tr>

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Oct 24 18:48:32 2011
@@ -759,7 +759,7 @@
 href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVMdev list</a>.</p>
 
 <ul>
-<li>The Alpha, Blackfin, CellSPU, MicroBlaze, MSP430, MIPS, PTX, SystemZ
+<li>The Alpha, Blackfin, CellSPU, MicroBlaze, MSP430, MIPS, PTX,
     and XCore backends are experimental.</li>
 <li><tt>llc</tt> "<tt>-filetype=obj</tt>" is experimental on all targets
     other than darwin and ELF X86 systems.</li>

Modified: llvm/trunk/include/llvm/ADT/Triple.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/Triple.h (original)
+++ llvm/trunk/include/llvm/ADT/Triple.h Mon Oct 24 18:48:32 2011
@@ -56,7 +56,6 @@
     ppc64,   // PPC64: powerpc64, ppu
     sparc,   // Sparc: sparc
     sparcv9, // Sparcv9: Sparcv9
-    systemz, // SystemZ: s390x
     tce,     // TCE (http://tce.cs.tut.fi/): tce
     thumb,   // Thumb: thumb, thumbv.*
     x86,     // X86: i[3-9]86

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Oct 24 18:48:32 2011
@@ -92,7 +92,7 @@
 
   /// IsLegalToFold - Returns true if the specific operand node N of
   /// U can be folded during instruction selection that starts at Root.
-  /// FIXME: This is a static member function because the MSP430/SystemZ/X86
+  /// FIXME: This is a static member function because the MSP430/X86
   /// targets, which uses it during isel.  This could become a proper member.
   static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
                             CodeGenOpt::Level OptLevel,

Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Mon Oct 24 18:48:32 2011
@@ -31,7 +31,6 @@
   case ppc:     return "powerpc";
   case sparc:   return "sparc";
   case sparcv9: return "sparcv9";
-  case systemz: return "s390x";
   case tce:     return "tce";
   case thumb:   return "thumb";
   case x86:     return "i386";
@@ -165,8 +164,6 @@
     return sparc;
   if (Name == "sparcv9")
     return sparcv9;
-  if (Name == "systemz")
-    return systemz;
   if (Name == "tce")
     return tce;
   if (Name == "thumb")
@@ -316,8 +313,6 @@
     return sparc;
   else if (ArchName == "sparcv9")
     return sparcv9;
-  else if (ArchName == "s390x")
-    return systemz;
   else if (ArchName == "tce")
     return tce;
   else if (ArchName == "xcore")

Modified: llvm/trunk/projects/sample/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/autoconf/configure.ac?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/projects/sample/autoconf/configure.ac (original)
+++ llvm/trunk/projects/sample/autoconf/configure.ac Mon Oct 24 18:48:32 2011
@@ -301,7 +301,6 @@
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
   msp430-*)               llvm_cv_target_arch="MSP430" ;;
-  s390x-*)                llvm_cv_target_arch="SystemZ" ;;
   bfin-*)                 llvm_cv_target_arch="Blackfin" ;;
   mblaze-*)               llvm_cv_target_arch="MBlaze" ;;
   ptx-*)                  llvm_cv_target_arch="PTX" ;;
@@ -438,7 +437,6 @@
     Mips)        AC_SUBST(TARGET_HAS_JIT,1) ;;
     XCore)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     MSP430)      AC_SUBST(TARGET_HAS_JIT,0) ;;
-    SystemZ)     AC_SUBST(TARGET_HAS_JIT,0) ;;
     Blackfin)    AC_SUBST(TARGET_HAS_JIT,0) ;;
     MBlaze)      AC_SUBST(TARGET_HAS_JIT,0) ;;
     PTX)         AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -552,13 +550,13 @@
 AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
     [Build specific host targets: all or target1,target2,... Valid targets are:
      host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu,
-     xcore, msp430, systemz, blackfin, ptx, cbe, and cpp (default=all)]),,
+     xcore, msp430, blackfin, ptx, cbe, and cpp (default=all)]),,
     enableval=all)
 if test "$enableval" = host-only ; then
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 SystemZ Blackfin CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 Blackfin CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -571,7 +569,6 @@
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
         xcore)    TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
         msp430)   TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-        systemz)  TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
         blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
         cbe)      TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
         cpp)      TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
@@ -589,7 +586,6 @@
             CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
             XCore)       TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
             MSP430)      TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-            s390x)       TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
             Blackfin)    TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
             PTX)         TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
             *)       AC_MSG_ERROR([Can not set target to build]) ;;

Modified: llvm/trunk/projects/sample/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/configure?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/projects/sample/configure (original)
+++ llvm/trunk/projects/sample/configure Mon Oct 24 18:48:32 2011
@@ -1402,7 +1402,7 @@
   --enable-targets        Build specific host targets: all or
                           target1,target2,... Valid targets are: host, x86,
                           x86_64, sparc, powerpc, alpha, arm, mips, spu,
-                          xcore, msp430, systemz, blackfin, ptx, cbe, and cpp
+                          xcore, msp430, blackfin, ptx, cbe, and cpp
                           (default=all)
   --enable-cbe-printf-a   Enable C Backend output with hex floating point via
                           %a (default is YES)
@@ -3845,7 +3845,6 @@
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
   msp430-*)               llvm_cv_target_arch="MSP430" ;;
-  s390x-*)                llvm_cv_target_arch="SystemZ" ;;
   bfin-*)                 llvm_cv_target_arch="Blackfin" ;;
   mblaze-*)               llvm_cv_target_arch="MBlaze" ;;
   ptx-*)                  llvm_cv_target_arch="PTX" ;;
@@ -5050,8 +5049,6 @@
  ;;
     MSP430)      TARGET_HAS_JIT=0
  ;;
-    SystemZ)     TARGET_HAS_JIT=0
- ;;
     Blackfin)    TARGET_HAS_JIT=0
  ;;
     MBlaze)      TARGET_HAS_JIT=0
@@ -5242,7 +5239,7 @@
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 SystemZ Blackfin CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 Blackfin CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5255,7 +5252,6 @@
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
         xcore)    TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
         msp430)   TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-        systemz)  TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
         blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
         cbe)      TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
         cpp)      TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
@@ -5273,7 +5269,6 @@
             CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
             XCore)       TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
             MSP430)      TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-            s390x)       TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
             Blackfin)    TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
             PTX)         TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
             *)       { { echo "$as_me:$LINENO: error: Can not set target to build" >&5

Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp Mon Oct 24 18:48:32 2011
@@ -2,7 +2,7 @@
 # Do not edit here.  If you wish to override these values
 # edit the last section
 set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
 set llvmgcc_langs "c,c++,objc,obj-c++"
 set prcontext "/usr/bin/tclsh8.4 /Volumes/Data/ddunbar/llvm/test/Scripts/prcontext.tcl"
 set llvmtoolsdir "/Users/ddunbar/llvm.obj.64/Debug/bin"

Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp?rev=142878&r1=142877&r2=142878&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp Mon Oct 24 18:48:32 2011
@@ -2,7 +2,7 @@
 # Do not edit here.  If you wish to override these values
 # edit the last section
 set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
 set llvmgcc_langs "c,c++,objc,obj-c++"
 set prcontext "/usr/bin/tclsh8.4 /Volumes/Data/ddunbar/llvm/test/Scripts/prcontext.tcl"
 set llvmtoolsdir "/Users/ddunbar/llvm.obj.64/Debug/bin"



From gohman at apple.com  Mon Oct 24 19:05:43 2011
From: gohman at apple.com (Dan Gohman)
Date: Tue, 25 Oct 2011 00:05:43 -0000
Subject: [llvm-commits] [llvm] r142880 - in /llvm/trunk: CMakeLists.txt
 autoconf/configure.ac configure docs/CodeGenerator.html
 docs/ReleaseNotes.html include/llvm/ADT/Triple.h lib/Support/Triple.cpp
 lib/Target/Blackfin/ projects/sample/autoconf/configure.ac
 projects/sample/configure test/CodeGen/Blackfin/
 utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
 utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
Message-ID: <20111025000543.9415D312800A@llvm.org>

Author: djg
Date: Mon Oct 24 19:05:42 2011
New Revision: 142880

URL: http://llvm.org/viewvc/llvm-project?rev=142880&view=rev
Log:
Remove the Blackfin backend.

Removed:
    llvm/trunk/lib/Target/Blackfin/
    llvm/trunk/test/CodeGen/Blackfin/
Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/configure
    llvm/trunk/docs/CodeGenerator.html
    llvm/trunk/docs/ReleaseNotes.html
    llvm/trunk/include/llvm/ADT/Triple.h
    llvm/trunk/lib/Support/Triple.cpp
    llvm/trunk/projects/sample/autoconf/configure.ac
    llvm/trunk/projects/sample/configure
    llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
    llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=142880&r1=142879&r2=142880&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Mon Oct 24 19:05:42 2011
@@ -66,7 +66,6 @@
 set(LLVM_ALL_TARGETS
   Alpha
   ARM
-  Blackfin
   CBackend
   CellSPU
   CppBackend

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=142880&r1=142879&r2=142880&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Mon Oct 24 19:05:42 2011
@@ -357,7 +357,6 @@
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
   msp430-*)               llvm_cv_target_arch="MSP430" ;;
-  bfin-*)                 llvm_cv_target_arch="Blackfin" ;;
   mblaze-*)               llvm_cv_target_arch="MBlaze" ;;
   ptx-*)                  llvm_cv_target_arch="PTX" ;;
   *)                      llvm_cv_target_arch="Unknown" ;;
@@ -493,7 +492,6 @@
     Mips)        AC_SUBST(TARGET_HAS_JIT,1) ;;
     XCore)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     MSP430)      AC_SUBST(TARGET_HAS_JIT,0) ;;
-    Blackfin)    AC_SUBST(TARGET_HAS_JIT,0) ;;
     MBlaze)      AC_SUBST(TARGET_HAS_JIT,0) ;;
     PTX)         AC_SUBST(TARGET_HAS_JIT,0) ;;
     *)           AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -606,13 +604,13 @@
 AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
     [Build specific host targets: all or target1,target2,... Valid targets are:
      host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu,
-     xcore, msp430, blackfin, ptx, cbe, and cpp (default=all)]),,
+     xcore, msp430, ptx, cbe, and cpp (default=all)]),,
     enableval=all)
 if test "$enableval" = host-only ; then
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 Blackfin CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -625,7 +623,6 @@
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
         xcore)    TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
         msp430)   TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-        blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
         cbe)      TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
         cpp)      TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
         mblaze)   TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
@@ -642,7 +639,6 @@
             CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
             XCore)       TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
             MSP430)      TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-            Blackfin)    TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
             PTX)         TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
             *)       AC_MSG_ERROR([Can not set target to build]) ;;
           esac ;;

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=142880&r1=142879&r2=142880&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Mon Oct 24 19:05:42 2011
@@ -1416,7 +1416,7 @@
   --enable-targets        Build specific host targets: all or
                           target1,target2,... Valid targets are: host, x86,
                           x86_64, sparc, powerpc, alpha, arm, mips, spu,
-                          xcore, msp430, blackfin, ptx, cbe, and cpp
+                          xcore, msp430, ptx, cbe, and cpp
                           (default=all)
   --enable-cbe-printf-a   Enable C Backend output with hex floating point via
                           %a (default is YES)
@@ -3880,7 +3880,6 @@
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
   msp430-*)               llvm_cv_target_arch="MSP430" ;;
-  bfin-*)                 llvm_cv_target_arch="Blackfin" ;;
   mblaze-*)               llvm_cv_target_arch="MBlaze" ;;
   ptx-*)                  llvm_cv_target_arch="PTX" ;;
   *)                      llvm_cv_target_arch="Unknown" ;;
@@ -5287,7 +5286,6 @@
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
         xcore)    TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
         msp430)   TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-        blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
         cbe)      TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
         cpp)      TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
         mblaze)   TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;

Modified: llvm/trunk/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=142880&r1=142879&r2=142880&view=diff
==============================================================================
--- llvm/trunk/docs/CodeGenerator.html (original)
+++ llvm/trunk/docs/CodeGenerator.html Mon Oct 24 19:05:42 2011
@@ -2209,7 +2209,6 @@
     <th>Feature</th>
     <th>ARM</th>
     <th>Alpha</th>
-    <th>Blackfin</th>
     <th>CellSPU</th>
     <th>MBlaze</th>
     <th>MSP430</th>
@@ -2225,7 +2224,6 @@
   <td><a href="#feat_reliable">is generally reliable</a></td>
   <td class="yes"></td> <!-- ARM -->
   <td class="unknown"></td> <!-- Alpha -->
-  <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
@@ -2241,7 +2239,6 @@
   <td><a href="#feat_asmparser">assembly parser</a></td>
   <td class="no"></td> <!-- ARM -->
   <td class="no"></td> <!-- Alpha -->
-  <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
@@ -2257,7 +2254,6 @@
   <td><a href="#feat_disassembler">disassembler</a></td>
   <td class="yes"></td> <!-- ARM -->
   <td class="no"></td> <!-- Alpha -->
-  <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
@@ -2273,7 +2269,6 @@
   <td><a href="#feat_inlineasm">inline asm</a></td>
   <td class="yes"></td> <!-- ARM -->
   <td class="unknown"></td> <!-- Alpha -->
-  <td class="yes"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
@@ -2289,7 +2284,6 @@
   <td><a href="#feat_jit">jit</a></td>
   <td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
   <td class="no"></td> <!-- Alpha -->
-  <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
@@ -2305,7 +2299,6 @@
   <td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>
   <td class="no"></td> <!-- ARM -->
   <td class="no"></td> <!-- Alpha -->
-  <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
@@ -2321,7 +2314,6 @@
   <td><a href="#feat_tailcall">tail calls</a></td>
   <td class="yes"></td> <!-- ARM -->
   <td class="unknown"></td> <!-- Alpha -->
-  <td class="no"></td> <!-- Blackfin -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142880&r1=142879&r2=142880&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Oct 24 19:05:42 2011
@@ -759,7 +759,7 @@
 href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVMdev list</a>.</p>
 
 <ul>
-<li>The Alpha, Blackfin, CellSPU, MicroBlaze, MSP430, MIPS, PTX,
+<li>The Alpha, CellSPU, MicroBlaze, MSP430, MIPS, PTX,
     and XCore backends are experimental.</li>
 <li><tt>llc</tt> "<tt>-filetype=obj</tt>" is experimental on all targets
     other than darwin and ELF X86 systems.</li>

Modified: llvm/trunk/include/llvm/ADT/Triple.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=142880&r1=142879&r2=142880&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/Triple.h (original)
+++ llvm/trunk/include/llvm/ADT/Triple.h Mon Oct 24 19:05:42 2011
@@ -45,7 +45,6 @@
 
     alpha,   // Alpha: alpha
     arm,     // ARM; arm, armv.*, xscale
-    bfin,    // Blackfin: bfin
     cellspu, // CellSPU: spu, cellspu
     mips,    // MIPS: mips, mipsallegrex
     mipsel,  // MIPSEL: mipsel, mipsallegrexel, psp

Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=142880&r1=142879&r2=142880&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Mon Oct 24 19:05:42 2011
@@ -20,7 +20,6 @@
 
   case alpha:   return "alpha";
   case arm:     return "arm";
-  case bfin:    return "bfin";
   case cellspu: return "cellspu";
   case mips:    return "mips";
   case mipsel:  return "mipsel";
@@ -56,8 +55,6 @@
   case arm:
   case thumb:   return "arm";
 
-  case bfin:    return "bfin";
-
   case cellspu: return "spu";
 
   case ppc64:
@@ -138,8 +135,6 @@
     return alpha;
   if (Name == "arm")
     return arm;
-  if (Name == "bfin")
-    return bfin;
   if (Name == "cellspu")
     return cellspu;
   if (Name == "mips")
@@ -278,8 +273,6 @@
     return x86;
   else if (ArchName == "amd64" || ArchName == "x86_64")
     return x86_64;
-  else if (ArchName == "bfin")
-    return bfin;
   else if (ArchName == "powerpc")
     return ppc;
   else if ((ArchName == "powerpc64") || (ArchName == "ppu"))

Modified: llvm/trunk/projects/sample/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/autoconf/configure.ac?rev=142880&r1=142879&r2=142880&view=diff
==============================================================================
--- llvm/trunk/projects/sample/autoconf/configure.ac (original)
+++ llvm/trunk/projects/sample/autoconf/configure.ac Mon Oct 24 19:05:42 2011
@@ -301,7 +301,6 @@
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
   msp430-*)               llvm_cv_target_arch="MSP430" ;;
-  bfin-*)                 llvm_cv_target_arch="Blackfin" ;;
   mblaze-*)               llvm_cv_target_arch="MBlaze" ;;
   ptx-*)                  llvm_cv_target_arch="PTX" ;;
   *)                      llvm_cv_target_arch="Unknown" ;;
@@ -437,7 +436,6 @@
     Mips)        AC_SUBST(TARGET_HAS_JIT,1) ;;
     XCore)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     MSP430)      AC_SUBST(TARGET_HAS_JIT,0) ;;
-    Blackfin)    AC_SUBST(TARGET_HAS_JIT,0) ;;
     MBlaze)      AC_SUBST(TARGET_HAS_JIT,0) ;;
     PTX)         AC_SUBST(TARGET_HAS_JIT,0) ;;
     *)           AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -550,13 +548,13 @@
 AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
     [Build specific host targets: all or target1,target2,... Valid targets are:
      host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu,
-     xcore, msp430, blackfin, ptx, cbe, and cpp (default=all)]),,
+     xcore, msp430, ptx, cbe, and cpp (default=all)]),,
     enableval=all)
 if test "$enableval" = host-only ; then
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 Blackfin CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -569,7 +567,6 @@
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
         xcore)    TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
         msp430)   TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-        blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
         cbe)      TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
         cpp)      TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
         mblaze)   TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
@@ -586,7 +583,6 @@
             CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
             XCore)       TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
             MSP430)      TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-            Blackfin)    TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
             PTX)         TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
             *)       AC_MSG_ERROR([Can not set target to build]) ;;
           esac ;;

Modified: llvm/trunk/projects/sample/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/configure?rev=142880&r1=142879&r2=142880&view=diff
==============================================================================
--- llvm/trunk/projects/sample/configure (original)
+++ llvm/trunk/projects/sample/configure Mon Oct 24 19:05:42 2011
@@ -1402,7 +1402,7 @@
   --enable-targets        Build specific host targets: all or
                           target1,target2,... Valid targets are: host, x86,
                           x86_64, sparc, powerpc, alpha, arm, mips, spu,
-                          xcore, msp430, blackfin, ptx, cbe, and cpp
+                          xcore, msp430, ptx, cbe, and cpp
                           (default=all)
   --enable-cbe-printf-a   Enable C Backend output with hex floating point via
                           %a (default is YES)
@@ -3845,7 +3845,6 @@
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
   msp430-*)               llvm_cv_target_arch="MSP430" ;;
-  bfin-*)                 llvm_cv_target_arch="Blackfin" ;;
   mblaze-*)               llvm_cv_target_arch="MBlaze" ;;
   ptx-*)                  llvm_cv_target_arch="PTX" ;;
   *)                      llvm_cv_target_arch="Unknown" ;;
@@ -5049,8 +5048,6 @@
  ;;
     MSP430)      TARGET_HAS_JIT=0
  ;;
-    Blackfin)    TARGET_HAS_JIT=0
- ;;
     MBlaze)      TARGET_HAS_JIT=0
  ;;
     PTX)         TARGET_HAS_JIT=0
@@ -5239,7 +5236,7 @@
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 Blackfin CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5252,7 +5249,6 @@
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
         xcore)    TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
         msp430)   TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-        blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
         cbe)      TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
         cpp)      TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
         mblaze)   TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
@@ -5269,7 +5265,6 @@
             CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
             XCore)       TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
             MSP430)      TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-            Blackfin)    TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
             PTX)         TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
             *)       { { echo "$as_me:$LINENO: error: Can not set target to build" >&5
 echo "$as_me: error: Can not set target to build" >&2;}

Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp?rev=142880&r1=142879&r2=142880&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp Mon Oct 24 19:05:42 2011
@@ -2,7 +2,7 @@
 # Do not edit here.  If you wish to override these values
 # edit the last section
 set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 CBackend MSIL CppBackend"
 set llvmgcc_langs "c,c++,objc,obj-c++"
 set prcontext "/usr/bin/tclsh8.4 /Volumes/Data/ddunbar/llvm/test/Scripts/prcontext.tcl"
 set llvmtoolsdir "/Users/ddunbar/llvm.obj.64/Debug/bin"

Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp?rev=142880&r1=142879&r2=142880&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp Mon Oct 24 19:05:42 2011
@@ -2,7 +2,7 @@
 # Do not edit here.  If you wish to override these values
 # edit the last section
 set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 CBackend MSIL CppBackend"
 set llvmgcc_langs "c,c++,objc,obj-c++"
 set prcontext "/usr/bin/tclsh8.4 /Volumes/Data/ddunbar/llvm/test/Scripts/prcontext.tcl"
 set llvmtoolsdir "/Users/ddunbar/llvm.obj.64/Debug/bin"



From grosbach at apple.com  Mon Oct 24 19:14:01 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 25 Oct 2011 00:14:01 -0000
Subject: [llvm-commits] [llvm] r142882 - in /llvm/trunk:
 lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMInstrNEON.td
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/ARM/neon-vld-encoding.s
Message-ID: <20111025001401.5D39A312800A@llvm.org>

Author: grosbach
Date: Mon Oct 24 19:14:01 2011
New Revision: 142882

URL: http://llvm.org/viewvc/llvm-project?rev=142882&view=rev
Log:
ARM assembly parsing and encoding for VLD1 with writeback.

Four entry register lists.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/ARM/neon-vld-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=142882&r1=142881&r2=142882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Oct 24 19:14:01 2011
@@ -2440,7 +2440,8 @@
     case ARM::VLD4d8_UPD:
     case ARM::VLD4d16_UPD:
     case ARM::VLD4d32_UPD:
-    case ARM::VLD1d64Q_UPD:
+    case ARM::VLD1d64Qwb_fixed:
+    case ARM::VLD1d64Qwb_register:
     case ARM::VLD4q8_UPD:
     case ARM::VLD4q16_UPD:
     case ARM::VLD4q32_UPD:

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142882&r1=142881&r2=142882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 24 19:14:01 2011
@@ -424,13 +424,24 @@
   let Inst{5-4} = Rn{5-4};
   let DecoderMethod = "DecodeVLDInstruction";
 }
-class VLD1D4WB<bits<4> op7_4, string Dt>
-  : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
-          (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
-          "$Vd, $Rn$Rm", "$Rn.addr = $wb",
-          []> {
-  let Inst{5-4} = Rn{5-4};
-  let DecoderMethod = "DecodeVLDInstruction";
+multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
+  def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
+                    (ins addrmode6:$Rn), IIC_VLD1x2u,
+                     "vld1", Dt, "$Vd, $Rn!",
+                     "$Rn.addr = $wb", []> {
+    let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
+    let Inst{5-4} = Rn{5-4};
+    let DecoderMethod = "DecodeVLDInstruction";
+    let AsmMatchConverter = "cvtVLDwbFixed";
+  }
+  def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
+                        (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
+                        "vld1", Dt, "$Vd, $Rn, $Rm",
+                        "$Rn.addr = $wb", []> {
+    let Inst{5-4} = Rn{5-4};
+    let DecoderMethod = "DecodeVLDInstruction";
+    let AsmMatchConverter = "cvtVLDwbRegister";
+  }
 }
 
 def VLD1d8Q      : VLD1D4<{0,0,?,?}, "8">;
@@ -438,12 +449,12 @@
 def VLD1d32Q     : VLD1D4<{1,0,?,?}, "32">;
 def VLD1d64Q     : VLD1D4<{1,1,?,?}, "64">;
 
-def VLD1d8Q_UPD  : VLD1D4WB<{0,0,?,?}, "8">;
-def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
-def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
-def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
+defm VLD1d8Qwb   : VLD1D4WB<{0,0,?,?}, "8">;
+defm VLD1d16Qwb  : VLD1D4WB<{0,1,?,?}, "16">;
+defm VLD1d32Qwb  : VLD1D4WB<{1,0,?,?}, "32">;
+defm VLD1d64Qwb  : VLD1D4WB<{1,1,?,?}, "64">;
 
-def VLD1d64QPseudo     : VLDQQPseudo<IIC_VLD1x4>;
+def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
 
 //   VLD2     : Vector Load (multiple 2-element structures)
 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=142882&r1=142881&r2=142882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Oct 24 19:14:01 2011
@@ -2078,10 +2078,14 @@
     case ARM::VLD1d32Twb_register:
     case ARM::VLD1d64Twb_fixed:
     case ARM::VLD1d64Twb_register:
-    case ARM::VLD1d8Q_UPD:
-    case ARM::VLD1d16Q_UPD:
-    case ARM::VLD1d32Q_UPD:
-    case ARM::VLD1d64Q_UPD:
+    case ARM::VLD1d8Qwb_fixed:
+    case ARM::VLD1d8Qwb_register:
+    case ARM::VLD1d16Qwb_fixed:
+    case ARM::VLD1d16Qwb_register:
+    case ARM::VLD1d32Qwb_fixed:
+    case ARM::VLD1d32Qwb_register:
+    case ARM::VLD1d64Qwb_fixed:
+    case ARM::VLD1d64Qwb_register:
     case ARM::VLD2d8_UPD:
     case ARM::VLD2d16_UPD:
     case ARM::VLD2d32_UPD:

Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=142882&r1=142881&r2=142882&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Mon Oct 24 19:14:01 2011
@@ -45,6 +45,16 @@
 	vld1.32 {d5, d6, d7}, [r3], r6
 	vld1.64 {d6, d7, d8}, [r3, :64], r6
 
+	vld1.8 {d1, d2, d3, d4}, [r3]!
+	vld1.16 {d4, d5, d6, d7}, [r3, :64]!
+	vld1.32 {d5, d6, d7, d8}, [r3]!
+	vld1.64 {d6, d7, d8, d9}, [r3, :64]!
+
+	vld1.8 {d1, d2, d3, d4}, [r3], r8
+	vld1.16 {d4, d5, d6, d7}, [r3, :64], r8
+	vld1.32 {d5, d6, d7, d8}, [r3], r8
+	vld1.64 {d6, d7, d8, d9}, [r3, :64], r8
+
 @ CHECK: vld1.8 {d16}, [r0, :64]        @ encoding: [0x1f,0x07,0x60,0xf4]
 @ CHECK: vld1.16 {d16}, [r0]            @ encoding: [0x4f,0x07,0x60,0xf4]
 @ CHECK: vld1.32 {d16}, [r0]            @ encoding: [0x8f,0x07,0x60,0xf4]
@@ -90,6 +100,16 @@
 @ CHECK: vld1.32 {d5, d6, d7}, [r3], r6  @ encoding: [0x86,0x56,0x23,0xf4]
 @ CHECK: vld1.64 {d6, d7, d8}, [r3, :64], r6 @ encoding: [0xd6,0x66,0x23,0xf4]
 
+@ CHECK: vld1.8	{d1, d2, d3, d4}, [r3]! @ encoding: [0x0d,0x12,0x23,0xf4]
+@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64]! @ encoding: [0x5d,0x42,0x23,0xf4]
+@ CHECK: vld1.32 {d5, d6, d7, d8}, [r3]! @ encoding: [0x8d,0x52,0x23,0xf4]
+@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64]! @ encoding: [0xdd,0x62,0x23,0xf4]
+
+@ CHECK: vld1.8	{d1, d2, d3, d4}, [r3], r8 @ encoding: [0x08,0x12,0x23,0xf4]
+@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64], r8 @ encoding: [0x58,0x42,0x23,0xf4]
+@ CHECK: vld1.32 {d5, d6, d7, d8}, [r3], r8 @ encoding: [0x88,0x52,0x23,0xf4]
+@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64], r8 @ encoding: [0xd8,0x62,0x23,0xf4]
+
 
 	vld2.8	{d16, d17}, [r0, :64]
 	vld2.16	{d16, d17}, [r0, :128]



From gohman at apple.com  Mon Oct 24 19:36:31 2011
From: gohman at apple.com (Dan Gohman)
Date: Tue, 25 Oct 2011 00:36:31 -0000
Subject: [llvm-commits] [llvm] r142889 - /llvm/trunk/configure
Message-ID: <20111025003631.D73A7312800A@llvm.org>

Author: djg
Date: Mon Oct 24 19:36:31 2011
New Revision: 142889

URL: http://llvm.org/viewvc/llvm-project?rev=142889&view=rev
Log:
Really remove Blackfin from the configure script.

Modified:
    llvm/trunk/configure

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=142889&r1=142888&r2=142889&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Mon Oct 24 19:36:31 2011
@@ -5083,8 +5083,6 @@
  ;;
     MSP430)      TARGET_HAS_JIT=0
  ;;
-    Blackfin)    TARGET_HAS_JIT=0
- ;;
     MBlaze)      TARGET_HAS_JIT=0
  ;;
     PTX)         TARGET_HAS_JIT=0
@@ -5273,7 +5271,7 @@
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 Blackfin CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5302,7 +5300,6 @@
             CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
             XCore)       TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
             MSP430)      TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
-            Blackfin)    TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;;
             PTX)         TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
             *)       { { echo "$as_me:$LINENO: error: Can not set target to build" >&5
 echo "$as_me: error: Can not set target to build" >&2;}



From isanbard at gmail.com  Mon Oct 24 19:54:05 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 25 Oct 2011 00:54:05 -0000
Subject: [llvm-commits] [llvm] r142891 -
	/llvm/trunk/lib/CodeGen/BranchFolding.cpp
Message-ID: <20111025005405.4FEBC312800A@llvm.org>

Author: void
Date: Mon Oct 24 19:54:05 2011
New Revision: 142891

URL: http://llvm.org/viewvc/llvm-project?rev=142891&view=rev
Log:
An MBB which branches to an EH landing pad shouldn't be considered for tail merging.

In SjLj EH, the jump to the landing pad is not done explicitly through a branch
statement. The EH landing pad is added as a successor to the throwing
BB. Because of that however, the branch folding pass could mistakenly think that
it could merge the throwing BB with another BB. This isn't safe to do.
<rdar://problem/10334833>

Modified:
    llvm/trunk/lib/CodeGen/BranchFolding.cpp

Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=142891&r1=142890&r2=142891&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Mon Oct 24 19:54:05 2011
@@ -913,7 +913,8 @@
               // reinsert conditional branch only, for now
               TII->InsertBranch(*PBB, (TBB == IBB) ? FBB : TBB, 0, NewCond, dl);
           }
-          MergePotentials.push_back(MergePotentialsElt(HashEndOfMBB(PBB), *P));
+          if (!PBB->getLandingPadSuccessor())
+            MergePotentials.push_back(MergePotentialsElt(HashEndOfMBB(PBB),*P));
         }
       }
       // If this is a large problem, avoid visiting the same basic blocks



From echristo at apple.com  Mon Oct 24 19:55:35 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 25 Oct 2011 00:55:35 -0000
Subject: [llvm-commits] [llvm] r142892 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
Message-ID: <20111025005535.B72E3312800A@llvm.org>

Author: echristo
Date: Mon Oct 24 19:55:35 2011
New Revision: 142892

URL: http://llvm.org/viewvc/llvm-project?rev=142892&view=rev
Log:
Remove unused forward decl.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=142892&r1=142891&r2=142892&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Oct 24 19:55:35 2011
@@ -31,7 +31,6 @@
 namespace llvm {
 
 class CompileUnit;
-class DbgConcreteScope;
 class DbgVariable;
 class MachineFrameInfo;
 class MachineModuleInfo;



From isanbard at gmail.com  Mon Oct 24 20:01:42 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 25 Oct 2011 01:01:42 -0000
Subject: [llvm-commits] [llvm] r142893 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111025010142.C80CB312800A@llvm.org>

Author: void
Date: Mon Oct 24 20:01:42 2011
New Revision: 142893

URL: http://llvm.org/viewvc/llvm-project?rev=142893&view=rev
Log:
Comment out external projects so that they can be refreshed for 3.0.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142893&r1=142892&r2=142893&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Oct 24 20:01:42 2011
@@ -284,6 +284,8 @@
    projects that have already been updated to work with LLVM 3.0.</p>
 
 <!--=========================================================================-->
+
+<!-- FIXME: Comment out
 <h3>Crack Programming Language</h3>
 
 <div>
@@ -293,9 +295,10 @@
 language. The language derives concepts from C++, Java and Python, incorporating
 object-oriented programming, operator overloading and strong typing.</p>
 </div>
-  
+-->  
   
 <!--=========================================================================-->
+<!--
 <h3>TTA-based Codesign Environment (TCE)</h3>
   
 <div>
@@ -311,10 +314,11 @@
 to the compiler backend as runtime libraries to avoid per-target recompilation
 of larger parts of the compiler chain.</p>
 </div>
-
+-->
 
   
 <!--=========================================================================-->
+<!--
 <h3>PinaVM</h3>
   
 <div>
@@ -324,8 +328,11 @@
 program analyzed using LLVM's JIT infrastructure. It later enriches the
 bitcode with SystemC-specific information.</p>
 </div>
+-->
+
 
 <!--=========================================================================-->
+<!--
 <h3>Pure</h3>
   
 <div>
@@ -345,8 +352,10 @@
 <p>Pure version 0.47 has been tested and is known to work with LLVM 3.0
   (and continues to work with older LLVM releases &gt;= 2.5).</p>
 </div>
+-->
 
 <!--=========================================================================-->
+<!--
 <h3 id="icedtea">IcedTea Java Virtual Machine Implementation</h3>
 
 <div>
@@ -364,8 +373,10 @@
 and are known to work with LLVM 3.0 (and continue to work with older LLVM
 releases &gt;= 2.6 as well).</p>
 </div>
+-->
 
 <!--=========================================================================-->
+<!--
 <h3>Glasgow Haskell Compiler (GHC)</h3>
   
 <div>
@@ -378,8 +389,10 @@
 <p>In addition to the existing C and native code generators, GHC 7.0 now
 supports an LLVM code generator. GHC supports LLVM 2.7 and later.</p>
 </div>
+-->
 
 <!--=========================================================================-->
+<!--
 <h3>Polly - Polyhedral optimizations for LLVM</h3>
   
 <div>
@@ -393,8 +406,10 @@
 Furthermore, Polly can use PoCC(Pluto) an advanced optimizer for data-locality
 and parallelism.</p>
 </div>
+-->
 
 <!--=========================================================================-->
+<!--
 <h3>Rubinius</h3>
 
 <div>
@@ -405,9 +420,10 @@
   feedback, method inlining, and deoptimization are all used to remove dynamism
   from ruby execution and increase performance.</p>
 </div>
-
+-->
 
 <!--=========================================================================-->
+<!--
 <h3>
 <a name="FAUST">FAUST Real-Time Audio Signal Processing Language</a>
 </h3>
@@ -421,6 +437,7 @@
 Faust compiler can now generate LLVM bitcode, and works with LLVM 2.7-3.0.</p>
 
 </div>
+-->
   
 </div>
 



From mcrosier at apple.com  Mon Oct 24 20:22:20 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Tue, 25 Oct 2011 01:22:20 -0000
Subject: [llvm-commits] [llvm] r142896 - in /llvm/trunk/test/Bitcode:
 sse42_crc32.ll sse42_crc32.ll.bc ssse3_palignr.ll ssse3_palignr.ll.bc
Message-ID: <20111025012220.6FCB0312800A@llvm.org>

Author: mcrosier
Date: Mon Oct 24 20:22:20 2011
New Revision: 142896

URL: http://llvm.org/viewvc/llvm-project?rev=142896&view=rev
Log:
Fix these test cases to not use .bc files.  Otherwise, we run into issues with
bitcode reader/writer backward compatibility.

Removed:
    llvm/trunk/test/Bitcode/sse42_crc32.ll.bc
    llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc
Modified:
    llvm/trunk/test/Bitcode/sse42_crc32.ll
    llvm/trunk/test/Bitcode/ssse3_palignr.ll

Modified: llvm/trunk/test/Bitcode/sse42_crc32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/sse42_crc32.ll?rev=142896&r1=142895&r2=142896&view=diff
==============================================================================
--- llvm/trunk/test/Bitcode/sse42_crc32.ll (original)
+++ llvm/trunk/test/Bitcode/sse42_crc32.ll Mon Oct 24 20:22:20 2011
@@ -3,7 +3,7 @@
 ;
 ; Rdar: 9472944
 ;
-; RUN: llvm-dis < %s.bc | FileCheck %s
+; RUN: opt < %s | llvm-dis | FileCheck %s
 
 ; crc32.8 should upgrade to crc32.32.8
 ; CHECK: i32 @llvm.x86.sse42.crc32.32.8(
@@ -26,3 +26,18 @@
 ; CHECK-NOT: i64 @llvm.x86.sse42.crc64.64(
 
 
+define void @foo() nounwind readnone ssp {
+entry:
+  %0 = call i32 @llvm.x86.sse42.crc32.8(i32 0, i8 0)
+  %1 = call i32 @llvm.x86.sse42.crc32.16(i32 0, i16 0)
+  %2 = call i32 @llvm.x86.sse42.crc32.32(i32 0, i32 0)
+  %3 = call i64 @llvm.x86.sse42.crc64.8(i64 0, i8 0)
+  %4 = call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 0)
+  ret void
+}
+
+declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind readnone
+declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind readnone
+declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind readnone
+declare i64 @llvm.x86.sse42.crc64.8(i64, i8) nounwind readnone
+declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone

Removed: llvm/trunk/test/Bitcode/sse42_crc32.ll.bc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/sse42_crc32.ll.bc?rev=142895&view=auto
==============================================================================
Binary file - no diff available.

Modified: llvm/trunk/test/Bitcode/ssse3_palignr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/ssse3_palignr.ll?rev=142896&r1=142895&r2=142896&view=diff
==============================================================================
--- llvm/trunk/test/Bitcode/ssse3_palignr.ll (original)
+++ llvm/trunk/test/Bitcode/ssse3_palignr.ll Mon Oct 24 20:22:20 2011
@@ -1,2 +1,82 @@
-; RUN: llvm-dis < %s.bc | FileCheck %s 
+; RUN: opt < %s | llvm-dis | FileCheck %s
 ; CHECK-NOT: {@llvm\\.palign}
+
+define <4 x i32> @align1(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 15) ; <<2 x i64>> [#uses=1]
+  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
+  ret <4 x i32> %3
+}
+
+define double @align8(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 7) ; <<1 x i64>> [#uses=1]
+  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
+  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
+  ret double %retval12
+}
+
+declare <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64>, <1 x i64>, i8) nounwind readnone
+
+define double @align7(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 16) ; <<1 x i64>> [#uses=1]
+  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
+  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
+  ret double %retval12
+}
+
+define double @align6(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 9) ; <<1 x i64>> [#uses=1]
+  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
+  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
+  ret double %retval12
+}
+
+define double @align5(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
+  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 8) ; <<1 x i64>> [#uses=1]
+  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
+  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
+  ret double %retval12
+}
+
+define <4 x i32> @align4(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) ; <<2 x i64>> [#uses=1]
+  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
+  ret <4 x i32> %3
+}
+
+declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
+
+define <4 x i32> @align3(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 17) ; <<2 x i64>> [#uses=1]
+  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
+  ret <4 x i32> %3
+}
+
+define <4 x i32> @align2(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
+entry:
+  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
+  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 16) ; <<2 x i64>> [#uses=1]
+  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
+  ret <4 x i32> %3
+}

Removed: llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc?rev=142895&view=auto
==============================================================================
Binary file - no diff available.



From gkistanova at gmail.com  Mon Oct 24 20:28:53 2011
From: gkistanova at gmail.com (Galina Kistanova)
Date: Tue, 25 Oct 2011 01:28:53 -0000
Subject: [llvm-commits] [zorg] r142899 - in
 /zorg/trunk/buildbot/osuosl/master/config: builders.py slaves.py
Message-ID: <20111025012853.BCA56312800A@llvm.org>

Author: gkistanova
Date: Mon Oct 24 20:28:53 2011
New Revision: 142899

URL: http://llvm.org/viewvc/llvm-project?rev=142899&view=rev
Log:
Removed few not working build slaves.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py
    zorg/trunk/buildbot/osuosl/master/config/slaves.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=142899&r1=142898&r2=142899&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Oct 24 20:28:53 2011
@@ -54,18 +54,6 @@
                                     'CXX': "/usr/bin/g++-4.2" },
                             extra_configure_args=['--enable-shared'],
                             timeout=600)},
-        {'name': "llvm-i686-linux-vg_leak",
-         'slavenames':["osu8"],
-         'builddir':"llvm-i686-linux-vg_leak",
-         'factory': LLVMBuilder.getLLVMBuildFactory("i686-pc-linux-gnu", valgrind=True,
-                                                     valgrindLeakCheck=True,
-                                                     valgrindSuppressions='utils/valgrind/i386-pc-linux-gnu.supp')},
-        {'name': "llvm-x86_64-linux-vg_leak",
-         'slavenames':["osu7"],
-         'builddir':"llvm-x86_64-linux-vg_leak",
-         'factory': LLVMBuilder.getLLVMBuildFactory("x86_64-pc-linux-gnu", valgrind=True,
-                                                     valgrindLeakCheck=True,
-                                                     valgrindSuppressions='utils/valgrind/x86_64-pc-linux-gnu.supp')},
         {'name': "llvm-i686-debian",
          'slavenames': ["gcc15"],
          'builddir': "llvm-i686-debian",
@@ -120,11 +108,7 @@
 #         'builddir':"llvm-gcc-x86_64-darwin10-selfhost",
 #         'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(4, triple='x86_64-apple-darwin10',
 #                                                         gxxincludedir='/usr/include/c++/4.2.1')},
-        {'name' : "llvm-gcc-x86_64-linux-selfhost",
-         'slavenames':["osu7"],
-         'builddir':"llvm-gcc-x86_64-linux-selfhost",
-         'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(triple='x86_64-pc-linux-gnu',
-                                                         extra_configure_args=['--disable-multilib'])},
+
         {'name' : "llvm-x86_64-linux-checks",
          'slavenames':["gcc10"],
          'builddir':"llvm-x86_64-linux-checks",
@@ -192,12 +176,6 @@
 #         'slavenames' :['dunbar-win32-2'],
 #         'builddir' :"clang-i686-xp-msvc9",
 #         'factory' : ClangBuilder.getClangMSVCBuildFactory(jobs=2)},
-
-         {'name': "clang-x86_64-linux-vg",
-          'slavenames':["osu7"],
-          'builddir':"clang-x86_64-linux-vg",
-          'factory': ClangBuilder.getClangBuildFactory(valgrind=True)},
-
 #        {'name' : "clang-x86_64-darwin10-selfhost",
 #         'slavenames' : ["dunbar-darwin10"],
 #         'builddir' : "clang-x86_64-darwin10-selfhost",
@@ -206,14 +184,6 @@
 #                                                       stage1_config='Release+Asserts',
 #                                                       stage2_config='Debug+Asserts')},
 
-        {'name' : "clang-x86_64-linux-selfhost-rel",
-         'slavenames' : ["osu7"],
-         'builddir' : "clang-x86_64-linux-selfhost-rel",
-         'factory' : ClangBuilder.getClangBuildFactory(triple='x86_64-pc-linux-gnu',
-                                                       useTwoStage=True,
-                                                       stage1_config='Release+Asserts',
-                                                       stage2_config='Release+Asserts')},
-
         {'name' : "clang-i686-linux-fnt",
          'slavenames' : ['balint1'],
          'builddir' : "clang-i686-linux-fnt",
@@ -222,14 +192,6 @@
                                                                        test=False,
                                                                        xfails=clang_i386_linux_xfails) },
 
-        {'name' : "clang-x86_64-linux-fnt",
-         'slavenames' : ['osu7'],
-         'builddir' : "clang-x86_64-linux-fnt",
-         'factory' : NightlytestBuilder.getFastNightlyTestBuildFactory(triple='x86_64-pc-linux-gnu',
-                                                                       stage1_config='Release+Asserts',
-                                                                       test=False,
-                                                                       xfails=clang_x86_64_linux_xfails) },
-
         {'name': "clang-x86_64-debian",
          'slavenames':["gcc12"],
          'builddir':"clang-x86_64-debian",
@@ -763,16 +725,6 @@
 #                                        'description'   : 'install llvm-gcc',
 #                                        'haltOnFailure' : True },]),
 #         'category'  : 'llvm-gcc' },
-
-        {'name' : "clang-i686-linux-selfhost-rel",
-         'slavenames' : ["osu8"],
-         'builddir' : "clang-i686-linux-selfhost-rel",
-         'factory' : ClangBuilder.getClangBuildFactory(triple='i686-pc-linux-gnu',
-                                                       useTwoStage=True,
-                                                       stage1_config='Release+Asserts',
-                                                       stage2_config='Release+Asserts'),
-         'category' : 'clang.exp' },
-
 #        {'name' : "clang-i686-xp-msvc9_alt",
 #         'slavenames' :['adobe1'],
 #         'builddir' :"clang-i686-xp-msvc9_alt",
@@ -821,8 +773,4 @@
  'builddir':"clang-x86_64-openbsd",
  'factory': ClangBuilder.getClangBuildFactory(),
  'category':'clang.exp'}
-{'name': "clang-x86_64-linux-checks",
- 'slavenames':["osu2"],
- 'builddir':"clang-x86_64-linux-checks",
- 'factory': ClangBuilder.getClangBuildFactory(stage1_config='Debug+Asserts+Checks'),
- 'category':'clang.exp'}
+

Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=142899&r1=142898&r2=142899&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Mon Oct 24 20:28:53 2011
@@ -10,8 +10,6 @@
 
 def get_build_slaves():
     return [
-        create_slave("osu1", properties={'jobs' : 4}, max_builds=1),
-
         # FreeBSD zero.sajd.net 9.0-CURRENT i386
         create_slave("freebsd1", properties={'jobs' : 1}, max_builds=1),
 
@@ -159,10 +157,6 @@
         # gcc201 8011  80G   4x0.4 GHz  TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64
         create_slave("gcc201", properties={'jobs' : 2}, max_builds=1),
 
-        # Debian x86_64, 2 x 6-core Opteron 2.6 GHz
-        create_slave("osu7", properties={'jobs' : 6}, max_builds=4),
-        create_slave("osu8", properties={'jobs' : 6}, max_builds=4),
-
         # Debian, P4 2.8GHz, 1GB mem
         create_slave("balint1", properties={'jobs' : 1}, max_builds=1),
 
@@ -179,7 +173,6 @@
         create_slave("arxan_bellini", properties={'jobs': 2}, max_builds=1),
 
         # Defunct.
-        #create_slave("osu2", properties={'jobs' : 4}, max_builds=2),
         #create_slave("andrew1"),
         #create_slave("danmbp1"),
         ]



From mcrosier at apple.com  Mon Oct 24 20:41:43 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Mon, 24 Oct 2011 18:41:43 -0700
Subject: [llvm-commits] [llvm] r140627 - in /llvm/trunk:
 test/Object/TestObjectFiles/archive-test.a-bitcode
 test/Object/TestObjectFiles/archive-test.a-coff-i386
 test/Object/nm-archive.test tools/llvm-nm/llvm-nm.cpp
In-Reply-To: <20110927193718.333882A6C12C@llvm.org>
References: <20110927193718.333882A6C12C@llvm.org>
Message-ID: <77A37FBC-A751-4FB7-B5E6-1EFE405C266E@apple.com>

Hi Michael,
Would it be possible for you to rework this test case so that it can generate the archive on the fly, rather than reading in the archive-test.a-* files?  I'm going to begin work on the bitcode reader/writer very soon that will break backward compatibility and in turn break this test case.  See r142896 for examples of what was necessary for a few other test cases.

 Regards,
  Chad


On Sep 27, 2011, at 12:37 PM, Michael J. Spencer wrote:

> Author: mspencer
> Date: Tue Sep 27 14:37:18 2011
> New Revision: 140627
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=140627&view=rev
> Log:
> Add binary archive support to llvm-nm.
> 
> Added:
>    llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode
>    llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386
>    llvm/trunk/test/Object/nm-archive.test
> Modified:
>    llvm/trunk/tools/llvm-nm/llvm-nm.cpp
> 
> Added: llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode?rev=140627&view=auto
> ==============================================================================
> Binary files llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode (added) and llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode Tue Sep 27 14:37:18 2011 differ
> 
> Added: llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386?rev=140627&view=auto
> ==============================================================================
> Binary files llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386 (added) and llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386 Tue Sep 27 14:37:18 2011 differ
> 
> Added: llvm/trunk/test/Object/nm-archive.test
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/nm-archive.test?rev=140627&view=auto
> ==============================================================================
> --- llvm/trunk/test/Object/nm-archive.test (added)
> +++ llvm/trunk/test/Object/nm-archive.test Tue Sep 27 14:37:18 2011
> @@ -0,0 +1,17 @@
> +RUN: llvm-nm %p/TestObjectFiles/archive-test.a-coff-i386 \
> +RUN:         | FileCheck %s -check-prefix COFF
> +RUN: llvm-nm %p/TestObjectFiles/archive-test.a-bitcode \
> +RUN:         | FileCheck %s -check-prefix BITCODE
> +
> +
> +COFF: trivial-object-test.coff-i386:
> +COFF-NEXT: 00000000 d .data
> +COFF-NEXT: 00000000 t .text
> +COFF-NEXT: 00000000 d L_.str
> +COFF-NEXT:          U _SomeOtherFunction
> +COFF-NEXT: 00000000 T _main
> +COFF-NEXT:          U _puts
> +
> +BITCODE:          U SomeOtherFunction
> +BITCODE-NEXT:          T main
> +BITCODE-NEXT:          U puts
> 
> Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=140627&r1=140626&r2=140627&view=diff
> ==============================================================================
> --- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
> +++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Tue Sep 27 14:37:18 2011
> @@ -20,6 +20,7 @@
> #include "llvm/Module.h"
> #include "llvm/Bitcode/ReaderWriter.h"
> #include "llvm/Bitcode/Archive.h"
> +#include "llvm/Object/Archive.h"
> #include "llvm/Object/ObjectFile.h"
> #include "llvm/Support/CommandLine.h"
> #include "llvm/Support/FileSystem.h"
> @@ -318,18 +319,34 @@
>       errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n";
> 
>   } else if (aPath.isArchive()) {
> -    std::string ErrMsg;
> -    Archive* archive = Archive::OpenAndLoad(sys::Path(Filename), Context,
> -                                            &ErrorMessage);
> -    if (!archive)
> -      errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n";
> -    std::vector<Module *> Modules;
> -    if (archive->getAllModules(Modules, &ErrorMessage)) {
> -      errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n";
> +    OwningPtr<Binary> arch;
> +    if (error_code ec = object::createBinary(aPath.str(), arch)) {
> +      errs() << ToolName << ": " << Filename << ": " << ec.message() << ".\n";
>       return;
>     }
> -    MultipleFiles = true;
> -    std::for_each (Modules.begin(), Modules.end(), DumpSymbolNamesFromModule);
> +    if (object::Archive *a = dyn_cast<object::Archive>(arch.get())) {
> +      for (object::Archive::child_iterator i = a->begin_children(),
> +                                           e = a->end_children(); i != e; ++i) {
> +        OwningPtr<Binary> child;
> +        if (error_code ec = i->getAsBinary(child)) {
> +          // Try opening it as a bitcode file.
> +          MemoryBuffer *buff = i->getBuffer();
> +          Module *Result = 0;
> +          if (buff)
> +            Result = ParseBitcodeFile(buff, Context, &ErrorMessage);
> +
> +          if (Result) {
> +            DumpSymbolNamesFromModule(Result);
> +            delete Result;
> +          }
> +          continue;
> +        }
> +        if (object::ObjectFile *o = dyn_cast<ObjectFile>(child.get())) {
> +          outs() << o->getFileName() << ":\n";
> +          DumpSymbolNamesFromObject(o);
> +        }
> +      }
> +    }
>   } else if (aPath.isObjectFile()) {
>     OwningPtr<Binary> obj;
>     if (error_code ec = object::createBinary(aPath.str(), obj)) {
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From dblaikie at gmail.com  Mon Oct 24 21:17:46 2011
From: dblaikie at gmail.com (David Blaikie)
Date: Mon, 24 Oct 2011 19:17:46 -0700
Subject: [llvm-commits] [llvm] r142731 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
In-Reply-To: <CAENS6EvZqx4aO9Z7D6k4Y+x_6EMDL8X0T9MivyLsoQHqrctjRg@mail.gmail.com>
References: <20111022195820.621CC2A6C12C@llvm.org>
	<CAENS6EvZqx4aO9Z7D6k4Y+x_6EMDL8X0T9MivyLsoQHqrctjRg@mail.gmail.com>
Message-ID: <CAENS6EtM52EkVYhuRA-KSRCMTpY7DVdL8iU25+mi0S0kopcC6w@mail.gmail.com>

On Mon, Oct 24, 2011 at 11:14 AM, David Blaikie <dblaikie at gmail.com> wrote:
>> Make SCEV's brute force analysis stronger in two ways. Firstly, we should be
>> able to constant fold load instructions where the argument is a constant.
>> Second, we should be able to watch multiple PHI nodes through the loop; this
>> patch only supports PHIs in loop headers, more can be done here.
>>
>> With this patch, we now constant evaluate:
>> ?static const int arr[] = {1, 2, 3, 4, 5};
>> ?int test() {
>> ? ?int sum = 0;
>> ? ?for (int i = 0; i < 5; ++i) sum += arr[i];
>> ? ?return sum;
>> ?}
>
> [I'll test this myself this evening, but I thought this might be worth
> asking/discussing]
>
> What happens if you invoke UB in this code by, say, iterating past the
> end of the array? Does SCEV act on this in any way, such as replacing
> the whole block with unreachable? Would it be possible to produce a
> diagnostic of some kind? (I realize once LLVM's doing codegen it's a
> bit late for front ends, but I don't know if there are any hooks for
> such functionality)

So this currently produces a "return i32 undef" as the body of the
test() function given above. This is a bit generous - the value is
more than undefined, it invokes undefined behavior to compute it
(granted undef is one such possible UB). Would it be better to mark it
as unreachable?  (& I'm still curious if there's any precedent/way for
the llvm backend to emit warnings/errors through the clang (or other)
front ends, though I can see how that might not be entirely practical
given various optimizations, inlining, etc such that the source of
this UB was not directly correlated with the input)

- David


From nlewycky at google.com  Mon Oct 24 21:27:47 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Mon, 24 Oct 2011 19:27:47 -0700
Subject: [llvm-commits] patch: pick direct or indirect strings in DWARF
Message-ID: <CADbEz-jaVTjVkBLoFU0rvU7Vc83_T0vHWeqS21QLMy=WOQmM6w@mail.gmail.com>

DWARF allows string to be specified in one of two ways, either by writing
them literally (DW_FORM_string) or by including a pointer into the
.debug_str section and putting the NUL-terminated string there.

The attached patch removes the Form argument from CompileUnit::AddString and
changes addString to emit either a DIEString or a DIELabel depending on how
long the string is. If the string would fit in 4 bytes in the direct
encoding, do that. Otherwise, hoist it out into .debug_str so that it can be
interned.

This is a major issue on linux where the linker does not turn direct strings
into indirect strings, but does merge the string tables. On Darwin, the
linker will turn direct strings into indirect strings as needed. However,
this change should probably be enabled on all platforms as it generally
makes .o files smaller.

Please review! The one thing I don't like about this patch is that we emit
the bytes (via .ascii) and then emit the NUL (via. ".zero 1"). The
alternatives I see are either to create a copy of the string, or to create a
new emitBytesWithNUL API in MCStreamer.

Nick

PS. If this patch doesn't work on Darwin out-of-the-box, please try one
thing for me: comment out the change to DIELabel::SizeOf (adding a case for
DW_FORM_strp), and let me know whether that fixes things.
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From nicholas at mxc.ca  Mon Oct 24 22:57:08 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 24 Oct 2011 20:57:08 -0700
Subject: [llvm-commits] [llvm] r142731 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
In-Reply-To: <CAENS6EtM52EkVYhuRA-KSRCMTpY7DVdL8iU25+mi0S0kopcC6w@mail.gmail.com>
References: <20111022195820.621CC2A6C12C@llvm.org>	<CAENS6EvZqx4aO9Z7D6k4Y+x_6EMDL8X0T9MivyLsoQHqrctjRg@mail.gmail.com>
	<CAENS6EtM52EkVYhuRA-KSRCMTpY7DVdL8iU25+mi0S0kopcC6w@mail.gmail.com>
Message-ID: <4EA63394.20405@mxc.ca>

David Blaikie wrote:
> On Mon, Oct 24, 2011 at 11:14 AM, David Blaikie<dblaikie at gmail.com>  wrote:
>>> Make SCEV's brute force analysis stronger in two ways. Firstly, we should be
>>> able to constant fold load instructions where the argument is a constant.
>>> Second, we should be able to watch multiple PHI nodes through the loop; this
>>> patch only supports PHIs in loop headers, more can be done here.
>>>
>>> With this patch, we now constant evaluate:
>>>   static const int arr[] = {1, 2, 3, 4, 5};
>>>   int test() {
>>>     int sum = 0;
>>>     for (int i = 0; i<  5; ++i) sum += arr[i];
>>>     return sum;
>>>   }
>>
>> [I'll test this myself this evening, but I thought this might be worth
>> asking/discussing]
>>
>> What happens if you invoke UB in this code by, say, iterating past the
>> end of the array? Does SCEV act on this in any way, such as replacing
>> the whole block with unreachable? Would it be possible to produce a
>> diagnostic of some kind? (I realize once LLVM's doing codegen it's a
>> bit late for front ends, but I don't know if there are any hooks for
>> such functionality)
>
> So this currently produces a "return i32 undef" as the body of the
> test() function given above. This is a bit generous - the value is
> more than undefined, it invokes undefined behavior to compute it
> (granted undef is one such possible UB). Would it be better to mark it
> as unreachable?

Sure, that'd be better. However, turning this into unreachable will be 
rather difficult.

   (&  I'm still curious if there's any precedent/way for
> the llvm backend to emit warnings/errors through the clang (or other)
> front ends, though I can see how that might not be entirely practical
> given various optimizations, inlining, etc such that the source of
> this UB was not directly correlated with the input)

No, and please please don't do this. Doing this would mean that which 
warnings you get will vary with whether you run -O0 or -O2. It means 
that changing code in a library header will affect inlining decisions 
and cause new warnings (or removal of warnings) over there. It breaks 
users trying to use -Wall (raises hand) and erodes the user's confidence 
in the sanity of the compiler warnings.

This is what the Clang static analysis bits are for.

Nick

From cdavis at mymail.mines.edu  Mon Oct 24 23:09:02 2011
From: cdavis at mymail.mines.edu (Charles Davis)
Date: Mon, 24 Oct 2011 22:09:02 -0600
Subject: [llvm-commits] [PATCH] Fix compiling source files in
	subdirectories with autoconf
In-Reply-To: <0B972CF2-93FD-485E-80D1-2E9386D8D8E3@mymail.mines.edu>
References: <8963C7C2-E230-4BB3-B0EC-F0ABB529E95A@mymail.mines.edu>
	<4E9D34FF.6040001@free.fr>
	<0B972CF2-93FD-485E-80D1-2E9386D8D8E3@mymail.mines.edu>
Message-ID: <AF0BD947-D821-4DC5-BA10-61CB82C7CD79@mymail.mines.edu>

Ping...

Patch reattached.

Chip

On Oct 18, 2011, at 10:36 AM, Charles Davis wrote:

> 
> On Oct 18, 2011, at 2:12 AM, Duncan Sands wrote:
> 
>> Hi Charles,
>> 
>>> This patch fixes an issue with source files located in subdirectories (relative to the Makefile referencing them). The build system was not creating those directories in the build tree, which caused compiling the sources to fail. This patch fixes that. I encountered this getting the LLDB Host library and LLDB debug server to compile from Makefiles.
>> 
>> your patch has a bunch of changes to lib/Target/X86 in it.  I presume
>> that was an accident?
> Yeah. Here's a fixed patch. 
> 
> Chip
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From nicholas at mxc.ca  Tue Oct 25 02:05:26 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 25 Oct 2011 07:05:26 -0000
Subject: [llvm-commits] [llvm] r142912 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h
Message-ID: <20111025070526.A21F3312800A@llvm.org>

Author: nicholas
Date: Tue Oct 25 02:05:26 2011
New Revision: 142912

URL: http://llvm.org/viewvc/llvm-project?rev=142912&view=rev
Log:
Remove dead enum value. There is no DIESectionOffset.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h?rev=142912&r1=142911&r2=142912&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h Tue Oct 25 02:05:26 2011
@@ -200,7 +200,6 @@
       isInteger,
       isString,
       isLabel,
-      isSectionOffset,
       isDelta,
       isEntry,
       isBlock



From baldrick at free.fr  Tue Oct 25 02:38:20 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 25 Oct 2011 09:38:20 +0200
Subject: [llvm-commits] [llvm] r142731 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
In-Reply-To: <CADbEz-iYBk6zegG3rc19n7KdJjNPc5fTkocvrQjDeCuKBpDkMw@mail.gmail.com>
References: <20111022195820.621CC2A6C12C@llvm.org> <4EA42164.8040509@free.fr>
	<CADbEz-iYBk6zegG3rc19n7KdJjNPc5fTkocvrQjDeCuKBpDkMw@mail.gmail.com>
Message-ID: <4EA6676C.7@free.fr>

Hi Nick,

>     maybe you could use instsimplify here?  It does constant folding and more
>     besides.  It can break LCSSA form, so y so,
>     check out the loop transform users of instsimplify to seou may need to check
>     for that (ife how).
>
>
> As far as I can see, LCSSA isn't documented and I don't understand it well
> enough to know whether I'm preserving it or breaking it etc.

you don't need to know, there is a helper that tells you:
replacementPreservesLCSSAForm

  I know it involves
> creating 1-operand PHI nodes in strategic places and that's about it.
>
> Are there cases where InstructionSimplify will return a Constant that the
> constant folder won't?

Yes, because the constant folder only folds constants, while InstructionSimplify
can fold instructions to constants (eg: X - X -> 0) as well as to other pre
existing instructions (eg: (X + Y) - X -> Y).

  This code is entirely based off of a mapping to
> Constant*, so instsimplify won't help without more refactoring.

OK.

Ciao, Duncan.

>
> That refactoring would be scary because while we can represent the arbitrary
> values, we'll find ourselves effectively unrolling the loop as we build up a
> larger and larger SCEV expression. I'd like to leave unrolling to the unrolling
> pass.
>
> Nick
>
>      > @@ -4993,7 +5109,10 @@
>      >             if (const CmpInst *CI = dyn_cast<CmpInst>(I))
>      >               C = ConstantFoldCompareInstOperands(CI->getPredicate(),
>      >                                                   Operands[0],
>     Operands[1], TD);
>      > -          else
>      > +          else if (const LoadInst *LI = dyn_cast<LoadInst>(I)) {
>      > +            if (!LI->isVolatile())
>      > +              C = ConstantFoldLoadFromConstPtr(Operands[0], TD);
>      > +          } else
>      >               C = ConstantFoldInstOperands(I->getOpcode(), I->getType(),
>      >                                            Operands, TD);
>      >             if (!C) return V;
>
>     Likewise.
>
>     Ciao, Duncan.
>     _______________________________________________
>     llvm-commits mailing list
>     llvm-commits at cs.uiuc.edu <mailto:llvm-commits at cs.uiuc.edu>
>     http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>


From baldrick at free.fr  Tue Oct 25 03:07:03 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 25 Oct 2011 10:07:03 +0200
Subject: [llvm-commits] [zorg] r142899 - in
 /zorg/trunk/buildbot/osuosl/master/config: builders.py slaves.py
In-Reply-To: <20111025012853.BCA56312800A@llvm.org>
References: <20111025012853.BCA56312800A@llvm.org>
Message-ID: <4EA66E27.3090606@free.fr>

Hi Galina,

> @@ -54,18 +54,6 @@
>                                       'CXX': "/usr/bin/g++-4.2" },
>                               extra_configure_args=['--enable-shared'],
>                               timeout=600)},
> -        {'name': "llvm-i686-linux-vg_leak",
> -         'slavenames':["osu8"],
> -         'builddir':"llvm-i686-linux-vg_leak",
> -         'factory': LLVMBuilder.getLLVMBuildFactory("i686-pc-linux-gnu", valgrind=True,
> -                                                     valgrindLeakCheck=True,
> -                                                     valgrindSuppressions='utils/valgrind/i386-pc-linux-gnu.supp')},
> -        {'name': "llvm-x86_64-linux-vg_leak",
> -         'slavenames':["osu7"],
> -         'builddir':"llvm-x86_64-linux-vg_leak",
> -         'factory': LLVMBuilder.getLLVMBuildFactory("x86_64-pc-linux-gnu", valgrind=True,
> -                                                     valgrindLeakCheck=True,
> -                                                     valgrindSuppressions='utils/valgrind/x86_64-pc-linux-gnu.supp')},
>           {'name': "llvm-i686-debian",
>            'slavenames': ["gcc15"],
>            'builddir': "llvm-i686-debian",
...
maybe it would be better to comment these out rather than deleting them, to make
it easier to resurrect them on a different machine?

Ciao, Duncan.

From nicholas at mxc.ca  Tue Oct 25 03:11:54 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 25 Oct 2011 01:11:54 -0700
Subject: [llvm-commits] patch: pick direct or indirect strings in DWARF
In-Reply-To: <CADbEz-jaVTjVkBLoFU0rvU7Vc83_T0vHWeqS21QLMy=WOQmM6w@mail.gmail.com>
References: <CADbEz-jaVTjVkBLoFU0rvU7Vc83_T0vHWeqS21QLMy=WOQmM6w@mail.gmail.com>
Message-ID: <4EA66F4A.4070901@mxc.ca>

Updated patch, this one works on Darwin now too.

I have tested this patch on Darwin in both -m32 and -m64 modes. The 
difference from the previous patch is that I now use DIEDelta to compute 
a section offset against the string pool, instead of DIELabel to refer 
to the string directly (hey, it worked for me on Linux).

Please review!

Nick

Nick Lewycky wrote:
> DWARF allows string to be specified in one of two ways, either by
> writing them literally (DW_FORM_string) or by including a pointer into
> the .debug_str section and putting the NUL-terminated string there.
>
> The attached patch removes the Form argument from CompileUnit::AddString
> and changes addString to emit either a DIEString or a DIELabel depending
> on how long the string is. If the string would fit in 4 bytes in the
> direct encoding, do that. Otherwise, hoist it out into .debug_str so
> that it can be interned.
>
> This is a major issue on linux where the linker does not turn direct
> strings into indirect strings, but does merge the string tables. On
> Darwin, the linker will turn direct strings into indirect strings as
> needed. However, this change should probably be enabled on all platforms
> as it generally makes .o files smaller.
>
> Please review! The one thing I don't like about this patch is that we
> emit the bytes (via .ascii) and then emit the NUL (via. ".zero 1"). The
> alternatives I see are either to create a copy of the string, or to
> create a new emitBytesWithNUL API in MCStreamer.
>
> Nick
>
> PS. If this patch doesn't work on Darwin out-of-the-box, please try one
> thing for me: comment out the change to DIELabel::SizeOf (adding a case
> for DW_FORM_strp), and let me know whether that fixes things.
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From stpworld at narod.ru  Tue Oct 25 04:14:11 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Tue, 25 Oct 2011 13:14:11 +0400
Subject: [llvm-commits] [LLVM,
	llvm-objdump] Fix for clang-native-arm-cortex-a9.
Message-ID: <4EA67DE3.8060803@narod.ru>

Hi all,

Please find the patch in attachment that fixes llvm-objdump test 
failures for clang-native-arm-cortex-a9.

Regards,
Stepan.
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From baldrick at free.fr  Tue Oct 25 04:26:43 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 25 Oct 2011 09:26:43 -0000
Subject: [llvm-commits] [llvm] r142916 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
 test/Analysis/ScalarEvolution/trip-count11.ll
Message-ID: <20111025092643.61DA7312800A@llvm.org>

Author: baldrick
Date: Tue Oct 25 04:26:43 2011
New Revision: 142916

URL: http://llvm.org/viewvc/llvm-project?rev=142916&view=rev
Log:
Speculatively revert commits 142790 and 142843 to see if it fixes
the dragonegg and llvm-gcc self-host buildbots.  Original commit
messages:
- Reapply r142781 with fix. Original message:

  Enhance SCEV's brute force loop analysis to handle multiple PHI nodes in the
  loop header when computing the trip count.

  With this, we now constant evaluate:
    struct ListNode { const struct ListNode *next; int i; };
    static const struct ListNode node1 = {0, 1};
    static const struct ListNode node2 = {&node1, 2};
    static const struct ListNode node3 = {&node2, 3};
    int test() {
      int sum = 0;
      for (const struct ListNode *n = &node3; n != 0; n = n->next)
        sum += n->i;
      return sum;
    }

- Now that we look at all the header PHIs, we need to consider all the header PHIs
when deciding that the loop has stopped evolving. Fixes miscompile in the gcc
torture testsuite!


Removed:
    llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll
Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Analysis/ScalarEvolution/load.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=142916&r1=142915&r2=142916&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Oct 25 04:26:43 2011
@@ -4844,12 +4844,12 @@
     // EvaluateExpression adds non-phi values to the CurrentIterVals map.
     DenseMap<Instruction *, Constant *> NextIterVals;
     Constant *NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
+    if (NextPHI == CurrentIterVals[PN])
+      return RetVal = NextPHI;  // Stopped evolving!
     if (NextPHI == 0)
       return 0;        // Couldn't evaluate!
     NextIterVals[PN] = NextPHI;
 
-    bool StoppedEvolving = NextPHI == CurrentIterVals[PN];
-
     // Also evaluate the other PHI nodes.  However, we don't get to stop if we
     // cease to be able to evaluate one of them or if they stop evolving,
     // because that doesn't necessarily prevent us from computing PN.
@@ -4858,19 +4858,11 @@
       PHINode *PHI = dyn_cast<PHINode>(I->first);
       if (!PHI || PHI == PN || PHI->getParent() != Header) continue;
       Constant *&NextPHI = NextIterVals[PHI];
-      if (!NextPHI) {   // Not already computed.
-        Value *BEValue = PHI->getIncomingValue(SecondIsBackedge);
-        NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
-      }
-      if (NextPHI != I->second)
-        StoppedEvolving = false;
-    }
-
-    // If all entries in CurrentIterVals == NextIterVals then we can stop
-    // iterating, the loop can't continue to change.
-    if (StoppedEvolving)
-      return RetVal = CurrentIterVals[PN];
+      if (NextPHI) continue;    // Already computed!
 
+      Value *BEValue = PHI->getIncomingValue(SecondIsBackedge);
+      NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
+    }
     CurrentIterVals.swap(NextIterVals);
   }
 }
@@ -4890,33 +4882,29 @@
   // That's the only form we support here.
   if (PN->getNumIncomingValues() != 2) return getCouldNotCompute();
 
-  DenseMap<Instruction *, Constant *> CurrentIterVals;
-  BasicBlock *Header = L->getHeader();
-  assert(PN->getParent() == Header && "Can't evaluate PHI not in loop header!");
-
   // One entry must be a constant (coming in from outside of the loop), and the
   // second must be derived from the same PHI.
   bool SecondIsBackedge = L->contains(PN->getIncomingBlock(1));
-  PHINode *PHI = 0;
-  for (BasicBlock::iterator I = Header->begin();
-       (PHI = dyn_cast<PHINode>(I)); ++I) {
-    Constant *StartCST =
-      dyn_cast<Constant>(PHI->getIncomingValue(!SecondIsBackedge));
-    if (StartCST == 0) continue;
-    CurrentIterVals[PHI] = StartCST;
-  }
-  if (!CurrentIterVals.count(PN))
-    return getCouldNotCompute();
+  Constant *StartCST =
+    dyn_cast<Constant>(PN->getIncomingValue(!SecondIsBackedge));
+  if (StartCST == 0) return getCouldNotCompute();  // Must be a constant.
+
+  Value *BEValue = PN->getIncomingValue(SecondIsBackedge);
+  if (getConstantEvolvingPHI(BEValue, L) != PN &&
+      !isa<Constant>(BEValue))
+    return getCouldNotCompute();  // Not derived from same PHI.
 
   // Okay, we find a PHI node that defines the trip count of this loop.  Execute
   // the loop symbolically to determine when the condition gets a value of
   // "ExitWhen".
-
-  unsigned MaxIterations = MaxBruteForceIterations;   // Limit analysis.  
-  for (unsigned IterationNum = 0; IterationNum != MaxIterations;++IterationNum){
+  unsigned IterationNum = 0;
+  unsigned MaxIterations = MaxBruteForceIterations;   // Limit analysis.
+  for (Constant *PHIVal = StartCST;
+       IterationNum != MaxIterations; ++IterationNum) {
+    DenseMap<Instruction *, Constant *> PHIValMap;
+    PHIValMap[PN] = PHIVal;
     ConstantInt *CondVal =
-      dyn_cast_or_null<ConstantInt>(EvaluateExpression(Cond, L,
-                                                       CurrentIterVals, TD));
+      dyn_cast_or_null<ConstantInt>(EvaluateExpression(Cond, L, PHIValMap, TD));
 
     // Couldn't symbolically evaluate.
     if (!CondVal) return getCouldNotCompute();
@@ -4926,19 +4914,11 @@
       return getConstant(Type::getInt32Ty(getContext()), IterationNum);
     }
 
-    // Update all the PHI nodes for the next iteration.
-    DenseMap<Instruction *, Constant *> NextIterVals;
-    for (DenseMap<Instruction *, Constant *>::const_iterator
-           I = CurrentIterVals.begin(), E = CurrentIterVals.end(); I != E; ++I){
-      PHINode *PHI = dyn_cast<PHINode>(I->first);
-      if (!PHI || PHI->getParent() != Header) continue;
-      Constant *&NextPHI = NextIterVals[PHI];
-      if (NextPHI) continue;    // Already computed!
-
-      Value *BEValue = PHI->getIncomingValue(SecondIsBackedge);
-      NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
-    }
-    CurrentIterVals.swap(NextIterVals);
+    // Compute the value of the PHI node for the next iteration.
+    Constant *NextPHI = EvaluateExpression(BEValue, L, PHIValMap, TD);
+    if (NextPHI == 0 || NextPHI == PHIVal)
+      return getCouldNotCompute();// Couldn't evaluate or not making progress...
+    PHIVal = NextPHI;
   }
 
   // Too many iterations were needed to evaluate.

Modified: llvm/trunk/test/Analysis/ScalarEvolution/load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/load.ll?rev=142916&r1=142915&r2=142916&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/load.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/load.ll Tue Oct 25 04:26:43 2011
@@ -1,4 +1,5 @@
 ; RUN: opt -analyze -scalar-evolution < %s 2>&1 | FileCheck %s
+; PR11034
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
 target triple = "i386-pc-linux-gnu"
@@ -6,7 +7,6 @@
 @arr1 = internal unnamed_addr constant [50 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50], align 4
 @arr2 = internal unnamed_addr constant [50 x i32] [i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0], align 4
 
-; PR11034
 define i32 @test1() nounwind readnone {
 ; CHECK: test1
 entry:
@@ -31,35 +31,3 @@
 for.end:                                          ; preds = %for.body
   ret i32 %add2
 }
-
-
-%struct.ListNode = type { %struct.ListNode*, i32 }
-
- at node5 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node4 to %struct.ListNode*), i32 4, [4 x i8] undef }, align 8
- at node4 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node3 to %struct.ListNode*), i32 3, [4 x i8] undef }, align 8
- at node3 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node2 to %struct.ListNode*), i32 2, [4 x i8] undef }, align 8
- at node2 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node1 to %struct.ListNode*), i32 1, [4 x i8] undef }, align 8
- at node1 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* null, i32 0, [4 x i8] undef }, align 8
-
-define i32 @test2() nounwind uwtable readonly {
-; CHECK: test2
-entry:
-  br label %for.body
-
-for.body:                                         ; preds = %entry, %for.body
-  %sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-; CHECK: -->  %sum.02{{ *}}Exits: 10
-  %n.01 = phi %struct.ListNode* [ bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node5 to %struct.ListNode*), %entry ], [ %1, %for.body ]
-; CHECK: -->  %n.01{{ *}}Exits: @node1
-  %i = getelementptr inbounds %struct.ListNode* %n.01, i64 0, i32 1
-  %0 = load i32* %i, align 4
-  %add = add nsw i32 %0, %sum.02
-  %next = getelementptr inbounds %struct.ListNode* %n.01, i64 0, i32 0
-  %1 = load %struct.ListNode** %next, align 8
-; CHECK: -->  %1{{ *}}Exits: 0
-  %cmp = icmp eq %struct.ListNode* %1, null
-  br i1 %cmp, label %for.end, label %for.body
-
-for.end:                                          ; preds = %for.body
-  ret i32 %add
-}

Removed: llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll?rev=142915&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll (removed)
@@ -1,29 +0,0 @@
-; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-linux-gnu"
-
- at foo.a = internal constant [8 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7], align 16
-
-define i32 @foo() nounwind uwtable noinline {
-entry:
-  br label %for.cond
-
-for.cond:                                         ; preds = %for.inc, %entry
-  %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
-; CHECK: --> %sum.0 Exits: 28
-  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
-  %cmp = icmp ult i32 %i.0, 8
-  br i1 %cmp, label %for.inc, label %for.end
-
-for.inc:                                          ; preds = %for.cond
-  %idxprom = sext i32 %i.0 to i64
-  %arrayidx = getelementptr inbounds [8 x i32]* @foo.a, i64 0, i64 %idxprom
-  %0 = load i32* %arrayidx, align 4
-  %add = add nsw i32 %sum.0, %0
-  %inc = add nsw i32 %i.0, 1
-  br label %for.cond
-
-for.end:                                          ; preds = %for.cond
-  ret i32 %sum.0
-}



From chandlerc at gmail.com  Tue Oct 25 04:47:42 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Tue, 25 Oct 2011 09:47:42 -0000
Subject: [llvm-commits] [llvm] r142917 - in /llvm/trunk:
 lib/Analysis/BranchProbabilityInfo.cpp
 test/Analysis/BranchProbabilityInfo/loop.ll
Message-ID: <20111025094742.1791D312800A@llvm.org>

Author: chandlerc
Date: Tue Oct 25 04:47:41 2011
New Revision: 142917

URL: http://llvm.org/viewvc/llvm-project?rev=142917&view=rev
Log:
Fix the API usage in loop probability heuristics. It was incorrectly
classifying many edges as exiting which were in fact not. These mainly
formed edges into sub-loops. It was also not correctly classifying all
returning edges out of loops as leaving the loop. With this match most
of the loop heuristics are more rational.

Several serious regressions on loop-intesive benchmarks like perlbench's
loop tests when built with -enable-block-placement are fixed by these
updated heuristics. Unfortunately they in turn uncover some other
regressions. There are still several improvemenst that should be made to
loop heuristics including trip-count, and early back-edge management.

Added:
    llvm/trunk/test/Analysis/BranchProbabilityInfo/loop.ll
Modified:
    llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp

Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=142917&r1=142916&r2=142917&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Tue Oct 25 04:47:41 2011
@@ -216,8 +216,6 @@
 // Calculate Edge Weights using "Loop Branch Heuristics". Predict backedges
 // as taken, exiting edges as not-taken.
 bool BranchProbabilityInfo::calcLoopBranchHeuristics(BasicBlock *BB) {
-  uint32_t numSuccs = BB->getTerminator()->getNumSuccessors();
-
   Loop *L = LI->getLoopFor(BB);
   if (!L)
     return false;
@@ -226,17 +224,13 @@
   SmallPtrSet<BasicBlock *, 8> ExitingEdges;
   SmallPtrSet<BasicBlock *, 8> InEdges; // Edges from header to the loop.
 
-  bool isHeader = BB == L->getHeader();
-
   for (succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) {
-    BasicBlock *Succ = *I;
-    Loop *SuccL = LI->getLoopFor(Succ);
-    if (SuccL != L)
-      ExitingEdges.insert(Succ);
-    else if (Succ == L->getHeader())
-      BackEdges.insert(Succ);
-    else if (isHeader)
-      InEdges.insert(Succ);
+    if (!L->contains(*I))
+      ExitingEdges.insert(*I);
+    else if (L->getHeader() == *I)
+      BackEdges.insert(*I);
+    else
+      InEdges.insert(*I);
   }
 
   if (uint32_t numBackEdges = BackEdges.size()) {
@@ -263,9 +257,8 @@
     }
   }
 
-  uint32_t numExitingEdges = ExitingEdges.size();
-  if (uint32_t numNonExitingEdges = numSuccs - numExitingEdges) {
-    uint32_t exitWeight = LBH_NONTAKEN_WEIGHT / numNonExitingEdges;
+  if (uint32_t numExitingEdges = ExitingEdges.size()) {
+    uint32_t exitWeight = LBH_NONTAKEN_WEIGHT / numExitingEdges;
     if (exitWeight < MIN_WEIGHT)
       exitWeight = MIN_WEIGHT;
 

Added: llvm/trunk/test/Analysis/BranchProbabilityInfo/loop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BranchProbabilityInfo/loop.ll?rev=142917&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/BranchProbabilityInfo/loop.ll (added)
+++ llvm/trunk/test/Analysis/BranchProbabilityInfo/loop.ll Tue Oct 25 04:47:41 2011
@@ -0,0 +1,365 @@
+; Test the static branch probability heuristics for no-return functions.
+; RUN: opt < %s -analyze -branch-prob | FileCheck %s
+
+declare void @g1()
+declare void @g2()
+declare void @g3()
+declare void @g4()
+
+define void @test1(i32 %a, i32 %b) {
+entry:
+  br label %do.body
+; CHECK: edge entry -> do.body probability is 16 / 16 = 100%
+
+do.body:
+  %i.0 = phi i32 [ 0, %entry ], [ %inc3, %do.end ]
+  call void @g1()
+  br label %do.body1
+; CHECK: edge do.body -> do.body1 probability is 124 / 124 = 100%
+
+do.body1:
+  %j.0 = phi i32 [ 0, %do.body ], [ %inc, %do.body1 ]
+  call void @g2()
+  %inc = add nsw i32 %j.0, 1
+  %cmp = icmp slt i32 %inc, %b
+  br i1 %cmp, label %do.body1, label %do.end
+; CHECK: edge do.body1 -> do.body1 probability is 124 / 128
+; CHECK: edge do.body1 -> do.end probability is 4 / 128
+
+do.end:
+  call void @g3()
+  %inc3 = add nsw i32 %i.0, 1
+  %cmp4 = icmp slt i32 %inc3, %a
+  br i1 %cmp4, label %do.body, label %do.end5
+; CHECK: edge do.end -> do.body probability is 124 / 128
+; CHECK: edge do.end -> do.end5 probability is 4 / 128
+
+do.end5:
+  call void @g4()
+  ret void
+}
+
+define void @test2(i32 %a, i32 %b) {
+entry:
+  %cmp9 = icmp sgt i32 %a, 0
+  br i1 %cmp9, label %for.body.lr.ph, label %for.end6
+; CHECK: edge entry -> for.body.lr.ph probability is 20 / 32
+; CHECK: edge entry -> for.end6 probability is 12 / 32
+
+for.body.lr.ph:
+  %cmp27 = icmp sgt i32 %b, 0
+  br label %for.body
+; CHECK: edge for.body.lr.ph -> for.body probability is 16 / 16 = 100%
+
+for.body:
+  %i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc5, %for.end ]
+  call void @g1()
+  br i1 %cmp27, label %for.body3, label %for.end
+; CHECK: edge for.body -> for.body3 probability is 62 / 124 = 50%
+; CHECK: edge for.body -> for.end probability is 62 / 124 = 50%
+
+for.body3:
+  %j.08 = phi i32 [ %inc, %for.body3 ], [ 0, %for.body ]
+  call void @g2()
+  %inc = add nsw i32 %j.08, 1
+  %exitcond = icmp eq i32 %inc, %b
+  br i1 %exitcond, label %for.end, label %for.body3
+; CHECK: edge for.body3 -> for.end probability is 4 / 128
+; CHECK: edge for.body3 -> for.body3 probability is 124 / 128
+
+for.end:
+  call void @g3()
+  %inc5 = add nsw i32 %i.010, 1
+  %exitcond11 = icmp eq i32 %inc5, %a
+  br i1 %exitcond11, label %for.end6, label %for.body
+; CHECK: edge for.end -> for.end6 probability is 4 / 128
+; CHECK: edge for.end -> for.body probability is 124 / 128
+
+for.end6:
+  call void @g4()
+  ret void
+}
+
+define void @test3(i32 %a, i32 %b, i32* %c) {
+entry:
+  br label %do.body
+; CHECK: edge entry -> do.body probability is 16 / 16 = 100%
+
+do.body:
+  %i.0 = phi i32 [ 0, %entry ], [ %inc4, %if.end ]
+  call void @g1()
+  %0 = load i32* %c, align 4
+  %cmp = icmp slt i32 %0, 42
+  br i1 %cmp, label %do.body1, label %if.end
+; CHECK: edge do.body -> do.body1 probability is 62 / 124 = 50%
+; CHECK: edge do.body -> if.end probability is 62 / 124 = 50%
+
+do.body1:
+  %j.0 = phi i32 [ %inc, %do.body1 ], [ 0, %do.body ]
+  call void @g2()
+  %inc = add nsw i32 %j.0, 1
+  %cmp2 = icmp slt i32 %inc, %b
+  br i1 %cmp2, label %do.body1, label %if.end
+; CHECK: edge do.body1 -> do.body1 probability is 124 / 128
+; CHECK: edge do.body1 -> if.end probability is 4 / 128
+
+if.end:
+  call void @g3()
+  %inc4 = add nsw i32 %i.0, 1
+  %cmp5 = icmp slt i32 %inc4, %a
+  br i1 %cmp5, label %do.body, label %do.end6
+; CHECK: edge if.end -> do.body probability is 124 / 128
+; CHECK: edge if.end -> do.end6 probability is 4 / 128
+
+do.end6:
+  call void @g4()
+  ret void
+}
+
+define void @test4(i32 %a, i32 %b, i32* %c) {
+entry:
+  br label %do.body
+; CHECK: edge entry -> do.body probability is 16 / 16 = 100%
+
+do.body:
+  %i.0 = phi i32 [ 0, %entry ], [ %inc4, %do.end ]
+  call void @g1()
+  %0 = load i32* %c, align 4
+  %cmp = icmp slt i32 %0, 42
+  br i1 %cmp, label %return, label %do.body1
+; CHECK: edge do.body -> return probability is 4 / 128
+; CHECK: edge do.body -> do.body1 probability is 124 / 128
+
+do.body1:
+  %j.0 = phi i32 [ %inc, %do.body1 ], [ 0, %do.body ]
+  call void @g2()
+  %inc = add nsw i32 %j.0, 1
+  %cmp2 = icmp slt i32 %inc, %b
+  br i1 %cmp2, label %do.body1, label %do.end
+; CHECK: edge do.body1 -> do.body1 probability is 124 / 128
+; CHECK: edge do.body1 -> do.end probability is 4 / 128
+
+do.end:
+  call void @g3()
+  %inc4 = add nsw i32 %i.0, 1
+  %cmp5 = icmp slt i32 %inc4, %a
+  br i1 %cmp5, label %do.body, label %do.end6
+; CHECK: edge do.end -> do.body probability is 124 / 128
+; CHECK: edge do.end -> do.end6 probability is 4 / 128
+
+do.end6:
+  call void @g4()
+  br label %return
+; CHECK: edge do.end6 -> return probability is 16 / 16 = 100%
+
+return:
+  ret void
+}
+
+define void @test5(i32 %a, i32 %b, i32* %c) {
+entry:
+  br label %do.body
+; CHECK: edge entry -> do.body probability is 16 / 16 = 100%
+
+do.body:
+  %i.0 = phi i32 [ 0, %entry ], [ %inc4, %do.end ]
+  call void @g1()
+  br label %do.body1
+; CHECK: edge do.body -> do.body1 probability is 124 / 124 = 100%
+
+do.body1:
+  %j.0 = phi i32 [ 0, %do.body ], [ %inc, %if.end ]
+  %0 = load i32* %c, align 4
+  %cmp = icmp slt i32 %0, 42
+  br i1 %cmp, label %return, label %if.end
+; CHECK: edge do.body1 -> return probability is 4 / 128
+; CHECK: edge do.body1 -> if.end probability is 124 / 128
+
+if.end:
+  call void @g2()
+  %inc = add nsw i32 %j.0, 1
+  %cmp2 = icmp slt i32 %inc, %b
+  br i1 %cmp2, label %do.body1, label %do.end
+; CHECK: edge if.end -> do.body1 probability is 124 / 128
+; CHECK: edge if.end -> do.end probability is 4 / 128
+
+do.end:
+  call void @g3()
+  %inc4 = add nsw i32 %i.0, 1
+  %cmp5 = icmp slt i32 %inc4, %a
+  br i1 %cmp5, label %do.body, label %do.end6
+; CHECK: edge do.end -> do.body probability is 124 / 128
+; CHECK: edge do.end -> do.end6 probability is 4 / 128
+
+do.end6:
+  call void @g4()
+  br label %return
+; CHECK: edge do.end6 -> return probability is 16 / 16 = 100%
+
+return:
+  ret void
+}
+
+define void @test6(i32 %a, i32 %b, i32* %c) {
+entry:
+  br label %do.body
+; CHECK: edge entry -> do.body probability is 16 / 16 = 100%
+
+do.body:
+  %i.0 = phi i32 [ 0, %entry ], [ %inc4, %do.end ]
+  call void @g1()
+  br label %do.body1
+; CHECK: edge do.body -> do.body1 probability is 124 / 124 = 100%
+
+do.body1:
+  %j.0 = phi i32 [ 0, %do.body ], [ %inc, %do.cond ]
+  call void @g2()
+  %0 = load i32* %c, align 4
+  %cmp = icmp slt i32 %0, 42
+  br i1 %cmp, label %return, label %do.cond
+; CHECK: edge do.body1 -> return probability is 4 / 128
+; CHECK: edge do.body1 -> do.cond probability is 124 / 128
+
+do.cond:
+  %inc = add nsw i32 %j.0, 1
+  %cmp2 = icmp slt i32 %inc, %b
+  br i1 %cmp2, label %do.body1, label %do.end
+; CHECK: edge do.cond -> do.body1 probability is 124 / 128
+; CHECK: edge do.cond -> do.end probability is 4 / 128
+
+do.end:
+  call void @g3()
+  %inc4 = add nsw i32 %i.0, 1
+  %cmp5 = icmp slt i32 %inc4, %a
+  br i1 %cmp5, label %do.body, label %do.end6
+; CHECK: edge do.end -> do.body probability is 124 / 128
+; CHECK: edge do.end -> do.end6 probability is 4 / 128
+
+do.end6:
+  call void @g4()
+  br label %return
+; CHECK: edge do.end6 -> return probability is 16 / 16 = 100%
+
+return:
+  ret void
+}
+
+define void @test7(i32 %a, i32 %b, i32* %c) {
+entry:
+  %cmp10 = icmp sgt i32 %a, 0
+  br i1 %cmp10, label %for.body.lr.ph, label %for.end7
+; CHECK: edge entry -> for.body.lr.ph probability is 20 / 32
+; CHECK: edge entry -> for.end7 probability is 12 / 32
+
+for.body.lr.ph:
+  %cmp38 = icmp sgt i32 %b, 0
+  br label %for.body
+; CHECK: edge for.body.lr.ph -> for.body probability is 16 / 16 = 100%
+
+for.body:
+  %i.011 = phi i32 [ 0, %for.body.lr.ph ], [ %inc6, %for.inc5 ]
+  %0 = load i32* %c, align 4
+  %cmp1 = icmp eq i32 %0, %i.011
+  br i1 %cmp1, label %for.inc5, label %if.end
+; CHECK: edge for.body -> for.inc5 probability is 62 / 124 = 50%
+; CHECK: edge for.body -> if.end probability is 62 / 124 = 50%
+
+if.end:
+  call void @g1()
+  br i1 %cmp38, label %for.body4, label %for.end
+; CHECK: edge if.end -> for.body4 probability is 62 / 124 = 50%
+; CHECK: edge if.end -> for.end probability is 62 / 124 = 50%
+
+for.body4:
+  %j.09 = phi i32 [ %inc, %for.body4 ], [ 0, %if.end ]
+  call void @g2()
+  %inc = add nsw i32 %j.09, 1
+  %exitcond = icmp eq i32 %inc, %b
+  br i1 %exitcond, label %for.end, label %for.body4
+; CHECK: edge for.body4 -> for.end probability is 4 / 128
+; CHECK: edge for.body4 -> for.body4 probability is 124 / 128
+
+for.end:
+  call void @g3()
+  br label %for.inc5
+; CHECK: edge for.end -> for.inc5 probability is 124 / 124 = 100%
+
+for.inc5:
+  %inc6 = add nsw i32 %i.011, 1
+  %exitcond12 = icmp eq i32 %inc6, %a
+  br i1 %exitcond12, label %for.end7, label %for.body
+; CHECK: edge for.inc5 -> for.end7 probability is 4 / 128
+; CHECK: edge for.inc5 -> for.body probability is 124 / 128
+
+for.end7:
+  call void @g4()
+  ret void
+}
+
+define void @test8(i32 %a, i32 %b, i32* %c) {
+entry:
+  %cmp18 = icmp sgt i32 %a, 0
+  br i1 %cmp18, label %for.body.lr.ph, label %for.end15
+; CHECK: edge entry -> for.body.lr.ph probability is 20 / 32
+; CHECK: edge entry -> for.end15 probability is 12 / 32
+
+for.body.lr.ph:
+  %cmp216 = icmp sgt i32 %b, 0
+  %arrayidx5 = getelementptr inbounds i32* %c, i64 1
+  %arrayidx9 = getelementptr inbounds i32* %c, i64 2
+  br label %for.body
+; CHECK: edge for.body.lr.ph -> for.body probability is 16 / 16 = 100%
+
+for.body:
+  %i.019 = phi i32 [ 0, %for.body.lr.ph ], [ %inc14, %for.end ]
+  call void @g1()
+  br i1 %cmp216, label %for.body3, label %for.end
+; CHECK: edge for.body -> for.body3 probability is 62 / 124 = 50%
+; CHECK: edge for.body -> for.end probability is 62 / 124 = 50%
+
+for.body3:
+  %j.017 = phi i32 [ 0, %for.body ], [ %inc, %for.inc ]
+  %0 = load i32* %c, align 4
+  %cmp4 = icmp eq i32 %0, %j.017
+  br i1 %cmp4, label %for.inc, label %if.end
+; CHECK: edge for.body3 -> for.inc probability is 62 / 124 = 50%
+; CHECK: edge for.body3 -> if.end probability is 62 / 124 = 50%
+
+if.end:
+  %1 = load i32* %arrayidx5, align 4
+  %cmp6 = icmp eq i32 %1, %j.017
+  br i1 %cmp6, label %for.inc, label %if.end8
+; CHECK: edge if.end -> for.inc probability is 62 / 124 = 50%
+; CHECK: edge if.end -> if.end8 probability is 62 / 124 = 50%
+
+if.end8:
+  %2 = load i32* %arrayidx9, align 4
+  %cmp10 = icmp eq i32 %2, %j.017
+  br i1 %cmp10, label %for.inc, label %if.end12
+; CHECK: edge if.end8 -> for.inc probability is 62 / 124 = 50%
+; CHECK: edge if.end8 -> if.end12 probability is 62 / 124 = 50%
+
+if.end12:
+  call void @g2()
+  br label %for.inc
+; CHECK: edge if.end12 -> for.inc probability is 124 / 124 = 100%
+
+for.inc:
+  %inc = add nsw i32 %j.017, 1
+  %exitcond = icmp eq i32 %inc, %b
+  br i1 %exitcond, label %for.end, label %for.body3
+; CHECK: edge for.inc -> for.end probability is 4 / 128
+; CHECK: edge for.inc -> for.body3 probability is 124 / 128
+
+for.end:
+  call void @g3()
+  %inc14 = add nsw i32 %i.019, 1
+  %exitcond20 = icmp eq i32 %inc14, %a
+  br i1 %exitcond20, label %for.end15, label %for.body
+; CHECK: edge for.end -> for.end15 probability is 4 / 128
+; CHECK: edge for.end -> for.body probability is 124 / 128
+
+for.end15:
+  call void @g4()
+  ret void
+}



From baldrick at free.fr  Tue Oct 25 07:28:52 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 25 Oct 2011 12:28:52 -0000
Subject: [llvm-commits] [llvm] r142919 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/load.ll
 test/Analysis/ScalarEvolution/trip-count11.ll
Message-ID: <20111025122852.4349A312800A@llvm.org>

Author: baldrick
Date: Tue Oct 25 07:28:52 2011
New Revision: 142919

URL: http://llvm.org/viewvc/llvm-project?rev=142919&view=rev
Log:
Restore commits 142790 and 142843 - they weren't breaking the build
bots.  Original commit messages:
- Reapply r142781 with fix. Original message:

  Enhance SCEV's brute force loop analysis to handle multiple PHI nodes in the
  loop header when computing the trip count.

  With this, we now constant evaluate:
    struct ListNode { const struct ListNode *next; int i; };
    static const struct ListNode node1 = {0, 1};
    static const struct ListNode node2 = {&node1, 2};
    static const struct ListNode node3 = {&node2, 3};
    int test() {
      int sum = 0;
      for (const struct ListNode *n = &node3; n != 0; n = n->next)
        sum += n->i;
      return sum;
    }

- Now that we look at all the header PHIs, we need to consider all the header PHIs
  when deciding that the loop has stopped evolving. Fixes miscompile in the gcc
  torture testsuite!


Added:
    llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll
Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Analysis/ScalarEvolution/load.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=142919&r1=142918&r2=142919&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Oct 25 07:28:52 2011
@@ -4844,12 +4844,12 @@
     // EvaluateExpression adds non-phi values to the CurrentIterVals map.
     DenseMap<Instruction *, Constant *> NextIterVals;
     Constant *NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
-    if (NextPHI == CurrentIterVals[PN])
-      return RetVal = NextPHI;  // Stopped evolving!
     if (NextPHI == 0)
       return 0;        // Couldn't evaluate!
     NextIterVals[PN] = NextPHI;
 
+    bool StoppedEvolving = NextPHI == CurrentIterVals[PN];
+
     // Also evaluate the other PHI nodes.  However, we don't get to stop if we
     // cease to be able to evaluate one of them or if they stop evolving,
     // because that doesn't necessarily prevent us from computing PN.
@@ -4858,11 +4858,19 @@
       PHINode *PHI = dyn_cast<PHINode>(I->first);
       if (!PHI || PHI == PN || PHI->getParent() != Header) continue;
       Constant *&NextPHI = NextIterVals[PHI];
-      if (NextPHI) continue;    // Already computed!
-
-      Value *BEValue = PHI->getIncomingValue(SecondIsBackedge);
-      NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
+      if (!NextPHI) {   // Not already computed.
+        Value *BEValue = PHI->getIncomingValue(SecondIsBackedge);
+        NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
+      }
+      if (NextPHI != I->second)
+        StoppedEvolving = false;
     }
+
+    // If all entries in CurrentIterVals == NextIterVals then we can stop
+    // iterating, the loop can't continue to change.
+    if (StoppedEvolving)
+      return RetVal = CurrentIterVals[PN];
+
     CurrentIterVals.swap(NextIterVals);
   }
 }
@@ -4882,29 +4890,33 @@
   // That's the only form we support here.
   if (PN->getNumIncomingValues() != 2) return getCouldNotCompute();
 
+  DenseMap<Instruction *, Constant *> CurrentIterVals;
+  BasicBlock *Header = L->getHeader();
+  assert(PN->getParent() == Header && "Can't evaluate PHI not in loop header!");
+
   // One entry must be a constant (coming in from outside of the loop), and the
   // second must be derived from the same PHI.
   bool SecondIsBackedge = L->contains(PN->getIncomingBlock(1));
-  Constant *StartCST =
-    dyn_cast<Constant>(PN->getIncomingValue(!SecondIsBackedge));
-  if (StartCST == 0) return getCouldNotCompute();  // Must be a constant.
-
-  Value *BEValue = PN->getIncomingValue(SecondIsBackedge);
-  if (getConstantEvolvingPHI(BEValue, L) != PN &&
-      !isa<Constant>(BEValue))
-    return getCouldNotCompute();  // Not derived from same PHI.
+  PHINode *PHI = 0;
+  for (BasicBlock::iterator I = Header->begin();
+       (PHI = dyn_cast<PHINode>(I)); ++I) {
+    Constant *StartCST =
+      dyn_cast<Constant>(PHI->getIncomingValue(!SecondIsBackedge));
+    if (StartCST == 0) continue;
+    CurrentIterVals[PHI] = StartCST;
+  }
+  if (!CurrentIterVals.count(PN))
+    return getCouldNotCompute();
 
   // Okay, we find a PHI node that defines the trip count of this loop.  Execute
   // the loop symbolically to determine when the condition gets a value of
   // "ExitWhen".
-  unsigned IterationNum = 0;
-  unsigned MaxIterations = MaxBruteForceIterations;   // Limit analysis.
-  for (Constant *PHIVal = StartCST;
-       IterationNum != MaxIterations; ++IterationNum) {
-    DenseMap<Instruction *, Constant *> PHIValMap;
-    PHIValMap[PN] = PHIVal;
+
+  unsigned MaxIterations = MaxBruteForceIterations;   // Limit analysis.  
+  for (unsigned IterationNum = 0; IterationNum != MaxIterations;++IterationNum){
     ConstantInt *CondVal =
-      dyn_cast_or_null<ConstantInt>(EvaluateExpression(Cond, L, PHIValMap, TD));
+      dyn_cast_or_null<ConstantInt>(EvaluateExpression(Cond, L,
+                                                       CurrentIterVals, TD));
 
     // Couldn't symbolically evaluate.
     if (!CondVal) return getCouldNotCompute();
@@ -4914,11 +4926,19 @@
       return getConstant(Type::getInt32Ty(getContext()), IterationNum);
     }
 
-    // Compute the value of the PHI node for the next iteration.
-    Constant *NextPHI = EvaluateExpression(BEValue, L, PHIValMap, TD);
-    if (NextPHI == 0 || NextPHI == PHIVal)
-      return getCouldNotCompute();// Couldn't evaluate or not making progress...
-    PHIVal = NextPHI;
+    // Update all the PHI nodes for the next iteration.
+    DenseMap<Instruction *, Constant *> NextIterVals;
+    for (DenseMap<Instruction *, Constant *>::const_iterator
+           I = CurrentIterVals.begin(), E = CurrentIterVals.end(); I != E; ++I){
+      PHINode *PHI = dyn_cast<PHINode>(I->first);
+      if (!PHI || PHI->getParent() != Header) continue;
+      Constant *&NextPHI = NextIterVals[PHI];
+      if (NextPHI) continue;    // Already computed!
+
+      Value *BEValue = PHI->getIncomingValue(SecondIsBackedge);
+      NextPHI = EvaluateExpression(BEValue, L, CurrentIterVals, TD);
+    }
+    CurrentIterVals.swap(NextIterVals);
   }
 
   // Too many iterations were needed to evaluate.

Modified: llvm/trunk/test/Analysis/ScalarEvolution/load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/load.ll?rev=142919&r1=142918&r2=142919&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/load.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/load.ll Tue Oct 25 07:28:52 2011
@@ -1,5 +1,4 @@
 ; RUN: opt -analyze -scalar-evolution < %s 2>&1 | FileCheck %s
-; PR11034
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
 target triple = "i386-pc-linux-gnu"
@@ -7,6 +6,7 @@
 @arr1 = internal unnamed_addr constant [50 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50], align 4
 @arr2 = internal unnamed_addr constant [50 x i32] [i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0], align 4
 
+; PR11034
 define i32 @test1() nounwind readnone {
 ; CHECK: test1
 entry:
@@ -31,3 +31,35 @@
 for.end:                                          ; preds = %for.body
   ret i32 %add2
 }
+
+
+%struct.ListNode = type { %struct.ListNode*, i32 }
+
+ at node5 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node4 to %struct.ListNode*), i32 4, [4 x i8] undef }, align 8
+ at node4 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node3 to %struct.ListNode*), i32 3, [4 x i8] undef }, align 8
+ at node3 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node2 to %struct.ListNode*), i32 2, [4 x i8] undef }, align 8
+ at node2 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node1 to %struct.ListNode*), i32 1, [4 x i8] undef }, align 8
+ at node1 = internal constant { %struct.ListNode*, i32, [4 x i8] } { %struct.ListNode* null, i32 0, [4 x i8] undef }, align 8
+
+define i32 @test2() nounwind uwtable readonly {
+; CHECK: test2
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ]
+; CHECK: -->  %sum.02{{ *}}Exits: 10
+  %n.01 = phi %struct.ListNode* [ bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node5 to %struct.ListNode*), %entry ], [ %1, %for.body ]
+; CHECK: -->  %n.01{{ *}}Exits: @node1
+  %i = getelementptr inbounds %struct.ListNode* %n.01, i64 0, i32 1
+  %0 = load i32* %i, align 4
+  %add = add nsw i32 %0, %sum.02
+  %next = getelementptr inbounds %struct.ListNode* %n.01, i64 0, i32 0
+  %1 = load %struct.ListNode** %next, align 8
+; CHECK: -->  %1{{ *}}Exits: 0
+  %cmp = icmp eq %struct.ListNode* %1, null
+  br i1 %cmp, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret i32 %add
+}

Added: llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll?rev=142919&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll (added)
+++ llvm/trunk/test/Analysis/ScalarEvolution/trip-count11.ll Tue Oct 25 07:28:52 2011
@@ -0,0 +1,29 @@
+; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+ at foo.a = internal constant [8 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7], align 16
+
+define i32 @foo() nounwind uwtable noinline {
+entry:
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
+; CHECK: --> %sum.0 Exits: 28
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
+  %cmp = icmp ult i32 %i.0, 8
+  br i1 %cmp, label %for.inc, label %for.end
+
+for.inc:                                          ; preds = %for.cond
+  %idxprom = sext i32 %i.0 to i64
+  %arrayidx = getelementptr inbounds [8 x i32]* @foo.a, i64 0, i64 %idxprom
+  %0 = load i32* %arrayidx, align 4
+  %add = add nsw i32 %sum.0, %0
+  %inc = add nsw i32 %i.0, 1
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  ret i32 %sum.0
+}



From baldrick at free.fr  Tue Oct 25 07:30:22 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 25 Oct 2011 12:30:22 -0000
Subject: [llvm-commits] [llvm] r142920 -
	/llvm/trunk/lib/CodeGen/BranchFolding.cpp
Message-ID: <20111025123022.A0F64312800A@llvm.org>

Author: baldrick
Date: Tue Oct 25 07:30:22 2011
New Revision: 142920

URL: http://llvm.org/viewvc/llvm-project?rev=142920&view=rev
Log:
Revert commit 142891.  Takumi bisected the tablegen miscompiles
down to this commit.  Original commit message:

An MBB which branches to an EH landing pad shouldn't be considered for tail merging.

In SjLj EH, the jump to the landing pad is not done explicitly through a branch
statement. The EH landing pad is added as a successor to the throwing
BB. Because of that however, the branch folding pass could mistakenly think that
it could merge the throwing BB with another BB. This isn't safe to do.
<rdar://problem/10334833>


Modified:
    llvm/trunk/lib/CodeGen/BranchFolding.cpp

Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=142920&r1=142919&r2=142920&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Oct 25 07:30:22 2011
@@ -913,8 +913,7 @@
               // reinsert conditional branch only, for now
               TII->InsertBranch(*PBB, (TBB == IBB) ? FBB : TBB, 0, NewCond, dl);
           }
-          if (!PBB->getLandingPadSuccessor())
-            MergePotentials.push_back(MergePotentialsElt(HashEndOfMBB(PBB),*P));
+          MergePotentials.push_back(MergePotentialsElt(HashEndOfMBB(PBB), *P));
         }
       }
       // If this is a large problem, avoid visiting the same basic blocks



From peter at pcc.me.uk  Tue Oct 25 09:38:39 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Tue, 25 Oct 2011 14:38:39 -0000
Subject: [llvm-commits] [zorg] r142922 - /zorg/trunk/.gitignore
Message-ID: <20111025143839.69D9E312800A@llvm.org>

Author: pcc
Date: Tue Oct 25 09:38:39 2011
New Revision: 142922

URL: http://llvm.org/viewvc/llvm-project?rev=142922&view=rev
Log:
Add a .gitignore file

Added:
    zorg/trunk/.gitignore

Added: zorg/trunk/.gitignore
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/.gitignore?rev=142922&view=auto
==============================================================================
--- zorg/trunk/.gitignore (added)
+++ zorg/trunk/.gitignore Tue Oct 25 09:38:39 2011
@@ -0,0 +1 @@
+*.pyc



From peter at pcc.me.uk  Tue Oct 25 09:38:45 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Tue, 25 Oct 2011 14:38:45 -0000
Subject: [llvm-commits] [zorg] r142923 -
	/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
Message-ID: <20111025143846.03505312800A@llvm.org>

Author: pcc
Date: Tue Oct 25 09:38:45 2011
New Revision: 142923

URL: http://llvm.org/viewvc/llvm-project?rev=142923&view=rev
Log:
Add trunk_revision and force_checkout parameters to ClangBuilder.getClangBuildFactory()

trunk_revision is used to specify a specific revision of LLVM/Clang
trunk to check out.  It is subject to WithProperties substitution.

force_checkout is used to control whether to supply the --force
argument to "svn checkout" when checking out LLVM/Clang.  It currently
only works if trunk_revision is set.

Modified:
    zorg/trunk/zorg/buildbot/builders/ClangBuilder.py

Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=142923&r1=142922&r2=142923&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original)
+++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Tue Oct 25 09:38:45 2011
@@ -34,6 +34,8 @@
             env={}, # Environmental variables for all steps.
             extra_configure_args=[],
             use_pty_in_tests=False,
+            trunk_revision=None,
+            force_checkout=False,
             checkout_compiler_rt=False):
     # Prepare environmental variables. Set here all env we want everywhere.
     merged_env = {
@@ -79,22 +81,48 @@
                                env=merged_env))
 
     # Checkout sources.
-    f.addStep(SVN(name='svn-llvm',
-                  mode='update',
-                  baseURL='http://llvm.org/svn/llvm-project/llvm/',
-                  defaultBranch='trunk',
-                  workdir=llvm_srcdir))
-    f.addStep(SVN(name='svn-clang',
-                  mode='update',
-                  baseURL='http://llvm.org/svn/llvm-project/cfe/',
-                  defaultBranch='trunk',
-                  workdir='%s/tools/clang' % llvm_srcdir))
-    if checkout_compiler_rt:
-        f.addStep(SVN(name='svn-compiler-rt',
+    if trunk_revision:
+        # The SVN build step provides no mechanism to check out a specific revision
+        # based on a property, so just run the commands directly here.
+        svn_co = ['svn', 'checkout']
+        if force_checkout:
+            svn_co += ['--force']
+        svn_co += ['--revision', WithProperties(trunk_revision)]
+
+        svn_co_llvm = svn_co + \
+          [WithProperties('http://llvm.org/svn/llvm-project/llvm/trunk@%s' %
+                          trunk_revision),
+           llvm_srcdir]
+        svn_co_clang = svn_co + \
+          [WithProperties('http://llvm.org/svn/llvm-project/cfe/trunk@%s' %
+                          trunk_revision),
+           '%s/tools/clang' % llvm_srcdir]
+
+        f.addStep(ShellCommand(name='svn-llvm',
+                               command=svn_co_llvm,
+                               haltOnFailure=True,
+                               workdir='.'))
+        f.addStep(ShellCommand(name='svn-clang',
+                               command=svn_co_clang,
+                               haltOnFailure=True,
+                               workdir='.'))
+    else:
+        f.addStep(SVN(name='svn-llvm',
+                      mode='update',
+                      baseURL='http://llvm.org/svn/llvm-project/llvm/',
+                      defaultBranch='trunk',
+                      workdir=llvm_srcdir))
+        f.addStep(SVN(name='svn-clang',
                       mode='update',
-                      baseURL='http://llvm.org/svn/llvm-project/compiler-rt/',
+                      baseURL='http://llvm.org/svn/llvm-project/cfe/',
                       defaultBranch='trunk',
-                      workdir='%s/projects/compiler-rt' % llvm_srcdir))
+                      workdir='%s/tools/clang' % llvm_srcdir))
+        if checkout_compiler_rt:
+            f.addStep(SVN(name='svn-compiler-rt',
+                          mode='update',
+                          baseURL='http://llvm.org/svn/llvm-project/compiler-rt/',
+                          defaultBranch='trunk',
+                          workdir='%s/projects/compiler-rt' % llvm_srcdir))
 
     # Clean up llvm (stage 1); unless in-dir.
     if clean and llvm_srcdir != llvm_1_objdir:



From peter at pcc.me.uk  Tue Oct 25 09:38:52 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Tue, 25 Oct 2011 14:38:52 -0000
Subject: [llvm-commits] [zorg] r142924 -
	/zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py
Message-ID: <20111025143852.A2756312800A@llvm.org>

Author: pcc
Date: Tue Oct 25 09:38:52 2011
New Revision: 142924

URL: http://llvm.org/viewvc/llvm-project?rev=142924&view=rev
Log:
Add an LLDB builder module

Added:
    zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py

Added: zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py?rev=142924&view=auto
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py (added)
+++ zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py Tue Oct 25 09:38:52 2011
@@ -0,0 +1,62 @@
+import os
+
+import buildbot
+import buildbot.process.factory
+from buildbot.steps.source import SVN
+from buildbot.steps.shell import SetProperty, ShellCommand
+from buildbot.process.properties import WithProperties
+
+import ClangBuilder
+
+def getLLDBBuildFactory(triple, outOfDir=False, useTwoStage=False,
+                        always_install=False, extra_configure_args=[],
+                        *args, **kwargs):
+    # FIXME: this code is copied from getClangBuildFactory
+    inDir = not outOfDir and not useTwoStage
+    if inDir:
+        llvm_srcdir = "llvm"
+        llvm_1_objdir = "llvm"
+        if always_install:
+            llvm_1_installdir = "llvm.install"
+        else:
+            llvm_1_installdir = None
+    else:
+        llvm_srcdir = "llvm.src"
+        llvm_1_objdir = "llvm.obj"
+        llvm_1_installdir = "llvm.install.1"
+        llvm_2_objdir = "llvm.obj.2"
+        llvm_2_installdir = "llvm.install"
+
+    f = buildbot.process.factory.BuildFactory()
+
+    f.addStep(SVN(name='svn-lldb',
+                  mode='update',
+                  baseURL='https://llvm.org/svn/llvm-project/lldb/',
+                  defaultBranch='trunk',
+                  workdir='%s/tools/lldb' % llvm_srcdir))
+    f.addStep(SetProperty(command='grep ^our.*llvm_revision scripts/build-llvm.pl | cut -d \\" -f 2',
+                          property='llvmrev',
+                          workdir='%s/tools/lldb' % llvm_srcdir))
+
+    # We use force_checkout to ensure the initial checkout is not aborted due to
+    # the presence of the tools/lldb directory
+    clangf = ClangBuilder.getClangBuildFactory(triple, test=False,
+                                               outOfDir=outOfDir,
+                                               useTwoStage=useTwoStage,
+                                               always_install=always_install,
+                                               extra_configure_args=
+                                                 extra_configure_args+
+                                                 ['--enable-targets=host'],
+                                               trunk_revision='%(llvmrev)s',
+                                               force_checkout=True,
+                                               *args, **kwargs)
+    f.steps += clangf.steps
+
+    # Test.
+    f.addStep(ShellCommand(name="test",
+                           command=['nice', '-n', '10',
+                                    'make'],
+                           haltOnFailure=True, description="test lldb",
+                           workdir='%s/tools/lldb/test' % llvm_1_objdir))
+
+    return f



From peter at pcc.me.uk  Tue Oct 25 09:39:00 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Tue, 25 Oct 2011 14:39:00 -0000
Subject: [llvm-commits] [zorg] r142925 - in
 /zorg/trunk/buildbot/osuosl/master: config/builders.py master.cfg
Message-ID: <20111025143900.11D84312800A@llvm.org>

Author: pcc
Date: Tue Oct 25 09:38:59 2011
New Revision: 142925

URL: http://llvm.org/viewvc/llvm-project?rev=142925&view=rev
Log:
Add LLDB builders for osuosl

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py
    zorg/trunk/buildbot/osuosl/master/master.cfg

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=142925&r1=142924&r2=142925&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Tue Oct 25 09:38:59 2011
@@ -26,6 +26,10 @@
 reload(PollyBuilder)
 from zorg.buildbot.builders import PollyBuilder
 
+from zorg.buildbot.builders import LLDBBuilder
+reload(LLDBBuilder)
+from zorg.buildbot.builders import LLDBBuilder
+
 from buildbot.steps.source import SVN
 from zorg.buildbot.commands.ClangTestCommand import ClangTestCommand
 
@@ -266,6 +270,30 @@
          'factory': PollyBuilder.getPollyBuildFactory()}
        ]
 
+# LLDB builders.
+def _get_lldb_builders():
+    gcc_latest_env = {
+        'LD_LIBRARY_PATH': '/opt/cfarm/mpc-latest/lib:/opt/cfarm/mpfr-latest/lib:/opt/cfarm/gmp-latest/lib',
+        'CC':  '/opt/cfarm/gcc-core-latest/bin/gcc',
+        'CXX': '/opt/cfarm/gcc-core-latest/bin/g++'}
+
+    gcc_m32_latest_env = gcc_latest_env.copy()
+    gcc_m32_latest_env['CC'] += ' -m32'
+    gcc_m32_latest_env['CXX'] += ' -m32'
+
+    return [
+        {'name': "lldb-x86_64-linux",
+         'slavenames': ["gcc14"],
+         'builddir': "lldb-x86_64",
+         'factory': LLDBBuilder.getLLDBBuildFactory(triple="x86_64-pc-linux-gnu",
+                                                    env=gcc_latest_env)},
+        {'name': "lldb-i686-debian",
+         'slavenames': ["gcc15"],
+         'builddir': "lldb-i686-debian",
+         'factory': LLDBBuilder.getLLDBBuildFactory(triple="i686-pc-linux-gnu",
+                                                    env=gcc_m32_latest_env)}
+       ]
+
 def _get_experimental_builders():
     return [
 
@@ -763,6 +791,10 @@
         b['category'] = 'polly'
         yield b
 
+    for b in _get_lldb_builders():
+        b['category'] = 'lldb'
+        yield b
+
     for b in _get_experimental_builders():
         yield b
 

Modified: zorg/trunk/buildbot/osuosl/master/master.cfg
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/master.cfg?rev=142925&r1=142924&r2=142925&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/master.cfg (original)
+++ zorg/trunk/buildbot/osuosl/master/master.cfg Tue Oct 25 09:38:59 2011
@@ -51,6 +51,7 @@
   c['change_source'].append(LLVMPoller("llvm-gcc-4.2/trunk"))
   c['change_source'].append(LLVMPoller("compiler-rt/trunk"))
   c['change_source'].append(LLVMPoller("dragonegg/trunk"))
+  c['change_source'].append(LLVMPoller("lldb/trunk"))
 #  c['change_source'].append(LLVMPoller("test-suite/trunk"))
 
 ####### BUILDERS



From criswell at uiuc.edu  Tue Oct 25 10:08:10 2011
From: criswell at uiuc.edu (John Criswell)
Date: Tue, 25 Oct 2011 15:08:10 -0000
Subject: [llvm-commits] [poolalloc] r142927 -
	/poolalloc/trunk/lib/AssistDS/ArgCast.cpp
Message-ID: <20111025150810.DF2A0312800A@llvm.org>

Author: criswell
Date: Tue Oct 25 10:08:10 2011
New Revision: 142927

URL: http://llvm.org/viewvc/llvm-project?rev=142927&view=rev
Log:
Squelch a warning in Release builds by using abort() to terminate the pass
instead of relying on assert() (which is a no-op in Release builds).
Thanks to Pavel Borzenkov for finding this problem.

Modified:
    poolalloc/trunk/lib/AssistDS/ArgCast.cpp

Modified: poolalloc/trunk/lib/AssistDS/ArgCast.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/ArgCast.cpp?rev=142927&r1=142926&r2=142927&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/ArgCast.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/ArgCast.cpp Tue Oct 25 10:08:10 2011
@@ -188,6 +188,7 @@
         else {
           // TODO: I'm not sure what right behavior is here, but this case should be handled.
           assert(0 && "Unexpected type conversion in call!");
+          abort();
         }
         CI->replaceAllUsesWith(RetCast);
       } else {



From bob.wilson at apple.com  Tue Oct 25 10:50:32 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 25 Oct 2011 08:50:32 -0700
Subject: [llvm-commits] [llvm] r142896 - in /llvm/trunk/test/Bitcode:
 sse42_crc32.ll sse42_crc32.ll.bc ssse3_palignr.ll ssse3_palignr.ll.bc
In-Reply-To: <20111025012220.6FCB0312800A@llvm.org>
References: <20111025012220.6FCB0312800A@llvm.org>
Message-ID: <6D6DA0D2-AAC9-4EB9-8373-AA35B5667071@apple.com>

This completely defeats the point of those tests.  The bitcode reader needs to be able to read old bitcode files and to auto-upgrade various constructs such as intrinsics when it does that.  That is what those tests were checking.  If you ran into issues it is probably because you broke something that wasn't supposed to be broken.

On Oct 24, 2011, at 6:22 PM, Chad Rosier wrote:

> Author: mcrosier
> Date: Mon Oct 24 20:22:20 2011
> New Revision: 142896
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=142896&view=rev
> Log:
> Fix these test cases to not use .bc files.  Otherwise, we run into issues with
> bitcode reader/writer backward compatibility.
> 
> Removed:
>    llvm/trunk/test/Bitcode/sse42_crc32.ll.bc
>    llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc
> Modified:
>    llvm/trunk/test/Bitcode/sse42_crc32.ll
>    llvm/trunk/test/Bitcode/ssse3_palignr.ll
> 
> Modified: llvm/trunk/test/Bitcode/sse42_crc32.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/sse42_crc32.ll?rev=142896&r1=142895&r2=142896&view=diff
> ==============================================================================
> --- llvm/trunk/test/Bitcode/sse42_crc32.ll (original)
> +++ llvm/trunk/test/Bitcode/sse42_crc32.ll Mon Oct 24 20:22:20 2011
> @@ -3,7 +3,7 @@
> ;
> ; Rdar: 9472944
> ;
> -; RUN: llvm-dis < %s.bc | FileCheck %s
> +; RUN: opt < %s | llvm-dis | FileCheck %s
> 
> ; crc32.8 should upgrade to crc32.32.8
> ; CHECK: i32 @llvm.x86.sse42.crc32.32.8(
> @@ -26,3 +26,18 @@
> ; CHECK-NOT: i64 @llvm.x86.sse42.crc64.64(
> 
> 
> +define void @foo() nounwind readnone ssp {
> +entry:
> +  %0 = call i32 @llvm.x86.sse42.crc32.8(i32 0, i8 0)
> +  %1 = call i32 @llvm.x86.sse42.crc32.16(i32 0, i16 0)
> +  %2 = call i32 @llvm.x86.sse42.crc32.32(i32 0, i32 0)
> +  %3 = call i64 @llvm.x86.sse42.crc64.8(i64 0, i8 0)
> +  %4 = call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 0)
> +  ret void
> +}
> +
> +declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind readnone
> +declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind readnone
> +declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind readnone
> +declare i64 @llvm.x86.sse42.crc64.8(i64, i8) nounwind readnone
> +declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone
> 
> Removed: llvm/trunk/test/Bitcode/sse42_crc32.ll.bc
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/sse42_crc32.ll.bc?rev=142895&view=auto
> ==============================================================================
> Binary file - no diff available.
> 
> Modified: llvm/trunk/test/Bitcode/ssse3_palignr.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/ssse3_palignr.ll?rev=142896&r1=142895&r2=142896&view=diff
> ==============================================================================
> --- llvm/trunk/test/Bitcode/ssse3_palignr.ll (original)
> +++ llvm/trunk/test/Bitcode/ssse3_palignr.ll Mon Oct 24 20:22:20 2011
> @@ -1,2 +1,82 @@
> -; RUN: llvm-dis < %s.bc | FileCheck %s 
> +; RUN: opt < %s | llvm-dis | FileCheck %s
> ; CHECK-NOT: {@llvm\\.palign}
> +
> +define <4 x i32> @align1(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
> +entry:
> +  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
> +  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
> +  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 15) ; <<2 x i64>> [#uses=1]
> +  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
> +  ret <4 x i32> %3
> +}
> +
> +define double @align8(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
> +entry:
> +  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
> +  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
> +  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 7) ; <<1 x i64>> [#uses=1]
> +  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
> +  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
> +  ret double %retval12
> +}
> +
> +declare <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64>, <1 x i64>, i8) nounwind readnone
> +
> +define double @align7(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
> +entry:
> +  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
> +  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
> +  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 16) ; <<1 x i64>> [#uses=1]
> +  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
> +  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
> +  ret double %retval12
> +}
> +
> +define double @align6(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
> +entry:
> +  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
> +  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
> +  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 9) ; <<1 x i64>> [#uses=1]
> +  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
> +  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
> +  ret double %retval12
> +}
> +
> +define double @align5(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
> +entry:
> +  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
> +  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
> +  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 8) ; <<1 x i64>> [#uses=1]
> +  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
> +  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
> +  ret double %retval12
> +}
> +
> +define <4 x i32> @align4(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
> +entry:
> +  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
> +  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
> +  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) ; <<2 x i64>> [#uses=1]
> +  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
> +  ret <4 x i32> %3
> +}
> +
> +declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
> +
> +define <4 x i32> @align3(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
> +entry:
> +  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
> +  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
> +  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 17) ; <<2 x i64>> [#uses=1]
> +  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
> +  ret <4 x i32> %3
> +}
> +
> +define <4 x i32> @align2(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
> +entry:
> +  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
> +  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
> +  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 16) ; <<2 x i64>> [#uses=1]
> +  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
> +  ret <4 x i32> %3
> +}
> 
> Removed: llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc?rev=142895&view=auto
> ==============================================================================
> Binary file - no diff available.
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From stpworld at narod.ru  Tue Oct 25 12:21:58 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Tue, 25 Oct 2011 21:21:58 +0400
Subject: [llvm-commits] [LLVM, llvm-nm,
 arm] Fix for nm-trivial-object.test and for nm-archive.test
In-Reply-To: <4EA5BE51.7040105@narod.ru>
References: <4EA1BF05.7030307@narod.ru>
	<CACXTSinHzMOEUhDi2nJ17ZFs54zwX5WuNbpQgh+Qrw=scVTeow@mail.gmail.com>
	<4EA514A1.3020109@narod.ru> <4EA5BE51.7040105@narod.ru>
Message-ID: <4EA6F036.1000300@narod.ru>

ping.

Regards,
Stepan.

Stepan Dyatkovskiy wrote:
> Hi all. Please find the reworked patch in attachment.
>
> Regards,
> Stepan.
>
> Stepan Dyatkovskiy wrote:
>> Hi,
>> Yes, you right. Sorry, I actually mean clang-native-arm-cortex-a9:
>> http://lab.llvm.org:8011/builders/clang-native-arm-cortex-a9/builds/155
>>
>> Regards,
>> Stepan.
>>
>> Michael Spencer wrote:
>>> On Fri, Oct 21, 2011 at 11:50 AM, Stepan
>>> Dyatkovskiy<stpworld at narod.ru> wrote:
>>>> Hi all,
>>>> Please find the patch for review that fixes nm-trivial-object.test and
>>>> nm-archive.test for arm architecture.
>>>>
>>>> Regards,
>>>> Stepan
>>>
>>> These tests are currently passing on the llvm-arm-linux buildbot.
>>> Where are you encountering the failure?
>>>
>>> This does, however, show that the code is currently wrong. It's trying
>>> to print a uint64_t as an unsigned. The code needs to use the address
>>> size from the object file to print either 8 byte or 4 byte addresses
>>> and sizes using the correct format string.
>>>
>>> Thanks for bringing this up!
>>>
>>> - Michael Spencer
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From bruno.cardoso at gmail.com  Tue Oct 25 12:30:47 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 25 Oct 2011 17:30:47 -0000
Subject: [llvm-commits] [llvm] r142930 -
	/llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp
Message-ID: <20111025173047.98B85312800A@llvm.org>

Author: bruno
Date: Tue Oct 25 12:30:47 2011
New Revision: 142930

URL: http://llvm.org/viewvc/llvm-project?rev=142930&view=rev
Log:
Corrects previously incorrect $sp change in MipsCompilationCallback.
The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned

Patch by Petar Jovanovic.

Modified:
    llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp?rev=142930&r1=142929&r2=142930&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp Tue Oct 25 12:30:47 2011
@@ -57,11 +57,11 @@
     ".globl " ASMPREFIX "MipsCompilationCallback\n"
     ASMPREFIX "MipsCompilationCallback:\n"
     ".ent " ASMPREFIX "MipsCompilationCallback\n"
-    ".frame  $29, 32, $31\n"
+    ".frame  $sp, 32, $ra\n"
     ".set  noreorder\n"
     ".cpload $t9\n"
 
-    "addiu $sp, $sp, -60\n"
+    "addiu $sp, $sp, -64\n"
     ".cprestore 16\n"
 
     // Save argument registers a0, a1, a2, a3, f12, f14 since they may contain
@@ -76,8 +76,8 @@
     "sw $a3, 32($sp)\n"
     "sw $ra, 36($sp)\n"
     "sw $t8, 40($sp)\n"
-    "sdc1 $f12, 44($sp)\n"
-    "sdc1 $f14, 52($sp)\n"
+    "sdc1 $f12, 48($sp)\n"
+    "sdc1 $f14, 56($sp)\n"
 
     // t8 points at the end of function stub. Pass the beginning of the stub
     // to the MipsCompilationCallbackC.
@@ -92,9 +92,9 @@
     "lw $a3, 32($sp)\n"
     "lw $ra, 36($sp)\n"
     "lw $t8, 40($sp)\n"
-    "ldc1 $f12, 44($sp)\n"
-    "ldc1 $f14, 52($sp)\n"
-    "addiu $sp, $sp, 60\n"
+    "ldc1 $f12, 48($sp)\n"
+    "ldc1 $f14, 56($sp)\n"
+    "addiu $sp, $sp, 64\n"
 
     // Jump to the (newly modified) stub to invoke the real function.
     "addiu $t8, $t8, -16\n"



From mcrosier at apple.com  Tue Oct 25 12:33:47 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Tue, 25 Oct 2011 10:33:47 -0700
Subject: [llvm-commits] [llvm] r142896 - in /llvm/trunk/test/Bitcode:
 sse42_crc32.ll sse42_crc32.ll.bc ssse3_palignr.ll ssse3_palignr.ll.bc
In-Reply-To: <6D6DA0D2-AAC9-4EB9-8373-AA35B5667071@apple.com>
References: <20111025012220.6FCB0312800A@llvm.org>
	<6D6DA0D2-AAC9-4EB9-8373-AA35B5667071@apple.com>
Message-ID: <1ECBC53E-D20D-4FA0-8C9D-6A52434D2B17@apple.com>

Bob,
The auto-upgrade code is called when parsing either an IR file or a bitcode file.  Previously, the test was exercising this code when reading the bitcode file, but now it's exercised when reading the IR (I could run opt -S and FileCheck that output to simplify things).  Thus, I believe it tests the same code, but in a slightly different way.  The main difference being I don't rely on bitcode backward compatibility, which I believe is a entirely different issue (i.e., these tests check API backward compatibility, not bitcode backward compatibility).  I'm fine with reverting the commit, but please tell me where I'm being short sighted.

In terms of breaking bitcode backward compatibility, this was expected with my change.  My long term goal is to preserve the Value use-lists ordering across bitcode writing/reading, which I don't expect to break compatibility.  However, if you grep for FIXME comments in the Bitcode directories you'll find a number of comments along the lines of "FIXME: Remove in LLVM 3.0".  It's not necessary that I fix those, I was just hoping to remove some cruft before beginning my other work.

 Chad


On Oct 25, 2011, at 8:50 AM, Bob Wilson wrote:

> This completely defeats the point of those tests.  The bitcode reader needs to be able to read old bitcode files and to auto-upgrade various constructs such as intrinsics when it does that.  That is what those tests were checking.  If you ran into issues it is probably because you broke something that wasn't supposed to be broken.
> 
> On Oct 24, 2011, at 6:22 PM, Chad Rosier wrote:
> 
>> Author: mcrosier
>> Date: Mon Oct 24 20:22:20 2011
>> New Revision: 142896
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=142896&view=rev
>> Log:
>> Fix these test cases to not use .bc files.  Otherwise, we run into issues with
>> bitcode reader/writer backward compatibility.
>> 
>> Removed:
>>   llvm/trunk/test/Bitcode/sse42_crc32.ll.bc
>>   llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc
>> Modified:
>>   llvm/trunk/test/Bitcode/sse42_crc32.ll
>>   llvm/trunk/test/Bitcode/ssse3_palignr.ll
>> 
>> Modified: llvm/trunk/test/Bitcode/sse42_crc32.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/sse42_crc32.ll?rev=142896&r1=142895&r2=142896&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/Bitcode/sse42_crc32.ll (original)
>> +++ llvm/trunk/test/Bitcode/sse42_crc32.ll Mon Oct 24 20:22:20 2011
>> @@ -3,7 +3,7 @@
>> ;
>> ; Rdar: 9472944
>> ;
>> -; RUN: llvm-dis < %s.bc | FileCheck %s
>> +; RUN: opt < %s | llvm-dis | FileCheck %s
>> 
>> ; crc32.8 should upgrade to crc32.32.8
>> ; CHECK: i32 @llvm.x86.sse42.crc32.32.8(
>> @@ -26,3 +26,18 @@
>> ; CHECK-NOT: i64 @llvm.x86.sse42.crc64.64(
>> 
>> 
>> +define void @foo() nounwind readnone ssp {
>> +entry:
>> +  %0 = call i32 @llvm.x86.sse42.crc32.8(i32 0, i8 0)
>> +  %1 = call i32 @llvm.x86.sse42.crc32.16(i32 0, i16 0)
>> +  %2 = call i32 @llvm.x86.sse42.crc32.32(i32 0, i32 0)
>> +  %3 = call i64 @llvm.x86.sse42.crc64.8(i64 0, i8 0)
>> +  %4 = call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 0)
>> +  ret void
>> +}
>> +
>> +declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind readnone
>> +declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind readnone
>> +declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind readnone
>> +declare i64 @llvm.x86.sse42.crc64.8(i64, i8) nounwind readnone
>> +declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone
>> 
>> Removed: llvm/trunk/test/Bitcode/sse42_crc32.ll.bc
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/sse42_crc32.ll.bc?rev=142895&view=auto
>> ==============================================================================
>> Binary file - no diff available.
>> 
>> Modified: llvm/trunk/test/Bitcode/ssse3_palignr.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/ssse3_palignr.ll?rev=142896&r1=142895&r2=142896&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/Bitcode/ssse3_palignr.ll (original)
>> +++ llvm/trunk/test/Bitcode/ssse3_palignr.ll Mon Oct 24 20:22:20 2011
>> @@ -1,2 +1,82 @@
>> -; RUN: llvm-dis < %s.bc | FileCheck %s 
>> +; RUN: opt < %s | llvm-dis | FileCheck %s
>> ; CHECK-NOT: {@llvm\\.palign}
>> +
>> +define <4 x i32> @align1(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
>> +entry:
>> +  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
>> +  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
>> +  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 15) ; <<2 x i64>> [#uses=1]
>> +  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
>> +  ret <4 x i32> %3
>> +}
>> +
>> +define double @align8(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
>> +entry:
>> +  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
>> +  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
>> +  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 7) ; <<1 x i64>> [#uses=1]
>> +  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
>> +  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
>> +  ret double %retval12
>> +}
>> +
>> +declare <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64>, <1 x i64>, i8) nounwind readnone
>> +
>> +define double @align7(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
>> +entry:
>> +  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
>> +  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
>> +  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 16) ; <<1 x i64>> [#uses=1]
>> +  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
>> +  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
>> +  ret double %retval12
>> +}
>> +
>> +define double @align6(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
>> +entry:
>> +  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
>> +  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
>> +  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 9) ; <<1 x i64>> [#uses=1]
>> +  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
>> +  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
>> +  ret double %retval12
>> +}
>> +
>> +define double @align5(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
>> +entry:
>> +  %0 = bitcast <2 x i32> %b to <1 x i64>          ; <<1 x i64>> [#uses=1]
>> +  %1 = bitcast <2 x i32> %a to <1 x i64>          ; <<1 x i64>> [#uses=1]
>> +  %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 8) ; <<1 x i64>> [#uses=1]
>> +  %3 = extractelement <1 x i64> %2, i32 0         ; <i64> [#uses=1]
>> +  %retval12 = bitcast i64 %3 to double            ; <double> [#uses=1]
>> +  ret double %retval12
>> +}
>> +
>> +define <4 x i32> @align4(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
>> +entry:
>> +  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
>> +  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
>> +  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) ; <<2 x i64>> [#uses=1]
>> +  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
>> +  ret <4 x i32> %3
>> +}
>> +
>> +declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
>> +
>> +define <4 x i32> @align3(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
>> +entry:
>> +  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
>> +  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
>> +  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 17) ; <<2 x i64>> [#uses=1]
>> +  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
>> +  ret <4 x i32> %3
>> +}
>> +
>> +define <4 x i32> @align2(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
>> +entry:
>> +  %0 = bitcast <4 x i32> %b to <2 x i64>          ; <<2 x i64>> [#uses=1]
>> +  %1 = bitcast <4 x i32> %a to <2 x i64>          ; <<2 x i64>> [#uses=1]
>> +  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 16) ; <<2 x i64>> [#uses=1]
>> +  %3 = bitcast <2 x i64> %2 to <4 x i32>          ; <<4 x i32>> [#uses=1]
>> +  ret <4 x i32> %3
>> +}
>> 
>> Removed: llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/ssse3_palignr.ll.bc?rev=142895&view=auto
>> ==============================================================================
>> Binary file - no diff available.
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 


From bigcheesegs at gmail.com  Tue Oct 25 12:35:27 2011
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Tue, 25 Oct 2011 10:35:27 -0700
Subject: [llvm-commits] [llvm] r140627 - in /llvm/trunk:
 test/Object/TestObjectFiles/archive-test.a-bitcode
 test/Object/TestObjectFiles/archive-test.a-coff-i386
 test/Object/nm-archive.test tools/llvm-nm/llvm-nm.cpp
In-Reply-To: <77A37FBC-A751-4FB7-B5E6-1EFE405C266E@apple.com>
References: <20110927193718.333882A6C12C@llvm.org>
	<77A37FBC-A751-4FB7-B5E6-1EFE405C266E@apple.com>
Message-ID: <CACXTSimHniTmZ=-DD=GtFvqys1iatcCCfDMSEyZbr=ROtWGr5w@mail.gmail.com>

On Mon, Oct 24, 2011 at 6:41 PM, Chad Rosier <mcrosier at apple.com> wrote:
> Hi Michael,
> Would it be possible for you to rework this test case so that it can generate the archive on the fly, rather than reading in the archive-test.a-* files? ?I'm going to begin work on the bitcode reader/writer very soon that will break backward compatibility and in turn break this test case. ?See r142896 for examples of what was necessary for a few other test cases.
>
> ?Regards,
> ?Chad

In attempting to do this I ran into a bug with either llvm-ar or
llvm-nm in dealing with directory paths in archives. Once that is
fixed I will be able to fix the test case.

- Michael Spencer

> On Sep 27, 2011, at 12:37 PM, Michael J. Spencer wrote:
>
>> Author: mspencer
>> Date: Tue Sep 27 14:37:18 2011
>> New Revision: 140627
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=140627&view=rev
>> Log:
>> Add binary archive support to llvm-nm.
>>
>> Added:
>> ? ?llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode
>> ? ?llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386
>> ? ?llvm/trunk/test/Object/nm-archive.test
>> Modified:
>> ? ?llvm/trunk/tools/llvm-nm/llvm-nm.cpp
>>
>> Added: llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode?rev=140627&view=auto
>> ==============================================================================
>> Binary files llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode (added) and llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode Tue Sep 27 14:37:18 2011 differ
>>
>> Added: llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386?rev=140627&view=auto
>> ==============================================================================
>> Binary files llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386 (added) and llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386 Tue Sep 27 14:37:18 2011 differ
>>
>> Added: llvm/trunk/test/Object/nm-archive.test
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/nm-archive.test?rev=140627&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/Object/nm-archive.test (added)
>> +++ llvm/trunk/test/Object/nm-archive.test Tue Sep 27 14:37:18 2011
>> @@ -0,0 +1,17 @@
>> +RUN: llvm-nm %p/TestObjectFiles/archive-test.a-coff-i386 \
>> +RUN: ? ? ? ? | FileCheck %s -check-prefix COFF
>> +RUN: llvm-nm %p/TestObjectFiles/archive-test.a-bitcode \
>> +RUN: ? ? ? ? | FileCheck %s -check-prefix BITCODE
>> +
>> +
>> +COFF: trivial-object-test.coff-i386:
>> +COFF-NEXT: 00000000 d .data
>> +COFF-NEXT: 00000000 t .text
>> +COFF-NEXT: 00000000 d L_.str
>> +COFF-NEXT: ? ? ? ? ?U _SomeOtherFunction
>> +COFF-NEXT: 00000000 T _main
>> +COFF-NEXT: ? ? ? ? ?U _puts
>> +
>> +BITCODE: ? ? ? ? ?U SomeOtherFunction
>> +BITCODE-NEXT: ? ? ? ? ?T main
>> +BITCODE-NEXT: ? ? ? ? ?U puts
>>
>> Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=140627&r1=140626&r2=140627&view=diff
>> ==============================================================================
>> --- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
>> +++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Tue Sep 27 14:37:18 2011
>> @@ -20,6 +20,7 @@
>> #include "llvm/Module.h"
>> #include "llvm/Bitcode/ReaderWriter.h"
>> #include "llvm/Bitcode/Archive.h"
>> +#include "llvm/Object/Archive.h"
>> #include "llvm/Object/ObjectFile.h"
>> #include "llvm/Support/CommandLine.h"
>> #include "llvm/Support/FileSystem.h"
>> @@ -318,18 +319,34 @@
>> ? ? ? errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n";
>>
>> ? } else if (aPath.isArchive()) {
>> - ? ?std::string ErrMsg;
>> - ? ?Archive* archive = Archive::OpenAndLoad(sys::Path(Filename), Context,
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?&ErrorMessage);
>> - ? ?if (!archive)
>> - ? ? ?errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n";
>> - ? ?std::vector<Module *> Modules;
>> - ? ?if (archive->getAllModules(Modules, &ErrorMessage)) {
>> - ? ? ?errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n";
>> + ? ?OwningPtr<Binary> arch;
>> + ? ?if (error_code ec = object::createBinary(aPath.str(), arch)) {
>> + ? ? ?errs() << ToolName << ": " << Filename << ": " << ec.message() << ".\n";
>> ? ? ? return;
>> ? ? }
>> - ? ?MultipleFiles = true;
>> - ? ?std::for_each (Modules.begin(), Modules.end(), DumpSymbolNamesFromModule);
>> + ? ?if (object::Archive *a = dyn_cast<object::Archive>(arch.get())) {
>> + ? ? ?for (object::Archive::child_iterator i = a->begin_children(),
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? e = a->end_children(); i != e; ++i) {
>> + ? ? ? ?OwningPtr<Binary> child;
>> + ? ? ? ?if (error_code ec = i->getAsBinary(child)) {
>> + ? ? ? ? ?// Try opening it as a bitcode file.
>> + ? ? ? ? ?MemoryBuffer *buff = i->getBuffer();
>> + ? ? ? ? ?Module *Result = 0;
>> + ? ? ? ? ?if (buff)
>> + ? ? ? ? ? ?Result = ParseBitcodeFile(buff, Context, &ErrorMessage);
>> +
>> + ? ? ? ? ?if (Result) {
>> + ? ? ? ? ? ?DumpSymbolNamesFromModule(Result);
>> + ? ? ? ? ? ?delete Result;
>> + ? ? ? ? ?}
>> + ? ? ? ? ?continue;
>> + ? ? ? ?}
>> + ? ? ? ?if (object::ObjectFile *o = dyn_cast<ObjectFile>(child.get())) {
>> + ? ? ? ? ?outs() << o->getFileName() << ":\n";
>> + ? ? ? ? ?DumpSymbolNamesFromObject(o);
>> + ? ? ? ?}
>> + ? ? ?}
>> + ? ?}
>> ? } else if (aPath.isObjectFile()) {
>> ? ? OwningPtr<Binary> obj;
>> ? ? if (error_code ec = object::createBinary(aPath.str(), obj)) {
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>


From mcrosier at apple.com  Tue Oct 25 13:06:24 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Tue, 25 Oct 2011 11:06:24 -0700
Subject: [llvm-commits] [llvm] r140627 - in /llvm/trunk:
 test/Object/TestObjectFiles/archive-test.a-bitcode
 test/Object/TestObjectFiles/archive-test.a-coff-i386
 test/Object/nm-archive.test tools/llvm-nm/llvm-nm.cpp
In-Reply-To: <CACXTSimHniTmZ=-DD=GtFvqys1iatcCCfDMSEyZbr=ROtWGr5w@mail.gmail.com>
References: <20110927193718.333882A6C12C@llvm.org>
	<77A37FBC-A751-4FB7-B5E6-1EFE405C266E@apple.com>
	<CACXTSimHniTmZ=-DD=GtFvqys1iatcCCfDMSEyZbr=ROtWGr5w@mail.gmail.com>
Message-ID: <BE3D05D8-62FC-474A-A343-2A640C3490F2@apple.com>

Hi Michael,
Please disregard my request.  After some discussion with Bob (Wilson) we decided this isn't necessary and I don't foresee changing bitcode compatibility.

 Chad

On Oct 25, 2011, at 10:35 AM, Michael Spencer wrote:

> On Mon, Oct 24, 2011 at 6:41 PM, Chad Rosier <mcrosier at apple.com> wrote:
>> Hi Michael,
>> Would it be possible for you to rework this test case so that it can generate the archive on the fly, rather than reading in the archive-test.a-* files?  I'm going to begin work on the bitcode reader/writer very soon that will break backward compatibility and in turn break this test case.  See r142896 for examples of what was necessary for a few other test cases.
>> 
>>  Regards,
>>  Chad
> 
> In attempting to do this I ran into a bug with either llvm-ar or
> llvm-nm in dealing with directory paths in archives. Once that is
> fixed I will be able to fix the test case.
> 
> - Michael Spencer
> 
>> On Sep 27, 2011, at 12:37 PM, Michael J. Spencer wrote:
>> 
>>> Author: mspencer
>>> Date: Tue Sep 27 14:37:18 2011
>>> New Revision: 140627
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=140627&view=rev
>>> Log:
>>> Add binary archive support to llvm-nm.
>>> 
>>> Added:
>>>    llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode
>>>    llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386
>>>    llvm/trunk/test/Object/nm-archive.test
>>> Modified:
>>>    llvm/trunk/tools/llvm-nm/llvm-nm.cpp
>>> 
>>> Added: llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode?rev=140627&view=auto
>>> ==============================================================================
>>> Binary files llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode (added) and llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode Tue Sep 27 14:37:18 2011 differ
>>> 
>>> Added: llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386?rev=140627&view=auto
>>> ==============================================================================
>>> Binary files llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386 (added) and llvm/trunk/test/Object/TestObjectFiles/archive-test.a-coff-i386 Tue Sep 27 14:37:18 2011 differ
>>> 
>>> Added: llvm/trunk/test/Object/nm-archive.test
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/nm-archive.test?rev=140627&view=auto
>>> ==============================================================================
>>> --- llvm/trunk/test/Object/nm-archive.test (added)
>>> +++ llvm/trunk/test/Object/nm-archive.test Tue Sep 27 14:37:18 2011
>>> @@ -0,0 +1,17 @@
>>> +RUN: llvm-nm %p/TestObjectFiles/archive-test.a-coff-i386 \
>>> +RUN:         | FileCheck %s -check-prefix COFF
>>> +RUN: llvm-nm %p/TestObjectFiles/archive-test.a-bitcode \
>>> +RUN:         | FileCheck %s -check-prefix BITCODE
>>> +
>>> +
>>> +COFF: trivial-object-test.coff-i386:
>>> +COFF-NEXT: 00000000 d .data
>>> +COFF-NEXT: 00000000 t .text
>>> +COFF-NEXT: 00000000 d L_.str
>>> +COFF-NEXT:          U _SomeOtherFunction
>>> +COFF-NEXT: 00000000 T _main
>>> +COFF-NEXT:          U _puts
>>> +
>>> +BITCODE:          U SomeOtherFunction
>>> +BITCODE-NEXT:          T main
>>> +BITCODE-NEXT:          U puts
>>> 
>>> Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=140627&r1=140626&r2=140627&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
>>> +++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Tue Sep 27 14:37:18 2011
>>> @@ -20,6 +20,7 @@
>>> #include "llvm/Module.h"
>>> #include "llvm/Bitcode/ReaderWriter.h"
>>> #include "llvm/Bitcode/Archive.h"
>>> +#include "llvm/Object/Archive.h"
>>> #include "llvm/Object/ObjectFile.h"
>>> #include "llvm/Support/CommandLine.h"
>>> #include "llvm/Support/FileSystem.h"
>>> @@ -318,18 +319,34 @@
>>>       errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n";
>>> 
>>>   } else if (aPath.isArchive()) {
>>> -    std::string ErrMsg;
>>> -    Archive* archive = Archive::OpenAndLoad(sys::Path(Filename), Context,
>>> -                                            &ErrorMessage);
>>> -    if (!archive)
>>> -      errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n";
>>> -    std::vector<Module *> Modules;
>>> -    if (archive->getAllModules(Modules, &ErrorMessage)) {
>>> -      errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n";
>>> +    OwningPtr<Binary> arch;
>>> +    if (error_code ec = object::createBinary(aPath.str(), arch)) {
>>> +      errs() << ToolName << ": " << Filename << ": " << ec.message() << ".\n";
>>>       return;
>>>     }
>>> -    MultipleFiles = true;
>>> -    std::for_each (Modules.begin(), Modules.end(), DumpSymbolNamesFromModule);
>>> +    if (object::Archive *a = dyn_cast<object::Archive>(arch.get())) {
>>> +      for (object::Archive::child_iterator i = a->begin_children(),
>>> +                                           e = a->end_children(); i != e; ++i) {
>>> +        OwningPtr<Binary> child;
>>> +        if (error_code ec = i->getAsBinary(child)) {
>>> +          // Try opening it as a bitcode file.
>>> +          MemoryBuffer *buff = i->getBuffer();
>>> +          Module *Result = 0;
>>> +          if (buff)
>>> +            Result = ParseBitcodeFile(buff, Context, &ErrorMessage);
>>> +
>>> +          if (Result) {
>>> +            DumpSymbolNamesFromModule(Result);
>>> +            delete Result;
>>> +          }
>>> +          continue;
>>> +        }
>>> +        if (object::ObjectFile *o = dyn_cast<ObjectFile>(child.get())) {
>>> +          outs() << o->getFileName() << ":\n";
>>> +          DumpSymbolNamesFromObject(o);
>>> +        }
>>> +      }
>>> +    }
>>>   } else if (aPath.isObjectFile()) {
>>>     OwningPtr<Binary> obj;
>>>     if (error_code ec = object::createBinary(aPath.str(), obj)) {
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
>> 


From ahatanak at gmail.com  Tue Oct 25 13:11:37 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Tue, 25 Oct 2011 11:11:37 -0700
Subject: [llvm-commits] [PATCH][Review request] Change handling of byval
	arguments passed in registers.
Message-ID: <CAB297QxWzSeCdO0NCpysTABP6vNK0ic97eH6BK-hDrQneMwJrA@mail.gmail.com>

This patch enables handling of functions with multiple byval arguments.
foo(struct S1 a0, struct S1 a1);
This feature hasn't been necessary since it seems that ARM, which was
the only user of FirstByValReg, allows just one byval argument being
passed.

All registers used to pass or receive byval arguments are stored in a
map, which obviates the need to rediscover them later.

Also, I think the following functions can be simplified if variable
FirstByValRegValid is removed. You can tell whether FirstByValReg is
valid or not by checking whether it is 0 since enums for registers are
non-zero (NoRegister is 0).

unsigned getFirstByValReg() { return FirstByValRegValid ? FirstByValReg : 0; }
void setFirstByValReg(unsigned r) { FirstByValReg = r;
FirstByValRegValid = true; }
void clearFirstByValReg() { FirstByValReg = 0; FirstByValRegValid = false; }
bool isFirstByValRegValid() { return FirstByValRegValid; }
-------------- next part --------------
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From bruno.cardoso at gmail.com  Tue Oct 25 13:13:21 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 25 Oct 2011 18:13:21 -0000
Subject: [llvm-commits] [llvm] r142934 - in /llvm/trunk:
 include/llvm/MC/MCExpr.h lib/MC/MCELFStreamer.cpp lib/MC/MCExpr.cpp
Message-ID: <20111025181321.1FB19312800A@llvm.org>

Author: bruno
Date: Tue Oct 25 13:13:20 2011
New Revision: 142934

URL: http://llvm.org/viewvc/llvm-project?rev=142934&view=rev
Log:
This is the first of several patches for Mips direct object generation.
This first patch is for expression variable kinds.

Patch by Jack Carter!

Modified:
    llvm/trunk/include/llvm/MC/MCExpr.h
    llvm/trunk/lib/MC/MCELFStreamer.cpp
    llvm/trunk/lib/MC/MCExpr.cpp

Modified: llvm/trunk/include/llvm/MC/MCExpr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=142934&r1=142933&r2=142934&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCExpr.h (original)
+++ llvm/trunk/include/llvm/MC/MCExpr.h Tue Oct 25 13:13:20 2011
@@ -174,7 +174,23 @@
     VK_PPC_DARWIN_HA16,  // ha16(symbol)
     VK_PPC_DARWIN_LO16,  // lo16(symbol)
     VK_PPC_GAS_HA16,     // symbol at ha
-    VK_PPC_GAS_LO16      // symbol at l
+    VK_PPC_GAS_LO16,      // symbol at l
+
+    VK_Mips_None,
+    VK_Mips_GPREL,
+    VK_Mips_GOT_CALL,
+    VK_Mips_GOT,
+    VK_Mips_ABS_HI,
+    VK_Mips_ABS_LO,
+    VK_Mips_TLSGD,
+    VK_Mips_GOTTPREL,
+    VK_Mips_TPREL_HI,
+    VK_Mips_TPREL_LO,
+    VK_Mips_GPOFF_HI,
+    VK_Mips_GPOFF_LO,
+    VK_Mips_GOT_DISP,
+    VK_Mips_GOT_PAGE,
+    VK_Mips_GOT_OFST 
   };
 
 private:

Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=142934&r1=142933&r2=142934&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCELFStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCELFStreamer.cpp Tue Oct 25 13:13:20 2011
@@ -308,6 +308,10 @@
     case MCSymbolRefExpr::VK_ARM_TLSGD:
     case MCSymbolRefExpr::VK_ARM_TPOFF:
     case MCSymbolRefExpr::VK_ARM_GOTTPOFF:
+    case MCSymbolRefExpr::VK_Mips_TLSGD:
+    case MCSymbolRefExpr::VK_Mips_GOTTPREL:
+    case MCSymbolRefExpr::VK_Mips_TPREL_HI:
+    case MCSymbolRefExpr::VK_Mips_TPREL_LO:
       break;
     }
     MCSymbolData &SD = getAssembler().getOrCreateSymbolData(symRef.getSymbol());

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=142934&r1=142933&r2=142934&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Tue Oct 25 13:13:20 2011
@@ -26,6 +26,38 @@
 }
 }
 
+static bool printMipsSymbolRef(const MCSymbolRefExpr &SRE,
+                               const MCSymbol &Sym, raw_ostream &OS) {
+  MCSymbolRefExpr::VariantKind Kind= SRE.getKind();
+
+  switch (Kind) {
+  default:
+    return false;
+  case MCSymbolRefExpr::VK_Mips_None:     break;
+  case MCSymbolRefExpr::VK_Mips_GPREL:    OS << "%gp_rel("; break;
+  case MCSymbolRefExpr::VK_Mips_GOT_CALL: OS << "%call16("; break;
+  case MCSymbolRefExpr::VK_Mips_GOT:      OS << "%got(";    break;
+  case MCSymbolRefExpr::VK_Mips_ABS_HI:   OS << "%hi(";     break;
+  case MCSymbolRefExpr::VK_Mips_ABS_LO:   OS << "%lo(";     break;
+  case MCSymbolRefExpr::VK_Mips_TLSGD:    OS << "%tlsgd(";  break;
+  case MCSymbolRefExpr::VK_Mips_GOTTPREL: OS << "%gottprel("; break;
+  case MCSymbolRefExpr::VK_Mips_TPREL_HI: OS << "%tprel_hi("; break;
+  case MCSymbolRefExpr::VK_Mips_TPREL_LO: OS << "%tprel_lo("; break;
+  case MCSymbolRefExpr::VK_Mips_GPOFF_HI: OS << "%hi(%neg(%gp_rel("; break;
+  case MCSymbolRefExpr::VK_Mips_GPOFF_LO: OS << "%lo(%neg(%gp_rel("; break;
+  case MCSymbolRefExpr::VK_Mips_GOT_DISP: OS << "%got_disp("; break;
+  case MCSymbolRefExpr::VK_Mips_GOT_PAGE: OS << "%got_page("; break;
+  case MCSymbolRefExpr::VK_Mips_GOT_OFST: OS << "%got_ofst("; break;
+  }
+
+  OS << Sym;
+
+  if (Kind != MCSymbolRefExpr::VK_Mips_None)
+    OS << ')';
+
+  return true;
+}
+
 void MCExpr::print(raw_ostream &OS) const {
   switch (getKind()) {
   case MCExpr::Target:
@@ -41,6 +73,9 @@
     // absolute names.
     bool UseParens = Sym.getName()[0] == '$';
 
+    if (printMipsSymbolRef(SRE, Sym, OS))
+      return;
+
     if (SRE.getKind() == MCSymbolRefExpr::VK_PPC_DARWIN_HA16 ||
         SRE.getKind() == MCSymbolRefExpr::VK_PPC_DARWIN_LO16) {
       OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind());



From bruno.cardoso at gmail.com  Tue Oct 25 13:16:58 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 25 Oct 2011 16:16:58 -0200
Subject: [llvm-commits] [PATCH][Review request] Mips direct object
	generation patch #1
In-Reply-To: <86AC779C188FE74F88F6494478B46332E8259C@exchdb03.mips.com>
References: <86AC779C188FE74F88F6494478B46332E8259C@exchdb03.mips.com>
Message-ID: <CACk9FxZip2S7NjhmAprXojUD_eCFjoL0ScfNd-ubpsuXnyCHCg@mail.gmail.com>

Hi Jack,

On Fri, Oct 21, 2011 at 10:28 PM, Carter, Jack <jcarter at mips.com> wrote:
> This is the first of several patches for Mips direct object generation. This
> first patch is for expression variable kinds.

Sorry for the delay, I've missed your patch!

LGTM
Committed r142934
Next time, please send a ".patch" file!

Thanks

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc

From resistor at mac.com  Tue Oct 25 13:48:41 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 25 Oct 2011 18:48:41 -0000
Subject: [llvm-commits] [llvm] r142938 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20111025184841.D18D8312800A@llvm.org>

Author: resistor
Date: Tue Oct 25 13:48:41 2011
New Revision: 142938

URL: http://llvm.org/viewvc/llvm-project?rev=142938&view=rev
Log:
Teach the MachO relocation pretty-printer to interpret ARM half-relocations.

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=142938&r1=142937&r2=142938&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Tue Oct 25 13:48:41 2011
@@ -793,98 +793,160 @@
   InMemoryStruct<macho::RelocationEntry> RE;
   getRelocation(Rel, RE);
 
-  std::string addend;
-  raw_string_ostream addend_fmt(addend);
-
   bool isPCRel = (RE->Word1 >> 25) & 1;
   unsigned Type = (RE->Word1 >> 28) & 0xF;
 
+  std::string fmtbuf;
+  raw_string_ostream fmt(fmtbuf);
+
   // Determine any addends that should be displayed with the relocation.
   // These require decoding the relocation type, which is triple-specific.
   unsigned Arch = getArch();
 
   // X86_64 has entirely custom relocation types.
   if (Arch == Triple::x86_64) {
+    StringRef Name;
+    if (error_code ec = getRelocationTargetName(RE->Word1, Name))
+      report_fatal_error(ec.message());
+
     switch (Type) {
       case 5: { // X86_64_RELOC_SUBTRACTOR
-        RelocationRef NextReloc;
-        if (error_code ec = getRelocationNext(Rel, NextReloc))
-          report_fatal_error(ec.message());
-
-        uint32_t SucessorType;
-        if (error_code ec = NextReloc.getType(SucessorType))
-          report_fatal_error(ec.message());
+        InMemoryStruct<macho::RelocationEntry> RENext;
+        DataRefImpl RelNext = Rel;
+        RelNext.d.a++;
+        getRelocation(RelNext, RENext);
 
         // X86_64_SUBTRACTOR must be followed by a relocation of type
         // X86_64_RELOC_UNSIGNED.
-        unsigned RType = (SucessorType >> 28) & 0xF;
+        unsigned RType = (RENext->Word1 >> 28) & 0xF;
         if (RType != 0)
           report_fatal_error("Expected X86_64_RELOC_UNSIGNED after "
                              "X86_64_RELOC_SUBTRACTOR.");
 
-        StringRef Name;
-        if (error_code ec = getRelocationTargetName(SucessorType, Name))
+        StringRef SucName;
+        if (error_code ec = getRelocationTargetName(RENext->Word1, SucName))
           report_fatal_error(ec.message());
 
-        addend_fmt << "-" << Name;
+        fmt << Name << "-" << SucName;
+        if (isPCRel) fmt << "-PC";
       }
       case 6: // X86_64_RELOC_SIGNED1
-        addend_fmt << "-1";
+        fmt << Name << "-1";
         break;
       case 7: // X86_64_RELOC_SIGNED2
-        addend_fmt << "-2";
+        fmt << Name << "-2";
         break;
       case 8: // X86_64_RELOC_SIGNED4
-        addend_fmt << "-4";
+        fmt << Name << "-4";
+        break;
+      default:
+        fmt << Name;
         break;
     }
-  }
-
   // X86 and ARM share some relocation types in common.
-  if (Arch == Triple::x86 || Arch == Triple::arm) {
+  } else if (Arch == Triple::x86 || Arch == Triple::arm) {
+    // Generic relocation types...
     switch (Type) {
       case 1: // GENERIC_RELOC_PAIR - prints no info
         return object_error::success;
       case 2:   // GENERIC_RELOC_SECTDIFF
       case 4: { // GENERIC_RELOC_LOCAL_SECTDIFF
-        RelocationRef NextReloc;
-        if (error_code ec = getRelocationNext(Rel, NextReloc))
-          report_fatal_error(ec.message());
-
-        uint32_t SucessorType;
-        if (error_code ec = NextReloc.getType(SucessorType))
-          report_fatal_error(ec.message());
+        InMemoryStruct<macho::RelocationEntry> RENext;
+        DataRefImpl RelNext = Rel;
+        RelNext.d.a++;
+        getRelocation(RelNext, RENext);
 
         // X86 sect diff's must be followed by a relocation of type
         // GENERIC_RELOC_PAIR.
-        unsigned RType = (SucessorType >> 28) & 0xF;
+        unsigned RType = (RENext->Word1 >> 28) & 0xF;
         if (RType != 1)
           report_fatal_error("Expected GENERIC_RELOC_PAIR after "
                              "GENERIC_RELOC_SECTDIFF or "
                              "GENERIC_RELOC_LOCAL_SECTDIFF.");
 
+        StringRef SucName;
+        if (error_code ec = getRelocationTargetName(RENext->Word1, SucName))
+          report_fatal_error(ec.message());
+
         StringRef Name;
-        if (error_code ec = getRelocationTargetName(SucessorType, Name))
+        if (error_code ec = getRelocationTargetName(RE->Word1, Name))
           report_fatal_error(ec.message());
 
-        addend_fmt << "-" << Name;
+        fmt << Name << "-" << SucName;
+        break;
+      }
+    }
 
+    if (Arch == Triple::x86 && Type != 1) {
+      // All X86 relocations that need special printing were already
+      // handled in the generic code.
+      StringRef Name;
+      if (error_code ec = getRelocationTargetName(RE->Word1, Name))
+        report_fatal_error(ec.message());
+      fmt << Name;
+    } else { // ARM-specific relocations
+      switch (Type) {
+        case 8:   // ARM_RELOC_HALF
+        case 9: { // ARM_RELOC_HALF_SECTDIFF
+          StringRef Name;
+          if (error_code ec = getRelocationTargetName(RE->Word1, Name))
+            report_fatal_error(ec.message());
+
+          // Half relocations steal a bit from the length field to encode
+          // whether this is an upper16 or a lower16 relocation.
+          bool isUpper = (RE->Word1 >> 25) & 1;
+          if (isUpper)
+            fmt << ":upper16:(" << Name;
+          else
+            fmt << ":lower16:(" << Name;
+
+          InMemoryStruct<macho::RelocationEntry> RENext;
+          DataRefImpl RelNext = Rel;
+          RelNext.d.a++;
+          getRelocation(RelNext, RENext);
+
+          // ARM half relocs must be followed by a relocation of type
+          // ARM_RELOC_PAIR.
+          unsigned RType = (RENext->Word1 >> 28) & 0xF;
+          if (RType != 1)
+            report_fatal_error("Expected ARM_RELOC_PAIR after "
+                               "GENERIC_RELOC_HALF");
+
+          // A constant addend for the relocation is stored in the address
+          // field of the follow-on relocation.  If this is a lower16 relocation
+          // we need to shift it left by 16 before using it.
+          int32_t Addend = RENext->Word0;
+          if (!isUpper) Addend <<= 16;
+
+          // ARM_RELOC_HALF_SECTDIFF encodes the second section in the
+          // symbol/section pointer of the follow-on relocation.
+          StringRef SucName;
+          if (Type == 9) { // ARM_RELOC_HALF_SECTDIFF
+            if (error_code ec = getRelocationTargetName(RENext->Word1, SucName))
+              report_fatal_error(ec.message());
+          }
+
+          if (SucName.size()) fmt << "-" << SucName;
+          if (Addend > 0) fmt << "+" << Addend;
+          else if (Addend < 0) fmt << Addend;
+          fmt << ")";
+          break;
+        }
+        default: {
+          StringRef Name;
+          if (error_code ec = getRelocationTargetName(RE->Word1, Name))
+            report_fatal_error(ec.message());
+          fmt << Name;
+        }
       }
     }
+  } else {
+    StringRef Name;
+    if (error_code ec = getRelocationTargetName(RE->Word1, Name))
+      report_fatal_error(ec.message());
+    fmt << Name;
   }
 
-  addend_fmt.flush();
-
-  std::string fmtbuf;
-  raw_string_ostream fmt(fmtbuf);
-
-  StringRef Name;
-  if (error_code ec = getRelocationTargetName(RE->Word1, Name))
-    report_fatal_error(ec.message());
-
-  fmt << Name << addend;
-  if (isPCRel) fmt << "-P";
-
   fmt.flush();
   Result.append(fmtbuf.begin(), fmtbuf.end());
   return object_error::success;



From bruno.cardoso at gmail.com  Tue Oct 25 13:50:37 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 25 Oct 2011 16:50:37 -0200
Subject: [llvm-commits] [PATCH][Review request] Change handling of byval
 arguments passed in registers.
In-Reply-To: <CAB297QxWzSeCdO0NCpysTABP6vNK0ic97eH6BK-hDrQneMwJrA@mail.gmail.com>
References: <CAB297QxWzSeCdO0NCpysTABP6vNK0ic97eH6BK-hDrQneMwJrA@mail.gmail.com>
Message-ID: <CACk9Fxab4Jpv8Q0p-asNxLu6S0EbogCQDC-hgQbbD8T=9rOv9g@mail.gmail.com>

Hi Akira,

On Tue, Oct 25, 2011 at 4:11 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> This patch enables handling of functions with multiple byval arguments.
> foo(struct S1 a0, struct S1 a1);
> This feature hasn't been necessary since it seems that ARM, which was
> the only user of FirstByValReg, allows just one byval argument being
> passed.
>
> All registers used to pass or receive byval arguments are stored in a
> map, which obviates the need to rediscover them later.
>
> Also, I think the following functions can be simplified if variable
> FirstByValRegValid is removed. You can tell whether FirstByValReg is
> valid or not by checking whether it is 0 since enums for registers are
> non-zero (NoRegister is 0).
>
> unsigned getFirstByValReg() { return FirstByValRegValid ? FirstByValReg : 0; }
> void setFirstByValReg(unsigned r) { FirstByValReg = r;
> FirstByValRegValid = true; }
> void clearFirstByValReg() { FirstByValReg = 0; FirstByValRegValid = false; }
> bool isFirstByValRegValid() { return FirstByValRegValid; }

I may be missing something, but why don't handle this sort of Mips
requirement in the front-end (clang)?


-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc

From mcrosier at apple.com  Tue Oct 25 14:59:50 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Tue, 25 Oct 2011 19:59:50 -0000
Subject: [llvm-commits] [llvm] r142948 - in /llvm/trunk/test/Bitcode:
	sse42_crc32.ll ssse3_palignr.ll
Message-ID: <20111025195950.414CB312800A@llvm.org>

Author: mcrosier
Date: Tue Oct 25 14:59:50 2011
New Revision: 142948

URL: http://llvm.org/viewvc/llvm-project?rev=142948&view=rev
Log:
Simplify tests by not piping them through llvm-dis.

Modified:
    llvm/trunk/test/Bitcode/sse42_crc32.ll
    llvm/trunk/test/Bitcode/ssse3_palignr.ll

Modified: llvm/trunk/test/Bitcode/sse42_crc32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/sse42_crc32.ll?rev=142948&r1=142947&r2=142948&view=diff
==============================================================================
--- llvm/trunk/test/Bitcode/sse42_crc32.ll (original)
+++ llvm/trunk/test/Bitcode/sse42_crc32.ll Tue Oct 25 14:59:50 2011
@@ -1,9 +1,10 @@
-; Check to make sure old CRC32 intrinsics are auto-upgraded
-; correctly.
+; Check to make sure old CRC32 intrinsics are auto-upgraded correctly.  
+; Auto-upgrade happens when parsing a .bc or a .ll file.  Thus, leave the test
+; case as a .ll file so we can see what's going on.
 ;
 ; Rdar: 9472944
 ;
-; RUN: opt < %s | llvm-dis | FileCheck %s
+; RUN: opt < %s -S | FileCheck %s
 
 ; crc32.8 should upgrade to crc32.32.8
 ; CHECK: i32 @llvm.x86.sse42.crc32.32.8(

Modified: llvm/trunk/test/Bitcode/ssse3_palignr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/ssse3_palignr.ll?rev=142948&r1=142947&r2=142948&view=diff
==============================================================================
--- llvm/trunk/test/Bitcode/ssse3_palignr.ll (original)
+++ llvm/trunk/test/Bitcode/ssse3_palignr.ll Tue Oct 25 14:59:50 2011
@@ -1,4 +1,4 @@
-; RUN: opt < %s | llvm-dis | FileCheck %s
+; RUN: opt < %s -S | FileCheck %s
 ; CHECK-NOT: {@llvm\\.palign}
 
 define <4 x i32> @align1(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {



From bruno.cardoso at gmail.com  Tue Oct 25 15:09:31 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 25 Oct 2011 20:09:31 -0000
Subject: [llvm-commits] [llvm] r142950 - /llvm/trunk/docs/CodeGenerator.html
Message-ID: <20111025200931.BD57B312800A@llvm.org>

Author: bruno
Date: Tue Oct 25 15:09:31 2011
New Revision: 142950

URL: http://llvm.org/viewvc/llvm-project?rev=142950&view=rev
Log:
According to Mips folks, the backend is now generally reliable (they can
compile and use a bunch of stuff using o32 abi). Also the rt-rk.com team
claims that the JIT support they contributed, is complete for the mips
"static" relocation model.

Modified:
    llvm/trunk/docs/CodeGenerator.html

Modified: llvm/trunk/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=142950&r1=142949&r2=142950&view=diff
==============================================================================
--- llvm/trunk/docs/CodeGenerator.html (original)
+++ llvm/trunk/docs/CodeGenerator.html Tue Oct 25 15:09:31 2011
@@ -2227,7 +2227,7 @@
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
-  <td class="no"></td> <!-- Mips -->
+  <td class="yes"></td> <!-- Mips -->
   <td class="no"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="yes"></td> <!-- Sparc -->
@@ -2287,7 +2287,7 @@
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
-  <td class="no"></td> <!-- Mips -->
+  <td class="yes"></td> <!-- Mips -->
   <td class="unknown"></td> <!-- PTX -->
   <td class="yes"></td> <!-- PowerPC -->
   <td class="unknown"></td> <!-- Sparc -->



From resistor at mac.com  Tue Oct 25 15:15:39 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 25 Oct 2011 20:15:39 -0000
Subject: [llvm-commits] [llvm] r142952 -
	/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
Message-ID: <20111025201539.7A428312800A@llvm.org>

Author: resistor
Date: Tue Oct 25 15:15:39 2011
New Revision: 142952

URL: http://llvm.org/viewvc/llvm-project?rev=142952&view=rev
Log:
Fix off-by-one error when printing relocations inline with disassembly.

Modified:
    llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp

Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=142952&r1=142951&r2=142952&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Tue Oct 25 15:15:39 2011
@@ -306,7 +306,7 @@
           SmallString<32> val;
           if (error(rel_cur->getAddress(addr))) goto skip_print_rel;
           // Stop when rel_cur's address is past the current instruction.
-          if (addr > Index + Size) break;
+          if (addr >= Index + Size) break;
           if (error(rel_cur->getTypeName(name))) goto skip_print_rel;
           if (error(rel_cur->getValueString(val))) goto skip_print_rel;
 



From jcarter at mips.com  Tue Oct 25 15:19:59 2011
From: jcarter at mips.com (Carter, Jack)
Date: Tue, 25 Oct 2011 20:19:59 +0000
Subject: [llvm-commits] [PATCH][Review request] Mips direct object
	generation patch #2
Message-ID: <86AC779C188FE74F88F6494478B46332E82CEF@exchdb03.mips.com>

This is the first of several patches for Mips direct object generation. This first patch is for expression variable kinds.

In this patch we are following the current convention of putting target specific  ELF relocation handling in the base class due to unfortunate expression class mechanics.

Hopefully after our port settles down we can address this issue with the community and coordinate a structural change that pushes the target specific relocation and expression handling completely down to the Target level.

The patch is attached.

Jack
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From isanbard at gmail.com  Tue Oct 25 15:24:32 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 25 Oct 2011 20:24:32 -0000
Subject: [llvm-commits] [llvm] r142954 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111025202433.0BCEA312800A@llvm.org>

Author: void
Date: Tue Oct 25 15:24:32 2011
New Revision: 142954

URL: http://llvm.org/viewvc/llvm-project?rev=142954&view=rev
Log:
Add TTA-based Co-design Environment to external OS projects.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142954&r1=142953&r2=142954&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 15:24:32 2011
@@ -298,23 +298,22 @@
 -->  
   
 <!--=========================================================================-->
-<!--
-<h3>TTA-based Codesign Environment (TCE)</h3>
-  
+<h3>TTA-based Co-design Environment (TCE)</h3>
+
 <div>
+
 <p>TCE is a toolset for designing application-specific processors (ASP) based on
-the Transport triggered architecture (TTA). The toolset provides a complete
-co-design flow from C/C++ programs down to synthesizable VHDL and parallel
-program binaries. Processor customization points include the register files,
-function units, supported operations, and the interconnection network.</p>
-  
+   the Transport triggered architecture (TTA). The toolset provides a complete
+   co-design flow from C/C++ programs down to synthesizable VHDL and parallel
+   program binaries. Processor customization points include the register files,
+   function units, supported operations, and the interconnection network.</p>
+
 <p>TCE uses Clang and LLVM for C/C++ language support, target independent
-optimizations and also for parts of code generation. It generates new LLVM-based
-code generators "on the fly" for the designed TTA processors and loads them in
-to the compiler backend as runtime libraries to avoid per-target recompilation
-of larger parts of the compiler chain.</p>
+   optimizations and also for parts of code generation. It generates new
+   LLVM-based code generators <i>on the fly</i> for the designed TTA processors
+   and loads them in to the compiler backend as runtime libraries to avoid
+   per-target recompilation of larger parts of the compiler chain.</p>
 </div>
--->
 
   
 <!--=========================================================================-->



From isanbard at gmail.com  Tue Oct 25 15:27:37 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 25 Oct 2011 20:27:37 -0000
Subject: [llvm-commits] [llvm] r142955 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111025202737.942CF312800A@llvm.org>

Author: void
Date: Tue Oct 25 15:27:37 2011
New Revision: 142955

URL: http://llvm.org/viewvc/llvm-project?rev=142955&view=rev
Log:
Add mention of Tart to external OS projects.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142955&r1=142954&r2=142955&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 15:27:37 2011
@@ -317,6 +317,27 @@
 
   
 <!--=========================================================================-->
+<h3>Tart Programming Language</h3>
+
+<div>
+
+<p><a href="http://code.google.com/p/tart/">Tart</a> is a general-purpose,
+   strongly typed programming language designed for application
+   developers. Strongly inspired by Python and C#, Tart focuses on practical
+   solutions for the professional software developer, while avoiding the clutter
+   and boilerplate of legacy languages like Java and C++. Although Tart is still
+   in development, the current implementation supports many features expected of
+   a modern programming language, such as garbage collection, powerful
+   bidirectional type inference, a greatly simplified syntax for template
+   metaprogramming, closures and function literals, reflection, operator
+   overloading, explicit mutability and immutability, and much more. Tart is
+   flexible enough to accommodate a broad range of programming styles and
+   philosophies, while maintaining a strong commitment to simplicity, minimalism
+   and elegance in design.</p>
+
+</div>
+
+<!--=========================================================================-->
 <!--
 <h3>PinaVM</h3>
   



From grosbach at apple.com  Tue Oct 25 15:30:48 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 25 Oct 2011 20:30:48 -0000
Subject: [llvm-commits] [llvm] r142956 -
	/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
Message-ID: <20111025203048.A0560312800A@llvm.org>

Author: grosbach
Date: Tue Oct 25 15:30:48 2011
New Revision: 142956

URL: http://llvm.org/viewvc/llvm-project?rev=142956&view=rev
Log:
Make assert() message more informative.

PR11217.

Modified:
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=142956&r1=142955&r2=142956&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Tue Oct 25 15:30:48 2011
@@ -121,7 +121,8 @@
   // we'll crash later.
   // Provide the user with a useful error message about what's wrong.
   assert(AsmInfo && "MCAsmInfo not initialized."
-	 "Make sure you include the correct TargetSelect.h!");
+         "Make sure you include the correct TargetSelect.h"
+         "and that InitializeAllTargetMCs() is being invoked!");
 }
 
 bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,



From mcrosier at apple.com  Tue Oct 25 15:33:19 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Tue, 25 Oct 2011 20:33:19 -0000
Subject: [llvm-commits] [llvm] r142958 - in /llvm/trunk/test/Bitcode:
 fbench-llvm-2.9.ll fbench-llvm-2.9.ll.bc spirit-llvm-2.9.ll
 spirit-llvm-2.9.ll.bc
Message-ID: <20111025203319.403E1312800A@llvm.org>

Author: mcrosier
Date: Tue Oct 25 15:33:19 2011
New Revision: 142958

URL: http://llvm.org/viewvc/llvm-project?rev=142958&view=rev
Log:
Add a few test cases to ensure the bitcode reader is backward compatible with
LLVM 2.9.  My understanding is that we plan to maintain compatibility with 2.9
until the 3.1 release.  At that time we can generate new test cases using LLVM
3.0.

Added:
    llvm/trunk/test/Bitcode/fbench-llvm-2.9.ll
    llvm/trunk/test/Bitcode/fbench-llvm-2.9.ll.bc   (with props)
    llvm/trunk/test/Bitcode/spirit-llvm-2.9.ll
    llvm/trunk/test/Bitcode/spirit-llvm-2.9.ll.bc   (with props)

Added: llvm/trunk/test/Bitcode/fbench-llvm-2.9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/fbench-llvm-2.9.ll?rev=142958&view=auto
==============================================================================
--- llvm/trunk/test/Bitcode/fbench-llvm-2.9.ll (added)
+++ llvm/trunk/test/Bitcode/fbench-llvm-2.9.ll Tue Oct 25 15:33:19 2011
@@ -0,0 +1,5 @@
+; This isn't really an assembly file. It just runs the test on the bitcode to 
+; ensure bitcode file backward compatibility.  No need for FileCheck as the 
+; BitcodeReader will fail with an assert if broken. This test case was 
+; generated using a clang binary, based on LLVM 2.9, downloaded from llvm.org.
+; RUN: llvm-dis < %s.bc > /dev/null

Added: llvm/trunk/test/Bitcode/fbench-llvm-2.9.ll.bc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/fbench-llvm-2.9.ll.bc?rev=142958&view=auto
==============================================================================
Binary file - no diff available.

Propchange: llvm/trunk/test/Bitcode/fbench-llvm-2.9.ll.bc
------------------------------------------------------------------------------
    svn:mime-type = application/octet-stream

Added: llvm/trunk/test/Bitcode/spirit-llvm-2.9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/spirit-llvm-2.9.ll?rev=142958&view=auto
==============================================================================
--- llvm/trunk/test/Bitcode/spirit-llvm-2.9.ll (added)
+++ llvm/trunk/test/Bitcode/spirit-llvm-2.9.ll Tue Oct 25 15:33:19 2011
@@ -0,0 +1,5 @@
+; This isn't really an assembly file. It just runs the test on the bitcode to 
+; ensure bitcode file backward compatibility.  No need for FileCheck as the 
+; BitcodeReader will fail with an assert if broken. This test case was 
+; generated using a clang binary, based on LLVM 2.9, downloaded from llvm.org.
+; RUN: llvm-dis < %s.bc > /dev/null

Added: llvm/trunk/test/Bitcode/spirit-llvm-2.9.ll.bc
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/spirit-llvm-2.9.ll.bc?rev=142958&view=auto
==============================================================================
Binary file - no diff available.

Propchange: llvm/trunk/test/Bitcode/spirit-llvm-2.9.ll.bc
------------------------------------------------------------------------------
    svn:mime-type = application/octet-stream



From eli.friedman at gmail.com  Tue Oct 25 15:34:22 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 25 Oct 2011 20:34:22 -0000
Subject: [llvm-commits] [llvm] r142959 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <20111025203422.677C2312800A@llvm.org>

Author: efriedma
Date: Tue Oct 25 15:34:22 2011
New Revision: 142959

URL: http://llvm.org/viewvc/llvm-project?rev=142959&view=rev
Log:
Remove a couple redundant checks.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=142959&r1=142958&r2=142959&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Oct 25 15:34:22 2011
@@ -7528,8 +7528,6 @@
   // Check to see if we can perform the "gzip trick", transforming
   // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
   if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
-      N0.getValueType().isInteger() &&
-      N2.getValueType().isInteger() &&
       (N1C->isNullValue() ||                         // (a < 0) ? b : 0
        (N1C->getAPIntValue() == 1 && N0 == N2))) {   // (a < 1) ? a : 0
     EVT XType = N0.getValueType();



From isanbard at gmail.com  Tue Oct 25 15:35:31 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 25 Oct 2011 20:35:31 -0000
Subject: [llvm-commits] [llvm] r142960 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111025203531.86AFA312800A@llvm.org>

Author: void
Date: Tue Oct 25 15:35:31 2011
New Revision: 142960

URL: http://llvm.org/viewvc/llvm-project?rev=142960&view=rev
Log:
Add mention of gwScript to external OS projects.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142960&r1=142959&r2=142960&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 15:35:31 2011
@@ -298,6 +298,31 @@
 -->  
   
 <!--=========================================================================-->
+<h3>gwXscript</h3>
+
+<div>
+
+<p><a href="http://botwars.tk/gwscript/">gwXscript</a> is an object oriented,
+   aspect orientied programing language which can create both, executables (ELF,
+   EXE) and shared libraries (DLL, SO, DYNLIB). The compiler is implemented in
+   its own language and translates scripts into LLVM-IR which can be optimized
+   and translated into native code by the LLVM framework. Source code in
+   gwScript contains definitions that expand the namespaces. So you can build
+   your project and simply 'plug out' features by removing a file. The remaining
+   project does not leave scars since you directly separate concerns by the
+   'template' feature of gwX. It is also possible to add new features to a
+   project by just adding files and without editing the original project. This
+   language is used for example to create games or content management systems
+   that should be extendable.</p>
+
+<p>gwXscript is strongly typed and offers comfort with its native types string,
+   hash and array. You can easily write new libraries in gwXscript or native
+   code. gwXscript is type safe and users should not be able to crash your
+   program or execute malicious code except code that is eating CPU time.</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>TTA-based Co-design Environment (TCE)</h3>
 
 <div>



From resistor at mac.com  Tue Oct 25 15:35:53 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 25 Oct 2011 20:35:53 -0000
Subject: [llvm-commits] [llvm] r142961 - in /llvm/trunk:
 include/llvm/Object/MachO.h include/llvm/Object/ObjectFile.h
 lib/Object/MachOObjectFile.cpp tools/llvm-objdump/llvm-objdump.cpp
Message-ID: <20111025203554.0C9A4312800A@llvm.org>

Author: resistor
Date: Tue Oct 25 15:35:53 2011
New Revision: 142961

URL: http://llvm.org/viewvc/llvm-project?rev=142961&view=rev
Log:
Add support for the notion of "hidden" relocations.  On MachO, these are relocation entries that are used as additional information for other, real relocations, rather than being relocations themselves.
I'm not familiar enough with ELF or COFF to know if they should have any relocations marked hidden.

Modified:
    llvm/trunk/include/llvm/Object/MachO.h
    llvm/trunk/include/llvm/Object/ObjectFile.h
    llvm/trunk/lib/Object/MachOObjectFile.cpp
    llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp

Modified: llvm/trunk/include/llvm/Object/MachO.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachO.h?rev=142961&r1=142960&r2=142961&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/MachO.h (original)
+++ llvm/trunk/include/llvm/Object/MachO.h Tue Oct 25 15:35:53 2011
@@ -88,6 +88,7 @@
                                                  int64_t &Res) const;
   virtual error_code getRelocationValueString(DataRefImpl Rel,
                                            SmallVectorImpl<char> &Result) const;
+  virtual error_code getRelocationHidden(DataRefImpl Rel, bool &Result) const;
 
 private:
   MachOObject *MachOObj;

Modified: llvm/trunk/include/llvm/Object/ObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=142961&r1=142960&r2=142961&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/ObjectFile.h (original)
+++ llvm/trunk/include/llvm/Object/ObjectFile.h Tue Oct 25 15:35:53 2011
@@ -101,6 +101,11 @@
   error_code getSymbol(SymbolRef &Result) const;
   error_code getType(uint32_t &Result) const;
 
+  /// @brief Indicates whether this relocation should hidden when listing
+  /// relocations, usually because it is the trailing part of a multipart
+  /// relocation that will be printed as part of the leading relocation.
+  error_code getHidden(bool &Result) const;
+
   /// @brief Get a string that represents the type of this relocation.
   ///
   /// This is for display purposes only.
@@ -286,6 +291,10 @@
                                                  int64_t &Res) const = 0;
   virtual error_code getRelocationValueString(DataRefImpl Rel,
                                        SmallVectorImpl<char> &Result) const = 0;
+  virtual error_code getRelocationHidden(DataRefImpl Rel, bool &Result) const {
+    Result = false;
+    return object_error::success;
+  }
 
 public:
 
@@ -483,6 +492,10 @@
   return OwningObject->getRelocationValueString(RelocationPimpl, Result);
 }
 
+inline error_code RelocationRef::getHidden(bool &Result) const {
+  return OwningObject->getRelocationHidden(RelocationPimpl, Result);
+}
+
 } // end namespace object
 } // end namespace llvm
 

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=142961&r1=142960&r2=142961&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Tue Oct 25 15:35:53 2011
@@ -952,6 +952,38 @@
   return object_error::success;
 }
 
+error_code MachOObjectFile::getRelocationHidden(DataRefImpl Rel,
+                                                bool &Result) const {
+  InMemoryStruct<macho::RelocationEntry> RE;
+  getRelocation(Rel, RE);
+
+  unsigned Type = (RE->Word1 >> 28) & 0xF;
+  unsigned Arch = getArch();
+
+  Result = false;
+
+  // On arches that use the generic relocations, GENERIC_RELOC_PAIR
+  // is always hidden.
+  if (Arch == Triple::x86 || Arch == Triple::arm) {
+    if (Type == 1) Result = true;
+  } else if (Arch == Triple::x86_64) {
+    // On x86_64, X86_64_RELOC_UNSIGNED is hidden only when it follows
+    // an X864_64_RELOC_SUBTRACTOR.
+    if (Type == 0 && Rel.d.a > 0) {
+      DataRefImpl RelPrev = Rel;
+      RelPrev.d.a--;
+      InMemoryStruct<macho::RelocationEntry> REPrev;
+      getRelocation(RelPrev, REPrev);
+
+      unsigned PrevType = (REPrev->Word1 >> 28) & 0xF;
+
+      if (PrevType == 5) Result = true;
+    }
+  }
+
+  return object_error::success;
+}
+
 /*===-- Miscellaneous -----------------------------------------------------===*/
 
 uint8_t MachOObjectFile::getBytesInAddress() const {

Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=142961&r1=142960&r2=142961&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Tue Oct 25 15:35:53 2011
@@ -301,9 +301,15 @@
 
         // Print relocation for instruction.
         while (rel_cur != rel_end) {
+          bool hidden = false;
           uint64_t addr;
           SmallString<16> name;
           SmallString<32> val;
+
+          // If this relocation is hidden, skip it.
+          if (error(rel_cur->getHidden(hidden))) goto skip_print_rel;
+          if (hidden) goto skip_print_rel;
+
           if (error(rel_cur->getAddress(addr))) goto skip_print_rel;
           // Stop when rel_cur's address is past the current instruction.
           if (addr >= Index + Size) break;
@@ -336,9 +342,12 @@
                              ri != re; ri.increment(ec)) {
       if (error(ec)) return;
 
+      bool hidden;
       uint64_t address;
       SmallString<32> relocname;
       SmallString<32> valuestr;
+      if (error(ri->getHidden(hidden))) continue;
+      if (hidden) continue;
       if (error(ri->getTypeName(relocname))) continue;
       if (error(ri->getAddress(address))) continue;
       if (error(ri->getValueString(valuestr))) continue;



From isanbard at gmail.com  Tue Oct 25 15:37:45 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 25 Oct 2011 20:37:45 -0000
Subject: [llvm-commits] [llvm] r142963 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111025203746.09231312800A@llvm.org>

Author: void
Date: Tue Oct 25 15:37:45 2011
New Revision: 142963

URL: http://llvm.org/viewvc/llvm-project?rev=142963&view=rev
Log:
Add mention of Portable OpenCL to external OS projects.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142963&r1=142962&r2=142963&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 15:37:45 2011
@@ -323,6 +323,19 @@
 </div>
 
 <!--=========================================================================-->
+<h3>Portable OpenCL (pocl)</h3>
+
+<div>
+
+<p>Portable OpenCL is an open source implementation of the OpenCL standard which
+   can be easily adapted for new targets. One of the goals of the project is
+   improving performance portability of OpenCL programs, avoiding the need for
+   target-dependent manual optimizations. A "native" target is included, which
+   allows running OpenCL kernels on the host (CPU).</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>TTA-based Co-design Environment (TCE)</h3>
 
 <div>



From isanbard at gmail.com  Tue Oct 25 15:39:06 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 25 Oct 2011 20:39:06 -0000
Subject: [llvm-commits] [llvm] r142965 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111025203906.DFBCE312800A@llvm.org>

Author: void
Date: Tue Oct 25 15:39:06 2011
New Revision: 142965

URL: http://llvm.org/viewvc/llvm-project?rev=142965&view=rev
Log:
Add mention of Pure to external OS projects.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142965&r1=142964&r2=142965&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 15:39:06 2011
@@ -336,6 +336,27 @@
 </div>
 
 <!--=========================================================================-->
+<h3>Pure</h3>
+  
+<div>
+<p><a href="http://pure-lang.googlecode.com/">Pure</a> is an
+  algebraic/functional programming language based on term rewriting. Programs
+  are collections of equations which are used to evaluate expressions in a
+  symbolic fashion. The interpreter uses LLVM as a backend to JIT-compile Pure
+  programs to fast native code. Pure offers dynamic typing, eager and lazy
+  evaluation, lexical closures, a hygienic macro system (also based on term
+  rewriting), built-in list and matrix support (including list and matrix
+  comprehensions) and an easy-to-use interface to C and other programming
+  languages (including the ability to load LLVM bitcode modules, and inline C,
+  C++, Fortran and Faust code in Pure programs if the corresponding LLVM-enabled
+  compilers are installed).</p>
+  
+<p>Pure version 0.48 has been tested and is known to work with LLVM 3.0
+  (and continues to work with older LLVM releases &gt;= 2.5).</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>TTA-based Co-design Environment (TCE)</h3>
 
 <div>
@@ -391,29 +412,6 @@
 
 <!--=========================================================================-->
 <!--
-<h3>Pure</h3>
-  
-<div>
-<p><a href="http://pure-lang.googlecode.com/">Pure</a> is an
-  algebraic/functional
-  programming language based on term rewriting. Programs are collections
-  of equations which are used to evaluate expressions in a symbolic
-  fashion. The interpreter uses LLVM as a backend to JIT-compile Pure
-  programs to fast native code. Pure offers dynamic typing, eager and lazy
-  evaluation, lexical closures, a hygienic macro system (also based on
-  term rewriting), built-in list and matrix support (including list and
-  matrix comprehensions) and an easy-to-use interface to C and other
-  programming languages (including the ability to load LLVM bitcode
-  modules, and inline C, C++, Fortran and Faust code in Pure programs if
-  the corresponding LLVM-enabled compilers are installed).</p>
-  
-<p>Pure version 0.47 has been tested and is known to work with LLVM 3.0
-  (and continues to work with older LLVM releases &gt;= 2.5).</p>
-</div>
--->
-
-<!--=========================================================================-->
-<!--
 <h3 id="icedtea">IcedTea Java Virtual Machine Implementation</h3>
 
 <div>



From isanbard at gmail.com  Tue Oct 25 15:40:26 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 25 Oct 2011 20:40:26 -0000
Subject: [llvm-commits] [llvm] r142966 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111025204026.51829312800A@llvm.org>

Author: void
Date: Tue Oct 25 15:40:26 2011
New Revision: 142966

URL: http://llvm.org/viewvc/llvm-project?rev=142966&view=rev
Log:
Add mention of SAFECode to external OS projects.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142966&r1=142965&r2=142966&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 15:40:26 2011
@@ -357,6 +357,21 @@
 </div>
 
 <!--=========================================================================-->
+<h3>SAFECode</h3>
+
+<div>
+
+<p><a href="http://safecode.cs.illinois.edu">SAFECode</a> is a memory safe C/C++
+   compiler built using LLVM.  It takes standard, unannotated C/C++ code,
+   analyzes the code to ensure that memory accesses and array indexing
+   operations are safe, and instruments the code with run-time checks when
+   safety cannot be proven statically.  SAFECode can be used as a debugging aid
+   (like Valgrind) to find and repair memory safety bugs.  It can also be used
+   to protect code from security attacks at run-time.</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>TTA-based Co-design Environment (TCE)</h3>
 
 <div>



From resistor at mac.com  Tue Oct 25 15:44:01 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 25 Oct 2011 20:44:01 -0000
Subject: [llvm-commits] [llvm] r142970 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20111025204401.1C28E3128018@llvm.org>

Author: resistor
Date: Tue Oct 25 15:44:00 2011
New Revision: 142970

URL: http://llvm.org/viewvc/llvm-project?rev=142970&view=rev
Log:
Remove extraneous printing of "-PC".

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=142970&r1=142969&r2=142970&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Tue Oct 25 15:44:00 2011
@@ -828,7 +828,6 @@
           report_fatal_error(ec.message());
 
         fmt << Name << "-" << SucName;
-        if (isPCRel) fmt << "-PC";
       }
       case 6: // X86_64_RELOC_SIGNED1
         fmt << Name << "-1";



From gkistanova at gmail.com  Tue Oct 25 16:02:32 2011
From: gkistanova at gmail.com (Galina Kistanova)
Date: Tue, 25 Oct 2011 21:02:32 -0000
Subject: [llvm-commits] [zorg] r142972 -
	/zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py
Message-ID: <20111025210232.31581312800A@llvm.org>

Author: gkistanova
Date: Tue Oct 25 16:02:32 2011
New Revision: 142972

URL: http://llvm.org/viewvc/llvm-project?rev=142972&view=rev
Log:
Change https to http.

Modified:
    zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py

Modified: zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py?rev=142972&r1=142971&r2=142972&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py (original)
+++ zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py Tue Oct 25 16:02:32 2011
@@ -31,7 +31,7 @@
 
     f.addStep(SVN(name='svn-lldb',
                   mode='update',
-                  baseURL='https://llvm.org/svn/llvm-project/lldb/',
+                  baseURL='http://llvm.org/svn/llvm-project/lldb/',
                   defaultBranch='trunk',
                   workdir='%s/tools/lldb' % llvm_srcdir))
     f.addStep(SetProperty(command='grep ^our.*llvm_revision scripts/build-llvm.pl | cut -d \\" -f 2',



From ahatanak at gmail.com  Tue Oct 25 16:07:03 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Tue, 25 Oct 2011 14:07:03 -0700
Subject: [llvm-commits] [PATCH][Review request] Change handling of byval
 arguments passed in registers.
In-Reply-To: <CACk9Fxab4Jpv8Q0p-asNxLu6S0EbogCQDC-hgQbbD8T=9rOv9g@mail.gmail.com>
References: <CAB297QxWzSeCdO0NCpysTABP6vNK0ic97eH6BK-hDrQneMwJrA@mail.gmail.com>
	<CACk9Fxab4Jpv8Q0p-asNxLu6S0EbogCQDC-hgQbbD8T=9rOv9g@mail.gmail.com>
Message-ID: <CAB297QxJ6w2F0Gu65NSHF4LJa3feMMtTw5WaOu6Cju=+jpLhOQ@mail.gmail.com>

Hi Bruno,

Are you suggesting front-end (clang) should stop generating byval args
altogether?
That might work, but it is a fairly major change, and I am reluctant
to do that now.

The intent of the patch was to make what seemed to me an ARM specific
implementation more generic. I think it is possible to handle more
than one byvals without changing CallingConvLower.cpp or
CallingConvLower.h, but it probably will not look as simple as the
implementation in the patch.

On Tue, Oct 25, 2011 at 11:50 AM, Bruno Cardoso Lopes
<bruno.cardoso at gmail.com> wrote:
> Hi Akira,
>
> On Tue, Oct 25, 2011 at 4:11 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>> This patch enables handling of functions with multiple byval arguments.
>> foo(struct S1 a0, struct S1 a1);
>> This feature hasn't been necessary since it seems that ARM, which was
>> the only user of FirstByValReg, allows just one byval argument being
>> passed.
>>
>> All registers used to pass or receive byval arguments are stored in a
>> map, which obviates the need to rediscover them later.
>>
>> Also, I think the following functions can be simplified if variable
>> FirstByValRegValid is removed. You can tell whether FirstByValReg is
>> valid or not by checking whether it is 0 since enums for registers are
>> non-zero (NoRegister is 0).
>>
>> unsigned getFirstByValReg() { return FirstByValRegValid ? FirstByValReg : 0; }
>> void setFirstByValReg(unsigned r) { FirstByValReg = r;
>> FirstByValRegValid = true; }
>> void clearFirstByValReg() { FirstByValReg = 0; FirstByValRegValid = false; }
>> bool isFirstByValRegValid() { return FirstByValRegValid; }
>
> I may be missing something, but why don't handle this sort of Mips
> requirement in the front-end (clang)?
>


>
> --
> Bruno Cardoso Lopes
> http://www.brunocardoso.cc
>

From hfinkel at anl.gov  Tue Oct 25 16:23:02 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Tue, 25 Oct 2011 16:23:02 -0500
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <1319231089.6498.6223.camel@sapling>
References: <1319231089.6498.6223.camel@sapling>
Message-ID: <1319577782.6498.6360.camel@sapling>

I've attached an improved version of the autovectorization pass. This
version will also vectorize loads and stores, casts, and some intrinsics
(fma and trig. functions).

There are, correspondingly, a few new options:
bb-vectorize-no-casts -- Don't try to vectorize casting (conversion)
operations
bb-vectorize-no-math -- Don't try to vectorize floating-point math
intrinsics (this is just the trig. functions right now)
bb-vectorize-no-fma -- Don't try to vectorize the fused-multiply-add
intrinsic
bb-vectorize-no-mem-ops -- Don't try to vectorize loads and stores
bb-vectorize-aligned-only -- Only generate aligned loads and stores

To make this really useful, there are some improvements necessary to
InstCombine (and a few other things). But the autovectorization process
itself now seems to work well. Please review this patch; adding the
vectorization pass itself should not affect any other code (although it
does touch some common files to add support for the pass into opt). If
it looks okay, please let me know, and I'll commit it.

Thanks in advance,
Hal

On Fri, 2011-10-21 at 16:04 -0500, Hal Finkel wrote:
> I've attached an initial version of a basic-block autovectorization
> pass. It works by searching a basic block for pairable (independent)
> instructions, and, using a chain-seeking heuristic, selects pairings
> likely to provide an overall speedup (if such pairings can be found).
> The selected pairs are then fused and, if necessary, other instructions
> are moved in order to maintain data-flow consistency. This works only
> within one basic block, but can do loop vectorization in combination
> with (partial) unrolling. The basic idea was inspired by the Vienna MAP
> Vectorizor, which has been used to vectorize FFT kernels, but the
> algorithm used here is different.
> 
> To try it, use -bb-vectorize with opt. There are a few options:
> -bb-vectorize-req-chain-depth: default: 3 -- The depth of the chain of
> instruction pairs necessary in order to consider the pairs that compose
> the chain worthy of vectorization.
> -bb-vectorize-vector-bits: default: 128 -- The size of the target vector
> registers
> -bb-vectorize-no-ints -- Don't consider integer instructions
> -bb-vectorize-no-floats -- Don't consider floating-point instructions  
> 
> The vectorizor generates a lot of insert_element/extract_element pairs;
> The assumption is that other passes will turn these into shuffles when
> possible (it looks like some work is necessary here). It will also
> vectorize vector instructions, and generates shuffles in this case
> (again, other passes should combine these as appropriate).
> 
> Currently, it does not fuse load or store instructions, but that is a
> feature that I'd like to add. Of course, alignment information is an
> issue for load/store vectorization (or maybe I should just fuse them
> anyway and let isel deal with unaligned cases?).
> 
> Also, support needs to be added for fusing known intrinsics (fma, etc.),
> and, as has been discussed on llvmdev, we should add some intrinsics to
> allow the generation of addsub-type instructions.
> 
> I've included a few tests, but it needs more. Please review (I'll commit
> if and when everyone is happy).
> 
> Thanks in advance,
> Hal
> 
> P.S. There is another option (not so useful right now, but could be):
> -bb-vectorize-fast-dep -- Don't do a full inter-instruction dependency
> analysis; instead stop looking for instruction pairs after the first use
> of an instruction's value. [This makes the pass faster, but would
> require a data-dependence-based reordering pass in order to be
> effective].
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory
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From nadav.rotem at intel.com  Tue Oct 25 17:02:03 2011
From: nadav.rotem at intel.com (Rotem, Nadav)
Date: Wed, 26 Oct 2011 00:02:03 +0200
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <1319577782.6498.6360.camel@sapling>
References: <1319231089.6498.6223.camel@sapling>
	<1319577782.6498.6360.camel@sapling>
Message-ID: <6594DDFF12B03D4E89690887C248699402A2D7A454@hasmsx504.ger.corp.intel.com>

Hal, 

As you mentioned, your patch implements only one kind of vectorization. There may be other kinds of vectorizations in LLVM. As such, I suggest that you create a 'vectorize' directory with your pass in it. You can name it bb-vectorization.

Thanks,
Nadav

-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Hal Finkel
Sent: Tuesday, October 25, 2011 23:23
To: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass

I've attached an improved version of the autovectorization pass. This version will also vectorize loads and stores, casts, and some intrinsics (fma and trig. functions).

There are, correspondingly, a few new options:
bb-vectorize-no-casts -- Don't try to vectorize casting (conversion) operations bb-vectorize-no-math -- Don't try to vectorize floating-point math intrinsics (this is just the trig. functions right now) bb-vectorize-no-fma -- Don't try to vectorize the fused-multiply-add intrinsic bb-vectorize-no-mem-ops -- Don't try to vectorize loads and stores bb-vectorize-aligned-only -- Only generate aligned loads and stores

To make this really useful, there are some improvements necessary to InstCombine (and a few other things). But the autovectorization process itself now seems to work well. Please review this patch; adding the vectorization pass itself should not affect any other code (although it does touch some common files to add support for the pass into opt). If it looks okay, please let me know, and I'll commit it.

Thanks in advance,
Hal

On Fri, 2011-10-21 at 16:04 -0500, Hal Finkel wrote:
> I've attached an initial version of a basic-block autovectorization 
> pass. It works by searching a basic block for pairable (independent) 
> instructions, and, using a chain-seeking heuristic, selects pairings 
> likely to provide an overall speedup (if such pairings can be found).
> The selected pairs are then fused and, if necessary, other 
> instructions are moved in order to maintain data-flow consistency. 
> This works only within one basic block, but can do loop vectorization 
> in combination with (partial) unrolling. The basic idea was inspired 
> by the Vienna MAP Vectorizor, which has been used to vectorize FFT 
> kernels, but the algorithm used here is different.
> 
> To try it, use -bb-vectorize with opt. There are a few options:
> -bb-vectorize-req-chain-depth: default: 3 -- The depth of the chain of 
> instruction pairs necessary in order to consider the pairs that 
> compose the chain worthy of vectorization.
> -bb-vectorize-vector-bits: default: 128 -- The size of the target 
> vector registers -bb-vectorize-no-ints -- Don't consider integer 
> instructions -bb-vectorize-no-floats -- Don't consider floating-point 
> instructions
> 
> The vectorizor generates a lot of insert_element/extract_element 
> pairs; The assumption is that other passes will turn these into 
> shuffles when possible (it looks like some work is necessary here). It 
> will also vectorize vector instructions, and generates shuffles in 
> this case (again, other passes should combine these as appropriate).
> 
> Currently, it does not fuse load or store instructions, but that is a 
> feature that I'd like to add. Of course, alignment information is an 
> issue for load/store vectorization (or maybe I should just fuse them 
> anyway and let isel deal with unaligned cases?).
> 
> Also, support needs to be added for fusing known intrinsics (fma, 
> etc.), and, as has been discussed on llvmdev, we should add some 
> intrinsics to allow the generation of addsub-type instructions.
> 
> I've included a few tests, but it needs more. Please review (I'll 
> commit if and when everyone is happy).
> 
> Thanks in advance,
> Hal
> 
> P.S. There is another option (not so useful right now, but could be):
> -bb-vectorize-fast-dep -- Don't do a full inter-instruction dependency 
> analysis; instead stop looking for instruction pairs after the first 
> use of an instruction's value. [This makes the pass faster, but would 
> require a data-dependence-based reordering pass in order to be 
> effective].
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

--
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
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From bigcheesegs at gmail.com  Tue Oct 25 17:30:42 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Tue, 25 Oct 2011 22:30:42 -0000
Subject: [llvm-commits] [llvm] r142981 - in /llvm/trunk:
 include/llvm/Object/Archive.h lib/Object/Archive.cpp
Message-ID: <20111025223042.7274D312800A@llvm.org>

Author: mspencer
Date: Tue Oct 25 17:30:42 2011
New Revision: 142981

URL: http://llvm.org/viewvc/llvm-project?rev=142981&view=rev
Log:
Object/Archive: Add BSD style long file name support and skip internal members.

Modified:
    llvm/trunk/include/llvm/Object/Archive.h
    llvm/trunk/lib/Object/Archive.cpp

Modified: llvm/trunk/include/llvm/Object/Archive.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/Archive.h?rev=142981&r1=142980&r2=142981&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/Archive.h (original)
+++ llvm/trunk/include/llvm/Object/Archive.h Tue Oct 25 17:30:42 2011
@@ -71,7 +71,7 @@
 
   Archive(MemoryBuffer *source, error_code &ec);
 
-  child_iterator begin_children() const;
+  child_iterator begin_children(bool skip_internal = true) const;
   child_iterator end_children() const;
 
   // Cast methods.

Modified: llvm/trunk/lib/Object/Archive.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/Archive.cpp?rev=142981&r1=142980&r2=142981&view=diff
==============================================================================
--- llvm/trunk/lib/Object/Archive.cpp (original)
+++ llvm/trunk/lib/Object/Archive.cpp Tue Oct 25 17:30:42 2011
@@ -32,7 +32,11 @@
 
   ///! Get the name without looking up long names.
   StringRef getName() const {
-    char EndCond = Name[0] == '/' ? ' ' : '/';
+    char EndCond;
+    if (Name[0] == '/' || Name[0] == '#')
+      EndCond = ' ';
+    else
+      EndCond = '/';
     StringRef::size_type end = StringRef(Name, sizeof(Name)).find(EndCond);
     if (end == StringRef::npos)
       end = sizeof(Name);
@@ -53,6 +57,21 @@
 }
 }
 
+static bool isInternalMember(const ArchiveMemberHeader &amh) {
+  const char *internals[] = {
+    "/",
+    "//",
+    "#_LLVM_SYM_TAB_#"
+    };
+
+  StringRef name = amh.getName();
+  for (std::size_t i = 0; i < sizeof(internals) / sizeof(*internals); ++i) {
+    if (name == internals[i])
+      return true;
+  }
+  return false;
+}
+
 Archive::Child Archive::Child::getNext() const {
   size_t SpaceToSkip = sizeof(ArchiveMemberHeader) +
     ToHeader(Data.data())->getSize();
@@ -101,6 +120,11 @@
       return object_error::parse_failed;
     Result = addr;
     return object_error::success;
+  } else if (name.startswith("#1/")) {
+    APInt name_size;
+    name.substr(3).getAsInteger(10, name_size);
+    Result = Data.substr(0, name_size.getZExtValue());
+    return object_error::success;
   }
   // It's a simple name.
   if (name[name.size() - 1] == '/')
@@ -111,14 +135,27 @@
 }
 
 uint64_t Archive::Child::getSize() const {
-  return ToHeader(Data.data())->getSize();
+  uint64_t size = ToHeader(Data.data())->getSize();
+  // Don't include attached name.
+  StringRef name =  ToHeader(Data.data())->getName();
+  if (name.startswith("#1/")) {
+    APInt name_size;
+    name.substr(3).getAsInteger(10, name_size);
+    size -= name_size.getZExtValue();
+  }
+  return size;
 }
 
 MemoryBuffer *Archive::Child::getBuffer() const {
   StringRef name;
   if (getName(name)) return NULL;
-  return MemoryBuffer::getMemBuffer(Data.substr(sizeof(ArchiveMemberHeader),
-                                                getSize()),
+  int size = sizeof(ArchiveMemberHeader);
+  if (name.startswith("#1/")) {
+    APInt name_size;
+    name.substr(3).getAsInteger(10, name_size);
+    size += name_size.getZExtValue();
+  }
+  return MemoryBuffer::getMemBuffer(Data.substr(size, getSize()),
                                     name,
                                     false);
 }
@@ -144,7 +181,7 @@
   }
 
   // Get the string table. It's the 3rd member.
-  child_iterator StrTable = begin_children();
+  child_iterator StrTable = begin_children(false);
   child_iterator e = end_children();
   for (int i = 0; StrTable != e && i < 2; ++StrTable, ++i) {}
 
@@ -156,11 +193,15 @@
   ec = object_error::success;
 }
 
-Archive::child_iterator Archive::begin_children() const {
+Archive::child_iterator Archive::begin_children(bool skip_internal) const {
   const char *Loc = Data->getBufferStart() + Magic.size();
   size_t Size = sizeof(ArchiveMemberHeader) +
     ToHeader(Loc)->getSize();
-  return Child(this, StringRef(Loc, Size));
+  Child c(this, StringRef(Loc, Size));
+  // Skip internals at the beginning of an archive.
+  if (skip_internal && isInternalMember(*ToHeader(Loc)))
+    return c.getNext();
+  return c;
 }
 
 Archive::child_iterator Archive::end_children() const {



From bigcheesegs at gmail.com  Tue Oct 25 17:30:58 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Tue, 25 Oct 2011 22:30:58 -0000
Subject: [llvm-commits] [llvm] r142982 - in /llvm/trunk/test/Object:
 TestObjectFiles/archive-test.a-bitcode TestObjectFiles/trivial.ll
 nm-archive.test
Message-ID: <20111025223058.7FE62312800A@llvm.org>

Author: mspencer
Date: Tue Oct 25 17:30:58 2011
New Revision: 142982

URL: http://llvm.org/viewvc/llvm-project?rev=142982&view=rev
Log:
Object: change test to create archive.

Added:
    llvm/trunk/test/Object/TestObjectFiles/trivial.ll
Removed:
    llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode
Modified:
    llvm/trunk/test/Object/nm-archive.test

Removed: llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode?rev=142981&view=auto
==============================================================================
Binary files llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode (original) and llvm/trunk/test/Object/TestObjectFiles/archive-test.a-bitcode (removed) differ

Added: llvm/trunk/test/Object/TestObjectFiles/trivial.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/TestObjectFiles/trivial.ll?rev=142982&view=auto
==============================================================================
--- llvm/trunk/test/Object/TestObjectFiles/trivial.ll (added)
+++ llvm/trunk/test/Object/TestObjectFiles/trivial.ll Tue Oct 25 17:30:58 2011
@@ -0,0 +1,12 @@
+ at .str = private unnamed_addr constant [13 x i8] c"Hello World\0A\00", align 1
+
+define i32 @main() nounwind {
+entry:
+  %call = tail call i32 @puts(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) nounwind
+  tail call void bitcast (void (...)* @SomeOtherFunction to void ()*)() nounwind
+  ret i32 0
+}
+
+declare i32 @puts(i8* nocapture) nounwind
+
+declare void @SomeOtherFunction(...)

Modified: llvm/trunk/test/Object/nm-archive.test
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Object/nm-archive.test?rev=142982&r1=142981&r2=142982&view=diff
==============================================================================
--- llvm/trunk/test/Object/nm-archive.test (original)
+++ llvm/trunk/test/Object/nm-archive.test Tue Oct 25 17:30:58 2011
@@ -1,7 +1,8 @@
 RUN: llvm-nm %p/TestObjectFiles/archive-test.a-coff-i386 \
 RUN:         | FileCheck %s -check-prefix COFF
-RUN: llvm-nm %p/TestObjectFiles/archive-test.a-bitcode \
-RUN:         | FileCheck %s -check-prefix BITCODE
+RUN: llvm-as %p/TestObjectFiles/trivial.ll -o=%t1
+RUN: llvm-ar rcs %t2 %t1
+RUN: llvm-nm %t2 | FileCheck %s -check-prefix BITCODE
 
 
 COFF: trivial-object-test.coff-i386:



From bigcheesegs at gmail.com  Tue Oct 25 17:31:11 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Tue, 25 Oct 2011 22:31:11 -0000
Subject: [llvm-commits] [llvm] r142983 - /llvm/trunk/lib/Object/Archive.cpp
Message-ID: <20111025223111.F02B3312800A@llvm.org>

Author: mspencer
Date: Tue Oct 25 17:31:11 2011
New Revision: 142983

URL: http://llvm.org/viewvc/llvm-project?rev=142983&view=rev
Log:
Object/Archive: Cleanup anon namespace.

Modified:
    llvm/trunk/lib/Object/Archive.cpp

Modified: llvm/trunk/lib/Object/Archive.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/Archive.cpp?rev=142983&r1=142982&r2=142983&view=diff
==============================================================================
--- llvm/trunk/lib/Object/Archive.cpp (original)
+++ llvm/trunk/lib/Object/Archive.cpp Tue Oct 25 17:31:11 2011
@@ -18,9 +18,9 @@
 using namespace llvm;
 using namespace object;
 
-namespace {
-const StringRef Magic = "!<arch>\n";
+static const StringRef Magic = "!<arch>\n";
 
+namespace {
 struct ArchiveMemberHeader {
   char Name[16];
   char LastModified[12];
@@ -51,11 +51,12 @@
     return ret.getZExtValue();
   }
 };
+}
 
-const ArchiveMemberHeader *ToHeader(const char *base) {
+static const ArchiveMemberHeader *ToHeader(const char *base) {
   return reinterpret_cast<const ArchiveMemberHeader *>(base);
 }
-}
+
 
 static bool isInternalMember(const ArchiveMemberHeader &amh) {
   const char *internals[] = {
@@ -207,7 +208,3 @@
 Archive::child_iterator Archive::end_children() const {
   return Child(this, StringRef(0, 0));
 }
-
-namespace llvm {
-
-} // end namespace llvm



From bigcheesegs at gmail.com  Tue Oct 25 17:45:47 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Tue, 25 Oct 2011 22:45:47 -0000
Subject: [llvm-commits] [llvm] r142984 -
	/llvm/trunk/tools/llvm-nm/llvm-nm.cpp
Message-ID: <20111025224548.04569312800A@llvm.org>

Author: mspencer
Date: Tue Oct 25 17:45:47 2011
New Revision: 142984

URL: http://llvm.org/viewvc/llvm-project?rev=142984&view=rev
Log:
llvm-nm: Use correct format string. Patch by Stepan Dyatkovskiy!

Modified:
    llvm/trunk/tools/llvm-nm/llvm-nm.cpp

Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=142984&r1=142983&r2=142984&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
+++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Tue Oct 25 17:45:47 2011
@@ -192,9 +192,9 @@
       strcpy(SymbolSizeStr, "        ");
 
     if (i->Address != object::UnknownAddressOrSize)
-      format("%08x", i->Address).print(SymbolAddrStr, sizeof(SymbolAddrStr));
+      format("%08llx", i->Address).print(SymbolAddrStr, sizeof(SymbolAddrStr));
     if (i->Size != object::UnknownAddressOrSize)
-      format("%08x", i->Size).print(SymbolSizeStr, sizeof(SymbolSizeStr));
+      format("%08llx", i->Size).print(SymbolSizeStr, sizeof(SymbolSizeStr));
 
     if (OutputFormat == posix) {
       outs() << i->Name << " " << i->TypeChar << " "



From bigcheesegs at gmail.com  Tue Oct 25 17:48:50 2011
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Tue, 25 Oct 2011 15:48:50 -0700
Subject: [llvm-commits] [LLVM, llvm-nm,
 arm] Fix for nm-trivial-object.test and for nm-archive.test
In-Reply-To: <4EA6F036.1000300@narod.ru>
References: <4EA1BF05.7030307@narod.ru>
	<CACXTSinHzMOEUhDi2nJ17ZFs54zwX5WuNbpQgh+Qrw=scVTeow@mail.gmail.com>
	<4EA514A1.3020109@narod.ru> <4EA5BE51.7040105@narod.ru>
	<4EA6F036.1000300@narod.ru>
Message-ID: <CACXTSim=FdU9xwB8J+2XsCh3076EP4A7SeGd0gMBbr7dzwrABA@mail.gmail.com>

On Tue, Oct 25, 2011 at 10:21 AM, Stepan Dyatkovskiy <stpworld at narod.ru> wrote:
> ping.
>
> Regards,
> Stepan.
>
> Stepan Dyatkovskiy wrote:
>> Hi all. Please find the reworked patch in attachment.
>>
>> Regards,
>> Stepan.

Committed as r142984. Thanks!

- Michael Spencer

>> Stepan Dyatkovskiy wrote:
>>> Hi,
>>> Yes, you right. Sorry, I actually mean clang-native-arm-cortex-a9:
>>> http://lab.llvm.org:8011/builders/clang-native-arm-cortex-a9/builds/155
>>>
>>> Regards,
>>> Stepan.
>>>
>>> Michael Spencer wrote:
>>>> On Fri, Oct 21, 2011 at 11:50 AM, Stepan
>>>> Dyatkovskiy<stpworld at narod.ru> wrote:
>>>>> Hi all,
>>>>> Please find the patch for review that fixes nm-trivial-object.test and
>>>>> nm-archive.test for arm architecture.
>>>>>
>>>>> Regards,
>>>>> Stepan
>>>>
>>>> These tests are currently passing on the llvm-arm-linux buildbot.
>>>> Where are you encountering the failure?
>>>>
>>>> This does, however, show that the code is currently wrong. It's trying
>>>> to print a uint64_t as an unsigned. The code needs to use the address
>>>> size from the object file to print either 8 byte or 4 byte addresses
>>>> and sizes using the correct format string.
>>>>
>>>> Thanks for bringing this up!
>>>>
>>>> - Michael Spencer
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>

From peter at pcc.me.uk  Tue Oct 25 18:05:16 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Tue, 25 Oct 2011 23:05:16 -0000
Subject: [llvm-commits] [zorg] r142985 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20111025230516.372DA312800A@llvm.org>

Author: pcc
Date: Tue Oct 25 18:05:16 2011
New Revision: 142985

URL: http://llvm.org/viewvc/llvm-project?rev=142985&view=rev
Log:
Switch to a gcc installation which actually provides g++

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=142985&r1=142984&r2=142985&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Tue Oct 25 18:05:16 2011
@@ -273,9 +273,8 @@
 # LLDB builders.
 def _get_lldb_builders():
     gcc_latest_env = {
-        'LD_LIBRARY_PATH': '/opt/cfarm/mpc-latest/lib:/opt/cfarm/mpfr-latest/lib:/opt/cfarm/gmp-latest/lib',
-        'CC':  '/opt/cfarm/gcc-core-latest/bin/gcc',
-        'CXX': '/opt/cfarm/gcc-core-latest/bin/g++'}
+        'CC':  '/opt/cfarm/release/4.5.1/bin/gcc',
+        'CXX': '/opt/cfarm/release/4.5.1/bin/g++'}
 
     gcc_m32_latest_env = gcc_latest_env.copy()
     gcc_m32_latest_env['CC'] += ' -m32'



From jcarter at mips.com  Tue Oct 25 19:05:27 2011
From: jcarter at mips.com (Carter, Jack)
Date: Wed, 26 Oct 2011 00:05:27 +0000
Subject: [llvm-commits] [PATCH][Review request] Mips direct object
	generation patch #3 of 6
Message-ID: <86AC779C188FE74F88F6494478B46332E82D84@exchdb03.mips.com>

This is the third of six patches for Mips direct object generation.

    lib/Target/Mips/MipsMCInstLower.cpp
    lib/Target/Mips/MipsMCInstLower.h

The patch is attached.

Jack
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From hfinkel at anl.gov  Tue Oct 25 19:06:10 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Tue, 25 Oct 2011 19:06:10 -0500
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <6594DDFF12B03D4E89690887C248699402A2D7A454@hasmsx504.ger.corp.intel.com>
References: <1319231089.6498.6223.camel@sapling>
	<1319577782.6498.6360.camel@sapling>
	<6594DDFF12B03D4E89690887C248699402A2D7A454@hasmsx504.ger.corp.intel.com>
Message-ID: <1319587570.6498.6369.camel@sapling>

On Wed, 2011-10-26 at 00:02 +0200, Rotem, Nadav wrote:
> Hal, 
> 
> As you mentioned, your patch implements only one kind of vectorization. There may be other kinds of vectorizations in LLVM.

I certainly hope that will be so. Actually, I've talked to Ralf
Karrenberg about his whole-function vectorization work, and I think that
he and his collaborators plan to contribute that as well.

> As such, I suggest that you create a 'vectorize' directory with your pass in it. You can name it bb-vectorization.

The current patch does that; it creates lib/Transforms/Vectorize and
implements a BBVectorize pass.

 -Hal

> 
> Thanks,
> Nadav
> 
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Hal Finkel
> Sent: Tuesday, October 25, 2011 23:23
> To: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
> 
> I've attached an improved version of the autovectorization pass. This version will also vectorize loads and stores, casts, and some intrinsics (fma and trig. functions).
> 
> There are, correspondingly, a few new options:
> bb-vectorize-no-casts -- Don't try to vectorize casting (conversion) operations bb-vectorize-no-math -- Don't try to vectorize floating-point math intrinsics (this is just the trig. functions right now) bb-vectorize-no-fma -- Don't try to vectorize the fused-multiply-add intrinsic bb-vectorize-no-mem-ops -- Don't try to vectorize loads and stores bb-vectorize-aligned-only -- Only generate aligned loads and stores
> 
> To make this really useful, there are some improvements necessary to InstCombine (and a few other things). But the autovectorization process itself now seems to work well. Please review this patch; adding the vectorization pass itself should not affect any other code (although it does touch some common files to add support for the pass into opt). If it looks okay, please let me know, and I'll commit it.
> 
> Thanks in advance,
> Hal
> 
> On Fri, 2011-10-21 at 16:04 -0500, Hal Finkel wrote:
> > I've attached an initial version of a basic-block autovectorization 
> > pass. It works by searching a basic block for pairable (independent) 
> > instructions, and, using a chain-seeking heuristic, selects pairings 
> > likely to provide an overall speedup (if such pairings can be found).
> > The selected pairs are then fused and, if necessary, other 
> > instructions are moved in order to maintain data-flow consistency. 
> > This works only within one basic block, but can do loop vectorization 
> > in combination with (partial) unrolling. The basic idea was inspired 
> > by the Vienna MAP Vectorizor, which has been used to vectorize FFT 
> > kernels, but the algorithm used here is different.
> > 
> > To try it, use -bb-vectorize with opt. There are a few options:
> > -bb-vectorize-req-chain-depth: default: 3 -- The depth of the chain of 
> > instruction pairs necessary in order to consider the pairs that 
> > compose the chain worthy of vectorization.
> > -bb-vectorize-vector-bits: default: 128 -- The size of the target 
> > vector registers -bb-vectorize-no-ints -- Don't consider integer 
> > instructions -bb-vectorize-no-floats -- Don't consider floating-point 
> > instructions
> > 
> > The vectorizor generates a lot of insert_element/extract_element 
> > pairs; The assumption is that other passes will turn these into 
> > shuffles when possible (it looks like some work is necessary here). It 
> > will also vectorize vector instructions, and generates shuffles in 
> > this case (again, other passes should combine these as appropriate).
> > 
> > Currently, it does not fuse load or store instructions, but that is a 
> > feature that I'd like to add. Of course, alignment information is an 
> > issue for load/store vectorization (or maybe I should just fuse them 
> > anyway and let isel deal with unaligned cases?).
> > 
> > Also, support needs to be added for fusing known intrinsics (fma, 
> > etc.), and, as has been discussed on llvmdev, we should add some 
> > intrinsics to allow the generation of addsub-type instructions.
> > 
> > I've included a few tests, but it needs more. Please review (I'll 
> > commit if and when everyone is happy).
> > 
> > Thanks in advance,
> > Hal
> > 
> > P.S. There is another option (not so useful right now, but could be):
> > -bb-vectorize-fast-dep -- Don't do a full inter-instruction dependency 
> > analysis; instead stop looking for instruction pairs after the first 
> > use of an instruction's value. [This makes the pass faster, but would 
> > require a data-dependence-based reordering pass in order to be 
> > effective].
> > 
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> --
> Hal Finkel
> Postdoctoral Appointee
> Leadership Computing Facility
> Argonne National Laboratory
> ---------------------------------------------------------------------
> Intel Israel (74) Limited
> 
> This e-mail and any attachments may contain confidential material for
> the sole use of the intended recipient(s). Any review or distribution
> by others is strictly prohibited. If you are not the intended
> recipient, please contact the sender and delete all copies.

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From isanbard at gmail.com  Tue Oct 25 19:09:55 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 00:09:55 -0000
Subject: [llvm-commits] [llvm] r142987 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026000955.56A33312800A@llvm.org>

Author: void
Date: Tue Oct 25 19:09:55 2011
New Revision: 142987

URL: http://llvm.org/viewvc/llvm-project?rev=142987&view=rev
Log:
Add mention of GHC to external OS projects.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142987&r1=142986&r2=142987&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 19:09:55 2011
@@ -298,6 +298,22 @@
 -->  
   
 <!--=========================================================================-->
+<h3>Glasgow Haskell Compiler (GHC)</h3>
+  
+<div>
+
+<p>GHC is an open source, state-of-the-art programming suite for Haskell, a
+   standard lazy functional programming language. It includes an optimizing
+   static compiler generating good code for a variety of platforms, together
+   with an interactive system for convenient, quick development.</p>
+
+<p>GHC 7.0 and onwards include an LLVM code generator, supporting LLVM 2.8 and
+   later. Since LLVM 2.9, GHC now includes experimental support for the ARM
+   platform with LLVM 3.0.</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>gwXscript</h3>
 
 <div>
@@ -448,22 +464,6 @@
 
 <!--=========================================================================-->
 <!--
-<h3>Glasgow Haskell Compiler (GHC)</h3>
-  
-<div>
-<p>GHC is an open source, state-of-the-art programming suite for Haskell,
-a standard lazy functional programming language. It includes an
-optimizing static compiler generating good code for a variety of
-platforms, together with an interactive system for convenient, quick
-development.</p>
-
-<p>In addition to the existing C and native code generators, GHC 7.0 now
-supports an LLVM code generator. GHC supports LLVM 2.7 and later.</p>
-</div>
--->
-
-<!--=========================================================================-->
-<!--
 <h3>Polly - Polyhedral optimizations for LLVM</h3>
   
 <div>



From jcarter at mips.com  Tue Oct 25 19:13:06 2011
From: jcarter at mips.com (Carter, Jack)
Date: Wed, 26 Oct 2011 00:13:06 +0000
Subject: [llvm-commits] [PATCH][Review request] Mips direct object
	generation patch #4
Message-ID: <86AC779C188FE74F88F6494478B46332E82DBE@exchdb03.mips.com>

This is the fourth of six patches for Mips direct object generation.

    lib/Target/Mips/MipsCodeEmitter.cpp
    lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
    lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

The patch is attached.

Jack
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From isanbard at gmail.com  Tue Oct 25 19:12:04 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 00:12:04 -0000
Subject: [llvm-commits] [llvm] r142988 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026001205.087DB312800A@llvm.org>

Author: void
Date: Tue Oct 25 19:12:04 2011
New Revision: 142988

URL: http://llvm.org/viewvc/llvm-project?rev=142988&view=rev
Log:
Add mention of Renderscript to external OS projects.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142988&r1=142987&r2=142988&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 19:12:04 2011
@@ -373,6 +373,25 @@
 </div>
 
 <!--=========================================================================-->
+<h3>Renderscript</h3>
+
+<div>
+
+<p><a href="http://developer.android.com/guide/topics/renderscript/index.html">Renderscript</a>
+   is Android's advanced 3D graphics rendering and compute API. It provides a
+   portable C99-based language with extensions to facilitate common use cases
+   for enhancing graphics and thread level parallelism. The Renderscript
+   compiler frontend is based on Clang/LLVM. It emits a portable bitcode format
+   for the actual compiled script code, as well as reflects a Java interface for
+   developers to control the execution of the compiled bitcode. Executable
+   machine code is then generated from this bitcode by an LLVM backend on the
+   device. Renderscript is thus able to provide a mechanism by which Android
+   developers can improve performance of their applications while retaining
+   portability.</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>SAFECode</h3>
 
 <div>



From isanbard at gmail.com  Tue Oct 25 19:14:36 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 00:14:36 -0000
Subject: [llvm-commits] [llvm] r142989 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026001436.4E5F6312800A@llvm.org>

Author: void
Date: Tue Oct 25 19:14:36 2011
New Revision: 142989

URL: http://llvm.org/viewvc/llvm-project?rev=142989&view=rev
Log:
Add mention of ClamAV to external OS projects.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142989&r1=142988&r2=142989&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 19:14:36 2011
@@ -284,7 +284,25 @@
    projects that have already been updated to work with LLVM 3.0.</p>
 
 <!--=========================================================================-->
+<h3>ClamAV</h3>
+  
+<div>
+
+<p><a href="http://www.clamav.net">Clam AntiVirus</a> is an open source (GPL)
+   anti-virus toolkit for UNIX, designed especially for e-mail scanning on mail
+   gateways.</p>
+
+<p>Since version 0.96 it
+   has <a href="http://vrt-sourcefire.blogspot.com/2010/09/introduction-to-clamavs-low-level.html">bytecode
+   signatures</a> that allow writing detections for complex malware.</p>
 
+<p>It uses LLVM's JIT to speed up the execution of bytecode on X86, X86-64,
+   PPC32/64, falling back to its own interpreter otherwise.  The git version was
+   updated to work with LLVM 3.0.</p>
+
+</div>
+
+<!--=========================================================================-->
 <!-- FIXME: Comment out
 <h3>Crack Programming Language</h3>
 



From isanbard at gmail.com  Tue Oct 25 19:16:17 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 00:16:17 -0000
Subject: [llvm-commits] [llvm] r142990 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026001617.719CD312800A@llvm.org>

Author: void
Date: Tue Oct 25 19:16:17 2011
New Revision: 142990

URL: http://llvm.org/viewvc/llvm-project?rev=142990&view=rev
Log:
Add mention of Mono to external OS projects.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142990&r1=142989&r2=142990&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 19:16:17 2011
@@ -357,6 +357,20 @@
 </div>
 
 <!--=========================================================================-->
+<h3>Mono</h3>
+
+<div>
+
+<p>An open source, cross-platform implementation of C# and the CLR that is
+   binary compatible with Microsoft.NET. Has an optional, dynamically-loaded
+   LLVM code generation backend in Mini, the JIT compiler.</p>
+
+<p>Note that we use a Git mirror of LLVM with some patches. See:
+   https://github.com/mono/llvm</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>Portable OpenCL (pocl)</h3>
 
 <div>



From isanbard at gmail.com  Tue Oct 25 19:17:54 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 00:17:54 -0000
Subject: [llvm-commits] [llvm] r142991 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026001754.641E4312800A@llvm.org>

Author: void
Date: Tue Oct 25 19:17:54 2011
New Revision: 142991

URL: http://llvm.org/viewvc/llvm-project?rev=142991&view=rev
Log:
Add mention of AddressSanitizer to external OS projects.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142991&r1=142990&r2=142991&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 19:17:54 2011
@@ -284,6 +284,19 @@
    projects that have already been updated to work with LLVM 3.0.</p>
 
 <!--=========================================================================-->
+<h3>AddressSanitizer</h3>
+  
+<div>
+
+<p><a href="http://code.google.com/p/address-sanitizer/">AddressSanitizer</a>
+   uses compiler instrumentation and a specialized malloc library to find C/C++
+   bugs such as use-after-free and out-of-bound accesses to heap, stack, and
+   globals. The key feature of the tool is speed: the average slowdown
+   introduced by AddressSanitizer is less than 2x.</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>ClamAV</h3>
   
 <div>



From jcarter at mips.com  Tue Oct 25 19:24:30 2011
From: jcarter at mips.com (Carter, Jack)
Date: Wed, 26 Oct 2011 00:24:30 +0000
Subject: [llvm-commits] [PATCH][Review request] Mips direct object
	generation patch #5 of 6
Message-ID: <86AC779C188FE74F88F6494478B46332E82DD8@exchdb03.mips.com>

This is the fifth of 6 patches for Mips direct object generation.

    lib/Target/Mips/MipsAsmPrinter.cpp

The patch is attached.

Jack
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From jcarter at mips.com  Tue Oct 25 19:31:15 2011
From: jcarter at mips.com (Carter, Jack)
Date: Wed, 26 Oct 2011 00:31:15 +0000
Subject: [llvm-commits] [PATCH][Review request] Mips direct object
	generation patch #6 of 6
Message-ID: <86AC779C188FE74F88F6494478B46332E82DEA@exchdb03.mips.com>

This is the sixth of six patches for Mips direct object generation.

With this final of six patches we can compile and execute a number of simple C tests beyond hello.c.

    lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
    lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
    lib/Target/Mips/MipsInstrInfo.td
    lib/Target/Mips/Makefile

This patch is a bit meatier than the others, but is more exclusive to the Mips direct object production. Once again we tried to pattern after the other targets that have already done direct object generation.

Future MIPS direct object generation patches will be fixes and enhancements based issues uncovered during testing.

The patch is attached.

Jack
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From wangmp at apple.com  Tue Oct 25 19:34:48 2011
From: wangmp at apple.com (Mon P Wang)
Date: Wed, 26 Oct 2011 00:34:48 -0000
Subject: [llvm-commits] [llvm] r142992 - in /llvm/trunk:
 lib/VMCore/Instructions.cpp test/Bitcode/shuffle.ll
Message-ID: <20111026003448.41B96312800A@llvm.org>

Author: wangmp
Date: Tue Oct 25 19:34:48 2011
New Revision: 142992

URL: http://llvm.org/viewvc/llvm-project?rev=142992&view=rev
Log:
The bitcode reader can create an shuffle with a place holder mask which it will
fix up later. For this special case, allow such a mask to be considered valid.
<rdar://problem/8622574>

Added:
    llvm/trunk/test/Bitcode/shuffle.ll
Modified:
    llvm/trunk/lib/VMCore/Instructions.cpp

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=142992&r1=142991&r2=142992&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Tue Oct 25 19:34:48 2011
@@ -1576,10 +1576,17 @@
         return false;
       }
     }
-  }
-  else if (!isa<UndefValue>(Mask) && !isa<ConstantAggregateZero>(Mask))
+  } else if (!isa<UndefValue>(Mask) && !isa<ConstantAggregateZero>(Mask)) {
+    // The bitcode reader can create a place holder for a forward reference
+    // used as the shuffle mask. When this occurs, the shuffle mask will
+    // fall into this case and fail. To avoid this error, do this bit of
+    // ugliness to allow such a mask pass.
+    if (const ConstantExpr* CE = dyn_cast<ConstantExpr>(Mask)) {
+      if (CE->getOpcode() == Instruction::UserOp1)
+        return true;
+    }
     return false;
-  
+  }
   return true;
 }
 

Added: llvm/trunk/test/Bitcode/shuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/shuffle.ll?rev=142992&view=auto
==============================================================================
--- llvm/trunk/test/Bitcode/shuffle.ll (added)
+++ llvm/trunk/test/Bitcode/shuffle.ll Tue Oct 25 19:34:48 2011
@@ -0,0 +1,31 @@
+; RUN: llvm-as < %s | llvm-dis
+
+; <rdar://problem/8622574>
+; tests the bitcodereader can handle the case where the reader will initially
+; create shuffle with a place holder mask.
+
+
+define <4 x float> @test(<2 x double> %d2)  {
+entry:
+  %call20.i = tail call <4 x float> @cmp(<2 x double> %d2,
+                                        <2 x double> bitcast (
+                                          <4 x float> shufflevector (
+                                            <3 x float> shufflevector (
+                                              <4 x float> shufflevector (
+                                                <3 x float> bitcast (
+                                                  i96 trunc (
+                                                    i128 bitcast (<2 x double> bitcast (
+                                                      <4 x i32> <i32 0, i32 0, i32 0, i32 undef> to <2 x double>)
+                                                    to i128) to i96)
+                                                  to <3 x float>),
+                                                <3 x float> undef,
+                                                <4 x i32> <i32 0, i32 1, i32 2, i32 undef>),
+                                              <4 x float> undef,
+                                            <3 x i32> <i32 0, i32 1, i32 2>),
+                                            <3 x float> undef,
+                                            <4 x i32> <i32 0, i32 1, i32 2, i32 undef>)
+                                          to <2 x double>))
+  ret <4 x float> %call20.i
+}
+
+declare <4 x float> @cmp(<2 x double>, <2 x double>)



From eli.friedman at gmail.com  Tue Oct 25 19:36:41 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 26 Oct 2011 00:36:41 -0000
Subject: [llvm-commits] [llvm] r142994 - /llvm/trunk/docs/LangRef.html
Message-ID: <20111026003641.72FC8312800A@llvm.org>

Author: efriedma
Date: Tue Oct 25 19:36:41 2011
New Revision: 142994

URL: http://llvm.org/viewvc/llvm-project?rev=142994&view=rev
Log:
Remove dead atomic intrinsics from LangRef.


Modified:
    llvm/trunk/docs/LangRef.html

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=142994&r1=142993&r2=142994&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Tue Oct 25 19:36:41 2011
@@ -281,23 +281,6 @@
           <li><a href="#int_at">'<tt>llvm.adjust.trampoline</tt>' Intrinsic</a></li>
         </ol>
       </li>
-      <li><a href="#int_atomics">Atomic intrinsics</a>
-        <ol>
-          <li><a href="#int_memory_barrier"><tt>llvm.memory_barrier</tt></a></li>
-          <li><a href="#int_atomic_cmp_swap"><tt>llvm.atomic.cmp.swap</tt></a></li>
-          <li><a href="#int_atomic_swap"><tt>llvm.atomic.swap</tt></a></li>
-          <li><a href="#int_atomic_load_add"><tt>llvm.atomic.load.add</tt></a></li>
-          <li><a href="#int_atomic_load_sub"><tt>llvm.atomic.load.sub</tt></a></li>
-          <li><a href="#int_atomic_load_and"><tt>llvm.atomic.load.and</tt></a></li>
-          <li><a href="#int_atomic_load_nand"><tt>llvm.atomic.load.nand</tt></a></li>
-          <li><a href="#int_atomic_load_or"><tt>llvm.atomic.load.or</tt></a></li>
-          <li><a href="#int_atomic_load_xor"><tt>llvm.atomic.load.xor</tt></a></li>
-          <li><a href="#int_atomic_load_max"><tt>llvm.atomic.load.max</tt></a></li>
-          <li><a href="#int_atomic_load_min"><tt>llvm.atomic.load.min</tt></a></li>
-          <li><a href="#int_atomic_load_umax"><tt>llvm.atomic.load.umax</tt></a></li>
-          <li><a href="#int_atomic_load_umin"><tt>llvm.atomic.load.umin</tt></a></li>
-        </ol>
-      </li>
       <li><a href="#int_memorymarkers">Memory Use Markers</a>
         <ol>
           <li><a href="#int_lifetime_start"><tt>llvm.lifetime.start</tt></a></li>
@@ -7812,503 +7795,6 @@
 
 <!-- ======================================================================= -->
 <h3>
-  <a name="int_atomics">Atomic Operations and Synchronization Intrinsics</a>
-</h3>
-
-<div>
-
-<p>These intrinsic functions expand the "universal IR" of LLVM to represent
-   hardware constructs for atomic operations and memory synchronization.  This
-   provides an interface to the hardware, not an interface to the programmer. It
-   is aimed at a low enough level to allow any programming models or APIs
-   (Application Programming Interfaces) which need atomic behaviors to map
-   cleanly onto it. It is also modeled primarily on hardware behavior. Just as
-   hardware provides a "universal IR" for source languages, it also provides a
-   starting point for developing a "universal" atomic operation and
-   synchronization IR.</p>
-
-<p>These do <em>not</em> form an API such as high-level threading libraries,
-   software transaction memory systems, atomic primitives, and intrinsic
-   functions as found in BSD, GNU libc, atomic_ops, APR, and other system and
-   application libraries.  The hardware interface provided by LLVM should allow
-   a clean implementation of all of these APIs and parallel programming models.
-   No one model or paradigm should be selected above others unless the hardware
-   itself ubiquitously does so.</p>
-
-<!-- _______________________________________________________________________ -->
-<h4>
-  <a name="int_memory_barrier">'<tt>llvm.memory.barrier</tt>' Intrinsic</a>
-</h4>
-
-<div>
-<h5>Syntax:</h5>
-<pre>
-  declare void @llvm.memory.barrier(i1 &lt;ll&gt;, i1 &lt;ls&gt;, i1 &lt;sl&gt;, i1 &lt;ss&gt;, i1 &lt;device&gt;)
-</pre>
-
-<h5>Overview:</h5>
-<p>The <tt>llvm.memory.barrier</tt> intrinsic guarantees ordering between
-   specific pairs of memory access types.</p>
-
-<h5>Arguments:</h5>
-<p>The <tt>llvm.memory.barrier</tt> intrinsic requires five boolean arguments.
-   The first four arguments enables a specific barrier as listed below.  The
-   fifth argument specifies that the barrier applies to io or device or uncached
-   memory.</p>
-
-<ul>
-  <li><tt>ll</tt>: load-load barrier</li>
-  <li><tt>ls</tt>: load-store barrier</li>
-  <li><tt>sl</tt>: store-load barrier</li>
-  <li><tt>ss</tt>: store-store barrier</li>
-  <li><tt>device</tt>: barrier applies to device and uncached memory also.</li>
-</ul>
-
-<h5>Semantics:</h5>
-<p>This intrinsic causes the system to enforce some ordering constraints upon
-   the loads and stores of the program. This barrier does not
-   indicate <em>when</em> any events will occur, it only enforces
-   an <em>order</em> in which they occur. For any of the specified pairs of load
-   and store operations (f.ex.  load-load, or store-load), all of the first
-   operations preceding the barrier will complete before any of the second
-   operations succeeding the barrier begin. Specifically the semantics for each
-   pairing is as follows:</p>
-
-<ul>
-  <li><tt>ll</tt>: All loads before the barrier must complete before any load
-      after the barrier begins.</li>
-  <li><tt>ls</tt>: All loads before the barrier must complete before any
-      store after the barrier begins.</li>
-  <li><tt>ss</tt>: All stores before the barrier must complete before any
-      store after the barrier begins.</li>
-  <li><tt>sl</tt>: All stores before the barrier must complete before any
-      load after the barrier begins.</li>
-</ul>
-
-<p>These semantics are applied with a logical "and" behavior when more than one
-   is enabled in a single memory barrier intrinsic.</p>
-
-<p>Backends may implement stronger barriers than those requested when they do
-   not support as fine grained a barrier as requested.  Some architectures do
-   not need all types of barriers and on such architectures, these become
-   noops.</p>
-
-<h5>Example:</h5>
-<pre>
-%mallocP  = tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
-%ptr      = bitcast i8* %mallocP to i32*
-            store i32 4, %ptr
-
-%result1  = load i32* %ptr      <i>; yields {i32}:result1 = 4</i>
-            call void @llvm.memory.barrier(i1 false, i1 true, i1 false, i1 false, i1 true)
-                                <i>; guarantee the above finishes</i>
-            store i32 8, %ptr   <i>; before this begins</i>
-</pre>
-
-</div>
-
-<!-- _______________________________________________________________________ -->
-<h4>
-  <a name="int_atomic_cmp_swap">'<tt>llvm.atomic.cmp.swap.*</tt>' Intrinsic</a>
-</h4>
-
-<div>
-
-<h5>Syntax:</h5>
-<p>This is an overloaded intrinsic. You can use <tt>llvm.atomic.cmp.swap</tt> on
-   any integer bit width and for different address spaces. Not all targets
-   support all bit widths however.</p>
-
-<pre>
-  declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;cmp&gt;, i8 &lt;val&gt;)
-  declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;cmp&gt;, i16 &lt;val&gt;)
-  declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;cmp&gt;, i32 &lt;val&gt;)
-  declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;cmp&gt;, i64 &lt;val&gt;)
-</pre>
-
-<h5>Overview:</h5>
-<p>This loads a value in memory and compares it to a given value. If they are
-   equal, it stores a new value into the memory.</p>
-
-<h5>Arguments:</h5>
-<p>The <tt>llvm.atomic.cmp.swap</tt> intrinsic takes three arguments. The result
-   as well as both <tt>cmp</tt> and <tt>val</tt> must be integer values with the
-   same bit width. The <tt>ptr</tt> argument must be a pointer to a value of
-   this integer type. While any bit width integer may be used, targets may only
-   lower representations they support in hardware.</p>
-
-<h5>Semantics:</h5>
-<p>This entire intrinsic must be executed atomically. It first loads the value
-   in memory pointed to by <tt>ptr</tt> and compares it with the
-   value <tt>cmp</tt>. If they are equal, <tt>val</tt> is stored into the
-   memory. The loaded value is yielded in all cases. This provides the
-   equivalent of an atomic compare-and-swap operation within the SSA
-   framework.</p>
-
-<h5>Examples:</h5>
-<pre>
-%mallocP  = tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
-%ptr      = bitcast i8* %mallocP to i32*
-            store i32 4, %ptr
-
-%val1     = add i32 4, 4
-%result1  = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %ptr, i32 4, %val1)
-                                          <i>; yields {i32}:result1 = 4</i>
-%stored1  = icmp eq i32 %result1, 4       <i>; yields {i1}:stored1 = true</i>
-%memval1  = load i32* %ptr                <i>; yields {i32}:memval1 = 8</i>
-
-%val2     = add i32 1, 1
-%result2  = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %ptr, i32 5, %val2)
-                                          <i>; yields {i32}:result2 = 8</i>
-%stored2  = icmp eq i32 %result2, 5       <i>; yields {i1}:stored2 = false</i>
-
-%memval2  = load i32* %ptr                <i>; yields {i32}:memval2 = 8</i>
-</pre>
-
-</div>
-
-<!-- _______________________________________________________________________ -->
-<h4>
-  <a name="int_atomic_swap">'<tt>llvm.atomic.swap.*</tt>' Intrinsic</a>
-</h4>
-
-<div>
-<h5>Syntax:</h5>
-
-<p>This is an overloaded intrinsic. You can use <tt>llvm.atomic.swap</tt> on any
-   integer bit width. Not all targets support all bit widths however.</p>
-
-<pre>
-  declare i8 @llvm.atomic.swap.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;val&gt;)
-  declare i16 @llvm.atomic.swap.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;val&gt;)
-  declare i32 @llvm.atomic.swap.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;val&gt;)
-  declare i64 @llvm.atomic.swap.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;val&gt;)
-</pre>
-
-<h5>Overview:</h5>
-<p>This intrinsic loads the value stored in memory at <tt>ptr</tt> and yields
-   the value from memory. It then stores the value in <tt>val</tt> in the memory
-   at <tt>ptr</tt>.</p>
-
-<h5>Arguments:</h5>
-<p>The <tt>llvm.atomic.swap</tt> intrinsic takes two arguments. Both
-  the <tt>val</tt> argument and the result must be integers of the same bit
-  width.  The first argument, <tt>ptr</tt>, must be a pointer to a value of this
-  integer type. The targets may only lower integer representations they
-  support.</p>
-
-<h5>Semantics:</h5>
-<p>This intrinsic loads the value pointed to by <tt>ptr</tt>, yields it, and
-   stores <tt>val</tt> back into <tt>ptr</tt> atomically. This provides the
-   equivalent of an atomic swap operation within the SSA framework.</p>
-
-<h5>Examples:</h5>
-<pre>
-%mallocP  = tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
-%ptr      = bitcast i8* %mallocP to i32*
-            store i32 4, %ptr
-
-%val1     = add i32 4, 4
-%result1  = call i32 @llvm.atomic.swap.i32.p0i32(i32* %ptr, i32 %val1)
-                                        <i>; yields {i32}:result1 = 4</i>
-%stored1  = icmp eq i32 %result1, 4     <i>; yields {i1}:stored1 = true</i>
-%memval1  = load i32* %ptr              <i>; yields {i32}:memval1 = 8</i>
-
-%val2     = add i32 1, 1
-%result2  = call i32 @llvm.atomic.swap.i32.p0i32(i32* %ptr, i32 %val2)
-                                        <i>; yields {i32}:result2 = 8</i>
-
-%stored2  = icmp eq i32 %result2, 8     <i>; yields {i1}:stored2 = true</i>
-%memval2  = load i32* %ptr              <i>; yields {i32}:memval2 = 2</i>
-</pre>
-
-</div>
-
-<!-- _______________________________________________________________________ -->
-<h4>
-  <a name="int_atomic_load_add">'<tt>llvm.atomic.load.add.*</tt>' Intrinsic</a>
-</h4>
-
-<div>
-
-<h5>Syntax:</h5>
-<p>This is an overloaded intrinsic. You can use <tt>llvm.atomic.load.add</tt> on
-   any integer bit width. Not all targets support all bit widths however.</p>
-
-<pre>
-  declare i8 @llvm.atomic.load.add.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
-  declare i16 @llvm.atomic.load.add.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
-  declare i32 @llvm.atomic.load.add.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
-  declare i64 @llvm.atomic.load.add.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
-</pre>
-
-<h5>Overview:</h5>
-<p>This intrinsic adds <tt>delta</tt> to the value stored in memory
-   at <tt>ptr</tt>. It yields the original value at <tt>ptr</tt>.</p>
-
-<h5>Arguments:</h5>
-<p>The intrinsic takes two arguments, the first a pointer to an integer value
-   and the second an integer value. The result is also an integer value. These
-   integer types can have any bit width, but they must all have the same bit
-   width. The targets may only lower integer representations they support.</p>
-
-<h5>Semantics:</h5>
-<p>This intrinsic does a series of operations atomically. It first loads the
-   value stored at <tt>ptr</tt>. It then adds <tt>delta</tt>, stores the result
-   to <tt>ptr</tt>. It yields the original value stored at <tt>ptr</tt>.</p>
-
-<h5>Examples:</h5>
-<pre>
-%mallocP  = tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
-%ptr      = bitcast i8* %mallocP to i32*
-            store i32 4, %ptr
-%result1  = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %ptr, i32 4)
-                                <i>; yields {i32}:result1 = 4</i>
-%result2  = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %ptr, i32 2)
-                                <i>; yields {i32}:result2 = 8</i>
-%result3  = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %ptr, i32 5)
-                                <i>; yields {i32}:result3 = 10</i>
-%memval1  = load i32* %ptr      <i>; yields {i32}:memval1 = 15</i>
-</pre>
-
-</div>
-
-<!-- _______________________________________________________________________ -->
-<h4>
-  <a name="int_atomic_load_sub">'<tt>llvm.atomic.load.sub.*</tt>' Intrinsic</a>
-</h4>
-
-<div>
-
-<h5>Syntax:</h5>
-<p>This is an overloaded intrinsic. You can use <tt>llvm.atomic.load.sub</tt> on
-   any integer bit width and for different address spaces. Not all targets
-   support all bit widths however.</p>
-
-<pre>
-  declare i8 @llvm.atomic.load.sub.i8.p0i32(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
-  declare i16 @llvm.atomic.load.sub.i16.p0i32(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
-  declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
-  declare i64 @llvm.atomic.load.sub.i64.p0i32(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
-</pre>
-
-<h5>Overview:</h5>
-<p>This intrinsic subtracts <tt>delta</tt> to the value stored in memory at
-   <tt>ptr</tt>. It yields the original value at <tt>ptr</tt>.</p>
-
-<h5>Arguments:</h5>
-<p>The intrinsic takes two arguments, the first a pointer to an integer value
-   and the second an integer value. The result is also an integer value. These
-   integer types can have any bit width, but they must all have the same bit
-   width. The targets may only lower integer representations they support.</p>
-
-<h5>Semantics:</h5>
-<p>This intrinsic does a series of operations atomically. It first loads the
-   value stored at <tt>ptr</tt>. It then subtracts <tt>delta</tt>, stores the
-   result to <tt>ptr</tt>. It yields the original value stored
-   at <tt>ptr</tt>.</p>
-
-<h5>Examples:</h5>
-<pre>
-%mallocP  = tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
-%ptr      = bitcast i8* %mallocP to i32*
-            store i32 8, %ptr
-%result1  = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %ptr, i32 4)
-                                <i>; yields {i32}:result1 = 8</i>
-%result2  = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %ptr, i32 2)
-                                <i>; yields {i32}:result2 = 4</i>
-%result3  = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %ptr, i32 5)
-                                <i>; yields {i32}:result3 = 2</i>
-%memval1  = load i32* %ptr      <i>; yields {i32}:memval1 = -3</i>
-</pre>
-
-</div>
-
-<!-- _______________________________________________________________________ -->
-<h4>
-  <a name="int_atomic_load_and">
-    '<tt>llvm.atomic.load.and.*</tt>' Intrinsic
-  </a>
-  <br>
-  <a name="int_atomic_load_nand">
-    '<tt>llvm.atomic.load.nand.*</tt>' Intrinsic
-  </a>
-  <br>
-  <a name="int_atomic_load_or">
-    '<tt>llvm.atomic.load.or.*</tt>' Intrinsic
-  </a>
-  <br>
-  <a name="int_atomic_load_xor">
-    '<tt>llvm.atomic.load.xor.*</tt>' Intrinsic
-  </a>
-</h4>
-
-<div>
-
-<h5>Syntax:</h5>
-<p>These are overloaded intrinsics. You can
-  use <tt>llvm.atomic.load_and</tt>, <tt>llvm.atomic.load_nand</tt>,
-  <tt>llvm.atomic.load_or</tt>, and <tt>llvm.atomic.load_xor</tt> on any integer
-  bit width and for different address spaces. Not all targets support all bit
-  widths however.</p>
-
-<pre>
-  declare i8 @llvm.atomic.load.and.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
-  declare i16 @llvm.atomic.load.and.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
-  declare i32 @llvm.atomic.load.and.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
-  declare i64 @llvm.atomic.load.and.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
-</pre>
-
-<pre>
-  declare i8 @llvm.atomic.load.or.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
-  declare i16 @llvm.atomic.load.or.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
-  declare i32 @llvm.atomic.load.or.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
-  declare i64 @llvm.atomic.load.or.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
-</pre>
-
-<pre>
-  declare i8 @llvm.atomic.load.nand.i8.p0i32(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
-  declare i16 @llvm.atomic.load.nand.i16.p0i32(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
-  declare i32 @llvm.atomic.load.nand.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
-  declare i64 @llvm.atomic.load.nand.i64.p0i32(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
-</pre>
-
-<pre>
-  declare i8 @llvm.atomic.load.xor.i8.p0i32(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
-  declare i16 @llvm.atomic.load.xor.i16.p0i32(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
-  declare i32 @llvm.atomic.load.xor.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
-  declare i64 @llvm.atomic.load.xor.i64.p0i32(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
-</pre>
-
-<h5>Overview:</h5>
-<p>These intrinsics bitwise the operation (and, nand, or, xor) <tt>delta</tt> to
-   the value stored in memory at <tt>ptr</tt>. It yields the original value
-   at <tt>ptr</tt>.</p>
-
-<h5>Arguments:</h5>
-<p>These intrinsics take two arguments, the first a pointer to an integer value
-   and the second an integer value. The result is also an integer value. These
-   integer types can have any bit width, but they must all have the same bit
-   width. The targets may only lower integer representations they support.</p>
-
-<h5>Semantics:</h5>
-<p>These intrinsics does a series of operations atomically. They first load the
-   value stored at <tt>ptr</tt>. They then do the bitwise
-   operation <tt>delta</tt>, store the result to <tt>ptr</tt>. They yield the
-   original value stored at <tt>ptr</tt>.</p>
-
-<h5>Examples:</h5>
-<pre>
-%mallocP  = tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
-%ptr      = bitcast i8* %mallocP to i32*
-            store i32 0x0F0F, %ptr
-%result0  = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %ptr, i32 0xFF)
-                                <i>; yields {i32}:result0 = 0x0F0F</i>
-%result1  = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %ptr, i32 0xFF)
-                                <i>; yields {i32}:result1 = 0xFFFFFFF0</i>
-%result2  = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %ptr, i32 0F)
-                                <i>; yields {i32}:result2 = 0xF0</i>
-%result3  = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %ptr, i32 0F)
-                                <i>; yields {i32}:result3 = FF</i>
-%memval1  = load i32* %ptr      <i>; yields {i32}:memval1 = F0</i>
-</pre>
-
-</div>
-
-<!-- _______________________________________________________________________ -->
-<h4>
-  <a name="int_atomic_load_max">
-    '<tt>llvm.atomic.load.max.*</tt>' Intrinsic
-  </a>
-  <br>
-  <a name="int_atomic_load_min">
-    '<tt>llvm.atomic.load.min.*</tt>' Intrinsic
-  </a>
-  <br>
-  <a name="int_atomic_load_umax">
-    '<tt>llvm.atomic.load.umax.*</tt>' Intrinsic
-  </a>
-  <br>
-  <a name="int_atomic_load_umin">
-    '<tt>llvm.atomic.load.umin.*</tt>' Intrinsic
-  </a>
-</h4>
-
-<div>
-
-<h5>Syntax:</h5>
-<p>These are overloaded intrinsics. You can use <tt>llvm.atomic.load_max</tt>,
-   <tt>llvm.atomic.load_min</tt>, <tt>llvm.atomic.load_umax</tt>, and
-   <tt>llvm.atomic.load_umin</tt> on any integer bit width and for different
-   address spaces. Not all targets support all bit widths however.</p>
-
-<pre>
-  declare i8 @llvm.atomic.load.max.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
-  declare i16 @llvm.atomic.load.max.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
-  declare i32 @llvm.atomic.load.max.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
-  declare i64 @llvm.atomic.load.max.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
-</pre>
-
-<pre>
-  declare i8 @llvm.atomic.load.min.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
-  declare i16 @llvm.atomic.load.min.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
-  declare i32 @llvm.atomic.load.min.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
-  declare i64 @llvm.atomic.load.min.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
-</pre>
-
-<pre>
-  declare i8 @llvm.atomic.load.umax.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
-  declare i16 @llvm.atomic.load.umax.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
-  declare i32 @llvm.atomic.load.umax.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
-  declare i64 @llvm.atomic.load.umax.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
-</pre>
-
-<pre>
-  declare i8 @llvm.atomic.load.umin.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
-  declare i16 @llvm.atomic.load.umin.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
-  declare i32 @llvm.atomic.load.umin.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
-  declare i64 @llvm.atomic.load.umin.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
-</pre>
-
-<h5>Overview:</h5>
-<p>These intrinsics takes the signed or unsigned minimum or maximum of
-   <tt>delta</tt> and the value stored in memory at <tt>ptr</tt>. It yields the
-   original value at <tt>ptr</tt>.</p>
-
-<h5>Arguments:</h5>
-<p>These intrinsics take two arguments, the first a pointer to an integer value
-   and the second an integer value. The result is also an integer value. These
-   integer types can have any bit width, but they must all have the same bit
-   width. The targets may only lower integer representations they support.</p>
-
-<h5>Semantics:</h5>
-<p>These intrinsics does a series of operations atomically. They first load the
-   value stored at <tt>ptr</tt>. They then do the signed or unsigned min or
-   max <tt>delta</tt> and the value, store the result to <tt>ptr</tt>. They
-   yield the original value stored at <tt>ptr</tt>.</p>
-
-<h5>Examples:</h5>
-<pre>
-%mallocP  = tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
-%ptr      = bitcast i8* %mallocP to i32*
-            store i32 7, %ptr
-%result0  = call i32 @llvm.atomic.load.min.i32.p0i32(i32* %ptr, i32 -2)
-                                <i>; yields {i32}:result0 = 7</i>
-%result1  = call i32 @llvm.atomic.load.max.i32.p0i32(i32* %ptr, i32 8)
-                                <i>; yields {i32}:result1 = -2</i>
-%result2  = call i32 @llvm.atomic.load.umin.i32.p0i32(i32* %ptr, i32 10)
-                                <i>; yields {i32}:result2 = 8</i>
-%result3  = call i32 @llvm.atomic.load.umax.i32.p0i32(i32* %ptr, i32 30)
-                                <i>; yields {i32}:result3 = 8</i>
-%memval1  = load i32* %ptr      <i>; yields {i32}:memval1 = 30</i>
-</pre>
-
-</div>
-
-</div>
-
-<!-- ======================================================================= -->
-<h3>
   <a name="int_memorymarkers">Memory Use Markers</a>
 </h3>
 



From echristo at apple.com  Tue Oct 25 19:42:12 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 26 Oct 2011 00:42:12 -0000
Subject: [llvm-commits] [llvm] r142995 - in /llvm/trunk: autoconf/ltmain.sh
 autoconf/m4/libtool.m4 configure include/llvm/Config/config.h.in
 projects/sample/autoconf/ltmain.sh projects/sample/autoconf/m4/libtool.m4
Message-ID: <20111026004213.0DB0D312800A@llvm.org>

Author: echristo
Date: Tue Oct 25 19:42:12 2011
New Revision: 142995

URL: http://llvm.org/viewvc/llvm-project?rev=142995&view=rev
Log:
Handle newer cases for freebsd which is approaching 10.0 and not 1.0.

Patch by Dimitry Andric!

Modified:
    llvm/trunk/autoconf/ltmain.sh
    llvm/trunk/autoconf/m4/libtool.m4
    llvm/trunk/configure
    llvm/trunk/include/llvm/Config/config.h.in
    llvm/trunk/projects/sample/autoconf/ltmain.sh
    llvm/trunk/projects/sample/autoconf/m4/libtool.m4

Modified: llvm/trunk/autoconf/ltmain.sh
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/ltmain.sh?rev=142995&r1=142994&r2=142995&view=diff
==============================================================================
Binary files - no diff available.

Modified: llvm/trunk/autoconf/m4/libtool.m4
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/m4/libtool.m4?rev=142995&r1=142994&r2=142995&view=diff
==============================================================================
--- llvm/trunk/autoconf/m4/libtool.m4 (original)
+++ llvm/trunk/autoconf/m4/libtool.m4 Tue Oct 25 19:42:12 2011
@@ -1384,7 +1384,7 @@
   shlibpath_var=LD_LIBRARY_PATH
   ;;
 
-freebsd1*)
+freebsd1.*)
   dynamic_linker=no
   ;;
 
@@ -1407,7 +1407,7 @@
     objformat=`/usr/bin/objformat`
   else
     case $host_os in
-    freebsd[[123]]*) objformat=aout ;;
+    freebsd[[123]].*) objformat=aout ;;
     *) objformat=elf ;;
     esac
   fi
@@ -1425,7 +1425,7 @@
   esac
   shlibpath_var=LD_LIBRARY_PATH
   case $host_os in
-  freebsd2*)
+  freebsd2.*)
     shlibpath_overrides_runpath=yes
     ;;
   freebsd3.[[01]]* | freebsdelf3.[[01]]*)
@@ -3099,7 +3099,7 @@
 	;;
     esac
     ;;
-  freebsd[[12]]*)
+  freebsd[[12]].*)
     # C++ shared libraries reported to be fairly broken before switch to ELF
     _LT_AC_TAGVAR(ld_shlibs, $1)=no
     ;;
@@ -5858,7 +5858,7 @@
       _LT_AC_TAGVAR(hardcode_shlibpath_var, $1)=no
       ;;
 
-    freebsd1*)
+    freebsd1.*)
       _LT_AC_TAGVAR(ld_shlibs, $1)=no
       ;;
 
@@ -5874,7 +5874,7 @@
       ;;
 
     # Unfortunately, older versions of FreeBSD 2 do not have this feature.
-    freebsd2*)
+    freebsd2.*)
       _LT_AC_TAGVAR(archive_cmds, $1)='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
       _LT_AC_TAGVAR(hardcode_direct, $1)=yes
       _LT_AC_TAGVAR(hardcode_minus_L, $1)=yes

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=142995&r1=142994&r2=142995&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Tue Oct 25 19:42:12 2011
@@ -1416,8 +1416,7 @@
   --enable-targets        Build specific host targets: all or
                           target1,target2,... Valid targets are: host, x86,
                           x86_64, sparc, powerpc, alpha, arm, mips, spu,
-                          xcore, msp430, ptx, cbe, and cpp
-                          (default=all)
+                          xcore, msp430, ptx, cbe, and cpp (default=all)
   --enable-cbe-printf-a   Enable C Backend output with hex floating point via
                           %a (default is YES)
   --enable-bindings       Build specific language bindings:
@@ -8906,7 +8905,7 @@
   shlibpath_var=LD_LIBRARY_PATH
   ;;
 
-freebsd1*)
+freebsd1.*)
   dynamic_linker=no
   ;;
 
@@ -8929,7 +8928,7 @@
     objformat=`/usr/bin/objformat`
   else
     case $host_os in
-    freebsd[123]*) objformat=aout ;;
+    freebsd[123].*) objformat=aout ;;
     *) objformat=elf ;;
     esac
   fi
@@ -8947,7 +8946,7 @@
   esac
   shlibpath_var=LD_LIBRARY_PATH
   case $host_os in
-  freebsd2*)
+  freebsd2.*)
     shlibpath_overrides_runpath=yes
     ;;
   freebsd3.[01]* | freebsdelf3.[01]*)
@@ -10461,7 +10460,7 @@
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<EOF
-#line 10474 "configure"
+#line 10463 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -21060,6 +21059,7 @@
 
 ac_config_files="$ac_config_files Makefile.config"
 
+
 ac_config_files="$ac_config_files llvm.spec"
 
 
@@ -21072,8 +21072,10 @@
 
 ac_config_files="$ac_config_files tools/llvm-config/llvm-config.in"
 
+
 ac_config_files="$ac_config_files bindings/ocaml/llvm/META.llvm"
 
+
 ac_config_commands="$ac_config_commands setup"
 
 ac_config_commands="$ac_config_commands Makefile"
@@ -21691,6 +21693,7 @@
     "docs/doxygen.cfg") CONFIG_FILES="$CONFIG_FILES docs/doxygen.cfg" ;;
     "tools/clang/docs/doxygen.cfg") CONFIG_FILES="$CONFIG_FILES tools/clang/docs/doxygen.cfg" ;;
     "tools/llvm-config/llvm-config.in") CONFIG_FILES="$CONFIG_FILES tools/llvm-config/llvm-config.in" ;;
+    "bindings/ocaml/llvm/META.llvm") CONFIG_FILES="$CONFIG_FILES bindings/ocaml/llvm/META.llvm" ;;
     "setup") CONFIG_COMMANDS="$CONFIG_COMMANDS setup" ;;
     "Makefile") CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;;
     "Makefile.common") CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile.common" ;;

Modified: llvm/trunk/include/llvm/Config/config.h.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.in?rev=142995&r1=142994&r2=142995&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Config/config.h.in (original)
+++ llvm/trunk/include/llvm/Config/config.h.in Tue Oct 25 19:42:12 2011
@@ -666,6 +666,9 @@
 /* Define to 1 if the `S_IS*' macros in <sys/stat.h> do not work properly. */
 #undef STAT_MACROS_BROKEN
 
+/* Define to 1 if you have the ANSI C header files. */
+#undef STDC_HEADERS
+
 /* Define to 1 if you can safely include both <sys/time.h> and <time.h>. */
 #undef TIME_WITH_SYS_TIME
 

Modified: llvm/trunk/projects/sample/autoconf/ltmain.sh
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/autoconf/ltmain.sh?rev=142995&r1=142994&r2=142995&view=diff
==============================================================================
--- llvm/trunk/projects/sample/autoconf/ltmain.sh (original)
+++ llvm/trunk/projects/sample/autoconf/ltmain.sh Tue Oct 25 19:42:12 2011
@@ -4668,7 +4668,7 @@
 	  # linked before any other PIC object.  But we must not use
 	  # pic_flag when linking with -static.  The problem exists in
 	  # FreeBSD 2.2.6 and is fixed in FreeBSD 3.1.
-	  *-*-freebsd2*|*-*-freebsd3.0*|*-*-freebsdelf3.0*)
+	  *-*-freebsd2.*|*-*-freebsd3.0*|*-*-freebsdelf3.0*)
 	    case "$compile_command " in
 	    *" -static "*) ;;
 	    *) pic_flag_for_symtable=" $pic_flag -DFREEBSD_WORKAROUND";;

Modified: llvm/trunk/projects/sample/autoconf/m4/libtool.m4
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/autoconf/m4/libtool.m4?rev=142995&r1=142994&r2=142995&view=diff
==============================================================================
--- llvm/trunk/projects/sample/autoconf/m4/libtool.m4 (original)
+++ llvm/trunk/projects/sample/autoconf/m4/libtool.m4 Tue Oct 25 19:42:12 2011
@@ -1384,7 +1384,7 @@
   shlibpath_var=LD_LIBRARY_PATH
   ;;
 
-freebsd1*)
+freebsd1.*)
   dynamic_linker=no
   ;;
 
@@ -1407,7 +1407,7 @@
     objformat=`/usr/bin/objformat`
   else
     case $host_os in
-    freebsd[[123]]*) objformat=aout ;;
+    freebsd[[123]].*) objformat=aout ;;
     *) objformat=elf ;;
     esac
   fi
@@ -1425,7 +1425,7 @@
   esac
   shlibpath_var=LD_LIBRARY_PATH
   case $host_os in
-  freebsd2*)
+  freebsd2.*)
     shlibpath_overrides_runpath=yes
     ;;
   freebsd3.[[01]]* | freebsdelf3.[[01]]*)
@@ -3099,7 +3099,7 @@
 	;;
     esac
     ;;
-  freebsd[[12]]*)
+  freebsd[[12]].*)
     # C++ shared libraries reported to be fairly broken before switch to ELF
     _LT_AC_TAGVAR(ld_shlibs, $1)=no
     ;;
@@ -5858,7 +5858,7 @@
       _LT_AC_TAGVAR(hardcode_shlibpath_var, $1)=no
       ;;
 
-    freebsd1*)
+    freebsd1.*)
       _LT_AC_TAGVAR(ld_shlibs, $1)=no
       ;;
 
@@ -5874,7 +5874,7 @@
       ;;
 
     # Unfortunately, older versions of FreeBSD 2 do not have this feature.
-    freebsd2*)
+    freebsd2.*)
       _LT_AC_TAGVAR(archive_cmds, $1)='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
       _LT_AC_TAGVAR(hardcode_direct, $1)=yes
       _LT_AC_TAGVAR(hardcode_minus_L, $1)=yes



From eli.friedman at gmail.com  Tue Oct 25 19:48:42 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 25 Oct 2011 17:48:42 -0700
Subject: [llvm-commits] [llvm] r142994 - /llvm/trunk/docs/LangRef.html
In-Reply-To: <20111026003641.72FC8312800A@llvm.org>
References: <20111026003641.72FC8312800A@llvm.org>
Message-ID: <CAJdarcFnGu=sTQOETBDz5_MyyxPQxCWFRSEi8SgT_TyP7uqZnA@mail.gmail.com>

On Tue, Oct 25, 2011 at 5:36 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> Author: efriedma
> Date: Tue Oct 25 19:36:41 2011
> New Revision: 142994
>
> URL: http://llvm.org/viewvc/llvm-project?rev=142994&view=rev
> Log:
> Remove dead atomic intrinsics from LangRef.

Bill, please take this for the 3.0 branch (the underlying change went
in before the branch).

-Eli

>
> Modified:
> ? ?llvm/trunk/docs/LangRef.html
>
> Modified: llvm/trunk/docs/LangRef.html
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=142994&r1=142993&r2=142994&view=diff
> ==============================================================================
> --- llvm/trunk/docs/LangRef.html (original)
> +++ llvm/trunk/docs/LangRef.html Tue Oct 25 19:36:41 2011
> @@ -281,23 +281,6 @@
> ? ? ? ? ? <li><a href="#int_at">'<tt>llvm.adjust.trampoline</tt>' Intrinsic</a></li>
> ? ? ? ? </ol>
> ? ? ? </li>
> - ? ? ?<li><a href="#int_atomics">Atomic intrinsics</a>
> - ? ? ? ?<ol>
> - ? ? ? ? ?<li><a href="#int_memory_barrier"><tt>llvm.memory_barrier</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_cmp_swap"><tt>llvm.atomic.cmp.swap</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_swap"><tt>llvm.atomic.swap</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_load_add"><tt>llvm.atomic.load.add</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_load_sub"><tt>llvm.atomic.load.sub</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_load_and"><tt>llvm.atomic.load.and</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_load_nand"><tt>llvm.atomic.load.nand</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_load_or"><tt>llvm.atomic.load.or</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_load_xor"><tt>llvm.atomic.load.xor</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_load_max"><tt>llvm.atomic.load.max</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_load_min"><tt>llvm.atomic.load.min</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_load_umax"><tt>llvm.atomic.load.umax</tt></a></li>
> - ? ? ? ? ?<li><a href="#int_atomic_load_umin"><tt>llvm.atomic.load.umin</tt></a></li>
> - ? ? ? ?</ol>
> - ? ? ?</li>
> ? ? ? <li><a href="#int_memorymarkers">Memory Use Markers</a>
> ? ? ? ? <ol>
> ? ? ? ? ? <li><a href="#int_lifetime_start"><tt>llvm.lifetime.start</tt></a></li>
> @@ -7812,503 +7795,6 @@
>
> ?<!-- ======================================================================= -->
> ?<h3>
> - ?<a name="int_atomics">Atomic Operations and Synchronization Intrinsics</a>
> -</h3>
> -
> -<div>
> -
> -<p>These intrinsic functions expand the "universal IR" of LLVM to represent
> - ? hardware constructs for atomic operations and memory synchronization. ?This
> - ? provides an interface to the hardware, not an interface to the programmer. It
> - ? is aimed at a low enough level to allow any programming models or APIs
> - ? (Application Programming Interfaces) which need atomic behaviors to map
> - ? cleanly onto it. It is also modeled primarily on hardware behavior. Just as
> - ? hardware provides a "universal IR" for source languages, it also provides a
> - ? starting point for developing a "universal" atomic operation and
> - ? synchronization IR.</p>
> -
> -<p>These do <em>not</em> form an API such as high-level threading libraries,
> - ? software transaction memory systems, atomic primitives, and intrinsic
> - ? functions as found in BSD, GNU libc, atomic_ops, APR, and other system and
> - ? application libraries. ?The hardware interface provided by LLVM should allow
> - ? a clean implementation of all of these APIs and parallel programming models.
> - ? No one model or paradigm should be selected above others unless the hardware
> - ? itself ubiquitously does so.</p>
> -
> -<!-- _______________________________________________________________________ -->
> -<h4>
> - ?<a name="int_memory_barrier">'<tt>llvm.memory.barrier</tt>' Intrinsic</a>
> -</h4>
> -
> -<div>
> -<h5>Syntax:</h5>
> -<pre>
> - ?declare void @llvm.memory.barrier(i1 &lt;ll&gt;, i1 &lt;ls&gt;, i1 &lt;sl&gt;, i1 &lt;ss&gt;, i1 &lt;device&gt;)
> -</pre>
> -
> -<h5>Overview:</h5>
> -<p>The <tt>llvm.memory.barrier</tt> intrinsic guarantees ordering between
> - ? specific pairs of memory access types.</p>
> -
> -<h5>Arguments:</h5>
> -<p>The <tt>llvm.memory.barrier</tt> intrinsic requires five boolean arguments.
> - ? The first four arguments enables a specific barrier as listed below. ?The
> - ? fifth argument specifies that the barrier applies to io or device or uncached
> - ? memory.</p>
> -
> -<ul>
> - ?<li><tt>ll</tt>: load-load barrier</li>
> - ?<li><tt>ls</tt>: load-store barrier</li>
> - ?<li><tt>sl</tt>: store-load barrier</li>
> - ?<li><tt>ss</tt>: store-store barrier</li>
> - ?<li><tt>device</tt>: barrier applies to device and uncached memory also.</li>
> -</ul>
> -
> -<h5>Semantics:</h5>
> -<p>This intrinsic causes the system to enforce some ordering constraints upon
> - ? the loads and stores of the program. This barrier does not
> - ? indicate <em>when</em> any events will occur, it only enforces
> - ? an <em>order</em> in which they occur. For any of the specified pairs of load
> - ? and store operations (f.ex. ?load-load, or store-load), all of the first
> - ? operations preceding the barrier will complete before any of the second
> - ? operations succeeding the barrier begin. Specifically the semantics for each
> - ? pairing is as follows:</p>
> -
> -<ul>
> - ?<li><tt>ll</tt>: All loads before the barrier must complete before any load
> - ? ? ?after the barrier begins.</li>
> - ?<li><tt>ls</tt>: All loads before the barrier must complete before any
> - ? ? ?store after the barrier begins.</li>
> - ?<li><tt>ss</tt>: All stores before the barrier must complete before any
> - ? ? ?store after the barrier begins.</li>
> - ?<li><tt>sl</tt>: All stores before the barrier must complete before any
> - ? ? ?load after the barrier begins.</li>
> -</ul>
> -
> -<p>These semantics are applied with a logical "and" behavior when more than one
> - ? is enabled in a single memory barrier intrinsic.</p>
> -
> -<p>Backends may implement stronger barriers than those requested when they do
> - ? not support as fine grained a barrier as requested. ?Some architectures do
> - ? not need all types of barriers and on such architectures, these become
> - ? noops.</p>
> -
> -<h5>Example:</h5>
> -<pre>
> -%mallocP ?= tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
> -%ptr ? ? ?= bitcast i8* %mallocP to i32*
> - ? ? ? ? ? ?store i32 4, %ptr
> -
> -%result1 ?= load i32* %ptr ? ? ?<i>; yields {i32}:result1 = 4</i>
> - ? ? ? ? ? ?call void @llvm.memory.barrier(i1 false, i1 true, i1 false, i1 false, i1 true)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; guarantee the above finishes</i>
> - ? ? ? ? ? ?store i32 8, %ptr ? <i>; before this begins</i>
> -</pre>
> -
> -</div>
> -
> -<!-- _______________________________________________________________________ -->
> -<h4>
> - ?<a name="int_atomic_cmp_swap">'<tt>llvm.atomic.cmp.swap.*</tt>' Intrinsic</a>
> -</h4>
> -
> -<div>
> -
> -<h5>Syntax:</h5>
> -<p>This is an overloaded intrinsic. You can use <tt>llvm.atomic.cmp.swap</tt> on
> - ? any integer bit width and for different address spaces. Not all targets
> - ? support all bit widths however.</p>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;cmp&gt;, i8 &lt;val&gt;)
> - ?declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;cmp&gt;, i16 &lt;val&gt;)
> - ?declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;cmp&gt;, i32 &lt;val&gt;)
> - ?declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;cmp&gt;, i64 &lt;val&gt;)
> -</pre>
> -
> -<h5>Overview:</h5>
> -<p>This loads a value in memory and compares it to a given value. If they are
> - ? equal, it stores a new value into the memory.</p>
> -
> -<h5>Arguments:</h5>
> -<p>The <tt>llvm.atomic.cmp.swap</tt> intrinsic takes three arguments. The result
> - ? as well as both <tt>cmp</tt> and <tt>val</tt> must be integer values with the
> - ? same bit width. The <tt>ptr</tt> argument must be a pointer to a value of
> - ? this integer type. While any bit width integer may be used, targets may only
> - ? lower representations they support in hardware.</p>
> -
> -<h5>Semantics:</h5>
> -<p>This entire intrinsic must be executed atomically. It first loads the value
> - ? in memory pointed to by <tt>ptr</tt> and compares it with the
> - ? value <tt>cmp</tt>. If they are equal, <tt>val</tt> is stored into the
> - ? memory. The loaded value is yielded in all cases. This provides the
> - ? equivalent of an atomic compare-and-swap operation within the SSA
> - ? framework.</p>
> -
> -<h5>Examples:</h5>
> -<pre>
> -%mallocP ?= tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
> -%ptr ? ? ?= bitcast i8* %mallocP to i32*
> - ? ? ? ? ? ?store i32 4, %ptr
> -
> -%val1 ? ? = add i32 4, 4
> -%result1 ?= call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %ptr, i32 4, %val1)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result1 = 4</i>
> -%stored1 ?= icmp eq i32 %result1, 4 ? ? ? <i>; yields {i1}:stored1 = true</i>
> -%memval1 ?= load i32* %ptr ? ? ? ? ? ? ? ?<i>; yields {i32}:memval1 = 8</i>
> -
> -%val2 ? ? = add i32 1, 1
> -%result2 ?= call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %ptr, i32 5, %val2)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result2 = 8</i>
> -%stored2 ?= icmp eq i32 %result2, 5 ? ? ? <i>; yields {i1}:stored2 = false</i>
> -
> -%memval2 ?= load i32* %ptr ? ? ? ? ? ? ? ?<i>; yields {i32}:memval2 = 8</i>
> -</pre>
> -
> -</div>
> -
> -<!-- _______________________________________________________________________ -->
> -<h4>
> - ?<a name="int_atomic_swap">'<tt>llvm.atomic.swap.*</tt>' Intrinsic</a>
> -</h4>
> -
> -<div>
> -<h5>Syntax:</h5>
> -
> -<p>This is an overloaded intrinsic. You can use <tt>llvm.atomic.swap</tt> on any
> - ? integer bit width. Not all targets support all bit widths however.</p>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.swap.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;val&gt;)
> - ?declare i16 @llvm.atomic.swap.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;val&gt;)
> - ?declare i32 @llvm.atomic.swap.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;val&gt;)
> - ?declare i64 @llvm.atomic.swap.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;val&gt;)
> -</pre>
> -
> -<h5>Overview:</h5>
> -<p>This intrinsic loads the value stored in memory at <tt>ptr</tt> and yields
> - ? the value from memory. It then stores the value in <tt>val</tt> in the memory
> - ? at <tt>ptr</tt>.</p>
> -
> -<h5>Arguments:</h5>
> -<p>The <tt>llvm.atomic.swap</tt> intrinsic takes two arguments. Both
> - ?the <tt>val</tt> argument and the result must be integers of the same bit
> - ?width. ?The first argument, <tt>ptr</tt>, must be a pointer to a value of this
> - ?integer type. The targets may only lower integer representations they
> - ?support.</p>
> -
> -<h5>Semantics:</h5>
> -<p>This intrinsic loads the value pointed to by <tt>ptr</tt>, yields it, and
> - ? stores <tt>val</tt> back into <tt>ptr</tt> atomically. This provides the
> - ? equivalent of an atomic swap operation within the SSA framework.</p>
> -
> -<h5>Examples:</h5>
> -<pre>
> -%mallocP ?= tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
> -%ptr ? ? ?= bitcast i8* %mallocP to i32*
> - ? ? ? ? ? ?store i32 4, %ptr
> -
> -%val1 ? ? = add i32 4, 4
> -%result1 ?= call i32 @llvm.atomic.swap.i32.p0i32(i32* %ptr, i32 %val1)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result1 = 4</i>
> -%stored1 ?= icmp eq i32 %result1, 4 ? ? <i>; yields {i1}:stored1 = true</i>
> -%memval1 ?= load i32* %ptr ? ? ? ? ? ? ?<i>; yields {i32}:memval1 = 8</i>
> -
> -%val2 ? ? = add i32 1, 1
> -%result2 ?= call i32 @llvm.atomic.swap.i32.p0i32(i32* %ptr, i32 %val2)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result2 = 8</i>
> -
> -%stored2 ?= icmp eq i32 %result2, 8 ? ? <i>; yields {i1}:stored2 = true</i>
> -%memval2 ?= load i32* %ptr ? ? ? ? ? ? ?<i>; yields {i32}:memval2 = 2</i>
> -</pre>
> -
> -</div>
> -
> -<!-- _______________________________________________________________________ -->
> -<h4>
> - ?<a name="int_atomic_load_add">'<tt>llvm.atomic.load.add.*</tt>' Intrinsic</a>
> -</h4>
> -
> -<div>
> -
> -<h5>Syntax:</h5>
> -<p>This is an overloaded intrinsic. You can use <tt>llvm.atomic.load.add</tt> on
> - ? any integer bit width. Not all targets support all bit widths however.</p>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.load.add.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
> - ?declare i16 @llvm.atomic.load.add.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
> - ?declare i32 @llvm.atomic.load.add.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
> - ?declare i64 @llvm.atomic.load.add.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
> -</pre>
> -
> -<h5>Overview:</h5>
> -<p>This intrinsic adds <tt>delta</tt> to the value stored in memory
> - ? at <tt>ptr</tt>. It yields the original value at <tt>ptr</tt>.</p>
> -
> -<h5>Arguments:</h5>
> -<p>The intrinsic takes two arguments, the first a pointer to an integer value
> - ? and the second an integer value. The result is also an integer value. These
> - ? integer types can have any bit width, but they must all have the same bit
> - ? width. The targets may only lower integer representations they support.</p>
> -
> -<h5>Semantics:</h5>
> -<p>This intrinsic does a series of operations atomically. It first loads the
> - ? value stored at <tt>ptr</tt>. It then adds <tt>delta</tt>, stores the result
> - ? to <tt>ptr</tt>. It yields the original value stored at <tt>ptr</tt>.</p>
> -
> -<h5>Examples:</h5>
> -<pre>
> -%mallocP ?= tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
> -%ptr ? ? ?= bitcast i8* %mallocP to i32*
> - ? ? ? ? ? ?store i32 4, %ptr
> -%result1 ?= call i32 @llvm.atomic.load.add.i32.p0i32(i32* %ptr, i32 4)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result1 = 4</i>
> -%result2 ?= call i32 @llvm.atomic.load.add.i32.p0i32(i32* %ptr, i32 2)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result2 = 8</i>
> -%result3 ?= call i32 @llvm.atomic.load.add.i32.p0i32(i32* %ptr, i32 5)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result3 = 10</i>
> -%memval1 ?= load i32* %ptr ? ? ?<i>; yields {i32}:memval1 = 15</i>
> -</pre>
> -
> -</div>
> -
> -<!-- _______________________________________________________________________ -->
> -<h4>
> - ?<a name="int_atomic_load_sub">'<tt>llvm.atomic.load.sub.*</tt>' Intrinsic</a>
> -</h4>
> -
> -<div>
> -
> -<h5>Syntax:</h5>
> -<p>This is an overloaded intrinsic. You can use <tt>llvm.atomic.load.sub</tt> on
> - ? any integer bit width and for different address spaces. Not all targets
> - ? support all bit widths however.</p>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.load.sub.i8.p0i32(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
> - ?declare i16 @llvm.atomic.load.sub.i16.p0i32(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
> - ?declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
> - ?declare i64 @llvm.atomic.load.sub.i64.p0i32(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
> -</pre>
> -
> -<h5>Overview:</h5>
> -<p>This intrinsic subtracts <tt>delta</tt> to the value stored in memory at
> - ? <tt>ptr</tt>. It yields the original value at <tt>ptr</tt>.</p>
> -
> -<h5>Arguments:</h5>
> -<p>The intrinsic takes two arguments, the first a pointer to an integer value
> - ? and the second an integer value. The result is also an integer value. These
> - ? integer types can have any bit width, but they must all have the same bit
> - ? width. The targets may only lower integer representations they support.</p>
> -
> -<h5>Semantics:</h5>
> -<p>This intrinsic does a series of operations atomically. It first loads the
> - ? value stored at <tt>ptr</tt>. It then subtracts <tt>delta</tt>, stores the
> - ? result to <tt>ptr</tt>. It yields the original value stored
> - ? at <tt>ptr</tt>.</p>
> -
> -<h5>Examples:</h5>
> -<pre>
> -%mallocP ?= tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
> -%ptr ? ? ?= bitcast i8* %mallocP to i32*
> - ? ? ? ? ? ?store i32 8, %ptr
> -%result1 ?= call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %ptr, i32 4)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result1 = 8</i>
> -%result2 ?= call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %ptr, i32 2)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result2 = 4</i>
> -%result3 ?= call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %ptr, i32 5)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result3 = 2</i>
> -%memval1 ?= load i32* %ptr ? ? ?<i>; yields {i32}:memval1 = -3</i>
> -</pre>
> -
> -</div>
> -
> -<!-- _______________________________________________________________________ -->
> -<h4>
> - ?<a name="int_atomic_load_and">
> - ? ?'<tt>llvm.atomic.load.and.*</tt>' Intrinsic
> - ?</a>
> - ?<br>
> - ?<a name="int_atomic_load_nand">
> - ? ?'<tt>llvm.atomic.load.nand.*</tt>' Intrinsic
> - ?</a>
> - ?<br>
> - ?<a name="int_atomic_load_or">
> - ? ?'<tt>llvm.atomic.load.or.*</tt>' Intrinsic
> - ?</a>
> - ?<br>
> - ?<a name="int_atomic_load_xor">
> - ? ?'<tt>llvm.atomic.load.xor.*</tt>' Intrinsic
> - ?</a>
> -</h4>
> -
> -<div>
> -
> -<h5>Syntax:</h5>
> -<p>These are overloaded intrinsics. You can
> - ?use <tt>llvm.atomic.load_and</tt>, <tt>llvm.atomic.load_nand</tt>,
> - ?<tt>llvm.atomic.load_or</tt>, and <tt>llvm.atomic.load_xor</tt> on any integer
> - ?bit width and for different address spaces. Not all targets support all bit
> - ?widths however.</p>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.load.and.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
> - ?declare i16 @llvm.atomic.load.and.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
> - ?declare i32 @llvm.atomic.load.and.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
> - ?declare i64 @llvm.atomic.load.and.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
> -</pre>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.load.or.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
> - ?declare i16 @llvm.atomic.load.or.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
> - ?declare i32 @llvm.atomic.load.or.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
> - ?declare i64 @llvm.atomic.load.or.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
> -</pre>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.load.nand.i8.p0i32(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
> - ?declare i16 @llvm.atomic.load.nand.i16.p0i32(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
> - ?declare i32 @llvm.atomic.load.nand.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
> - ?declare i64 @llvm.atomic.load.nand.i64.p0i32(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
> -</pre>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.load.xor.i8.p0i32(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
> - ?declare i16 @llvm.atomic.load.xor.i16.p0i32(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
> - ?declare i32 @llvm.atomic.load.xor.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
> - ?declare i64 @llvm.atomic.load.xor.i64.p0i32(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
> -</pre>
> -
> -<h5>Overview:</h5>
> -<p>These intrinsics bitwise the operation (and, nand, or, xor) <tt>delta</tt> to
> - ? the value stored in memory at <tt>ptr</tt>. It yields the original value
> - ? at <tt>ptr</tt>.</p>
> -
> -<h5>Arguments:</h5>
> -<p>These intrinsics take two arguments, the first a pointer to an integer value
> - ? and the second an integer value. The result is also an integer value. These
> - ? integer types can have any bit width, but they must all have the same bit
> - ? width. The targets may only lower integer representations they support.</p>
> -
> -<h5>Semantics:</h5>
> -<p>These intrinsics does a series of operations atomically. They first load the
> - ? value stored at <tt>ptr</tt>. They then do the bitwise
> - ? operation <tt>delta</tt>, store the result to <tt>ptr</tt>. They yield the
> - ? original value stored at <tt>ptr</tt>.</p>
> -
> -<h5>Examples:</h5>
> -<pre>
> -%mallocP ?= tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
> -%ptr ? ? ?= bitcast i8* %mallocP to i32*
> - ? ? ? ? ? ?store i32 0x0F0F, %ptr
> -%result0 ?= call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %ptr, i32 0xFF)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result0 = 0x0F0F</i>
> -%result1 ?= call i32 @llvm.atomic.load.and.i32.p0i32(i32* %ptr, i32 0xFF)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result1 = 0xFFFFFFF0</i>
> -%result2 ?= call i32 @llvm.atomic.load.or.i32.p0i32(i32* %ptr, i32 0F)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result2 = 0xF0</i>
> -%result3 ?= call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %ptr, i32 0F)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result3 = FF</i>
> -%memval1 ?= load i32* %ptr ? ? ?<i>; yields {i32}:memval1 = F0</i>
> -</pre>
> -
> -</div>
> -
> -<!-- _______________________________________________________________________ -->
> -<h4>
> - ?<a name="int_atomic_load_max">
> - ? ?'<tt>llvm.atomic.load.max.*</tt>' Intrinsic
> - ?</a>
> - ?<br>
> - ?<a name="int_atomic_load_min">
> - ? ?'<tt>llvm.atomic.load.min.*</tt>' Intrinsic
> - ?</a>
> - ?<br>
> - ?<a name="int_atomic_load_umax">
> - ? ?'<tt>llvm.atomic.load.umax.*</tt>' Intrinsic
> - ?</a>
> - ?<br>
> - ?<a name="int_atomic_load_umin">
> - ? ?'<tt>llvm.atomic.load.umin.*</tt>' Intrinsic
> - ?</a>
> -</h4>
> -
> -<div>
> -
> -<h5>Syntax:</h5>
> -<p>These are overloaded intrinsics. You can use <tt>llvm.atomic.load_max</tt>,
> - ? <tt>llvm.atomic.load_min</tt>, <tt>llvm.atomic.load_umax</tt>, and
> - ? <tt>llvm.atomic.load_umin</tt> on any integer bit width and for different
> - ? address spaces. Not all targets support all bit widths however.</p>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.load.max.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
> - ?declare i16 @llvm.atomic.load.max.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
> - ?declare i32 @llvm.atomic.load.max.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
> - ?declare i64 @llvm.atomic.load.max.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
> -</pre>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.load.min.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
> - ?declare i16 @llvm.atomic.load.min.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
> - ?declare i32 @llvm.atomic.load.min.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
> - ?declare i64 @llvm.atomic.load.min.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
> -</pre>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.load.umax.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
> - ?declare i16 @llvm.atomic.load.umax.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
> - ?declare i32 @llvm.atomic.load.umax.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
> - ?declare i64 @llvm.atomic.load.umax.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
> -</pre>
> -
> -<pre>
> - ?declare i8 @llvm.atomic.load.umin.i8.p0i8(i8* &lt;ptr&gt;, i8 &lt;delta&gt;)
> - ?declare i16 @llvm.atomic.load.umin.i16.p0i16(i16* &lt;ptr&gt;, i16 &lt;delta&gt;)
> - ?declare i32 @llvm.atomic.load.umin.i32.p0i32(i32* &lt;ptr&gt;, i32 &lt;delta&gt;)
> - ?declare i64 @llvm.atomic.load.umin.i64.p0i64(i64* &lt;ptr&gt;, i64 &lt;delta&gt;)
> -</pre>
> -
> -<h5>Overview:</h5>
> -<p>These intrinsics takes the signed or unsigned minimum or maximum of
> - ? <tt>delta</tt> and the value stored in memory at <tt>ptr</tt>. It yields the
> - ? original value at <tt>ptr</tt>.</p>
> -
> -<h5>Arguments:</h5>
> -<p>These intrinsics take two arguments, the first a pointer to an integer value
> - ? and the second an integer value. The result is also an integer value. These
> - ? integer types can have any bit width, but they must all have the same bit
> - ? width. The targets may only lower integer representations they support.</p>
> -
> -<h5>Semantics:</h5>
> -<p>These intrinsics does a series of operations atomically. They first load the
> - ? value stored at <tt>ptr</tt>. They then do the signed or unsigned min or
> - ? max <tt>delta</tt> and the value, store the result to <tt>ptr</tt>. They
> - ? yield the original value stored at <tt>ptr</tt>.</p>
> -
> -<h5>Examples:</h5>
> -<pre>
> -%mallocP ?= tail call i8* @malloc(i32 ptrtoint (i32* getelementptr (i32* null, i32 1) to i32))
> -%ptr ? ? ?= bitcast i8* %mallocP to i32*
> - ? ? ? ? ? ?store i32 7, %ptr
> -%result0 ?= call i32 @llvm.atomic.load.min.i32.p0i32(i32* %ptr, i32 -2)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result0 = 7</i>
> -%result1 ?= call i32 @llvm.atomic.load.max.i32.p0i32(i32* %ptr, i32 8)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result1 = -2</i>
> -%result2 ?= call i32 @llvm.atomic.load.umin.i32.p0i32(i32* %ptr, i32 10)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result2 = 8</i>
> -%result3 ?= call i32 @llvm.atomic.load.umax.i32.p0i32(i32* %ptr, i32 30)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<i>; yields {i32}:result3 = 8</i>
> -%memval1 ?= load i32* %ptr ? ? ?<i>; yields {i32}:memval1 = 30</i>
> -</pre>
> -
> -</div>
> -
> -</div>
> -
> -<!-- ======================================================================= -->
> -<h3>
> ? <a name="int_memorymarkers">Memory Use Markers</a>
> ?</h3>
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From echristo at apple.com  Tue Oct 25 19:52:13 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 26 Oct 2011 00:52:13 -0000
Subject: [llvm-commits] [llvm] r142997 - in /llvm/trunk: Makefile.config.in
 Makefile.rules autoconf/configure.ac configure
Message-ID: <20111026005213.526A6312800A@llvm.org>

Author: echristo
Date: Tue Oct 25 19:52:13 2011
New Revision: 142997

URL: http://llvm.org/viewvc/llvm-project?rev=142997&view=rev
Log:
Search for and use the strip program and pass it to install for it
to use for stripping final executables.

Patch by Simon Atanasyan!

Modified:
    llvm/trunk/Makefile.config.in
    llvm/trunk/Makefile.rules
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/configure

Modified: llvm/trunk/Makefile.config.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.config.in?rev=142997&r1=142996&r2=142997&view=diff
==============================================================================
--- llvm/trunk/Makefile.config.in (original)
+++ llvm/trunk/Makefile.config.in Tue Oct 25 19:52:13 2011
@@ -149,6 +149,9 @@
 AR_PATH = @AR@
 AR = @AR@
 
+# Path to the strip program,
+STRIP = @STRIP@
+
 # Path to the nm program
 NM_PATH = @NM@
 

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=142997&r1=142996&r2=142997&view=diff
==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Tue Oct 25 19:52:13 2011
@@ -531,7 +531,7 @@
 ifndef KEEP_SYMBOLS
   Strip := $(PLATFORMSTRIPOPTS)
   StripWarnMsg := "(without symbols)"
-  Install.StripFlag += -s
+  Install.StripFlag += -s --strip-program=$(STRIP)
 endif
 
 ifdef TOOL_NO_EXPORTS

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=142997&r1=142996&r2=142997&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Tue Oct 25 19:52:13 2011
@@ -897,6 +897,7 @@
 AC_PATH_PROG(MV,   [mv],   [mv])
 AC_PROG_RANLIB
 AC_CHECK_TOOL(AR, ar, false)
+AC_CHECK_TOOL(STRIP,[strip], false)
 AC_PATH_PROG(RM,   [rm],   [rm])
 AC_PATH_PROG(SED,  [sed],  [sed])
 AC_PATH_PROG(TAR,  [tar],  [gtar])

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=142997&r1=142996&r2=142997&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Tue Oct 25 19:52:13 2011
@@ -721,6 +721,7 @@
 MV
 RANLIB
 AR
+STRIP
 RM
 SED
 TAR
@@ -6226,6 +6227,102 @@
   AR="$ac_cv_prog_AR"
 fi
 
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args.
+set dummy ${ac_tool_prefix}strip; ac_word=$2
+{ echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; }
+if test "${ac_cv_prog_STRIP+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if test -n "$STRIP"; then
+  ac_cv_prog_STRIP="$STRIP" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; }; then
+    ac_cv_prog_STRIP="${ac_tool_prefix}strip"
+    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+IFS=$as_save_IFS
+
+fi
+fi
+STRIP=$ac_cv_prog_STRIP
+if test -n "$STRIP"; then
+  { echo "$as_me:$LINENO: result: $STRIP" >&5
+echo "${ECHO_T}$STRIP" >&6; }
+else
+  { echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6; }
+fi
+
+
+fi
+if test -z "$ac_cv_prog_STRIP"; then
+  ac_ct_STRIP=$STRIP
+  # Extract the first word of "strip", so it can be a program name with args.
+set dummy strip; ac_word=$2
+{ echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; }
+if test "${ac_cv_prog_ac_ct_STRIP+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if test -n "$ac_ct_STRIP"; then
+  ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; }; then
+    ac_cv_prog_ac_ct_STRIP="strip"
+    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP
+if test -n "$ac_ct_STRIP"; then
+  { echo "$as_me:$LINENO: result: $ac_ct_STRIP" >&5
+echo "${ECHO_T}$ac_ct_STRIP" >&6; }
+else
+  { echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6; }
+fi
+
+  if test "x$ac_ct_STRIP" = x; then
+    STRIP="false"
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ echo "$as_me:$LINENO: WARNING: In the future, Autoconf will not detect cross-tools
+whose name does not start with the host triplet.  If you think this
+configuration is useful to you, please write to autoconf at gnu.org." >&5
+echo "$as_me: WARNING: In the future, Autoconf will not detect cross-tools
+whose name does not start with the host triplet.  If you think this
+configuration is useful to you, please write to autoconf at gnu.org." >&2;}
+ac_tool_warned=yes ;;
+esac
+    STRIP=$ac_ct_STRIP
+  fi
+else
+  STRIP="$ac_cv_prog_STRIP"
+fi
+
 # Extract the first word of "rm", so it can be a program name with args.
 set dummy rm; ac_word=$2
 { echo "$as_me:$LINENO: checking for $ac_word" >&5
@@ -10460,7 +10557,7 @@
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<EOF
-#line 10463 "configure"
+#line 10560 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -21930,6 +22027,7 @@
 MV!$MV$ac_delim
 RANLIB!$RANLIB$ac_delim
 AR!$AR$ac_delim
+STRIP!$STRIP$ac_delim
 RM!$RM$ac_delim
 SED!$SED$ac_delim
 TAR!$TAR$ac_delim
@@ -21999,7 +22097,7 @@
 LTLIBOBJS!$LTLIBOBJS$ac_delim
 _ACEOF
 
-  if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 89; then
+  if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 90; then
     break
   elif $ac_last_try; then
     { { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5



From eli.friedman at gmail.com  Tue Oct 25 19:55:23 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 26 Oct 2011 00:55:23 -0000
Subject: [llvm-commits] [llvm] r142998 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026005523.B315A312800A@llvm.org>

Author: efriedma
Date: Tue Oct 25 19:55:23 2011
New Revision: 142998

URL: http://llvm.org/viewvc/llvm-project?rev=142998&view=rev
Log:
Add a note about the removal of the atomic intrinsics to the "Major Changes" section of the release notes.


Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142998&r1=142997&r2=142998&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 19:55:23 2011
@@ -758,6 +758,9 @@
       "<code>load volatile</code>"/"<code>store volatile</code>".  The old
       syntax ("<code>volatile load</code>"/"<code>volatile store</code>")
       is still accepted, but is now considered deprecated.</li>
+  <li>The old atomic intrinscs (<code>llvm.memory.barrier</code> and
+      <code>llvm.atomic.*</code>) are now gone.  Please use the new atomic
+      instructions, described in the <a href="Atomics.html">atomics guide</a>.
 </ul>
 
 <h4>Windows (32-bit)</h4>



From hfinkel at anl.gov  Tue Oct 25 20:01:29 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Tue, 25 Oct 2011 20:01:29 -0500
Subject: [llvm-commits] Bottom-Up Scheduling?
In-Reply-To: <2A12F36F-CEC9-4C9F-913E-9F0315BFB33F@apple.com>
References: <20111017040355.918882A6C12C@llvm.org>
	<C7AD0F52-99F9-4E75-BEEB-9852950D5385@apple.com>
	<1319077746.6498.6164.camel@sapling>
	<2A12F36F-CEC9-4C9F-913E-9F0315BFB33F@apple.com>
Message-ID: <1319590889.6498.6388.camel@sapling>

Is there documentation somewhere for the bottom-up scheduling? I'm
trying to figure out what changes are necessary in order to support it
in the PPC backend.

Thanks in advance,
Hal

On Thu, 2011-10-20 at 10:21 -0700, Evan Cheng wrote:
> 
> On Oct 19, 2011, at 7:29 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> 
> > Evan,
> > 
> > Thanks for the heads up! Is there a current target that implements the
> > scheduling as it will be? And does the bottom-up scheduling also account
> 
> ARM is a good model. 

What part of ARM's implementation is associated with the bottom-up
scheduling? I am confused because it looks like it is essentially using
the same kind of ScoreboardHazardRecognizer that was commented out of
the PPC 440 code.

Thanks in advance,
Hal

> 
> > for pipeline-conflict hazards?
> 
> Yes, definitely. And it should be doing a much better job of it. 
> 
> Evan
> 
> > 
> > -Hal
> > 
> > On Wed, 2011-10-19 at 16:45 -0700, Evan Cheng wrote:
> >> Hi Hal,
> >> 
> >> Heads up. We'll soon abolish top-down pre-register allocation scheduler and force every target to bottom up scheduling. The problem is tt list scheduler does not handle physical register dependency at all but it is something that's required for some upcoming legalizer change.
> >> 
> >> If you are interested in PPC, you might want to look into switching its scheduler now. The bottom up register pressure aware scheduler should work quite well for PPC.
> >> 
> >> Thanks,
> >> 
> >> Evan
> >> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From evan.cheng at apple.com  Tue Oct 25 20:08:37 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 25 Oct 2011 18:08:37 -0700
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <20111019141108.15BB73128018@llvm.org>
References: <20111019141108.15BB73128018@llvm.org>
Message-ID: <8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>

Hi James,

Sorry I missed this patch earlier. I have some problem with this.

1. Note -Os for LLVM, especially for Darwin, means reduce code size without hurting performance. Did you test the impact of this patch on the performance of generated code? Our tests has shown movw / movt to be faster than ldr. This is especially a concern for Cortex-A9 with more limited address generation bandwidth. Also note, for PIC codegen, at least on Darwin, loading a global would require ldr + add + ldr. That's especially unfriendly:
        ldr.n   r1, LCPI1_0
LPC1_0:
        add     r1, pc
        ldr     r1, [r1]
...
LCPI1_0:
        .long   _foo

vs.
        movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc
        ldr     r0, [r0]

2. Where is code size saving from? You are talking about movw + movt vs. ldr + a constantpool entry.

3. There are good reasons to avoid constantpools. The constantpools in text makes assembly hard to read and it sometimes would end up introducing jumps. That hurts both performance, compile time, and sometimes code size.

4. Darwin is especially sensitive to this because of objective-c code. SPEC is interesting, but it's not the only benchmarks.

Please check with me before making changes that can impact Darwin codegen in the future. We can continue the discussion, but I'm going revert the change for Darwin.

Thanks.

Evan


On Oct 19, 2011, at 7:11 AM, James Molloy wrote:

> Author: jamesm
> Date: Wed Oct 19 09:11:07 2011
> New Revision: 142530
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=142530&view=rev
> Log:
> Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.
> 
> On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
> codesize including literal pools.
> 
> The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
> is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.
> 
> Fixes PR11087.
> 
> 
> Added:
>    llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll   (with props)
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142530&r1=142529&r2=142530&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Oct 19 09:11:07 2011
> @@ -2103,8 +2103,10 @@
>   }
> 
>   // If we have T2 ops, we can materialize the address directly via movt/movw
> -  // pair. This is always cheaper.
> -  if (Subtarget->useMovt()) {
> +  // pair. This is always cheaper in terms of performance, but uses at least 2
> +  // extra bytes.
> +  if (Subtarget->useMovt() &&
> +      !DAG.getMachineFunction().getFunction()->hasFnAttr(Attribute::OptimizeForSize)) {
>     ++NumMovwMovt;
>     // FIXME: Once remat is capable of dealing with instructions with register
>     // operands, expand this into two nodes.
> @@ -2129,7 +2131,8 @@
>   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
> 
>   // FIXME: Enable this for static codegen when tool issues are fixed.
> -  if (Subtarget->useMovt() && RelocM != Reloc::Static) {
> +  if (Subtarget->useMovt() && RelocM != Reloc::Static &&
> +      !DAG.getMachineFunction().getFunction()->hasFnAttr(Attribute::OptimizeForSize)) {
>     ++NumMovwMovt;
>     // FIXME: Once remat is capable of dealing with instructions with register
>     // operands, expand this into two nodes.
> 
> Added: llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll?rev=142530&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll Wed Oct 19 09:11:07 2011
> @@ -0,0 +1,27 @@
> +; RUN: llc < %s -mtriple=armv7-apple-darwin  | FileCheck %s
> +; RUN: llc < %s -mtriple=armv7-unknown-linux-eabi | FileCheck %s
> +
> +; Check that when optimizing for size, a literal pool load is used
> +; instead of the (potentially faster) movw/movt pair when loading
> +; a large constant.
> +
> + at x = global i32* inttoptr (i32 305419888 to i32*), align 4
> +
> +define i32 @f() optsize {
> +  ; CHECK: f:
> +  ; CHECK: ldr  r{{.}}, {{.?}}LCPI{{.}}_{{.}}
> +  ; CHECK: ldr  r{{.}}, [{{(pc, )?}}r{{.}}]
> +  ; CHECK: ldr  r{{.}}, [r{{.}}]
> +  %1 = load i32** @x, align 4
> +  %2 = load i32* %1
> +  ret i32 %2
> +}
> +
> +define i32 @g() {
> +  ; CHECK: g:
> +  ; CHECK: movw
> +  ; CHECK: movt
> +  %1 = load i32** @x, align 4
> +  %2 = load i32* %1
> +  ret i32 %2
> +}
> 
> Propchange: llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
> ------------------------------------------------------------------------------
>    svn:eol-style = native
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From isanbard at gmail.com  Tue Oct 25 20:10:25 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 01:10:25 -0000
Subject: [llvm-commits] [llvm] r143001 -
	/llvm/trunk/lib/CodeGen/BranchFolding.cpp
Message-ID: <20111026011025.ED72D312800A@llvm.org>

Author: void
Date: Tue Oct 25 20:10:25 2011
New Revision: 143001

URL: http://llvm.org/viewvc/llvm-project?rev=143001&view=rev
Log:
Reapply r142920 with fix:

An MBB which branches to an EH landing pad shouldn't be considered for tail merging.

In SjLj EH, the jump to the landing pad is not done explicitly through a branch
statement. The EH landing pad is added as a successor to the throwing
BB. Because of that however, the branch folding pass could mistakenly think that
it could merge the throwing BB with another BB. This isn't safe to do.
<rdar://problem/10334833>

Modified:
    llvm/trunk/lib/CodeGen/BranchFolding.cpp

Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=143001&r1=143000&r2=143001&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Oct 25 20:10:25 2011
@@ -870,6 +870,9 @@
         // Visit each predecessor only once.
         if (!UniquePreds.insert(PBB))
           continue;
+        // Skip blocks which may jump to a landing pad. Can't tail merge these.
+        if (PBB->getLandingPadSuccessor())
+          continue;
         MachineBasicBlock *TBB = 0, *FBB = 0;
         SmallVector<MachineOperand, 4> Cond;
         if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond, true)) {



From evan.cheng at apple.com  Tue Oct 25 20:17:44 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 26 Oct 2011 01:17:44 -0000
Subject: [llvm-commits] [llvm] r143002 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
Message-ID: <20111026011744.59F66312800A@llvm.org>

Author: evancheng
Date: Tue Oct 25 20:17:44 2011
New Revision: 143002

URL: http://llvm.org/viewvc/llvm-project?rev=143002&view=rev
Log:
Revert part of r142530. The patch potentially hurts performance especially
on Darwin platforms where -Os means optimize for size without hurting
performance.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=143002&r1=143001&r2=143002&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Oct 25 20:17:44 2011
@@ -2106,8 +2106,9 @@
   // If we have T2 ops, we can materialize the address directly via movt/movw
   // pair. This is always cheaper in terms of performance, but uses at least 2
   // extra bytes.
+  MachineFunction &MF = DAG.getMachineFunction();
   if (Subtarget->useMovt() &&
-      !DAG.getMachineFunction().getFunction()->hasFnAttr(Attribute::OptimizeForSize)) {
+      !MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) {
     ++NumMovwMovt;
     // FIXME: Once remat is capable of dealing with instructions with register
     // operands, expand this into two nodes.
@@ -2132,8 +2133,7 @@
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
 
   // FIXME: Enable this for static codegen when tool issues are fixed.
-  if (Subtarget->useMovt() && RelocM != Reloc::Static &&
-      !DAG.getMachineFunction().getFunction()->hasFnAttr(Attribute::OptimizeForSize)) {
+  if (Subtarget->useMovt() && RelocM != Reloc::Static) {
     ++NumMovwMovt;
     // FIXME: Once remat is capable of dealing with instructions with register
     // operands, expand this into two nodes.

Modified: llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll?rev=143002&r1=143001&r2=143002&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll Tue Oct 25 20:17:44 2011
@@ -1,4 +1,3 @@
-; RUN: llc < %s -mtriple=armv7-apple-darwin  | FileCheck %s
 ; RUN: llc < %s -mtriple=armv7-unknown-linux-eabi | FileCheck %s
 
 ; Check that when optimizing for size, a literal pool load is used



From evan.cheng at apple.com  Tue Oct 25 20:26:57 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 26 Oct 2011 01:26:57 -0000
Subject: [llvm-commits] [llvm] r143003 -
	/llvm/trunk/lib/CodeGen/MachineLICM.cpp
Message-ID: <20111026012657.963C3312800A@llvm.org>

Author: evancheng
Date: Tue Oct 25 20:26:57 2011
New Revision: 143003

URL: http://llvm.org/viewvc/llvm-project?rev=143003&view=rev
Log:
Disable LICM speculation in high register pressure situation again now that Devang has fixed other issues.

Modified:
    llvm/trunk/lib/CodeGen/MachineLICM.cpp

Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=143003&r1=143002&r2=143003&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Tue Oct 25 20:26:57 2011
@@ -45,7 +45,7 @@
 static cl::opt<bool>
 AvoidSpeculation("avoid-speculation",
                  cl::desc("MachineLICM should avoid speculation"),
-                 cl::init(false), cl::Hidden);
+                 cl::init(true), cl::Hidden);
 
 STATISTIC(NumHoisted,
           "Number of machine instructions hoisted out of loops");



From grosser at fim.uni-passau.de  Tue Oct 25 20:27:49 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 26 Oct 2011 01:27:49 -0000
Subject: [llvm-commits] [polly] r143004 -
	/polly/trunk/lib/Analysis/ScopDetection.cpp
Message-ID: <20111026012749.E7997312800A@llvm.org>

Author: grosser
Date: Tue Oct 25 20:27:49 2011
New Revision: 143004

URL: http://llvm.org/viewvc/llvm-project?rev=143004&view=rev
Log:
ScopInfo: Print SCEV and not the pointer to it

Modified:
    polly/trunk/lib/Analysis/ScopDetection.cpp

Modified: polly/trunk/lib/Analysis/ScopDetection.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=143004&r1=143003&r2=143004&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopDetection.cpp (original)
+++ polly/trunk/lib/Analysis/ScopDetection.cpp Tue Oct 25 20:27:49 2011
@@ -402,7 +402,7 @@
   // Is the loop count affine?
   const SCEV *LoopCount = SE->getBackedgeTakenCount(L);
   if (!isValidAffineFunction(LoopCount, Context.CurRegion))
-    INVALID(LoopBound, "Non affine loop bound '" << LoopCount << "'for loop: "
+    INVALID(LoopBound, "Non affine loop bound '" << *LoopCount << "' in loop: "
                        << L->getHeader()->getNameStr());
 
   return true;



From grosser at fim.uni-passau.de  Tue Oct 25 20:27:53 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 26 Oct 2011 01:27:53 -0000
Subject: [llvm-commits] [polly] r143005 -
	/polly/trunk/www/example_load_Polly_into_clang.html
Message-ID: <20111026012753.A88A0312800A@llvm.org>

Author: grosser
Date: Tue Oct 25 20:27:53 2011
New Revision: 143005

URL: http://llvm.org/viewvc/llvm-project?rev=143005&view=rev
Log:
www: Emphasize clang/LLVM/Polly need to be in sync

Modified:
    polly/trunk/www/example_load_Polly_into_clang.html

Modified: polly/trunk/www/example_load_Polly_into_clang.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/example_load_Polly_into_clang.html?rev=143005&r1=143004&r2=143005&view=diff
==============================================================================
--- polly/trunk/www/example_load_Polly_into_clang.html (original)
+++ polly/trunk/www/example_load_Polly_into_clang.html Tue Oct 25 20:27:53 2011
@@ -26,6 +26,9 @@
 ${POLLY_BUILD_DIR}/lib/LLVMPolly.so' to your command line or your CFLAGS and
 Polly is automatically executed at -O3.
 
+<b>WARNING: You need clang/LLVM/Polly need to be in sync. This normally means
+            you need to compile all of them from a recent svn/git checkout</b>
+
 <pre class="code">clang -load ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 file.c</pre>
 
 <h2>Automatic OpenMP code generation</h2>



From bruno.cardoso at gmail.com  Tue Oct 25 20:47:48 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 25 Oct 2011 23:47:48 -0200
Subject: [llvm-commits] [PATCH][Review request] Mips direct object
	generation patch #2
In-Reply-To: <86AC779C188FE74F88F6494478B46332E82CEF@exchdb03.mips.com>
References: <86AC779C188FE74F88F6494478B46332E82CEF@exchdb03.mips.com>
Message-ID: <CACk9FxaB7mfJU=JAXTcRSZeC=+msGoDHWUm6rFs=BuotSWskrQ@mail.gmail.com>

Hi,

On Tue, Oct 25, 2011 at 6:19 PM, Carter, Jack <jcarter at mips.com> wrote:
> This is the first of several patches for Mips direct object generation. This
> first patch is for expression variable kinds.
>
> In this patch we are following the current convention of putting target
> specific? ELF relocation handling in the base class due to unfortunate
> expression class mechanics.
>
> Hopefully after our port settles down we can address this issue with the
> community and coordinate a structural change that pushes the target specific
> relocation and expression handling completely down to the Target level.

On the snippet below, early exit returning ELF::R_MIPS_NONE

+  // determine the type of the relocation
+  unsigned Type;
+  if (IsPCRel) {
+    switch ((unsigned)Fixup.getKind()) {
+    default:
+      llvm_unreachable("Unimplemented");
+      case Mips::fixup_Mips_Branch_PCRel:
+      case Mips::fixup_Mips_PC16:
+        Type = ELF::R_MIPS_NONE;
+        break;
+      break;
+    }

After that, remove the else below, use only 2 spaces for indentation
under the switch statement, and also return directly the other
relocation types.

+  } else {
+    switch ((unsigned)Fixup.getKind()) {
+        default:
+            llvm_unreachable("invalid fixup kind!");
+        case FK_Data_4:
+            Type = ELF::R_MIPS_32;
+            break;
+        case Mips::fixup_Mips_GPREL16:
+            Type = ELF::R_MIPS_GPREL16;
+            break;



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From stoklund at 2pi.dk  Tue Oct 25 20:47:48 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 26 Oct 2011 01:47:48 -0000
Subject: [llvm-commits] [llvm] r143006 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20111026014748.9E2C6312800A@llvm.org>

Author: stoklund
Date: Tue Oct 25 20:47:48 2011
New Revision: 143006

URL: http://llvm.org/viewvc/llvm-project?rev=143006&view=rev
Log:
Don't use floating point to do an integer's job.

This code makes different decisions when compiled into x87 instructions
because of different rounding behavior.  That caused phase 2/3
miscompares on 32-bit Linux when the phase 1 compiler was built with gcc
(using x87), and the phase 2 compiler was built with clang (using SSE).

This fixes PR11200.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=143006&r1=143005&r2=143006&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Oct 25 20:47:48 2011
@@ -2034,14 +2034,17 @@
     return false;
 
   APInt Range = ComputeRange(First, Last);
-  double Density = TSize.roundToDouble() / Range.roundToDouble();
-  if (Density < 0.4)
+  // The density is TSize / Range. Require at least 40%.
+  // It should not be possible for IntTSize to saturate for sane code, but make
+  // sure we handle Range saturation correctly.
+  uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
+  uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
+  if (IntTSize * 10 < IntRange * 4)
     return false;
 
   DEBUG(dbgs() << "Lowering jump table\n"
                << "First entry: " << First << ". Last entry: " << Last << '\n'
-               << "Range: " << Range
-               << ". Size: " << TSize << ". Density: " << Density << "\n\n");
+               << "Range: " << Range << ". Size: " << TSize << ".\n\n");
 
   // Get the MachineFunction which holds the current MBB.  This is used when
   // inserting any additional MBBs necessary to represent the switch.



From matthewbg at google.com  Tue Oct 25 20:53:17 2011
From: matthewbg at google.com (Matt Beaumont-Gay)
Date: Tue, 25 Oct 2011 18:53:17 -0700
Subject: [llvm-commits] [llvm] r142960 -
	/llvm/trunk/docs/ReleaseNotes.html
In-Reply-To: <20111025203531.86AFA312800A@llvm.org>
References: <20111025203531.86AFA312800A@llvm.org>
Message-ID: <CAOL_hqDGxRM9_cHyBoRXNxYbKCr2ZuvK9b4TpDqndnMT2vWxFw@mail.gmail.com>

On Tue, Oct 25, 2011 at 13:35, Bill Wendling <isanbard at gmail.com> wrote:
> Author: void
> Date: Tue Oct 25 15:35:31 2011
> New Revision: 142960
>
> URL: http://llvm.org/viewvc/llvm-project?rev=142960&view=rev
> Log:
> Add mention of gwScript to external OS projects.
>
> Modified:
> ? ?llvm/trunk/docs/ReleaseNotes.html
>
> Modified: llvm/trunk/docs/ReleaseNotes.html
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=142960&r1=142959&r2=142960&view=diff
> ==============================================================================
> --- llvm/trunk/docs/ReleaseNotes.html (original)
> +++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 15:35:31 2011
> @@ -298,6 +298,31 @@
> ?-->
>
> ?<!--=========================================================================-->
> +<h3>gwXscript</h3>
> +
> +<div>
> +
> +<p><a href="http://botwars.tk/gwscript/">gwXscript</a> is an object oriented,
> + ? aspect orientied programing language which can create both, executables (ELF,

s/orientied/oriented/, s/programing/programming/ (and probably remove
the comma after "both")

> + ? EXE) and shared libraries (DLL, SO, DYNLIB). The compiler is implemented in
> + ? its own language and translates scripts into LLVM-IR which can be optimized
> + ? and translated into native code by the LLVM framework. Source code in
> + ? gwScript contains definitions that expand the namespaces. So you can build
> + ? your project and simply 'plug out' features by removing a file. The remaining
> + ? project does not leave scars since you directly separate concerns by the
> + ? 'template' feature of gwX. It is also possible to add new features to a
> + ? project by just adding files and without editing the original project. This
> + ? language is used for example to create games or content management systems
> + ? that should be extendable.</p>
> +
> +<p>gwXscript is strongly typed and offers comfort with its native types string,
> + ? hash and array. You can easily write new libraries in gwXscript or native
> + ? code. gwXscript is type safe and users should not be able to crash your
> + ? program or execute malicious code except code that is eating CPU time.</p>
> +
> +</div>
> +
> +<!--=========================================================================-->
> ?<h3>TTA-based Co-design Environment (TCE)</h3>
>
> ?<div>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From bruno.cardoso at gmail.com  Tue Oct 25 20:58:44 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 25 Oct 2011 23:58:44 -0200
Subject: [llvm-commits] [PATCH][Review request] Mips direct object
	generation patch #3 of 6
In-Reply-To: <86AC779C188FE74F88F6494478B46332E82D84@exchdb03.mips.com>
References: <86AC779C188FE74F88F6494478B46332E82D84@exchdb03.mips.com>
Message-ID: <CACk9FxbY=d5pj0z-iSWikzYuWRbnu3A_NNjXj7U74jEEAZGUHA@mail.gmail.com>

I was looking forward to see cpload and cprestore go this way. Nice.
Let me know when you fix the remaining failing tests, and will commit it!
Thanks

On Tue, Oct 25, 2011 at 10:05 PM, Carter, Jack <jcarter at mips.com> wrote:
> This is the third of six patches for Mips direct object generation.
>
> ??? lib/Target/Mips/MipsMCInstLower.cpp
> ??? lib/Target/Mips/MipsMCInstLower.h
>
> The patch is attached.
>
> Jack
>



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From grosser at fim.uni-passau.de  Tue Oct 25 21:09:11 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 26 Oct 2011 02:09:11 -0000
Subject: [llvm-commits] [polly] r143007 -
	/polly/trunk/www/example_load_Polly_into_clang.html
Message-ID: <20111026020911.4168A312800A@llvm.org>

Author: grosser
Date: Tue Oct 25 21:09:11 2011
New Revision: 143007

URL: http://llvm.org/viewvc/llvm-project?rev=143007&view=rev
Log:
www: reformat warning

Modified:
    polly/trunk/www/example_load_Polly_into_clang.html

Modified: polly/trunk/www/example_load_Polly_into_clang.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/example_load_Polly_into_clang.html?rev=143007&r1=143006&r2=143007&view=diff
==============================================================================
--- polly/trunk/www/example_load_Polly_into_clang.html (original)
+++ polly/trunk/www/example_load_Polly_into_clang.html Tue Oct 25 21:09:11 2011
@@ -26,8 +26,10 @@
 ${POLLY_BUILD_DIR}/lib/LLVMPolly.so' to your command line or your CFLAGS and
 Polly is automatically executed at -O3.
 
-<b>WARNING: You need clang/LLVM/Polly need to be in sync. This normally means
-            you need to compile all of them from a recent svn/git checkout</b>
+<p>
+<b>WARNING: clang/LLVM/Polly need to be in sync. This means
+            you need to compile them yourself from a recent svn/git checkout</b>
+            </p>
 
 <pre class="code">clang -load ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 file.c</pre>
 



From grosser at fim.uni-passau.de  Tue Oct 25 21:14:40 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 26 Oct 2011 02:14:40 -0000
Subject: [llvm-commits] [polly] r143008 -
	/polly/trunk/www/example_load_Polly_into_clang.html
Message-ID: <20111026021440.7948F312800A@llvm.org>

Author: grosser
Date: Tue Oct 25 21:14:40 2011
New Revision: 143008

URL: http://llvm.org/viewvc/llvm-project?rev=143008&view=rev
Log:
Add forgotten -Xclang option

Reported by: yabin.hwu at gmail.com

Modified:
    polly/trunk/www/example_load_Polly_into_clang.html

Modified: polly/trunk/www/example_load_Polly_into_clang.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/example_load_Polly_into_clang.html?rev=143008&r1=143007&r2=143008&view=diff
==============================================================================
--- polly/trunk/www/example_load_Polly_into_clang.html (original)
+++ polly/trunk/www/example_load_Polly_into_clang.html Tue Oct 25 21:14:40 2011
@@ -22,7 +22,7 @@
 database</a> and consider reporting the bug.
 <h2>Compiling code with Polly</h2>
 
-To compile code with Polly you only need to add '-load
+To compile code with Polly you only need to add '-Xclang -load -Xclang
 ${POLLY_BUILD_DIR}/lib/LLVMPolly.so' to your command line or your CFLAGS and
 Polly is automatically executed at -O3.
 
@@ -31,21 +31,21 @@
             you need to compile them yourself from a recent svn/git checkout</b>
             </p>
 
-<pre class="code">clang -load ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 file.c</pre>
+<pre class="code">clang -Xclang -load -Xclang ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 file.c</pre>
 
 <h2>Automatic OpenMP code generation</h2>
 
 To automatically detect parallel loops and generate OpenMP code for them you
 also need to add '-mllvm -enable-polly-openmp -lgomp' to your CFLAGS.
 
-<pre class="code">clang -load ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 -mllvm -enable-polly-openmp -lgomp file.c</pre>
+<pre class="code">clang -Xclang -load -Xclang ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 -mllvm -enable-polly-openmp -lgomp file.c</pre>
 
 <h2>Automatic Vector code generation</h2>
 
 Automatic vector code generation can be enabled by adding '-mllvm
 -enable-polly-vector' to your CFLAGS.
 
-<pre class="code">clang -load ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 -mllvm -enable-polly-vector file.c</pre>
+<pre class="code">clang -Xclang -load -Xclang ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 -mllvm -enable-polly-vector file.c</pre>
 
 <h2>Further options</h2>
 



From cdavis at mines.edu  Tue Oct 25 21:28:32 2011
From: cdavis at mines.edu (Charles Davis)
Date: Wed, 26 Oct 2011 02:28:32 -0000
Subject: [llvm-commits] [llvm] r143009 - in /llvm/trunk: Makefile.config.in
 Makefile.rules autoconf/configure.ac configure
Message-ID: <20111026022832.B6DA1312800A@llvm.org>

Author: cdavis
Date: Tue Oct 25 21:28:32 2011
New Revision: 143009

URL: http://llvm.org/viewvc/llvm-project?rev=143009&view=rev
Log:
Revert 142997. It doesn't work on Mac OS or the BSDs, which all use the BSD
version of the install program, which does not have the --strip-program
switch.

Modified:
    llvm/trunk/Makefile.config.in
    llvm/trunk/Makefile.rules
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/configure

Modified: llvm/trunk/Makefile.config.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.config.in?rev=143009&r1=143008&r2=143009&view=diff
==============================================================================
--- llvm/trunk/Makefile.config.in (original)
+++ llvm/trunk/Makefile.config.in Tue Oct 25 21:28:32 2011
@@ -149,9 +149,6 @@
 AR_PATH = @AR@
 AR = @AR@
 
-# Path to the strip program,
-STRIP = @STRIP@
-
 # Path to the nm program
 NM_PATH = @NM@
 

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=143009&r1=143008&r2=143009&view=diff
==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Tue Oct 25 21:28:32 2011
@@ -531,7 +531,7 @@
 ifndef KEEP_SYMBOLS
   Strip := $(PLATFORMSTRIPOPTS)
   StripWarnMsg := "(without symbols)"
-  Install.StripFlag += -s --strip-program=$(STRIP)
+  Install.StripFlag += -s
 endif
 
 ifdef TOOL_NO_EXPORTS

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=143009&r1=143008&r2=143009&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Tue Oct 25 21:28:32 2011
@@ -897,7 +897,6 @@
 AC_PATH_PROG(MV,   [mv],   [mv])
 AC_PROG_RANLIB
 AC_CHECK_TOOL(AR, ar, false)
-AC_CHECK_TOOL(STRIP,[strip], false)
 AC_PATH_PROG(RM,   [rm],   [rm])
 AC_PATH_PROG(SED,  [sed],  [sed])
 AC_PATH_PROG(TAR,  [tar],  [gtar])

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=143009&r1=143008&r2=143009&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Tue Oct 25 21:28:32 2011
@@ -721,7 +721,6 @@
 MV
 RANLIB
 AR
-STRIP
 RM
 SED
 TAR
@@ -6227,102 +6226,6 @@
   AR="$ac_cv_prog_AR"
 fi
 
-if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args.
-set dummy ${ac_tool_prefix}strip; ac_word=$2
-{ echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; }
-if test "${ac_cv_prog_STRIP+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$STRIP"; then
-  ac_cv_prog_STRIP="$STRIP" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; }; then
-    ac_cv_prog_STRIP="${ac_tool_prefix}strip"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-IFS=$as_save_IFS
-
-fi
-fi
-STRIP=$ac_cv_prog_STRIP
-if test -n "$STRIP"; then
-  { echo "$as_me:$LINENO: result: $STRIP" >&5
-echo "${ECHO_T}$STRIP" >&6; }
-else
-  { echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6; }
-fi
-
-
-fi
-if test -z "$ac_cv_prog_STRIP"; then
-  ac_ct_STRIP=$STRIP
-  # Extract the first word of "strip", so it can be a program name with args.
-set dummy strip; ac_word=$2
-{ echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; }
-if test "${ac_cv_prog_ac_ct_STRIP+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_STRIP"; then
-  ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; }; then
-    ac_cv_prog_ac_ct_STRIP="strip"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-IFS=$as_save_IFS
-
-fi
-fi
-ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP
-if test -n "$ac_ct_STRIP"; then
-  { echo "$as_me:$LINENO: result: $ac_ct_STRIP" >&5
-echo "${ECHO_T}$ac_ct_STRIP" >&6; }
-else
-  { echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6; }
-fi
-
-  if test "x$ac_ct_STRIP" = x; then
-    STRIP="false"
-  else
-    case $cross_compiling:$ac_tool_warned in
-yes:)
-{ echo "$as_me:$LINENO: WARNING: In the future, Autoconf will not detect cross-tools
-whose name does not start with the host triplet.  If you think this
-configuration is useful to you, please write to autoconf at gnu.org." >&5
-echo "$as_me: WARNING: In the future, Autoconf will not detect cross-tools
-whose name does not start with the host triplet.  If you think this
-configuration is useful to you, please write to autoconf at gnu.org." >&2;}
-ac_tool_warned=yes ;;
-esac
-    STRIP=$ac_ct_STRIP
-  fi
-else
-  STRIP="$ac_cv_prog_STRIP"
-fi
-
 # Extract the first word of "rm", so it can be a program name with args.
 set dummy rm; ac_word=$2
 { echo "$as_me:$LINENO: checking for $ac_word" >&5
@@ -10557,7 +10460,7 @@
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<EOF
-#line 10560 "configure"
+#line 10463 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -22027,7 +21930,6 @@
 MV!$MV$ac_delim
 RANLIB!$RANLIB$ac_delim
 AR!$AR$ac_delim
-STRIP!$STRIP$ac_delim
 RM!$RM$ac_delim
 SED!$SED$ac_delim
 TAR!$TAR$ac_delim
@@ -22097,7 +21999,7 @@
 LTLIBOBJS!$LTLIBOBJS$ac_delim
 _ACEOF
 
-  if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 90; then
+  if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 89; then
     break
   elif $ac_last_try; then
     { { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5



From echristo at apple.com  Tue Oct 25 21:47:11 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 25 Oct 2011 19:47:11 -0700
Subject: [llvm-commits] [llvm] r143009 - in /llvm/trunk:
 Makefile.config.in Makefile.rules autoconf/configure.ac configure
In-Reply-To: <20111026022832.B6DA1312800A@llvm.org>
References: <20111026022832.B6DA1312800A@llvm.org>
Message-ID: <46A0A8FA-D995-47CA-93AD-8B5C97CA1615@apple.com>


On Oct 25, 2011, at 7:28 PM, Charles Davis wrote:

> Revert 142997. It doesn't work on Mac OS or the BSDs, which all use the BSD
> version of the install program, which does not have the --strip-program
> switch.

Thanks.

At least now we know why gnu install has --strip-program

Hrm.

-eric
-------------- next part --------------
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URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111025/6aa9d755/attachment.html 

From hfinkel at anl.gov  Tue Oct 25 21:51:28 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Tue, 25 Oct 2011 21:51:28 -0500
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <1319577782.6498.6360.camel@sapling>
References: <1319231089.6498.6223.camel@sapling>
	<1319577782.6498.6360.camel@sapling>
Message-ID: <1319597488.6498.6416.camel@sapling>

On Tue, 2011-10-25 at 16:23 -0500, Hal Finkel wrote:
> I've attached an improved version of the autovectorization pass. This
> version will also vectorize loads and stores, casts, and some intrinsics
> (fma and trig. functions).
> 
> There are, correspondingly, a few new options:
> bb-vectorize-no-casts -- Don't try to vectorize casting (conversion)
> operations
> bb-vectorize-no-math -- Don't try to vectorize floating-point math
> intrinsics (this is just the trig. functions right now)
> bb-vectorize-no-fma -- Don't try to vectorize the fused-multiply-add
> intrinsic
> bb-vectorize-no-mem-ops -- Don't try to vectorize loads and stores
> bb-vectorize-aligned-only -- Only generate aligned loads and stores
> 
> To make this really useful, there are some improvements necessary to
> InstCombine (and a few other things).

As it turns out, the situation with instruction combination is not bad;
you just need to make sure that instcombine is run after the
vectorizer. In other words, run "opt -bb-vectorize -std-compile-opts"
instead of "opt -std-compile-opts -bb-vectorize". [Is there currently a
way that a pass can request that another pass be run after it?]

 -Hal

> But the autovectorization process
> itself now seems to work well. Please review this patch; adding the
> vectorization pass itself should not affect any other code (although it
> does touch some common files to add support for the pass into opt). If
> it looks okay, please let me know, and I'll commit it.
> 
> Thanks in advance,
> Hal
> 
> On Fri, 2011-10-21 at 16:04 -0500, Hal Finkel wrote:
> > I've attached an initial version of a basic-block autovectorization
> > pass. It works by searching a basic block for pairable (independent)
> > instructions, and, using a chain-seeking heuristic, selects pairings
> > likely to provide an overall speedup (if such pairings can be found).
> > The selected pairs are then fused and, if necessary, other instructions
> > are moved in order to maintain data-flow consistency. This works only
> > within one basic block, but can do loop vectorization in combination
> > with (partial) unrolling. The basic idea was inspired by the Vienna MAP
> > Vectorizor, which has been used to vectorize FFT kernels, but the
> > algorithm used here is different.
> > 
> > To try it, use -bb-vectorize with opt. There are a few options:
> > -bb-vectorize-req-chain-depth: default: 3 -- The depth of the chain of
> > instruction pairs necessary in order to consider the pairs that compose
> > the chain worthy of vectorization.
> > -bb-vectorize-vector-bits: default: 128 -- The size of the target vector
> > registers
> > -bb-vectorize-no-ints -- Don't consider integer instructions
> > -bb-vectorize-no-floats -- Don't consider floating-point instructions  
> > 
> > The vectorizor generates a lot of insert_element/extract_element pairs;
> > The assumption is that other passes will turn these into shuffles when
> > possible (it looks like some work is necessary here). It will also
> > vectorize vector instructions, and generates shuffles in this case
> > (again, other passes should combine these as appropriate).
> > 
> > Currently, it does not fuse load or store instructions, but that is a
> > feature that I'd like to add. Of course, alignment information is an
> > issue for load/store vectorization (or maybe I should just fuse them
> > anyway and let isel deal with unaligned cases?).
> > 
> > Also, support needs to be added for fusing known intrinsics (fma, etc.),
> > and, as has been discussed on llvmdev, we should add some intrinsics to
> > allow the generation of addsub-type instructions.
> > 
> > I've included a few tests, but it needs more. Please review (I'll commit
> > if and when everyone is happy).
> > 
> > Thanks in advance,
> > Hal
> > 
> > P.S. There is another option (not so useful right now, but could be):
> > -bb-vectorize-fast-dep -- Don't do a full inter-instruction dependency
> > analysis; instead stop looking for instruction pairs after the first use
> > of an instruction's value. [This makes the pass faster, but would
> > require a data-dependence-based reordering pass in order to be
> > effective].
> > 
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From bruno.cardoso at gmail.com  Tue Oct 25 22:08:04 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 26 Oct 2011 01:08:04 -0200
Subject: [llvm-commits] [PATCH][Review request] Mips direct object
	generation patch #5 of 6
In-Reply-To: <86AC779C188FE74F88F6494478B46332E82DD8@exchdb03.mips.com>
References: <86AC779C188FE74F88F6494478B46332E82DD8@exchdb03.mips.com>
Message-ID: <CACk9FxbBQJCa86=+v0A4mHj0tEFmR=tXf7sOqo--jWF7SyxAxQ@mail.gmail.com>

Hi,

On Tue, Oct 25, 2011 at 10:24 PM, Carter, Jack <jcarter at mips.com> wrote:
> This is the fifth of 6 patches for Mips direct object generation.
>
> ??? lib/Target/Mips/MipsAsmPrinter.cpp
>
> The patch is attached.
>
> Jack

+      return;
+    }

Since you use "return" above, remove the "else" below.

+    else if (Opc == Mips::CPRESTORE) {
+      MCInstLowering.LowerCPRESTORE(MI, TmpInst0);
+      OutStreamer.EmitInstruction(TmpInst0);
+      return;
+    }
+  }

LGTM!

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From nicholas at mxc.ca  Tue Oct 25 22:40:27 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 25 Oct 2011 20:40:27 -0700
Subject: [llvm-commits] [llvm] r142896 - in /llvm/trunk/test/Bitcode:
 sse42_crc32.ll sse42_crc32.ll.bc ssse3_palignr.ll ssse3_palignr.ll.bc
In-Reply-To: <1ECBC53E-D20D-4FA0-8C9D-6A52434D2B17@apple.com>
References: <20111025012220.6FCB0312800A@llvm.org>	<6D6DA0D2-AAC9-4EB9-8373-AA35B5667071@apple.com>
	<1ECBC53E-D20D-4FA0-8C9D-6A52434D2B17@apple.com>
Message-ID: <4EA7812B.1010507@mxc.ca>

Chad Rosier wrote:
> My long term goal is to preserve the Value use-lists ordering across bitcode writing/reading

Excellent! How?

Nick

From echristo at apple.com  Tue Oct 25 22:47:16 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 26 Oct 2011 03:47:16 -0000
Subject: [llvm-commits] [llvm] r143011 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20111026034717.0AB8F312800A@llvm.org>

Author: echristo
Date: Tue Oct 25 22:47:16 2011
New Revision: 143011

URL: http://llvm.org/viewvc/llvm-project?rev=143011&view=rev
Log:
Remove unused variable.

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=143011&r1=143010&r2=143011&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Tue Oct 25 22:47:16 2011
@@ -793,7 +793,6 @@
   InMemoryStruct<macho::RelocationEntry> RE;
   getRelocation(Rel, RE);
 
-  bool isPCRel = (RE->Word1 >> 25) & 1;
   unsigned Type = (RE->Word1 >> 28) & 0xF;
 
   std::string fmtbuf;



From isanbard at gmail.com  Tue Oct 25 23:24:15 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 04:24:15 -0000
Subject: [llvm-commits] [llvm] r143012 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026042415.6D798312800A@llvm.org>

Author: void
Date: Tue Oct 25 23:24:15 2011
New Revision: 143012

URL: http://llvm.org/viewvc/llvm-project?rev=143012&view=rev
Log:
Fix grammar.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143012&r1=143011&r2=143012&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Oct 25 23:24:15 2011
@@ -350,7 +350,7 @@
 <div>
 
 <p><a href="http://botwars.tk/gwscript/">gwXscript</a> is an object oriented,
-   aspect orientied programing language which can create both, executables (ELF,
+   aspect oriented programming language which can create both executables (ELF,
    EXE) and shared libraries (DLL, SO, DYNLIB). The compiler is implemented in
    its own language and translates scripts into LLVM-IR which can be optimized
    and translated into native code by the LLVM framework. Source code in



From atrick at apple.com  Wed Oct 26 01:18:36 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 25 Oct 2011 23:18:36 -0700
Subject: [llvm-commits] [llvm] r142743 - in /llvm/trunk:
 lib/CodeGen/MachineBlockPlacement.cpp test/CodeGen/X86/block-placement.ll
In-Reply-To: <20111023091845.40B6F3524006@llvm.org>
References: <20111023091845.40B6F3524006@llvm.org>
Message-ID: <55AF1F03-232E-4AD1-9FAE-43285BBC89DE@apple.com>


On Oct 23, 2011, at 2:18 AM, Chandler Carruth wrote:

> Author: chandlerc
> Date: Sun Oct 23 04:18:45 2011
> New Revision: 142743
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=142743&view=rev
> Log:
> Completely re-write the algorithm behind MachineBlockPlacement based on
> discussions with Andy. Fundamentally, the previous algorithm is both
> counter productive on several fronts and prioritizing things which
> aren't necessarily the most important: static branch prediction.
> 
> The new algorithm uses the existing loop CFG structure information to
> walk through the CFG itself to layout blocks. It coalesces adjacent
> blocks within the loop where the CFG allows based on the most likely
> path taken. Finally, it topologically orders the block chains that have
> been formed. This allows it to choose a (mostly) topologically valid
> ordering which still priorizes fallthrough within the structural
> constraints.
> 
> As a final twist in the algorithm, it does violate the CFG when it
> discovers a "hot" edge, that is an edge that is more than 4x hotter than
> the competing edges in the CFG. These are forcibly merged into
> a fallthrough chain.
> 
> Future transformations that need te be added are rotation of loop exit
> conditions to be fallthrough, and better isolation of cold block chains.
> I'm also planning on adding statistics to model how well the algorithm
> does at laying out blocks based on the probabilities it receives.
> 
> The old tests mostly still pass, and I have some new tests to add, but
> the nested loops are still behaving very strangely. This almost seems
> like working-as-intended as it rotated the exit branch to be
> fallthrough, but I'm not convinced this is actually the best layout. It
> is well supported by the probabilities for loops we currently get, but
> those are pretty broken for nested loops, so this may change later.
> 
> Modified:
>    llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
>    llvm/trunk/test/CodeGen/X86/block-placement.ll

Hi Chandler,

Sorry, I've been neglecting this a bit. My initial impression of your
current design is that the framework is good and the intention of the
algorithm is good, but placeChainsTopogically could do a better job in
few areas (1) biasing "warm" edges, (2) placing "cold" chains, (3)
loop handling.

(1) "Warm" edges are those that cross chains, and whose successor is
the head of a chain. In other words, you've decided to place the
chains "in-line" in topological order. Placing them in any arbitrary
topological/RPO order is not bad at all since you've already chosen
good chains. But consider a merge point with three or more
predecessors. You actually want the most frequent predecessor to fall
through to the merge, unless the head of that chain dominates the
other predecessors. This is tricky, rife with corner cases, and
probably not too important, especially without perfect profile
information. So it would be fair to punt on this issue.

(2) "Cold" edges branch into the middle of another chain. But it looks
like placeChainsTopogically happily follows the RPO order of the
chain's head. I'm guessing they'll end up in strange places unrelated
to their adjacent chains. This doesn't seem like what you intended. If
you avoid placing those in RPO order, then they should float down to
the end of the function.

(3) I've always thought we would regret that LoopInfo doesn't keep
it's list of blocks in RPO order. You're currently sidestepping the
issue by placing chains in a single iteration through the function's
blocks. If that works well, I don't have a problem with it, but it
seems to complicate the issue of loop layout. For example, our simple
RPO iterator makes no attempt to visit blocks in loop order, so
following this order will not result in contiguous loops. I think
laying out one loop at a time is much easier to deal with. If you want
to follow blocks within a loop in RPO order, you can use the
LoopIterator that I recently added for this purpose. It does need to
be adapted for MachineLoopInfo. I actually like the BranchProbability
approach of implementing the generic code in an implementation header
that's only included once per instantiation
(BranchProbabilityInfo.cpp + MachineBranchProbabilityInfo.cpp).

Another alternative is to do the topological sort without relying on
DFS. This can be done using a worklist of valid blocks. You need to
attach a "remaining predecessor" counter to each block. When all preds
have been laid out (or pushed out-of-line), the block can be pushed on
the valid queue. This might provide the freedom you need to implement
better profile-based heuristics, but could also result in more
arbitrary shuffling of blocks in the absence of good heuristics for
picking the next candidate. In other words, it could be the basis of a
solution to both the "warm" layout problem, and loop handling, but you
have an additional problem of choosing a "valid" block that is somehow
related to the last block that was laid out. I supposed you could just
sort the chains within the valid set similar to how you sorted the
full chain list in the Pettis & Hansen prototype. I think it's an
interesting idea, but haven't completely thought through it.

Another thing to keep in mind: where the profile doesn't indicate
otherwise, it's not a bad idea to preserve the incoming layout. So if
you have cases where the algorithm can't make a good choice, falling
back on the current layout within some region is a way to avoid making
things worse.

Implementation Details:

Do you think it's important to keep a vector of blocks inside each
chain, as opposed to incrementally updating the existing ilist and
storing pointers to the chain head and tail? AFAIK, you can reorder
the blocks all you want then update terminators later, but I could be
wrong. Either way, chain merge can't be constant time because of the
BlockChain map update. But you could avoid regrowing a lot of
vectors. Along those lines, if you ever decide to use union-find, we
have IntEqClasses.

Should we have an inline version of getEdgeProbability() that simply
returns BranchProbability::getOne() for single-successor blocks?

-Andy

From anton at korobeynikov.info  Wed Oct 26 01:47:06 2011
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Wed, 26 Oct 2011 10:47:06 +0400
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
References: <20111019141108.15BB73128018@llvm.org>
	<8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
Message-ID: <CA+Ov9+nnS-aj3c=WaMczTD_Z7iqibhC5DqzktzRHbfcATznPbQ@mail.gmail.com>

Hi Evan,

> 1. Note -Os for LLVM, especially for Darwin, means reduce code size without hurting performance.
It seems to be -Os vs -Oz problem - we cannot distinguish between two
of them at IR level, for example.

> Please check with me before making changes that can impact Darwin codegen in the future. We can continue the discussion, but I'm going revert the change for Darwin.
I don't think Darwin is something special here, so, most probably the
patch should be reverted as a whole and we can continue the
discussion.
James, will you please do this?

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

From eli.friedman at gmail.com  Wed Oct 26 02:04:15 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 26 Oct 2011 00:04:15 -0700
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
References: <20111019141108.15BB73128018@llvm.org>
	<8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
Message-ID: <CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>

On Tue, Oct 25, 2011 at 6:08 PM, Evan Cheng <evan.cheng at apple.com> wrote:
> 2. Where is code size saving from? You are talking about movw + movt vs. ldr + a constantpool entry.

movw+movt is 8 bytes, ldr+constantpool entry is roughly 6 bytes.

-Eli

From anton at korobeynikov.info  Wed Oct 26 02:12:05 2011
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Wed, 26 Oct 2011 11:12:05 +0400
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>
References: <20111019141108.15BB73128018@llvm.org>
	<8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
	<CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>
Message-ID: <CA+Ov9+krA4yc8mvBGbWSYCgaNMOtMTMA7SYsthtRny2Rp0uoCQ@mail.gmail.com>

> On Tue, Oct 25, 2011 at 6:08 PM, Evan Cheng <evan.cheng at apple.com> wrote:
>> 2. Where is code size saving from? You are talking about movw + movt vs. ldr + a constantpool entry.
> movw+movt is 8 bytes, ldr+constantpool entry is roughly 6 bytes.
Yes. That's why I asked James to present the results of something big
(gcc from SPEC in this case) so the code save size would be clearly
visible.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

From isanbard at gmail.com  Wed Oct 26 02:16:18 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 07:16:18 -0000
Subject: [llvm-commits] [llvm] r143018 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20111026071618.5E9A0312800A@llvm.org>

Author: void
Date: Wed Oct 26 02:16:18 2011
New Revision: 143018

URL: http://llvm.org/viewvc/llvm-project?rev=143018&view=rev
Log:
Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=143018&r1=143017&r2=143018&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Oct 26 02:16:18 2011
@@ -5996,9 +5996,10 @@
 
     // Remove the landing pad successor from the invoke block and replace it
     // with the new dispatch block.
-    for (MachineBasicBlock::succ_iterator
-           SI = BB->succ_begin(), SE = BB->succ_end(); SI != SE; ++SI) {
-      MachineBasicBlock *SMBB = *SI;
+    SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
+                                                  BB->succ_end());
+    while (!Successors.empty()) {
+      MachineBasicBlock *SMBB = Successors.pop_back_val();
       if (SMBB->isLandingPad()) {
         BB->removeSuccessor(SMBB);
         MBBLPads.push_back(SMBB);



From james.molloy at arm.com  Wed Oct 26 02:23:31 2011
From: james.molloy at arm.com (James Molloy)
Date: Wed, 26 Oct 2011 08:23:31 +0100
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
	lib/Target/ARM/ARMISelLowering.cpp
	test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>
References: <20111019141108.15BB73128018@llvm.org>	<8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
	<CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>
Message-ID: <003301cc93b0$2a200350$7e6009f0$@molloy@arm.com>

Quite - even less if you can reuse constant pool entries.

James

-----Original Message-----
From: Eli Friedman [mailto:eli.friedman at gmail.com] 
Sent: 26 October 2011 08:04
To: Evan Cheng
Cc: James Molloy; llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
lib/Target/ARM/ARMISelLowering.cpp
test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll

On Tue, Oct 25, 2011 at 6:08 PM, Evan Cheng <evan.cheng at apple.com> wrote:
> 2. Where is code size saving from? You are talking about movw + movt vs.
ldr + a constantpool entry.

movw+movt is 8 bytes, ldr+constantpool entry is roughly 6 bytes.

-Eli






From baldrick at free.fr  Wed Oct 26 02:36:12 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 26 Oct 2011 09:36:12 +0200
Subject: [llvm-commits] [llvm] r142992 - in /llvm/trunk:
 lib/VMCore/Instructions.cpp test/Bitcode/shuffle.ll
In-Reply-To: <20111026003448.41B96312800A@llvm.org>
References: <20111026003448.41B96312800A@llvm.org>
Message-ID: <4EA7B86C.5090103@free.fr>

Hi,

> The bitcode reader can create an shuffle with a place holder mask which it will
> fix up later. For this special case, allow such a mask to be considered valid.
> <rdar://problem/8622574>

why does it create a placeholder - is it really needed?  I mean, I don't see any
other special casing of UserOp in Instructions.cpp, so it seems that no other
instructions do this - in which case what makes shufflevector different?  Also,
if you do follow this route, maybe you can have the verifier check that the
mask is really valid (no UserOp1).  This would catch bugs in which the
placeholder leaked out of the bitcode reader somehow.

Ciao, Duncan.

>
> Added:
>      llvm/trunk/test/Bitcode/shuffle.ll
> Modified:
>      llvm/trunk/lib/VMCore/Instructions.cpp
>
> Modified: llvm/trunk/lib/VMCore/Instructions.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=142992&r1=142991&r2=142992&view=diff
> ==============================================================================
> --- llvm/trunk/lib/VMCore/Instructions.cpp (original)
> +++ llvm/trunk/lib/VMCore/Instructions.cpp Tue Oct 25 19:34:48 2011
> @@ -1576,10 +1576,17 @@
>           return false;
>         }
>       }
> -  }
> -  else if (!isa<UndefValue>(Mask)&&  !isa<ConstantAggregateZero>(Mask))
> +  } else if (!isa<UndefValue>(Mask)&&  !isa<ConstantAggregateZero>(Mask)) {
> +    // The bitcode reader can create a place holder for a forward reference
> +    // used as the shuffle mask. When this occurs, the shuffle mask will
> +    // fall into this case and fail. To avoid this error, do this bit of
> +    // ugliness to allow such a mask pass.
> +    if (const ConstantExpr* CE = dyn_cast<ConstantExpr>(Mask)) {
> +      if (CE->getOpcode() == Instruction::UserOp1)
> +        return true;
> +    }
>       return false;
> -
> +  }
>     return true;
>   }
>
>
> Added: llvm/trunk/test/Bitcode/shuffle.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/shuffle.ll?rev=142992&view=auto
> ==============================================================================
> --- llvm/trunk/test/Bitcode/shuffle.ll (added)
> +++ llvm/trunk/test/Bitcode/shuffle.ll Tue Oct 25 19:34:48 2011
> @@ -0,0 +1,31 @@
> +; RUN: llvm-as<  %s | llvm-dis
> +
> +;<rdar://problem/8622574>
> +; tests the bitcodereader can handle the case where the reader will initially
> +; create shuffle with a place holder mask.
> +
> +
> +define<4 x float>  @test(<2 x double>  %d2)  {
> +entry:
> +  %call20.i = tail call<4 x float>  @cmp(<2 x double>  %d2,
> +<2 x double>  bitcast (
> +<4 x float>  shufflevector (
> +<3 x float>  shufflevector (
> +<4 x float>  shufflevector (
> +<3 x float>  bitcast (
> +                                                  i96 trunc (
> +                                                    i128 bitcast (<2 x double>  bitcast (
> +<4 x i32>  <i32 0, i32 0, i32 0, i32 undef>  to<2 x double>)
> +                                                    to i128) to i96)
> +                                                  to<3 x float>),
> +<3 x float>  undef,
> +<4 x i32>  <i32 0, i32 1, i32 2, i32 undef>),
> +<4 x float>  undef,
> +<3 x i32>  <i32 0, i32 1, i32 2>),
> +<3 x float>  undef,
> +<4 x i32>  <i32 0, i32 1, i32 2, i32 undef>)
> +                                          to<2 x double>))
> +  ret<4 x float>  %call20.i
> +}
> +
> +declare<4 x float>  @cmp(<2 x double>,<2 x double>)
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From james.molloy at arm.com  Wed Oct 26 02:37:58 2011
From: james.molloy at arm.com (James Molloy)
Date: Wed, 26 Oct 2011 08:37:58 +0100
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
	lib/Target/ARM/ARMISelLowering.cpp
	test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <CA+Ov9+krA4yc8mvBGbWSYCgaNMOtMTMA7SYsthtRny2Rp0uoCQ@mail.gmail.com>
References: <20111019141108.15BB73128018@llvm.org>	<8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>	<CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>
	<CA+Ov9+krA4yc8mvBGbWSYCgaNMOtMTMA7SYsthtRny2Rp0uoCQ@mail.gmail.com>
Message-ID: <003401cc93b2$2f4c40d0$8de4c270$@molloy@arm.com>

Hi Anton, Eli, Evan,

I'm reverting the patch now, at least temporarily (just running a build to
ensure it doesn't break anything).

The patch gave a 5% codesize drop on SPEC.gcc, and I've already had a
request from a user to try and remove more MOVW/MOVT pairs generated
elsewhere in the codebase. *Size does matter* to some people, us included.

I personally think LLVM has rather a crude mechanism for defining size-based
optimizations. How hard do you want to optimize - where is your tradeoff?
-Os/-Oz go some way towards this, but there is no way to check which has
been asked for.

I think we need to sort out what to do for these kind of optimizations now -
there are people and cores (Cortex-M/R class for example) where codesize
does matter massively, and for M/R series processors the MOVW/MOVT pair may
well be slower.

I also heavily dislike the Darwin-specific stuff in the backend and the
whole idea of "We don't want to do this for Darwin" - if something is a
negative tradeoff, have an appropriate target-independent knob that can be
turned to a different position for Darwin.

Cheers,

James

-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu
[mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Anton Korobeynikov
Sent: 26 October 2011 08:12
To: Eli Friedman
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
lib/Target/ARM/ARMISelLowering.cpp
test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll

> On Tue, Oct 25, 2011 at 6:08 PM, Evan Cheng <evan.cheng at apple.com> wrote:
>> 2. Where is code size saving from? You are talking about movw + movt vs.
ldr + a constantpool entry.
> movw+movt is 8 bytes, ldr+constantpool entry is roughly 6 bytes.
Yes. That's why I asked James to present the results of something big
(gcc from SPEC in this case) so the code save size would be clearly
visible.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University
_______________________________________________
llvm-commits mailing list
llvm-commits at cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits






From baldrick at free.fr  Wed Oct 26 02:38:46 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 26 Oct 2011 09:38:46 +0200
Subject: [llvm-commits] [llvm] r143001
	-	/llvm/trunk/lib/CodeGen/BranchFolding.cpp
In-Reply-To: <20111026011025.ED72D312800A@llvm.org>
References: <20111026011025.ED72D312800A@llvm.org>
Message-ID: <4EA7B906.40304@free.fr>

Hi Bill,

> Reapply r142920 with fix:
>
> An MBB which branches to an EH landing pad shouldn't be considered for tail merging.
>
> In SjLj EH, the jump to the landing pad is not done explicitly through a branch
> statement. The EH landing pad is added as a successor to the throwing
> BB. Because of that however, the branch folding pass could mistakenly think that
> it could merge the throwing BB with another BB. This isn't safe to do.
> <rdar://problem/10334833>

testcase?

Ciao, Duncan.

From isanbard at gmail.com  Wed Oct 26 02:38:19 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 07:38:19 -0000
Subject: [llvm-commits] [llvm] r143020 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026073819.97A12312800A@llvm.org>

Author: void
Date: Wed Oct 26 02:38:19 2011
New Revision: 143020

URL: http://llvm.org/viewvc/llvm-project?rev=143020&view=rev
Log:
Add the Stupid D Compiler to the External Projects list.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143020&r1=143019&r2=143020&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Wed Oct 26 02:38:19 2011
@@ -452,6 +452,17 @@
 </div>
 
 <!--=========================================================================-->
+<h3>The Stupid D Compiler (SDC)</h3>
+
+<div>
+
+<p><a href="https://github.com/bhelyer/SDC">The Stupid D Compiler</a> is a
+   project seeking to write a self-hosting compiler for the D programming
+   language without using the frontend of the reference compiler (DMD).</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>TTA-based Co-design Environment (TCE)</h3>
 
 <div>



From isanbard at gmail.com  Wed Oct 26 02:42:45 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 07:42:45 -0000
Subject: [llvm-commits] [llvm] r143022 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026074245.B3F25312800A@llvm.org>

Author: void
Date: Wed Oct 26 02:42:45 2011
New Revision: 143022

URL: http://llvm.org/viewvc/llvm-project?rev=143022&view=rev
Log:
Add ZooLib to the External Projects list.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143022&r1=143021&r2=143022&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Wed Oct 26 02:42:45 2011
@@ -503,6 +503,24 @@
 </div>
 
 <!--=========================================================================-->
+<h3>The ZooLib C++ Cross-Platform Application Framework</h3>
+
+<div>
+
+<p><a href="http://www.zoolib.org/">ZooLib</a> is Open Source under the MIT
+   License. It provides GUI, filesystem access, TCP networking, thread-safe
+   memory management, threading and locking for Mac OS X, Classic Mac OS,
+   Microsoft Windows, POSIX operating systems with X11, BeOS, Haiku, Apple's iOS
+   and Research in Motion's BlackBerry.</p>
+
+<p>My current work is to use CLang's static analyzer to improve ZooLib's code
+   quality.  I also plan to set up LLVM compiles of the demo programs and test
+   programs using CLang and LLVM on all the platforms that CLang, LLVM and
+   ZooLib all support.</p>
+
+</div>
+
+<!--=========================================================================-->
 <!--
 <h3>PinaVM</h3>
   



From chandlerc at gmail.com  Wed Oct 26 03:13:19 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Wed, 26 Oct 2011 01:13:19 -0700
Subject: [llvm-commits] [llvm] r142743 - in /llvm/trunk:
 lib/CodeGen/MachineBlockPlacement.cpp test/CodeGen/X86/block-placement.ll
In-Reply-To: <55AF1F03-232E-4AD1-9FAE-43285BBC89DE@apple.com>
References: <20111023091845.40B6F3524006@llvm.org>
	<55AF1F03-232E-4AD1-9FAE-43285BBC89DE@apple.com>
Message-ID: <CAGCO0Ki2FvFfu7gUf+TVuq5PYxGPDJ76iypq9ztO-ex93n7s-w@mail.gmail.com>

Just a brief note at the moment, I'll dig into this more deeply hopefully
soon.

On Tue, Oct 25, 2011 at 11:18 PM, Andrew Trick <atrick at apple.com> wrote:

> Sorry, I've been neglecting this a bit. My initial impression of your
> current design is that the framework is good and the intention of the
> algorithm is good, but placeChainsTopogically could do a better job in
> few areas (1) biasing "warm" edges, (2) placing "cold" chains, (3)
> loop handling.
>

For reference, I couldn't agree more with the assessment. It's exactly the
conclusion I came to. However, it got far enough that the problems with our
probability heuristics became quite painful. I'm working on making those
better while mulling over some of the very issues you highlight.


> (1) "Warm" edges are those that cross chains, and whose successor is
> the head of a chain. In other words, you've decided to place the
> chains "in-line" in topological order. Placing them in any arbitrary
> topological/RPO order is not bad at all since you've already chosen
> good chains. But consider a merge point with three or more
> predecessors. You actually want the most frequent predecessor to fall
> through to the merge, unless the head of that chain dominates the
> other predecessors. This is tricky, rife with corner cases, and
> probably not too important, especially without perfect profile
> information. So it would be fair to punt on this issue.
>
> (2) "Cold" edges branch into the middle of another chain. But it looks
> like placeChainsTopogically happily follows the RPO order of the
> chain's head. I'm guessing they'll end up in strange places unrelated
> to their adjacent chains. This doesn't seem like what you intended. If
> you avoid placing those in RPO order, then they should float down to
> the end of the function.
>

Yea, the way #1 (and to an extent #2) work currently is that we merge the
"best" successor with a particular block whenever it doesn't violate the
topological ordering, and when we see a particularly hot edge that does, we
"merge" it to force sequential layout. Then the cold chain ends up getting
inserted the next time we fail to merge. You're absolutely correct that this
isn't really great on either side.

Handling the cold chains is, I suspect, the easier of the two problems. I
just think we should have a completely separate layout mechanism for them
that runs after finishing the warm chain layout.

I'm still not 100% certain what the best approach is to ensure warm chain
layout is as good as it can be within the topological ordering... Going to
keep thinking here.


> (3) I've always thought we would regret that LoopInfo doesn't keep
> it's list of blocks in RPO order.


YES. I would greatly appreciate making an RPO order guarantee at the loop
info and/or function layer from an analysis that I can piggyback on. Doing
it at the loop layer would be wonderful for implementing this kind of
algorithm.


> You're currently sidestepping the
> issue by placing chains in a single iteration through the function's
> blocks. If that works well, I don't have a problem with it, but it
> seems to complicate the issue of loop layout. For example, our simple
> RPO iterator makes no attempt to visit blocks in loop order, so
> following this order will not result in contiguous loops. I think
> laying out one loop at a time is much easier to deal with. If you want
> to follow blocks within a loop in RPO order, you can use the
> LoopIterator that I recently added for this purpose. It does need to
> be adapted for MachineLoopInfo.


I'll look into LoopIterator. If it were to get adapted for MachineLoopInfo,
that would certainly help. =D

I wonder however, the Loop object already has a vector of BB*; it would seem
like it could just place that vector in RPO, and be done with it? Dunno, as
I've not looked at LoopIterator, etc.

I actually like the BranchProbability
> approach of implementing the generic code in an implementation header
> that's only included once per instantiation
> (BranchProbabilityInfo.cpp + MachineBranchProbabilityInfo.cpp).
>

I think you mean BlockFrequencyInfo, but yes I agree with the spirit here.
LoopInfo is already done this way, with generic templated base classes that
are specialized for MachineLoop* classes.


> Another alternative is to do the topological sort without relying on
> DFS. This can be done using a worklist of valid blocks. You need to
> attach a "remaining predecessor" counter to each block. When all preds
> have been laid out (or pushed out-of-line), the block can be pushed on
> the valid queue. This might provide the freedom you need to implement
> better profile-based heuristics, but could also result in more
> arbitrary shuffling of blocks in the absence of good heuristics for
> picking the next candidate. In other words, it could be the basis of a
> solution to both the "warm" layout problem, and loop handling, but you
> have an additional problem of choosing a "valid" block that is somehow
> related to the last block that was laid out. I supposed you could just
> sort the chains within the valid set similar to how you sorted the
> full chain list in the Pettis & Hansen prototype. I think it's an
> interesting idea, but haven't completely thought through it.
>

This is actually a really interesting approach. I'm going to think about it
more. Having a worklist would indeed simplify much, and as you mention
below, it shouldn't be hard to pull in the existing layout as a tie breaker
which won't introduce noise.

Implementation Details:
>
> Do you think it's important to keep a vector of blocks inside each
> chain, as opposed to incrementally updating the existing ilist and
> storing pointers to the chain head and tail? AFAIK, you can reorder
> the blocks all you want then update terminators later, but I could be
> wrong.


My first implementation did this, and I have to say I found it frought with
peril. Iterator invalidation is a nightmare here. Also, once you commit to
doing this, you loose the easy ability to check for the existing code layout
as a metric. As long as the merging occurs in a forward-moving algorithm,
and thus we append to block chains only, I suspect the vector approach will
be both simpler and not noticeably slower. There are already special cases
to avoid creating needless 1-block chains, and a small vector could be used
to further reduce malloc traffic. I just wanted to wait for a sad profile
before doing anything drastic.

Either way, chain merge can't be constant time because of the
> BlockChain map update. But you could avoid regrowing a lot of
> vectors. Along those lines, if you ever decide to use union-find, we
> have IntEqClasses.
>
> Should we have an inline version of getEdgeProbability() that simply
> returns BranchProbability::getOne() for single-successor blocks?


Probably. I'll look into to that as I clean up BranchProbability stuff.
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From james.molloy at arm.com  Wed Oct 26 03:53:19 2011
From: james.molloy at arm.com (James Molloy)
Date: Wed, 26 Oct 2011 08:53:19 -0000
Subject: [llvm-commits] [llvm] r143023 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
Message-ID: <20111026085319.6813F312800A@llvm.org>

Author: jamesm
Date: Wed Oct 26 03:53:19 2011
New Revision: 143023

URL: http://llvm.org/viewvc/llvm-project?rev=143023&view=rev
Log:
Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance.

Removed:
    llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=143023&r1=143022&r2=143023&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Oct 26 03:53:19 2011
@@ -2104,11 +2104,8 @@
   }
 
   // If we have T2 ops, we can materialize the address directly via movt/movw
-  // pair. This is always cheaper in terms of performance, but uses at least 2
-  // extra bytes.
-  MachineFunction &MF = DAG.getMachineFunction();
-  if (Subtarget->useMovt() &&
-      !MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) {
+  // pair. This is always cheaper.
+  if (Subtarget->useMovt()) {
     ++NumMovwMovt;
     // FIXME: Once remat is capable of dealing with instructions with register
     // operands, expand this into two nodes.

Removed: llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll?rev=143022&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll (removed)
@@ -1,26 +0,0 @@
-; RUN: llc < %s -mtriple=armv7-unknown-linux-eabi | FileCheck %s
-
-; Check that when optimizing for size, a literal pool load is used
-; instead of the (potentially faster) movw/movt pair when loading
-; a large constant.
-
- at x = global i32* inttoptr (i32 305419888 to i32*), align 4
-
-define i32 @f() optsize {
-  ; CHECK: f:
-  ; CHECK: ldr  r{{.}}, {{.?}}LCPI{{.}}_{{.}}
-  ; CHECK: ldr  r{{.}}, [{{(pc, )?}}r{{.}}]
-  ; CHECK: ldr  r{{.}}, [r{{.}}]
-  %1 = load i32** @x, align 4
-  %2 = load i32* %1
-  ret i32 %2
-}
-
-define i32 @g() {
-  ; CHECK: g:
-  ; CHECK: movw
-  ; CHECK: movt
-  %1 = load i32** @x, align 4
-  %2 = load i32* %1
-  ret i32 %2
-}



From isanbard at gmail.com  Wed Oct 26 04:25:01 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 09:25:01 -0000
Subject: [llvm-commits] [llvm] r143024 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026092501.B5574312800A@llvm.org>

Author: void
Date: Wed Oct 26 04:25:01 2011
New Revision: 143024

URL: http://llvm.org/viewvc/llvm-project?rev=143024&view=rev
Log:
Add ThreadSanitizer to the External Projects list.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143024&r1=143023&r2=143024&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Wed Oct 26 04:25:01 2011
@@ -503,6 +503,20 @@
 </div>
 
 <!--=========================================================================-->
+<h3>ThreadSanitizer</h3>
+
+<div>
+
+<p><a href="http://code.google.com/p/data-race-test/">ThreadSanitizer</a> is a
+   data race detector for (mostly) C and C++ code, available for Linux, Mac OS
+   and Windows. On different systems, we use binary instrumentation frameworks
+   (Valgrind, Pin and DynamoRio) as frontends that generate the program events
+   for the race detection algorithm. On Linux, there's an option of using
+   LLVM-based compile-time instrumentation.</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>The ZooLib C++ Cross-Platform Application Framework</h3>
 
 <div>



From stpworld at narod.ru  Wed Oct 26 05:21:31 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Wed, 26 Oct 2011 14:21:31 +0400
Subject: [llvm-commits] [LLVM,
	llvm-objdump] Fix for clang-native-arm-cortex-a9.
In-Reply-To: <4EA67DE3.8060803@narod.ru>
References: <4EA67DE3.8060803@narod.ru>
Message-ID: <4EA7DF2B.2070100@narod.ru>

ping.

Regards,
Stepan.

Stepan Dyatkovskiy wrote:
> Hi all,
>
> Please find the patch in attachment that fixes llvm-objdump test
> failures for clang-native-arm-cortex-a9.
>
> Regards,
> Stepan.
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From raghesh.a at gmail.com  Wed Oct 26 07:25:50 2011
From: raghesh.a at gmail.com (Raghesh Aloor)
Date: Wed, 26 Oct 2011 12:25:50 -0000
Subject: [llvm-commits] [polly] r143025 - /polly/trunk/www/get_started.html
Message-ID: <20111026122550.214AB312800A@llvm.org>

Author: raghesh
Date: Wed Oct 26 07:25:49 2011
New Revision: 143025

URL: http://llvm.org/viewvc/llvm-project?rev=143025&view=rev
Log:
www: Change in cloog installation procedure


Modified:
    polly/trunk/www/get_started.html

Modified: polly/trunk/www/get_started.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/get_started.html?rev=143025&r1=143024&r2=143025&view=diff
==============================================================================
--- polly/trunk/www/get_started.html (original)
+++ polly/trunk/www/get_started.html Wed Oct 26 07:25:49 2011
@@ -65,9 +65,11 @@
 <h4> First installation</h4>
 <pre>
 ${POLLY_SRC}/utils/checkout_cloog.sh ${CLOOG_SRC}
-${POLLY_SRC}/configure --prefix=${CLOOG_INSTALL}
+cd ${CLOOG_SRC}
+./configure --prefix=${CLOOG_INSTALL}
 make
 make install
+cd ${BASE}
 </pre>
 
 <h4> Update the installation</h4>
@@ -76,8 +78,10 @@
 only available in a recent version of CLooG.
 <pre>
 ${POLLY_SRC}/utils/checkout_cloog.sh ${CLOOG_SRC}
+cd ${CLOOG_SRC}
 make
 make install
+cd ${BASE}
 </pre>
 
 <h3> Install Pocc (Optional) </h3>



From baldrick at free.fr  Wed Oct 26 09:11:18 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 26 Oct 2011 14:11:18 -0000
Subject: [llvm-commits] [llvm] r143026 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Message-ID: <20111026141118.E4F20312800A@llvm.org>

Author: baldrick
Date: Wed Oct 26 09:11:18 2011
New Revision: 143026

URL: http://llvm.org/viewvc/llvm-project?rev=143026&view=rev
Log:
Simplify SplitVecRes_UnaryOp by removing all the code that is
trying to legalize the operand types when only the result type
is required to be legalized - the type legalization machinery
will get round to the operands later if they need legalizing.
There can be a point to legalizing operands in parallel with
the result: when this saves compile time or results in better
code.  There was only one case in which this was true: when
the operand is also split, so keep the logic for that bit.
As a result of this change, additional operand legalization
methods may need to be introduced to handle nodes where the
result and operand types can differ, like SIGN_EXTEND, but
the testsuite doesn't contain any tests where this is the case.
In any case, it seems better to require such methods (and die
with an assert if they doesn't exist) than to quietly produce
wrong code if we forgot to special case the node in
SplitVecRes_UnaryOp.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=143026&r1=143025&r2=143026&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Wed Oct 26 09:11:18 2011
@@ -773,56 +773,18 @@
   DebugLoc dl = N->getDebugLoc();
   GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
 
-  // Split the input.
+  // If the input also splits, handle it directly for a compile time speedup.
+  // Otherwise split it by hand.
   EVT InVT = N->getOperand(0).getValueType();
-  switch (getTypeAction(InVT)) {
-  default: llvm_unreachable("Unexpected type action!");
-  case TargetLowering::TypeLegal: {
+  if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
+    GetSplitVector(N->getOperand(0), Lo, Hi);
+  } else {
     EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
                                  LoVT.getVectorNumElements());
     Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
                      DAG.getIntPtrConstant(0));
     Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
                      DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
-    break;
-  }
-  case TargetLowering::TypePromoteInteger: {
-    SDValue InOp;
-    if (N->getOpcode() == ISD::SIGN_EXTEND ||
-        N->getOpcode() == ISD::SINT_TO_FP) {
-      InOp =   SExtPromotedInteger(N->getOperand(0));
-    } else if (
-        N->getOpcode() == ISD::ZERO_EXTEND ||
-        N->getOpcode() == ISD::UINT_TO_FP) {
-      InOp =   ZExtPromotedInteger(N->getOperand(0));
-    } else {
-      InOp = GetPromotedInteger(N->getOperand(0));
-    }
-    EVT InNVT = EVT::getVectorVT(*DAG.getContext(),
-                                 InOp.getValueType().getVectorElementType(),
-                                 LoVT.getVectorNumElements());
-    Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
-                     DAG.getIntPtrConstant(0));
-    Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
-                     DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
-    break;
-  }
-  case TargetLowering::TypeSplitVector:
-    GetSplitVector(N->getOperand(0), Lo, Hi);
-    break;
-  case TargetLowering::TypeWidenVector: {
-    // If the result needs to be split and the input needs to be widened,
-    // the two types must have different lengths. Use the widened result
-    // and extract from it to do the split.
-    SDValue InOp = GetWidenedVector(N->getOperand(0));
-    EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
-                                 LoVT.getVectorNumElements());
-    Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
-                     DAG.getIntPtrConstant(0));
-    Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
-                     DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
-    break;
-  }
   }
 
   if (N->getOpcode() == ISD::FP_ROUND) {



From baldrick at free.fr  Wed Oct 26 10:31:51 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 26 Oct 2011 15:31:51 -0000
Subject: [llvm-commits] [llvm] r143028 - in /llvm/trunk:
 lib/Analysis/ValueTracking.cpp test/Transforms/InstSimplify/compare.ll
Message-ID: <20111026153151.C3D4E312800A@llvm.org>

Author: baldrick
Date: Wed Oct 26 10:31:51 2011
New Revision: 143028

URL: http://llvm.org/viewvc/llvm-project?rev=143028&view=rev
Log:
My super-optimizer noticed that we weren't folding this expression to
true: (x *nsw x) sgt 0, where x = (y | 1).  This occurs in 464.h264ref.

Modified:
    llvm/trunk/lib/Analysis/ValueTracking.cpp
    llvm/trunk/test/Transforms/InstSimplify/compare.ll

Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=143028&r1=143027&r2=143028&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Wed Oct 26 10:31:51 2011
@@ -201,9 +201,36 @@
     ComputeMaskedBits(I->getOperand(1), Mask2, KnownZero, KnownOne, TD,Depth+1);
     ComputeMaskedBits(I->getOperand(0), Mask2, KnownZero2, KnownOne2, TD,
                       Depth+1);
-    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 
-    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 
-    
+    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+
+    bool isKnownNegative = false;
+    bool isKnownNonNegative = false;
+    // If the multiplication is known not to overflow, compute the sign bit.
+    if (Mask.isNegative() && cast<BinaryOperator>(I)->hasNoSignedWrap()) {
+      Value *Op1 = I->getOperand(1), *Op2 = I->getOperand(0);
+      if (Op1 == Op2) {
+        // The product of a number with itself is non-negative.
+        isKnownNonNegative = true;
+      } else {
+        bool isKnownNonNegative1 = KnownZero.isNegative();
+        bool isKnownNonNegative2 = KnownZero2.isNegative();
+        bool isKnownNegative1 = KnownOne.isNegative();
+        bool isKnownNegative2 = KnownOne2.isNegative();
+        // The product of two numbers with the same sign is non-negative.
+        isKnownNonNegative = (isKnownNegative1 && isKnownNegative2) ||
+          (isKnownNonNegative1 && isKnownNonNegative2);
+        // The product of a negative number and a non-negative number is either
+        // negative or zero.
+        isKnownNegative = (isKnownNegative1 && isKnownNonNegative2 &&
+                           isKnownNonZero(Op2, TD, Depth)) ||
+                          (isKnownNegative2 && isKnownNonNegative1 &&
+                           isKnownNonZero(Op1, TD, Depth));
+        assert(!(isKnownNegative && isKnownNonNegative) &&
+               "Sign bit both zero and one?");
+      }
+    }
+
     // If low bits are zero in either operand, output low known-0 bits.
     // Also compute a conserative estimate for high known-0 bits.
     // More trickiness is possible, but this is sufficient for the
@@ -220,6 +247,12 @@
     KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) |
                 APInt::getHighBitsSet(BitWidth, LeadZ);
     KnownZero &= Mask;
+
+    if (isKnownNonNegative)
+      KnownZero.setBit(BitWidth - 1);
+    else if (isKnownNegative)
+      KnownOne.setBit(BitWidth - 1);
+
     return;
   }
   case Instruction::UDiv: {
@@ -767,7 +800,7 @@
   }
 
   // The remaining tests are all recursive, so bail out if we hit the limit.
-  if (Depth++ == MaxDepth)
+  if (Depth++ >= MaxDepth)
     return false;
 
   unsigned BitWidth = getBitWidth(V->getType(), TD);
@@ -851,6 +884,15 @@
     if (YKnownNonNegative && isPowerOfTwo(X, TD, Depth))
       return true;
   }
+  // X * Y.
+  else if (match(V, m_Mul(m_Value(X), m_Value(Y)))) {
+    BinaryOperator *BO = cast<BinaryOperator>(V);
+    // If X and Y are non-zero then so is X * Y as long as the multiplication
+    // does not overflow.
+    if ((BO->hasNoSignedWrap() || BO->hasNoUnsignedWrap()) &&
+        isKnownNonZero(X, TD, Depth) && isKnownNonZero(Y, TD, Depth))
+      return true;
+  }
   // (C ? X : Y) != 0 if X != 0 and Y != 0.
   else if (SelectInst *SI = dyn_cast<SelectInst>(V)) {
     if (isKnownNonZero(SI->getTrueValue(), TD, Depth) &&

Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=143028&r1=143027&r2=143028&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Wed Oct 26 10:31:51 2011
@@ -323,3 +323,34 @@
   ret i1 %B
 ; CHECK: ret i1 false
 }
+
+define i1 @mul1(i32 %X) {
+; CHECK: @mul1
+; Square of a non-zero number is non-zero if there is no overflow.
+  %Y = or i32 %X, 1
+  %M = mul nuw i32 %Y, %Y
+  %C = icmp eq i32 %M, 0
+  ret i1 %C
+; CHECK: ret i1 false
+}
+
+define i1 @mul2(i32 %X) {
+; CHECK: @mul2
+; Square of a non-zero number is positive if there is no signed overflow.
+  %Y = or i32 %X, 1
+  %M = mul nsw i32 %Y, %Y
+  %C = icmp sgt i32 %M, 0
+  ret i1 %C
+; CHECK: ret i1 true
+}
+
+define i1 @mul3(i32 %X, i32 %Y) {
+; CHECK: @mul3
+; Product of non-negative numbers is non-negative if there is no signed overflow.
+  %XX = mul nsw i32 %X, %X
+  %YY = mul nsw i32 %Y, %Y
+  %M = mul nsw i32 %XX, %YY
+  %C = icmp sge i32 %M, 0
+  ret i1 %C
+; CHECK: ret i1 true
+}



From kristof.beyls at arm.com  Wed Oct 26 10:40:29 2011
From: kristof.beyls at arm.com (Kristof Beyls)
Date: Wed, 26 Oct 2011 16:40:29 +0100
Subject: [llvm-commits] [patch][pr11029] fix for internal crash due to
	ExpandUnalignedLoad/Store not handling indexed loads correctly
Message-ID: <000001cc93f5$98ab1040$ca0130c0$@beyls@arm.com>

The attached patch fixes PR11029 (
http://llvm.org/bugs/show_bug.cgi?id=11029 ).

The root cause of the problem seems to be that ExpandUnalignedLoad and
ExpandUnalignedStore doesn't handle indexed loads or stores correctly.

There seem to be 2 possible ways to fix this:
1. Implement support for indexed loads/stores in the above functions.
2. Don't generate indexed load/stores in cases where these will need to be
expanded.

The attached patch implements the second approach. The reasons for going
with the second approach are:
* The generation of indexed loads/stores seems to be an optimization. The
second approach chooses not to do the optimization when it's not supported.
* There will not be a regression in code generation, since in the cases that
the patch prohibits optimization, the compiler would crash or generate
incorrect code with a high probability.
* It's unclear whether generating indexed loads/stores for unaligned
loads/stores that need expanding would actually result in better quality of
the generated code.

Could someone review the patch and commit it if fine?

Thanks,

Kristof
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From spop at codeaurora.org  Wed Oct 26 11:01:18 2011
From: spop at codeaurora.org (Sebastian Pop)
Date: Wed, 26 Oct 2011 11:01:18 -0500
Subject: [llvm-commits] [cfe-commits] Ping^2: Fix for bug 11060:
 configure --target does not work
In-Reply-To: <64775AFC-9ADD-4C75-86EE-9688036285EB@apple.com>
References: <CAE5reQLPxYDFQB3zi3FO-dU1xKtndJM+pwFy+kmFxg23hFgJ2w@mail.gmail.com>
	<03B3C19A-52C5-48D5-BBFB-479966ECA09C@apple.com>
	<CAE5reQKS3TWCGnZB9V5FUHh18tPu15Rqeb4hPp7ziHa1c_+YRA@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713404@GEORGE.Emea.Arm.com>
	<CAE5reQKuxURmZcTRhjU1p7MURECVKXFF8tjRZmD23+6zHBVQWQ@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713405@GEORGE.Emea.Arm.com>
	<64775AFC-9ADD-4C75-86EE-9688036285EB@apple.com>
Message-ID: <CAE5reQJ3J5T1z8JCfkdHM63u8Shsddpty5=PCjx1X-Xp4yjR5Q@mail.gmail.com>

On Fri, Oct 21, 2011 at 5:27 PM, Eric Christopher <echristo at apple.com> wrote:
>
> On Oct 21, 2011, at 3:22 PM, James Molloy wrote:
>
> Eric, I agree that this is only a stopgap until a "new and improved" driver
> mechanism is in place, but it does look to be a good addition?
>
> Yeah, should be fine. I was mostly coming up with doomsday scenarios of bug
> reports due to people not knowing that /a/b/clang only supports arm while
> /d/e/clang only supports x86, but thought better about it :)

Eric, could you please commit the configure --target patches?
I have attached an updated version of the patches on top of
today's trunk.

Thanks,
Sebastian
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
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From wmatyjewicz at fastmail.fm  Wed Oct 26 11:18:36 2011
From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz)
Date: Wed, 26 Oct 2011 18:18:36 +0200
Subject: [llvm-commits] [llvm] r141992 - in /llvm/trunk:
 autoconf/configure.ac bindings/ocaml/llvm/META.llvm.in
 bindings/ocaml/llvm/Makefile configure
Message-ID: <4EA832DC.8080009@fastmail.fm>

Hi,

Shouldn't the install-meta rule of Makefile use $(OcamlDir) variable 
instead of $(ObjDir)?

Wojtek


From peter at pcc.me.uk  Wed Oct 26 11:40:18 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Wed, 26 Oct 2011 16:40:18 -0000
Subject: [llvm-commits] [zorg] r143030 - in
 /zorg/trunk/zorg/buildbot/builders: ClangBuilder.py LLDBBuilder.py
Message-ID: <20111026164018.13A3C312800A@llvm.org>

Author: pcc
Date: Wed Oct 26 11:40:17 2011
New Revision: 143030

URL: http://llvm.org/viewvc/llvm-project?rev=143030&view=rev
Log:
LLDB builder: clean LLVM only if its revision number changed since
the last build.  Otherwise, only clean LLDB.

Modified:
    zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
    zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py

Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=143030&r1=143029&r2=143030&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original)
+++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Wed Oct 26 11:40:17 2011
@@ -36,6 +36,7 @@
             use_pty_in_tests=False,
             trunk_revision=None,
             force_checkout=False,
+            extra_clean_step=None,
             checkout_compiler_rt=False):
     # Prepare environmental variables. Set here all env we want everywhere.
     merged_env = {
@@ -158,8 +159,12 @@
                                               description="cleaning llvm",
                                               descriptionDone="clean llvm",
                                               workdir=llvm_1_objdir,
+                                              doStepIf=clean,
                                               env=merged_env))
 
+    if extra_clean_step:
+        f.addStep(extra_clean_step)
+
     f.addStep(WarningCountingShellCommand(name="compile",
                                           command=['nice', '-n', '10',
                                                    make, WithProperties("-j%s" % jobs)],

Modified: zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py?rev=143030&r1=143029&r2=143030&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py (original)
+++ zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py Wed Oct 26 11:40:17 2011
@@ -3,11 +3,24 @@
 import buildbot
 import buildbot.process.factory
 from buildbot.steps.source import SVN
-from buildbot.steps.shell import SetProperty, ShellCommand
+from buildbot.steps.shell import SetProperty, ShellCommand, WarningCountingShellCommand
 from buildbot.process.properties import WithProperties
 
 import ClangBuilder
 
+def isNewLLVMRevision(build_status):
+    if build_status.getNumber() == 0:
+        return true
+
+    current_llvmrev = build_status.getProperty('llvmrev')
+    try:
+        prev_build_no = build_status.getNumber()-1
+        prev_build_status = build_status.getBuilder().getBuild(prev_build_no)
+        prev_llvmrev = prev_build_status.getProperty('llvmrev')
+        return prev_llvmrev != current_llvmrev
+    except IndexError:
+        return true
+
 def getLLDBBuildFactory(triple, outOfDir=False, useTwoStage=False,
                         always_install=False, extra_configure_args=[],
                         *args, **kwargs):
@@ -38,6 +51,20 @@
                           property='llvmrev',
                           workdir='%s/tools/lldb' % llvm_srcdir))
 
+    same_llvmrev = lambda step: not isNewLLVMRevision(step.build.getStatus())
+    new_llvmrev = lambda step: isNewLLVMRevision(step.build.getStatus())
+
+    # Clean LLVM only if its revision number changed since the last build.
+    # Otherwise, only clean LLDB.
+    clean_lldb = \
+        WarningCountingShellCommand(name="clean-lldb",
+                                    command=['make', "clean"],
+                                    haltOnFailure=True,
+                                    description="cleaning lldb",
+                                    descriptionDone="clean lldb",
+                                    workdir='%s/tools/lldb' % llvm_1_objdir,
+                                    doStepIf=same_llvmrev)
+
     # We use force_checkout to ensure the initial checkout is not aborted due to
     # the presence of the tools/lldb directory
     clangf = ClangBuilder.getClangBuildFactory(triple, test=False,
@@ -49,6 +76,8 @@
                                                  ['--enable-targets=host'],
                                                trunk_revision='%(llvmrev)s',
                                                force_checkout=True,
+                                               clean=new_llvmrev,
+                                               extra_clean_step=clean_lldb,
                                                *args, **kwargs)
     f.steps += clangf.steps
 



From atrick at apple.com  Wed Oct 26 11:44:47 2011
From: atrick at apple.com (Andrew Trick)
Date: Wed, 26 Oct 2011 09:44:47 -0700
Subject: [llvm-commits] [llvm] r142743 - in /llvm/trunk:
 lib/CodeGen/MachineBlockPlacement.cpp test/CodeGen/X86/block-placement.ll
In-Reply-To: <CAGCO0Ki2FvFfu7gUf+TVuq5PYxGPDJ76iypq9ztO-ex93n7s-w@mail.gmail.com>
References: <20111023091845.40B6F3524006@llvm.org>
	<55AF1F03-232E-4AD1-9FAE-43285BBC89DE@apple.com>
	<CAGCO0Ki2FvFfu7gUf+TVuq5PYxGPDJ76iypq9ztO-ex93n7s-w@mail.gmail.com>
Message-ID: <BF6E4423-9219-4B61-9BEE-7C076C55280E@apple.com>

On Oct 26, 2011, at 1:13 AM, Chandler Carruth wrote:

> YES. I would greatly appreciate making an RPO order guarantee at the loop info and/or function layer from an analysis that I can piggyback on. Doing it at the loop layer would be wonderful for implementing this kind of algorithm.
>  
> You're currently sidestepping the
> issue by placing chains in a single iteration through the function's
> blocks. If that works well, I don't have a problem with it, but it
> seems to complicate the issue of loop layout. For example, our simple
> RPO iterator makes no attempt to visit blocks in loop order, so
> following this order will not result in contiguous loops. I think
> laying out one loop at a time is much easier to deal with. If you want
> to follow blocks within a loop in RPO order, you can use the
> LoopIterator that I recently added for this purpose. It does need to
> be adapted for MachineLoopInfo.
> 
> I'll look into LoopIterator. If it were to get adapted for MachineLoopInfo, that would certainly help. =D
> 
> I wonder however, the Loop object already has a vector of BB*; it would seem like it could just place that vector in RPO, and be done with it? Dunno, as I've not looked at LoopIterator, etc.

Totally agreed. I don't think we can guarantee the Loop's blocks are RPO at all times, but a particular pass could sort the blocks up front. We have to be careful that some underlying CFG utility doesn't invalidate the order. But giving LoopIterator a separate blocks list doesn't really solve that problem, just hides it.

If it will help you, I can throw together a patch to provides a MachineLoopIterator. That should be straightforward. Later, if need be, someone can modify it to sort the original Loop blocks instead of maintaining its own list as an optimization.

-Andy
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From resistor at mac.com  Wed Oct 26 11:50:42 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 26 Oct 2011 09:50:42 -0700
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <003401cc93b2$2f4c40d0$8de4c270$%molloy@arm.com>
References: <20111019141108.15BB73128018@llvm.org>
	<8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
	<CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>
	<CA+Ov9+krA4yc8mvBGbWSYCgaNMOtMTMA7SYsthtRny2Rp0uoCQ@mail.gmail.com>
	<003401cc93b2$2f4c40d0$8de4c270$%molloy@arm.com>
Message-ID: <5E97CD9C-A2E0-457A-9190-20C18B02E691@mac.com>


On Oct 26, 2011, at 12:37 AM, James Molloy wrote:

> I also heavily dislike the Darwin-specific stuff in the backend and the
> whole idea of "We don't want to do this for Darwin" - if something is a
> negative tradeoff, have an appropriate target-independent knob that can be
> turned to a different position for Darwin.

+1

I think the real issue here is that we don't have a way to distinguish -Os vs. -Oz at the IR level.  Perhaps we need a new function attribute to distinguish the two, though I don't know a good name for it offhand.  Then "We don't want this for Darwin" just becomes a policy decision in the driver.

--Owen

From joerg at britannica.bec.de  Wed Oct 26 11:54:42 2011
From: joerg at britannica.bec.de (Joerg Sonnenberger)
Date: Wed, 26 Oct 2011 09:54:42 -0700
Subject: [llvm-commits] [cfe-commits] Ping^2: Fix for bug 11060:
 configure --target does not work
In-Reply-To: <CAE5reQJ3J5T1z8JCfkdHM63u8Shsddpty5=PCjx1X-Xp4yjR5Q@mail.gmail.com>
References: <CAE5reQLPxYDFQB3zi3FO-dU1xKtndJM+pwFy+kmFxg23hFgJ2w@mail.gmail.com>
	<03B3C19A-52C5-48D5-BBFB-479966ECA09C@apple.com>
	<CAE5reQKS3TWCGnZB9V5FUHh18tPu15Rqeb4hPp7ziHa1c_+YRA@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713404@GEORGE.Emea.Arm.com>
	<CAE5reQKuxURmZcTRhjU1p7MURECVKXFF8tjRZmD23+6zHBVQWQ@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713405@GEORGE.Emea.Arm.com>
	<64775AFC-9ADD-4C75-86EE-9688036285EB@apple.com>
	<CAE5reQJ3J5T1z8JCfkdHM63u8Shsddpty5=PCjx1X-Xp4yjR5Q@mail.gmail.com>
Message-ID: <20111026165442.GD19773@britannica.bec.de>

On Wed, Oct 26, 2011 at 11:01:18AM -0500, Sebastian Pop wrote:
> Eric, could you please commit the configure --target patches?
> I have attached an updated version of the patches on top of
> today's trunk.

You are still introducing a redundant macro and associated code. Which
part of "LLVM_HOSTTRIPLE controls the target" was unclear?

Joerg

From resistor at mac.com  Wed Oct 26 12:05:20 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 26 Oct 2011 17:05:20 -0000
Subject: [llvm-commits] [llvm] r143031 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20111026170521.0287D312800A@llvm.org>

Author: resistor
Date: Wed Oct 26 12:05:20 2011
New Revision: 143031

URL: http://llvm.org/viewvc/llvm-project?rev=143031&view=rev
Log:
Improve pretty printing of GOT relocations in MachO on x86_64.

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=143031&r1=143030&r2=143031&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Wed Oct 26 12:05:20 2011
@@ -807,8 +807,15 @@
     StringRef Name;
     if (error_code ec = getRelocationTargetName(RE->Word1, Name))
       report_fatal_error(ec.message());
+    bool isPCRel = ((RE->Word1 >> 24) & 1);
 
     switch (Type) {
+      case 3:   // X86_64_RELOC_GOT_LOAD
+      case 4: { // X86_64_RELOC_GOT
+        fmt << Name << "@GOT";
+        if (isPCRel) fmt << "PCREL";
+        break;
+      }
       case 5: { // X86_64_RELOC_SUBTRACTOR
         InMemoryStruct<macho::RelocationEntry> RENext;
         DataRefImpl RelNext = Rel;



From mcrosier at apple.com  Wed Oct 26 12:10:12 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 26 Oct 2011 10:10:12 -0700
Subject: [llvm-commits] [llvm] r142896 - in /llvm/trunk/test/Bitcode:
 sse42_crc32.ll sse42_crc32.ll.bc ssse3_palignr.ll ssse3_palignr.ll.bc
In-Reply-To: <4EA7812B.1010507@mxc.ca>
References: <20111025012220.6FCB0312800A@llvm.org>
	<6D6DA0D2-AAC9-4EB9-8373-AA35B5667071@apple.com>
	<1ECBC53E-D20D-4FA0-8C9D-6A52434D2B17@apple.com>
	<4EA7812B.1010507@mxc.ca>
Message-ID: <054B4266-3BD2-4BE2-8334-07F685870F12@apple.com>


On Oct 25, 2011, at 8:40 PM, Nick Lewycky wrote:

> Chad Rosier wrote:
>> My long term goal is to preserve the Value use-lists ordering across bitcode writing/reading
> 
> Excellent! How?

Great question.  I'm still investigating how this is all going to work, but I'm happy to describe the general direction I would like to pursue.  When the bitcode is emitted by the BitcodeWriter, we know the in-memory ordering of the use-lists we're hoping to preserve.  We also know the order in which the BitcodeReader parses the bitcode file is deterministic (and hopefully rarely changes).  Thus, the BitcodeWriter *should* be able to determine the state of the use-lists that will be restored by the BitcodeReader.  Once we have these two states (i.e., the in-memory state prior to writing and the restored state by the reader), we can generate a diff of sorts.  The BitcodeWriter can then emit the diff into the bitcode, which can then be used by the BitcodeReader to restore the original ordering.  Sounds easy enough, but as Chris said, "the devil's in the details."

This feature has several goals that include: 1) it must not break bitcode compatibility, 2) it must be configurable (i.e., have an on/off switch), 3) when enabled the diffs should be as small as possible so as to not bloat the bitcode files, and 4) when disabled it shouldn't effect the size of the bitcode files.  It goes without say that this enhancement should not effect correctness.

 Chad 

> Nick


From resistor at mac.com  Wed Oct 26 12:08:49 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 26 Oct 2011 17:08:49 -0000
Subject: [llvm-commits] [llvm] r143032 - in /llvm/trunk:
 include/llvm/Object/COFF.h include/llvm/Object/MachO.h
 include/llvm/Object/ObjectFile.h lib/Object/COFFObjectFile.cpp
 lib/Object/ELFObjectFile.cpp lib/Object/MachOObjectFile.cpp
 tools/llvm-objdump/MachODump.cpp
Message-ID: <20111026170849.72BD0312800A@llvm.org>

Author: resistor
Date: Wed Oct 26 12:08:49 2011
New Revision: 143032

URL: http://llvm.org/viewvc/llvm-project?rev=143032&view=rev
Log:
Expand relocation type field to 64 bits.  MachO scattered relocations require 33 bits of type info.

Modified:
    llvm/trunk/include/llvm/Object/COFF.h
    llvm/trunk/include/llvm/Object/MachO.h
    llvm/trunk/include/llvm/Object/ObjectFile.h
    llvm/trunk/lib/Object/COFFObjectFile.cpp
    llvm/trunk/lib/Object/ELFObjectFile.cpp
    llvm/trunk/lib/Object/MachOObjectFile.cpp
    llvm/trunk/tools/llvm-objdump/MachODump.cpp

Modified: llvm/trunk/include/llvm/Object/COFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=143032&r1=143031&r2=143032&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/COFF.h (original)
+++ llvm/trunk/include/llvm/Object/COFF.h Wed Oct 26 12:08:49 2011
@@ -138,7 +138,7 @@
   virtual error_code getRelocationSymbol(DataRefImpl Rel,
                                          SymbolRef &Res) const;
   virtual error_code getRelocationType(DataRefImpl Rel,
-                                       uint32_t &Res) const;
+                                       uint64_t &Res) const;
   virtual error_code getRelocationTypeName(DataRefImpl Rel,
                                            SmallVectorImpl<char> &Result) const;
   virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,

Modified: llvm/trunk/include/llvm/Object/MachO.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachO.h?rev=143032&r1=143031&r2=143032&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/MachO.h (original)
+++ llvm/trunk/include/llvm/Object/MachO.h Wed Oct 26 12:08:49 2011
@@ -81,7 +81,7 @@
   virtual error_code getRelocationSymbol(DataRefImpl Rel,
                                          SymbolRef &Res) const;
   virtual error_code getRelocationType(DataRefImpl Rel,
-                                       uint32_t &Res) const;
+                                       uint64_t &Res) const;
   virtual error_code getRelocationTypeName(DataRefImpl Rel,
                                            SmallVectorImpl<char> &Result) const;
   virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,

Modified: llvm/trunk/include/llvm/Object/ObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=143032&r1=143031&r2=143032&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/ObjectFile.h (original)
+++ llvm/trunk/include/llvm/Object/ObjectFile.h Wed Oct 26 12:08:49 2011
@@ -99,7 +99,7 @@
 
   error_code getAddress(uint64_t &Result) const;
   error_code getSymbol(SymbolRef &Result) const;
-  error_code getType(uint32_t &Result) const;
+  error_code getType(uint64_t &Result) const;
 
   /// @brief Indicates whether this relocation should hidden when listing
   /// relocations, usually because it is the trailing part of a multipart
@@ -284,7 +284,7 @@
   virtual error_code getRelocationSymbol(DataRefImpl Rel,
                                          SymbolRef &Res) const = 0;
   virtual error_code getRelocationType(DataRefImpl Rel,
-                                       uint32_t &Res) const = 0;
+                                       uint64_t &Res) const = 0;
   virtual error_code getRelocationTypeName(DataRefImpl Rel,
                                        SmallVectorImpl<char> &Result) const = 0;
   virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
@@ -474,7 +474,7 @@
   return OwningObject->getRelocationSymbol(RelocationPimpl, Result);
 }
 
-inline error_code RelocationRef::getType(uint32_t &Result) const {
+inline error_code RelocationRef::getType(uint64_t &Result) const {
   return OwningObject->getRelocationType(RelocationPimpl, Result);
 }
 

Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=143032&r1=143031&r2=143032&view=diff
==============================================================================
--- llvm/trunk/lib/Object/COFFObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/COFFObjectFile.cpp Wed Oct 26 12:08:49 2011
@@ -623,7 +623,7 @@
   return object_error::success;
 }
 error_code COFFObjectFile::getRelocationType(DataRefImpl Rel,
-                                             uint32_t &Res) const {
+                                             uint64_t &Res) const {
   const coff_relocation* R = toRel(Rel);
   Res = R->Type;
   return object_error::success;

Modified: llvm/trunk/lib/Object/ELFObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ELFObjectFile.cpp?rev=143032&r1=143031&r2=143032&view=diff
==============================================================================
--- llvm/trunk/lib/Object/ELFObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/ELFObjectFile.cpp Wed Oct 26 12:08:49 2011
@@ -358,7 +358,7 @@
   virtual error_code getRelocationSymbol(DataRefImpl Rel,
                                          SymbolRef &Res) const;
   virtual error_code getRelocationType(DataRefImpl Rel,
-                                       uint32_t &Res) const;
+                                       uint64_t &Res) const;
   virtual error_code getRelocationTypeName(DataRefImpl Rel,
                                            SmallVectorImpl<char> &Result) const;
   virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
@@ -923,7 +923,7 @@
 template<support::endianness target_endianness, bool is64Bits>
 error_code ELFObjectFile<target_endianness, is64Bits>
                         ::getRelocationType(DataRefImpl Rel,
-                                            uint32_t &Result) const {
+                                            uint64_t &Result) const {
   const Elf_Shdr *sec = getSection(Rel.w.b);
   switch (sec->sh_type) {
     default :

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=143032&r1=143031&r2=143032&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Wed Oct 26 12:08:49 2011
@@ -634,7 +634,7 @@
   return object_error::success;
 }
 error_code MachOObjectFile::getRelocationType(DataRefImpl Rel,
-                                              uint32_t &Res) const {
+                                              uint64_t &Res) const {
   InMemoryStruct<macho::RelocationEntry> RE;
   getRelocation(Rel, RE);
   Res = RE->Word1;

Modified: llvm/trunk/tools/llvm-objdump/MachODump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/MachODump.cpp?rev=143032&r1=143031&r2=143032&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/MachODump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/MachODump.cpp Wed Oct 26 12:08:49 2011
@@ -394,7 +394,7 @@
       Sections[SectIdx].getAddress(SectionAddress);
       RelocOffset -= SectionAddress;
 
-      uint32_t RelocInfo;
+      uint64_t RelocInfo;
       RI->getType(RelocInfo);
 
       Relocs.push_back(std::make_pair(RelocOffset, RelocInfo));



From echristo at apple.com  Wed Oct 26 12:11:01 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 26 Oct 2011 10:11:01 -0700
Subject: [llvm-commits] [cfe-commits] Ping^2: Fix for bug 11060:
 configure --target does not work
In-Reply-To: <20111026165442.GD19773@britannica.bec.de>
References: <CAE5reQLPxYDFQB3zi3FO-dU1xKtndJM+pwFy+kmFxg23hFgJ2w@mail.gmail.com>
	<03B3C19A-52C5-48D5-BBFB-479966ECA09C@apple.com>
	<CAE5reQKS3TWCGnZB9V5FUHh18tPu15Rqeb4hPp7ziHa1c_+YRA@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713404@GEORGE.Emea.Arm.com>
	<CAE5reQKuxURmZcTRhjU1p7MURECVKXFF8tjRZmD23+6zHBVQWQ@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713405@GEORGE.Emea.Arm.com>
	<64775AFC-9ADD-4C75-86EE-9688036285EB@apple.com>
	<CAE5reQJ3J5T1z8JCfkdHM63u8Shsddpty5=PCjx1X-Xp4yjR5Q@mail.gmail.com>
	<20111026165442.GD19773@britannica.bec.de>
Message-ID: <A84AFB42-6CC0-40C8-8079-9757B7666F42@apple.com>


On Oct 26, 2011, at 9:54 AM, Joerg Sonnenberger wrote:

> On Wed, Oct 26, 2011 at 11:01:18AM -0500, Sebastian Pop wrote:
>> Eric, could you please commit the configure --target patches?
>> I have attached an updated version of the patches on top of
>> today's trunk.
> 
> You are still introducing a redundant macro and associated code. Which
> part of "LLVM_HOSTTRIPLE controls the target" was unclear?

Can you elaborate on this here? What, in particular, do you think should
change with Sebastian's patch? He's adding functionality that --target (and
similar cmake-isms) control the default target, not host of the compiler.

True that the host isn't used in a lot of places at the moment, but I'm
not sure why we need to keep the requirement that "host-triple" is
the triple we're targeting.

-eric

From resistor at mac.com  Wed Oct 26 12:10:22 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 26 Oct 2011 17:10:22 -0000
Subject: [llvm-commits] [llvm] r143033 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20111026171022.E85CD312800A@llvm.org>

Author: resistor
Date: Wed Oct 26 12:10:22 2011
New Revision: 143033

URL: http://llvm.org/viewvc/llvm-project?rev=143033&view=rev
Log:
Include the full 64 bits of relocation data in the type info for MachO relocations, so that we can recognize scattered relocations.

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=143033&r1=143032&r2=143033&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Wed Oct 26 12:10:22 2011
@@ -637,7 +637,9 @@
                                               uint64_t &Res) const {
   InMemoryStruct<macho::RelocationEntry> RE;
   getRelocation(Rel, RE);
-  Res = RE->Word1;
+  Res = RE->Word0;
+  Res <<= 32;
+  Res |= RE->Word1;
   return object_error::success;
 }
 error_code MachOObjectFile::getRelocationTypeName(DataRefImpl Rel,



From grosbach at apple.com  Wed Oct 26 12:28:15 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 26 Oct 2011 17:28:15 -0000
Subject: [llvm-commits] [llvm] r143034 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/select-imm.ll
Message-ID: <20111026172815.DAE5E312800A@llvm.org>

Author: grosbach
Date: Wed Oct 26 12:28:15 2011
New Revision: 143034

URL: http://llvm.org/viewvc/llvm-project?rev=143034&view=rev
Log:
Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/CodeGen/ARM/select-imm.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=143034&r1=143033&r2=143034&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Oct 26 12:28:15 2011
@@ -2887,7 +2887,7 @@
 
 let isMoveImm = 1 in
 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
-                   IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
+                   IIC_iCMOVi, "mvn", "\t$Rd, $imm",
 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
                    imm:$cc, CCR:$ccr))*/]>,
                    RegConstraint<"$false = $Rd"> {

Modified: llvm/trunk/test/CodeGen/ARM/select-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select-imm.ll?rev=143034&r1=143033&r2=143034&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select-imm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select-imm.ll Wed Oct 26 12:28:15 2011
@@ -71,7 +71,7 @@
 ; ARMT2: movtlt [[R0]], #65365
 
 ; THUMB2: t4:
-; THUMB2: mvnlt.w [[R0:r[0-9]+]], #11141290
+; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290
   %0 = icmp slt i32 %a, %b
   %1 = select i1 %0, i32 4283826005, i32 %x
   ret i32 %1



From resistor at mac.com  Wed Oct 26 12:28:49 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 26 Oct 2011 17:28:49 -0000
Subject: [llvm-commits] [llvm] r143035 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20111026172849.777A8312800A@llvm.org>

Author: resistor
Date: Wed Oct 26 12:28:49 2011
New Revision: 143035

URL: http://llvm.org/viewvc/llvm-project?rev=143035&view=rev
Log:
The order of the two symbol listings in a Macho x86_64 subtractor relocation is reversed from what seems intuitive to me.

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=143035&r1=143034&r2=143035&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Wed Oct 26 12:28:49 2011
@@ -835,7 +835,9 @@
         if (error_code ec = getRelocationTargetName(RENext->Word1, SucName))
           report_fatal_error(ec.message());
 
-        fmt << Name << "-" << SucName;
+        // The X86_64_RELOC_UNSIGNED contains the minuend symbol,
+        // X86_64_SUBTRACTOR contains to the subtrahend.
+        fmt << SucName << "-" << Name;
       }
       case 6: // X86_64_RELOC_SIGNED1
         fmt << Name << "-1";



From evan.cheng at apple.com  Wed Oct 26 12:26:44 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 26 Oct 2011 10:26:44 -0700
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <5E97CD9C-A2E0-457A-9190-20C18B02E691@mac.com>
References: <20111019141108.15BB73128018@llvm.org>
	<8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
	<CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>
	<CA+Ov9+krA4yc8mvBGbWSYCgaNMOtMTMA7SYsthtRny2Rp0uoCQ@mail.gmail.com>
	<003401cc93b2$2f4c40d0$8de4c270$%molloy@arm.com>
	<5E97CD9C-A2E0-457A-9190-20C18B02E691@mac.com>
Message-ID: <5278DE66-B996-4554-8524-B5A28B761BEE@apple.com>


On Oct 26, 2011, at 9:50 AM, Owen Anderson wrote:

> 
> On Oct 26, 2011, at 12:37 AM, James Molloy wrote:
> 
>> I also heavily dislike the Darwin-specific stuff in the backend and the
>> whole idea of "We don't want to do this for Darwin" - if something is a
>> negative tradeoff, have an appropriate target-independent knob that can be
>> turned to a different position for Darwin.
> 
> +1
> 
> I think the real issue here is that we don't have a way to distinguish -Os vs. -Oz at the IR level.  Perhaps we need a new function attribute to distinguish the two, though I don't know a good name for it offhand.  Then "We don't want this for Darwin" just becomes a policy decision in the driver.

I agree with this. We should either 1) rename the current attribute OptimizeForSize and add another one for -Oz or 2) change the attribute so it's not true / false rather a OptimizeForSize level.

LLVM traditionally hasn't cared much about optimizing for size. I would love for someone to be the champion for this task and drive it.

Evan

> 
> --Owen
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From bob.wilson at apple.com  Wed Oct 26 13:17:17 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 26 Oct 2011 18:17:17 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r143039 -
	/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h
Message-ID: <20111026181717.4F6AF312800A@llvm.org>

Author: bwilson
Date: Wed Oct 26 13:17:17 2011
New Revision: 143039

URL: http://llvm.org/viewvc/llvm-project?rev=143039&view=rev
Log:
Allow enabling the aapcs-vfp ABI when aapcs is not the default.

Modified:
    llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h

Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h?rev=143039&r1=143038&r2=143039&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h Wed Oct 26 13:17:17 2011
@@ -38,7 +38,7 @@
               (TREE_VALUE(tree_last(TYPE_ARG_TYPES(type))) == \
                void_type_node)))                              \
         CC = CallingConv::ARM_AAPCS_VFP;                      \
-      if (!DEFAULT_TARGET_AAPCS_BASED)                        \
+      else if (!DEFAULT_TARGET_AAPCS_BASED)                   \
         CC = CallingConv::ARM_AAPCS;                          \
     } else if (DEFAULT_TARGET_AAPCS_BASED) {                  \
         CC = CallingConv::ARM_APCS;                           \



From isanbard at gmail.com  Wed Oct 26 13:20:54 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 18:20:54 -0000
Subject: [llvm-commits] [llvm] r143040 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026182054.8FE80312800A@llvm.org>

Author: void
Date: Wed Oct 26 13:20:54 2011
New Revision: 143040

URL: http://llvm.org/viewvc/llvm-project?rev=143040&view=rev
Log:
Add LanguageKit and Pragmatic Smalltalk to the External Projects list.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143040&r1=143039&r2=143040&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Wed Oct 26 13:20:54 2011
@@ -370,6 +370,21 @@
 </div>
 
 <!--=========================================================================-->
+<h3>LanguageKit and Pragmatic Smalltalk</h3>
+
+<div>
+
+<p><a href="http://etoileos.com/etoile/features/languagekit/">LanguageKit</a> is
+   a framework for implementing dynamic languages sharing an object model with
+   Objective-C. It provides static and JIT compilation using LLVM along with
+   its own interpreter. Pragmatic Smalltalk is a dialect of Smalltalk, built on
+   top of LanguageKit, that interfaces directly with Objective-C, sharing the
+   same object representation and message sending behaviour. These projects are
+   developed as part of the &Eacute;toi&eacute; desktop environment.</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>Mono</h3>
 
 <div>



From isanbard at gmail.com  Wed Oct 26 13:23:06 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 18:23:06 -0000
Subject: [llvm-commits] [llvm] r143041 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026182306.7CE94312800A@llvm.org>

Author: void
Date: Wed Oct 26 13:23:06 2011
New Revision: 143041

URL: http://llvm.org/viewvc/llvm-project?rev=143041&view=rev
Log:
Add clReflect to the External Projects list.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143041&r1=143040&r2=143041&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Wed Oct 26 13:23:06 2011
@@ -316,6 +316,20 @@
 </div>
 
 <!--=========================================================================-->
+<h3>clReflect</h3>
+
+<div>
+
+<p><a href="https://bitbucket.org/dwilliamson/clreflect">clReflect</a> is a C++
+   parser that uses clang/LLVM to derive a light-weight reflection database
+   suitable for use in game development. It comes with a very simple runtime
+   library for loading and querying the database, requiring no external
+   dependencies (including CRT), and an additional utility library for object
+   management and serialisation.</p>
+
+</div>
+
+<!--=========================================================================-->
 <!-- FIXME: Comment out
 <h3>Crack Programming Language</h3>
 



From clattner at apple.com  Wed Oct 26 13:22:53 2011
From: clattner at apple.com (Chris Lattner)
Date: Wed, 26 Oct 2011 11:22:53 -0700
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <5E97CD9C-A2E0-457A-9190-20C18B02E691@mac.com>
References: <20111019141108.15BB73128018@llvm.org>
	<8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
	<CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>
	<CA+Ov9+krA4yc8mvBGbWSYCgaNMOtMTMA7SYsthtRny2Rp0uoCQ@mail.gmail.com>
	<003401cc93b2$2f4c40d0$8de4c270$%molloy@arm.com>
	<5E97CD9C-A2E0-457A-9190-20C18B02E691@mac.com>
Message-ID: <B0B56AD4-3A51-4283-907C-DACC97CA8231@apple.com>


On Oct 26, 2011, at 9:50 AM, Owen Anderson wrote:

> 
> On Oct 26, 2011, at 12:37 AM, James Molloy wrote:
> 
>> I also heavily dislike the Darwin-specific stuff in the backend and the
>> whole idea of "We don't want to do this for Darwin" - if something is a
>> negative tradeoff, have an appropriate target-independent knob that can be
>> turned to a different position for Darwin.
> 
> +1
> 
> I think the real issue here is that we don't have a way to distinguish -Os vs. -Oz at the IR level.  Perhaps we need a new function attribute to distinguish the two, though I don't know a good name for it offhand.  Then "We don't want this for Darwin" just becomes a policy decision in the driver.

I think we just want another attribute, just like OptimizeForSize but the Oz variant.  Maybe OptimizeForSizeHarder ;-)

-Chris

From spop at codeaurora.org  Wed Oct 26 13:33:38 2011
From: spop at codeaurora.org (Sebastian Pop)
Date: Wed, 26 Oct 2011 13:33:38 -0500
Subject: [llvm-commits] [cfe-commits] Ping^2: Fix for bug 11060:
 configure --target does not work
In-Reply-To: <20111026165442.GD19773@britannica.bec.de>
References: <CAE5reQLPxYDFQB3zi3FO-dU1xKtndJM+pwFy+kmFxg23hFgJ2w@mail.gmail.com>
	<03B3C19A-52C5-48D5-BBFB-479966ECA09C@apple.com>
	<CAE5reQKS3TWCGnZB9V5FUHh18tPu15Rqeb4hPp7ziHa1c_+YRA@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713404@GEORGE.Emea.Arm.com>
	<CAE5reQKuxURmZcTRhjU1p7MURECVKXFF8tjRZmD23+6zHBVQWQ@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713405@GEORGE.Emea.Arm.com>
	<64775AFC-9ADD-4C75-86EE-9688036285EB@apple.com>
	<CAE5reQJ3J5T1z8JCfkdHM63u8Shsddpty5=PCjx1X-Xp4yjR5Q@mail.gmail.com>
	<20111026165442.GD19773@britannica.bec.de>
Message-ID: <CAE5reQLEvirPzur-q0HPKkBvJZ=EDnWOm6BXogCvbQNUu6bw6g@mail.gmail.com>

On Wed, Oct 26, 2011 at 11:54 AM, Joerg Sonnenberger
<joerg at britannica.bec.de> wrote:
> On Wed, Oct 26, 2011 at 11:01:18AM -0500, Sebastian Pop wrote:
>> Eric, could you please commit the configure --target patches?
>> I have attached an updated version of the patches on top of
>> today's trunk.
>
> You are still introducing a redundant macro and associated code.

I disagree.  The code that I am adding is non redundant:
LLVM_DEFAULT_TARGET_TRIPLE is set from $target:
+AC_DEFINE_UNQUOTED(LLVM_DEFAULT_TARGET_TRIPLE, "$target",
+                   [Default target triple to build for])

LLVM_HOSTTRIPLE is defined from $host:
AC_DEFINE_UNQUOTED(LLVM_HOSTTRIPLE, "$host",
                   [Host triple we were built on])

(The comment here is confusing HOST and BUILD as well:
it should be modified to read "Host triple the compiler is running on".)

> Which part of "LLVM_HOSTTRIPLE controls the target" was unclear?

LLVM_HOSTTRIPLE should *not* control the target.
$host and $target are two different things (in the cross compilers world.)

How would you select the value set by configure in $target after you
have thrown away the information that configure has set in $target?

The only way "$host controls $target" is when --target is not specified.
That's exactly configure's job to set the value for $target according to
the options that you provide to configure.

configure --help says:
[...]
Defaults for the options are specified in brackets.
[...]
System types:
  --build=BUILD     configure for building on BUILD [guessed]
  --host=HOST       cross-compile to build programs to run on HOST [BUILD]
  --target=TARGET   configure for building compilers for TARGET [HOST]

So if you do not specify --target, configure sets in $target the value that
it previously set in $host.

Sebastian
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

From wendling at apple.com  Wed Oct 26 13:30:55 2011
From: wendling at apple.com (Bill Wendling)
Date: Wed, 26 Oct 2011 11:30:55 -0700
Subject: [llvm-commits] [llvm] r143001	-
 /llvm/trunk/lib/CodeGen/BranchFolding.cpp
In-Reply-To: <4EA7B906.40304@free.fr>
References: <20111026011025.ED72D312800A@llvm.org> <4EA7B906.40304@free.fr>
Message-ID: <6AE12498-7078-48E8-8438-7D78711D0E83@apple.com>

On Oct 26, 2011, at 12:38 AM, Duncan Sands wrote:

> Hi Bill,
> 
>> Reapply r142920 with fix:
>> 
>> An MBB which branches to an EH landing pad shouldn't be considered for tail merging.
>> 
>> In SjLj EH, the jump to the landing pad is not done explicitly through a branch
>> statement. The EH landing pad is added as a successor to the throwing
>> BB. Because of that however, the branch folding pass could mistakenly think that
>> it could merge the throwing BB with another BB. This isn't safe to do.
>> <rdar://problem/10334833>
> 
> testcase?
> 
Unfortunately, the testcase is way too large to go into the regression suite.

-bw


From wendling at apple.com  Wed Oct 26 13:32:26 2011
From: wendling at apple.com (Bill Wendling)
Date: Wed, 26 Oct 2011 11:32:26 -0700
Subject: [llvm-commits] [LLVM,
 llvm-objdump] Fix for clang-native-arm-cortex-a9.
In-Reply-To: <4EA7DF2B.2070100@narod.ru>
References: <4EA67DE3.8060803@narod.ru> <4EA7DF2B.2070100@narod.ru>
Message-ID: <E7BD9520-EDC1-4BCB-8A99-8A30ECF1C370@apple.com>

This looks fine to me. Do you have commit access?

-bw

On Oct 26, 2011, at 3:21 AM, Stepan Dyatkovskiy wrote:

> ping.
> 
> Regards,
> Stepan.
> 
> Stepan Dyatkovskiy wrote:
>> Hi all,
>> 
>> Please find the patch in attachment that fixes llvm-objdump test
>> failures for clang-native-arm-cortex-a9.
>> 
>> Regards,
>> Stepan.
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From isanbard at gmail.com  Wed Oct 26 13:33:01 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 18:33:01 -0000
Subject: [llvm-commits] [llvm] r143042 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026183301.E4CF8312800A@llvm.org>

Author: void
Date: Wed Oct 26 13:33:01 2011
New Revision: 143042

URL: http://llvm.org/viewvc/llvm-project?rev=143042&view=rev
Log:
Add the blurb about the new exception handling.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143042&r1=143041&r2=143042&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Wed Oct 26 13:33:01 2011
@@ -689,11 +689,116 @@
 <p>LLVM IR has several new features for better support of new targets and that
 expose new optimization opportunities:</p>
 
-<ul>
-<!--
-<li></li>
--->
-</ul>
+<p>One of the biggest changes is that 3.0 has a new exception handling
+   system. The old system used LLVM intrinsics to convey the exception handling
+   information to the code generator. It worked in most cases, but not
+   all. Inlining was especially difficult to get right. Also, the intrinsics
+   could be moved away from the <code>invoke</code> instruction, making it hard
+   to recover that information.</p>
+
+<p>The new EH system makes exception handling a first-class member of the IR. It
+   adds two new instructions:</p>
+
+<ul>
+  <li><a href="LangRef.html#i_landingpad"><code>landingpad</code></a> &mdash;
+      this instruction defines a landing pad basic block. It contains all of the
+      information that's needed by the code generator. It's also required to be
+      the first non-PHI instruction in the landing pad. In addition, a landing
+      pad may be jumped to only by the unwind edge of an <code>invoke</code>
+      instruction.</li>
+
+  <li><a href="LangRef.html#i_resume"><code>resume</code></a> &mdash; this
+      instruction causes the current exception to resume traveling up the
+      stack. It replaces the <code>@llvm.eh.resume</code> intrinsic.</li>
+</ul>
+
+<p>Converting from the old EH API to the new EH API is rather simple, because a
+   lot of complexity has been removed. The two intrinsics,
+   <code>@llvm.eh.exception</code> and <code>@llvm.eh.selector</code> have been
+   superceded by the <code>landingpad</code> instruction. Instead of generating
+   a call to <code>@llvm.eh.exception</code> and <code>@llvm.eh.selector</code>:
+
+<div class="doc_code">
+<pre>
+Function *ExcIntr = Intrinsic::getDeclaration(TheModule,
+                                              Intrinsic::eh_exception);
+Function *SlctrIntr = Intrinsic::getDeclaration(TheModule,
+                                                Intrinsic::eh_selector);
+
+// The exception pointer.
+Value *ExnPtr = Builder.CreateCall(ExcIntr, "exc_ptr");
+
+std::vector&lt;Value*&gt; Args;
+Args.push_back(ExnPtr);
+Args.push_back(Builder.CreateBitCast(Personality,
+                                     Type::getInt8PtrTy(Context)));
+
+<i>// Add selector clauses to Args.</i>
+
+// The selector call.
+Builder.CreateCall(SlctrIntr, Args, "exc_sel");
+</pre>
+</div>
+
+<p>You should instead generate a <code>landingpad</code> instruction, that
+   returns an exception object and selector value:</p>
+
+<div class="doc_code">
+<pre>
+LandingPadInst *LPadInst =
+  Builder.CreateLandingPad(StructType::get(Int8PtrTy, Int32Ty, NULL),
+                           Personality, 0);
+
+Value *LPadExn = Builder.CreateExtractValue(LPadInst, 0);
+Builder.CreateStore(LPadExn, getExceptionSlot());
+
+Value *LPadSel = Builder.CreateExtractValue(LPadInst, 1);
+Builder.CreateStore(LPadSel, getEHSelectorSlot());
+</pre>
+</div>
+
+<p>It's now trivial to add the individual clauses to the <code>landingpad</code>
+   instruction.</p>
+
+<div class="doc_code">
+<pre>
+<i><b>// Adding a catch clause</b></i>
+Constant *TypeInfo = getTypeInfo();
+LPadInst-&gt;addClause(TypeInfo);
+
+<i><b>// Adding a C++ catch-all</b></i>
+LPadInst-&gt;addClause(Constant::getNullValue(Builder.getInt8PtrTy()));
+
+<i><b>// Adding a cleanup</b></i>
+LPadInst-&gt;setCleanup(true);
+
+<i><b>// Adding a filter clause</b></i>
+std::vector&lt;Constant*&gt; TypeInfos;
+Constant *TypeInfo = getFilterTypeInfo();
+TypeInfos.push_back(Builder.CreateBitCast(TypeInfo, Builder.getInt8PtrTy()));
+
+ArrayType *FilterTy = ArrayType::get(Int8PtrTy, TypeInfos.size());
+LPadInst-&gt;addClause(ConstantArray::get(FilterTy, TypeInfos));
+</pre>
+</div>
+
+<p>Converting from using the <code>@llvm.eh.resume</code> intrinsic to
+   the <code>resume</code> instruction is trivial. It takes the exception
+   pointer and exception selector values returned by
+   the <code>landingpad</code> instruction:</p>
+
+<div class="doc_code">
+<pre>
+Type *UnwindDataTy = StructType::get(Builder.getInt8PtrTy(),
+                                     Builder.getInt32Ty(), NULL);
+Value *UnwindData = UndefValue::get(UnwindDataTy);
+Value *ExcPtr = Builder.CreateLoad(getExceptionObjSlot());
+Value *ExcSel = Builder.CreateLoad(getExceptionSelSlot());
+UnwindData = Builder.CreateInsertValue(UnwindData, ExcPtr, 0, "exc_ptr");
+UnwindData = Builder.CreateInsertValue(UnwindData, ExcSel, 1, "exc_sel");
+Builder.CreateResume(UnwindData);
+</pre>
+</div>
 
 </div>
 



From nicholas at mxc.ca  Wed Oct 26 13:44:32 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 26 Oct 2011 18:44:32 -0000
Subject: [llvm-commits] [llvm] r143044 -
	/llvm/trunk/lib/MC/MCObjectFileInfo.cpp
Message-ID: <20111026184432.DADDC312800A@llvm.org>

Author: nicholas
Date: Wed Oct 26 13:44:32 2011
New Revision: 143044

URL: http://llvm.org/viewvc/llvm-project?rev=143044&view=rev
Log:
On an ELF system, ".debug_str" is mergeable and contains null terminated strings
composed of one byte characters.

Modified:
    llvm/trunk/lib/MC/MCObjectFileInfo.cpp

Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=143044&r1=143043&r2=143044&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Wed Oct 26 13:44:32 2011
@@ -354,8 +354,9 @@
     Ctx->getELFSection(".debug_pubtypes", ELF::SHT_PROGBITS, 0,
                        SectionKind::getMetadata());
   DwarfStrSection =
-    Ctx->getELFSection(".debug_str", ELF::SHT_PROGBITS, 0,
-                       SectionKind::getMetadata());
+    Ctx->getELFSection(".debug_str", ELF::SHT_PROGBITS,
+                       ELF::SHF_MERGE | ELF::SHF_STRINGS,
+                       SectionKind::getMergeable1ByteCString());
   DwarfLocSection =
     Ctx->getELFSection(".debug_loc", ELF::SHT_PROGBITS, 0,
                        SectionKind::getMetadata());



From isanbard at gmail.com  Wed Oct 26 13:46:16 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 18:46:16 -0000
Subject: [llvm-commits] [llvm] r143045 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026184616.DFFD4312800A@llvm.org>

Author: void
Date: Wed Oct 26 13:46:16 2011
New Revision: 143045

URL: http://llvm.org/viewvc/llvm-project?rev=143045&view=rev
Log:
Some formatting changes.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143045&r1=143044&r2=143045&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Wed Oct 26 13:46:16 2011
@@ -44,21 +44,21 @@
 <div>
 
 <p>This document contains the release notes for the LLVM Compiler
-Infrastructure, release 3.0.  Here we describe the status of LLVM, including
-major improvements from the previous release and significant known problems.
-All LLVM releases may be downloaded from the <a
-href="http://llvm.org/releases/">LLVM releases web site</a>.</p>
+   Infrastructure, release 3.0.  Here we describe the status of LLVM, including
+   major improvements from the previous release and significant known problems.
+   All LLVM releases may be downloaded from
+   the <a href="http://llvm.org/releases/">LLVM releases web site</a>.</p>
 
 <p>For more information about LLVM, including information about the latest
-release, please check out the <a href="http://llvm.org/">main LLVM
-web site</a>.  If you have questions or comments, the <a
-href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVM Developer's
-Mailing List</a> is a good place to send them.</p>
-
-<p>Note that if you are reading this file from a Subversion checkout or the
-main LLVM web page, this document applies to the <i>next</i> release, not the
-current one.  To see the release notes for a specific release, please see the
-<a href="http://llvm.org/releases/">releases page</a>.</p>
+   release, please check out the <a href="http://llvm.org/">main LLVM web
+   site</a>.  If you have questions or comments,
+   the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVM
+   Developer's Mailing List</a> is a good place to send them.</p>
+
+<p>Note that if you are reading this file from a Subversion checkout or the main
+   LLVM web page, this document applies to the <i>next</i> release, not the
+   current one.  To see the release notes for a specific release, please see the
+   <a href="http://llvm.org/releases/">releases page</a>.</p>
 
 </div>
    
@@ -78,13 +78,12 @@
 <!-- *********************************************************************** -->
 
 <div>
-<p>
-The LLVM 3.0 distribution currently consists of code from the core LLVM
-repository (which roughly includes the LLVM optimizers, code generators
-and supporting tools), the Clang repository and the llvm-gcc repository.  In
-addition to this code, the LLVM Project includes other sub-projects that are in
-development.  Here we include updates on these subprojects.
-</p>
+
+<p>The LLVM 3.0 distribution currently consists of code from the core LLVM
+   repository (which roughly includes the LLVM optimizers, code generators and
+   supporting tools), the Clang repository and the llvm-gcc repository.  In
+   addition to this code, the LLVM Project includes other sub-projects that are
+   in development.  Here we include updates on these subprojects.</p>
 
 <!--=========================================================================-->
 <h3>
@@ -94,35 +93,47 @@
 <div>
 
 <p><a href="http://clang.llvm.org/">Clang</a> is an LLVM front end for the C,
-C++, and Objective-C languages. Clang aims to provide a better user experience
-through expressive diagnostics, a high level of conformance to language
-standards, fast compilation, and low memory use. Like LLVM, Clang provides a
-modular, library-based architecture that makes it suitable for creating or
-integrating with other development tools. Clang is considered a
-production-quality compiler for C, Objective-C, C++ and Objective-C++ on x86
-(32- and 64-bit), and for darwin/arm targets.</p>
+   C++, and Objective-C languages. Clang aims to provide a better user
+   experience through expressive diagnostics, a high level of conformance to
+   language standards, fast compilation, and low memory use. Like LLVM, Clang
+   provides a modular, library-based architecture that makes it suitable for
+   creating or integrating with other development tools. Clang is considered a
+   production-quality compiler for C, Objective-C, C++ and Objective-C++ on x86
+   (32- and 64-bit), and for darwin/arm targets.</p>
 
 <p>In the LLVM 3.0 time-frame, the Clang team has made many improvements:</p>
 
 <ul>
-  <li>Greatly improved support for building C++ applications, with greater stability and better diagnostics.</li>
-  
-  <li><a href="http://clang.llvm.org/cxx_status.html">Improved support</a> for the <a href="http://www.iso.org/iso/iso_catalogue/catalogue_tc/catalogue_detail.htm?csnumber=50372 ">C++ 2011</a> standard, including implementations of non-static data member initializers, alias templates, delegating constructors, the range-based for loop, and implicitly-generated move constructors and move assignment operators, among others.</li>
-
-  <li>Implemented support for some features of the upcoming C1x standard, including static assertions and generic selections.</li>
+  <li>Greatly improved support for building C++ applications, with greater
+      stability and better diagnostics.</li>
   
-  <li>Better detection of include and linking paths for system headers and libraries, especially for Linux distributions.</li>
-
-  <li>Implemented support for <a href="http://clang.llvm.org/docs/AutomaticReferenceCounting.html">Automatic Reference Counting</a> for Objective-C.</li>
-
-  <li>Implemented a number of optimizations in <tt>libclang</tt>, the Clang C interface, to improve the performance of code completion and the mapping from source locations to abstract syntax tree nodes.</li>
+  <li><a href="http://clang.llvm.org/cxx_status.html">Improved support</a> for
+      the <a href="http://www.iso.org/iso/iso_catalogue/catalogue_tc/catalogue_detail.htm?csnumber=50372">C++
+      2011</a> standard, including implementations of non-static data member
+      initializers, alias templates, delegating constructors, the range-based
+      for loop, and implicitly-generated move constructors and move assignment
+      operators, among others.</li>
+
+  <li>Implemented support for some features of the upcoming C1x standard,
+      including static assertions and generic selections.</li>
+  
+  <li>Better detection of include and linking paths for system headers and
+      libraries, especially for Linux distributions.</li>
+
+  <li>Implemented support
+      for <a href="http://clang.llvm.org/docs/AutomaticReferenceCounting.html">Automatic
+      Reference Counting</a> for Objective-C.</li>
+
+  <li>Implemented a number of optimizations in <tt>libclang</tt>, the Clang C
+      interface, to improve the performance of code completion and the mapping
+      from source locations to abstract syntax tree nodes.</li>
 </ul>
 
   
 <p>If Clang rejects your code but another compiler accepts it, please take a
-look at the <a href="http://clang.llvm.org/compatibility.html">language
-compatibility</a> guide to make sure this is not intentional or a known issue.
-</p>
+   look at the <a href="http://clang.llvm.org/compatibility.html">language
+   compatibility</a> guide to make sure this is not intentional or a known
+   issue.</p>
 
 </div>
 
@@ -132,20 +143,17 @@
 </h3>
 
 <div>
-<p>
-<a href="http://dragonegg.llvm.org/">DragonEgg</a> is a
-<a href="http://gcc.gnu.org/wiki/plugins">gcc plugin</a> that replaces GCC's
-optimizers and code generators with LLVM's.
-Currently it requires a patched version of gcc-4.5.
-The plugin can target the x86-32 and x86-64 processor families and has been
-used successfully on the Darwin, FreeBSD and Linux platforms.
-The Ada, C, C++ and Fortran languages work well.
-The plugin is capable of compiling plenty of Obj-C, Obj-C++ and Java but it is
-not known whether the compiled code actually works or not!
-</p>
+<p><a href="http://dragonegg.llvm.org/">DragonEgg</a> is a
+   <a href="http://gcc.gnu.org/wiki/plugins">gcc plugin</a> that replaces GCC's
+   optimizers and code generators with LLVM's. Currently it requires a patched
+   version of gcc-4.5.  The plugin can target the x86-32 and x86-64 processor
+   families and has been used successfully on the Darwin, FreeBSD and Linux
+   platforms.  The Ada, C, C++ and Fortran languages work well.  The plugin is
+   capable of compiling plenty of Obj-C, Obj-C++ and Java but it is not known
+   whether the compiled code actually works or not!</p>
+
+<p>The 3.0 release has the following notable changes:</p>
 
-<p>
-The 3.0 release has the following notable changes:
 <ul>
 <!--
 <li></li>
@@ -160,15 +168,15 @@
 </h3>
 
 <div>
-<p>
-The new LLVM <a href="http://compiler-rt.llvm.org/">compiler-rt project</a>
-is a simple library that provides an implementation of the low-level
-target-specific hooks required by code generation and other runtime components.
-For example, when compiling for a 32-bit target, converting a double to a 64-bit
-unsigned integer is compiled into a runtime call to the "__fixunsdfdi"
-function. The compiler-rt library provides highly optimized implementations of
-this and other low-level routines (some are 3x faster than the equivalent
-libgcc routines).</p>
+
+<p>The new LLVM <a href="http://compiler-rt.llvm.org/">compiler-rt project</a>
+   is a simple library that provides an implementation of the low-level
+   target-specific hooks required by code generation and other runtime
+   components.  For example, when compiling for a 32-bit target, converting a
+   double to a 64-bit unsigned integer is compiled into a runtime call to the
+   "__fixunsdfdi" function. The compiler-rt library provides highly optimized
+   implementations of this and other low-level routines (some are 3x faster than
+   the equivalent libgcc routines).</p>
 
 <p>In the LLVM 3.0 timeframe,</p>
 
@@ -180,19 +188,12 @@
 </h3>
 
 <div>
-<p>
-<a href="http://lldb.llvm.org/">LLDB</a> is a brand new member of the LLVM
-umbrella of projects. LLDB is a next generation, high-performance debugger. It
-is built as a set of reusable components which highly leverage existing
-libraries in the larger LLVM Project, such as the Clang expression parser, the
-LLVM disassembler and the LLVM JIT.</p>
 
-<p>
-LLDB is has advanced by leaps and bounds in the 3.0 timeframe.  It is
-dramatically more stable and useful, and includes both a new <a 
-href="http://lldb.llvm.org/tutorial.html">tutorial</a> and a <a
-href="http://lldb.llvm.org/lldb-gdb.html">side-by-side comparison with 
-GDB</a>.</p>
+<p>LLDB has advanced by leaps and bounds in the 3.0 timeframe.  It is
+   dramatically more stable and useful, and includes both a
+   new <a href="http://lldb.llvm.org/tutorial.html">tutorial</a> and
+   a <a href="http://lldb.llvm.org/lldb-gdb.html">side-by-side comparison with
+   GDB</a>.</p>
 
 </div>
 
@@ -202,20 +203,10 @@
 </h3>
 
 <div>
-<p>
-<a href="http://libcxx.llvm.org/">libc++</a> is another new member of the LLVM
-family.  It is an implementation of the C++ standard library, written from the
-ground up to specifically target the forthcoming C++'0X standard and focus on
-delivering great performance.</p>
 
-<p>
-In the LLVM 3.0 timeframe,</p>
-  
-<p>
-Like compiler_rt, libc++ is now <a href="DeveloperPolicy.html#license">dual
-  licensed</a> under the MIT and UIUC license, allowing it to be used more
-  permissively.
-</p>
+<p>Like compiler_rt, libc++ is now <a href="DeveloperPolicy.html#license">dual
+   licensed</a> under the MIT and UIUC license, allowing it to be used more
+   permissively.</p>
 
 </div>
 
@@ -226,13 +217,14 @@
 </h3>
 
 <div>
-<p>
-<a href="http://llvm.org/svn/llvm-project/llbrowse/trunk/doc/LLBrowse.html">
-  LLBrowse</a> is an interactive viewer for LLVM modules. It can load any LLVM
-  module and displays its contents as an expandable tree view, facilitating an
-  easy way to inspect types, functions, global variables, or metadata nodes. It
-  is fully cross-platform, being based on the popular wxWidgets GUI toolkit.
-</p>
+
+<p><a href="http://llvm.org/svn/llvm-project/llbrowse/trunk/doc/LLBrowse.html">
+   LLBrowse</a> is an interactive viewer for LLVM modules. It can load any LLVM
+   module and displays its contents as an expandable tree view, facilitating an
+   easy way to inspect types, functions, global variables, or metadata nodes. It
+   is fully cross-platform, being based on the popular wxWidgets GUI
+   toolkit.</p>
+
 </div>
 
 <!--=========================================================================-->
@@ -241,13 +233,14 @@
 </h3>
 
 <div>
+
 <p>The <a href="http://vmkit.llvm.org/">VMKit project</a> is an implementation
-  of a Java Virtual Machine (Java VM or JVM) that uses LLVM for static and
-  just-in-time compilation. As of LLVM 3.0, VMKit now supports generational
-  garbage collectors. The garbage collectors are provided by the MMTk framework,
-  and VMKit can be configured to use one of the numerous implemented collectors
-  of MMTk.
-</p>
+   of a Java Virtual Machine (Java VM or JVM) that uses LLVM for static and
+   just-in-time compilation. As of LLVM 3.0, VMKit now supports generational
+   garbage collectors. The garbage collectors are provided by the MMTk
+   framework, and VMKit can be configured to use one of the numerous implemented
+   collectors of MMTk.</p>
+
 </div>
   
   
@@ -501,14 +494,14 @@
    co-design flow from C/C++ programs down to synthesizable VHDL and parallel
    program binaries. Processor customization points include the register files,
    function units, supported operations, and the interconnection network.</p>
-
+  
 <p>TCE uses Clang and LLVM for C/C++ language support, target independent
    optimizations and also for parts of code generation. It generates new
-   LLVM-based code generators <i>on the fly</i> for the designed TTA processors
-   and loads them in to the compiler backend as runtime libraries to avoid
+   LLVM-based code generators "on the fly" for the designed TTA processors and
+   loads them in to the compiler backend as runtime libraries to avoid
    per-target recompilation of larger parts of the compiler chain.</p>
-</div>
 
+</div>
   
 <!--=========================================================================-->
 <h3>Tart Programming Language</h3>
@@ -657,9 +650,8 @@
 <div>
 
 <p>This release includes a huge number of bug fixes, performance tweaks and
-minor improvements.  Some of the major improvements and new features are listed
-in this section.
-</p>
+   minor improvements.  Some of the major improvements and new features are
+   listed in this section.</p>
 
 <!--=========================================================================-->
 <h3>
@@ -686,8 +678,9 @@
 </h3>
 
 <div>
+
 <p>LLVM IR has several new features for better support of new targets and that
-expose new optimization opportunities:</p>
+   expose new optimization opportunities:</p>
 
 <p>One of the biggest changes is that 3.0 has a new exception handling
    system. The old system used LLVM intrinsics to convey the exception handling
@@ -810,7 +803,8 @@
 <div>
 
 <p>In addition to a large array of minor performance tweaks and bug fixes, this
-release includes a few major enhancements and additions to the optimizers:</p>
+   release includes a few major enhancements and additions to the
+   optimizers:</p>
 
 <ul>
 <!--
@@ -828,11 +822,11 @@
 </h3>
 
 <div>
-<p>
-The LLVM Machine Code (aka MC) subsystem was created to solve a number
-of problems in the realm of assembly, disassembly, object file format handling,
-and a number of other related areas that CPU instruction-set level tools work
-in.</p>
+
+<p>The LLVM Machine Code (aka MC) subsystem was created to solve a number of
+   problems in the realm of assembly, disassembly, object file format handling,
+   and a number of other related areas that CPU instruction-set level tools work
+   in.</p>
 
 <ul>
 <!--
@@ -840,10 +834,9 @@
 -->
 </ul>
 
-<p>For more information, please see the <a
-href="http://blog.llvm.org/2010/04/intro-to-llvm-mc-project.html">Intro to the
-LLVM MC Project Blog Post</a>.
-</p>
+<p>For more information, please see
+   the <a href="http://blog.llvm.org/2010/04/intro-to-llvm-mc-project.html">Intro
+   to the LLVM MC Project Blog Post</a>.</p>
 
 </div>
 
@@ -855,8 +848,8 @@
 <div>
 
 <p>We have put a significant amount of work into the code generator
-infrastructure, which allows us to implement more aggressive algorithms and make
-it run faster:</p>
+   infrastructure, which allows us to implement more aggressive algorithms and
+   make it run faster:</p>
 
 <ul>
 <!--
@@ -871,14 +864,16 @@
 </h3>
 
 <div>
-<p>New features and major changes in the X86 target include:
-</p>
+
+<p>New features and major changes in the X86 target include:</p>
 
 <ul>
-<li>The CRC32 intrinsics have been renamed.  The intrinsics were previously
-  @llvm.x86.sse42.crc32.[8|16|32] and @llvm.x86.sse42.crc64.[8|64].  They have
-  been renamed to @llvm.x86.sse42.crc32.32.[8|16|32] and 
-  @llvm.x86.sse42.crc32.64.[8|64].</li>
+
+  <li>The CRC32 intrinsics have been renamed.  The intrinsics were previously
+      <code>@llvm.x86.sse42.crc32.[8|16|32]</code>
+      and <code>@llvm.x86.sse42.crc64.[8|64]</code>. They have been renamed to
+      <code>@llvm.x86.sse42.crc32.32.[8|16|32]</code> and
+      <code>@llvm.x86.sse42.crc32.64.[8|64]</code>.</li>
 
 </ul>
 
@@ -890,8 +885,8 @@
 </h3>
 
 <div>
-<p>New features of the ARM target include:
-</p>
+
+<p>New features of the ARM target include:</p>
 
 <ul>
 <!--
@@ -906,11 +901,13 @@
 </h3>
 
 <div>
+
 <ul>
 <!--
 <li></li>
 -->
 </ul>
+
 </div>
 
 <!--=========================================================================-->
@@ -942,10 +939,12 @@
 
 <h4>Windows (32-bit)</h4>
 <div>
+
 <ul>
   <li>On Win32(MinGW32 and MSVC), Windows 2000 will not be supported.
       Windows XP or higher is required.</li>
 </ul>
+
 </div>
 
 </div>
@@ -961,24 +960,25 @@
    LLVM API changes are:</p>
 
 <ul>
-<li>The biggest and most pervasive change is that llvm::Type's are no longer
-    returned or accepted as 'const' values.  Instead, just pass around non-const
-    Type's.</li>
-  
-<li><code>PHINode::reserveOperandSpace</code> has been removed. Instead, you
-  must specify how many operands to reserve space for when you create the
-  PHINode, by passing an extra argument into <code>PHINode::Create</code>.</li>
-
-<li>PHINodes no longer store their incoming BasicBlocks as operands. Instead,
-  the list of incoming BasicBlocks is stored separately, and can be accessed
-  with new functions <code>PHINode::block_begin</code>
-  and <code>PHINode::block_end</code>.</li>
-
-<li>Various functions now take an <code>ArrayRef</code> instead of either a pair
-  of pointers (or iterators) to the beginning and end of a range, or a pointer
-  and a length. Others now return an <code>ArrayRef</code> instead of a
-  reference to a <code>SmallVector</code> or <code>std::vector</code>. These
-  include:
+  <li>The biggest and most pervasive change is that llvm::Type's are no longer
+      returned or accepted as 'const' values.  Instead, just pass around
+      non-const Type's.</li>
+  
+  <li><code>PHINode::reserveOperandSpace</code> has been removed. Instead, you
+      must specify how many operands to reserve space for when you create the
+      PHINode, by passing an extra argument
+      into <code>PHINode::Create</code>.</li>
+
+  <li>PHINodes no longer store their incoming BasicBlocks as operands. Instead,
+      the list of incoming BasicBlocks is stored separately, and can be accessed
+      with new functions <code>PHINode::block_begin</code>
+      and <code>PHINode::block_end</code>.</li>
+
+  <li>Various functions now take an <code>ArrayRef</code> instead of either a
+      pair of pointers (or iterators) to the beginning and end of a range, or a
+      pointer and a length. Others now return an <code>ArrayRef</code> instead
+      of a reference to a <code>SmallVector</code>
+      or <code>std::vector</code>. These include:
 <ul>
 <!-- Please keep this list sorted. -->
 <li><code>CallInst::Create</code></li>
@@ -1021,44 +1021,45 @@
 <li><code>TargetData::getIndexedOffset</code></li>
 </ul></li>
 
-<li>All forms of <code>StringMap::getOrCreateValue</code> have been remove
-  except for the one which takes a <code>StringRef</code>.</li>
-
-<li>The <code>LLVMBuildUnwind</code> function from the C API was removed. The
-    LLVM <code>unwind</code> instruction has been deprecated for a long time and
-    isn't used by the current front-ends. So this was removed during the
-    exception handling rewrite.</li>
-
-<li>The <code>LLVMAddLowerSetJmpPass</code> function from the C API was removed
-    because the <code>LowerSetJmp</code> pass was removed.</li>
-
-<li>The <code>DIBuilder</code> interface used by front ends to encode debugging 
-    information in the LLVM IR now expects clients to use <code>DIBuilder::finalize()</code>
-    at the end of translation unit to complete debugging information encoding.</li>
-
-<li>The way the type system works has been rewritten: <code>PATypeHolder</code>
-and <code>OpaqueType</code> are gone, and all APIs deal with <code>Type*</code>
-instead of <code>const Type*</code>.
-If you need to create recursive structures, then create a named structure,
-and use <code>setBody()</code> when all its elements are built.
-Type merging and refining is gone too: named structures are not
-merged with other structures, even if their layout is identical.
-(of course anonymous structures are still uniqued by layout).
-</li>
-
-<li>TargetSelect.h moved to Support/ from Target/</li>
-
-<li>UpgradeIntrinsicCall no longer upgrades pre-2.9 intrinsic calls
-(for example <code>llvm.memset.i32</code>).</li>
-
-<li>It is mandatory to initialize all out-of-tree passes too and their dependencies now with
-<code>INITIALIZE_PASS{BEGIN,END,}</code> and <code>INITIALIZE_{PASS,AG}_DEPENDENCY</code>.</li>
-
-<li>The interface for MemDepResult in MemoryDependenceAnalysis has been enhanced
-    with new return types Unknown and NonFuncLocal, in addition to the existing
-    types Clobber, Def, and NonLocal.</li>
+  <li>All forms of <code>StringMap::getOrCreateValue</code> have been remove
+      except for the one which takes a <code>StringRef</code>.</li>
 
+  <li>The <code>LLVMBuildUnwind</code> function from the C API was removed. The
+      LLVM <code>unwind</code> instruction has been deprecated for a long time
+      and isn't used by the current front-ends. So this was removed during the
+      exception handling rewrite.</li>
+
+  <li>The <code>LLVMAddLowerSetJmpPass</code> function from the C API was
+      removed because the <code>LowerSetJmp</code> pass was removed.</li>
+
+  <li>The <code>DIBuilder</code> interface used by front ends to encode
+      debugging information in the LLVM IR now expects clients to
+      use <code>DIBuilder::finalize()</code> at the end of translation unit to
+      complete debugging information encoding.</li>
+
+  <li>The way the type system works has been
+      rewritten: <code>PATypeHolder</code> and <code>OpaqueType</code> are gone,
+      and all APIs deal with <code>Type*</code> instead of <code>const
+      Type*</code>.  If you need to create recursive structures, then create a
+      named structure, and use <code>setBody()</code> when all its elements are
+      built.  Type merging and refining is gone too: named structures are not
+      merged with other structures, even if their layout is identical.  (of
+      course anonymous structures are still uniqued by layout).</li>
+
+  <li>TargetSelect.h moved to Support/ from Target/</li>
+
+  <li>UpgradeIntrinsicCall no longer upgrades pre-2.9 intrinsic calls (for
+      example <code>llvm.memset.i32</code>).</li>
+
+  <li>It is mandatory to initialize all out-of-tree passes too and their dependencies now with
+      <code>INITIALIZE_PASS{BEGIN,END,}</code>
+      and <code>INITIALIZE_{PASS,AG}_DEPENDENCY</code>.</li>
+
+  <li>The interface for MemDepResult in MemoryDependenceAnalysis has been
+      enhanced with new return types Unknown and NonFuncLocal, in addition to
+      the existing types Clobber, Def, and NonLocal.</li>
 </ul>
+
 </div>
 
 </div>
@@ -1071,10 +1072,10 @@
 
 <div>
 
-<p>This section contains significant known problems with the LLVM system,
-listed by component.  If you run into a problem, please check the <a
-href="http://llvm.org/bugs/">LLVM bug database</a> and submit a bug if
-there isn't already one.</p>
+<p>This section contains significant known problems with the LLVM system, listed
+   by component.  If you run into a problem, please check
+   the <a href="http://llvm.org/bugs/">LLVM bug database</a> and submit a bug if
+   there isn't already one.</p>
 
 <!-- ======================================================================= -->
 <h3>
@@ -1084,18 +1085,19 @@
 <div>
 
 <p>The following components of this LLVM release are either untested, known to
-be broken or unreliable, or are in early development.  These components should
-not be relied on, and bugs should not be filed against them, but they may be
-useful to some people.  In particular, if you would like to work on one of these
-components, please contact us on the <a
-href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVMdev list</a>.</p>
+   be broken or unreliable, or are in early development.  These components
+   should not be relied on, and bugs should not be filed against them, but they
+   may be useful to some people.  In particular, if you would like to work on
+   one of these components, please contact us on
+   the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVMdev
+   list</a>.</p>
 
 <ul>
-<li>The Alpha, CellSPU, MicroBlaze, MSP430, MIPS, PTX,
-    and XCore backends are experimental.</li>
-<li><tt>llc</tt> "<tt>-filetype=obj</tt>" is experimental on all targets
-    other than darwin and ELF X86 systems.</li>
-    
+  <li>The Alpha, Blackfin, CellSPU, MicroBlaze, MSP430, MIPS, PTX, SystemZ and
+      XCore backends are experimental.</li>
+
+  <li><tt>llc</tt> "<tt>-filetype=obj</tt>" is experimental on all targets other
+      than darwin and ELF X86 systems.</li>
 </ul>
 
 </div>
@@ -1109,23 +1111,28 @@
 
 <ul>
   <li>The X86 backend does not yet support
-    all <a href="http://llvm.org/PR879">inline assembly that uses the X86
-    floating point stack</a>.  It supports the 'f' and 't' constraints, but not
-    'u'.</li>
+      all <a href="http://llvm.org/PR879">inline assembly that uses the X86
+      floating point stack</a>.  It supports the 'f' and 't' constraints, but
+      not 'u'.</li>
+
   <li>The X86-64 backend does not yet support the LLVM IR instruction
-      <tt>va_arg</tt>. Currently, front-ends support variadic
-      argument constructs on X86-64 by lowering them manually.</li>
+      <tt>va_arg</tt>. Currently, front-ends support variadic argument
+      constructs on X86-64 by lowering them manually.</li>
+
   <li>Windows x64 (aka Win64) code generator has a few issues.
     <ul>
-      <li>llvm-gcc cannot build the mingw-w64 runtime currently
-       due to lack of support for the 'u' inline assembly
-       constraint and for X87 floating point inline assembly.</li>
-      <li>On mingw-w64, you will see unresolved symbol <tt>__chkstk</tt>
-       due to <a href="http://llvm.org/bugs/show_bug.cgi?id=8919">Bug 8919</a>.
-       It is fixed in <a href="http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110321/118499.html">r128206</a>.</li>
+      <li>llvm-gcc cannot build the mingw-w64 runtime currently due to lack of
+          support for the 'u' inline assembly constraint and for X87 floating
+          point inline assembly.</li>
+
+      <li>On mingw-w64, you will see unresolved symbol <tt>__chkstk</tt> due
+          to <a href="http://llvm.org/bugs/show_bug.cgi?id=8919">Bug 8919</a>.
+          It is fixed
+          in <a href="http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110321/118499.html">r128206</a>.</li>
+
       <li>Miss-aligned MOVDQA might crash your program. It is due to
-       <a href="http://llvm.org/bugs/show_bug.cgi?id=9483">Bug 9483</a>,
-       lack of handling aligned internal globals.</li>
+          <a href="http://llvm.org/bugs/show_bug.cgi?id=9483">Bug 9483</a>, lack
+          of handling aligned internal globals.</li>
       </ul>
   </li>
 
@@ -1141,8 +1148,8 @@
 <div>
 
 <ul>
-<li>The Linux PPC32/ABI support needs testing for the interpreter and static
-compilation, and lacks support for debug information.</li>
+  <li>The Linux PPC32/ABI support needs testing for the interpreter and static
+      compilation, and lacks support for debug information.</li>
 </ul>
 
 </div>
@@ -1155,11 +1162,12 @@
 <div>
 
 <ul>
-<li>Thumb mode works only on ARMv6 or higher processors. On sub-ARMv6
-processors, thumb programs can crash or produce wrong
-results (<a href="http://llvm.org/PR1388">PR1388</a>).</li>
-<li>Compilation for ARM Linux OABI (old ABI) is supported but not fully tested.
-</li>
+  <li>Thumb mode works only on ARMv6 or higher processors. On sub-ARMv6
+      processors, thumb programs can crash or produce wrong results
+      (<a href="http://llvm.org/PR1388">PR1388</a>).</li>
+
+  <li>Compilation for ARM Linux OABI (old ABI) is supported but not fully
+      tested.</li>
 </ul>
 
 </div>
@@ -1172,8 +1180,8 @@
 <div>
 
 <ul>
-<li>The SPARC backend only supports the 32-bit SPARC ABI (-m32); it does not
-    support the 64-bit SPARC ABI (-m64).</li>
+  <li>The SPARC backend only supports the 32-bit SPARC ABI (-m32); it does not
+      support the 64-bit SPARC ABI (-m64).</li>
 </ul>
 
 </div>
@@ -1186,7 +1194,7 @@
 <div>
 
 <ul>
-<li>64-bit MIPS targets are not supported yet.</li>
+  <li>64-bit MIPS targets are not supported yet.</li>
 </ul>
 
 </div>
@@ -1199,11 +1207,10 @@
 <div>
 
 <ul>
-
-<li>On 21164s, some rare FP arithmetic sequences which may trap do not have the
-appropriate nops inserted to ensure restartability.</li>
-
+  <li>On 21164s, some rare FP arithmetic sequences which may trap do not have
+      the appropriate nops inserted to ensure restartability.</li>
 </ul>
+
 </div>
 
 <!-- ======================================================================= -->
@@ -1214,16 +1221,19 @@
 <div>
 
 <p>The C backend has numerous problems and is not being actively maintained.
-Depending on it for anything serious is not advised.</p>
+   Depending on it for anything serious is not advised.</p>
 
 <ul>
-<li><a href="http://llvm.org/PR802">The C backend has only basic support for
-    inline assembly code</a>.</li>
-<li><a href="http://llvm.org/PR1658">The C backend violates the ABI of common
-    C++ programs</a>, preventing intermixing between C++ compiled by the CBE and
-    C++ code compiled with <tt>llc</tt> or native compilers.</li>
-<li>The C backend does not support all exception handling constructs.</li>
-<li>The C backend does not support arbitrary precision integers.</li>
+  <li><a href="http://llvm.org/PR802">The C backend has only basic support for
+      inline assembly code</a>.</li>
+
+  <li><a href="http://llvm.org/PR1658">The C backend violates the ABI of common
+      C++ programs</a>, preventing intermixing between C++ compiled by the CBE
+      and C++ code compiled with <tt>llc</tt> or native compilers.</li>
+
+  <li>The C backend does not support all exception handling constructs.</li>
+
+  <li>The C backend does not support arbitrary precision integers.</li>
 </ul>
 
 </div>
@@ -1236,7 +1246,7 @@
 
 <div>
 
-<p><b>LLVM 3.0 will be the last release of llvm-gcc.</b></p>
+<p><b>LLVM 2.9 was the last release of llvm-gcc.</b></p>
 
 <p>llvm-gcc is generally very stable for the C family of languages.  The only
    major language feature of GCC not supported by llvm-gcc is the
@@ -1253,8 +1263,9 @@
    <a href="#dragonegg">dragonegg</a> instead.</p>
 
 <p>The llvm-gcc 4.2 Ada compiler has basic functionality, but is no longer being
-actively maintained.  If you are interested in Ada, we recommend that you
-consider using <a href="#dragonegg">dragonegg</a> instead.</p>
+   actively maintained.  If you are interested in Ada, we recommend that you
+   consider using <a href="#dragonegg">dragonegg</a> instead.</p>
+
 </div>
 
 </div>
@@ -1267,17 +1278,16 @@
 
 <div>
 
-<p>A wide variety of additional information is available on the <a
-href="http://llvm.org/">LLVM web page</a>, in particular in the <a
-href="http://llvm.org/docs/">documentation</a> section.  The web page also
-contains versions of the API documentation which is up-to-date with the
-Subversion version of the source code.
-You can access versions of these documents specific to this release by going
-into the "<tt>llvm/doc/</tt>" directory in the LLVM tree.</p>
+<p>A wide variety of additional information is available on
+   the <a href="http://llvm.org/">LLVM web page</a>, in particular in
+   the <a href="http://llvm.org/docs/">documentation</a> section.  The web page
+   also contains versions of the API documentation which is up-to-date with the
+   Subversion version of the source code.  You can access versions of these
+   documents specific to this release by going into the "<tt>llvm/doc/</tt>"
+   directory in the LLVM tree.</p>
 
 <p>If you have any questions or comments about LLVM, please feel free to contact
-us via the <a href="http://llvm.org/docs/#maillist"> mailing
-lists</a>.</p>
+   us via the <a href="http://llvm.org/docs/#maillist"> mailing lists</a>.</p>
 
 </div>
 



From stpworld at narod.ru  Wed Oct 26 13:57:52 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Wed, 26 Oct 2011 22:57:52 +0400
Subject: [llvm-commits] [LLVM,
	llvm-objdump] Fix for clang-native-arm-cortex-a9.
In-Reply-To: <E7BD9520-EDC1-4BCB-8A99-8A30ECF1C370@apple.com>
References: <4EA67DE3.8060803@narod.ru> <4EA7DF2B.2070100@narod.ru>
	<E7BD9520-EDC1-4BCB-8A99-8A30ECF1C370@apple.com>
Message-ID: <4EA85830.8080701@narod.ru>

Yes, I have.

-Stepan.

Bill Wendling wrote:
> This looks fine to me. Do you have commit access?
>
> -bw
>
> On Oct 26, 2011, at 3:21 AM, Stepan Dyatkovskiy wrote:
>
>> ping.
>>
>> Regards,
>> Stepan.
>>
>> Stepan Dyatkovskiy wrote:
>>> Hi all,
>>>
>>> Please find the patch in attachment that fixes llvm-objdump test
>>> failures for clang-native-arm-cortex-a9.
>>>
>>> Regards,
>>> Stepan.
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From evan.cheng at apple.com  Wed Oct 26 14:32:30 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 26 Oct 2011 12:32:30 -0700
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <B0B56AD4-3A51-4283-907C-DACC97CA8231@apple.com>
References: <20111019141108.15BB73128018@llvm.org>
	<8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
	<CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>
	<CA+Ov9+krA4yc8mvBGbWSYCgaNMOtMTMA7SYsthtRny2Rp0uoCQ@mail.gmail.com>
	<003401cc93b2$2f4c40d0$8de4c270$%molloy@arm.com>
	<5E97CD9C-A2E0-457A-9190-20C18B02E691@mac.com>
	<B0B56AD4-3A51-4283-907C-DACC97CA8231@apple.com>
Message-ID: <CEBD5B85-C291-49C4-AFE5-98EBBB730C01@apple.com>


On Oct 26, 2011, at 11:22 AM, Chris Lattner wrote:

> 
> On Oct 26, 2011, at 9:50 AM, Owen Anderson wrote:
> 
>> 
>> On Oct 26, 2011, at 12:37 AM, James Molloy wrote:
>> 
>>> I also heavily dislike the Darwin-specific stuff in the backend and the
>>> whole idea of "We don't want to do this for Darwin" - if something is a
>>> negative tradeoff, have an appropriate target-independent knob that can be
>>> turned to a different position for Darwin.
>> 
>> +1
>> 
>> I think the real issue here is that we don't have a way to distinguish -Os vs. -Oz at the IR level.  Perhaps we need a new function attribute to distinguish the two, though I don't know a good name for it offhand.  Then "We don't want this for Darwin" just becomes a policy decision in the driver.
> 
> I think we just want another attribute, just like OptimizeForSize but the Oz variant.  Maybe OptimizeForSizeHarder ;-)

Chris, you should go into marketing. :-)

Also note, there are cases where we should use loads in place of movw / movt even without -Oz. More specifically, in cases where we can combine multiple constantpool entries into one. We can then issue ldrd / ldm etc. for load multiple constantpool entries with a single instruction. However, there are several dependencies for this optimization.

1. LLVM needs to be able to model multi-literal constantpool entries (shouldn't be too hard)
2. We need to be able to model register sequences
3. Register allocator needs to be able rematerialize loads from individual entries.
4. The constantpool island pass should be able to handle these combined constantpool entries.
5. Test various ARM variants to understand what scenarios are actual wins.

Evan


> 
> -Chris
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From rafael.espindola at gmail.com  Wed Oct 26 15:26:28 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Wed, 26 Oct 2011 16:26:28 -0400
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <B0B56AD4-3A51-4283-907C-DACC97CA8231@apple.com>
References: <20111019141108.15BB73128018@llvm.org>
	<8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
	<CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>
	<CA+Ov9+krA4yc8mvBGbWSYCgaNMOtMTMA7SYsthtRny2Rp0uoCQ@mail.gmail.com>
	<003401cc93b2$2f4c40d0$8de4c270$%molloy@arm.com>
	<5E97CD9C-A2E0-457A-9190-20C18B02E691@mac.com>
	<B0B56AD4-3A51-4283-907C-DACC97CA8231@apple.com>
Message-ID: <4EA86CF4.8040704@gmail.com>

> I think we just want another attribute, just like OptimizeForSize but
> the Oz variant.  Maybe OptimizeForSizeHarder ;-)

Do you have an example or two of things that should go in 
OptimizeForSize or OptimizeForSizeHarder?

I find the current description of -Os a bit hard to understand. If it 
introduces no performance regression, why it is not in -O2?

A quick look a the code suggest that we could says that -Os is supposed 
to limit passes that can introduce code bloat like inlining or tail 
duplication. It should not be used for introducing tradeoffs in codegen. 
In summary, "don't bloat the code to make it faster".

The decisions for using slower but smaller code would go to -Oz.

Does this sound like a correct description?

> -Chris

Cheers,
Rafael



From bruno.cardoso at gmail.com  Wed Oct 26 15:18:59 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 26 Oct 2011 18:18:59 -0200
Subject: [llvm-commits] [PATCH][Review request] Mips direct object
	generation patch #4
In-Reply-To: <86AC779C188FE74F88F6494478B46332E82DBE@exchdb03.mips.com>
References: <86AC779C188FE74F88F6494478B46332E82DBE@exchdb03.mips.com>
Message-ID: <CACk9FxYSSt9egZ95aUcz3jVNYCrfftmsYBtU-y7Xi4oFGOOjRQ@mail.gmail.com>

Hi,

On Tue, Oct 25, 2011 at 10:13 PM, Carter, Jack <jcarter at mips.com> wrote:
> This is the fourth of six patches for Mips direct object generation.
>
> ??? lib/Target/Mips/MipsCodeEmitter.cpp
> ??? lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
> ??? lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

I believe you don't need the includes here:

+#include "llvm/Support/DataTypes.h"
+#include <string>
+

If you happen to need the first (which I don't believe you will),
include it in the .cpp file which needs it.
Also, merge this patch with another that change Mips*CodeEmitter files.

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From bruno.cardoso at gmail.com  Wed Oct 26 15:33:10 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 26 Oct 2011 18:33:10 -0200
Subject: [llvm-commits] [PATCH][Review request] Mips direct object
	generation patch #6 of 6
In-Reply-To: <86AC779C188FE74F88F6494478B46332E82DEA@exchdb03.mips.com>
References: <86AC779C188FE74F88F6494478B46332E82DEA@exchdb03.mips.com>
Message-ID: <CACk9FxbgspjNx9O_L7p1zjLo0_BHjhMpunqghHRorX03CYX8Xg@mail.gmail.com>

Hi,

On Tue, Oct 25, 2011 at 10:31 PM, Carter, Jack <jcarter at mips.com> wrote:
> This is the sixth of six patches for Mips direct object generation.
>
> With this final of six patches we can compile and execute a number of simple
> C tests beyond hello.c.
>
> ??? lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
> ??? lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
> ??? lib/Target/Mips/MipsInstrInfo.td
> ??? lib/Target/Mips/Makefile
>
> This patch is a bit meatier than the others, but is more exclusive to the
> Mips direct object production. Once again we tried to pattern after the
> other targets that have already done direct object generation.
>
> Future MIPS direct object generation patches will be fixes and enhancements
> based issues uncovered during testing.
>
> The patch is attached.

A good part of the patch uses 4 spaces instead of 2, please fix that!
Also, don't leave empty newlines here:

+    case Mips::fixup_Mips_LO16:
+    case Mips::fixup_Mips_PC16:
+
+        Value &= 0xffff;
+      break;

Here you don't need braces and don't place the comments above the if condition.

+       if (!Value) {
+           return;           // Doesn't change encoding.
+       }
+       unsigned Offset = Fixup.getOffset();
+       switch (Kind) {
+       default:

Remove the comment below and just leave the llvm_unreachable directly.
If you really want it to "break" here instead, please provide an
explanation of what it does and why in a comment (also don't need to
leave your name in the comment):

+           // I don't know why we get values that are not suppose to be
+           // written out here yet - JCC
+           break;
+         //llvm_unreachable("Unknown fixup kind!");

Proper indent the code below and remove braces:

+     };
+      if (Kind < FirstTargetFixupKind) {
+       return MCAsmBackend::getFixupKindInfo(Kind);
+     }

Ditto again about useless newlines, remove all of them in other places too:

+  if (MO.isReg()) {
+    unsigned Reg = MO.getReg();
+
+    unsigned RegNo = getMipsRegisterNumbering(Reg);
+    return RegNo;
+
+  }

Try to follow more closely llvm style, in the code below, don't use
names like "p_expr" or "e_kind" please:

+  } else if (MO.isExpr()) {
+    const MCExpr *p_expr = MO.getExpr();
+    MCExpr::ExprKind e_kind = p_expr->getKind();
+    if (e_kind == MCExpr::SymbolRef) {

On the snippet below, make this more readable, break it in some local
vars, and then return them.

+    return
+      (getMachineOpValue(MI,
+                         MI.getOperand(OpNo+1),
+                         Fixups) & 0xFFFF) | RegBits;

Also, look at the JIT implementation when implementing the function below:

+/// EncodeInstruction - Emit the instruction.
+/// Size the instruction (currently only 4 bytes and
+/// throwing away any macros.
+void MipsMCCodeEmitter::
+EncodeInstruction(const MCInst &MI, raw_ostream &OS,
+                  SmallVectorImpl<MCFixup> &Fixups) const
+{
+  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
+  unsigned opcode = MI.getOpcode();
+
+  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
+  int Size = Desc.getSize();
+  // If the opcode is a pseudo op its value will be 0 same as a nop
+  if ((!Binary) && (opcode != Mips::SLL) && (opcode != Mips::NOP)) {
+      return;
+  }
+
+  // For now all instructions are 4 bytes
+  Size = 4;
+
+  EmitConstant(Binary, Size, OS);
+}

You must use TSFlags to check for Pseudos, please look at
emitIntruction in MipsCodeEmitter, and do the same thing as possible.

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From peter at pcc.me.uk  Wed Oct 26 15:41:34 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Wed, 26 Oct 2011 20:41:34 -0000
Subject: [llvm-commits] [zorg] r143050 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20111026204134.907F4312800A@llvm.org>

Author: pcc
Date: Wed Oct 26 15:41:34 2011
New Revision: 143050

URL: http://llvm.org/viewvc/llvm-project?rev=143050&view=rev
Log:
Add a non-ancient version of python to $PATH

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=143050&r1=143049&r2=143050&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Wed Oct 26 15:41:34 2011
@@ -273,6 +273,7 @@
 # LLDB builders.
 def _get_lldb_builders():
     gcc_latest_env = {
+        'PATH': '/opt/cfarm/python2-latest/bin:/usr/local/bin:/usr/bin:/bin:/usr/games',
         'CC':  '/opt/cfarm/release/4.5.1/bin/gcc',
         'CXX': '/opt/cfarm/release/4.5.1/bin/g++'}
 



From resistor at mac.com  Wed Oct 26 15:42:54 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 26 Oct 2011 20:42:54 -0000
Subject: [llvm-commits] [llvm] r143051 - in /llvm/trunk:
 include/llvm/Object/MachO.h lib/Object/MachOObjectFile.cpp
Message-ID: <20111026204254.47253312800A@llvm.org>

Author: resistor
Date: Wed Oct 26 15:42:54 2011
New Revision: 143051

URL: http://llvm.org/viewvc/llvm-project?rev=143051&view=rev
Log:
Add support for scattered relocations to the MachO relocatation pretty printer.

Modified:
    llvm/trunk/include/llvm/Object/MachO.h
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/include/llvm/Object/MachO.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachO.h?rev=143051&r1=143050&r2=143051&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/MachO.h (original)
+++ llvm/trunk/include/llvm/Object/MachO.h Wed Oct 26 15:42:54 2011
@@ -18,6 +18,7 @@
 #include "llvm/Object/ObjectFile.h"
 #include "llvm/Object/MachOObject.h"
 #include "llvm/Support/MachO.h"
+#include "llvm/Support/raw_ostream.h"
 #include "llvm/ADT/SmallVector.h"
 
 namespace llvm {
@@ -110,7 +111,8 @@
                      InMemoryStruct<macho::RelocationEntry> &Res) const;
   std::size_t getSectionIndex(DataRefImpl Sec) const;
 
-  error_code getRelocationTargetName(uint32_t Idx, StringRef &S) const;
+  void printRelocationTargetName(InMemoryStruct<macho::RelocationEntry>& RE,
+                                 raw_string_ostream &fmt) const;
 };
 
 }

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=143051&r1=143050&r2=143051&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Wed Oct 26 15:42:54 2011
@@ -15,8 +15,8 @@
 #include "llvm/ADT/Triple.h"
 #include "llvm/Object/MachO.h"
 #include "llvm/Object/MachOFormat.h"
+#include "llvm/Support/Format.h"
 #include "llvm/Support/MemoryBuffer.h"
-#include "llvm/Support/raw_ostream.h"
 
 #include <cctype>
 #include <cstring>
@@ -609,7 +609,17 @@
   }
   InMemoryStruct<macho::RelocationEntry> RE;
   getRelocation(Rel, RE);
-  Res = reinterpret_cast<uintptr_t>(sectAddress + RE->Word0);
+
+  unsigned Arch = getArch();
+  bool isScattered = (Arch != Triple::x86_64) &&
+                     (RE->Word0 & macho::RF_Scattered);
+  uint64_t RelAddr = 0;
+  if (isScattered) 
+    RelAddr = RE->Word0 & 0xFFFFFF;
+  else
+    RelAddr = RE->Word0;
+
+  Res = reinterpret_cast<uintptr_t>(sectAddress + RelAddr);
   return object_error::success;
 }
 error_code MachOObjectFile::getRelocationSymbol(DataRefImpl Rel,
@@ -648,9 +658,17 @@
   StringRef res;
   InMemoryStruct<macho::RelocationEntry> RE;
   getRelocation(Rel, RE);
-  unsigned r_type = (RE->Word1 >> 28) & 0xF;
 
   unsigned Arch = getArch();
+  bool isScattered = (Arch != Triple::x86_64) &&
+                     (RE->Word0 & macho::RF_Scattered);
+
+  unsigned r_type;
+  if (isScattered)
+    r_type = (RE->Word0 >> 24) & 0xF;
+  else
+    r_type = (RE->Word1 >> 28) & 0xF;
+
   switch (Arch) {
     case Triple::x86: {
       const char* Table[] =  {
@@ -771,23 +789,56 @@
     report_fatal_error(ec.message());
 }
 
-error_code
-MachOObjectFile::getRelocationTargetName(uint32_t Idx, StringRef &S) const {
-  bool isExtern = (Idx >> 27) & 1;
-  uint32_t Val = Idx & 0xFFFFFF;
-  error_code ec;
+void MachOObjectFile::printRelocationTargetName(
+                                     InMemoryStruct<macho::RelocationEntry>& RE,
+                                     raw_string_ostream &fmt) const {
+  unsigned Arch = getArch();
+  bool isScattered = (Arch != Triple::x86_64) &&
+                     (RE->Word0 & macho::RF_Scattered);
+
+  // Target of a scattered relocation is an address.  In the interest of
+  // generating pretty output, scan through the symbol table looking for a
+  // symbol that aligns with that address.  If we find one, print it.
+  // Otherwise, we just print the hex address of the target.
+  if (isScattered) {
+    uint32_t Val = RE->Word1;
+
+    error_code ec;
+    for (symbol_iterator SI = begin_symbols(), SE = end_symbols(); SI != SE;
+        SI.increment(ec)) {
+      if (ec) report_fatal_error(ec.message());
+
+      uint64_t Addr;
+      StringRef Name;
+
+      if ((ec = SI->getAddress(Addr)))
+        report_fatal_error(ec.message());
+      if (Addr != Val) continue;
+      if ((ec = SI->getName(Name)))
+        report_fatal_error(ec.message());
+      fmt << Name;
+      return;
+    }
+
+    fmt << format("0x%x", Val);
+    return;
+  }
+
+  StringRef S;
+  bool isExtern = (RE->Word1 >> 27) & 1;
+  uint32_t Val = RE->Word1 & 0xFFFFFF;
 
   if (isExtern) {
     symbol_iterator SI = begin_symbols();
     advanceTo(SI, Val);
-    ec = SI->getName(S);
+    SI->getName(S);
   } else {
     section_iterator SI = begin_sections();
     advanceTo(SI, Val);
-    ec = SI->getName(S);
+    SI->getName(S);
   }
 
-  return ec;
+  fmt << S;
 }
 
 error_code MachOObjectFile::getRelocationValueString(DataRefImpl Rel,
@@ -795,30 +846,35 @@
   InMemoryStruct<macho::RelocationEntry> RE;
   getRelocation(Rel, RE);
 
-  unsigned Type = (RE->Word1 >> 28) & 0xF;
+  unsigned Arch = getArch();
+  bool isScattered = (Arch != Triple::x86_64) &&
+                     (RE->Word0 & macho::RF_Scattered);
 
   std::string fmtbuf;
   raw_string_ostream fmt(fmtbuf);
 
+  unsigned Type;
+  if (isScattered)
+    Type = (RE->Word0 >> 24) & 0xF;
+  else
+    Type = (RE->Word1 >> 28) & 0xF;
+
   // Determine any addends that should be displayed with the relocation.
   // These require decoding the relocation type, which is triple-specific.
-  unsigned Arch = getArch();
 
   // X86_64 has entirely custom relocation types.
   if (Arch == Triple::x86_64) {
-    StringRef Name;
-    if (error_code ec = getRelocationTargetName(RE->Word1, Name))
-      report_fatal_error(ec.message());
     bool isPCRel = ((RE->Word1 >> 24) & 1);
 
     switch (Type) {
-      case 3:   // X86_64_RELOC_GOT_LOAD
-      case 4: { // X86_64_RELOC_GOT
-        fmt << Name << "@GOT";
+      case macho::RIT_X86_64_GOTLoad:   // X86_64_RELOC_GOT_LOAD
+      case macho::RIT_X86_64_GOT: {     // X86_64_RELOC_GOT
+        printRelocationTargetName(RE, fmt);
+        fmt << "@GOT";
         if (isPCRel) fmt << "PCREL";
         break;
       }
-      case 5: { // X86_64_RELOC_SUBTRACTOR
+      case macho::RIT_X86_64_Subtractor: { // X86_64_RELOC_SUBTRACTOR
         InMemoryStruct<macho::RelocationEntry> RENext;
         DataRefImpl RelNext = Rel;
         RelNext.d.a++;
@@ -826,40 +882,42 @@
 
         // X86_64_SUBTRACTOR must be followed by a relocation of type
         // X86_64_RELOC_UNSIGNED.
+        // NOTE: Scattered relocations don't exist on x86_64.
         unsigned RType = (RENext->Word1 >> 28) & 0xF;
         if (RType != 0)
           report_fatal_error("Expected X86_64_RELOC_UNSIGNED after "
                              "X86_64_RELOC_SUBTRACTOR.");
 
-        StringRef SucName;
-        if (error_code ec = getRelocationTargetName(RENext->Word1, SucName))
-          report_fatal_error(ec.message());
-
         // The X86_64_RELOC_UNSIGNED contains the minuend symbol,
         // X86_64_SUBTRACTOR contains to the subtrahend.
-        fmt << SucName << "-" << Name;
+        printRelocationTargetName(RENext, fmt);
+        fmt << "-";
+        printRelocationTargetName(RE, fmt);
       }
-      case 6: // X86_64_RELOC_SIGNED1
-        fmt << Name << "-1";
+      case macho::RIT_X86_64_Signed1: // X86_64_RELOC_SIGNED1
+        printRelocationTargetName(RE, fmt);
+        fmt << "-1";
         break;
-      case 7: // X86_64_RELOC_SIGNED2
-        fmt << Name << "-2";
+      case macho::RIT_X86_64_Signed2: // X86_64_RELOC_SIGNED2
+        printRelocationTargetName(RE, fmt);
+        fmt << "-2";
         break;
-      case 8: // X86_64_RELOC_SIGNED4
-        fmt << Name << "-4";
+      case macho::RIT_X86_64_Signed4: // X86_64_RELOC_SIGNED4
+        printRelocationTargetName(RE, fmt);
+        fmt << "-4";
         break;
       default:
-        fmt << Name;
+        printRelocationTargetName(RE, fmt);
         break;
     }
   // X86 and ARM share some relocation types in common.
   } else if (Arch == Triple::x86 || Arch == Triple::arm) {
     // Generic relocation types...
     switch (Type) {
-      case 1: // GENERIC_RELOC_PAIR - prints no info
+      case macho::RIT_Pair: // GENERIC_RELOC_PAIR - prints no info
         return object_error::success;
-      case 2:   // GENERIC_RELOC_SECTDIFF
-      case 4: { // GENERIC_RELOC_LOCAL_SECTDIFF
+      case macho::RIT_Difference:                // GENERIC_RELOC_SECTDIFF
+      case macho::RIT_Generic_LocalDifference: { // GENERIC_RELOC_LOCAL_SECTDIFF
         InMemoryStruct<macho::RelocationEntry> RENext;
         DataRefImpl RelNext = Rel;
         RelNext.d.a++;
@@ -867,47 +925,46 @@
 
         // X86 sect diff's must be followed by a relocation of type
         // GENERIC_RELOC_PAIR.
-        unsigned RType = (RENext->Word1 >> 28) & 0xF;
+        bool isNextScattered = (Arch != Triple::x86_64) &&
+                               (RENext->Word0 & macho::RF_Scattered);
+        unsigned RType;
+        if (isNextScattered)
+          RType = (RENext->Word0 >> 24) & 0xF;
+        else
+          RType = (RENext->Word1 >> 28) & 0xF;
         if (RType != 1)
           report_fatal_error("Expected GENERIC_RELOC_PAIR after "
                              "GENERIC_RELOC_SECTDIFF or "
                              "GENERIC_RELOC_LOCAL_SECTDIFF.");
 
-        StringRef SucName;
-        if (error_code ec = getRelocationTargetName(RENext->Word1, SucName))
-          report_fatal_error(ec.message());
-
-        StringRef Name;
-        if (error_code ec = getRelocationTargetName(RE->Word1, Name))
-          report_fatal_error(ec.message());
-
-        fmt << Name << "-" << SucName;
+        printRelocationTargetName(RE, fmt);
+        fmt << "-";
+        printRelocationTargetName(RENext, fmt);
         break;
       }
     }
 
-    if (Arch == Triple::x86 && Type != 1) {
+    if (Arch == Triple::x86) {
       // All X86 relocations that need special printing were already
       // handled in the generic code.
-      StringRef Name;
-      if (error_code ec = getRelocationTargetName(RE->Word1, Name))
-        report_fatal_error(ec.message());
-      fmt << Name;
+      printRelocationTargetName(RE, fmt);
     } else { // ARM-specific relocations
       switch (Type) {
-        case 8:   // ARM_RELOC_HALF
-        case 9: { // ARM_RELOC_HALF_SECTDIFF
-          StringRef Name;
-          if (error_code ec = getRelocationTargetName(RE->Word1, Name))
-            report_fatal_error(ec.message());
-
+        case macho::RIT_ARM_Half:             // ARM_RELOC_HALF
+        case macho::RIT_ARM_HalfDifference: { // ARM_RELOC_HALF_SECTDIFF
           // Half relocations steal a bit from the length field to encode
           // whether this is an upper16 or a lower16 relocation.
-          bool isUpper = (RE->Word1 >> 25) & 1;
+          bool isUpper;
+          if (isScattered)
+            isUpper = (RE->Word0 >> 28) & 1;
+          else
+            isUpper = (RE->Word1 >> 25) & 1;
+
           if (isUpper)
-            fmt << ":upper16:(" << Name;
+            fmt << ":upper16:(";
           else
-            fmt << ":lower16:(" << Name;
+            fmt << ":lower16:(";
+          printRelocationTargetName(RE, fmt);
 
           InMemoryStruct<macho::RelocationEntry> RENext;
           DataRefImpl RelNext = Rel;
@@ -916,45 +973,40 @@
 
           // ARM half relocs must be followed by a relocation of type
           // ARM_RELOC_PAIR.
-          unsigned RType = (RENext->Word1 >> 28) & 0xF;
+          bool isNextScattered = (Arch != Triple::x86_64) &&
+                                 (RENext->Word0 & macho::RF_Scattered);
+          unsigned RType;
+          if (isNextScattered)
+            RType = (RENext->Word0 >> 24) & 0xF;
+          else
+            RType = (RENext->Word1 >> 28) & 0xF;
+
           if (RType != 1)
             report_fatal_error("Expected ARM_RELOC_PAIR after "
                                "GENERIC_RELOC_HALF");
 
-          // A constant addend for the relocation is stored in the address
-          // field of the follow-on relocation.  If this is a lower16 relocation
-          // we need to shift it left by 16 before using it.
-          int32_t Addend = RENext->Word0;
-          if (!isUpper) Addend <<= 16;
+          // NOTE: The half of the target virtual address is stashed in the
+          // address field of the secondary relocation, but we can't reverse
+          // engineer the constant offset from it without decoding the movw/movt
+          // instruction to find the other half in its immediate field.
 
           // ARM_RELOC_HALF_SECTDIFF encodes the second section in the
           // symbol/section pointer of the follow-on relocation.
-          StringRef SucName;
-          if (Type == 9) { // ARM_RELOC_HALF_SECTDIFF
-            if (error_code ec = getRelocationTargetName(RENext->Word1, SucName))
-              report_fatal_error(ec.message());
+          if (Type == macho::RIT_ARM_HalfDifference) {
+            fmt << "-";
+            printRelocationTargetName(RENext, fmt);
           }
 
-          if (SucName.size()) fmt << "-" << SucName;
-          if (Addend > 0) fmt << "+" << Addend;
-          else if (Addend < 0) fmt << Addend;
           fmt << ")";
           break;
         }
         default: {
-          StringRef Name;
-          if (error_code ec = getRelocationTargetName(RE->Word1, Name))
-            report_fatal_error(ec.message());
-          fmt << Name;
+          printRelocationTargetName(RE, fmt);
         }
       }
     }
-  } else {
-    StringRef Name;
-    if (error_code ec = getRelocationTargetName(RE->Word1, Name))
-      report_fatal_error(ec.message());
-    fmt << Name;
-  }
+  } else
+    printRelocationTargetName(RE, fmt);
 
   fmt.flush();
   Result.append(fmtbuf.begin(), fmtbuf.end());
@@ -966,19 +1018,25 @@
   InMemoryStruct<macho::RelocationEntry> RE;
   getRelocation(Rel, RE);
 
-  unsigned Type = (RE->Word1 >> 28) & 0xF;
   unsigned Arch = getArch();
+  bool isScattered = (Arch != Triple::x86_64) &&
+                     (RE->Word0 & macho::RF_Scattered);
+  unsigned Type;
+  if (isScattered)
+    Type = (RE->Word0 >> 24) & 0xF;
+  else
+    Type = (RE->Word1 >> 28) & 0xF;
 
   Result = false;
 
   // On arches that use the generic relocations, GENERIC_RELOC_PAIR
   // is always hidden.
   if (Arch == Triple::x86 || Arch == Triple::arm) {
-    if (Type == 1) Result = true;
+    if (Type == macho::RIT_Pair) Result = true;
   } else if (Arch == Triple::x86_64) {
     // On x86_64, X86_64_RELOC_UNSIGNED is hidden only when it follows
     // an X864_64_RELOC_SUBTRACTOR.
-    if (Type == 0 && Rel.d.a > 0) {
+    if (Type == macho::RIT_X86_64_Unsigned && Rel.d.a > 0) {
       DataRefImpl RelPrev = Rel;
       RelPrev.d.a--;
       InMemoryStruct<macho::RelocationEntry> REPrev;
@@ -986,7 +1044,7 @@
 
       unsigned PrevType = (REPrev->Word1 >> 28) & 0xF;
 
-      if (PrevType == 5) Result = true;
+      if (PrevType == macho::RIT_X86_64_Subtractor) Result = true;
     }
   }
 



From bruno.cardoso at gmail.com  Wed Oct 26 15:49:35 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 26 Oct 2011 18:49:35 -0200
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <1319231089.6498.6223.camel@sapling>
References: <1319231089.6498.6223.camel@sapling>
Message-ID: <CACk9Fxb1S79ZuEFhPAHFvjXnDOb5cSpYARVTL7pNYB3X9idaYw@mail.gmail.com>

Hi Hal,

On Fri, Oct 21, 2011 at 7:04 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> I've attached an initial version of a basic-block autovectorization
> pass. It works by searching a basic block for pairable (independent)
> instructions, and, using a chain-seeking heuristic, selects pairings
> likely to provide an overall speedup (if such pairings can be found).
> The selected pairs are then fused and, if necessary, other instructions
> are moved in order to maintain data-flow consistency. This works only
> within one basic block, but can do loop vectorization in combination
> with (partial) unrolling. The basic idea was inspired by the Vienna MAP
> Vectorizor, which has been used to vectorize FFT kernels, but the
> algorithm used here is different.
>
> To try it, use -bb-vectorize with opt. There are a few options:
> -bb-vectorize-req-chain-depth: default: 3 -- The depth of the chain of
> instruction pairs necessary in order to consider the pairs that compose
> the chain worthy of vectorization.
> -bb-vectorize-vector-bits: default: 128 -- The size of the target vector
> registers
> -bb-vectorize-no-ints -- Don't consider integer instructions
> -bb-vectorize-no-floats -- Don't consider floating-point instructions
>
> The vectorizor generates a lot of insert_element/extract_element pairs;
> The assumption is that other passes will turn these into shuffles when
> possible (it looks like some work is necessary here). It will also
> vectorize vector instructions, and generates shuffles in this case
> (again, other passes should combine these as appropriate).
>
> Currently, it does not fuse load or store instructions, but that is a
> feature that I'd like to add. Of course, alignment information is an
> issue for load/store vectorization (or maybe I should just fuse them
> anyway and let isel deal with unaligned cases?).
>
> Also, support needs to be added for fusing known intrinsics (fma, etc.),
> and, as has been discussed on llvmdev, we should add some intrinsics to
> allow the generation of addsub-type instructions.
>
> I've included a few tests, but it needs more. Please review (I'll commit
> if and when everyone is happy).
>
> Thanks in advance,
> Hal
>
> P.S. There is another option (not so useful right now, but could be):
> -bb-vectorize-fast-dep -- Don't do a full inter-instruction dependency
> analysis; instead stop looking for instruction pairs after the first use
> of an instruction's value. [This makes the pass faster, but would
> require a data-dependence-based reordering pass in order to be
> effective].

Cool! :)
Have you run this pass with any benchmark or the llvm testsuite? Does
it presents any regression?
Do you have any performance results?
Cheers,

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc

From evan.cheng at apple.com  Wed Oct 26 15:50:50 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 26 Oct 2011 13:50:50 -0700
Subject: [llvm-commits] [llvm] r142530 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-18-DisableMovtSize.ll
In-Reply-To: <4EA86CF4.8040704@gmail.com>
References: <20111019141108.15BB73128018@llvm.org>
	<8262B856-2A38-4A25-AA56-9AA8500833DC@apple.com>
	<CAJdarcEh2DiyjvnhK0bvU8ErVMBUoPx4yrKHEddBVb0_vakjHw@mail.gmail.com>
	<CA+Ov9+krA4yc8mvBGbWSYCgaNMOtMTMA7SYsthtRny2Rp0uoCQ@mail.gmail.com>
	<003401cc93b2$2f4c40d0$8de4c270$%molloy@arm.com>
	<5E97CD9C-A2E0-457A-9190-20C18B02E691@mac.com>
	<B0B56AD4-3A51-4283-907C-DACC97CA8231@apple.com>
	<4EA86CF4.8040704@gmail.com>
Message-ID: <883299C9-484D-49A4-A192-F2CE62EB60EE@apple.com>


On Oct 26, 2011, at 1:26 PM, Rafael ?vila de Esp?ndola wrote:

>> I think we just want another attribute, just like OptimizeForSize but
>> the Oz variant.  Maybe OptimizeForSizeHarder ;-)
> 
> Do you have an example or two of things that should go in 
> OptimizeForSize or OptimizeForSizeHarder?
> 
> I find the current description of -Os a bit hard to understand. If it 
> introduces no performance regression, why it is not in -O2?

> 
> A quick look a the code suggest that we could says that -Os is supposed 
> to limit passes that can introduce code bloat like inlining or tail 
> duplication. It should not be used for introducing tradeoffs in codegen. 
> In summary, "don't bloat the code to make it faster".
> 
> The decisions for using slower but smaller code would go to -Oz.
> 
> Does this sound like a correct description?

This is the correct description.

Evan

> 
>> -Chris
> 
> Cheers,
> Rafael
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From baldrick at free.fr  Wed Oct 26 15:55:21 2011
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 26 Oct 2011 20:55:21 -0000
Subject: [llvm-commits] [llvm] r143054 - in /llvm/trunk:
 include/llvm/Analysis/ValueTracking.h lib/Analysis/InstructionSimplify.cpp
 lib/Analysis/ValueTracking.cpp test/Transforms/InstSimplify/AndOrXor.ll
Message-ID: <20111026205521.4E88A312800A@llvm.org>

Author: baldrick
Date: Wed Oct 26 15:55:21 2011
New Revision: 143054

URL: http://llvm.org/viewvc/llvm-project?rev=143054&view=rev
Log:
The maximum power of 2 dividing a power of 2 is itself.  This occurs
in 403.gcc and was spotted by my super-optimizer.

Added:
    llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll
Modified:
    llvm/trunk/include/llvm/Analysis/ValueTracking.h
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp
    llvm/trunk/lib/Analysis/ValueTracking.cpp

Modified: llvm/trunk/include/llvm/Analysis/ValueTracking.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ValueTracking.h?rev=143054&r1=143053&r2=143054&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/ValueTracking.h (original)
+++ llvm/trunk/include/llvm/Analysis/ValueTracking.h Wed Oct 26 15:55:21 2011
@@ -48,8 +48,10 @@
   /// isPowerOfTwo - Return true if the given value is known to have exactly one
   /// bit set when defined. For vectors return true if every element is known to
   /// be a power of two when defined.  Supports values with integer or pointer
-  /// type and vectors of integers.
-  bool isPowerOfTwo(Value *V, const TargetData *TD = 0, unsigned Depth = 0);
+  /// type and vectors of integers.  If 'OrZero' is set then returns true if the
+  /// given value is either a power of two or zero.
+  bool isPowerOfTwo(Value *V, const TargetData *TD = 0, bool OrZero = false,
+                    unsigned Depth = 0);
 
   /// isKnownNonZero - Return true if the given value is known to be non-zero
   /// when defined.  For vectors return true if every element is known to be

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=143054&r1=143053&r2=143054&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Wed Oct 26 15:55:21 2011
@@ -1197,6 +1197,15 @@
       (A == Op0 || B == Op0))
     return Op0;
 
+  // A & (-A) = A if A is a power of two or zero.
+  if (match(Op0, m_Neg(m_Specific(Op1))) ||
+      match(Op1, m_Neg(m_Specific(Op0)))) {
+    if (isPowerOfTwo(Op0, TD, /*OrZero*/true))
+      return Op0;
+    if (isPowerOfTwo(Op1, TD, /*OrZero*/true))
+      return Op1;
+  }
+
   // Try some generic simplifications for associative operations.
   if (Value *V = SimplifyAssociativeBinOp(Instruction::And, Op0, Op1, TD, DT,
                                           MaxRecurse))

Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=143054&r1=143053&r2=143054&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Wed Oct 26 15:55:21 2011
@@ -745,10 +745,15 @@
 /// bit set when defined. For vectors return true if every element is known to
 /// be a power of two when defined.  Supports values with integer or pointer
 /// types and vectors of integers.
-bool llvm::isPowerOfTwo(Value *V, const TargetData *TD, unsigned Depth) {
-  if (ConstantInt *CI = dyn_cast<ConstantInt>(V))
-    return CI->getValue().isPowerOf2();
-  // TODO: Handle vector constants.
+bool llvm::isPowerOfTwo(Value *V, const TargetData *TD, bool OrZero,
+                        unsigned Depth) {
+  if (Constant *C = dyn_cast<Constant>(V)) {
+    if (C->isNullValue())
+      return OrZero;
+    if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
+      return CI->getValue().isPowerOf2();
+    // TODO: Handle vector constants.
+  }
 
   // 1 << X is clearly a power of two if the one is not shifted off the end.  If
   // it is shifted off the end then the result is undefined.
@@ -765,11 +770,23 @@
     return false;
 
   if (ZExtInst *ZI = dyn_cast<ZExtInst>(V))
-    return isPowerOfTwo(ZI->getOperand(0), TD, Depth);
+    return isPowerOfTwo(ZI->getOperand(0), TD, OrZero, Depth);
 
   if (SelectInst *SI = dyn_cast<SelectInst>(V))
-    return isPowerOfTwo(SI->getTrueValue(), TD, Depth) &&
-      isPowerOfTwo(SI->getFalseValue(), TD, Depth);
+    return isPowerOfTwo(SI->getTrueValue(), TD, OrZero, Depth) &&
+      isPowerOfTwo(SI->getFalseValue(), TD, OrZero, Depth);
+
+  Value *X = 0, *Y = 0;
+  if (OrZero && match(V, m_And(m_Value(X), m_Value(Y)))) {
+    // A power of two and'd with anything is a power of two or zero.
+    if (isPowerOfTwo(X, TD, /*OrZero*/true, Depth) ||
+        isPowerOfTwo(Y, TD, /*OrZero*/true, Depth))
+      return true;
+    // X & (-X) is always a power of two or zero.
+    if (match(X, m_Neg(m_Specific(Y))) || match(Y, m_Neg(m_Specific(X))))
+      return true;
+    return false;
+  }
 
   // An exact divide or right shift can only shift off zero bits, so the result
   // is a power of two only if the first operand is a power of two and not
@@ -778,7 +795,7 @@
       match(V, m_UDiv(m_Value(), m_Value()))) {
     PossiblyExactOperator *PEO = cast<PossiblyExactOperator>(V);
     if (PEO->isExact())
-      return isPowerOfTwo(PEO->getOperand(0), TD, Depth);
+      return isPowerOfTwo(PEO->getOperand(0), TD, OrZero, Depth);
   }
 
   return false;
@@ -879,9 +896,9 @@
     }
 
     // The sum of a non-negative number and a power of two is not zero.
-    if (XKnownNonNegative && isPowerOfTwo(Y, TD, Depth))
+    if (XKnownNonNegative && isPowerOfTwo(Y, TD, /*OrZero*/false, Depth))
       return true;
-    if (YKnownNonNegative && isPowerOfTwo(X, TD, Depth))
+    if (YKnownNonNegative && isPowerOfTwo(X, TD, /*OrZero*/false, Depth))
       return true;
   }
   // X * Y.

Added: llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll?rev=143054&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll (added)
+++ llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll Wed Oct 26 15:55:21 2011
@@ -0,0 +1,12 @@
+; RUN: opt < %s -instsimplify -S | FileCheck %s
+
+define i64 @pow2(i32 %x) {
+; CHECK: @pow2
+  %negx = sub i32 0, %x
+  %x2 = and i32 %x, %negx
+  %e = zext i32 %x2 to i64
+  %nege = sub i64 0, %e
+  %e2 = and i64 %e, %nege
+  ret i64 %e2
+; CHECK: ret i64 %e
+}



From lhames at gmail.com  Wed Oct 26 15:56:52 2011
From: lhames at gmail.com (Lang Hames)
Date: Wed, 26 Oct 2011 20:56:52 -0000
Subject: [llvm-commits] [llvm] r143055 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/ARM/2011-10-26-memset-inline.ll
Message-ID: <20111026205653.0A95C312800A@llvm.org>

Author: lhames
Date: Wed Oct 26 15:56:52 2011
New Revision: 143055

URL: http://llvm.org/viewvc/llvm-project?rev=143055&view=rev
Log:
Make sure short memsets on ARM lower to stores, even when optimizing for size.

Added:
    llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-inline.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=143055&r1=143054&r2=143055&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Oct 26 15:56:52 2011
@@ -752,6 +752,8 @@
 
   //// temporary - rewrite interface to use type
   maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
+  maxStoresPerMemset = 16;
+  maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
 
   // On ARM arguments smaller than 4 bytes are extended, so all arguments
   // are at least 4 bytes aligned.

Added: llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-inline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-inline.ll?rev=143055&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-inline.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-inline.ll Wed Oct 26 15:56:52 2011
@@ -0,0 +1,18 @@
+; Make sure short memsets on ARM lower to stores, even when optimizing for size.
+; RUN: llc -march=arm < %s | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
+target triple = "thumbv7-apple-ios5.0.0"
+
+; CHECK:      strb
+; CHECK-NEXT: strb
+; CHECK-NEXT: strb
+; CHECK-NEXT: strb
+; CHECK-NEXT: strb 
+define void @foo(i8* nocapture %c) nounwind optsize {
+entry:
+  call void @llvm.memset.p0i8.i64(i8* %c, i8 -1, i64 5, i32 1, i1 false)
+  ret void
+}
+
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind



From rafael.espindola at gmail.com  Wed Oct 26 16:12:27 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 26 Oct 2011 21:12:27 -0000
Subject: [llvm-commits] [llvm] r143062 - in /llvm/trunk:
 lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86InstrCompiler.td
 lib/Target/X86/X86MCInstLower.cpp test/CodeGen/X86/segmented-stacks.ll
Message-ID: <20111026211228.0DBF0312800A@llvm.org>

Author: rafael
Date: Wed Oct 26 16:12:27 2011
New Revision: 143062

URL: http://llvm.org/viewvc/llvm-project?rev=143062&view=rev
Log:
This commit introduces two fake instructions MORESTACK_RET and
MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET
followed by a MOV respectively.  Having a fake instruction prevents
the verifier from seeing a MachineBasicBlock end with a
non-terminator (MOV).  It also prevents the rather eccentric case of a
MachineBasicBlock ending with RET but having successors nevertheless.

Patch by Sanjoy Das.

Modified:
    llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td
    llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
    llvm/trunk/test/CodeGen/X86/segmented-stacks.ll

Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=143062&r1=143061&r2=143062&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Wed Oct 26 16:12:27 2011
@@ -1336,26 +1336,16 @@
 
   // The MOV R10, RAX needs to be in a different block, since the RET we emit in
   // allocMBB needs to be last (terminating) instruction.
-  MachineBasicBlock *restoreR10MBB = NULL;
-  if (IsNested)
-    restoreR10MBB = MF.CreateMachineBasicBlock();
 
   for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
          e = prologueMBB.livein_end(); i != e; i++) {
     allocMBB->addLiveIn(*i);
     checkMBB->addLiveIn(*i);
-
-    if (IsNested)
-      restoreR10MBB->addLiveIn(*i);
   }
 
-  if (IsNested) {
+  if (IsNested)
     allocMBB->addLiveIn(X86::R10);
-    restoreR10MBB->addLiveIn(X86::RAX);
-  }
 
-  if (IsNested)
-    MF.push_front(restoreR10MBB);
   MF.push_front(allocMBB);
   MF.push_front(checkMBB);
 
@@ -1425,18 +1415,12 @@
   if (!Is64Bit)
     BuildMI(allocMBB, DL, TII.get(X86::ADD32ri), X86::ESP).addReg(X86::ESP)
       .addImm(8);
-  BuildMI(allocMBB, DL, TII.get(X86::RET));
-
   if (IsNested)
-    BuildMI(restoreR10MBB, DL, TII.get(X86::MOV64rr), X86::R10)
-      .addReg(X86::RAX);
+    BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
+  else
+    BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
 
-  if (IsNested) {
-    allocMBB->addSuccessor(restoreR10MBB);
-    restoreR10MBB->addSuccessor(&prologueMBB);
-  } else {
-    allocMBB->addSuccessor(&prologueMBB);
-  }
+  allocMBB->addSuccessor(&prologueMBB);
 
   checkMBB->addSuccessor(allocMBB);
   checkMBB->addSuccessor(&prologueMBB);

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=143062&r1=143061&r2=143062&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Wed Oct 26 16:12:27 2011
@@ -150,6 +150,24 @@
 }
 
 //===----------------------------------------------------------------------===//
+// Pseudo instructions used by segmented stacks.
+//
+
+// This is lowered into a RET instruction by MCInstLower.  We need
+// this so that we don't have to have a MachineBasicBlock which ends
+// with a RET and also has successors.
+let isPseudo = 1 in {
+def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
+                          "", []>;
+
+// This instruction is lowered to a RET followed by a MOV.  The two
+// instructions are not generated on a higher level since then the
+// verifier sees a MachineBasicBlock ending with a non-terminator.
+def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
+                                  "", []>;
+}
+
+//===----------------------------------------------------------------------===//
 // Alias Instructions
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=143062&r1=143061&r2=143062&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Wed Oct 26 16:12:27 2011
@@ -527,6 +527,22 @@
   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
+
+  case X86::MORESTACK_RET:
+    OutMI.setOpcode(X86::RET);
+    break;
+
+  case X86::MORESTACK_RET_RESTORE_R10: {
+    MCInst retInst;
+
+    OutMI.setOpcode(X86::MOV64rr);
+    OutMI.addOperand(MCOperand::CreateReg(X86::R10));
+    OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
+
+    retInst.setOpcode(X86::RET);
+    AsmPrinter.OutStreamer.EmitInstruction(retInst);
+    break;
+  }
   }
 }
 

Modified: llvm/trunk/test/CodeGen/X86/segmented-stacks.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/segmented-stacks.ll?rev=143062&r1=143061&r2=143062&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/segmented-stacks.ll (original)
+++ llvm/trunk/test/CodeGen/X86/segmented-stacks.ll Wed Oct 26 16:12:27 2011
@@ -82,6 +82,6 @@
 ; X64-NEXT: movabsq $0, %r11
 ; X64-NEXT: callq __morestack
 ; X64-NEXT: ret
-; X64:      movq %rax, %r10
+; X64-NEXT: movq %rax, %r10
 
 }



From grosbach at apple.com  Wed Oct 26 16:14:09 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 26 Oct 2011 21:14:09 -0000
Subject: [llvm-commits] [llvm] r143063 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20111026211409.2FA4E312800A@llvm.org>

Author: grosbach
Date: Wed Oct 26 16:14:08 2011
New Revision: 143063

URL: http://llvm.org/viewvc/llvm-project?rev=143063&view=rev
Log:
ARM parse parenthesized expressions for label references.

Partial fix for rdar://10348687.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=143063&r1=143062&r2=143063&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Oct 26 16:14:08 2011
@@ -3691,6 +3691,7 @@
     // Fall though for the Identifier case that is not a register or a
     // special name.
   }
+  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
   case AsmToken::Integer: // things like 1f and 2b as a branch targets
   case AsmToken::Dot: {   // . as a branch target
     // This was not a register so parse other operands that start with an



From rafael.espindola at gmail.com  Wed Oct 26 16:16:41 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 26 Oct 2011 21:16:41 -0000
Subject: [llvm-commits] [llvm] r143064 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrCompiler.td
 test/CodeGen/X86/segmented-stacks.ll
Message-ID: <20111026211641.D4C91312800A@llvm.org>

Author: rafael
Date: Wed Oct 26 16:16:41 2011
New Revision: 143064

URL: http://llvm.org/viewvc/llvm-project?rev=143064&view=rev
Log:
Fixes an issue reported by -verify-machineinstrs.

Patch by Sanjoy Das.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td
    llvm/trunk/test/CodeGen/X86/segmented-stacks.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=143064&r1=143063&r2=143064&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Oct 26 16:16:41 2011
@@ -11784,6 +11784,7 @@
   unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
     bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
     tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
+    SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
     sizeVReg = MI->getOperand(1).getReg(),
     physSPReg = Is64Bit ? X86::RSP : X86::ESP;
 
@@ -11801,19 +11802,19 @@
   // Add code to the main basic block to check if the stack limit has been hit,
   // and if so, jump to mallocMBB otherwise to bumpMBB.
   BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
-  BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg)
+  BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
     .addReg(tmpSPVReg).addReg(sizeVReg);
   BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
     .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
-    .addReg(tmpSPVReg);
+    .addReg(SPLimitVReg);
   BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
 
   // bumpMBB simply decreases the stack pointer, since we know the current
   // stacklet has enough space.
   BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
-    .addReg(tmpSPVReg);
+    .addReg(SPLimitVReg);
   BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
-    .addReg(tmpSPVReg);
+    .addReg(SPLimitVReg);
   BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
 
   // Calls into a routine in libgcc to allocate more space from the heap.

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=143064&r1=143063&r2=143064&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Wed Oct 26 16:16:41 2011
@@ -112,14 +112,14 @@
 // allocated by bumping the stack pointer. Otherwise memory is allocated from 
 // the heap.
 
-let Defs = [EAX, ESP, EFLAGS], Uses = [ESP, EAX] in
+let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
                       "# variable sized alloca for segmented stacks",
                       [(set GR32:$dst,
                          (X86SegAlloca GR32:$size))]>,
                     Requires<[In32BitMode]>;
 
-let Defs = [RAX, RSP, EFLAGS], Uses = [RSP, RAX] in
+let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
                       "# variable sized alloca for segmented stacks",
                       [(set GR64:$dst,

Modified: llvm/trunk/test/CodeGen/X86/segmented-stacks.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/segmented-stacks.ll?rev=143064&r1=143063&r2=143064&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/segmented-stacks.ll (original)
+++ llvm/trunk/test/CodeGen/X86/segmented-stacks.ll Wed Oct 26 16:16:41 2011
@@ -30,6 +30,10 @@
 ; X32-NEXT: addl $8, %esp
 ; X32-NEXT: ret 
 
+; X32:      movl %esp, %eax
+; X32-NEXT: subl %ecx, %eax
+; X32-NEXT: cmpl %eax, %gs:48
+
 ; X32:      movl %eax, %esp
 
 ; X32:      subl $12, %esp
@@ -47,14 +51,15 @@
 ; X64-NEXT: callq __morestack
 ; X64-NEXT: ret
 
-; X64:      movq %rsp, %rax
-; X64-NEXT: subq %rcx, %rax
-; X64-NEXT: cmpq %rax, %fs:112
+; X64:      movq %rsp, %rdi
+; X64-NEXT: subq %rax, %rdi
+; X64-NEXT: cmpq %rdi, %fs:112
 
-; X64:      movq %rax, %rsp
+; X64:      movq %rdi, %rsp
 
-; X64:      movq %rcx, %rdi
+; X64:      movq %rax, %rdi
 ; X64-NEXT: callq __morestack_allocate_stack_space
+; X64-NEXT: movq %rax, %rdi
 
 }
 



From rafael.espindola at gmail.com  Wed Oct 26 16:20:26 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 26 Oct 2011 21:20:26 -0000
Subject: [llvm-commits] [llvm] r143066 -
	/llvm/trunk/test/CodeGen/X86/segmented-stacks.ll
Message-ID: <20111026212026.C43E1312800A@llvm.org>

Author: rafael
Date: Wed Oct 26 16:20:26 2011
New Revision: 143066

URL: http://llvm.org/viewvc/llvm-project?rev=143066&view=rev
Log:
Run test with -verify-machineinstrs.

Patch by Sanjoy Das.

Modified:
    llvm/trunk/test/CodeGen/X86/segmented-stacks.ll

Modified: llvm/trunk/test/CodeGen/X86/segmented-stacks.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/segmented-stacks.ll?rev=143066&r1=143065&r2=143066&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/segmented-stacks.ll (original)
+++ llvm/trunk/test/CodeGen/X86/segmented-stacks.ll Wed Oct 26 16:20:26 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=i686-linux -segmented-stacks | FileCheck %s -check-prefix=X32
-; RUN: llc < %s -mtriple=x86_64-linux  -segmented-stacks | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=i686-linux -segmented-stacks -verify-machineinstrs | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-linux  -segmented-stacks -verify-machineinstrs | FileCheck %s -check-prefix=X64
 
 ; Just to prevent the alloca from being optimized away
 declare void @dummy_use(i32*, i32)



From grosbach at apple.com  Wed Oct 26 17:22:01 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 26 Oct 2011 22:22:01 -0000
Subject: [llvm-commits] [llvm] r143068 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20111026222201.8C6CA312800A@llvm.org>

Author: grosbach
Date: Wed Oct 26 17:22:01 2011
New Revision: 143068

URL: http://llvm.org/viewvc/llvm-project?rev=143068&view=rev
Log:
Thumb2 ldr pc-relative encoding fixes.

We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=143068&r1=143067&r2=143068&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Oct 26 17:22:01 2011
@@ -1460,7 +1460,7 @@
                  "$addr.base = $wb", []>;
 
 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
-// data/instruction access.  These are for disassembly only.
+// data/instruction access.
 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
 // (prefetch 1) -> (preload 2),  (prefetch 2) -> (preload 1).
 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
@@ -1518,6 +1518,10 @@
 
     let DecoderMethod = "DecodeT2LoadShift";
   }
+  // FIXME: We should have a separate 'pci' variant here. As-is we represent
+  // it via the i12 variant, which it's related to, but that means we can
+  // represent negative immediates, which aren't legal for anything except
+  // the 'pci' case (Rn == 15).
 }
 
 defm t2PLD  : T2Ipl<0, 0, "pld">,  Requires<[IsThumb2]>;
@@ -3906,6 +3910,17 @@
 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
                   (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
 
+def : t2InstAlias<"ldr${p} $Rt, $addr",
+                  (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
+def : t2InstAlias<"ldrb${p} $Rt, $addr",
+                  (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
+def : t2InstAlias<"ldrh${p} $Rt, $addr",
+                  (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
+def : t2InstAlias<"ldrsb${p} $Rt, $addr",
+                  (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
+def : t2InstAlias<"ldrsh${p} $Rt, $addr",
+                  (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
+
 // Alias for MVN without the ".w" optional width specifier.
 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
            (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=143068&r1=143067&r2=143068&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Oct 26 17:22:01 2011
@@ -865,12 +865,6 @@
     return Val > -256 && Val < 0;
   }
   bool isMemUImm12Offset() const {
-    // If we have an immediate that's not a constant, treat it as a label
-    // reference needing a fixup. If it is a constant, it's something else
-    // and we reject it.
-    if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
-      return true;
-
     if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
       return false;
     // Immediate offset in range [0, 4095].

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=143068&r1=143067&r2=143068&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Oct 26 17:22:01 2011
@@ -638,9 +638,12 @@
 @ LDR(literal)
 @------------------------------------------------------------------------------
         ldr.w r5, _foo
+        ldr   lr, (_strcmp-4)
 
 @ CHECK: ldr.w	r5, _foo                @ encoding: [0x5f'A',0xf8'A',A,0x50'A']
-            @   fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
+@ CHECK: @   fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
+@ CHECK: ldr.w	lr, _strcmp-4           @ encoding: [0x5f'A',0xf8'A',A,0xe0'A']
+@ CHECK: @   fixup A - offset: 0, value: _strcmp-4, kind: fixup_t2_ldst_pcrel_12
 
 
 @------------------------------------------------------------------------------
@@ -813,7 +816,7 @@
 @------------------------------------------------------------------------------
         ldrh r5, _bar
 
-@ CHECK: ldrh.w	r5, _bar                @ encoding: [0xbf'A',0xf8'A',A,0x50'A']
+@ CHECK: ldrh.w	r5, _bar                @ encoding: [0x3f'A',0xf8'A',A,0x50'A']
 @ CHECK:     @   fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
 
 
@@ -882,7 +885,7 @@
 @------------------------------------------------------------------------------
         ldrsb r5, _bar
 
-@ CHECK: ldrsb.w r5, _bar               @ encoding: [0x9f'A',0xf9'A',A,0x50'A']
+@ CHECK: ldrsb.w r5, _bar               @ encoding: [0x1f'A',0xf9'A',A,0x50'A']
 @ CHECK:      @   fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
 
 
@@ -951,7 +954,7 @@
 @------------------------------------------------------------------------------
         ldrsh r5, _bar
 
-@ CHECK: ldrsh.w r5, _bar               @ encoding: [0xbf'A',0xf9'A',A,0x50'A']
+@ CHECK: ldrsh.w r5, _bar               @ encoding: [0x3f'A',0xf9'A',A,0x50'A']
 @ CHECK:      @   fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
 
 @ TEMPORARILY DISABLED:
@@ -1354,9 +1357,9 @@
 @------------------------------------------------------------------------------
 @ PLD(literal)
 @------------------------------------------------------------------------------
-        pld  _foo
+@        pld  _foo
 
-@ CHECK: pld	_foo                    @ encoding: [0x9f'A',0xf8'A',A,0xf0'A']
+@ FIXME: pld	_foo                    @ encoding: [0x9f'A',0xf8'A',A,0xf0'A']
             @   fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
 
 
@@ -1396,10 +1399,10 @@
 @------------------------------------------------------------------------------
 @ PLI(literal)
 @------------------------------------------------------------------------------
-        pli  _foo
+@        pli  _foo
 
 
-@ CHECK: pli	_foo                    @ encoding: [0x9f'A',0xf9'A',A,0xf0'A']
+@ FIXME: pli	_foo                    @ encoding: [0x9f'A',0xf9'A',A,0xf0'A']
            @   fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
 
 



From grosbach at apple.com  Wed Oct 26 17:44:41 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 26 Oct 2011 22:44:41 -0000
Subject: [llvm-commits] [llvm] r143071 - /llvm/trunk/lib/MC/MCAssembler.cpp
Message-ID: <20111026224441.7DF18312800A@llvm.org>

Author: grosbach
Date: Wed Oct 26 17:44:41 2011
New Revision: 143071

URL: http://llvm.org/viewvc/llvm-project?rev=143071&view=rev
Log:
Trailing whitespace.

Modified:
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=143071&r1=143070&r2=143071&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Oct 26 17:44:41 2011
@@ -118,7 +118,7 @@
     if (Target.getSymB() && Target.getSymB()->getSymbol().isUndefined())
       report_fatal_error("unable to evaluate offset to undefined symbol '" +
                          Target.getSymB()->getSymbol().getName() + "'");
-      
+
     uint64_t Offset = Target.getConstant();
     if (Target.getSymA())
       Offset += getSymbolOffset(&Assembler.getSymbolData(
@@ -295,7 +295,7 @@
 
   if (IsPCRel) {
     uint32_t Offset = Layout.getFragmentOffset(DF) + Fixup.getOffset();
-    
+
     // A number of ARM fixups in Thumb mode require that the effective PC
     // address be determined as the 32-bit aligned version of the actual offset.
     if (ShouldAlignPC) Offset &= ~0x3;



From mcrosier at apple.com  Wed Oct 26 17:47:55 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 26 Oct 2011 22:47:55 -0000
Subject: [llvm-commits] [llvm] r143072 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20111026224755.A9DE6312800A@llvm.org>

Author: mcrosier
Date: Wed Oct 26 17:47:55 2011
New Revision: 143072

URL: http://llvm.org/viewvc/llvm-project?rev=143072&view=rev
Log:
Factor out an EmitCmp function that can be used by both SelectCmp and
SelectBranch.  No functional change intended.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=143072&r1=143071&r2=143072&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Oct 26 17:47:55 2011
@@ -173,6 +173,7 @@
   private:
     bool isTypeLegal(Type *Ty, MVT &VT);
     bool isLoadTypeLegal(Type *Ty, MVT &VT);
+    bool ARMEmitCmp(Type *Ty, const Value *Src1Value, const Value *Src2Value);
     bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
     bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
     bool ARMComputeAddress(const Value *Obj, Address &Addr);
@@ -1214,54 +1215,58 @@
   return true;
 }
 
-bool ARMFastISel::SelectCmp(const Instruction *I) {
-  const CmpInst *CI = cast<CmpInst>(I);
-
+bool ARMFastISel::ARMEmitCmp(Type *Ty, const Value *Src1Value,
+                             const Value *Src2Value) {
   MVT VT;
-  Type *Ty = CI->getOperand(0)->getType();
   if (!isTypeLegal(Ty, VT))
     return false;
 
-  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
-  if (isFloat && !Subtarget->hasVFP2())
+  if ((Ty->isFloatTy() || Ty->isDoubleTy()) && !Subtarget->hasVFP2())
     return false;
 
   unsigned CmpOpc;
-  unsigned CondReg;
   switch (VT.SimpleTy) {
     default: return false;
     // TODO: Verify compares.
     case MVT::f32:
       CmpOpc = ARM::VCMPES;
-      CondReg = ARM::FPSCR;
       break;
     case MVT::f64:
       CmpOpc = ARM::VCMPED;
-      CondReg = ARM::FPSCR;
       break;
     case MVT::i32:
       CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
-      CondReg = ARM::CPSR;
       break;
   }
 
+  unsigned Src1 = getRegForValue(Src1Value);
+  if (Src1 == 0) return false;
+
+  unsigned Src2 = getRegForValue(Src2Value);
+  if (Src2 == 0) return false;
+
+  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
+                  .addReg(Src1).addReg(Src2));
+  return true;
+}
+
+bool ARMFastISel::SelectCmp(const Instruction *I) {
+  const CmpInst *CI = cast<CmpInst>(I);
+
   // Get the compare predicate.
   ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
 
   // We may not handle every CC for now.
   if (ARMPred == ARMCC::AL) return false;
 
-  unsigned Arg1 = getRegForValue(CI->getOperand(0));
-  if (Arg1 == 0) return false;
-
-  unsigned Arg2 = getRegForValue(CI->getOperand(1));
-  if (Arg2 == 0) return false;
-
-  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
-                  .addReg(Arg1).addReg(Arg2));
+  // Emit the compare.
+  Type *Ty = CI->getOperand(0)->getType();
+  if (!ARMEmitCmp(Ty, CI->getOperand(0), CI->getOperand(1)))
+    return false;
 
   // For floating point we need to move the result to a comparison register
   // that we can then use for branches.
+  bool isFloat = Ty->isFloatTy() || Ty->isDoubleTy();
   if (isFloat)
     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                             TII.get(ARM::FMSTAT)));
@@ -1275,6 +1280,7 @@
   Constant *Zero
     = ConstantInt::get(Type::getInt32Ty(*Context), 0);
   unsigned ZeroReg = TargetMaterializeConstant(Zero);
+  unsigned CondReg = isFloat ? ARM::FPSCR : ARM::CPSR;
   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
           .addReg(ZeroReg).addImm(1)
           .addImm(ARMPred).addReg(CondReg);



From isanbard at gmail.com  Wed Oct 26 17:55:18 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 26 Oct 2011 22:55:18 -0000
Subject: [llvm-commits] [llvm] r143073 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111026225518.C696D312800A@llvm.org>

Author: void
Date: Wed Oct 26 17:55:18 2011
New Revision: 143073

URL: http://llvm.org/viewvc/llvm-project?rev=143073&view=rev
Log:
Add include-what-you-use to the External Projects list.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143073&r1=143072&r2=143073&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Wed Oct 26 17:55:18 2011
@@ -377,6 +377,18 @@
 </div>
 
 <!--=========================================================================-->
+<h3>include-what-you-use</h3>
+
+<div>
+
+<p><a href="http://code.google.com/p/include-what-you-use">include-what-you-use</a>
+   is a tool to ensure that a file directly <code>#include</code>s
+   all <code>.h</code> files that provide a symbol that the file uses. It also
+   removes superfluous <code>#include</code>s from source files.</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>LanguageKit and Pragmatic Smalltalk</h3>
 
 <div>



From nicholas at mxc.ca  Wed Oct 26 17:55:33 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 26 Oct 2011 22:55:33 -0000
Subject: [llvm-commits] [llvm] r143074 - in /llvm/trunk:
 include/llvm/MC/MCAsmInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
 lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20111026225533.B64B3312800A@llvm.org>

Author: nicholas
Date: Wed Oct 26 17:55:33 2011
New Revision: 143074

URL: http://llvm.org/viewvc/llvm-project?rev=143074&view=rev
Log:
Reflow lines, fix comments for doxygen style, fix whitespace. No functionality
change.

Modified:
    llvm/trunk/include/llvm/MC/MCAsmInfo.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=143074&r1=143073&r2=143074&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Wed Oct 26 17:55:33 2011
@@ -323,11 +323,11 @@
     const char* DwarfSectionOffsetDirective; // Defaults to NULL
 
     /// DwarfRequiresRelocationForSectionOffset - True if we need to produce a
-    // relocation when we want a section offset in dwarf.
+    /// relocation when we want a section offset in dwarf.
     bool DwarfRequiresRelocationForSectionOffset;  // Defaults to true;
 
-    // DwarfUsesLabelOffsetDifference - True if Dwarf2 output can
-    // use EmitLabelOffsetDifference.
+    /// DwarfUsesLabelOffsetDifference - True if Dwarf2 output can
+    /// use EmitLabelOffsetDifference.
     bool DwarfUsesLabelOffsetForRanges;
 
     /// DwarfRegNumForCFI - True if dwarf register numbers are printed

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=143074&r1=143073&r2=143074&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Wed Oct 26 17:55:33 2011
@@ -98,7 +98,6 @@
   Die->addValue(Attribute, Form, createDIEEntry(Entry));
 }
 
-
 /// addBlock - Add block data.
 ///
 void CompileUnit::addBlock(DIE *Die, unsigned Attribute, unsigned Form,
@@ -135,8 +134,7 @@
   unsigned Line = G.getLineNumber();
   if (Line == 0)
     return;
-  unsigned FileID = DD->GetOrCreateSourceID(G.getFilename(),
-                                            G.getDirectory());
+  unsigned FileID = DD->GetOrCreateSourceID(G.getFilename(), G.getDirectory());
   assert(FileID && "Invalid file id");
   addUInt(Die, dwarf::DW_AT_decl_file, 0, FileID);
   addUInt(Die, dwarf::DW_AT_decl_line, 0, Line);
@@ -155,7 +153,8 @@
   unsigned Line = SP.getLineNumber();
   if (!SP.getContext().Verify())
     return;
-  unsigned FileID = DD->GetOrCreateSourceID(SP.getFilename(), SP.getDirectory());
+  unsigned FileID = DD->GetOrCreateSourceID(SP.getFilename(),
+                                            SP.getDirectory());
   assert(FileID && "Invalid file id");
   addUInt(Die, dwarf::DW_AT_decl_file, 0, FileID);
   addUInt(Die, dwarf::DW_AT_decl_line, 0, Line);
@@ -171,7 +170,8 @@
   unsigned Line = Ty.getLineNumber();
   if (Line == 0 || !Ty.getContext().Verify())
     return;
-  unsigned FileID = DD->GetOrCreateSourceID(Ty.getFilename(), Ty.getDirectory());
+  unsigned FileID = DD->GetOrCreateSourceID(Ty.getFilename(),
+                                            Ty.getDirectory());
   assert(FileID && "Invalid file id");
   addUInt(Die, dwarf::DW_AT_decl_file, 0, FileID);
   addUInt(Die, dwarf::DW_AT_decl_line, 0, Line);
@@ -458,7 +458,7 @@
 /// addConstantValue - Add constant value entry in variable DIE.
 bool CompileUnit::addConstantValue(DIE *Die, const MachineOperand &MO,
                                    DIType Ty) {
-  assert (MO.isImm() && "Invalid machine operand!");
+  assert(MO.isImm() && "Invalid machine operand!");
   DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
   int SizeInBits = -1;
   bool SignedConstant = isTypeSigned(Ty, &SizeInBits);
@@ -479,7 +479,7 @@
 
 /// addConstantFPValue - Add constant value entry in variable DIE.
 bool CompileUnit::addConstantFPValue(DIE *Die, const MachineOperand &MO) {
-  assert (MO.isFPImm() && "Invalid machine operand!");
+  assert(MO.isFPImm() && "Invalid machine operand!");
   DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
   APFloat FPImm = MO.getFPImm()->getValueAPF();
 
@@ -556,8 +556,8 @@
       Buffer.addChild(getOrCreateTemplateValueParameterDIE(
                         DITemplateValueParameter(Element)));
   }
-
 }
+
 /// addToContextOwner - Add Die into the list of its context owner's children.
 void CompileUnit::addToContextOwner(DIE *Die, DIDescriptor Context) {
   if (Context.isType()) {
@@ -669,7 +669,7 @@
   }
 
   Buffer.setTag(dwarf::DW_TAG_base_type);
-  addUInt(&Buffer, dwarf::DW_AT_encoding,  dwarf::DW_FORM_data1,
+  addUInt(&Buffer, dwarf::DW_AT_encoding, dwarf::DW_FORM_data1,
 	  BTy.getEncoding());
 
   uint64_t Size = BTy.getSizeInBits() >> 3;
@@ -840,7 +840,7 @@
 
   if (Tag == dwarf::DW_TAG_enumeration_type || Tag == dwarf::DW_TAG_class_type
       || Tag == dwarf::DW_TAG_structure_type || Tag == dwarf::DW_TAG_union_type)
-    {
+  {
     // Add size if non-zero (derived types might be zero-sized.)
     if (Size)
       addUInt(&Buffer, dwarf::DW_AT_byte_size, 0, Size);
@@ -932,9 +932,8 @@
 
   StringRef LinkageName = SP.getLinkageName();
   if (!LinkageName.empty())
-    addString(SPDie, dwarf::DW_AT_MIPS_linkage_name, 
-                    dwarf::DW_FORM_string,
-                    getRealLinkageName(LinkageName));
+    addString(SPDie, dwarf::DW_AT_MIPS_linkage_name, dwarf::DW_FORM_string,
+              getRealLinkageName(LinkageName));
 
   // If this DIE is going to refer declaration info using AT_specification
   // then there is no need to add other attributes.
@@ -943,8 +942,7 @@
 
   // Constructors and operators for anonymous aggregates do not have names.
   if (!SP.getName().empty())
-    addString(SPDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, 
-                    SP.getName());
+    addString(SPDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, SP.getName());
 
   addSourceLine(SPDie, SP);
 
@@ -1051,13 +1049,12 @@
 
   // Add name.
   addString(VariableDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string,
-                   GV.getDisplayName());
+            GV.getDisplayName());
   StringRef LinkageName = GV.getLinkageName();
   bool isGlobalVariable = GV.getGlobal() != NULL;
   if (!LinkageName.empty() && isGlobalVariable)
-    addString(VariableDIE, dwarf::DW_AT_MIPS_linkage_name, 
-                     dwarf::DW_FORM_string,
-                     getRealLinkageName(LinkageName));
+    addString(VariableDIE, dwarf::DW_AT_MIPS_linkage_name,
+              dwarf::DW_FORM_string, getRealLinkageName(LinkageName));
   // Add type.
   DIType GTy = GV.getType();
   addType(VariableDIE, GTy);

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=143074&r1=143073&r2=143074&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Oct 26 17:55:33 2011
@@ -203,7 +203,7 @@
     if (SP.isDefinition() && !SP.getContext().isCompileUnit() &&
         !SP.getContext().isFile() &&
         !isSubprogramContext(SP.getContext())) {
-      SPCU-> addUInt(SPDie, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag, 1);
+      SPCU->addUInt(SPDie, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag, 1);
       
       // Add arguments.
       DICompositeType SPTy = SP.getType();
@@ -248,7 +248,6 @@
 /// for this scope and attach DW_AT_low_pc/DW_AT_high_pc labels.
 DIE *DwarfDebug::constructLexicalScopeDIE(CompileUnit *TheCU, 
                                           LexicalScope *Scope) {
-
   DIE *ScopeDIE = new DIE(dwarf::DW_TAG_lexical_block);
   if (Scope->isAbstractScope())
     return ScopeDIE;
@@ -294,10 +293,9 @@
 /// of the function.
 DIE *DwarfDebug::constructInlinedScopeDIE(CompileUnit *TheCU,
                                           LexicalScope *Scope) {
-
   const SmallVector<InsnRange, 4> &Ranges = Scope->getRanges();
-  assert (Ranges.empty() == false
-          && "LexicalScope does not have instruction markers!");
+  assert(Ranges.empty() == false &&
+         "LexicalScope does not have instruction markers!");
 
   if (!Scope->getScopeNode())
     return NULL;
@@ -314,7 +312,7 @@
   const MCSymbol *EndLabel = getLabelAfterInsn(RI->second);
 
   if (StartLabel == 0 || EndLabel == 0) {
-    assert (0 && "Unexpected Start and End labels for a inlined scope!");
+    assert(0 && "Unexpected Start and End labels for a inlined scope!");
     return 0;
   }
   assert(StartLabel->isDefined() &&
@@ -358,8 +356,7 @@
     I = InlineInfo.find(InlinedSP);
 
   if (I == InlineInfo.end()) {
-    InlineInfo[InlinedSP].push_back(std::make_pair(StartLabel,
-                                                             ScopeDIE));
+    InlineInfo[InlinedSP].push_back(std::make_pair(StartLabel, ScopeDIE));
     InlinedSPNodes.push_back(InlinedSP);
   } else
     I->second.push_back(std::make_pair(StartLabel, ScopeDIE));
@@ -376,7 +373,7 @@
   if (!Scope || !Scope->getScopeNode())
     return NULL;
 
-  SmallVector <DIE *, 8> Children;
+  SmallVector<DIE *, 8> Children;
 
   // Collect arguments for current function.
   if (LScopes.isCurrentFunctionScope(Scope))
@@ -435,7 +432,6 @@
 /// source file names. If none currently exists, create a new id and insert it
 /// in the SourceIds map. This can update DirectoryNames and SourceFileNames
 /// maps as well.
-
 unsigned DwarfDebug::GetOrCreateSourceID(StringRef FileName, 
                                          StringRef DirName) {
   // If FE did not provide a file name, then assume stdin.
@@ -673,7 +669,7 @@
         
         // Construct subprogram DIE and add variables DIEs.
         CompileUnit *SPCU = CUMap.lookup(TheCU);
-        assert (SPCU && "Unable to find Compile Unit!");
+        assert(SPCU && "Unable to find Compile Unit!");
         constructSubprogramDIE(SPCU, SP);
         DIE *ScopeDIE = SPCU->getDIE(SP);
         for (unsigned vi = 0, ve = Variables.getNumElements(); vi != ve; ++vi) {
@@ -834,7 +830,7 @@
 /// isDbgValueInDefinedReg - Return true if debug value, encoded by
 /// DBG_VALUE instruction, is in a defined reg.
 static bool isDbgValueInDefinedReg(const MachineInstr *MI) {
-  assert (MI->isDebugValue() && "Invalid DBG_VALUE machine instruction!");
+  assert(MI->isDebugValue() && "Invalid DBG_VALUE machine instruction!");
   return MI->getNumOperands() == 3 &&
          MI->getOperand(0).isReg() && MI->getOperand(0).getReg() &&
          MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0;
@@ -864,7 +860,7 @@
   if (MI->getOperand(0).isCImm())
     return DotDebugLocEntry(FLabel, SLabel, MI->getOperand(0).getCImm());
 
-  assert (0 && "Unexpected 3 operand DBG_VALUE instruction!");
+  assert(0 && "Unexpected 3 operand DBG_VALUE instruction!");
   return DotDebugLocEntry();
 }
 
@@ -1132,7 +1128,7 @@
       const MachineInstr *MI = II;
 
       if (MI->isDebugValue()) {
-        assert (MI->getNumOperands() > 1 && "Invalid machine instruction!");
+        assert(MI->getNumOperands() > 1 && "Invalid machine instruction!");
 
         // Keep track of user variables.
         const MDNode *Var =
@@ -1300,7 +1296,7 @@
   
   LexicalScope *FnScope = LScopes.getCurrentFunctionScope();
   CompileUnit *TheCU = SPMap.lookup(FnScope->getScopeNode());
-  assert (TheCU && "Unable to find compile unit!");
+  assert(TheCU && "Unable to find compile unit!");
 
   // Construct abstract scopes.
   ArrayRef<LexicalScope *> AList = LScopes.getAbstractScopesList();



From mcrosier at apple.com  Wed Oct 26 18:17:28 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 26 Oct 2011 23:17:28 -0000
Subject: [llvm-commits] [llvm] r143076 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20111026231728.A4D0A312800A@llvm.org>

Author: mcrosier
Date: Wed Oct 26 18:17:28 2011
New Revision: 143076

URL: http://llvm.org/viewvc/llvm-project?rev=143076&view=rev
Log:
Use EmitCmp in SelectBranch.  No functional change intended.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=143076&r1=143075&r2=143076&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Oct 26 18:17:28 2011
@@ -1100,30 +1100,8 @@
 
   // If we can, avoid recomputing the compare - redoing it could lead to wonky
   // behavior.
-  // TODO: Factor this out.
   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
-    MVT SourceVT;
-    Type *Ty = CI->getOperand(0)->getType();
-    if (CI->hasOneUse() && (CI->getParent() == I->getParent())
-        && isTypeLegal(Ty, SourceVT)) {
-      bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
-      if (isFloat && !Subtarget->hasVFP2())
-        return false;
-
-      unsigned CmpOpc;
-      switch (SourceVT.SimpleTy) {
-        default: return false;
-        // TODO: Verify compares.
-        case MVT::f32:
-          CmpOpc = ARM::VCMPES;
-          break;
-        case MVT::f64:
-          CmpOpc = ARM::VCMPED;
-          break;
-        case MVT::i32:
-          CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
-          break;
-      }
+    if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
 
       // Get the compare predicate.
       // Try to take advantage of fallthrough opportunities.
@@ -1138,19 +1116,14 @@
       // We may not handle every CC for now.
       if (ARMPred == ARMCC::AL) return false;
 
-      unsigned Arg1 = getRegForValue(CI->getOperand(0));
-      if (Arg1 == 0) return false;
-
-      unsigned Arg2 = getRegForValue(CI->getOperand(1));
-      if (Arg2 == 0) return false;
-
-      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
-                              TII.get(CmpOpc))
-                      .addReg(Arg1).addReg(Arg2));
+      // Emit the compare.
+      Type *Ty = CI->getOperand(0)->getType();
+      if (!ARMEmitCmp(Ty, CI->getOperand(0), CI->getOperand(1)))
+        return false;
 
       // For floating point we need to move the result to a comparison register
       // that we can then use for branches.
-      if (isFloat)
+      if (Ty->isFloatTy() || Ty->isDoubleTy())
         AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                                 TII.get(ARM::FMSTAT)));
 



From lattner at apple.com  Wed Oct 26 18:26:27 2011
From: lattner at apple.com (Tanya Lattner)
Date: Wed, 26 Oct 2011 16:26:27 -0700
Subject: [llvm-commits] [PATCH] Lazily Link functions
Message-ID: <F9BF4DF3-6A0B-45B2-8B47-5E9AA8AF64F2@apple.com>

The attached patch will only link functions marked with specific linkage (Internal, LO_ODR, or LO linkage) if they have uses in the destination module. Instead of automatically linking, these functions are placed onto a worklist to be processed in the final stage of linking. We iterate over the list and if any functions on the list have uses in the destination module, we link them in and repeat the process until no changes in the state (uses) has changed. This means that any functions in the LazilyLink worklist that have a use in the destination module will be linked in and none that don't. 

Please review.

Thanks,
Tanya
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From mcrosier at apple.com  Wed Oct 26 18:25:44 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 26 Oct 2011 23:25:44 -0000
Subject: [llvm-commits] [llvm] r143078 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20111026232544.5C722312800A@llvm.org>

Author: mcrosier
Date: Wed Oct 26 18:25:44 2011
New Revision: 143078

URL: http://llvm.org/viewvc/llvm-project?rev=143078&view=rev
Log:
Factor a little more code into EmitCmp, which should have been done in the first
place.  No functional change intended.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=143078&r1=143077&r2=143078&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Oct 26 18:25:44 2011
@@ -173,7 +173,7 @@
   private:
     bool isTypeLegal(Type *Ty, MVT &VT);
     bool isLoadTypeLegal(Type *Ty, MVT &VT);
-    bool ARMEmitCmp(Type *Ty, const Value *Src1Value, const Value *Src2Value);
+    bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value);
     bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
     bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
     bool ARMComputeAddress(const Value *Obj, Address &Addr);
@@ -1117,16 +1117,9 @@
       if (ARMPred == ARMCC::AL) return false;
 
       // Emit the compare.
-      Type *Ty = CI->getOperand(0)->getType();
-      if (!ARMEmitCmp(Ty, CI->getOperand(0), CI->getOperand(1)))
+      if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1)))
         return false;
 
-      // For floating point we need to move the result to a comparison register
-      // that we can then use for branches.
-      if (Ty->isFloatTy() || Ty->isDoubleTy())
-        AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
-                                TII.get(ARM::FMSTAT)));
-
       unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
       .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
@@ -1188,13 +1181,14 @@
   return true;
 }
 
-bool ARMFastISel::ARMEmitCmp(Type *Ty, const Value *Src1Value,
-                             const Value *Src2Value) {
+bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value) {
   MVT VT;
+  Type *Ty = Src1Value->getType();
   if (!isTypeLegal(Ty, VT))
     return false;
 
-  if ((Ty->isFloatTy() || Ty->isDoubleTy()) && !Subtarget->hasVFP2())
+  bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
+  if (isFloat && !Subtarget->hasVFP2())
     return false;
 
   unsigned CmpOpc;
@@ -1220,11 +1214,18 @@
 
   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
                   .addReg(Src1).addReg(Src2));
+
+  // For floating point we need to move the result to a comparison register
+  // that we can then use for branches.
+  if (Ty->isFloatTy() || Ty->isDoubleTy())
+    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+                            TII.get(ARM::FMSTAT)));
   return true;
 }
 
 bool ARMFastISel::SelectCmp(const Instruction *I) {
   const CmpInst *CI = cast<CmpInst>(I);
+  Type *Ty = CI->getOperand(0)->getType();
 
   // Get the compare predicate.
   ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
@@ -1233,26 +1234,18 @@
   if (ARMPred == ARMCC::AL) return false;
 
   // Emit the compare.
-  Type *Ty = CI->getOperand(0)->getType();
-  if (!ARMEmitCmp(Ty, CI->getOperand(0), CI->getOperand(1)))
+  if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1)))
     return false;
 
-  // For floating point we need to move the result to a comparison register
-  // that we can then use for branches.
-  bool isFloat = Ty->isFloatTy() || Ty->isDoubleTy();
-  if (isFloat)
-    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
-                            TII.get(ARM::FMSTAT)));
-
   // Now set a register based on the comparison. Explicitly set the predicates
   // here.
   unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
   TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
                                     : ARM::GPRRegisterClass;
   unsigned DestReg = createResultReg(RC);
-  Constant *Zero
-    = ConstantInt::get(Type::getInt32Ty(*Context), 0);
+  Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
   unsigned ZeroReg = TargetMaterializeConstant(Zero);
+  bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
   unsigned CondReg = isFloat ? ARM::FPSCR : ARM::CPSR;
   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
           .addReg(ZeroReg).addImm(1)



From mcrosier at apple.com  Wed Oct 26 18:34:37 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 26 Oct 2011 23:34:37 -0000
Subject: [llvm-commits] [llvm] r143079 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20111026233437.C3883312800A@llvm.org>

Author: mcrosier
Date: Wed Oct 26 18:34:37 2011
New Revision: 143079

URL: http://llvm.org/viewvc/llvm-project?rev=143079&view=rev
Log:
Add a TODO comment.  FastISel works by parsing each basic block from the bottom
up.  Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle.  This creates many more 
opportunities for target specific fast-isel.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=143079&r1=143078&r2=143079&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Oct 26 18:34:37 2011
@@ -1193,6 +1193,7 @@
 
   unsigned CmpOpc;
   switch (VT.SimpleTy) {
+    // TODO: Add support for non-legal types (i.e., i1, i8, i16).
     default: return false;
     // TODO: Verify compares.
     case MVT::f32:



From peter at pcc.me.uk  Wed Oct 26 18:47:01 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Thu, 27 Oct 2011 00:47:01 +0100
Subject: [llvm-commits] [PATCH] Lazily Link functions
In-Reply-To: <F9BF4DF3-6A0B-45B2-8B47-5E9AA8AF64F2@apple.com>
References: <F9BF4DF3-6A0B-45B2-8B47-5E9AA8AF64F2@apple.com>
Message-ID: <20111026234701.GA17710@pcc.me.uk>

On Wed, Oct 26, 2011 at 04:26:27PM -0700, Tanya Lattner wrote:
> The attached patch will only link functions marked with specific linkage (Internal, LO_ODR, or LO linkage) if they have uses in the destination module. Instead of automatically linking, these functions are placed onto a worklist to be processed in the final stage of linking. We iterate over the list and if any functions on the list have uses in the destination module, we link them in and repeat the process until no changes in the state (uses) has changed. This means that any functions in the LazilyLink worklist that have a use in the destination module will be linked in and none that don't. 
> 
> Please review.

Hi Tanya,

> 
> Index: lib/Linker/LinkModules.cpp
> ===================================================================
> --- lib/Linker/LinkModules.cpp	(revision 142986)
> +++ lib/Linker/LinkModules.cpp	(working copy)
> @@ -341,6 +341,9 @@
>      // Set of items not to link in from source.
>      SmallPtrSet<const Value*, 16> DoNotLinkFromSource;
>      
> +    // Vector of functions to lazily link in.
> +    std::vector<Function*> LazilyLinkFunctions;
> +    
>    public:
>      std::string ErrorMsg;
>      
> @@ -449,7 +452,7 @@
>    bool SrcIsDeclaration = Src->isDeclaration();
>    bool DestIsDeclaration = Dest->isDeclaration();
>    
> -  if (SrcIsDeclaration) {
> +  if (SrcIsDeclaration && !Src->isMaterializable()) {
>      // If Src is external or if both Src & Dest are external..  Just link the
>      // external globals, we aren't adding anything.
>      if (Src->hasDLLImportLinkage()) {
> @@ -708,6 +711,12 @@
>      // Any uses of DF need to change to NewDF, with cast.
>      DGV->replaceAllUsesWith(ConstantExpr::getBitCast(NewDF, DGV->getType()));
>      DGV->eraseFromParent();
> +  } else {
> +    // Internal, LO_ODR, or LO linkage - stick in set to ignore and lazily link.
> +    if (SF->hasLinkOnceLinkage() || SF->hasInternalLinkage()) {
> +      DoNotLinkFromSource.insert(SF);
> +      LazilyLinkFunctions.push_back(SF);
> +    }

Shouldn't this use the same set of linkages as globaldce; i.e. hasLocalLinkage,
hasLinkOnceLinkage or hasAvailableExternallyLinkage?

Thanks,
-- 
Peter

From lhames at gmail.com  Wed Oct 26 18:50:43 2011
From: lhames at gmail.com (Lang Hames)
Date: Wed, 26 Oct 2011 23:50:43 -0000
Subject: [llvm-commits] [llvm] r143080 - in /llvm/trunk:
 include/llvm/Target/TargetLowering.h
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.h
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
Message-ID: <20111026235043.A7D3F312800A@llvm.org>

Author: lhames
Date: Wed Oct 26 18:50:43 2011
New Revision: 143080

URL: http://llvm.org/viewvc/llvm-project?rev=143080&view=rev
Log:
Rename NonScalarIntSafe to something more appropriate.

Modified:
    llvm/trunk/include/llvm/Target/TargetLowering.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h

Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=143080&r1=143079&r2=143080&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Oct 26 18:50:43 2011
@@ -646,7 +646,7 @@
   /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
   /// means there isn't a need to check it against alignment requirement,
   /// probably because the source does not need to be loaded. If
-  /// 'NonScalarIntSafe' is true, that means it's safe to return a
+  /// 'IsZeroVal' is true, that means it's safe to return a
   /// non-scalar-integer type, e.g. empty string source, constant, or loaded
   /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
   /// constant so it does not need to be loaded.
@@ -654,7 +654,7 @@
   /// target-independent logic.
   virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
                                   unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
-                                  bool /*NonScalarIntSafe*/,
+                                  bool /*IsZeroVal*/,
                                   bool /*MemcpyStrSrc*/,
                                   MachineFunction &/*MF*/) const {
     return MVT::Other;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=143080&r1=143079&r2=143080&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Oct 26 18:50:43 2011
@@ -3345,7 +3345,7 @@
 static bool FindOptimalMemOpLowering(std::vector<EVT> &MemOps,
                                      unsigned Limit, uint64_t Size,
                                      unsigned DstAlign, unsigned SrcAlign,
-                                     bool NonScalarIntSafe,
+                                     bool IsZeroVal,
                                      bool MemcpyStrSrc,
                                      SelectionDAG &DAG,
                                      const TargetLowering &TLI) {
@@ -3359,7 +3359,7 @@
   // 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does
   // not need to be loaded.
   EVT VT = TLI.getOptimalMemOpType(Size, DstAlign, SrcAlign,
-                                   NonScalarIntSafe, MemcpyStrSrc,
+                                   IsZeroVal, MemcpyStrSrc,
                                    DAG.getMachineFunction());
 
   if (VT == MVT::Other) {
@@ -3606,11 +3606,11 @@
   FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Dst);
   if (FI && !MFI->isFixedObjectIndex(FI->getIndex()))
     DstAlignCanChange = true;
-  bool NonScalarIntSafe =
+  bool IsZeroVal =
     isa<ConstantSDNode>(Src) && cast<ConstantSDNode>(Src)->isNullValue();
   if (!FindOptimalMemOpLowering(MemOps, TLI.getMaxStoresPerMemset(OptSize),
                                 Size, (DstAlignCanChange ? 0 : Align), 0,
-                                NonScalarIntSafe, false, DAG, TLI))
+                                IsZeroVal, false, DAG, TLI))
     return SDValue();
 
   if (DstAlignCanChange) {

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=143080&r1=143079&r2=143080&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Oct 26 18:50:43 2011
@@ -5774,7 +5774,7 @@
 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
 /// means there isn't a need to check it against alignment requirement,
 /// probably because the source does not need to be loaded. If
-/// 'NonScalarIntSafe' is true, that means it's safe to return a
+/// 'IsZeroVal' is true, that means it's safe to return a
 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
 /// constant so it does not need to be loaded.
@@ -5782,7 +5782,7 @@
 /// target-independent logic.
 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
                                            unsigned DstAlign, unsigned SrcAlign,
-                                           bool NonScalarIntSafe,
+                                           bool IsZeroVal,
                                            bool MemcpyStrSrc,
                                            MachineFunction &MF) const {
   if (this->PPCSubTarget.isPPC64()) {

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=143080&r1=143079&r2=143080&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Wed Oct 26 18:50:43 2011
@@ -353,7 +353,7 @@
     /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
     /// means there isn't a need to check it against alignment requirement,
     /// probably because the source does not need to be loaded. If
-    /// 'NonScalarIntSafe' is true, that means it's safe to return a
+    /// 'IsZeroVal' is true, that means it's safe to return a
     /// non-scalar-integer type, e.g. empty string source, constant, or loaded
     /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
     /// constant so it does not need to be loaded.
@@ -361,7 +361,7 @@
     /// target-independent logic.
     virtual EVT
     getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
-                        bool NonScalarIntSafe, bool MemcpyStrSrc,
+                        bool IsZeroVal, bool MemcpyStrSrc,
                         MachineFunction &MF) const;
 
   private:

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=143080&r1=143079&r2=143080&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Oct 26 18:50:43 2011
@@ -1232,7 +1232,7 @@
 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
 /// means there isn't a need to check it against alignment requirement,
 /// probably because the source does not need to be loaded. If
-/// 'NonScalarIntSafe' is true, that means it's safe to return a
+/// 'IsZeroVal' is true, that means it's safe to return a
 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
 /// constant so it does not need to be loaded.
@@ -1241,14 +1241,14 @@
 EVT
 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
                                        unsigned DstAlign, unsigned SrcAlign,
-                                       bool NonScalarIntSafe,
+                                       bool IsZeroVal,
                                        bool MemcpyStrSrc,
                                        MachineFunction &MF) const {
   // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
   // linux.  This is because the stack realignment code can't handle certain
   // cases like PR2962.  This should be removed when PR2962 is fixed.
   const Function *F = MF.getFunction();
-  if (NonScalarIntSafe &&
+  if (IsZeroVal &&
       !F->hasFnAttr(Attribute::NoImplicitFloat)) {
     if (Size >= 16 &&
         (Subtarget->isUnalignedMemAccessFast() ||

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=143080&r1=143079&r2=143080&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Oct 26 18:50:43 2011
@@ -533,7 +533,7 @@
     /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
     /// means there isn't a need to check it against alignment requirement,
     /// probably because the source does not need to be loaded. If
-    /// 'NonScalarIntSafe' is true, that means it's safe to return a
+    /// 'IsZeroVal' is true, that means it's safe to return a
     /// non-scalar-integer type, e.g. empty string source, constant, or loaded
     /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
     /// constant so it does not need to be loaded.
@@ -541,7 +541,7 @@
     /// target-independent logic.
     virtual EVT
     getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
-                        bool NonScalarIntSafe, bool MemcpyStrSrc,
+                        bool IsZeroVal, bool MemcpyStrSrc,
                         MachineFunction &MF) const;
 
     /// allowsUnalignedMemoryAccesses - Returns true if the target allows



From lattner at apple.com  Wed Oct 26 19:12:43 2011
From: lattner at apple.com (Tanya Lattner)
Date: Wed, 26 Oct 2011 17:12:43 -0700
Subject: [llvm-commits] [PATCH] Lazily Link functions
In-Reply-To: <20111026234701.GA17710@pcc.me.uk>
References: <F9BF4DF3-6A0B-45B2-8B47-5E9AA8AF64F2@apple.com>
	<20111026234701.GA17710@pcc.me.uk>
Message-ID: <4CDF3ACC-822A-42D5-AA8C-5DA4758ED516@apple.com>


On Oct 26, 2011, at 4:47 PM, Peter Collingbourne wrote:

> On Wed, Oct 26, 2011 at 04:26:27PM -0700, Tanya Lattner wrote:
>> The attached patch will only link functions marked with specific linkage (Internal, LO_ODR, or LO linkage) if they have uses in the destination module. Instead of automatically linking, these functions are placed onto a worklist to be processed in the final stage of linking. We iterate over the list and if any functions on the list have uses in the destination module, we link them in and repeat the process until no changes in the state (uses) has changed. This means that any functions in the LazilyLink worklist that have a use in the destination module will be linked in and none that don't. 
>> 
>> Please review.
> 
> Hi Tanya,
> 
>> 
>> Index: lib/Linker/LinkModules.cpp
>> ===================================================================
>> --- lib/Linker/LinkModules.cpp	(revision 142986)
>> +++ lib/Linker/LinkModules.cpp	(working copy)
>> @@ -341,6 +341,9 @@
>>     // Set of items not to link in from source.
>>     SmallPtrSet<const Value*, 16> DoNotLinkFromSource;
>> 
>> +    // Vector of functions to lazily link in.
>> +    std::vector<Function*> LazilyLinkFunctions;
>> +    
>>   public:
>>     std::string ErrorMsg;
>> 
>> @@ -449,7 +452,7 @@
>>   bool SrcIsDeclaration = Src->isDeclaration();
>>   bool DestIsDeclaration = Dest->isDeclaration();
>> 
>> -  if (SrcIsDeclaration) {
>> +  if (SrcIsDeclaration && !Src->isMaterializable()) {
>>     // If Src is external or if both Src & Dest are external..  Just link the
>>     // external globals, we aren't adding anything.
>>     if (Src->hasDLLImportLinkage()) {
>> @@ -708,6 +711,12 @@
>>     // Any uses of DF need to change to NewDF, with cast.
>>     DGV->replaceAllUsesWith(ConstantExpr::getBitCast(NewDF, DGV->getType()));
>>     DGV->eraseFromParent();
>> +  } else {
>> +    // Internal, LO_ODR, or LO linkage - stick in set to ignore and lazily link.
>> +    if (SF->hasLinkOnceLinkage() || SF->hasInternalLinkage()) {
>> +      DoNotLinkFromSource.insert(SF);
>> +      LazilyLinkFunctions.push_back(SF);
>> +    }
> 
> Shouldn't this use the same set of linkages as globaldce; i.e. hasLocalLinkage,
> hasLinkOnceLinkage or hasAvailableExternallyLinkage?

Hmm.. if I am understanding all these different linkage types correctly, then I don't think it should be a problem to change this to:
if (SF->hasLocalLinkage() || SF->hasLinkOnceLinkage() || SF.hashasAvailableExternallyLinkage())

This would then capture:
internal, private, linker_private, linker_private_weak, linker_private_weak_def_auto, linkonce, linkonce_odr, and available_externally

-Tanya


From mcrosier at apple.com  Wed Oct 26 19:21:16 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Thu, 27 Oct 2011 00:21:16 -0000
Subject: [llvm-commits] [llvm] r143086 - in /llvm/trunk:
 lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel-br-const.ll
Message-ID: <20111027002116.C4E63312800A@llvm.org>

Author: mcrosier
Date: Wed Oct 26 19:21:16 2011
New Revision: 143086

URL: http://llvm.org/viewvc/llvm-project?rev=143086&view=rev
Log:
A branch predicated on a constant can just FastEmit an unconditional branch.

Added:
    llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=143086&r1=143085&r2=143086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Oct 26 19:21:16 2011
@@ -1151,6 +1151,12 @@
       FuncInfo.MBB->addSuccessor(TBB);
       return true;
     }
+  } else if (const ConstantInt *CI =
+             dyn_cast<ConstantInt>(BI->getCondition())) {
+    uint64_t Imm = CI->getZExtValue();
+    MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
+    FastEmitBranch(Target, DL);
+    return true;
   }
 
   unsigned CmpReg = getRegForValue(BI->getCondition());

Added: llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll?rev=143086&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-br-const.ll Wed Oct 26 19:21:16 2011
@@ -0,0 +1,47 @@
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
+
+define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
+entry:
+; THUMB: t1:
+; ARM: t1:
+
+  br i1 1, label %if.then, label %if.else
+; THUMB-NOT: b LBB0_1
+; ARM-NOT:  b LBB0_1
+
+if.then:                                          ; preds = %entry
+  call void @foo1()
+  br label %if.end7
+
+if.else:                                          ; preds = %entry
+  br i1 0, label %if.then2, label %if.else3
+; THUMB: b LBB0_4
+; ARM:  b LBB0_4
+
+if.then2:                                         ; preds = %if.else
+  call void @foo2()
+  br label %if.end6
+
+if.else3:                                         ; preds = %if.else
+  br i1 1, label %if.then5, label %if.end
+; THUMB-NOT: b LBB0_5
+; ARM-NOT:  b LBB0_5
+
+if.then5:                                         ; preds = %if.else3
+  call void @foo1()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then5, %if.else3
+  br label %if.end6
+
+if.end6:                                          ; preds = %if.end, %if.then2
+  br label %if.end7
+
+if.end7:                                          ; preds = %if.end6, %if.then
+  ret i32 0
+}
+
+declare void @foo1()
+
+declare void @foo2()



From echristo at apple.com  Wed Oct 26 19:28:50 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 26 Oct 2011 17:28:50 -0700
Subject: [llvm-commits] [llvm] r143086 - in /llvm/trunk:
 lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel-br-const.ll
In-Reply-To: <20111027002116.C4E63312800A@llvm.org>
References: <20111027002116.C4E63312800A@llvm.org>
Message-ID: <70580F7F-B502-4D0D-BAEB-415603AB21FD@apple.com>


On Oct 26, 2011, at 5:21 PM, Chad Rosier wrote:

> A branch predicated on a constant can just FastEmit an unconditional branch.

Nice! Thanks :)

-eric
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From nlewycky at google.com  Wed Oct 26 19:37:23 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Wed, 26 Oct 2011 17:37:23 -0700
Subject: [llvm-commits] patch: pick direct or indirect strings in DWARF
In-Reply-To: <4EA66F4A.4070901@mxc.ca>
References: <CADbEz-jaVTjVkBLoFU0rvU7Vc83_T0vHWeqS21QLMy=WOQmM6w@mail.gmail.com>
	<4EA66F4A.4070901@mxc.ca>
Message-ID: <CADbEz-gDnE1W1A4k2=HOUj1cEPdCRgwgFFOu296Kz4HKc2NrZQ@mail.gmail.com>

New patch! Updates tests and adds new test. Tested on Linux and Darwin.

The previous patch looked like it worked on linux but didn't (readelf -w on
the .o file was fine, but it didn't have relocations so after linking the
debug info in the result was wrong). Darwin needs to not have relocations
for its string pool entries, while linux needs to have them.

Please review!

I have not tested this for size improvements in .o files, but I expect it to
help there too. If you have a function with an overload or that is
templated, the DW_AT_name will be repeated each time. This patch interns
those copies. For strings that only occur once, we pay an overhead of 4
bytes (unless the string is 4 bytes, in which case we provide it
immediately)

I have however looked at the size reduction of a few small real-world C++
programs at -g -O0 on Linux.

Before this patch:
Clang: 804,833,856 bytes
Program 1: 1,732,799,096 bytes
Program 2: 2,277,486,312 bytes
Program 3: 1,509,342,448 bytes

After this patch:
Clang: 417,182,256 bytes
Program 1: 935,406,928 bytes
Program 2: 1,239,206,568 bytes
Program 3: 825,010,104 bytes

So in my small sample, the new binaries are roughly 50-55% the size after
this patch is applied. Before we get too excited, I should also show gcc's
numbers:

Clang: 286,878,920 bytes
Program 1: 694,820,176 bytes
Program 2: 909,171,592 bytes
Program 3: 613,554,952 bytes

which suggests that we have further room to improve.

Nick

On 25 October 2011 01:11, Nick Lewycky <nicholas at mxc.ca> wrote:

> Updated patch, this one works on Darwin now too.
>
> I have tested this patch on Darwin in both -m32 and -m64 modes. The
> difference from the previous patch is that I now use DIEDelta to compute a
> section offset against the string pool, instead of DIELabel to refer to the
> string directly (hey, it worked for me on Linux).
>
> Please review!
>
> Nick
>
> Nick Lewycky wrote:
>
>> DWARF allows string to be specified in one of two ways, either by
>> writing them literally (DW_FORM_string) or by including a pointer into
>> the .debug_str section and putting the NUL-terminated string there.
>>
>> The attached patch removes the Form argument from CompileUnit::AddString
>> and changes addString to emit either a DIEString or a DIELabel depending
>> on how long the string is. If the string would fit in 4 bytes in the
>> direct encoding, do that. Otherwise, hoist it out into .debug_str so
>> that it can be interned.
>>
>> This is a major issue on linux where the linker does not turn direct
>> strings into indirect strings, but does merge the string tables. On
>> Darwin, the linker will turn direct strings into indirect strings as
>> needed. However, this change should probably be enabled on all platforms
>> as it generally makes .o files smaller.
>>
>> Please review! The one thing I don't like about this patch is that we
>> emit the bytes (via .ascii) and then emit the NUL (via. ".zero 1"). The
>> alternatives I see are either to create a copy of the string, or to
>> create a new emitBytesWithNUL API in MCStreamer.
>>
>> Nick
>>
>> PS. If this patch doesn't work on Darwin out-of-the-box, please try one
>> thing for me: comment out the change to DIELabel::SizeOf (adding a case
>> for DW_FORM_strp), and let me know whether that fixes things.
>>
>>
>>
>> ______________________________**_________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/**mailman/listinfo/llvm-commits<http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits>
>>
>
>
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From eli.friedman at gmail.com  Wed Oct 26 20:33:51 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 27 Oct 2011 01:33:51 -0000
Subject: [llvm-commits] [llvm] r143093 - in /llvm/trunk:
 lib/Transforms/Scalar/IndVarSimplify.cpp
 test/Transforms/IndVarSimplify/sink-alloca.ll
Message-ID: <20111027013351.BF02A312800A@llvm.org>

Author: efriedma
Date: Wed Oct 26 20:33:51 2011
New Revision: 143093

URL: http://llvm.org/viewvc/llvm-project?rev=143093&view=rev
Log:
It is not safe to sink an alloca into a stacksave/stackrestore pair, so don't do that. <rdar://problem/10352360>


Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
    llvm/trunk/test/Transforms/IndVarSimplify/sink-alloca.ll

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=143093&r1=143092&r2=143093&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Wed Oct 26 20:33:51 2011
@@ -1680,11 +1680,12 @@
     if (isa<LandingPadInst>(I))
       continue;
 
-    // Don't sink static AllocaInsts out of the entry block, which would
-    // turn them into dynamic allocas!
-    if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
-      if (AI->isStaticAlloca())
-        continue;
+    // Don't sink alloca: we never want to sink static alloca's out of the
+    // entry block, and correctly sinking dynamic alloca's requires
+    // checks for stacksave/stackrestore intrinsics.
+    // FIXME: Refactor this check somehow?
+    if (isa<AllocaInst>(I))
+      continue;
 
     // Determine if there is a use in or before the loop (direct or
     // otherwise).

Modified: llvm/trunk/test/Transforms/IndVarSimplify/sink-alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/sink-alloca.ll?rev=143093&r1=143092&r2=143093&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/sink-alloca.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/sink-alloca.ll Wed Oct 26 20:33:51 2011
@@ -1,15 +1,10 @@
 ; RUN: opt < %s -indvars -S | FileCheck %s
-; PR4775
-
-; Indvars shouldn't sink the alloca out of the entry block, even though
-; it's not used until after the loop.
-
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin10.0"
 
- at llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @main to i8*)],
-section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
-
+; PR4775
+; Indvars shouldn't sink the alloca out of the entry block, even though
+; it's not used until after the loop.
 define i32 @main() nounwind {
 ; CHECK: entry:
 ; CHECK-NEXT: %result.i = alloca i32, align 4
@@ -27,5 +22,35 @@
   %tmp.i = volatile load i32* %result.i           ; <i32> [#uses=0]
   ret i32 0
 }
-
 declare i32 @bar()
+
+; <rdar://problem/10352360>
+; Indvars shouldn't sink the first alloca between the stacksave and stackrestore
+; intrinsics.
+declare i8* @a(...)
+declare i8* @llvm.stacksave() nounwind
+declare void @llvm.stackrestore(i8*) nounwind
+define void @h(i64 %n) nounwind uwtable ssp {
+; CHECK: entry:
+; CHECK-NEXT: %vla = alloca i8*
+; CHECK-NEXT: %savedstack = call i8* @llvm.stacksave()
+entry:
+  %vla = alloca i8*, i64 %n, align 16
+  %savedstack = call i8* @llvm.stacksave() nounwind
+  %vla.i = alloca i8*, i64 %n, align 16
+  br label %for.body.i
+
+for.body.i:
+  %indvars.iv37.i = phi i64 [ %indvars.iv.next38.i, %for.body.i ], [ 0, %entry ]
+  %call.i = call i8* (...)* @a() nounwind
+  %arrayidx.i = getelementptr inbounds i8** %vla.i, i64 %indvars.iv37.i
+  store i8* %call.i, i8** %arrayidx.i, align 8
+  %indvars.iv.next38.i = add i64 %indvars.iv37.i, 1
+  %exitcond5 = icmp eq i64 %indvars.iv.next38.i, %n
+  br i1 %exitcond5, label %g.exit, label %for.body.i
+
+g.exit:
+  call void @llvm.stackrestore(i8* %savedstack) nounwind
+  %call1 = call i8* (...)* @a(i8** %vla) nounwind
+  ret void
+}



From eli.friedman at gmail.com  Wed Oct 26 21:06:39 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 27 Oct 2011 02:06:39 -0000
Subject: [llvm-commits] [llvm] r143095 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/i128-sdiv.ll
Message-ID: <20111027020639.BC9A5312800A@llvm.org>

Author: efriedma
Date: Wed Oct 26 21:06:39 2011
New Revision: 143095

URL: http://llvm.org/viewvc/llvm-project?rev=143095&view=rev
Log:
Don't crash on 128-bit sdiv by constant.  Found by inspection.
 

Added:
    llvm/trunk/test/CodeGen/X86/i128-sdiv.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=143095&r1=143094&r2=143095&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Oct 26 21:06:39 2011
@@ -1756,7 +1756,7 @@
   if (N0C && N1C && !N1C->isNullValue())
     return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
   // fold (sdiv X, 1) -> X
-  if (N1C && N1C->getSExtValue() == 1LL)
+  if (N1C && N1C->getAPIntValue() == 1LL)
     return N0;
   // fold (sdiv X, -1) -> 0-X
   if (N1C && N1C->isAllOnesValue())
@@ -1771,16 +1771,14 @@
   }
   // fold (sdiv X, pow2) -> simple ops after legalize
   if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
-      (isPowerOf2_64(N1C->getSExtValue()) ||
-       isPowerOf2_64(-N1C->getSExtValue()))) {
+      (N1C->getAPIntValue().isPowerOf2() ||
+       (-N1C->getAPIntValue()).isPowerOf2())) {
     // If dividing by powers of two is cheap, then don't perform the following
     // fold.
     if (TLI.isPow2DivCheap())
       return SDValue();
 
-    int64_t pow2 = N1C->getSExtValue();
-    int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
-    unsigned lg2 = Log2_64(abs2);
+    unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
 
     // Splat the sign bit into the register
     SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
@@ -1800,7 +1798,7 @@
 
     // If we're dividing by a positive value, we're done.  Otherwise, we must
     // negate the result.
-    if (pow2 > 0)
+    if (N1C->getAPIntValue().isNonNegative())
       return SRA;
 
     AddToWorkList(SRA.getNode());
@@ -1810,8 +1808,7 @@
 
   // if integer divide is expensive and we satisfy the requirements, emit an
   // alternate sequence.
-  if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
-      !TLI.isIntDivCheap()) {
+  if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
     SDValue Op = BuildSDIV(N);
     if (Op.getNode()) return Op;
   }

Added: llvm/trunk/test/CodeGen/X86/i128-sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i128-sdiv.ll?rev=143095&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/i128-sdiv.ll (added)
+++ llvm/trunk/test/CodeGen/X86/i128-sdiv.ll Wed Oct 26 21:06:39 2011
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+; Make sure none of these crash, and that the power-of-two transformations
+; trigger correctly.
+
+define i128 @test1(i128 %x) {
+  ; CHECK: test1:
+  ; CHECK-NOT: call
+  %tmp = sdiv i128 %x, 73786976294838206464
+  ret i128 %tmp
+}
+
+define i128 @test2(i128 %x) {
+  ; CHECK: test2:
+  ; CHECK-NOT: call
+  %tmp = sdiv i128 %x, -73786976294838206464
+  ret i128 %tmp
+}
+
+define i128 @test3(i128 %x) {
+  ; CHECK: test3:
+  ; CHECK: call
+  %tmp = sdiv i128 %x, -73786976294838206467
+  ret i128 %tmp
+}



From joerg at britannica.bec.de  Wed Oct 26 21:29:13 2011
From: joerg at britannica.bec.de (Joerg Sonnenberger)
Date: Wed, 26 Oct 2011 19:29:13 -0700
Subject: [llvm-commits] [cfe-commits] Ping^2: Fix for bug 11060:
 configure --target does not work
In-Reply-To: <CAE5reQLEvirPzur-q0HPKkBvJZ=EDnWOm6BXogCvbQNUu6bw6g@mail.gmail.com>
References: <CAE5reQLPxYDFQB3zi3FO-dU1xKtndJM+pwFy+kmFxg23hFgJ2w@mail.gmail.com>
	<03B3C19A-52C5-48D5-BBFB-479966ECA09C@apple.com>
	<CAE5reQKS3TWCGnZB9V5FUHh18tPu15Rqeb4hPp7ziHa1c_+YRA@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713404@GEORGE.Emea.Arm.com>
	<CAE5reQKuxURmZcTRhjU1p7MURECVKXFF8tjRZmD23+6zHBVQWQ@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713405@GEORGE.Emea.Arm.com>
	<64775AFC-9ADD-4C75-86EE-9688036285EB@apple.com>
	<CAE5reQJ3J5T1z8JCfkdHM63u8Shsddpty5=PCjx1X-Xp4yjR5Q@mail.gmail.com>
	<20111026165442.GD19773@britannica.bec.de>
	<CAE5reQLEvirPzur-q0HPKkBvJZ=EDnWOm6BXogCvbQNUu6bw6g@mail.gmail.com>
Message-ID: <20111027022913.GA21866@britannica.bec.de>

On Wed, Oct 26, 2011 at 01:33:38PM -0500, Sebastian Pop wrote:
[snip]
> 
> > Which part of "LLVM_HOSTTRIPLE controls the target" was unclear?
> 
> LLVM_HOSTTRIPLE should *not* control the target.
> $host and $target are two different things (in the cross compilers world.)

*sigh* Can you please check what the code is using LLVM_HOSTTRIPLE for?
Hint: it is the default target. As I said earlier and as you have
ignored, the notation of host and target in LLVM/Clang is generally
bogus and and most (if not all) notions of "host" actually mean
"target". The host system for the compiler is pretty much irrelevant
other than to get the right compiler for building and maybe the right
endianess.

> How would you select the value set by configure in $target after you
> have thrown away the information that configure has set in $target?

I've told you already, I think deriving the default value of
LLVM_HOSTTRIPLE from $target makes more sense. What I object to is
introducing another macro and associated support code which doesn't
serve any purpose.

Joerg

From spop at codeaurora.org  Wed Oct 26 21:45:41 2011
From: spop at codeaurora.org (Sebastian Pop)
Date: Wed, 26 Oct 2011 21:45:41 -0500
Subject: [llvm-commits] [cfe-commits] Ping^2: Fix for bug 11060:
 configure --target does not work
In-Reply-To: <20111027022913.GA21866@britannica.bec.de>
References: <CAE5reQLPxYDFQB3zi3FO-dU1xKtndJM+pwFy+kmFxg23hFgJ2w@mail.gmail.com>
	<03B3C19A-52C5-48D5-BBFB-479966ECA09C@apple.com>
	<CAE5reQKS3TWCGnZB9V5FUHh18tPu15Rqeb4hPp7ziHa1c_+YRA@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713404@GEORGE.Emea.Arm.com>
	<CAE5reQKuxURmZcTRhjU1p7MURECVKXFF8tjRZmD23+6zHBVQWQ@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713405@GEORGE.Emea.Arm.com>
	<64775AFC-9ADD-4C75-86EE-9688036285EB@apple.com>
	<CAE5reQJ3J5T1z8JCfkdHM63u8Shsddpty5=PCjx1X-Xp4yjR5Q@mail.gmail.com>
	<20111026165442.GD19773@britannica.bec.de>
	<CAE5reQLEvirPzur-q0HPKkBvJZ=EDnWOm6BXogCvbQNUu6bw6g@mail.gmail.com>
	<20111027022913.GA21866@britannica.bec.de>
Message-ID: <CAE5reQ+oyYNMuuCCC2hgnsWUwCYXR1zfZs+nkT6Y9dyKznK7pQ@mail.gmail.com>

On Wed, Oct 26, 2011 at 9:29 PM, Joerg Sonnenberger
<joerg at britannica.bec.de> wrote:
> I've told you already, I think deriving the default value of
> LLVM_HOSTTRIPLE from $target makes more sense. What I object to is
> introducing another macro and associated support code which doesn't
> serve any purpose.

How are these two different:

1. create LLVM_DEFAULT_TARGET from $target, and remove LLVM_HOSTTRIPLE
(I'll let you post a patch that removes LLVM_HOSTTRIPLE as you said
that HOST is unused)

2. derive LLVM_HOSTTRIPLE from $target as you proposed, then rename
LLVM_HOSTTRIPLE into something more meaningful, like what I proposed
LLVM_DEFAULT_TARGET.

?

Thanks for clarifying your stand point if it differs from the two above.

Sebastian
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

From chenwj at iis.sinica.edu.tw  Mon Oct 24 03:37:02 2011
From: chenwj at iis.sinica.edu.tw (=?utf-8?B?6Zmz6Z+L5Lu7?=)
Date: Mon, 24 Oct 2011 16:37:02 +0800
Subject: [llvm-commits] [PATCH][docs/CommandGuide] Reveal there is a
 "-help-hidden" option for opt command
In-Reply-To: <F78C3E71-7674-4E05-A990-A8E9DF42F918@apple.com>
References: <20111023100324.GA3546@cs.nctu.edu.tw>
	<F78C3E71-7674-4E05-A990-A8E9DF42F918@apple.com>
Message-ID: <20111024083702.GA36571@cs.nctu.edu.tw>

> >  I think it's a good idea to tell people there is a "-help-hidden"
> > which shows more available options for `opt` command. For example,
> > people might need to control how inline is done by `opt` but don't
> > know there is "-inline-threshold" option which only appears with
> > "-help-hidden" (see the link below).  
> > 
> >  [LLVMdev] inline functions
> >  http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-October/044484.html
> > 
> Hi Chenwj,
> 
> I think that runs counter to what -help-hidden is for. The option is meant to hide those flags. Some of those flags are for works in progress. Some of them are for developer debugging. None of them are meant to be used by normal folk... :-)

  I know. What I think is people (developers) might need this option,
but don't know its existence. You know there are a lot of message
printed by `opt -help`, -help-hidden might just slip past their eyes
(at least to me ;-))  

Regards,
chenwj

-- 
Wei-Ren Chen (???)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667


From chenwj at iis.sinica.edu.tw  Mon Oct 24 04:12:11 2011
From: chenwj at iis.sinica.edu.tw (=?utf-8?B?6Zmz6Z+L5Lu7?=)
Date: Mon, 24 Oct 2011 17:12:11 +0800
Subject: [llvm-commits] [PATCH][docs/CommandGuide] Reveal there is a
 "-help-hidden" option for opt command
In-Reply-To: <4EA52204.6090903@free.fr>
References: <20111023100324.GA3546@cs.nctu.edu.tw> <4EA52204.6090903@free.fr>
Message-ID: <20111024091211.GA37465@cs.nctu.edu.tw>

Hi, Duncan

> I think it would be best to make -inline-threshold not be hidden.  I suspect
> there are a bunch of hidden options that shouldn't be hidden, and a bunch of
> not hidden options that should be hidden.  I think you shouldn't hesitate to
> send patches that change the hidden flag.

  Should we discuss which options should be hidden or not hidden on
LLVMdev mailing list? I want to collect developers' comment on this.

Regards,
chenwj

-- 
Wei-Ren Chen (???)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667


From gkistanova at gmail.com  Wed Oct 26 18:55:10 2011
From: gkistanova at gmail.com (Galina Kistanova)
Date: Wed, 26 Oct 2011 23:55:10 -0000
Subject: [llvm-commits] [zorg] r143081 - in
 /zorg/trunk/buildbot/osuosl/master/config: builders.py slaves.py status.py
Message-ID: <20111026235510.AC870312800A@llvm.org>

Author: gkistanova
Date: Wed Oct 26 18:55:10 2011
New Revision: 143081

URL: http://llvm.org/viewvc/llvm-project?rev=143081&view=rev
Log:
Moved off-line builders and slaves to #Offline sections instead of deleting.
Moved all clang builders to one place.
Change buildbot email address.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py
    zorg/trunk/buildbot/osuosl/master/config/slaves.py
    zorg/trunk/buildbot/osuosl/master/config/status.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=143081&r1=143080&r2=143081&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Wed Oct 26 18:55:10 2011
@@ -36,10 +36,6 @@
 # Plain LLVM builders.
 def _get_llvm_builders():
     return [
-#        {'name': "llvm-i686-linux",
-#         'slavenames': ["dunbar1"],
-#         'builddir': "llvm-i686",
-#         'factory': LLVMBuilder.getLLVMBuildFactory("i686-pc-linux-gnu", jobs=2, enable_shared=True)},
         {'name': "llvm-x86_64-linux",
          'slavenames': ["gcc14"],
          'builddir': "llvm-x86_64",
@@ -73,7 +69,7 @@
 {'name': "llvm-alpha-linux",
  'slavenames':["andrew1"],
  'builddir':"llvm-alpha",
- 'factory': LLVMBuilder.getLLVMBuildFactory("alpha-linux-gnu", jobs=2)}
+ 'factory': LLVMBuilder.getLLVMBuildFactory("alpha-linux-gnu", jobs=2)},
 {'name': "llvm-i386-auroraux",
  'slavenames':["evocallaghan"],
  'builddir':"llvm-i386-auroraux",
@@ -82,15 +78,26 @@
  'slavenames':["nick1"],
  'builddir':"llvm-ppc",
  'factory': LLVMBuilder.getLLVMBuildFactory("ppc-linux-gnu", jobs=1, clean=False, timeout=40)},
+{'name': "llvm-i686-linux-vg_leak",
+ 'slavenames':["osu8"],
+ 'builddir':"llvm-i686-linux-vg_leak",
+ 'factory': LLVMBuilder.getLLVMBuildFactory("i686-pc-linux-gnu", valgrind=True,
+                                             valgrindLeakCheck=True,
+                                             valgrindSuppressions='utils/valgrind/i386-pc-linux-gnu.supp')},
+{'name': "llvm-x86_64-linux-vg_leak",
+ 'slavenames':["osu7"],
+ 'builddir':"llvm-x86_64-linux-vg_leak",
+ 'factory': LLVMBuilder.getLLVMBuildFactory("x86_64-pc-linux-gnu", valgrind=True,
+                                             valgrindLeakCheck=True,
+                                             valgrindSuppressions='utils/valgrind/x86_64-pc-linux-gnu.supp')},
+{'name': "llvm-i686-linux",
+ 'slavenames': ["dunbar1"],
+ 'builddir': "llvm-i686",
+ 'factory': LLVMBuilder.getLLVMBuildFactory("i686-pc-linux-gnu", jobs=2, enable_shared=True)},
 
 # llvm-gcc self hosting builders.
 def _get_llvmgcc_builders():
     return [
-#        {'name' : "llvm-gcc-i686-darwin10-selfhost",
-#         'slavenames':["dunbar-darwin10"],
-#         'builddir':"llvm-gcc-i686-darwin10-selfhost",
-#         'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(4, triple='i686-apple-darwin10',
-#                                                         gxxincludedir='/usr/include/c++/4.2.1')},
         {'name' : "llvm-gcc-i386-linux-selfhost",
          'slavenames':["gcc11"],
          'builddir':"llvm-gcc-i386-linux-selfhost",
@@ -107,11 +114,6 @@
                                                          '--with-as=/home/baldrick/bin32/as',
                                                          '--with-mpfr=/home/baldrick/cfarm-32',
                                                          '--with-gmp=/home/baldrick/cfarm-32'])},
-#        {'name' : "llvm-gcc-x86_64-darwin10-selfhost",
-#         'slavenames':["dunbar-darwin10"],
-#         'builddir':"llvm-gcc-x86_64-darwin10-selfhost",
-#         'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(4, triple='x86_64-apple-darwin10',
-#                                                         gxxincludedir='/usr/include/c++/4.2.1')},
 
         {'name' : "llvm-x86_64-linux-checks",
          'slavenames':["gcc10"],
@@ -126,6 +128,23 @@
                                                          timeout=120)},
         ]
 
+# Offline.
+{'name' : "llvm-gcc-x86_64-linux-selfhost",
+ 'slavenames':["osu7"],
+ 'builddir':"llvm-gcc-x86_64-linux-selfhost",
+ 'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(triple='x86_64-pc-linux-gnu',
+                                                 extra_configure_args=['--disable-multilib'])},
+{'name' : "llvm-gcc-i686-darwin10-selfhost",
+ 'slavenames':["dunbar-darwin10"],
+ 'builddir':"llvm-gcc-i686-darwin10-selfhost",
+ 'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(4, triple='i686-apple-darwin10',
+                                                 gxxincludedir='/usr/include/c++/4.2.1')},
+{'name' : "llvm-gcc-x86_64-darwin10-selfhost",
+ 'slavenames':["dunbar-darwin10"],
+ 'builddir':"llvm-gcc-x86_64-darwin10-selfhost",
+ 'factory':LLVMGCCBuilder.getLLVMGCCBuildFactory(4, triple='x86_64-apple-darwin10',
+                                                 gxxincludedir='/usr/include/c++/4.2.1')},
+
 clang_i386_linux_xfails = [
     'GCCAS.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4',
     'Bytecode.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4',
@@ -155,38 +174,10 @@
 # Clang builders.
 def _get_clang_builders():
     return [
-#        {'name': "clang-x86_64-linux",
-#         'slavenames':["gcc14"],
-#         'builddir':"clang-x86_64-linux",
-#         'factory': ClangBuilder.getClangBuildFactory(examples=True)},
-#        {'name': "clang-i686-linux",
-#         'slavenames':["dunbar1"],
-#         'builddir':"clang-i686-linux",
-#         'factory': ClangBuilder.getClangBuildFactory()},
-        {'name': "clang-arm-linux",
-         'slavenames':["nick3"],
-         'builddir':"clang-arm-linux",
-         'factory': ClangBuilder.getClangBuildFactory()},
-#        {'name' : "clang-i686-darwin10",
-#         'slavenames' :["dunbar-darwin10"],
-#         'builddir' :"clang-i686-darwin10",
-#         'factory': ClangBuilder.getClangBuildFactory(triple='i686-apple-darwin10',
-#                                                      stage1_config='Release')},
         {'name': "clang-i686-freebsd",
          'slavenames':["freebsd1"],
          'builddir':"clang-i686-freebsd",
          'factory': ClangBuilder.getClangBuildFactory(clean=True, use_pty_in_tests=True)},
-#        {'name' : "clang-i686-xp-msvc9",
-#         'slavenames' :['dunbar-win32-2'],
-#         'builddir' :"clang-i686-xp-msvc9",
-#         'factory' : ClangBuilder.getClangMSVCBuildFactory(jobs=2)},
-#        {'name' : "clang-x86_64-darwin10-selfhost",
-#         'slavenames' : ["dunbar-darwin10"],
-#         'builddir' : "clang-x86_64-darwin10-selfhost",
-#         'factory' : ClangBuilder.getClangBuildFactory(triple='x86_64-apple-darwin10',
-#                                                       useTwoStage=True,
-#                                                       stage1_config='Release+Asserts',
-#                                                       stage2_config='Debug+Asserts')},
 
         {'name' : "clang-i686-linux-fnt",
          'slavenames' : ['balint1'],
@@ -215,7 +206,52 @@
          'factory' : NightlytestBuilder.getFastNightlyTestBuildFactory(triple='x86_64-pc-linux-gnu',
                                                                        stage1_config='Release+Asserts',
                                                                        test=False,
-                                                                       xfails=clang_x86_64_linux_xfails) },
+                                                                       xfails=clang_x86_64_linux_xfails)},
+ 
+        {'name': "clang-native-arm-cortex-a9",
+         'slavenames':["kistanova6"],
+         'builddir':"clang-native-arm-cortex-a9",
+         'factory' : ClangBuilder.getClangBuildFactory(
+                     extra_configure_args=['--build=armv7l-unknown-linux-gnueabi',
+                                           '--host=armv7l-unknown-linux-gnueabi',
+                                           '--target=armv7l-unknown-linux-gnueabi',
+                                           '--with-cpu=cortex-a9',
+                                           '--with-fpu=neon', '--with-abi=aapcs',
+                                           '--with-float=hard',
+                                           '--enable-targets=arm,cbe',
+                                           '--enable-optimized'])},
+
+        {'name': "clang-X86_64-freebsd",
+         'slavenames':["kistanova7"],
+         'builddir':"clang-X86_64-freebsd",
+         'factory': NightlytestBuilder.getFastNightlyTestBuildFactory(triple='x86_64-unknown-freebsd8.2',
+                                                                       stage1_config='Release+Asserts',
+                                                                       test=True)},
+
+        {'name': "clang-native-mingw32-win7",
+         'slavenames':["kistanova8"],
+         'builddir':"clang-native-mingw32-win7",
+         'factory' : ClangBuilder.getClangBuildFactory(triple='i686-pc-mingw32',
+                                                       useTwoStage=True, test=True,
+                                                       stage1_config='Release+Asserts',
+                                                       stage2_config='Release+Asserts')},
+        # Clang cross builders.
+        {'name': "clang-x86_64-darwin10-self-mingw32",
+         'slavenames':["kistanova1"],
+         'builddir':"clang-x86_64-darwin10-self-mingw32",
+         'factory' : ClangBuilder.getClangBuildFactory(outOfDir=True, jobs=4, test=False,
+                                                       extra_configure_args=['--build=x86_64-apple-darwin10',
+                                                                             '--host=i686-pc-mingw32',
+                                                                             '--target=i686-pc-mingw32'])},
+        {'name' : "clang-x86_64-darwin10-cross-mingw32",
+         'slavenames' :["kistanova1"],
+         'builddir' :"clang-x86_64-darwin10-cross-mingw32",
+         'factory' : ClangBuilder.getClangBuildFactory(outOfDir=True, jobs=4,  use_pty_in_tests=True,
+                                                       run_cxx_tests=True,
+                                                       extra_configure_args=['--build=x86_64-apple-darwin10',
+                                                                             '--host=x86_64-apple-darwin10',
+                                                                             '--target=i686-pc-mingw32'])},
+
         ]
 
 # Offline.
@@ -224,6 +260,59 @@
  'builddir':"clang-i386-auroraux",
  'factory': ClangBuilder.getClangBuildFactory("i386-pc-auroraux",
                                               jobs="%(jobs)s", make='gmake')},
+{'name': "clang-x86_64-linux-vg",
+ 'slavenames':["osu7"],
+ 'builddir':"clang-x86_64-linux-vg",
+ 'factory': ClangBuilder.getClangBuildFactory(valgrind=True)},
+{'name' : "clang-x86_64-linux-selfhost-rel",
+ 'slavenames' : ["osu7"],
+ 'builddir' : "clang-x86_64-linux-selfhost-rel",
+ 'factory' : ClangBuilder.getClangBuildFactory(triple='x86_64-pc-linux-gnu',
+                                               useTwoStage=True,
+                                               stage1_config='Release+Asserts',
+                                               stage2_config='Release+Asserts')},
+{'name' : "clang-x86_64-linux-fnt",
+ 'slavenames' : ['osu7'],
+ 'builddir' : "clang-x86_64-linux-fnt",
+ 'factory' : NightlytestBuilder.getFastNightlyTestBuildFactory(triple='x86_64-pc-linux-gnu',
+                                                               stage1_config='Release+Asserts',
+                                                               test=False,
+                                                               xfails=clang_x86_64_linux_xfails) },
+{'name' : "clang-i686-linux-selfhost-rel",
+ 'slavenames' : ["osu8"],
+ 'builddir' : "clang-i686-linux-selfhost-rel",
+ 'factory' : ClangBuilder.getClangBuildFactory(triple='i686-pc-linux-gnu',
+                                               useTwoStage=True,
+                                               stage1_config='Release+Asserts',
+                                               stage2_config='Release+Asserts')},
+{'name': "clang-x86_64-linux",
+ 'slavenames':["gcc14"],
+ 'builddir':"clang-x86_64-linux",
+ 'factory': ClangBuilder.getClangBuildFactory(examples=True)},
+{'name': "clang-i686-linux",
+ 'slavenames':["dunbar1"],
+ 'builddir':"clang-i686-linux",
+ 'factory': ClangBuilder.getClangBuildFactory()},
+{'name': "clang-arm-linux",
+ 'slavenames':["nick3"],
+ 'builddir':"clang-arm-linux",
+ 'factory': ClangBuilder.getClangBuildFactory()},
+{'name' : "clang-i686-darwin10",
+ 'slavenames' :["dunbar-darwin10"],
+ 'builddir' :"clang-i686-darwin10",
+ 'factory': ClangBuilder.getClangBuildFactory(triple='i686-apple-darwin10',
+                                              stage1_config='Release')},
+#{'name' : "clang-i686-xp-msvc9",
+# 'slavenames' :['dunbar-win32-2'],
+# 'builddir' :"clang-i686-xp-msvc9",
+# 'factory' : ClangBuilder.getClangMSVCBuildFactory(jobs=2)},
+{'name' : "clang-x86_64-darwin10-selfhost",
+ 'slavenames' : ["dunbar-darwin10"],
+ 'builddir' : "clang-x86_64-darwin10-selfhost",
+ 'factory' : ClangBuilder.getClangBuildFactory(triple='x86_64-apple-darwin10',
+                                               useTwoStage=True,
+                                               stage1_config='Release+Asserts',
+                                               stage2_config='Debug+Asserts')},
 
 def _get_dragonegg_builders():
     return [
@@ -273,7 +362,6 @@
 # LLDB builders.
 def _get_lldb_builders():
     gcc_latest_env = {
-        'PATH': '/opt/cfarm/python2-latest/bin:/usr/local/bin:/usr/bin:/bin:/usr/games',
         'CC':  '/opt/cfarm/release/4.5.1/bin/gcc',
         'CXX': '/opt/cfarm/release/4.5.1/bin/g++'}
 
@@ -296,75 +384,6 @@
 
 def _get_experimental_builders():
     return [
-
-#        {'name' : "clang-i386-darwin10-selfhost-rel",
-#         'slavenames' : ["dunbar-darwin10"],
-#         'builddir' : "clang-i386-darwin10-selfhost-rel",
-#         'factory' : ClangBuilder.getClangBuildFactory(triple='i386-apple-darwin10',
-#                                                       useTwoStage=True,
-#                                                       stage1_config='Release+Asserts',
-#                                                       stage2_config='Release+Asserts'),
-#         'category' : 'clang.exp' },
-#        {'name' : "clang-x86_64-darwin10-selfhost-rel",
-#         'slavenames' : ["dunbar-darwin10"],
-#         'builddir' : "clang-x86_64-darwin10-selfhost-rel",
-#         'factory' : ClangBuilder.getClangBuildFactory(triple='x86_64-apple-darwin10',
-#                                                       useTwoStage=True,
-#                                                       stage1_config='Release+Asserts',
-#                                                       stage2_config='Release+Asserts'),
-#         'category' : 'clang.exp' },
-
-        {'name': "clang-native-arm-cortex-a9",
-         'slavenames':["kistanova6"],
-         'builddir':"clang-native-arm-cortex-a9",
-         'factory' : ClangBuilder.getClangBuildFactory(
-                     extra_configure_args=['--build=armv7l-unknown-linux-gnueabi',
-                                           '--host=armv7l-unknown-linux-gnueabi',
-                                           '--target=armv7l-unknown-linux-gnueabi',
-                                           '--with-cpu=cortex-a9',
-                                           '--with-fpu=neon', '--with-abi=aapcs',
-                                           '--with-float=hard',
-                                           '--enable-targets=arm,cbe',
-                                           '--enable-optimized']),
-         'category' : 'clang'},
-
-        {'name': "clang-X86_64-freebsd",
-         'slavenames':["kistanova7"],
-         'builddir':"clang-X86_64-freebsd",
-         'factory': NightlytestBuilder.getFastNightlyTestBuildFactory(triple='x86_64-unknown-freebsd8.2',
-                                                                       stage1_config='Release+Asserts',
-                                                                       test=True),
-         'category' : 'clang'},
-
-        {'name': "clang-native-mingw32-win7",
-         'slavenames':["kistanova8"],
-         'builddir':"clang-native-mingw32-win7",
-         'factory' : ClangBuilder.getClangBuildFactory(triple='i686-pc-mingw32',
-                                                       useTwoStage=True, test=True,
-                                                       stage1_config='Release+Asserts',
-                                                       stage2_config='Release+Asserts'),
-         'category' : 'clang'},
-
-        # Clang cross builders.
-        {'name': "clang-x86_64-darwin10-self-mingw32",
-         'slavenames':["kistanova1"],
-         'builddir':"clang-x86_64-darwin10-self-mingw32",
-         'factory' : ClangBuilder.getClangBuildFactory(outOfDir=True, jobs=4, test=False,
-                                                       extra_configure_args=['--build=x86_64-apple-darwin10',
-                                                                             '--host=i686-pc-mingw32',
-                                                                             '--target=i686-pc-mingw32']),
-         'category' : 'clang'},
-
-        {'name' : "clang-x86_64-darwin10-cross-mingw32",
-         'slavenames' :["kistanova1"],
-         'builddir' :"clang-x86_64-darwin10-cross-mingw32",
-         'factory' : ClangBuilder.getClangBuildFactory(outOfDir=True, jobs=4,  use_pty_in_tests=True,
-                                                       run_cxx_tests=True,
-                                                       extra_configure_args=['--build=x86_64-apple-darwin10',
-                                                                             '--host=x86_64-apple-darwin10',
-                                                                             '--target=i686-pc-mingw32']),
-         'category' : 'clang'},
-
         # Llvm-gcc cross builders.
         {'name'      : "build-self-4-mingw32",
          'slavenames': [ "kistanova1" ],
@@ -425,7 +444,7 @@
                                        {'name'          : 'install_llvmgcc_2',
                                         'description'   : 'install llvm-gcc (stage2)',
                                         'haltOnFailure' : True },]),
-          'category'  : 'llvm-gcc' },
+         'category'  : 'llvm-gcc' },
 
         {'name'      : "llvm-gcc-x86_64-darwin10-cross-i686-linux",
          'slavenames': [ "kistanova1" ],
@@ -541,7 +560,6 @@
                                        {'name'          : 'install_llvmgcc_3',
                                         'description'   : 'install llvm-gcc (stage 3)',
                                         'haltOnFailure' : True },]),
-
          'category'  : 'llvm-gcc' },
 
         {'name'      : "llvm-gcc-native-mingw32",
@@ -716,49 +734,6 @@
                                         'haltOnFailure' : True },]),
          'category'  : 'llvm-gcc' },
 
-#        {'name'      : "llvm-gcc-mingw32-cross-arm-linux-gnueabi-hard-float",
-#         'slavenames': [ "kistanova5" ],
-#         'builddir'  : "llvm-gcc-mingw32-cross-arm-linux-gnueabi-hard-float",
-#         'factory'   : ScriptedBuilder.getScriptedBuildFactory(
-#                       source_code  = [SVN(name='svn-llvm',
-#                                           mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm/',
-#                                           defaultBranch='trunk',
-#                                           workdir="llvm.src"),
-#                                       SVN(name='svn-llvm-gcc',
-#                                           mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm-gcc-4.2/',
-#                                           defaultBranch='trunk',
-#                                           workdir="llvm-gcc.src"),],
-#                       launcher     = 'llvm-gcc.src/extras/buildbot-launcher',
-#                       build_script = 'llvm-gcc.src/extras/llvm-gcc-mingw32-cross-arm-linux-gnueabi-hard-float',
-#                       extra_args   = [],
-#                       build_steps  = [{'name'          : 'clean',
-#                                        'description'   : 'clean',
-#                                        'haltOnFailure' : True },
-#                                       {'name'          : 'copy_cross_tools',
-#                                        'description'   : 'copy cross-tools',
-#                                        'haltOnFailure' : True },
-#                                       {'name'          : 'configure_llvm',
-#                                        'description'   : 'configure llvm',
-#                                        'haltOnFailure' : True },
-#                                       {'name'          : 'make_llvm',
-#                                        'description'   : 'make llvm',
-#                                        'haltOnFailure' : True },
-#                                       {'name'          : 'configure_llvmgcc',
-#                                        'description'   : 'configure llvm-gcc',
-#                                        'haltOnFailure' : True },
-#                                       {'name'          : 'make_llvmgcc',
-#                                        'description'   : 'make llvm-gcc',
-#                                        'haltOnFailure' : True },
-#                                       {'name'          : 'install_llvmgcc',
-#                                        'description'   : 'install llvm-gcc',
-#                                        'haltOnFailure' : True },]),
-#         'category'  : 'llvm-gcc' },
-#        {'name' : "clang-i686-xp-msvc9_alt",
-#         'slavenames' :['adobe1'],
-#         'builddir' :"clang-i686-xp-msvc9_alt",
-#         'factory' : ClangBuilder.getClangMSVCBuildFactory(jobs=2),
-#         'category' : 'clang.exp' },
-
         {'name': "clang-i686-freebsd-selfhost-rel",
          'slavenames':["freebsd1"],
          'builddir':"clang-i686-freebsd-selfhost-rel",
@@ -799,10 +774,71 @@
         yield b
 
 # Random other unused builders...
-
 {'name': "clang-x86_64-openbsd",
  'slavenames':["ocean1"],
  'builddir':"clang-x86_64-openbsd",
  'factory': ClangBuilder.getClangBuildFactory(),
- 'category':'clang.exp'}
-
+ 'category':'clang.exp'},
+{'name': "clang-x86_64-linux-checks",
+ 'slavenames':["osu2"],
+ 'builddir':"clang-x86_64-linux-checks",
+ 'factory': ClangBuilder.getClangBuildFactory(stage1_config='Debug+Asserts+Checks'),
+ 'category':'clang.exp'},
+{'name' : "clang-i386-darwin10-selfhost-rel",
+ 'slavenames' : ["dunbar-darwin10"],
+ 'builddir' : "clang-i386-darwin10-selfhost-rel",
+ 'factory' : ClangBuilder.getClangBuildFactory(triple='i386-apple-darwin10',
+                                               useTwoStage=True,
+                                               stage1_config='Release+Asserts',
+                                               stage2_config='Release+Asserts'),
+ 'category' : 'clang.exp' },
+{'name' : "clang-x86_64-darwin10-selfhost-rel",
+ 'slavenames' : ["dunbar-darwin10"],
+ 'builddir' : "clang-x86_64-darwin10-selfhost-rel",
+ 'factory' : ClangBuilder.getClangBuildFactory(triple='x86_64-apple-darwin10',
+                                               useTwoStage=True,
+                                               stage1_config='Release+Asserts',
+                                               stage2_config='Release+Asserts'),
+ 'category' : 'clang.exp' },
+{'name'      : "llvm-gcc-mingw32-cross-arm-linux-gnueabi-hard-float",
+ 'slavenames': [ "kistanova5" ],
+ 'builddir'  : "llvm-gcc-mingw32-cross-arm-linux-gnueabi-hard-float",
+ 'factory'   : ScriptedBuilder.getScriptedBuildFactory(
+               source_code  = [SVN(name='svn-llvm',
+                                   mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm/',
+                                   defaultBranch='trunk',
+                                   workdir="llvm.src"),
+                               SVN(name='svn-llvm-gcc',
+                                   mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm-gcc-4.2/',
+                                   defaultBranch='trunk',
+                                   workdir="llvm-gcc.src"),],
+               launcher     = 'llvm-gcc.src/extras/buildbot-launcher',
+               build_script = 'llvm-gcc.src/extras/llvm-gcc-mingw32-cross-arm-linux-gnueabi-hard-float',
+               extra_args   = [],
+               build_steps  = [{'name'          : 'clean',
+                                'description'   : 'clean',
+                                'haltOnFailure' : True },
+                               {'name'          : 'copy_cross_tools',
+                                'description'   : 'copy cross-tools',
+                                'haltOnFailure' : True },
+                               {'name'          : 'configure_llvm',
+                                'description'   : 'configure llvm',
+                                'haltOnFailure' : True },
+                               {'name'          : 'make_llvm',
+                                'description'   : 'make llvm',
+                                'haltOnFailure' : True },
+                               {'name'          : 'configure_llvmgcc',
+                                'description'   : 'configure llvm-gcc',
+                                'haltOnFailure' : True },
+                               {'name'          : 'make_llvmgcc',
+                                'description'   : 'make llvm-gcc',
+                                'haltOnFailure' : True },
+                               {'name'          : 'install_llvmgcc',
+                                'description'   : 'install llvm-gcc',
+                                'haltOnFailure' : True },]),
+ 'category'  : 'llvm-gcc' },
+#{'name' : "clang-i686-xp-msvc9_alt",
+# 'slavenames' :['adobe1'],
+# 'builddir' :"clang-i686-xp-msvc9_alt",
+# 'factory' : ClangBuilder.getClangMSVCBuildFactory(jobs=2),
+# 'category' : 'clang.exp' },

Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=143081&r1=143080&r2=143081&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Wed Oct 26 18:55:10 2011
@@ -13,27 +13,6 @@
         # FreeBSD zero.sajd.net 9.0-CURRENT i386
         create_slave("freebsd1", properties={'jobs' : 1}, max_builds=1),
 
-        # PowerPC Linux machine. 900MHz G3 processor with 256MB of RAM.
-        create_slave("nick1", properties={'jobs' : 1}, max_builds=1),
-
-        # Linux, Beagleboard, Cortex A8, 256MB RAM.
-        create_slave("nick2", properties={'jobs' : 1}, max_builds=1),
-
-        # Linux, NVidia Tegra 250, Dual-core Cortex A9, 1GB RAM
-        create_slave("nick3", properties={'jobs' : 2}, max_builds=1),
-
-        # Core 2 Duo running Ubuntu.
-        create_slave("dunbar1", properties={'jobs' : 2}, max_builds=1),
-
-        # Athlon 1.2 XP SP 3.
-        create_slave("dunbar-win32", properties={'jobs' : 1}, max_builds=1),
-
-        # Dual Quad Core Mc Pro (Nehalem) running SnowLeopard.
-        create_slave("dunbar-darwin10", properties={'jobs' : 4}, max_builds=2),
-
-        # Dual Core Pentium M, XP SP 3.
-        create_slave("dunbar-win32-2", properties={'jobs' : 2}, max_builds=1),
-
         # CPU Marvell Kirkwood 88F6281 ARM Based armv5tejl running at 1.2Ghz
         # Memory 512MB SDRAM
         # Power 2.3w idle no attached devices, 7.0w running at 100% CPU utilization
@@ -65,13 +44,6 @@
         # Windows 7 Ultimate
         create_slave("kistanova8", properties={'jobs' : 1}, max_builds=1),
 
-        # Quad Core x86_64, Solaris / AurorAUX
-        create_slave("evocallaghan", properties={'jobs' : 4}, max_builds=1),
-
-        # Adobe Contributed VM
-        # Win XP SP2, Intel Core2 Duo 2.99GHz -E6850, 2.93 GB
-        create_slave("adobe1", properties={'jobs' : 2}, max_builds=1),
-
         # GCC Compile Farm Slaves, see http://gcc.gnu.org/wiki/CompileFarm
 
         # gcc10  2TB   2x12x1.5 GHz AMD Opteron Magny-Cours / 64 GB RAM / Supermicro AS-1022G-BTF / Debian x86-64
@@ -160,9 +132,6 @@
         # Debian, P4 2.8GHz, 1GB mem
         create_slave("balint1", properties={'jobs' : 1}, max_builds=1),
 
-        # Pentium Dual CPU T3400 @ 2.1GHz
-        create_slave("dumitrescu1", properties={'jobs' : 2}, max_builds=1),
-
         # AMD Athlon(tm) 64 X2 Dual Core 3800+, Ubuntu x86_64
         create_slave("grosser1", properties={'jobs': 2}, max_builds=1),
 
@@ -173,6 +142,32 @@
         create_slave("arxan_bellini", properties={'jobs': 2}, max_builds=1),
 
         # Defunct.
+        # Pentium Dual CPU T3400 @ 2.1GHz
+        #create_slave("dumitrescu1", properties={'jobs' : 2}, max_builds=1),
+        # Quad Core x86_64, Solaris / AurorAUX
+        #create_slave("evocallaghan", properties={'jobs' : 4}, max_builds=1),
+        # Adobe Contributed VM
+        # Win XP SP2, Intel Core2 Duo 2.99GHz -E6850, 2.93 GB
+        #create_slave("adobe1", properties={'jobs' : 2}, max_builds=1),
+        # PowerPC Linux machine. 900MHz G3 processor with 256MB of RAM.
+        #create_slave("nick1", properties={'jobs' : 1}, max_builds=1),
+        # Linux, Beagleboard, Cortex A8, 256MB RAM.
+        #create_slave("nick2", properties={'jobs' : 1}, max_builds=1),
+        # Linux, NVidia Tegra 250, Dual-core Cortex A9, 1GB RAM
+        #create_slave("nick3", properties={'jobs' : 2}, max_builds=1),
+        # Core 2 Duo running Ubuntu.
+        #create_slave("dunbar1", properties={'jobs' : 2}, max_builds=1),
+        # Athlon 1.2 XP SP 3.
+        #create_slave("dunbar-win32", properties={'jobs' : 1}, max_builds=1),
+        # Dual Quad Core Mc Pro (Nehalem) running SnowLeopard.
+        #create_slave("dunbar-darwin10", properties={'jobs' : 4}, max_builds=2),
+        # Dual Core Pentium M, XP SP 3.
+        #create_slave("dunbar-win32-2", properties={'jobs' : 2}, max_builds=1),
+        #create_slave("osu1", properties={'jobs' : 4}, max_builds=1),
+        #create_slave("osu2", properties={'jobs' : 4}, max_builds=2),
+        # Debian x86_64, 2 x 6-core Opteron 2.6 GHz
+        #create_slave("osu7", properties={'jobs' : 6}, max_builds=4),
+        #create_slave("osu8", properties={'jobs' : 6}, max_builds=4),
         #create_slave("andrew1"),
         #create_slave("danmbp1"),
         ]

Modified: zorg/trunk/buildbot/osuosl/master/config/status.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/status.py?rev=143081&r1=143080&r2=143081&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/status.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/status.py Wed Oct 26 18:55:10 2011
@@ -33,20 +33,20 @@
     return [
         buildbot.status.html.WebStatus(
             http_port = 8011, authz=authz_cfg),
-#        buildbot.status.mail.MailNotifier(
-#            fromaddr = "buildbot at lab.llvm.org",
-#            extraRecipients = [default_email],
-#            lookup = ConfigEmailLookup(os.path.join(os.path.dirname(__file__),
-#                                                    "llvmauthors.cfg"),
-#                                       default_email),
-#            mode = "problem",
-#            builders = standard_builders),
+        buildbot.status.mail.MailNotifier(
+            fromaddr = "llvm.buildmaster at lab.llvm.org",
+            extraRecipients = [default_email],
+            lookup = ConfigEmailLookup(os.path.join(os.path.dirname(__file__),
+                                                    "llvmauthors.cfg"),
+                                       default_email),
+            mode = "problem",
+            builders = standard_builders),
         buildbot.status.words.IRC(
             host = "irc.oftc.net", nick = "llvmbb", channels = ["#llvm"],
             allowForce = True,
             notify_events = ['successToFailure', 'failureToSuccess']),
         InformativeMailNotifier(
-            fromaddr = "buildbot at lab.llvm.org",
+            fromaddr = "llvm.buildmaster at lab.llvm.org",
             sendToInterestedUsers= False,
             extraRecipients = ["baldrick at free.fr", "gkistanova at gmail.com"],
             subject="Build %(builder)s Failure",
@@ -55,7 +55,7 @@
             addLogs=False,
             num_lines = 15),
         InformativeMailNotifier(
-            fromaddr = "buildbot at lab.llvm.org",
+            fromaddr = "llvm.buildmaster at lab.llvm.org",
             sendToInterestedUsers= False,
             extraRecipients = ["tobias at grosser.es"],
             subject="Build %(builder)s Failure",



From echristo at apple.com  Thu Oct 27 01:14:23 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 26 Oct 2011 23:14:23 -0700
Subject: [llvm-commits] patch: pick direct or indirect strings in DWARF
In-Reply-To: <CADbEz-gDnE1W1A4k2=HOUj1cEPdCRgwgFFOu296Kz4HKc2NrZQ@mail.gmail.com>
References: <CADbEz-jaVTjVkBLoFU0rvU7Vc83_T0vHWeqS21QLMy=WOQmM6w@mail.gmail.com>
	<4EA66F4A.4070901@mxc.ca>
	<CADbEz-gDnE1W1A4k2=HOUj1cEPdCRgwgFFOu296Kz4HKc2NrZQ@mail.gmail.com>
Message-ID: <DFE80485-2F80-4A3B-AF42-F3215BFF45C7@apple.com>


On Oct 26, 2011, at 5:37 PM, Nick Lewycky wrote:

> New patch! Updates tests and adds new test. Tested on Linux and Darwin.
> 
> The previous patch looked like it worked on linux but didn't (readelf -w on the .o file was fine, but it didn't have relocations so after linking the debug info in the result was wrong). Darwin needs to not have relocations for its string pool entries, while linux needs to have them.
> 
> Please review!

Looks good. As we chatted about on IRC I don't know that the size savings is worth having to worry about str vs strp for lookup so if you could just make it do strp that'd be awesome.

Thanks for this! It looks great!

-eric


From baldrick at free.fr  Thu Oct 27 01:22:39 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 27 Oct 2011 08:22:39 +0200
Subject: [llvm-commits] [PATCH] Lazily Link functions
In-Reply-To: <4CDF3ACC-822A-42D5-AA8C-5DA4758ED516@apple.com>
References: <F9BF4DF3-6A0B-45B2-8B47-5E9AA8AF64F2@apple.com>	<20111026234701.GA17710@pcc.me.uk>
	<4CDF3ACC-822A-42D5-AA8C-5DA4758ED516@apple.com>
Message-ID: <4EA8F8AF.7020908@free.fr>

Hi Tanya,

> Hmm.. if I am understanding all these different linkage types correctly,

yeah, there are so many and often obscure - I'm not sure they are even all used
in practice...

  then I don't think it should be a problem to change this to:
> if (SF->hasLocalLinkage() || SF->hasLinkOnceLinkage() || SF.hashasAvailableExternallyLinkage())

how about introducing a helper function in GlobalValue for testing this, eg:
"notNeededIfUnusedLinkage", and use this in both places?

Ciao, Duncan.

From nicholas at mxc.ca  Thu Oct 27 01:44:11 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 27 Oct 2011 06:44:11 -0000
Subject: [llvm-commits] [llvm] r143097 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/MC/ lib/CodeGen/AsmPrinter/ lib/MC/
 test/CodeGen/ARM/ test/CodeGen/X86/ test/DebugInfo/
Message-ID: <20111027064411.6F491312800A@llvm.org>

Author: nicholas
Date: Thu Oct 27 01:44:11 2011
New Revision: 143097

URL: http://llvm.org/viewvc/llvm-project?rev=143097&view=rev
Log:
Teach our Dwarf emission to use the string pool.

Added:
    llvm/trunk/test/DebugInfo/stringpool.ll
Modified:
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/include/llvm/MC/MCAsmInfo.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
    llvm/trunk/lib/MC/MCAsmInfo.cpp
    llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
    llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll
    llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll
    llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Thu Oct 27 01:44:11 2011
@@ -194,6 +194,11 @@
 
     bool needsSEHMoves();
 
+    /// needsRelocationsForDwarfStringPool - Specifies whether the object format
+    /// expects to use relocations to refer to debug entries. Alternatively we
+    /// emit section offsets in bytes from the start of the string pool.
+    bool needsRelocationsForDwarfStringPool() const;
+
     /// EmitConstantPool - Print to the current output stream assembly
     /// representations of the constants in the constant pool MCP. This is
     /// used to print out constants which have been "spilled to memory" by

Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Thu Oct 27 01:44:11 2011
@@ -330,6 +330,10 @@
     /// use EmitLabelOffsetDifference.
     bool DwarfUsesLabelOffsetForRanges;
 
+    /// DwarfUsesRelocationsForStringPool - True if this Dwarf output must use
+    /// relocations to refer to entries in the string pool.
+    bool DwarfUsesRelocationsForStringPool;
+
     /// DwarfRegNumForCFI - True if dwarf register numbers are printed
     /// instead of symbolic register names in .cfi_* directives.
     bool DwarfRegNumForCFI;  // Defaults to false;
@@ -566,6 +570,9 @@
     bool doesDwarfUsesLabelOffsetForRanges() const {
       return DwarfUsesLabelOffsetForRanges;
     }
+    bool doesDwarfUseRelocationsForStringPool() const {
+      return DwarfUsesRelocationsForStringPool;
+    }
     bool useDwarfRegNumForCFI() const {
       return DwarfRegNumForCFI;
     }

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Oct 27 01:44:11 2011
@@ -613,6 +613,10 @@
     MF->getFunction()->needsUnwindTableEntry();
 }
 
+bool AsmPrinter::needsRelocationsForDwarfStringPool() const {
+  return MAI->doesDwarfUseRelocationsForStringPool();
+}
+
 void AsmPrinter::emitPrologLabel(const MachineInstr &MI) {
   MCSymbol *Label = MI.getOperand(0).getMCSymbol();
 
@@ -2092,4 +2096,3 @@
   report_fatal_error("no GCMetadataPrinter registered for GC: " + Twine(Name));
   return 0;
 }
-

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp Thu Oct 27 01:44:11 2011
@@ -267,6 +267,7 @@
 ///
 unsigned DIELabel::SizeOf(AsmPrinter *AP, unsigned Form) const {
   if (Form == dwarf::DW_FORM_data4) return 4;
+  if (Form == dwarf::DW_FORM_strp) return 4;
   return AP->getTargetData().getPointerSize();
 }
 
@@ -290,6 +291,7 @@
 ///
 unsigned DIEDelta::SizeOf(AsmPrinter *AP, unsigned Form) const {
   if (Form == dwarf::DW_FORM_data4) return 4;
+  if (Form == dwarf::DW_FORM_strp) return 4;
   return AP->getTargetData().getPointerSize();
 }
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Thu Oct 27 01:44:11 2011
@@ -69,10 +69,21 @@
 
 /// addString - Add a string attribute data and value. DIEString only
 /// keeps string reference.
-void CompileUnit::addString(DIE *Die, unsigned Attribute, unsigned Form,
-                            StringRef String) {
-  DIEValue *Value = new (DIEValueAllocator) DIEString(String);
-  Die->addValue(Attribute, Form, Value);
+void CompileUnit::addString(DIE *Die, unsigned Attribute, StringRef String) {
+  if (String.size() > 3) {
+    MCSymbol *Symb = DD->getStringPoolEntry(String);
+    DIEValue *Value;
+    if (Asm->needsRelocationsForDwarfStringPool())
+      Value = new (DIEValueAllocator) DIELabel(Symb);
+    else {
+      MCSymbol *StringPool = DD->getStringPool();
+      Value = new (DIEValueAllocator) DIEDelta(Symb, StringPool);
+    }
+    Die->addValue(Attribute, dwarf::DW_FORM_strp, Value);
+  } else {
+    DIEValue *Value = new (DIEValueAllocator) DIEString(String);
+    Die->addValue(Attribute, dwarf::DW_FORM_string, Value);
+  }
 }
 
 /// addLabel - Add a Dwarf label attribute data and value.
@@ -479,7 +490,7 @@
 
 /// addConstantFPValue - Add constant value entry in variable DIE.
 bool CompileUnit::addConstantFPValue(DIE *Die, const MachineOperand &MO) {
-  assert(MO.isFPImm() && "Invalid machine operand!");
+  assert (MO.isFPImm() && "Invalid machine operand!");
   DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
   APFloat FPImm = MO.getFPImm()->getValueAPF();
 
@@ -660,7 +671,7 @@
   StringRef Name = BTy.getName();
   // Add name if not anonymous or intermediate type.
   if (!Name.empty())
-    addString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
+    addString(&Buffer, dwarf::DW_AT_name, Name);
 
   if (BTy.getTag() == dwarf::DW_TAG_unspecified_type) {
     Buffer.setTag(dwarf::DW_TAG_unspecified_type);
@@ -694,7 +705,7 @@
 
   // Add name if not anonymous or intermediate type.
   if (!Name.empty())
-    addString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
+    addString(&Buffer, dwarf::DW_AT_name, Name);
 
   // Add size if non-zero (derived types might be zero-sized.)
   if (Size)
@@ -791,8 +802,7 @@
       else if (Element.isVariable()) {
         DIVariable DV(Element);
         ElemDie = new DIE(dwarf::DW_TAG_variable);
-        addString(ElemDie, dwarf::DW_AT_name, dwarf::DW_FORM_string,
-                  DV.getName());
+        addString(ElemDie, dwarf::DW_AT_name, DV.getName());
         addType(ElemDie, DV.getType());
         addUInt(ElemDie, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag, 1);
         addUInt(ElemDie, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1);
@@ -836,7 +846,7 @@
 
   // Add name if not anonymous or intermediate type.
   if (!Name.empty())
-    addString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
+    addString(&Buffer, dwarf::DW_AT_name, Name);
 
   if (Tag == dwarf::DW_TAG_enumeration_type || Tag == dwarf::DW_TAG_class_type
       || Tag == dwarf::DW_TAG_structure_type || Tag == dwarf::DW_TAG_union_type)
@@ -868,7 +878,7 @@
 
   ParamDIE = new DIE(dwarf::DW_TAG_template_type_parameter);
   addType(ParamDIE, TP.getType());
-  addString(ParamDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string, TP.getName());
+  addString(ParamDIE, dwarf::DW_AT_name, TP.getName());
   return ParamDIE;
 }
 
@@ -883,7 +893,7 @@
   ParamDIE = new DIE(dwarf::DW_TAG_template_value_parameter);
   addType(ParamDIE, TPV.getType());
   if (!TPV.getName().empty())
-    addString(ParamDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string, TPV.getName());
+    addString(ParamDIE, dwarf::DW_AT_name, TPV.getName());
   addUInt(ParamDIE, dwarf::DW_AT_const_value, dwarf::DW_FORM_udata, 
           TPV.getValue());
   return ParamDIE;
@@ -897,7 +907,7 @@
   NDie = new DIE(dwarf::DW_TAG_namespace);
   insertDIE(NS, NDie);
   if (!NS.getName().empty())
-    addString(NDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, NS.getName());
+    addString(NDie, dwarf::DW_AT_name, NS.getName());
   addSourceLine(NDie, NS);
   addToContextOwner(NDie, NS.getContext());
   return NDie;
@@ -932,7 +942,7 @@
 
   StringRef LinkageName = SP.getLinkageName();
   if (!LinkageName.empty())
-    addString(SPDie, dwarf::DW_AT_MIPS_linkage_name, dwarf::DW_FORM_string,
+    addString(SPDie, dwarf::DW_AT_MIPS_linkage_name,
               getRealLinkageName(LinkageName));
 
   // If this DIE is going to refer declaration info using AT_specification
@@ -942,7 +952,7 @@
 
   // Constructors and operators for anonymous aggregates do not have names.
   if (!SP.getName().empty())
-    addString(SPDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, SP.getName());
+    addString(SPDie, dwarf::DW_AT_name, SP.getName());
 
   addSourceLine(SPDie, SP);
 
@@ -1048,13 +1058,12 @@
   insertDIE(N, VariableDIE);
 
   // Add name.
-  addString(VariableDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string,
-            GV.getDisplayName());
+  addString(VariableDIE, dwarf::DW_AT_name, GV.getDisplayName());
   StringRef LinkageName = GV.getLinkageName();
   bool isGlobalVariable = GV.getGlobal() != NULL;
   if (!LinkageName.empty() && isGlobalVariable)
     addString(VariableDIE, dwarf::DW_AT_MIPS_linkage_name,
-              dwarf::DW_FORM_string, getRealLinkageName(LinkageName));
+              getRealLinkageName(LinkageName));
   // Add type.
   DIType GTy = GV.getType();
   addType(VariableDIE, GTy);
@@ -1170,7 +1179,7 @@
 DIE *CompileUnit::constructEnumTypeDIE(DIEnumerator ETy) {
   DIE *Enumerator = new DIE(dwarf::DW_TAG_enumerator);
   StringRef Name = ETy.getName();
-  addString(Enumerator, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
+  addString(Enumerator, dwarf::DW_AT_name, Name);
   int64_t Value = ETy.getEnumValue();
   addSInt(Enumerator, dwarf::DW_AT_const_value, dwarf::DW_FORM_sdata, Value);
   return Enumerator;
@@ -1207,8 +1216,7 @@
     addDIEEntry(VariableDie, dwarf::DW_AT_abstract_origin,
                             dwarf::DW_FORM_ref4, AbsDIE);
   else {
-    addString(VariableDie, dwarf::DW_AT_name, 
-                          dwarf::DW_FORM_string, Name);
+    addString(VariableDie, dwarf::DW_AT_name, Name);
     addSourceLine(VariableDie, DV->getVariable());
     addType(VariableDie, DV->getType());
   }
@@ -1303,7 +1311,7 @@
   DIE *MemberDie = new DIE(DT.getTag());
   StringRef Name = DT.getName();
   if (!Name.empty())
-    addString(MemberDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
+    addString(MemberDie, dwarf::DW_AT_name, Name);
 
   addType(MemberDie, DT.getTypeDerivedFrom());
 
@@ -1377,16 +1385,13 @@
   // Objective-C properties.
   StringRef PropertyName = DT.getObjCPropertyName();
   if (!PropertyName.empty()) {
-    addString(MemberDie, dwarf::DW_AT_APPLE_property_name, dwarf::DW_FORM_string,
-              PropertyName);
+    addString(MemberDie, dwarf::DW_AT_APPLE_property_name, PropertyName);
     StringRef GetterName = DT.getObjCPropertyGetterName();
     if (!GetterName.empty())
-      addString(MemberDie, dwarf::DW_AT_APPLE_property_getter,
-                dwarf::DW_FORM_string, GetterName);
+      addString(MemberDie, dwarf::DW_AT_APPLE_property_getter, GetterName);
     StringRef SetterName = DT.getObjCPropertySetterName();
     if (!SetterName.empty())
-      addString(MemberDie, dwarf::DW_AT_APPLE_property_setter,
-                dwarf::DW_FORM_string, SetterName);
+      addString(MemberDie, dwarf::DW_AT_APPLE_property_setter, SetterName);
     unsigned PropertyAttributes = 0;
     if (DT.isReadOnlyObjCProperty())
       PropertyAttributes |= dwarf::DW_APPLE_PROPERTY_readonly;

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Thu Oct 27 01:44:11 2011
@@ -150,8 +150,7 @@
 
   /// addString - Add a string attribute data and value.
   ///
-  void addString(DIE *Die, unsigned Attribute, unsigned Form,
-                 const StringRef Str);
+  void addString(DIE *Die, unsigned Attribute, const StringRef Str);
 
   /// addLabel - Add a Dwarf label attribute data and value.
   ///

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Oct 27 01:44:11 2011
@@ -136,6 +136,10 @@
 DwarfDebug::~DwarfDebug() {
 }
 
+MCSymbol *DwarfDebug::getStringPool() {
+  return Asm->GetTempSymbol("section_str");
+}
+
 MCSymbol *DwarfDebug::getStringPoolEntry(StringRef Str) {
   std::pair<MCSymbol*, unsigned> &Entry = StringPool[Str];
   if (Entry.first) return Entry.first;
@@ -467,11 +471,10 @@
 
   DIE *Die = new DIE(dwarf::DW_TAG_compile_unit);
   CompileUnit *NewCU = new CompileUnit(ID, Die, Asm, this);
-  NewCU->addString(Die, dwarf::DW_AT_producer, dwarf::DW_FORM_string,
-                   DIUnit.getProducer());
+  NewCU->addString(Die, dwarf::DW_AT_producer, DIUnit.getProducer());
   NewCU->addUInt(Die, dwarf::DW_AT_language, dwarf::DW_FORM_data2,
                  DIUnit.getLanguage());
-  NewCU->addString(Die, dwarf::DW_AT_name, dwarf::DW_FORM_string, FN);
+  NewCU->addString(Die, dwarf::DW_AT_name, FN);
   // Use DW_AT_entry_pc instead of DW_AT_low_pc/DW_AT_high_pc pair. This
   // simplifies debug range entries.
   NewCU->addUInt(Die, dwarf::DW_AT_entry_pc, dwarf::DW_FORM_addr, 0);
@@ -484,14 +487,13 @@
     NewCU->addUInt(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, 0);
 
   if (!Dir.empty())
-    NewCU->addString(Die, dwarf::DW_AT_comp_dir, dwarf::DW_FORM_string, Dir);
+    NewCU->addString(Die, dwarf::DW_AT_comp_dir, Dir);
   if (DIUnit.isOptimized())
     NewCU->addUInt(Die, dwarf::DW_AT_APPLE_optimized, dwarf::DW_FORM_flag, 1);
 
   StringRef Flags = DIUnit.getFlags();
   if (!Flags.empty())
-    NewCU->addString(Die, dwarf::DW_AT_APPLE_flags, dwarf::DW_FORM_string, 
-                     Flags);
+    NewCU->addString(Die, dwarf::DW_AT_APPLE_flags, Flags);
   
   if (unsigned RVer = DIUnit.getRunTimeVersion())
     NewCU->addUInt(Die, dwarf::DW_AT_APPLE_major_runtime_vers,
@@ -1796,6 +1798,7 @@
 
     // Emit the string itself.
     Asm->OutStreamer.EmitBytes(Entries[i].second->getKey(), 0/*addrspace*/);
+    Asm->OutStreamer.EmitZeros(1, 0);
   }
 }
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Thu Oct 27 01:44:11 2011
@@ -216,8 +216,6 @@
   StringMap<std::pair<MCSymbol*, unsigned> > StringPool;
   unsigned NextStringPoolNumber;
   
-  MCSymbol *getStringPoolEntry(StringRef Str);
-
   /// SectionMap - Provides a unique id per text section.
   ///
   UniqueVector<const MCSection*> SectionMap;
@@ -504,6 +502,13 @@
 
   /// createSubprogramDIE - Create new DIE using SP.
   DIE *createSubprogramDIE(DISubprogram SP);
+
+  /// getStringPool - returns the entry into the start of the pool.
+  MCSymbol *getStringPool();
+
+  /// getStringPoolEntry - returns an entry into the string pool with the given
+  /// string text.
+  MCSymbol *getStringPoolEntry(StringRef Str);
 };
 } // End of namespace llvm
 

Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmInfo.cpp Thu Oct 27 01:44:11 2011
@@ -91,6 +91,7 @@
   DwarfRequiresRelocationForSectionOffset = true;
   DwarfSectionOffsetDirective = 0;
   DwarfUsesLabelOffsetForRanges = true;
+  DwarfUsesRelocationsForStringPool = true;
   DwarfRegNumForCFI = false;
   HasMicrosoftFastStdCallMangling = false;
 

Modified: llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Thu Oct 27 01:44:11 2011
@@ -66,4 +66,5 @@
 
   DwarfRequiresRelocationForSectionOffset = false;
   DwarfUsesLabelOffsetForRanges = false;
+  DwarfUsesRelocationsForStringPool = false;
 }

Modified: llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll Thu Oct 27 01:44:11 2011
@@ -6,8 +6,8 @@
 ;CHECK: Ldebug_loc0:
 ;CHECK-NEXT:        .long   Ltmp1
 ;CHECK-NEXT:        .long   Ltmp2
-;CHECK-NEXT: Lset8 = Ltmp10-Ltmp9                    @ Loc expr size
-;CHECK-NEXT:        .short  Lset8
+;CHECK-NEXT: Lset[[N:[0-9]+]] = Ltmp10-Ltmp9        @ Loc expr size
+;CHECK-NEXT:        .short  Lset[[N]]
 ;CHECK-NEXT: Ltmp9:
 ;CHECK-NEXT:        .byte   144                     @ DW_OP_regx for S register
 

Modified: llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll Thu Oct 27 01:44:11 2011
@@ -5,17 +5,17 @@
 ; CHECK:	.byte	17                      ## DW_TAG_compile_unit
 ; CHECK-NEXT:	.byte	1                       ## DW_CHILDREN_yes
 ; CHECK-NEXT:	.byte	37                      ## DW_AT_producer
-; CHECK-NEXT:	.byte	8                       ## DW_FORM_string
+; CHECK-NEXT:	.byte	14                      ## DW_FORM_strp
 ; CHECK-NEXT:	.byte	19                      ## DW_AT_language
 ; CHECK-NEXT:	.byte	5                       ## DW_FORM_data2
 ; CHECK-NEXT:	.byte	3                       ## DW_AT_name
-; CHECK-NEXT:	.byte	8                       ## DW_FORM_string
+; CHECK-NEXT:	.byte	14                      ## DW_FORM_strp
 ; CHECK-NEXT:	.byte	82                      ## DW_AT_entry_pc
 ; CHECK-NEXT:	.byte	1                       ## DW_FORM_addr
 ; CHECK-NEXT:	.byte	16                      ## DW_AT_stmt_list
 ; CHECK-NEXT:	.byte	6                       ## DW_FORM_data4
 ; CHECK-NEXT:	.byte	27                      ## DW_AT_comp_dir
-; CHECK-NEXT:	.byte	8                       ## DW_FORM_string
+; CHECK-NEXT:	.byte	14                      ## DW_FORM_strp
 ; CHECK-NEXT:	.byte	225                     ## DW_AT_APPLE_optimized
 
 %struct.a = type { i32, %struct.a* }

Modified: llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll?rev=143097&r1=143096&r2=143097&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll (original)
+++ llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll Thu Oct 27 01:44:11 2011
@@ -2,14 +2,14 @@
 
 ; ModuleID = 'test.c'
 
- at GLOBAL = common global i32 0, align 4
+ at GLB = common global i32 0, align 4
 
 define i32 @f() nounwind {
-  %LOCAL = alloca i32, align 4
-  call void @llvm.dbg.declare(metadata !{i32* %LOCAL}, metadata !15), !dbg !17
-  %1 = load i32* @GLOBAL, align 4, !dbg !18
-  store i32 %1, i32* %LOCAL, align 4, !dbg !18
-  %2 = load i32* @GLOBAL, align 4, !dbg !19
+  %LOC = alloca i32, align 4
+  call void @llvm.dbg.declare(metadata !{i32* %LOC}, metadata !15), !dbg !17
+  %1 = load i32* @GLB, align 4, !dbg !18
+  store i32 %1, i32* %LOC, align 4, !dbg !18
+  %2 = load i32* @GLB, align 4, !dbg !19
   ret i32 %2, !dbg !19
 }
 
@@ -31,17 +31,17 @@
 !11 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
 !12 = metadata !{metadata !13}
 !13 = metadata !{metadata !14}
-!14 = metadata !{i32 720948, i32 0, null, metadata !"GLOBAL", metadata !"GLOBAL", metadata !"", metadata !6, i32 1, metadata !9, i32 0, i32 1, i32* @GLOBAL} ; [ DW_TAG_variable ]
-!15 = metadata !{i32 721152, metadata !16, metadata !"LOCAL", metadata !6, i32 4, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
+!14 = metadata !{i32 720948, i32 0, null, metadata !"GLB", metadata !"GLB", metadata !"", metadata !6, i32 1, metadata !9, i32 0, i32 1, i32* @GLB} ; [ DW_TAG_variable ]
+!15 = metadata !{i32 721152, metadata !16, metadata !"LOC", metadata !6, i32 4, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
 !16 = metadata !{i32 720907, metadata !5, i32 3, i32 9, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
 !17 = metadata !{i32 4, i32 9, metadata !16, null}
 !18 = metadata !{i32 4, i32 23, metadata !16, null}
 !19 = metadata !{i32 5, i32 5, metadata !16, null}
 
-; CHECK: .ascii	 "GLOBAL"
+; CHECK: .ascii	 "GLB"
 ; CHECK: .byte	1
 ; CHECK: .byte	1
 
-; CHECK: .ascii	 "LOCAL"
+; CHECK: .ascii	 "LOC"
 ; CHECK: .byte	1
 ; CHECK: .byte	4

Added: llvm/trunk/test/DebugInfo/stringpool.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/stringpool.ll?rev=143097&view=auto
==============================================================================
--- llvm/trunk/test/DebugInfo/stringpool.ll (added)
+++ llvm/trunk/test/DebugInfo/stringpool.ll Thu Oct 27 01:44:11 2011
@@ -0,0 +1,54 @@
+; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=LINUX
+; RUN: llc -O0 -mtriple=x86_64-darwin < %s | FileCheck %s --check-prefix=DARWIN
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+ at x = common global i32 0, align 4
+ at yyyyyyyy = common global i32 0, align 4
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"hello.c", metadata !"/home/nlewycky", metadata !"clang version 3.1 (trunk 143048)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{metadata !2}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{metadata !5, metadata !8}
+!5 = metadata !{i32 720948, i32 0, null, metadata !"x", metadata !"x", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, i32* @x} ; [ DW_TAG_variable ]
+!6 = metadata !{i32 720937, metadata !"hello.c", metadata !"/home/nlewycky", null} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 720948, i32 0, null, metadata !"yyyyyyyy", metadata !"yyyyyyyy", metadata !"", metadata !6, i32 2, metadata !7, i32 0, i32 1, i32* @yyyyyyyy} ; [ DW_TAG_variable ]
+
+; 120 is ASCII 'x'. Verify that we use it directly as its name and don't emit
+; a reference to the string pool.
+; LINUX:        .byte   120                     # DW_AT_name
+; DARWIN:       .byte   120                     ## DW_AT_name
+
+; Verify that we refer to 'yyyyyyyy' with a relocation.
+; LINUX:      .long   .Lstring{{[0-9]+}}      # DW_AT_name
+; LINUX-NEXT: .long   39                      # DW_AT_type
+; LINUX-NEXT: .byte   1                       # DW_AT_external
+; LINUX-NEXT: .byte   1                       # DW_AT_decl_file
+; LINUX-NEXT: .byte   2                       # DW_AT_decl_line
+; LINUX-NEXT: .byte   9                       # DW_AT_location
+; LINUX-NEXT: .byte   3
+; LINUX-NEXT: .quad   yyyyyyyy
+
+; Verify that we refer to 'yyyyyyyy' without a relocation.
+; DARWIN: Lset[[N:[0-9]+]] = Lstring{{[0-9]+}}-Lsection_str   ## DW_AT_name
+; DARWIN-NEXT:        .long   Lset[[N]]
+; DARWIN-NEXT:        .long   39                      ## DW_AT_type
+; DARWIN-NEXT:        .byte   1                       ## DW_AT_external
+; DARWIN-NEXT:        .byte   1                       ## DW_AT_decl_file
+; DARWIN-NEXT:        .byte   2                       ## DW_AT_decl_line
+; DARWIN-NEXT:        .byte   9                       ## DW_AT_location
+; DARWIN-NEXT:        .byte   3
+; DARWIN-NEXT:        .quad   _yyyyyyyy
+
+
+; Verify that "yyyyyyyy" ended up in the stringpool.
+; LINUX: .section .debug_str,"MS", at progbits,1
+; LINUX-NOT: .section
+; LINUX: yyyyyyyy
+; DARWIN: .section __DWARF,__debug_str,regular,debug
+; DARWIN-NOT: .section
+; DARWIN: yyyyyyyy



From nicholas at mxc.ca  Thu Oct 27 02:49:25 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 27 Oct 2011 00:49:25 -0700
Subject: [llvm-commits] patch: pick direct or indirect strings in DWARF
In-Reply-To: <DFE80485-2F80-4A3B-AF42-F3215BFF45C7@apple.com>
References: <CADbEz-jaVTjVkBLoFU0rvU7Vc83_T0vHWeqS21QLMy=WOQmM6w@mail.gmail.com>	<4EA66F4A.4070901@mxc.ca>	<CADbEz-gDnE1W1A4k2=HOUj1cEPdCRgwgFFOu296Kz4HKc2NrZQ@mail.gmail.com>
	<DFE80485-2F80-4A3B-AF42-F3215BFF45C7@apple.com>
Message-ID: <4EA90D05.7000806@mxc.ca>

Eric Christopher wrote:
>
> On Oct 26, 2011, at 5:37 PM, Nick Lewycky wrote:
>
>> New patch! Updates tests and adds new test. Tested on Linux and Darwin.
>>
>> The previous patch looked like it worked on linux but didn't (readelf -w on the .o file was fine, but it didn't have relocations so after linking the debug info in the result was wrong). Darwin needs to not have relocations for its string pool entries, while linux needs to have them.
>>
>> Please review!
>
> Looks good. As we chatted about on IRC I don't know that the size savings is worth having to worry about str vs strp for lookup so if you could just make it do strp that'd be awesome.
>
> Thanks for this! It looks great!

Thanks for the speedy review! Committed in r143097.

As we discussed over IRC, I submitted as-is and will look into changing 
it to always use strp.

Nick

From benny.kra at googlemail.com  Thu Oct 27 09:08:01 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 27 Oct 2011 14:08:01 -0000
Subject: [llvm-commits] [llvm] r143101 -
	/llvm/trunk/lib/AsmParser/LLLexer.cpp
Message-ID: <20111027140801.96B233128060@llvm.org>

Author: d0k
Date: Thu Oct 27 09:08:01 2011
New Revision: 143101

URL: http://llvm.org/viewvc/llvm-project?rev=143101&view=rev
Log:
LLLexer: Factor hex char parsing.

Modified:
    llvm/trunk/lib/AsmParser/LLLexer.cpp

Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=143101&r1=143100&r2=143101&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Thu Oct 27 09:08:01 2011
@@ -55,18 +55,22 @@
   return Result;
 }
 
+static char parseHexChar(char C) {
+  if (C >= '0' && C <= '9')
+    return C-'0';
+  if (C >= 'A' && C <= 'F')
+    return C-'A'+10;
+  if (C >= 'a' && C <= 'f')
+    return C-'a'+10;
+  return 0;
+}
+
 uint64_t LLLexer::HexIntToVal(const char *Buffer, const char *End) {
   uint64_t Result = 0;
   for (; Buffer != End; ++Buffer) {
     uint64_t OldRes = Result;
     Result *= 16;
-    char C = *Buffer;
-    if (C >= '0' && C <= '9')
-      Result += C-'0';
-    else if (C >= 'A' && C <= 'F')
-      Result += C-'A'+10;
-    else if (C >= 'a' && C <= 'f')
-      Result += C-'a'+10;
+    Result += parseHexChar(*Buffer);
 
     if (Result < OldRes) {   // Uh, oh, overflow detected!!!
       Error("constant bigger than 64 bits detected!");
@@ -82,24 +86,12 @@
   for (int i=0; i<16; i++, Buffer++) {
     assert(Buffer != End);
     Pair[0] *= 16;
-    char C = *Buffer;
-    if (C >= '0' && C <= '9')
-      Pair[0] += C-'0';
-    else if (C >= 'A' && C <= 'F')
-      Pair[0] += C-'A'+10;
-    else if (C >= 'a' && C <= 'f')
-      Pair[0] += C-'a'+10;
+    Pair[0] += parseHexChar(*Buffer);
   }
   Pair[1] = 0;
   for (int i=0; i<16 && Buffer != End; i++, Buffer++) {
     Pair[1] *= 16;
-    char C = *Buffer;
-    if (C >= '0' && C <= '9')
-      Pair[1] += C-'0';
-    else if (C >= 'A' && C <= 'F')
-      Pair[1] += C-'A'+10;
-    else if (C >= 'a' && C <= 'f')
-      Pair[1] += C-'a'+10;
+    Pair[1] += parseHexChar(*Buffer);
   }
   if (Buffer != End)
     Error("constant bigger than 128 bits detected!");
@@ -113,24 +105,12 @@
   for (int i=0; i<4 && Buffer != End; i++, Buffer++) {
     assert(Buffer != End);
     Pair[1] *= 16;
-    char C = *Buffer;
-    if (C >= '0' && C <= '9')
-      Pair[1] += C-'0';
-    else if (C >= 'A' && C <= 'F')
-      Pair[1] += C-'A'+10;
-    else if (C >= 'a' && C <= 'f')
-      Pair[1] += C-'a'+10;
+    Pair[1] += parseHexChar(*Buffer);
   }
   Pair[0] = 0;
   for (int i=0; i<16; i++, Buffer++) {
     Pair[0] *= 16;
-    char C = *Buffer;
-    if (C >= '0' && C <= '9')
-      Pair[0] += C-'0';
-    else if (C >= 'A' && C <= 'F')
-      Pair[0] += C-'A'+10;
-    else if (C >= 'a' && C <= 'f')
-      Pair[0] += C-'a'+10;
+    Pair[0] += parseHexChar(*Buffer);
   }
   if (Buffer != End)
     Error("constant bigger than 128 bits detected!");
@@ -149,9 +129,7 @@
         *BOut++ = '\\'; // Two \ becomes one
         BIn += 2;
       } else if (BIn < EndBuffer-2 && isxdigit(BIn[1]) && isxdigit(BIn[2])) {
-        char Tmp = BIn[3]; BIn[3] = 0;      // Terminate string
-        *BOut = (char)strtol(BIn+1, 0, 16); // Convert to number
-        BIn[3] = Tmp;                       // Restore character
+        *BOut = parseHexChar(BIn[1]) * 16 + parseHexChar(BIn[2]);
         BIn += 3;                           // Skip over handled chars
         ++BOut;
       } else {



From bob.wilson at apple.com  Thu Oct 27 10:46:47 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 27 Oct 2011 08:46:47 -0700
Subject: [llvm-commits] [llvm] r143028 - in /llvm/trunk:
 lib/Analysis/ValueTracking.cpp test/Transforms/InstSimplify/compare.ll
In-Reply-To: <20111026153151.C3D4E312800A@llvm.org>
References: <20111026153151.C3D4E312800A@llvm.org>
Message-ID: <CD8F2C13-7E90-4F21-83E5-092318BD235D@apple.com>

A bisection blamed this change for a regression in 483.xalancbmk: http://llvm.org/perf/db_default/simple/nts/347/
I'm going to revert this for now.

On Oct 26, 2011, at 8:31 AM, Duncan Sands wrote:

> Author: baldrick
> Date: Wed Oct 26 10:31:51 2011
> New Revision: 143028
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=143028&view=rev
> Log:
> My super-optimizer noticed that we weren't folding this expression to
> true: (x *nsw x) sgt 0, where x = (y | 1).  This occurs in 464.h264ref.
> 
> Modified:
>    llvm/trunk/lib/Analysis/ValueTracking.cpp
>    llvm/trunk/test/Transforms/InstSimplify/compare.ll
> 
> Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=143028&r1=143027&r2=143028&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
> +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Wed Oct 26 10:31:51 2011
> @@ -201,9 +201,36 @@
>     ComputeMaskedBits(I->getOperand(1), Mask2, KnownZero, KnownOne, TD,Depth+1);
>     ComputeMaskedBits(I->getOperand(0), Mask2, KnownZero2, KnownOne2, TD,
>                       Depth+1);
> -    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 
> -    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 
> -    
> +    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
> +    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
> +
> +    bool isKnownNegative = false;
> +    bool isKnownNonNegative = false;
> +    // If the multiplication is known not to overflow, compute the sign bit.
> +    if (Mask.isNegative() && cast<BinaryOperator>(I)->hasNoSignedWrap()) {
> +      Value *Op1 = I->getOperand(1), *Op2 = I->getOperand(0);
> +      if (Op1 == Op2) {
> +        // The product of a number with itself is non-negative.
> +        isKnownNonNegative = true;
> +      } else {
> +        bool isKnownNonNegative1 = KnownZero.isNegative();
> +        bool isKnownNonNegative2 = KnownZero2.isNegative();
> +        bool isKnownNegative1 = KnownOne.isNegative();
> +        bool isKnownNegative2 = KnownOne2.isNegative();
> +        // The product of two numbers with the same sign is non-negative.
> +        isKnownNonNegative = (isKnownNegative1 && isKnownNegative2) ||
> +          (isKnownNonNegative1 && isKnownNonNegative2);
> +        // The product of a negative number and a non-negative number is either
> +        // negative or zero.
> +        isKnownNegative = (isKnownNegative1 && isKnownNonNegative2 &&
> +                           isKnownNonZero(Op2, TD, Depth)) ||
> +                          (isKnownNegative2 && isKnownNonNegative1 &&
> +                           isKnownNonZero(Op1, TD, Depth));
> +        assert(!(isKnownNegative && isKnownNonNegative) &&
> +               "Sign bit both zero and one?");
> +      }
> +    }
> +
>     // If low bits are zero in either operand, output low known-0 bits.
>     // Also compute a conserative estimate for high known-0 bits.
>     // More trickiness is possible, but this is sufficient for the
> @@ -220,6 +247,12 @@
>     KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) |
>                 APInt::getHighBitsSet(BitWidth, LeadZ);
>     KnownZero &= Mask;
> +
> +    if (isKnownNonNegative)
> +      KnownZero.setBit(BitWidth - 1);
> +    else if (isKnownNegative)
> +      KnownOne.setBit(BitWidth - 1);
> +
>     return;
>   }
>   case Instruction::UDiv: {
> @@ -767,7 +800,7 @@
>   }
> 
>   // The remaining tests are all recursive, so bail out if we hit the limit.
> -  if (Depth++ == MaxDepth)
> +  if (Depth++ >= MaxDepth)
>     return false;
> 
>   unsigned BitWidth = getBitWidth(V->getType(), TD);
> @@ -851,6 +884,15 @@
>     if (YKnownNonNegative && isPowerOfTwo(X, TD, Depth))
>       return true;
>   }
> +  // X * Y.
> +  else if (match(V, m_Mul(m_Value(X), m_Value(Y)))) {
> +    BinaryOperator *BO = cast<BinaryOperator>(V);
> +    // If X and Y are non-zero then so is X * Y as long as the multiplication
> +    // does not overflow.
> +    if ((BO->hasNoSignedWrap() || BO->hasNoUnsignedWrap()) &&
> +        isKnownNonZero(X, TD, Depth) && isKnownNonZero(Y, TD, Depth))
> +      return true;
> +  }
>   // (C ? X : Y) != 0 if X != 0 and Y != 0.
>   else if (SelectInst *SI = dyn_cast<SelectInst>(V)) {
>     if (isKnownNonZero(SI->getTrueValue(), TD, Depth) &&
> 
> Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=143028&r1=143027&r2=143028&view=diff
> ==============================================================================
> --- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original)
> +++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Wed Oct 26 10:31:51 2011
> @@ -323,3 +323,34 @@
>   ret i1 %B
> ; CHECK: ret i1 false
> }
> +
> +define i1 @mul1(i32 %X) {
> +; CHECK: @mul1
> +; Square of a non-zero number is non-zero if there is no overflow.
> +  %Y = or i32 %X, 1
> +  %M = mul nuw i32 %Y, %Y
> +  %C = icmp eq i32 %M, 0
> +  ret i1 %C
> +; CHECK: ret i1 false
> +}
> +
> +define i1 @mul2(i32 %X) {
> +; CHECK: @mul2
> +; Square of a non-zero number is positive if there is no signed overflow.
> +  %Y = or i32 %X, 1
> +  %M = mul nsw i32 %Y, %Y
> +  %C = icmp sgt i32 %M, 0
> +  ret i1 %C
> +; CHECK: ret i1 true
> +}
> +
> +define i1 @mul3(i32 %X, i32 %Y) {
> +; CHECK: @mul3
> +; Product of non-negative numbers is non-negative if there is no signed overflow.
> +  %XX = mul nsw i32 %X, %X
> +  %YY = mul nsw i32 %Y, %Y
> +  %M = mul nsw i32 %XX, %YY
> +  %C = icmp sge i32 %M, 0
> +  ret i1 %C
> +; CHECK: ret i1 true
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From bob.wilson at apple.com  Thu Oct 27 10:47:25 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 27 Oct 2011 15:47:25 -0000
Subject: [llvm-commits] [llvm] r143102 - in /llvm/trunk:
 lib/Analysis/ValueTracking.cpp test/Transforms/InstSimplify/compare.ll
Message-ID: <20111027154725.4F8AC3128060@llvm.org>

Author: bwilson
Date: Thu Oct 27 10:47:25 2011
New Revision: 143102

URL: http://llvm.org/viewvc/llvm-project?rev=143102&view=rev
Log:
Revert Duncan's r143028 expression folding which appears to be the culprit
behind a compile failure on 483.xalancbmk.

Modified:
    llvm/trunk/lib/Analysis/ValueTracking.cpp
    llvm/trunk/test/Transforms/InstSimplify/compare.ll

Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=143102&r1=143101&r2=143102&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Thu Oct 27 10:47:25 2011
@@ -201,36 +201,9 @@
     ComputeMaskedBits(I->getOperand(1), Mask2, KnownZero, KnownOne, TD,Depth+1);
     ComputeMaskedBits(I->getOperand(0), Mask2, KnownZero2, KnownOne2, TD,
                       Depth+1);
-    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
-    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
-
-    bool isKnownNegative = false;
-    bool isKnownNonNegative = false;
-    // If the multiplication is known not to overflow, compute the sign bit.
-    if (Mask.isNegative() && cast<BinaryOperator>(I)->hasNoSignedWrap()) {
-      Value *Op1 = I->getOperand(1), *Op2 = I->getOperand(0);
-      if (Op1 == Op2) {
-        // The product of a number with itself is non-negative.
-        isKnownNonNegative = true;
-      } else {
-        bool isKnownNonNegative1 = KnownZero.isNegative();
-        bool isKnownNonNegative2 = KnownZero2.isNegative();
-        bool isKnownNegative1 = KnownOne.isNegative();
-        bool isKnownNegative2 = KnownOne2.isNegative();
-        // The product of two numbers with the same sign is non-negative.
-        isKnownNonNegative = (isKnownNegative1 && isKnownNegative2) ||
-          (isKnownNonNegative1 && isKnownNonNegative2);
-        // The product of a negative number and a non-negative number is either
-        // negative or zero.
-        isKnownNegative = (isKnownNegative1 && isKnownNonNegative2 &&
-                           isKnownNonZero(Op2, TD, Depth)) ||
-                          (isKnownNegative2 && isKnownNonNegative1 &&
-                           isKnownNonZero(Op1, TD, Depth));
-        assert(!(isKnownNegative && isKnownNonNegative) &&
-               "Sign bit both zero and one?");
-      }
-    }
-
+    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 
+    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 
+    
     // If low bits are zero in either operand, output low known-0 bits.
     // Also compute a conserative estimate for high known-0 bits.
     // More trickiness is possible, but this is sufficient for the
@@ -247,12 +220,6 @@
     KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) |
                 APInt::getHighBitsSet(BitWidth, LeadZ);
     KnownZero &= Mask;
-
-    if (isKnownNonNegative)
-      KnownZero.setBit(BitWidth - 1);
-    else if (isKnownNegative)
-      KnownOne.setBit(BitWidth - 1);
-
     return;
   }
   case Instruction::UDiv: {
@@ -817,7 +784,7 @@
   }
 
   // The remaining tests are all recursive, so bail out if we hit the limit.
-  if (Depth++ >= MaxDepth)
+  if (Depth++ == MaxDepth)
     return false;
 
   unsigned BitWidth = getBitWidth(V->getType(), TD);
@@ -901,15 +868,6 @@
     if (YKnownNonNegative && isPowerOfTwo(X, TD, /*OrZero*/false, Depth))
       return true;
   }
-  // X * Y.
-  else if (match(V, m_Mul(m_Value(X), m_Value(Y)))) {
-    BinaryOperator *BO = cast<BinaryOperator>(V);
-    // If X and Y are non-zero then so is X * Y as long as the multiplication
-    // does not overflow.
-    if ((BO->hasNoSignedWrap() || BO->hasNoUnsignedWrap()) &&
-        isKnownNonZero(X, TD, Depth) && isKnownNonZero(Y, TD, Depth))
-      return true;
-  }
   // (C ? X : Y) != 0 if X != 0 and Y != 0.
   else if (SelectInst *SI = dyn_cast<SelectInst>(V)) {
     if (isKnownNonZero(SI->getTrueValue(), TD, Depth) &&

Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=143102&r1=143101&r2=143102&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Thu Oct 27 10:47:25 2011
@@ -323,34 +323,3 @@
   ret i1 %B
 ; CHECK: ret i1 false
 }
-
-define i1 @mul1(i32 %X) {
-; CHECK: @mul1
-; Square of a non-zero number is non-zero if there is no overflow.
-  %Y = or i32 %X, 1
-  %M = mul nuw i32 %Y, %Y
-  %C = icmp eq i32 %M, 0
-  ret i1 %C
-; CHECK: ret i1 false
-}
-
-define i1 @mul2(i32 %X) {
-; CHECK: @mul2
-; Square of a non-zero number is positive if there is no signed overflow.
-  %Y = or i32 %X, 1
-  %M = mul nsw i32 %Y, %Y
-  %C = icmp sgt i32 %M, 0
-  ret i1 %C
-; CHECK: ret i1 true
-}
-
-define i1 @mul3(i32 %X, i32 %Y) {
-; CHECK: @mul3
-; Product of non-negative numbers is non-negative if there is no signed overflow.
-  %XX = mul nsw i32 %X, %X
-  %YY = mul nsw i32 %Y, %Y
-  %M = mul nsw i32 %XX, %YY
-  %C = icmp sge i32 %M, 0
-  ret i1 %C
-; CHECK: ret i1 true
-}



From grosbach at apple.com  Thu Oct 27 11:05:35 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 27 Oct 2011 09:05:35 -0700
Subject: [llvm-commits] RuntimeDyld RelocationResolver
In-Reply-To: <6AE1604EE3EC5F4296C096518C6B77EE1805966E8C@mail.accesssoftek.com>
References: <6AE1604EE3EC5F4296C096518C6B77EE18055C51D8@mail.accesssoftek.com>
	<39476213-96A7-4A46-8F6A-5DC1E0E2ECDC@apple.com>
	<6AE1604EE3EC5F4296C096518C6B77EE1805966E8C@mail.accesssoftek.com>
Message-ID: <0FCDF00D-9E99-43A8-86AE-32F8BAA06F65@apple.com>


On Oct 11, 2011, at 2:29 PM, Danil Malyshev wrote:

> Hello Jim,
> 
> Thank you for review. The changed patch is attached.
> 
> 
>> Target names for classes like this are generally done as a prefix, not 
>> a suffix. It would be better to do that here for consistency.
> 
> Fixed.
> 
> 
>> x86 vs. x86_64?
> 
> Both. I have added the explanation in the attached patch.
> 
> 
>> This seems odd? Placeholder? If so, a FIXME to that effect would be good.
> 
> Comment added.
> 
> 
>> LLVM doesn't generally use right-justified comments like this. Not a 
>> big deal, but it looks a bit odd in context.
> 
> Fixed.
> 
> 
>> For now, though, it'd be good to split the target bits into separate 
>> files rather than keeping it all together in one.
> 
> Fixed.
> 
> 
>> This seems odd. At minimum, copious comments are needed explaining 
>> what's going on here.
> 
> Comment added.
> 
> 
>> We shouldn't need to do by-name lookup here. Mapping names should have 
>> been handled by the loader when the symbol table was processed.
>> Everything at this level should be able to use symbol table indices.
> 
> Fixed.
> 
> 
>> No braces when there's just one statement.
> 
> Fixed.
> 
> 
>> Not all relocations are on functions. How are global values handled, 
>> for example?
> 
> This part of code runs only for branch relocations and will not be executed for global values.
> 
> 
>> Is this target memory? The local memory where our copy is stored? In 
>> any case, addr/length is probably better than start/end so we can 
>> handle symbols w/o any data associated (aliases).
> 
> I have added the explanation in the attached patch.
> 
> 
>> Relocations are inherently target and platform specific. ARM MachO vs. 
>> ARM ELF are very different, for example. This appears to be trying for 
>> a one-size-fits-all solution. I don't think that's going to work out.
>> This is the biggest concern I have with this patch. The relocations 
>> should use the definitions in the Object and ELF/MachO file format 
>> headers and handle them distinctly.
> 
> 
> You are right. Originally, relocations are inherently target and platform specific.
> 
> Though, emitter emits the relocations to the target memory on some unified manner, so once in the target memory they are target specific only (i.e. ARM specific, since ARM MachO vs. ARM ELF differences are handled).
> 

The code itself looks better. Thanks for the changes. I disagree fairly strongly with this approach, however. Relocations are target and platform specific. They should be handled as such directly rather than trying to map to a super-set representation that tries to do everything. Can you elaborate on why you find this approach compelling, perhaps?

-Jim


> Relocation resolver dials with already emitted relocations, and depdends on target only because of that.
> 
> 
> 
> Regards,
> Danil
> <RuntimeDyld_RelocationResolver-02.patch>


From benny.kra at googlemail.com  Thu Oct 27 11:38:50 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 27 Oct 2011 16:38:50 -0000
Subject: [llvm-commits] [llvm] r143106 -
	/llvm/trunk/lib/Support/BlockFrequency.cpp
Message-ID: <20111027163850.C047B3128060@llvm.org>

Author: d0k
Date: Thu Oct 27 11:38:50 2011
New Revision: 143106

URL: http://llvm.org/viewvc/llvm-project?rev=143106&view=rev
Log:
BlockFrequency: Use a smarter overflow check.

This trades one 64 bit div for one 64 bit mul and some arithmetic.

Modified:
    llvm/trunk/lib/Support/BlockFrequency.cpp

Modified: llvm/trunk/lib/Support/BlockFrequency.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/BlockFrequency.cpp?rev=143106&r1=143105&r2=143106&view=diff
==============================================================================
--- llvm/trunk/lib/Support/BlockFrequency.cpp (original)
+++ llvm/trunk/lib/Support/BlockFrequency.cpp Thu Oct 27 11:38:50 2011
@@ -70,8 +70,13 @@
 
   assert(n <= d && "Probability must be less or equal to 1.");
 
-  // If we can overflow use 96-bit operations.
-  if (n > 0 && Frequency > UINT64_MAX / n) {
+  // Calculate Frequency * n.
+  uint64_t mulLo = (Frequency & UINT32_MAX) * n;
+  uint64_t mulHi = (Frequency >> 32) * n;
+  uint64_t mulRes = (mulHi << 32) + mulLo;
+
+  // If there was overflow use 96-bit operations.
+  if (mulHi > UINT32_MAX || mulRes < mulLo) {
     // 96-bit value represented as W[1]:W[0].
     uint64_t W[2];
 
@@ -82,8 +87,7 @@
     return *this;
   }
 
-  Frequency *= n;
-  Frequency /= d;
+  Frequency = mulRes / d;
   return *this;
 }
 



From stpworld at narod.ru  Thu Oct 27 12:16:29 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Thu, 27 Oct 2011 21:16:29 +0400
Subject: [llvm-commits] [LLVM,
	llvm-objdump] Fix for clang-native-arm-cortex-a9.
In-Reply-To: <4EA85830.8080701@narod.ru>
References: <4EA67DE3.8060803@narod.ru> <4EA7DF2B.2070100@narod.ru>
	<E7BD9520-EDC1-4BCB-8A99-8A30ECF1C370@apple.com>
	<4EA85830.8080701@narod.ru>
Message-ID: <4EA991ED.5020805@narod.ru>

Should I commit that?

-Stepan.

Stepan Dyatkovskiy wrote:
> Yes, I have.
>
> -Stepan.
>
> Bill Wendling wrote:
>> This looks fine to me. Do you have commit access?
>>
>> -bw
>>
>> On Oct 26, 2011, at 3:21 AM, Stepan Dyatkovskiy wrote:
>>
>>> ping.
>>>
>>> Regards,
>>> Stepan.
>>>
>>> Stepan Dyatkovskiy wrote:
>>>> Hi all,
>>>>
>>>> Please find the patch in attachment that fixes llvm-objdump test
>>>> failures for clang-native-arm-cortex-a9.
>>>>
>>>> Regards,
>>>> Stepan.
>>>>
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From resistor at mac.com  Thu Oct 27 12:15:47 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 27 Oct 2011 17:15:47 -0000
Subject: [llvm-commits] [llvm] r143107 - in /llvm/trunk:
 include/llvm-c/Object.h lib/Object/Object.cpp
Message-ID: <20111027171547.DD4FA3128060@llvm.org>

Author: resistor
Date: Thu Oct 27 12:15:47 2011
New Revision: 143107

URL: http://llvm.org/viewvc/llvm-project?rev=143107&view=rev
Log:
Add relocation iterators to the libObject C API.

Modified:
    llvm/trunk/include/llvm-c/Object.h
    llvm/trunk/lib/Object/Object.cpp

Modified: llvm/trunk/include/llvm-c/Object.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Object.h?rev=143107&r1=143106&r2=143107&view=diff
==============================================================================
--- llvm/trunk/include/llvm-c/Object.h (original)
+++ llvm/trunk/include/llvm-c/Object.h Thu Oct 27 12:15:47 2011
@@ -32,6 +32,7 @@
 typedef struct LLVMOpaqueObjectFile *LLVMObjectFileRef;
 typedef struct LLVMOpaqueSectionIterator *LLVMSectionIteratorRef;
 typedef struct LLVMOpaqueSymbolIterator *LLVMSymbolIteratorRef;
+typedef struct LLVMOpaqueRelocationIterator *LLVMRelocationIteratorRef;
 
 // ObjectFile creation
 LLVMObjectFileRef LLVMCreateObjectFile(LLVMMemoryBufferRef MemBuf);
@@ -61,6 +62,14 @@
 LLVMBool LLVMGetSectionContainsSymbol(LLVMSectionIteratorRef SI,
                                  LLVMSymbolIteratorRef Sym);
 
+// Section Relocation iterators
+LLVMRelocationIteratorRef LLVMGetRelocations(LLVMSectionIteratorRef Section);
+void LLVMDisposeRelocationIterator(LLVMRelocationIteratorRef RI);
+LLVMBool LLVMIsRelocationIteratorAtEnd(LLVMSectionIteratorRef Section,
+                                       LLVMRelocationIteratorRef RI);
+void LLVMMoveToNextRelocation(LLVMRelocationIteratorRef RI);
+
+
 // SymbolRef accessors
 const char *LLVMGetSymbolName(LLVMSymbolIteratorRef SI);
 uint64_t LLVMGetSymbolAddress(LLVMSymbolIteratorRef SI);
@@ -99,6 +108,17 @@
       return reinterpret_cast<LLVMSymbolIteratorRef>
         (const_cast<symbol_iterator*>(SI));
     }
+
+    inline relocation_iterator *unwrap(LLVMRelocationIteratorRef SI) {
+      return reinterpret_cast<relocation_iterator*>(SI);
+    }
+
+    inline LLVMRelocationIteratorRef
+    wrap(const relocation_iterator *SI) {
+      return reinterpret_cast<LLVMRelocationIteratorRef>
+        (const_cast<relocation_iterator*>(SI));
+    }
+
   }
 }
 

Modified: llvm/trunk/lib/Object/Object.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/Object.cpp?rev=143107&r1=143106&r2=143107&view=diff
==============================================================================
--- llvm/trunk/lib/Object/Object.cpp (original)
+++ llvm/trunk/lib/Object/Object.cpp Thu Oct 27 12:15:47 2011
@@ -112,6 +112,29 @@
   return ret;
 }
 
+// Section Relocation iterators
+LLVMRelocationIteratorRef LLVMGetRelocations(LLVMSectionIteratorRef Section) {
+  relocation_iterator SI = (*unwrap(Section))->begin_relocations();
+  return wrap(new relocation_iterator(SI));
+}
+
+void LLVMDisposeRelocationIterator(LLVMRelocationIteratorRef SI) {
+  delete unwrap(SI);
+}
+
+LLVMBool LLVMIsRelocationIteratorAtEnd(LLVMSectionIteratorRef Section,
+                                       LLVMRelocationIteratorRef SI) {
+  return (*unwrap(SI) == (*unwrap(Section))->end_relocations()) ? 1 : 0;
+}
+
+void LLVMMoveToNextRelocation(LLVMRelocationIteratorRef SI) {
+  error_code ec;
+  unwrap(SI)->increment(ec);
+  if (ec) report_fatal_error("LLVMMoveToNextRelocation failed: " +
+                             ec.message());
+}
+
+
 // SymbolRef accessors
 const char *LLVMGetSymbolName(LLVMSymbolIteratorRef SI) {
   StringRef ret;



From grosbach at apple.com  Thu Oct 27 12:16:55 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 27 Oct 2011 17:16:55 -0000
Subject: [llvm-commits] [llvm] r143108 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20111027171655.D36A23128060@llvm.org>

Author: grosbach
Date: Thu Oct 27 12:16:55 2011
New Revision: 143108

URL: http://llvm.org/viewvc/llvm-project?rev=143108&view=rev
Log:
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.

rdar://10348584

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=143108&r1=143107&r2=143108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Oct 27 12:16:55 2011
@@ -3921,7 +3921,9 @@
 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
                   (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
 
-// Alias for MVN without the ".w" optional width specifier.
+// Alias for MVN with(out) the ".w" optional width specifier.
+def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
+           (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
            (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=143108&r1=143107&r2=143108&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Thu Oct 27 12:16:55 2011
@@ -1231,7 +1231,7 @@
         mvns r0, #0x3fc0000
         itte eq
         mvnseq r1, #12
-        mvneq r1, #12
+        mvneq.w r1, #12
         mvnne r1, #12
 
 @ CHECK: mvns	r8, #21                 @ encoding: [0x7f,0xf0,0x15,0x08]
@@ -1250,7 +1250,7 @@
         mvns r2, r3
         mvn r5, r6, lsl #19
         mvn r5, r6, lsr #9
-        mvn r5, r6, asr #4
+        mvn.w r5, r6, asr #4
         mvn r5, r6, ror #6
         mvn r5, r6, rrx
         it eq



From grosbach at apple.com  Thu Oct 27 12:24:08 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 27 Oct 2011 10:24:08 -0700
Subject: [llvm-commits] [llvm] r143097 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/MC/ lib/CodeGen/AsmPrinter/ lib/MC/
 test/CodeGen/ARM/ test/CodeGen/X86/ test/DebugInfo/
In-Reply-To: <20111027064411.6F491312800A@llvm.org>
References: <20111027064411.6F491312800A@llvm.org>
Message-ID: <E9EC3800-F327-4902-9CCF-CA15EACBD39E@apple.com>

Hey Nick,

This is great stuff. Thanks for doing this.

I'm seeing a few test failures in the GCC test suite (https://llvm.org/svn/llvm-project/clang-tests/trunk/gcc-4_2-testsuite), though. It's fairly likely that they're just tests that need to be updated. Can you have a look?

gcc.apple/block-debug-1.c scan-assembler __block_descriptor.*DW_AT_name
gcc.apple/block-debug-1.c scan-assembler __block_literal_generic.*DW_AT_name
gcc.apple/block-debug-2.c scan-assembler __block_descriptor.*DW_AT_name
gcc.apple/block-debug-2.c scan-assembler __block_literal_generic.*DW_AT_name
gcc.dg/debug/dwarf2/var1.c scan-assembler xyzzy[^\\n\\r]+DW_AT_name

-Jim

On Oct 26, 2011, at 11:44 PM, Nick Lewycky wrote:

> Author: nicholas
> Date: Thu Oct 27 01:44:11 2011
> New Revision: 143097
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=143097&view=rev
> Log:
> Teach our Dwarf emission to use the string pool.
> 
> Added:
>    llvm/trunk/test/DebugInfo/stringpool.ll
> Modified:
>    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
>    llvm/trunk/include/llvm/MC/MCAsmInfo.h
>    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
>    llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
>    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
>    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
>    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
>    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
>    llvm/trunk/lib/MC/MCAsmInfo.cpp
>    llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
>    llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll
>    llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll
>    llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll
> 
> Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Thu Oct 27 01:44:11 2011
> @@ -194,6 +194,11 @@
> 
>     bool needsSEHMoves();
> 
> +    /// needsRelocationsForDwarfStringPool - Specifies whether the object format
> +    /// expects to use relocations to refer to debug entries. Alternatively we
> +    /// emit section offsets in bytes from the start of the string pool.
> +    bool needsRelocationsForDwarfStringPool() const;
> +
>     /// EmitConstantPool - Print to the current output stream assembly
>     /// representations of the constants in the constant pool MCP. This is
>     /// used to print out constants which have been "spilled to memory" by
> 
> Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
> +++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Thu Oct 27 01:44:11 2011
> @@ -330,6 +330,10 @@
>     /// use EmitLabelOffsetDifference.
>     bool DwarfUsesLabelOffsetForRanges;
> 
> +    /// DwarfUsesRelocationsForStringPool - True if this Dwarf output must use
> +    /// relocations to refer to entries in the string pool.
> +    bool DwarfUsesRelocationsForStringPool;
> +
>     /// DwarfRegNumForCFI - True if dwarf register numbers are printed
>     /// instead of symbolic register names in .cfi_* directives.
>     bool DwarfRegNumForCFI;  // Defaults to false;
> @@ -566,6 +570,9 @@
>     bool doesDwarfUsesLabelOffsetForRanges() const {
>       return DwarfUsesLabelOffsetForRanges;
>     }
> +    bool doesDwarfUseRelocationsForStringPool() const {
> +      return DwarfUsesRelocationsForStringPool;
> +    }
>     bool useDwarfRegNumForCFI() const {
>       return DwarfRegNumForCFI;
>     }
> 
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Oct 27 01:44:11 2011
> @@ -613,6 +613,10 @@
>     MF->getFunction()->needsUnwindTableEntry();
> }
> 
> +bool AsmPrinter::needsRelocationsForDwarfStringPool() const {
> +  return MAI->doesDwarfUseRelocationsForStringPool();
> +}
> +
> void AsmPrinter::emitPrologLabel(const MachineInstr &MI) {
>   MCSymbol *Label = MI.getOperand(0).getMCSymbol();
> 
> @@ -2092,4 +2096,3 @@
>   report_fatal_error("no GCMetadataPrinter registered for GC: " + Twine(Name));
>   return 0;
> }
> -
> 
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp Thu Oct 27 01:44:11 2011
> @@ -267,6 +267,7 @@
> ///
> unsigned DIELabel::SizeOf(AsmPrinter *AP, unsigned Form) const {
>   if (Form == dwarf::DW_FORM_data4) return 4;
> +  if (Form == dwarf::DW_FORM_strp) return 4;
>   return AP->getTargetData().getPointerSize();
> }
> 
> @@ -290,6 +291,7 @@
> ///
> unsigned DIEDelta::SizeOf(AsmPrinter *AP, unsigned Form) const {
>   if (Form == dwarf::DW_FORM_data4) return 4;
> +  if (Form == dwarf::DW_FORM_strp) return 4;
>   return AP->getTargetData().getPointerSize();
> }
> 
> 
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Thu Oct 27 01:44:11 2011
> @@ -69,10 +69,21 @@
> 
> /// addString - Add a string attribute data and value. DIEString only
> /// keeps string reference.
> -void CompileUnit::addString(DIE *Die, unsigned Attribute, unsigned Form,
> -                            StringRef String) {
> -  DIEValue *Value = new (DIEValueAllocator) DIEString(String);
> -  Die->addValue(Attribute, Form, Value);
> +void CompileUnit::addString(DIE *Die, unsigned Attribute, StringRef String) {
> +  if (String.size() > 3) {
> +    MCSymbol *Symb = DD->getStringPoolEntry(String);
> +    DIEValue *Value;
> +    if (Asm->needsRelocationsForDwarfStringPool())
> +      Value = new (DIEValueAllocator) DIELabel(Symb);
> +    else {
> +      MCSymbol *StringPool = DD->getStringPool();
> +      Value = new (DIEValueAllocator) DIEDelta(Symb, StringPool);
> +    }
> +    Die->addValue(Attribute, dwarf::DW_FORM_strp, Value);
> +  } else {
> +    DIEValue *Value = new (DIEValueAllocator) DIEString(String);
> +    Die->addValue(Attribute, dwarf::DW_FORM_string, Value);
> +  }
> }
> 
> /// addLabel - Add a Dwarf label attribute data and value.
> @@ -479,7 +490,7 @@
> 
> /// addConstantFPValue - Add constant value entry in variable DIE.
> bool CompileUnit::addConstantFPValue(DIE *Die, const MachineOperand &MO) {
> -  assert(MO.isFPImm() && "Invalid machine operand!");
> +  assert (MO.isFPImm() && "Invalid machine operand!");
>   DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
>   APFloat FPImm = MO.getFPImm()->getValueAPF();
> 
> @@ -660,7 +671,7 @@
>   StringRef Name = BTy.getName();
>   // Add name if not anonymous or intermediate type.
>   if (!Name.empty())
> -    addString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
> +    addString(&Buffer, dwarf::DW_AT_name, Name);
> 
>   if (BTy.getTag() == dwarf::DW_TAG_unspecified_type) {
>     Buffer.setTag(dwarf::DW_TAG_unspecified_type);
> @@ -694,7 +705,7 @@
> 
>   // Add name if not anonymous or intermediate type.
>   if (!Name.empty())
> -    addString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
> +    addString(&Buffer, dwarf::DW_AT_name, Name);
> 
>   // Add size if non-zero (derived types might be zero-sized.)
>   if (Size)
> @@ -791,8 +802,7 @@
>       else if (Element.isVariable()) {
>         DIVariable DV(Element);
>         ElemDie = new DIE(dwarf::DW_TAG_variable);
> -        addString(ElemDie, dwarf::DW_AT_name, dwarf::DW_FORM_string,
> -                  DV.getName());
> +        addString(ElemDie, dwarf::DW_AT_name, DV.getName());
>         addType(ElemDie, DV.getType());
>         addUInt(ElemDie, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag, 1);
>         addUInt(ElemDie, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1);
> @@ -836,7 +846,7 @@
> 
>   // Add name if not anonymous or intermediate type.
>   if (!Name.empty())
> -    addString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
> +    addString(&Buffer, dwarf::DW_AT_name, Name);
> 
>   if (Tag == dwarf::DW_TAG_enumeration_type || Tag == dwarf::DW_TAG_class_type
>       || Tag == dwarf::DW_TAG_structure_type || Tag == dwarf::DW_TAG_union_type)
> @@ -868,7 +878,7 @@
> 
>   ParamDIE = new DIE(dwarf::DW_TAG_template_type_parameter);
>   addType(ParamDIE, TP.getType());
> -  addString(ParamDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string, TP.getName());
> +  addString(ParamDIE, dwarf::DW_AT_name, TP.getName());
>   return ParamDIE;
> }
> 
> @@ -883,7 +893,7 @@
>   ParamDIE = new DIE(dwarf::DW_TAG_template_value_parameter);
>   addType(ParamDIE, TPV.getType());
>   if (!TPV.getName().empty())
> -    addString(ParamDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string, TPV.getName());
> +    addString(ParamDIE, dwarf::DW_AT_name, TPV.getName());
>   addUInt(ParamDIE, dwarf::DW_AT_const_value, dwarf::DW_FORM_udata, 
>           TPV.getValue());
>   return ParamDIE;
> @@ -897,7 +907,7 @@
>   NDie = new DIE(dwarf::DW_TAG_namespace);
>   insertDIE(NS, NDie);
>   if (!NS.getName().empty())
> -    addString(NDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, NS.getName());
> +    addString(NDie, dwarf::DW_AT_name, NS.getName());
>   addSourceLine(NDie, NS);
>   addToContextOwner(NDie, NS.getContext());
>   return NDie;
> @@ -932,7 +942,7 @@
> 
>   StringRef LinkageName = SP.getLinkageName();
>   if (!LinkageName.empty())
> -    addString(SPDie, dwarf::DW_AT_MIPS_linkage_name, dwarf::DW_FORM_string,
> +    addString(SPDie, dwarf::DW_AT_MIPS_linkage_name,
>               getRealLinkageName(LinkageName));
> 
>   // If this DIE is going to refer declaration info using AT_specification
> @@ -942,7 +952,7 @@
> 
>   // Constructors and operators for anonymous aggregates do not have names.
>   if (!SP.getName().empty())
> -    addString(SPDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, SP.getName());
> +    addString(SPDie, dwarf::DW_AT_name, SP.getName());
> 
>   addSourceLine(SPDie, SP);
> 
> @@ -1048,13 +1058,12 @@
>   insertDIE(N, VariableDIE);
> 
>   // Add name.
> -  addString(VariableDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string,
> -            GV.getDisplayName());
> +  addString(VariableDIE, dwarf::DW_AT_name, GV.getDisplayName());
>   StringRef LinkageName = GV.getLinkageName();
>   bool isGlobalVariable = GV.getGlobal() != NULL;
>   if (!LinkageName.empty() && isGlobalVariable)
>     addString(VariableDIE, dwarf::DW_AT_MIPS_linkage_name,
> -              dwarf::DW_FORM_string, getRealLinkageName(LinkageName));
> +              getRealLinkageName(LinkageName));
>   // Add type.
>   DIType GTy = GV.getType();
>   addType(VariableDIE, GTy);
> @@ -1170,7 +1179,7 @@
> DIE *CompileUnit::constructEnumTypeDIE(DIEnumerator ETy) {
>   DIE *Enumerator = new DIE(dwarf::DW_TAG_enumerator);
>   StringRef Name = ETy.getName();
> -  addString(Enumerator, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
> +  addString(Enumerator, dwarf::DW_AT_name, Name);
>   int64_t Value = ETy.getEnumValue();
>   addSInt(Enumerator, dwarf::DW_AT_const_value, dwarf::DW_FORM_sdata, Value);
>   return Enumerator;
> @@ -1207,8 +1216,7 @@
>     addDIEEntry(VariableDie, dwarf::DW_AT_abstract_origin,
>                             dwarf::DW_FORM_ref4, AbsDIE);
>   else {
> -    addString(VariableDie, dwarf::DW_AT_name, 
> -                          dwarf::DW_FORM_string, Name);
> +    addString(VariableDie, dwarf::DW_AT_name, Name);
>     addSourceLine(VariableDie, DV->getVariable());
>     addType(VariableDie, DV->getType());
>   }
> @@ -1303,7 +1311,7 @@
>   DIE *MemberDie = new DIE(DT.getTag());
>   StringRef Name = DT.getName();
>   if (!Name.empty())
> -    addString(MemberDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
> +    addString(MemberDie, dwarf::DW_AT_name, Name);
> 
>   addType(MemberDie, DT.getTypeDerivedFrom());
> 
> @@ -1377,16 +1385,13 @@
>   // Objective-C properties.
>   StringRef PropertyName = DT.getObjCPropertyName();
>   if (!PropertyName.empty()) {
> -    addString(MemberDie, dwarf::DW_AT_APPLE_property_name, dwarf::DW_FORM_string,
> -              PropertyName);
> +    addString(MemberDie, dwarf::DW_AT_APPLE_property_name, PropertyName);
>     StringRef GetterName = DT.getObjCPropertyGetterName();
>     if (!GetterName.empty())
> -      addString(MemberDie, dwarf::DW_AT_APPLE_property_getter,
> -                dwarf::DW_FORM_string, GetterName);
> +      addString(MemberDie, dwarf::DW_AT_APPLE_property_getter, GetterName);
>     StringRef SetterName = DT.getObjCPropertySetterName();
>     if (!SetterName.empty())
> -      addString(MemberDie, dwarf::DW_AT_APPLE_property_setter,
> -                dwarf::DW_FORM_string, SetterName);
> +      addString(MemberDie, dwarf::DW_AT_APPLE_property_setter, SetterName);
>     unsigned PropertyAttributes = 0;
>     if (DT.isReadOnlyObjCProperty())
>       PropertyAttributes |= dwarf::DW_APPLE_PROPERTY_readonly;
> 
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Thu Oct 27 01:44:11 2011
> @@ -150,8 +150,7 @@
> 
>   /// addString - Add a string attribute data and value.
>   ///
> -  void addString(DIE *Die, unsigned Attribute, unsigned Form,
> -                 const StringRef Str);
> +  void addString(DIE *Die, unsigned Attribute, const StringRef Str);
> 
>   /// addLabel - Add a Dwarf label attribute data and value.
>   ///
> 
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Oct 27 01:44:11 2011
> @@ -136,6 +136,10 @@
> DwarfDebug::~DwarfDebug() {
> }
> 
> +MCSymbol *DwarfDebug::getStringPool() {
> +  return Asm->GetTempSymbol("section_str");
> +}
> +
> MCSymbol *DwarfDebug::getStringPoolEntry(StringRef Str) {
>   std::pair<MCSymbol*, unsigned> &Entry = StringPool[Str];
>   if (Entry.first) return Entry.first;
> @@ -467,11 +471,10 @@
> 
>   DIE *Die = new DIE(dwarf::DW_TAG_compile_unit);
>   CompileUnit *NewCU = new CompileUnit(ID, Die, Asm, this);
> -  NewCU->addString(Die, dwarf::DW_AT_producer, dwarf::DW_FORM_string,
> -                   DIUnit.getProducer());
> +  NewCU->addString(Die, dwarf::DW_AT_producer, DIUnit.getProducer());
>   NewCU->addUInt(Die, dwarf::DW_AT_language, dwarf::DW_FORM_data2,
>                  DIUnit.getLanguage());
> -  NewCU->addString(Die, dwarf::DW_AT_name, dwarf::DW_FORM_string, FN);
> +  NewCU->addString(Die, dwarf::DW_AT_name, FN);
>   // Use DW_AT_entry_pc instead of DW_AT_low_pc/DW_AT_high_pc pair. This
>   // simplifies debug range entries.
>   NewCU->addUInt(Die, dwarf::DW_AT_entry_pc, dwarf::DW_FORM_addr, 0);
> @@ -484,14 +487,13 @@
>     NewCU->addUInt(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, 0);
> 
>   if (!Dir.empty())
> -    NewCU->addString(Die, dwarf::DW_AT_comp_dir, dwarf::DW_FORM_string, Dir);
> +    NewCU->addString(Die, dwarf::DW_AT_comp_dir, Dir);
>   if (DIUnit.isOptimized())
>     NewCU->addUInt(Die, dwarf::DW_AT_APPLE_optimized, dwarf::DW_FORM_flag, 1);
> 
>   StringRef Flags = DIUnit.getFlags();
>   if (!Flags.empty())
> -    NewCU->addString(Die, dwarf::DW_AT_APPLE_flags, dwarf::DW_FORM_string, 
> -                     Flags);
> +    NewCU->addString(Die, dwarf::DW_AT_APPLE_flags, Flags);
> 
>   if (unsigned RVer = DIUnit.getRunTimeVersion())
>     NewCU->addUInt(Die, dwarf::DW_AT_APPLE_major_runtime_vers,
> @@ -1796,6 +1798,7 @@
> 
>     // Emit the string itself.
>     Asm->OutStreamer.EmitBytes(Entries[i].second->getKey(), 0/*addrspace*/);
> +    Asm->OutStreamer.EmitZeros(1, 0);
>   }
> }
> 
> 
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Thu Oct 27 01:44:11 2011
> @@ -216,8 +216,6 @@
>   StringMap<std::pair<MCSymbol*, unsigned> > StringPool;
>   unsigned NextStringPoolNumber;
> 
> -  MCSymbol *getStringPoolEntry(StringRef Str);
> -
>   /// SectionMap - Provides a unique id per text section.
>   ///
>   UniqueVector<const MCSection*> SectionMap;
> @@ -504,6 +502,13 @@
> 
>   /// createSubprogramDIE - Create new DIE using SP.
>   DIE *createSubprogramDIE(DISubprogram SP);
> +
> +  /// getStringPool - returns the entry into the start of the pool.
> +  MCSymbol *getStringPool();
> +
> +  /// getStringPoolEntry - returns an entry into the string pool with the given
> +  /// string text.
> +  MCSymbol *getStringPoolEntry(StringRef Str);
> };
> } // End of namespace llvm
> 
> 
> Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCAsmInfo.cpp (original)
> +++ llvm/trunk/lib/MC/MCAsmInfo.cpp Thu Oct 27 01:44:11 2011
> @@ -91,6 +91,7 @@
>   DwarfRequiresRelocationForSectionOffset = true;
>   DwarfSectionOffsetDirective = 0;
>   DwarfUsesLabelOffsetForRanges = true;
> +  DwarfUsesRelocationsForStringPool = true;
>   DwarfRegNumForCFI = false;
>   HasMicrosoftFastStdCallMangling = false;
> 
> 
> Modified: llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp (original)
> +++ llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Thu Oct 27 01:44:11 2011
> @@ -66,4 +66,5 @@
> 
>   DwarfRequiresRelocationForSectionOffset = false;
>   DwarfUsesLabelOffsetForRanges = false;
> +  DwarfUsesRelocationsForStringPool = false;
> }
> 
> Modified: llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/debug-info-sreg2.ll Thu Oct 27 01:44:11 2011
> @@ -6,8 +6,8 @@
> ;CHECK: Ldebug_loc0:
> ;CHECK-NEXT:        .long   Ltmp1
> ;CHECK-NEXT:        .long   Ltmp2
> -;CHECK-NEXT: Lset8 = Ltmp10-Ltmp9                    @ Loc expr size
> -;CHECK-NEXT:        .short  Lset8
> +;CHECK-NEXT: Lset[[N:[0-9]+]] = Ltmp10-Ltmp9        @ Loc expr size
> +;CHECK-NEXT:        .short  Lset[[N]]
> ;CHECK-NEXT: Ltmp9:
> ;CHECK-NEXT:        .byte   144                     @ DW_OP_regx for S register
> 
> 
> Modified: llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll Thu Oct 27 01:44:11 2011
> @@ -5,17 +5,17 @@
> ; CHECK:	.byte	17                      ## DW_TAG_compile_unit
> ; CHECK-NEXT:	.byte	1                       ## DW_CHILDREN_yes
> ; CHECK-NEXT:	.byte	37                      ## DW_AT_producer
> -; CHECK-NEXT:	.byte	8                       ## DW_FORM_string
> +; CHECK-NEXT:	.byte	14                      ## DW_FORM_strp
> ; CHECK-NEXT:	.byte	19                      ## DW_AT_language
> ; CHECK-NEXT:	.byte	5                       ## DW_FORM_data2
> ; CHECK-NEXT:	.byte	3                       ## DW_AT_name
> -; CHECK-NEXT:	.byte	8                       ## DW_FORM_string
> +; CHECK-NEXT:	.byte	14                      ## DW_FORM_strp
> ; CHECK-NEXT:	.byte	82                      ## DW_AT_entry_pc
> ; CHECK-NEXT:	.byte	1                       ## DW_FORM_addr
> ; CHECK-NEXT:	.byte	16                      ## DW_AT_stmt_list
> ; CHECK-NEXT:	.byte	6                       ## DW_FORM_data4
> ; CHECK-NEXT:	.byte	27                      ## DW_AT_comp_dir
> -; CHECK-NEXT:	.byte	8                       ## DW_FORM_string
> +; CHECK-NEXT:	.byte	14                      ## DW_FORM_strp
> ; CHECK-NEXT:	.byte	225                     ## DW_AT_APPLE_optimized
> 
> %struct.a = type { i32, %struct.a* }
> 
> Modified: llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll?rev=143097&r1=143096&r2=143097&view=diff
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll (original)
> +++ llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll Thu Oct 27 01:44:11 2011
> @@ -2,14 +2,14 @@
> 
> ; ModuleID = 'test.c'
> 
> - at GLOBAL = common global i32 0, align 4
> + at GLB = common global i32 0, align 4
> 
> define i32 @f() nounwind {
> -  %LOCAL = alloca i32, align 4
> -  call void @llvm.dbg.declare(metadata !{i32* %LOCAL}, metadata !15), !dbg !17
> -  %1 = load i32* @GLOBAL, align 4, !dbg !18
> -  store i32 %1, i32* %LOCAL, align 4, !dbg !18
> -  %2 = load i32* @GLOBAL, align 4, !dbg !19
> +  %LOC = alloca i32, align 4
> +  call void @llvm.dbg.declare(metadata !{i32* %LOC}, metadata !15), !dbg !17
> +  %1 = load i32* @GLB, align 4, !dbg !18
> +  store i32 %1, i32* %LOC, align 4, !dbg !18
> +  %2 = load i32* @GLB, align 4, !dbg !19
>   ret i32 %2, !dbg !19
> }
> 
> @@ -31,17 +31,17 @@
> !11 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
> !12 = metadata !{metadata !13}
> !13 = metadata !{metadata !14}
> -!14 = metadata !{i32 720948, i32 0, null, metadata !"GLOBAL", metadata !"GLOBAL", metadata !"", metadata !6, i32 1, metadata !9, i32 0, i32 1, i32* @GLOBAL} ; [ DW_TAG_variable ]
> -!15 = metadata !{i32 721152, metadata !16, metadata !"LOCAL", metadata !6, i32 4, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
> +!14 = metadata !{i32 720948, i32 0, null, metadata !"GLB", metadata !"GLB", metadata !"", metadata !6, i32 1, metadata !9, i32 0, i32 1, i32* @GLB} ; [ DW_TAG_variable ]
> +!15 = metadata !{i32 721152, metadata !16, metadata !"LOC", metadata !6, i32 4, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
> !16 = metadata !{i32 720907, metadata !5, i32 3, i32 9, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
> !17 = metadata !{i32 4, i32 9, metadata !16, null}
> !18 = metadata !{i32 4, i32 23, metadata !16, null}
> !19 = metadata !{i32 5, i32 5, metadata !16, null}
> 
> -; CHECK: .ascii	 "GLOBAL"
> +; CHECK: .ascii	 "GLB"
> ; CHECK: .byte	1
> ; CHECK: .byte	1
> 
> -; CHECK: .ascii	 "LOCAL"
> +; CHECK: .ascii	 "LOC"
> ; CHECK: .byte	1
> ; CHECK: .byte	4
> 
> Added: llvm/trunk/test/DebugInfo/stringpool.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/stringpool.ll?rev=143097&view=auto
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/stringpool.ll (added)
> +++ llvm/trunk/test/DebugInfo/stringpool.ll Thu Oct 27 01:44:11 2011
> @@ -0,0 +1,54 @@
> +; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=LINUX
> +; RUN: llc -O0 -mtriple=x86_64-darwin < %s | FileCheck %s --check-prefix=DARWIN
> +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
> +target triple = "x86_64-unknown-linux-gnu"
> +
> + at x = common global i32 0, align 4
> + at yyyyyyyy = common global i32 0, align 4
> +
> +!llvm.dbg.cu = !{!0}
> +
> +!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"hello.c", metadata !"/home/nlewycky", metadata !"clang version 3.1 (trunk 143048)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ]
> +!1 = metadata !{metadata !2}
> +!2 = metadata !{i32 0}
> +!3 = metadata !{metadata !4}
> +!4 = metadata !{metadata !5, metadata !8}
> +!5 = metadata !{i32 720948, i32 0, null, metadata !"x", metadata !"x", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, i32* @x} ; [ DW_TAG_variable ]
> +!6 = metadata !{i32 720937, metadata !"hello.c", metadata !"/home/nlewycky", null} ; [ DW_TAG_file_type ]
> +!7 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
> +!8 = metadata !{i32 720948, i32 0, null, metadata !"yyyyyyyy", metadata !"yyyyyyyy", metadata !"", metadata !6, i32 2, metadata !7, i32 0, i32 1, i32* @yyyyyyyy} ; [ DW_TAG_variable ]
> +
> +; 120 is ASCII 'x'. Verify that we use it directly as its name and don't emit
> +; a reference to the string pool.
> +; LINUX:        .byte   120                     # DW_AT_name
> +; DARWIN:       .byte   120                     ## DW_AT_name
> +
> +; Verify that we refer to 'yyyyyyyy' with a relocation.
> +; LINUX:      .long   .Lstring{{[0-9]+}}      # DW_AT_name
> +; LINUX-NEXT: .long   39                      # DW_AT_type
> +; LINUX-NEXT: .byte   1                       # DW_AT_external
> +; LINUX-NEXT: .byte   1                       # DW_AT_decl_file
> +; LINUX-NEXT: .byte   2                       # DW_AT_decl_line
> +; LINUX-NEXT: .byte   9                       # DW_AT_location
> +; LINUX-NEXT: .byte   3
> +; LINUX-NEXT: .quad   yyyyyyyy
> +
> +; Verify that we refer to 'yyyyyyyy' without a relocation.
> +; DARWIN: Lset[[N:[0-9]+]] = Lstring{{[0-9]+}}-Lsection_str   ## DW_AT_name
> +; DARWIN-NEXT:        .long   Lset[[N]]
> +; DARWIN-NEXT:        .long   39                      ## DW_AT_type
> +; DARWIN-NEXT:        .byte   1                       ## DW_AT_external
> +; DARWIN-NEXT:        .byte   1                       ## DW_AT_decl_file
> +; DARWIN-NEXT:        .byte   2                       ## DW_AT_decl_line
> +; DARWIN-NEXT:        .byte   9                       ## DW_AT_location
> +; DARWIN-NEXT:        .byte   3
> +; DARWIN-NEXT:        .quad   _yyyyyyyy
> +
> +
> +; Verify that "yyyyyyyy" ended up in the stringpool.
> +; LINUX: .section .debug_str,"MS", at progbits,1
> +; LINUX-NOT: .section
> +; LINUX: yyyyyyyy
> +; DARWIN: .section __DWARF,__debug_str,regular,debug
> +; DARWIN-NOT: .section
> +; DARWIN: yyyyyyyy
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From resistor at mac.com  Thu Oct 27 12:32:36 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 27 Oct 2011 17:32:36 -0000
Subject: [llvm-commits] [llvm] r143109 - in /llvm/trunk:
 include/llvm-c/Object.h lib/Object/Object.cpp
Message-ID: <20111027173236.DD97E3128060@llvm.org>

Author: resistor
Date: Thu Oct 27 12:32:36 2011
New Revision: 143109

URL: http://llvm.org/viewvc/llvm-project?rev=143109&view=rev
Log:
Expose relocation accessors through the libObject C API.

Modified:
    llvm/trunk/include/llvm-c/Object.h
    llvm/trunk/lib/Object/Object.cpp

Modified: llvm/trunk/include/llvm-c/Object.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Object.h?rev=143109&r1=143108&r2=143109&view=diff
==============================================================================
--- llvm/trunk/include/llvm-c/Object.h (original)
+++ llvm/trunk/include/llvm-c/Object.h Thu Oct 27 12:32:36 2011
@@ -76,6 +76,16 @@
 uint64_t LLVMGetSymbolOffset(LLVMSymbolIteratorRef SI);
 uint64_t LLVMGetSymbolSize(LLVMSymbolIteratorRef SI);
 
+// RelocationRef accessors
+uint64_t LLVMGetRelocationAddress(LLVMRelocationIteratorRef RI);
+LLVMSymbolIteratorRef LLVMGetRelocationSymbol(LLVMRelocationIteratorRef RI);
+uint64_t LLVMGetRelocationType(LLVMRelocationIteratorRef RI);
+// NOTE: Caller takes ownership of returned string of the two
+// following functions.
+const char *LLVMGetRelocationTypeName(LLVMRelocationIteratorRef RI);
+const char *LLVMGetRelocationValueString(LLVMRelocationIteratorRef RI);
+
+
 #ifdef __cplusplus
 }
 

Modified: llvm/trunk/lib/Object/Object.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/Object.cpp?rev=143109&r1=143108&r2=143109&view=diff
==============================================================================
--- llvm/trunk/lib/Object/Object.cpp (original)
+++ llvm/trunk/lib/Object/Object.cpp Thu Oct 27 12:32:36 2011
@@ -164,3 +164,48 @@
   return ret;
 }
 
+// RelocationRef accessors
+uint64_t LLVMGetRelocationAddress(LLVMRelocationIteratorRef RI) {
+  uint64_t ret;
+  if (error_code ec = (*unwrap(RI))->getAddress(ret))
+    report_fatal_error(ec.message());
+  return ret;
+}
+
+LLVMSymbolIteratorRef LLVMGetRelocationSymbol(LLVMRelocationIteratorRef RI) {
+  SymbolRef ret;
+  if (error_code ec = (*unwrap(RI))->getSymbol(ret))
+    report_fatal_error(ec.message());
+
+  return wrap(new symbol_iterator(ret));
+}
+
+uint64_t LLVMGetRelocationType(LLVMRelocationIteratorRef RI) {
+  uint64_t ret;
+  if (error_code ec = (*unwrap(RI))->getType(ret))
+    report_fatal_error(ec.message());
+  return ret;
+}
+
+// NOTE: Caller takes ownership of returned string.
+const char *LLVMGetRelocationTypeName(LLVMRelocationIteratorRef RI) {
+  SmallVector<char, 0> ret;
+  if (error_code ec = (*unwrap(RI))->getTypeName(ret))
+    report_fatal_error(ec.message());
+
+  char *str = static_cast<char*>(malloc(ret.size()));
+  std::copy(ret.begin(), ret.end(), str);
+  return str;
+}
+
+// NOTE: Caller takes ownership of returned string.
+const char *LLVMGetRelocationValueString(LLVMRelocationIteratorRef RI) {
+  SmallVector<char, 0> ret;
+  if (error_code ec = (*unwrap(RI))->getValueString(ret))
+    report_fatal_error(ec.message());
+
+  char *str = static_cast<char*>(malloc(ret.size()));
+  std::copy(ret.begin(), ret.end(), str);
+  return str;
+}
+



From grosbach at apple.com  Thu Oct 27 12:33:59 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 27 Oct 2011 17:33:59 -0000
Subject: [llvm-commits] [llvm] r143110 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20111027173359.8BD173128060@llvm.org>

Author: grosbach
Date: Thu Oct 27 12:33:59 2011
New Revision: 143110

URL: http://llvm.org/viewvc/llvm-project?rev=143110&view=rev
Log:
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.

rdar://10348844

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=143110&r1=143109&r2=143110&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Oct 27 12:33:59 2011
@@ -3944,6 +3944,12 @@
 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
 
+// LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
+def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
+                  (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
+def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
+                  (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
+
 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=143110&r1=143109&r2=143110&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Thu Oct 27 12:33:59 2011
@@ -599,11 +599,15 @@
         ldmdb r4, {r5, r6}
         ldmdb r5!, {r3, r8}
         ldmea r5!, {r3, r8}
+        ldmdb.w r4, {r5, r6}
+        ldmdb.w r5!, {r3, r8}
 
 @ CHECK: ldmdb	r4, {r4, r5, r8, r9}    @ encoding: [0x14,0xe9,0x30,0x03]
 @ CHECK: ldmdb	r4, {r5, r6}            @ encoding: [0x14,0xe9,0x60,0x00]
 @ CHECK: ldmdb	r5!, {r3, r8}           @ encoding: [0x35,0xe9,0x08,0x01]
 @ CHECK: ldmdb	r5!, {r3, r8}           @ encoding: [0x35,0xe9,0x08,0x01]
+@ CHECK: ldmdb	r4, {r5, r6}            @ encoding: [0x14,0xe9,0x60,0x00]
+@ CHECK: ldmdb	r5!, {r3, r8}           @ encoding: [0x35,0xe9,0x08,0x01]
 
 
 @------------------------------------------------------------------------------



From enderby at apple.com  Thu Oct 27 12:40:42 2011
From: enderby at apple.com (Kevin Enderby)
Date: Thu, 27 Oct 2011 17:40:42 -0000
Subject: [llvm-commits] [llvm] r143112 - in /llvm/trunk:
 lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSystem.td
 test/MC/X86/x86-32-coverage.s test/MC/X86/x86-64.s test/MC/X86/x86_errors.s
Message-ID: <20111027174042.6CFBB3128060@llvm.org>

Author: enderby
Date: Thu Oct 27 12:40:41 2011
New Revision: 143112

URL: http://llvm.org/viewvc/llvm-project?rev=143112&view=rev
Log:
Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and
not depend on In32BitMode.  Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode.  rdar://9738584

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/lib/Target/X86/X86InstrSystem.td
    llvm/trunk/test/MC/X86/x86-32-coverage.s
    llvm/trunk/test/MC/X86/x86-64.s
    llvm/trunk/test/MC/X86/x86_errors.s

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=143112&r1=143111&r2=143112&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Oct 27 12:40:41 2011
@@ -1573,6 +1573,7 @@
 // System instruction aliases.
 def : MnemonicAlias<"iret", "iretl">;
 def : MnemonicAlias<"sysret", "sysretl">;
+def : MnemonicAlias<"sysexit", "sysexitl">;
 
 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;

Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=143112&r1=143111&r2=143112&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Thu Oct 27 12:40:41 2011
@@ -51,9 +51,8 @@
 
 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
                  
-def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
-                Requires<[In32BitMode]>;
-def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
+def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexitl", []>, TB;
+def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
                 Requires<[In64BitMode]>;
 
 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;

Modified: llvm/trunk/test/MC/X86/x86-32-coverage.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=143112&r1=143111&r2=143112&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32-coverage.s (original)
+++ llvm/trunk/test/MC/X86/x86-32-coverage.s Thu Oct 27 12:40:41 2011
@@ -500,6 +500,9 @@
 // CHECK: 	sysexit
         	sysexit
 
+// CHECK: 	sysexitl
+        	sysexitl
+
 // CHECK: 	ud2
         	ud2
 
@@ -4417,6 +4420,10 @@
 // CHECK:  encoding: [0x0f,0x35]
         	sysexit
 
+// CHECK: sysexitl
+// CHECK:  encoding: [0x0f,0x35]
+        	sysexitl
+
 // CHECK: fxsave	3735928559(%ebx,%ecx,8)
 // CHECK:  encoding: [0x0f,0xae,0x84,0xcb,0xef,0xbe,0xad,0xde]
         	fxsave	0xdeadbeef(%ebx,%ecx,8)

Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=143112&r1=143111&r2=143112&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Thu Oct 27 12:40:41 2011
@@ -1191,3 +1191,15 @@
 // CHECK: xchgl %ecx, %eax
 // CHECK: encoding: [0x91]
 xchgl %eax, %ecx
+
+// CHECK: sysexit
+// CHECK: encoding: [0x0f,0x35]
+sysexit
+
+// CHECK: sysexitl
+// CHECK: encoding: [0x0f,0x35]
+sysexitl
+
+// CHECK: sysexitq
+// CHECK: encoding: [0x48,0x0f,0x35]
+sysexitq

Modified: llvm/trunk/test/MC/X86/x86_errors.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_errors.s?rev=143112&r1=143111&r2=143112&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_errors.s (original)
+++ llvm/trunk/test/MC/X86/x86_errors.s Thu Oct 27 12:40:41 2011
@@ -18,3 +18,5 @@
 
 movl 0(%rax), 0(%edx)  // error: invalid operand for instruction
 
+// 32: error: instruction requires a CPU feature not currently enabled
+sysexitq



From grosbach at apple.com  Thu Oct 27 12:44:01 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 27 Oct 2011 17:44:01 -0000
Subject: [llvm-commits] [llvm] r143113 -
	/llvm/trunk/include/llvm/MC/MCRegisterInfo.h
Message-ID: <20111027174401.913073128060@llvm.org>

Author: grosbach
Date: Thu Oct 27 12:44:01 2011
New Revision: 143113

URL: http://llvm.org/viewvc/llvm-project?rev=143113&view=rev
Log:
Trailing whitespace.

Modified:
    llvm/trunk/include/llvm/MC/MCRegisterInfo.h

Modified: llvm/trunk/include/llvm/MC/MCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCRegisterInfo.h?rev=143113&r1=143112&r2=143113&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Thu Oct 27 12:44:01 2011
@@ -169,7 +169,7 @@
     else
       L2DwarfRegs[LLVMReg] = DwarfReg;
   }
-    
+
   /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
   /// register number mapping. Called by TableGen auto-generated routines.
   /// *DO NOT USE*.
@@ -179,7 +179,7 @@
     else
       Dwarf2LRegs[DwarfReg] = LLVMReg;
   }
-     
+
   /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
   /// number mapping. By default the SEH register number is just the same
   /// as the LLVM register number.
@@ -301,7 +301,7 @@
     return Classes[i];
   }
 };
- 
+
 } // End llvm namespace
 
 #endif



From bigcheesegs at gmail.com  Thu Oct 27 13:13:24 2011
From: bigcheesegs at gmail.com (Michael Spencer)
Date: Thu, 27 Oct 2011 11:13:24 -0700
Subject: [llvm-commits] [LLVM,
	llvm-objdump] Fix for clang-native-arm-cortex-a9.
In-Reply-To: <4EA991ED.5020805@narod.ru>
References: <4EA67DE3.8060803@narod.ru> <4EA7DF2B.2070100@narod.ru>
	<E7BD9520-EDC1-4BCB-8A99-8A30ECF1C370@apple.com>
	<4EA85830.8080701@narod.ru> <4EA991ED.5020805@narod.ru>
Message-ID: <CACXTSikAmDN4jjRxZfkDvaWOT1i2=MKck0waRknj9C4vaxgarQ@mail.gmail.com>

On Thu, Oct 27, 2011 at 10:16 AM, Stepan Dyatkovskiy <stpworld at narod.ru> wrote:
> Should I commit that?
>
> -Stepan.

Yes, please do.

- Michael Spencer

> Stepan Dyatkovskiy wrote:
>> Yes, I have.
>>
>> -Stepan.
>>
>> Bill Wendling wrote:
>>> This looks fine to me. Do you have commit access?
>>>
>>> -bw
>>>
>>> On Oct 26, 2011, at 3:21 AM, Stepan Dyatkovskiy wrote:
>>>
>>>> ping.
>>>>
>>>> Regards,
>>>> Stepan.
>>>>
>>>> Stepan Dyatkovskiy wrote:
>>>>> Hi all,
>>>>>
>>>>> Please find the patch in attachment that fixes llvm-objdump test
>>>>> failures for clang-native-arm-cortex-a9.
>>>>>
>>>>> Regards,
>>>>> Stepan.
>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu
>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>

From benny.kra at googlemail.com  Thu Oct 27 13:27:46 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 27 Oct 2011 18:27:46 -0000
Subject: [llvm-commits] [llvm] r143117 -
	/llvm/trunk/test/Analysis/ScalarEvolution/load.ll
Message-ID: <20111027182746.1B7CA3128060@llvm.org>

Author: d0k
Date: Thu Oct 27 13:27:45 2011
New Revision: 143117

URL: http://llvm.org/viewvc/llvm-project?rev=143117&view=rev
Log:
2>&1 doesn't work here, it just creates an empty file called "&1"

Modified:
    llvm/trunk/test/Analysis/ScalarEvolution/load.ll

Modified: llvm/trunk/test/Analysis/ScalarEvolution/load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/load.ll?rev=143117&r1=143116&r2=143117&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/load.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/load.ll Thu Oct 27 13:27:45 2011
@@ -1,4 +1,4 @@
-; RUN: opt -analyze -scalar-evolution < %s 2>&1 | FileCheck %s
+; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
 target triple = "i386-pc-linux-gnu"



From chandlerc at google.com  Thu Oct 27 13:40:39 2011
From: chandlerc at google.com (Chandler Carruth)
Date: Thu, 27 Oct 2011 11:40:39 -0700
Subject: [llvm-commits] [llvm] r143097 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/MC/ lib/CodeGen/AsmPrinter/ lib/MC/
 test/CodeGen/ARM/ test/CodeGen/X86/ test/DebugInfo/
In-Reply-To: <E9EC3800-F327-4902-9CCF-CA15EACBD39E@apple.com>
References: <20111027064411.6F491312800A@llvm.org>
	<E9EC3800-F327-4902-9CCF-CA15EACBD39E@apple.com>
Message-ID: <CAGCO0KjsWtj4EjaT5A+W_n8q6SW--FwBmBGHDPnO0xk6oZBQWw@mail.gmail.com>

On Thu, Oct 27, 2011 at 10:24 AM, Jim Grosbach <grosbach at apple.com> wrote:

> Hey Nick,
>
> This is great stuff. Thanks for doing this.
>
> I'm seeing a few test failures in the GCC test suite (
> https://llvm.org/svn/llvm-project/clang-tests/trunk/gcc-4_2-testsuite),
> though. It's fairly likely that they're just tests that need to be updated.
> Can you have a look?
>
> gcc.apple/block-debug-1.c scan-assembler __block_descriptor.*DW_AT_name
> gcc.apple/block-debug-1.c scan-assembler
> __block_literal_generic.*DW_AT_name
> gcc.apple/block-debug-2.c scan-assembler __block_descriptor.*DW_AT_name
> gcc.apple/block-debug-2.c scan-assembler
> __block_literal_generic.*DW_AT_name
> gcc.dg/debug/dwarf2/var1.c scan-assembler xyzzy[^\\n\\r]+DW_AT_name
>

I've tried to fix these with r143119. I'll watch the IRC messages from the
bot, hopefully the regular expression magic isn't too much for dejagnu...
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From stpworld at narod.ru  Thu Oct 27 13:40:45 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Thu, 27 Oct 2011 18:40:45 -0000
Subject: [llvm-commits] [llvm] r143120 -
	/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
Message-ID: <20111027184045.636953128060@llvm.org>

Author: dyatkovskiy
Date: Thu Oct 27 13:40:45 2011
New Revision: 143120

URL: http://llvm.org/viewvc/llvm-project?rev=143120&view=rev
Log:
Fixed llvm-objdump uint64_t formatted output.

Modified:
    llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp

Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=143120&r1=143119&r2=143120&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Thu Oct 27 13:40:45 2011
@@ -289,7 +289,7 @@
 
         if (DisAsm->getInstruction(Inst, Size, memoryObject, Index,
                                    DebugOut, nulls())) {
-          outs() << format("%8x:\t", SectionAddr + Index);
+          outs() << format("%8llx:\t", SectionAddr + Index);
           DumpBytes(StringRef(Bytes.data() + Index, Size));
           IP->printInst(&Inst, outs(), "");
           outs() << "\n";
@@ -316,7 +316,7 @@
           if (error(rel_cur->getTypeName(name))) goto skip_print_rel;
           if (error(rel_cur->getValueString(val))) goto skip_print_rel;
 
-          outs() << format("\t\t\t%8x: ", SectionAddr + addr) << name << "\t"
+          outs() << format("\t\t\t%8llx: ", SectionAddr + addr) << name << "\t"
                  << val << "\n";
 
         skip_print_rel:
@@ -400,7 +400,7 @@
 
     // Dump out the content as hex and printable ascii characters.
     for (std::size_t addr = 0, end = Contents.size(); addr < end; addr += 16) {
-      outs() << format(" %04x ", BaseAddr + addr);
+      outs() << format(" %04llx ", BaseAddr + addr);
       // Dump line of hex.
       for (std::size_t i = 0; i < 16; ++i) {
         if (i != 0 && i % 4 == 0)
@@ -506,7 +506,7 @@
       else if (Type == SymbolRef::ST_Function)
         FileFunc = 'F';
 
-      outs() << format("%08x", Offset) << " "
+      outs() << format("%08llx", Offset) << " "
              << GlobLoc // Local -> 'l', Global -> 'g', Neither -> ' '
              << (Weak ? 'w' : ' ') // Weak?
              << ' ' // Constructor. Not supported yet.
@@ -526,7 +526,7 @@
         outs() << SectionName;
       }
       outs() << '\t'
-             << format("%08x ", Size)
+             << format("%08llx ", Size)
              << Name
              << '\n';
     }



From stpworld at narod.ru  Thu Oct 27 13:44:48 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Thu, 27 Oct 2011 22:44:48 +0400
Subject: [llvm-commits] [LLVM,
	llvm-objdump] Fix for clang-native-arm-cortex-a9.
In-Reply-To: <CACXTSikAmDN4jjRxZfkDvaWOT1i2=MKck0waRknj9C4vaxgarQ@mail.gmail.com>
References: <4EA67DE3.8060803@narod.ru> <4EA7DF2B.2070100@narod.ru>
	<E7BD9520-EDC1-4BCB-8A99-8A30ECF1C370@apple.com>
	<4EA85830.8080701@narod.ru> <4EA991ED.5020805@narod.ru>
	<CACXTSikAmDN4jjRxZfkDvaWOT1i2=MKck0waRknj9C4vaxgarQ@mail.gmail.com>
Message-ID: <4EA9A6A0.7000206@narod.ru>

Commited as r143120.

Regards,
Stepan.

Michael Spencer wrote:
> On Thu, Oct 27, 2011 at 10:16 AM, Stepan Dyatkovskiy<stpworld at narod.ru>  wrote:
>> Should I commit that?
>>
>> -Stepan.
>
> Yes, please do.
>
> - Michael Spencer
>
>> Stepan Dyatkovskiy wrote:
>>> Yes, I have.
>>>
>>> -Stepan.
>>>
>>> Bill Wendling wrote:
>>>> This looks fine to me. Do you have commit access?
>>>>
>>>> -bw
>>>>
>>>> On Oct 26, 2011, at 3:21 AM, Stepan Dyatkovskiy wrote:
>>>>
>>>>> ping.
>>>>>
>>>>> Regards,
>>>>> Stepan.
>>>>>
>>>>> Stepan Dyatkovskiy wrote:
>>>>>> Hi all,
>>>>>>
>>>>>> Please find the patch in attachment that fixes llvm-objdump test
>>>>>> failures for clang-native-arm-cortex-a9.
>>>>>>
>>>>>> Regards,
>>>>>> Stepan.
>>>>>>
>>>>>>
>>>>>> _______________________________________________
>>>>>> llvm-commits mailing list
>>>>>> llvm-commits at cs.uiuc.edu
>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>
>>>>> _______________________________________________
>>>>> llvm-commits mailing list
>>>>> llvm-commits at cs.uiuc.edu
>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>


From baldrick at free.fr  Thu Oct 27 14:16:21 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 27 Oct 2011 19:16:21 -0000
Subject: [llvm-commits] [llvm] r143125 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp lib/Analysis/ValueTracking.cpp
 test/Transforms/InstSimplify/2011-10-27-BinOpCrash.ll
 test/Transforms/InstSimplify/compare.ll
Message-ID: <20111027191621.5EB953128060@llvm.org>

Author: baldrick
Date: Thu Oct 27 14:16:21 2011
New Revision: 143125

URL: http://llvm.org/viewvc/llvm-project?rev=143125&view=rev
Log:
Reapply commit 143028 with a fix: the problem was casting a ConstantExpr Mul
using BinaryOperator (which only works for instructions) when it should have
been a cast to OverflowingBinaryOperator (which also works for constants).
While there, correct a few other dubious looking uses of BinaryOperator.
Thanks to Chad Rosier for the testcase.  Original commit message:
My super-optimizer noticed that we weren't folding this expression to
true: (x *nsw x) sgt 0, where x = (y | 1).  This occurs in 464.h264ref.

Added:
    llvm/trunk/test/Transforms/InstSimplify/2011-10-27-BinOpCrash.ll
Modified:
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp
    llvm/trunk/lib/Analysis/ValueTracking.cpp
    llvm/trunk/test/Transforms/InstSimplify/compare.ll

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=143125&r1=143124&r2=143125&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Oct 27 14:16:21 2011
@@ -758,7 +758,8 @@
   Value *X = 0, *Y = 0;
   if ((match(Op0, m_IDiv(m_Value(X), m_Value(Y))) && Y == Op1) || // (X / Y) * Y
       (match(Op1, m_IDiv(m_Value(X), m_Value(Y))) && Y == Op0)) { // Y * (X / Y)
-    BinaryOperator *Div = cast<BinaryOperator>(Y == Op1 ? Op0 : Op1);
+    PossiblyExactOperator *Div =
+      cast<PossiblyExactOperator>(Y == Op1 ? Op0 : Op1);
     if (Div->isExact())
       return X;
   }
@@ -842,7 +843,7 @@
   Value *X = 0, *Y = 0;
   if (match(Op0, m_Mul(m_Value(X), m_Value(Y))) && (X == Op1 || Y == Op1)) {
     if (Y != Op1) std::swap(X, Y); // Ensure expression is (X * Y) / Y, Y = Op1
-    BinaryOperator *Mul = cast<BinaryOperator>(Op0);
+    OverflowingBinaryOperator *Mul = cast<OverflowingBinaryOperator>(Op0);
     // If the Mul knows it does not overflow, then we are good to go.
     if ((isSigned && Mul->hasNoSignedWrap()) ||
         (!isSigned && Mul->hasNoUnsignedWrap()))

Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=143125&r1=143124&r2=143125&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Thu Oct 27 14:16:21 2011
@@ -201,9 +201,36 @@
     ComputeMaskedBits(I->getOperand(1), Mask2, KnownZero, KnownOne, TD,Depth+1);
     ComputeMaskedBits(I->getOperand(0), Mask2, KnownZero2, KnownOne2, TD,
                       Depth+1);
-    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 
-    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 
-    
+    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
+
+    bool isKnownNegative = false;
+    bool isKnownNonNegative = false;
+    // If the multiplication is known not to overflow, compute the sign bit.
+    if (Mask.isNegative() &&
+        cast<OverflowingBinaryOperator>(I)->hasNoSignedWrap()) {
+      Value *Op1 = I->getOperand(1), *Op2 = I->getOperand(0);
+      if (Op1 == Op2) {
+        // The product of a number with itself is non-negative.
+        isKnownNonNegative = true;
+      } else {
+        bool isKnownNonNegative1 = KnownZero.isNegative();
+        bool isKnownNonNegative2 = KnownZero2.isNegative();
+        bool isKnownNegative1 = KnownOne.isNegative();
+        bool isKnownNegative2 = KnownOne2.isNegative();
+        // The product of two numbers with the same sign is non-negative.
+        isKnownNonNegative = (isKnownNegative1 && isKnownNegative2) ||
+          (isKnownNonNegative1 && isKnownNonNegative2);
+        // The product of a negative number and a non-negative number is either
+        // negative or zero.
+        if (!isKnownNonNegative)
+          isKnownNegative = (isKnownNegative1 && isKnownNonNegative2 &&
+                             isKnownNonZero(Op2, TD, Depth)) ||
+                            (isKnownNegative2 && isKnownNonNegative1 &&
+                             isKnownNonZero(Op1, TD, Depth));
+      }
+    }
+
     // If low bits are zero in either operand, output low known-0 bits.
     // Also compute a conserative estimate for high known-0 bits.
     // More trickiness is possible, but this is sufficient for the
@@ -220,6 +247,12 @@
     KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) |
                 APInt::getHighBitsSet(BitWidth, LeadZ);
     KnownZero &= Mask;
+
+    if (isKnownNonNegative)
+      KnownZero.setBit(BitWidth - 1);
+    else if (isKnownNegative)
+      KnownOne.setBit(BitWidth - 1);
+
     return;
   }
   case Instruction::UDiv: {
@@ -784,7 +817,7 @@
   }
 
   // The remaining tests are all recursive, so bail out if we hit the limit.
-  if (Depth++ == MaxDepth)
+  if (Depth++ >= MaxDepth)
     return false;
 
   unsigned BitWidth = getBitWidth(V->getType(), TD);
@@ -802,7 +835,7 @@
   // if the lowest bit is shifted off the end.
   if (BitWidth && match(V, m_Shl(m_Value(X), m_Value(Y)))) {
     // shl nuw can't remove any non-zero bits.
-    BinaryOperator *BO = cast<BinaryOperator>(V);
+    OverflowingBinaryOperator *BO = cast<OverflowingBinaryOperator>(V);
     if (BO->hasNoUnsignedWrap())
       return isKnownNonZero(X, TD, Depth);
 
@@ -816,7 +849,7 @@
   // defined if the sign bit is shifted off the end.
   else if (match(V, m_Shr(m_Value(X), m_Value(Y)))) {
     // shr exact can only shift out zero bits.
-    BinaryOperator *BO = cast<BinaryOperator>(V);
+    PossiblyExactOperator *BO = cast<PossiblyExactOperator>(V);
     if (BO->isExact())
       return isKnownNonZero(X, TD, Depth);
 
@@ -827,7 +860,7 @@
   }
   // div exact can only produce a zero if the dividend is zero.
   else if (match(V, m_IDiv(m_Value(X), m_Value()))) {
-    BinaryOperator *BO = cast<BinaryOperator>(V);
+    PossiblyExactOperator *BO = cast<PossiblyExactOperator>(V);
     if (BO->isExact())
       return isKnownNonZero(X, TD, Depth);
   }
@@ -868,6 +901,15 @@
     if (YKnownNonNegative && isPowerOfTwo(X, TD, /*OrZero*/false, Depth))
       return true;
   }
+  // X * Y.
+  else if (match(V, m_Mul(m_Value(X), m_Value(Y)))) {
+    OverflowingBinaryOperator *BO = cast<OverflowingBinaryOperator>(V);
+    // If X and Y are non-zero then so is X * Y as long as the multiplication
+    // does not overflow.
+    if ((BO->hasNoSignedWrap() || BO->hasNoUnsignedWrap()) &&
+        isKnownNonZero(X, TD, Depth) && isKnownNonZero(Y, TD, Depth))
+      return true;
+  }
   // (C ? X : Y) != 0 if X != 0 and Y != 0.
   else if (SelectInst *SI = dyn_cast<SelectInst>(V)) {
     if (isKnownNonZero(SI->getTrueValue(), TD, Depth) &&

Added: llvm/trunk/test/Transforms/InstSimplify/2011-10-27-BinOpCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/2011-10-27-BinOpCrash.ll?rev=143125&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/2011-10-27-BinOpCrash.ll (added)
+++ llvm/trunk/test/Transforms/InstSimplify/2011-10-27-BinOpCrash.ll Thu Oct 27 14:16:21 2011
@@ -0,0 +1,12 @@
+; RUN: opt < %s -instcombine
+
+ at _ZN11xercesc_2_5L11gDigitCharsE = external constant [32 x i16], align 2
+ at _ZN11xercesc_2_5L10gBaseCharsE = external constant [354 x i16], align 2
+ at _ZN11xercesc_2_5L17gIdeographicCharsE = external constant [7 x i16], align 2
+ at _ZN11xercesc_2_5L15gCombiningCharsE = external constant [163 x i16], align 2
+
+define i32 @_ZN11xercesc_2_515XMLRangeFactory11buildRangesEv(i32 %x) {
+  %a = add i32 %x, add (i32 add (i32 ashr (i32 add (i32 mul (i32 ptrtoint ([32 x i16]* @_ZN11xercesc_2_5L11gDigitCharsE to i32), i32 -1), i32 ptrtoint (i16* getelementptr inbounds ([32 x i16]* @_ZN11xercesc_2_5L11gDigitCharsE, i32 0, i32 30) to i32)), i32 1), i32 ashr (i32 add (i32 mul (i32 ptrtoint ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE to i32), i32 -1), i32 ptrtoint (i16* getelementptr inbounds ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE, i32 0, i32 4) to i32)), i32 1)), i32 8)
+  %b = add i32 %a, %x
+  ret i32 %b
+}

Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=143125&r1=143124&r2=143125&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Thu Oct 27 14:16:21 2011
@@ -323,3 +323,34 @@
   ret i1 %B
 ; CHECK: ret i1 false
 }
+
+define i1 @mul1(i32 %X) {
+; CHECK: @mul1
+; Square of a non-zero number is non-zero if there is no overflow.
+  %Y = or i32 %X, 1
+  %M = mul nuw i32 %Y, %Y
+  %C = icmp eq i32 %M, 0
+  ret i1 %C
+; CHECK: ret i1 false
+}
+
+define i1 @mul2(i32 %X) {
+; CHECK: @mul2
+; Square of a non-zero number is positive if there is no signed overflow.
+  %Y = or i32 %X, 1
+  %M = mul nsw i32 %Y, %Y
+  %C = icmp sgt i32 %M, 0
+  ret i1 %C
+; CHECK: ret i1 true
+}
+
+define i1 @mul3(i32 %X, i32 %Y) {
+; CHECK: @mul3
+; Product of non-negative numbers is non-negative if there is no signed overflow.
+  %XX = mul nsw i32 %X, %X
+  %YY = mul nsw i32 %Y, %Y
+  %M = mul nsw i32 %XX, %YY
+  %C = icmp sge i32 %M, 0
+  ret i1 %C
+; CHECK: ret i1 true
+}



From peter at pcc.me.uk  Thu Oct 27 14:19:07 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Thu, 27 Oct 2011 19:19:07 -0000
Subject: [llvm-commits] [llvm] r143134 - in /llvm/trunk/docs:
	GetElementPtr.html LangRef.html
Message-ID: <20111027191908.3C2E33128060@llvm.org>

Author: pcc
Date: Thu Oct 27 14:19:07 2011
New Revision: 143134

URL: http://llvm.org/viewvc/llvm-project?rev=143134&view=rev
Log:
Document tbaa metadata in LangRef (documentation largely based on
comments at top of TypeBasedAliasAnalysis.cpp).

Modified:
    llvm/trunk/docs/GetElementPtr.html
    llvm/trunk/docs/LangRef.html

Modified: llvm/trunk/docs/GetElementPtr.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GetElementPtr.html?rev=143134&r1=143133&r2=143134&view=diff
==============================================================================
--- llvm/trunk/docs/GetElementPtr.html (original)
+++ llvm/trunk/docs/GetElementPtr.html Thu Oct 27 14:19:07 2011
@@ -594,10 +594,10 @@
      because LLVM has no restrictions on mixing types in addressing, loads or
      stores.</p>
 
-  <p>It would be possible to add special annotations to the IR, probably using
-     metadata, to describe a different type system (such as the C type system),
-     and do type-based aliasing on top of that. This is a much bigger
-     undertaking though.</p>
+  <p>LLVM's type-based alias analysis pass uses metadata to describe a different
+     type system (such as the C type system), and performs type-based aliasing
+     on top of that.  Further details are in the
+     <a href="LangRef.html#tbaa">language reference</a>.</p>
 
 </div>
 

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=143134&r1=143133&r2=143134&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Thu Oct 27 14:19:07 2011
@@ -100,7 +100,11 @@
   <li><a href="#othervalues">Other Values</a>
     <ol>
       <li><a href="#inlineasm">Inline Assembler Expressions</a></li>
-      <li><a href="#metadata">Metadata Nodes and Metadata Strings</a></li>
+      <li><a href="#metadata">Metadata Nodes and Metadata Strings</a>
+        <ol>
+          <li><a href="#tbaa">'<tt>tbaa</tt>' Metadata</a></li>
+        </ol>
+      </li>
     </ol>
   </li>
   <li><a href="#intrinsic_globals">Intrinsic Global Variables</a>
@@ -2915,6 +2919,53 @@
 </pre>
 </div>
 
+<p>More information about specific metadata nodes recognized by the optimizers
+   and code generator is found below.</p>
+
+<h4>
+  <a name="tbaa">'<tt>tbaa</tt>' Metadata</a>
+</h4>
+
+<div>
+
+<p>In LLVM IR, memory does not have types, so LLVM's own type system is not
+   suitable for doing TBAA. Instead, metadata is added to the IR to describe
+   a type system of a higher level language. This can be used to implement
+   typical C/C++ TBAA, but it can also be used to implement custom alias
+   analysis behavior for other languages.</p>
+
+<p>The current metadata format is very simple. TBAA metadata nodes have up to
+   three fields, e.g.:</p>
+
+<div class="doc_code">
+<pre>
+!0 = metadata !{ metadata !"an example type tree" }
+!1 = metadata !{ metadata !"int", metadata !0 }
+!2 = metadata !{ metadata !"float", metadata !0 }
+!3 = metadata !{ metadata !"const float", metadata !2, i64 1 }
+</pre>
+</div>
+
+<p>The first field is an identity field. It can be any value, usually
+   a metadata string, which uniquely identifies the type. The most important
+   name in the tree is the name of the root node. Two trees with
+   different root node names are entirely disjoint, even if they
+   have leaves with common names.</p>
+
+<p>The second field identifies the type's parent node in the tree, or
+   is null or omitted for a root node. A type is considered to alias
+   all of its descendants and all of its ancestors in the tree. Also,
+   a type is considered to alias all types in other trees, so that
+   bitcode produced from multiple front-ends is handled conservatively.</p>
+
+<p>If the third field is present, it's an integer which if equal to 1
+   indicates that the type is "constant" (meaning
+   <tt>pointsToConstantMemory</tt> should return true; see
+   <a href="AliasAnalysis.html#OtherItfs">other useful
+   <tt>AliasAnalysis</tt> methods</a>).</p>
+
+</div>
+
 </div>
 
 </div>



From peter at pcc.me.uk  Thu Oct 27 14:19:14 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Thu, 27 Oct 2011 19:19:14 -0000
Subject: [llvm-commits] [llvm] r143135 - in /llvm/trunk: docs/LangRef.html
 include/llvm/LLVMContext.h lib/VMCore/LLVMContext.cpp
Message-ID: <20111027191915.002033128060@llvm.org>

Author: pcc
Date: Thu Oct 27 14:19:14 2011
New Revision: 143135

URL: http://llvm.org/viewvc/llvm-project?rev=143135&view=rev
Log:
Add a pinned metadata name for fpaccuracy, and document it

Modified:
    llvm/trunk/docs/LangRef.html
    llvm/trunk/include/llvm/LLVMContext.h
    llvm/trunk/lib/VMCore/LLVMContext.cpp

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=143135&r1=143134&r2=143135&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Thu Oct 27 14:19:14 2011
@@ -103,6 +103,7 @@
       <li><a href="#metadata">Metadata Nodes and Metadata Strings</a>
         <ol>
           <li><a href="#tbaa">'<tt>tbaa</tt>' Metadata</a></li>
+          <li><a href="#fpaccuracy">'<tt>fpaccuracy</tt>' Metadata</a></li>
         </ol>
       </li>
     </ol>
@@ -2966,6 +2967,35 @@
 
 </div>
 
+<h4>
+  <a name="fpaccuracy">'<tt>fpaccuracy</tt>' Metadata</a>
+</h4>
+ 
+<div>
+
+<p><tt>fpaccuracy</tt> metadata may be attached to any instruction of floating
+   point type.  It expresses the maximum relative error of the result of
+   that instruction, in ULPs. ULP is defined as follows:</p>
+
+<blockquote><p>
+If x is a real number that lies between two finite consecutive floating-point
+numbers a and b, without being equal to one of them, then ulp(x) = |b - a|,
+otherwise ulp(x) is the distance between the two non-equal finite
+floating-point numbers nearest x. Moreover, ulp(NaN) is NaN.
+</p></blockquote>
+
+<p>The maximum relative error may be any rational number.  The metadata node
+   shall consist of a pair of unsigned integers respectively representing
+   the numerator and denominator.  For example, 2.5 ULP:</p>
+
+<div class="doc_code">
+<pre>
+!0 = metadata !{ i32 5, i32 2 }
+</pre>
+</div>
+
+</div>
+
 </div>
 
 </div>

Modified: llvm/trunk/include/llvm/LLVMContext.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=143135&r1=143134&r2=143135&view=diff
==============================================================================
--- llvm/trunk/include/llvm/LLVMContext.h (original)
+++ llvm/trunk/include/llvm/LLVMContext.h Thu Oct 27 14:19:14 2011
@@ -40,7 +40,8 @@
   enum {
     MD_dbg = 0,  // "dbg"
     MD_tbaa = 1, // "tbaa"
-    MD_prof = 2  // "prof"
+    MD_prof = 2,  // "prof"
+    MD_fpaccuracy = 3  // "fpaccuracy"
   };
   
   /// getMDKindID - Return a unique non-zero ID for the specified metadata kind.

Modified: llvm/trunk/lib/VMCore/LLVMContext.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContext.cpp?rev=143135&r1=143134&r2=143135&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/LLVMContext.cpp (original)
+++ llvm/trunk/lib/VMCore/LLVMContext.cpp Thu Oct 27 14:19:14 2011
@@ -43,6 +43,11 @@
   // Create the 'prof' metadata kind.
   unsigned ProfID = getMDKindID("prof");
   assert(ProfID == MD_prof && "prof kind id drifted"); (void)ProfID;
+
+  // Create the 'fpaccuracy' metadata kind.
+  unsigned FPAccuracyID = getMDKindID("fpaccuracy");
+  assert(FPAccuracyID == MD_fpaccuracy && "fpaccuracy kind id drifted");
+  (void)FPAccuracyID;
 }
 LLVMContext::~LLVMContext() { delete pImpl; }
 



From resistor at mac.com  Thu Oct 27 15:46:10 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 27 Oct 2011 20:46:10 -0000
Subject: [llvm-commits] [llvm] r143140 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20111027204610.158543128060@llvm.org>

Author: resistor
Date: Thu Oct 27 15:46:09 2011
New Revision: 143140

URL: http://llvm.org/viewvc/llvm-project?rev=143140&view=rev
Log:
Fix pretty printing of i386 local sect diff relocations, TLV relocations, and x86_64 TLV relocations in MachO.

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=143140&r1=143139&r2=143140&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Thu Oct 27 15:46:09 2011
@@ -675,10 +675,11 @@
         "GENERIC_RELOC_VANILLA",
         "GENERIC_RELOC_PAIR",
         "GENERIC_RELOC_SECTDIFF",
+        "GENERIC_RELOC_PB_LA_PTR",
         "GENERIC_RELOC_LOCAL_SECTDIFF",
-        "GENERIC_RELOC_PB_LA_PTR" };
+        "GENERIC_RELOC_TLV" };
 
-      if (r_type > 4)
+      if (r_type > 6)
         res = "Unknown";
       else
         res = Table[r_type];
@@ -859,6 +860,12 @@
   else
     Type = (RE->Word1 >> 28) & 0xF;
 
+  bool isPCRel;
+  if (isScattered)
+    isPCRel = ((RE->Word0 >> 30) & 1);
+  else
+    isPCRel = ((RE->Word1 >> 24) & 1);
+
   // Determine any addends that should be displayed with the relocation.
   // These require decoding the relocation type, which is triple-specific.
 
@@ -894,6 +901,11 @@
         fmt << "-";
         printRelocationTargetName(RE, fmt);
       }
+      case macho::RIT_X86_64_TLV:
+        printRelocationTargetName(RE, fmt);
+        fmt << "@TLV";
+        if (isPCRel) fmt << "P";
+        break;
       case macho::RIT_X86_64_Signed1: // X86_64_RELOC_SIGNED1
         printRelocationTargetName(RE, fmt);
         fmt << "-1";
@@ -916,8 +928,7 @@
     switch (Type) {
       case macho::RIT_Pair: // GENERIC_RELOC_PAIR - prints no info
         return object_error::success;
-      case macho::RIT_Difference:                // GENERIC_RELOC_SECTDIFF
-      case macho::RIT_Generic_LocalDifference: { // GENERIC_RELOC_LOCAL_SECTDIFF
+      case macho::RIT_Difference: { // GENERIC_RELOC_SECTDIFF
         InMemoryStruct<macho::RelocationEntry> RENext;
         DataRefImpl RelNext = Rel;
         RelNext.d.a++;
@@ -934,8 +945,7 @@
           RType = (RENext->Word1 >> 28) & 0xF;
         if (RType != 1)
           report_fatal_error("Expected GENERIC_RELOC_PAIR after "
-                             "GENERIC_RELOC_SECTDIFF or "
-                             "GENERIC_RELOC_LOCAL_SECTDIFF.");
+                             "GENERIC_RELOC_SECTDIFF.");
 
         printRelocationTargetName(RE, fmt);
         fmt << "-";
@@ -947,7 +957,40 @@
     if (Arch == Triple::x86) {
       // All X86 relocations that need special printing were already
       // handled in the generic code.
-      printRelocationTargetName(RE, fmt);
+      switch (Type) {
+        case macho::RIT_Generic_LocalDifference:{// GENERIC_RELOC_LOCAL_SECTDIFF
+          InMemoryStruct<macho::RelocationEntry> RENext;
+          DataRefImpl RelNext = Rel;
+          RelNext.d.a++;
+          getRelocation(RelNext, RENext);
+
+          // X86 sect diff's must be followed by a relocation of type
+          // GENERIC_RELOC_PAIR.
+          bool isNextScattered = (Arch != Triple::x86_64) &&
+                               (RENext->Word0 & macho::RF_Scattered);
+          unsigned RType;
+          if (isNextScattered)
+            RType = (RENext->Word0 >> 24) & 0xF;
+          else
+            RType = (RENext->Word1 >> 28) & 0xF;
+          if (RType != 1)
+            report_fatal_error("Expected GENERIC_RELOC_PAIR after "
+                               "GENERIC_RELOC_LOCAL_SECTDIFF.");
+
+          printRelocationTargetName(RE, fmt);
+          fmt << "-";
+          printRelocationTargetName(RENext, fmt);
+          break;
+        }
+        case macho::RIT_Generic_TLV: {
+          printRelocationTargetName(RE, fmt);
+          fmt << "@TLV";
+          if (isPCRel) fmt << "P";
+          break;
+        }
+        default:
+          printRelocationTargetName(RE, fmt);
+      }
     } else { // ARM-specific relocations
       switch (Type) {
         case macho::RIT_ARM_Half:             // ARM_RELOC_HALF



From nicholas at mxc.ca  Thu Oct 27 15:53:56 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 27 Oct 2011 13:53:56 -0700
Subject: [llvm-commits] [llvm] r143097 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/MC/ lib/CodeGen/AsmPrinter/ lib/MC/
 test/CodeGen/ARM/ test/CodeGen/X86/ test/DebugInfo/
In-Reply-To: <CAGCO0KjsWtj4EjaT5A+W_n8q6SW--FwBmBGHDPnO0xk6oZBQWw@mail.gmail.com>
References: <20111027064411.6F491312800A@llvm.org>	<E9EC3800-F327-4902-9CCF-CA15EACBD39E@apple.com>
	<CAGCO0KjsWtj4EjaT5A+W_n8q6SW--FwBmBGHDPnO0xk6oZBQWw@mail.gmail.com>
Message-ID: <4EA9C4E4.20500@mxc.ca>

Chandler Carruth wrote:
> On Thu, Oct 27, 2011 at 10:24 AM, Jim Grosbach <grosbach at apple.com
> <mailto:grosbach at apple.com>> wrote:
>
>     Hey Nick,
>
>     This is great stuff. Thanks for doing this.
>
>     I'm seeing a few test failures in the GCC test suite
>     (https://llvm.org/svn/llvm-project/clang-tests/trunk/gcc-4_2-testsuite),
>     though. It's fairly likely that they're just tests that need to be
>     updated. Can you have a look?
>
>     gcc.apple/block-debug-1.c scan-assembler __block_descriptor.*DW_AT_name
>     gcc.apple/block-debug-1.c scan-assembler
>     __block_literal_generic.*DW_AT_name
>     gcc.apple/block-debug-2.c scan-assembler __block_descriptor.*DW_AT_name
>     gcc.apple/block-debug-2.c scan-assembler
>     __block_literal_generic.*DW_AT_name
>     gcc.dg/debug/dwarf2/var1.c scan-assembler xyzzy[^\\n\\r]+DW_AT_name
>
>
> I've tried to fix these with r143119. I'll watch the IRC messages from
> the bot, hopefully the regular expression magic isn't too much for
> dejagnu...

Thank you!!

Nick

From nicholas at mxc.ca  Thu Oct 27 15:55:07 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 27 Oct 2011 13:55:07 -0700
Subject: [llvm-commits] [llvm] r143117
	-	/llvm/trunk/test/Analysis/ScalarEvolution/load.ll
In-Reply-To: <20111027182746.1B7CA3128060@llvm.org>
References: <20111027182746.1B7CA3128060@llvm.org>
Message-ID: <4EA9C52B.8050708@mxc.ca>

Benjamin Kramer wrote:
> Author: d0k
> Date: Thu Oct 27 13:27:45 2011
> New Revision: 143117
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143117&view=rev
> Log:
> 2>&1 doesn't work here, it just creates an empty file called "&1"

Whoops! This doesn't even output to stderr. Thanks!

Nick

>
> Modified:
>      llvm/trunk/test/Analysis/ScalarEvolution/load.ll
>
> Modified: llvm/trunk/test/Analysis/ScalarEvolution/load.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/load.ll?rev=143117&r1=143116&r2=143117&view=diff
> ==============================================================================
> --- llvm/trunk/test/Analysis/ScalarEvolution/load.ll (original)
> +++ llvm/trunk/test/Analysis/ScalarEvolution/load.ll Thu Oct 27 13:27:45 2011
> @@ -1,4 +1,4 @@
> -; RUN: opt -analyze -scalar-evolution<  %s 2>&1 | FileCheck %s
> +; RUN: opt -analyze -scalar-evolution<  %s | FileCheck %s
>
>   target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
>   target triple = "i386-pc-linux-gnu"
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From daniel at zuster.org  Thu Oct 27 15:59:19 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 27 Oct 2011 20:59:19 -0000
Subject: [llvm-commits] [llvm] r143141 - in
 /llvm/trunk/utils/lit/lit/ExampleTests: LLVM.InTree/test/lit.cfg
 LLVM.InTree/test/site.exp LLVM.OutOfTree/obj/test/site.exp
 LLVM.OutOfTree/src/test/lit.cfg
Message-ID: <20111027205919.567B23128060@llvm.org>

Author: ddunbar
Date: Thu Oct 27 15:59:19 2011
New Revision: 143141

URL: http://llvm.org/viewvc/llvm-project?rev=143141&view=rev
Log:
lit: Drop some unneeded code from example tests.
 - Also, cleanup site.exp files in example tests.

Modified:
    llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/lit.cfg
    llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
    llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
    llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/src/test/lit.cfg

Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/lit.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/lit.cfg?rev=143141&r1=143140&r2=143141&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/lit.cfg (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/lit.cfg Thu Oct 27 15:59:19 2011
@@ -75,16 +75,6 @@
     if m:
         site_exp[m.group(1)] = m.group(2)
 
-# Add substitutions.
-for sub in ['prcontext', 'llvmgcc', 'llvmgxx', 'compile_cxx', 'compile_c',
-            'link', 'shlibext', 'ocamlopt', 'llvmdsymutil', 'llvmlibsdir',
-            'bugpoint_topts']:
-    if sub in ('llvmgcc', 'llvmgxx'):
-        config.substitutions.append(('%' + sub,
-                                     site_exp[sub] + ' -emit-llvm -w'))
-    else:
-        config.substitutions.append(('%' + sub, site_exp[sub]))
-
 excludes = []
 
 # Provide target_triple for use in XFAIL and XTARGET.
@@ -95,10 +85,6 @@
 def llvm_supports_target(name):
     return name in targets
 
-langs = set(site_exp['llvmgcc_langs'].split(','))
-def llvm_gcc_supports(name):
-    return name in langs
-
 # Provide on_clone hook for reading 'dg.exp'.
 import os
 simpleLibData = re.compile(r"""load_lib llvm.exp

Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp?rev=143141&r1=143140&r2=143141&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp Thu Oct 27 15:59:19 2011
@@ -2,27 +2,9 @@
 # Do not edit here.  If you wish to override these values
 # edit the last section
 set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 CBackend MSIL CppBackend"
-set llvmgcc_langs "c,c++,objc,obj-c++"
-set prcontext "/usr/bin/tclsh8.4 /Volumes/Data/ddunbar/llvm/test/Scripts/prcontext.tcl"
-set llvmtoolsdir "/Users/ddunbar/llvm.obj.64/Debug/bin"
-set llvmlibsdir "/Users/ddunbar/llvm.obj.64/Debug/lib"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
 set srcroot "/Volumes/Data/ddunbar/llvm"
 set objroot "/Volumes/Data/ddunbar/llvm.obj.64"
 set srcdir "/Volumes/Data/ddunbar/llvm/test"
 set objdir "/Volumes/Data/ddunbar/llvm.obj.64/test"
-set gccpath "/usr/bin/gcc -arch x86_64"
-set gxxpath "/usr/bin/g++ -arch x86_64"
-set compile_c " /usr/bin/gcc -arch x86_64 -I/Users/ddunbar/llvm.obj.64/include -I/Users/ddunbar/llvm.obj.64/test -I/Volumes/Data/ddunbar/llvm.obj.64/include -I/Volumes/Data/ddunbar/llvm/include -I/Volumes/Data/ddunbar/llvm/test -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -m64 -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -c "
-set compile_cxx " /usr/bin/g++ -arch x86_64 -I/Users/ddunbar/llvm.obj.64/include -I/Users/ddunbar/llvm.obj.64/test -I/Volumes/Data/ddunbar/llvm.obj.64/include -I/Volumes/Data/ddunbar/llvm/include -I/Volumes/Data/ddunbar/llvm/test -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -g -fno-exceptions -fno-common -Woverloaded-virtual -m64 -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -c "
-set link " /usr/bin/g++ -arch x86_64 -I/Users/ddunbar/llvm.obj.64/include -I/Users/ddunbar/llvm.obj.64/test -I/Volumes/Data/ddunbar/llvm.obj.64/include -I/Volumes/Data/ddunbar/llvm/include -I/Volumes/Data/ddunbar/llvm/test -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -g -fno-exceptions -fno-common -Woverloaded-virtual -m64 -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -g -L/Users/ddunbar/llvm.obj.64/Debug/lib -L/Volumes/Data/ddunbar/llvm.obj.64/Debug/lib "
-set llvmgcc "/Users/ddunbar/llvm-gcc/install/bin/llvm-gcc -m64 "
-set llvmgxx "/Users/ddunbar/llvm-gcc/install/bin/llvm-gcc -m64 "
-set bugpoint_topts "-gcc-tool-args -m64"
-set shlibext ".dylib"
-set ocamlopt "/sw/bin/ocamlopt -cc \"g++ -Wall -D_FILE_OFFSET_BITS=64 -D_REENTRANT\" -I /Users/ddunbar/llvm.obj.64/Debug/lib/ocaml"
-set valgrind ""
-set grep "/usr/bin/grep"
-set gas "/usr/bin/as"
-set llvmdsymutil "dsymutil"
 ## All variables above are generated by configure. Do Not Edit ## 

Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp?rev=143141&r1=143140&r2=143141&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp Thu Oct 27 15:59:19 2011
@@ -2,27 +2,9 @@
 # Do not edit here.  If you wish to override these values
 # edit the last section
 set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 CBackend MSIL CppBackend"
-set llvmgcc_langs "c,c++,objc,obj-c++"
-set prcontext "/usr/bin/tclsh8.4 /Volumes/Data/ddunbar/llvm/test/Scripts/prcontext.tcl"
-set llvmtoolsdir "/Users/ddunbar/llvm.obj.64/Debug/bin"
-set llvmlibsdir "/Users/ddunbar/llvm.obj.64/Debug/lib"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
 set srcroot "/Volumes/Data/ddunbar/llvm"
 set objroot "/Volumes/Data/ddunbar/llvm.obj.64"
 set srcdir "/Volumes/Data/ddunbar/llvm/test"
 set objdir "/Volumes/Data/ddunbar/llvm.obj.64/test"
-set gccpath "/usr/bin/gcc -arch x86_64"
-set gxxpath "/usr/bin/g++ -arch x86_64"
-set compile_c " /usr/bin/gcc -arch x86_64 -I/Users/ddunbar/llvm.obj.64/include -I/Users/ddunbar/llvm.obj.64/test -I/Volumes/Data/ddunbar/llvm.obj.64/include -I/Volumes/Data/ddunbar/llvm/include -I/Volumes/Data/ddunbar/llvm/test -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -m64 -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -c "
-set compile_cxx " /usr/bin/g++ -arch x86_64 -I/Users/ddunbar/llvm.obj.64/include -I/Users/ddunbar/llvm.obj.64/test -I/Volumes/Data/ddunbar/llvm.obj.64/include -I/Volumes/Data/ddunbar/llvm/include -I/Volumes/Data/ddunbar/llvm/test -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -g -fno-exceptions -fno-common -Woverloaded-virtual -m64 -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -c "
-set link " /usr/bin/g++ -arch x86_64 -I/Users/ddunbar/llvm.obj.64/include -I/Users/ddunbar/llvm.obj.64/test -I/Volumes/Data/ddunbar/llvm.obj.64/include -I/Volumes/Data/ddunbar/llvm/include -I/Volumes/Data/ddunbar/llvm/test -D_DEBUG -D_GNU_SOURCE -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -g -fno-exceptions -fno-common -Woverloaded-virtual -m64 -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -g -L/Users/ddunbar/llvm.obj.64/Debug/lib -L/Volumes/Data/ddunbar/llvm.obj.64/Debug/lib "
-set llvmgcc "/Users/ddunbar/llvm-gcc/install/bin/llvm-gcc -m64 "
-set llvmgxx "/Users/ddunbar/llvm-gcc/install/bin/llvm-gcc -m64 "
-set bugpoint_topts "-gcc-tool-args -m64"
-set shlibext ".dylib"
-set ocamlopt "/sw/bin/ocamlopt -cc \"g++ -Wall -D_FILE_OFFSET_BITS=64 -D_REENTRANT\" -I /Users/ddunbar/llvm.obj.64/Debug/lib/ocaml"
-set valgrind ""
-set grep "/usr/bin/grep"
-set gas "/usr/bin/as"
-set llvmdsymutil "dsymutil"
 ## All variables above are generated by configure. Do Not Edit ## 

Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/src/test/lit.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/src/test/lit.cfg?rev=143141&r1=143140&r2=143141&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/src/test/lit.cfg (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/src/test/lit.cfg Thu Oct 27 15:59:19 2011
@@ -75,16 +75,6 @@
     if m:
         site_exp[m.group(1)] = m.group(2)
 
-# Add substitutions.
-for sub in ['prcontext', 'llvmgcc', 'llvmgxx', 'compile_cxx', 'compile_c',
-            'link', 'shlibext', 'ocamlopt', 'llvmdsymutil', 'llvmlibsdir',
-            'bugpoint_topts']:
-    if sub in ('llvmgcc', 'llvmgxx'):
-        config.substitutions.append(('%' + sub,
-                                     site_exp[sub] + ' -emit-llvm -w'))
-    else:
-        config.substitutions.append(('%' + sub, site_exp[sub]))
-
 excludes = []
 
 # Provide target_triple for use in XFAIL and XTARGET.
@@ -95,10 +85,6 @@
 def llvm_supports_target(name):
     return name in targets
 
-langs = set(site_exp['llvmgcc_langs'].split(','))
-def llvm_gcc_supports(name):
-    return name in langs
-
 # Provide on_clone hook for reading 'dg.exp'.
 import os
 simpleLibData = re.compile(r"""load_lib llvm.exp



From daniel at zuster.org  Thu Oct 27 15:59:21 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 27 Oct 2011 20:59:21 -0000
Subject: [llvm-commits] [llvm] r143142 - /llvm/trunk/test/lib/llvm2cpp.exp
Message-ID: <20111027205922.059B83128060@llvm.org>

Author: ddunbar
Date: Thu Oct 27 15:59:21 2011
New Revision: 143142

URL: http://llvm.org/viewvc/llvm-project?rev=143142&view=rev
Log:
tests: Remove llvm2cpp, I'm pretty sure no one uses this.

Removed:
    llvm/trunk/test/lib/llvm2cpp.exp

Removed: llvm/trunk/test/lib/llvm2cpp.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lib/llvm2cpp.exp?rev=143141&view=auto
==============================================================================
--- llvm/trunk/test/lib/llvm2cpp.exp (original)
+++ llvm/trunk/test/lib/llvm2cpp.exp (removed)
@@ -1,100 +0,0 @@
-# This file defines a tcl proc to assist with testing the llvm2cpp. There are
-# no llvm2cpp specific test cases. Instead, it utilizes all the existing test
-# cases and makes sure llvm2cpp can run them. The basic idea is that we find
-# all the LLVM Assembly (*.ll) files, run llvm2cpp on them to generate a C++
-# program, compile those programs, run them and see if what they produce matches
-# the original input to llvm2cpp.
-
-proc llvm2cpp-test { files } {
-  global subdir llvmtoolsdir llvmlibsdir objdir srcdir objroot srcroot 
-  set timeout 30
-  set path [file join $objdir $subdir]
-  set llc [file join $llvmtoolsdir llc ]
-  set llvmas [file join $llvmtoolsdir llvm-as ]
-  set llvmdis [file join $llvmtoolsdir llvm-dis ]
-
-  #Make Output Directory if it does not exist already
-  if { [file exists path] } {
-      cd $path
-  } else {
-      file mkdir $path
-      cd $path
-  }
-  
-  file mkdir Output
-
-  foreach test $files {
-      
-    set filename [file tail $test]
-    set generated [file join Output $filename.cpp]
-    set executable [file join Output $filename.exe]
-    set output [file join Output $filename.gen]
-    set assembly [file join Output $filename.asm]
-    set testname [file rootname $filename]
-    set bytecode [file join Output $filename.bc]
-
-    # Note that the stderr for llvm-as, etc. must be redirected to /dev/null 
-    # because otherwise exec will see the msgs and return 1 even though they 
-    # are only warnings. If real errors are generated on stderr then llvm-as 
-    # will return a non-zero retval anyway so we're good.
-
-    # Scan the test file to see if there's an XFAIL file. If so, don't run it
-    set retval [ catch { 
-      exec -keepnewline grep XFAIL $test 2>/dev/null } msg ]
-    if { $retval == 0 } {
-      continue;
-    }
-
-    # Run llvm-as/llvm-dis
-    set pipeline llvm-as|llvm-dis
-    set retval [ catch { 
-      exec -keepnewline $llvmas < $test -o - | $llvmdis -o $assembly 2>/dev/null } msg ]
-
-    if { $retval != 0 } {
-      fail "$test: $pipeline returned $retval\n$msg"
-      continue 
-    }
-
-    # Build bytecode for llvm2cpp input
-    set retval [ catch { 
-      exec -keepnewline $llvmas < $assembly > $bytecode 2>/dev/null } msg ]
-
-    if { $retval != 0 } {
-      fail "$test: llvm-as returned $retval\n$msg"
-      continue 
-    }
-
-    set retval [ catch { 
-      exec -keepnewline $llc -march=cpp -o $generated < $bytecode 2>/dev/null } msg]
-
-    if { $retval != 0 } {
-      fail "$test: llvm2cpp returned $retval\n$msg"
-      continue
-    }
-
-    set retval [ catch { 
-      exec -keepnewline gcc -g -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -o $executable $generated -I$srcroot/include -I$objroot/include -L$llvmlibsdir -lLLVMCore -lLLVMSupport -lLLVMSystem -lstdc++ } msg ] 
-    if { $retval != 0 } {
-      fail "$test: gcc returned $retval\n$msg"
-      continue
-    }
-
-    set retval [ catch { exec -keepnewline $executable > $output } msg ]
-    if { $retval != 0 } {
-      set execname [file tail $executable]
-      fail "$test: $execname returned $retval:\n$msg"
-      continue
-    } 
-
-    set retval [ catch { 
-      exec -keepnewline diff $assembly $output } msg ]
-
-    if { $retval != 0 } {
-      fail "$test: diff returned $retval:\n$msg"
-      continue
-    }
-    pass "$test"
-  }
-}
-
-



From daniel at zuster.org  Thu Oct 27 15:59:26 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 27 Oct 2011 20:59:26 -0000
Subject: [llvm-commits] [llvm] r143143 - in /llvm/trunk:
 docs/TestingGuide.html test/Makefile test/Unit/lit.site.cfg.in
 test/lib/llvm.exp test/lit.cfg test/lit.site.cfg.in test/site.exp.in
Message-ID: <20111027205926.4AB453128060@llvm.org>

Author: ddunbar
Date: Thu Oct 27 15:59:26 2011
New Revision: 143143

URL: http://llvm.org/viewvc/llvm-project?rev=143143&view=rev
Log:
tests: Rip out a bunch of now unused test code relating to use of llvm-gcc in LLVM tests.

Modified:
    llvm/trunk/docs/TestingGuide.html
    llvm/trunk/test/Makefile
    llvm/trunk/test/Unit/lit.site.cfg.in
    llvm/trunk/test/lib/llvm.exp
    llvm/trunk/test/lit.cfg
    llvm/trunk/test/lit.site.cfg.in
    llvm/trunk/test/site.exp.in

Modified: llvm/trunk/docs/TestingGuide.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/TestingGuide.html?rev=143143&r1=143142&r2=143143&view=diff
==============================================================================
--- llvm/trunk/docs/TestingGuide.html (original)
+++ llvm/trunk/docs/TestingGuide.html Thu Oct 27 15:59:26 2011
@@ -798,37 +798,10 @@
     you need multiple temporaries. This is useful as the destination of some
     redirected output.</dd>
 
-    <dt><b>llvmlibsdir</b> (%llvmlibsdir)</dt>
-    <dd>The directory where the LLVM libraries are located.</dd>
-
     <dt><b>target_triplet</b> (%target_triplet)</dt>
     <dd>The target triplet that corresponds to the current host machine (the one
     running the test cases). This should probably be called "host".<dd>
 
-    <dt><b>llvmgcc</b> (%llvmgcc)</dt>
-    <dd>The full path to the <tt>llvm-gcc</tt> executable as specified in the
-    configured LLVM environment</dd>
-
-    <dt><b>llvmgxx</b> (%llvmgxx)</dt>
-    <dd>The full path to the <tt>llvm-gxx</tt> executable as specified in the
-    configured LLVM environment</dd>
-
-    <dt><b>gccpath</b></dt>
-    <dd>The full path to the C compiler used to <i>build </i> LLVM. Note that 
-    this might not be gcc.</dd>
-
-    <dt><b>gxxpath</b></dt>
-    <dd>The full path to the C++ compiler used to <i>build </i> LLVM. Note that 
-    this might not be g++.</dd>
-
-    <dt><b>compile_c</b> (%compile_c)</dt>
-    <dd>The full command line used to compile LLVM C source  code. This has all 
-    the configured -I, -D and optimization options.</dd>
-
-    <dt><b>compile_cxx</b> (%compile_cxx)</dt>
-    <dd>The full command used to compile LLVM C++ source  code. This has 
-    all the configured -I, -D and optimization options.</dd>
-
     <dt><b>link</b> (%link)</dt> 
     <dd>This full link command used to link LLVM executables. This has all the
     configured -I, -L and -l options.</dd>

Modified: llvm/trunk/test/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=143143&r1=143142&r2=143143&view=diff
==============================================================================
--- llvm/trunk/test/Makefile (original)
+++ llvm/trunk/test/Makefile Thu Oct 27 15:59:26 2011
@@ -140,30 +140,18 @@
 	@echo '# Do not edit!' >> site.tmp
 	@echo 'set target_triplet "$(TARGET_TRIPLE)"' >> site.tmp
 	@echo 'set TARGETS_TO_BUILD "$(TARGETS_TO_BUILD)"' >> site.tmp
-	@echo 'set llvmgcc_langs "$(LLVMGCC_LANGS)"' >> site.tmp
-	@echo 'set llvmtoolsdir "$(ToolDir)"' >>site.tmp
-	@echo 'set llvmlibsdir "$(LibDir)"' >>site.tmp
 	@echo 'set llvmshlibdir "$(SharedLibDir)"' >>site.tmp
 	@echo 'set llvm_bindings "$(BINDINGS_TO_BUILD)"' >> site.tmp
 	@echo 'set srcroot "$(LLVM_SRC_ROOT)"' >>site.tmp
 	@echo 'set objroot "$(LLVM_OBJ_ROOT)"' >>site.tmp
 	@echo 'set srcdir "$(LLVM_SRC_ROOT)/test"' >>site.tmp
 	@echo 'set objdir "$(LLVM_OBJ_ROOT)/test"' >>site.tmp
-	@echo 'set gccpath "$(CC)"' >>site.tmp
-	@echo 'set gxxpath "$(CXX)"' >>site.tmp
-	@echo 'set compile_c "' $(CC) $(CPP.Flags) $(TargetCommonOpts) $(CompileCommonOpts) -c '"' >>site.tmp
-	@echo 'set compile_cxx "' $(CXX) $(CPP.Flags) $(CXX.Flags) $(TargetCommonOpts) $(CompileCommonOpts) -c -x c++ '"' >> site.tmp
 	@echo 'set link "' $(CXX) $(CPP.Flags) $(CXX.Flags) $(TargetCommonOpts) $(CompileCommonOpts) $(LD.Flags) '"' >>site.tmp
-	@echo 'set llvmgcc "$(LLVMGCC) $(TargetCommonOpts) $(EXTRA_OPTIONS)"' >> site.tmp
-	@echo 'set llvmgxx "$(LLVMGCC) $(TargetCommonOpts) $(EXTRA_OPTIONS)"' >> site.tmp
-	@echo 'set bugpoint_topts $(BUGPOINT_TOPTS)' >> site.tmp
 	@echo 'set shlibext "$(SHLIBEXT)"' >> site.tmp
 	@echo 'set ocamlopt "$(OCAMLOPT) -cc \"$(CXX_FOR_OCAMLOPT)\" -I $(LibDir)/ocaml"' >> site.tmp
 	@echo 'set valgrind "$(VALGRIND)"' >> site.tmp
 	@echo 'set grep "$(GREP)"' >>site.tmp
 	@echo 'set gas "$(GAS)"' >>site.tmp
-	@echo 'set llvmdsymutil "$(DSYMUTIL)"' >>site.tmp
-	@echo 'set emitir "$(LLVMCC_EMITIR_FLAG)"' >>site.tmp
 	@echo '## All variables above are generated by configure. Do Not Edit ## ' >>site.tmp
 	@test ! -f site.exp || \
 	sed '1,/^## All variables above are.*##/ d' site.exp >> site.tmp

Modified: llvm/trunk/test/Unit/lit.site.cfg.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Unit/lit.site.cfg.in?rev=143143&r1=143142&r2=143143&view=diff
==============================================================================
--- llvm/trunk/test/Unit/lit.site.cfg.in (original)
+++ llvm/trunk/test/Unit/lit.site.cfg.in Thu Oct 27 15:59:26 2011
@@ -3,7 +3,6 @@
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_tools_dir = "@LLVM_TOOLS_DIR@"
-config.llvmgcc_dir = "@LLVMGCCDIR@"
 config.llvm_build_mode = "@LLVM_BUILD_MODE@"
 config.enable_shared = @ENABLE_SHARED@
 config.shlibdir = "@SHLIBDIR@"

Modified: llvm/trunk/test/lib/llvm.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lib/llvm.exp?rev=143143&r1=143142&r2=143143&view=diff
==============================================================================
--- llvm/trunk/test/lib/llvm.exp (original)
+++ llvm/trunk/test/lib/llvm.exp Thu Oct 27 15:59:26 2011
@@ -47,9 +47,9 @@
 # cases.
 proc substitute { line test tmpFile } {
   global srcroot objroot srcdir objdir subdir target_triplet
-  global llvmgcc llvmgxx emitir ocamlopt
-  global gccpath gxxpath compile_c compile_cxx link shlibext llvmlibsdir
-  global llvmdsymutil valgrind grep gas bugpoint_topts
+  global ocamlopt
+  global link shlibext
+  global valgrind grep gas
   set path [file join $srcdir $subdir]
 
   # Substitute all Tcl variables.
@@ -57,28 +57,12 @@
 
   #replace %% with _#MARKER#_ to make the replacement of %% more predictable
   regsub -all {%%} $new_line {_#MARKER#_} new_line
-  #replace %llvmgcc_only with actual path to llvmgcc
-  regsub -all {%llvmgcc_only} $new_line "$llvmgcc" new_line
-  #replace %llvmgcc with actual path to llvmgcc
-  regsub -all {%llvmgcc} $new_line "$llvmgcc $emitir -w" new_line
-  #replace %llvmgxx with actual path to llvmg++
-  regsub -all {%llvmgxx} $new_line "$llvmgxx $emitir -w" new_line
-  #replace %compile_cxx with C++ compilation command
-  regsub -all {%compile_cxx} $new_line "$compile_cxx" new_line
-  #replace %compile_c with C compilation command
-  regsub -all {%compile_c} $new_line "$compile_c" new_line
   #replace %link with C++ link command
   regsub -all {%link} $new_line "$link" new_line
   #replace %shlibext with shared library extension
   regsub -all {%shlibext} $new_line "$shlibext" new_line
   #replace %ocamlopt with ocaml compiler command
   regsub -all {%ocamlopt} $new_line "$ocamlopt" new_line
-  #replace %llvmdsymutil with dsymutil command
-  regsub -all {%llvmdsymutil} $new_line "$llvmdsymutil" new_line
-  #replace %llvmlibsdir with configure library directory
-  regsub -all {%llvmlibsdir} $new_line "$llvmlibsdir" new_line
-  #replace %bugpoint_topts with actual bugpoint target options
-  regsub -all {%bugpoint_topts} $new_line "$bugpoint_topts" new_line
   #replace %p with path to source,
   regsub -all {%p} $new_line [file join $srcdir $subdir] new_line
   #replace %s with filename

Modified: llvm/trunk/test/lit.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.cfg?rev=143143&r1=143142&r2=143143&view=diff
==============================================================================
--- llvm/trunk/test/lit.cfg (original)
+++ llvm/trunk/test/lit.cfg Thu Oct 27 15:59:26 2011
@@ -42,18 +42,6 @@
 # Tweak the PATH to include the scripts dir, the tools dir, and the llvm-gcc bin
 # dir (if available).
 if llvm_obj_root is not None:
-    # Include llvm-gcc first, as the llvm-gcc binaryies will not appear
-    # neither in the tools nor in the scripts dir. However it might be
-    # possible, that some old llvm tools are in the llvm-gcc dir. Adding
-    # llvm-gcc dir first ensures, that those will always be overwritten
-    # by the new tools in llvm_tools_dir. So now outdated tools are used
-      # for testing
-    llvmgcc_dir = getattr(config, 'llvmgcc_dir', None)
-    if llvmgcc_dir:
-        path = os.path.pathsep.join((os.path.join(llvmgcc_dir, 'bin'),
-                                     config.environment['PATH']))
-        config.environment['PATH'] = path
-
     llvm_src_root = getattr(config, 'llvm_src_root', None)
     if not llvm_src_root:
         lit.fatal('No LLVM source root set!')
@@ -154,21 +142,8 @@
         site_exp[m.group(1)] = m.group(2)
 
 # Add substitutions.
-config.substitutions.append(('%llvmgcc_only', site_exp['llvmgcc']))
-for sub in ['llvmgcc', 'llvmgxx', 'emitir', 'compile_cxx', 'compile_c',
-            'link', 'shlibext', 'ocamlopt', 'llvmdsymutil', 'llvmlibsdir',
-            'llvmshlibdir',
-            'bugpoint_topts']:
-    if sub in ('llvmgcc', 'llvmgxx'):
-        config.substitutions.append(('%' + sub,
-                                     site_exp[sub] + ' %emitir -w'))
-    # FIXME: This is a hack to avoid LLVMC tests failing due to a clang driver
-    #        warning when passing in "-fexceptions -fno-exceptions".
-    elif sub == 'compile_cxx':
-        config.substitutions.append(('%' + sub,
-                                  site_exp[sub].replace('-fno-exceptions', '')))
-    else:
-        config.substitutions.append(('%' + sub, site_exp[sub]))
+for sub in ['link', 'shlibext', 'ocamlopt', 'llvmshlibdir']:
+    config.substitutions.append(('%' + sub, site_exp[sub]))
 
 # For each occurrence of an llvm tool name as its own word, replace it
 # with the full path to the build directory holding that tool.  This

Modified: llvm/trunk/test/lit.site.cfg.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.site.cfg.in?rev=143143&r1=143142&r2=143143&view=diff
==============================================================================
--- llvm/trunk/test/lit.site.cfg.in (original)
+++ llvm/trunk/test/lit.site.cfg.in Thu Oct 27 15:59:26 2011
@@ -3,7 +3,6 @@
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_tools_dir = "@LLVM_TOOLS_DIR@"
-config.llvmgcc_dir = "@LLVMGCCDIR@"
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"
 config.python_executable = "@PYTHON_EXECUTABLE@"
 config.enable_shared = @ENABLE_SHARED@

Modified: llvm/trunk/test/site.exp.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/site.exp.in?rev=143143&r1=143142&r2=143143&view=diff
==============================================================================
--- llvm/trunk/test/site.exp.in (original)
+++ llvm/trunk/test/site.exp.in Thu Oct 27 15:59:26 2011
@@ -2,27 +2,15 @@
 # Do not edit!
 set target_triplet "@TARGET_TRIPLE@"
 set TARGETS_TO_BUILD "@TARGETS_TO_BUILD@"
-set llvmgcc_langs "@LLVMGCC_LANGS@"
-set llvmtoolsdir "@LLVM_TOOLS_DIR@"
-set llvmlibsdir "@LLVM_LIBS_DIR@"
 set llvmshlibdir "@SHLIBDIR@"
 set llvm_bindings "@LLVM_BINDINGS@"
 set srcroot "@LLVM_SOURCE_DIR@"
 set objroot "@LLVM_BINARY_DIR@"
 set srcdir "@LLVM_SOURCE_DIR@"
 set objdir "@LLVM_BINARY_DIR@"
-set gccpath "@GCCPATH@"
-set gxxpath "@GXXPATH@"
-set compile_c "@TEST_COMPILE_C_CMD@"
-set compile_cxx "@TEST_COMPILE_CXX_CMD@"
 set link "@TEST_LINK_CMD@"
-set llvmgcc "@LLVMGCC@"
-set llvmgxx "@LLVMGXX@"
-set bugpoint_topts "@BUGPOINT_TOPTS@"
 set shlibext "@SHLIBEXT@"
 set ocamlopt "@OCAMLOPT@"
 set valgrind "@VALGRIND@"
 set grep "@GREP@"
 set gas "@AS@"
-set llvmdsymutil "@DSYMUTIL@"
-set emitir "@LLVMCC_EMITIR_FLAG@"



From peter_cooper at apple.com  Thu Oct 27 13:15:58 2011
From: peter_cooper at apple.com (Pete Cooper)
Date: Thu, 27 Oct 2011 18:15:58 -0000
Subject: [llvm-commits] [llvm] r143116 -
	/llvm/trunk/test/CodeGen/X86/widen_load-2.ll
Message-ID: <20111027181558.B87F13128060@llvm.org>

Author: pete
Date: Thu Oct 27 13:15:58 2011
New Revision: 143116

URL: http://llvm.org/viewvc/llvm-project?rev=143116&view=rev
Log:
Changed test to check for correct load size instead of shift as the shift might change if optimised

Modified:
    llvm/trunk/test/CodeGen/X86/widen_load-2.ll

Modified: llvm/trunk/test/CodeGen/X86/widen_load-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_load-2.ll?rev=143116&r1=143115&r2=143116&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_load-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_load-2.ll Thu Oct 27 13:15:58 2011
@@ -170,7 +170,7 @@
 ; CHECK: rot
 %i8vec3pack = type { <3 x i8>, i8 }
 define %i8vec3pack  @rot() nounwind {
-; CHECK: shrl
+; CHECK: movd {{-?[0-9]+}}(%rsp), {{%xmm[0-9]}}
 entry:
   %X = alloca %i8vec3pack, align 4
   %rot = alloca %i8vec3pack, align 4



From grosbach at apple.com  Thu Oct 27 16:13:15 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 27 Oct 2011 14:13:15 -0700
Subject: [llvm-commits] [llvm] r143097 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/MC/ lib/CodeGen/AsmPrinter/ lib/MC/
 test/CodeGen/ARM/ test/CodeGen/X86/ test/DebugInfo/
In-Reply-To: <CAGCO0KjsWtj4EjaT5A+W_n8q6SW--FwBmBGHDPnO0xk6oZBQWw@mail.gmail.com>
References: <20111027064411.6F491312800A@llvm.org>
	<E9EC3800-F327-4902-9CCF-CA15EACBD39E@apple.com>
	<CAGCO0KjsWtj4EjaT5A+W_n8q6SW--FwBmBGHDPnO0xk6oZBQWw@mail.gmail.com>
Message-ID: <98F5973F-1ABF-4878-8FDA-BCAF469E1DBD@apple.com>


On Oct 27, 2011, at 11:40 AM, Chandler Carruth wrote:

> On Thu, Oct 27, 2011 at 10:24 AM, Jim Grosbach <grosbach at apple.com> wrote:
> Hey Nick,
> 
> This is great stuff. Thanks for doing this.
> 
> I'm seeing a few test failures in the GCC test suite (https://llvm.org/svn/llvm-project/clang-tests/trunk/gcc-4_2-testsuite), though. It's fairly likely that they're just tests that need to be updated. Can you have a look?
> 
> gcc.apple/block-debug-1.c scan-assembler __block_descriptor.*DW_AT_name
> gcc.apple/block-debug-1.c scan-assembler __block_literal_generic.*DW_AT_name
> gcc.apple/block-debug-2.c scan-assembler __block_descriptor.*DW_AT_name
> gcc.apple/block-debug-2.c scan-assembler __block_literal_generic.*DW_AT_name
> gcc.dg/debug/dwarf2/var1.c scan-assembler xyzzy[^\\n\\r]+DW_AT_name
> 
> I've tried to fix these with r143119. I'll watch the IRC messages from the bot, hopefully the regular expression magic isn't too much for dejagnu... 

Bah. Latest run shows (as of r143125) failures still. 

gcc.apple/block-debug-1.c scan-assembler \\.Lstring12:[\\n\\r \\t]+\\.ascii\\s+"__block_descriptor"
gcc.apple/block-debug-1.c scan-assembler \\.Lstring12[^\\n\\r]+DW_AT_name
gcc.apple/block-debug-1.c scan-assembler \\.Lstring13:[\\n\\r \\t]+\\.ascii\\s+"__block_literal_generic"
gcc.apple/block-debug-1.c scan-assembler \\.Lstring13[^\\n\\r]+DW_AT_name
gcc.apple/block-debug-2.c scan-assembler \\.Lstring11:[\\n\\r \\t]+\\.ascii\\s+"__block_descriptor"
gcc.apple/block-debug-2.c scan-assembler \\.Lstring11[^\\n\\r]+DW_AT_name
gcc.apple/block-debug-2.c scan-assembler \\.Lstring12:[\\n\\r \\t]+\\.ascii\\s+"__block_literal_generic"
gcc.apple/block-debug-2.c scan-assembler \\.Lstring12[^\\n\\r]+DW_AT_name
gcc.dg/debug/dwarf2/var1.c scan-assembler \\.Lstring3:[\\n\\r \\t]+\\.ascii\\s+"xyzzy"
gcc.dg/debug/dwarf2/var1.c scan-assembler \\.Lstring3[^\\n\\r]+DW_AT_name

It does appear to have pulled the changes:
U    gcc-4_2-testsuite/src/gcc.dg/debug/dwarf2/var1.c
U    gcc-4_2-testsuite/src/gcc.apple/block-debug-1.c
U    gcc-4_2-testsuite/src/gcc.apple/block-debug-2.c
Updated to revision 143125.

Not quite sure what's going on. You may be spot on that your regex-fu is better than dejagnu's.


-Jim

From evan.cheng at apple.com  Thu Oct 27 16:21:05 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 27 Oct 2011 21:21:05 -0000
Subject: [llvm-commits] [llvm] r143145 - in /llvm/trunk:
 lib/Target/ARM/Thumb2SizeReduction.cpp test/CodeGen/ARM/avoid-cpsr-rmw.ll
Message-ID: <20111027212105.547F73128060@llvm.org>

Author: evancheng
Date: Thu Oct 27 16:21:05 2011
New Revision: 143145

URL: http://llvm.org/viewvc/llvm-project?rev=143145&view=rev
Log:
Avoid partial CPSR dependency from loop backedges. rdar://10357570

Modified:
    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
    llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll

Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=143145&r1=143144&r2=143145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Thu Oct 27 16:21:05 2011
@@ -146,7 +146,8 @@
     /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
     DenseMap<unsigned, unsigned> ReduceOpcodeMap;
 
-    bool canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use);
+    bool canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use,
+                             bool IsSelfLoop);
 
     bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
                          bool is2Addr, ARMCC::CondCodes Pred,
@@ -157,19 +158,21 @@
 
     bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
                        const ReduceEntry &Entry, bool LiveCPSR,
-                       MachineInstr *CPSRDef);
+                       MachineInstr *CPSRDef, bool IsSelfLoop);
 
     /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
     /// instruction.
     bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
                        const ReduceEntry &Entry,
-                       bool LiveCPSR, MachineInstr *CPSRDef);
+                       bool LiveCPSR, MachineInstr *CPSRDef,
+                       bool IsSelfLoop);
 
     /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
     /// non-two-address instruction.
     bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
                         const ReduceEntry &Entry,
-                        bool LiveCPSR, MachineInstr *CPSRDef);
+                        bool LiveCPSR, MachineInstr *CPSRDef,
+                        bool IsSelfLoop);
 
     /// ReduceMBB - Reduce width of instructions in the specified basic block.
     bool ReduceMBB(MachineBasicBlock &MBB);
@@ -210,10 +213,17 @@
 /// In this case it would have been ok to narrow the mul.w to muls since there
 /// are indirect RAW dependency between the muls and the mul.w
 bool
-Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use) {
-  if (!Def || !STI->avoidCPSRPartialUpdate())
+Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use,
+                                      bool FirstInSelfLoop) {
+  // FIXME: Disable check for -Oz (aka OptimizeForSizeHarder).
+  if (!STI->avoidCPSRPartialUpdate())
     return false;
 
+  if (!Def)
+    // If this BB loops back to itself, conservatively avoid narrowing the
+    // first instruction that does partial flag update.
+    return FirstInSelfLoop;
+
   SmallSet<unsigned, 2> Defs;
   for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = Def->getOperand(i);
@@ -476,15 +486,16 @@
 bool
 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
                                 const ReduceEntry &Entry,
-                                bool LiveCPSR, MachineInstr *CPSRDef) {
+                                bool LiveCPSR, MachineInstr *CPSRDef,
+                                bool IsSelfLoop) {
   unsigned Opc = MI->getOpcode();
   if (Opc == ARM::t2ADDri) {
     // If the source register is SP, try to reduce to tADDrSPi, otherwise
     // it's a normal reduce.
     if (MI->getOperand(1).getReg() != ARM::SP) {
-      if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef))
+      if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop))
         return true;
-      return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
+      return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
     }
     // Try to reduce to tADDrSPi.
     unsigned Imm = MI->getOperand(2).getImm();
@@ -535,12 +546,12 @@
       switch (Opc) {
       default: break;
       case ARM::t2ADDSri: {
-        if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef))
+        if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop))
           return true;
         // fallthrough
       }
       case ARM::t2ADDSrr:
-        return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
+        return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
       }
     }
     break;
@@ -552,13 +563,13 @@
   case ARM::t2UXTB:
   case ARM::t2UXTH:
     if (MI->getOperand(2).getImm() == 0)
-      return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
+      return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
     break;
   case ARM::t2MOVi16:
     // Can convert only 'pure' immediate operands, not immediates obtained as
     // globals' addresses.
     if (MI->getOperand(1).isImm())
-      return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
+      return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
     break;
   case ARM::t2CMPrr: {
     // Try to reduce to the lo-reg only version first. Why there are two
@@ -568,9 +579,9 @@
     // source insn opcode. So for now, we hack a local entry record to use.
     static const ReduceEntry NarrowEntry =
       { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1 };
-    if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef))
+    if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef, IsSelfLoop))
       return true;
-    return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
+    return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
   }
   }
   return false;
@@ -579,7 +590,8 @@
 bool
 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
                                 const ReduceEntry &Entry,
-                                bool LiveCPSR, MachineInstr *CPSRDef) {
+                                bool LiveCPSR, MachineInstr *CPSRDef,
+                                bool IsSelfLoop) {
 
   if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
     return false;
@@ -637,7 +649,7 @@
   // Avoid adding a false dependency on partial flag update by some 16-bit
   // instructions which has the 's' bit set.
   if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
-      canAddPseudoFlagDep(CPSRDef, MI))
+      canAddPseudoFlagDep(CPSRDef, MI, IsSelfLoop))
     return false;
 
   // Add the 16-bit instruction.
@@ -674,7 +686,8 @@
 bool
 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
                                  const ReduceEntry &Entry,
-                                 bool LiveCPSR, MachineInstr *CPSRDef) {
+                                 bool LiveCPSR, MachineInstr *CPSRDef,
+                                 bool IsSelfLoop) {
   if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
     return false;
 
@@ -727,7 +740,7 @@
   // Avoid adding a false dependency on partial flag update by some 16-bit
   // instructions which has the 's' bit set.
   if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
-      canAddPseudoFlagDep(CPSRDef, MI))
+      canAddPseudoFlagDep(CPSRDef, MI, IsSelfLoop))
     return false;
 
   // Add the 16-bit instruction.
@@ -818,6 +831,9 @@
   bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
   MachineInstr *CPSRDef = 0;
 
+  // If this BB loops back to itself, conservatively avoid narrowing the
+  // first instruction that does partial flag update.
+  bool IsSelfLoop = MBB.isSuccessor(&MBB);
   MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
   MachineBasicBlock::iterator NextMII;
   for (; MII != E; MII = NextMII) {
@@ -832,7 +848,7 @@
       const ReduceEntry &Entry = ReduceTable[OPI->second];
       // Ignore "special" cases for now.
       if (Entry.Special) {
-        if (ReduceSpecial(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
+        if (ReduceSpecial(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
           Modified = true;
           MachineBasicBlock::iterator I = prior(NextMII);
           MI = &*I;
@@ -842,7 +858,7 @@
 
       // Try to transform to a 16-bit two-address instruction.
       if (Entry.NarrowOpc2 &&
-          ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
+          ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
         Modified = true;
         MachineBasicBlock::iterator I = prior(NextMII);
         MI = &*I;
@@ -851,7 +867,7 @@
 
       // Try to transform to a 16-bit non-two-address instruction.
       if (Entry.NarrowOpc1 &&
-          ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
+          ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
         Modified = true;
         MachineBasicBlock::iterator I = prior(NextMII);
         MI = &*I;
@@ -861,12 +877,15 @@
   ProcessNext:
     bool DefCPSR = false;
     LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
-    if (MI->getDesc().isCall())
+    if (MI->getDesc().isCall()) {
       // Calls don't really set CPSR.
       CPSRDef = 0;
-    else if (DefCPSR)
+      IsSelfLoop = false;
+    } else if (DefCPSR) {
       // This is the last CPSR defining instruction.
       CPSRDef = MI;
+      IsSelfLoop = false;
+    }
   }
 
   return Modified;

Modified: llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll?rev=143145&r1=143144&r2=143145&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll Thu Oct 27 16:21:05 2011
@@ -3,9 +3,9 @@
 ; dependency) when it isn't dependent on last CPSR defining instruction.
 ; rdar://8928208
 
-define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
+define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
  entry:
-; CHECK: t:
+; CHECK: t1:
 ; CHECK: muls [[REG:(r[0-9]+)]], r2, r3
 ; CHECK-NEXT: mul  [[REG2:(r[0-9]+)]], r0, r1
 ; CHECK-NEXT: muls r0, [[REG2]], [[REG]]
@@ -14,3 +14,37 @@
   %2 = mul nsw i32 %0, %1
   ret i32 %2
 }
+
+; Avoid partial CPSR dependency via loop backedge.
+; rdar://10357570
+define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
+entry:
+; CHECK: t2:
+  %tobool7 = icmp eq i32* %ptr2, null
+  br i1 %tobool7, label %while.end, label %while.body
+
+while.body:
+; CHECK: while.body
+; CHECK: mul r{{[0-9]+}}
+; CHECK-NOT: muls
+  %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
+  %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
+  %0 = load i32* %ptr1.addr.09, align 4
+  %arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1
+  %1 = load i32* %arrayidx1, align 4
+  %arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2
+  %2 = load i32* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3
+  %3 = load i32* %arrayidx4, align 4
+  %add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4
+  %mul = mul i32 %1, %0
+  %mul5 = mul i32 %mul, %2
+  %mul6 = mul i32 %mul5, %3
+  store i32 %mul6, i32* %ptr2.addr.08, align 4
+  %incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1
+  %tobool = icmp eq i32* %incdec.ptr, null
+  br i1 %tobool, label %while.end, label %while.body
+
+while.end:
+  ret void
+}



From daniel at zuster.org  Thu Oct 27 16:25:09 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 27 Oct 2011 21:25:09 -0000
Subject: [llvm-commits] [llvm] r143148 -
	/llvm/trunk/projects/sample/Makefile.common.in
Message-ID: <20111027212509.595033128060@llvm.org>

Author: ddunbar
Date: Thu Oct 27 16:25:09 2011
New Revision: 143148

URL: http://llvm.org/viewvc/llvm-project?rev=143148&view=rev
Log:
projects/sample: Switch over to imported Makefile setup.
 - This will require you to manually reconfigure the projects/sample project (by running projects/config/sample/config.status --recheck) if you haven't updated/built since the 1st part of this commit went in.

Modified:
    llvm/trunk/projects/sample/Makefile.common.in

Modified: llvm/trunk/projects/sample/Makefile.common.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/Makefile.common.in?rev=143148&r1=143147&r2=143148&view=diff
==============================================================================
--- llvm/trunk/projects/sample/Makefile.common.in (original)
+++ llvm/trunk/projects/sample/Makefile.common.in Thu Oct 27 16:25:09 2011
@@ -18,5 +18,9 @@
 # Set the root directory of this project's install prefix
 PROJ_INSTALL_ROOT := @prefix@
 
-# Include LLVM's Master Makefile.
-include $(LLVM_SRC_ROOT)/Makefile.common
+# Configuration file to set paths specific to local installation of LLVM
+include $(PROJ_OBJ_ROOT)/Makefile.llvm.config
+
+# Include all of the build rules used for making LLVM
+include $(PROJ_SRC_ROOT)/Makefile.llvm.rules
+



From resistor at mac.com  Thu Oct 27 16:46:32 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 27 Oct 2011 21:46:32 -0000
Subject: [llvm-commits] [llvm] r143149 -
	/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
Message-ID: <20111027214632.18CD13128060@llvm.org>

Author: resistor
Date: Thu Oct 27 16:46:31 2011
New Revision: 143149

URL: http://llvm.org/viewvc/llvm-project?rev=143149&view=rev
Log:
Stub out support for symbol disassembly in llvm-objdump.

Modified:
    llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp

Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=143149&r1=143148&r2=143149&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Thu Oct 27 16:46:31 2011
@@ -23,9 +23,11 @@
 #include "llvm/ADT/Triple.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstPrinter.h"
+#include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
@@ -159,8 +161,30 @@
   return a_addr < b_addr;
 }
 
+// OperandInfoCallback - Callback from the MCDisassembler to perform
+// relocation resolution for operands while disassembling.
+int OperandInfoCallback(void *ObjectFile, uint64_t PC, uint64_t Offset,
+                            uint64_t Size, int TagType, void *TagBuf) {
+  LLVMOpInfo1 *OpInfo = static_cast<LLVMOpInfo1*>(TagBuf);
+  OpInfo->AddSymbol.Present = 0;
+  OpInfo->SubtractSymbol.Present = 0;
+  OpInfo->VariantKind = LLVMDisassembler_VariantKind_None;
+
+  return 0;
+}
+
+// SymbolLookupCallback - Callback from the MCDisassembler to convert
+// offsets to symbolic references while disassembling.
+const char* SymbolLookupCallback(void *ObjectFile, uint64_t ReferenceValue,
+                          uint64_t *ReferenceType, uint64_t PC,
+                          const char **ReferenceName) {
+  *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
+  return 0;
+}
+
 static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
   const Target *TheTarget = GetTarget(Obj);
+
   if (!TheTarget) {
     // GetTarget prints out stuff.
     return;
@@ -227,6 +251,14 @@
       return;
     }
 
+    OwningPtr<const MCRegisterInfo>
+       RegInfo(TheTarget->createMCRegInfo(TripleName));
+
+    if (!RegInfo) {
+      errs() << "error: no register info for target " << TripleName << "\n";
+      return;
+    }
+
     OwningPtr<const MCSubtargetInfo> STI(
       TheTarget->createMCSubtargetInfo(TripleName, "", ""));
 
@@ -235,13 +267,20 @@
       return;
     }
 
-    OwningPtr<const MCDisassembler> DisAsm(
+    MCContext Context(*AsmInfo, *RegInfo, 0);
+    OwningPtr<MCDisassembler> DisAsm(
       TheTarget->createMCDisassembler(*STI));
     if (!DisAsm) {
       errs() << "error: no disassembler for target " << TripleName << "\n";
       return;
     }
 
+    // Setup the disassembler for symbolic decoding.
+    DisAsm->setupForSymbolicDisassembly(OperandInfoCallback,
+                                        SymbolLookupCallback,
+                                        const_cast<ObjectFile*>(Obj),
+                                        &Context);
+
     int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
     OwningPtr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
                                 AsmPrinterVariant, *AsmInfo, *STI));
@@ -289,7 +328,7 @@
 
         if (DisAsm->getInstruction(Inst, Size, memoryObject, Index,
                                    DebugOut, nulls())) {
-          outs() << format("%8llx:\t", SectionAddr + Index);
+          outs() << format("%8x:\t", SectionAddr + Index);
           DumpBytes(StringRef(Bytes.data() + Index, Size));
           IP->printInst(&Inst, outs(), "");
           outs() << "\n";
@@ -316,7 +355,7 @@
           if (error(rel_cur->getTypeName(name))) goto skip_print_rel;
           if (error(rel_cur->getValueString(val))) goto skip_print_rel;
 
-          outs() << format("\t\t\t%8llx: ", SectionAddr + addr) << name << "\t"
+          outs() << format("\t\t\t%8x: ", SectionAddr + addr) << name << "\t"
                  << val << "\n";
 
         skip_print_rel:
@@ -400,7 +439,7 @@
 
     // Dump out the content as hex and printable ascii characters.
     for (std::size_t addr = 0, end = Contents.size(); addr < end; addr += 16) {
-      outs() << format(" %04llx ", BaseAddr + addr);
+      outs() << format(" %04x ", BaseAddr + addr);
       // Dump line of hex.
       for (std::size_t i = 0; i < 16; ++i) {
         if (i != 0 && i % 4 == 0)
@@ -506,7 +545,7 @@
       else if (Type == SymbolRef::ST_Function)
         FileFunc = 'F';
 
-      outs() << format("%08llx", Offset) << " "
+      outs() << format("%08x", Offset) << " "
              << GlobLoc // Local -> 'l', Global -> 'g', Neither -> ' '
              << (Weak ? 'w' : ' ') // Weak?
              << ' ' // Constructor. Not supported yet.
@@ -526,7 +565,7 @@
         outs() << SectionName;
       }
       outs() << '\t'
-             << format("%08llx ", Size)
+             << format("%08x ", Size)
              << Name
              << '\n';
     }



From resistor at mac.com  Thu Oct 27 16:53:50 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 27 Oct 2011 21:53:50 -0000
Subject: [llvm-commits] [llvm] r143151 -
	/llvm/trunk/lib/Object/MachOObjectFile.cpp
Message-ID: <20111027215350.C3A093128060@llvm.org>

Author: resistor
Date: Thu Oct 27 16:53:50 2011
New Revision: 143151

URL: http://llvm.org/viewvc/llvm-project?rev=143151&view=rev
Log:
If we're searching for a symbol reference to pretty-print a scattered relocation address, and we don't find a symbol table entry, try section begin addresses as well.

Modified:
    llvm/trunk/lib/Object/MachOObjectFile.cpp

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=143151&r1=143150&r2=143151&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Thu Oct 27 16:53:50 2011
@@ -821,6 +821,24 @@
       return;
     }
 
+    // If we couldn't find a symbol that this relocation refers to, try
+    // to find a section beginning instead.
+    for (section_iterator SI = begin_sections(), SE = end_sections(); SI != SE;
+         SI.increment(ec)) {
+      if (ec) report_fatal_error(ec.message());
+
+      uint64_t Addr;
+      StringRef Name;
+
+      if ((ec = SI->getAddress(Addr)))
+        report_fatal_error(ec.message());
+      if (Addr != Val) continue;
+      if ((ec = SI->getName(Name)))
+        report_fatal_error(ec.message());
+      fmt << Name;
+      return;
+    }
+
     fmt << format("0x%x", Val);
     return;
   }



From resistor at mac.com  Thu Oct 27 16:55:13 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 27 Oct 2011 21:55:13 -0000
Subject: [llvm-commits] [llvm] r143152 -
	/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
Message-ID: <20111027215513.EA68E3128060@llvm.org>

Author: resistor
Date: Thu Oct 27 16:55:13 2011
New Revision: 143152

URL: http://llvm.org/viewvc/llvm-project?rev=143152&view=rev
Log:
Revert r143149, stubbing out symbolic disassembly support.  The symbolic disassembly support is too MC-engrained to be useful in llvm-objdump.

Modified:
    llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp

Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=143152&r1=143151&r2=143152&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Thu Oct 27 16:55:13 2011
@@ -23,11 +23,9 @@
 #include "llvm/ADT/Triple.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstPrinter.h"
-#include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
@@ -161,30 +159,8 @@
   return a_addr < b_addr;
 }
 
-// OperandInfoCallback - Callback from the MCDisassembler to perform
-// relocation resolution for operands while disassembling.
-int OperandInfoCallback(void *ObjectFile, uint64_t PC, uint64_t Offset,
-                            uint64_t Size, int TagType, void *TagBuf) {
-  LLVMOpInfo1 *OpInfo = static_cast<LLVMOpInfo1*>(TagBuf);
-  OpInfo->AddSymbol.Present = 0;
-  OpInfo->SubtractSymbol.Present = 0;
-  OpInfo->VariantKind = LLVMDisassembler_VariantKind_None;
-
-  return 0;
-}
-
-// SymbolLookupCallback - Callback from the MCDisassembler to convert
-// offsets to symbolic references while disassembling.
-const char* SymbolLookupCallback(void *ObjectFile, uint64_t ReferenceValue,
-                          uint64_t *ReferenceType, uint64_t PC,
-                          const char **ReferenceName) {
-  *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
-  return 0;
-}
-
 static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
   const Target *TheTarget = GetTarget(Obj);
-
   if (!TheTarget) {
     // GetTarget prints out stuff.
     return;
@@ -251,14 +227,6 @@
       return;
     }
 
-    OwningPtr<const MCRegisterInfo>
-       RegInfo(TheTarget->createMCRegInfo(TripleName));
-
-    if (!RegInfo) {
-      errs() << "error: no register info for target " << TripleName << "\n";
-      return;
-    }
-
     OwningPtr<const MCSubtargetInfo> STI(
       TheTarget->createMCSubtargetInfo(TripleName, "", ""));
 
@@ -267,20 +235,13 @@
       return;
     }
 
-    MCContext Context(*AsmInfo, *RegInfo, 0);
-    OwningPtr<MCDisassembler> DisAsm(
+    OwningPtr<const MCDisassembler> DisAsm(
       TheTarget->createMCDisassembler(*STI));
     if (!DisAsm) {
       errs() << "error: no disassembler for target " << TripleName << "\n";
       return;
     }
 
-    // Setup the disassembler for symbolic decoding.
-    DisAsm->setupForSymbolicDisassembly(OperandInfoCallback,
-                                        SymbolLookupCallback,
-                                        const_cast<ObjectFile*>(Obj),
-                                        &Context);
-
     int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
     OwningPtr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
                                 AsmPrinterVariant, *AsmInfo, *STI));
@@ -328,7 +289,7 @@
 
         if (DisAsm->getInstruction(Inst, Size, memoryObject, Index,
                                    DebugOut, nulls())) {
-          outs() << format("%8x:\t", SectionAddr + Index);
+          outs() << format("%8llx:\t", SectionAddr + Index);
           DumpBytes(StringRef(Bytes.data() + Index, Size));
           IP->printInst(&Inst, outs(), "");
           outs() << "\n";
@@ -355,7 +316,7 @@
           if (error(rel_cur->getTypeName(name))) goto skip_print_rel;
           if (error(rel_cur->getValueString(val))) goto skip_print_rel;
 
-          outs() << format("\t\t\t%8x: ", SectionAddr + addr) << name << "\t"
+          outs() << format("\t\t\t%8llx: ", SectionAddr + addr) << name << "\t"
                  << val << "\n";
 
         skip_print_rel:
@@ -439,7 +400,7 @@
 
     // Dump out the content as hex and printable ascii characters.
     for (std::size_t addr = 0, end = Contents.size(); addr < end; addr += 16) {
-      outs() << format(" %04x ", BaseAddr + addr);
+      outs() << format(" %04llx ", BaseAddr + addr);
       // Dump line of hex.
       for (std::size_t i = 0; i < 16; ++i) {
         if (i != 0 && i % 4 == 0)
@@ -545,7 +506,7 @@
       else if (Type == SymbolRef::ST_Function)
         FileFunc = 'F';
 
-      outs() << format("%08x", Offset) << " "
+      outs() << format("%08llx", Offset) << " "
              << GlobLoc // Local -> 'l', Global -> 'g', Neither -> ' '
              << (Weak ? 'w' : ' ') // Weak?
              << ' ' // Constructor. Not supported yet.
@@ -565,7 +526,7 @@
         outs() << SectionName;
       }
       outs() << '\t'
-             << format("%08x ", Size)
+             << format("%08llx ", Size)
              << Name
              << '\n';
     }



From grosbach at apple.com  Thu Oct 27 16:59:17 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 27 Oct 2011 21:59:17 -0000
Subject: [llvm-commits] [llvm] r143153 -
	/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Message-ID: <20111027215917.5655A3128060@llvm.org>

Author: grosbach
Date: Thu Oct 27 16:59:17 2011
New Revision: 143153

URL: http://llvm.org/viewvc/llvm-project?rev=143153&view=rev
Log:
Delete dead code. Nothing ever instantiates this.

Modified:
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=143153&r1=143152&r2=143153&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Thu Oct 27 16:59:17 2011
@@ -253,10 +253,6 @@
   OS << "namespace llvm {\n\n";
 
   const std::string &TargetName = Target.getName();
-  std::string ClassName = TargetName + "GenMCRegisterInfo";
-  OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
-     << "  explicit " << ClassName << "(const MCRegisterDesc *D);\n";
-  OS << "};\n";
 
   OS << "\nnamespace {\n";
 



From grosbach at apple.com  Thu Oct 27 17:25:42 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 27 Oct 2011 22:25:42 -0000
Subject: [llvm-commits] [llvm] r143158 -
	/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
Message-ID: <20111027222542.A69983128060@llvm.org>

Author: grosbach
Date: Thu Oct 27 17:25:42 2011
New Revision: 143158

URL: http://llvm.org/viewvc/llvm-project?rev=143158&view=rev
Log:
ARM isel for vld1, opcode selection for register stride post-index pseudos.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=143158&r1=143157&r2=143158&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Oct 27 17:25:42 2011
@@ -1562,6 +1562,10 @@
   case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
   case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
   case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
+  case ARM::VLD1q8PseudoWB_fixed: return ARM::VLD1q8PseudoWB_register;
+  case ARM::VLD1q16PseudoWB_fixed: return ARM::VLD1q16PseudoWB_register;
+  case ARM::VLD1q32PseudoWB_fixed: return ARM::VLD1q32PseudoWB_register;
+  case ARM::VLD1q64PseudoWB_fixed: return ARM::VLD1q64PseudoWB_register;
   }
   return Opc; // If not one we handle, return it unchanged.
 }



From eli.friedman at gmail.com  Thu Oct 27 17:32:13 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 27 Oct 2011 22:32:13 -0000
Subject: [llvm-commits] [llvm] r143159 - /llvm/trunk/docs/Passes.html
Message-ID: <20111027223213.70B5E3128060@llvm.org>

Author: efriedma
Date: Thu Oct 27 17:32:13 2011
New Revision: 143159

URL: http://llvm.org/viewvc/llvm-project?rev=143159&view=rev
Log:
The default alias analysis is -noaa; update the docs to reflect that.  Patch by Michael Ilseman.


Modified:
    llvm/trunk/docs/Passes.html

Modified: llvm/trunk/docs/Passes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Passes.html?rev=143159&r1=143158&r2=143159&view=diff
==============================================================================
--- llvm/trunk/docs/Passes.html (original)
+++ llvm/trunk/docs/Passes.html Thu Oct 27 17:32:13 2011
@@ -226,11 +226,8 @@
   <a name="basicaa">-basicaa: Basic Alias Analysis (stateless AA impl)</a>
 </h3>
 <div>
-  <p>
-  This is the default implementation of the Alias Analysis interface
-  that simply implements a few identities (two different globals cannot alias,
-  etc), but otherwise does no analysis.
-  </p>
+  <p>A basic alias analysis pass that implements identities (two different
+  globals cannot alias, etc), but does no stateful analysis.</p>
 </div>
 
 <!-------------------------------------------------------------------------- -->
@@ -527,9 +524,10 @@
 </h3>
 <div>
   <p>
-  Always returns "I don't know" for alias queries.  NoAA is unlike other alias
-  analysis implementations, in that it does not chain to a previous analysis. As
-  such it doesn't follow many of the rules that other alias analyses must.
+  This is the default implementation of the Alias Analysis interface. It always
+  returns "I don't know" for alias queries.  NoAA is unlike other alias analysis
+  implementations, in that it does not chain to a previous analysis. As such it
+  doesn't follow many of the rules that other alias analyses must.
   </p>
 </div>
 



From stoklund at 2pi.dk  Thu Oct 27 17:39:16 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 27 Oct 2011 22:39:16 -0000
Subject: [llvm-commits] [llvm] r143160 - in /llvm/trunk:
 lib/Target/ARM/ARMISelDAGToDAG.cpp test/CodeGen/ARM/vlddup.ll
 test/CodeGen/ARM/vldlane.ll test/CodeGen/ARM/vstlane.ll
Message-ID: <20111027223916.3E82D3128060@llvm.org>

Author: stoklund
Date: Thu Oct 27 17:39:16 2011
New Revision: 143160

URL: http://llvm.org/viewvc/llvm-project?rev=143160&view=rev
Log:
Also set addrmode6 alignment when align==size.

Previously, we were only setting the alignment bits on over-aligned
loads and stores.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/ARM/vlddup.ll
    llvm/trunk/test/CodeGen/ARM/vldlane.ll
    llvm/trunk/test/CodeGen/ARM/vstlane.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=143160&r1=143159&r2=143160&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Oct 27 17:39:16 2011
@@ -923,7 +923,7 @@
     // The maximum alignment is equal to the memory size being referenced.
     unsigned LSNAlign = LSN->getAlignment();
     unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
-    if (LSNAlign > MemSize && MemSize > 1)
+    if (LSNAlign >= MemSize && MemSize > 1)
       Alignment = MemSize;
   } else {
     // All other uses of addrmode6 are for intrinsics.  For now just record

Modified: llvm/trunk/test/CodeGen/ARM/vlddup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vlddup.ll?rev=143160&r1=143159&r2=143160&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vlddup.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vlddup.ll Thu Oct 27 17:39:16 2011
@@ -32,7 +32,7 @@
 
 define <2 x float> @vld1dupf(float* %A) nounwind {
 ;CHECK: vld1dupf:
-;CHECK: vld1.32 {d16[]}, [r0]
+;CHECK: vld1.32 {d16[]}, [r0, :32]
 	%tmp0 = load float* %A
         %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
         %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
@@ -51,7 +51,7 @@
 
 define <4 x float> @vld1dupQf(float* %A) nounwind {
 ;CHECK: vld1dupQf:
-;CHECK: vld1.32 {d16[], d17[]}, [r0]
+;CHECK: vld1.32 {d16[], d17[]}, [r0, :32]
         %tmp0 = load float* %A
         %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
         %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer

Modified: llvm/trunk/test/CodeGen/ARM/vldlane.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vldlane.ll?rev=143160&r1=143159&r2=143160&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vldlane.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vldlane.ll Thu Oct 27 17:39:16 2011
@@ -31,9 +31,19 @@
         ret <2 x i32> %tmp3
 }
 
+define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vld1lanei32a32:
+;Check the alignment value.  Legal values are none or :32.
+;CHECK: vld1.32 {d16[1]}, [r0, :32]
+	%tmp1 = load <2 x i32>* %B
+	%tmp2 = load i32* %A, align 4
+	%tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
+        ret <2 x i32> %tmp3
+}
+
 define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
 ;CHECK: vld1lanef:
-;CHECK: vld1.32 {d16[1]}, [r0]
+;CHECK: vld1.32 {d16[1]}, [r0, :32]
 	%tmp1 = load <2 x float>* %B
 	%tmp2 = load float* %A, align 4
 	%tmp3 = insertelement <2 x float> %tmp1, float %tmp2, i32 1
@@ -69,7 +79,7 @@
 
 define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
 ;CHECK: vld1laneQf:
-;CHECK: vld1.32 {d16[0]}, [r0]
+;CHECK: vld1.32 {d16[0]}, [r0, :32]
 	%tmp1 = load <4 x float>* %B
 	%tmp2 = load float* %A
 	%tmp3 = insertelement <4 x float> %tmp1, float %tmp2, i32 0

Modified: llvm/trunk/test/CodeGen/ARM/vstlane.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vstlane.ll?rev=143160&r1=143159&r2=143160&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vstlane.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vstlane.ll Thu Oct 27 17:39:16 2011
@@ -45,7 +45,7 @@
 
 define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
 ;CHECK: vst1lanef:
-;CHECK: vst1.32 {d16[1]}, [r0]
+;CHECK: vst1.32 {d16[1]}, [r0, :32]
 	%tmp1 = load <2 x float>* %B
         %tmp2 = extractelement <2 x float> %tmp1, i32 1
         store float %tmp2, float* %A



From resistor at mac.com  Thu Oct 27 17:53:10 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 27 Oct 2011 22:53:10 -0000
Subject: [llvm-commits] [llvm] r143162 -
	/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Message-ID: <20111027225310.B79753128060@llvm.org>

Author: resistor
Date: Thu Oct 27 17:53:10 2011
New Revision: 143162

URL: http://llvm.org/viewvc/llvm-project?rev=143162&view=rev
Log:
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=143162&r1=143161&r2=143162&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Oct 27 17:53:10 2011
@@ -2136,6 +2136,10 @@
   case ARM::VLD1d16wb_fixed:
   case ARM::VLD1d32wb_fixed:
   case ARM::VLD1d64wb_fixed:
+  case ARM::VLD1d8Twb_fixed:
+  case ARM::VLD1d16Twb_fixed:
+  case ARM::VLD1d32Twb_fixed:
+  case ARM::VLD1d64Twb_fixed:
   case ARM::VLD1d8wb_register:
   case ARM::VLD1d16wb_register:
   case ARM::VLD1d32wb_register:



From resistor at mac.com  Thu Oct 27 17:54:15 2011
From: resistor at mac.com (Owen Anderson)
Date: Thu, 27 Oct 2011 22:54:15 -0000
Subject: [llvm-commits] [llvm] r143163 -
	/llvm/trunk/test/MC/Disassembler/ARM/neon.txt
Message-ID: <20111027225415.0D0F13128060@llvm.org>

Author: resistor
Date: Thu Oct 27 17:54:14 2011
New Revision: 143163

URL: http://llvm.org/viewvc/llvm-project?rev=143163&view=rev
Log:
Add testcase for r143162.

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/neon.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=143163&r1=143162&r2=143163&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Thu Oct 27 17:54:14 2011
@@ -1856,3 +1856,7 @@
 
 0xe9 0x1a 0xb2 0x4e
 # CHECK: vcvttmi.f32.f16	s2, s19
+
+0x3d 0x76 0x66 0xf4
+# CHECK: vld1.8	{d23, d24, d25}, [r6, :256]!
+



From gohman at apple.com  Thu Oct 27 17:56:33 2011
From: gohman at apple.com (Dan Gohman)
Date: Thu, 27 Oct 2011 22:56:33 -0000
Subject: [llvm-commits] [llvm] r143164 - in /llvm/trunk: ./ autoconf/ cmake/
 docs/ include/llvm/ include/llvm/ADT/ lib/Support/ lib/Target/Alpha/
 projects/sample/ projects/sample/autoconf/ test/CodeGen/Alpha/
 tools/bugpoint/ utils/lit/lit/ExampleTests/LLVM.InTree/test/
 utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/
Message-ID: <20111027225633.AFEF13128060@llvm.org>

Author: djg
Date: Thu Oct 27 17:56:32 2011
New Revision: 143164

URL: http://llvm.org/viewvc/llvm-project?rev=143164&view=rev
Log:
Remove the Alpha backend.

Removed:
    llvm/trunk/include/llvm/IntrinsicsAlpha.td
    llvm/trunk/lib/Target/Alpha/
    llvm/trunk/test/CodeGen/Alpha/
Modified:
    llvm/trunk/CMakeLists.txt
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/cmake/config-ix.cmake
    llvm/trunk/configure
    llvm/trunk/docs/CMake.html
    llvm/trunk/docs/CodeGenerator.html
    llvm/trunk/docs/CompilerWriterInfo.html
    llvm/trunk/docs/UsingLibraries.html
    llvm/trunk/include/llvm/ADT/Triple.h
    llvm/trunk/include/llvm/Intrinsics.td
    llvm/trunk/lib/Support/Triple.cpp
    llvm/trunk/projects/sample/autoconf/configure.ac
    llvm/trunk/projects/sample/configure
    llvm/trunk/tools/bugpoint/ToolRunner.cpp
    llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
    llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp

Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Thu Oct 27 17:56:32 2011
@@ -64,7 +64,6 @@
 endif()
 
 set(LLVM_ALL_TARGETS
-  Alpha
   ARM
   CBackend
   CellSPU

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Thu Oct 27 17:56:32 2011
@@ -352,7 +352,6 @@
   amd64-* | x86_64-*)     llvm_cv_target_arch="x86_64" ;;
   sparc*-*)               llvm_cv_target_arch="Sparc" ;;
   powerpc*-*)             llvm_cv_target_arch="PowerPC" ;;
-  alpha*-*)               llvm_cv_target_arch="Alpha" ;;
   arm*-*)                 llvm_cv_target_arch="ARM" ;;
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
@@ -487,7 +486,6 @@
     Sparc)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     PowerPC)     AC_SUBST(TARGET_HAS_JIT,1) ;;
     x86_64)      AC_SUBST(TARGET_HAS_JIT,1) ;;
-    Alpha)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     ARM)         AC_SUBST(TARGET_HAS_JIT,1) ;;
     Mips)        AC_SUBST(TARGET_HAS_JIT,1) ;;
     XCore)       AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -603,21 +601,20 @@
 TARGETS_TO_BUILD=""
 AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
     [Build specific host targets: all or target1,target2,... Valid targets are:
-     host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu,
+     host, x86, x86_64, sparc, powerpc, arm, mips, spu,
      xcore, msp430, ptx, cbe, and cpp (default=all)]),,
     enableval=all)
 if test "$enableval" = host-only ; then
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         x86_64)   TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         sparc)    TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
         powerpc)  TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-        alpha)    TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
         arm)      TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
         mips)     TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -632,7 +629,6 @@
             x86_64)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
             Sparc)       TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
             PowerPC)     TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-            Alpha)       TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
             ARM)         TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
             Mips)        TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
             MBlaze)      TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;

Modified: llvm/trunk/cmake/config-ix.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/cmake/config-ix.cmake (original)
+++ llvm/trunk/cmake/config-ix.cmake Thu Oct 27 17:56:32 2011
@@ -309,8 +309,6 @@
   set(LLVM_NATIVE_ARCH Sparc)
 elseif (LLVM_NATIVE_ARCH MATCHES "powerpc")
   set(LLVM_NATIVE_ARCH PowerPC)
-elseif (LLVM_NATIVE_ARCH MATCHES "alpha")
-  set(LLVM_NATIVE_ARCH Alpha)
 elseif (LLVM_NATIVE_ARCH MATCHES "arm")
   set(LLVM_NATIVE_ARCH ARM)
 elseif (LLVM_NATIVE_ARCH MATCHES "mips")

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Thu Oct 27 17:56:32 2011
@@ -1415,7 +1415,7 @@
                           (default is YES)
   --enable-targets        Build specific host targets: all or
                           target1,target2,... Valid targets are: host, x86,
-                          x86_64, sparc, powerpc, alpha, arm, mips, spu,
+                          x86_64, sparc, powerpc, arm, mips, spu,
                           xcore, msp430, ptx, cbe, and cpp (default=all)
   --enable-cbe-printf-a   Enable C Backend output with hex floating point via
                           %a (default is YES)
@@ -3874,7 +3874,6 @@
   amd64-* | x86_64-*)     llvm_cv_target_arch="x86_64" ;;
   sparc*-*)               llvm_cv_target_arch="Sparc" ;;
   powerpc*-*)             llvm_cv_target_arch="PowerPC" ;;
-  alpha*-*)               llvm_cv_target_arch="Alpha" ;;
   arm*-*)                 llvm_cv_target_arch="ARM" ;;
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
@@ -5072,8 +5071,6 @@
  ;;
     x86_64)      TARGET_HAS_JIT=1
  ;;
-    Alpha)       TARGET_HAS_JIT=0
- ;;
     ARM)         TARGET_HAS_JIT=1
  ;;
     Mips)        TARGET_HAS_JIT=1
@@ -5270,14 +5267,13 @@
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         x86_64)   TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         sparc)    TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
         powerpc)  TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-        alpha)    TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
         arm)      TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
         mips)     TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -5292,7 +5288,6 @@
             x86_64)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
             Sparc)       TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
             PowerPC)     TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-            Alpha)       TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
             ARM)         TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
             Mips)        TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
             MBlaze)      TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;

Modified: llvm/trunk/docs/CMake.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CMake.html?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/docs/CMake.html (original)
+++ llvm/trunk/docs/CMake.html Thu Oct 27 17:56:32 2011
@@ -249,7 +249,7 @@
   <dd>Semicolon-separated list of targets to build, or <i>all</i> for
     building all targets. Case-sensitive. For Visual C++ defaults
     to <i>X86</i>. On the other cases defaults to <i>all</i>. Example:
-    <i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC;Alpha"</i>.</dd>
+    <i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC"</i>.</dd>
 
   <dt><b>LLVM_BUILD_TOOLS</b>:BOOL</dt>
   <dd>Build LLVM tools. Defaults to ON. Targets for building each tool

Modified: llvm/trunk/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/docs/CodeGenerator.html (original)
+++ llvm/trunk/docs/CodeGenerator.html Thu Oct 27 17:56:32 2011
@@ -2208,7 +2208,6 @@
   <tr>
     <th>Feature</th>
     <th>ARM</th>
-    <th>Alpha</th>
     <th>CellSPU</th>
     <th>MBlaze</th>
     <th>MSP430</th>
@@ -2223,7 +2222,6 @@
 <tr>
   <td><a href="#feat_reliable">is generally reliable</a></td>
   <td class="yes"></td> <!-- ARM -->
-  <td class="unknown"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
@@ -2238,7 +2236,6 @@
 <tr>
   <td><a href="#feat_asmparser">assembly parser</a></td>
   <td class="no"></td> <!-- ARM -->
-  <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
@@ -2253,7 +2250,6 @@
 <tr>
   <td><a href="#feat_disassembler">disassembler</a></td>
   <td class="yes"></td> <!-- ARM -->
-  <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
@@ -2268,7 +2264,6 @@
 <tr>
   <td><a href="#feat_inlineasm">inline asm</a></td>
   <td class="yes"></td> <!-- ARM -->
-  <td class="unknown"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
@@ -2283,7 +2278,6 @@
 <tr>
   <td><a href="#feat_jit">jit</a></td>
   <td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
-  <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
@@ -2298,7 +2292,6 @@
 <tr>
   <td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>
   <td class="no"></td> <!-- ARM -->
-  <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
@@ -2313,7 +2306,6 @@
 <tr>
   <td><a href="#feat_tailcall">tail calls</a></td>
   <td class="yes"></td> <!-- ARM -->
-  <td class="unknown"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->

Modified: llvm/trunk/docs/CompilerWriterInfo.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CompilerWriterInfo.html?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/docs/CompilerWriterInfo.html (original)
+++ llvm/trunk/docs/CompilerWriterInfo.html Thu Oct 27 17:56:32 2011
@@ -21,7 +21,6 @@
 <ol>
   <li><a href="#hw">Hardware</a>
   <ol>
-    <li><a href="#alpha">Alpha</a></li>
     <li><a href="#arm">ARM</a></li>
     <li><a href="#ia64">Itanium</a></li>
     <li><a href="#mips">MIPS</a></li>
@@ -49,17 +48,6 @@
 <div>
 
 <!-- ======================================================================= -->
-<h3><a name="alpha">Alpha</a></h3>
-
-<div>
-<ul>
-<li><a
-href="http://ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html">Alpha manuals</a> 
-</li>
-</ul>
-</div>
-
-<!-- ======================================================================= -->
 <h3><a name="arm">ARM</a></h3>
 
 <div>

Modified: llvm/trunk/docs/UsingLibraries.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/UsingLibraries.html?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/docs/UsingLibraries.html (original)
+++ llvm/trunk/docs/UsingLibraries.html Thu Oct 27 17:56:32 2011
@@ -126,8 +126,6 @@
     <td>Aggressive instruction selector for directed acyclic graphs</td></tr>
 
   <tr><th colspan="3">Target Libraries</th></tr>
-  <tr><td>LLVMAlpha</td><td><tt>.o</tt></td>
-    <td>Code generation for Alpha architecture</td></tr>
   <tr><td>LLVMARM</td><td><tt>.o</tt></td>
     <td>Code generation for ARM architecture</td></tr>
   <tr><td>LLVMCBackend</td><td><tt>.o</tt></td>
@@ -333,14 +331,6 @@
     <li>libLLVMSystem.a</li>
     <li>libLLVMTarget.a</li>
   </ul></dd>
-  <dt><b>LLVMAlpha.o</b></dt><dd><ul>
-    <li>libLLVMCodeGen.a</li>
-    <li>libLLVMCore.a</li>
-    <li>libLLVMSelectionDAG.a</li>
-    <li>libLLVMSupport.a</li>
-    <li>libLLVMSystem.a</li>
-    <li>libLLVMTarget.a</li>
-  </ul></dd>
   <dt><b>LLVMCBackend.o</b></dt><dd><ul>
     <li>libLLVMAnalysis.a</li>
     <li>libLLVMCodeGen.a</li>

Modified: llvm/trunk/include/llvm/ADT/Triple.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/Triple.h (original)
+++ llvm/trunk/include/llvm/ADT/Triple.h Thu Oct 27 17:56:32 2011
@@ -43,7 +43,6 @@
   enum ArchType {
     UnknownArch,
 
-    alpha,   // Alpha: alpha
     arm,     // ARM; arm, armv.*, xscale
     cellspu, // CellSPU: spu, cellspu
     mips,    // MIPS: mips, mipsallegrex

Modified: llvm/trunk/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Thu Oct 27 17:56:32 2011
@@ -443,6 +443,5 @@
 include "llvm/IntrinsicsX86.td"
 include "llvm/IntrinsicsARM.td"
 include "llvm/IntrinsicsCellSPU.td"
-include "llvm/IntrinsicsAlpha.td"
 include "llvm/IntrinsicsXCore.td"
 include "llvm/IntrinsicsPTX.td"

Removed: llvm/trunk/include/llvm/IntrinsicsAlpha.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsAlpha.td?rev=143163&view=auto
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsAlpha.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsAlpha.td (removed)
@@ -1,18 +0,0 @@
-//===- IntrinsicsAlpha.td - Defines Alpha intrinsics -------*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// This file defines all of the Alpha-specific intrinsics.
-//
-//===----------------------------------------------------------------------===//
-
-
-let TargetPrefix = "alpha" in {  // All intrinsics start with "llvm.alpha.".
-  def int_alpha_umulh : GCCBuiltin<"__builtin_alpha_umulh">,
-              Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
-}

Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Thu Oct 27 17:56:32 2011
@@ -18,7 +18,6 @@
   case InvalidArch: return "<invalid>";
   case UnknownArch: return "unknown";
 
-  case alpha:   return "alpha";
   case arm:     return "arm";
   case cellspu: return "cellspu";
   case mips:    return "mips";
@@ -50,8 +49,6 @@
   default:
     return 0;
 
-  case alpha:   return "alpha";
-
   case arm:
   case thumb:   return "arm";
 
@@ -131,8 +128,6 @@
 }
 
 Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
-  if (Name == "alpha")
-    return alpha;
   if (Name == "arm")
     return arm;
   if (Name == "cellspu")
@@ -286,8 +281,6 @@
   else if (ArchName == "thumb" ||
            ArchName.startswith("thumbv"))
     return thumb;
-  else if (ArchName.startswith("alpha"))
-    return alpha;
   else if (ArchName == "spu" || ArchName == "cellspu")
     return cellspu;
   else if (ArchName == "msp430")

Modified: llvm/trunk/projects/sample/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/autoconf/configure.ac?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/projects/sample/autoconf/configure.ac (original)
+++ llvm/trunk/projects/sample/autoconf/configure.ac Thu Oct 27 17:56:32 2011
@@ -296,7 +296,6 @@
   amd64-* | x86_64-*)     llvm_cv_target_arch="x86_64" ;;
   sparc*-*)               llvm_cv_target_arch="Sparc" ;;
   powerpc*-*)             llvm_cv_target_arch="PowerPC" ;;
-  alpha*-*)               llvm_cv_target_arch="Alpha" ;;
   arm*-*)                 llvm_cv_target_arch="ARM" ;;
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
@@ -431,7 +430,6 @@
     Sparc)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     PowerPC)     AC_SUBST(TARGET_HAS_JIT,1) ;;
     x86_64)      AC_SUBST(TARGET_HAS_JIT,1) ;;
-    Alpha)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     ARM)         AC_SUBST(TARGET_HAS_JIT,1) ;;
     Mips)        AC_SUBST(TARGET_HAS_JIT,1) ;;
     XCore)       AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -547,21 +545,20 @@
 TARGETS_TO_BUILD=""
 AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
     [Build specific host targets: all or target1,target2,... Valid targets are:
-     host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu,
+     host, x86, x86_64, sparc, powerpc, arm, mips, spu,
      xcore, msp430, ptx, cbe, and cpp (default=all)]),,
     enableval=all)
 if test "$enableval" = host-only ; then
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         x86_64)   TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         sparc)    TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
         powerpc)  TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-        alpha)    TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
         arm)      TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
         mips)     TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -576,7 +573,6 @@
             x86_64)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
             Sparc)       TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
             PowerPC)     TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-            Alpha)       TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
             ARM)         TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
             Mips)        TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
             MBlaze)      TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;

Modified: llvm/trunk/projects/sample/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/configure?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/projects/sample/configure (original)
+++ llvm/trunk/projects/sample/configure Thu Oct 27 17:56:32 2011
@@ -1401,7 +1401,7 @@
                           (default is YES)
   --enable-targets        Build specific host targets: all or
                           target1,target2,... Valid targets are: host, x86,
-                          x86_64, sparc, powerpc, alpha, arm, mips, spu,
+                          x86_64, sparc, powerpc, arm, mips, spu,
                           xcore, msp430, ptx, cbe, and cpp
                           (default=all)
   --enable-cbe-printf-a   Enable C Backend output with hex floating point via
@@ -3840,7 +3840,6 @@
   amd64-* | x86_64-*)     llvm_cv_target_arch="x86_64" ;;
   sparc*-*)               llvm_cv_target_arch="Sparc" ;;
   powerpc*-*)             llvm_cv_target_arch="PowerPC" ;;
-  alpha*-*)               llvm_cv_target_arch="Alpha" ;;
   arm*-*)                 llvm_cv_target_arch="ARM" ;;
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
@@ -5038,8 +5037,6 @@
  ;;
     x86_64)      TARGET_HAS_JIT=1
  ;;
-    Alpha)       TARGET_HAS_JIT=0
- ;;
     ARM)         TARGET_HAS_JIT=1
  ;;
     Mips)        TARGET_HAS_JIT=1
@@ -5236,14 +5233,13 @@
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         x86_64)   TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         sparc)    TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
         powerpc)  TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-        alpha)    TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
         arm)      TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
         mips)     TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -5258,7 +5254,6 @@
             x86_64)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
             Sparc)       TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
             PowerPC)     TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-            Alpha)       TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
             ARM)         TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
             Mips)        TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
             MBlaze)      TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;

Modified: llvm/trunk/tools/bugpoint/ToolRunner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ToolRunner.cpp?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/tools/bugpoint/ToolRunner.cpp (original)
+++ llvm/trunk/tools/bugpoint/ToolRunner.cpp Thu Oct 27 17:56:32 2011
@@ -920,8 +920,7 @@
   } else
     GCCArgs.push_back("-shared");  // `-shared' for Linux/X86, maybe others
 
-  if ((TargetTriple.getArch() == Triple::alpha) ||
-      (TargetTriple.getArch() == Triple::x86_64))
+  if (TargetTriple.getArch() == Triple::x86_64)
     GCCArgs.push_back("-fPIC");   // Requires shared objs to contain PIC
 
   if (TargetTriple.getArch() == Triple::sparc)

Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp Thu Oct 27 17:56:32 2011
@@ -2,7 +2,7 @@
 # Do not edit here.  If you wish to override these values
 # edit the last section
 set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
 set srcroot "/Volumes/Data/ddunbar/llvm"
 set objroot "/Volumes/Data/ddunbar/llvm.obj.64"
 set srcdir "/Volumes/Data/ddunbar/llvm/test"

Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp Thu Oct 27 17:56:32 2011
@@ -2,7 +2,7 @@
 # Do not edit here.  If you wish to override these values
 # edit the last section
 set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
 set srcroot "/Volumes/Data/ddunbar/llvm"
 set objroot "/Volumes/Data/ddunbar/llvm.obj.64"
 set srcdir "/Volumes/Data/ddunbar/llvm/test"



From grosbach at apple.com  Thu Oct 27 19:06:50 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 28 Oct 2011 00:06:50 -0000
Subject: [llvm-commits] [llvm] r143167 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-vld-encoding.s
Message-ID: <20111028000650.9D8E33128060@llvm.org>

Author: grosbach
Date: Thu Oct 27 19:06:50 2011
New Revision: 143167

URL: http://llvm.org/viewvc/llvm-project?rev=143167&view=rev
Log:
ARM Allow 'q' registers in VLD/VST vector lists.

Just treat it as if the constituent D registers where specified.

rdar://10348896

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/neon-vld-encoding.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=143167&r1=143166&r2=143167&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Oct 27 19:06:50 2011
@@ -2440,6 +2440,29 @@
   return false;
 }
 
+// Return the low-subreg of a given Q register.
+static unsigned getDRegFromQReg(unsigned QReg) {
+  switch (QReg) {
+  default: llvm_unreachable("expected a Q register!");
+  case ARM::Q0:  return ARM::D0;
+  case ARM::Q1:  return ARM::D2;
+  case ARM::Q2:  return ARM::D4;
+  case ARM::Q3:  return ARM::D6;
+  case ARM::Q4:  return ARM::D8;
+  case ARM::Q5:  return ARM::D10;
+  case ARM::Q6:  return ARM::D12;
+  case ARM::Q7:  return ARM::D14;
+  case ARM::Q8:  return ARM::D16;
+  case ARM::Q9:  return ARM::D19;
+  case ARM::Q10: return ARM::D20;
+  case ARM::Q11: return ARM::D22;
+  case ARM::Q12: return ARM::D24;
+  case ARM::Q13: return ARM::D26;
+  case ARM::Q14: return ARM::D28;
+  case ARM::Q15: return ARM::D30;
+  }
+}
+
 // parse a vector register list
 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
@@ -2455,9 +2478,16 @@
     Error(RegLoc, "register expected");
     return MatchOperand_ParseFail;
   }
-
-  unsigned FirstReg = Reg;
   unsigned Count = 1;
+  unsigned FirstReg = Reg;
+  // The list is of D registers, but we also allow Q regs and just interpret
+  // them as the two D sub-registers.
+  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
+    FirstReg = Reg = getDRegFromQReg(Reg);
+    ++Reg;
+    ++Count;
+  }
+
   while (Parser.getTok().is(AsmToken::Comma)) {
     Parser.Lex(); // Eat the comma.
     RegLoc = Parser.getTok().getLoc();
@@ -2467,14 +2497,27 @@
       Error(RegLoc, "register expected");
       return MatchOperand_ParseFail;
     }
-    // vector register lists must also be contiguous.
+    // vector register lists must be contiguous.
     // It's OK to use the enumeration values directly here rather, as the
     // VFP register classes have the enum sorted properly.
+    //
+    // The list is of D registers, but we also allow Q regs and just interpret
+    // them as the two D sub-registers.
+    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
+      Reg = getDRegFromQReg(Reg);
+      if (Reg != OldReg + 1) {
+        Error(RegLoc, "non-contiguous register range");
+        return MatchOperand_ParseFail;
+      }
+      ++Reg;
+      Count += 2;
+      continue;
+    }
+    // Normal D register. Just check that it's contiguous and keep going.
     if (Reg != OldReg + 1) {
       Error(RegLoc, "non-contiguous register range");
       return MatchOperand_ParseFail;
     }
-
     ++Count;
   }
 

Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=143167&r1=143166&r2=143167&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Thu Oct 27 19:06:50 2011
@@ -214,3 +214,12 @@
 @ FIXME: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xe0,0xf4]
 @ FIXME: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] @ encoding: [0x7f,0x07,0xe0,0xf4]
 @ FIXME: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xe0,0xf4]
+
+
+@ Handle 'Q' registers in register lists as if the sub-reg D regs were
+@ specified instead.
+	vld1.8 {q3}, [r9]
+	vld1.8 {q3, q4}, [r9]
+
+@ CHECK: vld1.8	{d6, d7}, [r9]          @ encoding: [0x0f,0x6a,0x29,0xf4]
+@ CHECK: vld1.8	{d6, d7, d8, d9}, [r9]  @ encoding: [0x0f,0x62,0x29,0xf4]



From peter at pcc.me.uk  Thu Oct 27 20:02:16 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Fri, 28 Oct 2011 01:02:16 -0000
Subject: [llvm-commits] [llvm] r143171 - in /llvm/trunk/tools/llvm-config:
 CMakeLists.txt Makefile llvm-config.in.in
Message-ID: <20111028010216.C05673128060@llvm.org>

Author: pcc
Date: Thu Oct 27 20:02:16 2011
New Revision: 143171

URL: http://llvm.org/viewvc/llvm-project?rev=143171&view=rev
Log:
Have llvm-config --cppflags print correct flags when in CMake build directory

Previously, if invoked from a CMake build directory, 'llvm-config
--cppflags' and friends would only print a -I flag for the build
directory's header search path, because it would assume that it was
already installed, not recognising its parent directory as being the
build directory.  Teach llvm-config about CMake build directories
so that it prints a -I for both the source and build directory's
search paths.

Modified:
    llvm/trunk/tools/llvm-config/CMakeLists.txt
    llvm/trunk/tools/llvm-config/Makefile
    llvm/trunk/tools/llvm-config/llvm-config.in.in

Modified: llvm/trunk/tools/llvm-config/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/CMakeLists.txt?rev=143171&r1=143170&r2=143171&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-config/CMakeLists.txt (original)
+++ llvm/trunk/tools/llvm-config/CMakeLists.txt Thu Oct 27 20:02:16 2011
@@ -48,6 +48,7 @@
 set(LLVM_LDFLAGS "@LLVM_LDFLAGS@")
 set(LIBS "@LIBS@")
 set(LLVM_BUILDMODE "@LLVM_BUILDMODE@")
+set(LLVM_OBJ_SUFFIX "@LLVM_OBJ_SUFFIX@")
 
 configure_file(
   ${CMAKE_CURRENT_SOURCE_DIR}/llvm-config.in.in
@@ -114,6 +115,7 @@
   COMMAND echo s!@LLVM_LDFLAGS@!${CMAKE_SHARED_LINKER_FLAGS}! >> temp.sed
   COMMAND echo s!@LIBS@!${LLVM_SYSTEM_LIBS}! >> temp.sed
   COMMAND echo s!@LLVM_BUILDMODE@!${CMAKE_BUILD_TYPE}! >> temp.sed
+  COMMAND echo s!@LLVM_OBJ_SUFFIX@!! >> temp.sed
   COMMAND sed -f temp.sed < ${LLVM_CONFIG_IN} > ${LLVM_CONFIG}
   COMMAND ${CMAKE_COMMAND} -E remove -f temp.sed
   COMMAND cat ${FINAL_LIBDEPS} >> ${LLVM_CONFIG}

Modified: llvm/trunk/tools/llvm-config/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/Makefile?rev=143171&r1=143170&r2=143171&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-config/Makefile (original)
+++ llvm/trunk/tools/llvm-config/Makefile Thu Oct 27 20:02:16 2011
@@ -68,6 +68,8 @@
 	>> temp.sed
 	$(Verb) $(ECHO) 's/@LLVM_BUILDMODE@/$(subst /,\/,$(BuildMode))/' \
 	>> temp.sed
+	$(Verb) $(ECHO) 's/@LLVM_OBJ_SUFFIX@/$(subst /,\/,/$(BuildMode))/' \
+	>> temp.sed
 	$(Verb) $(SED) -f temp.sed < $< > $@
 	$(Verb) $(RM) temp.sed
 	$(Verb) cat PerobjDepsFinal.txt >> $@
@@ -88,6 +90,8 @@
 	>> temp.sed
 	$(Verb) $(ECHO) 's/@LLVM_BUILDMODE@/$(subst /,\/,$(BuildMode))/' \
 	>> temp.sed
+	$(Verb) $(ECHO) 's/@LLVM_OBJ_SUFFIX@/$(subst /,\/,/$(BuildMode))/' \
+	>> temp.sed
 	$(Verb) $(SED) -f temp.sed < $< > $@
 	$(Verb) $(RM) temp.sed
 	$(Verb) cat PerobjDepsInclFinal.txt >> $@
@@ -106,6 +110,8 @@
 	  >> temp.sed
 	$(Verb) $(ECHO) 's/@LLVM_BUILDMODE@/$(subst /,\/,$(BuildMode))/' \
 	  >> temp.sed
+	$(Verb) $(ECHO) 's/@LLVM_OBJ_SUFFIX@/$(subst /,\/,/$(BuildMode))/' \
+	  >> temp.sed
 	$(Verb) $(SED) -f temp.sed < $< > $@
 	$(Verb) $(RM) temp.sed
 	$(Verb) cat $(FinalLibDeps) >> $@

Modified: llvm/trunk/tools/llvm-config/llvm-config.in.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/llvm-config.in.in?rev=143171&r1=143170&r2=143171&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-config/llvm-config.in.in (original)
+++ llvm/trunk/tools/llvm-config/llvm-config.in.in Thu Oct 27 20:02:16 2011
@@ -45,6 +45,7 @@
 my $LDFLAGS             = q{@LLVM_LDFLAGS@};
 my $SYSTEM_LIBS         = q{@LIBS@};
 my $LLVM_BUILDMODE      = q{@LLVM_BUILDMODE@};
+my $LLVM_OBJ_SUFFIX     = q{@LLVM_OBJ_SUFFIX@};
 #---- end Makefile values ----
 
 # Figure out where llvm-config is being run from.  Primarily, we care if it has
@@ -60,7 +61,7 @@
 chomp($ABS_RUN_DIR);
 
 # Compute the absolute object directory build, e.g. "foo/llvm/Debug".
-my $ABS_OBJ_ROOT = "$LLVM_OBJ_ROOT/$LLVM_BUILDMODE";
+my $ABS_OBJ_ROOT = "$LLVM_OBJ_ROOT$LLVM_OBJ_SUFFIX";
 $ABS_OBJ_ROOT = abs_path("$ABS_OBJ_ROOT") if (-d $ABS_OBJ_ROOT);
 chomp($ABS_OBJ_ROOT);
 



From gohman at apple.com  Thu Oct 27 20:29:33 2011
From: gohman at apple.com (Dan Gohman)
Date: Fri, 28 Oct 2011 01:29:33 -0000
Subject: [llvm-commits] [llvm] r143177 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ lib/Target/XCore/
 test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb/
 test/CodeGen/X86/
Message-ID: <20111028012933.AFA263128060@llvm.org>

Author: djg
Date: Thu Oct 27 20:29:32 2011
New Revision: 143177

URL: http://llvm.org/viewvc/llvm-project?rev=143177&view=rev
Log:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.

Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.

Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.

Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.

This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.

Removed:
    llvm/trunk/test/CodeGen/X86/2009-02-05-CoalescerBug.ll
    llvm/trunk/test/CodeGen/X86/dbg-inline.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
    llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
    llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll
    llvm/trunk/test/CodeGen/CellSPU/nand.ll
    llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
    llvm/trunk/test/CodeGen/CellSPU/select_bits.ll
    llvm/trunk/test/CodeGen/CellSPU/struct_1.ll
    llvm/trunk/test/CodeGen/Mips/cprestore.ll
    llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
    llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
    llvm/trunk/test/CodeGen/X86/sse3.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Oct 27 20:29:32 2011
@@ -46,37 +46,18 @@
 /// will attempt merge setcc and brc instructions into brcc's.
 ///
 namespace {
-class SelectionDAGLegalize {
+class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
   const TargetMachine &TM;
   const TargetLowering &TLI;
   SelectionDAG &DAG;
 
-  // Libcall insertion helpers.
+  /// LegalizePosition - The iterator for walking through the node list.
+  SelectionDAG::allnodes_iterator LegalizePosition;
 
-  /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
-  /// legalized.  We use this to ensure that calls are properly serialized
-  /// against each other, including inserted libcalls.
-  SDValue LastCALLSEQ_END;
-
-  /// IsLegalizingCall - This member is used *only* for purposes of providing
-  /// helpful assertions that a libcall isn't created while another call is
-  /// being legalized (which could lead to non-serialized call sequences).
-  bool IsLegalizingCall;
-
-  /// LegalizedNodes - For nodes that are of legal width, and that have more
-  /// than one use, this map indicates what regularized operand to use.  This
-  /// allows us to avoid legalizing the same thing more than once.
-  DenseMap<SDValue, SDValue> LegalizedNodes;
-
-  void AddLegalizedOperand(SDValue From, SDValue To) {
-    LegalizedNodes.insert(std::make_pair(From, To));
-    // If someone requests legalization of the new node, return itself.
-    if (From != To)
-      LegalizedNodes.insert(std::make_pair(To, To));
+  /// LegalizedNodes - The set of nodes which have already been legalized.
+  SmallPtrSet<SDNode *, 16> LegalizedNodes;
 
-    // Transfer SDDbgValues.
-    DAG.TransferDbgValues(From, To);
-  }
+  // Libcall insertion helpers.
 
 public:
   explicit SelectionDAGLegalize(SelectionDAG &DAG);
@@ -84,9 +65,8 @@
   void LegalizeDAG();
 
 private:
-  /// LegalizeOp - Return a legal replacement for the given operation, with
-  /// all legal operands.
-  SDValue LegalizeOp(SDValue O);
+  /// LegalizeOp - Legalizes the given operation.
+  void LegalizeOp(SDNode *Node);
 
   SDValue OptimizeFloatStore(StoreSDNode *ST);
 
@@ -107,9 +87,6 @@
                                      SDValue N1, SDValue N2,
                                      SmallVectorImpl<int> &Mask) const;
 
-  bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
-                                    SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
-
   void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
                              DebugLoc dl);
 
@@ -150,10 +127,21 @@
   SDValue ExpandInsertToVectorThroughStack(SDValue Op);
   SDValue ExpandVectorBuildThroughStack(SDNode* Node);
 
+  SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
+
   std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
 
-  void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
-  void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
+  void ExpandNode(SDNode *Node);
+  void PromoteNode(SDNode *Node);
+
+  // DAGUpdateListener implementation.
+  virtual void NodeDeleted(SDNode *N, SDNode *E) {
+    LegalizedNodes.erase(N);
+    if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
+      ++LegalizePosition;
+  }
+
+  virtual void NodeUpdated(SDNode *N) {}
 };
 }
 
@@ -195,145 +183,54 @@
 }
 
 void SelectionDAGLegalize::LegalizeDAG() {
-  LastCALLSEQ_END = DAG.getEntryNode();
-  IsLegalizingCall = false;
-
-  // The legalize process is inherently a bottom-up recursive process (users
-  // legalize their uses before themselves).  Given infinite stack space, we
-  // could just start legalizing on the root and traverse the whole graph.  In
-  // practice however, this causes us to run out of stack space on large basic
-  // blocks.  To avoid this problem, compute an ordering of the nodes where each
-  // node is only legalized after all of its operands are legalized.
   DAG.AssignTopologicalOrder();
-  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
-       E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
-    LegalizeOp(SDValue(I, 0));
-
-  // Finally, it's possible the root changed.  Get the new root.
-  SDValue OldRoot = DAG.getRoot();
-  assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
-  DAG.setRoot(LegalizedNodes[OldRoot]);
-
-  LegalizedNodes.clear();
 
-  // Remove dead nodes now.
-  DAG.RemoveDeadNodes();
-}
-
-
-/// FindCallEndFromCallStart - Given a chained node that is part of a call
-/// sequence, find the CALLSEQ_END node that terminates the call sequence.
-static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
-  // Nested CALLSEQ_START/END constructs aren't yet legal,
-  // but we can DTRT and handle them correctly here.
-  if (Node->getOpcode() == ISD::CALLSEQ_START)
-    depth++;
-  else if (Node->getOpcode() == ISD::CALLSEQ_END) {
-    depth--;
-    if (depth == 0)
-      return Node;
-  }
-  if (Node->use_empty())
-    return 0;   // No CallSeqEnd
-
-  // The chain is usually at the end.
-  SDValue TheChain(Node, Node->getNumValues()-1);
-  if (TheChain.getValueType() != MVT::Other) {
-    // Sometimes it's at the beginning.
-    TheChain = SDValue(Node, 0);
-    if (TheChain.getValueType() != MVT::Other) {
-      // Otherwise, hunt for it.
-      for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
-        if (Node->getValueType(i) == MVT::Other) {
-          TheChain = SDValue(Node, i);
-          break;
-        }
-
-      // Otherwise, we walked into a node without a chain.
-      if (TheChain.getValueType() != MVT::Other)
-        return 0;
-    }
+#if 0
+  SDValue LastChain = DAG.getEntryNode();
+  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
+       E = DAG.allnodes_end(); I != E; ++I) {
+    SDNode *N = I;
+    if (N->getOpcode() == ISD::CALLSEQ_START) {
+      SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
+      Ops[0] = LastChain;
+      SDNode *New = DAG.UpdateNodeOperands(N, Ops.data(), Ops.size());
+      assert(New == N && "CALLSEQ_START got CSE'd!");
+    }
+    for (unsigned i = 0, e = N->getNumValues(); i != e; ++i)
+      if (N->getValueType(i) == MVT::Other)
+        LastChain = SDValue(N, i);
   }
+#endif
 
-  for (SDNode::use_iterator UI = Node->use_begin(),
-       E = Node->use_end(); UI != E; ++UI) {
-
-    // Make sure to only follow users of our token chain.
-    SDNode *User = *UI;
-    for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
-      if (User->getOperand(i) == TheChain)
-        if (SDNode *Result = FindCallEndFromCallStart(User, depth))
-          return Result;
-  }
-  return 0;
-}
-
-/// FindCallStartFromCallEnd - Given a chained node that is part of a call
-/// sequence, find the CALLSEQ_START node that initiates the call sequence.
-static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
-  int nested = 0;
-  assert(Node && "Didn't find callseq_start for a call??");
-  while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
-    Node = Node->getOperand(0).getNode();
-    assert(Node->getOperand(0).getValueType() == MVT::Other &&
-           "Node doesn't have a token chain argument!");
-    switch (Node->getOpcode()) {
-    default:
-      break;
-    case ISD::CALLSEQ_START:
-      if (!nested)
-        return Node;
-      nested--;
-      break;
-    case ISD::CALLSEQ_END:
-      nested++;
-      break;
+  // Visit all the nodes. We start in topological order, so that we see
+  // nodes with their original operands intact. Legalization can produce
+  // new nodes which may themselves need to be legalized. Iterate until all
+  // nodes have been legalized.
+  for (;;) {
+    bool AnyLegalized = false;
+    for (LegalizePosition = DAG.allnodes_end();
+         LegalizePosition != DAG.allnodes_begin(); ) {
+      --LegalizePosition;
+
+      SDNode *N = LegalizePosition;
+      if (LegalizedNodes.insert(N)) {
+        AnyLegalized = true;
+        LegalizeOp(N);
+      }
     }
-  }
-  return 0;
-}
+    if (!AnyLegalized)
+      break;
 
-/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
-/// see if any uses can reach Dest.  If no dest operands can get to dest,
-/// legalize them, legalize ourself, and return false, otherwise, return true.
-///
-/// Keep track of the nodes we fine that actually do lead to Dest in
-/// NodesLeadingTo.  This avoids retraversing them exponential number of times.
-///
-bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
-                                     SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
-  if (N == Dest) return true;  // N certainly leads to Dest :)
-
-  // If we've already processed this node and it does lead to Dest, there is no
-  // need to reprocess it.
-  if (NodesLeadingTo.count(N)) return true;
-
-  // If the first result of this node has been already legalized, then it cannot
-  // reach N.
-  if (LegalizedNodes.count(SDValue(N, 0))) return false;
-
-  // Okay, this node has not already been legalized.  Check and legalize all
-  // operands.  If none lead to Dest, then we can legalize this node.
-  bool OperandsLeadToDest = false;
-  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-    OperandsLeadToDest |=     // If an operand leads to Dest, so do we.
-      LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
-                                   NodesLeadingTo);
-
-  if (OperandsLeadToDest) {
-    NodesLeadingTo.insert(N);
-    return true;
   }
 
-  // Okay, this node looks safe, legalize it and return false.
-  LegalizeOp(SDValue(N, 0));
-  return false;
+  // Remove dead nodes now.
+  DAG.RemoveDeadNodes();
 }
 
 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
 /// a load from the constant pool.
-static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
-                                SelectionDAG &DAG, const TargetLowering &TLI) {
+SDValue
+SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
   bool Extend = false;
   DebugLoc dl = CFP->getDebugLoc();
 
@@ -369,20 +266,25 @@
 
   SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
   unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
-  if (Extend)
-    return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
-                          DAG.getEntryNode(),
-                          CPIdx, MachinePointerInfo::getConstantPool(),
-                          VT, false, false, Alignment);
-  return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
-                     MachinePointerInfo::getConstantPool(), false, false,
-                     Alignment);
+  if (Extend) {
+    SDValue Result =
+      DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
+                     DAG.getEntryNode(),
+                     CPIdx, MachinePointerInfo::getConstantPool(),
+                     VT, false, false, Alignment);
+    return Result;
+  }
+  SDValue Result =
+    DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
+                MachinePointerInfo::getConstantPool(), false, false,
+                Alignment);
+  return Result;
 }
 
 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
-static
-SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
-                             const TargetLowering &TLI) {
+static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
+                                 const TargetLowering &TLI,
+                                 SelectionDAG::DAGUpdateListener *DUL) {
   SDValue Chain = ST->getChain();
   SDValue Ptr = ST->getBasePtr();
   SDValue Val = ST->getValue();
@@ -397,8 +299,10 @@
       // same size, then a (misaligned) int store.
       // FIXME: Does not handle truncating floating point stores!
       SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
-      return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
-                          ST->isVolatile(), ST->isNonTemporal(), Alignment);
+      Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
+                           ST->isVolatile(), ST->isNonTemporal(), Alignment);
+      DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
+      return;
     }
     // Do a (aligned) store to a stack slot, then copy from the stack slot
     // to the final destination using (unaligned) integer loads and stores.
@@ -458,8 +362,11 @@
                                        ST->isNonTemporal(),
                                        MinAlign(ST->getAlignment(), Offset)));
     // The order of the stores doesn't matter - say it with a TokenFactor.
-    return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
-                       Stores.size());
+    SDValue Result =
+      DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
+                  Stores.size());
+    DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
+    return;
   }
   assert(ST->getMemoryVT().isInteger() &&
          !ST->getMemoryVT().isVector() &&
@@ -488,13 +395,16 @@
                              NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
                              Alignment);
 
-  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
+  SDValue Result =
+    DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
+  DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
 }
 
 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
-static
-SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
-                            const TargetLowering &TLI) {
+static void
+ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
+                    const TargetLowering &TLI,
+                    SDValue &ValResult, SDValue &ChainResult) {
   SDValue Chain = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
   EVT VT = LD->getValueType(0);
@@ -512,8 +422,9 @@
       if (VT.isFloatingPoint() && LoadedVT != VT)
         Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
 
-      SDValue Ops[] = { Result, Chain };
-      return DAG.getMergeValues(Ops, 2, dl);
+      ValResult = Result;
+      ChainResult = Chain;
+      return;
     }
 
     // Copy the value to a (aligned) stack slot using (unaligned) integer
@@ -572,8 +483,9 @@
                           MachinePointerInfo(), LoadedVT, false, false, 0);
 
     // Callers expect a MERGE_VALUES node.
-    SDValue Ops[] = { Load, TF };
-    return DAG.getMergeValues(Ops, 2, dl);
+    ValResult = Load;
+    ChainResult = TF;
+    return;
   }
   assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
          "Unaligned load of unsupported type.");
@@ -626,8 +538,8 @@
   SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                              Hi.getValue(1));
 
-  SDValue Ops[] = { Result, TF };
-  return DAG.getMergeValues(Ops, 2, dl);
+  ValResult = Result;
+  ChainResult = TF;
 }
 
 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
@@ -763,11 +675,10 @@
 
 /// LegalizeOp - Return a legal replacement for the given operation, with
 /// all legal operands.
-SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
-  if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
-    return Op;
+void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
+  if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
+    return;
 
-  SDNode *Node = Op.getNode();
   DebugLoc dl = Node->getDebugLoc();
 
   for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
@@ -782,13 +693,7 @@
             Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
            "Unexpected illegal type!");
 
-  // Note that LegalizeOp may be reentered even from single-use nodes, which
-  // means that we always must cache transformed nodes.
-  DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
-  if (I != LegalizedNodes.end()) return I->second;
-
   SDValue Tmp1, Tmp2, Tmp3, Tmp4;
-  SDValue Result = Op;
   bool isCustom = false;
 
   // Figure out the correct action; the way to query this varies by opcode
@@ -882,17 +787,6 @@
     if (Action == TargetLowering::Legal)
       Action = TargetLowering::Custom;
     break;
-  case ISD::BUILD_VECTOR:
-    // A weird case: legalization for BUILD_VECTOR never legalizes the
-    // operands!
-    // FIXME: This really sucks... changing it isn't semantically incorrect,
-    // but it massively pessimizes the code for floating-point BUILD_VECTORs
-    // because ConstantFP operands get legalized into constant pool loads
-    // before the BUILD_VECTOR code can see them.  It doesn't usually bite,
-    // though, because BUILD_VECTORS usually get lowered into other nodes
-    // which get legalized properly.
-    SimpleFinishLegalizing = false;
-    break;
   default:
     if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
       Action = TargetLowering::Legal;
@@ -903,22 +797,11 @@
   }
 
   if (SimpleFinishLegalizing) {
-    SmallVector<SDValue, 8> Ops, ResultVals;
+    SmallVector<SDValue, 8> Ops;
     for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
-      Ops.push_back(LegalizeOp(Node->getOperand(i)));
+      Ops.push_back(Node->getOperand(i));
     switch (Node->getOpcode()) {
     default: break;
-    case ISD::BR:
-    case ISD::BRIND:
-    case ISD::BR_JT:
-    case ISD::BR_CC:
-    case ISD::BRCOND:
-      // Branches tweak the chain to include LastCALLSEQ_END
-      Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
-                           LastCALLSEQ_END);
-      Ops[0] = LegalizeOp(Ops[0]);
-      LastCALLSEQ_END = DAG.getEntryNode();
-      break;
     case ISD::SHL:
     case ISD::SRL:
     case ISD::SRA:
@@ -926,57 +809,66 @@
     case ISD::ROTR:
       // Legalizing shifts/rotates requires adjusting the shift amount
       // to the appropriate width.
-      if (!Ops[1].getValueType().isVector())
-        Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
-                                                      Ops[1]));
+      if (!Ops[1].getValueType().isVector()) {
+        SDValue SAO = DAG.getShiftAmountOperand(Ops[0].getValueType(), Ops[1]);
+        HandleSDNode Handle(SAO);
+        LegalizeOp(SAO.getNode());
+        Ops[1] = Handle.getValue();
+      }
       break;
     case ISD::SRL_PARTS:
     case ISD::SRA_PARTS:
     case ISD::SHL_PARTS:
       // Legalizing shifts/rotates requires adjusting the shift amount
       // to the appropriate width.
-      if (!Ops[2].getValueType().isVector())
-        Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
-                                                      Ops[2]));
+      if (!Ops[2].getValueType().isVector()) {
+        SDValue SAO = DAG.getShiftAmountOperand(Ops[0].getValueType(), Ops[2]);
+        HandleSDNode Handle(SAO);
+        LegalizeOp(SAO.getNode());
+        Ops[2] = Handle.getValue();
+      }
       break;
     }
 
-    Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
-                                            Ops.size()), 0);
+    SDNode *NewNode = DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
+    if (NewNode != Node) {
+      DAG.ReplaceAllUsesWith(Node, NewNode, this);
+      for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
+        DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
+      DAG.RemoveDeadNode(Node, this);
+      Node = NewNode;
+    }
     switch (Action) {
     case TargetLowering::Legal:
-      for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
-        ResultVals.push_back(Result.getValue(i));
-      break;
+      return;
     case TargetLowering::Custom:
       // FIXME: The handling for custom lowering with multiple results is
       // a complete mess.
-      Tmp1 = TLI.LowerOperation(Result, DAG);
+      Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
       if (Tmp1.getNode()) {
+        SmallVector<SDValue, 8> ResultVals;
         for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
           if (e == 1)
             ResultVals.push_back(Tmp1);
           else
             ResultVals.push_back(Tmp1.getValue(i));
         }
-        break;
+        if (Tmp1.getNode() != Node || Tmp1.getResNo() != 0) {
+          DAG.ReplaceAllUsesWith(Node, ResultVals.data(), this);
+          for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
+            DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
+          DAG.RemoveDeadNode(Node, this);
+        }
+        return;
       }
 
       // FALL THROUGH
     case TargetLowering::Expand:
-      ExpandNode(Result.getNode(), ResultVals);
-      break;
+      ExpandNode(Node);
+      return;
     case TargetLowering::Promote:
-      PromoteNode(Result.getNode(), ResultVals);
-      break;
-    }
-    if (!ResultVals.empty()) {
-      for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
-        if (ResultVals[i] != SDValue(Node, i))
-          ResultVals[i] = LegalizeOp(ResultVals[i]);
-        AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
-      }
-      return ResultVals[Op.getResNo()];
+      PromoteNode(Node);
+      return;
     }
   }
 
@@ -989,155 +881,20 @@
 #endif
     assert(0 && "Do not know how to legalize this operator!");
 
-  case ISD::SRA:
-  case ISD::SRL:
-  case ISD::SHL: {
-    // Scalarize vector SRA/SRL/SHL.
-    EVT VT = Node->getValueType(0);
-    assert(VT.isVector() && "Unable to legalize non-vector shift");
-    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
-    unsigned NumElem = VT.getVectorNumElements();
-
-    SmallVector<SDValue, 8> Scalars;
-    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
-      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
-                               VT.getScalarType(),
-                               Node->getOperand(0), DAG.getIntPtrConstant(Idx));
-      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
-                               VT.getScalarType(),
-                               Node->getOperand(1), DAG.getIntPtrConstant(Idx));
-      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
-                                    VT.getScalarType(), Ex, Sh));
-    }
-    Result = DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
-                         &Scalars[0], Scalars.size());
-    break;
-  }
-
-  case ISD::BUILD_VECTOR:
-    switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
-    default: assert(0 && "This action is not supported yet!");
-    case TargetLowering::Custom:
-      Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.getNode()) {
-        Result = Tmp3;
-        break;
-      }
-      // FALLTHROUGH
-    case TargetLowering::Expand:
-      Result = ExpandBUILD_VECTOR(Result.getNode());
-      break;
-    }
-    break;
-  case ISD::CALLSEQ_START: {
-    SDNode *CallEnd = FindCallEndFromCallStart(Node);
-
-    // Recursively Legalize all of the inputs of the call end that do not lead
-    // to this call start.  This ensures that any libcalls that need be inserted
-    // are inserted *before* the CALLSEQ_START.
-    {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
-    for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
-      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
-                                   NodesLeadingTo);
-    }
-
-    // Now that we have legalized all of the inputs (which may have inserted
-    // libcalls), create the new CALLSEQ_START node.
-    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
-
-    // Merge in the last call to ensure that this call starts after the last
-    // call ended.
-    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
-      Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
-                         Tmp1, LastCALLSEQ_END);
-      Tmp1 = LegalizeOp(Tmp1);
-    }
-
-    // Do not try to legalize the target-specific arguments (#1+).
-    if (Tmp1 != Node->getOperand(0)) {
-      SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
-      Ops[0] = Tmp1;
-      Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
-                                              Ops.size()), Result.getResNo());
-    }
-
-    // Remember that the CALLSEQ_START is legalized.
-    AddLegalizedOperand(Op.getValue(0), Result);
-    if (Node->getNumValues() == 2)    // If this has a flag result, remember it.
-      AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
-
-    // Now that the callseq_start and all of the non-call nodes above this call
-    // sequence have been legalized, legalize the call itself.  During this
-    // process, no libcalls can/will be inserted, guaranteeing that no calls
-    // can overlap.
-    assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
-    // Note that we are selecting this call!
-    LastCALLSEQ_END = SDValue(CallEnd, 0);
-    IsLegalizingCall = true;
-
-    // Legalize the call, starting from the CALLSEQ_END.
-    LegalizeOp(LastCALLSEQ_END);
-    assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
-    return Result;
-  }
+  case ISD::CALLSEQ_START:
   case ISD::CALLSEQ_END:
-    // If the CALLSEQ_START node hasn't been legalized first, legalize it.  This
-    // will cause this node to be legalized as well as handling libcalls right.
-    if (LastCALLSEQ_END.getNode() != Node) {
-      LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
-      DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
-      assert(I != LegalizedNodes.end() &&
-             "Legalizing the call start should have legalized this node!");
-      return I->second;
-    }
-
-    // Otherwise, the call start has been legalized and everything is going
-    // according to plan.  Just legalize ourselves normally here.
-    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
-    // Do not try to legalize the target-specific arguments (#1+), except for
-    // an optional flag input.
-    if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
-      if (Tmp1 != Node->getOperand(0)) {
-        SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
-        Ops[0] = Tmp1;
-        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                                &Ops[0], Ops.size()),
-                         Result.getResNo());
-      }
-    } else {
-      Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
-      if (Tmp1 != Node->getOperand(0) ||
-          Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
-        SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
-        Ops[0] = Tmp1;
-        Ops.back() = Tmp2;
-        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                                &Ops[0], Ops.size()),
-                         Result.getResNo());
-      }
-    }
-    assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
-    // This finishes up call legalization.
-    IsLegalizingCall = false;
-
-    // If the CALLSEQ_END node has a flag, remember that we legalized it.
-    AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
-    if (Node->getNumValues() == 2)
-      AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.getResNo());
+    break;
   case ISD::LOAD: {
     LoadSDNode *LD = cast<LoadSDNode>(Node);
-    Tmp1 = LegalizeOp(LD->getChain());   // Legalize the chain.
-    Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
+    Tmp1 = LD->getChain();   // Legalize the chain.
+    Tmp2 = LD->getBasePtr(); // Legalize the base pointer.
 
     ISD::LoadExtType ExtType = LD->getExtensionType();
     if (ExtType == ISD::NON_EXTLOAD) {
       EVT VT = Node->getValueType(0);
-      Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                              Tmp1, Tmp2, LD->getOffset()),
-                       Result.getResNo());
-      Tmp3 = Result.getValue(0);
-      Tmp4 = Result.getValue(1);
+      Node = DAG.UpdateNodeOperands(Node, Tmp1, Tmp2, LD->getOffset());
+      Tmp3 = SDValue(Node, 0);
+      Tmp4 = SDValue(Node, 1);
 
       switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
       default: assert(0 && "This action is not supported yet!");
@@ -1148,20 +905,16 @@
           Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
           unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
           if (LD->getAlignment() < ABIAlignment){
-            Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
-                                         DAG, TLI);
-            Tmp3 = Result.getOperand(0);
-            Tmp4 = Result.getOperand(1);
-            Tmp3 = LegalizeOp(Tmp3);
-            Tmp4 = LegalizeOp(Tmp4);
+            ExpandUnalignedLoad(cast<LoadSDNode>(Node),
+                                DAG, TLI, Tmp3, Tmp4);
           }
         }
         break;
       case TargetLowering::Custom:
         Tmp1 = TLI.LowerOperation(Tmp3, DAG);
         if (Tmp1.getNode()) {
-          Tmp3 = LegalizeOp(Tmp1);
-          Tmp4 = LegalizeOp(Tmp1.getValue(1));
+          Tmp3 = Tmp1;
+          Tmp4 = Tmp1.getValue(1);
         }
         break;
       case TargetLowering::Promote: {
@@ -1173,16 +926,16 @@
         Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
                            LD->isVolatile(), LD->isNonTemporal(),
                            LD->getAlignment());
-        Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
-        Tmp4 = LegalizeOp(Tmp1.getValue(1));
+        Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1);
+        Tmp4 = Tmp1.getValue(1);
         break;
       }
       }
       // Since loads produce two values, make sure to remember that we
       // legalized both of them.
-      AddLegalizedOperand(SDValue(Node, 0), Tmp3);
-      AddLegalizedOperand(SDValue(Node, 1), Tmp4);
-      return Op.getResNo() ? Tmp4 : Tmp3;
+      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3);
+      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4);
+      return;
     }
 
     EVT SrcVT = LD->getMemoryVT();
@@ -1213,9 +966,10 @@
       ISD::LoadExtType NewExtType =
         ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
 
-      Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
-                              Tmp1, Tmp2, LD->getPointerInfo(),
-                              NVT, isVolatile, isNonTemporal, Alignment);
+      SDValue Result =
+        DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
+                       Tmp1, Tmp2, LD->getPointerInfo(),
+                       NVT, isVolatile, isNonTemporal, Alignment);
 
       Ch = Result.getValue(1); // The chain.
 
@@ -1230,8 +984,8 @@
                              Result.getValueType(), Result,
                              DAG.getValueType(SrcVT));
 
-      Tmp1 = LegalizeOp(Result);
-      Tmp2 = LegalizeOp(Ch);
+      Tmp1 = Result;
+      Tmp2 = Ch;
     } else if (SrcWidth & (SrcWidth - 1)) {
       // If not loading a power-of-2 number of bits, expand as two loads.
       assert(!SrcVT.isVector() && "Unsupported extload!");
@@ -1274,7 +1028,7 @@
                                       TLI.getShiftAmountTy(Hi.getValueType())));
 
         // Join the hi and lo parts.
-        Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
+        Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
       } else {
         // Big endian - avoid unaligned loads.
         // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD at +2:i8
@@ -1304,11 +1058,10 @@
                                       TLI.getShiftAmountTy(Hi.getValueType())));
 
         // Join the hi and lo parts.
-        Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
+        Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
       }
 
-      Tmp1 = LegalizeOp(Result);
-      Tmp2 = LegalizeOp(Ch);
+      Tmp2 = Ch;
     } else {
       switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
       default: assert(0 && "This action is not supported yet!");
@@ -1316,17 +1069,16 @@
         isCustom = true;
         // FALLTHROUGH
       case TargetLowering::Legal:
-        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                                Tmp1, Tmp2, LD->getOffset()),
-                         Result.getResNo());
-        Tmp1 = Result.getValue(0);
-        Tmp2 = Result.getValue(1);
+        Node = DAG.UpdateNodeOperands(Node,
+                                      Tmp1, Tmp2, LD->getOffset());
+        Tmp1 = SDValue(Node, 0);
+        Tmp2 = SDValue(Node, 1);
 
         if (isCustom) {
-          Tmp3 = TLI.LowerOperation(Result, DAG);
+          Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG);
           if (Tmp3.getNode()) {
-            Tmp1 = LegalizeOp(Tmp3);
-            Tmp2 = LegalizeOp(Tmp3.getValue(1));
+            Tmp1 = Tmp3;
+            Tmp2 = Tmp3.getValue(1);
           }
         } else {
           // If this is an unaligned load and the target doesn't support it,
@@ -1337,12 +1089,8 @@
             unsigned ABIAlignment =
               TLI.getTargetData()->getABITypeAlignment(Ty);
             if (LD->getAlignment() < ABIAlignment){
-              Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
-                                           DAG, TLI);
-              Tmp1 = Result.getOperand(0);
-              Tmp2 = Result.getOperand(1);
-              Tmp1 = LegalizeOp(Tmp1);
-              Tmp2 = LegalizeOp(Tmp2);
+              ExpandUnalignedLoad(cast<LoadSDNode>(Node),
+                                  DAG, TLI, Tmp1, Tmp2);
             }
           }
         }
@@ -1363,9 +1111,8 @@
           case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
           default: llvm_unreachable("Unexpected extend load type!");
           }
-          Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
-          Tmp1 = LegalizeOp(Result);  // Relegalize new nodes.
-          Tmp2 = LegalizeOp(Load.getValue(1));
+          Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
+          Tmp2 = Load.getValue(1);
           break;
         }
 
@@ -1380,10 +1127,10 @@
                "EXTLOAD should always be supported!");
         // Turn the unsupported load into an EXTLOAD followed by an explicit
         // zero/sign extend inreg.
-        Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
-                                Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
-                                LD->isVolatile(), LD->isNonTemporal(),
-                                LD->getAlignment());
+        SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
+                                        Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
+                                        LD->isVolatile(), LD->isNonTemporal(),
+                                        LD->getAlignment());
         SDValue ValRes;
         if (ExtType == ISD::SEXTLOAD)
           ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
@@ -1391,38 +1138,37 @@
                                Result, DAG.getValueType(SrcVT));
         else
           ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
-        Tmp1 = LegalizeOp(ValRes);  // Relegalize new nodes.
-        Tmp2 = LegalizeOp(Result.getValue(1));  // Relegalize new nodes.
+        Tmp1 = ValRes;
+        Tmp2 = Result.getValue(1);
         break;
       }
     }
 
     // Since loads produce two values, make sure to remember that we legalized
     // both of them.
-    AddLegalizedOperand(SDValue(Node, 0), Tmp1);
-    AddLegalizedOperand(SDValue(Node, 1), Tmp2);
-    return Op.getResNo() ? Tmp2 : Tmp1;
+    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1);
+    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2);
+    break;
   }
   case ISD::STORE: {
     StoreSDNode *ST = cast<StoreSDNode>(Node);
-    Tmp1 = LegalizeOp(ST->getChain());    // Legalize the chain.
-    Tmp2 = LegalizeOp(ST->getBasePtr());  // Legalize the pointer.
+    Tmp1 = ST->getChain();
+    Tmp2 = ST->getBasePtr();
     unsigned Alignment = ST->getAlignment();
     bool isVolatile = ST->isVolatile();
     bool isNonTemporal = ST->isNonTemporal();
 
     if (!ST->isTruncatingStore()) {
       if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
-        Result = SDValue(OptStore, 0);
+        DAG.ReplaceAllUsesWith(ST, OptStore, this);
         break;
       }
 
       {
-        Tmp3 = LegalizeOp(ST->getValue());
-        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                                Tmp1, Tmp3, Tmp2,
-                                                ST->getOffset()),
-                         Result.getResNo());
+        Tmp3 = ST->getValue();
+        Node = DAG.UpdateNodeOperands(Node,
+                                      Tmp1, Tmp3, Tmp2,
+                                      ST->getOffset());
 
         EVT VT = Tmp3.getValueType();
         switch (TLI.getOperationAction(ISD::STORE, VT)) {
@@ -1434,27 +1180,31 @@
             Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
             unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
             if (ST->getAlignment() < ABIAlignment)
-              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
-                                            DAG, TLI);
+              ExpandUnalignedStore(cast<StoreSDNode>(Node),
+                                   DAG, TLI, this);
           }
           break;
         case TargetLowering::Custom:
-          Tmp1 = TLI.LowerOperation(Result, DAG);
-          if (Tmp1.getNode()) Result = Tmp1;
+          Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
+          if (Tmp1.getNode())
+            DAG.ReplaceAllUsesWith(SDValue(Node, 0), Tmp1, this);
           break;
-        case TargetLowering::Promote:
+        case TargetLowering::Promote: {
           assert(VT.isVector() && "Unknown legal promote case!");
           Tmp3 = DAG.getNode(ISD::BITCAST, dl,
                              TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
-          Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
-                                ST->getPointerInfo(), isVolatile,
-                                isNonTemporal, Alignment);
+          SDValue Result =
+            DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
+                         ST->getPointerInfo(), isVolatile,
+                         isNonTemporal, Alignment);
+          DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
           break;
         }
+        }
         break;
       }
     } else {
-      Tmp3 = LegalizeOp(ST->getValue());
+      Tmp3 = ST->getValue();
 
       EVT StVT = ST->getMemoryVT();
       unsigned StWidth = StVT.getSizeInBits();
@@ -1466,8 +1216,10 @@
         EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
                                     StVT.getStoreSizeInBits());
         Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
-        Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
-                                   NVT, isVolatile, isNonTemporal, Alignment);
+        SDValue Result =
+          DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                            NVT, isVolatile, isNonTemporal, Alignment);
+        DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
       } else if (StWidth & (StWidth - 1)) {
         // If not storing a power-of-2 number of bits, expand as two stores.
         assert(!StVT.isVector() && "Unsupported truncstore!");
@@ -1521,14 +1273,13 @@
         }
 
         // The order of the stores doesn't matter.
-        Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+        SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+        DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
       } else {
         if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
             Tmp2 != ST->getBasePtr())
-          Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                                  Tmp1, Tmp3, Tmp2,
-                                                  ST->getOffset()),
-                           Result.getResNo());
+          Node = DAG.UpdateNodeOperands(Node, Tmp1, Tmp3, Tmp2,
+                                        ST->getOffset());
 
         switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
         default: assert(0 && "This action is not supported yet!");
@@ -1539,12 +1290,13 @@
             Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
             unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
             if (ST->getAlignment() < ABIAlignment)
-              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
-                                            DAG, TLI);
+              ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
           }
           break;
         case TargetLowering::Custom:
-          Result = TLI.LowerOperation(Result, DAG);
+          DAG.ReplaceAllUsesWith(SDValue(Node, 0),
+                                 TLI.LowerOperation(SDValue(Node, 0), DAG),
+                                 this);
           break;
         case TargetLowering::Expand:
           assert(!StVT.isVector() &&
@@ -1553,8 +1305,10 @@
           // TRUNCSTORE:i16 i32 -> STORE i16
           assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
           Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
-          Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
-                                isVolatile, isNonTemporal, Alignment);
+          SDValue Result =
+            DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                         isVolatile, isNonTemporal, Alignment);
+          DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
           break;
         }
       }
@@ -1562,17 +1316,6 @@
     break;
   }
   }
-  assert(Result.getValueType() == Op.getValueType() &&
-         "Bad legalization!");
-
-  // Make sure that the generated code is itself legal.
-  if (Result != Op)
-    Result = LegalizeOp(Result);
-
-  // Note that LegalizeOp may be reentered even from single-use nodes, which
-  // means that we always must cache transformed nodes.
-  AddLegalizedOperand(Op, Result);
-  return Result;
 }
 
 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
@@ -2011,7 +1754,6 @@
 // and leave the Hi part unset.
 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
                                             bool isSigned) {
-  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
   // The input chain to this libcall is the entry node of the function.
   // Legalizing the call will automatically add the previous call to the
   // dependence.
@@ -2030,7 +1772,6 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
-  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
 
   // isTailCall may be true since the callee does not reference caller stack
@@ -2046,10 +1787,6 @@
     // It's a tailcall, return the chain (which is the DAG root).
     return DAG.getRoot();
 
-  // Legalize the call sequence, starting with the chain.  This will advance
-  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
-  // was added by LowerCallTo (guaranteeing proper serialization of calls).
-  LegalizeOp(CallInfo.second);
   return CallInfo.first;
 }
 
@@ -2079,11 +1816,6 @@
                   /*isReturnValueUsed=*/true,
                   Callee, Args, DAG, dl);
 
-  // Legalize the call sequence, starting with the chain.  This will advance
-  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
-  // was added by LowerCallTo (guaranteeing proper serialization of calls).
-  LegalizeOp(CallInfo.second);
-
   return CallInfo.first;
 }
 
@@ -2093,7 +1825,6 @@
 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
                                          SDNode *Node,
                                          bool isSigned) {
-  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
   SDValue InChain = Node->getOperand(0);
 
   TargetLowering::ArgListTy Args;
@@ -2110,7 +1841,6 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
-  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
@@ -2118,10 +1848,6 @@
                     /*isReturnValueUsed=*/true,
                     Callee, Args, DAG, Node->getDebugLoc());
 
-  // Legalize the call sequence, starting with the chain.  This will advance
-  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
-  // was added by LowerCallTo (guaranteeing proper serialization of calls).
-  LegalizeOp(CallInfo.second);
   return CallInfo;
 }
 
@@ -2247,20 +1973,14 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
-  // Splice the libcall in wherever FindInputOutputChains tells us to.
   DebugLoc dl = Node->getDebugLoc();
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
                     0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
                     /*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
 
-  // Legalize the call sequence, starting with the chain.  This will advance
-  // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
-  // was added by LowerCallTo (guaranteeing proper serialization of calls).
-  LegalizeOp(CallInfo.second);
-
   // Remainder is loaded back from the stack frame.
-  SDValue Rem = DAG.getLoad(RetVT, dl, LastCALLSEQ_END, FIPtr,
+  SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
                             MachinePointerInfo(), false, false, 0);
   Results.push_back(CallInfo.first);
   Results.push_back(Rem);
@@ -2452,11 +2172,13 @@
                              MachinePointerInfo::getConstantPool(),
                              false, false, Alignment);
   else {
-    FudgeInReg =
-      LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
-                                DAG.getEntryNode(), CPIdx,
-                                MachinePointerInfo::getConstantPool(),
-                                MVT::f32, false, false, Alignment));
+    SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
+                                  DAG.getEntryNode(), CPIdx,
+                                  MachinePointerInfo::getConstantPool(),
+                                  MVT::f32, false, false, Alignment);
+    HandleSDNode Handle(Load);
+    LegalizeOp(Load.getNode());
+    FudgeInReg = Handle.getValue();
   }
 
   return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
@@ -2780,8 +2502,8 @@
   return ExpandChainLibCall(LC, Node, false);
 }
 
-void SelectionDAGLegalize::ExpandNode(SDNode *Node,
-                                      SmallVectorImpl<SDValue> &Results) {
+void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
+  SmallVector<SDValue, 8> Results;
   DebugLoc dl = Node->getDebugLoc();
   SDValue Tmp1, Tmp2, Tmp3, Tmp4;
   switch (Node->getOpcode()) {
@@ -3229,10 +2951,8 @@
     ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
     // Check to see if this FP immediate is already legal.
     // If this is a legal constant, turn it into a TargetConstantFP node.
-    if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
-      Results.push_back(SDValue(Node, 0));
-    else
-      Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
+    if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
+      Results.push_back(ExpandConstantFP(CFP, true));
     break;
   }
   case ISD::EHSELECTION: {
@@ -3478,6 +3198,10 @@
                                DAG.getIntPtrConstant(0));
       TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
                             DAG.getIntPtrConstant(1));
+      // Ret is a node with an illegal type. Because such things are not
+      // generally permitted during this phase of legalization, delete the
+      // node. The above EXTRACT_ELEMENT nodes should have been folded.
+      DAG.DeleteNode(Ret.getNode());
     }
 
     if (isSigned) {
@@ -3618,7 +3342,6 @@
 
     LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
                           Tmp2, Tmp3, Tmp4, dl);
-    LastCALLSEQ_END = DAG.getEntryNode();
 
     assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
     Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
@@ -3628,6 +3351,35 @@
     Results.push_back(Tmp1);
     break;
   }
+  case ISD::BUILD_VECTOR:
+    Results.push_back(ExpandBUILD_VECTOR(Node));
+    break;
+  case ISD::SRA:
+  case ISD::SRL:
+  case ISD::SHL: {
+    // Scalarize vector SRA/SRL/SHL.
+    EVT VT = Node->getValueType(0);
+    assert(VT.isVector() && "Unable to legalize non-vector shift");
+    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
+    unsigned NumElem = VT.getVectorNumElements();
+
+    SmallVector<SDValue, 8> Scalars;
+    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
+      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+                               VT.getScalarType(),
+                               Node->getOperand(0), DAG.getIntPtrConstant(Idx));
+      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+                               VT.getScalarType(),
+                               Node->getOperand(1), DAG.getIntPtrConstant(Idx));
+      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
+                                    VT.getScalarType(), Ex, Sh));
+    }
+    SDValue Result =
+      DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
+                  &Scalars[0], Scalars.size());
+    DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
+    break;
+  }
   case ISD::GLOBAL_OFFSET_TABLE:
   case ISD::GlobalAddress:
   case ISD::GlobalTLSAddress:
@@ -3638,13 +3390,16 @@
   case ISD::INTRINSIC_WO_CHAIN:
   case ISD::INTRINSIC_VOID:
     // FIXME: Custom lowering for these operations shouldn't return null!
-    for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
-      Results.push_back(SDValue(Node, i));
     break;
   }
+
+  // Replace the original node with the legalized result.
+  if (!Results.empty())
+    DAG.ReplaceAllUsesWith(Node, Results.data(), this);
 }
-void SelectionDAGLegalize::PromoteNode(SDNode *Node,
-                                       SmallVectorImpl<SDValue> &Results) {
+
+void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
+  SmallVector<SDValue, 8> Results;
   EVT OVT = Node->getValueType(0);
   if (Node->getOpcode() == ISD::UINT_TO_FP ||
       Node->getOpcode() == ISD::SINT_TO_FP ||
@@ -3772,6 +3527,10 @@
     break;
   }
   }
+
+  // Replace the original node with the legalized result.
+  if (!Results.empty())
+    DAG.ReplaceAllUsesWith(Node, Results.data(), this);
 }
 
 // SelectionDAG::Legalize - This is the entry point for the file.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Thu Oct 27 20:29:32 2011
@@ -1084,7 +1084,6 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
-  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Oct 27 20:29:32 2011
@@ -386,6 +386,90 @@
   }
 }
 
+/// IsChainDependent - Test if Outer is reachable from Inner through
+/// chain dependencies.
+static bool IsChainDependent(SDNode *Outer, SDNode *Inner) {
+  SDNode *N = Outer;
+  for (;;) {
+    if (N == Inner)
+      return true;
+    if (N->getOpcode() == ISD::TokenFactor) {
+      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+        if (IsChainDependent(N->getOperand(i).getNode(), Inner))
+          return true;
+      return false;
+    }
+    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+      if (N->getOperand(i).getValueType() == MVT::Other) {
+        N = N->getOperand(i).getNode();
+        goto found_chain_operand;
+      }
+    return false;
+  found_chain_operand:;
+    if (N->getOpcode() == ISD::EntryToken)
+      return false;
+  }
+}
+
+/// FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate
+/// the corresponding (lowered) CALLSEQ_BEGIN node.
+///
+/// NestLevel and MaxNested are used in recursion to indcate the current level
+/// of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum
+/// level seen so far.
+///
+/// TODO: It would be better to give CALLSEQ_END an explicit operand to point
+/// to the corresponding CALLSEQ_BEGIN to avoid needing to search for it.
+static SDNode *
+FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest,
+                 const TargetInstrInfo *TII) {
+  for (;;) {
+    // For a TokenFactor, examine each operand. There may be multiple ways
+    // to get to the CALLSEQ_BEGIN, but we need to find the path with the
+    // most nesting in order to ensure that we find the corresponding match.
+    if (N->getOpcode() == ISD::TokenFactor) {
+      SDNode *Best = 0;
+      unsigned BestMaxNest = MaxNest;
+      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
+        unsigned MyNestLevel = NestLevel;
+        unsigned MyMaxNest = MaxNest;
+        if (SDNode *New = FindCallSeqStart(N->getOperand(i).getNode(),
+                                           MyNestLevel, MyMaxNest, TII))
+          if (!Best || (MyMaxNest > BestMaxNest)) {
+            Best = New;
+            BestMaxNest = MyMaxNest;
+          }
+      }
+      assert(Best);
+      MaxNest = BestMaxNest;
+      return Best;
+    }
+    // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
+    if (N->isMachineOpcode()) {
+      if (N->getMachineOpcode() ==
+          (unsigned)TII->getCallFrameDestroyOpcode()) {
+        ++NestLevel;
+        MaxNest = std::max(MaxNest, NestLevel);
+      } else if (N->getMachineOpcode() ==
+                 (unsigned)TII->getCallFrameSetupOpcode()) {
+        --NestLevel;
+        if (NestLevel == 0)
+          return N;
+      }
+    }
+    // Otherwise, find the chain and continue climbing.
+    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+      if (N->getOperand(i).getValueType() == MVT::Other) {
+        N = N->getOperand(i).getNode();
+        goto found_chain_operand;
+      }
+    return 0;
+  found_chain_operand:;
+    if (N->getOpcode() == ISD::EntryToken)
+      return 0;
+  }
+}
+
 /// Call ReleasePred for each predecessor, then update register live def/gen.
 /// Always update LiveRegDefs for a register dependence even if the current SU
 /// also defines the register. This effectively create one large live range
@@ -423,6 +507,26 @@
       }
     }
   }
+
+  // If we're scheduling a lowered CALLSEQ_END, find the corresponding CALLSEQ_BEGIN.
+  // Inject an artificial physical register dependence between these nodes, to
+  // prevent other calls from being interscheduled with them.
+  const TargetLowering *TLI = TM.getTargetLowering();
+  unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
+  if (!LiveRegDefs[SP])
+    for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode())
+      if (Node->isMachineOpcode() &&
+          Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
+        unsigned NestLevel = 0;
+        unsigned MaxNest = 0;
+        SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
+
+        SUnit *Def = &SUnits[N->getNodeId()];
+        ++NumLiveRegs;
+        LiveRegDefs[SP] = Def;
+        LiveRegGens[SP] = SU;
+        break;
+      }
 }
 
 /// Check to see if any of the pending instructions are ready to issue.  If
@@ -605,6 +709,22 @@
       LiveRegGens[I->getReg()] = NULL;
     }
   }
+  // Release the special call resource dependence, if this is the beginning
+  // of a call.
+  const TargetLowering *TLI = TM.getTargetLowering();
+  unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
+  if (LiveRegDefs[SP] == SU)
+  for (const SDNode *SUNode = SU->getNode(); SUNode;
+       SUNode = SUNode->getGluedNode()) {
+    if (SUNode->isMachineOpcode() &&
+        SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode() &&
+        LiveRegDefs[SP] == SU) {
+      assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
+      --NumLiveRegs;
+      LiveRegDefs[SP] = NULL;
+      LiveRegGens[SP] = NULL;
+    }
+  }
 
   resetVRegCycle(SU);
 
@@ -1083,6 +1203,20 @@
 
     if (!Node->isMachineOpcode())
       continue;
+    // If we're in the middle of scheduling a call, don't begin scheduling
+    // another call.
+    if (Node->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode() ||
+        Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
+      for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
+        if (LiveRegDefs[i]) {
+          SDNode *Gen = LiveRegGens[i]->getNode();
+          while (SDNode *Glued = Gen->getGluedNode())
+            Gen = Glued;
+          if (!IsChainDependent(Gen, Node) && RegAdded.insert(i))
+            LRegs.push_back(i);
+        }
+      continue;
+    }
     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
     if (!MCID.ImplicitDefs)
       continue;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Oct 27 20:29:32 2011
@@ -5290,6 +5290,10 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
+
+  // If we just RAUW'd the root, take note.
+  if (FromN == getRoot())
+    setRoot(To);
 }
 
 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
@@ -5335,6 +5339,10 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
+
+  // If we just RAUW'd the root, take note.
+  if (From == getRoot().getNode())
+    setRoot(SDValue(To, getRoot().getResNo()));
 }
 
 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
@@ -5373,6 +5381,10 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
+
+  // If we just RAUW'd the root, take note.
+  if (From == getRoot().getNode())
+    setRoot(SDValue(To[getRoot().getResNo()]));
 }
 
 /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
@@ -5431,6 +5443,10 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
+
+  // If we just RAUW'd the root, take note.
+  if (From == getRoot())
+    setRoot(To);
 }
 
 namespace {

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Oct 27 20:29:32 2011
@@ -1353,12 +1353,10 @@
       SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
       SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
                                          MVT::i32);
-      // TODO: Disable AlwaysInline when it becomes possible
-      //       to emit a nested call sequence.
       MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
                                           Flags.getByValAlign(),
                                           /*isVolatile=*/false,
-                                          /*AlwaysInline=*/true,
+                                          /*AlwaysInline=*/false,
                                           MachinePointerInfo(0),
                                           MachinePointerInfo(0)));
 
@@ -4350,9 +4348,24 @@
       // If this is undef splat, generate it via "just" vdup, if possible.
       if (Lane == -1) Lane = 0;
 
+      // Test if V1 is a SCALAR_TO_VECTOR.
       if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
         return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
       }
+      // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
+      // (and probably will turn into a SCALAR_TO_VECTOR once legalization
+      // reaches it).
+      if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
+          !isa<ConstantSDNode>(V1.getOperand(0))) {
+        bool IsScalarToVector = true;
+        for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
+          if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
+            IsScalarToVector = false;
+            break;
+          }
+        if (IsScalarToVector)
+          return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
+      }
       return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
                          DAG.getConstant(Lane, MVT::i32));
     }

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Oct 27 20:29:32 2011
@@ -2114,7 +2114,9 @@
         HasNoSignedComparisonUses(Node))
       // Look past the truncate if CMP is the only use of it.
       N0 = N0.getOperand(0);
-    if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
+    if ((N0.getNode()->getOpcode() == ISD::AND ||
+         (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
+        N0.getNode()->hasOneUse() &&
         N0.getValueType() != MVT::i8 &&
         X86::isZeroNode(N1)) {
       ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Oct 27 20:29:32 2011
@@ -4220,6 +4220,29 @@
   return true;
 }
 
+// Test whether the given value is a vector value which will be legalized
+// into a load.
+static bool WillBeConstantPoolLoad(SDNode *N) {
+  if (N->getOpcode() != ISD::BUILD_VECTOR)
+    return false;
+
+  // Check for any non-constant elements.
+  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+    switch (N->getOperand(i).getNode()->getOpcode()) {
+    case ISD::UNDEF:
+    case ISD::ConstantFP:
+    case ISD::Constant:
+      break;
+    default:
+      return false;
+    }
+
+  // Vectors of all-zeros and all-ones are materialized with special
+  // instructions rather than being loaded.
+  return !ISD::isBuildVectorAllZeros(N) &&
+         !ISD::isBuildVectorAllOnes(N);
+}
+
 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
 /// match movlp{s|d}. The lower half elements should come from lower half of
 /// V1 (and in order), and the upper half elements should come from the upper
@@ -4235,7 +4258,7 @@
     return false;
   // Is V2 is a vector load, don't do this transformation. We will try to use
   // load folding shufps op.
-  if (ISD::isNON_EXTLoad(V2))
+  if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
     return false;
 
   unsigned NumElems = VT.getVectorNumElements();
@@ -6351,6 +6374,8 @@
   if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
     CanFoldLoad = true;
 
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
+
   // Both of them can't be memory operations though.
   if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
     CanFoldLoad = false;
@@ -6360,10 +6385,11 @@
       return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
 
     if (NumElems == 4)
-      return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
+      // If we don't care about the second element, procede to use movss.
+      if (SVOp->getMaskElt(1) != -1)
+        return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
   }
 
-  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
   // movl and movlp will both match v2i64, but v2i64 is never matched by
   // movl earlier because we make it strict to avoid messing with the movlp load
   // folding logic (see the code above getMOVLP call). Match it here then,
@@ -8681,8 +8707,9 @@
 
   // If condition flag is set by a X86ISD::CMP, then use it as the condition
   // setting operand in place of the X86ISD::SETCC.
-  if (Cond.getOpcode() == X86ISD::SETCC ||
-      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
+  unsigned CondOpcode = Cond.getOpcode();
+  if (CondOpcode == X86ISD::SETCC ||
+      CondOpcode == X86ISD::SETCC_CARRY) {
     CC = Cond.getOperand(0);
 
     SDValue Cmp = Cond.getOperand(1);
@@ -8699,6 +8726,39 @@
       Cond = Cmp;
       addTest = false;
     }
+  } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
+             CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
+             ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
+              Cond.getOperand(0).getValueType() != MVT::i8)) {
+    SDValue LHS = Cond.getOperand(0);
+    SDValue RHS = Cond.getOperand(1);
+    unsigned X86Opcode;
+    unsigned X86Cond;
+    SDVTList VTs;
+    switch (CondOpcode) {
+    case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
+    case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
+    case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
+    case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
+    case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
+    case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
+    default: llvm_unreachable("unexpected overflowing operator");
+    }
+    if (CondOpcode == ISD::UMULO)
+      VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
+                          MVT::i32);
+    else
+      VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
+
+    SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
+
+    if (CondOpcode == ISD::UMULO)
+      Cond = X86Op.getValue(2);
+    else
+      Cond = X86Op.getValue(1);
+
+    CC = DAG.getConstant(X86Cond, MVT::i8);
+    addTest = false;
   }
 
   if (addTest) {
@@ -8780,11 +8840,27 @@
   SDValue Dest  = Op.getOperand(2);
   DebugLoc dl = Op.getDebugLoc();
   SDValue CC;
+  bool Inverted = false;
 
   if (Cond.getOpcode() == ISD::SETCC) {
-    SDValue NewCond = LowerSETCC(Cond, DAG);
-    if (NewCond.getNode())
-      Cond = NewCond;
+    // Check for setcc([su]{add,sub,mul}o == 0).
+    if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
+        isa<ConstantSDNode>(Cond.getOperand(1)) &&
+        cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
+        Cond.getOperand(0).getResNo() == 1 &&
+        (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
+         Cond.getOperand(0).getOpcode() == ISD::UADDO ||
+         Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
+         Cond.getOperand(0).getOpcode() == ISD::USUBO ||
+         Cond.getOperand(0).getOpcode() == ISD::SMULO ||
+         Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
+      Inverted = true;
+      Cond = Cond.getOperand(0);
+    } else {
+      SDValue NewCond = LowerSETCC(Cond, DAG);
+      if (NewCond.getNode())
+        Cond = NewCond;
+    }
   }
 #if 0
   // FIXME: LowerXALUO doesn't handle these!!
@@ -8805,8 +8881,9 @@
 
   // If condition flag is set by a X86ISD::CMP, then use it as the condition
   // setting operand in place of the X86ISD::SETCC.
-  if (Cond.getOpcode() == X86ISD::SETCC ||
-      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
+  unsigned CondOpcode = Cond.getOpcode();
+  if (CondOpcode == X86ISD::SETCC ||
+      CondOpcode == X86ISD::SETCC_CARRY) {
     CC = Cond.getOperand(0);
 
     SDValue Cmp = Cond.getOperand(1);
@@ -8827,6 +8904,43 @@
         break;
       }
     }
+  }
+  CondOpcode = Cond.getOpcode();
+  if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
+      CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
+      ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
+       Cond.getOperand(0).getValueType() != MVT::i8)) {
+    SDValue LHS = Cond.getOperand(0);
+    SDValue RHS = Cond.getOperand(1);
+    unsigned X86Opcode;
+    unsigned X86Cond;
+    SDVTList VTs;
+    switch (CondOpcode) {
+    case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
+    case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
+    case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
+    case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
+    case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
+    case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
+    default: llvm_unreachable("unexpected overflowing operator");
+    }
+    if (Inverted)
+      X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
+    if (CondOpcode == ISD::UMULO)
+      VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
+                          MVT::i32);
+    else
+      VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
+
+    SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
+
+    if (CondOpcode == ISD::UMULO)
+      Cond = X86Op.getValue(2);
+    else
+      Cond = X86Op.getValue(1);
+
+    CC = DAG.getConstant(X86Cond, MVT::i8);
+    addTest = false;
   } else {
     unsigned CondOpc;
     if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
@@ -8890,6 +9004,66 @@
       CC = DAG.getConstant(CCode, MVT::i8);
       Cond = Cond.getOperand(0).getOperand(1);
       addTest = false;
+    } else if (Cond.getOpcode() == ISD::SETCC &&
+               cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
+      // For FCMP_OEQ, we can emit
+      // two branches instead of an explicit AND instruction with a
+      // separate test. However, we only do this if this block doesn't
+      // have a fall-through edge, because this requires an explicit
+      // jmp when the condition is false.
+      if (Op.getNode()->hasOneUse()) {
+        SDNode *User = *Op.getNode()->use_begin();
+        // Look for an unconditional branch following this conditional branch.
+        // We need this because we need to reverse the successors in order
+        // to implement FCMP_OEQ.
+        if (User->getOpcode() == ISD::BR) {
+          SDValue FalseBB = User->getOperand(1);
+          SDNode *NewBR =
+            DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
+          assert(NewBR == User);
+          (void)NewBR;
+          Dest = FalseBB;
+
+          SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
+                                    Cond.getOperand(0), Cond.getOperand(1));
+          CC = DAG.getConstant(X86::COND_NE, MVT::i8);
+          Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
+                              Chain, Dest, CC, Cmp);
+          CC = DAG.getConstant(X86::COND_P, MVT::i8);
+          Cond = Cmp;
+          addTest = false;
+        }
+      }
+    } else if (Cond.getOpcode() == ISD::SETCC &&
+               cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
+      // For FCMP_UNE, we can emit
+      // two branches instead of an explicit AND instruction with a
+      // separate test. However, we only do this if this block doesn't
+      // have a fall-through edge, because this requires an explicit
+      // jmp when the condition is false.
+      if (Op.getNode()->hasOneUse()) {
+        SDNode *User = *Op.getNode()->use_begin();
+        // Look for an unconditional branch following this conditional branch.
+        // We need this because we need to reverse the successors in order
+        // to implement FCMP_UNE.
+        if (User->getOpcode() == ISD::BR) {
+          SDValue FalseBB = User->getOperand(1);
+          SDNode *NewBR =
+            DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
+          assert(NewBR == User);
+          (void)NewBR;
+
+          SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
+                                    Cond.getOperand(0), Cond.getOperand(1));
+          CC = DAG.getConstant(X86::COND_NE, MVT::i8);
+          Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
+                              Chain, Dest, CC, Cmp);
+          CC = DAG.getConstant(X86::COND_NP, MVT::i8);
+          Cond = Cmp;
+          addTest = false;
+          Dest = FalseBB;
+        }
+      }
     }
   }
 

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Thu Oct 27 20:29:32 2011
@@ -386,6 +386,15 @@
     Offset = off;
     return true;
   }
+  // Check for an aligned global variable.
+  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(*Root)) {
+    const GlobalValue *GV = GA->getGlobal();
+    if (GA->getOffset() == 0 && GV->getAlignment() >= 4) {
+      AlignedBase = Base;
+      Offset = off;
+      return true;
+    }
+  }
   return false;
 }
 

Modified: llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/and_ops.ll?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/and_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/and_ops.ll Thu Oct 27 20:29:32 2011
@@ -5,6 +5,9 @@
 ; RUN: grep andhi  %t1.s | count 30
 ; RUN: grep andbi  %t1.s | count 4
 
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll Thu Oct 27 20:29:32 2011
@@ -15,6 +15,9 @@
 ; RUN: grep ai      %t2.s | count 9
 ; RUN: grep dispatch_tab %t2.s | count 6
 
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 ; ModuleID = 'call_indirect.bc'
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
 target triple = "spu-unknown-elf"

Modified: llvm/trunk/test/CodeGen/CellSPU/nand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/nand.ll?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/nand.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/nand.ll Thu Oct 27 20:29:32 2011
@@ -3,6 +3,10 @@
 ; RUN: grep and    %t1.s | count 94
 ; RUN: grep xsbh   %t1.s | count 2
 ; RUN: grep xshw   %t1.s | count 4
+
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/or_ops.ll?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/or_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/or_ops.ll Thu Oct 27 20:29:32 2011
@@ -6,6 +6,9 @@
 ; RUN: grep orbi   %t1.s | count 15
 ; RUN: FileCheck %s < %t1.s
 
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/select_bits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/select_bits.ll?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/select_bits.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/select_bits.ll Thu Oct 27 20:29:32 2011
@@ -1,6 +1,9 @@
 ; RUN: llc < %s -march=cellspu > %t1.s
 ; RUN: grep selb   %t1.s | count 56
 
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/struct_1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/struct_1.ll?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/struct_1.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/struct_1.ll Thu Oct 27 20:29:32 2011
@@ -22,6 +22,9 @@
 ; RUN: grep shufb   %t2.s | count 7
 ; RUN: grep stqd    %t2.s | count 7
 
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 ; ModuleID = 'struct_1.bc'
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"

Modified: llvm/trunk/test/CodeGen/Mips/cprestore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cprestore.ll?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cprestore.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cprestore.ll Thu Oct 27 20:29:32 2011
@@ -1,8 +1,4 @@
-; DISABLED: llc -march=mipsel < %s | FileCheck %s
-; RUN: false
-
-; byval is currently unsupported.
-; XFAIL: *
+; RUN: llc -march=mipsel < %s | FileCheck %s
 
 ; CHECK: .set macro
 ; CHECK-NEXT: .cprestore

Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Thu Oct 27 20:29:32 2011
@@ -1,8 +1,4 @@
-; DISABLED: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
-; RUN: false
-
-; byval is currently unsupported.
-; XFAIL: *
+; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
 
 %struct.S1 = type { [65536 x i8] }
 

Modified: llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll Thu Oct 27 20:29:32 2011
@@ -1,11 +1,7 @@
-; DISABLED: llc -mtriple=thumbv6-apple-darwin < %s
-; RUN: false
+; RUN: llc -mtriple=thumbv6-apple-darwin < %s
 ; rdar://problem/9416774
 ; ModuleID = 'reduced.ll'
 
-; byval is currently unsupported.
-; XFAIL: *
-
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
 target triple = "thumbv7-apple-ios"
 

Removed: llvm/trunk/test/CodeGen/X86/2009-02-05-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-05-CoalescerBug.ll?rev=143176&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-02-05-CoalescerBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-02-05-CoalescerBug.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 -o %t
-; RUN: grep movss %t | count 2
-; RUN: grep movaps %t | count 2
-; RUN: grep movdqa %t | count 2
-
-define i1 @t([2 x float]* %y, [2 x float]* %w, i32, [2 x float]* %x.pn59, i32 %smax190, i32 %j.1180, <4 x float> %wu.2179, <4 x float> %wr.2178, <4 x float>* %tmp89.out, <4 x float>* %tmp107.out, i32* %indvar.next218.out) nounwind {
-newFuncRoot:
-	%tmp82 = insertelement <4 x float> %wr.2178, float 0.000000e+00, i32 0		; <<4 x float>> [#uses=1]
-	%tmp85 = insertelement <4 x float> %tmp82, float 0.000000e+00, i32 1		; <<4 x float>> [#uses=1]
-	%tmp87 = insertelement <4 x float> %tmp85, float 0.000000e+00, i32 2		; <<4 x float>> [#uses=1]
-	%tmp89 = insertelement <4 x float> %tmp87, float 0.000000e+00, i32 3		; <<4 x float>> [#uses=1]
-	store <4 x float> %tmp89, <4 x float>* %tmp89.out
-	ret i1 false
-}

Removed: llvm/trunk/test/CodeGen/X86/dbg-inline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-inline.ll?rev=143176&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-inline.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dbg-inline.ll (removed)
@@ -1,140 +0,0 @@
-; RUN: llc < %s | FileCheck %s
-; Radar 7881628, 9747970
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
-target triple = "x86_64-apple-macosx10.7.0"
-
-%class.APFloat = type { i32 }
-
-define i32 @_ZNK7APFloat9partCountEv(%class.APFloat* nocapture %this) nounwind uwtable readonly optsize ssp align 2 {
-entry:
-  tail call void @llvm.dbg.value(metadata !{%class.APFloat* %this}, i64 0, metadata !28), !dbg !41
-  %prec = getelementptr inbounds %class.APFloat* %this, i64 0, i32 0, !dbg !42
-  %tmp = load i32* %prec, align 4, !dbg !42, !tbaa !44
-  tail call void @llvm.dbg.value(metadata !{i32 %tmp}, i64 0, metadata !47), !dbg !48
-  %add.i = add i32 %tmp, 42, !dbg !49
-  ret i32 %add.i, !dbg !42
-}
-
-define zeroext i1 @_ZNK7APFloat14bitwiseIsEqualERKS_(%class.APFloat* %this, %class.APFloat* %rhs) uwtable optsize ssp align 2 {
-entry:
-  tail call void @llvm.dbg.value(metadata !{%class.APFloat* %this}, i64 0, metadata !29), !dbg !51
-  tail call void @llvm.dbg.value(metadata !{%class.APFloat* %rhs}, i64 0, metadata !30), !dbg !52
-  tail call void @llvm.dbg.value(metadata !{%class.APFloat* %this}, i64 0, metadata !53), !dbg !55
-  %prec.i = getelementptr inbounds %class.APFloat* %this, i64 0, i32 0, !dbg !56
-;CHECK: DW_TAG_inlined_subroutine
-;CHECK: DW_AT_abstract_origin
-;CHECK: DW_AT_ranges
-  %tmp.i = load i32* %prec.i, align 4, !dbg !56, !tbaa !44
-  tail call void @llvm.dbg.value(metadata !{i32 %tmp.i}, i64 0, metadata !57), !dbg !58
-  %add.i.i = add i32 %tmp.i, 42, !dbg !59
-  tail call void @llvm.dbg.value(metadata !{i32 %add.i.i}, i64 0, metadata !31), !dbg !54
-  %call2 = tail call i64* @_ZNK7APFloat16significandPartsEv(%class.APFloat* %this) optsize, !dbg !60
-  tail call void @llvm.dbg.value(metadata !{i64* %call2}, i64 0, metadata !34), !dbg !60
-  %call3 = tail call i64* @_ZNK7APFloat16significandPartsEv(%class.APFloat* %rhs) optsize, !dbg !61
-  tail call void @llvm.dbg.value(metadata !{i64* %call3}, i64 0, metadata !37), !dbg !61
-  %tmp = zext i32 %add.i.i to i64
-  br label %for.cond, !dbg !62
-
-for.cond:                                         ; preds = %for.inc, %entry
-  %indvar = phi i64 [ %indvar.next, %for.inc ], [ 0, %entry ]
-  %tmp13 = sub i64 %tmp, %indvar, !dbg !62
-  %i.0 = trunc i64 %tmp13 to i32, !dbg !62
-  %cmp = icmp sgt i32 %i.0, 0, !dbg !62
-  br i1 %cmp, label %for.body, label %return, !dbg !62
-
-for.body:                                         ; preds = %for.cond
-  %p.0 = getelementptr i64* %call2, i64 %indvar, !dbg !63
-  %tmp6 = load i64* %p.0, align 8, !dbg !63, !tbaa !66
-  %tmp8 = load i64* %call3, align 8, !dbg !63, !tbaa !66
-  %cmp9 = icmp eq i64 %tmp6, %tmp8, !dbg !63
-  br i1 %cmp9, label %for.inc, label %return, !dbg !63
-
-for.inc:                                          ; preds = %for.body
-  %indvar.next = add i64 %indvar, 1, !dbg !67
-  br label %for.cond, !dbg !67
-
-return:                                           ; preds = %for.cond, %for.body
-  %retval.0 = phi i1 [ false, %for.body ], [ true, %for.cond ]
-  ret i1 %retval.0, !dbg !68
-}
-
-declare i64* @_ZNK7APFloat16significandPartsEv(%class.APFloat*) optsize
-
-declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
-
-!llvm.dbg.cu = !{!0}
-!llvm.dbg.sp = !{!1, !7, !12, !23, !24, !25}
-!llvm.dbg.lv._ZNK7APFloat9partCountEv = !{!28}
-!llvm.dbg.lv._ZNK7APFloat14bitwiseIsEqualERKS_ = !{!29, !30, !31, !34, !37}
-!llvm.dbg.lv._ZL16partCountForBitsj = !{!38}
-!llvm.dbg.gv = !{!39}
-
-!0 = metadata !{i32 655377, i32 0, i32 4, metadata !"/Volumes/Athwagate/R9747970/apf.cc", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 136149)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 655406, i32 0, metadata !2, metadata !"bitwiseIsEqual", metadata !"bitwiseIsEqual", metadata !"_ZNK7APFloat14bitwiseIsEqualERKS_", metadata !3, i32 8, metadata !19, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 true, null, null} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 655362, metadata !0, metadata !"APFloat", metadata !3, i32 6, i64 32, i64 32, i32 0, i32 0, null, metadata !4, i32 0, null, null} ; [ DW_TAG_class_type ]
-!3 = metadata !{i32 655401, metadata !"/Volumes/Athwagate/R9747970/apf.cc", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ]
-!4 = metadata !{metadata !5, metadata !1, metadata !7, metadata !12}
-!5 = metadata !{i32 655373, metadata !2, metadata !"prec", metadata !3, i32 13, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ]
-!6 = metadata !{i32 655396, metadata !0, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
-!7 = metadata !{i32 655406, i32 0, metadata !2, metadata !"partCount", metadata !"partCount", metadata !"_ZNK7APFloat9partCountEv", metadata !3, i32 9, metadata !8, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 true, null, null} ; [ DW_TAG_subprogram ]
-!8 = metadata !{i32 655381, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !9, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
-!9 = metadata !{metadata !6, metadata !10}
-!10 = metadata !{i32 655375, metadata !0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !11} ; [ DW_TAG_pointer_type ]
-!11 = metadata !{i32 655398, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ]
-!12 = metadata !{i32 655406, i32 0, metadata !2, metadata !"significandParts", metadata !"significandParts", metadata !"_ZNK7APFloat16significandPartsEv", metadata !3, i32 11, metadata !13, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 true, null, null} ; [ DW_TAG_subprogram ]
-!13 = metadata !{i32 655381, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !14, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
-!14 = metadata !{metadata !15, metadata !10}
-!15 = metadata !{i32 655375, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !16} ; [ DW_TAG_pointer_type ]
-!16 = metadata !{i32 655382, metadata !0, metadata !"integerPart", metadata !3, i32 2, i64 0, i64 0, i64 0, i32 0, metadata !17} ; [ DW_TAG_typedef ]
-!17 = metadata !{i32 655382, metadata !0, metadata !"uint64_t", metadata !3, i32 1, i64 0, i64 0, i64 0, i32 0, metadata !18} ; [ DW_TAG_typedef ]
-!18 = metadata !{i32 655396, metadata !0, metadata !"long long unsigned int", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
-!19 = metadata !{i32 655381, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !20, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
-!20 = metadata !{metadata !21, metadata !10, metadata !22}
-!21 = metadata !{i32 655396, metadata !0, metadata !"bool", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ]
-!22 = metadata !{i32 655376, metadata !0, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !11} ; [ DW_TAG_reference_type ]
-!23 = metadata !{i32 655406, i32 0, metadata !0, metadata !"partCount", metadata !"partCount", metadata !"_ZNK7APFloat9partCountEv", metadata !3, i32 23, metadata !8, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%class.APFloat*)* @_ZNK7APFloat9partCountEv, null, metadata !7} ; [ DW_TAG_subprogram ]
-!24 = metadata !{i32 655406, i32 0, metadata !0, metadata !"bitwiseIsEqual", metadata !"bitwiseIsEqual", metadata !"_ZNK7APFloat14bitwiseIsEqualERKS_", metadata !3, i32 28, metadata !19, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (%class.APFloat*, %class.APFloat*)* @_ZNK7APFloat14bitwiseIsEqualERKS_, null, metadata !1} ; [ DW_TAG_subprogram ]
-!25 = metadata !{i32 655406, i32 0, metadata !3, metadata !"partCountForBits", metadata !"partCountForBits", metadata !"", metadata !3, i32 17, metadata !26, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null} ; [ DW_TAG_subprogram ]
-!26 = metadata !{i32 655381, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !27, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
-!27 = metadata !{metadata !6}
-!28 = metadata !{i32 655617, metadata !23, metadata !"this", metadata !3, i32 16777238, metadata !10, i32 64, i32 0} ; [ DW_TAG_arg_variable ]
-!29 = metadata !{i32 655617, metadata !24, metadata !"this", metadata !3, i32 16777244, metadata !10, i32 64, i32 0} ; [ DW_TAG_arg_variable ]
-!30 = metadata !{i32 655617, metadata !24, metadata !"rhs", metadata !3, i32 33554460, metadata !22, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
-!31 = metadata !{i32 655616, metadata !32, metadata !"i", metadata !3, i32 29, metadata !33, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
-!32 = metadata !{i32 655371, metadata !24, i32 28, i32 56, metadata !3, i32 1} ; [ DW_TAG_lexical_block ]
-!33 = metadata !{i32 655396, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!34 = metadata !{i32 655616, metadata !32, metadata !"p", metadata !3, i32 30, metadata !35, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
-!35 = metadata !{i32 655375, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !36} ; [ DW_TAG_pointer_type ]
-!36 = metadata !{i32 655398, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !16} ; [ DW_TAG_const_type ]
-!37 = metadata !{i32 655616, metadata !32, metadata !"q", metadata !3, i32 31, metadata !35, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
-!38 = metadata !{i32 655617, metadata !25, metadata !"bits", metadata !3, i32 16777232, metadata !6, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
-!39 = metadata !{i32 655412, i32 0, metadata !3, metadata !"integerPartWidth", metadata !"integerPartWidth", metadata !"integerPartWidth", metadata !3, i32 3, metadata !40, i32 1, i32 1, i32 42} ; [ DW_TAG_variable ]
-!40 = metadata !{i32 655398, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_const_type ]
-!41 = metadata !{i32 22, i32 23, metadata !23, null}
-!42 = metadata !{i32 24, i32 10, metadata !43, null}
-!43 = metadata !{i32 655371, metadata !23, i32 23, i32 1, metadata !3, i32 0} ; [ DW_TAG_lexical_block ]
-!44 = metadata !{metadata !"int", metadata !45}
-!45 = metadata !{metadata !"omnipotent char", metadata !46}
-!46 = metadata !{metadata !"Simple C/C++ TBAA", null}
-!47 = metadata !{i32 655617, metadata !25, metadata !"bits", metadata !3, i32 16777232, metadata !6, i32 0, metadata !42} ; [ DW_TAG_arg_variable ]
-!48 = metadata !{i32 16, i32 58, metadata !25, metadata !42}
-!49 = metadata !{i32 18, i32 3, metadata !50, metadata !42}
-!50 = metadata !{i32 655371, metadata !25, i32 17, i32 1, metadata !3, i32 4} ; [ DW_TAG_lexical_block ]
-!51 = metadata !{i32 28, i32 15, metadata !24, null}
-!52 = metadata !{i32 28, i32 45, metadata !24, null}
-!53 = metadata !{i32 655617, metadata !23, metadata !"this", metadata !3, i32 16777238, metadata !10, i32 64, metadata !54} ; [ DW_TAG_arg_variable ]
-!54 = metadata !{i32 29, i32 10, metadata !32, null}
-!55 = metadata !{i32 22, i32 23, metadata !23, metadata !54}
-!56 = metadata !{i32 24, i32 10, metadata !43, metadata !54}
-!57 = metadata !{i32 655617, metadata !25, metadata !"bits", metadata !3, i32 16777232, metadata !6, i32 0, metadata !56} ; [ DW_TAG_arg_variable ]
-!58 = metadata !{i32 16, i32 58, metadata !25, metadata !56}
-!59 = metadata !{i32 18, i32 3, metadata !50, metadata !56}
-!60 = metadata !{i32 30, i32 24, metadata !32, null}
-!61 = metadata !{i32 31, i32 24, metadata !32, null}
-!62 = metadata !{i32 32, i32 3, metadata !32, null}
-!63 = metadata !{i32 33, i32 5, metadata !64, null}
-!64 = metadata !{i32 655371, metadata !65, i32 32, i32 25, metadata !3, i32 3} ; [ DW_TAG_lexical_block ]
-!65 = metadata !{i32 655371, metadata !32, i32 32, i32 3, metadata !3, i32 2} ; [ DW_TAG_lexical_block ]
-!66 = metadata !{metadata !"long long", metadata !45}
-!67 = metadata !{i32 32, i32 15, metadata !65, null}
-!68 = metadata !{i32 37, i32 1, metadata !32, null}

Modified: llvm/trunk/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=143177&r1=143176&r2=143177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3.ll Thu Oct 27 20:29:32 2011
@@ -16,10 +16,8 @@
 	ret void
         
 ; X64: t0:
-; X64: 	movddup	(%rsi), %xmm0
-; X64:  pshuflw	$0, %xmm0, %xmm0
-; X64:	xorl	%eax, %eax
-; X64:	pinsrw	$0, %eax, %xmm0
+; X64:	movdqa	(%rsi), %xmm0
+; X64:	pslldq	$2, %xmm0
 ; X64:	movdqa	%xmm0, (%rdi)
 ; X64:	ret
 }
@@ -31,9 +29,8 @@
 	ret <8 x i16> %tmp3
         
 ; X64: t1:
-; X64: 	movl	(%rsi), %eax
 ; X64: 	movdqa	(%rdi), %xmm0
-; X64: 	pinsrw	$0, %eax, %xmm0
+; X64: 	pinsrw	$0, (%rsi), %xmm0
 ; X64: 	ret
 }
 
@@ -168,7 +165,7 @@
         ret void
 ; X64: 	t10:
 ; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %eax
-; X64: 		unpcklpd [[X1:%xmm[0-9]+]]
+; X64: 		movlhps [[X1:%xmm[0-9]+]]
 ; X64: 		pshuflw	$8, [[X1]], [[X2:%xmm[0-9]+]]
 ; X64: 		pinsrw	$2, %eax, [[X2]]
 ; X64: 		pextrw	$6, [[X0]], %eax
@@ -250,13 +247,12 @@
         %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0,  <16 x i32> < i32 0, i32 1, i32 2, i32 17,  i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
         ret <16 x i8> %tmp9
 ; X64: 	t16:
-; X64: 		pinsrw	$0, %eax, [[X1:%xmm[0-9]+]]
-; X64: 		pextrw	$8, [[X0:%xmm[0-9]+]], %eax
-; X64: 		pinsrw	$1, %eax, [[X1]]
-; X64: 		pextrw	$1, [[X1]], %ecx
-; X64: 		movd	[[X1]], %edx
-; X64: 		pinsrw	$0, %edx, %xmm
-; X64: 		pinsrw	$1, %eax, %xmm
+; X64: 		movdqa	%xmm1, %xmm0
+; X64: 		pslldq	$2, %xmm0
+; X64: 		pextrw	$1, %xmm0, %eax
+; X64: 		movd	%xmm0, %ecx
+; X64: 		pinsrw	$0, %ecx, %xmm0
+; X64: 		pextrw	$8, %xmm1, %ecx
 ; X64: 		ret
 }
 



From chandlerc at google.com  Thu Oct 27 20:40:29 2011
From: chandlerc at google.com (Chandler Carruth)
Date: Thu, 27 Oct 2011 18:40:29 -0700
Subject: [llvm-commits] [llvm] r143177 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ lib/Target/XCore/
 test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb/
 test/CodeGen/X86/
In-Reply-To: <20111028012933.AFA263128060@llvm.org>
References: <20111028012933.AFA263128060@llvm.org>
Message-ID: <CAGCO0KiSRdmUd9pxw4jqL6f7cmzOZghqewYA4odBRrWsepa-rw@mail.gmail.com>

On Thu, Oct 27, 2011 at 6:29 PM, Dan Gohman <gohman at apple.com> wrote:

> Author: djg
> Date: Thu Oct 27 20:29:32 2011
> New Revision: 143177
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143177&view=rev
> Log:
> Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
> on every node as it legalizes them. This makes it easier to use
> hasOneUse() heuristics, since unneeded nodes can be removed from the
> DAG earlier.
>
> Make LegalizeOps visit the DAG in an operands-last order. It previously
> used operands-first, because LegalizeTypes has to go operands-first, and
> LegalizeTypes used to be part of LegalizeOps, but they're now split.
> The operands-last order is more natural for several legalization tasks.
> For example, it allows lowering code for nodes with floating-point or
> vector constants to see those constants directly instead of seeing the
> lowered form (often constant-pool loads). This makes some things
> somewhat more complicated today, though it ought to allow things to be
> simpler in the future. It also fixes some bugs exposed by Legalizing
> using RAUW aggressively.
>
> Remove the part of LegalizeOps that attempted to patch up invalid chain
> operands on libcalls generated by LegalizeTypes, since it doesn't work
> with the new LegalizeOps traversal order. Instead, define what
> LegalizeTypes is doing to be correct, and transfer the responsibility
> of keeping calls from having overlapping calling sequences into the
> scheduler.
>
> Teach the scheduler to model callseq_begin/end pairs as having a
> physical register definition/use to prevent calls from having
> overlapping calling sequences. This is also somewhat complicated, though
> there are ways it might be simplified in the future.
>
> This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
> Please direct high-level questions about this patch to management.
>
> Removed:
>    llvm/trunk/test/CodeGen/X86/2009-02-05-CoalescerBug.ll
>    llvm/trunk/test/CodeGen/X86/dbg-inline.ll
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
>    llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
>    llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll
>    llvm/trunk/test/CodeGen/CellSPU/nand.ll
>    llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
>    llvm/trunk/test/CodeGen/CellSPU/select_bits.ll
>    llvm/trunk/test/CodeGen/CellSPU/struct_1.ll
>    llvm/trunk/test/CodeGen/Mips/cprestore.ll
>    llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
>    llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
>    llvm/trunk/test/CodeGen/X86/sse3.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=143177&r1=143176&r2=143177&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Oct 27 20:29:32
> 2011
>

<snip>


> +#if 0
> +  SDValue LastChain = DAG.getEntryNode();
> +  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
> +       E = DAG.allnodes_end(); I != E; ++I) {
> +    SDNode *N = I;
> +    if (N->getOpcode() == ISD::CALLSEQ_START) {
> +      SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
> +      Ops[0] = LastChain;
> +      SDNode *New = DAG.UpdateNodeOperands(N, Ops.data(), Ops.size());
> +      assert(New == N && "CALLSEQ_START got CSE'd!");
> +    }
> +    for (unsigned i = 0, e = N->getNumValues(); i != e; ++i)
> +      if (N->getValueType(i) == MVT::Other)
> +        LastChain = SDValue(N, i);
>   }
> +#endif
>

FYI, was leaving this #if 0-ed code intentional?
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From gohman at apple.com  Thu Oct 27 20:41:21 2011
From: gohman at apple.com (Dan Gohman)
Date: Fri, 28 Oct 2011 01:41:21 -0000
Subject: [llvm-commits] [llvm] r143179 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Message-ID: <20111028014121.A7AE13128060@llvm.org>

Author: djg
Date: Thu Oct 27 20:41:21 2011
New Revision: 143179

URL: http://llvm.org/viewvc/llvm-project?rev=143179&view=rev
Log:
Delete #if 0 code accidentally left in.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=143179&r1=143178&r2=143179&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Oct 27 20:41:21 2011
@@ -185,23 +185,6 @@
 void SelectionDAGLegalize::LegalizeDAG() {
   DAG.AssignTopologicalOrder();
 
-#if 0
-  SDValue LastChain = DAG.getEntryNode();
-  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
-       E = DAG.allnodes_end(); I != E; ++I) {
-    SDNode *N = I;
-    if (N->getOpcode() == ISD::CALLSEQ_START) {
-      SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
-      Ops[0] = LastChain;
-      SDNode *New = DAG.UpdateNodeOperands(N, Ops.data(), Ops.size());
-      assert(New == N && "CALLSEQ_START got CSE'd!");
-    }
-    for (unsigned i = 0, e = N->getNumValues(); i != e; ++i)
-      if (N->getValueType(i) == MVT::Other)
-        LastChain = SDValue(N, i);
-  }
-#endif
-
   // Visit all the nodes. We start in topological order, so that we see
   // nodes with their original operands intact. Legalization can produce
   // new nodes which may themselves need to be legalized. Iterate until all



From gohman at apple.com  Thu Oct 27 20:44:29 2011
From: gohman at apple.com (Dan Gohman)
Date: Thu, 27 Oct 2011 18:44:29 -0700
Subject: [llvm-commits] [llvm] r143177 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ lib/Target/XCore/
 test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb/
 test/CodeGen/X86/
In-Reply-To: <CAGCO0KiSRdmUd9pxw4jqL6f7cmzOZghqewYA4odBRrWsepa-rw@mail.gmail.com>
References: <20111028012933.AFA263128060@llvm.org>
	<CAGCO0KiSRdmUd9pxw4jqL6f7cmzOZghqewYA4odBRrWsepa-rw@mail.gmail.com>
Message-ID: <CC055E43-BA50-4DD0-A3AF-536DDDE952E8@apple.com>

On Oct 27, 2011, at 6:40 PM, Chandler Carruth wrote:

> On Thu, Oct 27, 2011 at 6:29 PM, Dan Gohman <gohman at apple.com> wrote:
> 
> +#if 0
> +  SDValue LastChain = DAG.getEntryNode();
> +  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
> +       E = DAG.allnodes_end(); I != E; ++I) {
> +    SDNode *N = I;
> +    if (N->getOpcode() == ISD::CALLSEQ_START) {
> +      SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
> +      Ops[0] = LastChain;
> +      SDNode *New = DAG.UpdateNodeOperands(N, Ops.data(), Ops.size());
> +      assert(New == N && "CALLSEQ_START got CSE'd!");
> +    }
> +    for (unsigned i = 0, e = N->getNumValues(); i != e; ++i)
> +      if (N->getValueType(i) == MVT::Other)
> +        LastChain = SDValue(N, i);
>   }
> +#endif
> 
> FYI, was leaving this #if 0-ed code intentional?

Nope. Fixed now.

Dan


From eli.friedman at gmail.com  Thu Oct 27 20:56:18 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 27 Oct 2011 18:56:18 -0700
Subject: [llvm-commits] [llvm] r143177 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ lib/Target/XCore/
 test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb/
 test/CodeGen/X86/
In-Reply-To: <20111028012933.AFA263128060@llvm.org>
References: <20111028012933.AFA263128060@llvm.org>
Message-ID: <CAJdarcGxpPGtCEtLsoXFKzqxbRt5FCX_jXH9YrfnefDFAkYzQA@mail.gmail.com>

On Thu, Oct 27, 2011 at 6:29 PM, Dan Gohman <gohman at apple.com> wrote:
> @@ -3628,6 +3351,35 @@
> ? ? Results.push_back(Tmp1);
> ? ? break;
> ? }
> + ?case ISD::BUILD_VECTOR:
> + ? ?Results.push_back(ExpandBUILD_VECTOR(Node));
> + ? ?break;
> + ?case ISD::SRA:
> + ?case ISD::SRL:
> + ?case ISD::SHL: {
> + ? ?// Scalarize vector SRA/SRL/SHL.
> + ? ?EVT VT = Node->getValueType(0);
> + ? ?assert(VT.isVector() && "Unable to legalize non-vector shift");
> + ? ?assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
> + ? ?unsigned NumElem = VT.getVectorNumElements();
> +
> + ? ?SmallVector<SDValue, 8> Scalars;
> + ? ?for (unsigned Idx = 0; Idx < NumElem; Idx++) {
> + ? ? ?SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VT.getScalarType(),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Node->getOperand(0), DAG.getIntPtrConstant(Idx));
> + ? ? ?SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VT.getScalarType(),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Node->getOperand(1), DAG.getIntPtrConstant(Idx));
> + ? ? ?Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?VT.getScalarType(), Ex, Sh));
> + ? ?}
> + ? ?SDValue Result =
> + ? ? ?DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
> + ? ? ? ? ? ? ? ? ?&Scalars[0], Scalars.size());
> + ? ?DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
> + ? ?break;
> + ?}

We ought to be scalarizing vector shifts in LegalizeVectorOps; is
there some case where that is not sufficient?

-Eli


From bruno.cardoso at gmail.com  Thu Oct 27 21:02:56 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Fri, 28 Oct 2011 00:02:56 -0200
Subject: [llvm-commits] [llvm] r143177 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ lib/Target/XCore/
 test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb/
 test/CodeGen/X86/
In-Reply-To: <20111028012933.AFA263128060@llvm.org>
References: <20111028012933.AFA263128060@llvm.org>
Message-ID: <CACk9FxYu2hmCXYiSEW8QVG-M4xFYyafesG6Ka+BG-E3V73p4LA@mail.gmail.com>

On Thu, Oct 27, 2011 at 11:29 PM, Dan Gohman <gohman at apple.com> wrote:
> Author: djg
> Date: Thu Oct 27 20:29:32 2011
> New Revision: 143177
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143177&view=rev
> Log:
> Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
> on every node as it legalizes them. This makes it easier to use
> hasOneUse() heuristics, since unneeded nodes can be removed from the
> DAG earlier.
>
> Make LegalizeOps visit the DAG in an operands-last order. It previously
> used operands-first, because LegalizeTypes has to go operands-first, and
> LegalizeTypes used to be part of LegalizeOps, but they're now split.
> The operands-last order is more natural for several legalization tasks.
> For example, it allows lowering code for nodes with floating-point or
> vector constants to see those constants directly instead of seeing the
> lowered form (often constant-pool loads). This makes some things
> somewhat more complicated today, though it ought to allow things to be
> simpler in the future. It also fixes some bugs exposed by Legalizing
> using RAUW aggressively.
>
> Remove the part of LegalizeOps that attempted to patch up invalid chain
> operands on libcalls generated by LegalizeTypes, since it doesn't work
> with the new LegalizeOps traversal order. Instead, define what
> LegalizeTypes is doing to be correct, and transfer the responsibility
> of keeping calls from having overlapping calling sequences into the
> scheduler.
>
> Teach the scheduler to model callseq_begin/end pairs as having a
> physical register definition/use to prevent calls from having
> overlapping calling sequences. This is also somewhat complicated, though
> there are ways it might be simplified in the future.
>
> This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
> Please direct high-level questions about this patch to management.

As a reference, I believe this also fixes PR8156!

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc

From gohman at apple.com  Thu Oct 27 21:02:14 2011
From: gohman at apple.com (Dan Gohman)
Date: Thu, 27 Oct 2011 19:02:14 -0700
Subject: [llvm-commits] [llvm] r143177 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ lib/Target/XCore/
 test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb/
 test/CodeGen/X86/
In-Reply-To: <CAJdarcGxpPGtCEtLsoXFKzqxbRt5FCX_jXH9YrfnefDFAkYzQA@mail.gmail.com>
References: <20111028012933.AFA263128060@llvm.org>
	<CAJdarcGxpPGtCEtLsoXFKzqxbRt5FCX_jXH9YrfnefDFAkYzQA@mail.gmail.com>
Message-ID: <99EF7A0F-DA58-4CBB-9256-1F1DB920F4F5@apple.com>


On Oct 27, 2011, at 6:56 PM, Eli Friedman wrote:

> On Thu, Oct 27, 2011 at 6:29 PM, Dan Gohman <gohman at apple.com> wrote:
>> @@ -3628,6 +3351,35 @@
>>     Results.push_back(Tmp1);
>>     break;
>>   }
>> +  case ISD::BUILD_VECTOR:
>> +    Results.push_back(ExpandBUILD_VECTOR(Node));
>> +    break;
>> +  case ISD::SRA:
>> +  case ISD::SRL:
>> +  case ISD::SHL: {
>> +    // Scalarize vector SRA/SRL/SHL.
>> +    EVT VT = Node->getValueType(0);
>> +    assert(VT.isVector() && "Unable to legalize non-vector shift");
>> +    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
>> +    unsigned NumElem = VT.getVectorNumElements();
>> +
>> +    SmallVector<SDValue, 8> Scalars;
>> +    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
>> +      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
>> +                               VT.getScalarType(),
>> +                               Node->getOperand(0), DAG.getIntPtrConstant(Idx));
>> +      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
>> +                               VT.getScalarType(),
>> +                               Node->getOperand(1), DAG.getIntPtrConstant(Idx));
>> +      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
>> +                                    VT.getScalarType(), Ex, Sh));
>> +    }
>> +    SDValue Result =
>> +      DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
>> +                  &Scalars[0], Scalars.size());
>> +    DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
>> +    break;
>> +  }
> 
> We ought to be scalarizing vector shifts in LegalizeVectorOps; is
> there some case where that is not sufficient?

That code predates this patch. It may be a leftover from pre-LegalizeTypes days.

Dan


From joerg at britannica.bec.de  Thu Oct 27 22:01:22 2011
From: joerg at britannica.bec.de (Joerg Sonnenberger)
Date: Thu, 27 Oct 2011 20:01:22 -0700
Subject: [llvm-commits] [cfe-commits] Ping^2: Fix for bug 11060:
 configure --target does not work
In-Reply-To: <CAE5reQ+oyYNMuuCCC2hgnsWUwCYXR1zfZs+nkT6Y9dyKznK7pQ@mail.gmail.com>
References: <CAE5reQKS3TWCGnZB9V5FUHh18tPu15Rqeb4hPp7ziHa1c_+YRA@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713404@GEORGE.Emea.Arm.com>
	<CAE5reQKuxURmZcTRhjU1p7MURECVKXFF8tjRZmD23+6zHBVQWQ@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713405@GEORGE.Emea.Arm.com>
	<64775AFC-9ADD-4C75-86EE-9688036285EB@apple.com>
	<CAE5reQJ3J5T1z8JCfkdHM63u8Shsddpty5=PCjx1X-Xp4yjR5Q@mail.gmail.com>
	<20111026165442.GD19773@britannica.bec.de>
	<CAE5reQLEvirPzur-q0HPKkBvJZ=EDnWOm6BXogCvbQNUu6bw6g@mail.gmail.com>
	<20111027022913.GA21866@britannica.bec.de>
	<CAE5reQ+oyYNMuuCCC2hgnsWUwCYXR1zfZs+nkT6Y9dyKznK7pQ@mail.gmail.com>
Message-ID: <20111028030122.GA2196@britannica.bec.de>

On Wed, Oct 26, 2011 at 09:45:41PM -0500, Sebastian Pop wrote:
> On Wed, Oct 26, 2011 at 9:29 PM, Joerg Sonnenberger
> <joerg at britannica.bec.de> wrote:
> > I've told you already, I think deriving the default value of
> > LLVM_HOSTTRIPLE from $target makes more sense. What I object to is
> > introducing another macro and associated support code which doesn't
> > serve any purpose.
> 
> How are these two different:
> 
> 1. create LLVM_DEFAULT_TARGET from $target, and remove LLVM_HOSTTRIPLE
> (I'll let you post a patch that removes LLVM_HOSTTRIPLE as you said
> that HOST is unused)
> 
> 2. derive LLVM_HOSTTRIPLE from $target as you proposed, then rename
> LLVM_HOSTTRIPLE into something more meaningful, like what I proposed
> LLVM_DEFAULT_TARGET.
> 
> ?
> 
> Thanks for clarifying your stand point if it differs from the two above.

The second makes sure that everything is consistent from the start, no
chance of forgetting something in the middle. So yes, (2) is fine with
me, but the "rename to something meaningful" part has to be part of a
larger API change, since the host vs target misnaming is very sticky.

Joerg

From atrick at apple.com  Thu Oct 27 22:45:11 2011
From: atrick at apple.com (Andrew Trick)
Date: Fri, 28 Oct 2011 03:45:11 -0000
Subject: [llvm-commits] [llvm] r143183 - in /llvm/trunk:
 lib/Transforms/Scalar/IndVarSimplify.cpp
 test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll
Message-ID: <20111028034511.7677C3128060@llvm.org>

Author: atrick
Date: Thu Oct 27 22:45:11 2011
New Revision: 143183

URL: http://llvm.org/viewvc/llvm-project?rev=143183&view=rev
Log:
LFTR should avoid a type mismatch with null pointer IVs.

Fixes rdar://10359193 Indvar LinearFunctionTestReplace assertion

Added:
    llvm/trunk/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=143183&r1=143182&r2=143183&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Thu Oct 27 22:45:11 2011
@@ -1558,8 +1558,7 @@
   }
 
   // For unit stride, IVLimit = Start + BECount with 2's complement overflow.
-  // So for, non-zero start compute the IVLimit here.
-  bool isPtrIV = false;
+  // So for non-zero start compute the IVLimit here.
   Type *CmpTy = CntTy;
   const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(IndVar));
   assert(AR && AR->getLoop() == L && AR->isAffine() && "bad loop counter");
@@ -1571,8 +1570,7 @@
     // Note that for without EnableIVRewrite, we never run SCEVExpander on a
     // pointer type, because we must preserve the existing GEPs. Instead we
     // directly generate a GEP later.
-    if (IVInit->getType()->isPointerTy()) {
-      isPtrIV = true;
+    if (CmpIndVar->getType()->isPointerTy()) {
       CmpTy = SE->getEffectiveSCEVType(IVInit->getType());
       IVLimit = SE->getTruncateOrSignExtend(IVLimit, CmpTy);
     }
@@ -1590,21 +1588,25 @@
 
   assert(SE->isLoopInvariant(IVLimit, L) &&
          "Computed iteration count is not loop invariant!");
+  assert( !IVLimit->getType()->isPointerTy() &&
+          "Should not expand pointer types" );
   Value *ExitCnt = Rewriter.expandCodeFor(IVLimit, CmpTy, BI);
 
   // Create a gep for IVInit + IVLimit from on an existing pointer base.
-  assert(isPtrIV == IndVar->getType()->isPointerTy() &&
-         "IndVar type must match IVInit type");
-  if (isPtrIV) {
-      Value *IVStart = IndVar->getIncomingValueForBlock(L->getLoopPreheader());
-      assert(AR->getStart() == SE->getSCEV(IVStart) && "bad loop counter");
-      assert(SE->getSizeOfExpr(
-               cast<PointerType>(IVStart->getType())->getElementType())->isOne()
-             && "unit stride pointer IV must be i8*");
-
-      Builder.SetInsertPoint(L->getLoopPreheader()->getTerminator());
-      ExitCnt = Builder.CreateGEP(IVStart, ExitCnt, "lftr.limit");
-      Builder.SetInsertPoint(BI);
+  //
+  // In the presence of null pointer values, the SCEV expression may be an
+  // integer type while the IV is a pointer type. Ensure that the compare
+  // operands are always the same type by checking the IV type here.
+  if (CmpIndVar->getType()->isPointerTy()) {
+    Value *IVStart = IndVar->getIncomingValueForBlock(L->getLoopPreheader());
+    assert(AR->getStart() == SE->getSCEV(IVStart) && "bad loop counter");
+    assert(SE->getSizeOfExpr(
+             cast<PointerType>(IVStart->getType())->getElementType())->isOne()
+           && "unit stride pointer IV must be i8*");
+
+    Builder.SetInsertPoint(L->getLoopPreheader()->getTerminator());
+    ExitCnt = Builder.CreateGEP(IVStart, ExitCnt, "lftr.limit");
+    Builder.SetInsertPoint(BI);
   }
 
   // Insert a new icmp_ne or icmp_eq instruction before the branch.

Added: llvm/trunk/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll?rev=143183&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll (added)
+++ llvm/trunk/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll Thu Oct 27 22:45:11 2011
@@ -0,0 +1,59 @@
+; RUN: opt < %s -indvars -S | FileCheck %s
+; rdar://10359193: assert "IndVar type must match IVInit type"
+
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
+target triple = "thumbv7-apple-darwin"
+
+; CHECK: @test
+; CHECK: if.end.i126:
+; CHECK: %exitcond = icmp ne i8* %incdec.ptr.i, getelementptr (i8* null, i32 undef)
+define void @test() nounwind {
+entry:
+  br label %while.cond
+
+while.cond:
+  br i1 undef, label %while.end, label %while.body
+
+while.body:                                       ; preds = %while.cond
+  br i1 undef, label %if.then165, label %while.cond
+
+if.then165:                                       ; preds = %while.body
+  br i1 undef, label %while.cond, label %for.body.lr.ph.i81
+
+for.body.lr.ph.i81:                               ; preds = %if.then165
+  br label %for.body.i86
+
+for.body.i86:                                     ; preds = %for.end.i129, %for.body.lr.ph.i81
+  %cmp196.i = icmp ult i32 0, undef
+  br i1 %cmp196.i, label %for.body21.lr.ph.i, label %for.end.i129
+
+for.body21.lr.ph.i:                               ; preds = %for.body.i86
+  br label %for.body21.i
+
+for.body21.i:
+  %destYPixelPtr.010.i = phi i8* [ null, %for.body21.lr.ph.i ], [ %incdec.ptr.i, %if.end.i126 ]
+  %x.09.i = phi i32 [ 0, %for.body21.lr.ph.i ], [ %inc.i125, %if.end.i126 ]
+  br i1 undef, label %if.end.i126, label %if.else.i124
+
+if.else.i124:                                     ; preds = %for.body21.i
+  store i8 undef, i8* %destYPixelPtr.010.i, align 1
+  br label %if.end.i126
+
+if.end.i126:                                      ; preds = %if.else.i124, %for.body21.i
+  %incdec.ptr.i = getelementptr inbounds i8* %destYPixelPtr.010.i, i32 1
+  %inc.i125 = add i32 %x.09.i, 1
+  %cmp19.i = icmp ult i32 %inc.i125, undef
+  br i1 %cmp19.i, label %for.body21.i, label %for.end.i129
+
+for.end.i129:                                     ; preds = %if.end.i126, %for.body.i86
+  br i1 undef, label %for.body.i86, label %while.cond
+
+while.end:                                        ; preds = %while.cond
+  br label %bail
+
+bail:                                             ; preds = %while.end, %lor.lhs.false44, %lor.lhs.false41, %if.end29, %if.end
+  unreachable
+
+return:                                           ; preds = %lor.lhs.false20, %lor.lhs.false12, %lor.lhs.false, %entry
+  ret void
+}



From baldrick at free.fr  Thu Oct 27 23:05:19 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 28 Oct 2011 06:05:19 +0200
Subject: [llvm-commits] [llvm] r143135 - in /llvm/trunk:
 docs/LangRef.html include/llvm/LLVMContext.h lib/VMCore/LLVMContext.cpp
In-Reply-To: <20111027191915.002033128060@llvm.org>
References: <20111027191915.002033128060@llvm.org>
Message-ID: <4EAA29FF.4000208@free.fr>

Hi Peter, part of the metadata design is that it should always be safe (if
sub-optimal) to remove it.  Will you get correct results if fpaccuracy meta
data is dropped?

Ciao, Duncan.

> Add a pinned metadata name for fpaccuracy, and document it
>
> Modified:
>      llvm/trunk/docs/LangRef.html
>      llvm/trunk/include/llvm/LLVMContext.h
>      llvm/trunk/lib/VMCore/LLVMContext.cpp
>
> Modified: llvm/trunk/docs/LangRef.html
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=143135&r1=143134&r2=143135&view=diff
> ==============================================================================
> --- llvm/trunk/docs/LangRef.html (original)
> +++ llvm/trunk/docs/LangRef.html Thu Oct 27 14:19:14 2011
> @@ -103,6 +103,7 @@
>         <li><a href="#metadata">Metadata Nodes and Metadata Strings</a>
>           <ol>
>             <li><a href="#tbaa">'<tt>tbaa</tt>' Metadata</a></li>
> +<li><a href="#fpaccuracy">'<tt>fpaccuracy</tt>' Metadata</a></li>
>           </ol>
>         </li>
>       </ol>
> @@ -2966,6 +2967,35 @@
>
>   </div>
>
> +<h4>
> +<a name="fpaccuracy">'<tt>fpaccuracy</tt>' Metadata</a>
> +</h4>
> +
> +<div>
> +
> +<p><tt>fpaccuracy</tt>  metadata may be attached to any instruction of floating
> +   point type.  It expresses the maximum relative error of the result of
> +   that instruction, in ULPs. ULP is defined as follows:</p>
> +
> +<blockquote><p>
> +If x is a real number that lies between two finite consecutive floating-point
> +numbers a and b, without being equal to one of them, then ulp(x) = |b - a|,
> +otherwise ulp(x) is the distance between the two non-equal finite
> +floating-point numbers nearest x. Moreover, ulp(NaN) is NaN.
> +</p></blockquote>
> +
> +<p>The maximum relative error may be any rational number.  The metadata node
> +   shall consist of a pair of unsigned integers respectively representing
> +   the numerator and denominator.  For example, 2.5 ULP:</p>
> +
> +<div class="doc_code">
> +<pre>
> +!0 = metadata !{ i32 5, i32 2 }
> +</pre>
> +</div>
> +
> +</div>
> +
>   </div>
>
>   </div>
>
> Modified: llvm/trunk/include/llvm/LLVMContext.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=143135&r1=143134&r2=143135&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/LLVMContext.h (original)
> +++ llvm/trunk/include/llvm/LLVMContext.h Thu Oct 27 14:19:14 2011
> @@ -40,7 +40,8 @@
>     enum {
>       MD_dbg = 0,  // "dbg"
>       MD_tbaa = 1, // "tbaa"
> -    MD_prof = 2  // "prof"
> +    MD_prof = 2,  // "prof"
> +    MD_fpaccuracy = 3  // "fpaccuracy"
>     };
>
>     /// getMDKindID - Return a unique non-zero ID for the specified metadata kind.
>
> Modified: llvm/trunk/lib/VMCore/LLVMContext.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContext.cpp?rev=143135&r1=143134&r2=143135&view=diff
> ==============================================================================
> --- llvm/trunk/lib/VMCore/LLVMContext.cpp (original)
> +++ llvm/trunk/lib/VMCore/LLVMContext.cpp Thu Oct 27 14:19:14 2011
> @@ -43,6 +43,11 @@
>     // Create the 'prof' metadata kind.
>     unsigned ProfID = getMDKindID("prof");
>     assert(ProfID == MD_prof&&  "prof kind id drifted"); (void)ProfID;
> +
> +  // Create the 'fpaccuracy' metadata kind.
> +  unsigned FPAccuracyID = getMDKindID("fpaccuracy");
> +  assert(FPAccuracyID == MD_fpaccuracy&&  "fpaccuracy kind id drifted");
> +  (void)FPAccuracyID;
>   }
>   LLVMContext::~LLVMContext() { delete pImpl; }
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From spop at codeaurora.org  Fri Oct 28 00:01:31 2011
From: spop at codeaurora.org (Sebastian Pop)
Date: Fri, 28 Oct 2011 00:01:31 -0500
Subject: [llvm-commits] [cfe-commits] Ping^2: Fix for bug 11060:
 configure --target does not work
In-Reply-To: <20111028030122.GA2196@britannica.bec.de>
References: <CAE5reQKS3TWCGnZB9V5FUHh18tPu15Rqeb4hPp7ziHa1c_+YRA@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713404@GEORGE.Emea.Arm.com>
	<CAE5reQKuxURmZcTRhjU1p7MURECVKXFF8tjRZmD23+6zHBVQWQ@mail.gmail.com>
	<F01D8B85CFF58440B2A13965FBA90CA47375713405@GEORGE.Emea.Arm.com>
	<64775AFC-9ADD-4C75-86EE-9688036285EB@apple.com>
	<CAE5reQJ3J5T1z8JCfkdHM63u8Shsddpty5=PCjx1X-Xp4yjR5Q@mail.gmail.com>
	<20111026165442.GD19773@britannica.bec.de>
	<CAE5reQLEvirPzur-q0HPKkBvJZ=EDnWOm6BXogCvbQNUu6bw6g@mail.gmail.com>
	<20111027022913.GA21866@britannica.bec.de>
	<CAE5reQ+oyYNMuuCCC2hgnsWUwCYXR1zfZs+nkT6Y9dyKznK7pQ@mail.gmail.com>
	<20111028030122.GA2196@britannica.bec.de>
Message-ID: <CAE5reQKFgZndRkGyeqfvmyhq8vk5t3Z_Ko-YE0YibXZ27H0hvw@mail.gmail.com>

On Thu, Oct 27, 2011 at 10:01 PM, Joerg Sonnenberger
<joerg at britannica.bec.de> wrote:
>> 1. create LLVM_DEFAULT_TARGET from $target, and remove LLVM_HOSTTRIPLE
>> (I'll let you post a patch that removes LLVM_HOSTTRIPLE as you said
>> that HOST is unused)
>>
>> 2. derive LLVM_HOSTTRIPLE from $target as you proposed, then rename
>> LLVM_HOSTTRIPLE into something more meaningful, like what I proposed
>> LLVM_DEFAULT_TARGET.
>>
> The second makes sure that everything is consistent from the start, no

I fail to see how 2. will be consistent "from the start", when we will be
calling HOST the value in $target, but anyways...

> chance of forgetting something in the middle. So yes, (2) is fine with
> me, but the "rename to something meaningful" part has to be part of a
> larger API change, since the host vs target misnaming is very sticky.

That's fine with me, as I consider that the two paths are equivalent, leading
to the same state.  It will take me quite some time to come with patches for
the second option.  Eric, do you want to wait for another week or so until I
get the new set of patches out?  Or do you want to go with the first option?
It's your take Eric, as you are the maintainer here.

Also, is there consensus that changing "host" into "target" all over the place
(of course, only where it is meaningful to change) is the right thing to do?

Thanks,
Sebastian
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

From nicholas at mxc.ca  Fri Oct 28 00:29:47 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Fri, 28 Oct 2011 05:29:47 -0000
Subject: [llvm-commits] [llvm] r143186 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/DIE.cpp lib/CodeGen/AsmPrinter/DIE.h
 lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
 test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
 test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
 test/CodeGen/X86/2010-08-10-DbgConstant.ll
 test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
 test/CodeGen/X86/dbg-value-inlined-parameter.ll
 test/CodeGen/X86/dbg-value-location.ll
 test/DebugInfo/2011-09-26-GlobalVarContext.ll test/DebugInfo/stringpool.ll
Message-ID: <20111028052947.7E0F63128060@llvm.org>

Author: nicholas
Date: Fri Oct 28 00:29:47 2011
New Revision: 143186

URL: http://llvm.org/viewvc/llvm-project?rev=143186&view=rev
Log:
Always use the string pool, even when it makes the .o larger. This may help
tools that read the debug info in the .o files by making the DIE sizes more
consistent.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
    llvm/trunk/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
    llvm/trunk/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
    llvm/trunk/test/CodeGen/X86/2010-08-10-DbgConstant.ll
    llvm/trunk/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
    llvm/trunk/test/CodeGen/X86/dbg-value-inlined-parameter.ll
    llvm/trunk/test/CodeGen/X86/dbg-value-location.ll
    llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll
    llvm/trunk/test/DebugInfo/stringpool.ll

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp?rev=143186&r1=143185&r2=143186&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp Fri Oct 28 00:29:47 2011
@@ -236,24 +236,6 @@
 #endif
 
 //===----------------------------------------------------------------------===//
-// DIEString Implementation
-//===----------------------------------------------------------------------===//
-
-/// EmitValue - Emit string value.
-///
-void DIEString::EmitValue(AsmPrinter *AP, unsigned Form) const {
-  AP->OutStreamer.EmitBytes(Str, /*addrspace*/0);
-  // Emit nul terminator.
-  AP->OutStreamer.EmitIntValue(0, 1, /*addrspace*/0);
-}
-
-#ifndef NDEBUG
-void DIEString::print(raw_ostream &O) {
-  O << "Str: \"" << Str << "\"";
-}
-#endif
-
-//===----------------------------------------------------------------------===//
 // DIELabel Implementation
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h?rev=143186&r1=143185&r2=143186&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.h Fri Oct 28 00:29:47 2011
@@ -275,33 +275,6 @@
   };
 
   //===--------------------------------------------------------------------===//
-  /// DIEString - A string value DIE. This DIE keeps string reference only.
-  ///
-  class DIEString : public DIEValue {
-    const StringRef Str;
-  public:
-    explicit DIEString(const StringRef S) : DIEValue(isString), Str(S) {}
-
-    /// EmitValue - Emit string value.
-    ///
-    virtual void EmitValue(AsmPrinter *AP, unsigned Form) const;
-
-    /// SizeOf - Determine size of string value in bytes.
-    ///
-    virtual unsigned SizeOf(AsmPrinter *AP, unsigned /*Form*/) const {
-      return Str.size() + sizeof(char); // sizeof('\0');
-    }
-
-    // Implement isa/cast/dyncast.
-    static bool classof(const DIEString *) { return true; }
-    static bool classof(const DIEValue *S) { return S->getType() == isString; }
-
-#ifndef NDEBUG
-    virtual void print(raw_ostream &O);
-#endif
-  };
-
-  //===--------------------------------------------------------------------===//
   /// DIELabel - A label expression DIE.
   //
   class DIELabel : public DIEValue {

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=143186&r1=143185&r2=143186&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Fri Oct 28 00:29:47 2011
@@ -67,23 +67,19 @@
   Die->addValue(Attribute, Form, Value);
 }
 
-/// addString - Add a string attribute data and value. DIEString only
-/// keeps string reference.
+/// addString - Add a string attribute data and value. We always emit a
+/// reference to the string pool instead of immediate strings so that DIEs have
+/// more predictable sizes.
 void CompileUnit::addString(DIE *Die, unsigned Attribute, StringRef String) {
-  if (String.size() > 3) {
-    MCSymbol *Symb = DD->getStringPoolEntry(String);
-    DIEValue *Value;
-    if (Asm->needsRelocationsForDwarfStringPool())
-      Value = new (DIEValueAllocator) DIELabel(Symb);
-    else {
-      MCSymbol *StringPool = DD->getStringPool();
-      Value = new (DIEValueAllocator) DIEDelta(Symb, StringPool);
-    }
-    Die->addValue(Attribute, dwarf::DW_FORM_strp, Value);
-  } else {
-    DIEValue *Value = new (DIEValueAllocator) DIEString(String);
-    Die->addValue(Attribute, dwarf::DW_FORM_string, Value);
+  MCSymbol *Symb = DD->getStringPoolEntry(String);
+  DIEValue *Value;
+  if (Asm->needsRelocationsForDwarfStringPool())
+    Value = new (DIEValueAllocator) DIELabel(Symb);
+  else {
+    MCSymbol *StringPool = DD->getStringPool();
+    Value = new (DIEValueAllocator) DIEDelta(Symb, StringPool);
   }
+  Die->addValue(Attribute, dwarf::DW_FORM_strp, Value);
 }
 
 /// addLabel - Add a Dwarf label attribute data and value.

Modified: llvm/trunk/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll?rev=143186&r1=143185&r2=143186&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll Fri Oct 28 00:29:47 2011
@@ -17,8 +17,7 @@
 ; DW_OP_constu
 ; offset
 
-;CHECK:        .ascii   "x2"                   @ DW_AT_name
-;CHECK-NEXT:        .byte   0
+;CHECK: .long Lset6
 ;CHECK-NEXT:        @ DW_AT_type
 ;CHECK-NEXT:        @ DW_AT_decl_file
 ;CHECK-NEXT:        @ DW_AT_decl_line

Modified: llvm/trunk/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll?rev=143186&r1=143185&r2=143186&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll Fri Oct 28 00:29:47 2011
@@ -8,8 +8,7 @@
 ; DW_OP_constu
 ; offset
 
-;CHECK:        .ascii   "x2"                   @ DW_AT_name
-;CHECK-NEXT:        .byte   0
+;CHECK: .long Lset33
 ;CHECK-NEXT:        @ DW_AT_type
 ;CHECK-NEXT:        @ DW_AT_decl_file
 ;CHECK-NEXT:        @ DW_AT_decl_line

Modified: llvm/trunk/test/CodeGen/X86/2010-08-10-DbgConstant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-08-10-DbgConstant.ll?rev=143186&r1=143185&r2=143186&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-08-10-DbgConstant.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-08-10-DbgConstant.ll Fri Oct 28 00:29:47 2011
@@ -1,6 +1,6 @@
 ; RUN: llc  -march=x86 -O0 < %s | FileCheck %s
 ; CHECK: DW_TAG_constant
-; CHECK-NEXT: ascii	 "ro"                   #{{#?}} DW_AT_name
+; CHECK-NEXT: .long .Lstring3 #{{#?}} DW_AT_name
 
 define void @foo() nounwind ssp {
 entry:

Modified: llvm/trunk/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll?rev=143186&r1=143185&r2=143186&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll Fri Oct 28 00:29:47 2011
@@ -4,8 +4,7 @@
 target triple = "x86_64-apple-darwin10.0.0"
 
 ; Check debug info for variable z_s
-;CHECK:       .ascii   "z_s"                  ## DW_AT_name
-;CHECK-NEXT:  .byte   0
+;CHECK: .long Lset13
 ;CHECK-NEXT:  ## DW_AT_decl_file
 ;CHECK-NEXT:  ## DW_AT_decl_line
 ;CHECK-NEXT:  ## DW_AT_type

Modified: llvm/trunk/test/CodeGen/X86/dbg-value-inlined-parameter.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-inlined-parameter.ll?rev=143186&r1=143185&r2=143186&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-value-inlined-parameter.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dbg-value-inlined-parameter.ll Fri Oct 28 00:29:47 2011
@@ -8,7 +8,7 @@
 ;CHECK-NEXT: DW_AT_call_file
 ;CHECK-NEXT: DW_AT_call_line
 ;CHECK-NEXT: DW_TAG_formal_parameter
-;CHECK-NEXT: .ascii   "sp"                   ## DW_AT_name
+;CHECK-NEXT: Lstring11-Lsection_str ## DW_AT_name
 
 %struct.S1 = type { float*, i32 }
 

Modified: llvm/trunk/test/CodeGen/X86/dbg-value-location.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-location.ll?rev=143186&r1=143185&r2=143186&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-value-location.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dbg-value-location.ll Fri Oct 28 00:29:47 2011
@@ -4,8 +4,7 @@
 target triple = "x86_64-apple-darwin10.0.0"
 ;Radar 8950491
 
-;CHECK:        .ascii   "var"                  ## DW_AT_name
-;CHECK-NEXT:        .byte   0
+;CHECK: .long Lset5
 ;CHECK-NEXT:        ## DW_AT_decl_file
 ;CHECK-NEXT:        ## DW_AT_decl_line
 ;CHECK-NEXT:        ## DW_AT_type

Modified: llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll?rev=143186&r1=143185&r2=143186&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll (original)
+++ llvm/trunk/test/DebugInfo/2011-09-26-GlobalVarContext.ll Fri Oct 28 00:29:47 2011
@@ -1,4 +1,4 @@
-; RUN: llc -asm-verbose %s -o - | FileCheck %s
+; RUN: llc -mtriple=x86_64-pc-linux-gnu -asm-verbose %s -o - | FileCheck %s
 
 ; ModuleID = 'test.c'
 
@@ -38,10 +38,10 @@
 !18 = metadata !{i32 4, i32 23, metadata !16, null}
 !19 = metadata !{i32 5, i32 5, metadata !16, null}
 
-; CHECK: .ascii	 "GLB"
+; CHECK: .long .Lstring3
 ; CHECK: .byte	1
 ; CHECK: .byte	1
 
-; CHECK: .ascii	 "LOC"
+; CHECK: .long .Lstring6
 ; CHECK: .byte	1
 ; CHECK: .byte	4

Modified: llvm/trunk/test/DebugInfo/stringpool.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/stringpool.ll?rev=143186&r1=143185&r2=143186&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/stringpool.ll (original)
+++ llvm/trunk/test/DebugInfo/stringpool.ll Fri Oct 28 00:29:47 2011
@@ -1,54 +1,44 @@
-; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=LINUX
-; RUN: llc -O0 -mtriple=x86_64-darwin < %s | FileCheck %s --check-prefix=DARWIN
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-linux-gnu"
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=LINUX
+; RUN: llc -mtriple=x86_64-darwin < %s | FileCheck %s --check-prefix=DARWIN
 
- at x = common global i32 0, align 4
- at yyyyyyyy = common global i32 0, align 4
+ at yyyy = common global i32 0, align 4
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"hello.c", metadata !"/home/nlewycky", metadata !"clang version 3.1 (trunk 143048)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"z.c", metadata !"/home/nicholas", metadata !"clang version 3.1 (trunk 143009)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{metadata !2}
 !2 = metadata !{i32 0}
 !3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5, metadata !8}
-!5 = metadata !{i32 720948, i32 0, null, metadata !"x", metadata !"x", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, i32* @x} ; [ DW_TAG_variable ]
-!6 = metadata !{i32 720937, metadata !"hello.c", metadata !"/home/nlewycky", null} ; [ DW_TAG_file_type ]
+!4 = metadata !{metadata !5}
+!5 = metadata !{i32 720948, i32 0, null, metadata !"yyyy", metadata !"yyyy", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, i32* @yyyy} ; [ DW_TAG_variable ]
+!6 = metadata !{i32 720937, metadata !"z.c", metadata !"/home/nicholas", null} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!8 = metadata !{i32 720948, i32 0, null, metadata !"yyyyyyyy", metadata !"yyyyyyyy", metadata !"", metadata !6, i32 2, metadata !7, i32 0, i32 1, i32* @yyyyyyyy} ; [ DW_TAG_variable ]
 
-; 120 is ASCII 'x'. Verify that we use it directly as its name and don't emit
-; a reference to the string pool.
-; LINUX:        .byte   120                     # DW_AT_name
-; DARWIN:       .byte   120                     ## DW_AT_name
-
-; Verify that we refer to 'yyyyyyyy' with a relocation.
-; LINUX:      .long   .Lstring{{[0-9]+}}      # DW_AT_name
+; Verify that we refer to 'yyyy' with a relocation.
+; LINUX:      .long   .Lstring3               # DW_AT_name
 ; LINUX-NEXT: .long   39                      # DW_AT_type
 ; LINUX-NEXT: .byte   1                       # DW_AT_external
 ; LINUX-NEXT: .byte   1                       # DW_AT_decl_file
-; LINUX-NEXT: .byte   2                       # DW_AT_decl_line
+; LINUX-NEXT: .byte   1                       # DW_AT_decl_line
 ; LINUX-NEXT: .byte   9                       # DW_AT_location
 ; LINUX-NEXT: .byte   3
-; LINUX-NEXT: .quad   yyyyyyyy
+; LINUX-NEXT: .quad   yyyy
 
-; Verify that we refer to 'yyyyyyyy' without a relocation.
-; DARWIN: Lset[[N:[0-9]+]] = Lstring{{[0-9]+}}-Lsection_str   ## DW_AT_name
-; DARWIN-NEXT:        .long   Lset[[N]]
+; Verify that we refer to 'yyyy' without a relocation.
+; DARWIN: Lset5 = Lstring3-Lsection_str               ## DW_AT_name
+; DARWIN-NEXT:        .long   Lset5
 ; DARWIN-NEXT:        .long   39                      ## DW_AT_type
 ; DARWIN-NEXT:        .byte   1                       ## DW_AT_external
 ; DARWIN-NEXT:        .byte   1                       ## DW_AT_decl_file
-; DARWIN-NEXT:        .byte   2                       ## DW_AT_decl_line
+; DARWIN-NEXT:        .byte   1                       ## DW_AT_decl_line
 ; DARWIN-NEXT:        .byte   9                       ## DW_AT_location
 ; DARWIN-NEXT:        .byte   3
-; DARWIN-NEXT:        .quad   _yyyyyyyy
-
+; DARWIN-NEXT:        .quad   _yyyy
 
-; Verify that "yyyyyyyy" ended up in the stringpool.
+; Verify that "yyyy" ended up in the stringpool.
 ; LINUX: .section .debug_str,"MS", at progbits,1
 ; LINUX-NOT: .section
-; LINUX: yyyyyyyy
+; LINUX: yyyy
 ; DARWIN: .section __DWARF,__debug_str,regular,debug
 ; DARWIN-NOT: .section
-; DARWIN: yyyyyyyy
+; DARWIN: yyyy



From nadav.rotem at intel.com  Fri Oct 28 02:04:40 2011
From: nadav.rotem at intel.com (Rotem, Nadav)
Date: Fri, 28 Oct 2011 09:04:40 +0200
Subject: [llvm-commits] [llvm] r143177 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ lib/Target/XCore/
 test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb/
 test/CodeGen/X86/
In-Reply-To: <99EF7A0F-DA58-4CBB-9256-1F1DB920F4F5@apple.com>
References: <20111028012933.AFA263128060@llvm.org>
	<CAJdarcGxpPGtCEtLsoXFKzqxbRt5FCX_jXH9YrfnefDFAkYzQA@mail.gmail.com>
	<99EF7A0F-DA58-4CBB-9256-1F1DB920F4F5@apple.com>
Message-ID: <6594DDFF12B03D4E89690887C248699402A6205B38@hasmsx504.ger.corp.intel.com>

I added the discussed code when I worked on the type-legalizer because I legalized SIGN_EXTEND_INREG incorrectly. I think that this code is redundant now and can be removed. 

Thanks,
Nadav

-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Dan Gohman
Sent: Friday, October 28, 2011 04:02
To: Eli Friedman
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [llvm] r143177 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ lib/Target/XCore/ test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb/ test/CodeGen/X86/


On Oct 27, 2011, at 6:56 PM, Eli Friedman wrote:

> On Thu, Oct 27, 2011 at 6:29 PM, Dan Gohman <gohman at apple.com> wrote:
>> @@ -3628,6 +3351,35 @@
>>     Results.push_back(Tmp1);
>>     break;
>>   }
>> +  case ISD::BUILD_VECTOR:
>> +    Results.push_back(ExpandBUILD_VECTOR(Node));
>> +    break;
>> +  case ISD::SRA:
>> +  case ISD::SRL:
>> +  case ISD::SHL: {
>> +    // Scalarize vector SRA/SRL/SHL.
>> +    EVT VT = Node->getValueType(0);
>> +    assert(VT.isVector() && "Unable to legalize non-vector shift");
>> +    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
>> +    unsigned NumElem = VT.getVectorNumElements();
>> +
>> +    SmallVector<SDValue, 8> Scalars;
>> +    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
>> +      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
>> +                               VT.getScalarType(),
>> +                               Node->getOperand(0), DAG.getIntPtrConstant(Idx));
>> +      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
>> +                               VT.getScalarType(),
>> +                               Node->getOperand(1), DAG.getIntPtrConstant(Idx));
>> +      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
>> +                                    VT.getScalarType(), Ex, Sh));
>> +    }
>> +    SDValue Result =
>> +      DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
>> +                  &Scalars[0], Scalars.size());
>> +    DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
>> +    break;
>> +  }
> 
> We ought to be scalarizing vector shifts in LegalizeVectorOps; is
> there some case where that is not sufficient?

That code predates this patch. It may be a leftover from pre-LegalizeTypes days.

Dan

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From pichet2000 at gmail.com  Fri Oct 28 02:46:09 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Fri, 28 Oct 2011 03:46:09 -0400
Subject: [llvm-commits] [llvm] r143186 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/DIE.cpp lib/CodeGen/AsmPrinter/DIE.h
 lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
 test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
 test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
Message-ID: <CAH_MvcWJPBu1bB=Kc3snKNk9P8sSy+jyBw2h3bcYd5-_g-Kd7A@mail.gmail.com>

On Fri, Oct 28, 2011 at 1:29 AM, Nick Lewycky <nicholas at mxc.ca> wrote:
> Author: nicholas
> Date: Fri Oct 28 00:29:47 2011
> New Revision: 143186
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143186&view=rev
> Log:
> Always use the string pool, even when it makes the .o larger. This may help
> tools that read the debug info in the .o files by making the DIE sizes more
> consistent.

This fail on MSVC 2010:

1>  FAIL: LLVM :: CodeGen/X86/2010-08-10-DbgConstant.ll (6053 of 9480)
1>  ******************** TEST 'LLVM ::
CodeGen/X86/2010-08-10-DbgConstant.ll' FAILED ********************
1>  Script:
1>  --
1>  C:/dev/llvm/llvm_trunk2/bin/Release/llc.EXE  -march=x86 -O0 <
C:/dev/llvm/llvm_trunk2/test/CodeGen/X86/2010-08-10-DbgConstant.ll |
C:/dev/llvm/llvm_trunk2/bin/Release/FileCheck.EXE
C:/dev/llvm/llvm_trunk2/test/CodeGen/X86/2010-08-10-DbgConstant.ll
1>  --
1>  Exit Code: 1
1>  Command Output (stdout):
1>  --
1>  Command 0: "C:/dev/llvm/llvm_trunk2/bin/Release/llc.EXE" "-march=x86" "-O0"
1>  Command 0 Result: 0
1>  Command 0 Output:
1>
1>
1>  Command 0 Stderr:
1>
1>
1>  Command 1: "C:/dev/llvm/llvm_trunk2/bin/Release/FileCheck.EXE"
"C:/dev/llvm/llvm_trunk2/test/CodeGen/X86/2010-08-10-DbgConstant.ll"
1>  Command 1 Result: 1
1>  Command 1 Output:
1>
1>
1>  Command 1 Stderr:
1>  C:/dev/llvm/llvm_trunk2/test/CodeGen/X86/2010-08-10-DbgConstant.ll:3:15:
error: expected string not found in input
1>  ; CHECK-NEXT: .long .Lstring3 #{{#?}} DW_AT_name
1>                ^
1>  <stdin>:70:2: note: scanning from here
1>   .long Lstring3 # DW_AT_name
1>   ^
1>
1>
1>  --
1>
1>  ********************
1>
1>  Testing Time: 187.73s
1>  ********************
1>  Failing Tests (1):
1>      LLVM :: CodeGen/X86/2010-08-10-DbgConstant.ll

From monping at apple.com  Fri Oct 28 02:54:38 2011
From: monping at apple.com (Mon Ping Wang)
Date: Fri, 28 Oct 2011 00:54:38 -0700
Subject: [llvm-commits] [llvm] r142992 - in /llvm/trunk:
 lib/VMCore/Instructions.cpp test/Bitcode/shuffle.ll
In-Reply-To: <4EA7B86C.5090103@free.fr>
References: <20111026003448.41B96312800A@llvm.org> <4EA7B86C.5090103@free.fr>
Message-ID: <68BC306E-DC64-4EA8-9215-524F8D36A434@apple.com>


The bit code reader tries to look up the constant based on an index.  If it is hasn't encountered the constant yet, it places a placeholder and fixes it up later.  This happens rarely and allows the reader to run in one pass.  Updating the verifier is a good idea.  I'll do that.

-- Mon Ping

On Oct 26, 2011, at 12:36 AM, Duncan Sands wrote:

> Hi,
> 
>> The bitcode reader can create an shuffle with a place holder mask which it will
>> fix up later. For this special case, allow such a mask to be considered valid.
>> <rdar://problem/8622574>
> 
> why does it create a placeholder - is it really needed?  I mean, I don't see any
> other special casing of UserOp in Instructions.cpp, so it seems that no other
> instructions do this - in which case what makes shufflevector different?  Also,
> if you do follow this route, maybe you can have the verifier check that the
> mask is really valid (no UserOp1).  This would catch bugs in which the
> placeholder leaked out of the bitcode reader somehow.
> 
> Ciao, Duncan.
> 
>> 
>> Added:
>>     llvm/trunk/test/Bitcode/shuffle.ll
>> Modified:
>>     llvm/trunk/lib/VMCore/Instructions.cpp
>> 
>> Modified: llvm/trunk/lib/VMCore/Instructions.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=142992&r1=142991&r2=142992&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/VMCore/Instructions.cpp (original)
>> +++ llvm/trunk/lib/VMCore/Instructions.cpp Tue Oct 25 19:34:48 2011
>> @@ -1576,10 +1576,17 @@
>>          return false;
>>        }
>>      }
>> -  }
>> -  else if (!isa<UndefValue>(Mask)&&  !isa<ConstantAggregateZero>(Mask))
>> +  } else if (!isa<UndefValue>(Mask)&&  !isa<ConstantAggregateZero>(Mask)) {
>> +    // The bitcode reader can create a place holder for a forward reference
>> +    // used as the shuffle mask. When this occurs, the shuffle mask will
>> +    // fall into this case and fail. To avoid this error, do this bit of
>> +    // ugliness to allow such a mask pass.
>> +    if (const ConstantExpr* CE = dyn_cast<ConstantExpr>(Mask)) {
>> +      if (CE->getOpcode() == Instruction::UserOp1)
>> +        return true;
>> +    }
>>      return false;
>> -
>> +  }
>>    return true;
>>  }
>> 
>> 
>> Added: llvm/trunk/test/Bitcode/shuffle.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/shuffle.ll?rev=142992&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/Bitcode/shuffle.ll (added)
>> +++ llvm/trunk/test/Bitcode/shuffle.ll Tue Oct 25 19:34:48 2011
>> @@ -0,0 +1,31 @@
>> +; RUN: llvm-as<  %s | llvm-dis
>> +
>> +;<rdar://problem/8622574>
>> +; tests the bitcodereader can handle the case where the reader will initially
>> +; create shuffle with a place holder mask.
>> +
>> +
>> +define<4 x float>  @test(<2 x double>  %d2)  {
>> +entry:
>> +  %call20.i = tail call<4 x float>  @cmp(<2 x double>  %d2,
>> +<2 x double>  bitcast (
>> +<4 x float>  shufflevector (
>> +<3 x float>  shufflevector (
>> +<4 x float>  shufflevector (
>> +<3 x float>  bitcast (
>> +                                                  i96 trunc (
>> +                                                    i128 bitcast (<2 x double>  bitcast (
>> +<4 x i32>  <i32 0, i32 0, i32 0, i32 undef>  to<2 x double>)
>> +                                                    to i128) to i96)
>> +                                                  to<3 x float>),
>> +<3 x float>  undef,
>> +<4 x i32>  <i32 0, i32 1, i32 2, i32 undef>),
>> +<4 x float>  undef,
>> +<3 x i32>  <i32 0, i32 1, i32 2>),
>> +<3 x float>  undef,
>> +<4 x i32>  <i32 0, i32 1, i32 2, i32 undef>)
>> +                                          to<2 x double>))
>> +  ret<4 x float>  %call20.i
>> +}
>> +
>> +declare<4 x float>  @cmp(<2 x double>,<2 x double>)
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From baldrick at free.fr  Fri Oct 28 04:55:57 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 28 Oct 2011 09:55:57 -0000
Subject: [llvm-commits] [llvm] r143188 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ lib/Target/XCore/
 test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb/
 test/CodeGen/X86/
Message-ID: <20111028095558.6A7E8312800A@llvm.org>

Author: baldrick
Date: Fri Oct 28 04:55:57 2011
New Revision: 143188

URL: http://llvm.org/viewvc/llvm-project?rev=143188&view=rev
Log:
Speculatively disable Dan's commits 143177 and 143179 to see if
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.

Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.

Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.

Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.

This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.

Delete #if 0 code accidentally left in.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
    llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
    llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll
    llvm/trunk/test/CodeGen/CellSPU/nand.ll
    llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
    llvm/trunk/test/CodeGen/CellSPU/select_bits.ll
    llvm/trunk/test/CodeGen/CellSPU/struct_1.ll
    llvm/trunk/test/CodeGen/Mips/cprestore.ll
    llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
    llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
    llvm/trunk/test/CodeGen/X86/sse3.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 28 04:55:57 2011
@@ -46,18 +46,37 @@
 /// will attempt merge setcc and brc instructions into brcc's.
 ///
 namespace {
-class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
+class SelectionDAGLegalize {
   const TargetMachine &TM;
   const TargetLowering &TLI;
   SelectionDAG &DAG;
 
-  /// LegalizePosition - The iterator for walking through the node list.
-  SelectionDAG::allnodes_iterator LegalizePosition;
+  // Libcall insertion helpers.
 
-  /// LegalizedNodes - The set of nodes which have already been legalized.
-  SmallPtrSet<SDNode *, 16> LegalizedNodes;
+  /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
+  /// legalized.  We use this to ensure that calls are properly serialized
+  /// against each other, including inserted libcalls.
+  SDValue LastCALLSEQ_END;
+
+  /// IsLegalizingCall - This member is used *only* for purposes of providing
+  /// helpful assertions that a libcall isn't created while another call is
+  /// being legalized (which could lead to non-serialized call sequences).
+  bool IsLegalizingCall;
+
+  /// LegalizedNodes - For nodes that are of legal width, and that have more
+  /// than one use, this map indicates what regularized operand to use.  This
+  /// allows us to avoid legalizing the same thing more than once.
+  DenseMap<SDValue, SDValue> LegalizedNodes;
+
+  void AddLegalizedOperand(SDValue From, SDValue To) {
+    LegalizedNodes.insert(std::make_pair(From, To));
+    // If someone requests legalization of the new node, return itself.
+    if (From != To)
+      LegalizedNodes.insert(std::make_pair(To, To));
 
-  // Libcall insertion helpers.
+    // Transfer SDDbgValues.
+    DAG.TransferDbgValues(From, To);
+  }
 
 public:
   explicit SelectionDAGLegalize(SelectionDAG &DAG);
@@ -65,8 +84,9 @@
   void LegalizeDAG();
 
 private:
-  /// LegalizeOp - Legalizes the given operation.
-  void LegalizeOp(SDNode *Node);
+  /// LegalizeOp - Return a legal replacement for the given operation, with
+  /// all legal operands.
+  SDValue LegalizeOp(SDValue O);
 
   SDValue OptimizeFloatStore(StoreSDNode *ST);
 
@@ -87,6 +107,9 @@
                                      SDValue N1, SDValue N2,
                                      SmallVectorImpl<int> &Mask) const;
 
+  bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
+                                    SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
+
   void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
                              DebugLoc dl);
 
@@ -127,21 +150,10 @@
   SDValue ExpandInsertToVectorThroughStack(SDValue Op);
   SDValue ExpandVectorBuildThroughStack(SDNode* Node);
 
-  SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
-
   std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
 
-  void ExpandNode(SDNode *Node);
-  void PromoteNode(SDNode *Node);
-
-  // DAGUpdateListener implementation.
-  virtual void NodeDeleted(SDNode *N, SDNode *E) {
-    LegalizedNodes.erase(N);
-    if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
-      ++LegalizePosition;
-  }
-
-  virtual void NodeUpdated(SDNode *N) {}
+  void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
+  void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
 };
 }
 
@@ -183,37 +195,145 @@
 }
 
 void SelectionDAGLegalize::LegalizeDAG() {
+  LastCALLSEQ_END = DAG.getEntryNode();
+  IsLegalizingCall = false;
+
+  // The legalize process is inherently a bottom-up recursive process (users
+  // legalize their uses before themselves).  Given infinite stack space, we
+  // could just start legalizing on the root and traverse the whole graph.  In
+  // practice however, this causes us to run out of stack space on large basic
+  // blocks.  To avoid this problem, compute an ordering of the nodes where each
+  // node is only legalized after all of its operands are legalized.
   DAG.AssignTopologicalOrder();
+  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
+       E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
+    LegalizeOp(SDValue(I, 0));
+
+  // Finally, it's possible the root changed.  Get the new root.
+  SDValue OldRoot = DAG.getRoot();
+  assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
+  DAG.setRoot(LegalizedNodes[OldRoot]);
 
-  // Visit all the nodes. We start in topological order, so that we see
-  // nodes with their original operands intact. Legalization can produce
-  // new nodes which may themselves need to be legalized. Iterate until all
-  // nodes have been legalized.
-  for (;;) {
-    bool AnyLegalized = false;
-    for (LegalizePosition = DAG.allnodes_end();
-         LegalizePosition != DAG.allnodes_begin(); ) {
-      --LegalizePosition;
-
-      SDNode *N = LegalizePosition;
-      if (LegalizedNodes.insert(N)) {
-        AnyLegalized = true;
-        LegalizeOp(N);
-      }
+  LegalizedNodes.clear();
+
+  // Remove dead nodes now.
+  DAG.RemoveDeadNodes();
+}
+
+
+/// FindCallEndFromCallStart - Given a chained node that is part of a call
+/// sequence, find the CALLSEQ_END node that terminates the call sequence.
+static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
+  // Nested CALLSEQ_START/END constructs aren't yet legal,
+  // but we can DTRT and handle them correctly here.
+  if (Node->getOpcode() == ISD::CALLSEQ_START)
+    depth++;
+  else if (Node->getOpcode() == ISD::CALLSEQ_END) {
+    depth--;
+    if (depth == 0)
+      return Node;
+  }
+  if (Node->use_empty())
+    return 0;   // No CallSeqEnd
+
+  // The chain is usually at the end.
+  SDValue TheChain(Node, Node->getNumValues()-1);
+  if (TheChain.getValueType() != MVT::Other) {
+    // Sometimes it's at the beginning.
+    TheChain = SDValue(Node, 0);
+    if (TheChain.getValueType() != MVT::Other) {
+      // Otherwise, hunt for it.
+      for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
+        if (Node->getValueType(i) == MVT::Other) {
+          TheChain = SDValue(Node, i);
+          break;
+        }
+
+      // Otherwise, we walked into a node without a chain.
+      if (TheChain.getValueType() != MVT::Other)
+        return 0;
     }
-    if (!AnyLegalized)
+  }
+
+  for (SDNode::use_iterator UI = Node->use_begin(),
+       E = Node->use_end(); UI != E; ++UI) {
+
+    // Make sure to only follow users of our token chain.
+    SDNode *User = *UI;
+    for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
+      if (User->getOperand(i) == TheChain)
+        if (SDNode *Result = FindCallEndFromCallStart(User, depth))
+          return Result;
+  }
+  return 0;
+}
+
+/// FindCallStartFromCallEnd - Given a chained node that is part of a call
+/// sequence, find the CALLSEQ_START node that initiates the call sequence.
+static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
+  int nested = 0;
+  assert(Node && "Didn't find callseq_start for a call??");
+  while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
+    Node = Node->getOperand(0).getNode();
+    assert(Node->getOperand(0).getValueType() == MVT::Other &&
+           "Node doesn't have a token chain argument!");
+    switch (Node->getOpcode()) {
+    default:
+      break;
+    case ISD::CALLSEQ_START:
+      if (!nested)
+        return Node;
+      nested--;
+      break;
+    case ISD::CALLSEQ_END:
+      nested++;
       break;
+    }
+  }
+  return 0;
+}
 
+/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
+/// see if any uses can reach Dest.  If no dest operands can get to dest,
+/// legalize them, legalize ourself, and return false, otherwise, return true.
+///
+/// Keep track of the nodes we fine that actually do lead to Dest in
+/// NodesLeadingTo.  This avoids retraversing them exponential number of times.
+///
+bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
+                                     SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
+  if (N == Dest) return true;  // N certainly leads to Dest :)
+
+  // If we've already processed this node and it does lead to Dest, there is no
+  // need to reprocess it.
+  if (NodesLeadingTo.count(N)) return true;
+
+  // If the first result of this node has been already legalized, then it cannot
+  // reach N.
+  if (LegalizedNodes.count(SDValue(N, 0))) return false;
+
+  // Okay, this node has not already been legalized.  Check and legalize all
+  // operands.  If none lead to Dest, then we can legalize this node.
+  bool OperandsLeadToDest = false;
+  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+    OperandsLeadToDest |=     // If an operand leads to Dest, so do we.
+      LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
+                                   NodesLeadingTo);
+
+  if (OperandsLeadToDest) {
+    NodesLeadingTo.insert(N);
+    return true;
   }
 
-  // Remove dead nodes now.
-  DAG.RemoveDeadNodes();
+  // Okay, this node looks safe, legalize it and return false.
+  LegalizeOp(SDValue(N, 0));
+  return false;
 }
 
 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
 /// a load from the constant pool.
-SDValue
-SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
+static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
+                                SelectionDAG &DAG, const TargetLowering &TLI) {
   bool Extend = false;
   DebugLoc dl = CFP->getDebugLoc();
 
@@ -249,25 +369,20 @@
 
   SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
   unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
-  if (Extend) {
-    SDValue Result =
-      DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
-                     DAG.getEntryNode(),
-                     CPIdx, MachinePointerInfo::getConstantPool(),
-                     VT, false, false, Alignment);
-    return Result;
-  }
-  SDValue Result =
-    DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
-                MachinePointerInfo::getConstantPool(), false, false,
-                Alignment);
-  return Result;
+  if (Extend)
+    return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
+                          DAG.getEntryNode(),
+                          CPIdx, MachinePointerInfo::getConstantPool(),
+                          VT, false, false, Alignment);
+  return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
+                     MachinePointerInfo::getConstantPool(), false, false,
+                     Alignment);
 }
 
 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
-static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
-                                 const TargetLowering &TLI,
-                                 SelectionDAG::DAGUpdateListener *DUL) {
+static
+SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
+                             const TargetLowering &TLI) {
   SDValue Chain = ST->getChain();
   SDValue Ptr = ST->getBasePtr();
   SDValue Val = ST->getValue();
@@ -282,10 +397,8 @@
       // same size, then a (misaligned) int store.
       // FIXME: Does not handle truncating floating point stores!
       SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
-      Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
-                           ST->isVolatile(), ST->isNonTemporal(), Alignment);
-      DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
-      return;
+      return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
+                          ST->isVolatile(), ST->isNonTemporal(), Alignment);
     }
     // Do a (aligned) store to a stack slot, then copy from the stack slot
     // to the final destination using (unaligned) integer loads and stores.
@@ -345,11 +458,8 @@
                                        ST->isNonTemporal(),
                                        MinAlign(ST->getAlignment(), Offset)));
     // The order of the stores doesn't matter - say it with a TokenFactor.
-    SDValue Result =
-      DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
-                  Stores.size());
-    DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
-    return;
+    return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
+                       Stores.size());
   }
   assert(ST->getMemoryVT().isInteger() &&
          !ST->getMemoryVT().isVector() &&
@@ -378,16 +488,13 @@
                              NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
                              Alignment);
 
-  SDValue Result =
-    DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
-  DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
+  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
 }
 
 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
-static void
-ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
-                    const TargetLowering &TLI,
-                    SDValue &ValResult, SDValue &ChainResult) {
+static
+SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
+                            const TargetLowering &TLI) {
   SDValue Chain = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
   EVT VT = LD->getValueType(0);
@@ -405,9 +512,8 @@
       if (VT.isFloatingPoint() && LoadedVT != VT)
         Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
 
-      ValResult = Result;
-      ChainResult = Chain;
-      return;
+      SDValue Ops[] = { Result, Chain };
+      return DAG.getMergeValues(Ops, 2, dl);
     }
 
     // Copy the value to a (aligned) stack slot using (unaligned) integer
@@ -466,9 +572,8 @@
                           MachinePointerInfo(), LoadedVT, false, false, 0);
 
     // Callers expect a MERGE_VALUES node.
-    ValResult = Load;
-    ChainResult = TF;
-    return;
+    SDValue Ops[] = { Load, TF };
+    return DAG.getMergeValues(Ops, 2, dl);
   }
   assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
          "Unaligned load of unsupported type.");
@@ -521,8 +626,8 @@
   SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                              Hi.getValue(1));
 
-  ValResult = Result;
-  ChainResult = TF;
+  SDValue Ops[] = { Result, TF };
+  return DAG.getMergeValues(Ops, 2, dl);
 }
 
 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
@@ -658,10 +763,11 @@
 
 /// LegalizeOp - Return a legal replacement for the given operation, with
 /// all legal operands.
-void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
-  if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
-    return;
+SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
+  if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
+    return Op;
 
+  SDNode *Node = Op.getNode();
   DebugLoc dl = Node->getDebugLoc();
 
   for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
@@ -676,7 +782,13 @@
             Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
            "Unexpected illegal type!");
 
+  // Note that LegalizeOp may be reentered even from single-use nodes, which
+  // means that we always must cache transformed nodes.
+  DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
+  if (I != LegalizedNodes.end()) return I->second;
+
   SDValue Tmp1, Tmp2, Tmp3, Tmp4;
+  SDValue Result = Op;
   bool isCustom = false;
 
   // Figure out the correct action; the way to query this varies by opcode
@@ -770,6 +882,17 @@
     if (Action == TargetLowering::Legal)
       Action = TargetLowering::Custom;
     break;
+  case ISD::BUILD_VECTOR:
+    // A weird case: legalization for BUILD_VECTOR never legalizes the
+    // operands!
+    // FIXME: This really sucks... changing it isn't semantically incorrect,
+    // but it massively pessimizes the code for floating-point BUILD_VECTORs
+    // because ConstantFP operands get legalized into constant pool loads
+    // before the BUILD_VECTOR code can see them.  It doesn't usually bite,
+    // though, because BUILD_VECTORS usually get lowered into other nodes
+    // which get legalized properly.
+    SimpleFinishLegalizing = false;
+    break;
   default:
     if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
       Action = TargetLowering::Legal;
@@ -780,11 +903,22 @@
   }
 
   if (SimpleFinishLegalizing) {
-    SmallVector<SDValue, 8> Ops;
+    SmallVector<SDValue, 8> Ops, ResultVals;
     for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
-      Ops.push_back(Node->getOperand(i));
+      Ops.push_back(LegalizeOp(Node->getOperand(i)));
     switch (Node->getOpcode()) {
     default: break;
+    case ISD::BR:
+    case ISD::BRIND:
+    case ISD::BR_JT:
+    case ISD::BR_CC:
+    case ISD::BRCOND:
+      // Branches tweak the chain to include LastCALLSEQ_END
+      Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
+                           LastCALLSEQ_END);
+      Ops[0] = LegalizeOp(Ops[0]);
+      LastCALLSEQ_END = DAG.getEntryNode();
+      break;
     case ISD::SHL:
     case ISD::SRL:
     case ISD::SRA:
@@ -792,66 +926,57 @@
     case ISD::ROTR:
       // Legalizing shifts/rotates requires adjusting the shift amount
       // to the appropriate width.
-      if (!Ops[1].getValueType().isVector()) {
-        SDValue SAO = DAG.getShiftAmountOperand(Ops[0].getValueType(), Ops[1]);
-        HandleSDNode Handle(SAO);
-        LegalizeOp(SAO.getNode());
-        Ops[1] = Handle.getValue();
-      }
+      if (!Ops[1].getValueType().isVector())
+        Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
+                                                      Ops[1]));
       break;
     case ISD::SRL_PARTS:
     case ISD::SRA_PARTS:
     case ISD::SHL_PARTS:
       // Legalizing shifts/rotates requires adjusting the shift amount
       // to the appropriate width.
-      if (!Ops[2].getValueType().isVector()) {
-        SDValue SAO = DAG.getShiftAmountOperand(Ops[0].getValueType(), Ops[2]);
-        HandleSDNode Handle(SAO);
-        LegalizeOp(SAO.getNode());
-        Ops[2] = Handle.getValue();
-      }
+      if (!Ops[2].getValueType().isVector())
+        Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
+                                                      Ops[2]));
       break;
     }
 
-    SDNode *NewNode = DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
-    if (NewNode != Node) {
-      DAG.ReplaceAllUsesWith(Node, NewNode, this);
-      for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
-        DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
-      DAG.RemoveDeadNode(Node, this);
-      Node = NewNode;
-    }
+    Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
+                                            Ops.size()), 0);
     switch (Action) {
     case TargetLowering::Legal:
-      return;
+      for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
+        ResultVals.push_back(Result.getValue(i));
+      break;
     case TargetLowering::Custom:
       // FIXME: The handling for custom lowering with multiple results is
       // a complete mess.
-      Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
+      Tmp1 = TLI.LowerOperation(Result, DAG);
       if (Tmp1.getNode()) {
-        SmallVector<SDValue, 8> ResultVals;
         for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
           if (e == 1)
             ResultVals.push_back(Tmp1);
           else
             ResultVals.push_back(Tmp1.getValue(i));
         }
-        if (Tmp1.getNode() != Node || Tmp1.getResNo() != 0) {
-          DAG.ReplaceAllUsesWith(Node, ResultVals.data(), this);
-          for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
-            DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
-          DAG.RemoveDeadNode(Node, this);
-        }
-        return;
+        break;
       }
 
       // FALL THROUGH
     case TargetLowering::Expand:
-      ExpandNode(Node);
-      return;
+      ExpandNode(Result.getNode(), ResultVals);
+      break;
     case TargetLowering::Promote:
-      PromoteNode(Node);
-      return;
+      PromoteNode(Result.getNode(), ResultVals);
+      break;
+    }
+    if (!ResultVals.empty()) {
+      for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
+        if (ResultVals[i] != SDValue(Node, i))
+          ResultVals[i] = LegalizeOp(ResultVals[i]);
+        AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
+      }
+      return ResultVals[Op.getResNo()];
     }
   }
 
@@ -864,20 +989,155 @@
 #endif
     assert(0 && "Do not know how to legalize this operator!");
 
-  case ISD::CALLSEQ_START:
-  case ISD::CALLSEQ_END:
+  case ISD::SRA:
+  case ISD::SRL:
+  case ISD::SHL: {
+    // Scalarize vector SRA/SRL/SHL.
+    EVT VT = Node->getValueType(0);
+    assert(VT.isVector() && "Unable to legalize non-vector shift");
+    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
+    unsigned NumElem = VT.getVectorNumElements();
+
+    SmallVector<SDValue, 8> Scalars;
+    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
+      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+                               VT.getScalarType(),
+                               Node->getOperand(0), DAG.getIntPtrConstant(Idx));
+      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+                               VT.getScalarType(),
+                               Node->getOperand(1), DAG.getIntPtrConstant(Idx));
+      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
+                                    VT.getScalarType(), Ex, Sh));
+    }
+    Result = DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
+                         &Scalars[0], Scalars.size());
     break;
+  }
+
+  case ISD::BUILD_VECTOR:
+    switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
+    default: assert(0 && "This action is not supported yet!");
+    case TargetLowering::Custom:
+      Tmp3 = TLI.LowerOperation(Result, DAG);
+      if (Tmp3.getNode()) {
+        Result = Tmp3;
+        break;
+      }
+      // FALLTHROUGH
+    case TargetLowering::Expand:
+      Result = ExpandBUILD_VECTOR(Result.getNode());
+      break;
+    }
+    break;
+  case ISD::CALLSEQ_START: {
+    SDNode *CallEnd = FindCallEndFromCallStart(Node);
+
+    // Recursively Legalize all of the inputs of the call end that do not lead
+    // to this call start.  This ensures that any libcalls that need be inserted
+    // are inserted *before* the CALLSEQ_START.
+    {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
+    for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
+      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
+                                   NodesLeadingTo);
+    }
+
+    // Now that we have legalized all of the inputs (which may have inserted
+    // libcalls), create the new CALLSEQ_START node.
+    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
+
+    // Merge in the last call to ensure that this call starts after the last
+    // call ended.
+    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
+      Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+                         Tmp1, LastCALLSEQ_END);
+      Tmp1 = LegalizeOp(Tmp1);
+    }
+
+    // Do not try to legalize the target-specific arguments (#1+).
+    if (Tmp1 != Node->getOperand(0)) {
+      SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
+      Ops[0] = Tmp1;
+      Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
+                                              Ops.size()), Result.getResNo());
+    }
+
+    // Remember that the CALLSEQ_START is legalized.
+    AddLegalizedOperand(Op.getValue(0), Result);
+    if (Node->getNumValues() == 2)    // If this has a flag result, remember it.
+      AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
+
+    // Now that the callseq_start and all of the non-call nodes above this call
+    // sequence have been legalized, legalize the call itself.  During this
+    // process, no libcalls can/will be inserted, guaranteeing that no calls
+    // can overlap.
+    assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
+    // Note that we are selecting this call!
+    LastCALLSEQ_END = SDValue(CallEnd, 0);
+    IsLegalizingCall = true;
+
+    // Legalize the call, starting from the CALLSEQ_END.
+    LegalizeOp(LastCALLSEQ_END);
+    assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
+    return Result;
+  }
+  case ISD::CALLSEQ_END:
+    // If the CALLSEQ_START node hasn't been legalized first, legalize it.  This
+    // will cause this node to be legalized as well as handling libcalls right.
+    if (LastCALLSEQ_END.getNode() != Node) {
+      LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
+      DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
+      assert(I != LegalizedNodes.end() &&
+             "Legalizing the call start should have legalized this node!");
+      return I->second;
+    }
+
+    // Otherwise, the call start has been legalized and everything is going
+    // according to plan.  Just legalize ourselves normally here.
+    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
+    // Do not try to legalize the target-specific arguments (#1+), except for
+    // an optional flag input.
+    if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
+      if (Tmp1 != Node->getOperand(0)) {
+        SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
+        Ops[0] = Tmp1;
+        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                                &Ops[0], Ops.size()),
+                         Result.getResNo());
+      }
+    } else {
+      Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
+      if (Tmp1 != Node->getOperand(0) ||
+          Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
+        SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
+        Ops[0] = Tmp1;
+        Ops.back() = Tmp2;
+        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                                &Ops[0], Ops.size()),
+                         Result.getResNo());
+      }
+    }
+    assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
+    // This finishes up call legalization.
+    IsLegalizingCall = false;
+
+    // If the CALLSEQ_END node has a flag, remember that we legalized it.
+    AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
+    if (Node->getNumValues() == 2)
+      AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
+    return Result.getValue(Op.getResNo());
   case ISD::LOAD: {
     LoadSDNode *LD = cast<LoadSDNode>(Node);
-    Tmp1 = LD->getChain();   // Legalize the chain.
-    Tmp2 = LD->getBasePtr(); // Legalize the base pointer.
+    Tmp1 = LegalizeOp(LD->getChain());   // Legalize the chain.
+    Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
 
     ISD::LoadExtType ExtType = LD->getExtensionType();
     if (ExtType == ISD::NON_EXTLOAD) {
       EVT VT = Node->getValueType(0);
-      Node = DAG.UpdateNodeOperands(Node, Tmp1, Tmp2, LD->getOffset());
-      Tmp3 = SDValue(Node, 0);
-      Tmp4 = SDValue(Node, 1);
+      Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                              Tmp1, Tmp2, LD->getOffset()),
+                       Result.getResNo());
+      Tmp3 = Result.getValue(0);
+      Tmp4 = Result.getValue(1);
 
       switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
       default: assert(0 && "This action is not supported yet!");
@@ -888,16 +1148,20 @@
           Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
           unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
           if (LD->getAlignment() < ABIAlignment){
-            ExpandUnalignedLoad(cast<LoadSDNode>(Node),
-                                DAG, TLI, Tmp3, Tmp4);
+            Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
+                                         DAG, TLI);
+            Tmp3 = Result.getOperand(0);
+            Tmp4 = Result.getOperand(1);
+            Tmp3 = LegalizeOp(Tmp3);
+            Tmp4 = LegalizeOp(Tmp4);
           }
         }
         break;
       case TargetLowering::Custom:
         Tmp1 = TLI.LowerOperation(Tmp3, DAG);
         if (Tmp1.getNode()) {
-          Tmp3 = Tmp1;
-          Tmp4 = Tmp1.getValue(1);
+          Tmp3 = LegalizeOp(Tmp1);
+          Tmp4 = LegalizeOp(Tmp1.getValue(1));
         }
         break;
       case TargetLowering::Promote: {
@@ -909,16 +1173,16 @@
         Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
                            LD->isVolatile(), LD->isNonTemporal(),
                            LD->getAlignment());
-        Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1);
-        Tmp4 = Tmp1.getValue(1);
+        Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
+        Tmp4 = LegalizeOp(Tmp1.getValue(1));
         break;
       }
       }
       // Since loads produce two values, make sure to remember that we
       // legalized both of them.
-      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3);
-      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4);
-      return;
+      AddLegalizedOperand(SDValue(Node, 0), Tmp3);
+      AddLegalizedOperand(SDValue(Node, 1), Tmp4);
+      return Op.getResNo() ? Tmp4 : Tmp3;
     }
 
     EVT SrcVT = LD->getMemoryVT();
@@ -949,10 +1213,9 @@
       ISD::LoadExtType NewExtType =
         ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
 
-      SDValue Result =
-        DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
-                       Tmp1, Tmp2, LD->getPointerInfo(),
-                       NVT, isVolatile, isNonTemporal, Alignment);
+      Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
+                              Tmp1, Tmp2, LD->getPointerInfo(),
+                              NVT, isVolatile, isNonTemporal, Alignment);
 
       Ch = Result.getValue(1); // The chain.
 
@@ -967,8 +1230,8 @@
                              Result.getValueType(), Result,
                              DAG.getValueType(SrcVT));
 
-      Tmp1 = Result;
-      Tmp2 = Ch;
+      Tmp1 = LegalizeOp(Result);
+      Tmp2 = LegalizeOp(Ch);
     } else if (SrcWidth & (SrcWidth - 1)) {
       // If not loading a power-of-2 number of bits, expand as two loads.
       assert(!SrcVT.isVector() && "Unsupported extload!");
@@ -1011,7 +1274,7 @@
                                       TLI.getShiftAmountTy(Hi.getValueType())));
 
         // Join the hi and lo parts.
-        Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
+        Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
       } else {
         // Big endian - avoid unaligned loads.
         // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD at +2:i8
@@ -1041,10 +1304,11 @@
                                       TLI.getShiftAmountTy(Hi.getValueType())));
 
         // Join the hi and lo parts.
-        Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
+        Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
       }
 
-      Tmp2 = Ch;
+      Tmp1 = LegalizeOp(Result);
+      Tmp2 = LegalizeOp(Ch);
     } else {
       switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
       default: assert(0 && "This action is not supported yet!");
@@ -1052,16 +1316,17 @@
         isCustom = true;
         // FALLTHROUGH
       case TargetLowering::Legal:
-        Node = DAG.UpdateNodeOperands(Node,
-                                      Tmp1, Tmp2, LD->getOffset());
-        Tmp1 = SDValue(Node, 0);
-        Tmp2 = SDValue(Node, 1);
+        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                                Tmp1, Tmp2, LD->getOffset()),
+                         Result.getResNo());
+        Tmp1 = Result.getValue(0);
+        Tmp2 = Result.getValue(1);
 
         if (isCustom) {
-          Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG);
+          Tmp3 = TLI.LowerOperation(Result, DAG);
           if (Tmp3.getNode()) {
-            Tmp1 = Tmp3;
-            Tmp2 = Tmp3.getValue(1);
+            Tmp1 = LegalizeOp(Tmp3);
+            Tmp2 = LegalizeOp(Tmp3.getValue(1));
           }
         } else {
           // If this is an unaligned load and the target doesn't support it,
@@ -1072,8 +1337,12 @@
             unsigned ABIAlignment =
               TLI.getTargetData()->getABITypeAlignment(Ty);
             if (LD->getAlignment() < ABIAlignment){
-              ExpandUnalignedLoad(cast<LoadSDNode>(Node),
-                                  DAG, TLI, Tmp1, Tmp2);
+              Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
+                                           DAG, TLI);
+              Tmp1 = Result.getOperand(0);
+              Tmp2 = Result.getOperand(1);
+              Tmp1 = LegalizeOp(Tmp1);
+              Tmp2 = LegalizeOp(Tmp2);
             }
           }
         }
@@ -1094,8 +1363,9 @@
           case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
           default: llvm_unreachable("Unexpected extend load type!");
           }
-          Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
-          Tmp2 = Load.getValue(1);
+          Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
+          Tmp1 = LegalizeOp(Result);  // Relegalize new nodes.
+          Tmp2 = LegalizeOp(Load.getValue(1));
           break;
         }
 
@@ -1110,10 +1380,10 @@
                "EXTLOAD should always be supported!");
         // Turn the unsupported load into an EXTLOAD followed by an explicit
         // zero/sign extend inreg.
-        SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
-                                        Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
-                                        LD->isVolatile(), LD->isNonTemporal(),
-                                        LD->getAlignment());
+        Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
+                                Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
+                                LD->isVolatile(), LD->isNonTemporal(),
+                                LD->getAlignment());
         SDValue ValRes;
         if (ExtType == ISD::SEXTLOAD)
           ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
@@ -1121,37 +1391,38 @@
                                Result, DAG.getValueType(SrcVT));
         else
           ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
-        Tmp1 = ValRes;
-        Tmp2 = Result.getValue(1);
+        Tmp1 = LegalizeOp(ValRes);  // Relegalize new nodes.
+        Tmp2 = LegalizeOp(Result.getValue(1));  // Relegalize new nodes.
         break;
       }
     }
 
     // Since loads produce two values, make sure to remember that we legalized
     // both of them.
-    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1);
-    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2);
-    break;
+    AddLegalizedOperand(SDValue(Node, 0), Tmp1);
+    AddLegalizedOperand(SDValue(Node, 1), Tmp2);
+    return Op.getResNo() ? Tmp2 : Tmp1;
   }
   case ISD::STORE: {
     StoreSDNode *ST = cast<StoreSDNode>(Node);
-    Tmp1 = ST->getChain();
-    Tmp2 = ST->getBasePtr();
+    Tmp1 = LegalizeOp(ST->getChain());    // Legalize the chain.
+    Tmp2 = LegalizeOp(ST->getBasePtr());  // Legalize the pointer.
     unsigned Alignment = ST->getAlignment();
     bool isVolatile = ST->isVolatile();
     bool isNonTemporal = ST->isNonTemporal();
 
     if (!ST->isTruncatingStore()) {
       if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
-        DAG.ReplaceAllUsesWith(ST, OptStore, this);
+        Result = SDValue(OptStore, 0);
         break;
       }
 
       {
-        Tmp3 = ST->getValue();
-        Node = DAG.UpdateNodeOperands(Node,
-                                      Tmp1, Tmp3, Tmp2,
-                                      ST->getOffset());
+        Tmp3 = LegalizeOp(ST->getValue());
+        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                                Tmp1, Tmp3, Tmp2,
+                                                ST->getOffset()),
+                         Result.getResNo());
 
         EVT VT = Tmp3.getValueType();
         switch (TLI.getOperationAction(ISD::STORE, VT)) {
@@ -1163,31 +1434,27 @@
             Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
             unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
             if (ST->getAlignment() < ABIAlignment)
-              ExpandUnalignedStore(cast<StoreSDNode>(Node),
-                                   DAG, TLI, this);
+              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
+                                            DAG, TLI);
           }
           break;
         case TargetLowering::Custom:
-          Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
-          if (Tmp1.getNode())
-            DAG.ReplaceAllUsesWith(SDValue(Node, 0), Tmp1, this);
+          Tmp1 = TLI.LowerOperation(Result, DAG);
+          if (Tmp1.getNode()) Result = Tmp1;
           break;
-        case TargetLowering::Promote: {
+        case TargetLowering::Promote:
           assert(VT.isVector() && "Unknown legal promote case!");
           Tmp3 = DAG.getNode(ISD::BITCAST, dl,
                              TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
-          SDValue Result =
-            DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
-                         ST->getPointerInfo(), isVolatile,
-                         isNonTemporal, Alignment);
-          DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
+          Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
+                                ST->getPointerInfo(), isVolatile,
+                                isNonTemporal, Alignment);
           break;
         }
-        }
         break;
       }
     } else {
-      Tmp3 = ST->getValue();
+      Tmp3 = LegalizeOp(ST->getValue());
 
       EVT StVT = ST->getMemoryVT();
       unsigned StWidth = StVT.getSizeInBits();
@@ -1199,10 +1466,8 @@
         EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
                                     StVT.getStoreSizeInBits());
         Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
-        SDValue Result =
-          DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
-                            NVT, isVolatile, isNonTemporal, Alignment);
-        DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
+        Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                                   NVT, isVolatile, isNonTemporal, Alignment);
       } else if (StWidth & (StWidth - 1)) {
         // If not storing a power-of-2 number of bits, expand as two stores.
         assert(!StVT.isVector() && "Unsupported truncstore!");
@@ -1256,13 +1521,14 @@
         }
 
         // The order of the stores doesn't matter.
-        SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
-        DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
+        Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
       } else {
         if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
             Tmp2 != ST->getBasePtr())
-          Node = DAG.UpdateNodeOperands(Node, Tmp1, Tmp3, Tmp2,
-                                        ST->getOffset());
+          Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                                  Tmp1, Tmp3, Tmp2,
+                                                  ST->getOffset()),
+                           Result.getResNo());
 
         switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
         default: assert(0 && "This action is not supported yet!");
@@ -1273,13 +1539,12 @@
             Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
             unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
             if (ST->getAlignment() < ABIAlignment)
-              ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
+              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
+                                            DAG, TLI);
           }
           break;
         case TargetLowering::Custom:
-          DAG.ReplaceAllUsesWith(SDValue(Node, 0),
-                                 TLI.LowerOperation(SDValue(Node, 0), DAG),
-                                 this);
+          Result = TLI.LowerOperation(Result, DAG);
           break;
         case TargetLowering::Expand:
           assert(!StVT.isVector() &&
@@ -1288,10 +1553,8 @@
           // TRUNCSTORE:i16 i32 -> STORE i16
           assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
           Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
-          SDValue Result =
-            DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
-                         isVolatile, isNonTemporal, Alignment);
-          DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
+          Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                                isVolatile, isNonTemporal, Alignment);
           break;
         }
       }
@@ -1299,6 +1562,17 @@
     break;
   }
   }
+  assert(Result.getValueType() == Op.getValueType() &&
+         "Bad legalization!");
+
+  // Make sure that the generated code is itself legal.
+  if (Result != Op)
+    Result = LegalizeOp(Result);
+
+  // Note that LegalizeOp may be reentered even from single-use nodes, which
+  // means that we always must cache transformed nodes.
+  AddLegalizedOperand(Op, Result);
+  return Result;
 }
 
 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
@@ -1737,6 +2011,7 @@
 // and leave the Hi part unset.
 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
                                             bool isSigned) {
+  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
   // The input chain to this libcall is the entry node of the function.
   // Legalizing the call will automatically add the previous call to the
   // dependence.
@@ -1755,6 +2030,7 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
+  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
 
   // isTailCall may be true since the callee does not reference caller stack
@@ -1770,6 +2046,10 @@
     // It's a tailcall, return the chain (which is the DAG root).
     return DAG.getRoot();
 
+  // Legalize the call sequence, starting with the chain.  This will advance
+  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
+  // was added by LowerCallTo (guaranteeing proper serialization of calls).
+  LegalizeOp(CallInfo.second);
   return CallInfo.first;
 }
 
@@ -1799,6 +2079,11 @@
                   /*isReturnValueUsed=*/true,
                   Callee, Args, DAG, dl);
 
+  // Legalize the call sequence, starting with the chain.  This will advance
+  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
+  // was added by LowerCallTo (guaranteeing proper serialization of calls).
+  LegalizeOp(CallInfo.second);
+
   return CallInfo.first;
 }
 
@@ -1808,6 +2093,7 @@
 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
                                          SDNode *Node,
                                          bool isSigned) {
+  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
   SDValue InChain = Node->getOperand(0);
 
   TargetLowering::ArgListTy Args;
@@ -1824,6 +2110,7 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
+  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
@@ -1831,6 +2118,10 @@
                     /*isReturnValueUsed=*/true,
                     Callee, Args, DAG, Node->getDebugLoc());
 
+  // Legalize the call sequence, starting with the chain.  This will advance
+  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
+  // was added by LowerCallTo (guaranteeing proper serialization of calls).
+  LegalizeOp(CallInfo.second);
   return CallInfo;
 }
 
@@ -1956,14 +2247,20 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
+  // Splice the libcall in wherever FindInputOutputChains tells us to.
   DebugLoc dl = Node->getDebugLoc();
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
                     0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
                     /*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
 
+  // Legalize the call sequence, starting with the chain.  This will advance
+  // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
+  // was added by LowerCallTo (guaranteeing proper serialization of calls).
+  LegalizeOp(CallInfo.second);
+
   // Remainder is loaded back from the stack frame.
-  SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
+  SDValue Rem = DAG.getLoad(RetVT, dl, LastCALLSEQ_END, FIPtr,
                             MachinePointerInfo(), false, false, 0);
   Results.push_back(CallInfo.first);
   Results.push_back(Rem);
@@ -2155,13 +2452,11 @@
                              MachinePointerInfo::getConstantPool(),
                              false, false, Alignment);
   else {
-    SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
-                                  DAG.getEntryNode(), CPIdx,
-                                  MachinePointerInfo::getConstantPool(),
-                                  MVT::f32, false, false, Alignment);
-    HandleSDNode Handle(Load);
-    LegalizeOp(Load.getNode());
-    FudgeInReg = Handle.getValue();
+    FudgeInReg =
+      LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
+                                DAG.getEntryNode(), CPIdx,
+                                MachinePointerInfo::getConstantPool(),
+                                MVT::f32, false, false, Alignment));
   }
 
   return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
@@ -2485,8 +2780,8 @@
   return ExpandChainLibCall(LC, Node, false);
 }
 
-void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
-  SmallVector<SDValue, 8> Results;
+void SelectionDAGLegalize::ExpandNode(SDNode *Node,
+                                      SmallVectorImpl<SDValue> &Results) {
   DebugLoc dl = Node->getDebugLoc();
   SDValue Tmp1, Tmp2, Tmp3, Tmp4;
   switch (Node->getOpcode()) {
@@ -2934,8 +3229,10 @@
     ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
     // Check to see if this FP immediate is already legal.
     // If this is a legal constant, turn it into a TargetConstantFP node.
-    if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
-      Results.push_back(ExpandConstantFP(CFP, true));
+    if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
+      Results.push_back(SDValue(Node, 0));
+    else
+      Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
     break;
   }
   case ISD::EHSELECTION: {
@@ -3181,10 +3478,6 @@
                                DAG.getIntPtrConstant(0));
       TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
                             DAG.getIntPtrConstant(1));
-      // Ret is a node with an illegal type. Because such things are not
-      // generally permitted during this phase of legalization, delete the
-      // node. The above EXTRACT_ELEMENT nodes should have been folded.
-      DAG.DeleteNode(Ret.getNode());
     }
 
     if (isSigned) {
@@ -3325,6 +3618,7 @@
 
     LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
                           Tmp2, Tmp3, Tmp4, dl);
+    LastCALLSEQ_END = DAG.getEntryNode();
 
     assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
     Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
@@ -3334,35 +3628,6 @@
     Results.push_back(Tmp1);
     break;
   }
-  case ISD::BUILD_VECTOR:
-    Results.push_back(ExpandBUILD_VECTOR(Node));
-    break;
-  case ISD::SRA:
-  case ISD::SRL:
-  case ISD::SHL: {
-    // Scalarize vector SRA/SRL/SHL.
-    EVT VT = Node->getValueType(0);
-    assert(VT.isVector() && "Unable to legalize non-vector shift");
-    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
-    unsigned NumElem = VT.getVectorNumElements();
-
-    SmallVector<SDValue, 8> Scalars;
-    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
-      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
-                               VT.getScalarType(),
-                               Node->getOperand(0), DAG.getIntPtrConstant(Idx));
-      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
-                               VT.getScalarType(),
-                               Node->getOperand(1), DAG.getIntPtrConstant(Idx));
-      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
-                                    VT.getScalarType(), Ex, Sh));
-    }
-    SDValue Result =
-      DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
-                  &Scalars[0], Scalars.size());
-    DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
-    break;
-  }
   case ISD::GLOBAL_OFFSET_TABLE:
   case ISD::GlobalAddress:
   case ISD::GlobalTLSAddress:
@@ -3373,16 +3638,13 @@
   case ISD::INTRINSIC_WO_CHAIN:
   case ISD::INTRINSIC_VOID:
     // FIXME: Custom lowering for these operations shouldn't return null!
+    for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
+      Results.push_back(SDValue(Node, i));
     break;
   }
-
-  // Replace the original node with the legalized result.
-  if (!Results.empty())
-    DAG.ReplaceAllUsesWith(Node, Results.data(), this);
 }
-
-void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
-  SmallVector<SDValue, 8> Results;
+void SelectionDAGLegalize::PromoteNode(SDNode *Node,
+                                       SmallVectorImpl<SDValue> &Results) {
   EVT OVT = Node->getValueType(0);
   if (Node->getOpcode() == ISD::UINT_TO_FP ||
       Node->getOpcode() == ISD::SINT_TO_FP ||
@@ -3510,10 +3772,6 @@
     break;
   }
   }
-
-  // Replace the original node with the legalized result.
-  if (!Results.empty())
-    DAG.ReplaceAllUsesWith(Node, Results.data(), this);
 }
 
 // SelectionDAG::Legalize - This is the entry point for the file.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Fri Oct 28 04:55:57 2011
@@ -1084,6 +1084,7 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
+  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Oct 28 04:55:57 2011
@@ -386,90 +386,6 @@
   }
 }
 
-/// IsChainDependent - Test if Outer is reachable from Inner through
-/// chain dependencies.
-static bool IsChainDependent(SDNode *Outer, SDNode *Inner) {
-  SDNode *N = Outer;
-  for (;;) {
-    if (N == Inner)
-      return true;
-    if (N->getOpcode() == ISD::TokenFactor) {
-      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-        if (IsChainDependent(N->getOperand(i).getNode(), Inner))
-          return true;
-      return false;
-    }
-    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-      if (N->getOperand(i).getValueType() == MVT::Other) {
-        N = N->getOperand(i).getNode();
-        goto found_chain_operand;
-      }
-    return false;
-  found_chain_operand:;
-    if (N->getOpcode() == ISD::EntryToken)
-      return false;
-  }
-}
-
-/// FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate
-/// the corresponding (lowered) CALLSEQ_BEGIN node.
-///
-/// NestLevel and MaxNested are used in recursion to indcate the current level
-/// of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum
-/// level seen so far.
-///
-/// TODO: It would be better to give CALLSEQ_END an explicit operand to point
-/// to the corresponding CALLSEQ_BEGIN to avoid needing to search for it.
-static SDNode *
-FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest,
-                 const TargetInstrInfo *TII) {
-  for (;;) {
-    // For a TokenFactor, examine each operand. There may be multiple ways
-    // to get to the CALLSEQ_BEGIN, but we need to find the path with the
-    // most nesting in order to ensure that we find the corresponding match.
-    if (N->getOpcode() == ISD::TokenFactor) {
-      SDNode *Best = 0;
-      unsigned BestMaxNest = MaxNest;
-      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
-        unsigned MyNestLevel = NestLevel;
-        unsigned MyMaxNest = MaxNest;
-        if (SDNode *New = FindCallSeqStart(N->getOperand(i).getNode(),
-                                           MyNestLevel, MyMaxNest, TII))
-          if (!Best || (MyMaxNest > BestMaxNest)) {
-            Best = New;
-            BestMaxNest = MyMaxNest;
-          }
-      }
-      assert(Best);
-      MaxNest = BestMaxNest;
-      return Best;
-    }
-    // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
-    if (N->isMachineOpcode()) {
-      if (N->getMachineOpcode() ==
-          (unsigned)TII->getCallFrameDestroyOpcode()) {
-        ++NestLevel;
-        MaxNest = std::max(MaxNest, NestLevel);
-      } else if (N->getMachineOpcode() ==
-                 (unsigned)TII->getCallFrameSetupOpcode()) {
-        --NestLevel;
-        if (NestLevel == 0)
-          return N;
-      }
-    }
-    // Otherwise, find the chain and continue climbing.
-    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-      if (N->getOperand(i).getValueType() == MVT::Other) {
-        N = N->getOperand(i).getNode();
-        goto found_chain_operand;
-      }
-    return 0;
-  found_chain_operand:;
-    if (N->getOpcode() == ISD::EntryToken)
-      return 0;
-  }
-}
-
 /// Call ReleasePred for each predecessor, then update register live def/gen.
 /// Always update LiveRegDefs for a register dependence even if the current SU
 /// also defines the register. This effectively create one large live range
@@ -507,26 +423,6 @@
       }
     }
   }
-
-  // If we're scheduling a lowered CALLSEQ_END, find the corresponding CALLSEQ_BEGIN.
-  // Inject an artificial physical register dependence between these nodes, to
-  // prevent other calls from being interscheduled with them.
-  const TargetLowering *TLI = TM.getTargetLowering();
-  unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
-  if (!LiveRegDefs[SP])
-    for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode())
-      if (Node->isMachineOpcode() &&
-          Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
-        unsigned NestLevel = 0;
-        unsigned MaxNest = 0;
-        SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
-
-        SUnit *Def = &SUnits[N->getNodeId()];
-        ++NumLiveRegs;
-        LiveRegDefs[SP] = Def;
-        LiveRegGens[SP] = SU;
-        break;
-      }
 }
 
 /// Check to see if any of the pending instructions are ready to issue.  If
@@ -709,22 +605,6 @@
       LiveRegGens[I->getReg()] = NULL;
     }
   }
-  // Release the special call resource dependence, if this is the beginning
-  // of a call.
-  const TargetLowering *TLI = TM.getTargetLowering();
-  unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
-  if (LiveRegDefs[SP] == SU)
-  for (const SDNode *SUNode = SU->getNode(); SUNode;
-       SUNode = SUNode->getGluedNode()) {
-    if (SUNode->isMachineOpcode() &&
-        SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode() &&
-        LiveRegDefs[SP] == SU) {
-      assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
-      --NumLiveRegs;
-      LiveRegDefs[SP] = NULL;
-      LiveRegGens[SP] = NULL;
-    }
-  }
 
   resetVRegCycle(SU);
 
@@ -1203,20 +1083,6 @@
 
     if (!Node->isMachineOpcode())
       continue;
-    // If we're in the middle of scheduling a call, don't begin scheduling
-    // another call.
-    if (Node->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode() ||
-        Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
-      for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
-        if (LiveRegDefs[i]) {
-          SDNode *Gen = LiveRegGens[i]->getNode();
-          while (SDNode *Glued = Gen->getGluedNode())
-            Gen = Glued;
-          if (!IsChainDependent(Gen, Node) && RegAdded.insert(i))
-            LRegs.push_back(i);
-        }
-      continue;
-    }
     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
     if (!MCID.ImplicitDefs)
       continue;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Oct 28 04:55:57 2011
@@ -5290,10 +5290,6 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
-
-  // If we just RAUW'd the root, take note.
-  if (FromN == getRoot())
-    setRoot(To);
 }
 
 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
@@ -5339,10 +5335,6 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
-
-  // If we just RAUW'd the root, take note.
-  if (From == getRoot().getNode())
-    setRoot(SDValue(To, getRoot().getResNo()));
 }
 
 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
@@ -5381,10 +5373,6 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
-
-  // If we just RAUW'd the root, take note.
-  if (From == getRoot().getNode())
-    setRoot(SDValue(To[getRoot().getResNo()]));
 }
 
 /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
@@ -5443,10 +5431,6 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
-
-  // If we just RAUW'd the root, take note.
-  if (From == getRoot())
-    setRoot(To);
 }
 
 namespace {

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Oct 28 04:55:57 2011
@@ -1353,10 +1353,12 @@
       SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
       SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
                                          MVT::i32);
+      // TODO: Disable AlwaysInline when it becomes possible
+      //       to emit a nested call sequence.
       MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
                                           Flags.getByValAlign(),
                                           /*isVolatile=*/false,
-                                          /*AlwaysInline=*/false,
+                                          /*AlwaysInline=*/true,
                                           MachinePointerInfo(0),
                                           MachinePointerInfo(0)));
 
@@ -4348,24 +4350,9 @@
       // If this is undef splat, generate it via "just" vdup, if possible.
       if (Lane == -1) Lane = 0;
 
-      // Test if V1 is a SCALAR_TO_VECTOR.
       if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
         return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
       }
-      // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
-      // (and probably will turn into a SCALAR_TO_VECTOR once legalization
-      // reaches it).
-      if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
-          !isa<ConstantSDNode>(V1.getOperand(0))) {
-        bool IsScalarToVector = true;
-        for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
-          if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
-            IsScalarToVector = false;
-            break;
-          }
-        if (IsScalarToVector)
-          return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
-      }
       return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
                          DAG.getConstant(Lane, MVT::i32));
     }

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Oct 28 04:55:57 2011
@@ -2114,9 +2114,7 @@
         HasNoSignedComparisonUses(Node))
       // Look past the truncate if CMP is the only use of it.
       N0 = N0.getOperand(0);
-    if ((N0.getNode()->getOpcode() == ISD::AND ||
-         (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
-        N0.getNode()->hasOneUse() &&
+    if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
         N0.getValueType() != MVT::i8 &&
         X86::isZeroNode(N1)) {
       ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Oct 28 04:55:57 2011
@@ -4220,29 +4220,6 @@
   return true;
 }
 
-// Test whether the given value is a vector value which will be legalized
-// into a load.
-static bool WillBeConstantPoolLoad(SDNode *N) {
-  if (N->getOpcode() != ISD::BUILD_VECTOR)
-    return false;
-
-  // Check for any non-constant elements.
-  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-    switch (N->getOperand(i).getNode()->getOpcode()) {
-    case ISD::UNDEF:
-    case ISD::ConstantFP:
-    case ISD::Constant:
-      break;
-    default:
-      return false;
-    }
-
-  // Vectors of all-zeros and all-ones are materialized with special
-  // instructions rather than being loaded.
-  return !ISD::isBuildVectorAllZeros(N) &&
-         !ISD::isBuildVectorAllOnes(N);
-}
-
 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
 /// match movlp{s|d}. The lower half elements should come from lower half of
 /// V1 (and in order), and the upper half elements should come from the upper
@@ -4258,7 +4235,7 @@
     return false;
   // Is V2 is a vector load, don't do this transformation. We will try to use
   // load folding shufps op.
-  if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
+  if (ISD::isNON_EXTLoad(V2))
     return false;
 
   unsigned NumElems = VT.getVectorNumElements();
@@ -6374,8 +6351,6 @@
   if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
     CanFoldLoad = true;
 
-  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
-
   // Both of them can't be memory operations though.
   if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
     CanFoldLoad = false;
@@ -6385,11 +6360,10 @@
       return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
 
     if (NumElems == 4)
-      // If we don't care about the second element, procede to use movss.
-      if (SVOp->getMaskElt(1) != -1)
-        return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
+      return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
   }
 
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
   // movl and movlp will both match v2i64, but v2i64 is never matched by
   // movl earlier because we make it strict to avoid messing with the movlp load
   // folding logic (see the code above getMOVLP call). Match it here then,
@@ -8707,9 +8681,8 @@
 
   // If condition flag is set by a X86ISD::CMP, then use it as the condition
   // setting operand in place of the X86ISD::SETCC.
-  unsigned CondOpcode = Cond.getOpcode();
-  if (CondOpcode == X86ISD::SETCC ||
-      CondOpcode == X86ISD::SETCC_CARRY) {
+  if (Cond.getOpcode() == X86ISD::SETCC ||
+      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
     CC = Cond.getOperand(0);
 
     SDValue Cmp = Cond.getOperand(1);
@@ -8726,39 +8699,6 @@
       Cond = Cmp;
       addTest = false;
     }
-  } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
-             CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
-             ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
-              Cond.getOperand(0).getValueType() != MVT::i8)) {
-    SDValue LHS = Cond.getOperand(0);
-    SDValue RHS = Cond.getOperand(1);
-    unsigned X86Opcode;
-    unsigned X86Cond;
-    SDVTList VTs;
-    switch (CondOpcode) {
-    case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
-    case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
-    case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
-    case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
-    case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
-    case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
-    default: llvm_unreachable("unexpected overflowing operator");
-    }
-    if (CondOpcode == ISD::UMULO)
-      VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
-                          MVT::i32);
-    else
-      VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
-
-    SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
-
-    if (CondOpcode == ISD::UMULO)
-      Cond = X86Op.getValue(2);
-    else
-      Cond = X86Op.getValue(1);
-
-    CC = DAG.getConstant(X86Cond, MVT::i8);
-    addTest = false;
   }
 
   if (addTest) {
@@ -8840,27 +8780,11 @@
   SDValue Dest  = Op.getOperand(2);
   DebugLoc dl = Op.getDebugLoc();
   SDValue CC;
-  bool Inverted = false;
 
   if (Cond.getOpcode() == ISD::SETCC) {
-    // Check for setcc([su]{add,sub,mul}o == 0).
-    if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
-        isa<ConstantSDNode>(Cond.getOperand(1)) &&
-        cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
-        Cond.getOperand(0).getResNo() == 1 &&
-        (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
-         Cond.getOperand(0).getOpcode() == ISD::UADDO ||
-         Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
-         Cond.getOperand(0).getOpcode() == ISD::USUBO ||
-         Cond.getOperand(0).getOpcode() == ISD::SMULO ||
-         Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
-      Inverted = true;
-      Cond = Cond.getOperand(0);
-    } else {
-      SDValue NewCond = LowerSETCC(Cond, DAG);
-      if (NewCond.getNode())
-        Cond = NewCond;
-    }
+    SDValue NewCond = LowerSETCC(Cond, DAG);
+    if (NewCond.getNode())
+      Cond = NewCond;
   }
 #if 0
   // FIXME: LowerXALUO doesn't handle these!!
@@ -8881,9 +8805,8 @@
 
   // If condition flag is set by a X86ISD::CMP, then use it as the condition
   // setting operand in place of the X86ISD::SETCC.
-  unsigned CondOpcode = Cond.getOpcode();
-  if (CondOpcode == X86ISD::SETCC ||
-      CondOpcode == X86ISD::SETCC_CARRY) {
+  if (Cond.getOpcode() == X86ISD::SETCC ||
+      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
     CC = Cond.getOperand(0);
 
     SDValue Cmp = Cond.getOperand(1);
@@ -8904,43 +8827,6 @@
         break;
       }
     }
-  }
-  CondOpcode = Cond.getOpcode();
-  if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
-      CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
-      ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
-       Cond.getOperand(0).getValueType() != MVT::i8)) {
-    SDValue LHS = Cond.getOperand(0);
-    SDValue RHS = Cond.getOperand(1);
-    unsigned X86Opcode;
-    unsigned X86Cond;
-    SDVTList VTs;
-    switch (CondOpcode) {
-    case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
-    case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
-    case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
-    case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
-    case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
-    case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
-    default: llvm_unreachable("unexpected overflowing operator");
-    }
-    if (Inverted)
-      X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
-    if (CondOpcode == ISD::UMULO)
-      VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
-                          MVT::i32);
-    else
-      VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
-
-    SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
-
-    if (CondOpcode == ISD::UMULO)
-      Cond = X86Op.getValue(2);
-    else
-      Cond = X86Op.getValue(1);
-
-    CC = DAG.getConstant(X86Cond, MVT::i8);
-    addTest = false;
   } else {
     unsigned CondOpc;
     if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
@@ -9004,66 +8890,6 @@
       CC = DAG.getConstant(CCode, MVT::i8);
       Cond = Cond.getOperand(0).getOperand(1);
       addTest = false;
-    } else if (Cond.getOpcode() == ISD::SETCC &&
-               cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
-      // For FCMP_OEQ, we can emit
-      // two branches instead of an explicit AND instruction with a
-      // separate test. However, we only do this if this block doesn't
-      // have a fall-through edge, because this requires an explicit
-      // jmp when the condition is false.
-      if (Op.getNode()->hasOneUse()) {
-        SDNode *User = *Op.getNode()->use_begin();
-        // Look for an unconditional branch following this conditional branch.
-        // We need this because we need to reverse the successors in order
-        // to implement FCMP_OEQ.
-        if (User->getOpcode() == ISD::BR) {
-          SDValue FalseBB = User->getOperand(1);
-          SDNode *NewBR =
-            DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
-          assert(NewBR == User);
-          (void)NewBR;
-          Dest = FalseBB;
-
-          SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
-                                    Cond.getOperand(0), Cond.getOperand(1));
-          CC = DAG.getConstant(X86::COND_NE, MVT::i8);
-          Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
-                              Chain, Dest, CC, Cmp);
-          CC = DAG.getConstant(X86::COND_P, MVT::i8);
-          Cond = Cmp;
-          addTest = false;
-        }
-      }
-    } else if (Cond.getOpcode() == ISD::SETCC &&
-               cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
-      // For FCMP_UNE, we can emit
-      // two branches instead of an explicit AND instruction with a
-      // separate test. However, we only do this if this block doesn't
-      // have a fall-through edge, because this requires an explicit
-      // jmp when the condition is false.
-      if (Op.getNode()->hasOneUse()) {
-        SDNode *User = *Op.getNode()->use_begin();
-        // Look for an unconditional branch following this conditional branch.
-        // We need this because we need to reverse the successors in order
-        // to implement FCMP_UNE.
-        if (User->getOpcode() == ISD::BR) {
-          SDValue FalseBB = User->getOperand(1);
-          SDNode *NewBR =
-            DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
-          assert(NewBR == User);
-          (void)NewBR;
-
-          SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
-                                    Cond.getOperand(0), Cond.getOperand(1));
-          CC = DAG.getConstant(X86::COND_NE, MVT::i8);
-          Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
-                              Chain, Dest, CC, Cmp);
-          CC = DAG.getConstant(X86::COND_NP, MVT::i8);
-          Cond = Cmp;
-          addTest = false;
-          Dest = FalseBB;
-        }
-      }
     }
   }
 

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Fri Oct 28 04:55:57 2011
@@ -386,15 +386,6 @@
     Offset = off;
     return true;
   }
-  // Check for an aligned global variable.
-  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(*Root)) {
-    const GlobalValue *GV = GA->getGlobal();
-    if (GA->getOffset() == 0 && GV->getAlignment() >= 4) {
-      AlignedBase = Base;
-      Offset = off;
-      return true;
-    }
-  }
   return false;
 }
 

Modified: llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/and_ops.ll?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/and_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/and_ops.ll Fri Oct 28 04:55:57 2011
@@ -5,9 +5,6 @@
 ; RUN: grep andhi  %t1.s | count 30
 ; RUN: grep andbi  %t1.s | count 4
 
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll Fri Oct 28 04:55:57 2011
@@ -15,9 +15,6 @@
 ; RUN: grep ai      %t2.s | count 9
 ; RUN: grep dispatch_tab %t2.s | count 6
 
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 ; ModuleID = 'call_indirect.bc'
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
 target triple = "spu-unknown-elf"

Modified: llvm/trunk/test/CodeGen/CellSPU/nand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/nand.ll?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/nand.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/nand.ll Fri Oct 28 04:55:57 2011
@@ -3,10 +3,6 @@
 ; RUN: grep and    %t1.s | count 94
 ; RUN: grep xsbh   %t1.s | count 2
 ; RUN: grep xshw   %t1.s | count 4
-
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/or_ops.ll?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/or_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/or_ops.ll Fri Oct 28 04:55:57 2011
@@ -6,9 +6,6 @@
 ; RUN: grep orbi   %t1.s | count 15
 ; RUN: FileCheck %s < %t1.s
 
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/select_bits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/select_bits.ll?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/select_bits.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/select_bits.ll Fri Oct 28 04:55:57 2011
@@ -1,9 +1,6 @@
 ; RUN: llc < %s -march=cellspu > %t1.s
 ; RUN: grep selb   %t1.s | count 56
 
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/struct_1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/struct_1.ll?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/struct_1.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/struct_1.ll Fri Oct 28 04:55:57 2011
@@ -22,9 +22,6 @@
 ; RUN: grep shufb   %t2.s | count 7
 ; RUN: grep stqd    %t2.s | count 7
 
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 ; ModuleID = 'struct_1.bc'
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"

Modified: llvm/trunk/test/CodeGen/Mips/cprestore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cprestore.ll?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cprestore.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cprestore.ll Fri Oct 28 04:55:57 2011
@@ -1,4 +1,8 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; DISABLED: llc -march=mipsel < %s | FileCheck %s
+; RUN: false
+
+; byval is currently unsupported.
+; XFAIL: *
 
 ; CHECK: .set macro
 ; CHECK-NEXT: .cprestore

Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Fri Oct 28 04:55:57 2011
@@ -1,4 +1,8 @@
-; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+; DISABLED: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+; RUN: false
+
+; byval is currently unsupported.
+; XFAIL: *
 
 %struct.S1 = type { [65536 x i8] }
 

Modified: llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll Fri Oct 28 04:55:57 2011
@@ -1,7 +1,11 @@
-; RUN: llc -mtriple=thumbv6-apple-darwin < %s
+; DISABLED: llc -mtriple=thumbv6-apple-darwin < %s
+; RUN: false
 ; rdar://problem/9416774
 ; ModuleID = 'reduced.ll'
 
+; byval is currently unsupported.
+; XFAIL: *
+
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
 target triple = "thumbv7-apple-ios"
 

Modified: llvm/trunk/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=143188&r1=143187&r2=143188&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3.ll Fri Oct 28 04:55:57 2011
@@ -16,8 +16,10 @@
 	ret void
         
 ; X64: t0:
-; X64:	movdqa	(%rsi), %xmm0
-; X64:	pslldq	$2, %xmm0
+; X64: 	movddup	(%rsi), %xmm0
+; X64:  pshuflw	$0, %xmm0, %xmm0
+; X64:	xorl	%eax, %eax
+; X64:	pinsrw	$0, %eax, %xmm0
 ; X64:	movdqa	%xmm0, (%rdi)
 ; X64:	ret
 }
@@ -29,8 +31,9 @@
 	ret <8 x i16> %tmp3
         
 ; X64: t1:
+; X64: 	movl	(%rsi), %eax
 ; X64: 	movdqa	(%rdi), %xmm0
-; X64: 	pinsrw	$0, (%rsi), %xmm0
+; X64: 	pinsrw	$0, %eax, %xmm0
 ; X64: 	ret
 }
 
@@ -165,7 +168,7 @@
         ret void
 ; X64: 	t10:
 ; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %eax
-; X64: 		movlhps [[X1:%xmm[0-9]+]]
+; X64: 		unpcklpd [[X1:%xmm[0-9]+]]
 ; X64: 		pshuflw	$8, [[X1]], [[X2:%xmm[0-9]+]]
 ; X64: 		pinsrw	$2, %eax, [[X2]]
 ; X64: 		pextrw	$6, [[X0]], %eax
@@ -247,12 +250,13 @@
         %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0,  <16 x i32> < i32 0, i32 1, i32 2, i32 17,  i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
         ret <16 x i8> %tmp9
 ; X64: 	t16:
-; X64: 		movdqa	%xmm1, %xmm0
-; X64: 		pslldq	$2, %xmm0
-; X64: 		pextrw	$1, %xmm0, %eax
-; X64: 		movd	%xmm0, %ecx
-; X64: 		pinsrw	$0, %ecx, %xmm0
-; X64: 		pextrw	$8, %xmm1, %ecx
+; X64: 		pinsrw	$0, %eax, [[X1:%xmm[0-9]+]]
+; X64: 		pextrw	$8, [[X0:%xmm[0-9]+]], %eax
+; X64: 		pinsrw	$1, %eax, [[X1]]
+; X64: 		pextrw	$1, [[X1]], %ecx
+; X64: 		movd	[[X1]], %edx
+; X64: 		pinsrw	$0, %edx, %xmm
+; X64: 		pinsrw	$1, %eax, %xmm
 ; X64: 		ret
 }
 



From baldrick at free.fr  Fri Oct 28 05:11:40 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 28 Oct 2011 12:11:40 +0200
Subject: [llvm-commits] [llvm] r142992 - in /llvm/trunk:
 lib/VMCore/Instructions.cpp test/Bitcode/shuffle.ll
In-Reply-To: <68BC306E-DC64-4EA8-9215-524F8D36A434@apple.com>
References: <20111026003448.41B96312800A@llvm.org> <4EA7B86C.5090103@free.fr>
	<68BC306E-DC64-4EA8-9215-524F8D36A434@apple.com>
Message-ID: <4EAA7FDC.6080401@free.fr>

Hi Mon Ping,

> The bit code reader tries to look up the constant based on an index.  If it is hasn't encountered the constant yet, it places a placeholder and fixes it up later.  This happens rarely and allows the reader to run in one pass.  Updating the verifier is a good idea.  I'll do that.

thanks for the explanation.  If I understand right, what is special about
shufflevector is that it's not enough that the mask has the right type,
it is also required to be a vector of ConstantInt (or undef).  Presumably
placeholders always have the right type, which is enough to satisfy other
instructions.

Ciao, Duncan.

From geek4civic at gmail.com  Fri Oct 28 05:19:13 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Fri, 28 Oct 2011 19:19:13 +0900
Subject: [llvm-commits] [llvm] r143120 -
	/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
In-Reply-To: <20111027184045.636953128060@llvm.org>
References: <20111027184045.636953128060@llvm.org>
Message-ID: <CADiQthMBbGOdeKyf+8SC+UUDWW2mYTNmYrXRm_yS454GyLrfkQ@mail.gmail.com>

Stepan, thanks for working!

2011?10?28? 3:40:45 UTC+9 Stepan Dyatkovskiy <stpworld at narod.ru>:
> Author: dyatkovskiy
> Date: Thu Oct 27 13:40:45 2011
> New Revision: 143120
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143120&view=rev
> Log:
> Fixed llvm-objdump uint64_t formatted output.
>
> Modified:
>    llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
>
> Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=143120&r1=143119&r2=143120&view=diff

> -          outs() << format("%8x:\t", SectionAddr + Index);
> +          outs() << format("%8llx:\t", SectionAddr + Index);
(ditto)

Unfortunately, msvcrt does not support %ll.
It works, though %llx is treated as %x, and msvc is on little-endian host.
(Yeah, it had been failing on big-endian ppc-linux)

Could you tweak again with PRI_* macros? (You can see in DataTypes.h.cmake)

...Takumi

From peter at pcc.me.uk  Fri Oct 28 05:37:58 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Fri, 28 Oct 2011 11:37:58 +0100
Subject: [llvm-commits] [llvm] r143135 - in
	/llvm/trunk:	docs/LangRef.html
	include/llvm/LLVMContext.h	lib/VMCore/LLVMContext.cpp
In-Reply-To: <4EAA29FF.4000208@free.fr>
References: <20111027191915.002033128060@llvm.org> <4EAA29FF.4000208@free.fr>
Message-ID: <20111028103758.GA31917@pcc.me.uk>

On Fri, Oct 28, 2011 at 06:05:19AM +0200, Duncan Sands wrote:
> Hi Peter, part of the metadata design is that it should always be safe (if
> sub-optimal) to remove it.  Will you get correct results if fpaccuracy meta
> data is dropped?

Yes.  The intention is that the code generator will select the most
accurate instruction if fpaccuracy metadata is not present.

Thanks,
-- 
Peter

From geek4civic at gmail.com  Fri Oct 28 05:50:52 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Fri, 28 Oct 2011 10:50:52 -0000
Subject: [llvm-commits] [llvm] r143189 -
	/llvm/trunk/test/CodeGen/X86/2010-08-10-DbgConstant.ll
Message-ID: <20111028105052.741F3312800A@llvm.org>

Author: chapuni
Date: Fri Oct 28 05:50:52 2011
New Revision: 143189

URL: http://llvm.org/viewvc/llvm-project?rev=143189&view=rev
Log:
test/CodeGen/X86/2010-08-10-DbgConstant.ll: Add explicit -mtriple=i686-linux. It must be for elf!

Modified:
    llvm/trunk/test/CodeGen/X86/2010-08-10-DbgConstant.ll

Modified: llvm/trunk/test/CodeGen/X86/2010-08-10-DbgConstant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-08-10-DbgConstant.ll?rev=143189&r1=143188&r2=143189&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-08-10-DbgConstant.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-08-10-DbgConstant.ll Fri Oct 28 05:50:52 2011
@@ -1,4 +1,4 @@
-; RUN: llc  -march=x86 -O0 < %s | FileCheck %s
+; RUN: llc  -mtriple=i686-linux -O0 < %s | FileCheck %s
 ; CHECK: DW_TAG_constant
 ; CHECK-NEXT: .long .Lstring3 #{{#?}} DW_AT_name
 



From kristof.beyls at arm.com  Fri Oct 28 06:06:49 2011
From: kristof.beyls at arm.com (Kristof Beyls)
Date: Fri, 28 Oct 2011 12:06:49 +0100
Subject: [llvm-commits] [patch][pr11029] fix for internal crash due
	to	ExpandUnalignedLoad/Store not handling indexed loads correctly
In-Reply-To: <000001cc93f5$98ab1040$ca0130c0$@beyls@arm.com>
References: <000001cc93f5$98ab1040$ca0130c0$@beyls@arm.com>
Message-ID: <000401cc9561$b0ea1940$12be4bc0$@beyls@arm.com>

After the changes in r143177, the patch needed to be adapted.
I've adapted the patch so that it works with current head of trunk, see
attachment.

Thanks,

Kristof

-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu
[mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Kristof Beyls
Sent: 26 October 2011 16:40
To: llvm-commits at cs.uiuc.edu
Subject: [llvm-commits] [patch][pr11029] fix for internal crash due to
ExpandUnalignedLoad/Store not handling indexed loads correctly

The attached patch fixes PR11029 (
http://llvm.org/bugs/show_bug.cgi?id=11029 ).

The root cause of the problem seems to be that ExpandUnalignedLoad and
ExpandUnalignedStore doesn't handle indexed loads or stores correctly.

There seem to be 2 possible ways to fix this:
1. Implement support for indexed loads/stores in the above functions.
2. Don't generate indexed load/stores in cases where these will need to be
expanded.

The attached patch implements the second approach. The reasons for going
with the second approach are:
* The generation of indexed loads/stores seems to be an optimization. The
second approach chooses not to do the optimization when it's not supported.
* There will not be a regression in code generation, since in the cases that
the patch prohibits optimization, the compiler would crash or generate
incorrect code with a high probability.
* It's unclear whether generating indexed loads/stores for unaligned
loads/stores that need expanding would actually result in better quality of
the generated code.

Could someone review the patch and commit it if fine?

Thanks,

Kristof
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From benny.kra at googlemail.com  Fri Oct 28 06:14:31 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Fri, 28 Oct 2011 11:14:31 -0000
Subject: [llvm-commits] [llvm] r143190 -
	/llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp
Message-ID: <20111028111431.430C8312800A@llvm.org>

Author: d0k
Date: Fri Oct 28 06:14:31 2011
New Revision: 143190

URL: http://llvm.org/viewvc/llvm-project?rev=143190&view=rev
Log:
Use BranchProbability compare operators.

Modified:
    llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp

Modified: llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp?rev=143190&r1=143189&r2=143190&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp Fri Oct 28 06:14:31 2011
@@ -55,12 +55,8 @@
 bool MachineBranchProbabilityInfo::isEdgeHot(MachineBasicBlock *Src,
                                              MachineBasicBlock *Dst) const {
   // Hot probability is at least 4/5 = 80%
-  uint32_t Weight = getEdgeWeight(Src, Dst);
-  uint32_t Sum = getSumForBlock(Src);
-
-  // FIXME: Implement BranchProbability::compare then change this code to
-  // compare this BranchProbability against a static "hot" BranchProbability.
-  return (uint64_t)Weight * 5 > (uint64_t)Sum * 4;
+  // FIXME: Compare against a static "hot" BranchProbability.
+  return getEdgeProbability(Src, Dst) > BranchProbability(4, 5);
 }
 
 MachineBasicBlock *
@@ -84,8 +80,7 @@
     }
   }
 
-  // FIXME: Use BranchProbability::compare.
-  if ((uint64_t)MaxWeight * 5 >= (uint64_t)Sum * 4)
+  if (BranchProbability(MaxWeight, Sum) >= BranchProbability(4, 5))
     return MaxSucc;
 
   return 0;



From geek4civic at gmail.com  Fri Oct 28 06:35:03 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Fri, 28 Oct 2011 20:35:03 +0900
Subject: [llvm-commits] [llvm] r143186 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/DIE.cpp lib/CodeGen/AsmPrinter/DIE.h
 lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
 test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
 test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
In-Reply-To: <CAH_MvcWJPBu1bB=Kc3snKNk9P8sSy+jyBw2h3bcYd5-_g-Kd7A@mail.gmail.com>
References: <CAH_MvcWJPBu1bB=Kc3snKNk9P8sSy+jyBw2h3bcYd5-_g-Kd7A@mail.gmail.com>
Message-ID: <CADiQthMFGEwUah-3n3QS+oNzmbZQwph-gRKc5p_xjBOvpc7voA@mail.gmail.com>

Fixed in r143189.

2011/10/28 Francois Pichet <pichet2000 at gmail.com>:
> On Fri, Oct 28, 2011 at 1:29 AM, Nick Lewycky <nicholas at mxc.ca> wrote:
>> Author: nicholas
>> Date: Fri Oct 28 00:29:47 2011
>> New Revision: 143186
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=143186&view=rev
>> Log:
>> Always use the string pool, even when it makes the .o larger. This may help
>> tools that read the debug info in the .o files by making the DIE sizes more
>> consistent.
>
> This fail on MSVC 2010:
>
> 1> ?FAIL: LLVM :: CodeGen/X86/2010-08-10-DbgConstant.ll (6053 of 9480)
> 1> ?******************** TEST 'LLVM ::
> CodeGen/X86/2010-08-10-DbgConstant.ll' FAILED ********************
> 1> ?Script:
> 1> ?--
> 1> ?C:/dev/llvm/llvm_trunk2/bin/Release/llc.EXE ?-march=x86 -O0 <
> C:/dev/llvm/llvm_trunk2/test/CodeGen/X86/2010-08-10-DbgConstant.ll |
> C:/dev/llvm/llvm_trunk2/bin/Release/FileCheck.EXE
> C:/dev/llvm/llvm_trunk2/test/CodeGen/X86/2010-08-10-DbgConstant.ll
> 1> ?--
> 1> ?Exit Code: 1
> 1> ?Command Output (stdout):
> 1> ?--
> 1> ?Command 0: "C:/dev/llvm/llvm_trunk2/bin/Release/llc.EXE" "-march=x86" "-O0"
> 1> ?Command 0 Result: 0
> 1> ?Command 0 Output:
> 1>
> 1>
> 1> ?Command 0 Stderr:
> 1>
> 1>
> 1> ?Command 1: "C:/dev/llvm/llvm_trunk2/bin/Release/FileCheck.EXE"
> "C:/dev/llvm/llvm_trunk2/test/CodeGen/X86/2010-08-10-DbgConstant.ll"
> 1> ?Command 1 Result: 1
> 1> ?Command 1 Output:
> 1>
> 1>
> 1> ?Command 1 Stderr:
> 1> ?C:/dev/llvm/llvm_trunk2/test/CodeGen/X86/2010-08-10-DbgConstant.ll:3:15:
> error: expected string not found in input
> 1> ?; CHECK-NEXT: .long .Lstring3 #{{#?}} DW_AT_name
> 1> ? ? ? ? ? ? ? ?^
> 1> ?<stdin>:70:2: note: scanning from here
> 1> ? .long Lstring3 # DW_AT_name
> 1> ? ^
> 1>
> 1>
> 1> ?--
> 1>
> 1> ?********************
> 1>
> 1> ?Testing Time: 187.73s
> 1> ?********************
> 1> ?Failing Tests (1):
> 1> ? ? ?LLVM :: CodeGen/X86/2010-08-10-DbgConstant.ll


From hfinkel at anl.gov  Fri Oct 28 06:50:00 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Fri, 28 Oct 2011 06:50:00 -0500
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <CACk9Fxb1S79ZuEFhPAHFvjXnDOb5cSpYARVTL7pNYB3X9idaYw@mail.gmail.com>
References: <1319231089.6498.6223.camel@sapling>
	<CACk9Fxb1S79ZuEFhPAHFvjXnDOb5cSpYARVTL7pNYB3X9idaYw@mail.gmail.com>
Message-ID: <1319802600.23036.632.camel@sapling>

Bruno, et al.,

I've attached a new version of the patch that contains improvements (and
a critical bug fix [the code output is not more right, but the pass in
the older patch would crash in certain cases and now does not]) compared
to previous versions that I've posted.

First, these are preliminary results because I did not do the things
necessary to make them real (explicitly quiet the machine, bind the
processes to one cpu, etc.). But they should be good enough for
discussion.

I'm using LLVM head r143101, with the attached patch applied, and clang
head r143100 on an x86_64 machine (some kind of Intel Xeon). For the gcc
comparison, I'm using build Ubuntu 4.4.3-4ubuntu5. gcc was run -O3
without any other optimization flags. opt was run -vectorize
-unroll-allow-partial -O3 with no other optimization flags (the patch
adds the -vectorize option). llc was just given -O3.

It is not difficult to construct an example in which vectorization would
be useful: take a loop that does more computation than load/stores, and
(partially) unroll it. Here is a simple case:

#define ITER 5000
#define NUM 200
double a[NUM][NUM];
double b[NUM][NUM];

...

int main()
{
...

  for (int i = 0; i < ITER; ++i) {
    for (int x = 0; x < NUM; ++x)
    for (int y = 0; y < NUM; ++y) {
      double v = a[x][y], w = b[x][y];
      double z1 = v*w;
      double z2 = v+w;
      double z3 = z1*z2;
      double z4 = z3+v;
      double z5 = z2+w;
      double z6 = z4*z5;
      double z7 = z4+z5;
      a[x][y] = v*v-z6;
      b[x][y] = w-z7;
    }
  }

 ...

  return 0;
}

Results:
gcc -03: 0m1.790s
llvm -vectorize: 0m2.360s
llvm: 0m2.780s
gcc -fno-tree-vectorize: 0m2.810s
(these are the user times after I've run enough for the times to settle
to three decimal places)

So the vectorization gives a ~15% improvement in the running time. gcc's
vectorization still does a much better job, however (yielding an ~36%
improvement). So there is still work to do ;)

Additionally, I've checked the autovectorization on some classic
numerical benchmarks from netlib. On these benchmarks, clang/llvm
already do a good job compared to gcc (gcc is only about 10% better, and
this is true regardless of whether gcc's vectorization is on or off).
For these cases, autovectorization provides an insignificant speedup in
most cases (but does not tend to make things worse, just not really any
better either). Because gcc's vectorization also did not really help gcc
in these cases, I'm not surprised. A good collection of these is
available here:
http://www.roylongbottom.org.uk/classic_benchmarks.tar.gz

I've yet to run the test suite using the pass to validate it. That is
something that I plan to do. Actually, the "Livermore Loops" test in the
aforementioned archive contains checksums to validate the results, and
it looks like 1 or 2 of the loop results are wrong with vectorization
turned on, so I'll have to investigate that.

 -Hal

On Wed, 2011-10-26 at 18:49 -0200, Bruno Cardoso Lopes wrote:
> Hi Hal,
> 
> On Fri, Oct 21, 2011 at 7:04 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> > I've attached an initial version of a basic-block autovectorization
> > pass. It works by searching a basic block for pairable (independent)
> > instructions, and, using a chain-seeking heuristic, selects pairings
> > likely to provide an overall speedup (if such pairings can be found).
> > The selected pairs are then fused and, if necessary, other instructions
> > are moved in order to maintain data-flow consistency. This works only
> > within one basic block, but can do loop vectorization in combination
> > with (partial) unrolling. The basic idea was inspired by the Vienna MAP
> > Vectorizor, which has been used to vectorize FFT kernels, but the
> > algorithm used here is different.
> >
> > To try it, use -bb-vectorize with opt. There are a few options:
> > -bb-vectorize-req-chain-depth: default: 3 -- The depth of the chain of
> > instruction pairs necessary in order to consider the pairs that compose
> > the chain worthy of vectorization.
> > -bb-vectorize-vector-bits: default: 128 -- The size of the target vector
> > registers
> > -bb-vectorize-no-ints -- Don't consider integer instructions
> > -bb-vectorize-no-floats -- Don't consider floating-point instructions
> >
> > The vectorizor generates a lot of insert_element/extract_element pairs;
> > The assumption is that other passes will turn these into shuffles when
> > possible (it looks like some work is necessary here). It will also
> > vectorize vector instructions, and generates shuffles in this case
> > (again, other passes should combine these as appropriate).
> >
> > Currently, it does not fuse load or store instructions, but that is a
> > feature that I'd like to add. Of course, alignment information is an
> > issue for load/store vectorization (or maybe I should just fuse them
> > anyway and let isel deal with unaligned cases?).
> >
> > Also, support needs to be added for fusing known intrinsics (fma, etc.),
> > and, as has been discussed on llvmdev, we should add some intrinsics to
> > allow the generation of addsub-type instructions.
> >
> > I've included a few tests, but it needs more. Please review (I'll commit
> > if and when everyone is happy).
> >
> > Thanks in advance,
> > Hal
> >
> > P.S. There is another option (not so useful right now, but could be):
> > -bb-vectorize-fast-dep -- Don't do a full inter-instruction dependency
> > analysis; instead stop looking for instruction pairs after the first use
> > of an instruction's value. [This makes the pass faster, but would
> > require a data-dependence-based reordering pass in order to be
> > effective].
> 
> Cool! :)
> Have you run this pass with any benchmark or the llvm testsuite? Does
> it presents any regression?
> Do you have any performance results?
> Cheers,
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory
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From stpworld at narod.ru  Fri Oct 28 07:09:01 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Fri, 28 Oct 2011 16:09:01 +0400
Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1
Message-ID: <4EAA9B5D.802@narod.ru>

Hi all. The main discussion branch of this feature is here:
http://llvm.org/bugs/show_bug.cgi?id=1255

We need change SwitchInst internals: replace case value type from 
"ConstantInt" to "APInt", then move case values out from operands 
collection. To do that we need add APInt::isInitialized feature. We also 
need extend SmallSet class adding Compare parameter to this template:
template <typename T, unsigned N,  typename C = std::less<T> >

Please find attached patches for review.

Regards,
Stepan.
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From baldrick at free.fr  Fri Oct 28 07:19:52 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 28 Oct 2011 14:19:52 +0200
Subject: [llvm-commits] [LLVM, SwitchInst,
 case ranges] Auxiliary patch #1
In-Reply-To: <4EAA9B5D.802@narod.ru>
References: <4EAA9B5D.802@narod.ru>
Message-ID: <4EAA9DE8.80000@free.fr>

Hi Stepan, I have to ask: what are switch case ranges good for?  Will they
actually result in better code, or just more complexity in the optimizers
and code generators?  Sorry to ask at this late date.  I know I'm the one
that first suggested adding case ranges, but I've since come to wonder
whether they are really useful.

Ciao, Duncan.

> Hi all. The main discussion branch of this feature is here:
> http://llvm.org/bugs/show_bug.cgi?id=1255
>
> We need change SwitchInst internals: replace case value type from "ConstantInt"
> to "APInt", then move case values out from operands collection. To do that we
> need add APInt::isInitialized feature. We also need extend SmallSet class adding
> Compare parameter to this template:
> template <typename T, unsigned N, typename C = std::less<T> >
>
> Please find attached patches for review.
>
> Regards,
> Stepan.
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From STPWORLD at narod.ru  Fri Oct 28 07:38:07 2011
From: STPWORLD at narod.ru (Stepan Dyatkovskiy)
Date: Fri, 28 Oct 2011 16:38:07 +0400
Subject: [llvm-commits] [LLVM, SwitchInst,
	case ranges] Auxiliary patch #1
In-Reply-To: <4EAA9DE8.80000@free.fr>
References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr>
Message-ID: <485181319805488@web67.yandex.ru>

Hi, Duncan.

Well, on instruction selection level switch cases are already grouped to switch ranges. I don't think that case ranges increases complexity of existing optimizers. I think that its useful when we work with front-ends like Fortran, since we doesn't need to split fortran's case-ranges and combine them again during switch lowering procedure.

-Stepan

28.10.2011, 16:19, "Duncan Sands" <baldrick at free.fr>:
> Hi Stepan, I have to ask: what are switch case ranges good for? ?Will they
> actually result in better code, or just more complexity in the optimizers
> and code generators? ?Sorry to ask at this late date. ?I know I'm the one
> that first suggested adding case ranges, but I've since come to wonder
> whether they are really useful.
>
> Ciao, Duncan.
>
>> ?Hi all. The main discussion branch of this feature is here:
>> ?http://llvm.org/bugs/show_bug.cgi?id=1255
>>
>> ?We need change SwitchInst internals: replace case value type from "ConstantInt"
>> ?to "APInt", then move case values out from operands collection. To do that we
>> ?need add APInt::isInitialized feature. We also need extend SmallSet class adding
>> ?Compare parameter to this template:
>> ?template <typename T, unsigned N, typename C = std::less<T> >
>>
>> ?Please find attached patches for review.
>>
>> ?Regards,
>> ?Stepan.
>>
>> ?_______________________________________________
>> ?llvm-commits mailing list
>> ?llvm-commits at cs.uiuc.edu
>> ?http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

From stpworld at narod.ru  Fri Oct 28 07:45:40 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Fri, 28 Oct 2011 16:45:40 +0400
Subject: [llvm-commits] [llvm] r143120 -
	/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
In-Reply-To: <CADiQthMBbGOdeKyf+8SC+UUDWW2mYTNmYrXRm_yS454GyLrfkQ@mail.gmail.com>
References: <20111027184045.636953128060@llvm.org>
	<CADiQthMBbGOdeKyf+8SC+UUDWW2mYTNmYrXRm_yS454GyLrfkQ@mail.gmail.com>
Message-ID: <4EAAA3F4.5090004@narod.ru>

Hi, Takumi.

I attached fixes you ask. If all is OK, I can commit it again.

-Stepan.

NAKAMURA Takumi wrote:
> Stepan, thanks for working!
> 
> 2011?10?28? 3:40:45 UTC+9 Stepan Dyatkovskiy<stpworld at narod.ru>:
>> Author: dyatkovskiy
>> Date: Thu Oct 27 13:40:45 2011
>> New Revision: 143120
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=143120&view=rev
>> Log:
>> Fixed llvm-objdump uint64_t formatted output.
>>
>> Modified:
>>     llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
>>
>> Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=143120&r1=143119&r2=143120&view=diff
> 
>> -          outs()<<  format("%8x:\t", SectionAddr + Index);
>> +          outs()<<  format("%8llx:\t", SectionAddr + Index);
> (ditto)
> 
> Unfortunately, msvcrt does not support %ll.
> It works, though %llx is treated as %x, and msvc is on little-endian host.
> (Yeah, it had been failing on big-endian ppc-linux)
> 
> Could you tweak again with PRI_* macros? (You can see in DataTypes.h.cmake)
> 
> ...Takumi


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From geek4civic at gmail.com  Fri Oct 28 07:48:52 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Fri, 28 Oct 2011 21:48:52 +0900
Subject: [llvm-commits] [llvm] r143120 -
	/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
In-Reply-To: <4EAAA3F4.5090004@narod.ru>
References: <20111027184045.636953128060@llvm.org>
	<CADiQthMBbGOdeKyf+8SC+UUDWW2mYTNmYrXRm_yS454GyLrfkQ@mail.gmail.com>
	<4EAAA3F4.5090004@narod.ru>
Message-ID: <CADiQthOJmVrFuUpNdGwGyqeGbNJetnAmo0xSWGPoYJLD8uV53A@mail.gmail.com>

2011?10?28?21:45 Stepan Dyatkovskiy <stpworld at narod.ru>:
> I attached fixes you ask. If all is OK, I can commit it again.

Stepan, LGTM. Thanks for working on this!

...Takumi

From stpworld at narod.ru  Fri Oct 28 08:07:32 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Fri, 28 Oct 2011 13:07:32 -0000
Subject: [llvm-commits] [llvm] r143191 - in /llvm/trunk/tools:
 llvm-nm/llvm-nm.cpp llvm-objdump/llvm-objdump.cpp
Message-ID: <20111028130732.46208312800A@llvm.org>

Author: dyatkovskiy
Date: Fri Oct 28 08:07:32 2011
New Revision: 143191

URL: http://llvm.org/viewvc/llvm-project?rev=143191&view=rev
Log:
uint64 formatted output: replaced %llx with PRIx64 macro.

Modified:
    llvm/trunk/tools/llvm-nm/llvm-nm.cpp
    llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp

Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=143191&r1=143190&r2=143191&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
+++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Fri Oct 28 08:07:32 2011
@@ -192,9 +192,9 @@
       strcpy(SymbolSizeStr, "        ");
 
     if (i->Address != object::UnknownAddressOrSize)
-      format("%08llx", i->Address).print(SymbolAddrStr, sizeof(SymbolAddrStr));
+      format("%08"PRIx64, i->Address).print(SymbolAddrStr, sizeof(SymbolAddrStr));
     if (i->Size != object::UnknownAddressOrSize)
-      format("%08llx", i->Size).print(SymbolSizeStr, sizeof(SymbolSizeStr));
+      format("%08"PRIx64, i->Size).print(SymbolSizeStr, sizeof(SymbolSizeStr));
 
     if (OutputFormat == posix) {
       outs() << i->Name << " " << i->TypeChar << " "

Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=143191&r1=143190&r2=143191&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Fri Oct 28 08:07:32 2011
@@ -289,7 +289,7 @@
 
         if (DisAsm->getInstruction(Inst, Size, memoryObject, Index,
                                    DebugOut, nulls())) {
-          outs() << format("%8llx:\t", SectionAddr + Index);
+          outs() << format("%8"PRIx64":\t", SectionAddr + Index);
           DumpBytes(StringRef(Bytes.data() + Index, Size));
           IP->printInst(&Inst, outs(), "");
           outs() << "\n";
@@ -316,7 +316,7 @@
           if (error(rel_cur->getTypeName(name))) goto skip_print_rel;
           if (error(rel_cur->getValueString(val))) goto skip_print_rel;
 
-          outs() << format("\t\t\t%8llx: ", SectionAddr + addr) << name << "\t"
+          outs() << format("\t\t\t%8"PRIx64": ", SectionAddr + addr) << name << "\t"
                  << val << "\n";
 
         skip_print_rel:
@@ -400,7 +400,7 @@
 
     // Dump out the content as hex and printable ascii characters.
     for (std::size_t addr = 0, end = Contents.size(); addr < end; addr += 16) {
-      outs() << format(" %04llx ", BaseAddr + addr);
+      outs() << format(" %04"PRIx64" ", BaseAddr + addr);
       // Dump line of hex.
       for (std::size_t i = 0; i < 16; ++i) {
         if (i != 0 && i % 4 == 0)
@@ -506,7 +506,7 @@
       else if (Type == SymbolRef::ST_Function)
         FileFunc = 'F';
 
-      outs() << format("%08llx", Offset) << " "
+      outs() << format("%08"PRIx64, Offset) << " "
              << GlobLoc // Local -> 'l', Global -> 'g', Neither -> ' '
              << (Weak ? 'w' : ' ') // Weak?
              << ' ' // Constructor. Not supported yet.
@@ -526,7 +526,7 @@
         outs() << SectionName;
       }
       outs() << '\t'
-             << format("%08llx ", Size)
+             << format("%08"PRIx64" ", Size)
              << Name
              << '\n';
     }



From stpworld at narod.ru  Fri Oct 28 08:10:30 2011
From: stpworld at narod.ru (Stepan Dyatkovskiy)
Date: Fri, 28 Oct 2011 17:10:30 +0400
Subject: [llvm-commits] [llvm] r143120 -
	/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
In-Reply-To: <CADiQthOJmVrFuUpNdGwGyqeGbNJetnAmo0xSWGPoYJLD8uV53A@mail.gmail.com>
References: <20111027184045.636953128060@llvm.org>
	<CADiQthMBbGOdeKyf+8SC+UUDWW2mYTNmYrXRm_yS454GyLrfkQ@mail.gmail.com>
	<4EAAA3F4.5090004@narod.ru>
	<CADiQthOJmVrFuUpNdGwGyqeGbNJetnAmo0xSWGPoYJLD8uV53A@mail.gmail.com>
Message-ID: <4EAAA9C6.9070904@narod.ru>

Commited as r143191.

-Stepan

NAKAMURA Takumi wrote:
> 2011?10?28?21:45 Stepan Dyatkovskiy<stpworld at narod.ru>:
>> I attached fixes you ask. If all is OK, I can commit it again.
> 
> Stepan, LGTM. Thanks for working on this!
> 
> ...Takumi


From geek4civic at gmail.com  Fri Oct 28 09:12:23 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Fri, 28 Oct 2011 14:12:23 -0000
Subject: [llvm-commits] [llvm] r143194 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
 test/CodeGen/X86/dbg-i128-const.ll
Message-ID: <20111028141223.129AD312800A@llvm.org>

Author: chapuni
Date: Fri Oct 28 09:12:22 2011
New Revision: 143194

URL: http://llvm.org/viewvc/llvm-project?rev=143194&view=rev
Log:
Dwarf: [PR11022] Fix emitting DW_AT_const_value(>i64), to be host-endian-neutral.

Don't assume APInt::getRawData() would hold target-aware endianness nor host-compliant endianness. rawdata[0] holds most lower i64, even on big endian host.

FIXME: Add a testcase for big endian target.

FIXME: Ditto on CompileUnit::addConstantFPValue() ?

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
    llvm/trunk/test/CodeGen/X86/dbg-i128-const.ll

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=143194&r1=143193&r2=143194&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Fri Oct 28 09:12:22 2011
@@ -534,18 +534,20 @@
 
   // Get the raw data form of the large APInt.
   const APInt Val = CI->getValue();
-  const char *Ptr = (const char*)Val.getRawData();
+  const uint64_t *Ptr64 = Val.getRawData();
 
   int NumBytes = Val.getBitWidth() / 8; // 8 bits per byte.
   bool LittleEndian = Asm->getTargetData().isLittleEndian();
-  int Incr = (LittleEndian ? 1 : -1);
-  int Start = (LittleEndian ? 0 : NumBytes - 1);
-  int Stop = (LittleEndian ? NumBytes : -1);
 
   // Output the constant to DWARF one byte at a time.
-  for (; Start != Stop; Start += Incr)
-    addUInt(Block, 0, dwarf::DW_FORM_data1,
-            (unsigned char)0xFF & Ptr[Start]);
+  for (int i = 0; i < NumBytes; i++) {
+    uint8_t c;
+    if (LittleEndian)
+      c = Ptr64[i / 8] >> (8 * (i & 7));
+    else
+      c = Ptr64[(NumBytes - 1 - i) / 8] >> (8 * ((NumBytes - 1 - i) & 7));
+    addUInt(Block, 0, dwarf::DW_FORM_data1, c);
+  }
 
   addBlock(Die, dwarf::DW_AT_const_value, 0, Block);
   return true;

Modified: llvm/trunk/test/CodeGen/X86/dbg-i128-const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-i128-const.ll?rev=143194&r1=143193&r2=143194&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-i128-const.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dbg-i128-const.ll Fri Oct 28 09:12:22 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-linux < %s | FileCheck %s
 
 ; CHECK: DW_AT_const_value
 ; CHECK-NEXT: 42



From geek4civic at gmail.com  Fri Oct 28 09:12:30 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Fri, 28 Oct 2011 14:12:30 -0000
Subject: [llvm-commits] [llvm] r143195 -
	/llvm/trunk/test/MC/AsmParser/2011-09-06-NoNewline.s
Message-ID: <20111028141230.771AA312800A@llvm.org>

Author: chapuni
Date: Fri Oct 28 09:12:30 2011
New Revision: 143195

URL: http://llvm.org/viewvc/llvm-project?rev=143195&view=rev
Log:
test/MC/AsmParser/2011-09-06-NoNewline.s: Add explicit -mtriple=i386. It uses X86 instruction.

FIXME: Would it be reproduced without target-specific operands?
FIXME: Why run llvm-mc as the same input by 3 times?

Modified:
    llvm/trunk/test/MC/AsmParser/2011-09-06-NoNewline.s

Modified: llvm/trunk/test/MC/AsmParser/2011-09-06-NoNewline.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/2011-09-06-NoNewline.s?rev=143195&r1=143194&r2=143195&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/2011-09-06-NoNewline.s (original)
+++ llvm/trunk/test/MC/AsmParser/2011-09-06-NoNewline.s Fri Oct 28 09:12:30 2011
@@ -1,6 +1,6 @@
-// RUN: llvm-mc %s
+// RUN: llvm-mc -triple i386-unknown-unknown %s
 movl %gs:8, %eax
-// RUN: llvm-mc %s
+// RUN: llvm-mc -triple i386-unknown-unknown %s
 movl %gs:8, %eax
-// RUN: llvm-mc %s
+// RUN: llvm-mc -triple i386-unknown-unknown %s
 movl %gs:8, %eax
\ No newline at end of file



From grosbach at apple.com  Fri Oct 28 11:43:40 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 28 Oct 2011 16:43:40 -0000
Subject: [llvm-commits] [llvm] r143200 -
	/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
Message-ID: <20111028164340.D6896312800A@llvm.org>

Author: grosbach
Date: Fri Oct 28 11:43:40 2011
New Revision: 143200

URL: http://llvm.org/viewvc/llvm-project?rev=143200&view=rev
Log:
Allow register classes to match a containing class in InstAliases.

If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.

Modified:
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=143200&r1=143199&r2=143200&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Fri Oct 28 11:43:40 2011
@@ -423,6 +423,15 @@
     return true;
   }
 
+  // For register operands, the source register class can be a subclass
+  // of the instruction register class, not just an exact match.
+  if (ADI && ADI->getDef()->isSubClassOf("RegisterClass")) {
+    if (!InstOpRec->isSubClassOf("RegisterClass"))
+      return false;
+    return T.getRegisterClass(InstOpRec)
+              .hasSubClass(&T.getRegisterClass(ADI->getDef()));
+  }
+
   // Handle explicit registers.
   if (ADI && ADI->getDef()->isSubClassOf("Register")) {
     if (InstOpRec->isSubClassOf("OptionalDefOperand")) {



From grosbach at apple.com  Fri Oct 28 11:57:08 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 28 Oct 2011 16:57:08 -0000
Subject: [llvm-commits] [llvm] r143201 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
 test/MC/ARM/thumb-diagnostics.s
Message-ID: <20111028165708.28DFA312800A@llvm.org>

Author: grosbach
Date: Fri Oct 28 11:57:07 2011
New Revision: 143201

URL: http://llvm.org/viewvc/llvm-project?rev=143201&view=rev
Log:
Thumb2 ADD/SUB instructions encoding selection outside IT block.

Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
    llvm/trunk/test/MC/ARM/thumb-diagnostics.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=143201&r1=143200&r2=143201&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Oct 28 11:57:07 2011
@@ -3861,6 +3861,16 @@
 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
                   (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
                            pred:$p, cc_out:$s)>;
+// ... and with the destination and source register combined.
+def : t2InstAlias<"add${s}${p} $Rdn, $imm",
+      (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"add${p} $Rdn, $imm",
+           (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
+def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
+            (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
+                  (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
+                           pred:$p, cc_out:$s)>;
 
 // Aliases for SUB without the ".w" optional width specifier.
 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
@@ -3872,6 +3882,17 @@
 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
                   (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
                            pred:$p, cc_out:$s)>;
+// ... and with the destination and source register combined.
+def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
+      (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"sub${p} $Rdn, $imm",
+           (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
+def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
+            (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
+                  (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
+                           pred:$p, cc_out:$s)>;
+
 
 // Alias for compares without the ".w" optional width specifier.
 def : t2InstAlias<"cmn${p} $Rn, $Rm",

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=143201&r1=143200&r2=143201&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Oct 28 11:57:07 2011
@@ -73,6 +73,7 @@
         add r12, r6, #0x100
         addw r12, r6, #0x100
         adds r1, r2, #0x1f0
+	add r2, #1
 
 @ CHECK: itet	eq                      @ encoding: [0x0a,0xbf]
 @ CHECK: addeq	r1, r2, #4              @ encoding: [0x11,0x1d]
@@ -85,6 +86,7 @@
 @ CHECK: add.w	r12, r6, #256           @ encoding: [0x06,0xf5,0x80,0x7c]
 @ CHECK: addw	r12, r6, #256           @ encoding: [0x06,0xf2,0x00,0x1c]
 @ CHECK: adds.w	r1, r2, #496            @ encoding: [0x12,0xf5,0xf8,0x71]
+@ CHECK: add.w	r2, r2, #1              @ encoding: [0x02,0xf1,0x01,0x02]
 
 
 @------------------------------------------------------------------------------
@@ -2533,6 +2535,7 @@
         sub r12, r6, #0x100
         subw r12, r6, #0x100
         subs r1, r2, #0x1f0
+	sub r2, #1
 
 @ CHECK: itet	eq                      @ encoding: [0x0a,0xbf]
 @ CHECK: subeq	r1, r2, #4              @ encoding: [0x11,0x1f]
@@ -2545,6 +2548,7 @@
 @ CHECK: sub.w	r12, r6, #256           @ encoding: [0xa6,0xf5,0x80,0x7c]
 @ CHECK: subw	r12, r6, #256           @ encoding: [0xa6,0xf2,0x00,0x1c]
 @ CHECK: subs.w	r1, r2, #496            @ encoding: [0xb2,0xf5,0xf8,0x71]
+@ CHECK: sub.w	r2, r2, #1              @ encoding: [0xa2,0xf1,0x01,0x02]
 
 
 @------------------------------------------------------------------------------

Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=143201&r1=143200&r2=143201&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Fri Oct 28 11:57:07 2011
@@ -125,10 +125,10 @@
         add sp, #3
         add sp, sp, #512
         add r2, sp, #1024
-@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
 @ CHECK-ERRORS:         add sp, #-1
 @ CHECK-ERRORS:                 ^
-@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
 @ CHECK-ERRORS:         add sp, #3
 @ CHECK-ERRORS:                 ^
 @ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled



From resistor at mac.com  Fri Oct 28 12:29:39 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 28 Oct 2011 17:29:39 -0000
Subject: [llvm-commits] [llvm] r143202 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20111028172939.6723E312800A@llvm.org>

Author: resistor
Date: Fri Oct 28 12:29:39 2011
New Revision: 143202

URL: http://llvm.org/viewvc/llvm-project?rev=143202&view=rev
Log:
Specify fixed bits on CPS instructions to enable roundtripping.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=143202&r1=143201&r2=143202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Oct 28 12:29:39 2011
@@ -1640,7 +1640,7 @@
   let Inst{27-20} = 0b00010000;
   let Inst{19-18} = imod;
   let Inst{17}    = M; // Enabled if mode is set;
-  let Inst{16}    = 0;
+  let Inst{16-9}  = 0b00000000;
   let Inst{8-6}   = iflags;
   let Inst{5}     = 0;
   let Inst{4-0}   = mode;



From resistor at mac.com  Fri Oct 28 12:38:30 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 28 Oct 2011 17:38:30 -0000
Subject: [llvm-commits] [llvm] r143203 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20111028173830.640B9312800A@llvm.org>

Author: resistor
Date: Fri Oct 28 12:38:30 2011
New Revision: 143203

URL: http://llvm.org/viewvc/llvm-project?rev=143203&view=rev
Log:
Revert r143202.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=143203&r1=143202&r2=143203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Oct 28 12:38:30 2011
@@ -1640,7 +1640,7 @@
   let Inst{27-20} = 0b00010000;
   let Inst{19-18} = imod;
   let Inst{17}    = M; // Enabled if mode is set;
-  let Inst{16-9}  = 0b00000000;
+  let Inst{16}    = 0;
   let Inst{8-6}   = iflags;
   let Inst{5}     = 0;
   let Inst{4-0}   = mode;



From gohman at apple.com  Fri Oct 28 12:55:38 2011
From: gohman at apple.com (Dan Gohman)
Date: Fri, 28 Oct 2011 17:55:38 -0000
Subject: [llvm-commits] [llvm] r143206 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ lib/Target/XCore/
 test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb/
 test/CodeGen/X86/
Message-ID: <20111028175539.94B08312800A@llvm.org>

Author: djg
Date: Fri Oct 28 12:55:38 2011
New Revision: 143206

URL: http://llvm.org/viewvc/llvm-project?rev=143206&view=rev
Log:
Reapply r143177 and r143179 (reverting r143188), with scheduler
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.

Added:
    llvm/trunk/test/CodeGen/X86/legalize-libcalls.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
    llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
    llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll
    llvm/trunk/test/CodeGen/CellSPU/nand.ll
    llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
    llvm/trunk/test/CodeGen/CellSPU/select_bits.ll
    llvm/trunk/test/CodeGen/CellSPU/struct_1.ll
    llvm/trunk/test/CodeGen/Mips/cprestore.ll
    llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
    llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
    llvm/trunk/test/CodeGen/X86/sse3.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 28 12:55:38 2011
@@ -46,37 +46,18 @@
 /// will attempt merge setcc and brc instructions into brcc's.
 ///
 namespace {
-class SelectionDAGLegalize {
+class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
   const TargetMachine &TM;
   const TargetLowering &TLI;
   SelectionDAG &DAG;
 
-  // Libcall insertion helpers.
+  /// LegalizePosition - The iterator for walking through the node list.
+  SelectionDAG::allnodes_iterator LegalizePosition;
 
-  /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
-  /// legalized.  We use this to ensure that calls are properly serialized
-  /// against each other, including inserted libcalls.
-  SDValue LastCALLSEQ_END;
-
-  /// IsLegalizingCall - This member is used *only* for purposes of providing
-  /// helpful assertions that a libcall isn't created while another call is
-  /// being legalized (which could lead to non-serialized call sequences).
-  bool IsLegalizingCall;
-
-  /// LegalizedNodes - For nodes that are of legal width, and that have more
-  /// than one use, this map indicates what regularized operand to use.  This
-  /// allows us to avoid legalizing the same thing more than once.
-  DenseMap<SDValue, SDValue> LegalizedNodes;
-
-  void AddLegalizedOperand(SDValue From, SDValue To) {
-    LegalizedNodes.insert(std::make_pair(From, To));
-    // If someone requests legalization of the new node, return itself.
-    if (From != To)
-      LegalizedNodes.insert(std::make_pair(To, To));
+  /// LegalizedNodes - The set of nodes which have already been legalized.
+  SmallPtrSet<SDNode *, 16> LegalizedNodes;
 
-    // Transfer SDDbgValues.
-    DAG.TransferDbgValues(From, To);
-  }
+  // Libcall insertion helpers.
 
 public:
   explicit SelectionDAGLegalize(SelectionDAG &DAG);
@@ -84,9 +65,8 @@
   void LegalizeDAG();
 
 private:
-  /// LegalizeOp - Return a legal replacement for the given operation, with
-  /// all legal operands.
-  SDValue LegalizeOp(SDValue O);
+  /// LegalizeOp - Legalizes the given operation.
+  void LegalizeOp(SDNode *Node);
 
   SDValue OptimizeFloatStore(StoreSDNode *ST);
 
@@ -107,9 +87,6 @@
                                      SDValue N1, SDValue N2,
                                      SmallVectorImpl<int> &Mask) const;
 
-  bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
-                                    SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
-
   void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
                              DebugLoc dl);
 
@@ -150,10 +127,21 @@
   SDValue ExpandInsertToVectorThroughStack(SDValue Op);
   SDValue ExpandVectorBuildThroughStack(SDNode* Node);
 
+  SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
+
   std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
 
-  void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
-  void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
+  void ExpandNode(SDNode *Node);
+  void PromoteNode(SDNode *Node);
+
+  // DAGUpdateListener implementation.
+  virtual void NodeDeleted(SDNode *N, SDNode *E) {
+    LegalizedNodes.erase(N);
+    if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
+      ++LegalizePosition;
+  }
+
+  virtual void NodeUpdated(SDNode *N) {}
 };
 }
 
@@ -195,145 +183,37 @@
 }
 
 void SelectionDAGLegalize::LegalizeDAG() {
-  LastCALLSEQ_END = DAG.getEntryNode();
-  IsLegalizingCall = false;
-
-  // The legalize process is inherently a bottom-up recursive process (users
-  // legalize their uses before themselves).  Given infinite stack space, we
-  // could just start legalizing on the root and traverse the whole graph.  In
-  // practice however, this causes us to run out of stack space on large basic
-  // blocks.  To avoid this problem, compute an ordering of the nodes where each
-  // node is only legalized after all of its operands are legalized.
   DAG.AssignTopologicalOrder();
-  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
-       E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
-    LegalizeOp(SDValue(I, 0));
-
-  // Finally, it's possible the root changed.  Get the new root.
-  SDValue OldRoot = DAG.getRoot();
-  assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
-  DAG.setRoot(LegalizedNodes[OldRoot]);
-
-  LegalizedNodes.clear();
-
-  // Remove dead nodes now.
-  DAG.RemoveDeadNodes();
-}
-
-
-/// FindCallEndFromCallStart - Given a chained node that is part of a call
-/// sequence, find the CALLSEQ_END node that terminates the call sequence.
-static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
-  // Nested CALLSEQ_START/END constructs aren't yet legal,
-  // but we can DTRT and handle them correctly here.
-  if (Node->getOpcode() == ISD::CALLSEQ_START)
-    depth++;
-  else if (Node->getOpcode() == ISD::CALLSEQ_END) {
-    depth--;
-    if (depth == 0)
-      return Node;
-  }
-  if (Node->use_empty())
-    return 0;   // No CallSeqEnd
-
-  // The chain is usually at the end.
-  SDValue TheChain(Node, Node->getNumValues()-1);
-  if (TheChain.getValueType() != MVT::Other) {
-    // Sometimes it's at the beginning.
-    TheChain = SDValue(Node, 0);
-    if (TheChain.getValueType() != MVT::Other) {
-      // Otherwise, hunt for it.
-      for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
-        if (Node->getValueType(i) == MVT::Other) {
-          TheChain = SDValue(Node, i);
-          break;
-        }
 
-      // Otherwise, we walked into a node without a chain.
-      if (TheChain.getValueType() != MVT::Other)
-        return 0;
+  // Visit all the nodes. We start in topological order, so that we see
+  // nodes with their original operands intact. Legalization can produce
+  // new nodes which may themselves need to be legalized. Iterate until all
+  // nodes have been legalized.
+  for (;;) {
+    bool AnyLegalized = false;
+    for (LegalizePosition = DAG.allnodes_end();
+         LegalizePosition != DAG.allnodes_begin(); ) {
+      --LegalizePosition;
+
+      SDNode *N = LegalizePosition;
+      if (LegalizedNodes.insert(N)) {
+        AnyLegalized = true;
+        LegalizeOp(N);
+      }
     }
-  }
-
-  for (SDNode::use_iterator UI = Node->use_begin(),
-       E = Node->use_end(); UI != E; ++UI) {
-
-    // Make sure to only follow users of our token chain.
-    SDNode *User = *UI;
-    for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
-      if (User->getOperand(i) == TheChain)
-        if (SDNode *Result = FindCallEndFromCallStart(User, depth))
-          return Result;
-  }
-  return 0;
-}
-
-/// FindCallStartFromCallEnd - Given a chained node that is part of a call
-/// sequence, find the CALLSEQ_START node that initiates the call sequence.
-static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
-  int nested = 0;
-  assert(Node && "Didn't find callseq_start for a call??");
-  while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
-    Node = Node->getOperand(0).getNode();
-    assert(Node->getOperand(0).getValueType() == MVT::Other &&
-           "Node doesn't have a token chain argument!");
-    switch (Node->getOpcode()) {
-    default:
-      break;
-    case ISD::CALLSEQ_START:
-      if (!nested)
-        return Node;
-      nested--;
-      break;
-    case ISD::CALLSEQ_END:
-      nested++;
+    if (!AnyLegalized)
       break;
-    }
-  }
-  return 0;
-}
 
-/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
-/// see if any uses can reach Dest.  If no dest operands can get to dest,
-/// legalize them, legalize ourself, and return false, otherwise, return true.
-///
-/// Keep track of the nodes we fine that actually do lead to Dest in
-/// NodesLeadingTo.  This avoids retraversing them exponential number of times.
-///
-bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
-                                     SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
-  if (N == Dest) return true;  // N certainly leads to Dest :)
-
-  // If we've already processed this node and it does lead to Dest, there is no
-  // need to reprocess it.
-  if (NodesLeadingTo.count(N)) return true;
-
-  // If the first result of this node has been already legalized, then it cannot
-  // reach N.
-  if (LegalizedNodes.count(SDValue(N, 0))) return false;
-
-  // Okay, this node has not already been legalized.  Check and legalize all
-  // operands.  If none lead to Dest, then we can legalize this node.
-  bool OperandsLeadToDest = false;
-  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-    OperandsLeadToDest |=     // If an operand leads to Dest, so do we.
-      LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
-                                   NodesLeadingTo);
-
-  if (OperandsLeadToDest) {
-    NodesLeadingTo.insert(N);
-    return true;
   }
 
-  // Okay, this node looks safe, legalize it and return false.
-  LegalizeOp(SDValue(N, 0));
-  return false;
+  // Remove dead nodes now.
+  DAG.RemoveDeadNodes();
 }
 
 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
 /// a load from the constant pool.
-static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
-                                SelectionDAG &DAG, const TargetLowering &TLI) {
+SDValue
+SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
   bool Extend = false;
   DebugLoc dl = CFP->getDebugLoc();
 
@@ -369,20 +249,25 @@
 
   SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
   unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
-  if (Extend)
-    return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
-                          DAG.getEntryNode(),
-                          CPIdx, MachinePointerInfo::getConstantPool(),
-                          VT, false, false, Alignment);
-  return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
-                     MachinePointerInfo::getConstantPool(), false, false,
-                     Alignment);
+  if (Extend) {
+    SDValue Result =
+      DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
+                     DAG.getEntryNode(),
+                     CPIdx, MachinePointerInfo::getConstantPool(),
+                     VT, false, false, Alignment);
+    return Result;
+  }
+  SDValue Result =
+    DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
+                MachinePointerInfo::getConstantPool(), false, false,
+                Alignment);
+  return Result;
 }
 
 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
-static
-SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
-                             const TargetLowering &TLI) {
+static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
+                                 const TargetLowering &TLI,
+                                 SelectionDAG::DAGUpdateListener *DUL) {
   SDValue Chain = ST->getChain();
   SDValue Ptr = ST->getBasePtr();
   SDValue Val = ST->getValue();
@@ -397,8 +282,10 @@
       // same size, then a (misaligned) int store.
       // FIXME: Does not handle truncating floating point stores!
       SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
-      return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
-                          ST->isVolatile(), ST->isNonTemporal(), Alignment);
+      Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
+                           ST->isVolatile(), ST->isNonTemporal(), Alignment);
+      DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
+      return;
     }
     // Do a (aligned) store to a stack slot, then copy from the stack slot
     // to the final destination using (unaligned) integer loads and stores.
@@ -458,8 +345,11 @@
                                        ST->isNonTemporal(),
                                        MinAlign(ST->getAlignment(), Offset)));
     // The order of the stores doesn't matter - say it with a TokenFactor.
-    return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
-                       Stores.size());
+    SDValue Result =
+      DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
+                  Stores.size());
+    DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
+    return;
   }
   assert(ST->getMemoryVT().isInteger() &&
          !ST->getMemoryVT().isVector() &&
@@ -488,13 +378,16 @@
                              NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
                              Alignment);
 
-  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
+  SDValue Result =
+    DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
+  DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
 }
 
 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
-static
-SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
-                            const TargetLowering &TLI) {
+static void
+ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
+                    const TargetLowering &TLI,
+                    SDValue &ValResult, SDValue &ChainResult) {
   SDValue Chain = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
   EVT VT = LD->getValueType(0);
@@ -512,8 +405,9 @@
       if (VT.isFloatingPoint() && LoadedVT != VT)
         Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
 
-      SDValue Ops[] = { Result, Chain };
-      return DAG.getMergeValues(Ops, 2, dl);
+      ValResult = Result;
+      ChainResult = Chain;
+      return;
     }
 
     // Copy the value to a (aligned) stack slot using (unaligned) integer
@@ -572,8 +466,9 @@
                           MachinePointerInfo(), LoadedVT, false, false, 0);
 
     // Callers expect a MERGE_VALUES node.
-    SDValue Ops[] = { Load, TF };
-    return DAG.getMergeValues(Ops, 2, dl);
+    ValResult = Load;
+    ChainResult = TF;
+    return;
   }
   assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
          "Unaligned load of unsupported type.");
@@ -626,8 +521,8 @@
   SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                              Hi.getValue(1));
 
-  SDValue Ops[] = { Result, TF };
-  return DAG.getMergeValues(Ops, 2, dl);
+  ValResult = Result;
+  ChainResult = TF;
 }
 
 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
@@ -763,11 +658,10 @@
 
 /// LegalizeOp - Return a legal replacement for the given operation, with
 /// all legal operands.
-SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
-  if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
-    return Op;
+void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
+  if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
+    return;
 
-  SDNode *Node = Op.getNode();
   DebugLoc dl = Node->getDebugLoc();
 
   for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
@@ -782,13 +676,7 @@
             Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
            "Unexpected illegal type!");
 
-  // Note that LegalizeOp may be reentered even from single-use nodes, which
-  // means that we always must cache transformed nodes.
-  DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
-  if (I != LegalizedNodes.end()) return I->second;
-
   SDValue Tmp1, Tmp2, Tmp3, Tmp4;
-  SDValue Result = Op;
   bool isCustom = false;
 
   // Figure out the correct action; the way to query this varies by opcode
@@ -882,17 +770,6 @@
     if (Action == TargetLowering::Legal)
       Action = TargetLowering::Custom;
     break;
-  case ISD::BUILD_VECTOR:
-    // A weird case: legalization for BUILD_VECTOR never legalizes the
-    // operands!
-    // FIXME: This really sucks... changing it isn't semantically incorrect,
-    // but it massively pessimizes the code for floating-point BUILD_VECTORs
-    // because ConstantFP operands get legalized into constant pool loads
-    // before the BUILD_VECTOR code can see them.  It doesn't usually bite,
-    // though, because BUILD_VECTORS usually get lowered into other nodes
-    // which get legalized properly.
-    SimpleFinishLegalizing = false;
-    break;
   default:
     if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
       Action = TargetLowering::Legal;
@@ -903,22 +780,11 @@
   }
 
   if (SimpleFinishLegalizing) {
-    SmallVector<SDValue, 8> Ops, ResultVals;
+    SmallVector<SDValue, 8> Ops;
     for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
-      Ops.push_back(LegalizeOp(Node->getOperand(i)));
+      Ops.push_back(Node->getOperand(i));
     switch (Node->getOpcode()) {
     default: break;
-    case ISD::BR:
-    case ISD::BRIND:
-    case ISD::BR_JT:
-    case ISD::BR_CC:
-    case ISD::BRCOND:
-      // Branches tweak the chain to include LastCALLSEQ_END
-      Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
-                           LastCALLSEQ_END);
-      Ops[0] = LegalizeOp(Ops[0]);
-      LastCALLSEQ_END = DAG.getEntryNode();
-      break;
     case ISD::SHL:
     case ISD::SRL:
     case ISD::SRA:
@@ -926,57 +792,66 @@
     case ISD::ROTR:
       // Legalizing shifts/rotates requires adjusting the shift amount
       // to the appropriate width.
-      if (!Ops[1].getValueType().isVector())
-        Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
-                                                      Ops[1]));
+      if (!Ops[1].getValueType().isVector()) {
+        SDValue SAO = DAG.getShiftAmountOperand(Ops[0].getValueType(), Ops[1]);
+        HandleSDNode Handle(SAO);
+        LegalizeOp(SAO.getNode());
+        Ops[1] = Handle.getValue();
+      }
       break;
     case ISD::SRL_PARTS:
     case ISD::SRA_PARTS:
     case ISD::SHL_PARTS:
       // Legalizing shifts/rotates requires adjusting the shift amount
       // to the appropriate width.
-      if (!Ops[2].getValueType().isVector())
-        Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
-                                                      Ops[2]));
+      if (!Ops[2].getValueType().isVector()) {
+        SDValue SAO = DAG.getShiftAmountOperand(Ops[0].getValueType(), Ops[2]);
+        HandleSDNode Handle(SAO);
+        LegalizeOp(SAO.getNode());
+        Ops[2] = Handle.getValue();
+      }
       break;
     }
 
-    Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
-                                            Ops.size()), 0);
+    SDNode *NewNode = DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
+    if (NewNode != Node) {
+      DAG.ReplaceAllUsesWith(Node, NewNode, this);
+      for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
+        DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
+      DAG.RemoveDeadNode(Node, this);
+      Node = NewNode;
+    }
     switch (Action) {
     case TargetLowering::Legal:
-      for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
-        ResultVals.push_back(Result.getValue(i));
-      break;
+      return;
     case TargetLowering::Custom:
       // FIXME: The handling for custom lowering with multiple results is
       // a complete mess.
-      Tmp1 = TLI.LowerOperation(Result, DAG);
+      Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
       if (Tmp1.getNode()) {
+        SmallVector<SDValue, 8> ResultVals;
         for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
           if (e == 1)
             ResultVals.push_back(Tmp1);
           else
             ResultVals.push_back(Tmp1.getValue(i));
         }
-        break;
+        if (Tmp1.getNode() != Node || Tmp1.getResNo() != 0) {
+          DAG.ReplaceAllUsesWith(Node, ResultVals.data(), this);
+          for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
+            DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
+          DAG.RemoveDeadNode(Node, this);
+        }
+        return;
       }
 
       // FALL THROUGH
     case TargetLowering::Expand:
-      ExpandNode(Result.getNode(), ResultVals);
-      break;
+      ExpandNode(Node);
+      return;
     case TargetLowering::Promote:
-      PromoteNode(Result.getNode(), ResultVals);
-      break;
-    }
-    if (!ResultVals.empty()) {
-      for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
-        if (ResultVals[i] != SDValue(Node, i))
-          ResultVals[i] = LegalizeOp(ResultVals[i]);
-        AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
-      }
-      return ResultVals[Op.getResNo()];
+      PromoteNode(Node);
+      return;
     }
   }
 
@@ -989,155 +864,20 @@
 #endif
     assert(0 && "Do not know how to legalize this operator!");
 
-  case ISD::SRA:
-  case ISD::SRL:
-  case ISD::SHL: {
-    // Scalarize vector SRA/SRL/SHL.
-    EVT VT = Node->getValueType(0);
-    assert(VT.isVector() && "Unable to legalize non-vector shift");
-    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
-    unsigned NumElem = VT.getVectorNumElements();
-
-    SmallVector<SDValue, 8> Scalars;
-    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
-      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
-                               VT.getScalarType(),
-                               Node->getOperand(0), DAG.getIntPtrConstant(Idx));
-      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
-                               VT.getScalarType(),
-                               Node->getOperand(1), DAG.getIntPtrConstant(Idx));
-      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
-                                    VT.getScalarType(), Ex, Sh));
-    }
-    Result = DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
-                         &Scalars[0], Scalars.size());
-    break;
-  }
-
-  case ISD::BUILD_VECTOR:
-    switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
-    default: assert(0 && "This action is not supported yet!");
-    case TargetLowering::Custom:
-      Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.getNode()) {
-        Result = Tmp3;
-        break;
-      }
-      // FALLTHROUGH
-    case TargetLowering::Expand:
-      Result = ExpandBUILD_VECTOR(Result.getNode());
-      break;
-    }
-    break;
-  case ISD::CALLSEQ_START: {
-    SDNode *CallEnd = FindCallEndFromCallStart(Node);
-
-    // Recursively Legalize all of the inputs of the call end that do not lead
-    // to this call start.  This ensures that any libcalls that need be inserted
-    // are inserted *before* the CALLSEQ_START.
-    {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
-    for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
-      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
-                                   NodesLeadingTo);
-    }
-
-    // Now that we have legalized all of the inputs (which may have inserted
-    // libcalls), create the new CALLSEQ_START node.
-    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
-
-    // Merge in the last call to ensure that this call starts after the last
-    // call ended.
-    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
-      Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
-                         Tmp1, LastCALLSEQ_END);
-      Tmp1 = LegalizeOp(Tmp1);
-    }
-
-    // Do not try to legalize the target-specific arguments (#1+).
-    if (Tmp1 != Node->getOperand(0)) {
-      SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
-      Ops[0] = Tmp1;
-      Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
-                                              Ops.size()), Result.getResNo());
-    }
-
-    // Remember that the CALLSEQ_START is legalized.
-    AddLegalizedOperand(Op.getValue(0), Result);
-    if (Node->getNumValues() == 2)    // If this has a flag result, remember it.
-      AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
-
-    // Now that the callseq_start and all of the non-call nodes above this call
-    // sequence have been legalized, legalize the call itself.  During this
-    // process, no libcalls can/will be inserted, guaranteeing that no calls
-    // can overlap.
-    assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
-    // Note that we are selecting this call!
-    LastCALLSEQ_END = SDValue(CallEnd, 0);
-    IsLegalizingCall = true;
-
-    // Legalize the call, starting from the CALLSEQ_END.
-    LegalizeOp(LastCALLSEQ_END);
-    assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
-    return Result;
-  }
+  case ISD::CALLSEQ_START:
   case ISD::CALLSEQ_END:
-    // If the CALLSEQ_START node hasn't been legalized first, legalize it.  This
-    // will cause this node to be legalized as well as handling libcalls right.
-    if (LastCALLSEQ_END.getNode() != Node) {
-      LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
-      DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
-      assert(I != LegalizedNodes.end() &&
-             "Legalizing the call start should have legalized this node!");
-      return I->second;
-    }
-
-    // Otherwise, the call start has been legalized and everything is going
-    // according to plan.  Just legalize ourselves normally here.
-    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
-    // Do not try to legalize the target-specific arguments (#1+), except for
-    // an optional flag input.
-    if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
-      if (Tmp1 != Node->getOperand(0)) {
-        SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
-        Ops[0] = Tmp1;
-        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                                &Ops[0], Ops.size()),
-                         Result.getResNo());
-      }
-    } else {
-      Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
-      if (Tmp1 != Node->getOperand(0) ||
-          Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
-        SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
-        Ops[0] = Tmp1;
-        Ops.back() = Tmp2;
-        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                                &Ops[0], Ops.size()),
-                         Result.getResNo());
-      }
-    }
-    assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
-    // This finishes up call legalization.
-    IsLegalizingCall = false;
-
-    // If the CALLSEQ_END node has a flag, remember that we legalized it.
-    AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
-    if (Node->getNumValues() == 2)
-      AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.getResNo());
+    break;
   case ISD::LOAD: {
     LoadSDNode *LD = cast<LoadSDNode>(Node);
-    Tmp1 = LegalizeOp(LD->getChain());   // Legalize the chain.
-    Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
+    Tmp1 = LD->getChain();   // Legalize the chain.
+    Tmp2 = LD->getBasePtr(); // Legalize the base pointer.
 
     ISD::LoadExtType ExtType = LD->getExtensionType();
     if (ExtType == ISD::NON_EXTLOAD) {
       EVT VT = Node->getValueType(0);
-      Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                              Tmp1, Tmp2, LD->getOffset()),
-                       Result.getResNo());
-      Tmp3 = Result.getValue(0);
-      Tmp4 = Result.getValue(1);
+      Node = DAG.UpdateNodeOperands(Node, Tmp1, Tmp2, LD->getOffset());
+      Tmp3 = SDValue(Node, 0);
+      Tmp4 = SDValue(Node, 1);
 
       switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
       default: assert(0 && "This action is not supported yet!");
@@ -1148,20 +888,16 @@
           Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
           unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
           if (LD->getAlignment() < ABIAlignment){
-            Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
-                                         DAG, TLI);
-            Tmp3 = Result.getOperand(0);
-            Tmp4 = Result.getOperand(1);
-            Tmp3 = LegalizeOp(Tmp3);
-            Tmp4 = LegalizeOp(Tmp4);
+            ExpandUnalignedLoad(cast<LoadSDNode>(Node),
+                                DAG, TLI, Tmp3, Tmp4);
           }
         }
         break;
       case TargetLowering::Custom:
         Tmp1 = TLI.LowerOperation(Tmp3, DAG);
         if (Tmp1.getNode()) {
-          Tmp3 = LegalizeOp(Tmp1);
-          Tmp4 = LegalizeOp(Tmp1.getValue(1));
+          Tmp3 = Tmp1;
+          Tmp4 = Tmp1.getValue(1);
         }
         break;
       case TargetLowering::Promote: {
@@ -1173,16 +909,16 @@
         Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
                            LD->isVolatile(), LD->isNonTemporal(),
                            LD->getAlignment());
-        Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
-        Tmp4 = LegalizeOp(Tmp1.getValue(1));
+        Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1);
+        Tmp4 = Tmp1.getValue(1);
         break;
       }
       }
       // Since loads produce two values, make sure to remember that we
       // legalized both of them.
-      AddLegalizedOperand(SDValue(Node, 0), Tmp3);
-      AddLegalizedOperand(SDValue(Node, 1), Tmp4);
-      return Op.getResNo() ? Tmp4 : Tmp3;
+      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3);
+      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4);
+      return;
     }
 
     EVT SrcVT = LD->getMemoryVT();
@@ -1213,9 +949,10 @@
       ISD::LoadExtType NewExtType =
         ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
 
-      Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
-                              Tmp1, Tmp2, LD->getPointerInfo(),
-                              NVT, isVolatile, isNonTemporal, Alignment);
+      SDValue Result =
+        DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
+                       Tmp1, Tmp2, LD->getPointerInfo(),
+                       NVT, isVolatile, isNonTemporal, Alignment);
 
       Ch = Result.getValue(1); // The chain.
 
@@ -1230,8 +967,8 @@
                              Result.getValueType(), Result,
                              DAG.getValueType(SrcVT));
 
-      Tmp1 = LegalizeOp(Result);
-      Tmp2 = LegalizeOp(Ch);
+      Tmp1 = Result;
+      Tmp2 = Ch;
     } else if (SrcWidth & (SrcWidth - 1)) {
       // If not loading a power-of-2 number of bits, expand as two loads.
       assert(!SrcVT.isVector() && "Unsupported extload!");
@@ -1274,7 +1011,7 @@
                                       TLI.getShiftAmountTy(Hi.getValueType())));
 
         // Join the hi and lo parts.
-        Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
+        Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
       } else {
         // Big endian - avoid unaligned loads.
         // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD at +2:i8
@@ -1304,11 +1041,10 @@
                                       TLI.getShiftAmountTy(Hi.getValueType())));
 
         // Join the hi and lo parts.
-        Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
+        Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
       }
 
-      Tmp1 = LegalizeOp(Result);
-      Tmp2 = LegalizeOp(Ch);
+      Tmp2 = Ch;
     } else {
       switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
       default: assert(0 && "This action is not supported yet!");
@@ -1316,17 +1052,16 @@
         isCustom = true;
         // FALLTHROUGH
       case TargetLowering::Legal:
-        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                                Tmp1, Tmp2, LD->getOffset()),
-                         Result.getResNo());
-        Tmp1 = Result.getValue(0);
-        Tmp2 = Result.getValue(1);
+        Node = DAG.UpdateNodeOperands(Node,
+                                      Tmp1, Tmp2, LD->getOffset());
+        Tmp1 = SDValue(Node, 0);
+        Tmp2 = SDValue(Node, 1);
 
         if (isCustom) {
-          Tmp3 = TLI.LowerOperation(Result, DAG);
+          Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG);
           if (Tmp3.getNode()) {
-            Tmp1 = LegalizeOp(Tmp3);
-            Tmp2 = LegalizeOp(Tmp3.getValue(1));
+            Tmp1 = Tmp3;
+            Tmp2 = Tmp3.getValue(1);
           }
         } else {
           // If this is an unaligned load and the target doesn't support it,
@@ -1337,12 +1072,8 @@
             unsigned ABIAlignment =
               TLI.getTargetData()->getABITypeAlignment(Ty);
             if (LD->getAlignment() < ABIAlignment){
-              Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
-                                           DAG, TLI);
-              Tmp1 = Result.getOperand(0);
-              Tmp2 = Result.getOperand(1);
-              Tmp1 = LegalizeOp(Tmp1);
-              Tmp2 = LegalizeOp(Tmp2);
+              ExpandUnalignedLoad(cast<LoadSDNode>(Node),
+                                  DAG, TLI, Tmp1, Tmp2);
             }
           }
         }
@@ -1363,9 +1094,8 @@
           case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
           default: llvm_unreachable("Unexpected extend load type!");
           }
-          Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
-          Tmp1 = LegalizeOp(Result);  // Relegalize new nodes.
-          Tmp2 = LegalizeOp(Load.getValue(1));
+          Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
+          Tmp2 = Load.getValue(1);
           break;
         }
 
@@ -1380,10 +1110,10 @@
                "EXTLOAD should always be supported!");
         // Turn the unsupported load into an EXTLOAD followed by an explicit
         // zero/sign extend inreg.
-        Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
-                                Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
-                                LD->isVolatile(), LD->isNonTemporal(),
-                                LD->getAlignment());
+        SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
+                                        Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
+                                        LD->isVolatile(), LD->isNonTemporal(),
+                                        LD->getAlignment());
         SDValue ValRes;
         if (ExtType == ISD::SEXTLOAD)
           ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
@@ -1391,38 +1121,37 @@
                                Result, DAG.getValueType(SrcVT));
         else
           ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
-        Tmp1 = LegalizeOp(ValRes);  // Relegalize new nodes.
-        Tmp2 = LegalizeOp(Result.getValue(1));  // Relegalize new nodes.
+        Tmp1 = ValRes;
+        Tmp2 = Result.getValue(1);
         break;
       }
     }
 
     // Since loads produce two values, make sure to remember that we legalized
     // both of them.
-    AddLegalizedOperand(SDValue(Node, 0), Tmp1);
-    AddLegalizedOperand(SDValue(Node, 1), Tmp2);
-    return Op.getResNo() ? Tmp2 : Tmp1;
+    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1);
+    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2);
+    break;
   }
   case ISD::STORE: {
     StoreSDNode *ST = cast<StoreSDNode>(Node);
-    Tmp1 = LegalizeOp(ST->getChain());    // Legalize the chain.
-    Tmp2 = LegalizeOp(ST->getBasePtr());  // Legalize the pointer.
+    Tmp1 = ST->getChain();
+    Tmp2 = ST->getBasePtr();
     unsigned Alignment = ST->getAlignment();
     bool isVolatile = ST->isVolatile();
     bool isNonTemporal = ST->isNonTemporal();
 
     if (!ST->isTruncatingStore()) {
       if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
-        Result = SDValue(OptStore, 0);
+        DAG.ReplaceAllUsesWith(ST, OptStore, this);
         break;
       }
 
       {
-        Tmp3 = LegalizeOp(ST->getValue());
-        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                                Tmp1, Tmp3, Tmp2,
-                                                ST->getOffset()),
-                         Result.getResNo());
+        Tmp3 = ST->getValue();
+        Node = DAG.UpdateNodeOperands(Node,
+                                      Tmp1, Tmp3, Tmp2,
+                                      ST->getOffset());
 
         EVT VT = Tmp3.getValueType();
         switch (TLI.getOperationAction(ISD::STORE, VT)) {
@@ -1434,27 +1163,31 @@
             Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
             unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
             if (ST->getAlignment() < ABIAlignment)
-              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
-                                            DAG, TLI);
+              ExpandUnalignedStore(cast<StoreSDNode>(Node),
+                                   DAG, TLI, this);
           }
           break;
         case TargetLowering::Custom:
-          Tmp1 = TLI.LowerOperation(Result, DAG);
-          if (Tmp1.getNode()) Result = Tmp1;
+          Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
+          if (Tmp1.getNode())
+            DAG.ReplaceAllUsesWith(SDValue(Node, 0), Tmp1, this);
           break;
-        case TargetLowering::Promote:
+        case TargetLowering::Promote: {
           assert(VT.isVector() && "Unknown legal promote case!");
           Tmp3 = DAG.getNode(ISD::BITCAST, dl,
                              TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
-          Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
-                                ST->getPointerInfo(), isVolatile,
-                                isNonTemporal, Alignment);
+          SDValue Result =
+            DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
+                         ST->getPointerInfo(), isVolatile,
+                         isNonTemporal, Alignment);
+          DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
           break;
         }
+        }
         break;
       }
     } else {
-      Tmp3 = LegalizeOp(ST->getValue());
+      Tmp3 = ST->getValue();
 
       EVT StVT = ST->getMemoryVT();
       unsigned StWidth = StVT.getSizeInBits();
@@ -1466,8 +1199,10 @@
         EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
                                     StVT.getStoreSizeInBits());
         Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
-        Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
-                                   NVT, isVolatile, isNonTemporal, Alignment);
+        SDValue Result =
+          DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                            NVT, isVolatile, isNonTemporal, Alignment);
+        DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
       } else if (StWidth & (StWidth - 1)) {
         // If not storing a power-of-2 number of bits, expand as two stores.
         assert(!StVT.isVector() && "Unsupported truncstore!");
@@ -1521,14 +1256,13 @@
         }
 
         // The order of the stores doesn't matter.
-        Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+        SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+        DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
       } else {
         if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
             Tmp2 != ST->getBasePtr())
-          Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
-                                                  Tmp1, Tmp3, Tmp2,
-                                                  ST->getOffset()),
-                           Result.getResNo());
+          Node = DAG.UpdateNodeOperands(Node, Tmp1, Tmp3, Tmp2,
+                                        ST->getOffset());
 
         switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
         default: assert(0 && "This action is not supported yet!");
@@ -1539,12 +1273,13 @@
             Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
             unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
             if (ST->getAlignment() < ABIAlignment)
-              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
-                                            DAG, TLI);
+              ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
           }
           break;
         case TargetLowering::Custom:
-          Result = TLI.LowerOperation(Result, DAG);
+          DAG.ReplaceAllUsesWith(SDValue(Node, 0),
+                                 TLI.LowerOperation(SDValue(Node, 0), DAG),
+                                 this);
           break;
         case TargetLowering::Expand:
           assert(!StVT.isVector() &&
@@ -1553,8 +1288,10 @@
           // TRUNCSTORE:i16 i32 -> STORE i16
           assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
           Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
-          Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
-                                isVolatile, isNonTemporal, Alignment);
+          SDValue Result =
+            DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                         isVolatile, isNonTemporal, Alignment);
+          DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
           break;
         }
       }
@@ -1562,17 +1299,6 @@
     break;
   }
   }
-  assert(Result.getValueType() == Op.getValueType() &&
-         "Bad legalization!");
-
-  // Make sure that the generated code is itself legal.
-  if (Result != Op)
-    Result = LegalizeOp(Result);
-
-  // Note that LegalizeOp may be reentered even from single-use nodes, which
-  // means that we always must cache transformed nodes.
-  AddLegalizedOperand(Op, Result);
-  return Result;
 }
 
 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
@@ -2011,7 +1737,6 @@
 // and leave the Hi part unset.
 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
                                             bool isSigned) {
-  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
   // The input chain to this libcall is the entry node of the function.
   // Legalizing the call will automatically add the previous call to the
   // dependence.
@@ -2030,7 +1755,6 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
-  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
 
   // isTailCall may be true since the callee does not reference caller stack
@@ -2046,10 +1770,6 @@
     // It's a tailcall, return the chain (which is the DAG root).
     return DAG.getRoot();
 
-  // Legalize the call sequence, starting with the chain.  This will advance
-  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
-  // was added by LowerCallTo (guaranteeing proper serialization of calls).
-  LegalizeOp(CallInfo.second);
   return CallInfo.first;
 }
 
@@ -2079,11 +1799,6 @@
                   /*isReturnValueUsed=*/true,
                   Callee, Args, DAG, dl);
 
-  // Legalize the call sequence, starting with the chain.  This will advance
-  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
-  // was added by LowerCallTo (guaranteeing proper serialization of calls).
-  LegalizeOp(CallInfo.second);
-
   return CallInfo.first;
 }
 
@@ -2093,7 +1808,6 @@
 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
                                          SDNode *Node,
                                          bool isSigned) {
-  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
   SDValue InChain = Node->getOperand(0);
 
   TargetLowering::ArgListTy Args;
@@ -2110,7 +1824,6 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
-  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
@@ -2118,10 +1831,6 @@
                     /*isReturnValueUsed=*/true,
                     Callee, Args, DAG, Node->getDebugLoc());
 
-  // Legalize the call sequence, starting with the chain.  This will advance
-  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
-  // was added by LowerCallTo (guaranteeing proper serialization of calls).
-  LegalizeOp(CallInfo.second);
   return CallInfo;
 }
 
@@ -2247,20 +1956,14 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
-  // Splice the libcall in wherever FindInputOutputChains tells us to.
   DebugLoc dl = Node->getDebugLoc();
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
                     0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
                     /*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
 
-  // Legalize the call sequence, starting with the chain.  This will advance
-  // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
-  // was added by LowerCallTo (guaranteeing proper serialization of calls).
-  LegalizeOp(CallInfo.second);
-
   // Remainder is loaded back from the stack frame.
-  SDValue Rem = DAG.getLoad(RetVT, dl, LastCALLSEQ_END, FIPtr,
+  SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
                             MachinePointerInfo(), false, false, 0);
   Results.push_back(CallInfo.first);
   Results.push_back(Rem);
@@ -2452,11 +2155,13 @@
                              MachinePointerInfo::getConstantPool(),
                              false, false, Alignment);
   else {
-    FudgeInReg =
-      LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
-                                DAG.getEntryNode(), CPIdx,
-                                MachinePointerInfo::getConstantPool(),
-                                MVT::f32, false, false, Alignment));
+    SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
+                                  DAG.getEntryNode(), CPIdx,
+                                  MachinePointerInfo::getConstantPool(),
+                                  MVT::f32, false, false, Alignment);
+    HandleSDNode Handle(Load);
+    LegalizeOp(Load.getNode());
+    FudgeInReg = Handle.getValue();
   }
 
   return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
@@ -2780,8 +2485,8 @@
   return ExpandChainLibCall(LC, Node, false);
 }
 
-void SelectionDAGLegalize::ExpandNode(SDNode *Node,
-                                      SmallVectorImpl<SDValue> &Results) {
+void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
+  SmallVector<SDValue, 8> Results;
   DebugLoc dl = Node->getDebugLoc();
   SDValue Tmp1, Tmp2, Tmp3, Tmp4;
   switch (Node->getOpcode()) {
@@ -3229,10 +2934,8 @@
     ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
     // Check to see if this FP immediate is already legal.
     // If this is a legal constant, turn it into a TargetConstantFP node.
-    if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
-      Results.push_back(SDValue(Node, 0));
-    else
-      Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
+    if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
+      Results.push_back(ExpandConstantFP(CFP, true));
     break;
   }
   case ISD::EHSELECTION: {
@@ -3478,6 +3181,10 @@
                                DAG.getIntPtrConstant(0));
       TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
                             DAG.getIntPtrConstant(1));
+      // Ret is a node with an illegal type. Because such things are not
+      // generally permitted during this phase of legalization, delete the
+      // node. The above EXTRACT_ELEMENT nodes should have been folded.
+      DAG.DeleteNode(Ret.getNode());
     }
 
     if (isSigned) {
@@ -3618,7 +3325,6 @@
 
     LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
                           Tmp2, Tmp3, Tmp4, dl);
-    LastCALLSEQ_END = DAG.getEntryNode();
 
     assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
     Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
@@ -3628,6 +3334,35 @@
     Results.push_back(Tmp1);
     break;
   }
+  case ISD::BUILD_VECTOR:
+    Results.push_back(ExpandBUILD_VECTOR(Node));
+    break;
+  case ISD::SRA:
+  case ISD::SRL:
+  case ISD::SHL: {
+    // Scalarize vector SRA/SRL/SHL.
+    EVT VT = Node->getValueType(0);
+    assert(VT.isVector() && "Unable to legalize non-vector shift");
+    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
+    unsigned NumElem = VT.getVectorNumElements();
+
+    SmallVector<SDValue, 8> Scalars;
+    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
+      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+                               VT.getScalarType(),
+                               Node->getOperand(0), DAG.getIntPtrConstant(Idx));
+      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+                               VT.getScalarType(),
+                               Node->getOperand(1), DAG.getIntPtrConstant(Idx));
+      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
+                                    VT.getScalarType(), Ex, Sh));
+    }
+    SDValue Result =
+      DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
+                  &Scalars[0], Scalars.size());
+    DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
+    break;
+  }
   case ISD::GLOBAL_OFFSET_TABLE:
   case ISD::GlobalAddress:
   case ISD::GlobalTLSAddress:
@@ -3638,13 +3373,16 @@
   case ISD::INTRINSIC_WO_CHAIN:
   case ISD::INTRINSIC_VOID:
     // FIXME: Custom lowering for these operations shouldn't return null!
-    for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
-      Results.push_back(SDValue(Node, i));
     break;
   }
+
+  // Replace the original node with the legalized result.
+  if (!Results.empty())
+    DAG.ReplaceAllUsesWith(Node, Results.data(), this);
 }
-void SelectionDAGLegalize::PromoteNode(SDNode *Node,
-                                       SmallVectorImpl<SDValue> &Results) {
+
+void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
+  SmallVector<SDValue, 8> Results;
   EVT OVT = Node->getValueType(0);
   if (Node->getOpcode() == ISD::UINT_TO_FP ||
       Node->getOpcode() == ISD::SINT_TO_FP ||
@@ -3772,6 +3510,10 @@
     break;
   }
   }
+
+  // Replace the original node with the legalized result.
+  if (!Results.empty())
+    DAG.ReplaceAllUsesWith(Node, Results.data(), this);
 }
 
 // SelectionDAG::Legalize - This is the entry point for the file.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Fri Oct 28 12:55:38 2011
@@ -1084,7 +1084,6 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
-  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Oct 28 12:55:38 2011
@@ -315,8 +315,10 @@
   IssueCount = 0;
   MinAvailableCycle = DisableSchedCycles ? 0 : UINT_MAX;
   NumLiveRegs = 0;
-  LiveRegDefs.resize(TRI->getNumRegs(), NULL);
-  LiveRegGens.resize(TRI->getNumRegs(), NULL);
+  // Allocate slots for each physical register, plus one for a special register
+  // to track the virtual resource of a calling sequence.
+  LiveRegDefs.resize(TRI->getNumRegs() + 1, NULL);
+  LiveRegGens.resize(TRI->getNumRegs() + 1, NULL);
 
   // Build the scheduling graph.
   BuildSchedGraph(NULL);
@@ -386,6 +388,90 @@
   }
 }
 
+/// IsChainDependent - Test if Outer is reachable from Inner through
+/// chain dependencies.
+static bool IsChainDependent(SDNode *Outer, SDNode *Inner) {
+  SDNode *N = Outer;
+  for (;;) {
+    if (N == Inner)
+      return true;
+    if (N->getOpcode() == ISD::TokenFactor) {
+      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+        if (IsChainDependent(N->getOperand(i).getNode(), Inner))
+          return true;
+      return false;
+    }
+    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+      if (N->getOperand(i).getValueType() == MVT::Other) {
+        N = N->getOperand(i).getNode();
+        goto found_chain_operand;
+      }
+    return false;
+  found_chain_operand:;
+    if (N->getOpcode() == ISD::EntryToken)
+      return false;
+  }
+}
+
+/// FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate
+/// the corresponding (lowered) CALLSEQ_BEGIN node.
+///
+/// NestLevel and MaxNested are used in recursion to indcate the current level
+/// of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum
+/// level seen so far.
+///
+/// TODO: It would be better to give CALLSEQ_END an explicit operand to point
+/// to the corresponding CALLSEQ_BEGIN to avoid needing to search for it.
+static SDNode *
+FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest,
+                 const TargetInstrInfo *TII) {
+  for (;;) {
+    // For a TokenFactor, examine each operand. There may be multiple ways
+    // to get to the CALLSEQ_BEGIN, but we need to find the path with the
+    // most nesting in order to ensure that we find the corresponding match.
+    if (N->getOpcode() == ISD::TokenFactor) {
+      SDNode *Best = 0;
+      unsigned BestMaxNest = MaxNest;
+      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
+        unsigned MyNestLevel = NestLevel;
+        unsigned MyMaxNest = MaxNest;
+        if (SDNode *New = FindCallSeqStart(N->getOperand(i).getNode(),
+                                           MyNestLevel, MyMaxNest, TII))
+          if (!Best || (MyMaxNest > BestMaxNest)) {
+            Best = New;
+            BestMaxNest = MyMaxNest;
+          }
+      }
+      assert(Best);
+      MaxNest = BestMaxNest;
+      return Best;
+    }
+    // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
+    if (N->isMachineOpcode()) {
+      if (N->getMachineOpcode() ==
+          (unsigned)TII->getCallFrameDestroyOpcode()) {
+        ++NestLevel;
+        MaxNest = std::max(MaxNest, NestLevel);
+      } else if (N->getMachineOpcode() ==
+                 (unsigned)TII->getCallFrameSetupOpcode()) {
+        --NestLevel;
+        if (NestLevel == 0)
+          return N;
+      }
+    }
+    // Otherwise, find the chain and continue climbing.
+    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+      if (N->getOperand(i).getValueType() == MVT::Other) {
+        N = N->getOperand(i).getNode();
+        goto found_chain_operand;
+      }
+    return 0;
+  found_chain_operand:;
+    if (N->getOpcode() == ISD::EntryToken)
+      return 0;
+  }
+}
+
 /// Call ReleasePred for each predecessor, then update register live def/gen.
 /// Always update LiveRegDefs for a register dependence even if the current SU
 /// also defines the register. This effectively create one large live range
@@ -423,6 +509,25 @@
       }
     }
   }
+
+  // If we're scheduling a lowered CALLSEQ_END, find the corresponding CALLSEQ_BEGIN.
+  // Inject an artificial physical register dependence between these nodes, to
+  // prevent other calls from being interscheduled with them.
+  unsigned CallResource = TRI->getNumRegs();
+  if (!LiveRegDefs[CallResource])
+    for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode())
+      if (Node->isMachineOpcode() &&
+          Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
+        unsigned NestLevel = 0;
+        unsigned MaxNest = 0;
+        SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
+
+        SUnit *Def = &SUnits[N->getNodeId()];
+        ++NumLiveRegs;
+        LiveRegDefs[CallResource] = Def;
+        LiveRegGens[CallResource] = SU;
+        break;
+      }
 }
 
 /// Check to see if any of the pending instructions are ready to issue.  If
@@ -605,6 +710,20 @@
       LiveRegGens[I->getReg()] = NULL;
     }
   }
+  // Release the special call resource dependence, if this is the beginning
+  // of a call.
+  unsigned CallResource = TRI->getNumRegs();
+  if (LiveRegDefs[CallResource] == SU)
+    for (const SDNode *SUNode = SU->getNode(); SUNode;
+         SUNode = SUNode->getGluedNode()) {
+      if (SUNode->isMachineOpcode() &&
+          SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
+        assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
+        --NumLiveRegs;
+        LiveRegDefs[CallResource] = NULL;
+        LiveRegGens[CallResource] = NULL;
+      }
+    }
 
   resetVRegCycle(SU);
 
@@ -661,6 +780,33 @@
     }
   }
 
+  // Reclaim the special call resource dependence, if this is the beginning
+  // of a call.
+  unsigned CallResource = TRI->getNumRegs();
+  for (const SDNode *SUNode = SU->getNode(); SUNode;
+       SUNode = SUNode->getGluedNode()) {
+    if (SUNode->isMachineOpcode() &&
+        SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
+      ++NumLiveRegs;
+      LiveRegDefs[CallResource] = SU;
+      LiveRegGens[CallResource] = NULL;
+    }
+  }
+
+  // Release the special call resource dependence, if this is the end
+  // of a call.
+  if (LiveRegGens[CallResource] == SU)
+    for (const SDNode *SUNode = SU->getNode(); SUNode;
+         SUNode = SUNode->getGluedNode()) {
+      if (SUNode->isMachineOpcode() &&
+          SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
+        assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
+        --NumLiveRegs;
+        LiveRegDefs[CallResource] = NULL;
+        LiveRegGens[CallResource] = NULL;
+      }
+    }
+
   for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
        I != E; ++I) {
     if (I->isAssignedRegDep()) {
@@ -1083,6 +1229,21 @@
 
     if (!Node->isMachineOpcode())
       continue;
+    // If we're in the middle of scheduling a call, don't begin scheduling
+    // another call. Also, don't allow any physical registers to be live across
+    // the call.
+    if (Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
+      // Add one here so that we include the special calling-sequence resource.
+      for (unsigned i = 0, e = TRI->getNumRegs() + 1; i != e; ++i)
+        if (LiveRegDefs[i]) {
+          SDNode *Gen = LiveRegGens[i]->getNode();
+          while (SDNode *Glued = Gen->getGluedNode())
+            Gen = Glued;
+          if (!IsChainDependent(Gen, Node) && RegAdded.insert(i))
+            LRegs.push_back(i);
+        }
+      continue;
+    }
     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
     if (!MCID.ImplicitDefs)
       continue;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Oct 28 12:55:38 2011
@@ -5290,6 +5290,10 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
+
+  // If we just RAUW'd the root, take note.
+  if (FromN == getRoot())
+    setRoot(To);
 }
 
 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
@@ -5335,6 +5339,10 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
+
+  // If we just RAUW'd the root, take note.
+  if (From == getRoot().getNode())
+    setRoot(SDValue(To, getRoot().getResNo()));
 }
 
 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
@@ -5373,6 +5381,10 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
+
+  // If we just RAUW'd the root, take note.
+  if (From == getRoot().getNode())
+    setRoot(SDValue(To[getRoot().getResNo()]));
 }
 
 /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
@@ -5431,6 +5443,10 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
+
+  // If we just RAUW'd the root, take note.
+  if (From == getRoot())
+    setRoot(To);
 }
 
 namespace {

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Oct 28 12:55:38 2011
@@ -1353,12 +1353,10 @@
       SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
       SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
                                          MVT::i32);
-      // TODO: Disable AlwaysInline when it becomes possible
-      //       to emit a nested call sequence.
       MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
                                           Flags.getByValAlign(),
                                           /*isVolatile=*/false,
-                                          /*AlwaysInline=*/true,
+                                          /*AlwaysInline=*/false,
                                           MachinePointerInfo(0),
                                           MachinePointerInfo(0)));
 
@@ -4350,9 +4348,24 @@
       // If this is undef splat, generate it via "just" vdup, if possible.
       if (Lane == -1) Lane = 0;
 
+      // Test if V1 is a SCALAR_TO_VECTOR.
       if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
         return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
       }
+      // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
+      // (and probably will turn into a SCALAR_TO_VECTOR once legalization
+      // reaches it).
+      if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
+          !isa<ConstantSDNode>(V1.getOperand(0))) {
+        bool IsScalarToVector = true;
+        for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
+          if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
+            IsScalarToVector = false;
+            break;
+          }
+        if (IsScalarToVector)
+          return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
+      }
       return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
                          DAG.getConstant(Lane, MVT::i32));
     }

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Oct 28 12:55:38 2011
@@ -2114,7 +2114,9 @@
         HasNoSignedComparisonUses(Node))
       // Look past the truncate if CMP is the only use of it.
       N0 = N0.getOperand(0);
-    if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
+    if ((N0.getNode()->getOpcode() == ISD::AND ||
+         (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
+        N0.getNode()->hasOneUse() &&
         N0.getValueType() != MVT::i8 &&
         X86::isZeroNode(N1)) {
       ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Oct 28 12:55:38 2011
@@ -4220,6 +4220,29 @@
   return true;
 }
 
+// Test whether the given value is a vector value which will be legalized
+// into a load.
+static bool WillBeConstantPoolLoad(SDNode *N) {
+  if (N->getOpcode() != ISD::BUILD_VECTOR)
+    return false;
+
+  // Check for any non-constant elements.
+  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+    switch (N->getOperand(i).getNode()->getOpcode()) {
+    case ISD::UNDEF:
+    case ISD::ConstantFP:
+    case ISD::Constant:
+      break;
+    default:
+      return false;
+    }
+
+  // Vectors of all-zeros and all-ones are materialized with special
+  // instructions rather than being loaded.
+  return !ISD::isBuildVectorAllZeros(N) &&
+         !ISD::isBuildVectorAllOnes(N);
+}
+
 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
 /// match movlp{s|d}. The lower half elements should come from lower half of
 /// V1 (and in order), and the upper half elements should come from the upper
@@ -4235,7 +4258,7 @@
     return false;
   // Is V2 is a vector load, don't do this transformation. We will try to use
   // load folding shufps op.
-  if (ISD::isNON_EXTLoad(V2))
+  if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
     return false;
 
   unsigned NumElems = VT.getVectorNumElements();
@@ -6351,6 +6374,8 @@
   if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
     CanFoldLoad = true;
 
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
+
   // Both of them can't be memory operations though.
   if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
     CanFoldLoad = false;
@@ -6360,10 +6385,11 @@
       return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
 
     if (NumElems == 4)
-      return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
+      // If we don't care about the second element, procede to use movss.
+      if (SVOp->getMaskElt(1) != -1)
+        return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
   }
 
-  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
   // movl and movlp will both match v2i64, but v2i64 is never matched by
   // movl earlier because we make it strict to avoid messing with the movlp load
   // folding logic (see the code above getMOVLP call). Match it here then,
@@ -8681,8 +8707,9 @@
 
   // If condition flag is set by a X86ISD::CMP, then use it as the condition
   // setting operand in place of the X86ISD::SETCC.
-  if (Cond.getOpcode() == X86ISD::SETCC ||
-      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
+  unsigned CondOpcode = Cond.getOpcode();
+  if (CondOpcode == X86ISD::SETCC ||
+      CondOpcode == X86ISD::SETCC_CARRY) {
     CC = Cond.getOperand(0);
 
     SDValue Cmp = Cond.getOperand(1);
@@ -8699,6 +8726,39 @@
       Cond = Cmp;
       addTest = false;
     }
+  } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
+             CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
+             ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
+              Cond.getOperand(0).getValueType() != MVT::i8)) {
+    SDValue LHS = Cond.getOperand(0);
+    SDValue RHS = Cond.getOperand(1);
+    unsigned X86Opcode;
+    unsigned X86Cond;
+    SDVTList VTs;
+    switch (CondOpcode) {
+    case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
+    case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
+    case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
+    case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
+    case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
+    case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
+    default: llvm_unreachable("unexpected overflowing operator");
+    }
+    if (CondOpcode == ISD::UMULO)
+      VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
+                          MVT::i32);
+    else
+      VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
+
+    SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
+
+    if (CondOpcode == ISD::UMULO)
+      Cond = X86Op.getValue(2);
+    else
+      Cond = X86Op.getValue(1);
+
+    CC = DAG.getConstant(X86Cond, MVT::i8);
+    addTest = false;
   }
 
   if (addTest) {
@@ -8780,11 +8840,27 @@
   SDValue Dest  = Op.getOperand(2);
   DebugLoc dl = Op.getDebugLoc();
   SDValue CC;
+  bool Inverted = false;
 
   if (Cond.getOpcode() == ISD::SETCC) {
-    SDValue NewCond = LowerSETCC(Cond, DAG);
-    if (NewCond.getNode())
-      Cond = NewCond;
+    // Check for setcc([su]{add,sub,mul}o == 0).
+    if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
+        isa<ConstantSDNode>(Cond.getOperand(1)) &&
+        cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
+        Cond.getOperand(0).getResNo() == 1 &&
+        (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
+         Cond.getOperand(0).getOpcode() == ISD::UADDO ||
+         Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
+         Cond.getOperand(0).getOpcode() == ISD::USUBO ||
+         Cond.getOperand(0).getOpcode() == ISD::SMULO ||
+         Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
+      Inverted = true;
+      Cond = Cond.getOperand(0);
+    } else {
+      SDValue NewCond = LowerSETCC(Cond, DAG);
+      if (NewCond.getNode())
+        Cond = NewCond;
+    }
   }
 #if 0
   // FIXME: LowerXALUO doesn't handle these!!
@@ -8805,8 +8881,9 @@
 
   // If condition flag is set by a X86ISD::CMP, then use it as the condition
   // setting operand in place of the X86ISD::SETCC.
-  if (Cond.getOpcode() == X86ISD::SETCC ||
-      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
+  unsigned CondOpcode = Cond.getOpcode();
+  if (CondOpcode == X86ISD::SETCC ||
+      CondOpcode == X86ISD::SETCC_CARRY) {
     CC = Cond.getOperand(0);
 
     SDValue Cmp = Cond.getOperand(1);
@@ -8827,6 +8904,43 @@
         break;
       }
     }
+  }
+  CondOpcode = Cond.getOpcode();
+  if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
+      CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
+      ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
+       Cond.getOperand(0).getValueType() != MVT::i8)) {
+    SDValue LHS = Cond.getOperand(0);
+    SDValue RHS = Cond.getOperand(1);
+    unsigned X86Opcode;
+    unsigned X86Cond;
+    SDVTList VTs;
+    switch (CondOpcode) {
+    case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
+    case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
+    case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
+    case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
+    case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
+    case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
+    default: llvm_unreachable("unexpected overflowing operator");
+    }
+    if (Inverted)
+      X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
+    if (CondOpcode == ISD::UMULO)
+      VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
+                          MVT::i32);
+    else
+      VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
+
+    SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
+
+    if (CondOpcode == ISD::UMULO)
+      Cond = X86Op.getValue(2);
+    else
+      Cond = X86Op.getValue(1);
+
+    CC = DAG.getConstant(X86Cond, MVT::i8);
+    addTest = false;
   } else {
     unsigned CondOpc;
     if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
@@ -8890,6 +9004,66 @@
       CC = DAG.getConstant(CCode, MVT::i8);
       Cond = Cond.getOperand(0).getOperand(1);
       addTest = false;
+    } else if (Cond.getOpcode() == ISD::SETCC &&
+               cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
+      // For FCMP_OEQ, we can emit
+      // two branches instead of an explicit AND instruction with a
+      // separate test. However, we only do this if this block doesn't
+      // have a fall-through edge, because this requires an explicit
+      // jmp when the condition is false.
+      if (Op.getNode()->hasOneUse()) {
+        SDNode *User = *Op.getNode()->use_begin();
+        // Look for an unconditional branch following this conditional branch.
+        // We need this because we need to reverse the successors in order
+        // to implement FCMP_OEQ.
+        if (User->getOpcode() == ISD::BR) {
+          SDValue FalseBB = User->getOperand(1);
+          SDNode *NewBR =
+            DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
+          assert(NewBR == User);
+          (void)NewBR;
+          Dest = FalseBB;
+
+          SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
+                                    Cond.getOperand(0), Cond.getOperand(1));
+          CC = DAG.getConstant(X86::COND_NE, MVT::i8);
+          Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
+                              Chain, Dest, CC, Cmp);
+          CC = DAG.getConstant(X86::COND_P, MVT::i8);
+          Cond = Cmp;
+          addTest = false;
+        }
+      }
+    } else if (Cond.getOpcode() == ISD::SETCC &&
+               cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
+      // For FCMP_UNE, we can emit
+      // two branches instead of an explicit AND instruction with a
+      // separate test. However, we only do this if this block doesn't
+      // have a fall-through edge, because this requires an explicit
+      // jmp when the condition is false.
+      if (Op.getNode()->hasOneUse()) {
+        SDNode *User = *Op.getNode()->use_begin();
+        // Look for an unconditional branch following this conditional branch.
+        // We need this because we need to reverse the successors in order
+        // to implement FCMP_UNE.
+        if (User->getOpcode() == ISD::BR) {
+          SDValue FalseBB = User->getOperand(1);
+          SDNode *NewBR =
+            DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
+          assert(NewBR == User);
+          (void)NewBR;
+
+          SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
+                                    Cond.getOperand(0), Cond.getOperand(1));
+          CC = DAG.getConstant(X86::COND_NE, MVT::i8);
+          Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
+                              Chain, Dest, CC, Cmp);
+          CC = DAG.getConstant(X86::COND_NP, MVT::i8);
+          Cond = Cmp;
+          addTest = false;
+          Dest = FalseBB;
+        }
+      }
     }
   }
 

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Fri Oct 28 12:55:38 2011
@@ -386,6 +386,15 @@
     Offset = off;
     return true;
   }
+  // Check for an aligned global variable.
+  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(*Root)) {
+    const GlobalValue *GV = GA->getGlobal();
+    if (GA->getOffset() == 0 && GV->getAlignment() >= 4) {
+      AlignedBase = Base;
+      Offset = off;
+      return true;
+    }
+  }
   return false;
 }
 

Modified: llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/and_ops.ll?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/and_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/and_ops.ll Fri Oct 28 12:55:38 2011
@@ -5,6 +5,9 @@
 ; RUN: grep andhi  %t1.s | count 30
 ; RUN: grep andbi  %t1.s | count 4
 
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll Fri Oct 28 12:55:38 2011
@@ -15,6 +15,9 @@
 ; RUN: grep ai      %t2.s | count 9
 ; RUN: grep dispatch_tab %t2.s | count 6
 
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 ; ModuleID = 'call_indirect.bc'
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
 target triple = "spu-unknown-elf"

Modified: llvm/trunk/test/CodeGen/CellSPU/nand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/nand.ll?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/nand.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/nand.ll Fri Oct 28 12:55:38 2011
@@ -3,6 +3,10 @@
 ; RUN: grep and    %t1.s | count 94
 ; RUN: grep xsbh   %t1.s | count 2
 ; RUN: grep xshw   %t1.s | count 4
+
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/or_ops.ll?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/or_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/or_ops.ll Fri Oct 28 12:55:38 2011
@@ -6,6 +6,9 @@
 ; RUN: grep orbi   %t1.s | count 15
 ; RUN: FileCheck %s < %t1.s
 
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/select_bits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/select_bits.ll?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/select_bits.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/select_bits.ll Fri Oct 28 12:55:38 2011
@@ -1,6 +1,9 @@
 ; RUN: llc < %s -march=cellspu > %t1.s
 ; RUN: grep selb   %t1.s | count 56
 
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/struct_1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/struct_1.ll?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/struct_1.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/struct_1.ll Fri Oct 28 12:55:38 2011
@@ -22,6 +22,9 @@
 ; RUN: grep shufb   %t2.s | count 7
 ; RUN: grep stqd    %t2.s | count 7
 
+; CellSPU legalization is over-sensitive to Legalize's traversal order.
+; XFAIL: *
+
 ; ModuleID = 'struct_1.bc'
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"

Modified: llvm/trunk/test/CodeGen/Mips/cprestore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cprestore.ll?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cprestore.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cprestore.ll Fri Oct 28 12:55:38 2011
@@ -1,8 +1,4 @@
-; DISABLED: llc -march=mipsel < %s | FileCheck %s
-; RUN: false
-
-; byval is currently unsupported.
-; XFAIL: *
+; RUN: llc -march=mipsel < %s | FileCheck %s
 
 ; CHECK: .set macro
 ; CHECK-NEXT: .cprestore

Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Fri Oct 28 12:55:38 2011
@@ -1,8 +1,4 @@
-; DISABLED: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
-; RUN: false
-
-; byval is currently unsupported.
-; XFAIL: *
+; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
 
 %struct.S1 = type { [65536 x i8] }
 

Modified: llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll Fri Oct 28 12:55:38 2011
@@ -1,11 +1,7 @@
-; DISABLED: llc -mtriple=thumbv6-apple-darwin < %s
-; RUN: false
+; RUN: llc -mtriple=thumbv6-apple-darwin < %s
 ; rdar://problem/9416774
 ; ModuleID = 'reduced.ll'
 
-; byval is currently unsupported.
-; XFAIL: *
-
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
 target triple = "thumbv7-apple-ios"
 

Added: llvm/trunk/test/CodeGen/X86/legalize-libcalls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/legalize-libcalls.ll?rev=143206&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/legalize-libcalls.ll (added)
+++ llvm/trunk/test/CodeGen/X86/legalize-libcalls.ll Fri Oct 28 12:55:38 2011
@@ -0,0 +1,19 @@
+; RUN: llc -march=x86 < %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
+target triple = "i386-apple-macosx10.7.0"
+
+define float @MakeSphere(float %theta.079) nounwind {
+entry:
+  %add36 = fadd float %theta.079, undef
+  %call = call float @cosf(float %theta.079) nounwind readnone
+  %call45 = call float @sinf(float %theta.079) nounwind readnone
+  %call37 = call float @sinf(float %add36) nounwind readnone
+  store float %call, float* undef, align 8
+  store float %call37, float* undef, align 8
+  store float %call45, float* undef, align 8
+  ret float %add36
+}
+
+declare float @cosf(float) nounwind readnone
+declare float @sinf(float) nounwind readnone

Modified: llvm/trunk/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=143206&r1=143205&r2=143206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3.ll Fri Oct 28 12:55:38 2011
@@ -16,10 +16,8 @@
 	ret void
         
 ; X64: t0:
-; X64: 	movddup	(%rsi), %xmm0
-; X64:  pshuflw	$0, %xmm0, %xmm0
-; X64:	xorl	%eax, %eax
-; X64:	pinsrw	$0, %eax, %xmm0
+; X64:	movdqa	(%rsi), %xmm0
+; X64:	pslldq	$2, %xmm0
 ; X64:	movdqa	%xmm0, (%rdi)
 ; X64:	ret
 }
@@ -31,9 +29,8 @@
 	ret <8 x i16> %tmp3
         
 ; X64: t1:
-; X64: 	movl	(%rsi), %eax
 ; X64: 	movdqa	(%rdi), %xmm0
-; X64: 	pinsrw	$0, %eax, %xmm0
+; X64: 	pinsrw	$0, (%rsi), %xmm0
 ; X64: 	ret
 }
 
@@ -168,7 +165,7 @@
         ret void
 ; X64: 	t10:
 ; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %eax
-; X64: 		unpcklpd [[X1:%xmm[0-9]+]]
+; X64: 		movlhps [[X1:%xmm[0-9]+]]
 ; X64: 		pshuflw	$8, [[X1]], [[X2:%xmm[0-9]+]]
 ; X64: 		pinsrw	$2, %eax, [[X2]]
 ; X64: 		pextrw	$6, [[X0]], %eax
@@ -250,13 +247,12 @@
         %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0,  <16 x i32> < i32 0, i32 1, i32 2, i32 17,  i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
         ret <16 x i8> %tmp9
 ; X64: 	t16:
-; X64: 		pinsrw	$0, %eax, [[X1:%xmm[0-9]+]]
-; X64: 		pextrw	$8, [[X0:%xmm[0-9]+]], %eax
-; X64: 		pinsrw	$1, %eax, [[X1]]
-; X64: 		pextrw	$1, [[X1]], %ecx
-; X64: 		movd	[[X1]], %edx
-; X64: 		pinsrw	$0, %edx, %xmm
-; X64: 		pinsrw	$1, %eax, %xmm
+; X64: 		movdqa	%xmm1, %xmm0
+; X64: 		pslldq	$2, %xmm0
+; X64: 		pextrw	$1, %xmm0, %eax
+; X64: 		movd	%xmm0, %ecx
+; X64: 		pinsrw	$0, %ecx, %xmm0
+; X64: 		pextrw	$8, %xmm1, %ecx
 ; X64: 		ret
 }
 



From resistor at mac.com  Fri Oct 28 13:02:13 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 28 Oct 2011 18:02:13 -0000
Subject: [llvm-commits] [llvm] r143208 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrInfo.td
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
Message-ID: <20111028180213.D8BB9312800A@llvm.org>

Author: resistor
Date: Fri Oct 28 13:02:13 2011
New Revision: 143208

URL: http://llvm.org/viewvc/llvm-project?rev=143208&view=rev
Log:
Reapply r143202, with a manual decoding hook for SWP.  This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=143208&r1=143207&r2=143208&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Oct 28 13:02:13 2011
@@ -481,6 +481,8 @@
   let Inst{15-12} = Rt;
   let Inst{11-4} = 0b00001001;
   let Inst{3-0} = Rt2;
+
+  let DecoderMethod = "DecodeSwap";
 }
 
 // addrmode1 instructions

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=143208&r1=143207&r2=143208&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Oct 28 13:02:13 2011
@@ -1640,7 +1640,7 @@
   let Inst{27-20} = 0b00010000;
   let Inst{19-18} = imod;
   let Inst{17}    = M; // Enabled if mode is set;
-  let Inst{16}    = 0;
+  let Inst{16-9}  = 0b00000000;
   let Inst{8-6}   = iflags;
   let Inst{5}     = 0;
   let Inst{4-0}   = mode;

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=143208&r1=143207&r2=143208&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Oct 28 13:02:13 2011
@@ -249,6 +249,8 @@
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
 
 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
                                uint64_t Address, const void *Decoder);
@@ -4043,3 +4045,25 @@
   return S;
 }
 
+static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder) {
+  unsigned Rt   = fieldFromInstruction32(Insn, 12, 4);
+  unsigned Rt2  = fieldFromInstruction32(Insn, 0,  4);
+  unsigned Rn   = fieldFromInstruction32(Insn, 16, 4);
+  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
+
+  if (pred == 0xF)
+    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
+
+  DecodeStatus S = MCDisassembler::Success;
+  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  return S;
+}

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt?rev=143208&r1=143207&r2=143208&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt Fri Oct 28 13:02:13 2011
@@ -1,4 +1,4 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding}
 
 # invalid (imod, M, iflags) combination
-0x93 0x1c 0x02 0xf1
+0x93 0x00 0x02 0xf1



From baldrick at free.fr  Fri Oct 28 13:17:44 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 28 Oct 2011 18:17:44 -0000
Subject: [llvm-commits] [llvm] r143209 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp
 test/Transforms/InstSimplify/compare.ll
Message-ID: <20111028181744.8C85E312800A@llvm.org>

Author: baldrick
Date: Fri Oct 28 13:17:44 2011
New Revision: 143209

URL: http://llvm.org/viewvc/llvm-project?rev=143209&view=rev
Log:
Fold icmp ugt (udiv X, Y), X to false.  Spotted by my super-optimizer
in 186.crafty.

Modified:
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp
    llvm/trunk/test/Transforms/InstSimplify/compare.ll

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=143209&r1=143208&r2=143209&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Fri Oct 28 13:17:44 2011
@@ -1574,6 +1574,9 @@
       // 'srem x, CI2' produces (-|CI2|, |CI2|).
       Upper = CI2->getValue().abs();
       Lower = (-Upper) + 1;
+    } else if (match(LHS, m_UDiv(m_ConstantInt(CI2), m_Value()))) {
+      // 'udiv CI2, x' produces [0, CI2].
+      Upper = CI2->getValue();
     } else if (match(LHS, m_UDiv(m_Value(), m_ConstantInt(CI2)))) {
       // 'udiv x, CI2' produces [0, UINT_MAX / CI2].
       APInt NegOne = APInt::getAllOnesValue(Width);
@@ -1880,6 +1883,15 @@
     }
   }
 
+  // x udiv y <=u x.
+  if (LBO && match(LBO, m_UDiv(m_Specific(RHS), m_Value()))) {
+    // icmp pred (X /u Y), X
+    if (Pred == ICmpInst::ICMP_UGT)
+      return getFalse(ITy);
+    if (Pred == ICmpInst::ICMP_ULE)
+      return getTrue(ITy);
+  }
+
   if (MaxRecurse && LBO && RBO && LBO->getOpcode() == RBO->getOpcode() &&
       LBO->getOperand(1) == RBO->getOperand(1)) {
     switch (LBO->getOpcode()) {

Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=143209&r1=143208&r2=143209&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Fri Oct 28 13:17:44 2011
@@ -300,6 +300,30 @@
 ; CHECK: ret i1 true
 }
 
+define i1 @udiv3(i32 %X, i32 %Y) {
+; CHECK: @udiv3
+  %A = udiv i32 %X, %Y
+  %C = icmp ugt i32 %A, %X
+  ret i1 %C
+; CHECK: ret i1 false
+}
+
+define i1 @udiv4(i32 %X, i32 %Y) {
+; CHECK: @udiv4
+  %A = udiv i32 %X, %Y
+  %C = icmp ule i32 %A, %X
+  ret i1 %C
+; CHECK: ret i1 true
+}
+
+define i1 @udiv5(i32 %X) {
+; CHECK: @udiv5
+  %A = udiv i32 123, %X
+  %C = icmp ugt i32 %A, 124
+  ret i1 %C
+; CHECK: ret i1 false
+}
+
 define i1 @sdiv1(i32 %X) {
 ; CHECK: @sdiv1
   %A = sdiv i32 %X, 1000000



From baldrick at free.fr  Fri Oct 28 13:30:05 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 28 Oct 2011 18:30:05 -0000
Subject: [llvm-commits] [llvm] r143211 - in /llvm/trunk:
 lib/Analysis/ValueTracking.cpp test/Transforms/InstSimplify/AndOrXor.ll
Message-ID: <20111028183005.D4B6C312800A@llvm.org>

Author: baldrick
Date: Fri Oct 28 13:30:05 2011
New Revision: 143211

URL: http://llvm.org/viewvc/llvm-project?rev=143211&view=rev
Log:
A shift of a power of two is a power of two or zero.
For completeness - not spotted in the wild.

Modified:
    llvm/trunk/lib/Analysis/ValueTracking.cpp
    llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll

Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=143211&r1=143210&r2=143211&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Fri Oct 28 13:30:05 2011
@@ -769,6 +769,12 @@
   if (Depth++ == MaxDepth)
     return false;
 
+  Value *X = 0, *Y = 0;
+  // A shift of a power of two is a power of two or zero.
+  if (OrZero && (match(V, m_Shl(m_Value(X), m_Value())) ||
+                 match(V, m_Shr(m_Value(X), m_Value()))))
+    return isPowerOfTwo(X, TD, /*OrZero*/true, Depth);
+
   if (ZExtInst *ZI = dyn_cast<ZExtInst>(V))
     return isPowerOfTwo(ZI->getOperand(0), TD, OrZero, Depth);
 
@@ -776,7 +782,6 @@
     return isPowerOfTwo(SI->getTrueValue(), TD, OrZero, Depth) &&
       isPowerOfTwo(SI->getFalseValue(), TD, OrZero, Depth);
 
-  Value *X = 0, *Y = 0;
   if (OrZero && match(V, m_And(m_Value(X), m_Value(Y)))) {
     // A power of two and'd with anything is a power of two or zero.
     if (isPowerOfTwo(X, TD, /*OrZero*/true, Depth) ||

Modified: llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll?rev=143211&r1=143210&r2=143211&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll Fri Oct 28 13:30:05 2011
@@ -10,3 +10,13 @@
   ret i64 %e2
 ; CHECK: ret i64 %e
 }
+
+define i64 @pow2b(i32 %x) {
+; CHECK: @pow2b
+  %sh = shl i32 2, %x
+  %e = zext i32 %sh to i64
+  %nege = sub i64 0, %e
+  %e2 = and i64 %e, %nege
+  ret i64 %e2
+; CHECK: ret i64 %e
+}



From gkistanova at gmail.com  Fri Oct 28 13:33:08 2011
From: gkistanova at gmail.com (Galina Kistanova)
Date: Fri, 28 Oct 2011 18:33:08 -0000
Subject: [llvm-commits] [zorg] r143212 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20111028183309.0928D312800A@llvm.org>

Author: gkistanova
Date: Fri Oct 28 13:33:08 2011
New Revision: 143212

URL: http://llvm.org/viewvc/llvm-project?rev=143212&view=rev
Log:
Restored lost $PATH.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=143212&r1=143211&r2=143212&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Oct 28 13:33:08 2011
@@ -362,6 +362,7 @@
 # LLDB builders.
 def _get_lldb_builders():
     gcc_latest_env = {
+        'PATH': '/opt/cfarm/python2-latest/bin:/usr/local/bin:/usr/bin:/bin:/usr/games',
         'CC':  '/opt/cfarm/release/4.5.1/bin/gcc',
         'CXX': '/opt/cfarm/release/4.5.1/bin/g++'}
 



From ahatanaka at mips.com  Fri Oct 28 13:47:24 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Fri, 28 Oct 2011 18:47:24 -0000
Subject: [llvm-commits] [llvm] r143213 - in /llvm/trunk/lib/Target/Mips:
 MipsISelLowering.cpp MipsISelLowering.h
Message-ID: <20111028184724.B3BA0312800A@llvm.org>

Author: ahatanak
Date: Fri Oct 28 13:47:24 2011
New Revision: 143213

URL: http://llvm.org/viewvc/llvm-project?rev=143213&view=rev
Log:
Add variable IsO32 to MipsTargetLowering.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.h

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=143213&r1=143212&r2=143213&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Oct 28 13:47:24 2011
@@ -84,7 +84,8 @@
 MipsTargetLowering(MipsTargetMachine &TM)
   : TargetLowering(TM, new MipsTargetObjectFile()),
     Subtarget(&TM.getSubtarget<MipsSubtarget>()),
-    HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()) {
+    HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
+    IsO32(Subtarget->isABI_O32()) {
 
   // Mips does not have i1 type, so use i32 for
   // setcc operations results (slt, sgt, ...).
@@ -1926,7 +1927,7 @@
   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
 		 getTargetMachine(), ArgLocs, *DAG.getContext());
 
-  if (Subtarget->isABI_O32())
+  if (IsO32)
     CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
   else
     CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
@@ -1954,7 +1955,7 @@
   // Update size of the maximum argument space.
   // For O32, a minimum of four words (16 bytes) of argument space is
   // allocated.
-  if (Subtarget->isABI_O32())
+  if (IsO32)
     NextStackOffset = std::max(NextStackOffset, (unsigned)16);
 
   unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
@@ -1990,7 +1991,7 @@
     switch (VA.getLocInfo()) {
     default: llvm_unreachable("Unknown loc info!");
     case CCValAssign::Full:
-      if (Subtarget->isABI_O32() && VA.isRegLoc()) {
+      if (IsO32 && VA.isRegLoc()) {
         if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
           Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
         if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
@@ -2032,7 +2033,7 @@
     // ByVal Arg.
     ISD::ArgFlagsTy Flags = Outs[i].Flags;
     if (Flags.isByVal()) {
-      assert(Subtarget->isABI_O32() &&
+      assert(IsO32 &&
              "No support for ByVal args by ABIs other than O32 yet.");
       assert(Flags.getByValSize() &&
              "ByVal args of size 0 should have been ignored by front-end.");
@@ -2243,7 +2244,7 @@
   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
 		 getTargetMachine(), ArgLocs, *DAG.getContext());
 
-  if (Subtarget->isABI_O32())
+  if (IsO32)
     CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
   else
     CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
@@ -2291,7 +2292,7 @@
       }
 
       // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
-      if (Subtarget->isABI_O32()) {
+      if (IsO32) {
         if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
           ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
         if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
@@ -2314,7 +2315,7 @@
       ISD::ArgFlagsTy Flags = Ins[i].Flags;
 
       if (Flags.isByVal()) {
-        assert(Subtarget->isABI_O32() &&
+        assert(IsO32 &&
                "No support for ByVal args by ABIs other than O32 yet.");
         assert(Flags.getByValSize() &&
                "ByVal args of size 0 should have been ignored by front-end.");
@@ -2353,7 +2354,7 @@
     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
   }
 
-  if (isVarArg && Subtarget->isABI_O32()) {
+  if (isVarArg && IsO32) {
     // Record the frame index of the first variable argument
     // which is a value necessary to VASTART.
     unsigned NextStackOffset = CCInfo.getNextStackOffset();

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=143213&r1=143212&r2=143213&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Fri Oct 28 13:47:24 2011
@@ -115,7 +115,7 @@
     // Subtarget Info
     const MipsSubtarget *Subtarget;
     
-    bool HasMips64, IsN64;
+    bool HasMips64, IsN64, IsO32;
 
     // Lower Operand helpers
     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,



From baldrick at free.fr  Fri Oct 28 14:01:21 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 28 Oct 2011 19:01:21 -0000
Subject: [llvm-commits] [llvm] r143214 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp
 test/Transforms/InstSimplify/compare.ll
Message-ID: <20111028190121.1A318312800A@llvm.org>

Author: baldrick
Date: Fri Oct 28 14:01:20 2011
New Revision: 143214

URL: http://llvm.org/viewvc/llvm-project?rev=143214&view=rev
Log:
The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
Spotted by my super-optimizer in 186.crafty and 450.soplex.  We really
need a proper infrastructure for handling generalizations of this kind
of thing (which occur a lot), however this case is so simple that I decided
to go ahead and implement it directly.

Modified:
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp
    llvm/trunk/test/Transforms/InstSimplify/compare.ll

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=143214&r1=143213&r2=143214&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Fri Oct 28 14:01:20 2011
@@ -416,39 +416,55 @@
   }
   assert(isa<SelectInst>(LHS) && "Not comparing with a select instruction!");
   SelectInst *SI = cast<SelectInst>(LHS);
+  Value *Cond = SI->getCondition();
+  Value *TV = SI->getTrueValue();
+  Value *FV = SI->getFalseValue();
 
   // Now that we have "cmp select(Cond, TV, FV), RHS", analyse it.
   // Does "cmp TV, RHS" simplify?
-  if (Value *TCmp = SimplifyCmpInst(Pred, SI->getTrueValue(), RHS, TD, DT,
-                                    MaxRecurse)) {
-    // It does!  Does "cmp FV, RHS" simplify?
-    if (Value *FCmp = SimplifyCmpInst(Pred, SI->getFalseValue(), RHS, TD, DT,
-                                      MaxRecurse)) {
-      // It does!  If they simplified to the same value, then use it as the
-      // result of the original comparison.
-      if (TCmp == FCmp)
-        return TCmp;
-      Value *Cond = SI->getCondition();
-      // If the false value simplified to false, then the result of the compare
-      // is equal to "Cond && TCmp".  This also catches the case when the false
-      // value simplified to false and the true value to true, returning "Cond".
-      if (match(FCmp, m_Zero()))
-        if (Value *V = SimplifyAndInst(Cond, TCmp, TD, DT, MaxRecurse))
-          return V;
-      // If the true value simplified to true, then the result of the compare
-      // is equal to "Cond || FCmp".
-      if (match(TCmp, m_One()))
-        if (Value *V = SimplifyOrInst(Cond, FCmp, TD, DT, MaxRecurse))
-          return V;
-      // Finally, if the false value simplified to true and the true value to
-      // false, then the result of the compare is equal to "!Cond".
-      if (match(FCmp, m_One()) && match(TCmp, m_Zero()))
-        if (Value *V =
-            SimplifyXorInst(Cond, Constant::getAllOnesValue(Cond->getType()),
-                            TD, DT, MaxRecurse))
-          return V;
-    }
+  Value *TCmp = SimplifyCmpInst(Pred, TV, RHS, TD, DT, MaxRecurse);
+  if (!TCmp) {
+    // It didn't simplify.  However if "cmp TV, RHS" is equal to the select
+    // condition itself then we can replace it with 'true'.
+    if (match(Cond, m_ICmp(Pred, m_Specific(TV), m_Specific(RHS))))
+      TCmp = getTrue(Cond->getType());
+  }
+  if (!TCmp)
+    return 0;
+
+  // Does "cmp FV, RHS" simplify?
+  Value *FCmp = SimplifyCmpInst(Pred, FV, RHS, TD, DT, MaxRecurse);
+  if (!FCmp) {
+    // It didn't simplify.  However if "cmp FV, RHS" is equal to the select
+    // condition itself then we can replace it with 'false'.
+    if (match(Cond, m_ICmp(Pred, m_Specific(FV), m_Specific(RHS))))
+      FCmp = getFalse(Cond->getType());
   }
+  if (!FCmp)
+    return 0;
+
+  // If both sides simplified to the same value, then use it as the result of
+  // the original comparison.
+  if (TCmp == FCmp)
+    return TCmp;
+  // If the false value simplified to false, then the result of the compare
+  // is equal to "Cond && TCmp".  This also catches the case when the false
+  // value simplified to false and the true value to true, returning "Cond".
+  if (match(FCmp, m_Zero()))
+    if (Value *V = SimplifyAndInst(Cond, TCmp, TD, DT, MaxRecurse))
+      return V;
+  // If the true value simplified to true, then the result of the compare
+  // is equal to "Cond || FCmp".
+  if (match(TCmp, m_One()))
+    if (Value *V = SimplifyOrInst(Cond, FCmp, TD, DT, MaxRecurse))
+      return V;
+  // Finally, if the false value simplified to true and the true value to
+  // false, then the result of the compare is equal to "!Cond".
+  if (match(FCmp, m_One()) && match(TCmp, m_Zero()))
+    if (Value *V =
+        SimplifyXorInst(Cond, Constant::getAllOnesValue(Cond->getType()),
+                        TD, DT, MaxRecurse))
+      return V;
 
   return 0;
 }

Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=143214&r1=143213&r2=143214&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Fri Oct 28 14:01:20 2011
@@ -204,6 +204,15 @@
 ; CHECK: ret i1 %cond
 }
 
+define i1 @select5(i32 %x) {
+; CHECK: @select5
+  %c = icmp eq i32 %x, 0
+  %s = select i1 %c, i32 1, i32 %x
+  %c2 = icmp eq i32 %s, 0
+  ret i1 %c2
+; CHECK: ret i1 false
+}
+
 define i1 @urem1(i32 %X, i32 %Y) {
 ; CHECK: @urem1
   %A = urem i32 %X, %Y



From ahatanaka at mips.com  Fri Oct 28 14:49:00 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Fri, 28 Oct 2011 19:49:00 -0000
Subject: [llvm-commits] [llvm] r143217 -
	/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
Message-ID: <20111028194900.E9232312800A@llvm.org>

Author: ahatanak
Date: Fri Oct 28 14:49:00 2011
New Revision: 143217

URL: http://llvm.org/viewvc/llvm-project?rev=143217&view=rev
Log:
Make changes necessary in LowerCall to support Mips64.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=143217&r1=143216&r2=143217&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Oct 28 14:49:00 2011
@@ -1945,7 +1945,7 @@
 
   // If this is the first call, create a stack frame object that points to
   // a location to which .cprestore saves $gp.
-  if (IsPIC && !MipsFI->getGPFI())
+  if (IsO32 && IsPIC && !MipsFI->getGPFI())
     MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
 
   // Get the frame index of the stack frame object that points to the location
@@ -1970,7 +1970,7 @@
     NextStackOffset = (NextStackOffset + StackAlignment - 1) /
                       StackAlignment * StackAlignment;
 
-    if (IsPIC)
+    if (MipsFI->needGPSaveRestore())
       MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
 
     MFI->setObjectOffset(DynAllocFI, NextStackOffset);
@@ -1986,15 +1986,17 @@
   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
     SDValue Arg = OutVals[i];
     CCValAssign &VA = ArgLocs[i];
-
+    MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
+    
     // Promote the value if needed.
     switch (VA.getLocInfo()) {
     default: llvm_unreachable("Unknown loc info!");
     case CCValAssign::Full:
-      if (IsO32 && VA.isRegLoc()) {
-        if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
-          Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
-        if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
+      if (VA.isRegLoc()) {
+        if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
+            (ValVT == MVT::f64 && LocVT == MVT::i64))
+          Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
+        else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
           SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
                                    Arg, DAG.getConstant(0, MVT::i32));
           SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
@@ -2010,13 +2012,13 @@
       }
       break;
     case CCValAssign::SExt:
-      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
+      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
       break;
     case CCValAssign::ZExt:
-      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
+      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
       break;
     case CCValAssign::AExt:
-      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
+      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
       break;
     }
 
@@ -2043,7 +2045,7 @@
     }
 
     // Create the frame index object for this incoming parameter
-    LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
+    LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
                                     VA.getLocMemOffset(), true);
     SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
 
@@ -2075,17 +2077,21 @@
   // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
   // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
   // node so that legalize doesn't hack it.
-  unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
+  unsigned char OpFlag;
+  bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
   bool LoadSymAddr = false;
   SDValue CalleeLo;
 
   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
-    if (IsPIC && G->getGlobal()->hasInternalLinkage()) {
-      Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
-                                          getPointerTy(), 0,MipsII:: MO_GOT);
+    if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
+      OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
+      unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
+      Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
+                                          OpFlag);
       CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
-                                            0, MipsII::MO_ABS_LO);
+                                            0, LoFlag);
     } else {
+      OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
       Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
                                           getPointerTy(), 0, OpFlag);
     }
@@ -2093,34 +2099,41 @@
     LoadSymAddr = true;
   }
   else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
+    if (IsN64 || (!IsO32 && IsPIC))
+      OpFlag = MipsII::MO_GOT_DISP;
+    else if (!IsPIC) // !N64 && static
+      OpFlag = MipsII::MO_NO_FLAG;
+    else // O32 & PIC
+      OpFlag = MipsII::MO_GOT_CALL;
     Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
-                                getPointerTy(), OpFlag);
+                                         getPointerTy(), OpFlag);
     LoadSymAddr = true;
   }
 
   SDValue InFlag;
 
   // Create nodes that load address of callee and copy it to T9
-  if (IsPIC) {
+  if (IsPICCall) {
     if (LoadSymAddr) {
       // Load callee address
-      Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee);
-      SDValue LoadValue = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), Callee,
-                                      MachinePointerInfo::getGOT(),
+      Callee = DAG.getNode(MipsISD::WrapperPIC, dl, getPointerTy(), Callee);
+      SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
+                                      Callee, MachinePointerInfo::getGOT(),
                                       false, false, 0);
 
       // Use GOT+LO if callee has internal linkage.
       if (CalleeLo.getNode()) {
-        SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo);
-        Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo);
+        SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
+        Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
       } else
         Callee = LoadValue;
     }
 
     // copy to T9
-    Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0));
+    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
+    Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
     InFlag = Chain.getValue(1);
-    Callee = DAG.getRegister(Mips::T9, MVT::i32);
+    Callee = DAG.getRegister(T9Reg, getPointerTy());
   }
 
   // Build a sequence of copy-to-reg nodes chained together with token



From ahatanaka at mips.com  Fri Oct 28 14:55:48 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Fri, 28 Oct 2011 19:55:48 -0000
Subject: [llvm-commits] [llvm] r143218 -
	/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
Message-ID: <20111028195548.C70FF312800A@llvm.org>

Author: ahatanak
Date: Fri Oct 28 14:55:48 2011
New Revision: 143218

URL: http://llvm.org/viewvc/llvm-project?rev=143218&view=rev
Log:
Make changes necessary in LowerFormalArguments to support Mips64.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=143218&r1=143217&r2=143218&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Oct 28 14:55:48 2011
@@ -2266,6 +2266,7 @@
 
   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
     CCValAssign &VA = ArgLocs[i];
+    EVT ValVT = VA.getValVT();
 
     // Arguments stored on registers
     if (VA.isRegLoc()) {
@@ -2300,23 +2301,22 @@
           Opcode = ISD::AssertZext;
         if (Opcode)
           ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
-                                 DAG.getValueType(VA.getValVT()));
-        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
+                                 DAG.getValueType(ValVT));
+        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
       }
 
-      // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
-      if (IsO32) {
-        if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
-          ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
-        if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
-          unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
-                                    getNextIntArgReg(ArgReg), RC);
-          SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
-          if (!Subtarget->isLittle())
-            std::swap(ArgValue, ArgValue2);
-          ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
-                                 ArgValue, ArgValue2);
-        }
+      // Handle floating point arguments passed in integer registers.
+      if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
+          (RegVT == MVT::i64 && ValVT == MVT::f64))
+        ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
+      else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
+        unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
+                                  getNextIntArgReg(ArgReg), RC);
+        SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
+        if (!Subtarget->isLittle())
+          std::swap(ArgValue, ArgValue2);
+        ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
+                               ArgValue, ArgValue2);
       }
 
       InVals.push_back(ArgValue);
@@ -2343,12 +2343,12 @@
       }
 
       // The stack pointer offset is relative to the caller stack frame.
-      LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
+      LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
                                       VA.getLocMemOffset(), true);
 
       // Create load nodes to retrieve arguments from the stack
       SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
-      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
+      InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
                                    MachinePointerInfo::getFixedStack(LastFI),
                                    false, false, 0));
     }



From kcc at google.com  Fri Oct 28 15:41:55 2011
From: kcc at google.com (Kostya Serebryany)
Date: Fri, 28 Oct 2011 13:41:55 -0700
Subject: [llvm-commits] appendToGlobalCtors
Message-ID: <CAN=P9piDgWqCE7bmFU5WB-SRzk_Dstz+Gq9k4_O8pzGkkyUDTg@mail.gmail.com>

Hello,

I would like to add a small utility function into llvm/Transforms/Utils.
appendToGlobalCtors() adds a function to the list of global constructors.
Currently it is used by AddressSanitizer; clattner suggested to move it
to llvm/Transforms/Utils.

Patch: http://codereview.appspot.com/5330046 (also in attachment).

Thanks,

--kcc
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From resistor at mac.com  Fri Oct 28 15:43:25 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 28 Oct 2011 20:43:25 -0000
Subject: [llvm-commits] [llvm] r143220 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20111028204325.33A69312800A@llvm.org>

Author: resistor
Date: Fri Oct 28 15:43:24 2011
New Revision: 143220

URL: http://llvm.org/viewvc/llvm-project?rev=143220&view=rev
Log:
Specify that the high bit of the alignment field is fixed to 0 on these instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=143220&r1=143219&r2=143220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Oct 28 15:43:24 2011
@@ -389,7 +389,7 @@
                      "vld1", Dt, "$Vd, $Rn!",
                      "$Rn.addr = $wb", []> {
     let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
-    let Inst{5-4} = Rn{5-4};
+    let Inst{4} = Rn{4};
     let DecoderMethod = "DecodeVLDInstruction";
     let AsmMatchConverter = "cvtVLDwbFixed";
   }
@@ -397,7 +397,7 @@
                         (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
                         "vld1", Dt, "$Vd, $Rn, $Rm",
                         "$Rn.addr = $wb", []> {
-    let Inst{5-4} = Rn{5-4};
+    let Inst{4} = Rn{4};
     let DecoderMethod = "DecodeVLDInstruction";
     let AsmMatchConverter = "cvtVLDwbRegister";
   }



From grosbach at apple.com  Fri Oct 28 15:52:20 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 28 Oct 2011 20:52:20 -0000
Subject: [llvm-commits] [llvm] r143224 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20111028205220.5E833312800A@llvm.org>

Author: grosbach
Date: Fri Oct 28 15:52:20 2011
New Revision: 143224

URL: http://llvm.org/viewvc/llvm-project?rev=143224&view=rev
Log:
Clarify example snippets a bit.

Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=143224&r1=143223&r2=143224&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Fri Oct 28 15:52:20 2011
@@ -998,7 +998,7 @@
 <pre>
 for ( ... ) {
    std::vector&lt;foo&gt; V;
-   use V;
+   // make use of V.
 }
 </pre>
 </div>
@@ -1009,7 +1009,7 @@
 <pre>
 std::vector&lt;foo&gt; V;
 for ( ... ) {
-   use V;
+   // make use of V.
    V.clear();
 }
 </pre>



From gkistanova at gmail.com  Fri Oct 28 16:29:38 2011
From: gkistanova at gmail.com (Galina Kistanova)
Date: Fri, 28 Oct 2011 21:29:38 -0000
Subject: [llvm-commits] [zorg] r143229 - in
 /zorg/trunk/buildbot/osuosl/master/config: builders.py slaves.py
Message-ID: <20111028212938.203E2312800A@llvm.org>

Author: gkistanova
Date: Fri Oct 28 16:29:37 2011
New Revision: 143229

URL: http://llvm.org/viewvc/llvm-project?rev=143229&view=rev
Log:
Added new builder "clang-x86_64-ubuntu"; removed two off-line builders.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py
    zorg/trunk/buildbot/osuosl/master/config/slaves.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=143229&r1=143228&r2=143229&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Oct 28 16:29:37 2011
@@ -174,24 +174,16 @@
 # Clang builders.
 def _get_clang_builders():
     return [
-        {'name': "clang-i686-freebsd",
-         'slavenames':["freebsd1"],
-         'builddir':"clang-i686-freebsd",
-         'factory': ClangBuilder.getClangBuildFactory(clean=True, use_pty_in_tests=True)},
-
-        {'name' : "clang-i686-linux-fnt",
-         'slavenames' : ['balint1'],
-         'builddir' : "clang-i686-linux-fnt",
-         'factory' : NightlytestBuilder.getFastNightlyTestBuildFactory(triple='i686-pc-linux-gnu',
-                                                                       stage1_config='Release+Asserts',
-                                                                       test=False,
-                                                                       xfails=clang_i386_linux_xfails) },
-
         {'name': "clang-x86_64-debian",
          'slavenames':["gcc12"],
          'builddir':"clang-x86_64-debian",
          'factory': ClangBuilder.getClangBuildFactory()},
 
+        {'name': "clang-x86_64-ubuntu",
+         'slavename':["arxan_raphael"],
+         'builddir':"clang-x86_64-ubuntu",
+         'factory' : ClangBuilder.getClangBuildFactory()},
+
         {'name' : "clang-x86_64-debian-selfhost-rel",
          'slavenames' : ["gcc13"],
          'builddir' : "clang-x86_64-debian-selfhost-rel",
@@ -207,7 +199,7 @@
                                                                        stage1_config='Release+Asserts',
                                                                        test=False,
                                                                        xfails=clang_x86_64_linux_xfails)},
- 
+
         {'name': "clang-native-arm-cortex-a9",
          'slavenames':["kistanova6"],
          'builddir':"clang-native-arm-cortex-a9",
@@ -313,6 +305,17 @@
                                                useTwoStage=True,
                                                stage1_config='Release+Asserts',
                                                stage2_config='Debug+Asserts')},
+{'name': "clang-i686-freebsd",
+ 'slavenames':["freebsd1"],
+ 'builddir':"clang-i686-freebsd",
+ 'factory': ClangBuilder.getClangBuildFactory(clean=True, use_pty_in_tests=True)},
+{'name' : "clang-i686-linux-fnt",
+ 'slavenames' : ['balint1'],
+ 'builddir' : "clang-i686-linux-fnt",
+ 'factory' : NightlytestBuilder.getFastNightlyTestBuildFactory(triple='i686-pc-linux-gnu',
+                                                               stage1_config='Release+Asserts',
+                                                               test=False,
+                                                               xfails=clang_i386_linux_xfails) },
 
 def _get_dragonegg_builders():
     return [
@@ -735,15 +738,6 @@
                                         'haltOnFailure' : True },]),
          'category'  : 'llvm-gcc' },
 
-        {'name': "clang-i686-freebsd-selfhost-rel",
-         'slavenames':["freebsd1"],
-         'builddir':"clang-i686-freebsd-selfhost-rel",
-         'factory': ClangBuilder.getClangBuildFactory(triple='i686-pc-freebsd',
-                                                      useTwoStage=True,
-                                                      stage1_config='Release+Asserts',
-                                                      stage2_config='Release+Asserts'),
-         'category' : 'clang.exp' },
-
         ]
 
 def get_builders():
@@ -843,3 +837,11 @@
 # 'builddir' :"clang-i686-xp-msvc9_alt",
 # 'factory' : ClangBuilder.getClangMSVCBuildFactory(jobs=2),
 # 'category' : 'clang.exp' },
+{'name': "clang-i686-freebsd-selfhost-rel",
+ 'slavenames':["freebsd1"],
+ 'builddir':"clang-i686-freebsd-selfhost-rel",
+ 'factory': ClangBuilder.getClangBuildFactory(triple='i686-pc-freebsd',
+                                              useTwoStage=True,
+                                              stage1_config='Release+Asserts',
+                                              stage2_config='Release+Asserts'),
+ 'category' : 'clang.exp' },

Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=143229&r1=143228&r2=143229&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Fri Oct 28 16:29:37 2011
@@ -10,9 +10,6 @@
 
 def get_build_slaves():
     return [
-        # FreeBSD zero.sajd.net 9.0-CURRENT i386
-        create_slave("freebsd1", properties={'jobs' : 1}, max_builds=1),
-
         # CPU Marvell Kirkwood 88F6281 ARM Based armv5tejl running at 1.2Ghz
         # Memory 512MB SDRAM
         # Power 2.3w idle no attached devices, 7.0w running at 100% CPU utilization
@@ -129,15 +126,15 @@
         # gcc201 8011  80G   4x0.4 GHz  TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64
         create_slave("gcc201", properties={'jobs' : 2}, max_builds=1),
 
-        # Debian, P4 2.8GHz, 1GB mem
-        create_slave("balint1", properties={'jobs' : 1}, max_builds=1),
-
         # AMD Athlon(tm) 64 X2 Dual Core 3800+, Ubuntu x86_64
         create_slave("grosser1", properties={'jobs': 2}, max_builds=1),
 
         # Intel(R) Core(TM)2 CPU 6420  @ 2.13GHz, Ubuntu Oneiric x86_64
         create_slave("arxan_davinci", properties={'jobs': 4}, max_builds=1),
 
+        # Intel(R) Core(TM)2 CPU 6420  @ 2.13GHz, Ubuntu Oneiric x86_64
+        create_slave("arxan_raphael", properties={'jobs': 4}, max_builds=1),
+
         # 2005 PowerPC Mac Mini, Mac OS X 10.5
         create_slave("arxan_bellini", properties={'jobs': 2}, max_builds=1),
 
@@ -170,4 +167,8 @@
         #create_slave("osu8", properties={'jobs' : 6}, max_builds=4),
         #create_slave("andrew1"),
         #create_slave("danmbp1"),
+        # FreeBSD zero.sajd.net 9.0-CURRENT i386
+        #create_slave("freebsd1", properties={'jobs' : 1}, max_builds=1),
+        # Debian, P4 2.8GHz, 1GB mem
+        #create_slave("balint1", properties={'jobs' : 1}, max_builds=1),
         ]



From resistor at mac.com  Fri Oct 28 16:45:09 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 28 Oct 2011 21:45:09 -0000
Subject: [llvm-commits] [llvm] r143231 -
	/llvm/trunk/test/MC/Disassembler/ARM/neon.txt
Message-ID: <20111028214509.5BBB2312800A@llvm.org>

Author: resistor
Date: Fri Oct 28 16:45:09 2011
New Revision: 143231

URL: http://llvm.org/viewvc/llvm-project?rev=143231&view=rev
Log:
Fix illegal disassembly testcase.

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/neon.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=143231&r1=143230&r2=143231&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Fri Oct 28 16:45:09 2011
@@ -1857,6 +1857,6 @@
 0xe9 0x1a 0xb2 0x4e
 # CHECK: vcvttmi.f32.f16	s2, s19
 
-0x3d 0x76 0x66 0xf4
-# CHECK: vld1.8	{d23, d24, d25}, [r6, :256]!
+0x1d 0x76 0x66 0xf4
+# CHECK: vld1.8	{d23, d24, d25}, [r6, :64]!
 



From grosbach at apple.com  Fri Oct 28 17:32:53 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 28 Oct 2011 22:32:53 -0000
Subject: [llvm-commits] [llvm] r143233 - in /llvm/trunk/utils/TableGen:
 AsmMatcherEmitter.cpp CodeGenInstruction.cpp
Message-ID: <20111028223253.E5F89312800A@llvm.org>

Author: grosbach
Date: Fri Oct 28 17:32:53 2011
New Revision: 143233

URL: http://llvm.org/viewvc/llvm-project?rev=143233&view=rev
Log:
Allow InstAlias's to use immediate matcher patterns that xform the value.

For example,

On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a
matcher pattern that handles the bitwise negation when mapping to t2MVNi.

Modified:
    llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp

Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=143233&r1=143232&r2=143233&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Fri Oct 28 17:32:53 2011
@@ -591,7 +591,8 @@
 
   /// getOperandClass - Lookup or create the class for the given operand.
   ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
-                             int SubOpIdx = -1);
+                             int SubOpIdx);
+  ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
 
   /// BuildRegisterClasses - Build the ClassInfo* instances for register
   /// classes.
@@ -870,7 +871,11 @@
   Record *Rec = OI.Rec;
   if (SubOpIdx != -1)
     Rec = dynamic_cast<DefInit*>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
+  return getOperandClass(Rec, SubOpIdx);
+}
 
+ClassInfo *
+AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
   if (Rec->isSubClassOf("RegisterOperand")) {
     // RegisterOperand may have an associated ParserMatchClass. If it does,
     // use it, else just fall back to the underlying register class.
@@ -1375,9 +1380,11 @@
         CGA.ResultOperands[i].getName() == OperandName) {
       // It's safe to go with the first one we find, because CodeGenInstAlias
       // validates that all operands with the same name have the same record.
-      unsigned ResultIdx = CGA.ResultInstOperandIndex[i].first;
       Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
-      Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx],
+      // Use the match class from the Alias definition, not the
+      // destination instruction, as we may have an immediate that's
+      // being munged by the match class.
+      Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
                                  Op.SubOpIdx);
       Op.SrcOpName = OperandName;
       return;

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=143233&r1=143232&r2=143233&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Fri Oct 28 17:32:53 2011
@@ -428,8 +428,11 @@
   if (ADI && ADI->getDef()->isSubClassOf("RegisterClass")) {
     if (!InstOpRec->isSubClassOf("RegisterClass"))
       return false;
-    return T.getRegisterClass(InstOpRec)
-              .hasSubClass(&T.getRegisterClass(ADI->getDef()));
+    if (!T.getRegisterClass(InstOpRec)
+              .hasSubClass(&T.getRegisterClass(ADI->getDef())))
+      return false;
+    ResOp = ResultOperand(Result->getArgName(AliasOpNo), ADI->getDef());
+    return true;
   }
 
   // Handle explicit registers.
@@ -473,6 +476,7 @@
     return true;
   }
 
+  // Literal integers.
   if (IntInit *II = dynamic_cast<IntInit*>(Arg)) {
     if (hasSubOps || !InstOpRec->isSubClassOf("Operand"))
       return false;
@@ -484,6 +488,19 @@
     return true;
   }
 
+  // If both are Operands with the same MVT, allow the conversion. It's
+  // up to the user to make sure the values are appropriate, just like
+  // for isel Pat's.
+  if (InstOpRec->isSubClassOf("Operand") &&
+      ADI->getDef()->isSubClassOf("Operand")) {
+    // FIXME: What other attributes should we check here? Identical
+    // MIOperandInfo perhaps?
+    if (InstOpRec->getValueInit("Type") != ADI->getDef()->getValueInit("Type"))
+      return false;
+    ResOp = ResultOperand(Result->getArgName(AliasOpNo), ADI->getDef());
+    return true;
+  }
+
   return false;
 }
 



From grosbach at apple.com  Fri Oct 28 17:36:30 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 28 Oct 2011 22:36:30 -0000
Subject: [llvm-commits] [llvm] r143235 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20111028223630.CC562312800A@llvm.org>

Author: grosbach
Date: Fri Oct 28 17:36:30 2011
New Revision: 143235

URL: http://llvm.org/viewvc/llvm-project?rev=143235&view=rev
Log:
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".

When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=143235&r1=143234&r2=143235&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Oct 28 17:36:30 2011
@@ -76,10 +76,16 @@
 
 // t2_so_imm_not - Match an immediate that is a complement
 // of a t2_so_imm.
+// Note: this pattern doesn't require an encoder method and such, as it's
+// only used on aliases (Pat<> and InstAlias<>). The actual encoding
+// is handled by the destination instructions, which use t2_so_imm.
+def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
 def t2_so_imm_not : Operand<i32>,
                     PatLeaf<(imm), [{
   return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
-}], t2_so_imm_not_XFORM>;
+}], t2_so_imm_not_XFORM> {
+  let ParserMatchClass = t2_so_imm_not_asmoperand;
+}
 
 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
 def t2_so_imm_neg : Operand<i32>,
@@ -4066,3 +4072,9 @@
                   (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
                   (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
+
+
+// "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
+// for isel.
+def : t2InstAlias<"mov${p} $Rd, $imm",
+                  (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=143235&r1=143234&r2=143235&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Oct 28 17:36:30 2011
@@ -665,6 +665,14 @@
     int64_t Value = CE->getValue();
     return ARM_AM::getT2SOImmVal(Value) != -1;
   }
+  bool isT2SOImmNot() const {
+    if (Kind != k_Immediate)
+      return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return ARM_AM::getT2SOImmVal(~Value) != -1;
+  }
   bool isSetEndImm() const {
     if (Kind != k_Immediate)
       return false;
@@ -1241,6 +1249,14 @@
     addExpr(Inst, getImm());
   }
 
+  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // The operand is actually a t2_so_imm, but we have its bitwise
+    // negation in the assembly source, so twiddle it here.
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
+  }
+
   void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     addExpr(Inst, getImm());

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=143235&r1=143234&r2=143235&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Oct 28 17:36:30 2011
@@ -1118,6 +1118,10 @@
         movne.w r1, #12
         mov.w r6, #450
 
+        @ alias for mvn
+	mov r3, #-3
+
+
 @ CHECK: movs	r1, #21                 @ encoding: [0x15,0x21]
 @ CHECK: movs.w	r1, #21                 @ encoding: [0x5f,0xf0,0x15,0x01]
 @ CHECK: movs.w	r8, #21                 @ encoding: [0x5f,0xf0,0x15,0x08]
@@ -1133,6 +1137,9 @@
 @ CHECK: movne.w r1, #12                @ encoding: [0x4f,0xf0,0x0c,0x01]
 @ CHECK: mov.w	r6, #450                @ encoding: [0x4f,0xf4,0xe1,0x76]
 
+@ CHECK: mvn	r3, #2                  @ encoding: [0x6f,0xf0,0x02,0x03]
+
+
 
 @------------------------------------------------------------------------------
 @ MOVT



From gkistanova at gmail.com  Fri Oct 28 17:40:52 2011
From: gkistanova at gmail.com (Galina Kistanova)
Date: Fri, 28 Oct 2011 22:40:52 -0000
Subject: [llvm-commits] [zorg] r143236 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20111028224052.7772E312800A@llvm.org>

Author: gkistanova
Date: Fri Oct 28 17:40:52 2011
New Revision: 143236

URL: http://llvm.org/viewvc/llvm-project?rev=143236&view=rev
Log:
Fixed misspell.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=143236&r1=143235&r2=143236&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Oct 28 17:40:52 2011
@@ -180,7 +180,7 @@
          'factory': ClangBuilder.getClangBuildFactory()},
 
         {'name': "clang-x86_64-ubuntu",
-         'slavename':["arxan_raphael"],
+         'slavenames':["arxan_raphael"],
          'builddir':"clang-x86_64-ubuntu",
          'factory' : ClangBuilder.getClangBuildFactory()},
 



From grosbach at apple.com  Fri Oct 28 17:50:54 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 28 Oct 2011 22:50:54 -0000
Subject: [llvm-commits] [llvm] r143237 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrInfo.td AsmParser/ARMAsmParser.cpp
Message-ID: <20111028225054.C0704312800A@llvm.org>

Author: grosbach
Date: Fri Oct 28 17:50:54 2011
New Revision: 143237

URL: http://llvm.org/viewvc/llvm-project?rev=143237&view=rev
Log:
ARM mode 'mov' to 'mvn' assembler alias.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=143237&r1=143236&r2=143237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Oct 28 17:50:54 2011
@@ -258,10 +258,16 @@
     return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
   }], so_imm_neg_XFORM>;
 
+// Note: this pattern doesn't require an encoder method and such, as it's
+// only used on aliases (Pat<> and InstAlias<>). The actual encoding
+// is handled by the destination instructions, which use t2_so_imm.
+def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
 def so_imm_not :
-  PatLeaf<(imm), [{
+  Operand<i32>, PatLeaf<(imm), [{
     return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
-  }], so_imm_not_XFORM>;
+  }], so_imm_not_XFORM> {
+  let ParserMatchClass = so_imm_not_asmoperand;
+}
 
 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
@@ -4988,3 +4994,9 @@
 //                (LDRHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;
 //def : InstAlias<"ldrsht${p} $Rt, $addr",
 //                (LDRSHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;
+
+
+// "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
+// for isel.
+def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
+                   (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=143237&r1=143236&r2=143237&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Oct 28 17:50:54 2011
@@ -657,6 +657,14 @@
     int64_t Value = CE->getValue();
     return ARM_AM::getSOImmVal(Value) != -1;
   }
+  bool isARMSOImmNot() const {
+    if (Kind != k_Immediate)
+      return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return ARM_AM::getSOImmVal(~Value) != -1;
+  }
   bool isT2SOImm() const {
     if (Kind != k_Immediate)
       return false;
@@ -1257,6 +1265,14 @@
     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
   }
 
+  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // The operand is actually a so_imm, but we have its bitwise
+    // negation in the assembly source, so twiddle it here.
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
+  }
+
   void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     addExpr(Inst, getImm());



From geek4civic at gmail.com  Fri Oct 28 18:11:04 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Fri, 28 Oct 2011 23:11:04 -0000
Subject: [llvm-commits] [llvm] r143247 -
 /llvm/trunk/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
Message-ID: <20111028231104.17B99312800A@llvm.org>

Author: chapuni
Date: Fri Oct 28 18:11:03 2011
New Revision: 143247

URL: http://llvm.org/viewvc/llvm-project?rev=143247&view=rev
Log:
test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUIRES: asserts" for now.

Modified:
    llvm/trunk/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll

Modified: llvm/trunk/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll?rev=143247&r1=143246&r2=143247&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll Fri Oct 28 18:11:03 2011
@@ -1,3 +1,7 @@
+; PR11218
+; FIXME: This depends on assertion failure for now.
+; REQUIRES: asserts
+
 ; RUN: llc < %s
 ; XFAIL: *
 ; PR2356



From eli.friedman at gmail.com  Fri Oct 28 18:56:06 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Fri, 28 Oct 2011 16:56:06 -0700
Subject: [llvm-commits] [llvm] r143214 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp
 test/Transforms/InstSimplify/compare.ll
In-Reply-To: <20111028190121.1A318312800A@llvm.org>
References: <20111028190121.1A318312800A@llvm.org>
Message-ID: <CAJdarcGim2JVGaDMihFNePMY6m+rEWHNoeX+UtXh-kuejLudtg@mail.gmail.com>

On Fri, Oct 28, 2011 at 12:01 PM, Duncan Sands <baldrick at free.fr> wrote:
> Author: baldrick
> Date: Fri Oct 28 14:01:20 2011
> New Revision: 143214
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143214&view=rev
> Log:
> The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
> Spotted by my super-optimizer in 186.crafty and 450.soplex. ?We really
> need a proper infrastructure for handling generalizations of this kind
> of thing (which occur a lot), however this case is so simple that I decided
> to go ahead and implement it directly.

This appears to be causing a miscompile on
MultiSource/Benchmarks/mediabench/gsm/toast, among other things.

-Eli


From gohman at apple.com  Fri Oct 28 19:41:52 2011
From: gohman at apple.com (Dan Gohman)
Date: Sat, 29 Oct 2011 00:41:52 -0000
Subject: [llvm-commits] [llvm] r143262 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/ lib/Target/XCore/
 test/CodeGen/CellSPU/ test/CodeGen/Mips/ test/CodeGen/Thumb/
 test/CodeGen/X86/
Message-ID: <20111029004153.1DF8D312800A@llvm.org>

Author: djg
Date: Fri Oct 28 19:41:52 2011
New Revision: 143262

URL: http://llvm.org/viewvc/llvm-project?rev=143262&view=rev
Log:
Revert r143206, as there are still some failing tests.

Removed:
    llvm/trunk/test/CodeGen/X86/legalize-libcalls.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
    llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
    llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll
    llvm/trunk/test/CodeGen/CellSPU/nand.ll
    llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
    llvm/trunk/test/CodeGen/CellSPU/select_bits.ll
    llvm/trunk/test/CodeGen/CellSPU/struct_1.ll
    llvm/trunk/test/CodeGen/Mips/cprestore.ll
    llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
    llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
    llvm/trunk/test/CodeGen/X86/sse3.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 28 19:41:52 2011
@@ -46,18 +46,37 @@
 /// will attempt merge setcc and brc instructions into brcc's.
 ///
 namespace {
-class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
+class SelectionDAGLegalize {
   const TargetMachine &TM;
   const TargetLowering &TLI;
   SelectionDAG &DAG;
 
-  /// LegalizePosition - The iterator for walking through the node list.
-  SelectionDAG::allnodes_iterator LegalizePosition;
+  // Libcall insertion helpers.
 
-  /// LegalizedNodes - The set of nodes which have already been legalized.
-  SmallPtrSet<SDNode *, 16> LegalizedNodes;
+  /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
+  /// legalized.  We use this to ensure that calls are properly serialized
+  /// against each other, including inserted libcalls.
+  SDValue LastCALLSEQ_END;
+
+  /// IsLegalizingCall - This member is used *only* for purposes of providing
+  /// helpful assertions that a libcall isn't created while another call is
+  /// being legalized (which could lead to non-serialized call sequences).
+  bool IsLegalizingCall;
+
+  /// LegalizedNodes - For nodes that are of legal width, and that have more
+  /// than one use, this map indicates what regularized operand to use.  This
+  /// allows us to avoid legalizing the same thing more than once.
+  DenseMap<SDValue, SDValue> LegalizedNodes;
+
+  void AddLegalizedOperand(SDValue From, SDValue To) {
+    LegalizedNodes.insert(std::make_pair(From, To));
+    // If someone requests legalization of the new node, return itself.
+    if (From != To)
+      LegalizedNodes.insert(std::make_pair(To, To));
 
-  // Libcall insertion helpers.
+    // Transfer SDDbgValues.
+    DAG.TransferDbgValues(From, To);
+  }
 
 public:
   explicit SelectionDAGLegalize(SelectionDAG &DAG);
@@ -65,8 +84,9 @@
   void LegalizeDAG();
 
 private:
-  /// LegalizeOp - Legalizes the given operation.
-  void LegalizeOp(SDNode *Node);
+  /// LegalizeOp - Return a legal replacement for the given operation, with
+  /// all legal operands.
+  SDValue LegalizeOp(SDValue O);
 
   SDValue OptimizeFloatStore(StoreSDNode *ST);
 
@@ -87,6 +107,9 @@
                                      SDValue N1, SDValue N2,
                                      SmallVectorImpl<int> &Mask) const;
 
+  bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
+                                    SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
+
   void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
                              DebugLoc dl);
 
@@ -127,21 +150,10 @@
   SDValue ExpandInsertToVectorThroughStack(SDValue Op);
   SDValue ExpandVectorBuildThroughStack(SDNode* Node);
 
-  SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
-
   std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
 
-  void ExpandNode(SDNode *Node);
-  void PromoteNode(SDNode *Node);
-
-  // DAGUpdateListener implementation.
-  virtual void NodeDeleted(SDNode *N, SDNode *E) {
-    LegalizedNodes.erase(N);
-    if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
-      ++LegalizePosition;
-  }
-
-  virtual void NodeUpdated(SDNode *N) {}
+  void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
+  void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
 };
 }
 
@@ -183,37 +195,145 @@
 }
 
 void SelectionDAGLegalize::LegalizeDAG() {
+  LastCALLSEQ_END = DAG.getEntryNode();
+  IsLegalizingCall = false;
+
+  // The legalize process is inherently a bottom-up recursive process (users
+  // legalize their uses before themselves).  Given infinite stack space, we
+  // could just start legalizing on the root and traverse the whole graph.  In
+  // practice however, this causes us to run out of stack space on large basic
+  // blocks.  To avoid this problem, compute an ordering of the nodes where each
+  // node is only legalized after all of its operands are legalized.
   DAG.AssignTopologicalOrder();
+  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
+       E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
+    LegalizeOp(SDValue(I, 0));
+
+  // Finally, it's possible the root changed.  Get the new root.
+  SDValue OldRoot = DAG.getRoot();
+  assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
+  DAG.setRoot(LegalizedNodes[OldRoot]);
 
-  // Visit all the nodes. We start in topological order, so that we see
-  // nodes with their original operands intact. Legalization can produce
-  // new nodes which may themselves need to be legalized. Iterate until all
-  // nodes have been legalized.
-  for (;;) {
-    bool AnyLegalized = false;
-    for (LegalizePosition = DAG.allnodes_end();
-         LegalizePosition != DAG.allnodes_begin(); ) {
-      --LegalizePosition;
-
-      SDNode *N = LegalizePosition;
-      if (LegalizedNodes.insert(N)) {
-        AnyLegalized = true;
-        LegalizeOp(N);
-      }
+  LegalizedNodes.clear();
+
+  // Remove dead nodes now.
+  DAG.RemoveDeadNodes();
+}
+
+
+/// FindCallEndFromCallStart - Given a chained node that is part of a call
+/// sequence, find the CALLSEQ_END node that terminates the call sequence.
+static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
+  // Nested CALLSEQ_START/END constructs aren't yet legal,
+  // but we can DTRT and handle them correctly here.
+  if (Node->getOpcode() == ISD::CALLSEQ_START)
+    depth++;
+  else if (Node->getOpcode() == ISD::CALLSEQ_END) {
+    depth--;
+    if (depth == 0)
+      return Node;
+  }
+  if (Node->use_empty())
+    return 0;   // No CallSeqEnd
+
+  // The chain is usually at the end.
+  SDValue TheChain(Node, Node->getNumValues()-1);
+  if (TheChain.getValueType() != MVT::Other) {
+    // Sometimes it's at the beginning.
+    TheChain = SDValue(Node, 0);
+    if (TheChain.getValueType() != MVT::Other) {
+      // Otherwise, hunt for it.
+      for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
+        if (Node->getValueType(i) == MVT::Other) {
+          TheChain = SDValue(Node, i);
+          break;
+        }
+
+      // Otherwise, we walked into a node without a chain.
+      if (TheChain.getValueType() != MVT::Other)
+        return 0;
     }
-    if (!AnyLegalized)
+  }
+
+  for (SDNode::use_iterator UI = Node->use_begin(),
+       E = Node->use_end(); UI != E; ++UI) {
+
+    // Make sure to only follow users of our token chain.
+    SDNode *User = *UI;
+    for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
+      if (User->getOperand(i) == TheChain)
+        if (SDNode *Result = FindCallEndFromCallStart(User, depth))
+          return Result;
+  }
+  return 0;
+}
+
+/// FindCallStartFromCallEnd - Given a chained node that is part of a call
+/// sequence, find the CALLSEQ_START node that initiates the call sequence.
+static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
+  int nested = 0;
+  assert(Node && "Didn't find callseq_start for a call??");
+  while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
+    Node = Node->getOperand(0).getNode();
+    assert(Node->getOperand(0).getValueType() == MVT::Other &&
+           "Node doesn't have a token chain argument!");
+    switch (Node->getOpcode()) {
+    default:
+      break;
+    case ISD::CALLSEQ_START:
+      if (!nested)
+        return Node;
+      nested--;
+      break;
+    case ISD::CALLSEQ_END:
+      nested++;
       break;
+    }
+  }
+  return 0;
+}
 
+/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
+/// see if any uses can reach Dest.  If no dest operands can get to dest,
+/// legalize them, legalize ourself, and return false, otherwise, return true.
+///
+/// Keep track of the nodes we fine that actually do lead to Dest in
+/// NodesLeadingTo.  This avoids retraversing them exponential number of times.
+///
+bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
+                                     SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
+  if (N == Dest) return true;  // N certainly leads to Dest :)
+
+  // If we've already processed this node and it does lead to Dest, there is no
+  // need to reprocess it.
+  if (NodesLeadingTo.count(N)) return true;
+
+  // If the first result of this node has been already legalized, then it cannot
+  // reach N.
+  if (LegalizedNodes.count(SDValue(N, 0))) return false;
+
+  // Okay, this node has not already been legalized.  Check and legalize all
+  // operands.  If none lead to Dest, then we can legalize this node.
+  bool OperandsLeadToDest = false;
+  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
+    OperandsLeadToDest |=     // If an operand leads to Dest, so do we.
+      LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
+                                   NodesLeadingTo);
+
+  if (OperandsLeadToDest) {
+    NodesLeadingTo.insert(N);
+    return true;
   }
 
-  // Remove dead nodes now.
-  DAG.RemoveDeadNodes();
+  // Okay, this node looks safe, legalize it and return false.
+  LegalizeOp(SDValue(N, 0));
+  return false;
 }
 
 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
 /// a load from the constant pool.
-SDValue
-SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
+static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
+                                SelectionDAG &DAG, const TargetLowering &TLI) {
   bool Extend = false;
   DebugLoc dl = CFP->getDebugLoc();
 
@@ -249,25 +369,20 @@
 
   SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
   unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
-  if (Extend) {
-    SDValue Result =
-      DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
-                     DAG.getEntryNode(),
-                     CPIdx, MachinePointerInfo::getConstantPool(),
-                     VT, false, false, Alignment);
-    return Result;
-  }
-  SDValue Result =
-    DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
-                MachinePointerInfo::getConstantPool(), false, false,
-                Alignment);
-  return Result;
+  if (Extend)
+    return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
+                          DAG.getEntryNode(),
+                          CPIdx, MachinePointerInfo::getConstantPool(),
+                          VT, false, false, Alignment);
+  return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
+                     MachinePointerInfo::getConstantPool(), false, false,
+                     Alignment);
 }
 
 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
-static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
-                                 const TargetLowering &TLI,
-                                 SelectionDAG::DAGUpdateListener *DUL) {
+static
+SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
+                             const TargetLowering &TLI) {
   SDValue Chain = ST->getChain();
   SDValue Ptr = ST->getBasePtr();
   SDValue Val = ST->getValue();
@@ -282,10 +397,8 @@
       // same size, then a (misaligned) int store.
       // FIXME: Does not handle truncating floating point stores!
       SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
-      Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
-                           ST->isVolatile(), ST->isNonTemporal(), Alignment);
-      DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
-      return;
+      return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
+                          ST->isVolatile(), ST->isNonTemporal(), Alignment);
     }
     // Do a (aligned) store to a stack slot, then copy from the stack slot
     // to the final destination using (unaligned) integer loads and stores.
@@ -345,11 +458,8 @@
                                        ST->isNonTemporal(),
                                        MinAlign(ST->getAlignment(), Offset)));
     // The order of the stores doesn't matter - say it with a TokenFactor.
-    SDValue Result =
-      DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
-                  Stores.size());
-    DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
-    return;
+    return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
+                       Stores.size());
   }
   assert(ST->getMemoryVT().isInteger() &&
          !ST->getMemoryVT().isVector() &&
@@ -378,16 +488,13 @@
                              NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
                              Alignment);
 
-  SDValue Result =
-    DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
-  DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL);
+  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
 }
 
 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
-static void
-ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
-                    const TargetLowering &TLI,
-                    SDValue &ValResult, SDValue &ChainResult) {
+static
+SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
+                            const TargetLowering &TLI) {
   SDValue Chain = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
   EVT VT = LD->getValueType(0);
@@ -405,9 +512,8 @@
       if (VT.isFloatingPoint() && LoadedVT != VT)
         Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
 
-      ValResult = Result;
-      ChainResult = Chain;
-      return;
+      SDValue Ops[] = { Result, Chain };
+      return DAG.getMergeValues(Ops, 2, dl);
     }
 
     // Copy the value to a (aligned) stack slot using (unaligned) integer
@@ -466,9 +572,8 @@
                           MachinePointerInfo(), LoadedVT, false, false, 0);
 
     // Callers expect a MERGE_VALUES node.
-    ValResult = Load;
-    ChainResult = TF;
-    return;
+    SDValue Ops[] = { Load, TF };
+    return DAG.getMergeValues(Ops, 2, dl);
   }
   assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
          "Unaligned load of unsupported type.");
@@ -521,8 +626,8 @@
   SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                              Hi.getValue(1));
 
-  ValResult = Result;
-  ChainResult = TF;
+  SDValue Ops[] = { Result, TF };
+  return DAG.getMergeValues(Ops, 2, dl);
 }
 
 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
@@ -658,10 +763,11 @@
 
 /// LegalizeOp - Return a legal replacement for the given operation, with
 /// all legal operands.
-void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
-  if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
-    return;
+SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
+  if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
+    return Op;
 
+  SDNode *Node = Op.getNode();
   DebugLoc dl = Node->getDebugLoc();
 
   for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
@@ -676,7 +782,13 @@
             Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
            "Unexpected illegal type!");
 
+  // Note that LegalizeOp may be reentered even from single-use nodes, which
+  // means that we always must cache transformed nodes.
+  DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
+  if (I != LegalizedNodes.end()) return I->second;
+
   SDValue Tmp1, Tmp2, Tmp3, Tmp4;
+  SDValue Result = Op;
   bool isCustom = false;
 
   // Figure out the correct action; the way to query this varies by opcode
@@ -770,6 +882,17 @@
     if (Action == TargetLowering::Legal)
       Action = TargetLowering::Custom;
     break;
+  case ISD::BUILD_VECTOR:
+    // A weird case: legalization for BUILD_VECTOR never legalizes the
+    // operands!
+    // FIXME: This really sucks... changing it isn't semantically incorrect,
+    // but it massively pessimizes the code for floating-point BUILD_VECTORs
+    // because ConstantFP operands get legalized into constant pool loads
+    // before the BUILD_VECTOR code can see them.  It doesn't usually bite,
+    // though, because BUILD_VECTORS usually get lowered into other nodes
+    // which get legalized properly.
+    SimpleFinishLegalizing = false;
+    break;
   default:
     if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
       Action = TargetLowering::Legal;
@@ -780,11 +903,22 @@
   }
 
   if (SimpleFinishLegalizing) {
-    SmallVector<SDValue, 8> Ops;
+    SmallVector<SDValue, 8> Ops, ResultVals;
     for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
-      Ops.push_back(Node->getOperand(i));
+      Ops.push_back(LegalizeOp(Node->getOperand(i)));
     switch (Node->getOpcode()) {
     default: break;
+    case ISD::BR:
+    case ISD::BRIND:
+    case ISD::BR_JT:
+    case ISD::BR_CC:
+    case ISD::BRCOND:
+      // Branches tweak the chain to include LastCALLSEQ_END
+      Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
+                           LastCALLSEQ_END);
+      Ops[0] = LegalizeOp(Ops[0]);
+      LastCALLSEQ_END = DAG.getEntryNode();
+      break;
     case ISD::SHL:
     case ISD::SRL:
     case ISD::SRA:
@@ -792,66 +926,57 @@
     case ISD::ROTR:
       // Legalizing shifts/rotates requires adjusting the shift amount
       // to the appropriate width.
-      if (!Ops[1].getValueType().isVector()) {
-        SDValue SAO = DAG.getShiftAmountOperand(Ops[0].getValueType(), Ops[1]);
-        HandleSDNode Handle(SAO);
-        LegalizeOp(SAO.getNode());
-        Ops[1] = Handle.getValue();
-      }
+      if (!Ops[1].getValueType().isVector())
+        Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
+                                                      Ops[1]));
       break;
     case ISD::SRL_PARTS:
     case ISD::SRA_PARTS:
     case ISD::SHL_PARTS:
       // Legalizing shifts/rotates requires adjusting the shift amount
       // to the appropriate width.
-      if (!Ops[2].getValueType().isVector()) {
-        SDValue SAO = DAG.getShiftAmountOperand(Ops[0].getValueType(), Ops[2]);
-        HandleSDNode Handle(SAO);
-        LegalizeOp(SAO.getNode());
-        Ops[2] = Handle.getValue();
-      }
+      if (!Ops[2].getValueType().isVector())
+        Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
+                                                      Ops[2]));
       break;
     }
 
-    SDNode *NewNode = DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
-    if (NewNode != Node) {
-      DAG.ReplaceAllUsesWith(Node, NewNode, this);
-      for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
-        DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
-      DAG.RemoveDeadNode(Node, this);
-      Node = NewNode;
-    }
+    Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
+                                            Ops.size()), 0);
     switch (Action) {
     case TargetLowering::Legal:
-      return;
+      for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
+        ResultVals.push_back(Result.getValue(i));
+      break;
     case TargetLowering::Custom:
       // FIXME: The handling for custom lowering with multiple results is
       // a complete mess.
-      Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
+      Tmp1 = TLI.LowerOperation(Result, DAG);
       if (Tmp1.getNode()) {
-        SmallVector<SDValue, 8> ResultVals;
         for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
           if (e == 1)
             ResultVals.push_back(Tmp1);
           else
             ResultVals.push_back(Tmp1.getValue(i));
         }
-        if (Tmp1.getNode() != Node || Tmp1.getResNo() != 0) {
-          DAG.ReplaceAllUsesWith(Node, ResultVals.data(), this);
-          for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
-            DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
-          DAG.RemoveDeadNode(Node, this);
-        }
-        return;
+        break;
       }
 
       // FALL THROUGH
     case TargetLowering::Expand:
-      ExpandNode(Node);
-      return;
+      ExpandNode(Result.getNode(), ResultVals);
+      break;
     case TargetLowering::Promote:
-      PromoteNode(Node);
-      return;
+      PromoteNode(Result.getNode(), ResultVals);
+      break;
+    }
+    if (!ResultVals.empty()) {
+      for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
+        if (ResultVals[i] != SDValue(Node, i))
+          ResultVals[i] = LegalizeOp(ResultVals[i]);
+        AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
+      }
+      return ResultVals[Op.getResNo()];
     }
   }
 
@@ -864,20 +989,155 @@
 #endif
     assert(0 && "Do not know how to legalize this operator!");
 
-  case ISD::CALLSEQ_START:
-  case ISD::CALLSEQ_END:
+  case ISD::SRA:
+  case ISD::SRL:
+  case ISD::SHL: {
+    // Scalarize vector SRA/SRL/SHL.
+    EVT VT = Node->getValueType(0);
+    assert(VT.isVector() && "Unable to legalize non-vector shift");
+    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
+    unsigned NumElem = VT.getVectorNumElements();
+
+    SmallVector<SDValue, 8> Scalars;
+    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
+      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+                               VT.getScalarType(),
+                               Node->getOperand(0), DAG.getIntPtrConstant(Idx));
+      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+                               VT.getScalarType(),
+                               Node->getOperand(1), DAG.getIntPtrConstant(Idx));
+      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
+                                    VT.getScalarType(), Ex, Sh));
+    }
+    Result = DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
+                         &Scalars[0], Scalars.size());
     break;
+  }
+
+  case ISD::BUILD_VECTOR:
+    switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
+    default: assert(0 && "This action is not supported yet!");
+    case TargetLowering::Custom:
+      Tmp3 = TLI.LowerOperation(Result, DAG);
+      if (Tmp3.getNode()) {
+        Result = Tmp3;
+        break;
+      }
+      // FALLTHROUGH
+    case TargetLowering::Expand:
+      Result = ExpandBUILD_VECTOR(Result.getNode());
+      break;
+    }
+    break;
+  case ISD::CALLSEQ_START: {
+    SDNode *CallEnd = FindCallEndFromCallStart(Node);
+
+    // Recursively Legalize all of the inputs of the call end that do not lead
+    // to this call start.  This ensures that any libcalls that need be inserted
+    // are inserted *before* the CALLSEQ_START.
+    {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
+    for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
+      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
+                                   NodesLeadingTo);
+    }
+
+    // Now that we have legalized all of the inputs (which may have inserted
+    // libcalls), create the new CALLSEQ_START node.
+    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
+
+    // Merge in the last call to ensure that this call starts after the last
+    // call ended.
+    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
+      Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+                         Tmp1, LastCALLSEQ_END);
+      Tmp1 = LegalizeOp(Tmp1);
+    }
+
+    // Do not try to legalize the target-specific arguments (#1+).
+    if (Tmp1 != Node->getOperand(0)) {
+      SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
+      Ops[0] = Tmp1;
+      Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
+                                              Ops.size()), Result.getResNo());
+    }
+
+    // Remember that the CALLSEQ_START is legalized.
+    AddLegalizedOperand(Op.getValue(0), Result);
+    if (Node->getNumValues() == 2)    // If this has a flag result, remember it.
+      AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
+
+    // Now that the callseq_start and all of the non-call nodes above this call
+    // sequence have been legalized, legalize the call itself.  During this
+    // process, no libcalls can/will be inserted, guaranteeing that no calls
+    // can overlap.
+    assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
+    // Note that we are selecting this call!
+    LastCALLSEQ_END = SDValue(CallEnd, 0);
+    IsLegalizingCall = true;
+
+    // Legalize the call, starting from the CALLSEQ_END.
+    LegalizeOp(LastCALLSEQ_END);
+    assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
+    return Result;
+  }
+  case ISD::CALLSEQ_END:
+    // If the CALLSEQ_START node hasn't been legalized first, legalize it.  This
+    // will cause this node to be legalized as well as handling libcalls right.
+    if (LastCALLSEQ_END.getNode() != Node) {
+      LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
+      DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
+      assert(I != LegalizedNodes.end() &&
+             "Legalizing the call start should have legalized this node!");
+      return I->second;
+    }
+
+    // Otherwise, the call start has been legalized and everything is going
+    // according to plan.  Just legalize ourselves normally here.
+    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
+    // Do not try to legalize the target-specific arguments (#1+), except for
+    // an optional flag input.
+    if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
+      if (Tmp1 != Node->getOperand(0)) {
+        SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
+        Ops[0] = Tmp1;
+        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                                &Ops[0], Ops.size()),
+                         Result.getResNo());
+      }
+    } else {
+      Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
+      if (Tmp1 != Node->getOperand(0) ||
+          Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
+        SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
+        Ops[0] = Tmp1;
+        Ops.back() = Tmp2;
+        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                                &Ops[0], Ops.size()),
+                         Result.getResNo());
+      }
+    }
+    assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
+    // This finishes up call legalization.
+    IsLegalizingCall = false;
+
+    // If the CALLSEQ_END node has a flag, remember that we legalized it.
+    AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
+    if (Node->getNumValues() == 2)
+      AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
+    return Result.getValue(Op.getResNo());
   case ISD::LOAD: {
     LoadSDNode *LD = cast<LoadSDNode>(Node);
-    Tmp1 = LD->getChain();   // Legalize the chain.
-    Tmp2 = LD->getBasePtr(); // Legalize the base pointer.
+    Tmp1 = LegalizeOp(LD->getChain());   // Legalize the chain.
+    Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
 
     ISD::LoadExtType ExtType = LD->getExtensionType();
     if (ExtType == ISD::NON_EXTLOAD) {
       EVT VT = Node->getValueType(0);
-      Node = DAG.UpdateNodeOperands(Node, Tmp1, Tmp2, LD->getOffset());
-      Tmp3 = SDValue(Node, 0);
-      Tmp4 = SDValue(Node, 1);
+      Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                              Tmp1, Tmp2, LD->getOffset()),
+                       Result.getResNo());
+      Tmp3 = Result.getValue(0);
+      Tmp4 = Result.getValue(1);
 
       switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
       default: assert(0 && "This action is not supported yet!");
@@ -888,16 +1148,20 @@
           Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
           unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
           if (LD->getAlignment() < ABIAlignment){
-            ExpandUnalignedLoad(cast<LoadSDNode>(Node),
-                                DAG, TLI, Tmp3, Tmp4);
+            Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
+                                         DAG, TLI);
+            Tmp3 = Result.getOperand(0);
+            Tmp4 = Result.getOperand(1);
+            Tmp3 = LegalizeOp(Tmp3);
+            Tmp4 = LegalizeOp(Tmp4);
           }
         }
         break;
       case TargetLowering::Custom:
         Tmp1 = TLI.LowerOperation(Tmp3, DAG);
         if (Tmp1.getNode()) {
-          Tmp3 = Tmp1;
-          Tmp4 = Tmp1.getValue(1);
+          Tmp3 = LegalizeOp(Tmp1);
+          Tmp4 = LegalizeOp(Tmp1.getValue(1));
         }
         break;
       case TargetLowering::Promote: {
@@ -909,16 +1173,16 @@
         Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
                            LD->isVolatile(), LD->isNonTemporal(),
                            LD->getAlignment());
-        Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1);
-        Tmp4 = Tmp1.getValue(1);
+        Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
+        Tmp4 = LegalizeOp(Tmp1.getValue(1));
         break;
       }
       }
       // Since loads produce two values, make sure to remember that we
       // legalized both of them.
-      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3);
-      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4);
-      return;
+      AddLegalizedOperand(SDValue(Node, 0), Tmp3);
+      AddLegalizedOperand(SDValue(Node, 1), Tmp4);
+      return Op.getResNo() ? Tmp4 : Tmp3;
     }
 
     EVT SrcVT = LD->getMemoryVT();
@@ -949,10 +1213,9 @@
       ISD::LoadExtType NewExtType =
         ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
 
-      SDValue Result =
-        DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
-                       Tmp1, Tmp2, LD->getPointerInfo(),
-                       NVT, isVolatile, isNonTemporal, Alignment);
+      Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
+                              Tmp1, Tmp2, LD->getPointerInfo(),
+                              NVT, isVolatile, isNonTemporal, Alignment);
 
       Ch = Result.getValue(1); // The chain.
 
@@ -967,8 +1230,8 @@
                              Result.getValueType(), Result,
                              DAG.getValueType(SrcVT));
 
-      Tmp1 = Result;
-      Tmp2 = Ch;
+      Tmp1 = LegalizeOp(Result);
+      Tmp2 = LegalizeOp(Ch);
     } else if (SrcWidth & (SrcWidth - 1)) {
       // If not loading a power-of-2 number of bits, expand as two loads.
       assert(!SrcVT.isVector() && "Unsupported extload!");
@@ -1011,7 +1274,7 @@
                                       TLI.getShiftAmountTy(Hi.getValueType())));
 
         // Join the hi and lo parts.
-        Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
+        Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
       } else {
         // Big endian - avoid unaligned loads.
         // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD at +2:i8
@@ -1041,10 +1304,11 @@
                                       TLI.getShiftAmountTy(Hi.getValueType())));
 
         // Join the hi and lo parts.
-        Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
+        Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
       }
 
-      Tmp2 = Ch;
+      Tmp1 = LegalizeOp(Result);
+      Tmp2 = LegalizeOp(Ch);
     } else {
       switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
       default: assert(0 && "This action is not supported yet!");
@@ -1052,16 +1316,17 @@
         isCustom = true;
         // FALLTHROUGH
       case TargetLowering::Legal:
-        Node = DAG.UpdateNodeOperands(Node,
-                                      Tmp1, Tmp2, LD->getOffset());
-        Tmp1 = SDValue(Node, 0);
-        Tmp2 = SDValue(Node, 1);
+        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                                Tmp1, Tmp2, LD->getOffset()),
+                         Result.getResNo());
+        Tmp1 = Result.getValue(0);
+        Tmp2 = Result.getValue(1);
 
         if (isCustom) {
-          Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG);
+          Tmp3 = TLI.LowerOperation(Result, DAG);
           if (Tmp3.getNode()) {
-            Tmp1 = Tmp3;
-            Tmp2 = Tmp3.getValue(1);
+            Tmp1 = LegalizeOp(Tmp3);
+            Tmp2 = LegalizeOp(Tmp3.getValue(1));
           }
         } else {
           // If this is an unaligned load and the target doesn't support it,
@@ -1072,8 +1337,12 @@
             unsigned ABIAlignment =
               TLI.getTargetData()->getABITypeAlignment(Ty);
             if (LD->getAlignment() < ABIAlignment){
-              ExpandUnalignedLoad(cast<LoadSDNode>(Node),
-                                  DAG, TLI, Tmp1, Tmp2);
+              Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
+                                           DAG, TLI);
+              Tmp1 = Result.getOperand(0);
+              Tmp2 = Result.getOperand(1);
+              Tmp1 = LegalizeOp(Tmp1);
+              Tmp2 = LegalizeOp(Tmp2);
             }
           }
         }
@@ -1094,8 +1363,9 @@
           case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
           default: llvm_unreachable("Unexpected extend load type!");
           }
-          Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
-          Tmp2 = Load.getValue(1);
+          Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
+          Tmp1 = LegalizeOp(Result);  // Relegalize new nodes.
+          Tmp2 = LegalizeOp(Load.getValue(1));
           break;
         }
 
@@ -1110,10 +1380,10 @@
                "EXTLOAD should always be supported!");
         // Turn the unsupported load into an EXTLOAD followed by an explicit
         // zero/sign extend inreg.
-        SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
-                                        Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
-                                        LD->isVolatile(), LD->isNonTemporal(),
-                                        LD->getAlignment());
+        Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
+                                Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
+                                LD->isVolatile(), LD->isNonTemporal(),
+                                LD->getAlignment());
         SDValue ValRes;
         if (ExtType == ISD::SEXTLOAD)
           ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
@@ -1121,37 +1391,38 @@
                                Result, DAG.getValueType(SrcVT));
         else
           ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
-        Tmp1 = ValRes;
-        Tmp2 = Result.getValue(1);
+        Tmp1 = LegalizeOp(ValRes);  // Relegalize new nodes.
+        Tmp2 = LegalizeOp(Result.getValue(1));  // Relegalize new nodes.
         break;
       }
     }
 
     // Since loads produce two values, make sure to remember that we legalized
     // both of them.
-    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1);
-    DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2);
-    break;
+    AddLegalizedOperand(SDValue(Node, 0), Tmp1);
+    AddLegalizedOperand(SDValue(Node, 1), Tmp2);
+    return Op.getResNo() ? Tmp2 : Tmp1;
   }
   case ISD::STORE: {
     StoreSDNode *ST = cast<StoreSDNode>(Node);
-    Tmp1 = ST->getChain();
-    Tmp2 = ST->getBasePtr();
+    Tmp1 = LegalizeOp(ST->getChain());    // Legalize the chain.
+    Tmp2 = LegalizeOp(ST->getBasePtr());  // Legalize the pointer.
     unsigned Alignment = ST->getAlignment();
     bool isVolatile = ST->isVolatile();
     bool isNonTemporal = ST->isNonTemporal();
 
     if (!ST->isTruncatingStore()) {
       if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
-        DAG.ReplaceAllUsesWith(ST, OptStore, this);
+        Result = SDValue(OptStore, 0);
         break;
       }
 
       {
-        Tmp3 = ST->getValue();
-        Node = DAG.UpdateNodeOperands(Node,
-                                      Tmp1, Tmp3, Tmp2,
-                                      ST->getOffset());
+        Tmp3 = LegalizeOp(ST->getValue());
+        Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                                Tmp1, Tmp3, Tmp2,
+                                                ST->getOffset()),
+                         Result.getResNo());
 
         EVT VT = Tmp3.getValueType();
         switch (TLI.getOperationAction(ISD::STORE, VT)) {
@@ -1163,31 +1434,27 @@
             Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
             unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
             if (ST->getAlignment() < ABIAlignment)
-              ExpandUnalignedStore(cast<StoreSDNode>(Node),
-                                   DAG, TLI, this);
+              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
+                                            DAG, TLI);
           }
           break;
         case TargetLowering::Custom:
-          Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
-          if (Tmp1.getNode())
-            DAG.ReplaceAllUsesWith(SDValue(Node, 0), Tmp1, this);
+          Tmp1 = TLI.LowerOperation(Result, DAG);
+          if (Tmp1.getNode()) Result = Tmp1;
           break;
-        case TargetLowering::Promote: {
+        case TargetLowering::Promote:
           assert(VT.isVector() && "Unknown legal promote case!");
           Tmp3 = DAG.getNode(ISD::BITCAST, dl,
                              TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
-          SDValue Result =
-            DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
-                         ST->getPointerInfo(), isVolatile,
-                         isNonTemporal, Alignment);
-          DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
+          Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
+                                ST->getPointerInfo(), isVolatile,
+                                isNonTemporal, Alignment);
           break;
         }
-        }
         break;
       }
     } else {
-      Tmp3 = ST->getValue();
+      Tmp3 = LegalizeOp(ST->getValue());
 
       EVT StVT = ST->getMemoryVT();
       unsigned StWidth = StVT.getSizeInBits();
@@ -1199,10 +1466,8 @@
         EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
                                     StVT.getStoreSizeInBits());
         Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
-        SDValue Result =
-          DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
-                            NVT, isVolatile, isNonTemporal, Alignment);
-        DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
+        Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                                   NVT, isVolatile, isNonTemporal, Alignment);
       } else if (StWidth & (StWidth - 1)) {
         // If not storing a power-of-2 number of bits, expand as two stores.
         assert(!StVT.isVector() && "Unsupported truncstore!");
@@ -1256,13 +1521,14 @@
         }
 
         // The order of the stores doesn't matter.
-        SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
-        DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
+        Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
       } else {
         if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
             Tmp2 != ST->getBasePtr())
-          Node = DAG.UpdateNodeOperands(Node, Tmp1, Tmp3, Tmp2,
-                                        ST->getOffset());
+          Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
+                                                  Tmp1, Tmp3, Tmp2,
+                                                  ST->getOffset()),
+                           Result.getResNo());
 
         switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
         default: assert(0 && "This action is not supported yet!");
@@ -1273,13 +1539,12 @@
             Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
             unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
             if (ST->getAlignment() < ABIAlignment)
-              ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
+              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
+                                            DAG, TLI);
           }
           break;
         case TargetLowering::Custom:
-          DAG.ReplaceAllUsesWith(SDValue(Node, 0),
-                                 TLI.LowerOperation(SDValue(Node, 0), DAG),
-                                 this);
+          Result = TLI.LowerOperation(Result, DAG);
           break;
         case TargetLowering::Expand:
           assert(!StVT.isVector() &&
@@ -1288,10 +1553,8 @@
           // TRUNCSTORE:i16 i32 -> STORE i16
           assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
           Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
-          SDValue Result =
-            DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
-                         isVolatile, isNonTemporal, Alignment);
-          DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
+          Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
+                                isVolatile, isNonTemporal, Alignment);
           break;
         }
       }
@@ -1299,6 +1562,17 @@
     break;
   }
   }
+  assert(Result.getValueType() == Op.getValueType() &&
+         "Bad legalization!");
+
+  // Make sure that the generated code is itself legal.
+  if (Result != Op)
+    Result = LegalizeOp(Result);
+
+  // Note that LegalizeOp may be reentered even from single-use nodes, which
+  // means that we always must cache transformed nodes.
+  AddLegalizedOperand(Op, Result);
+  return Result;
 }
 
 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
@@ -1737,6 +2011,7 @@
 // and leave the Hi part unset.
 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
                                             bool isSigned) {
+  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
   // The input chain to this libcall is the entry node of the function.
   // Legalizing the call will automatically add the previous call to the
   // dependence.
@@ -1755,6 +2030,7 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
+  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
 
   // isTailCall may be true since the callee does not reference caller stack
@@ -1770,6 +2046,10 @@
     // It's a tailcall, return the chain (which is the DAG root).
     return DAG.getRoot();
 
+  // Legalize the call sequence, starting with the chain.  This will advance
+  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
+  // was added by LowerCallTo (guaranteeing proper serialization of calls).
+  LegalizeOp(CallInfo.second);
   return CallInfo.first;
 }
 
@@ -1799,6 +2079,11 @@
                   /*isReturnValueUsed=*/true,
                   Callee, Args, DAG, dl);
 
+  // Legalize the call sequence, starting with the chain.  This will advance
+  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
+  // was added by LowerCallTo (guaranteeing proper serialization of calls).
+  LegalizeOp(CallInfo.second);
+
   return CallInfo.first;
 }
 
@@ -1808,6 +2093,7 @@
 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
                                          SDNode *Node,
                                          bool isSigned) {
+  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
   SDValue InChain = Node->getOperand(0);
 
   TargetLowering::ArgListTy Args;
@@ -1824,6 +2110,7 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
+  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
@@ -1831,6 +2118,10 @@
                     /*isReturnValueUsed=*/true,
                     Callee, Args, DAG, Node->getDebugLoc());
 
+  // Legalize the call sequence, starting with the chain.  This will advance
+  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
+  // was added by LowerCallTo (guaranteeing proper serialization of calls).
+  LegalizeOp(CallInfo.second);
   return CallInfo;
 }
 
@@ -1956,14 +2247,20 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
+  // Splice the libcall in wherever FindInputOutputChains tells us to.
   DebugLoc dl = Node->getDebugLoc();
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
                     0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
                     /*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
 
+  // Legalize the call sequence, starting with the chain.  This will advance
+  // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
+  // was added by LowerCallTo (guaranteeing proper serialization of calls).
+  LegalizeOp(CallInfo.second);
+
   // Remainder is loaded back from the stack frame.
-  SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
+  SDValue Rem = DAG.getLoad(RetVT, dl, LastCALLSEQ_END, FIPtr,
                             MachinePointerInfo(), false, false, 0);
   Results.push_back(CallInfo.first);
   Results.push_back(Rem);
@@ -2155,13 +2452,11 @@
                              MachinePointerInfo::getConstantPool(),
                              false, false, Alignment);
   else {
-    SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
-                                  DAG.getEntryNode(), CPIdx,
-                                  MachinePointerInfo::getConstantPool(),
-                                  MVT::f32, false, false, Alignment);
-    HandleSDNode Handle(Load);
-    LegalizeOp(Load.getNode());
-    FudgeInReg = Handle.getValue();
+    FudgeInReg =
+      LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
+                                DAG.getEntryNode(), CPIdx,
+                                MachinePointerInfo::getConstantPool(),
+                                MVT::f32, false, false, Alignment));
   }
 
   return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
@@ -2485,8 +2780,8 @@
   return ExpandChainLibCall(LC, Node, false);
 }
 
-void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
-  SmallVector<SDValue, 8> Results;
+void SelectionDAGLegalize::ExpandNode(SDNode *Node,
+                                      SmallVectorImpl<SDValue> &Results) {
   DebugLoc dl = Node->getDebugLoc();
   SDValue Tmp1, Tmp2, Tmp3, Tmp4;
   switch (Node->getOpcode()) {
@@ -2934,8 +3229,10 @@
     ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
     // Check to see if this FP immediate is already legal.
     // If this is a legal constant, turn it into a TargetConstantFP node.
-    if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
-      Results.push_back(ExpandConstantFP(CFP, true));
+    if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
+      Results.push_back(SDValue(Node, 0));
+    else
+      Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
     break;
   }
   case ISD::EHSELECTION: {
@@ -3181,10 +3478,6 @@
                                DAG.getIntPtrConstant(0));
       TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
                             DAG.getIntPtrConstant(1));
-      // Ret is a node with an illegal type. Because such things are not
-      // generally permitted during this phase of legalization, delete the
-      // node. The above EXTRACT_ELEMENT nodes should have been folded.
-      DAG.DeleteNode(Ret.getNode());
     }
 
     if (isSigned) {
@@ -3325,6 +3618,7 @@
 
     LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
                           Tmp2, Tmp3, Tmp4, dl);
+    LastCALLSEQ_END = DAG.getEntryNode();
 
     assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
     Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
@@ -3334,35 +3628,6 @@
     Results.push_back(Tmp1);
     break;
   }
-  case ISD::BUILD_VECTOR:
-    Results.push_back(ExpandBUILD_VECTOR(Node));
-    break;
-  case ISD::SRA:
-  case ISD::SRL:
-  case ISD::SHL: {
-    // Scalarize vector SRA/SRL/SHL.
-    EVT VT = Node->getValueType(0);
-    assert(VT.isVector() && "Unable to legalize non-vector shift");
-    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
-    unsigned NumElem = VT.getVectorNumElements();
-
-    SmallVector<SDValue, 8> Scalars;
-    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
-      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
-                               VT.getScalarType(),
-                               Node->getOperand(0), DAG.getIntPtrConstant(Idx));
-      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
-                               VT.getScalarType(),
-                               Node->getOperand(1), DAG.getIntPtrConstant(Idx));
-      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
-                                    VT.getScalarType(), Ex, Sh));
-    }
-    SDValue Result =
-      DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
-                  &Scalars[0], Scalars.size());
-    DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this);
-    break;
-  }
   case ISD::GLOBAL_OFFSET_TABLE:
   case ISD::GlobalAddress:
   case ISD::GlobalTLSAddress:
@@ -3373,16 +3638,13 @@
   case ISD::INTRINSIC_WO_CHAIN:
   case ISD::INTRINSIC_VOID:
     // FIXME: Custom lowering for these operations shouldn't return null!
+    for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
+      Results.push_back(SDValue(Node, i));
     break;
   }
-
-  // Replace the original node with the legalized result.
-  if (!Results.empty())
-    DAG.ReplaceAllUsesWith(Node, Results.data(), this);
 }
-
-void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
-  SmallVector<SDValue, 8> Results;
+void SelectionDAGLegalize::PromoteNode(SDNode *Node,
+                                       SmallVectorImpl<SDValue> &Results) {
   EVT OVT = Node->getValueType(0);
   if (Node->getOpcode() == ISD::UINT_TO_FP ||
       Node->getOpcode() == ISD::SINT_TO_FP ||
@@ -3510,10 +3772,6 @@
     break;
   }
   }
-
-  // Replace the original node with the legalized result.
-  if (!Results.empty())
-    DAG.ReplaceAllUsesWith(Node, Results.data(), this);
 }
 
 // SelectionDAG::Legalize - This is the entry point for the file.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Fri Oct 28 19:41:52 2011
@@ -1084,6 +1084,7 @@
   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
                                          TLI.getPointerTy());
 
+  // Splice the libcall in wherever FindInputOutputChains tells us to.
   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
   std::pair<SDValue, SDValue> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Oct 28 19:41:52 2011
@@ -315,10 +315,8 @@
   IssueCount = 0;
   MinAvailableCycle = DisableSchedCycles ? 0 : UINT_MAX;
   NumLiveRegs = 0;
-  // Allocate slots for each physical register, plus one for a special register
-  // to track the virtual resource of a calling sequence.
-  LiveRegDefs.resize(TRI->getNumRegs() + 1, NULL);
-  LiveRegGens.resize(TRI->getNumRegs() + 1, NULL);
+  LiveRegDefs.resize(TRI->getNumRegs(), NULL);
+  LiveRegGens.resize(TRI->getNumRegs(), NULL);
 
   // Build the scheduling graph.
   BuildSchedGraph(NULL);
@@ -388,90 +386,6 @@
   }
 }
 
-/// IsChainDependent - Test if Outer is reachable from Inner through
-/// chain dependencies.
-static bool IsChainDependent(SDNode *Outer, SDNode *Inner) {
-  SDNode *N = Outer;
-  for (;;) {
-    if (N == Inner)
-      return true;
-    if (N->getOpcode() == ISD::TokenFactor) {
-      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-        if (IsChainDependent(N->getOperand(i).getNode(), Inner))
-          return true;
-      return false;
-    }
-    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-      if (N->getOperand(i).getValueType() == MVT::Other) {
-        N = N->getOperand(i).getNode();
-        goto found_chain_operand;
-      }
-    return false;
-  found_chain_operand:;
-    if (N->getOpcode() == ISD::EntryToken)
-      return false;
-  }
-}
-
-/// FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate
-/// the corresponding (lowered) CALLSEQ_BEGIN node.
-///
-/// NestLevel and MaxNested are used in recursion to indcate the current level
-/// of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum
-/// level seen so far.
-///
-/// TODO: It would be better to give CALLSEQ_END an explicit operand to point
-/// to the corresponding CALLSEQ_BEGIN to avoid needing to search for it.
-static SDNode *
-FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest,
-                 const TargetInstrInfo *TII) {
-  for (;;) {
-    // For a TokenFactor, examine each operand. There may be multiple ways
-    // to get to the CALLSEQ_BEGIN, but we need to find the path with the
-    // most nesting in order to ensure that we find the corresponding match.
-    if (N->getOpcode() == ISD::TokenFactor) {
-      SDNode *Best = 0;
-      unsigned BestMaxNest = MaxNest;
-      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
-        unsigned MyNestLevel = NestLevel;
-        unsigned MyMaxNest = MaxNest;
-        if (SDNode *New = FindCallSeqStart(N->getOperand(i).getNode(),
-                                           MyNestLevel, MyMaxNest, TII))
-          if (!Best || (MyMaxNest > BestMaxNest)) {
-            Best = New;
-            BestMaxNest = MyMaxNest;
-          }
-      }
-      assert(Best);
-      MaxNest = BestMaxNest;
-      return Best;
-    }
-    // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
-    if (N->isMachineOpcode()) {
-      if (N->getMachineOpcode() ==
-          (unsigned)TII->getCallFrameDestroyOpcode()) {
-        ++NestLevel;
-        MaxNest = std::max(MaxNest, NestLevel);
-      } else if (N->getMachineOpcode() ==
-                 (unsigned)TII->getCallFrameSetupOpcode()) {
-        --NestLevel;
-        if (NestLevel == 0)
-          return N;
-      }
-    }
-    // Otherwise, find the chain and continue climbing.
-    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-      if (N->getOperand(i).getValueType() == MVT::Other) {
-        N = N->getOperand(i).getNode();
-        goto found_chain_operand;
-      }
-    return 0;
-  found_chain_operand:;
-    if (N->getOpcode() == ISD::EntryToken)
-      return 0;
-  }
-}
-
 /// Call ReleasePred for each predecessor, then update register live def/gen.
 /// Always update LiveRegDefs for a register dependence even if the current SU
 /// also defines the register. This effectively create one large live range
@@ -509,25 +423,6 @@
       }
     }
   }
-
-  // If we're scheduling a lowered CALLSEQ_END, find the corresponding CALLSEQ_BEGIN.
-  // Inject an artificial physical register dependence between these nodes, to
-  // prevent other calls from being interscheduled with them.
-  unsigned CallResource = TRI->getNumRegs();
-  if (!LiveRegDefs[CallResource])
-    for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode())
-      if (Node->isMachineOpcode() &&
-          Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
-        unsigned NestLevel = 0;
-        unsigned MaxNest = 0;
-        SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
-
-        SUnit *Def = &SUnits[N->getNodeId()];
-        ++NumLiveRegs;
-        LiveRegDefs[CallResource] = Def;
-        LiveRegGens[CallResource] = SU;
-        break;
-      }
 }
 
 /// Check to see if any of the pending instructions are ready to issue.  If
@@ -710,20 +605,6 @@
       LiveRegGens[I->getReg()] = NULL;
     }
   }
-  // Release the special call resource dependence, if this is the beginning
-  // of a call.
-  unsigned CallResource = TRI->getNumRegs();
-  if (LiveRegDefs[CallResource] == SU)
-    for (const SDNode *SUNode = SU->getNode(); SUNode;
-         SUNode = SUNode->getGluedNode()) {
-      if (SUNode->isMachineOpcode() &&
-          SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
-        assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
-        --NumLiveRegs;
-        LiveRegDefs[CallResource] = NULL;
-        LiveRegGens[CallResource] = NULL;
-      }
-    }
 
   resetVRegCycle(SU);
 
@@ -780,33 +661,6 @@
     }
   }
 
-  // Reclaim the special call resource dependence, if this is the beginning
-  // of a call.
-  unsigned CallResource = TRI->getNumRegs();
-  for (const SDNode *SUNode = SU->getNode(); SUNode;
-       SUNode = SUNode->getGluedNode()) {
-    if (SUNode->isMachineOpcode() &&
-        SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
-      ++NumLiveRegs;
-      LiveRegDefs[CallResource] = SU;
-      LiveRegGens[CallResource] = NULL;
-    }
-  }
-
-  // Release the special call resource dependence, if this is the end
-  // of a call.
-  if (LiveRegGens[CallResource] == SU)
-    for (const SDNode *SUNode = SU->getNode(); SUNode;
-         SUNode = SUNode->getGluedNode()) {
-      if (SUNode->isMachineOpcode() &&
-          SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
-        assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
-        --NumLiveRegs;
-        LiveRegDefs[CallResource] = NULL;
-        LiveRegGens[CallResource] = NULL;
-      }
-    }
-
   for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
        I != E; ++I) {
     if (I->isAssignedRegDep()) {
@@ -1229,21 +1083,6 @@
 
     if (!Node->isMachineOpcode())
       continue;
-    // If we're in the middle of scheduling a call, don't begin scheduling
-    // another call. Also, don't allow any physical registers to be live across
-    // the call.
-    if (Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
-      // Add one here so that we include the special calling-sequence resource.
-      for (unsigned i = 0, e = TRI->getNumRegs() + 1; i != e; ++i)
-        if (LiveRegDefs[i]) {
-          SDNode *Gen = LiveRegGens[i]->getNode();
-          while (SDNode *Glued = Gen->getGluedNode())
-            Gen = Glued;
-          if (!IsChainDependent(Gen, Node) && RegAdded.insert(i))
-            LRegs.push_back(i);
-        }
-      continue;
-    }
     const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
     if (!MCID.ImplicitDefs)
       continue;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Oct 28 19:41:52 2011
@@ -5290,10 +5290,6 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
-
-  // If we just RAUW'd the root, take note.
-  if (FromN == getRoot())
-    setRoot(To);
 }
 
 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
@@ -5339,10 +5335,6 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
-
-  // If we just RAUW'd the root, take note.
-  if (From == getRoot().getNode())
-    setRoot(SDValue(To, getRoot().getResNo()));
 }
 
 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
@@ -5381,10 +5373,6 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
-
-  // If we just RAUW'd the root, take note.
-  if (From == getRoot().getNode())
-    setRoot(SDValue(To[getRoot().getResNo()]));
 }
 
 /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving
@@ -5443,10 +5431,6 @@
     // already exists there, recursively merge the results together.
     AddModifiedNodeToCSEMaps(User, &Listener);
   }
-
-  // If we just RAUW'd the root, take note.
-  if (From == getRoot())
-    setRoot(To);
 }
 
 namespace {

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Oct 28 19:41:52 2011
@@ -1353,10 +1353,12 @@
       SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
       SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
                                          MVT::i32);
+      // TODO: Disable AlwaysInline when it becomes possible
+      //       to emit a nested call sequence.
       MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
                                           Flags.getByValAlign(),
                                           /*isVolatile=*/false,
-                                          /*AlwaysInline=*/false,
+                                          /*AlwaysInline=*/true,
                                           MachinePointerInfo(0),
                                           MachinePointerInfo(0)));
 
@@ -4348,24 +4350,9 @@
       // If this is undef splat, generate it via "just" vdup, if possible.
       if (Lane == -1) Lane = 0;
 
-      // Test if V1 is a SCALAR_TO_VECTOR.
       if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
         return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
       }
-      // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
-      // (and probably will turn into a SCALAR_TO_VECTOR once legalization
-      // reaches it).
-      if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
-          !isa<ConstantSDNode>(V1.getOperand(0))) {
-        bool IsScalarToVector = true;
-        for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
-          if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
-            IsScalarToVector = false;
-            break;
-          }
-        if (IsScalarToVector)
-          return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
-      }
       return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
                          DAG.getConstant(Lane, MVT::i32));
     }

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Oct 28 19:41:52 2011
@@ -2114,9 +2114,7 @@
         HasNoSignedComparisonUses(Node))
       // Look past the truncate if CMP is the only use of it.
       N0 = N0.getOperand(0);
-    if ((N0.getNode()->getOpcode() == ISD::AND ||
-         (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
-        N0.getNode()->hasOneUse() &&
+    if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
         N0.getValueType() != MVT::i8 &&
         X86::isZeroNode(N1)) {
       ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Oct 28 19:41:52 2011
@@ -4220,29 +4220,6 @@
   return true;
 }
 
-// Test whether the given value is a vector value which will be legalized
-// into a load.
-static bool WillBeConstantPoolLoad(SDNode *N) {
-  if (N->getOpcode() != ISD::BUILD_VECTOR)
-    return false;
-
-  // Check for any non-constant elements.
-  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-    switch (N->getOperand(i).getNode()->getOpcode()) {
-    case ISD::UNDEF:
-    case ISD::ConstantFP:
-    case ISD::Constant:
-      break;
-    default:
-      return false;
-    }
-
-  // Vectors of all-zeros and all-ones are materialized with special
-  // instructions rather than being loaded.
-  return !ISD::isBuildVectorAllZeros(N) &&
-         !ISD::isBuildVectorAllOnes(N);
-}
-
 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
 /// match movlp{s|d}. The lower half elements should come from lower half of
 /// V1 (and in order), and the upper half elements should come from the upper
@@ -4258,7 +4235,7 @@
     return false;
   // Is V2 is a vector load, don't do this transformation. We will try to use
   // load folding shufps op.
-  if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
+  if (ISD::isNON_EXTLoad(V2))
     return false;
 
   unsigned NumElems = VT.getVectorNumElements();
@@ -6374,8 +6351,6 @@
   if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
     CanFoldLoad = true;
 
-  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
-
   // Both of them can't be memory operations though.
   if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
     CanFoldLoad = false;
@@ -6385,11 +6360,10 @@
       return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
 
     if (NumElems == 4)
-      // If we don't care about the second element, procede to use movss.
-      if (SVOp->getMaskElt(1) != -1)
-        return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
+      return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
   }
 
+  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
   // movl and movlp will both match v2i64, but v2i64 is never matched by
   // movl earlier because we make it strict to avoid messing with the movlp load
   // folding logic (see the code above getMOVLP call). Match it here then,
@@ -8707,9 +8681,8 @@
 
   // If condition flag is set by a X86ISD::CMP, then use it as the condition
   // setting operand in place of the X86ISD::SETCC.
-  unsigned CondOpcode = Cond.getOpcode();
-  if (CondOpcode == X86ISD::SETCC ||
-      CondOpcode == X86ISD::SETCC_CARRY) {
+  if (Cond.getOpcode() == X86ISD::SETCC ||
+      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
     CC = Cond.getOperand(0);
 
     SDValue Cmp = Cond.getOperand(1);
@@ -8726,39 +8699,6 @@
       Cond = Cmp;
       addTest = false;
     }
-  } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
-             CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
-             ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
-              Cond.getOperand(0).getValueType() != MVT::i8)) {
-    SDValue LHS = Cond.getOperand(0);
-    SDValue RHS = Cond.getOperand(1);
-    unsigned X86Opcode;
-    unsigned X86Cond;
-    SDVTList VTs;
-    switch (CondOpcode) {
-    case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
-    case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
-    case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
-    case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
-    case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
-    case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
-    default: llvm_unreachable("unexpected overflowing operator");
-    }
-    if (CondOpcode == ISD::UMULO)
-      VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
-                          MVT::i32);
-    else
-      VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
-
-    SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
-
-    if (CondOpcode == ISD::UMULO)
-      Cond = X86Op.getValue(2);
-    else
-      Cond = X86Op.getValue(1);
-
-    CC = DAG.getConstant(X86Cond, MVT::i8);
-    addTest = false;
   }
 
   if (addTest) {
@@ -8840,27 +8780,11 @@
   SDValue Dest  = Op.getOperand(2);
   DebugLoc dl = Op.getDebugLoc();
   SDValue CC;
-  bool Inverted = false;
 
   if (Cond.getOpcode() == ISD::SETCC) {
-    // Check for setcc([su]{add,sub,mul}o == 0).
-    if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
-        isa<ConstantSDNode>(Cond.getOperand(1)) &&
-        cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
-        Cond.getOperand(0).getResNo() == 1 &&
-        (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
-         Cond.getOperand(0).getOpcode() == ISD::UADDO ||
-         Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
-         Cond.getOperand(0).getOpcode() == ISD::USUBO ||
-         Cond.getOperand(0).getOpcode() == ISD::SMULO ||
-         Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
-      Inverted = true;
-      Cond = Cond.getOperand(0);
-    } else {
-      SDValue NewCond = LowerSETCC(Cond, DAG);
-      if (NewCond.getNode())
-        Cond = NewCond;
-    }
+    SDValue NewCond = LowerSETCC(Cond, DAG);
+    if (NewCond.getNode())
+      Cond = NewCond;
   }
 #if 0
   // FIXME: LowerXALUO doesn't handle these!!
@@ -8881,9 +8805,8 @@
 
   // If condition flag is set by a X86ISD::CMP, then use it as the condition
   // setting operand in place of the X86ISD::SETCC.
-  unsigned CondOpcode = Cond.getOpcode();
-  if (CondOpcode == X86ISD::SETCC ||
-      CondOpcode == X86ISD::SETCC_CARRY) {
+  if (Cond.getOpcode() == X86ISD::SETCC ||
+      Cond.getOpcode() == X86ISD::SETCC_CARRY) {
     CC = Cond.getOperand(0);
 
     SDValue Cmp = Cond.getOperand(1);
@@ -8904,43 +8827,6 @@
         break;
       }
     }
-  }
-  CondOpcode = Cond.getOpcode();
-  if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
-      CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
-      ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
-       Cond.getOperand(0).getValueType() != MVT::i8)) {
-    SDValue LHS = Cond.getOperand(0);
-    SDValue RHS = Cond.getOperand(1);
-    unsigned X86Opcode;
-    unsigned X86Cond;
-    SDVTList VTs;
-    switch (CondOpcode) {
-    case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
-    case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
-    case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
-    case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
-    case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
-    case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
-    default: llvm_unreachable("unexpected overflowing operator");
-    }
-    if (Inverted)
-      X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
-    if (CondOpcode == ISD::UMULO)
-      VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
-                          MVT::i32);
-    else
-      VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
-
-    SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
-
-    if (CondOpcode == ISD::UMULO)
-      Cond = X86Op.getValue(2);
-    else
-      Cond = X86Op.getValue(1);
-
-    CC = DAG.getConstant(X86Cond, MVT::i8);
-    addTest = false;
   } else {
     unsigned CondOpc;
     if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
@@ -9004,66 +8890,6 @@
       CC = DAG.getConstant(CCode, MVT::i8);
       Cond = Cond.getOperand(0).getOperand(1);
       addTest = false;
-    } else if (Cond.getOpcode() == ISD::SETCC &&
-               cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
-      // For FCMP_OEQ, we can emit
-      // two branches instead of an explicit AND instruction with a
-      // separate test. However, we only do this if this block doesn't
-      // have a fall-through edge, because this requires an explicit
-      // jmp when the condition is false.
-      if (Op.getNode()->hasOneUse()) {
-        SDNode *User = *Op.getNode()->use_begin();
-        // Look for an unconditional branch following this conditional branch.
-        // We need this because we need to reverse the successors in order
-        // to implement FCMP_OEQ.
-        if (User->getOpcode() == ISD::BR) {
-          SDValue FalseBB = User->getOperand(1);
-          SDNode *NewBR =
-            DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
-          assert(NewBR == User);
-          (void)NewBR;
-          Dest = FalseBB;
-
-          SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
-                                    Cond.getOperand(0), Cond.getOperand(1));
-          CC = DAG.getConstant(X86::COND_NE, MVT::i8);
-          Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
-                              Chain, Dest, CC, Cmp);
-          CC = DAG.getConstant(X86::COND_P, MVT::i8);
-          Cond = Cmp;
-          addTest = false;
-        }
-      }
-    } else if (Cond.getOpcode() == ISD::SETCC &&
-               cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
-      // For FCMP_UNE, we can emit
-      // two branches instead of an explicit AND instruction with a
-      // separate test. However, we only do this if this block doesn't
-      // have a fall-through edge, because this requires an explicit
-      // jmp when the condition is false.
-      if (Op.getNode()->hasOneUse()) {
-        SDNode *User = *Op.getNode()->use_begin();
-        // Look for an unconditional branch following this conditional branch.
-        // We need this because we need to reverse the successors in order
-        // to implement FCMP_UNE.
-        if (User->getOpcode() == ISD::BR) {
-          SDValue FalseBB = User->getOperand(1);
-          SDNode *NewBR =
-            DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
-          assert(NewBR == User);
-          (void)NewBR;
-
-          SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
-                                    Cond.getOperand(0), Cond.getOperand(1));
-          CC = DAG.getConstant(X86::COND_NE, MVT::i8);
-          Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
-                              Chain, Dest, CC, Cmp);
-          CC = DAG.getConstant(X86::COND_NP, MVT::i8);
-          Cond = Cmp;
-          addTest = false;
-          Dest = FalseBB;
-        }
-      }
     }
   }
 

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Fri Oct 28 19:41:52 2011
@@ -386,15 +386,6 @@
     Offset = off;
     return true;
   }
-  // Check for an aligned global variable.
-  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(*Root)) {
-    const GlobalValue *GV = GA->getGlobal();
-    if (GA->getOffset() == 0 && GV->getAlignment() >= 4) {
-      AlignedBase = Base;
-      Offset = off;
-      return true;
-    }
-  }
   return false;
 }
 

Modified: llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/and_ops.ll?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/and_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/and_ops.ll Fri Oct 28 19:41:52 2011
@@ -5,9 +5,6 @@
 ; RUN: grep andhi  %t1.s | count 30
 ; RUN: grep andbi  %t1.s | count 4
 
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll Fri Oct 28 19:41:52 2011
@@ -15,9 +15,6 @@
 ; RUN: grep ai      %t2.s | count 9
 ; RUN: grep dispatch_tab %t2.s | count 6
 
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 ; ModuleID = 'call_indirect.bc'
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
 target triple = "spu-unknown-elf"

Modified: llvm/trunk/test/CodeGen/CellSPU/nand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/nand.ll?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/nand.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/nand.ll Fri Oct 28 19:41:52 2011
@@ -3,10 +3,6 @@
 ; RUN: grep and    %t1.s | count 94
 ; RUN: grep xsbh   %t1.s | count 2
 ; RUN: grep xshw   %t1.s | count 4
-
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/or_ops.ll?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/or_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/or_ops.ll Fri Oct 28 19:41:52 2011
@@ -6,9 +6,6 @@
 ; RUN: grep orbi   %t1.s | count 15
 ; RUN: FileCheck %s < %t1.s
 
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/select_bits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/select_bits.ll?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/select_bits.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/select_bits.ll Fri Oct 28 19:41:52 2011
@@ -1,9 +1,6 @@
 ; RUN: llc < %s -march=cellspu > %t1.s
 ; RUN: grep selb   %t1.s | count 56
 
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/trunk/test/CodeGen/CellSPU/struct_1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/struct_1.ll?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/struct_1.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/struct_1.ll Fri Oct 28 19:41:52 2011
@@ -22,9 +22,6 @@
 ; RUN: grep shufb   %t2.s | count 7
 ; RUN: grep stqd    %t2.s | count 7
 
-; CellSPU legalization is over-sensitive to Legalize's traversal order.
-; XFAIL: *
-
 ; ModuleID = 'struct_1.bc'
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"

Modified: llvm/trunk/test/CodeGen/Mips/cprestore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cprestore.ll?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cprestore.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cprestore.ll Fri Oct 28 19:41:52 2011
@@ -1,4 +1,8 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; DISABLED: llc -march=mipsel < %s | FileCheck %s
+; RUN: false
+
+; byval is currently unsupported.
+; XFAIL: *
 
 ; CHECK: .set macro
 ; CHECK-NEXT: .cprestore

Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Fri Oct 28 19:41:52 2011
@@ -1,4 +1,8 @@
-; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+; DISABLED: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+; RUN: false
+
+; byval is currently unsupported.
+; XFAIL: *
 
 %struct.S1 = type { [65536 x i8] }
 

Modified: llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll Fri Oct 28 19:41:52 2011
@@ -1,7 +1,11 @@
-; RUN: llc -mtriple=thumbv6-apple-darwin < %s
+; DISABLED: llc -mtriple=thumbv6-apple-darwin < %s
+; RUN: false
 ; rdar://problem/9416774
 ; ModuleID = 'reduced.ll'
 
+; byval is currently unsupported.
+; XFAIL: *
+
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
 target triple = "thumbv7-apple-ios"
 

Removed: llvm/trunk/test/CodeGen/X86/legalize-libcalls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/legalize-libcalls.ll?rev=143261&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/legalize-libcalls.ll (original)
+++ llvm/trunk/test/CodeGen/X86/legalize-libcalls.ll (removed)
@@ -1,19 +0,0 @@
-; RUN: llc -march=x86 < %s
-
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
-target triple = "i386-apple-macosx10.7.0"
-
-define float @MakeSphere(float %theta.079) nounwind {
-entry:
-  %add36 = fadd float %theta.079, undef
-  %call = call float @cosf(float %theta.079) nounwind readnone
-  %call45 = call float @sinf(float %theta.079) nounwind readnone
-  %call37 = call float @sinf(float %add36) nounwind readnone
-  store float %call, float* undef, align 8
-  store float %call37, float* undef, align 8
-  store float %call45, float* undef, align 8
-  ret float %add36
-}
-
-declare float @cosf(float) nounwind readnone
-declare float @sinf(float) nounwind readnone

Modified: llvm/trunk/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=143262&r1=143261&r2=143262&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3.ll Fri Oct 28 19:41:52 2011
@@ -16,8 +16,10 @@
 	ret void
         
 ; X64: t0:
-; X64:	movdqa	(%rsi), %xmm0
-; X64:	pslldq	$2, %xmm0
+; X64: 	movddup	(%rsi), %xmm0
+; X64:  pshuflw	$0, %xmm0, %xmm0
+; X64:	xorl	%eax, %eax
+; X64:	pinsrw	$0, %eax, %xmm0
 ; X64:	movdqa	%xmm0, (%rdi)
 ; X64:	ret
 }
@@ -29,8 +31,9 @@
 	ret <8 x i16> %tmp3
         
 ; X64: t1:
+; X64: 	movl	(%rsi), %eax
 ; X64: 	movdqa	(%rdi), %xmm0
-; X64: 	pinsrw	$0, (%rsi), %xmm0
+; X64: 	pinsrw	$0, %eax, %xmm0
 ; X64: 	ret
 }
 
@@ -165,7 +168,7 @@
         ret void
 ; X64: 	t10:
 ; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %eax
-; X64: 		movlhps [[X1:%xmm[0-9]+]]
+; X64: 		unpcklpd [[X1:%xmm[0-9]+]]
 ; X64: 		pshuflw	$8, [[X1]], [[X2:%xmm[0-9]+]]
 ; X64: 		pinsrw	$2, %eax, [[X2]]
 ; X64: 		pextrw	$6, [[X0]], %eax
@@ -247,12 +250,13 @@
         %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0,  <16 x i32> < i32 0, i32 1, i32 2, i32 17,  i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
         ret <16 x i8> %tmp9
 ; X64: 	t16:
-; X64: 		movdqa	%xmm1, %xmm0
-; X64: 		pslldq	$2, %xmm0
-; X64: 		pextrw	$1, %xmm0, %eax
-; X64: 		movd	%xmm0, %ecx
-; X64: 		pinsrw	$0, %ecx, %xmm0
-; X64: 		pextrw	$8, %xmm1, %ecx
+; X64: 		pinsrw	$0, %eax, [[X1:%xmm[0-9]+]]
+; X64: 		pextrw	$8, [[X0:%xmm[0-9]+]], %eax
+; X64: 		pinsrw	$1, %eax, [[X1]]
+; X64: 		pextrw	$1, [[X1]], %ecx
+; X64: 		movd	[[X1]], %edx
+; X64: 		pinsrw	$0, %edx, %xmm
+; X64: 		pinsrw	$1, %eax, %xmm
 ; X64: 		ret
 }
 



From geek4civic at gmail.com  Fri Oct 28 19:45:27 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Sat, 29 Oct 2011 09:45:27 +0900
Subject: [llvm-commits] [llvm] r143214 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp
 test/Transforms/InstSimplify/compare.ll
In-Reply-To: <20111028190121.1A318312800A@llvm.org>
References: <20111028190121.1A318312800A@llvm.org>
Message-ID: <CADiQthNp_ps3q+yNzneG6AFoDNtQg2SWnMCbesSJa=jWeq1ZMg@mail.gmail.com>

2011/10/29 Duncan Sands <baldrick at free.fr>:
> Author: baldrick
> Date: Fri Oct 28 14:01:20 2011
> New Revision: 143214
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143214&view=rev
> Log:
> The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
> Spotted by my super-optimizer in 186.crafty and 450.soplex. ?We really
> need a proper infrastructure for handling generalizations of this kind
> of thing (which occur a lot), however this case is so simple that I decided
> to go ahead and implement it directly.
>
> Modified:
> ? ?llvm/trunk/lib/Analysis/InstructionSimplify.cpp
> ? ?llvm/trunk/test/Transforms/InstSimplify/compare.ll

It seems it broke clang stage2.

...Takumi


From eli.friedman at gmail.com  Fri Oct 28 19:56:08 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Sat, 29 Oct 2011 00:56:08 -0000
Subject: [llvm-commits] [llvm] r143265 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp
 test/Transforms/InstSimplify/compare.ll
Message-ID: <20111029005608.1AEFE312800A@llvm.org>

Author: efriedma
Date: Fri Oct 28 19:56:07 2011
New Revision: 143265

URL: http://llvm.org/viewvc/llvm-project?rev=143265&view=rev
Log:
Revert r143214; it's breaking a bunch of stuff.


Modified:
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp
    llvm/trunk/test/Transforms/InstSimplify/compare.ll

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=143265&r1=143264&r2=143265&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Fri Oct 28 19:56:07 2011
@@ -416,55 +416,39 @@
   }
   assert(isa<SelectInst>(LHS) && "Not comparing with a select instruction!");
   SelectInst *SI = cast<SelectInst>(LHS);
-  Value *Cond = SI->getCondition();
-  Value *TV = SI->getTrueValue();
-  Value *FV = SI->getFalseValue();
 
   // Now that we have "cmp select(Cond, TV, FV), RHS", analyse it.
   // Does "cmp TV, RHS" simplify?
-  Value *TCmp = SimplifyCmpInst(Pred, TV, RHS, TD, DT, MaxRecurse);
-  if (!TCmp) {
-    // It didn't simplify.  However if "cmp TV, RHS" is equal to the select
-    // condition itself then we can replace it with 'true'.
-    if (match(Cond, m_ICmp(Pred, m_Specific(TV), m_Specific(RHS))))
-      TCmp = getTrue(Cond->getType());
-  }
-  if (!TCmp)
-    return 0;
-
-  // Does "cmp FV, RHS" simplify?
-  Value *FCmp = SimplifyCmpInst(Pred, FV, RHS, TD, DT, MaxRecurse);
-  if (!FCmp) {
-    // It didn't simplify.  However if "cmp FV, RHS" is equal to the select
-    // condition itself then we can replace it with 'false'.
-    if (match(Cond, m_ICmp(Pred, m_Specific(FV), m_Specific(RHS))))
-      FCmp = getFalse(Cond->getType());
+  if (Value *TCmp = SimplifyCmpInst(Pred, SI->getTrueValue(), RHS, TD, DT,
+                                    MaxRecurse)) {
+    // It does!  Does "cmp FV, RHS" simplify?
+    if (Value *FCmp = SimplifyCmpInst(Pred, SI->getFalseValue(), RHS, TD, DT,
+                                      MaxRecurse)) {
+      // It does!  If they simplified to the same value, then use it as the
+      // result of the original comparison.
+      if (TCmp == FCmp)
+        return TCmp;
+      Value *Cond = SI->getCondition();
+      // If the false value simplified to false, then the result of the compare
+      // is equal to "Cond && TCmp".  This also catches the case when the false
+      // value simplified to false and the true value to true, returning "Cond".
+      if (match(FCmp, m_Zero()))
+        if (Value *V = SimplifyAndInst(Cond, TCmp, TD, DT, MaxRecurse))
+          return V;
+      // If the true value simplified to true, then the result of the compare
+      // is equal to "Cond || FCmp".
+      if (match(TCmp, m_One()))
+        if (Value *V = SimplifyOrInst(Cond, FCmp, TD, DT, MaxRecurse))
+          return V;
+      // Finally, if the false value simplified to true and the true value to
+      // false, then the result of the compare is equal to "!Cond".
+      if (match(FCmp, m_One()) && match(TCmp, m_Zero()))
+        if (Value *V =
+            SimplifyXorInst(Cond, Constant::getAllOnesValue(Cond->getType()),
+                            TD, DT, MaxRecurse))
+          return V;
+    }
   }
-  if (!FCmp)
-    return 0;
-
-  // If both sides simplified to the same value, then use it as the result of
-  // the original comparison.
-  if (TCmp == FCmp)
-    return TCmp;
-  // If the false value simplified to false, then the result of the compare
-  // is equal to "Cond && TCmp".  This also catches the case when the false
-  // value simplified to false and the true value to true, returning "Cond".
-  if (match(FCmp, m_Zero()))
-    if (Value *V = SimplifyAndInst(Cond, TCmp, TD, DT, MaxRecurse))
-      return V;
-  // If the true value simplified to true, then the result of the compare
-  // is equal to "Cond || FCmp".
-  if (match(TCmp, m_One()))
-    if (Value *V = SimplifyOrInst(Cond, FCmp, TD, DT, MaxRecurse))
-      return V;
-  // Finally, if the false value simplified to true and the true value to
-  // false, then the result of the compare is equal to "!Cond".
-  if (match(FCmp, m_One()) && match(TCmp, m_Zero()))
-    if (Value *V =
-        SimplifyXorInst(Cond, Constant::getAllOnesValue(Cond->getType()),
-                        TD, DT, MaxRecurse))
-      return V;
 
   return 0;
 }

Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=143265&r1=143264&r2=143265&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Fri Oct 28 19:56:07 2011
@@ -204,15 +204,6 @@
 ; CHECK: ret i1 %cond
 }
 
-define i1 @select5(i32 %x) {
-; CHECK: @select5
-  %c = icmp eq i32 %x, 0
-  %s = select i1 %c, i32 1, i32 %x
-  %c2 = icmp eq i32 %s, 0
-  ret i1 %c2
-; CHECK: ret i1 false
-}
-
 define i1 @urem1(i32 %X, i32 %Y) {
 ; CHECK: @urem1
   %A = urem i32 %X, %Y



From eli.friedman at gmail.com  Fri Oct 28 19:58:39 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Fri, 28 Oct 2011 17:58:39 -0700
Subject: [llvm-commits] [llvm] r143214 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp
 test/Transforms/InstSimplify/compare.ll
In-Reply-To: <CAJdarcGim2JVGaDMihFNePMY6m+rEWHNoeX+UtXh-kuejLudtg@mail.gmail.com>
References: <20111028190121.1A318312800A@llvm.org>
	<CAJdarcGim2JVGaDMihFNePMY6m+rEWHNoeX+UtXh-kuejLudtg@mail.gmail.com>
Message-ID: <CAJdarcGU539ZpKwxss0JQn2eYCvQak1XrW+71_jHmBk6oiWsqg@mail.gmail.com>

On Fri, Oct 28, 2011 at 4:56 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Fri, Oct 28, 2011 at 12:01 PM, Duncan Sands <baldrick at free.fr> wrote:
>> Author: baldrick
>> Date: Fri Oct 28 14:01:20 2011
>> New Revision: 143214
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=143214&view=rev
>> Log:
>> The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
>> Spotted by my super-optimizer in 186.crafty and 450.soplex. ?We really
>> need a proper infrastructure for handling generalizations of this kind
>> of thing (which occur a lot), however this case is so simple that I decided
>> to go ahead and implement it directly.
>
> This appears to be causing a miscompile on
> MultiSource/Benchmarks/mediabench/gsm/toast, among other things.

Reverted in r143265.

-Eli


From isanbard at gmail.com  Fri Oct 28 20:10:01 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Sat, 29 Oct 2011 01:10:01 -0000
Subject: [llvm-commits] [llvm] r143267 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111029011001.57A08312800A@llvm.org>

Author: void
Date: Fri Oct 28 20:10:01 2011
New Revision: 143267

URL: http://llvm.org/viewvc/llvm-project?rev=143267&view=rev
Log:
Add Cling to the External Projects list.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143267&r1=143266&r2=143267&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Fri Oct 28 20:10:01 2011
@@ -323,6 +323,20 @@
 </div>
 
 <!--=========================================================================-->
+<h3>Cling C++ Interpreter</h3>
+
+<div>
+
+<p><a href="http://cern.ch/cling">Cling</a> is an interactive compiler interface
+   (aka C++ interpreter). It uses LLVM's JIT and clang; it currently supports
+   C++ and C. It has a prompt interface, runs source files, calls into shared
+   libraries, prints the value of expressions, even does runtime lookup of
+   identifiers (dynamic scopes). And it just behaves like one would expect from
+   an interpreter.</p>
+
+</div>
+
+<!--=========================================================================-->
 <!-- FIXME: Comment out
 <h3>Crack Programming Language</h3>
 



From isanbard at gmail.com  Fri Oct 28 20:11:15 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Sat, 29 Oct 2011 01:11:15 -0000
Subject: [llvm-commits] [llvm] r143268 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111029011115.563EE312800A@llvm.org>

Author: void
Date: Fri Oct 28 20:11:15 2011
New Revision: 143268

URL: http://llvm.org/viewvc/llvm-project?rev=143268&view=rev
Log:
Revise ThreadSanitizer mention so that it lists the correct frontends.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143268&r1=143267&r2=143268&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Fri Oct 28 20:11:15 2011
@@ -558,9 +558,9 @@
 <p><a href="http://code.google.com/p/data-race-test/">ThreadSanitizer</a> is a
    data race detector for (mostly) C and C++ code, available for Linux, Mac OS
    and Windows. On different systems, we use binary instrumentation frameworks
-   (Valgrind, Pin and DynamoRio) as frontends that generate the program events
-   for the race detection algorithm. On Linux, there's an option of using
-   LLVM-based compile-time instrumentation.</p>
+   (Valgrind and Pin) as frontends that generate the program events for the race
+   detection algorithm. On Linux, there's an option of using LLVM-based
+   compile-time instrumentation.</p>
 
 </div>
 



From clattner at apple.com  Sat Oct 29 00:38:13 2011
From: clattner at apple.com (Chris Lattner)
Date: Fri, 28 Oct 2011 22:38:13 -0700
Subject: [llvm-commits] appendToGlobalCtors
In-Reply-To: <CAN=P9piDgWqCE7bmFU5WB-SRzk_Dstz+Gq9k4_O8pzGkkyUDTg@mail.gmail.com>
References: <CAN=P9piDgWqCE7bmFU5WB-SRzk_Dstz+Gq9k4_O8pzGkkyUDTg@mail.gmail.com>
Message-ID: <FAA20AF3-1942-42ED-A69E-A4D26E22FF00@apple.com>


On Oct 28, 2011, at 1:41 PM, Kostya Serebryany wrote:

> Hello, 
> 
> I would like to add a small utility function into llvm/Transforms/Utils.
> appendToGlobalCtors() adds a function to the list of global constructors. 
> Currently it is used by AddressSanitizer; clattner suggested to move it to llvm/Transforms/Utils.
> 
> Patch: http://codereview.appspot.com/5330046 (also in attachment).

Great!  Thanks for working on this,  a few couple minor requests:

+//===-- GlobalCtors.h - Functions to manipulate global ctors ----*- C++ -*-===//

Transforms/Utils is kind of a mess, but I think it would be better to put this in a "ModuleUtils.h" file, which would be more general.  The logic in GlobalOpt.cpp for manipulating llvm.global_ctors should be moved here eventually as well.


+    GVCtor->setName("removed");
+    GVCtor->eraseFromParent();

No need for the setName call before eraseFromParent.

Otherwise, looks great!

-Chris



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From kcc at google.com  Sat Oct 29 11:39:34 2011
From: kcc at google.com (Kostya Serebryany)
Date: Sat, 29 Oct 2011 09:39:34 -0700
Subject: [llvm-commits] appendToGlobalCtors
In-Reply-To: <FAA20AF3-1942-42ED-A69E-A4D26E22FF00@apple.com>
References: <CAN=P9piDgWqCE7bmFU5WB-SRzk_Dstz+Gq9k4_O8pzGkkyUDTg@mail.gmail.com>
	<FAA20AF3-1942-42ED-A69E-A4D26E22FF00@apple.com>
Message-ID: <CAN=P9pjTmh00zQgESmJjAuYpdw-Q=ejXRhQJkT1cY_nKnpAXeg@mail.gmail.com>

Done both, new patch attached.
http://codereview.appspot.com/5330046

--kcc

On Fri, Oct 28, 2011 at 10:38 PM, Chris Lattner <clattner at apple.com> wrote:

>
> On Oct 28, 2011, at 1:41 PM, Kostya Serebryany wrote:
>
> Hello,
>
> I would like to add a small utility function into llvm/Transforms/Utils.
> appendToGlobalCtors() adds a function to the list of global constructors.
> Currently it is used by AddressSanitizer; clattner suggested to move it
> to llvm/Transforms/Utils.
>
> Patch: http://codereview.appspot.com/5330046 (also in attachment).
>
>
> Great!  Thanks for working on this,  a few couple minor requests:
>
> +//===-- GlobalCtors.h - Functions to manipulate global ctors ----*- C++
> -*-===//
>
> Transforms/Utils is kind of a mess, but I think it would be better to put
> this in a "ModuleUtils.h" file, which would be more general.  The logic in
> GlobalOpt.cpp for manipulating llvm.global_ctors should be moved here
> eventually as well.
>
>
> +    GVCtor->setName("removed");
> +    GVCtor->eraseFromParent();
>
> No need for the setName call before eraseFromParent.
>
> Otherwise, looks great!
>
> -Chris
>
>
>
>
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From hfinkel at anl.gov  Sat Oct 29 12:30:12 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Sat, 29 Oct 2011 12:30:12 -0500
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
Message-ID: <1319909412.23036.851.camel@sapling>

Ralf, et al.,

Attached is the latest version of my autovectorization patch. llvmdev
has been CC'd (as had been suggested to me); this e-mail contains
additional benchmark results.

First, these are preliminary results because I did not do the things
necessary to make them real (explicitly quiet the machine, bind the
processes to one cpu, etc.). But they should be good enough for
discussion.

I'm using LLVM head r143101, with the attached patch applied, and clang
head r143100 on an x86_64 machine (some kind of Intel Xeon). For the gcc
comparison, I'm using build Ubuntu 4.4.3-4ubuntu5. gcc was run -O3
without any other optimization flags. opt was run -vectorize
-unroll-allow-partial -O3 with no other optimization flags (the patch
adds the -vectorize option). llc was just given -O3.

Below I've included results using the benchmark program by Maleki, et
al. See:
An Evaluation of Vectorizing Compilers - PACT'11
(http://polaris.cs.uiuc.edu/~garzaran/doc/pact11.pdf). The source of
their benchmark program was retrieved from:
http://polaris.cs.uiuc.edu/~maleki1/TSVC.tar.gz

Also, when using clang, I had to pass -Dinline= on the command line:
when using -emit-llvm, clang appears not to emit code for functions
declared inline. This is a bug, but I've not yet tracked it down. There
are two such small functions in the benchmark program, and the regular
inliner *should* catch them anyway.

Results:
0. Name of the loop
1. Time using LLVM with vectorization
2. Time using LLVM without vectorization
3. Time using gcc with vectorization
4. Time using gcc without vectorization

Loop       llvm-v   llvm     gcc-v    gcc
-------------------------------------------
S000        9.59     9.49     4.55    10.04
S111        7.67     7.37     7.68     7.83
S1111      13.98    14.48    16.14    16.30
S112       17.43    17.41    16.54    17.52
S1112      13.87    14.21    14.83    14.84
S113       22.97    22.88    22.05    22.05
S1113      11.46    11.42    11.03    11.01
S114       13.47    13.75    13.53    13.48
S115       33.06    33.24    49.98    49.99
S1115      13.91    14.18    13.65    13.66
S116       48.74    49.40    49.54    48.11
S118       11.04    11.26    10.79    10.50
S119        8.97     9.07    11.83    11.82
S1119       9.04     9.14     4.31    11.87
S121       18.06    18.78    14.84    17.31
S122        7.58     7.54     6.11     6.11
S123        7.02     7.38     7.42     7.41
S124        9.62     9.77     9.42     9.33
S125        7.14     7.22     4.67     7.81
S126        2.32     2.53     2.57     2.37
S127       12.87    12.97     7.06    14.50
S128       12.58    12.43    12.42    11.52
S131       29.91    29.91    25.17    28.94
S132       17.04    17.04    15.53    21.03
S141       12.59    12.26    12.38    12.05
S151       28.92    29.43    24.89    28.95
S152       15.68    16.03    11.19    15.63
S161        6.06     6.06     5.52     5.46
S1161      14.46    14.40     8.80     8.79
S162        8.31     9.05     5.36     8.18
S171       15.47     7.94     2.81     5.70
S172        5.92     5.89     2.75     5.70
S173       31.59    30.92    18.15    30.13
S174       31.16    31.66    18.51    30.16
S175        5.80     6.18     4.94     5.77
S176        5.69     5.83     4.41     7.65
S211       16.56    17.14    16.82    16.38
S212       13.46    14.28    13.34    13.18
S1213      13.12    13.46    12.80    12.43
S221       10.88    11.09     8.65     8.63
S1221       5.80     6.04     5.40     6.05
S222        6.01     6.26     5.70     5.72
S231       23.78    22.94    22.36    22.11
S232        6.88     6.88     6.89     6.89
S1232      16.00    15.34    15.05    15.10
S233       57.48    58.55    54.21    49.56
S2233      27.65    29.77    29.68    28.40
S235       46.40    44.92    46.94    43.93
S241       31.62    31.35    32.53    31.01
S242        7.20     7.20     7.20     7.20
S243       16.78    17.09    17.69    16.84
S244       14.64    14.83    16.91    16.82
S1244      14.98    14.83    14.77    14.40
S2244      10.47    10.62    10.40    10.06
S251       35.10    35.75    19.70    34.38
S1251      56.65    57.84    41.77    56.11
S2251      15.96    15.87    17.02    15.70
S3251      16.41    16.21    19.60    15.34
S252        7.24     6.32     7.72     7.26
S253       12.55    11.38    14.40    14.40
S254       19.08    18.70    28.23    28.06
S255        5.94     6.09     9.96     9.95
S256        3.14     3.42     3.10     3.09
S257        2.18     2.25     2.21     2.20
S258        1.80     1.82     1.84     1.84
S261       12.00    12.08    10.98    10.95
S271       32.93    33.04    33.25    33.01
S272       15.48    15.82    15.39    15.26
S273       13.99    14.04    16.86    16.80
S274       18.38    18.31    18.15    17.89
S275        3.02     3.02     3.36     2.98
S2275      33.71    33.50     8.97    33.60
S276       39.52    39.44    40.80    40.55
S277        4.81     4.80     4.81     4.80
S278       14.43    14.42    14.70    14.66
S279        8.10     8.29     7.25     7.27
S1279       9.77    10.06     9.34     9.25
S2710       7.85     8.04     7.86     7.56
S2711      35.54    35.55    36.56    36.00
S2712      33.16    33.17    34.24    33.47
S281       10.97    11.09    12.46    12.02
S1281      79.37    77.55    57.78    68.06
S291       11.94    11.78    14.03    14.03
S292        7.88     7.78     9.94     9.96
S293       15.90    15.87    19.32    19.33
S2101       2.59     2.58     2.59     2.60
S2102      17.63    17.53    16.68    16.75
S2111       5.63     5.60     5.85     5.85
S311       72.07    72.03    72.23    72.03
S31111      7.49     6.00     6.00     6.00
S312       96.06    96.04    96.05    96.03
S313       36.50    36.13    36.03    36.02
S314       36.10    36.07    74.67    72.42
S315        9.00     8.99     9.35     9.30
S316       36.11    36.06    72.08    74.87
S317      444.92   444.94   451.82   451.78
S318        9.04     9.07     7.30     7.30
S319       34.76    36.53    34.42    34.19
S3110       8.53     8.57     4.11     4.11
S13110      5.76     5.77    12.12    12.12
S3111       3.60     3.62     3.60     3.60
S3112       7.20     7.30     7.21     7.20
S3113      35.12    35.47    60.21    60.20
S321       16.81    16.81    16.80    16.80
S322       12.42    12.60    12.60    12.60
S323       10.93    11.02     8.48     8.51
S331        4.23     4.23     7.20     7.20
S332        7.21     7.21     5.21     5.31
S341        4.74     4.85     7.23     7.20
S342        6.02     6.09     7.25     7.20
S343        2.14     2.06     2.16     2.01
S351       49.26    47.34    21.82    46.46
S1351      50.85    50.35    33.68    49.06
S352       58.14    58.04    57.68    57.64
S353        8.35     8.38     8.34     8.19
S421       43.13    43.34    20.62    22.46
S1421      25.25    25.81    15.85    24.76
S422       88.36    87.53    79.22    78.99
S423      155.13   155.29   154.56   154.38
S424       37.11    37.51    11.42    22.36
S431       58.22    60.66    27.59    57.16
S441       14.05    13.29    12.88    12.81
S442        6.08     6.00     6.96     6.90
S443       17.60    17.77    17.15    16.95
S451       48.95    49.08    49.03    49.14
S452       42.98    39.32    14.64    96.03
S453       28.06    28.06    14.60    14.40
S471        8.53     8.65     8.39     8.43
S481       10.98    11.15    12.04    12.00
S482        9.31     9.31     9.19     9.17
S491       11.54    11.38    11.37    11.28
S4112       8.21     8.36     9.13     8.94
S4113       8.77     8.81     8.86     8.85
S4114      12.32    12.15    12.18    11.77
S4115       8.48     8.46     8.95     8.59
S4116       3.21     3.23     6.02     5.94
S4117      14.08     9.61    10.16     9.98
S4121       8.53     8.26     4.04     8.17
va         30.09    28.58    23.58    48.46
vag        12.35    12.36    13.58    13.20
vas        13.74    13.49    13.03    12.47
vif         4.49     4.57     5.06     4.92
vpv        58.59    57.22    28.28    57.24
vtv        59.15    57.83    28.40    57.63
vpvtv      33.18    32.84    16.35    32.73
vpvts       5.99     5.83     2.99     6.38
vpvpv      33.25    32.89    16.54    32.85
vtvtv      32.83    32.80    16.84    35.97
vsumr      72.03    72.03    72.20    72.04
vdotr      72.05    72.05    72.42    72.04
vbor      205.22   380.81    99.80   372.05

I've yet to go through these in detail (they just finished running 5
minutes ago). But for the curious (and I've had several requests for
benchmarks), here you go. There is obviously more work to do.

 -Hal

On Fri, 2011-10-28 at 14:30 +0200, Ralf Karrenberg wrote:
> Hi Hal,
> 
> those numbers look very promising, great work! :)
> 
> Best,
> Ralf
> 
> ----- Original Message -----
> > From: "Hal Finkel" <hfinkel at anl.gov>
> > To: "Bruno Cardoso Lopes" <bruno.cardoso at gmail.com>
> > Cc: llvm-commits at cs.uiuc.edu
> > Sent: Freitag, 28. Oktober 2011 13:50:00
> > Subject: Re: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
> > 
> > Bruno, et al.,
> > 
> > I've attached a new version of the patch that contains improvements
> > (and
> > a critical bug fix [the code output is not more right, but the pass
> > in
> > the older patch would crash in certain cases and now does not])
> > compared
> > to previous versions that I've posted.
> > 
> > First, these are preliminary results because I did not do the things
> > necessary to make them real (explicitly quiet the machine, bind the
> > processes to one cpu, etc.). But they should be good enough for
> > discussion.
> > 
> > I'm using LLVM head r143101, with the attached patch applied, and
> > clang
> > head r143100 on an x86_64 machine (some kind of Intel Xeon). For the
> > gcc
> > comparison, I'm using build Ubuntu 4.4.3-4ubuntu5. gcc was run -O3
> > without any other optimization flags. opt was run -vectorize
> > -unroll-allow-partial -O3 with no other optimization flags (the patch
> > adds the -vectorize option). llc was just given -O3.
> > 
> > It is not difficult to construct an example in which vectorization
> > would
> > be useful: take a loop that does more computation than load/stores,
> > and
> > (partially) unroll it. Here is a simple case:
> > 
> > #define ITER 5000
> > #define NUM 200
> > double a[NUM][NUM];
> > double b[NUM][NUM];
> > 
> > ...
> > 
> > int main()
> > {
> > ...
> > 
> >   for (int i = 0; i < ITER; ++i) {
> >     for (int x = 0; x < NUM; ++x)
> >     for (int y = 0; y < NUM; ++y) {
> >       double v = a[x][y], w = b[x][y];
> >       double z1 = v*w;
> >       double z2 = v+w;
> >       double z3 = z1*z2;
> >       double z4 = z3+v;
> >       double z5 = z2+w;
> >       double z6 = z4*z5;
> >       double z7 = z4+z5;
> >       a[x][y] = v*v-z6;
> >       b[x][y] = w-z7;
> >     }
> >   }
> > 
> >  ...
> > 
> >   return 0;
> > }
> > 
> > Results:
> > gcc -03: 0m1.790s
> > llvm -vectorize: 0m2.360s
> > llvm: 0m2.780s
> > gcc -fno-tree-vectorize: 0m2.810s
> > (these are the user times after I've run enough for the times to
> > settle
> > to three decimal places)
> > 
> > So the vectorization gives a ~15% improvement in the running time.
> > gcc's
> > vectorization still does a much better job, however (yielding an ~36%
> > improvement). So there is still work to do ;)
> > 
> > Additionally, I've checked the autovectorization on some classic
> > numerical benchmarks from netlib. On these benchmarks, clang/llvm
> > already do a good job compared to gcc (gcc is only about 10% better,
> > and
> > this is true regardless of whether gcc's vectorization is on or off).
> > For these cases, autovectorization provides an insignificant speedup
> > in
> > most cases (but does not tend to make things worse, just not really
> > any
> > better either). Because gcc's vectorization also did not really help
> > gcc
> > in these cases, I'm not surprised. A good collection of these is
> > available here:
> > http://www.roylongbottom.org.uk/classic_benchmarks.tar.gz
> > 
> > I've yet to run the test suite using the pass to validate it. That is
> > something that I plan to do. Actually, the "Livermore Loops" test in
> > the
> > aforementioned archive contains checksums to validate the results,
> > and
> > it looks like 1 or 2 of the loop results are wrong with vectorization
> > turned on, so I'll have to investigate that.
> > 
> >  -Hal
> > 
> > On Wed, 2011-10-26 at 18:49 -0200, Bruno Cardoso Lopes wrote:
> > > Hi Hal,
> > > 
> > > On Fri, Oct 21, 2011 at 7:04 PM, Hal Finkel <hfinkel at anl.gov>
> > > wrote:
> > > > I've attached an initial version of a basic-block
> > > > autovectorization
> > > > pass. It works by searching a basic block for pairable
> > > > (independent)
> > > > instructions, and, using a chain-seeking heuristic, selects
> > > > pairings
> > > > likely to provide an overall speedup (if such pairings can be
> > > > found).
> > > > The selected pairs are then fused and, if necessary, other
> > > > instructions
> > > > are moved in order to maintain data-flow consistency. This works
> > > > only
> > > > within one basic block, but can do loop vectorization in
> > > > combination
> > > > with (partial) unrolling. The basic idea was inspired by the
> > > > Vienna MAP
> > > > Vectorizor, which has been used to vectorize FFT kernels, but the
> > > > algorithm used here is different.
> > > >
> > > > To try it, use -bb-vectorize with opt. There are a few options:
> > > > -bb-vectorize-req-chain-depth: default: 3 -- The depth of the
> > > > chain of
> > > > instruction pairs necessary in order to consider the pairs that
> > > > compose
> > > > the chain worthy of vectorization.
> > > > -bb-vectorize-vector-bits: default: 128 -- The size of the target
> > > > vector
> > > > registers
> > > > -bb-vectorize-no-ints -- Don't consider integer instructions
> > > > -bb-vectorize-no-floats -- Don't consider floating-point
> > > > instructions
> > > >
> > > > The vectorizor generates a lot of insert_element/extract_element
> > > > pairs;
> > > > The assumption is that other passes will turn these into shuffles
> > > > when
> > > > possible (it looks like some work is necessary here). It will
> > > > also
> > > > vectorize vector instructions, and generates shuffles in this
> > > > case
> > > > (again, other passes should combine these as appropriate).
> > > >
> > > > Currently, it does not fuse load or store instructions, but that
> > > > is a
> > > > feature that I'd like to add. Of course, alignment information is
> > > > an
> > > > issue for load/store vectorization (or maybe I should just fuse
> > > > them
> > > > anyway and let isel deal with unaligned cases?).
> > > >
> > > > Also, support needs to be added for fusing known intrinsics (fma,
> > > > etc.),
> > > > and, as has been discussed on llvmdev, we should add some
> > > > intrinsics to
> > > > allow the generation of addsub-type instructions.
> > > >
> > > > I've included a few tests, but it needs more. Please review (I'll
> > > > commit
> > > > if and when everyone is happy).
> > > >
> > > > Thanks in advance,
> > > > Hal
> > > >
> > > > P.S. There is another option (not so useful right now, but could
> > > > be):
> > > > -bb-vectorize-fast-dep -- Don't do a full inter-instruction
> > > > dependency
> > > > analysis; instead stop looking for instruction pairs after the
> > > > first use
> > > > of an instruction's value. [This makes the pass faster, but would
> > > > require a data-dependence-based reordering pass in order to be
> > > > effective].
> > > 
> > > Cool! :)
> > > Have you run this pass with any benchmark or the llvm testsuite?
> > > Does
> > > it presents any regression?
> > > Do you have any performance results?
> > > Cheers,
> > > 
> > 
> > --
> > Hal Finkel
> > Postdoctoral Appointee
> > Leadership Computing Facility
> > Argonne National Laboratory
> > 
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> > 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory
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From tonic at nondot.org  Sat Oct 29 13:57:52 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Sat, 29 Oct 2011 18:57:52 -0000
Subject: [llvm-commits] [www] r143283 - /www/trunk/index.html
Message-ID: <20111029185752.7C9F43524076@llvm.org>

Author: tbrethou
Date: Sat Oct 29 13:57:52 2011
New Revision: 143283

URL: http://llvm.org/viewvc/llvm-project?rev=143283&view=rev
Log:
Test.

Modified:
    www/trunk/index.html

Modified: www/trunk/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=143283&r1=143282&r2=143283&view=diff
==============================================================================
--- www/trunk/index.html (original)
+++ www/trunk/index.html Sat Oct 29 13:57:52 2011
@@ -1,6 +1,5 @@
 <!--#include virtual="header.incl" -->
 
-
 <table border="0" cellpadding="0" cellspacing="0" width="95%">
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 <tr>



From hfinkel at anl.gov  Sat Oct 29 14:02:03 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Sat, 29 Oct 2011 14:02:03 -0500
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <1319909412.23036.851.camel@sapling>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
Message-ID: <1319914924.23036.852.camel@sapling>

On Sat, 2011-10-29 at 12:30 -0500, Hal Finkel wrote:
> Ralf, et al.,
> 
> Attached is the latest version of my autovectorization patch. llvmdev
> has been CC'd (as had been suggested to me); this e-mail contains
> additional benchmark results.
> 
> First, these are preliminary results because I did not do the things
> necessary to make them real (explicitly quiet the machine, bind the
> processes to one cpu, etc.). But they should be good enough for
> discussion.
> 
> I'm using LLVM head r143101, with the attached patch applied, and clang
> head r143100 on an x86_64 machine (some kind of Intel Xeon). For the gcc
> comparison, I'm using build Ubuntu 4.4.3-4ubuntu5. gcc was run -O3
> without any other optimization flags. opt was run -vectorize
> -unroll-allow-partial -O3 with no other optimization flags (the patch
> adds the -vectorize option).

And opt had also been given the flag: -bb-vectorize-vector-bits=256

 -Hal

> llc was just given -O3.
> 
> Below I've included results using the benchmark program by Maleki, et
> al. See:
> An Evaluation of Vectorizing Compilers - PACT'11
> (http://polaris.cs.uiuc.edu/~garzaran/doc/pact11.pdf). The source of
> their benchmark program was retrieved from:
> http://polaris.cs.uiuc.edu/~maleki1/TSVC.tar.gz
> 
> Also, when using clang, I had to pass -Dinline= on the command line:
> when using -emit-llvm, clang appears not to emit code for functions
> declared inline. This is a bug, but I've not yet tracked it down. There
> are two such small functions in the benchmark program, and the regular
> inliner *should* catch them anyway.
> 
> Results:
> 0. Name of the loop
> 1. Time using LLVM with vectorization
> 2. Time using LLVM without vectorization
> 3. Time using gcc with vectorization
> 4. Time using gcc without vectorization
> 
> Loop       llvm-v   llvm     gcc-v    gcc
> -------------------------------------------
> S000        9.59     9.49     4.55    10.04
> S111        7.67     7.37     7.68     7.83
> S1111      13.98    14.48    16.14    16.30
> S112       17.43    17.41    16.54    17.52
> S1112      13.87    14.21    14.83    14.84
> S113       22.97    22.88    22.05    22.05
> S1113      11.46    11.42    11.03    11.01
> S114       13.47    13.75    13.53    13.48
> S115       33.06    33.24    49.98    49.99
> S1115      13.91    14.18    13.65    13.66
> S116       48.74    49.40    49.54    48.11
> S118       11.04    11.26    10.79    10.50
> S119        8.97     9.07    11.83    11.82
> S1119       9.04     9.14     4.31    11.87
> S121       18.06    18.78    14.84    17.31
> S122        7.58     7.54     6.11     6.11
> S123        7.02     7.38     7.42     7.41
> S124        9.62     9.77     9.42     9.33
> S125        7.14     7.22     4.67     7.81
> S126        2.32     2.53     2.57     2.37
> S127       12.87    12.97     7.06    14.50
> S128       12.58    12.43    12.42    11.52
> S131       29.91    29.91    25.17    28.94
> S132       17.04    17.04    15.53    21.03
> S141       12.59    12.26    12.38    12.05
> S151       28.92    29.43    24.89    28.95
> S152       15.68    16.03    11.19    15.63
> S161        6.06     6.06     5.52     5.46
> S1161      14.46    14.40     8.80     8.79
> S162        8.31     9.05     5.36     8.18
> S171       15.47     7.94     2.81     5.70
> S172        5.92     5.89     2.75     5.70
> S173       31.59    30.92    18.15    30.13
> S174       31.16    31.66    18.51    30.16
> S175        5.80     6.18     4.94     5.77
> S176        5.69     5.83     4.41     7.65
> S211       16.56    17.14    16.82    16.38
> S212       13.46    14.28    13.34    13.18
> S1213      13.12    13.46    12.80    12.43
> S221       10.88    11.09     8.65     8.63
> S1221       5.80     6.04     5.40     6.05
> S222        6.01     6.26     5.70     5.72
> S231       23.78    22.94    22.36    22.11
> S232        6.88     6.88     6.89     6.89
> S1232      16.00    15.34    15.05    15.10
> S233       57.48    58.55    54.21    49.56
> S2233      27.65    29.77    29.68    28.40
> S235       46.40    44.92    46.94    43.93
> S241       31.62    31.35    32.53    31.01
> S242        7.20     7.20     7.20     7.20
> S243       16.78    17.09    17.69    16.84
> S244       14.64    14.83    16.91    16.82
> S1244      14.98    14.83    14.77    14.40
> S2244      10.47    10.62    10.40    10.06
> S251       35.10    35.75    19.70    34.38
> S1251      56.65    57.84    41.77    56.11
> S2251      15.96    15.87    17.02    15.70
> S3251      16.41    16.21    19.60    15.34
> S252        7.24     6.32     7.72     7.26
> S253       12.55    11.38    14.40    14.40
> S254       19.08    18.70    28.23    28.06
> S255        5.94     6.09     9.96     9.95
> S256        3.14     3.42     3.10     3.09
> S257        2.18     2.25     2.21     2.20
> S258        1.80     1.82     1.84     1.84
> S261       12.00    12.08    10.98    10.95
> S271       32.93    33.04    33.25    33.01
> S272       15.48    15.82    15.39    15.26
> S273       13.99    14.04    16.86    16.80
> S274       18.38    18.31    18.15    17.89
> S275        3.02     3.02     3.36     2.98
> S2275      33.71    33.50     8.97    33.60
> S276       39.52    39.44    40.80    40.55
> S277        4.81     4.80     4.81     4.80
> S278       14.43    14.42    14.70    14.66
> S279        8.10     8.29     7.25     7.27
> S1279       9.77    10.06     9.34     9.25
> S2710       7.85     8.04     7.86     7.56
> S2711      35.54    35.55    36.56    36.00
> S2712      33.16    33.17    34.24    33.47
> S281       10.97    11.09    12.46    12.02
> S1281      79.37    77.55    57.78    68.06
> S291       11.94    11.78    14.03    14.03
> S292        7.88     7.78     9.94     9.96
> S293       15.90    15.87    19.32    19.33
> S2101       2.59     2.58     2.59     2.60
> S2102      17.63    17.53    16.68    16.75
> S2111       5.63     5.60     5.85     5.85
> S311       72.07    72.03    72.23    72.03
> S31111      7.49     6.00     6.00     6.00
> S312       96.06    96.04    96.05    96.03
> S313       36.50    36.13    36.03    36.02
> S314       36.10    36.07    74.67    72.42
> S315        9.00     8.99     9.35     9.30
> S316       36.11    36.06    72.08    74.87
> S317      444.92   444.94   451.82   451.78
> S318        9.04     9.07     7.30     7.30
> S319       34.76    36.53    34.42    34.19
> S3110       8.53     8.57     4.11     4.11
> S13110      5.76     5.77    12.12    12.12
> S3111       3.60     3.62     3.60     3.60
> S3112       7.20     7.30     7.21     7.20
> S3113      35.12    35.47    60.21    60.20
> S321       16.81    16.81    16.80    16.80
> S322       12.42    12.60    12.60    12.60
> S323       10.93    11.02     8.48     8.51
> S331        4.23     4.23     7.20     7.20
> S332        7.21     7.21     5.21     5.31
> S341        4.74     4.85     7.23     7.20
> S342        6.02     6.09     7.25     7.20
> S343        2.14     2.06     2.16     2.01
> S351       49.26    47.34    21.82    46.46
> S1351      50.85    50.35    33.68    49.06
> S352       58.14    58.04    57.68    57.64
> S353        8.35     8.38     8.34     8.19
> S421       43.13    43.34    20.62    22.46
> S1421      25.25    25.81    15.85    24.76
> S422       88.36    87.53    79.22    78.99
> S423      155.13   155.29   154.56   154.38
> S424       37.11    37.51    11.42    22.36
> S431       58.22    60.66    27.59    57.16
> S441       14.05    13.29    12.88    12.81
> S442        6.08     6.00     6.96     6.90
> S443       17.60    17.77    17.15    16.95
> S451       48.95    49.08    49.03    49.14
> S452       42.98    39.32    14.64    96.03
> S453       28.06    28.06    14.60    14.40
> S471        8.53     8.65     8.39     8.43
> S481       10.98    11.15    12.04    12.00
> S482        9.31     9.31     9.19     9.17
> S491       11.54    11.38    11.37    11.28
> S4112       8.21     8.36     9.13     8.94
> S4113       8.77     8.81     8.86     8.85
> S4114      12.32    12.15    12.18    11.77
> S4115       8.48     8.46     8.95     8.59
> S4116       3.21     3.23     6.02     5.94
> S4117      14.08     9.61    10.16     9.98
> S4121       8.53     8.26     4.04     8.17
> va         30.09    28.58    23.58    48.46
> vag        12.35    12.36    13.58    13.20
> vas        13.74    13.49    13.03    12.47
> vif         4.49     4.57     5.06     4.92
> vpv        58.59    57.22    28.28    57.24
> vtv        59.15    57.83    28.40    57.63
> vpvtv      33.18    32.84    16.35    32.73
> vpvts       5.99     5.83     2.99     6.38
> vpvpv      33.25    32.89    16.54    32.85
> vtvtv      32.83    32.80    16.84    35.97
> vsumr      72.03    72.03    72.20    72.04
> vdotr      72.05    72.05    72.42    72.04
> vbor      205.22   380.81    99.80   372.05
> 
> I've yet to go through these in detail (they just finished running 5
> minutes ago). But for the curious (and I've had several requests for
> benchmarks), here you go. There is obviously more work to do.
> 
>  -Hal
> 
> On Fri, 2011-10-28 at 14:30 +0200, Ralf Karrenberg wrote:
> > Hi Hal,
> > 
> > those numbers look very promising, great work! :)
> > 
> > Best,
> > Ralf
> > 
> > ----- Original Message -----
> > > From: "Hal Finkel" <hfinkel at anl.gov>
> > > To: "Bruno Cardoso Lopes" <bruno.cardoso at gmail.com>
> > > Cc: llvm-commits at cs.uiuc.edu
> > > Sent: Freitag, 28. Oktober 2011 13:50:00
> > > Subject: Re: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
> > > 
> > > Bruno, et al.,
> > > 
> > > I've attached a new version of the patch that contains improvements
> > > (and
> > > a critical bug fix [the code output is not more right, but the pass
> > > in
> > > the older patch would crash in certain cases and now does not])
> > > compared
> > > to previous versions that I've posted.
> > > 
> > > First, these are preliminary results because I did not do the things
> > > necessary to make them real (explicitly quiet the machine, bind the
> > > processes to one cpu, etc.). But they should be good enough for
> > > discussion.
> > > 
> > > I'm using LLVM head r143101, with the attached patch applied, and
> > > clang
> > > head r143100 on an x86_64 machine (some kind of Intel Xeon). For the
> > > gcc
> > > comparison, I'm using build Ubuntu 4.4.3-4ubuntu5. gcc was run -O3
> > > without any other optimization flags. opt was run -vectorize
> > > -unroll-allow-partial -O3 with no other optimization flags (the patch
> > > adds the -vectorize option). llc was just given -O3.
> > > 
> > > It is not difficult to construct an example in which vectorization
> > > would
> > > be useful: take a loop that does more computation than load/stores,
> > > and
> > > (partially) unroll it. Here is a simple case:
> > > 
> > > #define ITER 5000
> > > #define NUM 200
> > > double a[NUM][NUM];
> > > double b[NUM][NUM];
> > > 
> > > ...
> > > 
> > > int main()
> > > {
> > > ...
> > > 
> > >   for (int i = 0; i < ITER; ++i) {
> > >     for (int x = 0; x < NUM; ++x)
> > >     for (int y = 0; y < NUM; ++y) {
> > >       double v = a[x][y], w = b[x][y];
> > >       double z1 = v*w;
> > >       double z2 = v+w;
> > >       double z3 = z1*z2;
> > >       double z4 = z3+v;
> > >       double z5 = z2+w;
> > >       double z6 = z4*z5;
> > >       double z7 = z4+z5;
> > >       a[x][y] = v*v-z6;
> > >       b[x][y] = w-z7;
> > >     }
> > >   }
> > > 
> > >  ...
> > > 
> > >   return 0;
> > > }
> > > 
> > > Results:
> > > gcc -03: 0m1.790s
> > > llvm -vectorize: 0m2.360s
> > > llvm: 0m2.780s
> > > gcc -fno-tree-vectorize: 0m2.810s
> > > (these are the user times after I've run enough for the times to
> > > settle
> > > to three decimal places)
> > > 
> > > So the vectorization gives a ~15% improvement in the running time.
> > > gcc's
> > > vectorization still does a much better job, however (yielding an ~36%
> > > improvement). So there is still work to do ;)
> > > 
> > > Additionally, I've checked the autovectorization on some classic
> > > numerical benchmarks from netlib. On these benchmarks, clang/llvm
> > > already do a good job compared to gcc (gcc is only about 10% better,
> > > and
> > > this is true regardless of whether gcc's vectorization is on or off).
> > > For these cases, autovectorization provides an insignificant speedup
> > > in
> > > most cases (but does not tend to make things worse, just not really
> > > any
> > > better either). Because gcc's vectorization also did not really help
> > > gcc
> > > in these cases, I'm not surprised. A good collection of these is
> > > available here:
> > > http://www.roylongbottom.org.uk/classic_benchmarks.tar.gz
> > > 
> > > I've yet to run the test suite using the pass to validate it. That is
> > > something that I plan to do. Actually, the "Livermore Loops" test in
> > > the
> > > aforementioned archive contains checksums to validate the results,
> > > and
> > > it looks like 1 or 2 of the loop results are wrong with vectorization
> > > turned on, so I'll have to investigate that.
> > > 
> > >  -Hal
> > > 
> > > On Wed, 2011-10-26 at 18:49 -0200, Bruno Cardoso Lopes wrote:
> > > > Hi Hal,
> > > > 
> > > > On Fri, Oct 21, 2011 at 7:04 PM, Hal Finkel <hfinkel at anl.gov>
> > > > wrote:
> > > > > I've attached an initial version of a basic-block
> > > > > autovectorization
> > > > > pass. It works by searching a basic block for pairable
> > > > > (independent)
> > > > > instructions, and, using a chain-seeking heuristic, selects
> > > > > pairings
> > > > > likely to provide an overall speedup (if such pairings can be
> > > > > found).
> > > > > The selected pairs are then fused and, if necessary, other
> > > > > instructions
> > > > > are moved in order to maintain data-flow consistency. This works
> > > > > only
> > > > > within one basic block, but can do loop vectorization in
> > > > > combination
> > > > > with (partial) unrolling. The basic idea was inspired by the
> > > > > Vienna MAP
> > > > > Vectorizor, which has been used to vectorize FFT kernels, but the
> > > > > algorithm used here is different.
> > > > >
> > > > > To try it, use -bb-vectorize with opt. There are a few options:
> > > > > -bb-vectorize-req-chain-depth: default: 3 -- The depth of the
> > > > > chain of
> > > > > instruction pairs necessary in order to consider the pairs that
> > > > > compose
> > > > > the chain worthy of vectorization.
> > > > > -bb-vectorize-vector-bits: default: 128 -- The size of the target
> > > > > vector
> > > > > registers
> > > > > -bb-vectorize-no-ints -- Don't consider integer instructions
> > > > > -bb-vectorize-no-floats -- Don't consider floating-point
> > > > > instructions
> > > > >
> > > > > The vectorizor generates a lot of insert_element/extract_element
> > > > > pairs;
> > > > > The assumption is that other passes will turn these into shuffles
> > > > > when
> > > > > possible (it looks like some work is necessary here). It will
> > > > > also
> > > > > vectorize vector instructions, and generates shuffles in this
> > > > > case
> > > > > (again, other passes should combine these as appropriate).
> > > > >
> > > > > Currently, it does not fuse load or store instructions, but that
> > > > > is a
> > > > > feature that I'd like to add. Of course, alignment information is
> > > > > an
> > > > > issue for load/store vectorization (or maybe I should just fuse
> > > > > them
> > > > > anyway and let isel deal with unaligned cases?).
> > > > >
> > > > > Also, support needs to be added for fusing known intrinsics (fma,
> > > > > etc.),
> > > > > and, as has been discussed on llvmdev, we should add some
> > > > > intrinsics to
> > > > > allow the generation of addsub-type instructions.
> > > > >
> > > > > I've included a few tests, but it needs more. Please review (I'll
> > > > > commit
> > > > > if and when everyone is happy).
> > > > >
> > > > > Thanks in advance,
> > > > > Hal
> > > > >
> > > > > P.S. There is another option (not so useful right now, but could
> > > > > be):
> > > > > -bb-vectorize-fast-dep -- Don't do a full inter-instruction
> > > > > dependency
> > > > > analysis; instead stop looking for instruction pairs after the
> > > > > first use
> > > > > of an instruction's value. [This makes the pass faster, but would
> > > > > require a data-dependence-based reordering pass in order to be
> > > > > effective].
> > > > 
> > > > Cool! :)
> > > > Have you run this pass with any benchmark or the llvm testsuite?
> > > > Does
> > > > it presents any regression?
> > > > Do you have any performance results?
> > > > Cheers,
> > > > 
> > > 
> > > --
> > > Hal Finkel
> > > Postdoctoral Appointee
> > > Leadership Computing Facility
> > > Argonne National Laboratory
> > > 
> > > _______________________________________________
> > > llvm-commits mailing list
> > > llvm-commits at cs.uiuc.edu
> > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> > > 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory
1-630-252-0023
hfinkel at anl.gov


From tonic at nondot.org  Sat Oct 29 14:00:22 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Sat, 29 Oct 2011 19:00:22 -0000
Subject: [llvm-commits] [www] r143284 - /www/trunk/index.html
Message-ID: <20111029190022.1A44E3524076@llvm.org>

Author: tbrethou
Date: Sat Oct 29 14:00:21 2011
New Revision: 143284

URL: http://llvm.org/viewvc/llvm-project?rev=143284&view=rev
Log:
Testing svnmailer.

Modified:
    www/trunk/index.html

Modified: www/trunk/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=143284&r1=143283&r2=143284&view=diff
==============================================================================
--- www/trunk/index.html (original)
+++ www/trunk/index.html Sat Oct 29 14:00:21 2011
@@ -1,5 +1,6 @@
 <!--#include virtual="header.incl" -->
 
+
 <table border="0" cellpadding="0" cellspacing="0" width="95%">
 <!-- Start of the left bar... -->
 <tr>



From tonic at nondot.org  Sat Oct 29 14:04:18 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Sat, 29 Oct 2011 19:04:18 -0000
Subject: [llvm-commits] [www] r143285 - /www/trunk/index.html
Message-ID: <20111029190418.287763524076@llvm.org>

Author: tbrethou
Date: Sat Oct 29 14:04:17 2011
New Revision: 143285

URL: http://llvm.org/viewvc/llvm-project?rev=143285&view=rev
Log:
Testing auto website update.

Modified:
    www/trunk/index.html

Modified: www/trunk/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=143285&r1=143284&r2=143285&view=diff
==============================================================================
--- www/trunk/index.html (original)
+++ www/trunk/index.html Sat Oct 29 14:04:17 2011
@@ -1,6 +1,5 @@
 <!--#include virtual="header.incl" -->
 
-
 <table border="0" cellpadding="0" cellspacing="0" width="95%">
 <!-- Start of the left bar... -->
 <tr>



From tonic at nondot.org  Sat Oct 29 14:09:15 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Sat, 29 Oct 2011 19:09:15 -0000
Subject: [llvm-commits] [www] r143286 - /www/trunk/devmtg/index.html
Message-ID: <20111029190915.6D44E3524076@llvm.org>

Author: tbrethou
Date: Sat Oct 29 14:09:15 2011
New Revision: 143286

URL: http://llvm.org/viewvc/llvm-project?rev=143286&view=rev
Log:
Testing website auto-update.

Modified:
    www/trunk/devmtg/index.html

Modified: www/trunk/devmtg/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/index.html?rev=143286&r1=143285&r2=143286&view=diff
==============================================================================
--- www/trunk/devmtg/index.html (original)
+++ www/trunk/devmtg/index.html Sat Oct 29 14:09:15 2011
@@ -1,5 +1,6 @@
 <!--#include virtual="../header.incl" -->
 
+
 <div class="www_sectiontitle">LLVM Developers' Meeting</div>
 
 <p>The upcoming developer's meeting is on <a href="http://www.llvm.org/devmtg/2011-11/">November 18, 2011.</a></p>



From tonic at nondot.org  Sat Oct 29 14:23:29 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Sat, 29 Oct 2011 19:23:29 -0000
Subject: [llvm-commits] [www] r143287 - /www/trunk/index.html
Message-ID: <20111029192329.967B83524076@llvm.org>

Author: tbrethou
Date: Sat Oct 29 14:23:29 2011
New Revision: 143287

URL: http://llvm.org/viewvc/llvm-project?rev=143287&view=rev
Log:
Another test.

Modified:
    www/trunk/index.html

Modified: www/trunk/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=143287&r1=143286&r2=143287&view=diff
==============================================================================
--- www/trunk/index.html (original)
+++ www/trunk/index.html Sat Oct 29 14:23:29 2011
@@ -1,5 +1,6 @@
 <!--#include virtual="header.incl" -->
 
+
 <table border="0" cellpadding="0" cellspacing="0" width="95%">
 <!-- Start of the left bar... -->
 <tr>



From benny.kra at googlemail.com  Sat Oct 29 14:43:31 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Sat, 29 Oct 2011 19:43:31 -0000
Subject: [llvm-commits] [llvm] r143289 - in /llvm/trunk:
 lib/Transforms/Scalar/SimplifyLibCalls.cpp
 test/Transforms/SimplifyLibCalls/Printf.ll
Message-ID: <20111029194331.D816B3524076@llvm.org>

Author: d0k
Date: Sat Oct 29 14:43:31 2011
New Revision: 143289

URL: http://llvm.org/viewvc/llvm-project?rev=143289&view=rev
Log:
SimplifyLibCalls: Use IRBuilder.CreateGlobalString when creating a string for printf->puts, which correctly sets the unnamed_addr bit on the resulting GlobalVariable.

Fixes PR11264.

Modified:
    llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
    llvm/trunk/test/Transforms/SimplifyLibCalls/Printf.ll

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=143289&r1=143288&r2=143289&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Sat Oct 29 14:43:31 2011
@@ -1123,10 +1123,8 @@
       // Create a string literal with no \n on it.  We expect the constant merge
       // pass to be run after this pass, to merge duplicate strings.
       FormatStr.erase(FormatStr.end()-1);
-      Constant *C = ConstantArray::get(*Context, FormatStr, true);
-      C = new GlobalVariable(*Callee->getParent(), C->getType(), true,
-                             GlobalVariable::InternalLinkage, C, "str");
-      EmitPutS(C, B, TD);
+      Value *GV = B.CreateGlobalString(FormatStr, "str");
+      EmitPutS(GV, B, TD);
       return CI->use_empty() ? (Value*)CI :
                     ConstantInt::get(CI->getType(), FormatStr.size()+1);
     }

Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/Printf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/Printf.ll?rev=143289&r1=143288&r2=143289&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyLibCalls/Printf.ll (original)
+++ llvm/trunk/test/Transforms/SimplifyLibCalls/Printf.ll Sat Oct 29 14:43:31 2011
@@ -1,9 +1,10 @@
-; RUN: opt < %s -simplify-libcalls -S -o %t
-; RUN: FileCheck < %t %s
+; RUN: opt < %s -simplify-libcalls -S | FileCheck %s
 
 @str = internal constant [13 x i8] c"hello world\0A\00"         ; <[13 x i8]*> [#uses=1]
 @str1 = internal constant [2 x i8] c"h\00"              ; <[2 x i8]*> [#uses=1]
 
+; CHECK: internal unnamed_addr constant [12 x i8] c"hello world\00"
+
 declare i32 @printf(i8*, ...)
 
 ; CHECK: define void @f0



From benny.kra at googlemail.com  Sat Oct 29 14:43:38 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Sat, 29 Oct 2011 19:43:38 -0000
Subject: [llvm-commits] [llvm] r143290 -
	/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
Message-ID: <20111029194338.B0B883524076@llvm.org>

Author: d0k
Date: Sat Oct 29 14:43:38 2011
New Revision: 143290

URL: http://llvm.org/viewvc/llvm-project?rev=143290&view=rev
Log:
PPC: Disable moves for all CR subregisters.

Should fix assertion failures on ppc buildbots.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=143290&r1=143289&r2=143290&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Sat Oct 29 14:43:38 2011
@@ -490,10 +490,8 @@
 
       // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
       // subregisters of CR2. We just need to emit a move of CR2.
-      if (Reg == PPC::CR2LT || Reg == PPC::CR2GT || Reg == PPC::CR2EQ)
+      if (PPC::CRBITRCRegisterClass->contains(Reg))
         continue;
-      if (Reg == PPC::CR2UN)
-        Reg = PPC::CR2;
 
       MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
       MachineLocation CSSrc(Reg);



From benny.kra at googlemail.com  Sat Oct 29 14:43:44 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Sat, 29 Oct 2011 19:43:44 -0000
Subject: [llvm-commits] [llvm] r143291 -
 /llvm/trunk/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll
Message-ID: <20111029194344.BE1573524076@llvm.org>

Author: d0k
Date: Sat Oct 29 14:43:44 2011
New Revision: 143291

URL: http://llvm.org/viewvc/llvm-project?rev=143291&view=rev
Log:
Force SSE for this test.

Modified:
    llvm/trunk/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll

Modified: llvm/trunk/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll?rev=143291&r1=143290&r2=143291&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll Sat Oct 29 14:43:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=x86 -fast-isel < %s | FileCheck %s
+; RUN: llc -march=x86 -fast-isel -mattr=+sse < %s | FileCheck %s
 ; <rdar://problem/10215997>
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
 target triple = "i386-apple-macosx10.7"



From hfinkel at anl.gov  Sat Oct 29 15:16:58 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Sat, 29 Oct 2011 15:16:58 -0500
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <1319914924.23036.852.camel@sapling>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
Message-ID: <1319919418.23036.881.camel@sapling>

On Sat, 2011-10-29 at 14:02 -0500, Hal Finkel wrote:
> On Sat, 2011-10-29 at 12:30 -0500, Hal Finkel wrote:
> > Ralf, et al.,
> > 
> > Attached is the latest version of my autovectorization patch. llvmdev
> > has been CC'd (as had been suggested to me); this e-mail contains
> > additional benchmark results.
> > 
> > First, these are preliminary results because I did not do the things
> > necessary to make them real (explicitly quiet the machine, bind the
> > processes to one cpu, etc.). But they should be good enough for
> > discussion.
> > 
> > I'm using LLVM head r143101, with the attached patch applied, and clang
> > head r143100 on an x86_64 machine (some kind of Intel Xeon). For the gcc
> > comparison, I'm using build Ubuntu 4.4.3-4ubuntu5. gcc was run -O3
> > without any other optimization flags. opt was run -vectorize
> > -unroll-allow-partial -O3 with no other optimization flags (the patch
> > adds the -vectorize option).
> 
> And opt had also been given the flag: -bb-vectorize-vector-bits=256

And this was a mistake (because the machine on which the benchmarks were
run does not have AVX). I've rerun, see better results below...

> 
>  -Hal
> 
> > llc was just given -O3.
> > 
> > Below I've included results using the benchmark program by Maleki, et
> > al. See:
> > An Evaluation of Vectorizing Compilers - PACT'11
> > (http://polaris.cs.uiuc.edu/~garzaran/doc/pact11.pdf). The source of
> > their benchmark program was retrieved from:
> > http://polaris.cs.uiuc.edu/~maleki1/TSVC.tar.gz
> > 
> > Also, when using clang, I had to pass -Dinline= on the command line:
> > when using -emit-llvm, clang appears not to emit code for functions
> > declared inline. This is a bug, but I've not yet tracked it down. There
> > are two such small functions in the benchmark program, and the regular
> > inliner *should* catch them anyway.
> > 
> > Results:
> > 0. Name of the loop
> > 1. Time using LLVM with vectorization
> > 2. Time using LLVM without vectorization
> > 3. Time using gcc with vectorization
> > 4. Time using gcc without vectorization

Here are improved results where the correct (and default)
vector-register size was used.

Loop       llvm-v   llvm     gcc-v    gcc
-------------------------------------------
S000        9.09     9.49     4.55    10.04
S111        7.28     7.37     7.68     7.83
S1111      13.78    14.48    16.14    16.30
S112       16.67    17.41    16.54    17.52
S1112      13.12    14.21    14.83    14.84
S113       22.12    22.88    22.05    22.05
S1113      11.06    11.42    11.03    11.01
S114       13.23    13.75    13.53    13.48
S115       32.76    33.24    49.98    49.99
S1115      13.68    14.18    13.65    13.66
S116       47.42    49.40    49.54    48.11
S118       10.84    11.26    10.79    10.50
S119        8.74     9.07    11.83    11.82
S1119       8.81     9.14     4.31    11.87
S121       17.28    18.78    14.84    17.31
S122        7.53     7.54     6.11     6.11
S123        6.90     7.38     7.42     7.41
S124        9.60     9.77     9.42     9.33
S125        6.92     7.22     4.67     7.81
S126        2.34     2.53     2.57     2.37
S127       12.19    12.97     7.06    14.50
S128       11.74    12.43    12.42    11.52
S131       28.75    29.91    25.17    28.94
S132       17.04    17.04    15.53    21.03
S141       12.28    12.26    12.38    12.05
S151       28.80    29.43    24.89    28.95
S152       15.54    16.03    11.19    15.63
S161        6.00     6.06     5.52     5.46
S1161      14.39    14.40     8.80     8.79
S162        8.19     9.05     5.36     8.18
S171       15.41     7.94     2.81     5.70
S172        5.71     5.89     2.75     5.70
S173       30.31    30.92    18.15    30.13
S174       30.18    31.66    18.51    30.16
S175        5.78     6.18     4.94     5.77
S176        5.59     5.83     4.41     7.65
S211       16.27    17.14    16.82    16.38
S212       13.21    14.28    13.34    13.18
S1213      12.81    13.46    12.80    12.43
S221       10.86    11.09     8.65     8.63
S1221       5.72     6.04     5.40     6.05
S222        6.02     6.26     5.70     5.72
S231       22.33    22.94    22.36    22.11
S232        6.88     6.88     6.89     6.89
S1232      15.30    15.34    15.05    15.10
S233       55.38    58.55    54.21    49.56
S2233      27.08    29.77    29.68    28.40
S235       44.00    44.92    46.94    43.93
S241       31.09    31.35    32.53    31.01
S242        7.19     7.20     7.20     7.20
S243       16.52    17.09    17.69    16.84
S244       14.45    14.83    16.91    16.82
S1244      14.71    14.83    14.77    14.40
S2244      10.04    10.62    10.40    10.06
S251       34.15    35.75    19.70    34.38
S1251      55.23    57.84    41.77    56.11
S2251      15.73    15.87    17.02    15.70
S3251      15.66    16.21    19.60    15.34
S252        6.18     6.32     7.72     7.26
S253       11.14    11.38    14.40    14.40
S254       18.41    18.70    28.23    28.06
S255        5.93     6.09     9.96     9.95
S256        3.08     3.42     3.10     3.09
S257        2.13     2.25     2.21     2.20
S258        1.79     1.82     1.84     1.84
S261       12.00    12.08    10.98    10.95
S271       32.82    33.04    33.25    33.01
S272       14.98    15.82    15.39    15.26
S273       13.92    14.04    16.86    16.80
S274       17.83    18.31    18.15    17.89
S275        2.92     3.02     3.36     2.98
S2275      32.80    33.50     8.97    33.60
S276       39.43    39.44    40.80    40.55
S277        4.80     4.80     4.81     4.80
S278       14.41    14.42    14.70    14.66
S279        8.03     8.29     7.25     7.27
S1279       9.71    10.06     9.34     9.25
S2710       7.71     8.04     7.86     7.56
S2711      35.53    35.55    36.56    36.00
S2712      32.94    33.17    34.24    33.47
S281       10.79    11.09    12.46    12.02
S1281      79.13    77.55    57.78    68.06
S291       11.80    11.78    14.03    14.03
S292        7.77     7.78     9.94     9.96
S293       15.50    15.87    19.32    19.33
S2101       2.56     2.58     2.59     2.60
S2102      16.71    17.53    16.68    16.75
S2111       5.60     5.60     5.85     5.85
S311       72.03    72.03    72.23    72.03
S31111      7.49     6.00     6.00     6.00
S312       96.04    96.04    96.05    96.03
S313       36.02    36.13    36.03    36.02
S314       36.01    36.07    74.67    72.42
S315        8.96     8.99     9.35     9.30
S316       36.02    36.06    72.08    74.87
S317      444.93   444.94   451.82   451.78
S318        9.05     9.07     7.30     7.30
S319       34.54    36.53    34.42    34.19
S3110       8.51     8.57     4.11     4.11
S13110      5.75     5.77    12.12    12.12
S3111       3.60     3.62     3.60     3.60
S3112       7.19     7.30     7.21     7.20
S3113      35.13    35.47    60.21    60.20
S321       16.79    16.81    16.80    16.80
S322       12.42    12.60    12.60    12.60
S323       10.86    11.02     8.48     8.51
S331        4.23     4.23     7.20     7.20
S332        7.20     7.21     5.21     5.31
S341        4.79     4.85     7.23     7.20
S342        6.01     6.09     7.25     7.20
S343        2.04     2.06     2.16     2.01
S351       46.61    47.34    21.82    46.46
S1351      49.28    50.35    33.68    49.06
S352       57.65    58.04    57.68    57.64
S353        8.21     8.38     8.34     8.19
S421       42.94    43.34    20.62    22.46
S1421      25.15    25.81    15.85    24.76
S422       87.39    87.53    79.22    78.99
S423      155.01   155.29   154.56   154.38
S424       36.51    37.51    11.42    22.36
S431       57.10    60.66    27.59    57.16
S441       14.04    13.29    12.88    12.81
S442        6.00     6.00     6.96     6.90
S443       17.28    17.77    17.15    16.95
S451       48.92    49.08    49.03    49.14
S452       42.98    39.32    14.64    96.03
S453       28.05    28.06    14.60    14.40
S471        8.24     8.65     8.39     8.43
S481       10.88    11.15    12.04    12.00
S482        9.21     9.31     9.19     9.17
S491       11.26    11.38    11.37    11.28
S4112       8.21     8.36     9.13     8.94
S4113       8.65     8.81     8.86     8.85
S4114      11.82    12.15    12.18    11.77
S4115       8.28     8.46     8.95     8.59
S4116       3.22     3.23     6.02     5.94
S4117      13.95     9.61    10.16     9.98
S4121       8.21     8.26     4.04     8.17
va         28.46    28.58    23.58    48.46
vag        12.35    12.36    13.58    13.20
vas        13.45    13.49    13.03    12.47
vif         4.55     4.57     5.06     4.92
vpv        57.08    57.22    28.28    57.24
vtv        57.81    57.83    28.40    57.63
vpvtv      32.82    32.84    16.35    32.73
vpvts       5.82     5.83     2.99     6.38
vpvpv      32.87    32.89    16.54    32.85
vtvtv      32.82    32.80    16.84    35.97
vsumr      72.04    72.03    72.20    72.04
vdotr      72.06    72.05    72.42    72.04
vbor      205.24   380.81    99.80   372.05

 -Hal

> > 
> > Loop       llvm-v   llvm     gcc-v    gcc
> > -------------------------------------------
> > S000        9.59     9.49     4.55    10.04
> > S111        7.67     7.37     7.68     7.83
> > S1111      13.98    14.48    16.14    16.30
> > S112       17.43    17.41    16.54    17.52
> > S1112      13.87    14.21    14.83    14.84
> > S113       22.97    22.88    22.05    22.05
> > S1113      11.46    11.42    11.03    11.01
> > S114       13.47    13.75    13.53    13.48
> > S115       33.06    33.24    49.98    49.99
> > S1115      13.91    14.18    13.65    13.66
> > S116       48.74    49.40    49.54    48.11
> > S118       11.04    11.26    10.79    10.50
> > S119        8.97     9.07    11.83    11.82
> > S1119       9.04     9.14     4.31    11.87
> > S121       18.06    18.78    14.84    17.31
> > S122        7.58     7.54     6.11     6.11
> > S123        7.02     7.38     7.42     7.41
> > S124        9.62     9.77     9.42     9.33
> > S125        7.14     7.22     4.67     7.81
> > S126        2.32     2.53     2.57     2.37
> > S127       12.87    12.97     7.06    14.50
> > S128       12.58    12.43    12.42    11.52
> > S131       29.91    29.91    25.17    28.94
> > S132       17.04    17.04    15.53    21.03
> > S141       12.59    12.26    12.38    12.05
> > S151       28.92    29.43    24.89    28.95
> > S152       15.68    16.03    11.19    15.63
> > S161        6.06     6.06     5.52     5.46
> > S1161      14.46    14.40     8.80     8.79
> > S162        8.31     9.05     5.36     8.18
> > S171       15.47     7.94     2.81     5.70
> > S172        5.92     5.89     2.75     5.70
> > S173       31.59    30.92    18.15    30.13
> > S174       31.16    31.66    18.51    30.16
> > S175        5.80     6.18     4.94     5.77
> > S176        5.69     5.83     4.41     7.65
> > S211       16.56    17.14    16.82    16.38
> > S212       13.46    14.28    13.34    13.18
> > S1213      13.12    13.46    12.80    12.43
> > S221       10.88    11.09     8.65     8.63
> > S1221       5.80     6.04     5.40     6.05
> > S222        6.01     6.26     5.70     5.72
> > S231       23.78    22.94    22.36    22.11
> > S232        6.88     6.88     6.89     6.89
> > S1232      16.00    15.34    15.05    15.10
> > S233       57.48    58.55    54.21    49.56
> > S2233      27.65    29.77    29.68    28.40
> > S235       46.40    44.92    46.94    43.93
> > S241       31.62    31.35    32.53    31.01
> > S242        7.20     7.20     7.20     7.20
> > S243       16.78    17.09    17.69    16.84
> > S244       14.64    14.83    16.91    16.82
> > S1244      14.98    14.83    14.77    14.40
> > S2244      10.47    10.62    10.40    10.06
> > S251       35.10    35.75    19.70    34.38
> > S1251      56.65    57.84    41.77    56.11
> > S2251      15.96    15.87    17.02    15.70
> > S3251      16.41    16.21    19.60    15.34
> > S252        7.24     6.32     7.72     7.26
> > S253       12.55    11.38    14.40    14.40
> > S254       19.08    18.70    28.23    28.06
> > S255        5.94     6.09     9.96     9.95
> > S256        3.14     3.42     3.10     3.09
> > S257        2.18     2.25     2.21     2.20
> > S258        1.80     1.82     1.84     1.84
> > S261       12.00    12.08    10.98    10.95
> > S271       32.93    33.04    33.25    33.01
> > S272       15.48    15.82    15.39    15.26
> > S273       13.99    14.04    16.86    16.80
> > S274       18.38    18.31    18.15    17.89
> > S275        3.02     3.02     3.36     2.98
> > S2275      33.71    33.50     8.97    33.60
> > S276       39.52    39.44    40.80    40.55
> > S277        4.81     4.80     4.81     4.80
> > S278       14.43    14.42    14.70    14.66
> > S279        8.10     8.29     7.25     7.27
> > S1279       9.77    10.06     9.34     9.25
> > S2710       7.85     8.04     7.86     7.56
> > S2711      35.54    35.55    36.56    36.00
> > S2712      33.16    33.17    34.24    33.47
> > S281       10.97    11.09    12.46    12.02
> > S1281      79.37    77.55    57.78    68.06
> > S291       11.94    11.78    14.03    14.03
> > S292        7.88     7.78     9.94     9.96
> > S293       15.90    15.87    19.32    19.33
> > S2101       2.59     2.58     2.59     2.60
> > S2102      17.63    17.53    16.68    16.75
> > S2111       5.63     5.60     5.85     5.85
> > S311       72.07    72.03    72.23    72.03
> > S31111      7.49     6.00     6.00     6.00
> > S312       96.06    96.04    96.05    96.03
> > S313       36.50    36.13    36.03    36.02
> > S314       36.10    36.07    74.67    72.42
> > S315        9.00     8.99     9.35     9.30
> > S316       36.11    36.06    72.08    74.87
> > S317      444.92   444.94   451.82   451.78
> > S318        9.04     9.07     7.30     7.30
> > S319       34.76    36.53    34.42    34.19
> > S3110       8.53     8.57     4.11     4.11
> > S13110      5.76     5.77    12.12    12.12
> > S3111       3.60     3.62     3.60     3.60
> > S3112       7.20     7.30     7.21     7.20
> > S3113      35.12    35.47    60.21    60.20
> > S321       16.81    16.81    16.80    16.80
> > S322       12.42    12.60    12.60    12.60
> > S323       10.93    11.02     8.48     8.51
> > S331        4.23     4.23     7.20     7.20
> > S332        7.21     7.21     5.21     5.31
> > S341        4.74     4.85     7.23     7.20
> > S342        6.02     6.09     7.25     7.20
> > S343        2.14     2.06     2.16     2.01
> > S351       49.26    47.34    21.82    46.46
> > S1351      50.85    50.35    33.68    49.06
> > S352       58.14    58.04    57.68    57.64
> > S353        8.35     8.38     8.34     8.19
> > S421       43.13    43.34    20.62    22.46
> > S1421      25.25    25.81    15.85    24.76
> > S422       88.36    87.53    79.22    78.99
> > S423      155.13   155.29   154.56   154.38
> > S424       37.11    37.51    11.42    22.36
> > S431       58.22    60.66    27.59    57.16
> > S441       14.05    13.29    12.88    12.81
> > S442        6.08     6.00     6.96     6.90
> > S443       17.60    17.77    17.15    16.95
> > S451       48.95    49.08    49.03    49.14
> > S452       42.98    39.32    14.64    96.03
> > S453       28.06    28.06    14.60    14.40
> > S471        8.53     8.65     8.39     8.43
> > S481       10.98    11.15    12.04    12.00
> > S482        9.31     9.31     9.19     9.17
> > S491       11.54    11.38    11.37    11.28
> > S4112       8.21     8.36     9.13     8.94
> > S4113       8.77     8.81     8.86     8.85
> > S4114      12.32    12.15    12.18    11.77
> > S4115       8.48     8.46     8.95     8.59
> > S4116       3.21     3.23     6.02     5.94
> > S4117      14.08     9.61    10.16     9.98
> > S4121       8.53     8.26     4.04     8.17
> > va         30.09    28.58    23.58    48.46
> > vag        12.35    12.36    13.58    13.20
> > vas        13.74    13.49    13.03    12.47
> > vif         4.49     4.57     5.06     4.92
> > vpv        58.59    57.22    28.28    57.24
> > vtv        59.15    57.83    28.40    57.63
> > vpvtv      33.18    32.84    16.35    32.73
> > vpvts       5.99     5.83     2.99     6.38
> > vpvpv      33.25    32.89    16.54    32.85
> > vtvtv      32.83    32.80    16.84    35.97
> > vsumr      72.03    72.03    72.20    72.04
> > vdotr      72.05    72.05    72.42    72.04
> > vbor      205.22   380.81    99.80   372.05
> > 
> > I've yet to go through these in detail (they just finished running 5
> > minutes ago). But for the curious (and I've had several requests for
> > benchmarks), here you go. There is obviously more work to do.
> > 
> >  -Hal
> > 
> > On Fri, 2011-10-28 at 14:30 +0200, Ralf Karrenberg wrote:
> > > Hi Hal,
> > > 
> > > those numbers look very promising, great work! :)
> > > 
> > > Best,
> > > Ralf
> > > 
> > > ----- Original Message -----
> > > > From: "Hal Finkel" <hfinkel at anl.gov>
> > > > To: "Bruno Cardoso Lopes" <bruno.cardoso at gmail.com>
> > > > Cc: llvm-commits at cs.uiuc.edu
> > > > Sent: Freitag, 28. Oktober 2011 13:50:00
> > > > Subject: Re: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
> > > > 
> > > > Bruno, et al.,
> > > > 
> > > > I've attached a new version of the patch that contains improvements
> > > > (and
> > > > a critical bug fix [the code output is not more right, but the pass
> > > > in
> > > > the older patch would crash in certain cases and now does not])
> > > > compared
> > > > to previous versions that I've posted.
> > > > 
> > > > First, these are preliminary results because I did not do the things
> > > > necessary to make them real (explicitly quiet the machine, bind the
> > > > processes to one cpu, etc.). But they should be good enough for
> > > > discussion.
> > > > 
> > > > I'm using LLVM head r143101, with the attached patch applied, and
> > > > clang
> > > > head r143100 on an x86_64 machine (some kind of Intel Xeon). For the
> > > > gcc
> > > > comparison, I'm using build Ubuntu 4.4.3-4ubuntu5. gcc was run -O3
> > > > without any other optimization flags. opt was run -vectorize
> > > > -unroll-allow-partial -O3 with no other optimization flags (the patch
> > > > adds the -vectorize option). llc was just given -O3.
> > > > 
> > > > It is not difficult to construct an example in which vectorization
> > > > would
> > > > be useful: take a loop that does more computation than load/stores,
> > > > and
> > > > (partially) unroll it. Here is a simple case:
> > > > 
> > > > #define ITER 5000
> > > > #define NUM 200
> > > > double a[NUM][NUM];
> > > > double b[NUM][NUM];
> > > > 
> > > > ...
> > > > 
> > > > int main()
> > > > {
> > > > ...
> > > > 
> > > >   for (int i = 0; i < ITER; ++i) {
> > > >     for (int x = 0; x < NUM; ++x)
> > > >     for (int y = 0; y < NUM; ++y) {
> > > >       double v = a[x][y], w = b[x][y];
> > > >       double z1 = v*w;
> > > >       double z2 = v+w;
> > > >       double z3 = z1*z2;
> > > >       double z4 = z3+v;
> > > >       double z5 = z2+w;
> > > >       double z6 = z4*z5;
> > > >       double z7 = z4+z5;
> > > >       a[x][y] = v*v-z6;
> > > >       b[x][y] = w-z7;
> > > >     }
> > > >   }
> > > > 
> > > >  ...
> > > > 
> > > >   return 0;
> > > > }
> > > > 
> > > > Results:
> > > > gcc -03: 0m1.790s
> > > > llvm -vectorize: 0m2.360s
> > > > llvm: 0m2.780s
> > > > gcc -fno-tree-vectorize: 0m2.810s
> > > > (these are the user times after I've run enough for the times to
> > > > settle
> > > > to three decimal places)
> > > > 
> > > > So the vectorization gives a ~15% improvement in the running time.
> > > > gcc's
> > > > vectorization still does a much better job, however (yielding an ~36%
> > > > improvement). So there is still work to do ;)
> > > > 
> > > > Additionally, I've checked the autovectorization on some classic
> > > > numerical benchmarks from netlib. On these benchmarks, clang/llvm
> > > > already do a good job compared to gcc (gcc is only about 10% better,
> > > > and
> > > > this is true regardless of whether gcc's vectorization is on or off).
> > > > For these cases, autovectorization provides an insignificant speedup
> > > > in
> > > > most cases (but does not tend to make things worse, just not really
> > > > any
> > > > better either). Because gcc's vectorization also did not really help
> > > > gcc
> > > > in these cases, I'm not surprised. A good collection of these is
> > > > available here:
> > > > http://www.roylongbottom.org.uk/classic_benchmarks.tar.gz
> > > > 
> > > > I've yet to run the test suite using the pass to validate it. That is
> > > > something that I plan to do. Actually, the "Livermore Loops" test in
> > > > the
> > > > aforementioned archive contains checksums to validate the results,
> > > > and
> > > > it looks like 1 or 2 of the loop results are wrong with vectorization
> > > > turned on, so I'll have to investigate that.
> > > > 
> > > >  -Hal
> > > > 
> > > > On Wed, 2011-10-26 at 18:49 -0200, Bruno Cardoso Lopes wrote:
> > > > > Hi Hal,
> > > > > 
> > > > > On Fri, Oct 21, 2011 at 7:04 PM, Hal Finkel <hfinkel at anl.gov>
> > > > > wrote:
> > > > > > I've attached an initial version of a basic-block
> > > > > > autovectorization
> > > > > > pass. It works by searching a basic block for pairable
> > > > > > (independent)
> > > > > > instructions, and, using a chain-seeking heuristic, selects
> > > > > > pairings
> > > > > > likely to provide an overall speedup (if such pairings can be
> > > > > > found).
> > > > > > The selected pairs are then fused and, if necessary, other
> > > > > > instructions
> > > > > > are moved in order to maintain data-flow consistency. This works
> > > > > > only
> > > > > > within one basic block, but can do loop vectorization in
> > > > > > combination
> > > > > > with (partial) unrolling. The basic idea was inspired by the
> > > > > > Vienna MAP
> > > > > > Vectorizor, which has been used to vectorize FFT kernels, but the
> > > > > > algorithm used here is different.
> > > > > >
> > > > > > To try it, use -bb-vectorize with opt. There are a few options:
> > > > > > -bb-vectorize-req-chain-depth: default: 3 -- The depth of the
> > > > > > chain of
> > > > > > instruction pairs necessary in order to consider the pairs that
> > > > > > compose
> > > > > > the chain worthy of vectorization.
> > > > > > -bb-vectorize-vector-bits: default: 128 -- The size of the target
> > > > > > vector
> > > > > > registers
> > > > > > -bb-vectorize-no-ints -- Don't consider integer instructions
> > > > > > -bb-vectorize-no-floats -- Don't consider floating-point
> > > > > > instructions
> > > > > >
> > > > > > The vectorizor generates a lot of insert_element/extract_element
> > > > > > pairs;
> > > > > > The assumption is that other passes will turn these into shuffles
> > > > > > when
> > > > > > possible (it looks like some work is necessary here). It will
> > > > > > also
> > > > > > vectorize vector instructions, and generates shuffles in this
> > > > > > case
> > > > > > (again, other passes should combine these as appropriate).
> > > > > >
> > > > > > Currently, it does not fuse load or store instructions, but that
> > > > > > is a
> > > > > > feature that I'd like to add. Of course, alignment information is
> > > > > > an
> > > > > > issue for load/store vectorization (or maybe I should just fuse
> > > > > > them
> > > > > > anyway and let isel deal with unaligned cases?).
> > > > > >
> > > > > > Also, support needs to be added for fusing known intrinsics (fma,
> > > > > > etc.),
> > > > > > and, as has been discussed on llvmdev, we should add some
> > > > > > intrinsics to
> > > > > > allow the generation of addsub-type instructions.
> > > > > >
> > > > > > I've included a few tests, but it needs more. Please review (I'll
> > > > > > commit
> > > > > > if and when everyone is happy).
> > > > > >
> > > > > > Thanks in advance,
> > > > > > Hal
> > > > > >
> > > > > > P.S. There is another option (not so useful right now, but could
> > > > > > be):
> > > > > > -bb-vectorize-fast-dep -- Don't do a full inter-instruction
> > > > > > dependency
> > > > > > analysis; instead stop looking for instruction pairs after the
> > > > > > first use
> > > > > > of an instruction's value. [This makes the pass faster, but would
> > > > > > require a data-dependence-based reordering pass in order to be
> > > > > > effective].
> > > > > 
> > > > > Cool! :)
> > > > > Have you run this pass with any benchmark or the llvm testsuite?
> > > > > Does
> > > > > it presents any regression?
> > > > > Do you have any performance results?
> > > > > Cheers,
> > > > > 
> > > > 
> > > > --
> > > > Hal Finkel
> > > > Postdoctoral Appointee
> > > > Leadership Computing Facility
> > > > Argonne National Laboratory
> > > > 
> > > > _______________________________________________
> > > > llvm-commits mailing list
> > > > llvm-commits at cs.uiuc.edu
> > > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> > > > 
> > 
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From peter at pcc.me.uk  Sat Oct 29 15:54:49 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Sat, 29 Oct 2011 21:54:49 +0100
Subject: [llvm-commits] [LLVMdev] [PATCH] BasicBlock
	Autovectorization	Pass
In-Reply-To: <1319909412.23036.851.camel@sapling>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
Message-ID: <20111029205449.GA12781@pcc.me.uk>

On Sat, Oct 29, 2011 at 12:30:12PM -0500, Hal Finkel wrote:
> Also, when using clang, I had to pass -Dinline= on the command line:
> when using -emit-llvm, clang appears not to emit code for functions
> declared inline. This is a bug, but I've not yet tracked it down.

http://clang.llvm.org/compatibility.html#inline

Thanks,
-- 
Peter

From hfinkel at anl.gov  Sat Oct 29 16:24:15 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Sat, 29 Oct 2011 16:24:15 -0500
Subject: [llvm-commits] [LLVMdev] [PATCH] BasicBlock Autovectorization
 Pass
In-Reply-To: <20111029205449.GA12781@pcc.me.uk>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling> <20111029205449.GA12781@pcc.me.uk>
Message-ID: <1319923455.23036.902.camel@sapling>

On Sat, 2011-10-29 at 21:54 +0100, Peter Collingbourne wrote:
> On Sat, Oct 29, 2011 at 12:30:12PM -0500, Hal Finkel wrote:
> > Also, when using clang, I had to pass -Dinline= on the command line:
> > when using -emit-llvm, clang appears not to emit code for functions
> > declared inline. This is a bug, but I've not yet tracked it down.
> 
> http://clang.llvm.org/compatibility.html#inline

Thanks! (Of course, the standard does not govern the relationship
between the compiler frontend and the backend, so it *could* work some
other way).

 -Hal

> 
> Thanks,

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From nadav.rotem at intel.com  Sat Oct 29 16:23:04 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Sat, 29 Oct 2011 21:23:04 -0000
Subject: [llvm-commits] [llvm] r143297 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
 test/CodeGen/X86/2011-10-27-tstore.ll test/CodeGen/X86/vec_shuffle-37.ll
Message-ID: <20111029212304.BCD2C3524076@llvm.org>

Author: nadav
Date: Sat Oct 29 16:23:04 2011
New Revision: 143297

URL: http://llvm.org/viewvc/llvm-project?rev=143297&view=rev
Log:
Add a new DAGCombine optimization for BUILD_VECTOR.
If all of the inputs are zero/any_extended, create a new simple BV
which can be further optimized by other BV optimizations.


Added:
    llvm/trunk/test/CodeGen/X86/2011-10-27-tstore.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=143297&r1=143296&r2=143297&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Oct 29 16:23:04 2011
@@ -6936,7 +6936,90 @@
 
 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
   unsigned NumInScalars = N->getNumOperands();
+  DebugLoc dl = N->getDebugLoc();
   EVT VT = N->getValueType(0);
+  // Check to see if this is a BUILD_VECTOR of a bunch of values
+  // which come from any_extend or zero_extend nodes. If so, we can create
+  // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
+  // optimizations.
+  EVT SourceType = MVT::Other;
+  bool allExtend = true;
+  bool allAnyExt = true;
+  for (unsigned i = 0; i < NumInScalars; ++i) {
+    SDValue In = N->getOperand(i);
+    // Ignore undef inputs.
+    if (In.getOpcode() == ISD::UNDEF) continue;
+
+    bool AnyExt  = In.getOpcode() == ISD::ANY_EXTEND;
+    bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
+
+    // Abort non-extend incoming values.
+    if (!ZeroExt && !AnyExt) {
+      allExtend = false;
+      break;
+    }
+
+    // The input is a ZeroExt or AnyExt. Check the original type.
+    EVT InTy = In.getOperand(0).getValueType();
+
+    // Check that all of the widened source types are the same.
+    if (SourceType == MVT::Other)
+      SourceType = InTy;
+    else if (InTy != SourceType) {
+      // Multiple income types. Abort.
+      allExtend = false;
+      break;
+    }
+
+    // Check if all of the extends are ANY_EXTENDs.
+    allAnyExt &= AnyExt;
+  }
+
+  // And we are post type-legalization,
+  // If all of the values are Ext or undef,
+  // We have a non undef entry.
+  if (LegalTypes && allExtend && SourceType != MVT::Other) {
+    bool isLE = TLI.isLittleEndian();
+    EVT InScalarTy = SourceType.getScalarType();
+    EVT OutScalarTy = N->getValueType(0).getScalarType();
+    unsigned ElemRatio = OutScalarTy.getSizeInBits()/InScalarTy.getSizeInBits();
+    assert(ElemRatio > 1 && "Invalid element size ratio");
+    SDValue Filler = allAnyExt ? DAG.getUNDEF(InScalarTy):
+                                 DAG.getConstant(0, InScalarTy);
+
+    unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements();
+    SmallVector<SDValue,8> Ops(NewBVElems , Filler);
+
+    // Populate the new build_vector
+    for (unsigned i=0; i < N->getNumOperands(); ++i) {
+      SDValue Cast = N->getOperand(i);
+      assert(Cast.getOpcode() == ISD::ANY_EXTEND ||
+             Cast.getOpcode() == ISD::ZERO_EXTEND ||
+             Cast.getOpcode() == ISD::UNDEF && "Invalid cast opcode");
+      SDValue In;
+      if (Cast.getOpcode() == ISD::UNDEF)
+        In = DAG.getUNDEF(InScalarTy);
+      else
+        In = Cast->getOperand(0);
+      unsigned Index = isLE ? (i * ElemRatio) :
+                              (i * ElemRatio + (ElemRatio - 1));
+
+      assert(Index < Ops.size() && "Invalid index");
+      Ops[Index] = In;
+    }
+
+    // The type of the new BUILD_VECTOR node.
+    EVT VecVT = EVT::getVectorVT(*DAG.getContext(), InScalarTy, NewBVElems);
+    assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() &&
+           "Invalid vector size");
+
+    // Make the new BUILD_VECTOR.
+    SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
+                                 VecVT, &Ops[0], Ops.size());
+
+    // Bitcast to the desired type.
+    return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
+  }
 
   // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
   // operations.  If so, and if the EXTRACT_VECTOR_ELT vector inputs come from

Modified: llvm/trunk/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll?rev=143297&r1=143296&r2=143297&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll Sat Oct 29 16:23:04 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-linux -mattr=+mmx | grep movd | count 3
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+mmx | grep movd | count 2
 
 define i64 @a(i32 %a, i32 %b) nounwind readnone {
 entry:

Added: llvm/trunk/test/CodeGen/X86/2011-10-27-tstore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-27-tstore.ll?rev=143297&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-10-27-tstore.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2011-10-27-tstore.ll Sat Oct 29 16:23:04 2011
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
+
+target triple = "x86_64-unknown-linux-gnu"
+
+;CHECK: ltstore
+;CHECK: pshufd
+;CHECK: pshufd
+;CHECK: ret
+define void @ltstore() {
+entry:
+  %in = load <4 x i32>* undef
+  %j = shufflevector <4 x i32> %in, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
+  store <2 x i32> %j, <2 x i32>* undef
+  ret void
+}
+

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll?rev=143297&r1=143296&r2=143297&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll Sat Oct 29 16:23:04 2011
@@ -26,10 +26,12 @@
 
 define void @t02(<8 x i32>* %source, <2 x i32>* %dest) nounwind noinline {
 entry:
-; CHECK: movl  36({{%rdi|%rcx}})
-; CHECK-NEXT: movl  48({{%rdi|%rcx}})
-; CHECK: punpcklqdq
-; CHECK: movq    %xmm0, ({{%rsi|%rdx}})
+; CHECK: t02
+; CHECK: movaps
+; CHECK: shufps
+; CHECK: pshufd
+; CHECK: movq
+; CHECK: ret
   %0 = bitcast <8 x i32>* %source to <4 x i32>*
   %arrayidx = getelementptr inbounds <4 x i32>* %0, i64 3
   %tmp2 = load <4 x i32>* %arrayidx, align 16



From hfinkel at anl.gov  Sat Oct 29 17:56:31 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Sat, 29 Oct 2011 17:56:31 -0500
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <1319919418.23036.881.camel@sapling>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
	<1319919418.23036.881.camel@sapling>
Message-ID: <1319928991.23036.957.camel@sapling>

On Sat, 2011-10-29 at 15:16 -0500, Hal Finkel wrote:
> On Sat, 2011-10-29 at 14:02 -0500, Hal Finkel wrote:
> > On Sat, 2011-10-29 at 12:30 -0500, Hal Finkel wrote:
> > > Ralf, et al.,
> > > 
> > > Attached is the latest version of my autovectorization patch. llvmdev
> > > has been CC'd (as had been suggested to me); this e-mail contains
> > > additional benchmark results.
> > > 
> > > First, these are preliminary results because I did not do the things
> > > necessary to make them real (explicitly quiet the machine, bind the
> > > processes to one cpu, etc.). But they should be good enough for
> > > discussion.
> > > 
> > > I'm using LLVM head r143101, with the attached patch applied, and clang
> > > head r143100 on an x86_64 machine (some kind of Intel Xeon). For the gcc
> > > comparison, I'm using build Ubuntu 4.4.3-4ubuntu5. gcc was run -O3
> > > without any other optimization flags. opt was run -vectorize
> > > -unroll-allow-partial -O3 with no other optimization flags (the patch
> > > adds the -vectorize option).
> > 
> > And opt had also been given the flag: -bb-vectorize-vector-bits=256
> 
> And this was a mistake (because the machine on which the benchmarks were
> run does not have AVX). I've rerun, see better results below...
> 
> > 
> >  -Hal
> > 
> > > llc was just given -O3.
> > > 
> > > Below I've included results using the benchmark program by Maleki, et
> > > al. See:
> > > An Evaluation of Vectorizing Compilers - PACT'11
> > > (http://polaris.cs.uiuc.edu/~garzaran/doc/pact11.pdf). The source of
> > > their benchmark program was retrieved from:
> > > http://polaris.cs.uiuc.edu/~maleki1/TSVC.tar.gz
> > > 
> > > Also, when using clang, I had to pass -Dinline= on the command line:
> > > when using -emit-llvm, clang appears not to emit code for functions
> > > declared inline. This is a bug, but I've not yet tracked it down. There
> > > are two such small functions in the benchmark program, and the regular
> > > inliner *should* catch them anyway.
> > > 
> > > Results:
> > > 0. Name of the loop
> > > 1. Time using LLVM with vectorization
> > > 2. Time using LLVM without vectorization
> > > 3. Time using gcc with vectorization
> > > 4. Time using gcc without vectorization

As Peter Collingbourne indirectly pointed out to me, clang's
optimizations are still important (even if it is emitting only llvm).
I've rerun the llvm code generation steps, adding -O3 to clang. Here are
the results (they are significantly better):

Loop       llvm-v   llvm     gcc-v    gcc
-------------------------------------------
S000        9.10     9.59     4.55    10.04
S111        7.29     7.65     7.68     7.83
S1111      13.87    14.72    16.14    16.30
S112       16.67    17.45    16.54    17.52
S1112      13.16    13.87    14.83    14.84
S113       22.14    22.98    22.05    22.05
S1113      11.06    11.48    11.03    11.01
S114       13.21    13.81    13.53    13.48
S115       32.82    33.36    49.98    49.99
S1115      13.67    14.23    13.65    13.66
S116       47.37    49.43    49.54    48.11
S118       10.81    11.25    10.79    10.50
S119        8.73     9.09    11.83    11.82
S1119       8.82     9.15     4.31    11.87
S121       17.29    18.06    14.84    17.31
S122        7.53     7.70     6.11     6.11
S123        6.93     7.10     7.42     7.41
S124        9.63     9.84     9.42     9.33
S125        6.94     7.10     4.67     7.81
S126        2.34     2.55     2.57     2.37
S127       12.23    12.68     7.06    14.50
S128       11.78    12.41    12.42    11.52
S131       28.79    30.11    25.17    28.94
S132       17.04    17.04    15.53    21.03
S141       12.26    12.85    12.38    12.05
S151       28.79    30.11    24.89    28.95
S152       15.53    16.03    11.19    15.63
S161        6.00     6.12     5.52     5.46
S1161      14.40    14.50     8.80     8.79
S162        8.19     8.41     5.36     8.18
S171       15.41     7.96     2.81     5.70
S172        5.70     5.97     2.75     5.70
S173       30.32    31.69    18.15    30.13
S174       30.20    31.53    18.51    30.16
S175        5.79     6.04     4.94     5.77
S176        5.59     5.83     4.41     7.65
S211       16.31    16.89    16.82    16.38
S212       13.23    13.50    13.34    13.18
S1213      12.82    13.35    12.80    12.43
S221       10.87    11.09     8.65     8.63
S1221       5.72     6.03     5.40     6.05
S222        6.01     6.29     5.70     5.72
S231       22.38    24.22    22.36    22.11
S232        6.89     6.94     6.89     6.89
S1232      15.31    16.43    15.05    15.10
S233       55.47    59.98    54.21    49.56
S2233      27.23    29.71    29.68    28.40
S235       44.08    47.85    46.94    43.93
S241       31.14    31.72    32.53    31.01
S242        7.20     7.21     7.20     7.20
S243       16.54    16.99    17.69    16.84
S244       14.51    14.93    16.91    16.82
S1244      14.72    15.02    14.77    14.40
S2244      10.09    10.60    10.40    10.06
S251       34.42    35.55    19.70    34.38
S1251      55.39    57.11    41.77    56.11
S2251      15.69    16.26    17.02    15.70
S3251      15.69    16.52    19.60    15.34
S252        6.18     6.46     7.72     7.26
S253       11.19    11.52    14.40    14.40
S254       18.00    18.98    28.23    28.06
S255        5.94     6.14     9.96     9.95
S256        3.09     3.39     3.10     3.09
S257        2.13     2.31     2.21     2.20
S258        1.80     1.87     1.84     1.84
S261       12.00    12.22    10.98    10.95
S271       32.81    33.76    33.25    33.01
S272       15.04    15.52    15.39    15.26
S273       13.93    14.10    16.86    16.80
S274       17.83    18.53    18.15    17.89
S275        2.92     3.14     3.36     2.98
S2275      32.81    34.95     8.97    33.60
S276       41.26    41.97    40.80    40.55
S277        4.80     4.93     4.81     4.80
S278       14.43    14.76    14.70    14.66
S279        8.05     8.24     7.25     7.27
S1279       9.72     9.92     9.34     9.25
S2710       7.73     8.07     7.86     7.56
S2711      36.49    37.10    36.56    36.00
S2712      32.96    33.96    34.24    33.47
S281       10.80    11.32    12.46    12.02
S1281      79.10    78.11    57.78    68.06
S291       11.79    12.27    14.03    14.03
S292        6.70     6.91     9.94     9.96
S293       15.50    16.24    19.32    19.33
S2101       2.56     2.67     2.59     2.60
S2102      16.74    18.45    16.68    16.75
S2111       5.59     5.63     5.85     5.85
S311       72.04    72.27    72.23    72.03
S31111      7.50     6.01     6.00     6.00
S312       96.04    96.17    96.05    96.03
S313       36.02    36.61    36.03    36.02
S314       36.01    36.12    74.67    72.42
S315        9.11     9.21     9.35     9.30
S316       36.01    36.12    72.08    74.87
S317      444.91   444.94   451.82   451.78
S318        9.07     9.12     7.30     7.30
S319       34.57    36.46    34.42    34.19
S3110       8.52     8.61     4.11     4.11
S13110      5.75     5.78    12.12    12.12
S3111       3.60     3.64     3.60     3.60
S3112       7.20     7.30     7.21     7.20
S3113      33.68    34.18    60.21    60.20
S321       16.80    16.87    16.80    16.80
S322       12.42    12.64    12.60    12.60
S323       10.88    11.24     8.48     8.51
S331        4.23     4.36     7.20     7.20
S332        7.20     7.28     5.21     5.31
S341        4.80     5.04     7.23     7.20
S342        6.01     6.24     7.25     7.20
S343        2.04     2.16     2.16     2.01
S351       46.63    48.65    21.82    46.46
S1351      49.37    51.28    33.68    49.06
S352       57.64    58.44    57.68    57.64
S353        8.21     8.44     8.34     8.19
S421       24.26    25.29    20.62    22.46
S1421      25.18    26.16    15.85    24.76
S422       80.08    81.51    79.22    78.99
S423      155.02   155.21   154.56   154.38
S424       22.62    23.35    11.42    22.36
S431       57.22    59.82    27.59    57.16
S441       13.27    14.23    12.88    12.81
S442        5.99     6.13     6.96     6.90
S443       17.37    17.77    17.15    16.95
S451       48.92    48.99    49.03    49.14
S452       42.97    39.57    14.64    96.03
S453       28.06    28.07    14.60    14.40
S471        8.27     8.56     8.39     8.43
S481       10.93    11.23    12.04    12.00
S482        9.21     9.42     9.19     9.17
S491       11.31    11.60    11.37    11.28
S4112       8.21     8.45     9.13     8.94
S4113       8.65     8.95     8.86     8.85
S4114      11.87    12.35    12.18    11.77
S4115       8.28     8.51     8.95     8.59
S4116       3.23     3.22     6.02     5.94
S4117      13.97     9.69    10.16     9.98
S4121       8.20     8.44     4.04     8.17
va         28.50    29.33    23.58    48.46
vag        12.37    12.93    13.58    13.20
vas        13.46    14.15    13.03    12.47
vif         4.55     4.79     5.06     4.92
vpv        57.21    59.83    28.28    57.24
vtv        57.92    60.42    28.40    57.63
vpvtv      32.84    33.77    16.35    32.73
vpvts       5.82     6.07     2.99     6.38
vpvpv      32.87    33.84    16.54    32.85
vtvtv      32.82    33.75    16.84    35.97
vsumr      72.03    72.28    72.20    72.04
vdotr      72.05    73.22    72.42    72.04
vbor      205.24   381.18    99.80   372.05

I apologize for the multiple e-mails with a long list of numbers, but I
think that this was worth it (and I did not want to be unfair to the
clang developers).

 -Hal

> 
> Here are improved results where the correct (and default)
> vector-register size was used.
> 
> Loop       llvm-v   llvm     gcc-v    gcc
> -------------------------------------------
> S000        9.09     9.49     4.55    10.04
> S111        7.28     7.37     7.68     7.83
> S1111      13.78    14.48    16.14    16.30
> S112       16.67    17.41    16.54    17.52
> S1112      13.12    14.21    14.83    14.84
> S113       22.12    22.88    22.05    22.05
> S1113      11.06    11.42    11.03    11.01
> S114       13.23    13.75    13.53    13.48
> S115       32.76    33.24    49.98    49.99
> S1115      13.68    14.18    13.65    13.66
> S116       47.42    49.40    49.54    48.11
> S118       10.84    11.26    10.79    10.50
> S119        8.74     9.07    11.83    11.82
> S1119       8.81     9.14     4.31    11.87
> S121       17.28    18.78    14.84    17.31
> S122        7.53     7.54     6.11     6.11
> S123        6.90     7.38     7.42     7.41
> S124        9.60     9.77     9.42     9.33
> S125        6.92     7.22     4.67     7.81
> S126        2.34     2.53     2.57     2.37
> S127       12.19    12.97     7.06    14.50
> S128       11.74    12.43    12.42    11.52
> S131       28.75    29.91    25.17    28.94
> S132       17.04    17.04    15.53    21.03
> S141       12.28    12.26    12.38    12.05
> S151       28.80    29.43    24.89    28.95
> S152       15.54    16.03    11.19    15.63
> S161        6.00     6.06     5.52     5.46
> S1161      14.39    14.40     8.80     8.79
> S162        8.19     9.05     5.36     8.18
> S171       15.41     7.94     2.81     5.70
> S172        5.71     5.89     2.75     5.70
> S173       30.31    30.92    18.15    30.13
> S174       30.18    31.66    18.51    30.16
> S175        5.78     6.18     4.94     5.77
> S176        5.59     5.83     4.41     7.65
> S211       16.27    17.14    16.82    16.38
> S212       13.21    14.28    13.34    13.18
> S1213      12.81    13.46    12.80    12.43
> S221       10.86    11.09     8.65     8.63
> S1221       5.72     6.04     5.40     6.05
> S222        6.02     6.26     5.70     5.72
> S231       22.33    22.94    22.36    22.11
> S232        6.88     6.88     6.89     6.89
> S1232      15.30    15.34    15.05    15.10
> S233       55.38    58.55    54.21    49.56
> S2233      27.08    29.77    29.68    28.40
> S235       44.00    44.92    46.94    43.93
> S241       31.09    31.35    32.53    31.01
> S242        7.19     7.20     7.20     7.20
> S243       16.52    17.09    17.69    16.84
> S244       14.45    14.83    16.91    16.82
> S1244      14.71    14.83    14.77    14.40
> S2244      10.04    10.62    10.40    10.06
> S251       34.15    35.75    19.70    34.38
> S1251      55.23    57.84    41.77    56.11
> S2251      15.73    15.87    17.02    15.70
> S3251      15.66    16.21    19.60    15.34
> S252        6.18     6.32     7.72     7.26
> S253       11.14    11.38    14.40    14.40
> S254       18.41    18.70    28.23    28.06
> S255        5.93     6.09     9.96     9.95
> S256        3.08     3.42     3.10     3.09
> S257        2.13     2.25     2.21     2.20
> S258        1.79     1.82     1.84     1.84
> S261       12.00    12.08    10.98    10.95
> S271       32.82    33.04    33.25    33.01
> S272       14.98    15.82    15.39    15.26
> S273       13.92    14.04    16.86    16.80
> S274       17.83    18.31    18.15    17.89
> S275        2.92     3.02     3.36     2.98
> S2275      32.80    33.50     8.97    33.60
> S276       39.43    39.44    40.80    40.55
> S277        4.80     4.80     4.81     4.80
> S278       14.41    14.42    14.70    14.66
> S279        8.03     8.29     7.25     7.27
> S1279       9.71    10.06     9.34     9.25
> S2710       7.71     8.04     7.86     7.56
> S2711      35.53    35.55    36.56    36.00
> S2712      32.94    33.17    34.24    33.47
> S281       10.79    11.09    12.46    12.02
> S1281      79.13    77.55    57.78    68.06
> S291       11.80    11.78    14.03    14.03
> S292        7.77     7.78     9.94     9.96
> S293       15.50    15.87    19.32    19.33
> S2101       2.56     2.58     2.59     2.60
> S2102      16.71    17.53    16.68    16.75
> S2111       5.60     5.60     5.85     5.85
> S311       72.03    72.03    72.23    72.03
> S31111      7.49     6.00     6.00     6.00
> S312       96.04    96.04    96.05    96.03
> S313       36.02    36.13    36.03    36.02
> S314       36.01    36.07    74.67    72.42
> S315        8.96     8.99     9.35     9.30
> S316       36.02    36.06    72.08    74.87
> S317      444.93   444.94   451.82   451.78
> S318        9.05     9.07     7.30     7.30
> S319       34.54    36.53    34.42    34.19
> S3110       8.51     8.57     4.11     4.11
> S13110      5.75     5.77    12.12    12.12
> S3111       3.60     3.62     3.60     3.60
> S3112       7.19     7.30     7.21     7.20
> S3113      35.13    35.47    60.21    60.20
> S321       16.79    16.81    16.80    16.80
> S322       12.42    12.60    12.60    12.60
> S323       10.86    11.02     8.48     8.51
> S331        4.23     4.23     7.20     7.20
> S332        7.20     7.21     5.21     5.31
> S341        4.79     4.85     7.23     7.20
> S342        6.01     6.09     7.25     7.20
> S343        2.04     2.06     2.16     2.01
> S351       46.61    47.34    21.82    46.46
> S1351      49.28    50.35    33.68    49.06
> S352       57.65    58.04    57.68    57.64
> S353        8.21     8.38     8.34     8.19
> S421       42.94    43.34    20.62    22.46
> S1421      25.15    25.81    15.85    24.76
> S422       87.39    87.53    79.22    78.99
> S423      155.01   155.29   154.56   154.38
> S424       36.51    37.51    11.42    22.36
> S431       57.10    60.66    27.59    57.16
> S441       14.04    13.29    12.88    12.81
> S442        6.00     6.00     6.96     6.90
> S443       17.28    17.77    17.15    16.95
> S451       48.92    49.08    49.03    49.14
> S452       42.98    39.32    14.64    96.03
> S453       28.05    28.06    14.60    14.40
> S471        8.24     8.65     8.39     8.43
> S481       10.88    11.15    12.04    12.00
> S482        9.21     9.31     9.19     9.17
> S491       11.26    11.38    11.37    11.28
> S4112       8.21     8.36     9.13     8.94
> S4113       8.65     8.81     8.86     8.85
> S4114      11.82    12.15    12.18    11.77
> S4115       8.28     8.46     8.95     8.59
> S4116       3.22     3.23     6.02     5.94
> S4117      13.95     9.61    10.16     9.98
> S4121       8.21     8.26     4.04     8.17
> va         28.46    28.58    23.58    48.46
> vag        12.35    12.36    13.58    13.20
> vas        13.45    13.49    13.03    12.47
> vif         4.55     4.57     5.06     4.92
> vpv        57.08    57.22    28.28    57.24
> vtv        57.81    57.83    28.40    57.63
> vpvtv      32.82    32.84    16.35    32.73
> vpvts       5.82     5.83     2.99     6.38
> vpvpv      32.87    32.89    16.54    32.85
> vtvtv      32.82    32.80    16.84    35.97
> vsumr      72.04    72.03    72.20    72.04
> vdotr      72.06    72.05    72.42    72.04
> vbor      205.24   380.81    99.80   372.05
> 
>  -Hal
> 
> > > 
> > > Loop       llvm-v   llvm     gcc-v    gcc
> > > -------------------------------------------
> > > S000        9.59     9.49     4.55    10.04
> > > S111        7.67     7.37     7.68     7.83
> > > S1111      13.98    14.48    16.14    16.30
> > > S112       17.43    17.41    16.54    17.52
> > > S1112      13.87    14.21    14.83    14.84
> > > S113       22.97    22.88    22.05    22.05
> > > S1113      11.46    11.42    11.03    11.01
> > > S114       13.47    13.75    13.53    13.48
> > > S115       33.06    33.24    49.98    49.99
> > > S1115      13.91    14.18    13.65    13.66
> > > S116       48.74    49.40    49.54    48.11
> > > S118       11.04    11.26    10.79    10.50
> > > S119        8.97     9.07    11.83    11.82
> > > S1119       9.04     9.14     4.31    11.87
> > > S121       18.06    18.78    14.84    17.31
> > > S122        7.58     7.54     6.11     6.11
> > > S123        7.02     7.38     7.42     7.41
> > > S124        9.62     9.77     9.42     9.33
> > > S125        7.14     7.22     4.67     7.81
> > > S126        2.32     2.53     2.57     2.37
> > > S127       12.87    12.97     7.06    14.50
> > > S128       12.58    12.43    12.42    11.52
> > > S131       29.91    29.91    25.17    28.94
> > > S132       17.04    17.04    15.53    21.03
> > > S141       12.59    12.26    12.38    12.05
> > > S151       28.92    29.43    24.89    28.95
> > > S152       15.68    16.03    11.19    15.63
> > > S161        6.06     6.06     5.52     5.46
> > > S1161      14.46    14.40     8.80     8.79
> > > S162        8.31     9.05     5.36     8.18
> > > S171       15.47     7.94     2.81     5.70
> > > S172        5.92     5.89     2.75     5.70
> > > S173       31.59    30.92    18.15    30.13
> > > S174       31.16    31.66    18.51    30.16
> > > S175        5.80     6.18     4.94     5.77
> > > S176        5.69     5.83     4.41     7.65
> > > S211       16.56    17.14    16.82    16.38
> > > S212       13.46    14.28    13.34    13.18
> > > S1213      13.12    13.46    12.80    12.43
> > > S221       10.88    11.09     8.65     8.63
> > > S1221       5.80     6.04     5.40     6.05
> > > S222        6.01     6.26     5.70     5.72
> > > S231       23.78    22.94    22.36    22.11
> > > S232        6.88     6.88     6.89     6.89
> > > S1232      16.00    15.34    15.05    15.10
> > > S233       57.48    58.55    54.21    49.56
> > > S2233      27.65    29.77    29.68    28.40
> > > S235       46.40    44.92    46.94    43.93
> > > S241       31.62    31.35    32.53    31.01
> > > S242        7.20     7.20     7.20     7.20
> > > S243       16.78    17.09    17.69    16.84
> > > S244       14.64    14.83    16.91    16.82
> > > S1244      14.98    14.83    14.77    14.40
> > > S2244      10.47    10.62    10.40    10.06
> > > S251       35.10    35.75    19.70    34.38
> > > S1251      56.65    57.84    41.77    56.11
> > > S2251      15.96    15.87    17.02    15.70
> > > S3251      16.41    16.21    19.60    15.34
> > > S252        7.24     6.32     7.72     7.26
> > > S253       12.55    11.38    14.40    14.40
> > > S254       19.08    18.70    28.23    28.06
> > > S255        5.94     6.09     9.96     9.95
> > > S256        3.14     3.42     3.10     3.09
> > > S257        2.18     2.25     2.21     2.20
> > > S258        1.80     1.82     1.84     1.84
> > > S261       12.00    12.08    10.98    10.95
> > > S271       32.93    33.04    33.25    33.01
> > > S272       15.48    15.82    15.39    15.26
> > > S273       13.99    14.04    16.86    16.80
> > > S274       18.38    18.31    18.15    17.89
> > > S275        3.02     3.02     3.36     2.98
> > > S2275      33.71    33.50     8.97    33.60
> > > S276       39.52    39.44    40.80    40.55
> > > S277        4.81     4.80     4.81     4.80
> > > S278       14.43    14.42    14.70    14.66
> > > S279        8.10     8.29     7.25     7.27
> > > S1279       9.77    10.06     9.34     9.25
> > > S2710       7.85     8.04     7.86     7.56
> > > S2711      35.54    35.55    36.56    36.00
> > > S2712      33.16    33.17    34.24    33.47
> > > S281       10.97    11.09    12.46    12.02
> > > S1281      79.37    77.55    57.78    68.06
> > > S291       11.94    11.78    14.03    14.03
> > > S292        7.88     7.78     9.94     9.96
> > > S293       15.90    15.87    19.32    19.33
> > > S2101       2.59     2.58     2.59     2.60
> > > S2102      17.63    17.53    16.68    16.75
> > > S2111       5.63     5.60     5.85     5.85
> > > S311       72.07    72.03    72.23    72.03
> > > S31111      7.49     6.00     6.00     6.00
> > > S312       96.06    96.04    96.05    96.03
> > > S313       36.50    36.13    36.03    36.02
> > > S314       36.10    36.07    74.67    72.42
> > > S315        9.00     8.99     9.35     9.30
> > > S316       36.11    36.06    72.08    74.87
> > > S317      444.92   444.94   451.82   451.78
> > > S318        9.04     9.07     7.30     7.30
> > > S319       34.76    36.53    34.42    34.19
> > > S3110       8.53     8.57     4.11     4.11
> > > S13110      5.76     5.77    12.12    12.12
> > > S3111       3.60     3.62     3.60     3.60
> > > S3112       7.20     7.30     7.21     7.20
> > > S3113      35.12    35.47    60.21    60.20
> > > S321       16.81    16.81    16.80    16.80
> > > S322       12.42    12.60    12.60    12.60
> > > S323       10.93    11.02     8.48     8.51
> > > S331        4.23     4.23     7.20     7.20
> > > S332        7.21     7.21     5.21     5.31
> > > S341        4.74     4.85     7.23     7.20
> > > S342        6.02     6.09     7.25     7.20
> > > S343        2.14     2.06     2.16     2.01
> > > S351       49.26    47.34    21.82    46.46
> > > S1351      50.85    50.35    33.68    49.06
> > > S352       58.14    58.04    57.68    57.64
> > > S353        8.35     8.38     8.34     8.19
> > > S421       43.13    43.34    20.62    22.46
> > > S1421      25.25    25.81    15.85    24.76
> > > S422       88.36    87.53    79.22    78.99
> > > S423      155.13   155.29   154.56   154.38
> > > S424       37.11    37.51    11.42    22.36
> > > S431       58.22    60.66    27.59    57.16
> > > S441       14.05    13.29    12.88    12.81
> > > S442        6.08     6.00     6.96     6.90
> > > S443       17.60    17.77    17.15    16.95
> > > S451       48.95    49.08    49.03    49.14
> > > S452       42.98    39.32    14.64    96.03
> > > S453       28.06    28.06    14.60    14.40
> > > S471        8.53     8.65     8.39     8.43
> > > S481       10.98    11.15    12.04    12.00
> > > S482        9.31     9.31     9.19     9.17
> > > S491       11.54    11.38    11.37    11.28
> > > S4112       8.21     8.36     9.13     8.94
> > > S4113       8.77     8.81     8.86     8.85
> > > S4114      12.32    12.15    12.18    11.77
> > > S4115       8.48     8.46     8.95     8.59
> > > S4116       3.21     3.23     6.02     5.94
> > > S4117      14.08     9.61    10.16     9.98
> > > S4121       8.53     8.26     4.04     8.17
> > > va         30.09    28.58    23.58    48.46
> > > vag        12.35    12.36    13.58    13.20
> > > vas        13.74    13.49    13.03    12.47
> > > vif         4.49     4.57     5.06     4.92
> > > vpv        58.59    57.22    28.28    57.24
> > > vtv        59.15    57.83    28.40    57.63
> > > vpvtv      33.18    32.84    16.35    32.73
> > > vpvts       5.99     5.83     2.99     6.38
> > > vpvpv      33.25    32.89    16.54    32.85
> > > vtvtv      32.83    32.80    16.84    35.97
> > > vsumr      72.03    72.03    72.20    72.04
> > > vdotr      72.05    72.05    72.42    72.04
> > > vbor      205.22   380.81    99.80   372.05
> > > 
> > > I've yet to go through these in detail (they just finished running 5
> > > minutes ago). But for the curious (and I've had several requests for
> > > benchmarks), here you go. There is obviously more work to do.
> > > 
> > >  -Hal
> > > 
> > > On Fri, 2011-10-28 at 14:30 +0200, Ralf Karrenberg wrote:
> > > > Hi Hal,
> > > > 
> > > > those numbers look very promising, great work! :)
> > > > 
> > > > Best,
> > > > Ralf
> > > > 
> > > > ----- Original Message -----
> > > > > From: "Hal Finkel" <hfinkel at anl.gov>
> > > > > To: "Bruno Cardoso Lopes" <bruno.cardoso at gmail.com>
> > > > > Cc: llvm-commits at cs.uiuc.edu
> > > > > Sent: Freitag, 28. Oktober 2011 13:50:00
> > > > > Subject: Re: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
> > > > > 
> > > > > Bruno, et al.,
> > > > > 
> > > > > I've attached a new version of the patch that contains improvements
> > > > > (and
> > > > > a critical bug fix [the code output is not more right, but the pass
> > > > > in
> > > > > the older patch would crash in certain cases and now does not])
> > > > > compared
> > > > > to previous versions that I've posted.
> > > > > 
> > > > > First, these are preliminary results because I did not do the things
> > > > > necessary to make them real (explicitly quiet the machine, bind the
> > > > > processes to one cpu, etc.). But they should be good enough for
> > > > > discussion.
> > > > > 
> > > > > I'm using LLVM head r143101, with the attached patch applied, and
> > > > > clang
> > > > > head r143100 on an x86_64 machine (some kind of Intel Xeon). For the
> > > > > gcc
> > > > > comparison, I'm using build Ubuntu 4.4.3-4ubuntu5. gcc was run -O3
> > > > > without any other optimization flags. opt was run -vectorize
> > > > > -unroll-allow-partial -O3 with no other optimization flags (the patch
> > > > > adds the -vectorize option). llc was just given -O3.
> > > > > 
> > > > > It is not difficult to construct an example in which vectorization
> > > > > would
> > > > > be useful: take a loop that does more computation than load/stores,
> > > > > and
> > > > > (partially) unroll it. Here is a simple case:
> > > > > 
> > > > > #define ITER 5000
> > > > > #define NUM 200
> > > > > double a[NUM][NUM];
> > > > > double b[NUM][NUM];
> > > > > 
> > > > > ...
> > > > > 
> > > > > int main()
> > > > > {
> > > > > ...
> > > > > 
> > > > >   for (int i = 0; i < ITER; ++i) {
> > > > >     for (int x = 0; x < NUM; ++x)
> > > > >     for (int y = 0; y < NUM; ++y) {
> > > > >       double v = a[x][y], w = b[x][y];
> > > > >       double z1 = v*w;
> > > > >       double z2 = v+w;
> > > > >       double z3 = z1*z2;
> > > > >       double z4 = z3+v;
> > > > >       double z5 = z2+w;
> > > > >       double z6 = z4*z5;
> > > > >       double z7 = z4+z5;
> > > > >       a[x][y] = v*v-z6;
> > > > >       b[x][y] = w-z7;
> > > > >     }
> > > > >   }
> > > > > 
> > > > >  ...
> > > > > 
> > > > >   return 0;
> > > > > }
> > > > > 
> > > > > Results:
> > > > > gcc -03: 0m1.790s
> > > > > llvm -vectorize: 0m2.360s
> > > > > llvm: 0m2.780s
> > > > > gcc -fno-tree-vectorize: 0m2.810s
> > > > > (these are the user times after I've run enough for the times to
> > > > > settle
> > > > > to three decimal places)
> > > > > 
> > > > > So the vectorization gives a ~15% improvement in the running time.
> > > > > gcc's
> > > > > vectorization still does a much better job, however (yielding an ~36%
> > > > > improvement). So there is still work to do ;)
> > > > > 
> > > > > Additionally, I've checked the autovectorization on some classic
> > > > > numerical benchmarks from netlib. On these benchmarks, clang/llvm
> > > > > already do a good job compared to gcc (gcc is only about 10% better,
> > > > > and
> > > > > this is true regardless of whether gcc's vectorization is on or off).
> > > > > For these cases, autovectorization provides an insignificant speedup
> > > > > in
> > > > > most cases (but does not tend to make things worse, just not really
> > > > > any
> > > > > better either). Because gcc's vectorization also did not really help
> > > > > gcc
> > > > > in these cases, I'm not surprised. A good collection of these is
> > > > > available here:
> > > > > http://www.roylongbottom.org.uk/classic_benchmarks.tar.gz
> > > > > 
> > > > > I've yet to run the test suite using the pass to validate it. That is
> > > > > something that I plan to do. Actually, the "Livermore Loops" test in
> > > > > the
> > > > > aforementioned archive contains checksums to validate the results,
> > > > > and
> > > > > it looks like 1 or 2 of the loop results are wrong with vectorization
> > > > > turned on, so I'll have to investigate that.
> > > > > 
> > > > >  -Hal
> > > > > 
> > > > > On Wed, 2011-10-26 at 18:49 -0200, Bruno Cardoso Lopes wrote:
> > > > > > Hi Hal,
> > > > > > 
> > > > > > On Fri, Oct 21, 2011 at 7:04 PM, Hal Finkel <hfinkel at anl.gov>
> > > > > > wrote:
> > > > > > > I've attached an initial version of a basic-block
> > > > > > > autovectorization
> > > > > > > pass. It works by searching a basic block for pairable
> > > > > > > (independent)
> > > > > > > instructions, and, using a chain-seeking heuristic, selects
> > > > > > > pairings
> > > > > > > likely to provide an overall speedup (if such pairings can be
> > > > > > > found).
> > > > > > > The selected pairs are then fused and, if necessary, other
> > > > > > > instructions
> > > > > > > are moved in order to maintain data-flow consistency. This works
> > > > > > > only
> > > > > > > within one basic block, but can do loop vectorization in
> > > > > > > combination
> > > > > > > with (partial) unrolling. The basic idea was inspired by the
> > > > > > > Vienna MAP
> > > > > > > Vectorizor, which has been used to vectorize FFT kernels, but the
> > > > > > > algorithm used here is different.
> > > > > > >
> > > > > > > To try it, use -bb-vectorize with opt. There are a few options:
> > > > > > > -bb-vectorize-req-chain-depth: default: 3 -- The depth of the
> > > > > > > chain of
> > > > > > > instruction pairs necessary in order to consider the pairs that
> > > > > > > compose
> > > > > > > the chain worthy of vectorization.
> > > > > > > -bb-vectorize-vector-bits: default: 128 -- The size of the target
> > > > > > > vector
> > > > > > > registers
> > > > > > > -bb-vectorize-no-ints -- Don't consider integer instructions
> > > > > > > -bb-vectorize-no-floats -- Don't consider floating-point
> > > > > > > instructions
> > > > > > >
> > > > > > > The vectorizor generates a lot of insert_element/extract_element
> > > > > > > pairs;
> > > > > > > The assumption is that other passes will turn these into shuffles
> > > > > > > when
> > > > > > > possible (it looks like some work is necessary here). It will
> > > > > > > also
> > > > > > > vectorize vector instructions, and generates shuffles in this
> > > > > > > case
> > > > > > > (again, other passes should combine these as appropriate).
> > > > > > >
> > > > > > > Currently, it does not fuse load or store instructions, but that
> > > > > > > is a
> > > > > > > feature that I'd like to add. Of course, alignment information is
> > > > > > > an
> > > > > > > issue for load/store vectorization (or maybe I should just fuse
> > > > > > > them
> > > > > > > anyway and let isel deal with unaligned cases?).
> > > > > > >
> > > > > > > Also, support needs to be added for fusing known intrinsics (fma,
> > > > > > > etc.),
> > > > > > > and, as has been discussed on llvmdev, we should add some
> > > > > > > intrinsics to
> > > > > > > allow the generation of addsub-type instructions.
> > > > > > >
> > > > > > > I've included a few tests, but it needs more. Please review (I'll
> > > > > > > commit
> > > > > > > if and when everyone is happy).
> > > > > > >
> > > > > > > Thanks in advance,
> > > > > > > Hal
> > > > > > >
> > > > > > > P.S. There is another option (not so useful right now, but could
> > > > > > > be):
> > > > > > > -bb-vectorize-fast-dep -- Don't do a full inter-instruction
> > > > > > > dependency
> > > > > > > analysis; instead stop looking for instruction pairs after the
> > > > > > > first use
> > > > > > > of an instruction's value. [This makes the pass faster, but would
> > > > > > > require a data-dependence-based reordering pass in order to be
> > > > > > > effective].
> > > > > > 
> > > > > > Cool! :)
> > > > > > Have you run this pass with any benchmark or the llvm testsuite?
> > > > > > Does
> > > > > > it presents any regression?
> > > > > > Do you have any performance results?
> > > > > > Cheers,
> > > > > > 
> > > > > 
> > > > > --
> > > > > Hal Finkel
> > > > > Postdoctoral Appointee
> > > > > Leadership Computing Facility
> > > > > Argonne National Laboratory
> > > > > 
> > > > > _______________________________________________
> > > > > llvm-commits mailing list
> > > > > llvm-commits at cs.uiuc.edu
> > > > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> > > > > 
> > > 
> > > _______________________________________________
> > > llvm-commits mailing list
> > > llvm-commits at cs.uiuc.edu
> > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> > 
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From geek4civic at gmail.com  Sat Oct 29 18:42:14 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Sat, 29 Oct 2011 23:42:14 -0000
Subject: [llvm-commits] [llvm] r143300 - /llvm/trunk/CREDITS.TXT
Message-ID: <20111029234214.C44BF3524076@llvm.org>

Author: chapuni
Date: Sat Oct 29 18:42:14 2011
New Revision: 143300

URL: http://llvm.org/viewvc/llvm-project?rev=143300&view=rev
Log:
CREDITS.TXT: Add a line. (test commit)

Modified:
    llvm/trunk/CREDITS.TXT

Modified: llvm/trunk/CREDITS.TXT
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=143300&r1=143299&r2=143300&view=diff
==============================================================================
--- llvm/trunk/CREDITS.TXT (original)
+++ llvm/trunk/CREDITS.TXT Sat Oct 29 18:42:14 2011
@@ -267,6 +267,7 @@
 E: geek4civic at gmail.com
 E: chapuni at hf.rim.or.jp
 D: Cygwin and MinGW support.
+D: Win32 tweaks.
 S: Yokohama, Japan
 
 N: Edward O'Callaghan



From isanbard at gmail.com  Sat Oct 29 18:49:52 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Sat, 29 Oct 2011 23:49:52 -0000
Subject: [llvm-commits] [llvm] r143302 -
	/llvm/trunk/utils/release/test-release.sh
Message-ID: <20111029234952.5999F3524076@llvm.org>

Author: void
Date: Sat Oct 29 18:49:52 2011
New Revision: 143302

URL: http://llvm.org/viewvc/llvm-project?rev=143302&view=rev
Log:
Do a relative path ln command instead of an absolute path one. Some people strangely enough have different directory layouts...

Modified:
    llvm/trunk/utils/release/test-release.sh

Modified: llvm/trunk/utils/release/test-release.sh
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/test-release.sh?rev=143302&r1=143301&r2=143302&view=diff
==============================================================================
--- llvm/trunk/utils/release/test-release.sh (original)
+++ llvm/trunk/utils/release/test-release.sh Sat Oct 29 18:49:52 2011
@@ -199,11 +199,11 @@
     echo "# Creating symlinks"
     cd $BuildDir/llvm.src/tools
     if [ ! -h clang ]; then
-        ln -s $BuildDir/cfe.src clang
+        ln -s ../../cfe.src clang
     fi
     cd $BuildDir/llvm.src/projects
     if [ ! -h llvm-test ]; then
-        ln -s $BuildDir/test-suite.src llvm-test
+        ln -s ../../test-suite.src llvm-test
     fi
     cd $BuildDir
 }



From rdivacky at freebsd.org  Sun Oct 30 02:49:04 2011
From: rdivacky at freebsd.org (Roman Divacky)
Date: Sun, 30 Oct 2011 07:49:04 -0000
Subject: [llvm-commits] [llvm] r143306 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111030074904.A1F3E3524001@llvm.org>

Author: rdivacky
Date: Sun Oct 30 02:49:04 2011
New Revision: 143306

URL: http://llvm.org/viewvc/llvm-project?rev=143306&view=rev
Log:
Update on PPC32.


Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=143306&r1=143305&r2=143306&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Sun Oct 30 02:49:04 2011
@@ -926,6 +926,9 @@
 <a name="OtherTS">Other Target Specific Improvements</a>
 </h3>
 
+<p>PPC32/ELF va_arg was implemented.</p>
+<p>PPC32 initial support for .o file writing was implemented.</p>
+
 <div>
 
 <ul>
@@ -1174,8 +1177,7 @@
 <div>
 
 <ul>
-  <li>The Linux PPC32/ABI support needs testing for the interpreter and static
-      compilation, and lacks support for debug information.</li>
+  <li>The PPC32/ELF support lacks PIC support.</li>
 </ul>
 
 </div>



From nadav.rotem at intel.com  Sun Oct 30 03:07:50 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Sun, 30 Oct 2011 08:07:50 -0000
Subject: [llvm-commits] [llvm] r143307 -
	/llvm/trunk/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
Message-ID: <20111030080750.C06DB3524001@llvm.org>

Author: nadav
Date: Sun Oct 30 03:07:50 2011
New Revision: 143307

URL: http://llvm.org/viewvc/llvm-project?rev=143307&view=rev
Log:
Stabilize the test by specifying an exact cpu target

Modified:
    llvm/trunk/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll

Modified: llvm/trunk/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll?rev=143307&r1=143306&r2=143307&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll Sun Oct 30 03:07:50 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-linux -mattr=+mmx | grep movd | count 2
+; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 -mattr=+mmx | grep movd | count 2
 
 define i64 @a(i32 %a, i32 %b) nounwind readnone {
 entry:



From benny.kra at googlemail.com  Sun Oct 30 03:39:55 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Sun, 30 Oct 2011 08:39:55 -0000
Subject: [llvm-commits] [llvm] r143308 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <20111030083955.BB91F3524002@llvm.org>

Author: d0k
Date: Sun Oct 30 03:39:55 2011
New Revision: 143308

URL: http://llvm.org/viewvc/llvm-project?rev=143308&view=rev
Log:
Silence compiler warning.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=143308&r1=143307&r2=143308&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Oct 30 03:39:55 2011
@@ -6988,14 +6988,14 @@
                                  DAG.getConstant(0, InScalarTy);
 
     unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements();
-    SmallVector<SDValue,8> Ops(NewBVElems , Filler);
+    SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
 
     // Populate the new build_vector
     for (unsigned i=0; i < N->getNumOperands(); ++i) {
       SDValue Cast = N->getOperand(i);
-      assert(Cast.getOpcode() == ISD::ANY_EXTEND ||
-             Cast.getOpcode() == ISD::ZERO_EXTEND ||
-             Cast.getOpcode() == ISD::UNDEF && "Invalid cast opcode");
+      assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
+              Cast.getOpcode() == ISD::ZERO_EXTEND ||
+              Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
       SDValue In;
       if (Cast.getOpcode() == ISD::UNDEF)
         In = DAG.getUNDEF(InScalarTy);



From nadav.rotem at intel.com  Sun Oct 30 08:24:22 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Sun, 30 Oct 2011 13:24:22 -0000
Subject: [llvm-commits] [llvm] r143311 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-10-30-padd.ll
 test/CodeGen/X86/x86-shifts.ll
Message-ID: <20111030132422.6686B3524001@llvm.org>

Author: nadav
Date: Sun Oct 30 08:24:22 2011
New Revision: 143311

URL: http://llvm.org/viewvc/llvm-project?rev=143311&view=rev
Log:

Fix pr11266.

On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.


Added:
    llvm/trunk/test/CodeGen/X86/2011-10-30-padd.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/x86-shifts.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=143311&r1=143310&r2=143311&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Oct 30 08:24:22 2011
@@ -13042,7 +13042,8 @@
 
   // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
   // since the result of setcc_c is all zero's or all ones.
-  if (N1C && N0.getOpcode() == ISD::AND &&
+  if (VT.isInteger() && !VT.isVector() &&
+      N1C && N0.getOpcode() == ISD::AND &&
       N0.getOperand(1).getOpcode() == ISD::Constant) {
     SDValue N00 = N0.getOperand(0);
     if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
@@ -13058,6 +13059,22 @@
     }
   }
 
+
+  // Hardware support for vector shifts is sparse which makes us scalarize the
+  // vector operations in many cases. Also, on sandybridge ADD is faster than
+  // shl.
+  // (shl V, 1) -> add V,V
+  if (isSplatVector(N1.getNode())) {
+    assert(N0.getValueType().isVector() && "Invalid vector shift type");
+    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
+    // We shift all of the values by one. In many cases we do not have
+    // hardware support for this operation. This is better expressed as an ADD
+    // of two values.
+    if (N1C && (1 == N1C->getZExtValue())) {
+      return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
+    }
+  }
+
   return SDValue();
 }
 
@@ -13066,9 +13083,10 @@
 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
                                    const X86Subtarget *Subtarget) {
   EVT VT = N->getValueType(0);
-  if (!VT.isVector() && VT.isInteger() &&
-      N->getOpcode() == ISD::SHL)
-    return PerformSHLCombine(N, DAG);
+  if (N->getOpcode() == ISD::SHL) {
+    SDValue V = PerformSHLCombine(N, DAG);
+    if (V.getNode()) return V;
+  }
 
   // On X86 with SSE2 support, we can transform this to a vector shift if
   // all elements are shifted by the same amount.  We can't do this in legalize

Added: llvm/trunk/test/CodeGen/X86/2011-10-30-padd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-30-padd.ll?rev=143311&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-10-30-padd.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2011-10-30-padd.ll Sun Oct 30 08:24:22 2011
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
+
+;CHECK: addXX_test
+;CHECK: padd
+;CHECK: ret
+
+
+define <16 x i8> @addXX_test(<16 x i8> %a) {
+      %b = add <16 x i8> %a, %a
+      ret <16 x i8> %b
+}
+
+;CHECK: instcombine_test
+;CHECK: padd
+;CHECK: ret
+define <16 x i8> @instcombine_test(<16 x i8> %a) {
+  %b = shl <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %b
+}
+

Modified: llvm/trunk/test/CodeGen/X86/x86-shifts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-shifts.ll?rev=143311&r1=143310&r2=143311&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-shifts.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-shifts.ll Sun Oct 30 08:24:22 2011
@@ -6,8 +6,9 @@
 define <4 x i32> @shl4(<4 x i32> %A) nounwind {
 entry:
 ; CHECK:      shl4
+; CHECK:      padd
 ; CHECK:      pslld
-; CHECK-NEXT: pslld
+; CHECK:      ret
   %B = shl <4 x i32> %A,  < i32 2, i32 2, i32 2, i32 2>
   %C = shl <4 x i32> %A,  < i32 1, i32 1, i32 1, i32 1>
   %K = xor <4 x i32> %B, %C
@@ -19,6 +20,7 @@
 ; CHECK:      shr4
 ; CHECK:      psrld
 ; CHECK-NEXT: psrld
+; CHECK:      ret
   %B = lshr <4 x i32> %A,  < i32 2, i32 2, i32 2, i32 2>
   %C = lshr <4 x i32> %A,  < i32 1, i32 1, i32 1, i32 1>
   %K = xor <4 x i32> %B, %C
@@ -30,6 +32,7 @@
 ; CHECK:      sra4
 ; CHECK:      psrad
 ; CHECK-NEXT: psrad
+; CHECK:      ret
   %B = ashr <4 x i32> %A,  < i32 2, i32 2, i32 2, i32 2>
   %C = ashr <4 x i32> %A,  < i32 1, i32 1, i32 1, i32 1>
   %K = xor <4 x i32> %B, %C
@@ -41,6 +44,7 @@
 ; CHECK:      shl2
 ; CHECK:      psllq
 ; CHECK-NEXT: psllq
+; CHECK:      ret
   %B = shl <2 x i64> %A,  < i64 2, i64 2>
   %C = shl <2 x i64> %A,  < i64 9, i64 9>
   %K = xor <2 x i64> %B, %C
@@ -52,6 +56,7 @@
 ; CHECK:      shr2
 ; CHECK:      psrlq
 ; CHECK-NEXT: psrlq
+; CHECK:      ret
   %B = lshr <2 x i64> %A,  < i64 8, i64 8>
   %C = lshr <2 x i64> %A,  < i64 1, i64 1>
   %K = xor <2 x i64> %B, %C
@@ -62,8 +67,9 @@
 define <8 x i16> @shl8(<8 x i16> %A) nounwind {
 entry:
 ; CHECK:      shl8
+; CHECK:      padd
 ; CHECK:      psllw
-; CHECK-NEXT: psllw
+; CHECK:      ret
   %B = shl <8 x i16> %A,  < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
   %C = shl <8 x i16> %A,  < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %K = xor <8 x i16> %B, %C
@@ -75,6 +81,7 @@
 ; CHECK:      shr8
 ; CHECK:      psrlw
 ; CHECK-NEXT: psrlw
+; CHECK:      ret
   %B = lshr <8 x i16> %A,  < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
   %C = lshr <8 x i16> %A,  < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %K = xor <8 x i16> %B, %C
@@ -86,6 +93,7 @@
 ; CHECK:      sra8
 ; CHECK:      psraw
 ; CHECK-NEXT: psraw
+; CHECK:      ret
   %B = ashr <8 x i16> %A,  < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
   %C = ashr <8 x i16> %A,  < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %K = xor <8 x i16> %B, %C
@@ -100,6 +108,7 @@
 ; CHECK: sll8_nosplat
 ; CHECK-NOT: psll
 ; CHECK-NOT: psll
+; CHECK:      ret
   %B = shl <8 x i16> %A,  < i16 1, i16 2, i16 3, i16 6, i16 2, i16 2, i16 2, i16 2>
   %C = shl <8 x i16> %A,  < i16 9, i16 7, i16 5, i16 1, i16 4, i16 1, i16 1, i16 1>
   %K = xor <8 x i16> %B, %C
@@ -112,6 +121,7 @@
 ; CHECK: shr2_nosplat
 ; CHECK-NOT:  psrlq
 ; CHECK-NOT:  psrlq
+; CHECK:      ret
   %B = lshr <2 x i64> %A,  < i64 8, i64 1>
   %C = lshr <2 x i64> %A,  < i64 1, i64 0>
   %K = xor <2 x i64> %B, %C
@@ -125,6 +135,7 @@
 entry:
 ; CHECK: shl2_other
 ; CHECK: psllq
+; CHECK: ret
   %B = shl <2 x i32> %A,  < i32 2, i32 2>
   %C = shl <2 x i32> %A,  < i32 9, i32 9>
   %K = xor <2 x i32> %B, %C
@@ -135,6 +146,7 @@
 entry:
 ; CHECK: shr2_other
 ; CHECK: psrlq
+; CHECK: ret
   %B = lshr <2 x i32> %A,  < i32 8, i32 8>
   %C = lshr <2 x i32> %A,  < i32 1, i32 1>
   %K = xor <2 x i32> %B, %C



From craig.topper at gmail.com  Sun Oct 30 12:22:45 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sun, 30 Oct 2011 17:22:45 -0000
Subject: [llvm-commits] [llvm] r143313 - in /llvm/trunk:
 include/llvm/IntrinsicsX86.td test/CodeGen/X86/avx-intrinsics-x86.ll
Message-ID: <20111030172245.9779E3524001@llvm.org>

Author: ctopper
Date: Sun Oct 30 12:22:45 2011
New Revision: 143313

URL: http://llvm.org/viewvc/llvm-project?rev=143313&view=rev
Log:
Fix return type for X86 mpsadbw instrinsic. The instruction takes in a vector of 8-bit integers, but produces a vector of 16-bit integers.

Modified:
    llvm/trunk/include/llvm/IntrinsicsX86.td
    llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll

Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=143313&r1=143312&r2=143313&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Sun Oct 30 12:22:45 2011
@@ -919,7 +919,7 @@
 // Vector sum of absolute differences
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse41_mpsadbw         : GCCBuiltin<"__builtin_ia32_mpsadbw128">,
-          Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty,llvm_i32_ty],
+          Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty,llvm_i32_ty],
                     [IntrNoMem, Commutative]>;
 }
 

Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=143313&r1=143312&r2=143313&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Sun Oct 30 12:22:45 2011
@@ -964,12 +964,12 @@
 declare <2 x i64> @llvm.x86.sse41.movntdqa(i8*) nounwind readonly
 
 
-define <16 x i8> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
+define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
   ; CHECK: vmpsadbw
-  %res = call <16 x i8> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i32 7) ; <<16 x i8>> [#uses=1]
-  ret <16 x i8> %res
+  %res = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i32 7) ; <<8 x i16>> [#uses=1]
+  ret <8 x i16> %res
 }
-declare <16 x i8> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i32) nounwind readnone
+declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i32) nounwind readnone
 
 
 define <8 x i16> @test_x86_sse41_packusdw(<4 x i32> %a0, <4 x i32> %a1) {



From benny.kra at googlemail.com  Sun Oct 30 12:31:22 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Sun, 30 Oct 2011 17:31:22 -0000
Subject: [llvm-commits] [llvm] r143315 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/x86-shifts.ll
Message-ID: <20111030173122.2D29A3524001@llvm.org>

Author: d0k
Date: Sun Oct 30 12:31:21 2011
New Revision: 143315

URL: http://llvm.org/viewvc/llvm-project?rev=143315&view=rev
Log:
X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/x86-shifts.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=143315&r1=143314&r2=143315&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Oct 30 12:31:21 2011
@@ -9929,6 +9929,19 @@
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
       uint64_t ShiftAmt = C->getZExtValue();
 
+      if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) {
+        // Make a large shift.
+        SDValue SHL =
+          DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+                      DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
+                      R, DAG.getConstant(ShiftAmt, MVT::i32));
+        // Zero out the rightmost bits.
+        SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt),
+                                                       MVT::i8));
+        return DAG.getNode(ISD::AND, dl, VT, SHL,
+                           DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
+      }
+
       if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
        return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
                      DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
@@ -9944,6 +9957,19 @@
                      DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
                      R, DAG.getConstant(ShiftAmt, MVT::i32));
 
+      if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) {
+        // Make a large shift.
+        SDValue SRL =
+          DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+                      DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
+                      R, DAG.getConstant(ShiftAmt, MVT::i32));
+        // Zero out the leftmost bits.
+        SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
+                                                       MVT::i8));
+        return DAG.getNode(ISD::AND, dl, VT, SRL,
+                           DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
+      }
+
       if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
        return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
                      DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),

Modified: llvm/trunk/test/CodeGen/X86/x86-shifts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-shifts.ll?rev=143315&r1=143314&r2=143315&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-shifts.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-shifts.ll Sun Oct 30 12:31:21 2011
@@ -152,3 +152,21 @@
   %K = xor <2 x i32> %B, %C
   ret <2 x i32> %K
 }
+
+define <16 x i8> @shl9(<16 x i8> %A) nounwind {
+  %B = shl <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <16 x i8> %B
+; CHECK: shl9:
+; CHECK: psllw $3
+; CHECK: pand
+; CHECK: ret
+}
+
+define <16 x i8> @shr9(<16 x i8> %A) nounwind {
+  %B = lshr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <16 x i8> %B
+; CHECK: shr9:
+; CHECK: psrlw $3
+; CHECK: pand
+; CHECK: ret
+}



From peter at pcc.me.uk  Sun Oct 30 12:46:34 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Sun, 30 Oct 2011 17:46:34 -0000
Subject: [llvm-commits] [llvm] r143316 -
	/llvm/trunk/lib/Linker/LinkModules.cpp
Message-ID: <20111030174634.9BB1F2A6C12C@llvm.org>

Author: pcc
Date: Sun Oct 30 12:46:34 2011
New Revision: 143316

URL: http://llvm.org/viewvc/llvm-project?rev=143316&view=rev
Log:
Teach ModuleLinker::getLinkageResult about materialisable functions

Modified:
    llvm/trunk/lib/Linker/LinkModules.cpp

Modified: llvm/trunk/lib/Linker/LinkModules.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=143316&r1=143315&r2=143316&view=diff
==============================================================================
--- llvm/trunk/lib/Linker/LinkModules.cpp (original)
+++ llvm/trunk/lib/Linker/LinkModules.cpp Sun Oct 30 12:46:34 2011
@@ -446,7 +446,7 @@
   assert(!Src->hasLocalLinkage() &&
          "If Src has internal linkage, Dest shouldn't be set!");
   
-  bool SrcIsDeclaration = Src->isDeclaration();
+  bool SrcIsDeclaration = Src->isDeclaration() && !Src->isMaterializable();
   bool DestIsDeclaration = Dest->isDeclaration();
   
   if (SrcIsDeclaration) {



From peter at pcc.me.uk  Sun Oct 30 12:53:25 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Sun, 30 Oct 2011 17:53:25 +0000
Subject: [llvm-commits] [PATCH] Lazily Link functions
In-Reply-To: <F9BF4DF3-6A0B-45B2-8B47-5E9AA8AF64F2@apple.com>
References: <F9BF4DF3-6A0B-45B2-8B47-5E9AA8AF64F2@apple.com>
Message-ID: <20111030175324.GA18855@pcc.me.uk>

On Wed, Oct 26, 2011 at 04:26:27PM -0700, Tanya Lattner wrote:
> @@ -449,7 +452,7 @@
>    bool SrcIsDeclaration = Src->isDeclaration();
>    bool DestIsDeclaration = Dest->isDeclaration();
>    
> -  if (SrcIsDeclaration) {
> +  if (SrcIsDeclaration && !Src->isMaterializable()) {
>      // If Src is external or if both Src & Dest are external..  Just link the
>      // external globals, we aren't adding anything.
>      if (Src->hasDLLImportLinkage()) {

FYI, I committed a slightly modified version of this part of your
patch as r143316.

Thanks,
-- 
Peter

From craig.topper at gmail.com  Sun Oct 30 13:33:35 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sun, 30 Oct 2011 18:33:35 -0000
Subject: [llvm-commits] [llvm] r143317 -
	/llvm/trunk/include/llvm/IntrinsicsX86.td
Message-ID: <20111030183335.DFFC93524001@llvm.org>

Author: ctopper
Date: Sun Oct 30 13:33:35 2011
New Revision: 143317

URL: http://llvm.org/viewvc/llvm-project?rev=143317&view=rev
Log:
Mark X86 pcmpeq b/w/d intrinsics as being Commutative. pcmpeqq is already marked as Commutative.

Modified:
    llvm/trunk/include/llvm/IntrinsicsX86.td

Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=143317&r1=143316&r2=143317&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Sun Oct 30 13:33:35 2011
@@ -456,13 +456,13 @@
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse2_pcmpeq_b : GCCBuiltin<"__builtin_ia32_pcmpeqb128">,
               Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
-                         llvm_v16i8_ty], [IntrNoMem]>;
+                         llvm_v16i8_ty], [IntrNoMem, Commutative]>;
   def int_x86_sse2_pcmpeq_w : GCCBuiltin<"__builtin_ia32_pcmpeqw128">,
               Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
-                         llvm_v8i16_ty], [IntrNoMem]>;
+                         llvm_v8i16_ty], [IntrNoMem, Commutative]>;
   def int_x86_sse2_pcmpeq_d : GCCBuiltin<"__builtin_ia32_pcmpeqd128">,
               Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty,
-                         llvm_v4i32_ty], [IntrNoMem]>;
+                         llvm_v4i32_ty], [IntrNoMem, Commutative]>;
   def int_x86_sse2_pcmpgt_b : GCCBuiltin<"__builtin_ia32_pcmpgtb128">,
               Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
                          llvm_v16i8_ty], [IntrNoMem]>;
@@ -1587,13 +1587,13 @@
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_mmx_pcmpeq_b : GCCBuiltin<"__builtin_ia32_pcmpeqb">,
               Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
-                         llvm_x86mmx_ty], [IntrNoMem]>;
+                         llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
   def int_x86_mmx_pcmpeq_w : GCCBuiltin<"__builtin_ia32_pcmpeqw">,
               Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
-                         llvm_x86mmx_ty], [IntrNoMem]>;
+                         llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
   def int_x86_mmx_pcmpeq_d : GCCBuiltin<"__builtin_ia32_pcmpeqd">,
               Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
-                         llvm_x86mmx_ty], [IntrNoMem]>;
+                         llvm_x86mmx_ty], [IntrNoMem, Commutative]>;
 
   def int_x86_mmx_pcmpgt_b : GCCBuiltin<"__builtin_ia32_pcmpgtb">,
               Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,



From baldrick at free.fr  Sun Oct 30 14:56:37 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 30 Oct 2011 19:56:37 -0000
Subject: [llvm-commits] [llvm] r143318 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp
 test/Transforms/InstSimplify/compare.ll
Message-ID: <20111030195637.3F2A53524001@llvm.org>

Author: baldrick
Date: Sun Oct 30 14:56:36 2011
New Revision: 143318

URL: http://llvm.org/viewvc/llvm-project?rev=143318&view=rev
Log:
Reapply commit 143214 with a fix: m_ICmp doesn't match conditions
with the given predicate, it matches any condition and returns the
predicate - d'oh!  Original commit message:
The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
Spotted by my super-optimizer in 186.crafty and 450.soplex.  We really
need a proper infrastructure for handling generalizations of this kind
of thing (which occur a lot), however this case is so simple that I decided
to go ahead and implement it directly.

Modified:
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp
    llvm/trunk/test/Transforms/InstSimplify/compare.ll

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=143318&r1=143317&r2=143318&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Sun Oct 30 14:56:36 2011
@@ -68,6 +68,20 @@
   return Constant::getAllOnesValue(Ty);
 }
 
+/// isSameCompare - Is V equivalent to the comparison "LHS Pred RHS"?
+static bool isSameCompare(Value *V, CmpInst::Predicate Pred, Value *LHS,
+                          Value *RHS) {
+  CmpInst *Cmp = dyn_cast<CmpInst>(V);
+  if (!Cmp)
+    return false;
+  CmpInst::Predicate CPred = Cmp->getPredicate();
+  Value *CLHS = Cmp->getOperand(0), *CRHS = Cmp->getOperand(1);
+  if (CPred == Pred && CLHS == LHS && CRHS == RHS)
+    return true;
+  return CPred == CmpInst::getSwappedPredicate(Pred) && CLHS == RHS &&
+    CRHS == LHS;
+}
+
 /// ValueDominatesPHI - Does the given value dominate the specified phi node?
 static bool ValueDominatesPHI(Value *V, PHINode *P, const DominatorTree *DT) {
   Instruction *I = dyn_cast<Instruction>(V);
@@ -416,40 +430,62 @@
   }
   assert(isa<SelectInst>(LHS) && "Not comparing with a select instruction!");
   SelectInst *SI = cast<SelectInst>(LHS);
+  Value *Cond = SI->getCondition();
+  Value *TV = SI->getTrueValue();
+  Value *FV = SI->getFalseValue();
 
   // Now that we have "cmp select(Cond, TV, FV), RHS", analyse it.
   // Does "cmp TV, RHS" simplify?
-  if (Value *TCmp = SimplifyCmpInst(Pred, SI->getTrueValue(), RHS, TD, DT,
-                                    MaxRecurse)) {
-    // It does!  Does "cmp FV, RHS" simplify?
-    if (Value *FCmp = SimplifyCmpInst(Pred, SI->getFalseValue(), RHS, TD, DT,
-                                      MaxRecurse)) {
-      // It does!  If they simplified to the same value, then use it as the
-      // result of the original comparison.
-      if (TCmp == FCmp)
-        return TCmp;
-      Value *Cond = SI->getCondition();
-      // If the false value simplified to false, then the result of the compare
-      // is equal to "Cond && TCmp".  This also catches the case when the false
-      // value simplified to false and the true value to true, returning "Cond".
-      if (match(FCmp, m_Zero()))
-        if (Value *V = SimplifyAndInst(Cond, TCmp, TD, DT, MaxRecurse))
-          return V;
-      // If the true value simplified to true, then the result of the compare
-      // is equal to "Cond || FCmp".
-      if (match(TCmp, m_One()))
-        if (Value *V = SimplifyOrInst(Cond, FCmp, TD, DT, MaxRecurse))
-          return V;
-      // Finally, if the false value simplified to true and the true value to
-      // false, then the result of the compare is equal to "!Cond".
-      if (match(FCmp, m_One()) && match(TCmp, m_Zero()))
-        if (Value *V =
-            SimplifyXorInst(Cond, Constant::getAllOnesValue(Cond->getType()),
-                            TD, DT, MaxRecurse))
-          return V;
-    }
+  Value *TCmp = SimplifyCmpInst(Pred, TV, RHS, TD, DT, MaxRecurse);
+  if (TCmp == Cond) {
+    // It not only simplified, it simplified to the select condition.  Replace
+    // it with 'true'.
+    TCmp = getTrue(Cond->getType());
+  } else if (!TCmp) {
+    // It didn't simplify.  However if "cmp TV, RHS" is equal to the select
+    // condition then we can replace it with 'true'.  Otherwise give up.
+    if (!isSameCompare(Cond, Pred, TV, RHS))
+      return 0;
+    TCmp = getTrue(Cond->getType());
+  }
+
+  // Does "cmp FV, RHS" simplify?
+  Value *FCmp = SimplifyCmpInst(Pred, FV, RHS, TD, DT, MaxRecurse);
+  if (FCmp == Cond) {
+    // It not only simplified, it simplified to the select condition.  Replace
+    // it with 'false'.
+    FCmp = getFalse(Cond->getType());
+  } else if (!FCmp) {
+    // It didn't simplify.  However if "cmp FV, RHS" is equal to the select
+    // condition then we can replace it with 'false'.  Otherwise give up.
+    if (!isSameCompare(Cond, Pred, FV, RHS))
+      return 0;
+    FCmp = getFalse(Cond->getType());
   }
 
+  // If both sides simplified to the same value, then use it as the result of
+  // the original comparison.
+  if (TCmp == FCmp)
+    return TCmp;
+  // If the false value simplified to false, then the result of the compare
+  // is equal to "Cond && TCmp".  This also catches the case when the false
+  // value simplified to false and the true value to true, returning "Cond".
+  if (match(FCmp, m_Zero()))
+    if (Value *V = SimplifyAndInst(Cond, TCmp, TD, DT, MaxRecurse))
+      return V;
+  // If the true value simplified to true, then the result of the compare
+  // is equal to "Cond || FCmp".
+  if (match(TCmp, m_One()))
+    if (Value *V = SimplifyOrInst(Cond, FCmp, TD, DT, MaxRecurse))
+      return V;
+  // Finally, if the false value simplified to true and the true value to
+  // false, then the result of the compare is equal to "!Cond".
+  if (match(FCmp, m_One()) && match(TCmp, m_Zero()))
+    if (Value *V =
+        SimplifyXorInst(Cond, Constant::getAllOnesValue(Cond->getType()),
+                        TD, DT, MaxRecurse))
+      return V;
+
   return 0;
 }
 

Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=143318&r1=143317&r2=143318&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Sun Oct 30 14:56:36 2011
@@ -204,6 +204,24 @@
 ; CHECK: ret i1 %cond
 }
 
+define i1 @select5(i32 %x) {
+; CHECK: @select5
+  %c = icmp eq i32 %x, 0
+  %s = select i1 %c, i32 1, i32 %x
+  %c2 = icmp eq i32 %s, 0
+  ret i1 %c2
+; CHECK: ret i1 false
+}
+
+define i1 @select6(i32 %x) {
+; CHECK: @select6
+  %c = icmp sgt i32 %x, 0
+  %s = select i1 %c, i32 %x, i32 4
+  %c2 = icmp eq i32 %s, 0
+  ret i1 %c2
+; CHECK: ret i1 %c2
+}
+
 define i1 @urem1(i32 %X, i32 %Y) {
 ; CHECK: @urem1
   %A = urem i32 %X, %Y



From craig.topper at gmail.com  Sun Oct 30 14:57:21 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sun, 30 Oct 2011 19:57:21 -0000
Subject: [llvm-commits] [llvm] r143319 - in /llvm/trunk:
 include/llvm/IntrinsicsX86.td lib/Target/X86/X86.td
 lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSystem.td
 lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h
Message-ID: <20111030195721.781DD3524001@llvm.org>

Author: ctopper
Date: Sun Oct 30 14:57:21 2011
New Revision: 143319

URL: http://llvm.org/viewvc/llvm-project?rev=143319&view=rev
Log:
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag.

Modified:
    llvm/trunk/include/llvm/IntrinsicsX86.td
    llvm/trunk/lib/Target/X86/X86.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/lib/Target/X86/X86InstrSystem.td
    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
    llvm/trunk/lib/Target/X86/X86Subtarget.h

Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=143319&r1=143318&r2=143319&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Sun Oct 30 14:57:21 2011
@@ -1651,3 +1651,25 @@
   def int_x86_bmi_pext_64 : GCCBuiltin<"__builtin_ia32_pext_di">,
               Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
 }
+
+//===----------------------------------------------------------------------===//
+// FS/GS Base
+
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_rdfsbase_32 : GCCBuiltin<"__builtin_ia32_rdfsbase32">,
+              Intrinsic<[llvm_i32_ty], []>;
+  def int_x86_rdgsbase_32 : GCCBuiltin<"__builtin_ia32_rdgsbase32">,
+              Intrinsic<[llvm_i32_ty], []>;
+  def int_x86_rdfsbase_64 : GCCBuiltin<"__builtin_ia32_rdfsbase64">,
+              Intrinsic<[llvm_i64_ty], []>;
+  def int_x86_rdgsbase_64 : GCCBuiltin<"__builtin_ia32_rdgsbase64">,
+              Intrinsic<[llvm_i64_ty], []>;
+  def int_x86_wrfsbase_32 : GCCBuiltin<"__builtin_ia32_wrfsbase32">,
+              Intrinsic<[], [llvm_i32_ty]>;
+  def int_x86_wrgsbase_32 : GCCBuiltin<"__builtin_ia32_wrgsbase32">,
+              Intrinsic<[], [llvm_i32_ty]>;
+  def int_x86_wrfsbase_64 : GCCBuiltin<"__builtin_ia32_wrfsbase64">,
+              Intrinsic<[], [llvm_i64_ty]>;
+  def int_x86_wrgsbase_64 : GCCBuiltin<"__builtin_ia32_wrgsbase64">,
+              Intrinsic<[], [llvm_i64_ty]>;
+}

Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=143319&r1=143318&r2=143319&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Sun Oct 30 14:57:21 2011
@@ -82,6 +82,9 @@
 
 def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
                                       "Enable AVX instructions">;
+def FeatureAVX2    : SubtargetFeature<"avx2", "HasAVX2", "true",
+                                      "Enable AVX2 instructions",
+                                      [FeatureAVX]>;
 def FeatureCLMUL   : SubtargetFeature<"clmul", "HasCLMUL", "true",
                                "Enable carry-less multiplication instructions">;
 def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
@@ -99,6 +102,8 @@
                                       "Support RDRAND instruction">;
 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
                        "Support 16-bit floating point conversion instructions">;
+def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
+                                       "Support FS/GS Base instructions">;
 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
                                       "Support LZCNT instruction">;
 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
@@ -157,13 +162,14 @@
 // Ivy Bridge
 def : Proc<"core-avx-i",      [FeatureSSE42, FeatureCMPXCHG16B,
                                FeatureAES, FeatureCLMUL,
-                               FeatureRDRAND, FeatureF16C]>;
+                               FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
 
 // Haswell
+// FIXME: Disabling AVX/AVX2 for now since it's not ready.
 def : Proc<"core-avx2",       [FeatureSSE42, FeatureCMPXCHG16B, FeatureAES,
                                FeatureCLMUL, FeatureRDRAND, FeatureF16C,
-                               FeatureFMA3, FeatureMOVBE, FeatureLZCNT,
-                               FeatureBMI, FeatureBMI2]>;
+                               FeatureFSGSBase, FeatureFMA3, FeatureMOVBE,
+                               FeatureLZCNT, FeatureBMI, FeatureBMI2]>;
 
 def : Proc<"k6",              [FeatureMMX]>;
 def : Proc<"k6-2",            [Feature3DNow]>;
@@ -194,9 +200,8 @@
                                Feature3DNowA, FeatureCMPXCHG16B,
                                FeatureSlowBTMem]>;
 def : Proc<"istanbul",        [Feature3DNowA, FeatureCMPXCHG16B,
-                               FeatureSSE4A, Feature3DNowA]>;
-def : Proc<"shanghai",        [Feature3DNowA, FeatureCMPXCHG16B, FeatureSSE4A,
-                               Feature3DNowA]>;
+                               FeatureSSE4A]>;
+def : Proc<"shanghai",        [Feature3DNowA, FeatureCMPXCHG16B, FeatureSSE4A]>;
 
 def : Proc<"winchip-c6",      [FeatureMMX]>;
 def : Proc<"winchip2",        [Feature3DNow]>;

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=143319&r1=143318&r2=143319&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Oct 30 14:57:21 2011
@@ -472,6 +472,7 @@
 def HasSSE4A     : Predicate<"Subtarget->hasSSE4A()">;
 
 def HasAVX       : Predicate<"Subtarget->hasAVX()">;
+def HasAVX2      : Predicate<"Subtarget->hasAVX2()">;
 def HasXMMInt    : Predicate<"Subtarget->hasXMMInt()">;
 
 def HasPOPCNT    : Predicate<"Subtarget->hasPOPCNT()">;
@@ -482,6 +483,7 @@
 def HasMOVBE     : Predicate<"Subtarget->hasMOVBE()">;
 def HasRDRAND    : Predicate<"Subtarget->hasRDRAND()">;
 def HasF16C      : Predicate<"Subtarget->hasF16C()">;
+def HasFSGSBase  : Predicate<"Subtarget->hasFSGSBase()">;
 def HasLZCNT     : Predicate<"Subtarget->hasLZCNT()">;
 def HasBMI       : Predicate<"Subtarget->hasBMI()">;
 def HasBMI2      : Predicate<"Subtarget->hasBMI2()">;

Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=143319&r1=143318&r2=143319&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Sun Oct 30 14:57:21 2011
@@ -446,23 +446,31 @@
 
 //===----------------------------------------------------------------------===//
 // FS/GS Base Instructions
-let Predicates = [In64BitMode] in {
+let Predicates = [HasFSGSBase, In64BitMode] in {
   def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
-                   "rdfsbase{l}\t$dst", []>, TB, XS;
+                   "rdfsbase{l}\t$dst",
+                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS;
   def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
-                     "rdfsbase{q}\t$dst", []>, TB, XS;
+                     "rdfsbase{q}\t$dst",
+                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS;
   def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
-                   "rdgsbase{l}\t$dst", []>, TB, XS;
+                   "rdgsbase{l}\t$dst",
+                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS;
   def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
-                     "rdgsbase{q}\t$dst", []>, TB, XS;
-  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$dst),
-                   "wrfsbase{l}\t$dst", []>, TB, XS;
-  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$dst),
-                   "wrfsbase{q}\t$dst", []>, TB, XS;
-  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$dst),
-                   "wrgsbase{l}\t$dst", []>, TB, XS;
-  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$dst),
-                    "wrgsbase{q}\t$dst", []>, TB, XS;
+                     "rdgsbase{q}\t$dst",
+                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS;
+  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
+                   "wrfsbase{l}\t$src",
+                   [(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS;
+  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
+                      "wrfsbase{q}\t$src",
+                      [(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS;
+  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
+                   "wrgsbase{l}\t$src",
+                   [(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS;
+  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
+                      "wrgsbase{q}\t$src",
+                      [(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS;
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=143319&r1=143318&r2=143319&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Sun Oct 30 14:57:21 2011
@@ -279,10 +279,19 @@
 
   if (IsIntel && MaxLevel >= 7) {
     if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
+      if (EBX & 0x1) {
+        HasFSGSBase = true;
+        ToggleFeature(X86::FeatureFSGSBase);
+      }
       if ((EBX >> 3) & 0x1) {
         HasBMI = true;
         ToggleFeature(X86::FeatureBMI);
       }
+      // FIXME: AVX2 codegen support is not ready.
+      //if ((EBX >> 5) & 0x1) {
+      //  HasAVX2 = true;
+      //  ToggleFeature(X86::FeatureAVX2);
+      //}
       if ((EBX >> 8) & 0x1) {
         HasBMI2 = true;
         ToggleFeature(X86::FeatureBMI2);
@@ -303,6 +312,7 @@
   , HasPOPCNT(false)
   , HasSSE4A(false)
   , HasAVX(false)
+  , HasAVX2(false)
   , HasAES(false)
   , HasCLMUL(false)
   , HasFMA3(false)
@@ -310,6 +320,7 @@
   , HasMOVBE(false)
   , HasRDRAND(false)
   , HasF16C(false)
+  , HasFSGSBase(false)
   , HasLZCNT(false)
   , HasBMI(false)
   , HasBMI2(false)

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=143319&r1=143318&r2=143319&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Sun Oct 30 14:57:21 2011
@@ -78,6 +78,9 @@
   /// HasAVX - Target has AVX instructions
   bool HasAVX;
 
+  /// HasAVX2 - Target has AVX2 instructions
+  bool HasAVX2;
+
   /// HasAES - Target has AES instructions
   bool HasAES;
 
@@ -99,6 +102,9 @@
   /// HasF16C - Processor has 16-bit floating point conversion instructions.
   bool HasF16C;
 
+  /// HasFSGSBase - Processor has FS/GS base insturctions.
+  bool HasFSGSBase;
+
   /// HasLZCNT - Processor has LZCNT instruction.
   bool HasLZCNT;
 
@@ -181,6 +187,7 @@
   bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
   bool hasPOPCNT() const { return HasPOPCNT; }
   bool hasAVX() const { return HasAVX; }
+  bool hasAVX2() const { return HasAVX2; }
   bool hasXMM() const { return hasSSE1() || hasAVX(); }
   bool hasXMMInt() const { return hasSSE2() || hasAVX(); }
   bool hasAES() const { return HasAES; }
@@ -190,6 +197,7 @@
   bool hasMOVBE() const { return HasMOVBE; }
   bool hasRDRAND() const { return HasRDRAND; }
   bool hasF16C() const { return HasF16C; }
+  bool hasFSGSBase() const { return HasFSGSBase; }
   bool hasLZCNT() const { return HasLZCNT; }
   bool hasBMI() const { return HasBMI; }
   bool hasBMI2() const { return HasBMI2; }



From peter at pcc.me.uk  Sun Oct 30 19:49:38 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Mon, 31 Oct 2011 00:49:38 -0000
Subject: [llvm-commits] [zorg] r143325 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20111031004938.A677C2A6C12C@llvm.org>

Author: pcc
Date: Sun Oct 30 19:49:38 2011
New Revision: 143325

URL: http://llvm.org/viewvc/llvm-project?rev=143325&view=rev
Log:
LLDB: add more environment variables for 64-bit builder, and disable 32-bit builder

gcc15 lacks enough RAM to build clang or lldb in a reasonable amount
of time.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=143325&r1=143324&r2=143325&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Sun Oct 30 19:49:38 2011
@@ -365,25 +365,28 @@
 # LLDB builders.
 def _get_lldb_builders():
     gcc_latest_env = {
-        'PATH': '/opt/cfarm/python2-latest/bin:/usr/local/bin:/usr/bin:/bin:/usr/games',
+        'PATH': '/home/baldrick/python-shared/bin/Python-2.7.2/bin:/usr/local/bin:/usr/bin:/bin:/usr/games',
+        'LD_LIBRARY_PATH': '/opt/cfarm/release/4.5.1/lib64:/home/baldrick/python-shared/bin/Python-2.7.2/lib',
+        'CPATH': '/home/baldrick/libedit-dev/usr/include',
+        'LIBRARY_PATH': '/home/baldrick/libedit-dev/usr/lib:/home/baldrick/python-shared/bin/Python-2.7.2/lib',
         'CC':  '/opt/cfarm/release/4.5.1/bin/gcc',
         'CXX': '/opt/cfarm/release/4.5.1/bin/g++'}
 
-    gcc_m32_latest_env = gcc_latest_env.copy()
-    gcc_m32_latest_env['CC'] += ' -m32'
-    gcc_m32_latest_env['CXX'] += ' -m32'
-
+#   gcc_m32_latest_env = gcc_latest_env.copy()
+#   gcc_m32_latest_env['CC'] += ' -m32'
+#   gcc_m32_latest_env['CXX'] += ' -m32'
+#
     return [
         {'name': "lldb-x86_64-linux",
          'slavenames': ["gcc14"],
          'builddir': "lldb-x86_64",
          'factory': LLDBBuilder.getLLDBBuildFactory(triple="x86_64-pc-linux-gnu",
                                                     env=gcc_latest_env)},
-        {'name': "lldb-i686-debian",
-         'slavenames': ["gcc15"],
-         'builddir': "lldb-i686-debian",
-         'factory': LLDBBuilder.getLLDBBuildFactory(triple="i686-pc-linux-gnu",
-                                                    env=gcc_m32_latest_env)}
+#       {'name': "lldb-i686-debian",
+#        'slavenames': ["gcc15"],
+#        'builddir': "lldb-i686-debian",
+#        'factory': LLDBBuilder.getLLDBBuildFactory(triple="i686-pc-linux-gnu",
+#                                                   env=gcc_m32_latest_env)}
        ]
 
 def _get_experimental_builders():



From nicholas at mxc.ca  Sun Oct 30 20:06:02 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 31 Oct 2011 01:06:02 -0000
Subject: [llvm-commits] [llvm] r143326 - in /llvm/trunk:
 lib/Target/TargetMachine.cpp test/CodeGen/X86/dbg-file-name.ll
 tools/llc/llc.cpp
Message-ID: <20111031010602.929713524001@llvm.org>

Author: nicholas
Date: Sun Oct 30 20:06:02 2011
New Revision: 143326

URL: http://llvm.org/viewvc/llvm-project?rev=143326&view=rev
Log:
Switch new .file directive emission off by default, change llc's flag for it to
-enable-dwarf-directory.

Modified:
    llvm/trunk/lib/Target/TargetMachine.cpp
    llvm/trunk/test/CodeGen/X86/dbg-file-name.ll
    llvm/trunk/tools/llc/llc.cpp

Modified: llvm/trunk/lib/Target/TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=143326&r1=143325&r2=143326&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/TargetMachine.cpp Sun Oct 30 20:06:02 2011
@@ -198,7 +198,7 @@
     MCSaveTempLabels(false),
     MCUseLoc(true),
     MCUseCFI(true),
-    MCUseDwarfDirectory(true) {
+    MCUseDwarfDirectory(false) {
   // Typically it will be subtargets that will adjust FloatABIType from Default
   // to Soft or Hard.
   if (UseSoftFloat)

Modified: llvm/trunk/test/CodeGen/X86/dbg-file-name.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-file-name.ll?rev=143326&r1=143325&r2=143326&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-file-name.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dbg-file-name.ll Sun Oct 30 20:06:02 2011
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple x86_64-apple-darwin10.0.0  < %s | FileCheck %s
+; RUN: llc -enable-dwarf-directory -mtriple x86_64-apple-darwin10.0.0  < %s | FileCheck %s
 
 ; Radar 8884898
 ; CHECK: file	1 "/Users/manav/one/two" "simple.c"

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=143326&r1=143325&r2=143326&view=diff
==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Sun Oct 30 20:06:02 2011
@@ -133,8 +133,8 @@
 cl::opt<bool> DisableCFI("disable-cfi", cl::Hidden,
                          cl::desc("Do not use .cfi_* directives"));
 
-cl::opt<bool> DisableDwarfDirectory("disable-dwarf-directory", cl::Hidden,
-    cl::desc("Do not use file directives with an explicit directory."));
+cl::opt<bool> EnableDwarfDirectory("enable-dwarf-directory", cl::Hidden,
+    cl::desc("Use .file directives with an explicit directory."));
 
 static cl::opt<bool>
 DisableRedZone("disable-red-zone",
@@ -319,8 +319,8 @@
   if (DisableCFI)
     Target.setMCUseCFI(false);
 
-  if (DisableDwarfDirectory)
-    Target.setMCUseDwarfDirectory(false);
+  if (EnableDwarfDirectory)
+    Target.setMCUseDwarfDirectory(true);
 
   // Disable .loc support for older OS X versions.
   if (TheTriple.isMacOSX() &&



From nicholas at mxc.ca  Sun Oct 30 20:32:21 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 31 Oct 2011 01:32:21 -0000
Subject: [llvm-commits] [llvm] r143328 - /llvm/trunk/docs/LangRef.html
Message-ID: <20111031013221.A04F83524001@llvm.org>

Author: nicholas
Date: Sun Oct 30 20:32:21 2011
New Revision: 143328

URL: http://llvm.org/viewvc/llvm-project?rev=143328&view=rev
Log:
Close <div> that was indenting the rest of the page.

Modified:
    llvm/trunk/docs/LangRef.html

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=143328&r1=143327&r2=143328&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Sun Oct 30 20:32:21 2011
@@ -7148,6 +7148,9 @@
 <p>This function returns the same values as the libm <tt>log</tt> functions
    would, and handles error conditions in the same way.</p>
 
+</div>
+
+<!-- _______________________________________________________________________ -->
 <h4>
   <a name="int_fma">'<tt>llvm.fma.*</tt>' Intrinsic</a>
 </h4>



From craig.topper at gmail.com  Sun Oct 30 21:15:10 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Mon, 31 Oct 2011 02:15:10 -0000
Subject: [llvm-commits] [llvm] r143331 - in /llvm/trunk:
 include/llvm/IntrinsicsX86.td lib/Target/X86/X86InstrSSE.td
 test/CodeGen/X86/avx2-intrinsics-x86.ll
Message-ID: <20111031021510.A4C5E3524001@llvm.org>

Author: ctopper
Date: Sun Oct 30 21:15:10 2011
New Revision: 143331

URL: http://llvm.org/viewvc/llvm-project?rev=143331&view=rev
Log:
Begin adding AVX2 instructions. No selection support yet other than intrinsics.

Added:
    llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll
Modified:
    llvm/trunk/include/llvm/IntrinsicsX86.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=143331&r1=143330&r2=143331&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Sun Oct 30 21:15:10 2011
@@ -1361,6 +1361,171 @@
 }
 
 //===----------------------------------------------------------------------===//
+// AVX2
+
+// Integer arithmetic ops.
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_avx2_padds_b : GCCBuiltin<"__builtin_ia32_paddsb256">,
+              Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
+                         llvm_v32i8_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_padds_w : GCCBuiltin<"__builtin_ia32_paddsw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_paddus_b : GCCBuiltin<"__builtin_ia32_paddusb256">,
+              Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
+                         llvm_v32i8_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_paddus_w : GCCBuiltin<"__builtin_ia32_paddusw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_psubs_b : GCCBuiltin<"__builtin_ia32_psubsb256">,
+              Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
+                         llvm_v32i8_ty], [IntrNoMem]>;
+  def int_x86_avx2_psubs_w : GCCBuiltin<"__builtin_ia32_psubsw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem]>;
+  def int_x86_avx2_psubus_b : GCCBuiltin<"__builtin_ia32_psubusb256">,
+              Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
+                         llvm_v32i8_ty], [IntrNoMem]>;
+  def int_x86_avx2_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem]>;
+  def int_x86_avx2_pmulhu_w : GCCBuiltin<"__builtin_ia32_pmulhuw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pmulu_dq : GCCBuiltin<"__builtin_ia32_pmuludq256">,
+              Intrinsic<[llvm_v4i64_ty], [llvm_v8i32_ty,
+                         llvm_v8i32_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd256">,
+              Intrinsic<[llvm_v8i32_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pavg_b : GCCBuiltin<"__builtin_ia32_pavgb256">,
+              Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
+                         llvm_v32i8_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pavg_w : GCCBuiltin<"__builtin_ia32_pavgw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pmaxu_b : GCCBuiltin<"__builtin_ia32_pmaxub256">,
+              Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
+                         llvm_v32i8_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pmaxs_w : GCCBuiltin<"__builtin_ia32_pmaxsw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pminu_b : GCCBuiltin<"__builtin_ia32_pminub256">,
+              Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
+                         llvm_v32i8_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pmins_w : GCCBuiltin<"__builtin_ia32_pminsw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem, Commutative]>;
+  def int_x86_avx2_psad_bw : GCCBuiltin<"__builtin_ia32_psadbw256">,
+              Intrinsic<[llvm_v4i64_ty], [llvm_v32i8_ty,
+                         llvm_v32i8_ty], [IntrNoMem, Commutative]>;
+}
+
+// Integer shift ops.
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_avx2_psll_w : GCCBuiltin<"__builtin_ia32_psllw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v8i16_ty], [IntrNoMem]>;
+  def int_x86_avx2_psll_d : GCCBuiltin<"__builtin_ia32_pslld256">,
+              Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
+                         llvm_v4i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_psll_q : GCCBuiltin<"__builtin_ia32_psllq256">,
+              Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
+                         llvm_v2i64_ty], [IntrNoMem]>;
+  def int_x86_avx2_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v8i16_ty], [IntrNoMem]>;
+  def int_x86_avx2_psrl_d : GCCBuiltin<"__builtin_ia32_psrld256">,
+              Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
+                         llvm_v4i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq256">,
+              Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
+                         llvm_v2i64_ty], [IntrNoMem]>;
+  def int_x86_avx2_psra_w : GCCBuiltin<"__builtin_ia32_psraw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v8i16_ty], [IntrNoMem]>;
+  def int_x86_avx2_psra_d : GCCBuiltin<"__builtin_ia32_psrad256">,
+              Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
+                         llvm_v4i32_ty], [IntrNoMem]>;
+
+  def int_x86_avx2_pslli_w : GCCBuiltin<"__builtin_ia32_psllwi256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi256">,
+              Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi256">,
+              Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_psrli_w : GCCBuiltin<"__builtin_ia32_psrlwi256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi256">,
+              Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi256">,
+              Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_psrai_w : GCCBuiltin<"__builtin_ia32_psrawi256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_psrai_d : GCCBuiltin<"__builtin_ia32_psradi256">,
+              Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+
+  def int_x86_avx2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi256">,
+              Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_psrl_dq : GCCBuiltin<"__builtin_ia32_psrldqi256">,
+              Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_psll_dq_bs : GCCBuiltin<"__builtin_ia32_pslldqi256_byteshift">,
+              Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_psrl_dq_bs : GCCBuiltin<"__builtin_ia32_psrldqi256_byteshift">,
+              Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
+                         llvm_i32_ty], [IntrNoMem]>;
+}
+
+// Integer comparison ops
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_avx2_pcmpeq_b : GCCBuiltin<"__builtin_ia32_pcmpeqb256">,
+              Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty, llvm_v32i8_ty],
+                        [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pcmpeq_w : GCCBuiltin<"__builtin_ia32_pcmpeqw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty, llvm_v16i16_ty],
+                        [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pcmpeq_d : GCCBuiltin<"__builtin_ia32_pcmpeqd256">,
+              Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty],
+                        [IntrNoMem, Commutative]>;
+  def int_x86_avx2_pcmpgt_b : GCCBuiltin<"__builtin_ia32_pcmpgtb256">,
+              Intrinsic<[llvm_v32i8_ty], [llvm_v32i8_ty,
+                         llvm_v32i8_ty], [IntrNoMem]>;
+  def int_x86_avx2_pcmpgt_w : GCCBuiltin<"__builtin_ia32_pcmpgtw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem]>;
+  def int_x86_avx2_pcmpgt_d : GCCBuiltin<"__builtin_ia32_pcmpgtd256">,
+              Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty,
+                         llvm_v8i32_ty], [IntrNoMem]>;
+}
+
+// Pack ops.
+let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
+  def int_x86_avx2_packsswb : GCCBuiltin<"__builtin_ia32_packsswb256">,
+              Intrinsic<[llvm_v32i8_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem]>;
+  def int_x86_avx2_packssdw : GCCBuiltin<"__builtin_ia32_packssdw256">,
+              Intrinsic<[llvm_v16i16_ty], [llvm_v8i32_ty,
+                         llvm_v8i32_ty], [IntrNoMem]>;
+  def int_x86_avx2_packuswb : GCCBuiltin<"__builtin_ia32_packuswb256">,
+              Intrinsic<[llvm_v32i8_ty], [llvm_v16i16_ty,
+                         llvm_v16i16_ty], [IntrNoMem]>;
+}
+
+//===----------------------------------------------------------------------===//
 // MMX
 
 // Empty MMX state op.

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=143331&r1=143330&r2=143331&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Oct 30 21:15:10 2011
@@ -3343,64 +3343,68 @@
 let ExeDomain = SSEPackedInt in { // SSE integer instructions
 
 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
-                            bit IsCommutable = 0, bit Is2Addr = 1> {
+                            RegisterClass RC, PatFrag memop_frag,
+                            X86MemOperand x86memop, bit IsCommutable = 0,
+                            bit Is2Addr = 1> {
   let isCommutable = IsCommutable in
-  def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
-       (ins VR128:$src1, VR128:$src2),
+  def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
+       (ins RC:$src1, RC:$src2),
        !if(Is2Addr,
            !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
-       [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
-  def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
-       (ins VR128:$src1, i128mem:$src2),
+       [(set RC:$dst, (IntId RC:$src1, RC:$src2))]>;
+  def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
+       (ins RC:$src1, x86memop:$src2),
        !if(Is2Addr,
            !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
-       [(set VR128:$dst, (IntId VR128:$src1,
-                                (bitconvert (memopv2i64 addr:$src2))))]>;
+       [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))]>;
 }
 
 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
                              string OpcodeStr, Intrinsic IntId,
-                             Intrinsic IntId2, bit Is2Addr = 1> {
-  def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
-       (ins VR128:$src1, VR128:$src2),
+                             Intrinsic IntId2, RegisterClass RC,
+                             bit Is2Addr = 1> {
+  // src2 is always 128-bit
+  def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
+       (ins RC:$src1, VR128:$src2),
        !if(Is2Addr,
            !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
-       [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
-  def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
-       (ins VR128:$src1, i128mem:$src2),
+       [(set RC:$dst, (IntId RC:$src1, VR128:$src2))]>;
+  def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
+       (ins RC:$src1, i128mem:$src2),
        !if(Is2Addr,
            !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
-       [(set VR128:$dst, (IntId VR128:$src1,
-                                      (bitconvert (memopv2i64 addr:$src2))))]>;
-  def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
-       (ins VR128:$src1, i32i8imm:$src2),
+       [(set RC:$dst, (IntId RC:$src1, (bitconvert (memopv2i64 addr:$src2))))]>;
+  def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
+       (ins RC:$src1, i32i8imm:$src2),
        !if(Is2Addr,
            !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
-       [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
+       [(set RC:$dst, (IntId2 RC:$src1, (i32 imm:$src2)))]>;
 }
 
 /// PDI_binop_rm - Simple SSE2 binary operator.
 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
-                        ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
+                        ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
+                        X86MemOperand x86memop, bit IsCommutable = 0,
+                        bit Is2Addr = 1> {
   let isCommutable = IsCommutable in
-  def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
-       (ins VR128:$src1, VR128:$src2),
+  def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
+       (ins RC:$src1, RC:$src2),
        !if(Is2Addr,
            !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
-       [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
-  def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
-       (ins VR128:$src1, i128mem:$src2),
+       [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
+  def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
+       (ins RC:$src1, x86memop:$src2),
        !if(Is2Addr,
            !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
-       [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
-                                     (bitconvert (memopv2i64 addr:$src2)))))]>;
+       [(set RC:$dst, (OpVT (OpNode RC:$src1,
+                                     (bitconvert (memop_frag addr:$src2)))))]>;
 }
 
 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
@@ -3425,93 +3429,203 @@
        [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
 }
 
+/// PDI_binop_rm_v4i64 - Simple AVX2 binary operator whose type is v4i64.
+///
+/// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
+/// to collapse (bitconvert VT to VT) into its operand.
+///
+multiclass PDI_binop_rm_v4i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
+                              bit IsCommutable = 0> {
+  let isCommutable = IsCommutable in
+  def rr : PDI<opc, MRMSrcReg, (outs VR256:$dst),
+       (ins VR256:$src1, VR256:$src2),
+       !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+       [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))]>;
+  def rm : PDI<opc, MRMSrcMem, (outs VR256:$dst),
+       (ins VR256:$src1, i256mem:$src2),
+       !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+       [(set VR256:$dst, (OpNode VR256:$src1, (memopv4i64 addr:$src2)))]>;
+}
+
 } // ExeDomain = SSEPackedInt
 
 // 128-bit Integer Arithmetic
 
 let Predicates = [HasAVX] in {
-defm VPADDB  : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
-defm VPADDW  : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
-defm VPADDD  : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
+defm VPADDB  : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
+                            i128mem, 1, 0 /*3addr*/>, VEX_4V;
+defm VPADDW  : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
+                            i128mem, 1, 0>, VEX_4V;
+defm VPADDD  : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
+                            i128mem, 1, 0>, VEX_4V;
 defm VPADDQ  : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
-defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
-defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
-defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
-defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
+defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
+                            i128mem, 1, 0>, VEX_4V;
+defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
+                            i128mem, 0, 0>, VEX_4V;
+defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
+                            i128mem, 0, 0>, VEX_4V;
+defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
+                            i128mem, 0, 0>, VEX_4V;
 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
 
 // Intrinsic forms
-defm VPSUBSB  : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
-                                 VEX_4V;
-defm VPSUBSW  : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
-                                 VEX_4V;
-defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
-                                 VEX_4V;
-defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
-                                 VEX_4V;
-defm VPADDSB  : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
-                                 VEX_4V;
-defm VPADDSW  : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
-                                 VEX_4V;
-defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
-                                 VEX_4V;
-defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
-                                 VEX_4V;
-defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
-                                 VEX_4V;
-defm VPMULHW  : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
-                                 VEX_4V;
-defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
-                                 VEX_4V;
-defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
-                                 VEX_4V;
-defm VPAVGB   : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
-                                 VEX_4V;
-defm VPAVGW   : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
-                                 VEX_4V;
-defm VPMINUB  : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
-                                 VEX_4V;
-defm VPMINSW  : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
-                                 VEX_4V;
-defm VPMAXUB  : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
-                                 VEX_4V;
-defm VPMAXSW  : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
-                                 VEX_4V;
-defm VPSADBW  : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
-                                 VEX_4V;
+defm VPSUBSB  : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
+                                 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
+defm VPSUBSW  : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
+                                 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
+defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
+                                 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
+defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
+                                 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
+defm VPADDSB  : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPADDSW  : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPMULHW  : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPAVGB   : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPAVGW   : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPMINUB  : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPMINSW  : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPMAXUB  : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPMAXSW  : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+defm VPSADBW  : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
+                                 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+}
+
+let Predicates = [HasAVX2] in {
+defm VPADDBY  : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
+                            i256mem, 1, 0>, VEX_4V;
+defm VPADDWY  : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
+                            i256mem, 1, 0>, VEX_4V;
+defm VPADDDY  : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
+                            i256mem, 1, 0>, VEX_4V;
+defm VPADDQY  : PDI_binop_rm_v4i64<0xD4, "vpaddq", add, 1>, VEX_4V;
+defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
+                            i256mem, 1, 0>, VEX_4V;
+defm VPSUBBY  : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
+                            i256mem, 0, 0>, VEX_4V;
+defm VPSUBWY  : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
+                            i256mem,  0, 0>, VEX_4V;
+defm VPSUBDY  : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
+                            i256mem, 0, 0>, VEX_4V;
+defm VPSUBQY  : PDI_binop_rm_v4i64<0xFB, "vpsubq", sub, 0>, VEX_4V;
+
+// Intrinsic forms
+defm VPSUBSBY  : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
+                                  VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
+defm VPSUBSWY  : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
+                                  VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
+defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
+                                  VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
+defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
+                                  VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
+defm VPADDSBY  : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPADDSWY  : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPMULHWY  : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPMULUDQY : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_avx2_pmulu_dq,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPAVGBY   : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPAVGWY   : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPMINUBY  : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPMINSWY  : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPMAXUBY  : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPMAXSWY  : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+defm VPSADBWY  : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
+                                  VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
 }
 
 let Constraints = "$src1 = $dst" in {
-defm PADDB  : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
-defm PADDW  : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
-defm PADDD  : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
+defm PADDB  : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
+                           i128mem, 1>;
+defm PADDW  : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
+                           i128mem, 1>;
+defm PADDD  : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
+                           i128mem, 1>;
 defm PADDQ  : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
-defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
-defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
-defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
-defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
+defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
+                           i128mem, 1>;
+defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
+                          i128mem>;
+defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
+                          i128mem>;
+defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
+                          i128mem>;
 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
 
 // Intrinsic forms
-defm PSUBSB  : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
-defm PSUBSW  : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
-defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
-defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
-defm PADDSB  : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
-defm PADDSW  : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
-defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
-defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
-defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
-defm PMULHW  : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
-defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
-defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
-defm PAVGB   : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
-defm PAVGW   : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
-defm PMINUB  : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
-defm PMINSW  : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
-defm PMAXUB  : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
-defm PMAXSW  : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
-defm PSADBW  : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
+defm PSUBSB  : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
+                                VR128, memopv2i64, i128mem>;
+defm PSUBSW  : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
+                                VR128, memopv2i64, i128mem>;
+defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
+                                VR128, memopv2i64, i128mem>;
+defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
+                                VR128, memopv2i64, i128mem>;
+defm PADDSB  : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PADDSW  : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PMULHW  : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PAVGB   : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PAVGW   : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PMINUB  : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PMINSW  : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PMAXUB  : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PMAXSW  : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
+                                VR128, memopv2i64, i128mem, 1>;
+defm PSADBW  : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
+                                VR128, memopv2i64, i128mem, 1>;
 
 } // Constraints = "$src1 = $dst"
 
@@ -3521,31 +3635,31 @@
 
 let Predicates = [HasAVX] in {
 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
-                                int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
-                                VEX_4V;
+                                int_x86_sse2_psll_w, int_x86_sse2_pslli_w,
+                                VR128, 0>, VEX_4V;
 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
-                                int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
-                                VEX_4V;
+                                int_x86_sse2_psll_d, int_x86_sse2_pslli_d,
+                                VR128, 0>, VEX_4V;
 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
-                                int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
-                                VEX_4V;
+                                int_x86_sse2_psll_q, int_x86_sse2_pslli_q,
+                                VR128, 0>, VEX_4V;
 
 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
-                                int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
-                                VEX_4V;
+                                int_x86_sse2_psrl_w, int_x86_sse2_psrli_w,
+                                VR128, 0>, VEX_4V;
 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
-                                int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
-                                VEX_4V;
+                                int_x86_sse2_psrl_d, int_x86_sse2_psrli_d,
+                                VR128, 0>, VEX_4V;
 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
-                                int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
-                                VEX_4V;
+                                int_x86_sse2_psrl_q, int_x86_sse2_psrli_q,
+                                VR128, 0>, VEX_4V;
 
 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
-                                int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
-                                VEX_4V;
+                                int_x86_sse2_psra_w, int_x86_sse2_psrai_w,
+                                VR128, 0>, VEX_4V;
 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
-                                int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
-                                VEX_4V;
+                                int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
+                                VR128, 0>, VEX_4V;
 
 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
 defm VPOR  : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
@@ -3578,25 +3692,92 @@
 }
 }
 
+let Predicates = [HasAVX2] in {
+defm VPSLLWY : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
+                                 int_x86_avx2_psll_w, int_x86_avx2_pslli_w,
+                                 VR256, 0>, VEX_4V;
+defm VPSLLDY : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
+                                 int_x86_avx2_psll_d, int_x86_avx2_pslli_d,
+                                 VR256, 0>, VEX_4V;
+defm VPSLLQY : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
+                                 int_x86_avx2_psll_q, int_x86_avx2_pslli_q,
+                                 VR256, 0>, VEX_4V;
+
+defm VPSRLWY : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
+                                 int_x86_avx2_psrl_w, int_x86_avx2_psrli_w,
+                                 VR256, 0>, VEX_4V;
+defm VPSRLDY : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
+                                 int_x86_avx2_psrl_d, int_x86_avx2_psrli_d,
+                                 VR256, 0>, VEX_4V;
+defm VPSRLQY : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
+                                 int_x86_avx2_psrl_q, int_x86_avx2_psrli_q,
+                                 VR256, 0>, VEX_4V;
+
+defm VPSRAWY : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
+                                 int_x86_avx2_psra_w, int_x86_avx2_psrai_w,
+                                 VR256, 0>, VEX_4V;
+defm VPSRADY : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
+                                 int_x86_avx2_psra_d, int_x86_avx2_psrai_d,
+                                 VR256, 0>, VEX_4V;
+
+defm VPANDY : PDI_binop_rm_v4i64<0xDB, "vpand", and, 1>, VEX_4V;
+defm VPORY  : PDI_binop_rm_v4i64<0xEB, "vpor" , or, 1>, VEX_4V;
+defm VPXORY : PDI_binop_rm_v4i64<0xEF, "vpxor", xor, 1>, VEX_4V;
+
+let ExeDomain = SSEPackedInt in {
+  let neverHasSideEffects = 1 in {
+    // 128-bit logical shifts.
+    def VPSLLDQYri : PDIi8<0x73, MRM7r,
+                      (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
+                      "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+                      VEX_4V;
+    def VPSRLDQYri : PDIi8<0x73, MRM3r,
+                      (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
+                      "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+                      VEX_4V;
+    // PSRADQYri doesn't exist in SSE[1-3].
+  }
+  def VPANDNYrr : PDI<0xDF, MRMSrcReg,
+                     (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
+                     "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                     [(set VR256:$dst,
+                          (v4i64 (X86andnp VR256:$src1, VR256:$src2)))]>,VEX_4V;
+
+  def VPANDNYrm : PDI<0xDF, MRMSrcMem,
+                     (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
+                     "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                     [(set VR256:$dst, (X86andnp VR256:$src1,
+                                            (memopv4i64 addr:$src2)))]>, VEX_4V;
+}
+}
+
 let Constraints = "$src1 = $dst" in {
 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
-                               int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
+                               int_x86_sse2_psll_w, int_x86_sse2_pslli_w,
+                               VR128>;
 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
-                               int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
+                               int_x86_sse2_psll_d, int_x86_sse2_pslli_d,
+                               VR128>;
 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
-                               int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
+                               int_x86_sse2_psll_q, int_x86_sse2_pslli_q,
+                               VR128>;
 
 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
-                               int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
+                               int_x86_sse2_psrl_w, int_x86_sse2_psrli_w,
+                               VR128>;
 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
-                               int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
+                               int_x86_sse2_psrl_d, int_x86_sse2_psrli_d,
+                               VR128>;
 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
-                               int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
+                               int_x86_sse2_psrl_q, int_x86_sse2_psrli_q,
+                               VR128>;
 
 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
-                               int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
+                               int_x86_sse2_psra_w, int_x86_sse2_psrai_w,
+                               VR128>;
 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
-                               int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
+                               int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
+                               VR128>;
 
 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
 defm POR  : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
@@ -3642,6 +3823,17 @@
             (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
 }
 
+let Predicates = [HasAVX2] in {
+  def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
+            (v4i64 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2)))>;
+  def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
+            (v4i64 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2)))>;
+  def : Pat<(int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2),
+            (v4i64 (VPSLLDQYri VR256:$src1, imm:$src2))>;
+  def : Pat<(int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2),
+            (v4i64 (VPSRLDQYri VR256:$src1, imm:$src2))>;
+}
+
 let Predicates = [HasSSE2] in {
   def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
             (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
@@ -3666,18 +3858,18 @@
 //===---------------------------------------------------------------------===//
 
 let Predicates = [HasAVX] in {
-  defm VPCMPEQB  : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
-                                    0>, VEX_4V;
-  defm VPCMPEQW  : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
-                                    0>, VEX_4V;
-  defm VPCMPEQD  : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
-                                    0>, VEX_4V;
-  defm VPCMPGTB  : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
-                                    0>, VEX_4V;
-  defm VPCMPGTW  : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
-                                    0>, VEX_4V;
-  defm VPCMPGTD  : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
-                                    0>, VEX_4V;
+  defm VPCMPEQB  : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b,
+                                    VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+  defm VPCMPEQW  : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w,
+                                    VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+  defm VPCMPEQD  : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d,
+                                    VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
+  defm VPCMPGTB  : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b,
+                                    VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
+  defm VPCMPGTW  : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w,
+                                    VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
+  defm VPCMPGTD  : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d,
+                                    VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
 
   def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
             (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
@@ -3706,13 +3898,34 @@
             (VPCMPGTDrm VR128:$src1, addr:$src2)>;
 }
 
+let Predicates = [HasAVX2] in {
+  defm VPCMPEQBY : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_avx2_pcmpeq_b,
+                                    VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+  defm VPCMPEQWY : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_avx2_pcmpeq_w,
+                                    VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+  defm VPCMPEQDY : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_avx2_pcmpeq_d,
+                                    VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
+  defm VPCMPGTBY : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_avx2_pcmpgt_b,
+                                    VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
+  defm VPCMPGTWY : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_avx2_pcmpgt_w,
+                                    VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
+  defm VPCMPGTDY : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_avx2_pcmpgt_d,
+                                    VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
+}
+
 let Constraints = "$src1 = $dst" in {
-  defm PCMPEQB  : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
-  defm PCMPEQW  : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
-  defm PCMPEQD  : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
-  defm PCMPGTB  : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
-  defm PCMPGTW  : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
-  defm PCMPGTD  : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
+  defm PCMPEQB  : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b,
+                                   VR128, memopv2i64, i128mem, 1>;
+  defm PCMPEQW  : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w,
+                                   VR128, memopv2i64, i128mem, 1>;
+  defm PCMPEQD  : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d,
+                                   VR128, memopv2i64, i128mem, 1>;
+  defm PCMPGTB  : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b,
+                                   VR128, memopv2i64, i128mem>;
+  defm PCMPGTW  : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w,
+                                   VR128, memopv2i64, i128mem>;
+  defm PCMPGTD  : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d,
+                                   VR128, memopv2i64, i128mem>;
 } // Constraints = "$src1 = $dst"
 
 let Predicates = [HasSSE2] in {
@@ -3749,17 +3962,29 @@
 
 let Predicates = [HasAVX] in {
 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
-                                  0, 0>, VEX_4V;
+                                  VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
-                                  0, 0>, VEX_4V;
+                                  VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
-                                  0, 0>, VEX_4V;
+                                  VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
+}
+
+let Predicates = [HasAVX2] in {
+defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
+                                   VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
+defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
+                                   VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
+defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
+                                   VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
 }
 
 let Constraints = "$src1 = $dst" in {
-defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
-defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
-defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
+defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
+                                 VR128, memopv2i64, i128mem>;
+defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
+                                 VR128, memopv2i64, i128mem>;
+defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
+                                 VR128, memopv2i64, i128mem>;
 } // Constraints = "$src1 = $dst"
 
 //===---------------------------------------------------------------------===//

Added: llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll?rev=143331&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll (added)
+++ llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll Sun Oct 30 21:15:10 2011
@@ -0,0 +1,384 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=core-avx2 -mattr=avx2 | FileCheck %s
+
+define <16 x i16> @test_x86_avx2_packssdw(<8 x i32> %a0, <8 x i32> %a1) {
+  ; CHECK: vpackssdw
+  %res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %a0, <8 x i32> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32>, <8 x i32>) nounwind readnone
+
+
+define <32 x i8> @test_x86_avx2_packsswb(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpacksswb
+  %res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1]
+  ret <32 x i8> %res
+}
+declare <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <32 x i8> @test_x86_avx2_packuswb(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpackuswb
+  %res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1]
+  ret <32 x i8> %res
+}
+declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <32 x i8> @test_x86_avx2_padds_b(<32 x i8> %a0, <32 x i8> %a1) {
+  ; CHECK: vpaddsb
+  %res = call <32 x i8> @llvm.x86.avx2.padds.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
+  ret <32 x i8> %res
+}
+declare <32 x i8> @llvm.x86.avx2.padds.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_padds_w(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpaddsw
+  %res = call <16 x i16> @llvm.x86.avx2.padds.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.padds.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <32 x i8> @test_x86_avx2_paddus_b(<32 x i8> %a0, <32 x i8> %a1) {
+  ; CHECK: vpaddusb
+  %res = call <32 x i8> @llvm.x86.avx2.paddus.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
+  ret <32 x i8> %res
+}
+declare <32 x i8> @llvm.x86.avx2.paddus.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_paddus_w(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpaddusw
+  %res = call <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <32 x i8> @test_x86_avx2_pavg_b(<32 x i8> %a0, <32 x i8> %a1) {
+  ; CHECK: vpavgb
+  %res = call <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
+  ret <32 x i8> %res
+}
+declare <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_pavg_w(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpavgw
+  %res = call <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <32 x i8> @test_x86_avx2_pcmpeq_b(<32 x i8> %a0, <32 x i8> %a1) {
+  ; CHECK: vpcmpeqb
+  %res = call <32 x i8> @llvm.x86.avx2.pcmpeq.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
+  ret <32 x i8> %res
+}
+declare <32 x i8> @llvm.x86.avx2.pcmpeq.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+
+define <8 x i32> @test_x86_avx2_pcmpeq_d(<8 x i32> %a0, <8 x i32> %a1) {
+  ; CHECK: vpcmpeqd
+  %res = call <8 x i32> @llvm.x86.avx2.pcmpeq.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
+  ret <8 x i32> %res
+}
+declare <8 x i32> @llvm.x86.avx2.pcmpeq.d(<8 x i32>, <8 x i32>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_pcmpeq_w(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpcmpeqw
+  %res = call <16 x i16> @llvm.x86.avx2.pcmpeq.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.pcmpeq.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <32 x i8> @test_x86_avx2_pcmpgt_b(<32 x i8> %a0, <32 x i8> %a1) {
+  ; CHECK: vpcmpgtb
+  %res = call <32 x i8> @llvm.x86.avx2.pcmpgt.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
+  ret <32 x i8> %res
+}
+declare <32 x i8> @llvm.x86.avx2.pcmpgt.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+
+define <8 x i32> @test_x86_avx2_pcmpgt_d(<8 x i32> %a0, <8 x i32> %a1) {
+  ; CHECK: vpcmpgtd
+  %res = call <8 x i32> @llvm.x86.avx2.pcmpgt.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
+  ret <8 x i32> %res
+}
+declare <8 x i32> @llvm.x86.avx2.pcmpgt.d(<8 x i32>, <8 x i32>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_pcmpgt_w(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpcmpgtw
+  %res = call <16 x i16> @llvm.x86.avx2.pcmpgt.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.pcmpgt.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <8 x i32> @test_x86_avx2_pmadd_wd(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpmaddwd
+  %res = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a0, <16 x i16> %a1) ; <<8 x i32>> [#uses=1]
+  ret <8 x i32> %res
+}
+declare <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_pmaxs_w(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpmaxsw
+  %res = call <16 x i16> @llvm.x86.avx2.pmaxs.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.pmaxs.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <32 x i8> @test_x86_avx2_pmaxu_b(<32 x i8> %a0, <32 x i8> %a1) {
+  ; CHECK: vpmaxub
+  %res = call <32 x i8> @llvm.x86.avx2.pmaxu.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
+  ret <32 x i8> %res
+}
+declare <32 x i8> @llvm.x86.avx2.pmaxu.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_pmins_w(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpminsw
+  %res = call <16 x i16> @llvm.x86.avx2.pmins.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.pmins.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <32 x i8> @test_x86_avx2_pminu_b(<32 x i8> %a0, <32 x i8> %a1) {
+  ; CHECK: vpminub
+  %res = call <32 x i8> @llvm.x86.avx2.pminu.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
+  ret <32 x i8> %res
+}
+declare <32 x i8> @llvm.x86.avx2.pminu.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_pmulh_w(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpmulhw
+  %res = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_pmulhu_w(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpmulhuw
+  %res = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_pmulu_dq(<8 x i32> %a0, <8 x i32> %a1) {
+  ; CHECK: vpmuludq
+  %res = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> %a0, <8 x i32> %a1) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32>, <8 x i32>) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_psad_bw(<32 x i8> %a0, <32 x i8> %a1) {
+  ; CHECK: vpsadbw
+  %res = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %a0, <32 x i8> %a1) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8>, <32 x i8>) nounwind readnone
+
+
+define <8 x i32> @test_x86_avx2_psll_d(<8 x i32> %a0, <4 x i32> %a1) {
+  ; CHECK: vpslld
+  %res = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
+  ret <8 x i32> %res
+}
+declare <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32>, <4 x i32>) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_psll_dq(<4 x i64> %a0) {
+  ; CHECK: vpslldq
+  %res = call <4 x i64> @llvm.x86.avx2.psll.dq(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psll.dq(<4 x i64>, i32) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_psll_dq_bs(<4 x i64> %a0) {
+  ; CHECK: vpslldq
+  %res = call <4 x i64> @llvm.x86.avx2.psll.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psll.dq.bs(<4 x i64>, i32) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_psll_q(<4 x i64> %a0, <2 x i64> %a1) {
+  ; CHECK: vpsllq
+  %res = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64>, <2 x i64>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_psll_w(<16 x i16> %a0, <8 x i16> %a1) {
+  ; CHECK: vpsllw
+  %res = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16>, <8 x i16>) nounwind readnone
+
+
+define <8 x i32> @test_x86_avx2_pslli_d(<8 x i32> %a0) {
+  ; CHECK: vpslld
+  %res = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
+  ret <8 x i32> %res
+}
+declare <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32>, i32) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_pslli_q(<4 x i64> %a0) {
+  ; CHECK: vpsllq
+  %res = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64>, i32) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_pslli_w(<16 x i16> %a0) {
+  ; CHECK: vpsllw
+  %res = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16>, i32) nounwind readnone
+
+
+define <8 x i32> @test_x86_avx2_psra_d(<8 x i32> %a0, <4 x i32> %a1) {
+  ; CHECK: vpsrad
+  %res = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
+  ret <8 x i32> %res
+}
+declare <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32>, <4 x i32>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_psra_w(<16 x i16> %a0, <8 x i16> %a1) {
+  ; CHECK: vpsraw
+  %res = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16>, <8 x i16>) nounwind readnone
+
+
+define <8 x i32> @test_x86_avx2_psrai_d(<8 x i32> %a0) {
+  ; CHECK: vpsrad
+  %res = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
+  ret <8 x i32> %res
+}
+declare <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32>, i32) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_psrai_w(<16 x i16> %a0) {
+  ; CHECK: vpsraw
+  %res = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16>, i32) nounwind readnone
+
+
+define <8 x i32> @test_x86_avx2_psrl_d(<8 x i32> %a0, <4 x i32> %a1) {
+  ; CHECK: vpsrld
+  %res = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
+  ret <8 x i32> %res
+}
+declare <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32>, <4 x i32>) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_psrl_dq(<4 x i64> %a0) {
+  ; CHECK: vpsrldq
+  %res = call <4 x i64> @llvm.x86.avx2.psrl.dq(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psrl.dq(<4 x i64>, i32) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_psrl_dq_bs(<4 x i64> %a0) {
+  ; CHECK: vpsrldq
+  %res = call <4 x i64> @llvm.x86.avx2.psrl.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psrl.dq.bs(<4 x i64>, i32) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_psrl_q(<4 x i64> %a0, <2 x i64> %a1) {
+  ; CHECK: vpsrlq
+  %res = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64>, <2 x i64>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_psrl_w(<16 x i16> %a0, <8 x i16> %a1) {
+  ; CHECK: vpsrlw
+  %res = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16>, <8 x i16>) nounwind readnone
+
+
+define <8 x i32> @test_x86_avx2_psrli_d(<8 x i32> %a0) {
+  ; CHECK: vpsrld
+  %res = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
+  ret <8 x i32> %res
+}
+declare <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32>, i32) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_psrli_q(<4 x i64> %a0) {
+  ; CHECK: vpsrlq
+  %res = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
+  ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64>, i32) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_psrli_w(<16 x i16> %a0) {
+  ; CHECK: vpsrlw
+  %res = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16>, i32) nounwind readnone
+
+
+define <32 x i8> @test_x86_avx2_psubs_b(<32 x i8> %a0, <32 x i8> %a1) {
+  ; CHECK: vpsubsb
+  %res = call <32 x i8> @llvm.x86.avx2.psubs.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
+  ret <32 x i8> %res
+}
+declare <32 x i8> @llvm.x86.avx2.psubs.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_psubs_w(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpsubsw
+  %res = call <16 x i16> @llvm.x86.avx2.psubs.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.psubs.w(<16 x i16>, <16 x i16>) nounwind readnone
+
+
+define <32 x i8> @test_x86_avx2_psubus_b(<32 x i8> %a0, <32 x i8> %a1) {
+  ; CHECK: vpsubusb
+  %res = call <32 x i8> @llvm.x86.avx2.psubus.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
+  ret <32 x i8> %res
+}
+declare <32 x i8> @llvm.x86.avx2.psubus.b(<32 x i8>, <32 x i8>) nounwind readnone
+
+
+define <16 x i16> @test_x86_avx2_psubus_w(<16 x i16> %a0, <16 x i16> %a1) {
+  ; CHECK: vpsubusw
+  %res = call <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
+  ret <16 x i16> %res
+}
+declare <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16>, <16 x i16>) nounwind readnone



From craig.topper at gmail.com  Sun Oct 30 21:15:47 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Mon, 31 Oct 2011 02:15:47 -0000
Subject: [llvm-commits] [llvm] r143332 -
	/llvm/trunk/test/CodeGen/X86/fsgsbase.ll
Message-ID: <20111031021547.7E0623524001@llvm.org>

Author: ctopper
Date: Sun Oct 30 21:15:47 2011
New Revision: 143332

URL: http://llvm.org/viewvc/llvm-project?rev=143332&view=rev
Log:
Test case for X86 FS/GS Base intrinsics

Added:
    llvm/trunk/test/CodeGen/X86/fsgsbase.ll

Added: llvm/trunk/test/CodeGen/X86/fsgsbase.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fsgsbase.ll?rev=143332&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fsgsbase.ll (added)
+++ llvm/trunk/test/CodeGen/X86/fsgsbase.ll Sun Oct 30 21:15:47 2011
@@ -0,0 +1,57 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=core-avx-i -mattr=fsgsbase | FileCheck %s
+
+define i32 @test_x86_rdfsbase_32() {
+  ; CHECK: rdfsbasel
+  %res = call i32 @llvm.x86.rdfsbase.32()
+  ret i32 %res
+}
+declare i32 @llvm.x86.rdfsbase.32() nounwind readnone
+
+define i32 @test_x86_rdgsbase_32() {
+  ; CHECK: rdgsbasel
+  %res = call i32 @llvm.x86.rdgsbase.32()
+  ret i32 %res
+}
+declare i32 @llvm.x86.rdgsbase.32() nounwind readnone
+
+define i64 @test_x86_rdfsbase_64() {
+  ; CHECK: rdfsbaseq
+  %res = call i64 @llvm.x86.rdfsbase.64()
+  ret i64 %res
+}
+declare i64 @llvm.x86.rdfsbase.64() nounwind readnone
+
+define i64 @test_x86_rdgsbase_64() {
+  ; CHECK: rdgsbaseq
+  %res = call i64 @llvm.x86.rdgsbase.64()
+  ret i64 %res
+}
+declare i64 @llvm.x86.rdgsbase.64() nounwind readnone
+
+define void @test_x86_wrfsbase_32(i32 %x) {
+  ; CHECK: wrfsbasel
+  call void @llvm.x86.wrfsbase.32(i32 %x)
+  ret void
+}
+declare void @llvm.x86.wrfsbase.32(i32) nounwind readnone
+
+define void @test_x86_wrgsbase_32(i32 %x) {
+  ; CHECK: wrgsbasel
+  call void @llvm.x86.wrgsbase.32(i32 %x)
+  ret void
+}
+declare void @llvm.x86.wrgsbase.32(i32) nounwind readnone
+
+define void @test_x86_wrfsbase_64(i64 %x) {
+  ; CHECK: wrfsbaseq
+  call void @llvm.x86.wrfsbase.64(i64 %x)
+  ret void
+}
+declare void @llvm.x86.wrfsbase.64(i64) nounwind readnone
+
+define void @test_x86_wrgsbase_64(i64 %x) {
+  ; CHECK: wrgsbaseq
+  call void @llvm.x86.wrgsbase.64(i64 %x)
+  ret void
+}
+declare void @llvm.x86.wrgsbase.64(i64) nounwind readnone



From peter at pcc.me.uk  Sun Oct 30 23:22:10 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Mon, 31 Oct 2011 04:22:10 -0000
Subject: [llvm-commits] [zorg] r143333 -
	/zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py
Message-ID: <20111031042210.C6A073524001@llvm.org>

Author: pcc
Date: Sun Oct 30 23:22:10 2011
New Revision: 143333

URL: http://llvm.org/viewvc/llvm-project?rev=143333&view=rev
Log:
LLDB: pass environment variables to test command

Modified:
    zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py

Modified: zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py?rev=143333&r1=143332&r2=143333&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py (original)
+++ zorg/trunk/zorg/buildbot/builders/LLDBBuilder.py Sun Oct 30 23:22:10 2011
@@ -23,7 +23,7 @@
 
 def getLLDBBuildFactory(triple, outOfDir=False, useTwoStage=False,
                         always_install=False, extra_configure_args=[],
-                        *args, **kwargs):
+                        env={}, *args, **kwargs):
     # FIXME: this code is copied from getClangBuildFactory
     inDir = not outOfDir and not useTwoStage
     if inDir:
@@ -74,6 +74,7 @@
                                                extra_configure_args=
                                                  extra_configure_args+
                                                  ['--enable-targets=host'],
+                                               env=env,
                                                trunk_revision='%(llvmrev)s',
                                                force_checkout=True,
                                                clean=new_llvmrev,
@@ -86,6 +87,7 @@
                            command=['nice', '-n', '10',
                                     'make'],
                            haltOnFailure=True, description="test lldb",
+                           env=env,
                            workdir='%s/tools/lldb/test' % llvm_1_objdir))
 
     return f



From baldrick at free.fr  Fri Oct 28 14:50:53 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 28 Oct 2011 21:50:53 +0200
Subject: [llvm-commits] [LLVM, SwitchInst,
 case ranges] Auxiliary patch #1
In-Reply-To: <485181319805488@web67.yandex.ru>
References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr>
	<485181319805488@web67.yandex.ru>
Message-ID: <4EAB079D.6000606@free.fr>

Hi Stepan,

> Well, on instruction selection level switch cases are already grouped to switch ranges. I don't think that case ranges increases complexity of existing optimizers.

I guess Anton can comment on codegen, but the fact that it doesn't make codegen
harder has nothing to do with increasing the complexity of the optimizers, since
they work at the IR level.  It may be that case ranges allow the optimizers to
do a better job.  It may be that they simplify the optimizers.  But it also may
be the opposite: they might make switches harder to work with and reason about
for no advantage.  Which is it?  Do you have an example where case ranges would
result in better code, or make it easier to produce better code?

  I think that its useful when we work with front-ends like Fortran, since we 
doesn't need to split fortran's case-ranges and combine them again during switch 
lowering procedure.

Does doing this combining have a significant impact on anything (like compile
time)?  If not, then it doesn't matter much.  It's even a good thing if the
simple form switch statements currently have make the optimizers easier to write 
and improve.

By the way, Ada also produces ranges, but unlike in C (I don't remember how
this is in Fortran) switch conditions can be signed or unsigned, resulting in
signed or unsigned ranges.  Will your ranges be circular (along the lines of
LLVM's ConstantRange class), so that both are handled uniformly?

Ciao, Duncan.

>
> -Stepan
>
> 28.10.2011, 16:19, "Duncan Sands"<baldrick at free.fr>:
>> Hi Stepan, I have to ask: what are switch case ranges good for?  Will they
>> actually result in better code, or just more complexity in the optimizers
>> and code generators?  Sorry to ask at this late date.  I know I'm the one
>> that first suggested adding case ranges, but I've since come to wonder
>> whether they are really useful.
>>
>> Ciao, Duncan.
>>
>>>   Hi all. The main discussion branch of this feature is here:
>>>   http://llvm.org/bugs/show_bug.cgi?id=1255
>>>
>>>   We need change SwitchInst internals: replace case value type from "ConstantInt"
>>>   to "APInt", then move case values out from operands collection. To do that we
>>>   need add APInt::isInitialized feature. We also need extend SmallSet class adding
>>>   Compare parameter to this template:
>>>   template<typename T, unsigned N, typename C = std::less<T>  >
>>>
>>>   Please find attached patches for review.
>>>
>>>   Regards,
>>>   Stepan.
>>>
>>>   _______________________________________________
>>>   llvm-commits mailing list
>>>   llvm-commits at cs.uiuc.edu
>>>   http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From baldrick at free.fr  Sun Oct 30 04:04:28 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 30 Oct 2011 10:04:28 +0100
Subject: [llvm-commits] [llvm] r143214 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp
 test/Transforms/InstSimplify/compare.ll
In-Reply-To: <CAJdarcGim2JVGaDMihFNePMY6m+rEWHNoeX+UtXh-kuejLudtg@mail.gmail.com>
References: <20111028190121.1A318312800A@llvm.org>
	<CAJdarcGim2JVGaDMihFNePMY6m+rEWHNoeX+UtXh-kuejLudtg@mail.gmail.com>
Message-ID: <4EAD131C.4050507@free.fr>

Hi Eli,

> This appears to be causing a miscompile on
> MultiSource/Benchmarks/mediabench/gsm/toast, among other things.

I don't see a miscompilation of toast.  Do you have any other examples?

Thanks, Duncan.

From baldrick at free.fr  Sat Oct 29 14:12:15 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sat, 29 Oct 2011 21:12:15 +0200
Subject: [llvm-commits] [llvm] r143214 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp
 test/Transforms/InstSimplify/compare.ll
In-Reply-To: <CAJdarcGU539ZpKwxss0JQn2eYCvQak1XrW+71_jHmBk6oiWsqg@mail.gmail.com>
References: <20111028190121.1A318312800A@llvm.org>	<CAJdarcGim2JVGaDMihFNePMY6m+rEWHNoeX+UtXh-kuejLudtg@mail.gmail.com>
	<CAJdarcGU539ZpKwxss0JQn2eYCvQak1XrW+71_jHmBk6oiWsqg@mail.gmail.com>
Message-ID: <4EAC500F.1040909@free.fr>

On 10/29/11 02:58, Eli Friedman wrote:
> On Fri, Oct 28, 2011 at 4:56 PM, Eli Friedman<eli.friedman at gmail.com>  wrote:
>> On Fri, Oct 28, 2011 at 12:01 PM, Duncan Sands<baldrick at free.fr>  wrote:
>>> Author: baldrick
>>> Date: Fri Oct 28 14:01:20 2011
>>> New Revision: 143214
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=143214&view=rev
>>> Log:
>>> The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
>>> Spotted by my super-optimizer in 186.crafty and 450.soplex.  We really
>>> need a proper infrastructure for handling generalizations of this kind
>>> of thing (which occur a lot), however this case is so simple that I decided
>>> to go ahead and implement it directly.
>>
>> This appears to be causing a miscompile on
>> MultiSource/Benchmarks/mediabench/gsm/toast, among other things.
>
> Reverted in r143265.

OK, thanks for reverting.  Sorry for the breakage.

Ciao, Duncan.

From karrenberg at cdl.uni-saarland.de  Fri Oct 28 07:30:02 2011
From: karrenberg at cdl.uni-saarland.de (Ralf Karrenberg)
Date: Fri, 28 Oct 2011 14:30:02 +0200 (MESZ)
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <1319802600.23036.632.camel@sapling>
Message-ID: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>

Hi Hal,

those numbers look very promising, great work! :)

Best,
Ralf

----- Original Message -----
> From: "Hal Finkel" <hfinkel at anl.gov>
> To: "Bruno Cardoso Lopes" <bruno.cardoso at gmail.com>
> Cc: llvm-commits at cs.uiuc.edu
> Sent: Freitag, 28. Oktober 2011 13:50:00
> Subject: Re: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
> 
> Bruno, et al.,
> 
> I've attached a new version of the patch that contains improvements
> (and
> a critical bug fix [the code output is not more right, but the pass
> in
> the older patch would crash in certain cases and now does not])
> compared
> to previous versions that I've posted.
> 
> First, these are preliminary results because I did not do the things
> necessary to make them real (explicitly quiet the machine, bind the
> processes to one cpu, etc.). But they should be good enough for
> discussion.
> 
> I'm using LLVM head r143101, with the attached patch applied, and
> clang
> head r143100 on an x86_64 machine (some kind of Intel Xeon). For the
> gcc
> comparison, I'm using build Ubuntu 4.4.3-4ubuntu5. gcc was run -O3
> without any other optimization flags. opt was run -vectorize
> -unroll-allow-partial -O3 with no other optimization flags (the patch
> adds the -vectorize option). llc was just given -O3.
> 
> It is not difficult to construct an example in which vectorization
> would
> be useful: take a loop that does more computation than load/stores,
> and
> (partially) unroll it. Here is a simple case:
> 
> #define ITER 5000
> #define NUM 200
> double a[NUM][NUM];
> double b[NUM][NUM];
> 
> ...
> 
> int main()
> {
> ...
> 
>   for (int i = 0; i < ITER; ++i) {
>     for (int x = 0; x < NUM; ++x)
>     for (int y = 0; y < NUM; ++y) {
>       double v = a[x][y], w = b[x][y];
>       double z1 = v*w;
>       double z2 = v+w;
>       double z3 = z1*z2;
>       double z4 = z3+v;
>       double z5 = z2+w;
>       double z6 = z4*z5;
>       double z7 = z4+z5;
>       a[x][y] = v*v-z6;
>       b[x][y] = w-z7;
>     }
>   }
> 
>  ...
> 
>   return 0;
> }
> 
> Results:
> gcc -03: 0m1.790s
> llvm -vectorize: 0m2.360s
> llvm: 0m2.780s
> gcc -fno-tree-vectorize: 0m2.810s
> (these are the user times after I've run enough for the times to
> settle
> to three decimal places)
> 
> So the vectorization gives a ~15% improvement in the running time.
> gcc's
> vectorization still does a much better job, however (yielding an ~36%
> improvement). So there is still work to do ;)
> 
> Additionally, I've checked the autovectorization on some classic
> numerical benchmarks from netlib. On these benchmarks, clang/llvm
> already do a good job compared to gcc (gcc is only about 10% better,
> and
> this is true regardless of whether gcc's vectorization is on or off).
> For these cases, autovectorization provides an insignificant speedup
> in
> most cases (but does not tend to make things worse, just not really
> any
> better either). Because gcc's vectorization also did not really help
> gcc
> in these cases, I'm not surprised. A good collection of these is
> available here:
> http://www.roylongbottom.org.uk/classic_benchmarks.tar.gz
> 
> I've yet to run the test suite using the pass to validate it. That is
> something that I plan to do. Actually, the "Livermore Loops" test in
> the
> aforementioned archive contains checksums to validate the results,
> and
> it looks like 1 or 2 of the loop results are wrong with vectorization
> turned on, so I'll have to investigate that.
> 
>  -Hal
> 
> On Wed, 2011-10-26 at 18:49 -0200, Bruno Cardoso Lopes wrote:
> > Hi Hal,
> > 
> > On Fri, Oct 21, 2011 at 7:04 PM, Hal Finkel <hfinkel at anl.gov>
> > wrote:
> > > I've attached an initial version of a basic-block
> > > autovectorization
> > > pass. It works by searching a basic block for pairable
> > > (independent)
> > > instructions, and, using a chain-seeking heuristic, selects
> > > pairings
> > > likely to provide an overall speedup (if such pairings can be
> > > found).
> > > The selected pairs are then fused and, if necessary, other
> > > instructions
> > > are moved in order to maintain data-flow consistency. This works
> > > only
> > > within one basic block, but can do loop vectorization in
> > > combination
> > > with (partial) unrolling. The basic idea was inspired by the
> > > Vienna MAP
> > > Vectorizor, which has been used to vectorize FFT kernels, but the
> > > algorithm used here is different.
> > >
> > > To try it, use -bb-vectorize with opt. There are a few options:
> > > -bb-vectorize-req-chain-depth: default: 3 -- The depth of the
> > > chain of
> > > instruction pairs necessary in order to consider the pairs that
> > > compose
> > > the chain worthy of vectorization.
> > > -bb-vectorize-vector-bits: default: 128 -- The size of the target
> > > vector
> > > registers
> > > -bb-vectorize-no-ints -- Don't consider integer instructions
> > > -bb-vectorize-no-floats -- Don't consider floating-point
> > > instructions
> > >
> > > The vectorizor generates a lot of insert_element/extract_element
> > > pairs;
> > > The assumption is that other passes will turn these into shuffles
> > > when
> > > possible (it looks like some work is necessary here). It will
> > > also
> > > vectorize vector instructions, and generates shuffles in this
> > > case
> > > (again, other passes should combine these as appropriate).
> > >
> > > Currently, it does not fuse load or store instructions, but that
> > > is a
> > > feature that I'd like to add. Of course, alignment information is
> > > an
> > > issue for load/store vectorization (or maybe I should just fuse
> > > them
> > > anyway and let isel deal with unaligned cases?).
> > >
> > > Also, support needs to be added for fusing known intrinsics (fma,
> > > etc.),
> > > and, as has been discussed on llvmdev, we should add some
> > > intrinsics to
> > > allow the generation of addsub-type instructions.
> > >
> > > I've included a few tests, but it needs more. Please review (I'll
> > > commit
> > > if and when everyone is happy).
> > >
> > > Thanks in advance,
> > > Hal
> > >
> > > P.S. There is another option (not so useful right now, but could
> > > be):
> > > -bb-vectorize-fast-dep -- Don't do a full inter-instruction
> > > dependency
> > > analysis; instead stop looking for instruction pairs after the
> > > first use
> > > of an instruction's value. [This makes the pass faster, but would
> > > require a data-dependence-based reordering pass in order to be
> > > effective].
> > 
> > Cool! :)
> > Have you run this pass with any benchmark or the llvm testsuite?
> > Does
> > it presents any regression?
> > Do you have any performance results?
> > Cheers,
> > 
> 
> --
> Hal Finkel
> Postdoctoral Appointee
> Leadership Computing Facility
> Argonne National Laboratory
> 
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