From craig.topper at gmail.com Mon Nov 7 02:26:24 2011 From: craig.topper at gmail.com (Craig Topper) Date: Mon, 07 Nov 2011 08:26:24 -0000 Subject: [llvm-commits] [llvm] r143915 - in /llvm/trunk: include/llvm/IntrinsicsX86.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx2-intrinsics-x86.ll Message-ID: <20111107082624.DFCDC2A6C12C@llvm.org> Author: ctopper Date: Mon Nov 7 02:26:24 2011 New Revision: 143915 URL: http://llvm.org/viewvc/llvm-project?rev=143915&view=rev Log: Add AVX2 variable shift instructions and intrinsics. Modified: llvm/trunk/include/llvm/IntrinsicsX86.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=143915&r1=143914&r2=143915&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Mon Nov 7 02:26:24 2011 @@ -1771,6 +1771,42 @@ Intrinsic<[], [llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i64_ty], []>; } +// Variable bit shift ops +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_avx2_psllv_d : GCCBuiltin<"__builtin_ia32_psllv4si">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], + [IntrNoMem]>; + def int_x86_avx2_psllv_d_256 : GCCBuiltin<"__builtin_ia32_psllv8si">, + Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty], + [IntrNoMem]>; + def int_x86_avx2_psllv_q : GCCBuiltin<"__builtin_ia32_psllv2di">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], + [IntrNoMem]>; + def int_x86_avx2_psllv_q_256 : GCCBuiltin<"__builtin_ia32_psllv4di">, + Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty], + [IntrNoMem]>; + + def int_x86_avx2_psrlv_d : GCCBuiltin<"__builtin_ia32_psrlv4si">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], + [IntrNoMem]>; + def int_x86_avx2_psrlv_d_256 : GCCBuiltin<"__builtin_ia32_psrlv8si">, + Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty], + [IntrNoMem]>; + def int_x86_avx2_psrlv_q : GCCBuiltin<"__builtin_ia32_psrlv2di">, + Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], + [IntrNoMem]>; + def int_x86_avx2_psrlv_q_256 : GCCBuiltin<"__builtin_ia32_psrlv4di">, + Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty], + [IntrNoMem]>; + + def int_x86_avx2_psrav_d : GCCBuiltin<"__builtin_ia32_psrav4si">, + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], + [IntrNoMem]>; + def int_x86_avx2_psrav_d_256 : GCCBuiltin<"__builtin_ia32_psrav8si">, + Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty], + [IntrNoMem]>; +} + // Misc. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_avx2_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb256">, Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=143915&r1=143914&r2=143915&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Nov 7 02:26:24 2011 @@ -7601,3 +7601,43 @@ int_x86_avx2_maskstore_q, int_x86_avx2_maskstore_q_256, memopv2i64, memopv4i64>, VEX_W; + + +//===----------------------------------------------------------------------===// +// Variable Bit Shifts +// +multiclass avx2_var_shift opc, string OpcodeStr, + PatFrag pf128, PatFrag pf256, + Intrinsic Int128, Intrinsic Int256> { + def rr : AVX28I, VEX_4V; + def rm : AVX28I, + VEX_4V; + def Yrr : AVX28I, VEX_4V; + def Yrm : AVX28I, + VEX_4V; +} + +defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", memopv4i32, memopv8i32, + int_x86_avx2_psllv_d, int_x86_avx2_psllv_d_256>; +defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", memopv2i64, memopv4i64, + int_x86_avx2_psllv_q, int_x86_avx2_psllv_q_256>, + VEX_W; +defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", memopv4i32, memopv8i32, + int_x86_avx2_psrlv_d, int_x86_avx2_psrlv_d_256>; +defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", memopv2i64, memopv4i64, + int_x86_avx2_psrlv_q, int_x86_avx2_psrlv_q_256>, + VEX_W; +defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", memopv4i32, memopv8i32, + int_x86_avx2_psrav_d, int_x86_avx2_psrav_d_256>; Modified: llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll?rev=143915&r1=143914&r2=143915&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll Mon Nov 7 02:26:24 2011 @@ -966,3 +966,83 @@ ret void } declare void @llvm.x86.avx2.maskstore.d.256(i8*, <8 x i32>, <8 x i32>) nounwind + + +define <4 x i32> @test_x86_avx2_psllv_d(<4 x i32> %a0, <4 x i32> %a1) { + ; CHECK: vpsllvd + %res = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] + ret <4 x i32> %res +} +declare <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32>, <4 x i32>) nounwind readnone + + +define <8 x i32> @test_x86_avx2_psllv_d_256(<8 x i32> %a0, <8 x i32> %a1) { + ; CHECK: vpsllvd + %res = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1] + ret <8 x i32> %res +} +declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>) nounwind readnone + + +define <2 x i64> @test_x86_avx2_psllv_q(<2 x i64> %a0, <2 x i64> %a1) { + ; CHECK: vpsllvq + %res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] + ret <2 x i64> %res +} +declare <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64>, <2 x i64>) nounwind readnone + + +define <4 x i64> @test_x86_avx2_psllv_q_256(<4 x i64> %a0, <4 x i64> %a1) { + ; CHECK: vpsllvq + %res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1] + ret <4 x i64> %res +} +declare <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64>, <4 x i64>) nounwind readnone + + +define <4 x i32> @test_x86_avx2_psrlv_d(<4 x i32> %a0, <4 x i32> %a1) { + ; CHECK: vpsrlvd + %res = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] + ret <4 x i32> %res +} +declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>) nounwind readnone + + +define <8 x i32> @test_x86_avx2_psrlv_d_256(<8 x i32> %a0, <8 x i32> %a1) { + ; CHECK: vpsrlvd + %res = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1] + ret <8 x i32> %res +} +declare <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32>, <8 x i32>) nounwind readnone + + +define <2 x i64> @test_x86_avx2_psrlv_q(<2 x i64> %a0, <2 x i64> %a1) { + ; CHECK: vpsrlvq + %res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] + ret <2 x i64> %res +} +declare <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64>, <2 x i64>) nounwind readnone + + +define <4 x i64> @test_x86_avx2_psrlv_q_256(<4 x i64> %a0, <4 x i64> %a1) { + ; CHECK: vpsrlvq + %res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1] + ret <4 x i64> %res +} +declare <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64>, <4 x i64>) nounwind readnone + + +define <4 x i32> @test_x86_avx2_psrav_d(<4 x i32> %a0, <4 x i32> %a1) { + ; CHECK: vpsravd + %res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] + ret <4 x i32> %res +} +declare <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32>, <4 x i32>) nounwind readnone + + +define <8 x i32> @test_x86_avx2_psrav_d_256(<8 x i32> %a0, <8 x i32> %a1) { + ; CHECK: vpsravd + %res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1] + ret <8 x i32> %res +} +declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone From elena.demikhovsky at intel.com Mon Nov 7 02:08:18 2011 From: elena.demikhovsky at intel.com (Demikhovsky, Elena) Date: Mon, 7 Nov 2011 10:08:18 +0200 Subject: [llvm-commits] AVX1 Code Generation - VSHUFP extension Message-ID: <7CB6AC5AED596245A99BF3213DE8F4AA02FFEA3063@hasmsx504.ger.corp.intel.com> Hello, I added several lines in X86 code generator that allow to choose VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask. I extended the existing lit test. Please review. Thanks. - Elena --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: vshufp.diff Type: application/octet-stream Size: 3585 bytes Desc: vshufp.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111107/89a2db5a/attachment.obj From chenwj at iis.sinica.edu.tw Mon Nov 7 02:28:11 2011 From: chenwj at iis.sinica.edu.tw (=?utf-8?B?6Zmz6Z+L5Lu7?=) Date: Mon, 7 Nov 2011 16:28:11 +0800 Subject: [llvm-commits] [PATCH][docs/GettingStarted.html] Add git imap config for Traditional Chinese GMail account In-Reply-To: References: <20111105091029.GA48964@cs.nctu.edu.tw> Message-ID: <20111107082811.GA91687@cs.nctu.edu.tw> > Applied in r143862. I am afraid the section might grow like "the > Universal Expo". :p I think we can add instructions which tell people how to get the imap utf-7 encoding of their GMail Draft mail box. For example, http://search.cpan.org/~pmakholm/Encode-IMAPUTF7-1.05/lib/Encode/IMAPUTF7.pm What do you think? Regards, chenwj -- Wei-Ren Chen (???) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 From echristo at apple.com Mon Nov 7 03:18:32 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 09:18:32 -0000 Subject: [llvm-commits] [llvm] r143918 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Message-ID: <20111107091833.08D4C2A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 03:18:32 2011 New Revision: 143918 URL: http://llvm.org/viewvc/llvm-project?rev=143918&view=rev Log: Typo. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=143918&r1=143917&r2=143918&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Mon Nov 7 03:18:32 2011 @@ -29,7 +29,7 @@ class DbgVariable; //===----------------------------------------------------------------------===// -/// CompileUnit - This dwarf writer support class manages information associate +/// CompileUnit - This dwarf writer support class manages information associated /// with a source file. class CompileUnit { /// ID - File identifier for source. From echristo at apple.com Mon Nov 7 03:18:35 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 09:18:35 -0000 Subject: [llvm-commits] [llvm] r143919 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20111107091835.E45C12A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 03:18:35 2011 New Revision: 143919 URL: http://llvm.org/viewvc/llvm-project?rev=143919&view=rev Log: Fix up comment. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=143919&r1=143918&r2=143919&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 7 03:18:35 2011 @@ -1744,7 +1744,7 @@ for (DenseMap::iterator I = CUMap.begin(), E = CUMap.end(); I != E; ++I) { CompileUnit *TheCU = I->second; - // Start the dwarf pubnames section. + // Start the dwarf pubtypes section. Asm->OutStreamer.SwitchSection( Asm->getObjFileLowering().getDwarfPubTypesSection()); Asm->OutStreamer.AddComment("Length of Public Types Info"); From echristo at apple.com Mon Nov 7 03:18:38 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 09:18:38 -0000 Subject: [llvm-commits] [llvm] r143920 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h Message-ID: <20111107091838.EDDE72A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 03:18:38 2011 New Revision: 143920 URL: http://llvm.org/viewvc/llvm-project?rev=143920&view=rev Log: Expose a way to get the beginning of the dwarf string section. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=143920&r1=143919&r2=143920&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 7 03:18:38 2011 @@ -136,6 +136,18 @@ DwarfDebug::~DwarfDebug() { } +/// EmitSectionSym - Switch to the specified MCSection and emit an assembler +/// temporary label to it if SymbolStem is specified. +static MCSymbol *EmitSectionSym(AsmPrinter *Asm, const MCSection *Section, + const char *SymbolStem = 0) { + Asm->OutStreamer.SwitchSection(Section); + if (!SymbolStem) return 0; + + MCSymbol *TmpSym = Asm->GetTempSymbol(SymbolStem); + Asm->OutStreamer.EmitLabel(TmpSym); + return TmpSym; +} + MCSymbol *DwarfDebug::getStringPool() { return Asm->GetTempSymbol("section_str"); } @@ -148,6 +160,13 @@ return Entry.first = Asm->GetTempSymbol("string", Entry.second); } +MCSymbol *DwarfDebug::getDwarfStrSectionSym(void) { + if (DwarfStrSectionSym) return DwarfStrSectionSym; + DwarfStrSectionSym = + EmitSectionSym(Asm, Asm->getObjFileLowering().getDwarfStrSection(), + "section_str"); + return DwarfStrSectionSym; +} /// assignAbbrevNumber - Define a unique number for the abbreviation. /// @@ -1465,18 +1484,6 @@ } } -/// EmitSectionSym - Switch to the specified MCSection and emit an assembler -/// temporary label to it if SymbolStem is specified. -static MCSymbol *EmitSectionSym(AsmPrinter *Asm, const MCSection *Section, - const char *SymbolStem = 0) { - Asm->OutStreamer.SwitchSection(Section); - if (!SymbolStem) return 0; - - MCSymbol *TmpSym = Asm->GetTempSymbol(SymbolStem); - Asm->OutStreamer.EmitLabel(TmpSym); - return TmpSym; -} - /// EmitSectionLabels - Emit initial Dwarf sections with a label at /// the start of each one. void DwarfDebug::EmitSectionLabels() { Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=143920&r1=143919&r2=143920&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Nov 7 03:18:38 2011 @@ -513,6 +513,10 @@ /// getStringPoolEntry - returns an entry into the string pool with the given /// string text. MCSymbol *getStringPoolEntry(StringRef Str); + + /// getDwarfStrSectionSym - returns the symbol that starts the dwarf string + /// section. + MCSymbol *getDwarfStrSectionSym(); }; } // End of namespace llvm From echristo at apple.com Mon Nov 7 03:18:42 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 09:18:42 -0000 Subject: [llvm-commits] [llvm] r143921 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfAccelTable.cpp DwarfAccelTable.h Message-ID: <20111107091842.4FB7E3524001@llvm.org> Author: echristo Date: Mon Nov 7 03:18:42 2011 New Revision: 143921 URL: http://llvm.org/viewvc/llvm-project?rev=143921&view=rev Log: Add a new dwarf accelerator table prototype with the goal of replacing the pubnames and pubtypes tables. LLDB can currently use this format and a full spec is forthcoming and submission for standardization is planned. A basic summary: The dwarf accelerator tables are an indirect hash table optimized for null lookup rather than access to known data. They are output into an on-disk format that looks like this: .-------------. | HEADER | |-------------| | BUCKETS | |-------------| | HASHES | |-------------| | OFFSETS | |-------------| | DATA | `-------------' where the header contains a magic number, version, type of hash function, the number of buckets, total number of hashes, and room for a special struct of data and the length of that struct. The buckets contain an index (e.g. 6) into the hashes array. The hashes section contains all of the 32-bit hash values in contiguous memory, and the offsets contain the offset into the data area for the particular hash. For a lookup example, we could hash a function name and take it modulo the number of buckets giving us our bucket. From there we take the bucket value as an index into the hashes table and look at each successive hash as long as the hash value is still the same modulo result (bucket value) as earlier. If we have a match we look at that same entry in the offsets table and grab the offset in the data for our final match. Added: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Added: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp?rev=143921&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp (added) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Mon Nov 7 03:18:42 2011 @@ -0,0 +1,250 @@ +//=-- llvm/CodeGen/DwarfAccelTable.cpp - Dwarf Accelerator Tables -*- C++ -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains support for writing dwarf accelerator tables. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/Support/Debug.h" +#include "DwarfAccelTable.h" +#include "DwarfDebug.h" +#include "DIE.h" + +using namespace llvm; + +const char *DwarfAccelTable::Atom::AtomTypeString(enum AtomType AT) { + switch (AT) { + default: llvm_unreachable("invalid AtomType!"); + case eAtomTypeNULL: return "eAtomTypeNULL"; + case eAtomTypeDIEOffset: return "eAtomTypeDIEOffset"; + case eAtomTypeCUOffset: return "eAtomTypeCUOffset"; + case eAtomTypeTag: return "eAtomTypeTag"; + case eAtomTypeNameFlags: return "eAtomTypeNameFlags"; + case eAtomTypeTypeFlags: return "eAtomTypeTypeFlags"; + } +} + +// The general case would need to have a less hard coded size for the +// length of the HeaderData, however, if we're constructing based on a +// single Atom then we know it will always be: 4 + 4 + 2 + 2. +DwarfAccelTable::DwarfAccelTable(DwarfAccelTable::Atom atom) : + Header(12), + HeaderData(atom) { +} + +void DwarfAccelTable::AddName(StringRef Name, DIE* die) { + // If the string is in the list already then add this die to the list + // otherwise add a new one. + DIEArray &DIEs = Entries[Name]; + DIEs.push_back(die); +} + +void DwarfAccelTable::ComputeBucketCount(void) { + // First get the number of unique hashes. + std::vector uniques; + uniques.resize(Data.size()); + for (size_t i = 0; i < Data.size(); ++i) + uniques[i] = Data[i]->HashValue; + std::sort(uniques.begin(), uniques.end()); + std::vector::iterator p = + std::unique(uniques.begin(), uniques.end()); + uint32_t num = std::distance(uniques.begin(), p); + + // Then compute the bucket size, minimum of 1 bucket. + if (num > 1024) Header.bucket_count = num/4; + if (num > 16) Header.bucket_count = num/2; + else Header.bucket_count = num > 0 ? num : 1; + + Header.hashes_count = num; +} + +void DwarfAccelTable::FinalizeTable(AsmPrinter *Asm, const char *Prefix) { + // Create the individual hash data outputs. + for (StringMap::const_iterator + EI = Entries.begin(), EE = Entries.end(); EI != EE; ++EI) { + struct HashData *Entry = new HashData((*EI).getKeyData()); + for (DIEArray::const_iterator DI = (*EI).second.begin(), + DE = (*EI).second.end(); + DI != DE; ++DI) + Entry->addOffset((*DI)->getOffset()); + Data.push_back(Entry); + } + + // Figure out how many buckets we need, then compute the bucket + // contents and the final ordering. We'll emit the hashes and offsets + // by doing a walk during the emission phase. We add temporary + // symbols to the data so that we can reference them during the offset + // later, we'll emit them when we emit the data. + ComputeBucketCount(); + + // Compute bucket contents and final ordering. + Buckets.resize(Header.bucket_count); + for (size_t i = 0; i < Data.size(); ++i) { + uint32_t bucket = Data[i]->HashValue % Header.bucket_count; + Buckets[bucket].push_back(Data[i]); + Data[i]->Sym = Asm->GetTempSymbol(Prefix, i); + } +} + +// Emits the header for the table via the AsmPrinter. +void DwarfAccelTable::EmitHeader(AsmPrinter *Asm) { + Asm->OutStreamer.AddComment("Header Magic"); + Asm->EmitInt32(Header.magic); + Asm->OutStreamer.AddComment("Header Version"); + Asm->EmitInt16(Header.version); + Asm->OutStreamer.AddComment("Header Hash Function"); + Asm->EmitInt16(Header.hash_function); + Asm->OutStreamer.AddComment("Header Bucket Count"); + Asm->EmitInt32(Header.bucket_count); + Asm->OutStreamer.AddComment("Header Hash Count"); + Asm->EmitInt32(Header.hashes_count); + Asm->OutStreamer.AddComment("Header Data Length"); + Asm->EmitInt32(Header.header_data_len); + Asm->OutStreamer.AddComment("HeaderData Die Offset Base"); + Asm->EmitInt32(HeaderData.die_offset_base); + Asm->OutStreamer.AddComment("HeaderData Atom Count"); + Asm->EmitInt32(HeaderData.Atoms.size()); + for (size_t i = 0; i < HeaderData.Atoms.size(); i++) { + Atom A = HeaderData.Atoms[i]; + Asm->OutStreamer.AddComment(Atom::AtomTypeString(A.type)); + Asm->EmitInt16(A.type); + Asm->OutStreamer.AddComment(dwarf::FormEncodingString(A.form)); + Asm->EmitInt16(A.form); + } +} + +// Walk through and emit the buckets for the table. This will look +// like a list of numbers of how many elements are in each bucket. +void DwarfAccelTable::EmitBuckets(AsmPrinter *Asm) { + unsigned index = 0; + for (size_t i = 0; i < Buckets.size(); ++i) { + Twine Comment = Twine("Bucket ") + Twine(i); + Asm->OutStreamer.AddComment(Comment); + if (Buckets[i].size() != 0) + Asm->EmitInt32(index); + else + Asm->EmitInt32(UINT32_MAX); + index += Buckets[i].size(); + } +} + +// Walk through the buckets and emit the individual hashes for each +// bucket. +void DwarfAccelTable::EmitHashes(AsmPrinter *Asm) { + for (size_t i = 0; i < Buckets.size(); ++i) { + for (HashList::const_iterator HI = Buckets[i].begin(), + HE = Buckets[i].end(); HI != HE; ++HI) { + Twine Comment = Twine("Hash in Bucket ") + Twine(i); + Asm->OutStreamer.AddComment(Comment); + Asm->EmitInt32((*HI)->HashValue); + } + } +} + +// Walk through the buckets and emit the individual offsets for each +// element in each bucket. This is done via a symbol subtraction from the +// beginning of the section. The non-section symbol will be output later +// when we emit the actual data. +void DwarfAccelTable::EmitOffsets(AsmPrinter *Asm, MCSymbol *SecBegin) { + for (size_t i = 0; i < Buckets.size(); ++i) { + for (HashList::const_iterator HI = Buckets[i].begin(), + HE = Buckets[i].end(); HI != HE; ++HI) { + Twine Comment = Twine("Offset in Bucket ") + Twine(i); + Asm->OutStreamer.AddComment(Comment); + MCContext &Context = Asm->OutStreamer.getContext(); + const MCExpr *Sub = + MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create((*HI)->Sym, Context), + MCSymbolRefExpr::Create(SecBegin, Context), + Context); + Asm->OutStreamer.EmitValue(Sub, sizeof(uint32_t), 0); + } + } +} + +// Walk through the buckets and emit the full data for each element in +// the bucket. For the string case emit the dies and the various offsets. +// Terminate each HashData bucket with 0. +void DwarfAccelTable::EmitData(AsmPrinter *Asm, DwarfDebug *D) { + uint64_t PrevHash = UINT64_MAX; + for (size_t i = 0; i < Buckets.size(); ++i) { + for (HashList::const_iterator HI = Buckets[i].begin(), + HE = Buckets[i].end(); HI != HE; ++HI) { + // Remember to emit the label for our offset. + Asm->OutStreamer.EmitLabel((*HI)->Sym); + Asm->OutStreamer.AddComment((*HI)->Str); + Asm->EmitSectionOffset(D->getStringPoolEntry((*HI)->Str), + D->getDwarfStrSectionSym()); + Asm->OutStreamer.AddComment("Num DIEs"); + Asm->EmitInt32((*HI)->DIEOffsets.size()); + for (std::vector::const_iterator + DI = (*HI)->DIEOffsets.begin(), DE = (*HI)->DIEOffsets.end(); + DI != DE; ++DI) { + Asm->EmitInt32((*DI)); + } + // Emit a 0 to terminate the data unless we have a hash collision. + if (PrevHash != (*HI)->HashValue) + Asm->EmitInt32(0); + PrevHash = (*HI)->HashValue; + } + } +} + +// Emit the entire data structure to the output file. +void DwarfAccelTable::Emit(AsmPrinter *Asm, MCSymbol *SecBegin, + DwarfDebug *D) { + // Emit the header. + EmitHeader(Asm); + + // Emit the buckets. + EmitBuckets(Asm); + + // Emit the hashes. + EmitHashes(Asm); + + // Emit the offsets. + EmitOffsets(Asm, SecBegin); + + // Emit the hash data. + EmitData(Asm, D); +} + +#ifndef NDEBUG +void DwarfAccelTable::print(raw_ostream &O) { + + Header.print(O); + HeaderData.print(O); + + O << "Entries: \n"; + for (StringMap::const_iterator + EI = Entries.begin(), EE = Entries.end(); EI != EE; ++EI) { + O << "Name: " << (*EI).getKeyData() << "\n"; + for (DIEArray::const_iterator DI = (*EI).second.begin(), + DE = (*EI).second.end(); + DI != DE; ++DI) + (*DI)->print(O); + } + + O << "Buckets and Hashes: \n"; + for (size_t i = 0; i < Buckets.size(); ++i) + for (HashList::const_iterator HI = Buckets[i].begin(), + HE = Buckets[i].end(); HI != HE; ++HI) + (*HI)->print(O); + + O << "Data: \n"; + for (std::vector::const_iterator + DI = Data.begin(), DE = Data.end(); DI != DE; ++DI) + (*DI)->print(O); + + +} +#endif Added: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h?rev=143921&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h (added) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Mon Nov 7 03:18:42 2011 @@ -0,0 +1,254 @@ +//==-- llvm/CodeGen/DwarfAccelTable.h - Dwarf Accelerator Tables -*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains support for writing dwarf accelerator tables. +// +//===----------------------------------------------------------------------===// + +#ifndef CODEGEN_ASMPRINTER_DWARFACCELTABLE_H__ +#define CODEGEN_ASMPRINTER_DWARFACCELTABLE_H__ + +#include "llvm/ADT/StringMap.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/Support/Dwarf.h" +#include "llvm/Support/DataTypes.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/Format.h" +#include "llvm/Support/FormattedStream.h" +#include +#include + +// The apple dwarf accelerator tables are an indirect hash table optimized +// for null lookup rather than access to known data. They are output into +// an on-disk format that looks like this: +// +// .-------------. +// | HEADER | +// |-------------| +// | BUCKETS | +// |-------------| +// | HASHES | +// |-------------| +// | OFFSETS | +// |-------------| +// | DATA | +// `-------------' +// +// where the header contains a magic number, version, type of hash function, +// the number of buckets, total number of hashes, and room for a special +// struct of data and the length of that struct. +// +// The buckets contain an index (e.g. 6) into the hashes array. The hashes +// section contains all of the 32-bit hash values in contiguous memory, and +// the offsets contain the offset into the data area for the particular +// hash. +// +// For a lookup example, we could hash a function name and take it modulo the +// number of buckets giving us our bucket. From there we take the bucket value +// as an index into the hashes table and look at each successive hash as long +// as the hash value is still the same modulo result (bucket value) as earlier. +// If we have a match we look at that same entry in the offsets table and +// grab the offset in the data for our final match. + +namespace llvm { + +class AsmPrinter; +class DIE; +class DwarfDebug; + +class DwarfAccelTable { + + enum HashFunctionType { + eHashFunctionDJB = 0u + }; + + static uint32_t HashDJB (const char *s) { + uint32_t h = 5381; + for (unsigned char c = *s; c; c = *++s) + h = ((h << 5) + h) + c; + return h; + } + + // Helper function to compute the number of buckets needed based on + // the number of unique hashes. + void ComputeBucketCount (void); + + struct TableHeader { + uint32_t magic; // 'HASH' magic value to allow endian detection + uint16_t version; // Version number. + uint16_t hash_function; // The hash function enumeration that was used. + uint32_t bucket_count; // The number of buckets in this hash table. + uint32_t hashes_count; // The total number of unique hash values + // and hash data offsets in this table. + uint32_t header_data_len; // The bytes to skip to get to the hash + // indexes (buckets) for correct alignment. + // Also written to disk is the implementation specific header data. + + static const uint32_t MagicHash = 0x48415348; + + TableHeader (uint32_t data_len) : + magic (MagicHash), version (1), hash_function (eHashFunctionDJB), + bucket_count (0), hashes_count (0), header_data_len (data_len) + {}; + +#ifndef NDEBUG + void print(raw_ostream &O) { + O << "Magic: " << format("0x%x", magic) << "\n" + << "Version: " << version << "\n" + << "Hash Function: " << hash_function << "\n" + << "Bucket Count: " << bucket_count << "\n" + << "Header Data Length: " << header_data_len << "\n"; + } + void dump() { print(dbgs()); } +#endif + }; + +public: + // The HeaderData describes the form of each set of data. In general this + // is as a list of atoms (atom_count) where each atom contains a type + // (AtomType type) of data, and an encoding form (form). In the case of + // data that is referenced via DW_FORM_ref_* the die_offset_base is + // used to describe the offset for all forms in the list of atoms. + // This also serves as a public interface of sorts. + // When written to disk this will have the form: + // + // uint32_t die_offset_base + // uint32_t atom_count + // atom_count Atoms + enum AtomType { + eAtomTypeNULL = 0u, + eAtomTypeDIEOffset = 1u, // DIE offset, check form for encoding + eAtomTypeCUOffset = 2u, // DIE offset of the compiler unit header that + // contains the item in question + eAtomTypeTag = 3u, // DW_TAG_xxx value, should be encoded as + // DW_FORM_data1 (if no tags exceed 255) or + // DW_FORM_data2. + eAtomTypeNameFlags = 4u, // Flags from enum NameFlags + eAtomTypeTypeFlags = 5u // Flags from enum TypeFlags + }; + + // Make these public so that they can be used as a general interface to + // the class. + struct Atom { + AtomType type; // enum AtomType + uint16_t form; // DWARF DW_FORM_ defines + + Atom(AtomType type, uint16_t form) : type(type), form(form) {}; + static const char * AtomTypeString(enum AtomType); +#ifndef NDEBUG + void print(raw_ostream &O) { + O << "Type: " << dwarf::TagString(type) << "\n" + << "Form: " << dwarf::FormEncodingString(form) << "\n"; + } + void dump() { + print(dbgs()); + } +#endif + }; + + private: + struct TableHeaderData { + + uint32_t die_offset_base; + std::vector Atoms; + + TableHeaderData(DwarfAccelTable::Atom Atom, uint32_t offset = 0) + : die_offset_base(offset) { + Atoms.push_back(Atom); + } + +#ifndef NDEBUG + void print (raw_ostream &O) { + O << "die_offset_base: " << die_offset_base << "\n"; + for (size_t i = 0; i < Atoms.size(); i++) + Atoms[i].print(O); + } + void dump() { + print(dbgs()); + } +#endif + }; + + // The data itself consists of a str_offset (to deal with collisions in + // some magical way? this looks like the KeyType from the spec, which + // should mean an integer compare on read), a count of the DIEs in the + // hash and the offsets to the DIEs themselves. + // On disk each data section is ended with a 0 KeyType as the end of the + // hash chain. + // On output this looks like: + // uint32_t str_offset + // uint32_t hash_data_count + // HashData[hash_data_count] + struct HashData { + StringRef Str; + uint32_t HashValue; + MCSymbol *Sym; + std::vector DIEOffsets; // offsets + HashData(StringRef S) : Str(S) { + HashValue = DwarfAccelTable::HashDJB(S.str().c_str()); + } + void addOffset(uint32_t off) { DIEOffsets.push_back(off); } + #ifndef NDEBUG + void print(raw_ostream &O) { + O << "Name: " << Str << "\n"; + O << " Hash Value: " << format("0x%x", HashValue) << "\n"; + O << " Symbol: " ; + if (Sym) Sym->print(O); + else O << ""; + O << "\n"; + for (size_t i = 0; i < DIEOffsets.size(); i++) + O << " Offset: " << DIEOffsets[i] << "\n"; + } + void dump() { + print(dbgs()); + } + #endif + }; + + DwarfAccelTable(const DwarfAccelTable&); // DO NOT IMPLEMENT + void operator=(const DwarfAccelTable&); // DO NOT IMPLEMENT + + // Internal Functions + void EmitHeader(AsmPrinter *); + void EmitBuckets(AsmPrinter *); + void EmitHashes(AsmPrinter *); + void EmitOffsets(AsmPrinter *, MCSymbol *); + void EmitData(AsmPrinter *, DwarfDebug *D); + + // Output Variables + TableHeader Header; + TableHeaderData HeaderData; + std::vector Data; + + // String Data + typedef std::vector DIEArray; + typedef StringMap StringEntries; + StringEntries Entries; + + // Buckets/Hashes/Offsets + typedef std::vector HashList; + typedef std::vector BucketList; + BucketList Buckets; + HashList Hashes; + + // Public Implementation + public: + DwarfAccelTable(DwarfAccelTable::Atom Atom); + void AddName(StringRef, DIE*); + void FinalizeTable(AsmPrinter *, const char *); + void Emit(AsmPrinter *, MCSymbol *, DwarfDebug *); +#ifndef NDEBUG + void print(raw_ostream &O); + void dump() { print(dbgs()); } +#endif +}; + +} +#endif From echristo at apple.com Mon Nov 7 03:24:32 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 09:24:32 -0000 Subject: [llvm-commits] [llvm] r143923 - in /llvm/trunk: include/llvm/MC/MCObjectFileInfo.h lib/CodeGen/AsmPrinter/DwarfAccelTable.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp lib/CodeGen/AsmPrinter/DwarfCompileUnit.h lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/AsmPrinter/DwarfDebug.h lib/MC/MCObjectFileInfo.cpp Message-ID: <20111107092432.B3D972A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 03:24:32 2011 New Revision: 143923 URL: http://llvm.org/viewvc/llvm-project?rev=143923&view=rev Log: Add the support code to enable the dwarf accelerator tables. Upcoming patches to fix the types section (all types, not just global types), and testcases. The code to do the final emission is disabled by default. Modified: llvm/trunk/include/llvm/MC/MCObjectFileInfo.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h llvm/trunk/lib/MC/MCObjectFileInfo.cpp Modified: llvm/trunk/include/llvm/MC/MCObjectFileInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectFileInfo.h?rev=143923&r1=143922&r2=143923&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCObjectFileInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCObjectFileInfo.h Mon Nov 7 03:24:32 2011 @@ -82,6 +82,14 @@ /// this is the section to emit them into. const MCSection *CompactUnwindSection; + /// DwarfAccelNamesSection, DwarfAccelObjCSection + /// If we use the DWARF accelerated hash tables then we want toe emit these + /// sections. + const MCSection *DwarfAccelNamesSection; + const MCSection *DwarfAccelObjCSection; + const MCSection *DwarfAccelNamespaceSection; + const MCSection *DwarfAccelTypesSection; + // Dwarf sections for debug info. If a target supports debug info, these must // be set. const MCSection *DwarfAbbrevSection; @@ -187,6 +195,18 @@ const MCSection *getCompactUnwindSection() const{ return CompactUnwindSection; } + const MCSection *getDwarfAccelNamesSection() const { + return DwarfAccelNamesSection; + } + const MCSection *getDwarfAccelObjCSection() const { + return DwarfAccelObjCSection; + } + const MCSection *getDwarfAccelNamespaceSection() const { + return DwarfAccelNamespaceSection; + } + const MCSection *getDwarfAccelTypesSection() const { + return DwarfAccelTypesSection; + } const MCSection *getDwarfAbbrevSection() const { return DwarfAbbrevSection; } const MCSection *getDwarfInfoSection() const { return DwarfInfoSection; } const MCSection *getDwarfLineSection() const { return DwarfLineSection; } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h?rev=143923&r1=143922&r2=143923&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Mon Nov 7 03:24:32 2011 @@ -25,7 +25,7 @@ #include #include -// The apple dwarf accelerator tables are an indirect hash table optimized +// The dwarf accelerator tables are an indirect hash table optimized // for null lookup rather than access to known data. They are output into // an on-disk format that looks like this: // @@ -176,9 +176,7 @@ #endif }; - // The data itself consists of a str_offset (to deal with collisions in - // some magical way? this looks like the KeyType from the spec, which - // should mean an integer compare on read), a count of the DIEs in the + // The data itself consists of a str_offset, a count of the DIEs in the // hash and the offsets to the DIEs themselves. // On disk each data section is ended with a 0 KeyType as the end of the // hash chain. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=143923&r1=143922&r2=143923&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Mon Nov 7 03:24:32 2011 @@ -904,8 +904,11 @@ return NDie; NDie = new DIE(dwarf::DW_TAG_namespace); insertDIE(NS, NDie); - if (!NS.getName().empty()) + if (!NS.getName().empty()) { addString(NDie, dwarf::DW_AT_name, NS.getName()); + addAccelNamespace(NS.getName(), NDie); + } else + addAccelNamespace("(anonymous namespace)", NDie); addSourceLine(NDie, NS); addToContextOwner(NDie, NS.getContext()); return NDie; @@ -1078,7 +1081,9 @@ DIDescriptor GVContext = GV.getContext(); addToContextOwner(VariableDIE, GVContext); // Add location. + bool addToAccelTable = false; if (isGlobalVariable) { + addToAccelTable = true; DIEBlock *Block = new (DIEValueAllocator) DIEBlock(); addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_addr); addLabel(Block, 0, dwarf::DW_FORM_udata, @@ -1097,11 +1102,12 @@ addDie(VariableSpecDIE); } else { addBlock(VariableDIE, dwarf::DW_AT_location, 0, Block); - } + } } else if (const ConstantInt *CI = dyn_cast_or_null(GV.getConstant())) addConstantValue(VariableDIE, CI, GTy.isUnsignedDIType()); else if (const ConstantExpr *CE = getMergedGlobalExpr(N->getOperand(11))) { + addToAccelTable = true; // GV is a merged global. DIEBlock *Block = new (DIEValueAllocator) DIEBlock(); Value *Ptr = CE->getOperand(0); @@ -1116,6 +1122,9 @@ addBlock(VariableDIE, dwarf::DW_AT_location, 0, Block); } + if (addToAccelTable) + addAccelName(GV.getName(), VariableDIE); + return; } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=143923&r1=143922&r2=143923&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Mon Nov 7 03:24:32 2011 @@ -64,6 +64,13 @@ /// StringMap GlobalTypes; + /// AccelNames - A map of names for the name accelerator table. + /// + StringMap AccelNames; + StringMap > AccelObjC; + StringMap AccelNamespace; + StringMap AccelTypes; + /// DIEBlocks - A list of all the DIEBlocks in use. std::vector DIEBlocks; @@ -82,6 +89,13 @@ const StringMap &getGlobals() const { return Globals; } const StringMap &getGlobalTypes() const { return GlobalTypes; } + const StringMap &getAccelNames() const { return AccelNames; } + const StringMap > &getAccelObjC() const { + return AccelObjC; + } + const StringMap &getAccelNamespace() const { return AccelNamespace; } + const StringMap &getAccelTypes() const { return AccelTypes; } + /// hasContent - Return true if this compile unit has something to write out. /// bool hasContent() const { return !CUDie->getChildren().empty(); } @@ -94,6 +108,20 @@ /// void addGlobalType(DIType Ty); + + /// addAccelName - Add a new name to the name accelerator table. + void addAccelName(StringRef Name, DIE *Die) { AccelNames[Name] = Die; } + void addAccelObjC(StringRef Name, DIE *Die) { + std::vector &DIEs = AccelObjC[Name]; + DIEs.push_back(Die); + } + void addAccelNamespace(StringRef Name, DIE *Die) { + AccelNamespace[Name] = Die; + } + void addAccelType(StringRef Name, DIE *Die) { + AccelTypes[Name] = Die; + } + /// getDIE - Returns the debug information entry map slot for the /// specified debug variable. DIE *getDIE(const MDNode *N) { return MDNodeToDieMap.lookup(N); } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=143923&r1=143922&r2=143923&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 7 03:24:32 2011 @@ -14,6 +14,7 @@ #define DEBUG_TYPE "dwarfdebug" #include "DwarfDebug.h" #include "DIE.h" +#include "DwarfAccelTable.h" #include "DwarfCompileUnit.h" #include "llvm/Constants.h" #include "llvm/Module.h" @@ -52,6 +53,10 @@ cl::desc("Make an absence of debug location information explicit."), cl::init(false)); +static cl::opt DwarfAccelTables("dwarf-accel-tables", cl::Hidden, + cl::desc("Output prototype dwarf accelerator tables."), + cl::init(false)); + namespace { const char *DWARFGroupName = "DWARF Emission"; const char *DbgTimerName = "DWARF Debug Writer"; @@ -444,6 +449,9 @@ if (DS.isSubprogram()) TheCU->addPubTypes(DISubprogram(DS)); + if (DS.isSubprogram() && !Scope->isAbstractScope()) + TheCU->addAccelName(DISubprogram(DS).getName(), ScopeDIE); + return ScopeDIE; } @@ -524,6 +532,36 @@ return NewCU; } +static bool isObjCClass(StringRef Name) { + return Name[0] == '+' || Name[0] == '-'; +} + +static bool hasObjCCategory(StringRef Name) { + if (Name[0] != '+' && Name[0] != '-') + return false; + + size_t pos = Name.find(')'); + if (pos != std::string::npos) { + if (Name[pos+1] != ' ') return false; + return true; + } + + return false; +} + +static void getObjCClassCategory(StringRef In, StringRef &Class, + StringRef &Category) { + if (!hasObjCCategory(In)) { + Class = In.slice(In.find('[') + 1, In.find(' ')); + Category = ""; + return; + } + + Class = In.slice(In.find('[') + 1, In.find('(')); + Category = In.slice(In.find('[') + 1, In.find(' ')); + return; +} + /// construct SubprogramDIE - Construct subprogram DIE. void DwarfDebug::constructSubprogramDIE(CompileUnit *TheCU, const MDNode *N) { @@ -561,6 +599,18 @@ // Expose as global. TheCU->addGlobal(SP.getName(), SubprogramDie); + // Add to Accel Names + TheCU->addAccelName(SP.getName(), SubprogramDie); + + // If this is an Objective-C selector name add it to the ObjC accelerator too. + if (isObjCClass(SP.getName())) { + StringRef Class, Category; + getObjCClassCategory(SP.getName(), Class, Category); + TheCU->addAccelObjC(Class, SubprogramDie); + if (Category != "") + TheCU->addAccelObjC(Category, SubprogramDie); + } + return; } @@ -757,6 +807,14 @@ // Corresponding abbreviations into a abbrev section. emitAbbreviations(); + // Emit info into a dwarf accelerator table sections. + if (DwarfAccelTables) { + emitAccelNames(); + emitAccelObjC(); + emitAccelNamespaces(); + emitAccelTypes(); + } + // Emit info into a debug pubnames section. emitDebugPubNames(); @@ -1696,6 +1754,116 @@ Asm->EmitInt8(1); } +/// emitAccelNames - Emit visible names into a hashed accelerator table +/// section. +void DwarfDebug::emitAccelNames() { + DwarfAccelTable AT(DwarfAccelTable::Atom(DwarfAccelTable::eAtomTypeDIEOffset, + dwarf::DW_FORM_data4)); + for (DenseMap::iterator I = CUMap.begin(), + E = CUMap.end(); I != E; ++I) { + CompileUnit *TheCU = I->second; + const StringMap &Names = TheCU->getAccelNames(); + for (StringMap::const_iterator + GI = Names.begin(), GE = Names.end(); GI != GE; ++GI) { + const char *Name = GI->getKeyData(); + DIE *Entity = GI->second; + AT.AddName(Name, Entity); + } + } + + AT.FinalizeTable(Asm, "Names"); + Asm->OutStreamer.SwitchSection( + Asm->getObjFileLowering().getDwarfAccelNamesSection()); + MCSymbol *SectionBegin = Asm->GetTempSymbol("names_begin"); + Asm->OutStreamer.EmitLabel(SectionBegin); + + // Emit the full data. + AT.Emit(Asm, SectionBegin, this); +} + +/// emitAccelObjC - Emit objective C classes and categories into a hashed +/// accelerator table section. +void DwarfDebug::emitAccelObjC() { + DwarfAccelTable AT(DwarfAccelTable::Atom(DwarfAccelTable::eAtomTypeDIEOffset, + dwarf::DW_FORM_data4)); + for (DenseMap::iterator I = CUMap.begin(), + E = CUMap.end(); I != E; ++I) { + CompileUnit *TheCU = I->second; + const StringMap > &Names = TheCU->getAccelObjC(); + for (StringMap >::const_iterator + GI = Names.begin(), GE = Names.end(); GI != GE; ++GI) { + const char *Name = GI->getKeyData(); + std::vector Entities = GI->second; + for (std::vector::const_iterator DI = Entities.begin(), + DE = Entities.end(); DI != DE; ++DI) + AT.AddName(Name, (*DI)); + } + } + + AT.FinalizeTable(Asm, "ObjC"); + Asm->OutStreamer.SwitchSection(Asm->getObjFileLowering() + .getDwarfAccelObjCSection()); + MCSymbol *SectionBegin = Asm->GetTempSymbol("objc_begin"); + Asm->OutStreamer.EmitLabel(SectionBegin); + + // Emit the full data. + AT.Emit(Asm, SectionBegin, this); +} + +/// emitAccelNamespace - Emit namespace dies into a hashed accelerator +/// table. +void DwarfDebug::emitAccelNamespaces() { + DwarfAccelTable AT(DwarfAccelTable::Atom(DwarfAccelTable::eAtomTypeDIEOffset, + dwarf::DW_FORM_data4)); + for (DenseMap::iterator I = CUMap.begin(), + E = CUMap.end(); I != E; ++I) { + CompileUnit *TheCU = I->second; + const StringMap &Names = TheCU->getAccelNamespace(); + for (StringMap::const_iterator + GI = Names.begin(), GE = Names.end(); GI != GE; ++GI) { + const char *Name = GI->getKeyData(); + DIE *Entity = GI->second; + AT.AddName(Name, Entity); + } + } + + AT.FinalizeTable(Asm, "namespac"); + Asm->OutStreamer.SwitchSection(Asm->getObjFileLowering() + .getDwarfAccelNamespaceSection()); + MCSymbol *SectionBegin = Asm->GetTempSymbol("namespac_begin"); + Asm->OutStreamer.EmitLabel(SectionBegin); + + // Emit the full data. + AT.Emit(Asm, SectionBegin, this); +} + +/// emitAccelTypes() - Emit type dies into a hashed accelerator table. +void DwarfDebug::emitAccelTypes() { + DwarfAccelTable AT(DwarfAccelTable::Atom(DwarfAccelTable::eAtomTypeDIEOffset, + dwarf::DW_FORM_data4)); + for (DenseMap::iterator I = CUMap.begin(), + E = CUMap.end(); I != E; ++I) { + CompileUnit *TheCU = I->second; + const StringMap &Names = TheCU->getGlobalTypes(); + //TODO: TheCU->getAccelTypes(); + for (StringMap::const_iterator + GI = Names.begin(), GE = Names.end(); GI != GE; ++GI) { + const char *Name = GI->getKeyData(); + DIE *Entity = GI->second; + AT.AddName(Name, Entity); + } + } + + AT.FinalizeTable(Asm, "types"); + Asm->OutStreamer.SwitchSection(Asm->getObjFileLowering() + .getDwarfAccelTypesSection()); + MCSymbol *SectionBegin = Asm->GetTempSymbol("types_begin"); + Asm->OutStreamer.EmitLabel(SectionBegin); + + // Emit the full data. + AT.Emit(Asm, SectionBegin, this); +} + /// emitDebugPubNames - Emit visible names into a debug pubnames section. /// void DwarfDebug::emitDebugPubNames() { Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=143923&r1=143922&r2=143923&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Nov 7 03:24:32 2011 @@ -367,6 +367,21 @@ /// void emitEndOfLineMatrix(unsigned SectionEnd); + /// emitAccelNames - Emit visible names into a hashed accelerator table + /// section. + void emitAccelNames(); + + /// emitAccelObjC - Emit objective C classes and categories into a hashed + /// accelerator table section. + void emitAccelObjC(); + + /// emitAccelNamespace - Emit namespace dies into a hashed accelerator + /// table. + void emitAccelNamespaces(); + + /// emitAccelTypes() - Emit type dies into a hashed accelerator table. + void emitAccelTypes(); + /// emitDebugPubNames - Emit visible names into a debug pubnames section. /// void emitDebugPubNames(); Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=143923&r1=143922&r2=143923&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original) +++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Mon Nov 7 03:24:32 2011 @@ -152,6 +152,24 @@ SectionKind::getReadOnly()); // Debug Information. + DwarfAccelNamesSection = + Ctx->getMachOSection("__DWARF", "__apple_names", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfAccelObjCSection = + Ctx->getMachOSection("__DWARF", "__apple_objc", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + // 16 character section limit... + DwarfAccelNamespaceSection = + Ctx->getMachOSection("__DWARF", "__apple_namespac", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfAccelTypesSection = + Ctx->getMachOSection("__DWARF", "__apple_types", + MCSectionMachO::S_ATTR_DEBUG, + SectionKind::getMetadata()); + DwarfAbbrevSection = Ctx->getMachOSection("__DWARF", "__debug_abbrev", MCSectionMachO::S_ATTR_DEBUG, @@ -506,8 +524,12 @@ PersonalityEncoding = LSDAEncoding = FDEEncoding = FDECFIEncoding = TTypeEncoding = dwarf::DW_EH_PE_absptr; - EHFrameSection = 0; // Created on demand. - CompactUnwindSection = 0; // Used only by selected targets. + EHFrameSection = 0; // Created on demand. + CompactUnwindSection = 0; // Used only by selected targets. + DwarfAccelNamesSection = 0; // Used only by selected targets. + DwarfAccelObjCSection = 0; // Used only by selected targets. + DwarfAccelNamespaceSection = 0; // Used only by selected targets. + DwarfAccelTypesSection = 0; // Used only by selected targets. Triple T(TT); Triple::ArchType Arch = T.getArch(); From echristo at apple.com Mon Nov 7 03:37:06 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 09:37:06 -0000 Subject: [llvm-commits] [llvm] r143924 - /llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt Message-ID: <20111107093706.524BF2A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 03:37:06 2011 New Revision: 143924 URL: http://llvm.org/viewvc/llvm-project?rev=143924&view=rev Log: Add new files to cmake. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt Modified: llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt?rev=143924&r1=143923&r2=143924&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt Mon Nov 7 03:37:06 2011 @@ -4,6 +4,7 @@ AsmPrinterDwarf.cpp AsmPrinterInlineAsm.cpp DIE.cpp + DwarfAccelTable.cpp DwarfCFIException.cpp DwarfCompileUnit.cpp DwarfDebug.cpp From echristo at apple.com Mon Nov 7 03:38:43 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 09:38:43 -0000 Subject: [llvm-commits] [llvm] r143925 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfAccelTable.cpp DwarfDebug.cpp DwarfDebug.h Message-ID: <20111107093843.1D4E62A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 03:38:42 2011 New Revision: 143925 URL: http://llvm.org/viewvc/llvm-project?rev=143925&view=rev Log: Remove unnecessary addition to API. Replace with something much simpler. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp?rev=143925&r1=143924&r2=143925&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Mon Nov 7 03:38:42 2011 @@ -183,7 +183,7 @@ Asm->OutStreamer.EmitLabel((*HI)->Sym); Asm->OutStreamer.AddComment((*HI)->Str); Asm->EmitSectionOffset(D->getStringPoolEntry((*HI)->Str), - D->getDwarfStrSectionSym()); + D->getStringPool()); Asm->OutStreamer.AddComment("Num DIEs"); Asm->EmitInt32((*HI)->DIEOffsets.size()); for (std::vector::const_iterator Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=143925&r1=143924&r2=143925&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 7 03:38:42 2011 @@ -165,14 +165,6 @@ return Entry.first = Asm->GetTempSymbol("string", Entry.second); } -MCSymbol *DwarfDebug::getDwarfStrSectionSym(void) { - if (DwarfStrSectionSym) return DwarfStrSectionSym; - DwarfStrSectionSym = - EmitSectionSym(Asm, Asm->getObjFileLowering().getDwarfStrSection(), - "section_str"); - return DwarfStrSectionSym; -} - /// assignAbbrevNumber - Define a unique number for the abbreviation. /// void DwarfDebug::assignAbbrevNumber(DIEAbbrev &Abbrev) { Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=143925&r1=143924&r2=143925&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Nov 7 03:38:42 2011 @@ -528,10 +528,6 @@ /// getStringPoolEntry - returns an entry into the string pool with the given /// string text. MCSymbol *getStringPoolEntry(StringRef Str); - - /// getDwarfStrSectionSym - returns the symbol that starts the dwarf string - /// section. - MCSymbol *getDwarfStrSectionSym(); }; } // End of namespace llvm From grosser at fim.uni-passau.de Mon Nov 7 04:40:42 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 07 Nov 2011 10:40:42 -0000 Subject: [llvm-commits] [zorg] r143950 - /zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Message-ID: <20111107104042.594272A6C12C@llvm.org> Author: grosser Date: Mon Nov 7 04:40:42 2011 New Revision: 143950 URL: http://llvm.org/viewvc/llvm-project?rev=143950&view=rev Log: PollyBuilder: Use the CLooG/isl version as defined by Polly Modified: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Modified: zorg/trunk/zorg/buildbot/builders/PollyBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/PollyBuilder.py?rev=143950&r1=143949&r2=143950&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/PollyBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/PollyBuilder.py Mon Nov 7 04:40:42 2011 @@ -9,62 +9,20 @@ f = buildbot.process.factory.BuildFactory() def installRequiredLibs(): - cloog_srcdir = "cloog.src" - isl_srcdir = "isl.src" - cloog_installdir = isl_installdir = "cloog.install" + cloog_installdir = "cloog.install" global f - # Get Cloog - f.addStep(Git(repourl='http://repo.or.cz/r/cloog.git', - mode='update', - workdir=cloog_srcdir, - alwaysUseLatest=True, - retry=(30, 10))) - # Get isl - f.addStep(Git(repourl='http://repo.or.cz/r/isl.git', - mode='update', - workdir=isl_srcdir, - alwaysUseLatest=True, - retry=(30, 10))) - # Build isl - f.addStep(ShellCommand(name="autogen-isl", - command=["./autogen.sh"], - haltOnFailure=True, - description=["autogen cloog"], - workdir=isl_srcdir)) - islconfargs = [] - islconfargs.append(WithProperties("%%(builddir)s/%s/configure" - % isl_srcdir)) - islconfargs.append(WithProperties("--prefix=%%(builddir)s/%s" - % isl_installdir)) - f.addStep(Configure(name="isl-configure", - command=islconfargs, - workdir=isl_srcdir, - description=['isl-configure'])) - f.addStep(ShellCommand(name="build-isl", - command=["make"], - haltOnFailure=True, - description=["build isl"], - workdir=isl_srcdir)) - f.addStep(ShellCommand(name="install-isl", - command=["make", "install"], - haltOnFailure=True, - description=["install isl"], - workdir=isl_srcdir)) - # Build Cloog - f.addStep(ShellCommand(name="autogen-cloog", - command=["./autogen.sh"], - haltOnFailure=True, - description=["autogen cloog"], - workdir=cloog_srcdir)) + # Get Cloog and isl + checkout_cloog = WithProperties("%s/llvm.src/tools/polly/utils/checkout_cloog.sh", "builddir") + cloog_srcdir = WithProperties("%s/cloog.src", "builddir") + f.addStep(ShellCommand(name="get-cloog", + command=[checkout_cloog, + cloog_srcdir], + description="Get CLooG/isl source code")) + confargs = [] - confargs.append(WithProperties("%%(builddir)s/%s/configure" - % cloog_srcdir)) - confargs.append(WithProperties("--prefix=%%(builddir)s/%s" - % cloog_installdir)) - confargs.append(WithProperties("--with-isl-prefix=%%(builddir)s/%s" - % cloog_installdir)) - confargs.append(WithProperties("--with-isl=system")) + confargs.append(WithProperties("%s/cloog.src/configure", "builddir")) + confargs.append(WithProperties("--prefix=%s/cloog.install", "builddir")) f.addStep(Configure(name="cloog-configure", command=confargs, workdir=cloog_srcdir, @@ -92,8 +50,6 @@ property="builddir", description="set build dir", workdir=".")) - # Install Prerequisites - installRequiredLibs() # Get LLVM and Polly f.addStep(SVN(name='svn-llvm', mode='update', @@ -105,6 +61,10 @@ baseURL='http://llvm.org/svn/llvm-project/polly/', defaultBranch='trunk', workdir='%s/tools/polly' % llvm_srcdir)) + + # Install Prerequisites + installRequiredLibs() + # Create configuration files with cmake f.addStep(ShellCommand(name="create-build-dir", command=["mkdir", "-p", llvm_objdir], From stpworld at narod.ru Mon Nov 7 05:38:01 2011 From: stpworld at narod.ru (Stepan Dyatkovskiy) Date: Mon, 07 Nov 2011 15:38:01 +0400 Subject: [llvm-commits] [LLVM, SwitchInst, case ranges] Auxiliary patch #1 In-Reply-To: <4EB18F12.6060409@narod.ru> References: <4EAA9B5D.802@narod.ru> <4EAA9DE8.80000@free.fr> <485181319805488@web67.yandex.ru> <4EAB079D.6000606@free.fr> <4EB18F12.6060409@narod.ru> Message-ID: <4EB7C319.1000709@narod.ru> ping. -Stepan. Stepan Dyatkovskiy wrote: > Hello, Duncan. > > Duncan Sands wrote: > > I guess Anton can comment on codegen, but the fact that it doesn't make > > codegen > > harder has nothing to do with increasing the complexity of the > > optimizers, since > > they work at the IR level. It may be that case ranges allow the > > optimizers to > > do a better job. It may be that they simplify the optimizers. But it > > also may > > be the opposite: they might make switches harder to work with and reason > > about > > for no advantage. Which is it? Do you have an example where case ranges > > would > > result in better code, or make it easier to produce better code? > > I made impact analysis for new case ranges feature. > 24 out of more than 100 optimizations are affected. 20 of 24 just > require an integration of a new "case-range" type, i.e. small change of > code without. The remaining 4 requires some bigger changes. All affected > optimizers are listed in attached spreadsheet. > > Patches that are submitted in this branch are just functionality > extension for current classes. These patches doesn't brake any of > existing optimizations and keeps its speed without changes. > > Well. Let's enumerate 4 optimizations that should be reworked. > > 1. LowerSwitch::Clusterify > > This method groups neighbouring cases (by value) that goes to the same > destination. > > For example: > > switch i32 %cond, label %default [ > i32 1, label %successorA > i32 2, label %successorA > i32 5, label %successorB > i32 3, label %successorA > i32 6, label %successorB > ] > > will be grouped to the two clusters: > > [[i32 1] .. [i32 3]], label %successorA > [[i32 5] .. [i32 6]], label %successorB > > This method will work faster if clusters will presented explicitly using > new case ranges feature. > > 2. SimplifyCFG.cpp, TurnSwitchRangeIntoICmp (static function) > > "Turns a switch that contains only an integer range comparison into a > sub, an icmp and a branch." (written in method comments). Algorithm that > determines "solid" case range should be changed. > > Now compare two switches (don't look at syntax of second switch, it is > still a subject of another discussion): > > switch i32 %cond, label %default [ > i32 1, label %successorA > i32 2, label %successorA > i32 3, label %successorA > ] > > and hypothetical switch: > > switch i32 %cond, label %default [ > [[i32 1],[i32 3]], label %successorA ; case range [1..3] > ] > > or even this one: > > switch i32 %cond, label %default [ > [[i32 1],[i32 2]], label %successorA ; case range [1..2] > i32 3, label %successorA ; single case value "3" > ] > > Its obvious that last two switches will be processed faster than the > first one. We doesn't need to perform analysis for each separated case > value. We already know - that it is a range. > > 3. SimplifyCFG.cpp, EliminateDeadSwitchCases (static function). > > Here switch condition is analysed. We try to determine "1" and "0" bits > that MUST be in condition value. If we found them, then we look at case > values; if these bits are absent in case value we remove it since it > will be never equal to condition. > I need to think more about the ways of case ranges processing here. At > least we can represent case range as separated values set and apply > current algorithm to it. It slow down the processing a little bit, but > the complexity itself will be not increased. I'm sure that there are > also exists algorithms that allows to eliminate whole case ranges: e.g. > we can apply current algorithm to high bits that are constant in case > range. > > 4. lib/Transforms/Scalar/LoopUnswitch.cpp (the set of methods). > > Just a quote from LoopUnswitch.cpp header > > [quote] > This pass transforms loops that contain branches on loop-invariant > conditions > to have multiple loops. For example, it turns the left into the right code. > > for (...) if (lic) > A for (...) > if (lic) A; B; C > B else > C for (...) > A; C > [/quote] > > I also must think more about case ranges unswithing here. > By now loops with switch instruction are unswitched value-by-value. > There is no any case-values clustering before unswitching. For example > for case range [0..9] we need to run unswitch process 10 times! > Theoretically, explicitly given case ranges and properly implemented > unswitching should make this optimization better. > > So, as you can see complexity will not changed and even some of > optimizations will work faster. > > Regards, > Stepan. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Mon Nov 7 06:00:20 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 07 Nov 2011 13:00:20 +0100 Subject: [llvm-commits] [llvm] r143719 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/InstSimplify/undef.ll In-Reply-To: <20111104183243.1A9272A6C12C@llvm.org> References: <20111104183243.1A9272A6C12C@llvm.org> Message-ID: <4EB7C854.3030700@free.fr> Hi Dan, > +static Value *SimplifyCallInst(CallInst *CI) { > + // call undef -> undef > + if (isa(CI->getCalledValue())) > + return UndefValue::get(CI->getType()); won't this crash if the call returns void? Ciao, Duncan. > + > + return 0; > +} > + > /// SimplifyInstruction - See if we can compute a simplified version of this > /// instruction. If not, this returns null. > Value *llvm::SimplifyInstruction(Instruction *I, const TargetData *TD, > @@ -2569,6 +2577,9 @@ > case Instruction::PHI: > Result = SimplifyPHINode(cast(I), DT); > break; > + case Instruction::Call: > + Result = SimplifyCallInst(cast(I)); > + break; > } > > /// If called on unreachable code, the above logic may report that the > > Modified: llvm/trunk/test/Transforms/InstSimplify/undef.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/undef.ll?rev=143719&r1=143718&r2=143719&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/InstSimplify/undef.ll (original) > +++ llvm/trunk/test/Transforms/InstSimplify/undef.ll Fri Nov 4 13:32:42 2011 > @@ -125,3 +125,10 @@ > %r = select i1 undef, i64 undef, i64 %a > ret i64 %r > } > + > +; @test18 > +; CHECK: ret i64 undef > +define i64 @test18(i64 %a) { > + %r = call i64 (i64)* undef(i64 %a) > + ret i64 %r > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From richard at xmos.com Mon Nov 7 06:00:54 2011 From: richard at xmos.com (Richard Osborne) Date: Mon, 7 Nov 2011 12:00:54 +0000 Subject: [llvm-commits] [PATCH] Don't introduce custom nodes when building divide by constant after legalization In-Reply-To: <4EAFEF29.7080004@xmos.com> References: <4EAFEF29.7080004@xmos.com> Message-ID: <4EB7C876.7050806@xmos.com> Ping, is that patch OK to apply? Thanks, Richard On 01/11/11 13:07, Richard Osborne wrote: > This patch changes TargetLowering::BuildSDIV() and > TargetLowering::BuildUDIV() so they avoid introducing nodes that > require custom handling after legalization has taken place. This fixes > PR11283. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Richard Osborne | XMOS http://www.xmos.com -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111107/64f20b03/attachment.html From grosser at fim.uni-passau.de Mon Nov 7 06:58:42 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 07 Nov 2011 12:58:42 -0000 Subject: [llvm-commits] [polly] r143958 - /polly/trunk/lib/Analysis/ScopDetection.cpp Message-ID: <20111107125842.302162A6C12C@llvm.org> Author: grosser Date: Mon Nov 7 06:58:41 2011 New Revision: 143958 URL: http://llvm.org/viewvc/llvm-project?rev=143958&view=rev Log: ScopDetection: Add ValidatorResult class Modified: polly/trunk/lib/Analysis/ScopDetection.cpp Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=143958&r1=143957&r2=143958&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Mon Nov 7 06:58:41 2011 @@ -113,8 +113,22 @@ enum TYPE {INT, PARAM, IV, INVALID}; } +struct ValidatorResult { + SCEVType::TYPE type; + + ValidatorResult() : type(SCEVType::INVALID) {}; + + ValidatorResult(const ValidatorResult &vres) { + type = vres.type; + }; + + ValidatorResult(SCEVType::TYPE type) : type(type) {}; + +}; + /// Check if a SCEV is valid in a SCoP. -struct SCEVValidator : public SCEVVisitor { +struct SCEVValidator + : public SCEVVisitor { private: const Region *R; ScalarEvolution &SE; @@ -131,42 +145,44 @@ *BaseAddress = NULL; SCEVValidator Validator(R, SE, BaseAddress); - return Validator.visit(Scev) != SCEVType::INVALID; + ValidatorResult Result = Validator.visit(Scev); + + return Result.type != SCEVType::INVALID; } SCEVValidator(const Region *R, ScalarEvolution &SE, Value **BaseAddress) : R(R), SE(SE), BaseAddress(BaseAddress) {}; - SCEVType::TYPE visitConstant(const SCEVConstant *Constant) { - return SCEVType::INT; + struct ValidatorResult visitConstant(const SCEVConstant *Constant) { + return ValidatorResult(SCEVType::INT); } - SCEVType::TYPE visitTruncateExpr(const SCEVTruncateExpr* Expr) { - SCEVType::TYPE Op = visit(Expr->getOperand()); + struct ValidatorResult visitTruncateExpr(const SCEVTruncateExpr* Expr) { + ValidatorResult Op = visit(Expr->getOperand()); // We currently do not represent a truncate expression as an affine // expression. If it is constant during Scop execution, we treat it as a // parameter, otherwise we bail out. - if (Op == SCEVType::INT || Op == SCEVType::PARAM) - return SCEVType::PARAM; + if (Op.type == SCEVType::INT || Op.type == SCEVType::PARAM) + return ValidatorResult(SCEVType::PARAM); - return SCEVType::INVALID; + return ValidatorResult (SCEVType::INVALID); } - SCEVType::TYPE visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) { - SCEVType::TYPE Op = visit(Expr->getOperand()); + struct ValidatorResult visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) { + ValidatorResult Op = visit(Expr->getOperand()); // We currently do not represent a zero extend expression as an affine // expression. If it is constant during Scop execution, we treat it as a // parameter, otherwise we bail out. - if (Op == SCEVType::INT || Op == SCEVType::PARAM) - return SCEVType::PARAM; + if (Op.type == SCEVType::INT || Op.type == SCEVType::PARAM) + return ValidatorResult (SCEVType::PARAM); - return SCEVType::INVALID; + return ValidatorResult(SCEVType::INVALID); } - SCEVType::TYPE visitSignExtendExpr(const SCEVSignExtendExpr* Expr) { + struct ValidatorResult visitSignExtendExpr(const SCEVSignExtendExpr* Expr) { // We currently allow only signed SCEV expressions. In the case of a // signed value, a sign extend is a noop. // @@ -174,126 +190,130 @@ return visit(Expr->getOperand()); } - SCEVType::TYPE visitAddExpr(const SCEVAddExpr* Expr) { - SCEVType::TYPE Return = SCEVType::INT; + struct ValidatorResult visitAddExpr(const SCEVAddExpr* Expr) { + ValidatorResult Return(SCEVType::INT); for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { - SCEVType::TYPE OpType = visit(Expr->getOperand(i)); + ValidatorResult Op = visit(Expr->getOperand(i)); - if (OpType == SCEVType::INVALID) - return SCEVType::INVALID; + if (Op.type == SCEVType::INVALID) + return ValidatorResult(SCEVType::INVALID); - Return = std::max(Return, OpType); + Return.type = std::max(Return.type, Op.type); } // TODO: Check for NSW and NUW. return Return; } - SCEVType::TYPE visitMulExpr(const SCEVMulExpr* Expr) { - SCEVType::TYPE Return = SCEVType::INT; + struct ValidatorResult visitMulExpr(const SCEVMulExpr* Expr) { + ValidatorResult Return(SCEVType::INT); for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { - SCEVType::TYPE OpType = visit(Expr->getOperand(i)); + ValidatorResult Op = visit(Expr->getOperand(i)); - if (OpType == SCEVType::INT) + if (Op.type == SCEVType::INT) continue; - if (OpType == SCEVType::INVALID || Return != SCEVType::INT) - return SCEVType::INVALID; + if (Op.type == SCEVType::INVALID || Return.type != SCEVType::INT) + return ValidatorResult(SCEVType::INVALID); - Return = OpType; + Return.type = Op.type; } // TODO: Check for NSW and NUW. return Return; } - SCEVType::TYPE visitUDivExpr(const SCEVUDivExpr* Expr) { - SCEVType::TYPE LHS = visit(Expr->getLHS()); - SCEVType::TYPE RHS = visit(Expr->getRHS()); + struct ValidatorResult visitUDivExpr(const SCEVUDivExpr* Expr) { + ValidatorResult LHS = visit(Expr->getLHS()); + ValidatorResult RHS = visit(Expr->getRHS()); // We currently do not represent a unsigned devision as an affine // expression. If the division is constant during Scop execution we treat it // as a parameter, otherwise we bail out. - if (LHS == SCEVType::INT || LHS == SCEVType::PARAM || - RHS == SCEVType::INT || RHS == SCEVType::PARAM) - return SCEVType::PARAM; + if (LHS.type == SCEVType::INT || LHS.type == SCEVType::PARAM || + RHS.type == SCEVType::INT || RHS.type == SCEVType::PARAM) + return ValidatorResult(SCEVType::PARAM); - return SCEVType::INVALID; + return ValidatorResult(SCEVType::INVALID); } - SCEVType::TYPE visitAddRecExpr(const SCEVAddRecExpr* Expr) { + struct ValidatorResult visitAddRecExpr(const SCEVAddRecExpr* Expr) { if (!Expr->isAffine()) - return SCEVType::INVALID; + return ValidatorResult(SCEVType::INVALID); - SCEVType::TYPE Start = visit(Expr->getStart()); - SCEVType::TYPE Recurrence = visit(Expr->getStepRecurrence(SE)); + ValidatorResult Start = visit(Expr->getStart()); + ValidatorResult Recurrence = visit(Expr->getStepRecurrence(SE)); + + if (Start.type == SCEVType::INVALID || + Recurrence.type == SCEVType::INVALID || + Recurrence.type == SCEVType::IV) + return ValidatorResult(SCEVType::INVALID); - if (Start == SCEVType::INVALID || - Recurrence == SCEVType::INVALID || - Recurrence == SCEVType::IV) - return SCEVType::INVALID; if (!R->contains(Expr->getLoop())) { - if (Start == SCEVType::IV) - return SCEVType::INVALID; + if (Start.type == SCEVType::IV) + return ValidatorResult(SCEVType::INVALID); else - return SCEVType::PARAM; + return ValidatorResult(SCEVType::PARAM); } - if (Recurrence != SCEVType::INT) - return SCEVType::INVALID; + if (Recurrence.type != SCEVType::INT) + return ValidatorResult(SCEVType::INVALID); - return SCEVType::IV; + return ValidatorResult(SCEVType::IV); } - SCEVType::TYPE visitSMaxExpr(const SCEVSMaxExpr* Expr) { - SCEVType::TYPE Return = SCEVType::INT; + struct ValidatorResult visitSMaxExpr(const SCEVSMaxExpr* Expr) { + ValidatorResult Return(SCEVType::INT); for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { - SCEVType::TYPE OpType = visit(Expr->getOperand(i)); + ValidatorResult Op = visit(Expr->getOperand(i)); - if (OpType == SCEVType::INVALID) - return SCEVType::INVALID; + if (Op.type == SCEVType::INVALID) + return ValidatorResult(SCEVType::INVALID); - Return = std::max(Return, OpType); + Return.type = std::max(Return.type, Op.type); } return Return; } - SCEVType::TYPE visitUMaxExpr(const SCEVUMaxExpr* Expr) { + struct ValidatorResult visitUMaxExpr(const SCEVUMaxExpr* Expr) { // We do not support unsigned operations. If 'Expr' is constant during Scop // execution we treat this as a parameter, otherwise we bail out. for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { - SCEVType::TYPE OpType = visit(Expr->getOperand(i)); + ValidatorResult Op = visit(Expr->getOperand(i)); - if (OpType != SCEVType::INT && OpType != SCEVType::PARAM) - return SCEVType::INVALID; + if (Op.type != SCEVType::INT && Op.type != SCEVType::PARAM) + return ValidatorResult(SCEVType::INVALID); } - return SCEVType::PARAM; + return ValidatorResult(SCEVType::PARAM); } - SCEVType::TYPE visitUnknown(const SCEVUnknown* Expr) { + ValidatorResult visitUnknown(const SCEVUnknown* Expr) { Value *V = Expr->getValue(); if (isa(V)) - return SCEVType::INVALID; + return ValidatorResult(SCEVType::INVALID); if (BaseAddress) { if (*BaseAddress) - return SCEVType::INVALID; + return ValidatorResult(SCEVType::INVALID); else *BaseAddress = V; } if (Instruction *I = dyn_cast(Expr->getValue())) if (R->contains(I)) - return SCEVType::INVALID; + return ValidatorResult(SCEVType::INVALID); - return SCEVType::PARAM; + if (BaseAddress) + return ValidatorResult(SCEVType::PARAM); + else + return ValidatorResult(SCEVType::PARAM); } }; From grosser at fim.uni-passau.de Mon Nov 7 06:58:46 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 07 Nov 2011 12:58:46 -0000 Subject: [llvm-commits] [polly] r143959 - /polly/trunk/lib/Analysis/ScopDetection.cpp Message-ID: <20111107125847.038132A6C12C@llvm.org> Author: grosser Date: Mon Nov 7 06:58:46 2011 New Revision: 143959 URL: http://llvm.org/viewvc/llvm-project?rev=143959&view=rev Log: ScopDetection: Introduce methods to check attributes of ValidatorResult This simplifies e.g: if (Op.type == SCEVType::INT || Op.type == SCEVType::PARAM) to if (Op.isConstant()) Modified: polly/trunk/lib/Analysis/ScopDetection.cpp Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=143959&r1=143958&r2=143959&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Mon Nov 7 06:58:46 2011 @@ -124,6 +124,21 @@ ValidatorResult(SCEVType::TYPE type) : type(type) {}; + bool isConstant() { + return type == SCEVType::INT || type == SCEVType::PARAM; + } + + bool isValid() { + return type != SCEVType::INVALID; + } + + bool isIV() { + return type == SCEVType::IV; + } + + bool isINT() { + return type == SCEVType::INT; + } }; /// Check if a SCEV is valid in a SCoP. @@ -147,7 +162,7 @@ SCEVValidator Validator(R, SE, BaseAddress); ValidatorResult Result = Validator.visit(Scev); - return Result.type != SCEVType::INVALID; + return Result.isValid(); } SCEVValidator(const Region *R, ScalarEvolution &SE, @@ -164,7 +179,7 @@ // We currently do not represent a truncate expression as an affine // expression. If it is constant during Scop execution, we treat it as a // parameter, otherwise we bail out. - if (Op.type == SCEVType::INT || Op.type == SCEVType::PARAM) + if (Op.isConstant()) return ValidatorResult(SCEVType::PARAM); return ValidatorResult (SCEVType::INVALID); @@ -176,7 +191,7 @@ // We currently do not represent a zero extend expression as an affine // expression. If it is constant during Scop execution, we treat it as a // parameter, otherwise we bail out. - if (Op.type == SCEVType::INT || Op.type == SCEVType::PARAM) + if (Op.isConstant()) return ValidatorResult (SCEVType::PARAM); return ValidatorResult(SCEVType::INVALID); @@ -196,7 +211,7 @@ for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { ValidatorResult Op = visit(Expr->getOperand(i)); - if (Op.type == SCEVType::INVALID) + if (!Op.isValid()) return ValidatorResult(SCEVType::INVALID); Return.type = std::max(Return.type, Op.type); @@ -232,8 +247,7 @@ // We currently do not represent a unsigned devision as an affine // expression. If the division is constant during Scop execution we treat it // as a parameter, otherwise we bail out. - if (LHS.type == SCEVType::INT || LHS.type == SCEVType::PARAM || - RHS.type == SCEVType::INT || RHS.type == SCEVType::PARAM) + if (LHS.isConstant() && RHS.isConstant()) return ValidatorResult(SCEVType::PARAM); return ValidatorResult(SCEVType::INVALID); @@ -246,20 +260,18 @@ ValidatorResult Start = visit(Expr->getStart()); ValidatorResult Recurrence = visit(Expr->getStepRecurrence(SE)); - if (Start.type == SCEVType::INVALID || - Recurrence.type == SCEVType::INVALID || - Recurrence.type == SCEVType::IV) + if (!Start.isValid() || !Recurrence.isValid() || Recurrence.isIV()) return ValidatorResult(SCEVType::INVALID); if (!R->contains(Expr->getLoop())) { - if (Start.type == SCEVType::IV) + if (Start.isIV()) return ValidatorResult(SCEVType::INVALID); else return ValidatorResult(SCEVType::PARAM); } - if (Recurrence.type != SCEVType::INT) + if (!Recurrence.isINT()) return ValidatorResult(SCEVType::INVALID); return ValidatorResult(SCEVType::IV); @@ -271,7 +283,7 @@ for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { ValidatorResult Op = visit(Expr->getOperand(i)); - if (Op.type == SCEVType::INVALID) + if (!Op.isValid()) return ValidatorResult(SCEVType::INVALID); Return.type = std::max(Return.type, Op.type); @@ -286,7 +298,7 @@ for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { ValidatorResult Op = visit(Expr->getOperand(i)); - if (Op.type != SCEVType::INT && Op.type != SCEVType::PARAM) + if (!Op.isConstant()) return ValidatorResult(SCEVType::INVALID); } From grosser at fim.uni-passau.de Mon Nov 7 06:58:54 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 07 Nov 2011 12:58:54 -0000 Subject: [llvm-commits] [polly] r143960 - in /polly/trunk: include/polly/Support/SCEVValidator.h lib/Analysis/ScopDetection.cpp lib/Support/CMakeLists.txt lib/Support/SCEVValidator.cpp Message-ID: <20111107125854.552013524001@llvm.org> Author: grosser Date: Mon Nov 7 06:58:54 2011 New Revision: 143960 URL: http://llvm.org/viewvc/llvm-project?rev=143960&view=rev Log: SCEVValidator: Move into own file Added: polly/trunk/include/polly/Support/SCEVValidator.h (with props) polly/trunk/lib/Support/SCEVValidator.cpp Modified: polly/trunk/lib/Analysis/ScopDetection.cpp polly/trunk/lib/Support/CMakeLists.txt Added: polly/trunk/include/polly/Support/SCEVValidator.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/Support/SCEVValidator.h?rev=143960&view=auto ============================================================================== --- polly/trunk/include/polly/Support/SCEVValidator.h (added) +++ polly/trunk/include/polly/Support/SCEVValidator.h Mon Nov 7 06:58:54 2011 @@ -0,0 +1,27 @@ +//===--- SCEVValidator.h - Detect Scops -------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// Checks if a SCEV expression represents a valid affine expression. +//===----------------------------------------------------------------------===// + +#ifndef POLLY_SCEV_VALIDATOR_H +#define POLLY_SCEV_VALIDATOR_H + +namespace llvm { + class Region; + class SCEV; + class ScalarEvolution; + class Value; +} + +namespace polly { + bool isAffineExpr(const llvm::Region *R, const llvm::SCEV *Expression, + llvm::ScalarEvolution &SE, llvm::Value **BaseAddress = 0); +} + +#endif Propchange: polly/trunk/include/polly/Support/SCEVValidator.h ------------------------------------------------------------------------------ svn:executable = * Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=143960&r1=143959&r2=143960&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Mon Nov 7 06:58:54 2011 @@ -48,6 +48,7 @@ #include "polly/LinkAllPasses.h" #include "polly/Support/ScopHelper.h" +#include "polly/Support/SCEVValidator.h" #include "polly/Support/AffineSCEVIterator.h" #include "llvm/LLVMContext.h" @@ -108,227 +109,6 @@ //===----------------------------------------------------------------------===// // ScopDetection. - -namespace SCEVType { - enum TYPE {INT, PARAM, IV, INVALID}; -} - -struct ValidatorResult { - SCEVType::TYPE type; - - ValidatorResult() : type(SCEVType::INVALID) {}; - - ValidatorResult(const ValidatorResult &vres) { - type = vres.type; - }; - - ValidatorResult(SCEVType::TYPE type) : type(type) {}; - - bool isConstant() { - return type == SCEVType::INT || type == SCEVType::PARAM; - } - - bool isValid() { - return type != SCEVType::INVALID; - } - - bool isIV() { - return type == SCEVType::IV; - } - - bool isINT() { - return type == SCEVType::INT; - } -}; - -/// Check if a SCEV is valid in a SCoP. -struct SCEVValidator - : public SCEVVisitor { -private: - const Region *R; - ScalarEvolution &SE; - Value **BaseAddress; - -public: - static bool isValid(const Region *R, const SCEV *Scev, - ScalarEvolution &SE, - Value **BaseAddress = NULL) { - if (isa(Scev)) - return false; - - if (BaseAddress) - *BaseAddress = NULL; - - SCEVValidator Validator(R, SE, BaseAddress); - ValidatorResult Result = Validator.visit(Scev); - - return Result.isValid(); - } - - SCEVValidator(const Region *R, ScalarEvolution &SE, - Value **BaseAddress) : R(R), SE(SE), - BaseAddress(BaseAddress) {}; - - struct ValidatorResult visitConstant(const SCEVConstant *Constant) { - return ValidatorResult(SCEVType::INT); - } - - struct ValidatorResult visitTruncateExpr(const SCEVTruncateExpr* Expr) { - ValidatorResult Op = visit(Expr->getOperand()); - - // We currently do not represent a truncate expression as an affine - // expression. If it is constant during Scop execution, we treat it as a - // parameter, otherwise we bail out. - if (Op.isConstant()) - return ValidatorResult(SCEVType::PARAM); - - return ValidatorResult (SCEVType::INVALID); - } - - struct ValidatorResult visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) { - ValidatorResult Op = visit(Expr->getOperand()); - - // We currently do not represent a zero extend expression as an affine - // expression. If it is constant during Scop execution, we treat it as a - // parameter, otherwise we bail out. - if (Op.isConstant()) - return ValidatorResult (SCEVType::PARAM); - - return ValidatorResult(SCEVType::INVALID); - } - - struct ValidatorResult visitSignExtendExpr(const SCEVSignExtendExpr* Expr) { - // We currently allow only signed SCEV expressions. In the case of a - // signed value, a sign extend is a noop. - // - // TODO: Reconsider this when we add support for unsigned values. - return visit(Expr->getOperand()); - } - - struct ValidatorResult visitAddExpr(const SCEVAddExpr* Expr) { - ValidatorResult Return(SCEVType::INT); - - for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { - ValidatorResult Op = visit(Expr->getOperand(i)); - - if (!Op.isValid()) - return ValidatorResult(SCEVType::INVALID); - - Return.type = std::max(Return.type, Op.type); - } - - // TODO: Check for NSW and NUW. - return Return; - } - - struct ValidatorResult visitMulExpr(const SCEVMulExpr* Expr) { - ValidatorResult Return(SCEVType::INT); - - for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { - ValidatorResult Op = visit(Expr->getOperand(i)); - - if (Op.type == SCEVType::INT) - continue; - - if (Op.type == SCEVType::INVALID || Return.type != SCEVType::INT) - return ValidatorResult(SCEVType::INVALID); - - Return.type = Op.type; - } - - // TODO: Check for NSW and NUW. - return Return; - } - - struct ValidatorResult visitUDivExpr(const SCEVUDivExpr* Expr) { - ValidatorResult LHS = visit(Expr->getLHS()); - ValidatorResult RHS = visit(Expr->getRHS()); - - // We currently do not represent a unsigned devision as an affine - // expression. If the division is constant during Scop execution we treat it - // as a parameter, otherwise we bail out. - if (LHS.isConstant() && RHS.isConstant()) - return ValidatorResult(SCEVType::PARAM); - - return ValidatorResult(SCEVType::INVALID); - } - - struct ValidatorResult visitAddRecExpr(const SCEVAddRecExpr* Expr) { - if (!Expr->isAffine()) - return ValidatorResult(SCEVType::INVALID); - - ValidatorResult Start = visit(Expr->getStart()); - ValidatorResult Recurrence = visit(Expr->getStepRecurrence(SE)); - - if (!Start.isValid() || !Recurrence.isValid() || Recurrence.isIV()) - return ValidatorResult(SCEVType::INVALID); - - - if (!R->contains(Expr->getLoop())) { - if (Start.isIV()) - return ValidatorResult(SCEVType::INVALID); - else - return ValidatorResult(SCEVType::PARAM); - } - - if (!Recurrence.isINT()) - return ValidatorResult(SCEVType::INVALID); - - return ValidatorResult(SCEVType::IV); - } - - struct ValidatorResult visitSMaxExpr(const SCEVSMaxExpr* Expr) { - ValidatorResult Return(SCEVType::INT); - - for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { - ValidatorResult Op = visit(Expr->getOperand(i)); - - if (!Op.isValid()) - return ValidatorResult(SCEVType::INVALID); - - Return.type = std::max(Return.type, Op.type); - } - - return Return; - } - - struct ValidatorResult visitUMaxExpr(const SCEVUMaxExpr* Expr) { - // We do not support unsigned operations. If 'Expr' is constant during Scop - // execution we treat this as a parameter, otherwise we bail out. - for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { - ValidatorResult Op = visit(Expr->getOperand(i)); - - if (!Op.isConstant()) - return ValidatorResult(SCEVType::INVALID); - } - - return ValidatorResult(SCEVType::PARAM); - } - - ValidatorResult visitUnknown(const SCEVUnknown* Expr) { - Value *V = Expr->getValue(); - - if (isa(V)) - return ValidatorResult(SCEVType::INVALID); - - if (BaseAddress) { - if (*BaseAddress) - return ValidatorResult(SCEVType::INVALID); - else - *BaseAddress = V; - } - - if (Instruction *I = dyn_cast(Expr->getValue())) - if (R->contains(I)) - return ValidatorResult(SCEVType::INVALID); - - if (BaseAddress) - return ValidatorResult(SCEVType::PARAM); - else - return ValidatorResult(SCEVType::PARAM); - } -}; - bool ScopDetection::isMaxRegionInScop(const Region &R) const { // The Region is valid only if it could be found in the set. return ValidRegions.count(&R); @@ -457,8 +237,8 @@ const SCEV *ScevLHS = SE->getSCEV(ICmp->getOperand(0)); const SCEV *ScevRHS = SE->getSCEV(ICmp->getOperand(1)); - bool affineLHS = SCEVValidator::isValid(&Context.CurRegion, ScevLHS, *SE); - bool affineRHS = SCEVValidator::isValid(&Context.CurRegion, ScevRHS, *SE); + bool affineLHS = isAffineExpr(&Context.CurRegion, ScevLHS, *SE); + bool affineRHS = isAffineExpr(&Context.CurRegion, ScevRHS, *SE); if (!affineLHS || !affineRHS) INVALID(AffFunc, "Non affine branch in BB: " + BB.getNameStr()); @@ -499,8 +279,7 @@ Value *Ptr = getPointerOperand(Inst), *BasePtr; const SCEV *AccessFunction = SE->getSCEV(Ptr); - if (!SCEVValidator::isValid(&Context.CurRegion, AccessFunction, *SE, - &BasePtr)) + if (!isAffineExpr(&Context.CurRegion, AccessFunction, *SE, &BasePtr)) INVALID(AffFunc, "Bad memory address " << *AccessFunction); // FIXME: Also check with isValidAffineFunction, as for the moment it is @@ -628,7 +407,7 @@ // Is the loop count affine? const SCEV *LoopCount = SE->getBackedgeTakenCount(L); - if (!SCEVValidator::isValid(&Context.CurRegion, LoopCount, *SE)) + if (!isAffineExpr(&Context.CurRegion, LoopCount, *SE)) INVALID(LoopBound, "Non affine loop bound '" << *LoopCount << "' in loop: " << L->getHeader()->getNameStr()); Modified: polly/trunk/lib/Support/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/CMakeLists.txt?rev=143960&r1=143959&r2=143960&view=diff ============================================================================== --- polly/trunk/lib/Support/CMakeLists.txt (original) +++ polly/trunk/lib/Support/CMakeLists.txt Mon Nov 7 06:58:54 2011 @@ -1,5 +1,6 @@ add_polly_library(PollySupport AffSCEVItTester.cpp GICHelper.cpp + SCEVValidator.cpp ScopHelper.cpp ) Added: polly/trunk/lib/Support/SCEVValidator.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/SCEVValidator.cpp?rev=143960&view=auto ============================================================================== --- polly/trunk/lib/Support/SCEVValidator.cpp (added) +++ polly/trunk/lib/Support/SCEVValidator.cpp Mon Nov 7 06:58:54 2011 @@ -0,0 +1,231 @@ + +#include "polly/Support/SCEVValidator.h" + +#include "llvm/Analysis/ScalarEvolution.h" +#include "llvm/Analysis/ScalarEvolutionExpressions.h" +#include "llvm/Analysis/RegionInfo.h" + +using namespace llvm; + +namespace SCEVType { + enum TYPE {INT, PARAM, IV, INVALID}; +} + +struct ValidatorResult { + SCEVType::TYPE type; + + ValidatorResult() : type(SCEVType::INVALID) {}; + + ValidatorResult(const ValidatorResult &vres) { + type = vres.type; + }; + + ValidatorResult(SCEVType::TYPE type) : type(type) {}; + + bool isConstant() { + return type == SCEVType::INT || type == SCEVType::PARAM; + } + + bool isValid() { + return type != SCEVType::INVALID; + } + + bool isIV() { + return type == SCEVType::IV; + } + + bool isINT() { + return type == SCEVType::INT; + } +}; + +/// Check if a SCEV is valid in a SCoP. +struct SCEVValidator + : public SCEVVisitor { +private: + const Region *R; + ScalarEvolution &SE; + Value **BaseAddress; + +public: + SCEVValidator(const Region *R, ScalarEvolution &SE, + Value **BaseAddress) : R(R), SE(SE), + BaseAddress(BaseAddress) {}; + + struct ValidatorResult visitConstant(const SCEVConstant *Constant) { + return ValidatorResult(SCEVType::INT); + } + + struct ValidatorResult visitTruncateExpr(const SCEVTruncateExpr* Expr) { + ValidatorResult Op = visit(Expr->getOperand()); + + // We currently do not represent a truncate expression as an affine + // expression. If it is constant during Scop execution, we treat it as a + // parameter, otherwise we bail out. + if (Op.isConstant()) + return ValidatorResult(SCEVType::PARAM); + + return ValidatorResult (SCEVType::INVALID); + } + + struct ValidatorResult visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) { + ValidatorResult Op = visit(Expr->getOperand()); + + // We currently do not represent a zero extend expression as an affine + // expression. If it is constant during Scop execution, we treat it as a + // parameter, otherwise we bail out. + if (Op.isConstant()) + return ValidatorResult (SCEVType::PARAM); + + return ValidatorResult(SCEVType::INVALID); + } + + struct ValidatorResult visitSignExtendExpr(const SCEVSignExtendExpr* Expr) { + // We currently allow only signed SCEV expressions. In the case of a + // signed value, a sign extend is a noop. + // + // TODO: Reconsider this when we add support for unsigned values. + return visit(Expr->getOperand()); + } + + struct ValidatorResult visitAddExpr(const SCEVAddExpr* Expr) { + ValidatorResult Return(SCEVType::INT); + + for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { + ValidatorResult Op = visit(Expr->getOperand(i)); + + if (!Op.isValid()) + return ValidatorResult(SCEVType::INVALID); + + Return.type = std::max(Return.type, Op.type); + } + + // TODO: Check for NSW and NUW. + return Return; + } + + struct ValidatorResult visitMulExpr(const SCEVMulExpr* Expr) { + ValidatorResult Return(SCEVType::INT); + + for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { + ValidatorResult Op = visit(Expr->getOperand(i)); + + if (Op.type == SCEVType::INT) + continue; + + if (Op.type == SCEVType::INVALID || Return.type != SCEVType::INT) + return ValidatorResult(SCEVType::INVALID); + + Return.type = Op.type; + } + + // TODO: Check for NSW and NUW. + return Return; + } + + struct ValidatorResult visitUDivExpr(const SCEVUDivExpr* Expr) { + ValidatorResult LHS = visit(Expr->getLHS()); + ValidatorResult RHS = visit(Expr->getRHS()); + + // We currently do not represent a unsigned devision as an affine + // expression. If the division is constant during Scop execution we treat it + // as a parameter, otherwise we bail out. + if (LHS.isConstant() && RHS.isConstant()) + return ValidatorResult(SCEVType::PARAM); + + return ValidatorResult(SCEVType::INVALID); + } + + struct ValidatorResult visitAddRecExpr(const SCEVAddRecExpr* Expr) { + if (!Expr->isAffine()) + return ValidatorResult(SCEVType::INVALID); + + ValidatorResult Start = visit(Expr->getStart()); + ValidatorResult Recurrence = visit(Expr->getStepRecurrence(SE)); + + if (!Start.isValid() || !Recurrence.isValid() || Recurrence.isIV()) + return ValidatorResult(SCEVType::INVALID); + + + if (!R->contains(Expr->getLoop())) { + if (Start.isIV()) + return ValidatorResult(SCEVType::INVALID); + else + return ValidatorResult(SCEVType::PARAM); + } + + if (!Recurrence.isINT()) + return ValidatorResult(SCEVType::INVALID); + + return ValidatorResult(SCEVType::IV); + } + + struct ValidatorResult visitSMaxExpr(const SCEVSMaxExpr* Expr) { + ValidatorResult Return(SCEVType::INT); + + for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { + ValidatorResult Op = visit(Expr->getOperand(i)); + + if (!Op.isValid()) + return ValidatorResult(SCEVType::INVALID); + + Return.type = std::max(Return.type, Op.type); + } + + return Return; + } + + struct ValidatorResult visitUMaxExpr(const SCEVUMaxExpr* Expr) { + // We do not support unsigned operations. If 'Expr' is constant during Scop + // execution we treat this as a parameter, otherwise we bail out. + for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { + ValidatorResult Op = visit(Expr->getOperand(i)); + + if (!Op.isConstant()) + return ValidatorResult(SCEVType::INVALID); + } + + return ValidatorResult(SCEVType::PARAM); + } + + ValidatorResult visitUnknown(const SCEVUnknown* Expr) { + Value *V = Expr->getValue(); + + if (isa(V)) + return ValidatorResult(SCEVType::INVALID); + + if (BaseAddress) { + if (*BaseAddress) + return ValidatorResult(SCEVType::INVALID); + else + *BaseAddress = V; + } + + if (Instruction *I = dyn_cast(Expr->getValue())) + if (R->contains(I)) + return ValidatorResult(SCEVType::INVALID); + + if (BaseAddress) + return ValidatorResult(SCEVType::PARAM); + else + return ValidatorResult(SCEVType::PARAM); + } +}; + +namespace polly { + bool isAffineExpr(const Region *R, const SCEV *Expr, ScalarEvolution &SE, + Value **BaseAddress) { + if (isa(Expr)) + return false; + + if (BaseAddress) + *BaseAddress = NULL; + + SCEVValidator Validator(R, SE, BaseAddress); + ValidatorResult Result = Validator.visit(Expr); + + return Result.isValid(); + } +} + + From grosser at fim.uni-passau.de Mon Nov 7 06:58:59 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Mon, 07 Nov 2011 12:58:59 -0000 Subject: [llvm-commits] [polly] r143961 - in /polly/trunk: include/polly/ScopInfo.h lib/Analysis/ScopInfo.cpp Message-ID: <20111107125859.E56842A6C12C@llvm.org> Author: grosser Date: Mon Nov 7 06:58:59 2011 New Revision: 143961 URL: http://llvm.org/viewvc/llvm-project?rev=143961&view=rev Log: ScopInfo: Extract function getIdForParam() Modified: polly/trunk/include/polly/ScopInfo.h polly/trunk/lib/Analysis/ScopInfo.cpp Modified: polly/trunk/include/polly/ScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/ScopInfo.h?rev=143961&r1=143960&r2=143961&view=diff ============================================================================== --- polly/trunk/include/polly/ScopInfo.h (original) +++ polly/trunk/include/polly/ScopInfo.h Mon Nov 7 06:58:59 2011 @@ -40,6 +40,7 @@ struct isl_map; struct isl_basic_map; +struct isl_id; struct isl_set; struct isl_space; struct isl_constraint; @@ -454,6 +455,14 @@ /// @return The set containing the parameters used in this Scop. inline const ParamVecType &getParams() const { return Parameters; } + + /// @brief Return the isl_id that represents a certain parameter. + /// + /// @param Parameter A SCEV that was recognized as a Parameter. + /// + /// @return The corresponding isl_id or NULL otherwise. + isl_id *getIdForParam(const SCEV *Parameter) const; + /// @name Parameter Iterators /// /// These iterators iterate over all parameters of this Scop. Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=143961&r1=143960&r2=143961&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Mon Nov 7 06:58:59 2011 @@ -87,28 +87,20 @@ } isl_pw_aff *visit(const SCEV *scev) { - // In case the scev is contained in our list of parameters, we do not - // further analyze this expression, but create a new parameter in the - // isl_pw_aff. This allows us to treat subexpressions that we cannot - // translate into an piecewise affine expression, as constant parameters of - // the piecewise affine expression. - int i = 0; - for (Scop::const_param_iterator PI = scop->param_begin(), - PE = scop->param_end(); PI != PE; ++PI) { - if (*PI == scev) { - isl_id *ID = isl_id_alloc(ctx, ("p" + convertInt(i)).c_str(), - (void *) scev); - isl_space *Space = isl_space_set_alloc(ctx, 1, NbLoopSpaces); - Space = isl_space_set_dim_id(Space, isl_dim_param, 0, ID); - - isl_set *Domain = isl_set_universe(isl_space_copy(Space)); - isl_aff *Affine = isl_aff_zero_on_domain( - isl_local_space_from_space(Space)); - Affine = isl_aff_add_coefficient_si(Affine, isl_dim_param, 0, 1); + // In case the scev is a valid parameter, we do not further analyze this + // expression, but create a new parameter in the isl_pw_aff. This allows us + // to treat subexpressions that we cannot translate into an piecewise affine + // expression, as constant parameters of the piecewise affine expression. + if (isl_id *Id = scop->getIdForParam(scev)) { + isl_space *Space = isl_space_set_alloc(ctx, 1, NbLoopSpaces); + Space = isl_space_set_dim_id(Space, isl_dim_param, 0, Id); + + isl_set *Domain = isl_set_universe(isl_space_copy(Space)); + isl_aff *Affine = isl_aff_zero_on_domain( + isl_local_space_from_space(Space)); + Affine = isl_aff_add_coefficient_si(Affine, isl_dim_param, 0, 1); - return isl_pw_aff_alloc(Domain, Affine); - } - i++; + return isl_pw_aff_alloc(Domain, Affine); } return SCEVVisitor::visit(scev); @@ -854,6 +846,22 @@ //===----------------------------------------------------------------------===// /// Scop class implement +isl_id *Scop::getIdForParam(const SCEV *Parameter) const { + int i = 0; + + for (const_param_iterator PI = param_begin(), PE = param_end(); PI != PE; + ++PI) { + if (Parameter == *PI) { + std::string ParameterName = "p" + convertInt(i); + isl_id *id = isl_id_alloc(getIslCtx(), ParameterName.c_str(), + (void *) Parameter); + return id; + } + i++; + } + + return NULL; +} void Scop::buildContext(isl_ctx *IslCtx, ParamSetType *ParamSet) { isl_space *Space = isl_space_params_alloc(IslCtx, ParamSet->size()); From daniel at zuster.org Mon Nov 7 09:01:20 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 7 Nov 2011 08:01:20 -0700 Subject: [llvm-commits] [llvm] r143880 - in /llvm/trunk: include/llvm/ADT/StringRef.h lib/Support/StringRef.cpp In-Reply-To: <0246EF7D-B28C-4ED0-BEE5-8245597BAF77@gmail.com> References: <20111106180444.117382A6C12C@llvm.org> <0246EF7D-B28C-4ED0-BEE5-8245597BAF77@gmail.com> Message-ID: Yes, apparently I hadn't staged this. Thanks! And thanks Benjamin who already fixed it for me. - Daniel On Sun, Nov 6, 2011 at 11:16 AM, Joe Abbey wrote: > Shouldn't upper call ascii_toupper? > > Joe > > Sent from my iPhone > > On Nov 6, 2011, at 1:04 PM, Daniel Dunbar wrote: > >> Author: ddunbar >> Date: Sun Nov ?6 12:04:43 2011 >> New Revision: 143880 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=143880&view=rev >> Log: >> ADT/StringRef: Add ::lower() and ::upper() methods. >> >> Modified: >> ? ?llvm/trunk/include/llvm/ADT/StringRef.h >> ? ?llvm/trunk/lib/Support/StringRef.cpp >> >> Modified: llvm/trunk/include/llvm/ADT/StringRef.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringRef.h?rev=143880&r1=143879&r2=143880&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm/ADT/StringRef.h (original) >> +++ llvm/trunk/include/llvm/ADT/StringRef.h Sun Nov ?6 12:04:43 2011 >> @@ -327,6 +327,16 @@ >> ? ? bool getAsInteger(unsigned Radix, APInt &Result) const; >> >> ? ? /// @} >> + ? ?/// @name String Operations >> + ? ?/// @{ >> + >> + ? ?// lower - Convert the given ASCII string to lowercase. >> + ? ?std::string lower() const; >> + >> + ? ?/// upper - Convert the given ASCII string to uppercase. >> + ? ?std::string upper() const; >> + >> + ? ?/// @} >> ? ? /// @name Substring Operations >> ? ? /// @{ >> >> >> Modified: llvm/trunk/lib/Support/StringRef.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/StringRef.cpp?rev=143880&r1=143879&r2=143880&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Support/StringRef.cpp (original) >> +++ llvm/trunk/lib/Support/StringRef.cpp Sun Nov ?6 12:04:43 2011 >> @@ -25,6 +25,12 @@ >> ? return x; >> } >> >> +static char ascii_toupper(char x) { >> + ?if (x >= 'a' && x <= 'z') >> + ? ?return x - 'a' + 'A'; >> + ?return x; >> +} >> + >> static bool ascii_isdigit(char x) { >> ? return x >= '0' && x <= '9'; >> } >> @@ -132,6 +138,26 @@ >> } >> >> //===----------------------------------------------------------------------===// >> +// String Operations >> +//===----------------------------------------------------------------------===// >> + >> +std::string StringRef::lower() const { >> + ?std::string Result(size(), char()); >> + ?for (size_type i = 0, e = size(); i != e; ++i) { >> + ? ?Result[i] = ascii_tolower(Data[i]); >> + ?} >> + ?return Result; >> +} >> + >> +std::string StringRef::upper() const { >> + ?std::string Result(size(), char()); >> + ?for (size_type i = 0, e = size(); i != e; ++i) { >> + ? ?Result[i] = ascii_tolower(Data[i]); >> + ?} >> + ?return Result; >> +} >> + >> +//===----------------------------------------------------------------------===// >> // String Searching >> //===----------------------------------------------------------------------===// >> >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From benny.kra at googlemail.com Mon Nov 7 09:36:21 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 7 Nov 2011 16:36:21 +0100 Subject: [llvm-commits] [llvm] r143921 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfAccelTable.cpp DwarfAccelTable.h In-Reply-To: <20111107091842.4FB7E3524001@llvm.org> References: <20111107091842.4FB7E3524001@llvm.org> Message-ID: Some comments inline. Test cases would be nice but I can see that we're lacking infrastructure to test it properly. On 07.11.2011, at 10:18, Eric Christopher wrote: > Author: echristo > Date: Mon Nov 7 03:18:42 2011 > New Revision: 143921 > > URL: http://llvm.org/viewvc/llvm-project?rev=143921&view=rev > Log: > Add a new dwarf accelerator table prototype with the goal of replacing > the pubnames and pubtypes tables. LLDB can currently use this format > and a full spec is forthcoming and submission for standardization is planned. > > A basic summary: > > The dwarf accelerator tables are an indirect hash table optimized > for null lookup rather than access to known data. They are output into > an on-disk format that looks like this: > > .-------------. > | HEADER | > |-------------| > | BUCKETS | > |-------------| > | HASHES | > |-------------| > | OFFSETS | > |-------------| > | DATA | > `-------------' > > where the header contains a magic number, version, type of hash function, > the number of buckets, total number of hashes, and room for a special > struct of data and the length of that struct. > > The buckets contain an index (e.g. 6) into the hashes array. The hashes > section contains all of the 32-bit hash values in contiguous memory, and > the offsets contain the offset into the data area for the particular > hash. > > For a lookup example, we could hash a function name and take it modulo the > number of buckets giving us our bucket. From there we take the bucket value > as an index into the hashes table and look at each successive hash as long > as the hash value is still the same modulo result (bucket value) as earlier. > If we have a match we look at that same entry in the offsets table and > grab the offset in the data for our final match. > > Added: > llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp > llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h > > Added: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp?rev=143921&view=auto > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp (added) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Mon Nov 7 03:18:42 2011 > @@ -0,0 +1,250 @@ > +//=-- llvm/CodeGen/DwarfAccelTable.cpp - Dwarf Accelerator Tables -*- C++ -*-=// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// > +// This file contains support for writing dwarf accelerator tables. > +// > +//===----------------------------------------------------------------------===// > + > +#include "llvm/CodeGen/AsmPrinter.h" > +#include "llvm/MC/MCExpr.h" > +#include "llvm/MC/MCStreamer.h" > +#include "llvm/MC/MCSymbol.h" > +#include "llvm/Support/Debug.h" > +#include "DwarfAccelTable.h" > +#include "DwarfDebug.h" > +#include "DIE.h" > + > +using namespace llvm; > + > +const char *DwarfAccelTable::Atom::AtomTypeString(enum AtomType AT) { > + switch (AT) { > + default: llvm_unreachable("invalid AtomType!"); > + case eAtomTypeNULL: return "eAtomTypeNULL"; > + case eAtomTypeDIEOffset: return "eAtomTypeDIEOffset"; > + case eAtomTypeCUOffset: return "eAtomTypeCUOffset"; > + case eAtomTypeTag: return "eAtomTypeTag"; > + case eAtomTypeNameFlags: return "eAtomTypeNameFlags"; > + case eAtomTypeTypeFlags: return "eAtomTypeTypeFlags"; > + } > +} > + > +// The general case would need to have a less hard coded size for the > +// length of the HeaderData, however, if we're constructing based on a > +// single Atom then we know it will always be: 4 + 4 + 2 + 2. > +DwarfAccelTable::DwarfAccelTable(DwarfAccelTable::Atom atom) : > + Header(12), > + HeaderData(atom) { > +} > + > +void DwarfAccelTable::AddName(StringRef Name, DIE* die) { > + // If the string is in the list already then add this die to the list > + // otherwise add a new one. > + DIEArray &DIEs = Entries[Name]; > + DIEs.push_back(die); > +} > + > +void DwarfAccelTable::ComputeBucketCount(void) { > + // First get the number of unique hashes. > + std::vector uniques; > + uniques.resize(Data.size()); > + for (size_t i = 0; i < Data.size(); ++i) > + uniques[i] = Data[i]->HashValue; > + std::sort(uniques.begin(), uniques.end()); > + std::vector::iterator p = > + std::unique(uniques.begin(), uniques.end()); > + uint32_t num = std::distance(uniques.begin(), p); > + > + // Then compute the bucket size, minimum of 1 bucket. > + if (num > 1024) Header.bucket_count = num/4; > + if (num > 16) Header.bucket_count = num/2; > + else Header.bucket_count = num > 0 ? num : 1; > + > + Header.hashes_count = num; > +} > + > +void DwarfAccelTable::FinalizeTable(AsmPrinter *Asm, const char *Prefix) { > + // Create the individual hash data outputs. > + for (StringMap::const_iterator > + EI = Entries.begin(), EE = Entries.end(); EI != EE; ++EI) { > + struct HashData *Entry = new HashData((*EI).getKeyData()); Who's responsible for deleting these? > + for (DIEArray::const_iterator DI = (*EI).second.begin(), > + DE = (*EI).second.end(); > + DI != DE; ++DI) > + Entry->addOffset((*DI)->getOffset()); > + Data.push_back(Entry); > + } > + > + // Figure out how many buckets we need, then compute the bucket > + // contents and the final ordering. We'll emit the hashes and offsets > + // by doing a walk during the emission phase. We add temporary > + // symbols to the data so that we can reference them during the offset > + // later, we'll emit them when we emit the data. > + ComputeBucketCount(); > + > + // Compute bucket contents and final ordering. > + Buckets.resize(Header.bucket_count); > + for (size_t i = 0; i < Data.size(); ++i) { > + uint32_t bucket = Data[i]->HashValue % Header.bucket_count; > + Buckets[bucket].push_back(Data[i]); > + Data[i]->Sym = Asm->GetTempSymbol(Prefix, i); > + } > +} > + > +// Emits the header for the table via the AsmPrinter. > +void DwarfAccelTable::EmitHeader(AsmPrinter *Asm) { > + Asm->OutStreamer.AddComment("Header Magic"); > + Asm->EmitInt32(Header.magic); > + Asm->OutStreamer.AddComment("Header Version"); > + Asm->EmitInt16(Header.version); > + Asm->OutStreamer.AddComment("Header Hash Function"); > + Asm->EmitInt16(Header.hash_function); > + Asm->OutStreamer.AddComment("Header Bucket Count"); > + Asm->EmitInt32(Header.bucket_count); > + Asm->OutStreamer.AddComment("Header Hash Count"); > + Asm->EmitInt32(Header.hashes_count); > + Asm->OutStreamer.AddComment("Header Data Length"); > + Asm->EmitInt32(Header.header_data_len); > + Asm->OutStreamer.AddComment("HeaderData Die Offset Base"); > + Asm->EmitInt32(HeaderData.die_offset_base); > + Asm->OutStreamer.AddComment("HeaderData Atom Count"); > + Asm->EmitInt32(HeaderData.Atoms.size()); > + for (size_t i = 0; i < HeaderData.Atoms.size(); i++) { > + Atom A = HeaderData.Atoms[i]; > + Asm->OutStreamer.AddComment(Atom::AtomTypeString(A.type)); > + Asm->EmitInt16(A.type); > + Asm->OutStreamer.AddComment(dwarf::FormEncodingString(A.form)); > + Asm->EmitInt16(A.form); > + } > +} > + > +// Walk through and emit the buckets for the table. This will look > +// like a list of numbers of how many elements are in each bucket. > +void DwarfAccelTable::EmitBuckets(AsmPrinter *Asm) { > + unsigned index = 0; > + for (size_t i = 0; i < Buckets.size(); ++i) { > + Twine Comment = Twine("Bucket ") + Twine(i); Don't use local Twine variables, it works as long as you concatenate two chunks but will blow up in strange ways as soon as you add another chunk. Just move the Twine construction into the function call. > + Asm->OutStreamer.AddComment(Comment); > + if (Buckets[i].size() != 0) > + Asm->EmitInt32(index); > + else > + Asm->EmitInt32(UINT32_MAX); > + index += Buckets[i].size(); > + } > +} > + > +// Walk through the buckets and emit the individual hashes for each > +// bucket. > +void DwarfAccelTable::EmitHashes(AsmPrinter *Asm) { > + for (size_t i = 0; i < Buckets.size(); ++i) { > + for (HashList::const_iterator HI = Buckets[i].begin(), > + HE = Buckets[i].end(); HI != HE; ++HI) { > + Twine Comment = Twine("Hash in Bucket ") + Twine(i); ditto > + Asm->OutStreamer.AddComment(Comment); > + Asm->EmitInt32((*HI)->HashValue); > + } > + } > +} > + > +// Walk through the buckets and emit the individual offsets for each > +// element in each bucket. This is done via a symbol subtraction from the > +// beginning of the section. The non-section symbol will be output later > +// when we emit the actual data. > +void DwarfAccelTable::EmitOffsets(AsmPrinter *Asm, MCSymbol *SecBegin) { > + for (size_t i = 0; i < Buckets.size(); ++i) { > + for (HashList::const_iterator HI = Buckets[i].begin(), > + HE = Buckets[i].end(); HI != HE; ++HI) { > + Twine Comment = Twine("Offset in Bucket ") + Twine(i); ditto > + Asm->OutStreamer.AddComment(Comment); > + MCContext &Context = Asm->OutStreamer.getContext(); > + const MCExpr *Sub = > + MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create((*HI)->Sym, Context), > + MCSymbolRefExpr::Create(SecBegin, Context), > + Context); > + Asm->OutStreamer.EmitValue(Sub, sizeof(uint32_t), 0); > + } > + } > +} > + > +// Walk through the buckets and emit the full data for each element in > +// the bucket. For the string case emit the dies and the various offsets. > +// Terminate each HashData bucket with 0. > +void DwarfAccelTable::EmitData(AsmPrinter *Asm, DwarfDebug *D) { > + uint64_t PrevHash = UINT64_MAX; > + for (size_t i = 0; i < Buckets.size(); ++i) { > + for (HashList::const_iterator HI = Buckets[i].begin(), > + HE = Buckets[i].end(); HI != HE; ++HI) { > + // Remember to emit the label for our offset. > + Asm->OutStreamer.EmitLabel((*HI)->Sym); > + Asm->OutStreamer.AddComment((*HI)->Str); > + Asm->EmitSectionOffset(D->getStringPoolEntry((*HI)->Str), > + D->getDwarfStrSectionSym()); > + Asm->OutStreamer.AddComment("Num DIEs"); > + Asm->EmitInt32((*HI)->DIEOffsets.size()); > + for (std::vector::const_iterator > + DI = (*HI)->DIEOffsets.begin(), DE = (*HI)->DIEOffsets.end(); > + DI != DE; ++DI) { > + Asm->EmitInt32((*DI)); > + } > + // Emit a 0 to terminate the data unless we have a hash collision. > + if (PrevHash != (*HI)->HashValue) > + Asm->EmitInt32(0); > + PrevHash = (*HI)->HashValue; > + } > + } > +} > + > +// Emit the entire data structure to the output file. > +void DwarfAccelTable::Emit(AsmPrinter *Asm, MCSymbol *SecBegin, > + DwarfDebug *D) { > + // Emit the header. > + EmitHeader(Asm); > + > + // Emit the buckets. > + EmitBuckets(Asm); > + > + // Emit the hashes. > + EmitHashes(Asm); > + > + // Emit the offsets. > + EmitOffsets(Asm, SecBegin); > + > + // Emit the hash data. > + EmitData(Asm, D); > +} > + > +#ifndef NDEBUG > +void DwarfAccelTable::print(raw_ostream &O) { > + > + Header.print(O); > + HeaderData.print(O); > + > + O << "Entries: \n"; > + for (StringMap::const_iterator > + EI = Entries.begin(), EE = Entries.end(); EI != EE; ++EI) { > + O << "Name: " << (*EI).getKeyData() << "\n"; > + for (DIEArray::const_iterator DI = (*EI).second.begin(), > + DE = (*EI).second.end(); > + DI != DE; ++DI) > + (*DI)->print(O); > + } > + > + O << "Buckets and Hashes: \n"; > + for (size_t i = 0; i < Buckets.size(); ++i) > + for (HashList::const_iterator HI = Buckets[i].begin(), > + HE = Buckets[i].end(); HI != HE; ++HI) > + (*HI)->print(O); > + > + O << "Data: \n"; > + for (std::vector::const_iterator > + DI = Data.begin(), DE = Data.end(); DI != DE; ++DI) > + (*DI)->print(O); > + > + > +} > +#endif > > Added: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h?rev=143921&view=auto > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h (added) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Mon Nov 7 03:18:42 2011 > @@ -0,0 +1,254 @@ > +//==-- llvm/CodeGen/DwarfAccelTable.h - Dwarf Accelerator Tables -*- C++ -*-==// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// > +// This file contains support for writing dwarf accelerator tables. > +// > +//===----------------------------------------------------------------------===// > + > +#ifndef CODEGEN_ASMPRINTER_DWARFACCELTABLE_H__ > +#define CODEGEN_ASMPRINTER_DWARFACCELTABLE_H__ > + > +#include "llvm/ADT/StringMap.h" > +#include "llvm/MC/MCSymbol.h" > +#include "llvm/Support/Dwarf.h" > +#include "llvm/Support/DataTypes.h" > +#include "llvm/Support/Debug.h" > +#include "llvm/Support/ErrorHandling.h" > +#include "llvm/Support/Format.h" > +#include "llvm/Support/FormattedStream.h" > +#include > +#include > + > +// The apple dwarf accelerator tables are an indirect hash table optimized > +// for null lookup rather than access to known data. They are output into > +// an on-disk format that looks like this: > +// > +// .-------------. > +// | HEADER | > +// |-------------| > +// | BUCKETS | > +// |-------------| > +// | HASHES | > +// |-------------| > +// | OFFSETS | > +// |-------------| > +// | DATA | > +// `-------------' > +// > +// where the header contains a magic number, version, type of hash function, > +// the number of buckets, total number of hashes, and room for a special > +// struct of data and the length of that struct. > +// > +// The buckets contain an index (e.g. 6) into the hashes array. The hashes > +// section contains all of the 32-bit hash values in contiguous memory, and > +// the offsets contain the offset into the data area for the particular > +// hash. > +// > +// For a lookup example, we could hash a function name and take it modulo the > +// number of buckets giving us our bucket. From there we take the bucket value > +// as an index into the hashes table and look at each successive hash as long > +// as the hash value is still the same modulo result (bucket value) as earlier. > +// If we have a match we look at that same entry in the offsets table and > +// grab the offset in the data for our final match. > + > +namespace llvm { > + > +class AsmPrinter; > +class DIE; > +class DwarfDebug; > + > +class DwarfAccelTable { > + > + enum HashFunctionType { > + eHashFunctionDJB = 0u > + }; > + > + static uint32_t HashDJB (const char *s) { > + uint32_t h = 5381; > + for (unsigned char c = *s; c; c = *++s) > + h = ((h << 5) + h) + c; > + return h; > + } We have an implementation of djb's hash in StringExtras.h. If you don't want to use that function this version should at least take a StringRef ? > + > + // Helper function to compute the number of buckets needed based on > + // the number of unique hashes. > + void ComputeBucketCount (void); > + > + struct TableHeader { > + uint32_t magic; // 'HASH' magic value to allow endian detection > + uint16_t version; // Version number. > + uint16_t hash_function; // The hash function enumeration that was used. > + uint32_t bucket_count; // The number of buckets in this hash table. > + uint32_t hashes_count; // The total number of unique hash values > + // and hash data offsets in this table. > + uint32_t header_data_len; // The bytes to skip to get to the hash > + // indexes (buckets) for correct alignment. > + // Also written to disk is the implementation specific header data. > + > + static const uint32_t MagicHash = 0x48415348; > + > + TableHeader (uint32_t data_len) : > + magic (MagicHash), version (1), hash_function (eHashFunctionDJB), > + bucket_count (0), hashes_count (0), header_data_len (data_len) > + {}; > + > +#ifndef NDEBUG > + void print(raw_ostream &O) { > + O << "Magic: " << format("0x%x", magic) << "\n" > + << "Version: " << version << "\n" > + << "Hash Function: " << hash_function << "\n" > + << "Bucket Count: " << bucket_count << "\n" > + << "Header Data Length: " << header_data_len << "\n"; > + } > + void dump() { print(dbgs()); } > +#endif > + }; > + > +public: > + // The HeaderData describes the form of each set of data. In general this > + // is as a list of atoms (atom_count) where each atom contains a type > + // (AtomType type) of data, and an encoding form (form). In the case of > + // data that is referenced via DW_FORM_ref_* the die_offset_base is > + // used to describe the offset for all forms in the list of atoms. > + // This also serves as a public interface of sorts. > + // When written to disk this will have the form: > + // > + // uint32_t die_offset_base > + // uint32_t atom_count > + // atom_count Atoms > + enum AtomType { > + eAtomTypeNULL = 0u, > + eAtomTypeDIEOffset = 1u, // DIE offset, check form for encoding > + eAtomTypeCUOffset = 2u, // DIE offset of the compiler unit header that > + // contains the item in question > + eAtomTypeTag = 3u, // DW_TAG_xxx value, should be encoded as > + // DW_FORM_data1 (if no tags exceed 255) or > + // DW_FORM_data2. > + eAtomTypeNameFlags = 4u, // Flags from enum NameFlags > + eAtomTypeTypeFlags = 5u // Flags from enum TypeFlags > + }; > + > + // Make these public so that they can be used as a general interface to > + // the class. > + struct Atom { > + AtomType type; // enum AtomType > + uint16_t form; // DWARF DW_FORM_ defines > + > + Atom(AtomType type, uint16_t form) : type(type), form(form) {}; > + static const char * AtomTypeString(enum AtomType); > +#ifndef NDEBUG > + void print(raw_ostream &O) { > + O << "Type: " << dwarf::TagString(type) << "\n" > + << "Form: " << dwarf::FormEncodingString(form) << "\n"; > + } > + void dump() { > + print(dbgs()); > + } > +#endif > + }; > + > + private: > + struct TableHeaderData { > + > + uint32_t die_offset_base; > + std::vector Atoms; > + > + TableHeaderData(DwarfAccelTable::Atom Atom, uint32_t offset = 0) > + : die_offset_base(offset) { > + Atoms.push_back(Atom); > + } > + > +#ifndef NDEBUG > + void print (raw_ostream &O) { > + O << "die_offset_base: " << die_offset_base << "\n"; > + for (size_t i = 0; i < Atoms.size(); i++) > + Atoms[i].print(O); > + } > + void dump() { > + print(dbgs()); > + } > +#endif > + }; > + > + // The data itself consists of a str_offset (to deal with collisions in > + // some magical way? this looks like the KeyType from the spec, which > + // should mean an integer compare on read), a count of the DIEs in the > + // hash and the offsets to the DIEs themselves. > + // On disk each data section is ended with a 0 KeyType as the end of the > + // hash chain. > + // On output this looks like: > + // uint32_t str_offset > + // uint32_t hash_data_count > + // HashData[hash_data_count] > + struct HashData { > + StringRef Str; > + uint32_t HashValue; > + MCSymbol *Sym; > + std::vector DIEOffsets; // offsets > + HashData(StringRef S) : Str(S) { > + HashValue = DwarfAccelTable::HashDJB(S.str().c_str()); ? and eliminate the temporary string. > + } > + void addOffset(uint32_t off) { DIEOffsets.push_back(off); } > + #ifndef NDEBUG > + void print(raw_ostream &O) { > + O << "Name: " << Str << "\n"; > + O << " Hash Value: " << format("0x%x", HashValue) << "\n"; > + O << " Symbol: " ; > + if (Sym) Sym->print(O); > + else O << ""; > + O << "\n"; > + for (size_t i = 0; i < DIEOffsets.size(); i++) > + O << " Offset: " << DIEOffsets[i] << "\n"; > + } > + void dump() { > + print(dbgs()); > + } > + #endif > + }; > + > + DwarfAccelTable(const DwarfAccelTable&); // DO NOT IMPLEMENT > + void operator=(const DwarfAccelTable&); // DO NOT IMPLEMENT > + > + // Internal Functions > + void EmitHeader(AsmPrinter *); > + void EmitBuckets(AsmPrinter *); > + void EmitHashes(AsmPrinter *); > + void EmitOffsets(AsmPrinter *, MCSymbol *); > + void EmitData(AsmPrinter *, DwarfDebug *D); > + > + // Output Variables > + TableHeader Header; > + TableHeaderData HeaderData; > + std::vector Data; > + > + // String Data > + typedef std::vector DIEArray; > + typedef StringMap StringEntries; > + StringEntries Entries; > + > + // Buckets/Hashes/Offsets > + typedef std::vector HashList; > + typedef std::vector BucketList; > + BucketList Buckets; > + HashList Hashes; > + > + // Public Implementation > + public: > + DwarfAccelTable(DwarfAccelTable::Atom Atom); > + void AddName(StringRef, DIE*); > + void FinalizeTable(AsmPrinter *, const char *); > + void Emit(AsmPrinter *, MCSymbol *, DwarfDebug *); > +#ifndef NDEBUG > + void print(raw_ostream &O); > + void dump() { print(dbgs()); } > +#endif > +}; > + > +} > +#endif > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From eli.friedman at gmail.com Mon Nov 7 10:41:10 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 7 Nov 2011 08:41:10 -0800 Subject: [llvm-commits] [PATCH] Don't introduce custom nodes when building divide by constant after legalization In-Reply-To: <4EB7C876.7050806@xmos.com> References: <4EAFEF29.7080004@xmos.com> <4EB7C876.7050806@xmos.com> Message-ID: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20111031/131212.html -Eli On Mon, Nov 7, 2011 at 4:00 AM, Richard Osborne wrote: > Ping, is that patch OK to apply? > > Thanks, > > Richard > > On 01/11/11 13:07, Richard Osborne wrote: > > This patch changes TargetLowering::BuildSDIV() and > TargetLowering::BuildUDIV() so they avoid introducing nodes that require > custom handling after legalization has taken place. This fixes PR11283. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -- > Richard Osborne | XMOS > http://www.xmos.com > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From baldrick at free.fr Mon Nov 7 11:00:50 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 07 Nov 2011 17:00:50 -0000 Subject: [llvm-commits] [zorg] r143963 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20111107170050.E01A12A6C12C@llvm.org> Author: baldrick Date: Mon Nov 7 11:00:50 2011 New Revision: 143963 URL: http://llvm.org/viewvc/llvm-project?rev=143963&view=rev Log: Recent gcc miscompiles these - they are expected to fail. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=143963&r1=143962&r2=143963&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Nov 7 11:00:50 2011 @@ -146,6 +146,8 @@ gxxincludedir='/usr/include/c++/4.2.1')}, clang_i386_linux_xfails = [ + 'GCC.MultiSource/Applications/siod/siod', + 'GCC.MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame', 'GCCAS.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', 'Bytecode.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', 'LLC.MultiSource/Applications/oggenc/oggenc', From richard at xmos.com Mon Nov 7 11:09:05 2011 From: richard at xmos.com (Richard Osborne) Date: Mon, 07 Nov 2011 17:09:05 -0000 Subject: [llvm-commits] [llvm] r143964 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <20111107170905.876102A6C12C@llvm.org> Author: friedgold Date: Mon Nov 7 11:09:05 2011 New Revision: 143964 URL: http://llvm.org/viewvc/llvm-project?rev=143964&view=rev Log: Don't introduce custom nodes after legalization in TargetLowering::BuildSDIV() and TargetLowering::BuildUDIV(). Fixes PR11283 Modified: llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=143964&r1=143963&r2=143964&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Nov 7 11:09:05 2011 @@ -1595,9 +1595,9 @@ // SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, SelectionDAG &DAG) const; - SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, + SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector* Created) const; - SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, + SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector* Created) const; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=143964&r1=143963&r2=143964&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Nov 7 11:09:05 2011 @@ -7822,7 +7822,7 @@ /// SDValue DAGCombiner::BuildSDIV(SDNode *N) { std::vector Built; - SDValue S = TLI.BuildSDIV(N, DAG, &Built); + SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); for (std::vector::iterator ii = Built.begin(), ee = Built.end(); ii != ee; ++ii) @@ -7836,7 +7836,7 @@ /// SDValue DAGCombiner::BuildUDIV(SDNode *N) { std::vector Built; - SDValue S = TLI.BuildUDIV(N, DAG, &Built); + SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); for (std::vector::iterator ii = Built.begin(), ee = Built.end(); ii != ee; ++ii) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=143964&r1=143963&r2=143964&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Nov 7 11:09:05 2011 @@ -3242,8 +3242,9 @@ /// return a DAG expression to select that will generate the same value by /// multiplying by a magic number. See: /// -SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, - std::vector* Created) const { +SDValue TargetLowering:: +BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, + std::vector* Created) const { EVT VT = N->getValueType(0); DebugLoc dl= N->getDebugLoc(); @@ -3258,10 +3259,12 @@ // Multiply the numerator (operand 0) by the magic value // FIXME: We should support doing a MUL in a wider type SDValue Q; - if (isOperationLegalOrCustom(ISD::MULHS, VT)) + if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : + isOperationLegalOrCustom(ISD::MULHS, VT)) Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), DAG.getConstant(magics.m, VT)); - else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) + else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : + isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), N->getOperand(0), DAG.getConstant(magics.m, VT)).getNode(), 1); @@ -3299,8 +3302,9 @@ /// return a DAG expression to select that will generate the same value by /// multiplying by a magic number. See: /// -SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, - std::vector* Created) const { +SDValue TargetLowering:: +BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, + std::vector* Created) const { EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); @@ -3332,9 +3336,11 @@ // Multiply the numerator (operand 0) by the magic value // FIXME: We should support doing a MUL in a wider type - if (isOperationLegalOrCustom(ISD::MULHU, VT)) + if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : + isOperationLegalOrCustom(ISD::MULHU, VT)) Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); - else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) + else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : + isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, DAG.getConstant(magics.m, VT)).getNode(), 1); else From richard at xmos.com Mon Nov 7 11:11:55 2011 From: richard at xmos.com (Richard Osborne) Date: Mon, 7 Nov 2011 17:11:55 +0000 Subject: [llvm-commits] [PATCH] Don't introduce custom nodes when building divide by constant after legalization In-Reply-To: References: <4EAFEF29.7080004@xmos.com> <4EB7C876.7050806@xmos.com> Message-ID: <4EB8115B.3000602@xmos.com> Sorry, I somehow completely missed your first reply. Thanks for the review. Committed in r143964. On 07/11/11 16:41, Eli Friedman wrote: > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20111031/131212.html > > -Eli > > On Mon, Nov 7, 2011 at 4:00 AM, Richard Osborne wrote: >> Ping, is that patch OK to apply? >> >> Thanks, >> >> Richard >> >> On 01/11/11 13:07, Richard Osborne wrote: >> >> This patch changes TargetLowering::BuildSDIV() and >> TargetLowering::BuildUDIV() so they avoid introducing nodes that require >> custom handling after legalization has taken place. This fixes PR11283. >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> -- >> Richard Osborne | XMOS >> http://www.xmos.com >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> -- Richard Osborne | XMOS http://www.xmos.com From resistor at mac.com Mon Nov 7 11:21:37 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 07 Nov 2011 17:21:37 -0000 Subject: [llvm-commits] [llvm] r143966 - /llvm/trunk/tools/llvm-objdump/MachODump.cpp Message-ID: <20111107172137.377BF2A6C12C@llvm.org> Author: resistor Date: Mon Nov 7 11:21:36 2011 New Revision: 143966 URL: http://llvm.org/viewvc/llvm-project?rev=143966&view=rev Log: Fix llvm-objdump's MachO mode to not depend on the value returned by RelocationRef::getInfo(). Modified: llvm/trunk/tools/llvm-objdump/MachODump.cpp Modified: llvm/trunk/tools/llvm-objdump/MachODump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/MachODump.cpp?rev=143966&r1=143965&r2=143966&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/MachODump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/MachODump.cpp Mon Nov 7 11:21:36 2011 @@ -385,7 +385,7 @@ bool symbolTableWorked = false; // Parse relocations. - std::vector > Relocs; + std::vector > Relocs; error_code ec; for (relocation_iterator RI = Sections[SectIdx].begin_relocations(), RE = Sections[SectIdx].end_relocations(); RI != RE; RI.increment(ec)) { @@ -394,10 +394,10 @@ Sections[SectIdx].getAddress(SectionAddress); RelocOffset -= SectionAddress; - uint64_t RelocInfo; - RI->getType(RelocInfo); + SymbolRef RelocSym; + RI->getSymbol(RelocSym); - Relocs.push_back(std::make_pair(RelocOffset, RelocInfo)); + Relocs.push_back(std::make_pair(RelocOffset, RelocSym)); } array_pod_sort(Relocs.begin(), Relocs.end()); @@ -594,8 +594,8 @@ Relocs[j].first < SectAddress + Inst.Address + Inst.Size) { StringRef SymName; uint64_t Addr; - UnsortedSymbols[Relocs[j].second].getName(SymName); - UnsortedSymbols[Relocs[j].second].getAddress(Addr); + Relocs[j].second.getAddress(Addr); + Relocs[j].second.getName(SymName); outs() << "\t# " << SymName << ' '; DumpAddress(Addr, Sections, MachOObj, outs()); From echristo at apple.com Mon Nov 7 12:10:17 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 18:10:17 -0000 Subject: [llvm-commits] [llvm] r143970 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20111107181018.0BB062A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 12:10:17 2011 New Revision: 143970 URL: http://llvm.org/viewvc/llvm-project?rev=143970&view=rev Log: Allow for the case where the name of the subprogram is "". Fixes a self-host error. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=143970&r1=143969&r2=143970&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 7 12:10:17 2011 @@ -525,6 +525,7 @@ } static bool isObjCClass(StringRef Name) { + if (Name == "") return false; return Name[0] == '+' || Name[0] == '-'; } From echristo at apple.com Mon Nov 7 12:34:48 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 18:34:48 -0000 Subject: [llvm-commits] [llvm] r143974 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Message-ID: <20111107183448.1389C2A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 12:34:47 2011 New Revision: 143974 URL: http://llvm.org/viewvc/llvm-project?rev=143974&view=rev Log: Avoid the use of a local temporary for comment twines. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp?rev=143974&r1=143973&r2=143974&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Mon Nov 7 12:34:47 2011 @@ -128,8 +128,7 @@ void DwarfAccelTable::EmitBuckets(AsmPrinter *Asm) { unsigned index = 0; for (size_t i = 0; i < Buckets.size(); ++i) { - Twine Comment = Twine("Bucket ") + Twine(i); - Asm->OutStreamer.AddComment(Comment); + Asm->OutStreamer.AddComment("Bucket " + Twine(i)); if (Buckets[i].size() != 0) Asm->EmitInt32(index); else @@ -144,8 +143,7 @@ for (size_t i = 0; i < Buckets.size(); ++i) { for (HashList::const_iterator HI = Buckets[i].begin(), HE = Buckets[i].end(); HI != HE; ++HI) { - Twine Comment = Twine("Hash in Bucket ") + Twine(i); - Asm->OutStreamer.AddComment(Comment); + Asm->OutStreamer.AddComment("Hash in Bucket " + Twine(i)); Asm->EmitInt32((*HI)->HashValue); } } @@ -159,8 +157,7 @@ for (size_t i = 0; i < Buckets.size(); ++i) { for (HashList::const_iterator HI = Buckets[i].begin(), HE = Buckets[i].end(); HI != HE; ++HI) { - Twine Comment = Twine("Offset in Bucket ") + Twine(i); - Asm->OutStreamer.AddComment(Comment); + Asm->OutStreamer.AddComment("Offset in Bucket " + Twine(i)); MCContext &Context = Asm->OutStreamer.getContext(); const MCExpr *Sub = MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create((*HI)->Sym, Context), From dpatel at apple.com Mon Nov 7 12:38:34 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 07 Nov 2011 10:38:34 -0800 Subject: [llvm-commits] [llvm] r143970 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp In-Reply-To: <20111107181018.0BB062A6C12C@llvm.org> References: <20111107181018.0BB062A6C12C@llvm.org> Message-ID: On Nov 7, 2011, at 10:10 AM, Eric Christopher wrote: > Author: echristo > Date: Mon Nov 7 12:10:17 2011 > New Revision: 143970 > > URL: http://llvm.org/viewvc/llvm-project?rev=143970&view=rev > Log: > Allow for the case where the name of the subprogram is "". > > Fixes a self-host error. StringRef.startswith() is handy. Thanks! - Devang > > Modified: > llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=143970&r1=143969&r2=143970&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 7 12:10:17 2011 > @@ -525,6 +525,7 @@ > } > > static bool isObjCClass(StringRef Name) { > + if (Name == "") return false; > return Name[0] == '+' || Name[0] == '-'; > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Mon Nov 7 12:53:23 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 18:53:23 -0000 Subject: [llvm-commits] [llvm] r143982 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20111107185323.888932A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 12:53:23 2011 New Revision: 143982 URL: http://llvm.org/viewvc/llvm-project?rev=143982&view=rev Log: Use StringRef::startswith to do some string comparisons. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=143982&r1=143981&r2=143982&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 7 12:53:23 2011 @@ -525,20 +525,17 @@ } static bool isObjCClass(StringRef Name) { - if (Name == "") return false; - return Name[0] == '+' || Name[0] == '-'; + return Name.startswith("+") || Name.startswith("-"); } static bool hasObjCCategory(StringRef Name) { - if (Name[0] != '+' && Name[0] != '-') - return false; + if (!isObjCClass(Name)) return false; size_t pos = Name.find(')'); if (pos != std::string::npos) { if (Name[pos+1] != ' ') return false; return true; } - return false; } From echristo at apple.com Mon Nov 7 12:56:05 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 10:56:05 -0800 Subject: [llvm-commits] [llvm] r143970 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp In-Reply-To: References: <20111107181018.0BB062A6C12C@llvm.org> Message-ID: On Nov 7, 2011, at 10:38 AM, Devang Patel wrote: > > On Nov 7, 2011, at 10:10 AM, Eric Christopher wrote: > >> Author: echristo >> Date: Mon Nov 7 12:10:17 2011 >> New Revision: 143970 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=143970&view=rev >> Log: >> Allow for the case where the name of the subprogram is "". >> >> Fixes a self-host error. > > StringRef.startswith() is handy. Hey cool. Thanks :) -eric From ahatanaka at mips.com Mon Nov 7 12:57:41 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 07 Nov 2011 18:57:41 -0000 Subject: [llvm-commits] [llvm] r143988 - /llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Message-ID: <20111107185741.B48052A6C12C@llvm.org> Author: ahatanak Date: Mon Nov 7 12:57:41 2011 New Revision: 143988 URL: http://llvm.org/viewvc/llvm-project?rev=143988&view=rev Log: Add 64-bit to 32-bit trunc pattern. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=143988&r1=143987&r2=143988&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Nov 7 12:57:41 2011 @@ -172,3 +172,8 @@ defm : SetgtPats; defm : SetgePats; defm : SetgeImmPats; + +// truncate +def : Pat<(i32 (trunc CPU64Regs:$src)), + (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>; + From ahatanaka at mips.com Mon Nov 7 12:59:50 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 07 Nov 2011 18:59:50 -0000 Subject: [llvm-commits] [llvm] r143989 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsISelLowering.h MipsInstrInfo.td Message-ID: <20111107185950.411E12A6C12C@llvm.org> Author: ahatanak Date: Mon Nov 7 12:59:49 2011 New Revision: 143989 URL: http://llvm.org/viewvc/llvm-project?rev=143989&view=rev Log: Make the type of shift amount i32 in order to reduce the number of shift instruction definitions. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td llvm/trunk/lib/Target/Mips/MipsISelLowering.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=143989&r1=143988&r2=143989&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Nov 7 12:59:49 2011 @@ -32,7 +32,7 @@ def immZExt5_64 : ImmLeaf; // imm32_63 predicate - True if imm is in range [32, 63]. -def imm32_63 : ImmLeaf= 32 && (int32_t)Imm < 64;}], Subtract32>; @@ -43,12 +43,12 @@ // 64-bit shift instructions. class shift_rotate_imm64 func, bits<5> isRotate, string instr_asm, SDNode OpNode>: - shift_rotate_imm; class shift_rotate_imm64_32 func, bits<5> isRotate, string instr_asm, SDNode OpNode>: - shift_rotate_imm; // Mul, Div Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=143989&r1=143988&r2=143989&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Mon Nov 7 12:59:49 2011 @@ -98,6 +98,8 @@ public: explicit MipsTargetLowering(MipsTargetMachine &TM); + virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; } + virtual bool allowsUnalignedMemoryAccesses (EVT VT) const; /// LowerOperation - Provide custom lowering hooks for some operations. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=143989&r1=143988&r2=143989&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Nov 7 12:59:49 2011 @@ -327,9 +327,9 @@ class shift_rotate_reg func, bits<5> isRotate, string instr_asm, SDNode OpNode, RegisterClass RC>: - FR<0x00, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), + FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt), !strconcat(instr_asm, "\t$rd, $rt, $rs"), - [(set RC:$rd, (OpNode RC:$rt, RC:$rs))], IIAlu> { + [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> { let shamt = isRotate; } From ahatanaka at mips.com Mon Nov 7 13:01:49 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 07 Nov 2011 19:01:49 -0000 Subject: [llvm-commits] [llvm] r143990 - /llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Message-ID: <20111107190149.EC6D92A6C12C@llvm.org> Author: ahatanak Date: Mon Nov 7 13:01:49 2011 New Revision: 143990 URL: http://llvm.org/viewvc/llvm-project?rev=143990&view=rev Log: Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted when shift amount is larger than 32. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=143990&r1=143989&r2=143990&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Nov 7 13:01:49 2011 @@ -155,9 +155,9 @@ (ORi64 ZERO_64, imm:$in)>; // zextloadi32_u -def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>, +def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64_P8 addr:$a), 0), 0)>, Requires<[IsN64]>; -def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>, +def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64 addr:$a), 0), 0)>, Requires<[NotN64]>; // hi/lo relocs From ahatanaka at mips.com Mon Nov 7 13:03:41 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 07 Nov 2011 19:03:41 -0000 Subject: [llvm-commits] [llvm] r143991 - /llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Message-ID: <20111107190341.2C7FD2A6C12C@llvm.org> Author: ahatanak Date: Mon Nov 7 13:03:40 2011 New Revision: 143991 URL: http://llvm.org/viewvc/llvm-project?rev=143991&view=rev Log: Use array_lengthof to compute the number of iterations of a loop. Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=143991&r1=143990&r2=143991&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon Nov 7 13:03:40 2011 @@ -191,23 +191,23 @@ getReservedRegs(const MachineFunction &MF) const { static const unsigned ReservedCPURegs[] = { Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, - Mips::GP, Mips::SP, Mips::FP, Mips::RA, 0 + Mips::GP, Mips::SP, Mips::FP, Mips::RA }; static const unsigned ReservedCPU64Regs[] = { Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, - Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 0 + Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64 }; BitVector Reserved(getNumRegs()); typedef TargetRegisterClass::iterator RegIter; - for (const unsigned *Reg = ReservedCPURegs; *Reg; ++Reg) - Reserved.set(*Reg); + for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I) + Reserved.set(ReservedCPURegs[I]); if (Subtarget.hasMips64()) { - for (const unsigned *Reg = ReservedCPU64Regs; *Reg; ++Reg) - Reserved.set(*Reg); + for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I) + Reserved.set(ReservedCPU64Regs[I]); // Reserve all registers in AFGR64. for (RegIter Reg = Mips::AFGR64RegisterClass->begin(); From ahatanaka at mips.com Mon Nov 7 13:06:10 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 07 Nov 2011 19:06:10 -0000 Subject: [llvm-commits] [llvm] r143992 - /llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Message-ID: <20111107190610.C4CE22A6C12C@llvm.org> Author: ahatanak Date: Mon Nov 7 13:06:10 2011 New Revision: 143992 URL: http://llvm.org/viewvc/llvm-project?rev=143992&view=rev Log: Define functions that get or set the size of area on callee's stack frame which is used to save va_arg or byval arguments passed in registers. Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.h?rev=143992&r1=143991&r2=143992&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMachineFunction.h (original) +++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Mon Nov 7 13:06:10 2011 @@ -51,12 +51,16 @@ mutable int DynAllocFI; // Frame index of dynamically allocated stack area. unsigned MaxCallFrameSize; + // Size of area on callee's stack frame which is used to save va_arg or + // byval arguments passed in registers. + unsigned RegSaveAreaSize; + public: MipsFunctionInfo(MachineFunction& MF) : MF(MF), SRetReturnReg(0), GlobalBaseReg(0), VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)), OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), DynAllocFI(0), - MaxCallFrameSize(0) + MaxCallFrameSize(0), RegSaveAreaSize(0) {} bool isInArgFI(int FI) const { @@ -100,6 +104,11 @@ unsigned getMaxCallFrameSize() const { return MaxCallFrameSize; } void setMaxCallFrameSize(unsigned S) { MaxCallFrameSize = S; } + + unsigned getRegSaveAreaSize() const { return RegSaveAreaSize; } + void setRegSaveAreaSize(unsigned S) { + if (RegSaveAreaSize < S) RegSaveAreaSize = S; + } }; } // end of namespace llvm From ahatanaka at mips.com Mon Nov 7 13:07:35 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 07 Nov 2011 19:07:35 -0000 Subject: [llvm-commits] [llvm] r143993 - /llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Message-ID: <20111107190735.A946A2A6C12C@llvm.org> Author: ahatanak Date: Mon Nov 7 13:07:35 2011 New Revision: 143993 URL: http://llvm.org/viewvc/llvm-project?rev=143993&view=rev Log: Include RegSaveAreaSize in the computation of stack size. Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?rev=143993&r1=143992&r2=143993&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Mon Nov 7 13:07:35 2011 @@ -157,6 +157,7 @@ (MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) : MipsFI->getMaxCallFrameSize(); unsigned StackSize = AlignOffset(LocalVarAreaOffset, StackAlign) + + AlignOffset(MipsFI->getRegSaveAreaSize(), StackAlign) + AlignOffset(MFI->getStackSize(), StackAlign); // Update stack size From ahatanaka at mips.com Mon Nov 7 13:10:49 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 07 Nov 2011 19:10:49 -0000 Subject: [llvm-commits] [llvm] r143994 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsInstrInfo.td Message-ID: <20111107191050.0C76C2A6C12C@llvm.org> Author: ahatanak Date: Mon Nov 7 13:10:49 2011 New Revision: 143994 URL: http://llvm.org/viewvc/llvm-project?rev=143994&view=rev Log: Add definition of 64-bit load upper immediate. Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=143994&r1=143993&r2=143994&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Nov 7 13:10:49 2011 @@ -69,6 +69,7 @@ def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>; def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>; +def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; /// Arithmetic Instructions (3-Operand, R-Type) def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>; Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=143994&r1=143993&r2=143994&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Nov 7 13:10:49 2011 @@ -334,8 +334,8 @@ } // Load Upper Imediate -class LoadUpper op, string instr_asm>: - FI op, string instr_asm, RegisterClass RC, Operand Imm>: + FI { let rs = 0; } @@ -680,7 +680,7 @@ def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>; def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>; def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>; -def LUi : LoadUpper<0x0f, "lui">; +def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; /// Arithmetic Instructions (3-Operand, R-Type) def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>; From stoklund at 2pi.dk Mon Nov 7 13:15:59 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 07 Nov 2011 19:15:59 -0000 Subject: [llvm-commits] [llvm] r143996 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/avx-basic.ll test/CodeGen/X86/sse2-blend.ll test/CodeGen/X86/sse2.ll test/CodeGen/X86/vec_return.ll test/CodeGen/X86/vec_zero.ll test/CodeGen/X86/vec_zero_cse.ll test/CodeGen/X86/xor.ll Message-ID: <20111107191559.40ABF2A6C12C@llvm.org> Author: stoklund Date: Mon Nov 7 13:15:58 2011 New Revision: 143996 URL: http://llvm.org/viewvc/llvm-project?rev=143996&view=rev Log: Expand V_SET0 to xorps by default. The xorps instruction is smaller than pxor, so prefer that encoding. The ExecutionDepsFix pass will switch the encoding to pxor and xorpd when appropriate. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/test/CodeGen/X86/avx-basic.ll llvm/trunk/test/CodeGen/X86/sse2-blend.ll llvm/trunk/test/CodeGen/X86/sse2.ll llvm/trunk/test/CodeGen/X86/vec_return.ll llvm/trunk/test/CodeGen/X86/vec_zero.ll llvm/trunk/test/CodeGen/X86/vec_zero_cse.ll llvm/trunk/test/CodeGen/X86/xor.ll Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=143996&r1=143995&r2=143996&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Nov 7 13:15:58 2011 @@ -2420,7 +2420,7 @@ bool HasAVX = TM.getSubtarget().hasAVX(); switch (MI->getOpcode()) { case X86::V_SET0: - return Expand2AddrUndef(MI, get(HasAVX ? X86::VPXORrr : X86::PXORrr)); + return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); case X86::TEST8ri_NOREX: MI->setDesc(get(X86::TEST8ri)); return true; Modified: llvm/trunk/test/CodeGen/X86/avx-basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-basic.ll?rev=143996&r1=143995&r2=143996&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-basic.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-basic.ll Mon Nov 7 13:15:58 2011 @@ -6,7 +6,7 @@ define void @zero128() nounwind ssp { entry: - ; CHECK: vpxor + ; CHECK: vxorps ; CHECK: vmovaps store <4 x float> zeroinitializer, <4 x float>* @z, align 16 ret void Modified: llvm/trunk/test/CodeGen/X86/sse2-blend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-blend.ll?rev=143996&r1=143995&r2=143996&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse2-blend.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse2-blend.ll Mon Nov 7 13:15:58 2011 @@ -26,8 +26,10 @@ ret void } +; FIXME: The -mattr=+sse2,-sse41 disable the ExecutionDepsFix pass causing the +; mixed domains here. ; CHECK: vsel_i64 -; CHECK: pxor +; CHECK: xorps ; CHECK: pand ; CHECK: andnps ; CHECK: orps @@ -41,8 +43,10 @@ ret void } +; FIXME: The -mattr=+sse2,-sse41 disable the ExecutionDepsFix pass causing the +; mixed domains here. ; CHECK: vsel_double -; CHECK: pxor +; CHECK: xorps ; CHECK: pand ; CHECK: andnps ; CHECK: orps Modified: llvm/trunk/test/CodeGen/X86/sse2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2.ll?rev=143996&r1=143995&r2=143996&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse2.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse2.ll Mon Nov 7 13:15:58 2011 @@ -98,7 +98,7 @@ ret void ; CHECK: test7: -; CHECK: pxor %xmm0, %xmm0 +; CHECK: xorps %xmm0, %xmm0 ; CHECK: movaps %xmm0, 0 } Modified: llvm/trunk/test/CodeGen/X86/vec_return.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_return.ll?rev=143996&r1=143995&r2=143996&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_return.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_return.ll Mon Nov 7 13:15:58 2011 @@ -1,12 +1,17 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 > %t -; RUN: grep pxor %t | count 1 -; RUN: grep movaps %t | count 1 -; RUN: not grep shuf %t +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +; Without any typed operations, always use the smaller xorps. +; CHECK: test +; CHECK: xorps define <2 x double> @test() { ret <2 x double> zeroinitializer } +; Prefer a constant pool load here. +; CHECK: test2 +; CHECK-NOT: shuf +; CHECK: movaps LCP +; CHECK-NEXT: ret define <4 x i32> @test2() nounwind { ret <4 x i32> < i32 0, i32 0, i32 1, i32 0 > } Modified: llvm/trunk/test/CodeGen/X86/vec_zero.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_zero.ll?rev=143996&r1=143995&r2=143996&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_zero.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_zero.ll Mon Nov 7 13:15:58 2011 @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +; CHECK: foo ; CHECK: xorps define void @foo(<4 x float>* %P) { %T = load <4 x float>* %P ; <<4 x float>> [#uses=1] @@ -8,6 +9,7 @@ ret void } +; CHECK: bar ; CHECK: pxor define void @bar(<4 x i32>* %P) { %T = load <4 x i32>* %P ; <<4 x i32>> [#uses=1] @@ -16,3 +18,13 @@ ret void } +; Without any type hints from operations, we fall back to the smaller xorps. +; The IR type <4 x i32> is ignored. +; CHECK: untyped_zero +; CHECK: xorps +; CHECK: movaps +define void @untyped_zero(<4 x i32>* %p) { +entry: + store <4 x i32> zeroinitializer, <4 x i32>* %p, align 16 + ret void +} Modified: llvm/trunk/test/CodeGen/X86/vec_zero_cse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_zero_cse.ll?rev=143996&r1=143995&r2=143996&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_zero_cse.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_zero_cse.ll Mon Nov 7 13:15:58 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 1 +; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep xorps | count 1 ; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pcmpeqd | count 1 ; 64-bit stores here do not use MMX. Modified: llvm/trunk/test/CodeGen/X86/xor.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor.ll?rev=143996&r1=143995&r2=143996&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/xor.ll (original) +++ llvm/trunk/test/CodeGen/X86/xor.ll Mon Nov 7 13:15:58 2011 @@ -8,7 +8,7 @@ ret <4 x i32> %tmp ; X32: test1: -; X32: pxor %xmm0, %xmm0 +; X32: xorps %xmm0, %xmm0 ; X32: ret } From nicholas at mxc.ca Mon Nov 7 13:25:03 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 07 Nov 2011 11:25:03 -0800 Subject: [llvm-commits] patch: make gvn a little pickier about nocapture Message-ID: <4EB8308F.5000805@mxc.ca> This patch addresses a failure-to-devirtualize case that GCC handles. Long story short, the problem is that GVN looks at a load of an alloca and queries MemDep who walks upwards and finds a function call with no arguments. When MemDep asks BasicAA whether it could alias the alloca, BasicAA determines that the alloca escapes and concludes that the callee could modify it. The reality is that the pointer hasn't escaped yet at this point in the program, it only escapes some time after the call. The fix in this patch comes in two ugly parts. First I refactor PointerMayBeCaptured to take an object that it informs of the captures, and gives it the opportunity to prune the search. This isn't the prettiest design ever (the function is now templated and implemented in the header), but I think it's the right trade-off. The existing API is preserved and causes one instantiation inside CaptureTracking.cpp where it always used to be. Second I copy+paste part of basicaa's logic for analyzing ModRef of calls into MemDep, and replace its use of isNonEscapingLocalObject() with my own smarter capture logic that uses a DominatorTree. We can't put this logic inside basicaa because it requires a linear scan over the list of instructions. We could add a new "capture tracker" argument to the AA interface, but it doesn't make sense for any AA impl except basicaa. We could add a method to basicaa and have memdep hand it a pointer to the CaptureTracking callback object, but it's possible that would conflict with another basicaa user who wants to do the same. The other reasonable approach I can think of is adding a new AA pass. All that said, please review! This fixes inline-devirt-{1,2,8}.C in PR8886. Nick -------------- next part -------------- A non-text attachment was scrubbed... Name: rle-escape-1.patch Type: text/x-patch Size: 18922 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111107/2a01298d/attachment.bin From isanbard at gmail.com Mon Nov 7 13:38:34 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 07 Nov 2011 19:38:34 -0000 Subject: [llvm-commits] [llvm] r144000 - /llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp Message-ID: <20111107193834.AB49A2A6C12C@llvm.org> Author: void Date: Mon Nov 7 13:38:34 2011 New Revision: 144000 URL: http://llvm.org/viewvc/llvm-project?rev=144000&view=rev Log: Make sure we don't insert instructions before a landingpad instruction. Modified: llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp Modified: llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp?rev=144000&r1=143999&r2=144000&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp Mon Nov 7 13:38:34 2011 @@ -97,8 +97,8 @@ InsertPt = II.getNormalDest()->begin(); } - for (; isa(InsertPt); ++InsertPt) - /* empty */; // Don't insert before any PHI nodes. + for (; isa(InsertPt) || isa(InsertPt); ++InsertPt) + /* empty */; // Don't insert before any PHI nodes or landingpad instrs. new StoreInst(&I, Slot, InsertPt); return Slot; From stoklund at 2pi.dk Mon Nov 7 14:47:23 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 07 Nov 2011 20:47:23 -0000 Subject: [llvm-commits] [llvm] r144003 - /llvm/trunk/test/CodeGen/X86/vec_return.ll Message-ID: <20111107204723.4E58E2A6C12C@llvm.org> Author: stoklund Date: Mon Nov 7 14:47:23 2011 New Revision: 144003 URL: http://llvm.org/viewvc/llvm-project?rev=144003&view=rev Log: Fix test for Linux. Modified: llvm/trunk/test/CodeGen/X86/vec_return.ll Modified: llvm/trunk/test/CodeGen/X86/vec_return.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_return.ll?rev=144003&r1=144002&r2=144003&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_return.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_return.ll Mon Nov 7 14:47:23 2011 @@ -10,7 +10,7 @@ ; Prefer a constant pool load here. ; CHECK: test2 ; CHECK-NOT: shuf -; CHECK: movaps LCP +; CHECK: movaps {{.*}}CPI ; CHECK-NEXT: ret define <4 x i32> @test2() nounwind { ret <4 x i32> < i32 0, i32 0, i32 1, i32 0 > From isanbard at gmail.com Mon Nov 7 14:52:26 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 07 Nov 2011 20:52:26 -0000 Subject: [llvm-commits] [dragonegg] r144006 - /dragonegg/tags/RELEASE_30/rc3/ Message-ID: <20111107205226.9A45D2A6C12C@llvm.org> Author: void Date: Mon Nov 7 14:52:26 2011 New Revision: 144006 URL: http://llvm.org/viewvc/llvm-project?rev=144006&view=rev Log: Creating release candidate 3 from release_30 branch Added: dragonegg/tags/RELEASE_30/rc3/ (props changed) - copied from r144005, dragonegg/branches/release_30/ Propchange: dragonegg/tags/RELEASE_30/rc3/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Nov 7 14:52:26 2011 @@ -0,0 +1,2 @@ +*.d +target Propchange: dragonegg/tags/RELEASE_30/rc3/ ------------------------------------------------------------------------------ svn:mergeinfo = /dragonegg/trunk:142351,142575,142651,143357 From isanbard at gmail.com Mon Nov 7 14:52:34 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 07 Nov 2011 20:52:34 -0000 Subject: [llvm-commits] [test-suite] r144007 - /test-suite/tags/RELEASE_30/rc3/ Message-ID: <20111107205234.0A93C2A6C12C@llvm.org> Author: void Date: Mon Nov 7 14:52:33 2011 New Revision: 144007 URL: http://llvm.org/viewvc/llvm-project?rev=144007&view=rev Log: Creating release candidate 3 from release_30 branch Added: test-suite/tags/RELEASE_30/rc3/ (props changed) - copied from r144006, test-suite/branches/release_30/ Propchange: test-suite/tags/RELEASE_30/rc3/ ------------------------------------------------------------------------------ --- svn:ignore (added) +++ svn:ignore Mon Nov 7 14:52:33 2011 @@ -0,0 +1,4 @@ +Makefile.config +config.log +config.status +mklib Propchange: test-suite/tags/RELEASE_30/rc3/ ------------------------------------------------------------------------------ svn:mergeinfo = /test-suite/trunk:142659,143460 From isanbard at gmail.com Mon Nov 7 14:52:41 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 07 Nov 2011 20:52:41 -0000 Subject: [llvm-commits] [compiler-rt] r144008 - /compiler-rt/tags/RELEASE_30/rc3/ Message-ID: <20111107205241.4A1CA2A6C12C@llvm.org> Author: void Date: Mon Nov 7 14:52:41 2011 New Revision: 144008 URL: http://llvm.org/viewvc/llvm-project?rev=144008&view=rev Log: Creating release candidate 3 from release_30 branch Added: compiler-rt/tags/RELEASE_30/rc3/ - copied from r144007, compiler-rt/branches/release_30/ From benny.kra at googlemail.com Mon Nov 7 15:00:43 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 07 Nov 2011 21:00:43 -0000 Subject: [llvm-commits] [llvm] r144012 - /llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Message-ID: <20111107210043.AB1393524001@llvm.org> Author: d0k Date: Mon Nov 7 15:00:43 2011 New Revision: 144012 URL: http://llvm.org/viewvc/llvm-project?rev=144012&view=rev Log: Simplify code. No functionality change. Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=144012&r1=144011&r2=144012&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Mon Nov 7 15:00:43 2011 @@ -25,7 +25,6 @@ #include "llvm/Function.h" #include "llvm/Module.h" #include "llvm/ADT/SmallString.h" -#include "llvm/ADT/StringExtras.h" #include "llvm/ADT/Twine.h" #include "llvm/Analysis/DebugInfo.h" #include "llvm/CodeGen/AsmPrinter.h" @@ -139,15 +138,15 @@ const PTXSubtarget& ST = TM.getSubtarget(); // Emit the PTX .version and .target attributes - OutStreamer.EmitRawText(Twine("\t.version " + ST.getPTXVersionString())); - OutStreamer.EmitRawText(Twine("\t.target " + ST.getTargetString() + + OutStreamer.EmitRawText(Twine("\t.version ") + ST.getPTXVersionString()); + OutStreamer.EmitRawText(Twine("\t.target ") + ST.getTargetString() + (ST.supportsDouble() ? "" - : ", map_f64_to_f32"))); + : ", map_f64_to_f32")); // .address_size directive is optional, but it must immediately follow // the .target directive if present within a module if (ST.supportsPTX23()) { - std::string addrSize = ST.is64Bit() ? "64" : "32"; - OutStreamer.EmitRawText(Twine("\t.address_size " + addrSize)); + const char *addrSize = ST.is64Bit() ? "64" : "32"; + OutStreamer.EmitRawText(Twine("\t.address_size ") + addrSize); } OutStreamer.AddBlankLine(); @@ -179,68 +178,47 @@ const PTXParamManager &PM = MFI->getParamManager(); // Print register definitions - std::string regDefs; + SmallString<128> regDefs; + raw_svector_ostream os(regDefs); unsigned numRegs; // pred numRegs = MFI->getNumRegistersForClass(PTX::RegPredRegisterClass); - if(numRegs > 0) { - regDefs += "\t.reg .pred %p<"; - regDefs += utostr(numRegs); - regDefs += ">;\n"; - } + if(numRegs > 0) + os << "\t.reg .pred %p<" << numRegs << ">;\n"; // i16 numRegs = MFI->getNumRegistersForClass(PTX::RegI16RegisterClass); - if(numRegs > 0) { - regDefs += "\t.reg .b16 %rh<"; - regDefs += utostr(numRegs); - regDefs += ">;\n"; - } + if(numRegs > 0) + os << "\t.reg .b16 %rh<" << numRegs << ">;\n"; // i32 numRegs = MFI->getNumRegistersForClass(PTX::RegI32RegisterClass); - if(numRegs > 0) { - regDefs += "\t.reg .b32 %r<"; - regDefs += utostr(numRegs); - regDefs += ">;\n"; - } + if(numRegs > 0) + os << "\t.reg .b32 %r<" << numRegs << ">;\n"; // i64 numRegs = MFI->getNumRegistersForClass(PTX::RegI64RegisterClass); - if(numRegs > 0) { - regDefs += "\t.reg .b64 %rd<"; - regDefs += utostr(numRegs); - regDefs += ">;\n"; - } + if(numRegs > 0) + os << "\t.reg .b64 %rd<" << numRegs << ">;\n"; // f32 numRegs = MFI->getNumRegistersForClass(PTX::RegF32RegisterClass); - if(numRegs > 0) { - regDefs += "\t.reg .f32 %f<"; - regDefs += utostr(numRegs); - regDefs += ">;\n"; - } + if(numRegs > 0) + os << "\t.reg .f32 %f<" << numRegs << ">;\n"; // f64 numRegs = MFI->getNumRegistersForClass(PTX::RegF64RegisterClass); - if(numRegs > 0) { - regDefs += "\t.reg .f64 %fd<"; - regDefs += utostr(numRegs); - regDefs += ">;\n"; - } + if(numRegs > 0) + os << "\t.reg .f64 %fd<" << numRegs << ">;\n"; // Local params for (PTXParamManager::param_iterator i = PM.local_begin(), e = PM.local_end(); - i != e; ++i) { - regDefs += "\t.param .b"; - regDefs += utostr(PM.getParamSize(*i)); - regDefs += " "; - regDefs += PM.getParamName(*i); - regDefs += ";\n"; - } + i != e; ++i) + os << "\t.param .b" << PM.getParamSize(*i) << ' ' << PM.getParamName(*i) + << ";\n"; - OutStreamer.EmitRawText(Twine(regDefs)); + OutStreamer.EmitRawText(os.str()); const MachineFrameInfo* FrameInfo = MF->getFrameInfo(); @@ -249,16 +227,13 @@ for (unsigned i = 0, e = FrameInfo->getNumObjects(); i != e; ++i) { DEBUG(dbgs() << "Size of object: " << FrameInfo->getObjectSize(i) << "\n"); if (FrameInfo->getObjectSize(i) > 0) { - std::string def = "\t.local .align "; - def += utostr(FrameInfo->getObjectAlignment(i)); - def += " .b8"; - def += " __local"; - def += utostr(i); - def += "["; - def += utostr(FrameInfo->getObjectSize(i)); // Convert to bits - def += "]"; - def += ";"; - OutStreamer.EmitRawText(Twine(def)); + OutStreamer.EmitRawText("\t.local .align " + + Twine(FrameInfo->getObjectAlignment(i)) + + " .b8 __local" + + Twine(i) + + "[" + + Twine(FrameInfo->getObjectSize(i)) + + "];"); } } @@ -295,32 +270,27 @@ assert(gvsym->isUndefined() && "Cannot define a symbol twice!"); - std::string decl; + SmallString<128> decl; + raw_svector_ostream os(decl); // check if it is defined in some other translation unit if (gv->isDeclaration()) - decl += ".extern "; + os << ".extern "; // state space: e.g., .global - decl += "."; - decl += getStateSpaceName(gv->getType()->getAddressSpace()); - decl += " "; + os << '.' << getStateSpaceName(gv->getType()->getAddressSpace()) << ' '; // alignment (optional) unsigned alignment = gv->getAlignment(); - if (alignment != 0) { - decl += ".align "; - decl += utostr(gv->getAlignment()); - decl += " "; - } + if (alignment != 0) + os << ".align " << gv->getAlignment() << ' '; if (PointerType::classof(gv->getType())) { PointerType* pointerTy = dyn_cast(gv->getType()); Type* elementTy = pointerTy->getElementType(); - - if (elementTy->isArrayTy()) - { + + if (elementTy->isArrayTy()) { assert(elementTy->isArrayTy() && "Only pointers to arrays are supported"); ArrayType* arrayTy = dyn_cast(elementTy); @@ -329,7 +299,6 @@ unsigned numElements = arrayTy->getNumElements(); while (elementTy->isArrayTy()) { - arrayTy = dyn_cast(elementTy); elementTy = arrayTy->getElementType(); @@ -338,64 +307,46 @@ // FIXME: isPrimitiveType() == false for i16? assert(elementTy->isSingleValueType() && - "Non-primitive types are not handled"); - + "Non-primitive types are not handled"); + // Find the size of the element in bits unsigned elementSize = elementTy->getPrimitiveSizeInBits(); - decl += ".b"; - decl += utostr(elementSize); - decl += " "; - decl += gvsym->getName(); - decl += "["; - decl += utostr(numElements); - decl += "]"; - } - else - { - decl += ".b8 "; - decl += gvsym->getName(); - decl += "[]"; + os << ".b" << elementSize << ' ' << gvsym->getName() + << '[' << numElements << ']'; + } else { + os << ".b8" << gvsym->getName() << "[]"; } // handle string constants (assume ConstantArray means string) - - if (gv->hasInitializer()) - { + if (gv->hasInitializer()) { const Constant *C = gv->getInitializer(); - if (const ConstantArray *CA = dyn_cast(C)) - { - decl += " = {"; - - for (unsigned i = 0, e = C->getNumOperands(); i != e; ++i) - { - if (i > 0) decl += ","; + if (const ConstantArray *CA = dyn_cast(C)) { + os << " = {"; + + for (unsigned i = 0, e = C->getNumOperands(); i != e; ++i) { + if (i > 0) + os << ','; - decl += "0x" + - utohexstr(cast(CA->getOperand(i))->getZExtValue()); + os << "0x"; + os.write_hex(cast(CA->getOperand(i))->getZExtValue()); } - decl += "}"; + os << '}'; } } - } - else { + } else { // Note: this is currently the fall-through case and most likely generates // incorrect code. - decl += getTypeName(gv->getType()); - decl += " "; + os << getTypeName(gv->getType()) << ' ' << gvsym->getName(); - decl += gvsym->getName(); - - if (ArrayType::classof(gv->getType()) || - PointerType::classof(gv->getType())) - decl += "[]"; + if (isa(gv->getType()) || isa(gv->getType())) + os << "[]"; } - decl += ";"; - - OutStreamer.EmitRawText(Twine(decl)); + os << ';'; + OutStreamer.EmitRawText(os.str()); OutStreamer.AddBlankLine(); } @@ -414,43 +365,36 @@ const PTXSubtarget& ST = TM.getSubtarget(); const MachineRegisterInfo& MRI = MF->getRegInfo(); - std::string decl = isKernel ? ".entry" : ".func"; + SmallString<128> decl; + raw_svector_ostream os(decl); + os << (isKernel ? ".entry" : ".func"); if (!isKernel) { - decl += " ("; + os << " ("; if (ST.useParamSpaceForDeviceArgs()) { for (PTXParamManager::param_iterator i = PM.ret_begin(), e = PM.ret_end(), b = i; i != e; ++i) { - if (i != b) { - decl += ", "; - } + if (i != b) + os << ", "; - decl += ".param .b"; - decl += utostr(PM.getParamSize(*i)); - decl += " "; - decl += PM.getParamName(*i); + os << ".param .b" << PM.getParamSize(*i) << ' ' << PM.getParamName(*i); } } else { for (PTXMachineFunctionInfo::reg_iterator i = MFI->retreg_begin(), e = MFI->retreg_end(), b = i; i != e; ++i) { - if (i != b) { - decl += ", "; - } - decl += ".reg ."; - decl += getRegisterTypeName(*i, MRI); - decl += " "; - decl += MFI->getRegisterName(*i); + if (i != b) + os << ", "; + + os << ".reg ." << getRegisterTypeName(*i, MRI) << ' ' + << MFI->getRegisterName(*i); } } - decl += ")"; + os << ')'; } // Print function name - decl += " "; - decl += CurrentFnSym->getName().str(); - - decl += " ("; + os << ' ' << CurrentFnSym->getName() << " ("; const Function *F = MF->getFunction(); @@ -458,64 +402,56 @@ if (isKernel || ST.useParamSpaceForDeviceArgs()) { /*for (PTXParamManager::param_iterator i = PM.arg_begin(), e = PM.arg_end(), b = i; i != e; ++i) { - if (i != b) { - decl += ", "; - } + if (i != b) + os << ", "; - decl += ".param .b"; - decl += utostr(PM.getParamSize(*i)); - decl += " "; - decl += PM.getParamName(*i); + os << ".param .b" << PM.getParamSize(*i) << ' ' << PM.getParamName(*i); }*/ int Counter = 1; for (Function::const_arg_iterator i = F->arg_begin(), e = F->arg_end(), b = i; i != e; ++i) { if (i != b) - decl += ", "; + os << ", "; const Type *ArgType = (*i).getType(); - decl += ".param .b"; + os << ".param .b"; if (ArgType->isPointerTy()) { if (ST.is64Bit()) - decl += "64"; + os << "64"; else - decl += "32"; + os << "32"; } else { - decl += utostr(ArgType->getPrimitiveSizeInBits()); + os << ArgType->getPrimitiveSizeInBits(); } if (ArgType->isPointerTy() && ST.emitPtrAttribute()) { const PointerType *PtrType = dyn_cast(ArgType); - decl += " .ptr"; + os << " .ptr"; switch (PtrType->getAddressSpace()) { default: llvm_unreachable("Unknown address space in argument"); case PTXStateSpace::Global: - decl += " .global"; + os << " .global"; break; case PTXStateSpace::Shared: - decl += " .shared"; + os << " .shared"; break; } } - decl += " __param_"; - decl += utostr(Counter++); + os << " __param_" << Counter++; } } else { for (PTXMachineFunctionInfo::reg_iterator i = MFI->argreg_begin(), e = MFI->argreg_end(), b = i; i != e; ++i) { - if (i != b) { - decl += ", "; - } + if (i != b) + os << ", "; - decl += ".reg ."; - decl += getRegisterTypeName(*i, MRI); - decl += " "; - decl += MFI->getRegisterName(*i); + os << ".reg ." << getRegisterTypeName(*i, MRI) << ' ' + << MFI->getRegisterName(*i); } } - decl += ")"; + os << ')'; - OutStreamer.EmitRawText(Twine(decl)); + OutStreamer.EmitRawText(os.str()); } unsigned PTXAsmPrinter::GetOrCreateSourceID(StringRef FileName, From benny.kra at googlemail.com Mon Nov 7 15:00:59 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 07 Nov 2011 21:00:59 -0000 Subject: [llvm-commits] [llvm] r144013 - in /llvm/trunk: lib/MC/MCDwarf.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp test/CodeGen/ARM/reg_sequence.ll test/CodeGen/ARM/vmov.ll test/MC/ARM/neon-bitwise-encoding.s test/MC/ARM/neon-mov-encoding.s test/MC/ARM/neont2-mov-encoding.s test/MC/Disassembler/ARM/neon-tests.txt test/MC/Disassembler/ARM/neon.txt test/MC/Disassembler/ARM/neont2.txt Message-ID: <20111107210059.AC31C3524001@llvm.org> Author: d0k Date: Mon Nov 7 15:00:59 2011 New Revision: 144013 URL: http://llvm.org/viewvc/llvm-project?rev=144013&view=rev Log: Simplify some uses of utohexstr. As a side effect hex is printed lowercase instead of uppercase now. Modified: llvm/trunk/lib/MC/MCDwarf.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp llvm/trunk/test/CodeGen/ARM/reg_sequence.ll llvm/trunk/test/CodeGen/ARM/vmov.ll llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s llvm/trunk/test/MC/ARM/neon-mov-encoding.s llvm/trunk/test/MC/ARM/neont2-mov-encoding.s llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt llvm/trunk/test/MC/Disassembler/ARM/neon.txt llvm/trunk/test/MC/Disassembler/ARM/neont2.txt Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=144013&r1=144012&r2=144013&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Mon Nov 7 15:00:59 2011 @@ -21,7 +21,6 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/SmallString.h" -#include "llvm/ADT/StringExtras.h" #include "llvm/ADT/Twine.h" using namespace llvm; @@ -738,8 +737,8 @@ // Compact Encoding Size = getSizeForEncoding(Streamer, dwarf::DW_EH_PE_udata4); - if (VerboseAsm) Streamer.AddComment(Twine("Compact Unwind Encoding: 0x") + - Twine(llvm::utohexstr(Encoding))); + if (VerboseAsm) Streamer.AddComment("Compact Unwind Encoding: 0x" + + Twine::utohexstr(Encoding)); Streamer.EmitIntValue(Encoding, Size); Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=144013&r1=144012&r2=144013&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Nov 7 15:00:59 2011 @@ -18,7 +18,6 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" -#include "llvm/ADT/StringExtras.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -967,7 +966,8 @@ unsigned EncodedImm = MI->getOperand(OpNum).getImm(); unsigned EltBits; uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits); - O << "#0x" << utohexstr(Val); + O << "#0x"; + O.write_hex(Val); } void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=144013&r1=144012&r2=144013&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Mon Nov 7 15:00:59 2011 @@ -39,7 +39,6 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/SmallString.h" -#include "llvm/ADT/StringExtras.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" @@ -119,7 +118,7 @@ static void printHex32(unsigned int Value, raw_ostream &O) { O << "0x"; for (int i = 7; i >= 0; i--) - O << utohexstr((Value & (0xF << (i*4))) >> (i*4)); + O.write_hex((Value & (0xF << (i*4))) >> (i*4)); } // Create a bitmask with all callee saved registers for CPU or Floating Point Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=144013&r1=144012&r2=144013&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original) +++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Mon Nov 7 15:00:59 2011 @@ -272,7 +272,7 @@ define arm_aapcs_vfpcc i32 @t10() nounwind { entry: ; CHECK: t10: -; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3F000000 +; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3f000000 ; CHECK: vmul.f32 q8, q8, d0[0] ; CHECK: vadd.f32 q8, q8, q8 %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/vmov.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmov.ll?rev=144013&r1=144012&r2=144013&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmov.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vmov.ll Mon Nov 7 15:00:59 2011 @@ -56,13 +56,13 @@ define <2 x i32> @v_movi32e() nounwind { ;CHECK: v_movi32e: -;CHECK: vmov.i32 d{{.*}}, #0x20FF +;CHECK: vmov.i32 d{{.*}}, #0x20ff ret <2 x i32> < i32 8447, i32 8447 > } define <2 x i32> @v_movi32f() nounwind { ;CHECK: v_movi32f: -;CHECK: vmov.i32 d{{.*}}, #0x20FFFF +;CHECK: vmov.i32 d{{.*}}, #0x20ffff ret <2 x i32> < i32 2162687, i32 2162687 > } @@ -92,19 +92,19 @@ define <2 x i32> @v_mvni32e() nounwind { ;CHECK: v_mvni32e: -;CHECK: vmvn.i32 d{{.*}}, #0x20FF +;CHECK: vmvn.i32 d{{.*}}, #0x20ff ret <2 x i32> < i32 4294958848, i32 4294958848 > } define <2 x i32> @v_mvni32f() nounwind { ;CHECK: v_mvni32f: -;CHECK: vmvn.i32 d{{.*}}, #0x20FFFF +;CHECK: vmvn.i32 d{{.*}}, #0x20ffff ret <2 x i32> < i32 4292804608, i32 4292804608 > } define <1 x i64> @v_movi64() nounwind { ;CHECK: v_movi64: -;CHECK: vmov.i64 d{{.*}}, #0xFF0000FF0000FFFF +;CHECK: vmov.i64 d{{.*}}, #0xff0000ff0000ffff ret <1 x i64> < i64 18374687574888349695 > } @@ -152,19 +152,19 @@ define <4 x i32> @v_movQi32e() nounwind { ;CHECK: v_movQi32e: -;CHECK: vmov.i32 q{{.*}}, #0x20FF +;CHECK: vmov.i32 q{{.*}}, #0x20ff ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 > } define <4 x i32> @v_movQi32f() nounwind { ;CHECK: v_movQi32f: -;CHECK: vmov.i32 q{{.*}}, #0x20FFFF +;CHECK: vmov.i32 q{{.*}}, #0x20ffff ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 > } define <2 x i64> @v_movQi64() nounwind { ;CHECK: v_movQi64: -;CHECK: vmov.i64 q{{.*}}, #0xFF0000FF0000FFFF +;CHECK: vmov.i64 q{{.*}}, #0xff0000ff0000ffff ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > } @@ -182,7 +182,7 @@ define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: ;CHECK: vdupnneg75: -;CHECK: vmov.i8 d{{.*}}, #0xB5 +;CHECK: vmov.i8 d{{.*}}, #0xb5 %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1] store <8 x i8> , <8 x i8>* %0, align 8 ret void Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=144013&r1=144012&r2=144013&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Mon Nov 7 15:00:59 2011 @@ -33,8 +33,8 @@ @ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] @ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] -@ CHECK: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xf3] -@ CHECK: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xf3] +@ CHECK: vbic.i32 d16, #0xff000000 @ encoding: [0x3f,0x07,0xc7,0xf3] +@ CHECK: vbic.i32 q8, #0xff000000 @ encoding: [0x7f,0x07,0xc7,0xf3] vorn d16, d17, d16 vorn q8, q8, q9 Modified: llvm/trunk/test/MC/ARM/neon-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mov-encoding.s?rev=144013&r1=144012&r2=144013&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-mov-encoding.s Mon Nov 7 15:00:59 2011 @@ -18,9 +18,9 @@ @ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] @ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] @ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] -@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] -@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] -@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] +@ CHECK: vmov.i32 d16, #0x20ff @ encoding: [0x10,0x0c,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20ffff @ encoding: [0x10,0x0d,0xc2,0xf2] +@ CHECK: vmov.i64 d16, #0xff0000ff0000ffff @ encoding: [0x33,0x0e,0xc1,0xf3] @@ -42,9 +42,9 @@ @ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] @ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] @ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] -@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] -@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] -@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] +@ CHECK: vmov.i32 q8, #0x20ff @ encoding: [0x50,0x0c,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20ffff @ encoding: [0x50,0x0d,0xc2,0xf2] +@ CHECK: vmov.i64 q8, #0xff0000ff0000ffff @ encoding: [0x73,0x0e,0xc1,0xf3] vmvn.i16 d16, #0x10 vmvn.i16 d16, #0x1000 @@ -61,8 +61,8 @@ @ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] @ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] @ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] -@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] -@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20ff @ encoding: [0x30,0x0c,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20ffff @ encoding: [0x30,0x0d,0xc2,0xf2] vmovl.s8 q8, d16 vmovl.s16 q8, d16 Modified: llvm/trunk/test/MC/ARM/neont2-mov-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mov-encoding.s?rev=144013&r1=144012&r2=144013&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neont2-mov-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neont2-mov-encoding.s Mon Nov 7 15:00:59 2011 @@ -20,9 +20,9 @@ @ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x10,0x02] @ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x10,0x04] @ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x10,0x06] -@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x10,0x0c] -@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x10,0x0d] -@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x33,0x0e] +@ CHECK: vmov.i32 d16, #0x20ff @ encoding: [0xc2,0xef,0x10,0x0c] +@ CHECK: vmov.i32 d16, #0x20ffff @ encoding: [0xc2,0xef,0x10,0x0d] +@ CHECK: vmov.i64 d16, #0xff0000ff0000ffff @ encoding: [0xc1,0xff,0x33,0x0e] vmov.i8 q8, #0x8 @@ -43,9 +43,9 @@ @ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0xc2,0xef,0x50,0x02] @ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0xc2,0xef,0x50,0x04] @ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0xc2,0xef,0x50,0x06] -@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0xc2,0xef,0x50,0x0c] -@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0xc2,0xef,0x50,0x0d] -@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x73,0x0e] +@ CHECK: vmov.i32 q8, #0x20ff @ encoding: [0xc2,0xef,0x50,0x0c] +@ CHECK: vmov.i32 q8, #0x20ffff @ encoding: [0xc2,0xef,0x50,0x0d] +@ CHECK: vmov.i64 q8, #0xff0000ff0000ffff @ encoding: [0xc1,0xff,0x73,0x0e] vmvn.i16 d16, #0x10 @@ -63,8 +63,8 @@ @ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0xc2,0xef,0x30,0x02] @ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0xc2,0xef,0x30,0x04] @ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0xc2,0xef,0x30,0x06] -@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0xc2,0xef,0x30,0x0c] -@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0xc2,0xef,0x30,0x0d] +@ CHECK: vmvn.i32 d16, #0x20ff @ encoding: [0xc2,0xef,0x30,0x0c] +@ CHECK: vmvn.i32 d16, #0x20ffff @ encoding: [0xc2,0xef,0x30,0x0d] vmovl.s8 q8, d16 Modified: llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt?rev=144013&r1=144012&r2=144013&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt Mon Nov 7 15:00:59 2011 @@ -30,7 +30,7 @@ # CHECK: vorr d0, d15, d15 0x1f 0x01 0x2f 0xf2 -# CHECK: vmov.i64 q6, #0xFF00FF00FF +# CHECK: vmov.i64 q6, #0xff00ff00ff 0x75 0xce 0x81 0xf2 # CHECK: vmvn.i32 d0, #0x0 @@ -69,10 +69,10 @@ # CHECK: vpop {d8} 0x02 0x8b 0xbd 0xec -# CHECK: vorr.i32 q15, #0x4F0000 +# CHECK: vorr.i32 q15, #0x4f0000 0x5f 0xe5 0xc4 0xf2 -# CHECK: vbic.i32 q2, #0xA900 +# CHECK: vbic.i32 q2, #0xa900 0x79 0x43 0x82 0xf3 # CHECK: vst2.32 {d16, d18}, [r2, :64], r2 Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=144013&r1=144012&r2=144013&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Mon Nov 7 15:00:59 2011 @@ -307,9 +307,9 @@ 0xf2 0x01 0x50 0xf2 # CHECK: vbic q8, q8, q9 0x3f 0x07 0xc7 0xf3 -# CHECK: vbic.i32 d16, #0xFF000000 +# CHECK: vbic.i32 d16, #0xff000000 0x7f 0x07 0xc7 0xf3 -# CHECK: vbic.i32 q8, #0xFF000000 +# CHECK: vbic.i32 q8, #0xff000000 0xb0 0x01 0x71 0xf2 # CHECK: vorn d16, d17, d16 @@ -587,11 +587,11 @@ 0x10 0x06 0xc2 0xf2 # CHECK: vmov.i32 d16, #0x20000000 0x10 0x0c 0xc2 0xf2 -# CHECK: vmov.i32 d16, #0x20FF +# CHECK: vmov.i32 d16, #0x20ff 0x10 0x0d 0xc2 0xf2 -# CHECK: vmov.i32 d16, #0x20FFFF +# CHECK: vmov.i32 d16, #0x20ffff 0x33 0x0e 0xc1 0xf3 -# CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 d16, #0xff0000ff0000ffff 0x58 0x0e 0xc0 0xf2 # CHECK: vmov.i8 q8, #0x8 0x50 0x08 0xc1 0xf2 @@ -607,11 +607,11 @@ 0x50 0x06 0xc2 0xf2 # CHECK: vmov.i32 q8, #0x20000000 0x50 0x0c 0xc2 0xf2 -# CHECK: vmov.i32 q8, #0x20FF +# CHECK: vmov.i32 q8, #0x20ff 0x50 0x0d 0xc2 0xf2 -# CHECK: vmov.i32 q8, #0x20FFFF +# CHECK: vmov.i32 q8, #0x20ffff 0x73 0x0e 0xc1 0xf3 -# CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 q8, #0xff0000ff0000ffff 0x30 0x08 0xc1 0xf2 # CHECK: vmvn.i16 d16, #0x10 0x30 0x0a 0xc1 0xf2 @@ -625,9 +625,9 @@ 0x30 0x06 0xc2 0xf2 # CHECK: vmvn.i32 d16, #0x20000000 0x30 0x0c 0xc2 0xf2 -# CHECK: vmvn.i32 d16, #0x20FF +# CHECK: vmvn.i32 d16, #0x20ff 0x30 0x0d 0xc2 0xf2 -# CHECK: vmvn.i32 d16, #0x20FFFF +# CHECK: vmvn.i32 d16, #0x20ffff 0x30 0x0a 0xc8 0xf2 # CHECK: vmovl.s8 q8, d16 0x30 0x0a 0xd0 0xf2 Modified: llvm/trunk/test/MC/Disassembler/ARM/neont2.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neont2.txt?rev=144013&r1=144012&r2=144013&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/neont2.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/neont2.txt Mon Nov 7 15:00:59 2011 @@ -301,9 +301,9 @@ 0x50 0xef 0xf2 0x01 # CHECK: vbic q8, q8, q9 0xc7 0xff 0x3f 0x07 -# CHECK: vbic.i32 d16, #0xFF000000 +# CHECK: vbic.i32 d16, #0xff000000 0xc7 0xff 0x7f 0x07 -# CHECK: vbic.i32 q8, #0xFF000000 +# CHECK: vbic.i32 q8, #0xff000000 0x71 0xef 0xb0 0x01 # CHECK: vorn d16, d17, d16 @@ -486,11 +486,11 @@ 0xc2 0xef 0x10 0x06 # CHECK: vmov.i32 d16, #0x20000000 0xc2 0xef 0x10 0x0c -# CHECK: vmov.i32 d16, #0x20FF +# CHECK: vmov.i32 d16, #0x20ff 0xc2 0xef 0x10 0x0d -# CHECK: vmov.i32 d16, #0x20FFFF +# CHECK: vmov.i32 d16, #0x20ffff 0xc1 0xff 0x33 0x0e -# CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 d16, #0xff0000ff0000ffff 0xc0 0xef 0x58 0x0e # CHECK: vmov.i8 q8, #0x8 0xc1 0xef 0x50 0x08 @@ -506,11 +506,11 @@ 0xc2 0xef 0x50 0x06 # CHECK: vmov.i32 q8, #0x20000000 0xc2 0xef 0x50 0x0c -# CHECK: vmov.i32 q8, #0x20FF +# CHECK: vmov.i32 q8, #0x20ff 0xc2 0xef 0x50 0x0d -# CHECK: vmov.i32 q8, #0x20FFFF +# CHECK: vmov.i32 q8, #0x20ffff 0xc1 0xff 0x73 0x0e -# CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF +# CHECK: vmov.i64 q8, #0xff0000ff0000ffff 0xc1 0xef 0x30 0x08 # CHECK: vmvn.i16 d16, #0x10 0xc1 0xef 0x30 0x0a @@ -524,9 +524,9 @@ 0xc2 0xef 0x30 0x06 # CHECK: vmvn.i32 d16, #0x20000000 0xc2 0xef 0x30 0x0c -# CHECK: vmvn.i32 d16, #0x20FF +# CHECK: vmvn.i32 d16, #0x20ff 0xc2 0xef 0x30 0x0d -# CHECK: vmvn.i32 d16, #0x20FFFF +# CHECK: vmvn.i32 d16, #0x20ffff 0xc8 0xef 0x30 0x0a # CHECK: vmovl.s8 q8, d16 0xd0 0xef 0x30 0x0a From stoklund at 2pi.dk Mon Nov 7 15:23:39 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 07 Nov 2011 21:23:39 -0000 Subject: [llvm-commits] [llvm] r144014 - /llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Message-ID: <20111107212339.CCE472A6C12C@llvm.org> Author: stoklund Date: Mon Nov 7 15:23:39 2011 New Revision: 144014 URL: http://llvm.org/viewvc/llvm-project?rev=144014&view=rev Log: Fix pass name after the source was moved. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144014&r1=144013&r2=144014&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Mon Nov 7 15:23:39 2011 @@ -131,7 +131,7 @@ virtual bool runOnMachineFunction(MachineFunction &MF); virtual const char *getPassName() const { - return "SSE execution domain fixup"; + return "Execution dependency fix"; } private: From stoklund at 2pi.dk Mon Nov 7 15:23:42 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 07 Nov 2011 21:23:42 -0000 Subject: [llvm-commits] [llvm] r144015 - /llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Message-ID: <20111107212342.67E3E2A6C12C@llvm.org> Author: stoklund Date: Mon Nov 7 15:23:42 2011 New Revision: 144015 URL: http://llvm.org/viewvc/llvm-project?rev=144015&view=rev Log: MBB doesn't need to be a class member. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144015&r1=144014&r2=144015&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Mon Nov 7 15:23:42 2011 @@ -111,7 +111,6 @@ MachineFunction *MF; const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; - MachineBasicBlock *MBB; std::vector AliasMap; const unsigned NumRegs; DomainValue **LiveRegs; @@ -149,7 +148,7 @@ void Collapse(DomainValue *dv, unsigned domain); bool Merge(DomainValue *A, DomainValue *B); - void enterBasicBlock(); + void enterBasicBlock(MachineBasicBlock*); void visitGenericInstr(MachineInstr*); void visitSoftInstr(MachineInstr*, unsigned mask); void visitHardInstr(MachineInstr*, unsigned domain); @@ -271,7 +270,7 @@ return true; } -void ExeDepsFix::enterBasicBlock() { +void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) { // Try to coalesce live-out registers from predecessors. for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(), e = MBB->livein_end(); i != e; ++i) { @@ -451,7 +450,6 @@ MF = &mf; TII = MF->getTarget().getInstrInfo(); TRI = MF->getTarget().getRegisterInfo(); - MBB = 0; LiveRegs = 0; Distance = 0; assert(NumRegs == RC->getNumRegs() && "Bad regclass"); @@ -482,8 +480,8 @@ for (df_ext_iterator > DFI = df_ext_begin(Entry, Visited), DFE = df_ext_end(Entry, Visited); DFI != DFE; ++DFI) { - MBB = *DFI; - enterBasicBlock(); + MachineBasicBlock *MBB = *DFI; + enterBasicBlock(MBB); for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) { MachineInstr *mi = I; From ahatanaka at mips.com Mon Nov 7 15:32:59 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 07 Nov 2011 21:32:59 -0000 Subject: [llvm-commits] [llvm] r144016 - /llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Message-ID: <20111107213259.3A2972A6C12C@llvm.org> Author: ahatanak Date: Mon Nov 7 15:32:58 2011 New Revision: 144016 URL: http://llvm.org/viewvc/llvm-project?rev=144016&view=rev Log: Add definitions of 64-bit instructions which move data between integer and floating pointer registers. Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=144016&r1=144015&r2=144016&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Mon Nov 7 15:32:58 2011 @@ -183,6 +183,14 @@ "mtc1\t$rt, $fs", [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>; +def DMFC1 : FFRGPR<0x01, (outs CPU64Regs:$rt), (ins FGR64:$fs), + "dmfc1\t$rt, $fs", + [(set CPU64Regs:$rt, (bitconvert FGR64:$fs))]>; + +def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt), + "dmtc1\t$rt, $fs", + [(set FGR64:$fs, (bitconvert CPU64Regs:$rt))]>; + def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>; def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>, Requires<[NotFP64bit]>; From ahatanaka at mips.com Mon Nov 7 15:35:46 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 07 Nov 2011 21:35:46 -0000 Subject: [llvm-commits] [llvm] r144017 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Message-ID: <20111107213546.1ADED2A6C12C@llvm.org> Author: ahatanak Date: Mon Nov 7 15:35:45 2011 New Revision: 144017 URL: http://llvm.org/viewvc/llvm-project?rev=144017&view=rev Log: Add code needed for copying between 64-bit integer and floating pointer registers. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=144017&r1=144016&r2=144017&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Nov 7 15:35:45 2011 @@ -131,6 +131,8 @@ Opc = Mips::FMOV_S; else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) Opc = Mips::FMOV_D32; + else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) + Opc = Mips::FMOV_D64; else if (Mips::CCRRegClass.contains(DestReg, SrcReg)) Opc = Mips::MOVCCRToCCR; else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg. @@ -140,12 +142,16 @@ Opc = Mips::MFHI64, SrcReg = 0; else if (SrcReg == Mips::LO64) Opc = Mips::MFLO64, SrcReg = 0; + else if (Mips::FGR64RegClass.contains(SrcReg)) + Opc = Mips::DMFC1; } else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg. if (DestReg == Mips::HI64) Opc = Mips::MTHI64, DestReg = 0; else if (DestReg == Mips::LO64) Opc = Mips::MTLO64, DestReg = 0; + else if (Mips::FGR64RegClass.contains(DestReg)) + Opc = Mips::DMTC1; } assert(Opc && "Cannot copy registers"); From ahatanaka at mips.com Mon Nov 7 15:37:33 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 07 Nov 2011 21:37:33 -0000 Subject: [llvm-commits] [llvm] r144018 - /llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Message-ID: <20111107213733.CED022A6C12C@llvm.org> Author: ahatanak Date: Mon Nov 7 15:37:33 2011 New Revision: 144018 URL: http://llvm.org/viewvc/llvm-project?rev=144018&view=rev Log: Add definition of the base class for floating point comparison instructions and add Mips64's version too. Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=144018&r1=144017&r2=144018&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Mon Nov 7 15:37:33 2011 @@ -267,16 +267,16 @@ def MIPS_FCOND_LE : PatLeaf<(i32 14)>; def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; +class FCMP fmt, RegisterClass RC, string typestr> : + FCC; + /// Floating Point Compare let Defs=[FCR31] in { - def FCMP_S32 : FCC<0x10, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc), - "c.$cc.s\t$fs, $ft", - [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>; - - def FCMP_D32 : FCC<0x11, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc), - "c.$cc.d\t$fs, $ft", - [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>, - Requires<[NotFP64bit]>; + def FCMP_S32 : FCMP<0x10, FGR32, "s">; + def FCMP_D32 : FCMP<0x11, AFGR64, "d">, Requires<[NotFP64bit]>; + def FCMP_D64 : FCMP<0x11, FGR64, "d">, Requires<[IsFP64bit]>; } //===----------------------------------------------------------------------===// From ahatanaka at mips.com Mon Nov 7 15:38:58 2011 From: ahatanaka at mips.com (Akira Hatanaka) Date: Mon, 07 Nov 2011 21:38:58 -0000 Subject: [llvm-commits] [llvm] r144019 - /llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Message-ID: <20111107213858.BBE6D2A6C12C@llvm.org> Author: ahatanak Date: Mon Nov 7 15:38:58 2011 New Revision: 144019 URL: http://llvm.org/viewvc/llvm-project?rev=144019&view=rev Log: Various Mips64 floating point instruction patterns. Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=144019&r1=144018&r2=144019&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Mon Nov 7 15:38:58 2011 @@ -317,13 +317,28 @@ def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>; -def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>; - def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>; -def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>; let Predicates = [NotFP64bit] in { + def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>; + def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>; def : Pat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>; def : Pat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>; } +let Predicates = [IsFP64bit] in { + def : Pat<(f64 fpimm0), (DMTC1 ZERO_64)>; + def : Pat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; + + def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D64_W (MTC1 CPURegs:$src))>; + def : Pat<(f32 (sint_to_fp CPU64Regs:$src)), + (CVT_S_L (DMTC1 CPU64Regs:$src))>; + def : Pat<(f64 (sint_to_fp CPU64Regs:$src)), + (CVT_D64_L (DMTC1 CPU64Regs:$src))>; + + def : Pat<(i32 (fp_to_sint FGR64:$src)), (MFC1 (TRUNC_W_D64 FGR64:$src))>; + def : Pat<(i64 (fp_to_sint FGR64:$src)), (DMFC1 (TRUNC_L_D64 FGR64:$src))>; + + def : Pat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>; + def : Pat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>; +} \ No newline at end of file From stoklund at 2pi.dk Mon Nov 7 15:40:27 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 07 Nov 2011 21:40:27 -0000 Subject: [llvm-commits] [llvm] r144020 - /llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Message-ID: <20111107214027.45AF42A6C12C@llvm.org> Author: stoklund Date: Mon Nov 7 15:40:27 2011 New Revision: 144020 URL: http://llvm.org/viewvc/llvm-project?rev=144020&view=rev Log: Extract two methods. No functional change. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144020&r1=144019&r2=144020&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Mon Nov 7 15:40:27 2011 @@ -149,6 +149,8 @@ bool Merge(DomainValue *A, DomainValue *B); void enterBasicBlock(MachineBasicBlock*); + void leaveBasicBlock(MachineBasicBlock*); + void visitInstr(MachineInstr*); void visitGenericInstr(MachineInstr*); void visitSoftInstr(MachineInstr*, unsigned mask); void visitHardInstr(MachineInstr*, unsigned domain); @@ -305,6 +307,27 @@ } } +void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) { + // Save live registers at end of MBB - used by enterBasicBlock(). + if (LiveRegs) + LiveOuts.insert(std::make_pair(MBB, LiveRegs)); + LiveRegs = 0; +} + +void ExeDepsFix::visitInstr(MachineInstr *MI) { + if (MI->isDebugValue()) + return; + ++Distance; + std::pair domp = TII->getExecutionDomain(MI); + if (domp.first) + if (domp.second) + visitSoftInstr(MI, domp.second); + else + visitHardInstr(MI, domp.first); + else if (LiveRegs) + visitGenericInstr(MI); +} + // A hard instruction only works in one domain. All input registers will be // forced into that domain. void ExeDepsFix::visitHardInstr(MachineInstr *mi, unsigned domain) { @@ -483,24 +506,9 @@ MachineBasicBlock *MBB = *DFI; enterBasicBlock(MBB); for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; - ++I) { - MachineInstr *mi = I; - if (mi->isDebugValue()) continue; - ++Distance; - std::pair domp = TII->getExecutionDomain(mi); - if (domp.first) - if (domp.second) - visitSoftInstr(mi, domp.second); - else - visitHardInstr(mi, domp.first); - else if (LiveRegs) - visitGenericInstr(mi); - } - - // Save live registers at end of MBB - used by enterBasicBlock(). - if (LiveRegs) - LiveOuts.insert(std::make_pair(MBB, LiveRegs)); - LiveRegs = 0; + ++I) + visitInstr(I); + leaveBasicBlock(MBB); } // Clear the LiveOuts vectors. Should we also collapse any remaining From mcrosier at apple.com Mon Nov 7 15:43:40 2011 From: mcrosier at apple.com (Chad Rosier) Date: Mon, 07 Nov 2011 21:43:40 -0000 Subject: [llvm-commits] [llvm] r144021 - /llvm/trunk/lib/Target/ARM/ARMCallingConv.td Message-ID: <20111107214340.DB2A52A6C12C@llvm.org> Author: mcrosier Date: Mon Nov 7 15:43:40 2011 New Revision: 144021 URL: http://llvm.org/viewvc/llvm-project?rev=144021&view=rev Log: Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well. Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.td Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallingConv.td?rev=144021&r1=144020&r2=144021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCallingConv.td (original) +++ llvm/trunk/lib/Target/ARM/ARMCallingConv.td Mon Nov 7 15:43:40 2011 @@ -89,7 +89,7 @@ def CC_ARM_AAPCS_Common : CallingConv<[ - CCIfType<[i8, i16], CCPromoteToType>, + CCIfType<[i1, i8, i16], CCPromoteToType>, // i64/f64 is passed in even pairs of GPRs // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register From eli.friedman at gmail.com Mon Nov 7 15:46:51 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 7 Nov 2011 13:46:51 -0800 Subject: [llvm-commits] AVX1 Code Generation - VSHUFP extension In-Reply-To: <7CB6AC5AED596245A99BF3213DE8F4AA02FFEA3063@hasmsx504.ger.corp.intel.com> References: <7CB6AC5AED596245A99BF3213DE8F4AA02FFEA3063@hasmsx504.ger.corp.intel.com> Message-ID: On Mon, Nov 7, 2011 at 12:08 AM, Demikhovsky, Elena wrote: > Hello, > > I added several lines in X86 code generator that allow to choose VSHUFPS/VSHUFPD > instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask. > > I extended the existing lit test. > > Please review. +static bool isCommutedVSHUFPSY(SmallVectorImpl &Mask, EVT VT, + const X86Subtarget *Subtarget) { + + if ((VT.getSizeInBits() != 256) || (VT.getVectorNumElements() != 8)) + return false; + + CommuteVectorShuffleMask(Mask, VT); + return isVSHUFPSYMask(Mask, VT, Subtarget); +} It looks like this mutates the input Mask; I don't think you really want to do that. + // Try to swap operands in the node to match x86 shuffle ops + if (!V2IsUndef && isCommutedVSHUFPSY(M, VT, Subtarget)) { + // Now we need to commute operands. + SVOp = cast(CommuteVectorShuffle(SVOp, DAG)); This isn't consistent with the way other code in this function uses CommuteVectorShuffle. -Eli From gkistanova at gmail.com Mon Nov 7 15:46:58 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 07 Nov 2011 21:46:58 -0000 Subject: [llvm-commits] [zorg] r144022 - /zorg/trunk/buildbot/osuosl/master/master.cfg Message-ID: <20111107214658.62FF92A6C12C@llvm.org> Author: gkistanova Date: Mon Nov 7 15:46:58 2011 New Revision: 144022 URL: http://llvm.org/viewvc/llvm-project?rev=144022&view=rev Log: Add project-specific schedulers. Modified: zorg/trunk/buildbot/osuosl/master/master.cfg Modified: zorg/trunk/buildbot/osuosl/master/master.cfg URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/master.cfg?rev=144022&r1=144021&r2=144022&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/master.cfg (original) +++ zorg/trunk/buildbot/osuosl/master/master.cfg Mon Nov 7 15:46:58 2011 @@ -31,39 +31,21 @@ ####### CHANGESOURCES -from buildbot.changes.svnpoller import SVNPoller from buildbot.changes.pb import PBChangeSource +from zorg.buildbot.changes.llvmpoller import LLVMPoller -import buildbot.changes.svnpoller - -class LLVMPoller(buildbot.changes.svnpoller.SVNPoller): - def __init__(self, project, pollinterval=120, histmax=10): - buildbot.changes.svnpoller.SVNPoller.__init__(self, - 'http://llvm.org/svn/llvm-project/%s' % project, - pollinterval=pollinterval, - histmax=histmax, - revlinktmpl='http://llvm.org/viewvc/llvm-project/?view=rev&revision=%s') c['change_source'] = [PBChangeSource()] -if True: - c['change_source'].append(LLVMPoller("llvm/trunk")) - c['change_source'].append(LLVMPoller("cfe/trunk")) - c['change_source'].append(LLVMPoller("polly/trunk")) - c['change_source'].append(LLVMPoller("llvm-gcc-4.2/trunk")) - c['change_source'].append(LLVMPoller("compiler-rt/trunk")) - c['change_source'].append(LLVMPoller("dragonegg/trunk")) - c['change_source'].append(LLVMPoller("lldb/trunk")) -# c['change_source'].append(LLVMPoller("test-suite/trunk")) - -####### BUILDERS -c['builders'] = builders = list(config.builders.get_builders()) +c['change_source'].append(LLVMPoller(projects=[ + "llvm", + "cfe", + "polly", + "llvm-gcc-4.2", + "compiler-rt", + "dragonegg", + "lldb"])) -####### STATUS TARGETS - -# Schedule builds and email for all non-experimental builders. -standard_builders = [b['name'] for b in builders - if not b['category'].endswith('.exp')] -c['status'] = config.status.get_status_targets(standard_builders) +# c['change_source'].append(LLVMPoller("test-suite", "trunk")) ####### RESOURCE USAGE @@ -82,12 +64,77 @@ # Use gzip instead of bz2, to reduce server load. c['logCompressionMethod'] = 'gz' +####### BUILDERS + +c['builders'] = builders = list(config.builders.get_builders()) + +####### STATUS TARGETS + +# Schedule builds and email for all non-experimental builders. +standard_builders = [b['name'] for b in builders + if not b['category'].endswith('.exp')] +c['status'] = config.status.get_status_targets(standard_builders) + ####### SCHEDULERS from buildbot.scheduler import Scheduler -c['schedulers'] = [Scheduler(name="all",branch=None, - treeStableTimer=2*60, - builderNames=standard_builders)] +from buildbot.schedulers.filter import ChangeFilter +from buildbot.schedulers.basic import SingleBranchScheduler + +def depends_on(projects): + """ + Returns a ChangeFilter for the given projects. + """ + return ChangeFilter(project=projects) + +def get_all_for(category): + """ + Returns a list of builder names for the given category. + """ + return [ + b['name'] for b in builders + if b['category'] == category] + + +c['schedulers'] = [SingleBranchScheduler(name="llvm_scheduler", + treeStableTimer=2*60, + builderNames=get_all_for("llvm"), + change_filter=depends_on( + "llvm"))] + +c['schedulers'].append(SingleBranchScheduler(name="llvmgcc_scheduler", + treeStableTimer=2*60, + builderNames=get_all_for("llvm-gcc"), + change_filter=depends_on([ + "llvm", + "llvm-gcc-4.2"]))) + +c['schedulers'].append(SingleBranchScheduler(name="dragonegg_scheduler", + treeStableTimer=2*60, + builderNames=get_all_for("dragonegg"), + change_filter=depends_on([ + "llvm", + "dragonegg"]))) + +c['schedulers'].append(SingleBranchScheduler(name="clang_scheduler", + treeStableTimer=2*60, + builderNames=get_all_for("clang"), + change_filter=depends_on([ + "llvm", + "cfe"]))) + +c['schedulers'].append(SingleBranchScheduler(name="polly_scheduler", + treeStableTimer=2*60, + builderNames=get_all_for("polly"), + change_filter=depends_on([ + "llvm", + "polly"]))) + +c['schedulers'].append(SingleBranchScheduler(name="lldb_scheduler", + treeStableTimer=2*60, + builderNames=get_all_for("lldb"), + change_filter=depends_on( + "lldb"))) ####### PROJECT IDENTITY From echristo at apple.com Mon Nov 7 15:49:28 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 21:49:28 -0000 Subject: [llvm-commits] [llvm] r144023 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfAccelTable.cpp DwarfAccelTable.h Message-ID: <20111107214928.452682A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 15:49:28 2011 New Revision: 144023 URL: http://llvm.org/viewvc/llvm-project?rev=144023&view=rev Log: Simple destructor to delete the hash data we created earlier. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp?rev=144023&r1=144022&r2=144023&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Mon Nov 7 15:49:28 2011 @@ -42,6 +42,11 @@ HeaderData(atom) { } +DwarfAccelTable::~DwarfAccelTable() { + for (size_t i = 0 ; i < Data.size(); ++i) + delete Data[i]; +} + void DwarfAccelTable::AddName(StringRef Name, DIE* die) { // If the string is in the list already then add this die to the list // otherwise add a new one. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h?rev=144023&r1=144022&r2=144023&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Mon Nov 7 15:49:28 2011 @@ -239,6 +239,7 @@ // Public Implementation public: DwarfAccelTable(DwarfAccelTable::Atom Atom); + ~DwarfAccelTable(); void AddName(StringRef, DIE*); void FinalizeTable(AsmPrinter *, const char *); void Emit(AsmPrinter *, MCSymbol *, DwarfDebug *); From echristo at apple.com Mon Nov 7 15:49:36 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 21:49:36 -0000 Subject: [llvm-commits] [llvm] r144024 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Message-ID: <20111107214936.0FC0C2A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 15:49:35 2011 New Revision: 144024 URL: http://llvm.org/viewvc/llvm-project?rev=144024&view=rev Log: Move the hash function to using and taking a StringRef. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h?rev=144024&r1=144023&r2=144024&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Mon Nov 7 15:49:35 2011 @@ -69,10 +69,10 @@ eHashFunctionDJB = 0u }; - static uint32_t HashDJB (const char *s) { + static uint32_t HashDJB (StringRef Str) { uint32_t h = 5381; - for (unsigned char c = *s; c; c = *++s) - h = ((h << 5) + h) + c; + for (unsigned i = 0, e = Str.size(); i != e; ++i) + h = ((h << 5) + h) + Str[i]; return h; } @@ -190,7 +190,7 @@ MCSymbol *Sym; std::vector DIEOffsets; // offsets HashData(StringRef S) : Str(S) { - HashValue = DwarfAccelTable::HashDJB(S.str().c_str()); + HashValue = DwarfAccelTable::HashDJB(S); } void addOffset(uint32_t off) { DIEOffsets.push_back(off); } #ifndef NDEBUG From echristo at apple.com Mon Nov 7 15:56:47 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 13:56:47 -0800 Subject: [llvm-commits] [llvm] r143921 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfAccelTable.cpp DwarfAccelTable.h In-Reply-To: References: <20111107091842.4FB7E3524001@llvm.org> Message-ID: On Nov 7, 2011, at 7:36 AM, Benjamin Kramer wrote: > Test cases would be nice but I can see that we're lacking infrastructure to test it properly. Think I've got all of the bits you mentioned, thanks for the review. And yes, I have some ideas for test cases, I may put off adding them until I get llvm-dwarfdump handling it, or I may add some that FileCheck asm output. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111107/6372da5f/attachment.html From stoklund at 2pi.dk Mon Nov 7 15:59:29 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 07 Nov 2011 21:59:29 -0000 Subject: [llvm-commits] [llvm] r144025 - /llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Message-ID: <20111107215929.D3D262A6C12C@llvm.org> Author: stoklund Date: Mon Nov 7 15:59:29 2011 New Revision: 144025 URL: http://llvm.org/viewvc/llvm-project?rev=144025&view=rev Log: Use a reverse post order instead of a DFS order. The enterBasicBlock() function is combining live-out values from predecessor blocks. The RPO traversal means that more predecessors have been visited when that happens, only back-edges are missing. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144025&r1=144024&r2=144025&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Mon Nov 7 15:59:29 2011 @@ -26,7 +26,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/PostOrderIterator.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" @@ -499,11 +499,10 @@ } MachineBasicBlock *Entry = MF->begin(); - SmallPtrSet Visited; - for (df_ext_iterator > - DFI = df_ext_begin(Entry, Visited), DFE = df_ext_end(Entry, Visited); - DFI != DFE; ++DFI) { - MachineBasicBlock *MBB = *DFI; + ReversePostOrderTraversal RPOT(Entry); + for (ReversePostOrderTraversal::rpo_iterator + MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) { + MachineBasicBlock *MBB = *MBBI; enterBasicBlock(MBB); for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) From isanbard at gmail.com Mon Nov 7 16:05:17 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 07 Nov 2011 22:05:17 -0000 Subject: [llvm-commits] [llvm] r144026 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20111107220517.B99CD2A6C12C@llvm.org> Author: void Date: Mon Nov 7 16:05:17 2011 New Revision: 144026 URL: http://llvm.org/viewvc/llvm-project?rev=144026&view=rev Log: Add ISPC to the external projects list. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=144026&r1=144025&r2=144026&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Mon Nov 7 16:05:17 2011 @@ -403,6 +403,22 @@ +

ispc: The Intel SPMD Program Compiler

+ +
+ +

ispc is a compiler for "single program, + multiple data" (SPMD) programs. It compiles a C-based SPMD programming + language to run on the SIMD units of CPUs; it often delivers 5-6x speedups on + a single core of a CPU with an 8-wide SIMD unit compared to serial code, + while still providing a clean and easy-to-understand programming model. For + an introduction to the language and its performance, + see the walkthrough of a short + example program. ispc is licensed under the BSD license.

+ +
+ +

LanguageKit and Pragmatic Smalltalk

From echristo at apple.com Mon Nov 7 16:11:16 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 07 Nov 2011 22:11:16 -0000 Subject: [llvm-commits] [llvm] r144027 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfCompileUnit.cpp DwarfDebug.cpp Message-ID: <20111107221116.CA63F2A6C12C@llvm.org> Author: echristo Date: Mon Nov 7 16:11:16 2011 New Revision: 144027 URL: http://llvm.org/viewvc/llvm-project?rev=144027&view=rev Log: Add all completed and named types to the dwarf type accelerator tables. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=144027&r1=144026&r2=144027&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Mon Nov 7 16:11:16 2011 @@ -634,6 +634,12 @@ // If this is a complete composite type then include it in the // list of global types. addGlobalType(Ty); + + // If this is a named finished type then include it in the list of types + // for the accelerator tables. + if (!Ty.getName().empty() && !Ty.isForwardDecl()) + if (DIEEntry *Entry = getDIEEntry(Ty)) + AccelTypes[Ty.getName()] = Entry->getEntry(); } /// addGlobalType - Add a new global type to the compile unit. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=144027&r1=144026&r2=144027&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Nov 7 16:11:16 2011 @@ -1834,8 +1834,7 @@ for (DenseMap::iterator I = CUMap.begin(), E = CUMap.end(); I != E; ++I) { CompileUnit *TheCU = I->second; - const StringMap &Names = TheCU->getGlobalTypes(); - //TODO: TheCU->getAccelTypes(); + const StringMap &Names = TheCU->getAccelTypes(); for (StringMap::const_iterator GI = Names.begin(), GE = Names.end(); GI != GE; ++GI) { const char *Name = GI->getKeyData(); From dmalyshev at accesssoftek.com Mon Nov 7 16:40:51 2011 From: dmalyshev at accesssoftek.com (Danil Malyshev) Date: Mon, 7 Nov 2011 14:40:51 -0800 Subject: [llvm-commits] MachOObjectFile fix functions In-Reply-To: References: <6AE1604EE3EC5F4296C096518C6B77EE1805B07349@mail.accesssoftek.com> Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE1805C8FA97@mail.accesssoftek.com> Hello Owen, Please find attached the changed patch which addresses the following 2 things: 1. Functions in ELFObjectFile, MachOObjectFile and COFFObjectFile should returns same result. 2. We don't need have several functions with similar functionality which can be obtained by other means. getSymbolAddress - removed. getRelocationAddress - removed. getSymbolOffset - returns the offset from the beginning of the section. If we need the virtual address we can use something like symbol.getOffset() + symbol.getSection().getAddress() If we need the offset from the beginning of the object file, we can use something like symbol.getOffset() + symbol.getSection().getSectionContents().begin() - object->getData().begin() If we need the pointer to the first byte of symbol we can use something like getOffset() + getSection().getSectionContents().begin() getRelocationOffset - returns the offset from the beginning of the section. If we need the virtual address we can use somethings like reloc.getOffset() + reloc.getSection().getAddress() If we need the offset from the beginning of the object file, we can use something like reloc.getOffset() + reloc.getSection().getSectionContents().begin() - object->getData().begin() If we need the pointer to the first byte of relocation address we can use something like reloc.getOffset() + reloc.getSection().getSectionContents().begin() Regards, Danil ________________________________ From: Owen Anderson [mailto:resistor at mac.com] Sent: Friday, November 04, 2011 12:49 PM To: Danil Malyshev Cc: 'llvm-commits at cs.uiuc.edu' Subject: Re: [llvm-commits] MachOObjectFile fix functions Danil, These changes are not correct. I've spent a lot of time over the last few weeks getting these right by comparing them with existing MachO tools. While it's quite possible there are still bugs, I'm fairly confident of them in general. Specific incorrectness are noted below: - getSymbolOffset The Value field of a MachO symbol table entry is a virtual address, not a file offset. AFAIK, the best way to find the file offset for the symbol is to get the subtract the section virtual address from the symbol virtual address, and add that to section offset. - getSymbolAddress Your implementation of this seems to be based on an incorrect understanding of what this method is supposed to return. It is supposed to return the virtual address of the symbol, i.e. the address where the symbol will reside when the dynamic linker maps this object. Instead, you're returning a pointer in the current process's address space, based on where the object file happens to be memory mapped at the moment. If the ELF implementation does this, it is simply wrong. - getRelocationAddress This change is simply wrong. The value field on MachO relocations holds an offset from the beginning of the section, not a virtual address. You have to add that the the current section's virtual address to obtain the correct value, as the existing code currently does. --Owen On Nov 03, 2011, at 02:54 PM, Danil Malyshev wrote: Hello everyone, Please find attached the patch for review. The patch changed several MachOObjectFile functions: - Fix getSymbolOffset(), getSymbolAddress() and getRelocationAddress(), now it's works same as in ELFObjectFile. - Add implementation getSymbolSize() Regards, Danil _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111107/21bead27/attachment-0001.html -------------- next part -------------- A non-text attachment was scrubbed... Name: ObjectFile_fix_functions-01.patch Type: application/octet-stream Size: 17755 bytes Desc: ObjectFile_fix_functions-01.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111107/21bead27/attachment-0001.obj From eli.friedman at gmail.com Mon Nov 7 16:51:10 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 07 Nov 2011 22:51:10 -0000 Subject: [llvm-commits] [llvm] r144034 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll Message-ID: <20111107225110.47D172A6C12C@llvm.org> Author: efriedma Date: Mon Nov 7 16:51:10 2011 New Revision: 144034 URL: http://llvm.org/viewvc/llvm-project?rev=144034&view=rev Log: Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization doesn't get confused by CSE later on. Fixes PR11318. Added: llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=144034&r1=144033&r2=144034&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 7 16:51:10 2011 @@ -285,6 +285,7 @@ Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), ST->isVolatile(), ST->isNonTemporal(), Alignment); DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); + DAG.RemoveDeadNode(ST, DUL); return; } // Do a (aligned) store to a stack slot, then copy from the stack slot @@ -349,6 +350,7 @@ DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], Stores.size()); DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); + DAG.RemoveDeadNode(ST, DUL); return; } assert(ST->getMemoryVT().isInteger() && @@ -381,6 +383,7 @@ SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); + DAG.RemoveDeadNode(ST, DUL); } /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. @@ -1144,6 +1147,7 @@ if (!ST->isTruncatingStore()) { if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { DAG.ReplaceAllUsesWith(ST, OptStore, this); + DAG.RemoveDeadNode(ST, this); break; } @@ -1169,8 +1173,10 @@ break; case TargetLowering::Custom: Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG); - if (Tmp1.getNode()) + if (Tmp1.getNode()) { DAG.ReplaceAllUsesWith(SDValue(Node, 0), Tmp1, this); + DAG.RemoveDeadNode(Node, this); + } break; case TargetLowering::Promote: { assert(VT.isVector() && "Unknown legal promote case!"); @@ -1181,6 +1187,7 @@ ST->getPointerInfo(), isVolatile, isNonTemporal, Alignment); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); + DAG.RemoveDeadNode(Node, this); break; } } @@ -1203,6 +1210,7 @@ DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), NVT, isVolatile, isNonTemporal, Alignment); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); + DAG.RemoveDeadNode(Node, this); } else if (StWidth & (StWidth - 1)) { // If not storing a power-of-2 number of bits, expand as two stores. assert(!StVT.isVector() && "Unsupported truncstore!"); @@ -1258,6 +1266,7 @@ // The order of the stores doesn't matter. SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); + DAG.RemoveDeadNode(Node, this); } else { if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || Tmp2 != ST->getBasePtr()) @@ -1280,6 +1289,7 @@ DAG.ReplaceAllUsesWith(SDValue(Node, 0), TLI.LowerOperation(SDValue(Node, 0), DAG), this); + DAG.RemoveDeadNode(Node, this); break; case TargetLowering::Expand: assert(!StVT.isVector() && @@ -1292,6 +1302,7 @@ DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), isVolatile, isNonTemporal, Alignment); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); + DAG.RemoveDeadNode(Node, this); break; } } @@ -3361,6 +3372,7 @@ DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), &Scalars[0], Scalars.size()); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); + DAG.RemoveDeadNode(Node, this); break; } case ISD::GLOBAL_OFFSET_TABLE: @@ -3377,8 +3389,10 @@ } // Replace the original node with the legalized result. - if (!Results.empty()) + if (!Results.empty()) { DAG.ReplaceAllUsesWith(Node, Results.data(), this); + DAG.RemoveDeadNode(Node, this); + } } void SelectionDAGLegalize::PromoteNode(SDNode *Node) { @@ -3512,8 +3526,10 @@ } // Replace the original node with the legalized result. - if (!Results.empty()) + if (!Results.empty()) { DAG.ReplaceAllUsesWith(Node, Results.data(), this); + DAG.RemoveDeadNode(Node, this); + } } // SelectionDAG::Legalize - This is the entry point for the file. Added: llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll?rev=144034&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll Mon Nov 7 16:51:10 2011 @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s + +; We don't really care what this outputs; just make sure it's somewhat sane. +; CHECK: legalize_test +; CHECK: vmovups +define void @legalize_test(i32 %x, <8 x i32>* %p) nounwind { +entry: + %t1 = insertelement <8 x i32> , i32 %x, i32 0 + %t2 = shufflevector <8 x i32> %t1, <8 x i32> zeroinitializer, <8 x i32> + %int2float = sitofp <8 x i32> %t2 to <8 x float> + %blendAsInt.i821 = bitcast <8 x float> %int2float to <8 x i32> + store <8 x i32> %blendAsInt.i821, <8 x i32>* %p, align 4 + ret void +} From peter_cooper at apple.com Mon Nov 7 17:04:49 2011 From: peter_cooper at apple.com (Pete Cooper) Date: Mon, 07 Nov 2011 23:04:49 -0000 Subject: [llvm-commits] [llvm] r144036 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/CodeGen/X86/vec_udiv_to_shift.ll Message-ID: <20111107230449.7509D2A6C12C@llvm.org> Author: pete Date: Mon Nov 7 17:04:49 2011 New Revision: 144036 URL: http://llvm.org/viewvc/llvm-project?rev=144036&view=rev Log: InstCombine now optimizes vector udiv by power of 2 to shifts Fixes r8429 Added: llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=144036&r1=144035&r2=144036&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Mon Nov 7 17:04:49 2011 @@ -441,19 +441,23 @@ // Handle the integer div common cases if (Instruction *Common = commonIDivTransforms(I)) return Common; - - if (ConstantInt *C = dyn_cast(Op1)) { + + { // X udiv 2^C -> X >> C // Check to see if this is an unsigned division with an exact power of 2, // if so, convert to a right shift. - if (C->getValue().isPowerOf2()) { // 0 not included in isPowerOf2 + const APInt *C; + if (match(Op1, m_Power2(C))) { BinaryOperator *LShr = - BinaryOperator::CreateLShr(Op0, - ConstantInt::get(Op0->getType(), C->getValue().logBase2())); + BinaryOperator::CreateLShr(Op0, + ConstantInt::get(Op0->getType(), + C->logBase2())); if (I.isExact()) LShr->setIsExact(); return LShr; } + } + if (ConstantInt *C = dyn_cast(Op1)) { // X udiv C, where C >= signbit if (C->getValue().isNegative()) { Value *IC = Builder->CreateICmpULT(Op0, C); Added: llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll?rev=144036&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll (added) +++ llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll Mon Nov 7 17:04:49 2011 @@ -0,0 +1,15 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +define <8 x i16> @udiv_vec8x16(<8 x i16> %var) { +entry: +; CHECK: lshr <8 x i16> %var, +%0 = udiv <8 x i16> %var, +ret <8 x i16> %0 +} + +define <4 x i32> @udiv_vec4x32(<4 x i32> %var) { +entry: +; CHECK: lshr <4 x i32> %var, +%0 = udiv <4 x i32> %var, +ret <4 x i32> %0 +} \ No newline at end of file From stoklund at 2pi.dk Mon Nov 7 17:08:22 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 07 Nov 2011 23:08:22 -0000 Subject: [llvm-commits] [llvm] r144037 - in /llvm/trunk: lib/CodeGen/ExecutionDepsFix.cpp test/CodeGen/X86/avx-intrinsics-x86.ll test/CodeGen/X86/avx-logic.ll test/CodeGen/X86/nontemporal.ll test/CodeGen/X86/sse-align-3.ll test/CodeGen/X86/sse2-blend.ll test/CodeGen/X86/sse2.ll test/CodeGen/X86/vec_shuffle.ll Message-ID: <20111107230822.33E5F3524001@llvm.org> Author: stoklund Date: Mon Nov 7 17:08:21 2011 New Revision: 144037 URL: http://llvm.org/viewvc/llvm-project?rev=144037&view=rev Log: Kill and collapse outstanding DomainValues. DomainValues that are only used by "don't care" instructions are now collapsed to the first possible execution domain after all basic blocks have been processed. This typically means the PS domain on x86. For example, the vsel_i64 and vsel_double functions in sse2-blend.ll are completely collapsed to the PS domain instead of containing a mix of execution domains created by isel. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll llvm/trunk/test/CodeGen/X86/avx-logic.ll llvm/trunk/test/CodeGen/X86/nontemporal.ll llvm/trunk/test/CodeGen/X86/sse-align-3.ll llvm/trunk/test/CodeGen/X86/sse2-blend.ll llvm/trunk/test/CodeGen/X86/sse2.ll llvm/trunk/test/CodeGen/X86/vec_shuffle.ll Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144037&r1=144036&r2=144037&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Mon Nov 7 17:08:21 2011 @@ -510,11 +510,20 @@ leaveBasicBlock(MBB); } - // Clear the LiveOuts vectors. Should we also collapse any remaining - // DomainValues? - for (LiveOutMap::const_iterator i = LiveOuts.begin(), e = LiveOuts.end(); - i != e; ++i) - delete[] i->second; + // Clear the LiveOuts vectors and collapse any remaining DomainValues. + for (ReversePostOrderTraversal::rpo_iterator + MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) { + LiveOutMap::const_iterator FI = LiveOuts.find(*MBBI); + if (FI == LiveOuts.end()) + continue; + assert(FI->second && "Null entry"); + // The DomainValue is collapsed when the last reference is killed. + LiveRegs = FI->second; + for (unsigned i = 0, e = NumRegs; i != e; ++i) + if (LiveRegs[i]) + Kill(i); + delete[] LiveRegs; + } LiveOuts.clear(); Avail.clear(); Allocator.DestroyAll(); Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=144037&r1=144036&r2=144037&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Mon Nov 7 17:08:21 2011 @@ -315,24 +315,31 @@ define void @test_x86_sse2_movnt_dq(i8* %a0, <2 x i64> %a1) { + ; CHECK: test_x86_sse2_movnt_dq ; CHECK: movl ; CHECK: vmovntdq - call void @llvm.x86.sse2.movnt.dq(i8* %a0, <2 x i64> %a1) + ; add operation forces the execution domain. + %a2 = add <2 x i64> %a1, + call void @llvm.x86.sse2.movnt.dq(i8* %a0, <2 x i64> %a2) ret void } declare void @llvm.x86.sse2.movnt.dq(i8*, <2 x i64>) nounwind define void @test_x86_sse2_movnt_pd(i8* %a0, <2 x double> %a1) { + ; CHECK test_x86_sse2_movnt_pd ; CHECK: movl ; CHECK: vmovntpd - call void @llvm.x86.sse2.movnt.pd(i8* %a0, <2 x double> %a1) + ; fadd operation forces the execution domain. + %a2 = fadd <2 x double> %a1, + call void @llvm.x86.sse2.movnt.pd(i8* %a0, <2 x double> %a2) ret void } declare void @llvm.x86.sse2.movnt.pd(i8*, <2 x double>) nounwind define <2 x double> @test_x86_sse2_mul_sd(<2 x double> %a0, <2 x double> %a1) { + ; CHECK: test_x86_sse2_mul_sd ; CHECK: vmulsd %res = call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] ret <2 x double> %res @@ -749,6 +756,7 @@ define void @test_x86_sse2_storel_dq(i8* %a0, <4 x i32> %a1) { + ; CHECK: test_x86_sse2_storel_dq ; CHECK: movl ; CHECK: vmovq call void @llvm.x86.sse2.storel.dq(i8* %a0, <4 x i32> %a1) @@ -758,6 +766,7 @@ define void @test_x86_sse2_storeu_dq(i8* %a0, <16 x i8> %a1) { + ; CHECK: test_x86_sse2_storeu_dq ; CHECK: movl ; CHECK: vmovdqu call void @llvm.x86.sse2.storeu.dq(i8* %a0, <16 x i8> %a1) @@ -767,15 +776,18 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) { + ; CHECK: test_x86_sse2_storeu_pd ; CHECK: movl ; CHECK: vmovupd - call void @llvm.x86.sse2.storeu.pd(i8* %a0, <2 x double> %a1) + %a2 = fadd <2 x double> %a1, + call void @llvm.x86.sse2.storeu.pd(i8* %a0, <2 x double> %a2) ret void } declare void @llvm.x86.sse2.storeu.pd(i8*, <2 x double>) nounwind define <2 x double> @test_x86_sse2_sub_sd(<2 x double> %a0, <2 x double> %a1) { + ; CHECK: test_x86_sse2_sub_sd ; CHECK: vsubsd %res = call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] ret <2 x double> %res Modified: llvm/trunk/test/CodeGen/X86/avx-logic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-logic.ll?rev=144037&r1=144036&r2=144037&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-logic.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-logic.ll Mon Nov 7 17:08:21 2011 @@ -165,7 +165,9 @@ ; CHECK: vpandn %xmm define <2 x i64> @vpandn(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp { entry: - %y = xor <2 x i64> %a, + ; Force the execution domain with an add. + %a2 = add <2 x i64> %a, + %y = xor <2 x i64> %a2, %x = and <2 x i64> %a, %y ret <2 x i64> %x } @@ -173,7 +175,9 @@ ; CHECK: vpand %xmm define <2 x i64> @vpand(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp { entry: - %x = and <2 x i64> %a, %b + ; Force the execution domain with an add. + %a2 = add <2 x i64> %a, + %x = and <2 x i64> %a2, %b ret <2 x i64> %x } Modified: llvm/trunk/test/CodeGen/X86/nontemporal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/nontemporal.ll?rev=144037&r1=144036&r2=144037&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/nontemporal.ll (original) +++ llvm/trunk/test/CodeGen/X86/nontemporal.ll Mon Nov 7 17:08:21 2011 @@ -3,13 +3,16 @@ define void @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D, <2 x i64> %E) { ; CHECK: movntps %cast = bitcast i8* %B to <4 x float>* - store <4 x float> %A, <4 x float>* %cast, align 16, !nontemporal !0 + %A2 = fadd <4 x float> %A, + store <4 x float> %A2, <4 x float>* %cast, align 16, !nontemporal !0 ; CHECK: movntdq %cast1 = bitcast i8* %B to <2 x i64>* - store <2 x i64> %E, <2 x i64>* %cast1, align 16, !nontemporal !0 + %E2 = add <2 x i64> %E, + store <2 x i64> %E2, <2 x i64>* %cast1, align 16, !nontemporal !0 ; CHECK: movntpd %cast2 = bitcast i8* %B to <2 x double>* - store <2 x double> %C, <2 x double>* %cast2, align 16, !nontemporal !0 + %C2 = fadd <2 x double> %C, + store <2 x double> %C2, <2 x double>* %cast2, align 16, !nontemporal !0 ; CHECK: movnti %cast3 = bitcast i8* %B to i32* store i32 %D, i32* %cast3, align 16, !nontemporal !0 Modified: llvm/trunk/test/CodeGen/X86/sse-align-3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-align-3.ll?rev=144037&r1=144036&r2=144037&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse-align-3.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse-align-3.ll Mon Nov 7 17:08:21 2011 @@ -1,8 +1,8 @@ ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s ; CHECK-NOT: movapd ; CHECK: movaps -; CHECK-NOT: movaps -; CHECK: movapd +; CHECK-NOT: movapd +; CHECK: movaps ; CHECK-NOT: movap define void @foo(<4 x float>* %p, <4 x float> %x) nounwind { Modified: llvm/trunk/test/CodeGen/X86/sse2-blend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-blend.ll?rev=144037&r1=144036&r2=144037&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse2-blend.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse2-blend.ll Mon Nov 7 17:08:21 2011 @@ -26,11 +26,10 @@ ret void } -; FIXME: The -mattr=+sse2,-sse41 disable the ExecutionDepsFix pass causing the -; mixed domains here. +; Without forcing instructions, fall back to the preferred PS domain. ; CHECK: vsel_i64 ; CHECK: xorps -; CHECK: pand +; CHECK: andps ; CHECK: andnps ; CHECK: orps ; CHECK: ret @@ -43,16 +42,14 @@ ret void } -; FIXME: The -mattr=+sse2,-sse41 disable the ExecutionDepsFix pass causing the -; mixed domains here. +; Without forcing instructions, fall back to the preferred PS domain. ; CHECK: vsel_double ; CHECK: xorps -; CHECK: pand +; CHECK: andps ; CHECK: andnps ; CHECK: orps ; CHECK: ret - define void at vsel_double(<4 x double>* %v1, <4 x double>* %v2) { %A = load <4 x double>* %v1 %B = load <4 x double>* %v2 Modified: llvm/trunk/test/CodeGen/X86/sse2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2.ll?rev=144037&r1=144036&r2=144037&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse2.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse2.ll Mon Nov 7 17:08:21 2011 @@ -144,7 +144,7 @@ %tmp7 = insertelement <2 x double> %tmp, double %b, i32 1 ; <<2 x double>> [#uses=1] ret <2 x double> %tmp7 ; CHECK: test11: -; CHECK: movapd 4(%esp), %xmm0 +; CHECK: movaps 4(%esp), %xmm0 } define void @test12() nounwind { Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle.ll?rev=144037&r1=144036&r2=144037&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle.ll Mon Nov 7 17:08:21 2011 @@ -1,9 +1,8 @@ -; RUN: llc < %s -march=x86 -mcpu=core2 -o %t -; RUN: grep movq %t | count 1 -; RUN: grep pshufd %t | count 1 -; RUN: grep movupd %t | count 1 -; RUN: grep pshufhw %t | count 1 +; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s +; CHECK: test_v4sf +; CHECK: movq 8(%esp) +; CHECK: pshufd $80 define void @test_v4sf(<4 x float>* %P, float %X, float %Y) nounwind { %tmp = insertelement <4 x float> zeroinitializer, float %X, i32 0 ; <<4 x float>> [#uses=1] %tmp2 = insertelement <4 x float> %tmp, float %X, i32 1 ; <<4 x float>> [#uses=1] @@ -13,6 +12,9 @@ ret void } +; CHECK: test_v2sd +; CHECK: movups 8(%esp) +; CHECK: movaps define void @test_v2sd(<2 x double>* %P, double %X, double %Y) nounwind { %tmp = insertelement <2 x double> zeroinitializer, double %X, i32 0 ; <<2 x double>> [#uses=1] %tmp2 = insertelement <2 x double> %tmp, double %Y, i32 1 ; <<2 x double>> [#uses=1] @@ -20,6 +22,9 @@ ret void } +; CHECK: test_v8i16 +; CHECK: pshufhw $-58 +; CHECK: movdqa define void @test_v8i16(<2 x i64>* %res, <2 x i64>* %A) nounwind { %tmp = load <2 x i64>* %A ; <<2 x i64>> [#uses=1] %tmp.upgrd.1 = bitcast <2 x i64> %tmp to <8 x i16> ; <<8 x i16>> [#uses=8] From stoklund at 2pi.dk Mon Nov 7 17:10:43 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 07 Nov 2011 23:10:43 -0000 Subject: [llvm-commits] [llvm] r144038 - /llvm/trunk/test/CodeGen/X86/vec_return.ll Message-ID: <20111107231043.EC5392A6C12C@llvm.org> Author: stoklund Date: Mon Nov 7 17:10:43 2011 New Revision: 144038 URL: http://llvm.org/viewvc/llvm-project?rev=144038&view=rev Log: Fix test for Windows as well. Modified: llvm/trunk/test/CodeGen/X86/vec_return.ll Modified: llvm/trunk/test/CodeGen/X86/vec_return.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_return.ll?rev=144038&r1=144037&r2=144038&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_return.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_return.ll Mon Nov 7 17:10:43 2011 @@ -11,7 +11,6 @@ ; CHECK: test2 ; CHECK-NOT: shuf ; CHECK: movaps {{.*}}CPI -; CHECK-NEXT: ret define <4 x i32> @test2() nounwind { ret <4 x i32> < i32 0, i32 0, i32 1, i32 0 > } From eli.friedman at gmail.com Mon Nov 7 17:26:29 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 7 Nov 2011 15:26:29 -0800 Subject: [llvm-commits] [llvm] r144036 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/CodeGen/X86/vec_udiv_to_shift.ll In-Reply-To: <20111107230449.7509D2A6C12C@llvm.org> References: <20111107230449.7509D2A6C12C@llvm.org> Message-ID: On Mon, Nov 7, 2011 at 3:04 PM, Pete Cooper wrote: > Author: pete > Date: Mon Nov ?7 17:04:49 2011 > New Revision: 144036 > > URL: http://llvm.org/viewvc/llvm-project?rev=144036&view=rev > Log: > InstCombine now optimizes vector udiv by power of 2 to shifts > > Fixes r8429 > > Added: > ? ?llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll > Modified: > ? ?llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=144036&r1=144035&r2=144036&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Mon Nov ?7 17:04:49 2011 > @@ -441,19 +441,23 @@ > ? // Handle the integer div common cases > ? if (Instruction *Common = commonIDivTransforms(I)) > ? ? return Common; > - > - ?if (ConstantInt *C = dyn_cast(Op1)) { > + > + ?{ > ? ? // X udiv 2^C -> X >> C > ? ? // Check to see if this is an unsigned division with an exact power of 2, > ? ? // if so, convert to a right shift. > - ? ?if (C->getValue().isPowerOf2()) { // 0 not included in isPowerOf2 > + ? ?const APInt *C; > + ? ?if (match(Op1, m_Power2(C))) { > ? ? ? BinaryOperator *LShr = > - ? ? ? ?BinaryOperator::CreateLShr(Op0, > - ? ? ? ? ? ?ConstantInt::get(Op0->getType(), C->getValue().logBase2())); > + ? ? ?BinaryOperator::CreateLShr(Op0, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ConstantInt::get(Op0->getType(), > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?C->logBase2())); > ? ? ? if (I.isExact()) LShr->setIsExact(); > ? ? ? return LShr; > ? ? } > + ?} > > + ?if (ConstantInt *C = dyn_cast(Op1)) { > ? ? // X udiv C, where C >= signbit > ? ? if (C->getValue().isNegative()) { > ? ? ? Value *IC = Builder->CreateICmpULT(Op0, C); > > Added: llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll?rev=144036&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll (added) > +++ llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll Mon Nov ?7 17:04:49 2011 > @@ -0,0 +1,15 @@ > +; RUN: opt < %s -instcombine -S | FileCheck %s > + > +define <8 x i16> @udiv_vec8x16(<8 x i16> %var) { > +entry: > +; CHECK: lshr <8 x i16> %var, > +%0 = udiv <8 x i16> %var, > +ret <8 x i16> %0 > +} > + > +define <4 x i32> @udiv_vec4x32(<4 x i32> %var) { > +entry: > +; CHECK: lshr <4 x i32> %var, > +%0 = udiv <4 x i32> %var, > +ret <4 x i32> %0 > +} > \ No newline at end of file ^ Newline? -Eli From isanbard at gmail.com Mon Nov 7 17:36:48 2011 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 07 Nov 2011 23:36:48 -0000 Subject: [llvm-commits] [llvm] r144043 - /llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Message-ID: <20111107233649.03B012A6C12C@llvm.org> Author: void Date: Mon Nov 7 17:36:48 2011 New Revision: 144043 URL: http://llvm.org/viewvc/llvm-project?rev=144043&view=rev Log: This code is dead, what with the new EH model and the auto-upgraders in place. Delete! Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=144043&r1=144042&r2=144043&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Mon Nov 7 17:36:48 2011 @@ -28,98 +28,33 @@ #include "llvm/Transforms/Utils/SSAUpdater.h" using namespace llvm; -STATISTIC(NumLandingPadsSplit, "Number of landing pads split"); -STATISTIC(NumUnwindsLowered, "Number of unwind instructions lowered"); -STATISTIC(NumResumesLowered, "Number of eh.resume calls lowered"); -STATISTIC(NumExceptionValuesMoved, "Number of eh.exception calls moved"); +STATISTIC(NumResumesLowered, "Number of resume calls lowered"); namespace { class DwarfEHPrepare : public FunctionPass { const TargetMachine *TM; const TargetLowering *TLI; - // The eh.exception intrinsic. - Function *ExceptionValueIntrinsic; - - // The eh.selector intrinsic. - Function *SelectorIntrinsic; - - // _Unwind_Resume_or_Rethrow or _Unwind_SjLj_Resume call. - Constant *URoR; - - // The EH language-specific catch-all type. - GlobalVariable *EHCatchAllValue; - - // _Unwind_Resume or the target equivalent. + // RewindFunction - _Unwind_Resume or the target equivalent. Constant *RewindFunction; - // We both use and preserve dominator info. - DominatorTree *DT; + bool InsertUnwindResumeCalls(Function &Fn); - // The function we are running on. - Function *F; - - // The landing pads for this function. - typedef SmallPtrSet BBSet; - BBSet LandingPads; - - bool InsertUnwindResumeCalls(); - - bool NormalizeLandingPads(); - bool LowerUnwindsAndResumes(); - bool MoveExceptionValueCalls(); - - Instruction *CreateExceptionValueCall(BasicBlock *BB); - - /// CleanupSelectors - Any remaining eh.selector intrinsic calls which still - /// use the "llvm.eh.catch.all.value" call need to convert to using its - /// initializer instead. - bool CleanupSelectors(SmallPtrSet &Sels); - - bool HasCatchAllInSelector(IntrinsicInst *); - - /// FindAllCleanupSelectors - Find all eh.selector calls that are clean-ups. - void FindAllCleanupSelectors(SmallPtrSet &Sels, - SmallPtrSet &CatchAllSels); - - /// FindAllURoRInvokes - Find all URoR invokes in the function. - void FindAllURoRInvokes(SmallPtrSet &URoRInvokes); - - /// HandleURoRInvokes - Handle invokes of "_Unwind_Resume_or_Rethrow" or - /// "_Unwind_SjLj_Resume" calls. The "unwind" part of these invokes jump to - /// a landing pad within the current function. This is a candidate to merge - /// the selector associated with the URoR invoke with the one from the - /// URoR's landing pad. - bool HandleURoRInvokes(); - - /// FindSelectorAndURoR - Find the eh.selector call and URoR call associated - /// with the eh.exception call. This recursively looks past instructions - /// which don't change the EH pointer value, like casts or PHI nodes. - bool FindSelectorAndURoR(Instruction *Inst, bool &URoRInvoke, - SmallPtrSet &SelCalls, - SmallPtrSet &SeenPHIs); - public: static char ID; // Pass identification, replacement for typeid. DwarfEHPrepare(const TargetMachine *tm) : FunctionPass(ID), TM(tm), TLI(TM->getTargetLowering()), - ExceptionValueIntrinsic(0), SelectorIntrinsic(0), - URoR(0), EHCatchAllValue(0), RewindFunction(0) { + RewindFunction(0) { initializeDominatorTreePass(*PassRegistry::getPassRegistry()); } virtual bool runOnFunction(Function &Fn); - // getAnalysisUsage - We need the dominator tree for handling URoR. - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - AU.addPreserved(); - } + virtual void getAnalysisUsage(AnalysisUsage &AU) const { } const char *getPassName() const { return "Exception handling preparation"; } - }; } // end anonymous namespace @@ -129,543 +64,12 @@ return new DwarfEHPrepare(tm); } -/// HasCatchAllInSelector - Return true if the intrinsic instruction has a -/// catch-all. -bool DwarfEHPrepare::HasCatchAllInSelector(IntrinsicInst *II) { - if (!EHCatchAllValue) return false; - - unsigned ArgIdx = II->getNumArgOperands() - 1; - GlobalVariable *GV = dyn_cast(II->getArgOperand(ArgIdx)); - return GV == EHCatchAllValue; -} - -/// FindAllCleanupSelectors - Find all eh.selector calls that are clean-ups. -void DwarfEHPrepare:: -FindAllCleanupSelectors(SmallPtrSet &Sels, - SmallPtrSet &CatchAllSels) { - for (Value::use_iterator - I = SelectorIntrinsic->use_begin(), - E = SelectorIntrinsic->use_end(); I != E; ++I) { - IntrinsicInst *II = cast(*I); - - if (II->getParent()->getParent() != F) - continue; - - if (!HasCatchAllInSelector(II)) - Sels.insert(II); - else - CatchAllSels.insert(II); - } -} - -/// FindAllURoRInvokes - Find all URoR invokes in the function. -void DwarfEHPrepare:: -FindAllURoRInvokes(SmallPtrSet &URoRInvokes) { - for (Value::use_iterator - I = URoR->use_begin(), - E = URoR->use_end(); I != E; ++I) { - if (InvokeInst *II = dyn_cast(*I)) - URoRInvokes.insert(II); - } -} - -/// CleanupSelectors - Any remaining eh.selector intrinsic calls which still use -/// the "llvm.eh.catch.all.value" call need to convert to using its -/// initializer instead. -bool DwarfEHPrepare::CleanupSelectors(SmallPtrSet &Sels) { - if (!EHCatchAllValue) return false; - - if (!SelectorIntrinsic) { - SelectorIntrinsic = - Intrinsic::getDeclaration(F->getParent(), Intrinsic::eh_selector); - if (!SelectorIntrinsic) return false; - } - - bool Changed = false; - for (SmallPtrSet::iterator - I = Sels.begin(), E = Sels.end(); I != E; ++I) { - IntrinsicInst *Sel = *I; - - // Index of the "llvm.eh.catch.all.value" variable. - unsigned OpIdx = Sel->getNumArgOperands() - 1; - GlobalVariable *GV = dyn_cast(Sel->getArgOperand(OpIdx)); - if (GV != EHCatchAllValue) continue; - Sel->setArgOperand(OpIdx, EHCatchAllValue->getInitializer()); - Changed = true; - } - - return Changed; -} - -/// FindSelectorAndURoR - Find the eh.selector call associated with the -/// eh.exception call. And indicate if there is a URoR "invoke" associated with -/// the eh.exception call. This recursively looks past instructions which don't -/// change the EH pointer value, like casts or PHI nodes. -bool -DwarfEHPrepare::FindSelectorAndURoR(Instruction *Inst, bool &URoRInvoke, - SmallPtrSet &SelCalls, - SmallPtrSet &SeenPHIs) { - bool Changed = false; - - for (Value::use_iterator - I = Inst->use_begin(), E = Inst->use_end(); I != E; ++I) { - Instruction *II = dyn_cast(*I); - if (!II || II->getParent()->getParent() != F) continue; - - if (IntrinsicInst *Sel = dyn_cast(II)) { - if (Sel->getIntrinsicID() == Intrinsic::eh_selector) - SelCalls.insert(Sel); - } else if (InvokeInst *Invoke = dyn_cast(II)) { - if (Invoke->getCalledFunction() == URoR) - URoRInvoke = true; - } else if (CastInst *CI = dyn_cast(II)) { - Changed |= FindSelectorAndURoR(CI, URoRInvoke, SelCalls, SeenPHIs); - } else if (PHINode *PN = dyn_cast(II)) { - if (SeenPHIs.insert(PN)) - // Don't process a PHI node more than once. - Changed |= FindSelectorAndURoR(PN, URoRInvoke, SelCalls, SeenPHIs); - } - } - - return Changed; -} - -/// HandleURoRInvokes - Handle invokes of "_Unwind_Resume_or_Rethrow" or -/// "_Unwind_SjLj_Resume" calls. The "unwind" part of these invokes jump to a -/// landing pad within the current function. This is a candidate to merge the -/// selector associated with the URoR invoke with the one from the URoR's -/// landing pad. -bool DwarfEHPrepare::HandleURoRInvokes() { - if (!EHCatchAllValue) { - EHCatchAllValue = - F->getParent()->getNamedGlobal("llvm.eh.catch.all.value"); - if (!EHCatchAllValue) return false; - } - - if (!SelectorIntrinsic) { - SelectorIntrinsic = - Intrinsic::getDeclaration(F->getParent(), Intrinsic::eh_selector); - if (!SelectorIntrinsic) return false; - } - - SmallPtrSet Sels; - SmallPtrSet CatchAllSels; - FindAllCleanupSelectors(Sels, CatchAllSels); - - if (!URoR) { - URoR = F->getParent()->getFunction("_Unwind_Resume_or_Rethrow"); - if (!URoR) return CleanupSelectors(CatchAllSels); - } - - SmallPtrSet URoRInvokes; - FindAllURoRInvokes(URoRInvokes); - - SmallPtrSet SelsToConvert; - - for (SmallPtrSet::iterator - SI = Sels.begin(), SE = Sels.end(); SI != SE; ++SI) { - const BasicBlock *SelBB = (*SI)->getParent(); - for (SmallPtrSet::iterator - UI = URoRInvokes.begin(), UE = URoRInvokes.end(); UI != UE; ++UI) { - const BasicBlock *URoRBB = (*UI)->getParent(); - if (DT->dominates(SelBB, URoRBB)) { - SelsToConvert.insert(*SI); - break; - } - } - } - - bool Changed = false; - - if (Sels.size() != SelsToConvert.size()) { - // If we haven't been able to convert all of the clean-up selectors, then - // loop through the slow way to see if they still need to be converted. - if (!ExceptionValueIntrinsic) { - ExceptionValueIntrinsic = - Intrinsic::getDeclaration(F->getParent(), Intrinsic::eh_exception); - if (!ExceptionValueIntrinsic) - return CleanupSelectors(CatchAllSels); - } - - for (Value::use_iterator - I = ExceptionValueIntrinsic->use_begin(), - E = ExceptionValueIntrinsic->use_end(); I != E; ++I) { - IntrinsicInst *EHPtr = dyn_cast(*I); - if (!EHPtr || EHPtr->getParent()->getParent() != F) continue; - - bool URoRInvoke = false; - SmallPtrSet SelCalls; - SmallPtrSet SeenPHIs; - Changed |= FindSelectorAndURoR(EHPtr, URoRInvoke, SelCalls, SeenPHIs); - - if (URoRInvoke) { - // This EH pointer is being used by an invoke of an URoR instruction and - // an eh.selector intrinsic call. If the eh.selector is a 'clean-up', we - // need to convert it to a 'catch-all'. - for (SmallPtrSet::iterator - SI = SelCalls.begin(), SE = SelCalls.end(); SI != SE; ++SI) - if (!HasCatchAllInSelector(*SI)) - SelsToConvert.insert(*SI); - } - } - } - - if (!SelsToConvert.empty()) { - // Convert all clean-up eh.selectors, which are associated with "invokes" of - // URoR calls, into catch-all eh.selectors. - Changed = true; - - for (SmallPtrSet::iterator - SI = SelsToConvert.begin(), SE = SelsToConvert.end(); - SI != SE; ++SI) { - IntrinsicInst *II = *SI; - - // Use the exception object pointer and the personality function - // from the original selector. - CallSite CS(II); - IntrinsicInst::op_iterator I = CS.arg_begin(); - IntrinsicInst::op_iterator E = CS.arg_end(); - IntrinsicInst::op_iterator B = prior(E); - - // Exclude last argument if it is an integer. - if (isa(B)) E = B; - - // Add exception object pointer (front). - // Add personality function (next). - // Add in any filter IDs (rest). - SmallVector Args(I, E); - - Args.push_back(EHCatchAllValue->getInitializer()); // Catch-all indicator. - - CallInst *NewSelector = - CallInst::Create(SelectorIntrinsic, Args, "eh.sel.catch.all", II); - - NewSelector->setTailCall(II->isTailCall()); - NewSelector->setAttributes(II->getAttributes()); - NewSelector->setCallingConv(II->getCallingConv()); - - II->replaceAllUsesWith(NewSelector); - II->eraseFromParent(); - } - } - - Changed |= CleanupSelectors(CatchAllSels); - return Changed; -} - -/// NormalizeLandingPads - Normalize and discover landing pads, noting them -/// in the LandingPads set. A landing pad is normal if the only CFG edges -/// that end at it are unwind edges from invoke instructions. If we inlined -/// through an invoke we could have a normal branch from the previous -/// unwind block through to the landing pad for the original invoke. -/// Abnormal landing pads are fixed up by redirecting all unwind edges to -/// a new basic block which falls through to the original. -bool DwarfEHPrepare::NormalizeLandingPads() { - bool Changed = false; - - const MCAsmInfo *MAI = TM->getMCAsmInfo(); - bool usingSjLjEH = MAI->getExceptionHandlingType() == ExceptionHandling::SjLj; - - for (Function::iterator I = F->begin(), E = F->end(); I != E; ++I) { - TerminatorInst *TI = I->getTerminator(); - if (!isa(TI)) - continue; - BasicBlock *LPad = TI->getSuccessor(1); - // Skip landing pads that have already been normalized. - if (LandingPads.count(LPad)) - continue; - - // Check that only invoke unwind edges end at the landing pad. - bool OnlyUnwoundTo = true; - bool SwitchOK = usingSjLjEH; - for (pred_iterator PI = pred_begin(LPad), PE = pred_end(LPad); - PI != PE; ++PI) { - TerminatorInst *PT = (*PI)->getTerminator(); - // The SjLj dispatch block uses a switch instruction. This is effectively - // an unwind edge, so we can disregard it here. There will only ever - // be one dispatch, however, so if there are multiple switches, one - // of them truly is a normal edge, not an unwind edge. - if (SwitchOK && isa(PT)) { - SwitchOK = false; - continue; - } - if (!isa(PT) || LPad == PT->getSuccessor(0)) { - OnlyUnwoundTo = false; - break; - } - } - - if (OnlyUnwoundTo) { - // Only unwind edges lead to the landing pad. Remember the landing pad. - LandingPads.insert(LPad); - continue; - } - - // At least one normal edge ends at the landing pad. Redirect the unwind - // edges to a new basic block which falls through into this one. - - // Create the new basic block. - BasicBlock *NewBB = BasicBlock::Create(F->getContext(), - LPad->getName() + "_unwind_edge"); - - // Insert it into the function right before the original landing pad. - LPad->getParent()->getBasicBlockList().insert(LPad, NewBB); - - // Redirect unwind edges from the original landing pad to NewBB. - for (pred_iterator PI = pred_begin(LPad), PE = pred_end(LPad); PI != PE; ) { - TerminatorInst *PT = (*PI++)->getTerminator(); - if (isa(PT) && PT->getSuccessor(1) == LPad) - // Unwind to the new block. - PT->setSuccessor(1, NewBB); - } - - // If there are any PHI nodes in LPad, we need to update them so that they - // merge incoming values from NewBB instead. - for (BasicBlock::iterator II = LPad->begin(); isa(II); ++II) { - PHINode *PN = cast(II); - pred_iterator PB = pred_begin(NewBB), PE = pred_end(NewBB); - - // Check to see if all of the values coming in via unwind edges are the - // same. If so, we don't need to create a new PHI node. - Value *InVal = PN->getIncomingValueForBlock(*PB); - for (pred_iterator PI = PB; PI != PE; ++PI) { - if (PI != PB && InVal != PN->getIncomingValueForBlock(*PI)) { - InVal = 0; - break; - } - } - - if (InVal == 0) { - // Different unwind edges have different values. Create a new PHI node - // in NewBB. - PHINode *NewPN = PHINode::Create(PN->getType(), - PN->getNumIncomingValues(), - PN->getName()+".unwind", NewBB); - // Add an entry for each unwind edge, using the value from the old PHI. - for (pred_iterator PI = PB; PI != PE; ++PI) - NewPN->addIncoming(PN->getIncomingValueForBlock(*PI), *PI); - - // Now use this new PHI as the common incoming value for NewBB in PN. - InVal = NewPN; - } - - // Revector exactly one entry in the PHI node to come from NewBB - // and delete all other entries that come from unwind edges. If - // there are both normal and unwind edges from the same predecessor, - // this leaves an entry for the normal edge. - for (pred_iterator PI = PB; PI != PE; ++PI) - PN->removeIncomingValue(*PI); - PN->addIncoming(InVal, NewBB); - } - - // Add a fallthrough from NewBB to the original landing pad. - BranchInst::Create(LPad, NewBB); - - // Now update DominatorTree analysis information. - DT->splitBlock(NewBB); - - // Remember the newly constructed landing pad. The original landing pad - // LPad is no longer a landing pad now that all unwind edges have been - // revectored to NewBB. - LandingPads.insert(NewBB); - ++NumLandingPadsSplit; - Changed = true; - } - - return Changed; -} - -/// LowerUnwinds - Turn unwind instructions into calls to _Unwind_Resume, -/// rethrowing any previously caught exception. This will crash horribly -/// at runtime if there is no such exception: using unwind to throw a new -/// exception is currently not supported. -bool DwarfEHPrepare::LowerUnwindsAndResumes() { - SmallVector ResumeInsts; - - for (Function::iterator fi = F->begin(), fe = F->end(); fi != fe; ++fi) { - for (BasicBlock::iterator bi = fi->begin(), be = fi->end(); bi != be; ++bi){ - if (isa(bi)) - ResumeInsts.push_back(bi); - else if (CallInst *call = dyn_cast(bi)) - if (Function *fn = dyn_cast(call->getCalledValue())) - if (fn->getName() == "llvm.eh.resume") - ResumeInsts.push_back(bi); - } - } - - if (ResumeInsts.empty()) return false; - - // Find the rewind function if we didn't already. - if (!RewindFunction) { - LLVMContext &Ctx = ResumeInsts[0]->getContext(); - FunctionType *FTy = FunctionType::get(Type::getVoidTy(Ctx), - Type::getInt8PtrTy(Ctx), false); - const char *RewindName = TLI->getLibcallName(RTLIB::UNWIND_RESUME); - RewindFunction = F->getParent()->getOrInsertFunction(RewindName, FTy); - } - - bool Changed = false; - - for (SmallVectorImpl::iterator - I = ResumeInsts.begin(), E = ResumeInsts.end(); I != E; ++I) { - Instruction *RI = *I; - - // Replace the resuming instruction with a call to _Unwind_Resume (or the - // appropriate target equivalent). - - llvm::Value *ExnValue; - if (isa(RI)) - ExnValue = CreateExceptionValueCall(RI->getParent()); - else - ExnValue = cast(RI)->getArgOperand(0); - - // Create the call... - CallInst *CI = CallInst::Create(RewindFunction, ExnValue, "", RI); - CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME)); - - // ...followed by an UnreachableInst, if it was an unwind. - // Calls to llvm.eh.resume are typically already followed by this. - if (isa(RI)) - new UnreachableInst(RI->getContext(), RI); - - if (isa(RI)) - ++NumUnwindsLowered; - else - ++NumResumesLowered; - - // Nuke the resume instruction. - RI->eraseFromParent(); - - Changed = true; - } - - return Changed; -} - -/// MoveExceptionValueCalls - Ensure that eh.exception is only ever called from -/// landing pads by replacing calls outside of landing pads with direct use of -/// a register holding the appropriate value; this requires adding calls inside -/// all landing pads to initialize the register. Also, move eh.exception calls -/// inside landing pads to the start of the landing pad (optional, but may make -/// things simpler for later passes). -bool DwarfEHPrepare::MoveExceptionValueCalls() { - // If the eh.exception intrinsic is not declared in the module then there is - // nothing to do. Speed up compilation by checking for this common case. - if (!ExceptionValueIntrinsic && - !F->getParent()->getFunction(Intrinsic::getName(Intrinsic::eh_exception))) - return false; - - bool Changed = false; - - // Move calls to eh.exception that are inside a landing pad to the start of - // the landing pad. - for (BBSet::const_iterator LI = LandingPads.begin(), LE = LandingPads.end(); - LI != LE; ++LI) { - BasicBlock *LP = *LI; - for (BasicBlock::iterator II = LP->getFirstNonPHIOrDbg(), IE = LP->end(); - II != IE;) - if (EHExceptionInst *EI = dyn_cast(II++)) { - // Found a call to eh.exception. - if (!EI->use_empty()) { - // If there is already a call to eh.exception at the start of the - // landing pad, then get hold of it; otherwise create such a call. - Value *CallAtStart = CreateExceptionValueCall(LP); - - // If the call was at the start of a landing pad then leave it alone. - if (EI == CallAtStart) - continue; - EI->replaceAllUsesWith(CallAtStart); - } - EI->eraseFromParent(); - ++NumExceptionValuesMoved; - Changed = true; - } - } - - // Look for calls to eh.exception that are not in a landing pad. If one is - // found, then a register that holds the exception value will be created in - // each landing pad, and the SSAUpdater will be used to compute the values - // returned by eh.exception calls outside of landing pads. - SSAUpdater SSA; - - // Remember where we found the eh.exception call, to avoid rescanning earlier - // basic blocks which we already know contain no eh.exception calls. - bool FoundCallOutsideLandingPad = false; - Function::iterator BB = F->begin(); - for (Function::iterator BE = F->end(); BB != BE; ++BB) { - // Skip over landing pads. - if (LandingPads.count(BB)) - continue; - - for (BasicBlock::iterator II = BB->getFirstNonPHIOrDbg(), IE = BB->end(); - II != IE; ++II) - if (isa(II)) { - SSA.Initialize(II->getType(), II->getName()); - FoundCallOutsideLandingPad = true; - break; - } - - if (FoundCallOutsideLandingPad) - break; - } - - // If all calls to eh.exception are in landing pads then we are done. - if (!FoundCallOutsideLandingPad) - return Changed; - - // Add a call to eh.exception at the start of each landing pad, and tell the - // SSAUpdater that this is the value produced by the landing pad. - for (BBSet::iterator LI = LandingPads.begin(), LE = LandingPads.end(); - LI != LE; ++LI) - SSA.AddAvailableValue(*LI, CreateExceptionValueCall(*LI)); - - // Now turn all calls to eh.exception that are not in a landing pad into a use - // of the appropriate register. - for (Function::iterator BE = F->end(); BB != BE; ++BB) { - // Skip over landing pads. - if (LandingPads.count(BB)) - continue; - - for (BasicBlock::iterator II = BB->getFirstNonPHIOrDbg(), IE = BB->end(); - II != IE;) - if (EHExceptionInst *EI = dyn_cast(II++)) { - // Found a call to eh.exception, replace it with the value from any - // upstream landing pad(s). - EI->replaceAllUsesWith(SSA.GetValueAtEndOfBlock(BB)); - EI->eraseFromParent(); - ++NumExceptionValuesMoved; - } - } - - return true; -} - -/// CreateExceptionValueCall - Insert a call to the eh.exception intrinsic at -/// the start of the basic block (unless there already is one, in which case -/// the existing call is returned). -Instruction *DwarfEHPrepare::CreateExceptionValueCall(BasicBlock *BB) { - Instruction *Start = BB->getFirstNonPHIOrDbg(); - // Is this a call to eh.exception? - if (IntrinsicInst *CI = dyn_cast(Start)) - if (CI->getIntrinsicID() == Intrinsic::eh_exception) - // Reuse the existing call. - return Start; - - // Find the eh.exception intrinsic if we didn't already. - if (!ExceptionValueIntrinsic) - ExceptionValueIntrinsic = Intrinsic::getDeclaration(F->getParent(), - Intrinsic::eh_exception); - - // Create the call. - return CallInst::Create(ExceptionValueIntrinsic, "eh.value.call", Start); -} - /// InsertUnwindResumeCalls - Convert the ResumeInsts that are still present /// into calls to the appropriate _Unwind_Resume function. -bool DwarfEHPrepare::InsertUnwindResumeCalls() { +bool DwarfEHPrepare::InsertUnwindResumeCalls(Function &Fn) { bool UsesNewEH = false; SmallVector Resumes; - for (Function::iterator I = F->begin(), E = F->end(); I != E; ++I) { + for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { TerminatorInst *TI = I->getTerminator(); if (ResumeInst *RI = dyn_cast(TI)) Resumes.push_back(RI); @@ -682,18 +86,17 @@ FunctionType *FTy = FunctionType::get(Type::getVoidTy(Ctx), Type::getInt8PtrTy(Ctx), false); const char *RewindName = TLI->getLibcallName(RTLIB::UNWIND_RESUME); - RewindFunction = F->getParent()->getOrInsertFunction(RewindName, FTy); + RewindFunction = Fn.getParent()->getOrInsertFunction(RewindName, FTy); } // Create the basic block where the _Unwind_Resume call will live. - LLVMContext &Ctx = F->getContext(); - BasicBlock *UnwindBB = BasicBlock::Create(Ctx, "unwind_resume", F); + LLVMContext &Ctx = Fn.getContext(); + BasicBlock *UnwindBB = BasicBlock::Create(Ctx, "unwind_resume", &Fn); PHINode *PN = PHINode::Create(Type::getInt8PtrTy(Ctx), Resumes.size(), "exn.obj", UnwindBB); // Extract the exception object from the ResumeInst and add it to the PHI node // that feeds the _Unwind_Resume call. - BasicBlock *UnwindBBDom = Resumes[0]->getParent(); for (SmallVectorImpl::iterator I = Resumes.begin(), E = Resumes.end(); I != E; ++I) { ResumeInst *RI = *I; @@ -701,8 +104,8 @@ ExtractValueInst *ExnObj = ExtractValueInst::Create(RI->getOperand(0), 0, "exn.obj", RI); PN->addIncoming(ExnObj, RI->getParent()); - UnwindBBDom = DT->findNearestCommonDominator(RI->getParent(), UnwindBBDom); RI->eraseFromParent(); + ++NumResumesLowered; } // Call the function. @@ -711,40 +114,10 @@ // We never expect _Unwind_Resume to return. new UnreachableInst(Ctx, UnwindBB); - - // Now update DominatorTree analysis information. - DT->addNewBlock(UnwindBB, UnwindBBDom); return true; } bool DwarfEHPrepare::runOnFunction(Function &Fn) { - bool Changed = false; - - // Initialize internal state. - DT = &getAnalysis(); // FIXME: We won't need this with the new EH. - F = &Fn; - - if (InsertUnwindResumeCalls()) { - // FIXME: The reset of this function can go once the new EH is done. - LandingPads.clear(); - return true; - } - - // Ensure that only unwind edges end at landing pads (a landing pad is a - // basic block where an invoke unwind edge ends). - Changed |= NormalizeLandingPads(); - - // Turn unwind instructions and eh.resume calls into libcalls. - Changed |= LowerUnwindsAndResumes(); - - // TODO: Move eh.selector calls to landing pads and combine them. - - // Move eh.exception calls to landing pads. - Changed |= MoveExceptionValueCalls(); - - Changed |= HandleURoRInvokes(); - - LandingPads.clear(); - + bool Changed = InsertUnwindResumeCalls(Fn); return Changed; } From resistor at mac.com Mon Nov 7 17:40:45 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 07 Nov 2011 15:40:45 -0800 Subject: [llvm-commits] MachOObjectFile fix functions In-Reply-To: <6AE1604EE3EC5F4296C096518C6B77EE1805C8FA97@mail.accesssoftek.com> References: <6AE1604EE3EC5F4296C096518C6B77EE1805B07349@mail.accesssoftek.com> <6AE1604EE3EC5F4296C096518C6B77EE1805C8FA97@mail.accesssoftek.com> Message-ID: Danil, On Nov 7, 2011, at 2:40 PM, Danil Malyshev wrote: > Please find attached the changed patch which addresses the following 2 things: > 1. Functions in ELFObjectFile, MachOObjectFile and COFFObjectFile should returns same result. This is fine in general, but we need to make sure we're standardizing on the right behaviors. > 2. We don't need have several functions with similar functionality which can be obtained by other means. I have many more issues with this one. Comments inline. > getSymbolAddress - removed. I don't like this. Getting symbol virtual addresses is one of the most common operations we do in, say, llvm-objdump.cpp or MachODump.cpp. I think this will make that code needlessly complex and non-obvious. > getRelocationAddress - removed. This can't be removed. MachO scattered relocations relocate on a virtual address, rather than a symbol, so getSymbol().getAddress() doesn't work for them. > getSymbolOffset - returns the offset from the beginning of the section. I don't particularly mind standardizing on this as the definition for "getOffset" methods, but it doesn't seem particularly useful to me either. Why require a two-stage lookup (section offset + symbol offset from section) rather than just defining it to return a file offset? > If we need the virtual address we can use something like symbol.getOffset() + symbol.getSection().getAddress() See my above comments about how common this lookup is and why I don't think we should make it more complex. > If we need the pointer to the first byte of symbol we can use something like getOffset() + getSection().getSectionContents().begin() > getRelocationOffset - returns the offset from the beginning of the section. > If we need the virtual address we can use somethings like reloc.getOffset() + reloc.getSection().getAddress() This does not match my understanding of what getRelocationAddress() computes. My understanding is that it returns the virtual address of the value being relocated upon, in which case this is not the same as what you are proposing. See my comments above about why this value is necessary on MachO rather than just using getSymbol().getAddress(). --Owen -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111107/c3d85df4/attachment.html From eli.friedman at gmail.com Mon Nov 7 17:53:20 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 07 Nov 2011 23:53:20 -0000 Subject: [llvm-commits] [llvm] r144044 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll Message-ID: <20111107235320.CC7192A6C12C@llvm.org> Author: efriedma Date: Mon Nov 7 17:53:20 2011 New Revision: 144044 URL: http://llvm.org/viewvc/llvm-project?rev=144044&view=rev Log: Revert r144034 while I try to track down a crash. Removed: llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=144044&r1=144043&r2=144044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 7 17:53:20 2011 @@ -285,7 +285,6 @@ Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), ST->isVolatile(), ST->isNonTemporal(), Alignment); DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); - DAG.RemoveDeadNode(ST, DUL); return; } // Do a (aligned) store to a stack slot, then copy from the stack slot @@ -350,7 +349,6 @@ DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], Stores.size()); DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); - DAG.RemoveDeadNode(ST, DUL); return; } assert(ST->getMemoryVT().isInteger() && @@ -383,7 +381,6 @@ SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); - DAG.RemoveDeadNode(ST, DUL); } /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. @@ -1147,7 +1144,6 @@ if (!ST->isTruncatingStore()) { if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { DAG.ReplaceAllUsesWith(ST, OptStore, this); - DAG.RemoveDeadNode(ST, this); break; } @@ -1173,10 +1169,8 @@ break; case TargetLowering::Custom: Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG); - if (Tmp1.getNode()) { + if (Tmp1.getNode()) DAG.ReplaceAllUsesWith(SDValue(Node, 0), Tmp1, this); - DAG.RemoveDeadNode(Node, this); - } break; case TargetLowering::Promote: { assert(VT.isVector() && "Unknown legal promote case!"); @@ -1187,7 +1181,6 @@ ST->getPointerInfo(), isVolatile, isNonTemporal, Alignment); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); - DAG.RemoveDeadNode(Node, this); break; } } @@ -1210,7 +1203,6 @@ DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), NVT, isVolatile, isNonTemporal, Alignment); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); - DAG.RemoveDeadNode(Node, this); } else if (StWidth & (StWidth - 1)) { // If not storing a power-of-2 number of bits, expand as two stores. assert(!StVT.isVector() && "Unsupported truncstore!"); @@ -1266,7 +1258,6 @@ // The order of the stores doesn't matter. SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); - DAG.RemoveDeadNode(Node, this); } else { if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || Tmp2 != ST->getBasePtr()) @@ -1289,7 +1280,6 @@ DAG.ReplaceAllUsesWith(SDValue(Node, 0), TLI.LowerOperation(SDValue(Node, 0), DAG), this); - DAG.RemoveDeadNode(Node, this); break; case TargetLowering::Expand: assert(!StVT.isVector() && @@ -1302,7 +1292,6 @@ DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), isVolatile, isNonTemporal, Alignment); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); - DAG.RemoveDeadNode(Node, this); break; } } @@ -3372,7 +3361,6 @@ DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), &Scalars[0], Scalars.size()); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); - DAG.RemoveDeadNode(Node, this); break; } case ISD::GLOBAL_OFFSET_TABLE: @@ -3389,10 +3377,8 @@ } // Replace the original node with the legalized result. - if (!Results.empty()) { + if (!Results.empty()) DAG.ReplaceAllUsesWith(Node, Results.data(), this); - DAG.RemoveDeadNode(Node, this); - } } void SelectionDAGLegalize::PromoteNode(SDNode *Node) { @@ -3526,10 +3512,8 @@ } // Replace the original node with the legalized result. - if (!Results.empty()) { + if (!Results.empty()) DAG.ReplaceAllUsesWith(Node, Results.data(), this); - DAG.RemoveDeadNode(Node, this); - } } // SelectionDAG::Legalize - This is the entry point for the file. Removed: llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll?rev=144043&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll (original) +++ llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll (removed) @@ -1,14 +0,0 @@ -; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s - -; We don't really care what this outputs; just make sure it's somewhat sane. -; CHECK: legalize_test -; CHECK: vmovups -define void @legalize_test(i32 %x, <8 x i32>* %p) nounwind { -entry: - %t1 = insertelement <8 x i32> , i32 %x, i32 0 - %t2 = shufflevector <8 x i32> %t1, <8 x i32> zeroinitializer, <8 x i32> - %int2float = sitofp <8 x i32> %t2 to <8 x float> - %blendAsInt.i821 = bitcast <8 x float> %int2float to <8 x i32> - store <8 x i32> %blendAsInt.i821, <8 x i32>* %p, align 4 - ret void -} From peter_cooper at apple.com Mon Nov 7 18:03:24 2011 From: peter_cooper at apple.com (Pete Cooper) Date: Tue, 08 Nov 2011 00:03:24 -0000 Subject: [llvm-commits] [llvm] r144046 - /llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll Message-ID: <20111108000324.D59082A6C12C@llvm.org> Author: pete Date: Mon Nov 7 18:03:24 2011 New Revision: 144046 URL: http://llvm.org/viewvc/llvm-project?rev=144046&view=rev Log: Added missing newline Modified: llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll Modified: llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll?rev=144046&r1=144045&r2=144046&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll Mon Nov 7 18:03:24 2011 @@ -12,4 +12,4 @@ ; CHECK: lshr <4 x i32> %var, %0 = udiv <4 x i32> %var, ret <4 x i32> %0 -} \ No newline at end of file +} From mcrosier at apple.com Mon Nov 7 18:03:32 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 08 Nov 2011 00:03:32 -0000 Subject: [llvm-commits] [llvm] r144047 - in /llvm/trunk: lib/Target/ARM/ARMCallingConv.td lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel-call.ll Message-ID: <20111108000332.BE2C72A6C12C@llvm.org> Author: mcrosier Date: Mon Nov 7 18:03:32 2011 New Revision: 144047 URL: http://llvm.org/viewvc/llvm-project?rev=144047&view=rev Log: Enable support for returning i1, i8, and i16. Nothing special todo as it's the callee's responsibility to sign or zero-extend the return value. The additional test case just checks to make sure the calls are selected (i.e., -fast-isel-abort doesn't assert). Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.td llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallingConv.td?rev=144047&r1=144046&r2=144047&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCallingConv.td (original) +++ llvm/trunk/lib/Target/ARM/ARMCallingConv.td Mon Nov 7 18:03:32 2011 @@ -43,6 +43,7 @@ ]>; def RetCC_ARM_APCS : CallingConv<[ + CCIfType<[i1, i8, i16], CCPromoteToType>, CCIfType<[f32], CCBitConvertToType>, // Handle all vector types as either f64 or v2f64. @@ -106,6 +107,7 @@ ]>; def RetCC_ARM_AAPCS_Common : CallingConv<[ + CCIfType<[i1, i8, i16], CCPromoteToType>, CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> ]>; Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144047&r1=144046&r2=144047&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Nov 7 18:03:32 2011 @@ -1697,6 +1697,11 @@ } else { assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); EVT CopyVT = RVLocs[0].getValVT(); + + // Special handling for extended integers. + if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16) + CopyVT = MVT::i32; + TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); unsigned ResultReg = createResultReg(DstRC); @@ -1913,7 +1918,8 @@ MVT RetVT; if (RetTy->isVoidTy()) RetVT = MVT::isVoid; - else if (!isTypeLegal(RetTy, RetVT)) + else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 && + RetVT != MVT::i8 && RetVT != MVT::i1) return false; // TODO: For now if we have long calls specified we don't handle the call. Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll?rev=144047&r1=144046&r2=144047&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-call.ll Mon Nov 7 18:03:32 2011 @@ -65,3 +65,18 @@ %7 = call i32 @t4(i16 zeroext 65535) ret void } + +define void @foo2() nounwind { + %1 = call signext i16 @t5() + %2 = call zeroext i16 @t6() + %3 = call signext i8 @t7() + %4 = call zeroext i8 @t8() + %5 = call zeroext i1 @t9() + ret void +} + +declare signext i16 @t5(); +declare zeroext i16 @t6(); +declare signext i8 @t7(); +declare zeroext i8 @t8(); +declare zeroext i1 @t9(); From peter_cooper at apple.com Mon Nov 7 18:06:00 2011 From: peter_cooper at apple.com (Peter Cooper) Date: Mon, 07 Nov 2011 16:06:00 -0800 Subject: [llvm-commits] [llvm] r144036 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/CodeGen/X86/vec_udiv_to_shift.ll In-Reply-To: References: <20111107230449.7509D2A6C12C@llvm.org> Message-ID: <4291E75D-95AD-4321-AB13-DFF6672C2E62@apple.com> Thanks Eli. Had no idea i needed that in ll files On Nov 7, 2011, at 3:26 PM, Eli Friedman wrote: > On Mon, Nov 7, 2011 at 3:04 PM, Pete Cooper wrote: >> Author: pete >> Date: Mon Nov 7 17:04:49 2011 >> New Revision: 144036 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=144036&view=rev >> Log: >> InstCombine now optimizes vector udiv by power of 2 to shifts >> >> Fixes r8429 >> >> Added: >> llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll >> Modified: >> llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp >> >> Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=144036&r1=144035&r2=144036&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original) >> +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Mon Nov 7 17:04:49 2011 >> @@ -441,19 +441,23 @@ >> // Handle the integer div common cases >> if (Instruction *Common = commonIDivTransforms(I)) >> return Common; >> - >> - if (ConstantInt *C = dyn_cast(Op1)) { >> + >> + { >> // X udiv 2^C -> X >> C >> // Check to see if this is an unsigned division with an exact power of 2, >> // if so, convert to a right shift. >> - if (C->getValue().isPowerOf2()) { // 0 not included in isPowerOf2 >> + const APInt *C; >> + if (match(Op1, m_Power2(C))) { >> BinaryOperator *LShr = >> - BinaryOperator::CreateLShr(Op0, >> - ConstantInt::get(Op0->getType(), C->getValue().logBase2())); >> + BinaryOperator::CreateLShr(Op0, >> + ConstantInt::get(Op0->getType(), >> + C->logBase2())); >> if (I.isExact()) LShr->setIsExact(); >> return LShr; >> } >> + } >> >> + if (ConstantInt *C = dyn_cast(Op1)) { >> // X udiv C, where C >= signbit >> if (C->getValue().isNegative()) { >> Value *IC = Builder->CreateICmpULT(Op0, C); >> >> Added: llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll?rev=144036&view=auto >> ============================================================================== >> --- llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll (added) >> +++ llvm/trunk/test/CodeGen/X86/vec_udiv_to_shift.ll Mon Nov 7 17:04:49 2011 >> @@ -0,0 +1,15 @@ >> +; RUN: opt < %s -instcombine -S | FileCheck %s >> + >> +define <8 x i16> @udiv_vec8x16(<8 x i16> %var) { >> +entry: >> +; CHECK: lshr <8 x i16> %var, >> +%0 = udiv <8 x i16> %var, >> +ret <8 x i16> %0 >> +} >> + >> +define <4 x i32> @udiv_vec4x32(<4 x i32> %var) { >> +entry: >> +; CHECK: lshr <4 x i32> %var, >> +%0 = udiv <4 x i32> %var, >> +ret <4 x i32> %0 >> +} >> \ No newline at end of file > > ^ Newline? > > -Eli From isanbard at gmail.com Mon Nov 7 18:09:28 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 08 Nov 2011 00:09:28 -0000 Subject: [llvm-commits] [llvm] r144048 - in /llvm/trunk/test/CodeGen: ARM/2009-08-31-LSDA-Name.ll ARM/2010-07-26-GlobalMerge.ll ARM/2010-08-04-EHCrash.ll ARM/2011-05-04-MultipleLandingPadSuccs.ll ARM/eh-resume-darwin.ll X86/no-cfi.ll Message-ID: <20111108000928.35F592A6C12C@llvm.org> Author: void Date: Mon Nov 7 18:09:27 2011 New Revision: 144048 URL: http://llvm.org/viewvc/llvm-project?rev=144048&view=rev Log: Convert tests to the new EH model. Modified: llvm/trunk/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll llvm/trunk/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll llvm/trunk/test/CodeGen/ARM/2010-08-04-EHCrash.ll llvm/trunk/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll llvm/trunk/test/CodeGen/ARM/eh-resume-darwin.ll llvm/trunk/test/CodeGen/X86/no-cfi.ll Modified: llvm/trunk/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll?rev=144048&r1=144047&r2=144048&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll Mon Nov 7 18:09:27 2011 @@ -37,10 +37,11 @@ ret void lpad: ; preds = %entry - %eh_ptr = call i8* @llvm.eh.exception() + %exn = landingpad {i8*, i32} personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + cleanup + %eh_ptr = extractvalue {i8*, i32} %exn, 0 store i8* %eh_ptr, i8** %eh_exception - %eh_ptr1 = load i8** %eh_exception - %eh_select2 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %eh_ptr1, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i32 0) + %eh_select2 = extractvalue {i8*, i32} %exn, 1 store i32 %eh_select2, i32* %eh_selector br label %ppad @@ -94,10 +95,6 @@ declare void @_Z3barv() -declare i8* @llvm.eh.exception() nounwind readonly - -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare i32 @llvm.eh.typeid.for(i8*) nounwind declare i32 @__gxx_personality_sj0(...) Modified: llvm/trunk/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll?rev=144048&r1=144047&r2=144048&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll Mon Nov 7 18:09:27 2011 @@ -21,12 +21,8 @@ declare i8* @__cxa_allocate_exception(i32) -declare i8* @llvm.eh.exception() nounwind readonly - declare i32 @__gxx_personality_sj0(...) -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare i32 @llvm.eh.typeid.for(i8*) nounwind declare void @_Unwind_SjLj_Resume(i8*) @@ -75,8 +71,11 @@ ret i32 %conv lpad: ; preds = %entry - %exn = tail call i8* @llvm.eh.exception() nounwind ; [#uses=4] - %eh.selector = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* bitcast (%0* @_ZTI1A to i8*), i8* null) nounwind ; [#uses=1] + %exn.ptr = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* bitcast (%0* @_ZTI1A to i8*) + catch i8* null + %exn = extractvalue { i8*, i32 } %exn.ptr, 0 + %eh.selector = extractvalue { i8*, i32 } %exn.ptr, 1 %2 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (%0* @_ZTI1A to i8*)) nounwind ; [#uses=1] %3 = icmp eq i32 %eh.selector, %2 ; [#uses=1] br i1 %3, label %try.cont, label %eh.resume Modified: llvm/trunk/test/CodeGen/ARM/2010-08-04-EHCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-08-04-EHCrash.ll?rev=144048&r1=144047&r2=144048&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-08-04-EHCrash.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-08-04-EHCrash.ll Mon Nov 7 18:09:27 2011 @@ -34,10 +34,12 @@ ret void lpad: ; preds = %bb - %eh_ptr = call i8* @llvm.eh.exception() ; [#uses=1] - store i8* %eh_ptr, i8** %eh_exception + %eh_ptr = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + cleanup + %exn = extractvalue { i8*, i32 } %eh_ptr, 0 + store i8* %exn, i8** %eh_exception %eh_ptr13 = load i8** %eh_exception ; [#uses=1] - %eh_select14 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %eh_ptr13, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i32 1) + %eh_select14 = extractvalue { i8*, i32 } %eh_ptr, 1 store i32 %eh_select14, i32* %eh_selector br label %ppad @@ -54,10 +56,6 @@ declare arm_apcscc void @_ZSt9terminatev() noreturn nounwind -declare i8* @llvm.eh.exception() nounwind readonly - -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare arm_apcscc void @_Unwind_SjLj_Resume(i8*) declare arm_apcscc void @func3() Modified: llvm/trunk/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll?rev=144048&r1=144047&r2=144048&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll Mon Nov 7 18:09:27 2011 @@ -35,14 +35,14 @@ br label %for.cond lpad: - %exn = tail call i8* @llvm.eh.exception() nounwind - %eh.selector = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + %exn = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* null invoke void @foo() to label %eh.resume unwind label %terminate.lpad lpad26: - %exn27 = tail call i8* @llvm.eh.exception() nounwind - %eh.selector28 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn27, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + %exn27 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* null invoke void @foo() to label %eh.resume unwind label %terminate.lpad @@ -57,31 +57,26 @@ ret void lpad44: - %exn45 = tail call i8* @llvm.eh.exception() nounwind - %eh.selector46 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn45, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + %exn45 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* null invoke void @foo() to label %eh.resume unwind label %terminate.lpad eh.resume: - %exn.slot.0 = phi i8* [ %exn27, %lpad26 ], [ %exn, %lpad ], [ %exn45, %lpad44 ] - tail call void @_Unwind_SjLj_Resume_or_Rethrow(i8* %exn.slot.0) noreturn - unreachable + %exn.slot.0 = phi { i8*, i32 } [ %exn27, %lpad26 ], [ %exn, %lpad ], [ %exn45, %lpad44 ] + resume { i8*, i32 } %exn.slot.0 terminate.lpad: - %exn51 = tail call i8* @llvm.eh.exception() nounwind - %eh.selector52 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn51, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + %exn51 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* null tail call void @_ZSt9terminatev() noreturn nounwind unreachable } declare void @foo() -declare i8* @llvm.eh.exception() nounwind readonly - declare i32 @__gxx_personality_sj0(...) -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare void @_Unwind_SjLj_Resume_or_Rethrow(i8*) declare void @_ZSt9terminatev() Modified: llvm/trunk/test/CodeGen/ARM/eh-resume-darwin.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/eh-resume-darwin.ll?rev=144048&r1=144047&r2=144048&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/eh-resume-darwin.ll (original) +++ llvm/trunk/test/CodeGen/ARM/eh-resume-darwin.ll Mon Nov 7 18:09:27 2011 @@ -3,12 +3,6 @@ declare void @func() -declare i8* @llvm.eh.exception() nounwind readonly - -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - -declare void @llvm.eh.resume(i8*, i32) - declare i32 @__gxx_personality_sj0(...) define void @test0() { @@ -20,10 +14,9 @@ ret void lpad: - %exn = call i8* @llvm.eh.exception() - %sel = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i32 0) - call void @llvm.eh.resume(i8* %exn, i32 %sel) noreturn - unreachable + %exn = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + cleanup + resume { i8*, i32 } %exn } ; CHECK: __Unwind_SjLj_Resume Modified: llvm/trunk/test/CodeGen/X86/no-cfi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/no-cfi.ll?rev=144048&r1=144047&r2=144048&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/no-cfi.ll (original) +++ llvm/trunk/test/CodeGen/X86/no-cfi.ll Mon Nov 7 18:09:27 2011 @@ -24,15 +24,11 @@ ret void lpad: - %exn = call i8* @llvm.eh.exception() nounwind - %eh.selector = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* null) nounwind + %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0 + catch i8* null ret void } declare i32 @foo() -declare i8* @llvm.eh.exception() nounwind readonly - declare i32 @__gxx_personality_v0(...) - -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind From isanbard at gmail.com Mon Nov 7 18:17:28 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 08 Nov 2011 00:17:28 -0000 Subject: [llvm-commits] [llvm] r144049 - in /llvm/trunk/test/CodeGen/X86: 2007-05-05-Personality.ll 2010-04-30-LocalAlloc-LandingPad.ll 2010-08-04-MingWCrash.ll Message-ID: <20111108001728.91A422A6C12C@llvm.org> Author: void Date: Mon Nov 7 18:17:28 2011 New Revision: 144049 URL: http://llvm.org/viewvc/llvm-project?rev=144049&view=rev Log: Convert to the new EH model. Modified: llvm/trunk/test/CodeGen/X86/2007-05-05-Personality.ll llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll llvm/trunk/test/CodeGen/X86/2010-08-04-MingWCrash.ll Modified: llvm/trunk/test/CodeGen/X86/2007-05-05-Personality.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-05-05-Personality.ll?rev=144049&r1=144048&r2=144049&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2007-05-05-Personality.ll (original) +++ llvm/trunk/test/CodeGen/X86/2007-05-05-Personality.ll Mon Nov 7 18:17:28 2011 @@ -10,9 +10,10 @@ invoke void @raise() to label %eh_then unwind label %unwind -unwind: ; preds = %entry - %eh_ptr = tail call i8* @llvm.eh.exception() - %eh_select = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %eh_ptr, i8* bitcast (i32 (...)* @__gnat_eh_personality to i8*), i8* @error) +unwind: ; preds = %entry + %eh_ptr = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gnat_eh_personality to i8*) + catch i8* @error + %eh_select = extractvalue { i8*, i32 } %eh_ptr, 1 %eh_typeid = tail call i32 @llvm.eh.typeid.for(i8* @error) %tmp2 = icmp eq i32 %eh_select, %eh_typeid br i1 %tmp2, label %eh_then, label %Unwind @@ -21,16 +22,11 @@ ret void Unwind: ; preds = %unwind - %0 = tail call i32 (...)* @_Unwind_Resume(i8* %eh_ptr) - unreachable + resume { i8*, i32 } %eh_ptr } declare void @raise() -declare i8* @llvm.eh.exception() nounwind readonly - -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare i32 @llvm.eh.typeid.for(i8*) nounwind declare i32 @__gnat_eh_personality(...) Modified: llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll?rev=144049&r1=144048&r2=144049&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll Mon Nov 7 18:17:28 2011 @@ -30,14 +30,16 @@ br label %finally terminate.handler: ; preds = %match.end - %exc = call i8* @llvm.eh.exception() ; [#uses=1] - %1 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 1) ; [#uses=0] + %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup call void @_ZSt9terminatev() noreturn nounwind unreachable try.handler: ; preds = %entry - %exc1 = call i8* @llvm.eh.exception() ; [#uses=3] - %selector = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc1, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTIi to i8*), i8* null) ; [#uses=1] + %exc1.ptr = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + %exc1 = extractvalue { i8*, i32 } %exc1.ptr, 0 + %selector = extractvalue { i8*, i32 } %exc1.ptr, 1 %2 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) ; [#uses=1] %3 = icmp eq i32 %selector, %2 ; [#uses=1] br i1 %3, label %match, label %catch.next @@ -55,9 +57,10 @@ br label %match.end match.handler: ; preds = %match - %exc3 = call i8* @llvm.eh.exception() ; [#uses=2] - %7 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc3, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 0) ; [#uses=0] - store i8* %exc3, i8** %_rethrow + %exc3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + %7 = extractvalue { i8*, i32 } %exc3, 0 + store i8* %7, i8** %_rethrow store i32 2, i32* %cleanup.dst br label %match.end @@ -124,10 +127,6 @@ declare i32 @__gxx_personality_v0(...) -declare i8* @llvm.eh.exception() nounwind readonly - -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare void @_ZSt9terminatev() declare void @_Unwind_Resume_or_Rethrow(i8*) Modified: llvm/trunk/test/CodeGen/X86/2010-08-04-MingWCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-08-04-MingWCrash.ll?rev=144049&r1=144048&r2=144049&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-08-04-MingWCrash.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-08-04-MingWCrash.ll Mon Nov 7 18:17:28 2011 @@ -10,14 +10,15 @@ ret void lpad: - %exn = tail call i8* @llvm.eh.exception() nounwind - %eh.selector = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 1, i8* null) nounwind + %exn.ptr = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + %exn = extractvalue { i8*, i32 } %exn.ptr, 0 + %eh.selector = extractvalue { i8*, i32 } %exn.ptr, 1 %ehspec.fails = icmp slt i32 %eh.selector, 0 br i1 %ehspec.fails, label %ehspec.unexpected, label %cleanup cleanup: - tail call void @_Unwind_Resume_or_Rethrow(i8* %exn) noreturn nounwind - unreachable + resume { i8*, i32 } %exn.ptr ehspec.unexpected: tail call void @__cxa_call_unexpected(i8* %exn) noreturn nounwind @@ -26,12 +27,8 @@ declare noalias i8* @malloc() -declare i8* @llvm.eh.exception() nounwind readonly - declare i32 @__gxx_personality_v0(...) -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare void @_Unwind_Resume_or_Rethrow(i8*) declare void @__cxa_call_unexpected(i8*) From isanbard at gmail.com Mon Nov 7 18:23:02 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 08 Nov 2011 00:23:02 -0000 Subject: [llvm-commits] [llvm] r144050 - in /llvm/trunk/test/Transforms: InstCombine/crash.ll MergeFunc/2011-02-08-RemoveEqual.ll Message-ID: <20111108002302.2459F2A6C12C@llvm.org> Author: void Date: Mon Nov 7 18:23:01 2011 New Revision: 144050 URL: http://llvm.org/viewvc/llvm-project?rev=144050&view=rev Log: Convert to the new EH model. Modified: llvm/trunk/test/Transforms/InstCombine/crash.ll llvm/trunk/test/Transforms/MergeFunc/2011-02-08-RemoveEqual.ll Modified: llvm/trunk/test/Transforms/InstCombine/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/crash.ll?rev=144050&r1=144049&r2=144050&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/crash.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/crash.ll Mon Nov 7 18:23:01 2011 @@ -165,20 +165,19 @@ br i1 %tobool, label %cond.end, label %cond.false terminate.handler: ; preds = %ehcleanup - %exc = call i8* @llvm.eh.exception() ; [#uses=1] - %0 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 1) ; [#uses=0] + %exc = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup call void @_ZSt9terminatev() noreturn nounwind unreachable ehcleanup: ; preds = %cond.false - %exc1 = call i8* @llvm.eh.exception() ; [#uses=2] - %1 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc1, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* null) ; [#uses=0] + %exc1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null invoke void @_ZN6UStackD1Ev(%class.UStack* %breaks) to label %cont unwind label %terminate.handler cont: ; preds = %ehcleanup - call void @_Unwind_Resume_or_Rethrow(i8* %exc1) - unreachable + resume { i8*, i32 } %exc1 cond.false: ; preds = %entry %tmp4 = getelementptr inbounds %class.RuleBasedBreakIterator* %this, i32 0, i32 0 ; [#uses=1] @@ -199,10 +198,6 @@ declare i32 @__gxx_personality_v0(...) -declare i8* @llvm.eh.exception() nounwind readonly - -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare void @_ZSt9terminatev() declare void @_Unwind_Resume_or_Rethrow(i8*) Modified: llvm/trunk/test/Transforms/MergeFunc/2011-02-08-RemoveEqual.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/MergeFunc/2011-02-08-RemoveEqual.ll?rev=144050&r1=144049&r2=144050&view=diff ============================================================================== --- llvm/trunk/test/Transforms/MergeFunc/2011-02-08-RemoveEqual.ll (original) +++ llvm/trunk/test/Transforms/MergeFunc/2011-02-08-RemoveEqual.ll Mon Nov 7 18:23:01 2011 @@ -75,10 +75,12 @@ ret void lpad: ; preds = %bb - %eh_ptr = call i8* @llvm.eh.exception() - store i8* %eh_ptr, i8** %eh_exception + %eh_ptr = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + %exn = extractvalue { i8*, i32 } %eh_ptr, 0 + store i8* %exn, i8** %eh_exception %eh_ptr4 = load i8** %eh_exception - %eh_select5 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %eh_ptr4, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 0) + %eh_select5 = extractvalue { i8*, i32 } %eh_ptr, 1 store i32 %eh_select5, i32* %eh_selector %eh_select = load i32* %eh_selector store i32 %eh_select, i32* %save_filt.150, align 4 @@ -199,10 +201,12 @@ ret void lpad: ; preds = %bb - %eh_ptr = call i8* @llvm.eh.exception() - store i8* %eh_ptr, i8** %eh_exception + %eh_ptr = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + %exn = extractvalue { i8*, i32 } %eh_ptr, 0 + store i8* %exn, i8** %eh_exception %eh_ptr4 = load i8** %eh_exception - %eh_select5 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %eh_ptr4, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 0) + %eh_select5 = extractvalue { i8*, i32 } %eh_ptr, 1 store i32 %eh_select5, i32* %eh_selector %eh_select = load i32* %eh_selector store i32 %eh_select, i32* %save_filt.148, align 4 @@ -220,10 +224,6 @@ unreachable } -declare i8* @llvm.eh.exception() nounwind readonly - -declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind - declare i32 @__gxx_personality_v0(...) declare void @_Unwind_Resume_or_Rethrow() From evan.cheng at apple.com Mon Nov 7 18:31:58 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 08 Nov 2011 00:31:58 -0000 Subject: [llvm-commits] [llvm] r144052 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_shuffle-38.ll test/CodeGen/X86/vec_shuffle-39.ll Message-ID: <20111108003158.90F222A6C12C@llvm.org> Author: evancheng Date: Mon Nov 7 18:31:58 2011 New Revision: 144052 URL: http://llvm.org/viewvc/llvm-project?rev=144052&view=rev Log: Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222 Added: llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144052&r1=144051&r2=144052&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Nov 7 18:31:58 2011 @@ -6190,6 +6190,10 @@ V = V.getOperand(0); if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) V = V.getOperand(0); + if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && + V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) + // BUILD_VECTOR (load), undef + V = V.getOperand(0); if (MayFoldLoad(V)) return true; return false; @@ -6372,15 +6376,10 @@ // turns into: // (MOVLPSmr addr:$src1, VR128:$src2) // So, recognize this potential and also use MOVLPS or MOVLPD - if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) + else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) CanFoldLoad = true; ShuffleVectorSDNode *SVOp = cast(Op); - - // Both of them can't be memory operations though. - if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2)) - CanFoldLoad = false; - if (CanFoldLoad) { if (HasXMMInt && NumElems == 2) return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144052&r1=144051&r2=144052&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Nov 7 18:31:58 2011 @@ -1035,6 +1035,9 @@ } // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS + def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)), + (iPTR 0))), addr:$src1), + (MOVLPSmr addr:$src1, VR128:$src2)>; def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1), (MOVLPSmr addr:$src1, VR128:$src2)>; def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), @@ -1049,6 +1052,9 @@ def : Pat<(X86Movlps VR128:$src1, (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), (MOVLPSrm VR128:$src1, addr:$src2)>; + def : Pat<(X86Movlps VR128:$src1, + (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))), + (MOVLPSrm VR128:$src1, addr:$src2)>; // Store patterns def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll?rev=144052&r1=144051&r2=144052&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll Mon Nov 7 18:31:58 2011 @@ -48,8 +48,7 @@ ; CHECK: f define <4 x float> @f(<4 x float> %x, double* nocapture %y) nounwind uwtable readonly ssp { entry: - ; CHECK: movsd (% - ; CHECK-NEXT: movsd %xmm + ; CHECK: movlps (%rdi), %xmm0 %u110.i = load double* %y, align 1 %tmp8.i = insertelement <2 x double> undef, double %u110.i, i32 0 %tmp9.i = bitcast <2 x double> %tmp8.i to <4 x float> Added: llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll?rev=144052&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll (added) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll Mon Nov 7 18:31:58 2011 @@ -0,0 +1,51 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; rdar://10050222, rdar://10134392 + +define <4 x float> @t1(<4 x float> %a, <1 x i64>* nocapture %p) nounwind { +entry: +; CHECK: t1: +; CHECK: movlps (%rdi), %xmm0 +; CHECK: ret + %p.val = load <1 x i64>* %p, align 1 + %0 = bitcast <1 x i64> %p.val to <2 x float> + %shuffle.i = shufflevector <2 x float> %0, <2 x float> undef, <4 x i32> + %shuffle1.i = shufflevector <4 x float> %a, <4 x float> %shuffle.i, <4 x i32> + ret <4 x float> %shuffle1.i +} + +define <4 x float> @t1a(<4 x float> %a, <1 x i64>* nocapture %p) nounwind { +entry: +; CHECK: t1a: +; CHECK: movlps (%rdi), %xmm0 +; CHECK: ret + %0 = bitcast <1 x i64>* %p to double* + %1 = load double* %0 + %2 = insertelement <2 x double> undef, double %1, i32 0 + %3 = bitcast <2 x double> %2 to <4 x float> + %4 = shufflevector <4 x float> %a, <4 x float> %3, <4 x i32> + ret <4 x float> %4 +} + +define void @t2(<1 x i64>* nocapture %p, <4 x float> %a) nounwind { +entry: +; CHECK: t2: +; CHECK: movlps %xmm0, (%rdi) +; CHECK: ret + %cast.i = bitcast <4 x float> %a to <2 x i64> + %extract.i = extractelement <2 x i64> %cast.i, i32 0 + %0 = getelementptr inbounds <1 x i64>* %p, i64 0, i64 0 + store i64 %extract.i, i64* %0, align 8 + ret void +} + +define void @t2a(<1 x i64>* nocapture %p, <4 x float> %a) nounwind { +entry: +; CHECK: t2a: +; CHECK: movlps %xmm0, (%rdi) +; CHECK: ret + %0 = bitcast <1 x i64>* %p to double* + %1 = bitcast <4 x float> %a to <2 x double> + %2 = extractelement <2 x double> %1, i32 0 + store double %2, double* %0 + ret void +} From isanbard at gmail.com Mon Nov 7 18:32:45 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 08 Nov 2011 00:32:45 -0000 Subject: [llvm-commits] [llvm] r144053 - /llvm/trunk/docs/LangRef.html Message-ID: <20111108003245.F29862A6C12C@llvm.org> Author: void Date: Mon Nov 7 18:32:45 2011 New Revision: 144053 URL: http://llvm.org/viewvc/llvm-project?rev=144053&view=rev Log: Cleanup the formatting. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=144053&r1=144052&r2=144053&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Nov 7 18:32:45 2011 @@ -3023,26 +3023,29 @@ pointers to global variables and functions which may optionally have a pointer cast formed of bitcast or getelementptr. For example, a legal use of it is:

+
-  @X = global i8 4
-  @Y = global i32 123
+ at X = global i8 4
+ at Y = global i32 123
 
-  @llvm.used = appending global [2 x i8*] [
-     i8* @X,
-     i8* bitcast (i32* @Y to i8*)
-  ], section "llvm.metadata"
+ at llvm.used = appending global [2 x i8*] [
+   i8* @X,
+   i8* bitcast (i32* @Y to i8*)
+], section "llvm.metadata"
+

If a global variable appears in the @llvm.used list, then the -compiler, assembler, and linker are required to treat the symbol as if there is -a reference to the global that it cannot see. For example, if a variable has -internal linkage and no references other than that from the @llvm.used -list, it cannot be deleted. This is commonly used to represent references from -inline asms and other things the compiler cannot "see", and corresponds to -"attribute((used))" in GNU C.

+ compiler, assembler, and linker are required to treat the symbol as if there + is a reference to the global that it cannot see. For example, if a variable + has internal linkage and no references other than that from + the @llvm.used list, it cannot be deleted. This is commonly used to + represent references from inline asms and other things the compiler cannot + "see", and corresponds to "attribute((used))" in GNU C.

On some targets, the code generator must emit a directive to the assembler or -object file to prevent the assembler and linker from molesting the symbol.

+ object file to prevent the assembler and linker from molesting the + symbol.

@@ -3056,13 +3059,13 @@

The @llvm.compiler.used directive is the same as the -@llvm.used directive, except that it only prevents the compiler from -touching the symbol. On targets that support it, this allows an intelligent -linker to optimize references to the symbol without being impeded as it would be -by @llvm.used.

+ @llvm.used directive, except that it only prevents the compiler from + touching the symbol. On targets that support it, this allows an intelligent + linker to optimize references to the symbol without being impeded as it would + be by @llvm.used.

This is a rare construct that should only be used in rare circumstances, and -should not be exposed to source languages.

+ should not be exposed to source languages.

@@ -3072,12 +3075,19 @@
+ +
 %0 = type { i32, void ()* }
 @llvm.global_ctors = appending global [1 x %0] [%0 { i32 65535, void ()* @ctor }]
-

The @llvm.global_ctors array contains a list of constructor functions and associated priorities. The functions referenced by this array will be called in ascending order of priority (i.e. lowest first) when the module is loaded. The order of functions with the same priority is not defined. -

+
+ +

The @llvm.global_ctors array contains a list of constructor + functions and associated priorities. The functions referenced by this array + will be called in ascending order of priority (i.e. lowest first) when the + module is loaded. The order of functions with the same priority is not + defined.

@@ -3087,13 +3097,18 @@
+ +
 %0 = type { i32, void ()* }
 @llvm.global_dtors = appending global [1 x %0] [%0 { i32 65535, void ()* @dtor }]
+
-

The @llvm.global_dtors array contains a list of destructor functions and associated priorities. The functions referenced by this array will be called in descending order of priority (i.e. highest first) when the module is loaded. The order of functions with the same priority is not defined. -

+

The @llvm.global_dtors array contains a list of destructor functions + and associated priorities. The functions referenced by this array will be + called in descending order of priority (i.e. highest first) when the module + is loaded. The order of functions with the same priority is not defined.

From lhames at gmail.com Mon Nov 7 19:09:17 2011 From: lhames at gmail.com (Lang Hames) Date: Mon, 7 Nov 2011 17:09:17 -0800 Subject: [llvm-commits] [PATCH] Smarter unaligned stores of constant values. In-Reply-To: References: Message-ID: Ok - this patch adds a ISD::Constant case to GetDemandedBits. I went for this over SimplifyDemandedBits, since the latter expects single-use operands, and the aim here is to re-use the constant. The effect on the test case from the first email is the same. Please let me know what you think. Cheers, Lang. On Fri, Nov 4, 2011 at 4:58 PM, Lang Hames wrote: > Thanks Eli! Looking into SimplifyDemandedBits now... > > Cheers, > Lang. > > On Fri, Nov 4, 2011 at 4:41 PM, Eli Friedman wrote: > >> On Fri, Nov 4, 2011 at 4:30 PM, Lang Hames wrote: >> > Encountered the following when I tried outputting an unaligned store of >> -1 >> > on ARM: >> > _foo: @ @foo >> > @ BB#0: @ %entry >> > mov r1, #255 >> > mov r2, #255 >> > strb r1, [r0, #3] >> > orr r1, r2, #65280 >> > strb r1, [r0, #2] >> > mvn r1, #-16777216 >> > strb r1, [r0, #1] >> > mvn r1, #0 >> > strb r1, [r0] >> > mov pc, lr >> > The strange constants are coming out of the legalizer, which tries to >> > legalize the unaligned store by repeatedly splitting it into two >> half-sized >> > stores, and shifting the constant around. This results in several new >> and >> > confusing constants being introduced. >> > This patch checks for constant value stores, and if the two halves of >> the >> > constant have the same bit-pattern it avoids creating new constants. >> > Could someone who's more familiar with the legalizer take a look and >> let me >> > know if this is Ok to commit? (I'm also planning to enable unaligned >> stores >> > on supported subtargets, but that's a different issue) >> >> TargetLowering::SimplifyDemandedBits should be able to take care of >> this; if it can't, it should be fixed. >> >> -Eli >> > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111107/54a6a18e/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: dagcombiner.patch Type: application/octet-stream Size: 848 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111107/54a6a18e/attachment.obj From eli.friedman at gmail.com Mon Nov 7 19:25:24 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 08 Nov 2011 01:25:24 -0000 Subject: [llvm-commits] [llvm] r144055 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll Message-ID: <20111108012525.140002A6C12C@llvm.org> Author: efriedma Date: Mon Nov 7 19:25:24 2011 New Revision: 144055 URL: http://llvm.org/viewvc/llvm-project?rev=144055&view=rev Log: Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization doesn't get confused by CSE later on. Fixes PR11318. Re-commit of r144034, with an extra fix so that RemoveDeadNode doesn't blow up. Added: llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll - copied unchanged from r144043, llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=144055&r1=144054&r2=144055&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 7 19:25:24 2011 @@ -285,6 +285,7 @@ Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), ST->isVolatile(), ST->isNonTemporal(), Alignment); DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); + DAG.RemoveDeadNode(ST, DUL); return; } // Do a (aligned) store to a stack slot, then copy from the stack slot @@ -349,6 +350,7 @@ DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], Stores.size()); DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); + DAG.RemoveDeadNode(ST, DUL); return; } assert(ST->getMemoryVT().isInteger() && @@ -381,6 +383,7 @@ SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); + DAG.RemoveDeadNode(ST, DUL); } /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. @@ -1144,6 +1147,7 @@ if (!ST->isTruncatingStore()) { if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { DAG.ReplaceAllUsesWith(ST, OptStore, this); + DAG.RemoveDeadNode(ST, this); break; } @@ -1169,8 +1173,10 @@ break; case TargetLowering::Custom: Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG); - if (Tmp1.getNode()) + if (Tmp1.getNode()) { DAG.ReplaceAllUsesWith(SDValue(Node, 0), Tmp1, this); + DAG.RemoveDeadNode(Node, this); + } break; case TargetLowering::Promote: { assert(VT.isVector() && "Unknown legal promote case!"); @@ -1181,6 +1187,7 @@ ST->getPointerInfo(), isVolatile, isNonTemporal, Alignment); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); + DAG.RemoveDeadNode(Node, this); break; } } @@ -1203,6 +1210,7 @@ DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), NVT, isVolatile, isNonTemporal, Alignment); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); + DAG.RemoveDeadNode(Node, this); } else if (StWidth & (StWidth - 1)) { // If not storing a power-of-2 number of bits, expand as two stores. assert(!StVT.isVector() && "Unsupported truncstore!"); @@ -1258,6 +1266,7 @@ // The order of the stores doesn't matter. SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); + DAG.RemoveDeadNode(Node, this); } else { if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || Tmp2 != ST->getBasePtr()) @@ -1280,6 +1289,7 @@ DAG.ReplaceAllUsesWith(SDValue(Node, 0), TLI.LowerOperation(SDValue(Node, 0), DAG), this); + DAG.RemoveDeadNode(Node, this); break; case TargetLowering::Expand: assert(!StVT.isVector() && @@ -1292,6 +1302,7 @@ DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), isVolatile, isNonTemporal, Alignment); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); + DAG.RemoveDeadNode(Node, this); break; } } @@ -3361,6 +3372,7 @@ DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), &Scalars[0], Scalars.size()); DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); + DAG.RemoveDeadNode(Node, this); break; } case ISD::GLOBAL_OFFSET_TABLE: @@ -3377,8 +3389,10 @@ } // Replace the original node with the legalized result. - if (!Results.empty()) + if (!Results.empty()) { DAG.ReplaceAllUsesWith(Node, Results.data(), this); + DAG.RemoveDeadNode(Node, this); + } } void SelectionDAGLegalize::PromoteNode(SDNode *Node) { @@ -3512,8 +3526,10 @@ } // Replace the original node with the legalized result. - if (!Results.empty()) + if (!Results.empty()) { DAG.ReplaceAllUsesWith(Node, Results.data(), this); + DAG.RemoveDeadNode(Node, this); + } } // SelectionDAG::Legalize - This is the entry point for the file. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=144055&r1=144054&r2=144055&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Nov 7 19:25:24 2011 @@ -564,6 +564,12 @@ void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ SmallVector DeadNodes(1, N); + + // Create a dummy node that adds a reference to the root node, preventing + // it from being deleted. (This matters if the root is an operand of the + // dead node.) + HandleSDNode Dummy(getRoot()); + RemoveDeadNodes(DeadNodes, UpdateListener); } From eli.friedman at gmail.com Mon Nov 7 19:43:53 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 08 Nov 2011 01:43:53 -0000 Subject: [llvm-commits] [llvm] r144057 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll Message-ID: <20111108014353.9E7152A6C12C@llvm.org> Author: efriedma Date: Mon Nov 7 19:43:53 2011 New Revision: 144057 URL: http://llvm.org/viewvc/llvm-project?rev=144057&view=rev Log: Make sure to mark vector extload's as expand on ARM. Fixes PR11319. Added: llvm/trunk/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=144057&r1=144056&r2=144057&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Nov 7 19:43:53 2011 @@ -126,14 +126,7 @@ setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); - setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); - setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); - for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; - InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) - setTruncStoreAction(VT.getSimpleVT(), - (MVT::SimpleValueType)InnerVT, Expand); } - setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); // Promote all bit-wise operations. if (VT.isInteger() && VT != PromotedBitwiseVT) { @@ -442,6 +435,17 @@ setTruncStoreAction(MVT::f64, MVT::f32, Expand); } + for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; + VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { + for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; + InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) + setTruncStoreAction((MVT::SimpleValueType)VT, + (MVT::SimpleValueType)InnerVT, Expand); + setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); + setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); + setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); + } + if (Subtarget->hasNEON()) { addDRTypeForNEON(MVT::v2f32); addDRTypeForNEON(MVT::v8i8); @@ -483,8 +487,6 @@ setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); - setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); - // Neon does not support some operations on v1i64 and v2i64 types. setOperationAction(ISD::MUL, MVT::v1i64, Expand); // Custom handling for some quad-vector types to detect VMULL. Added: llvm/trunk/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll?rev=144057&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll Mon Nov 7 19:43:53 2011 @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; PR11319 + + at i8_res = global <2 x i8> + at i8_src1 = global <2 x i8> + at i8_src2 = global <2 x i8> + +define void @test_neon_vector_add_2xi8() nounwind { +; CHECK: test_neon_vector_add_2xi8: + %1 = load <2 x i8>* @i8_src1 + %2 = load <2 x i8>* @i8_src2 + %3 = add <2 x i8> %1, %2 + store <2 x i8> %3, <2 x i8>* @i8_res + ret void +} From peter_cooper at apple.com Mon Nov 7 20:27:19 2011 From: peter_cooper at apple.com (Peter Cooper) Date: Mon, 07 Nov 2011 18:27:19 -0800 Subject: [llvm-commits] LoadSDNode invariance In-Reply-To: References: <72DEEAEF-7CA4-45AF-9286-0ADD7082EB96@apple.com> <0CD49991-E497-4531-8554-E9168E566EB4@apple.com> Message-ID: I've made the changes to add invariance to the getLoad method and all the calls. There were more calls than i realized, but its an easy change to make to other backends. -------------- next part -------------- A non-text attachment was scrubbed... Name: 6027699.patch Type: application/octet-stream Size: 91368 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111107/b4158905/attachment-0001.obj -------------- next part -------------- Attached the patch for review. The optimizer changes to LICM will follow in a separate patch once this refactoring one is committed. Pete On Nov 4, 2011, at 1:52 PM, Peter Cooper wrote: > I'm happy doing that. Hopefully it doesn't end up as too many changes for people with their own backends. > > Pete > > On Nov 4, 2011, at 1:44 PM, Evan Cheng wrote: > >> >> On Nov 4, 2011, at 11:56 AM, Peter Cooper wrote: >> >>> Hi >>> >>> I've added new metadata to load IR instructions to say if they are invariant, i.e., don't change at runtime. >>> >>> The IR change was simple but i'm not sure about the MachineInstr/DAG level. I've attached the change which encodes the invariant flag in the MemSDNodeFlags next to the volatile flag. >>> >>> Please have a look and tell me if this is ideal? The main thing i wasn't happy doing was adding another DAG.getLoad method with the invariant flag, but the alternative was changing the existing method which would lead to changing dozens of calls. >> >> If it's only dozens of calls, then I vote for changing the existing method. >> >> Evan >> >>> >>> Thanks, >>> Pete >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From geek4civic at gmail.com Mon Nov 7 21:46:25 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 08 Nov 2011 03:46:25 -0000 Subject: [llvm-commits] [llvm] r144066 - /llvm/trunk/test/CodeGen/X86/vec_shuffle.ll Message-ID: <20111108034625.ECB742A6C12C@llvm.org> Author: chapuni Date: Mon Nov 7 21:46:25 2011 New Revision: 144066 URL: http://llvm.org/viewvc/llvm-project?rev=144066&view=rev Log: test/CodeGen/X86/vec_shuffle.ll: Add explicit -mtriple=i686-linux. We may see some suboptimal frame (%ebp) emission on certain hosts. Possible [PR11031] Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle.ll Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle.ll?rev=144066&r1=144065&r2=144066&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle.ll Mon Nov 7 21:46:25 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s +; RUN: llc < %s -mtriple=i686-linux -mcpu=core2 | FileCheck %s ; CHECK: test_v4sf ; CHECK: movq 8(%esp) From geek4civic at gmail.com Mon Nov 7 21:46:33 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 08 Nov 2011 03:46:33 -0000 Subject: [llvm-commits] [llvm] r144067 - /llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll Message-ID: <20111108034633.15CC72A6C12C@llvm.org> Author: chapuni Date: Mon Nov 7 21:46:32 2011 New Revision: 144067 URL: http://llvm.org/viewvc/llvm-project?rev=144067&view=rev Log: test/CodeGen/X86/vec_shuffle-38.ll: Relax expression for Win32 x64. Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll?rev=144067&r1=144066&r2=144067&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-38.ll Mon Nov 7 21:46:32 2011 @@ -48,7 +48,7 @@ ; CHECK: f define <4 x float> @f(<4 x float> %x, double* nocapture %y) nounwind uwtable readonly ssp { entry: - ; CHECK: movlps (%rdi), %xmm0 + ; CHECK: movlps (%{{rdi|rdx}}), %xmm0 %u110.i = load double* %y, align 1 %tmp8.i = insertelement <2 x double> undef, double %u110.i, i32 0 %tmp9.i = bitcast <2 x double> %tmp8.i to <4 x float> From geek4civic at gmail.com Mon Nov 7 21:46:40 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 08 Nov 2011 03:46:40 -0000 Subject: [llvm-commits] [llvm] r144068 - /llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll Message-ID: <20111108034640.1AB8E2A6C12C@llvm.org> Author: chapuni Date: Mon Nov 7 21:46:39 2011 New Revision: 144068 URL: http://llvm.org/viewvc/llvm-project?rev=144068&view=rev Log: test/CodeGen/X86/vec_shuffle-39.ll: Add explicit -mtriple=x86_64-linux. Passing packed value is not compatible on Win32 x64. Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll?rev=144068&r1=144067&r2=144068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll Mon Nov 7 21:46:39 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s ; rdar://10050222, rdar://10134392 define <4 x float> @t1(<4 x float> %a, <1 x i64>* nocapture %p) nounwind { From geek4civic at gmail.com Mon Nov 7 21:54:40 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 08 Nov 2011 03:54:40 -0000 Subject: [llvm-commits] [llvm] r144070 - /llvm/trunk/runtime/libprofile/PathProfiling.c Message-ID: <20111108035440.793A22A6C12C@llvm.org> Author: chapuni Date: Mon Nov 7 21:54:40 2011 New Revision: 144070 URL: http://llvm.org/viewvc/llvm-project?rev=144070&view=rev Log: runtime/libprofile/PathProfiling.c: Use __inline__ to appease clang -std=gnu89 -pedantic. FIXME: Should configure detect one? Modified: llvm/trunk/runtime/libprofile/PathProfiling.c Modified: llvm/trunk/runtime/libprofile/PathProfiling.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/runtime/libprofile/PathProfiling.c?rev=144070&r1=144069&r2=144070&view=diff ============================================================================== --- llvm/trunk/runtime/libprofile/PathProfiling.c (original) +++ llvm/trunk/runtime/libprofile/PathProfiling.c Mon Nov 7 21:54:40 2011 @@ -28,7 +28,7 @@ /* Must use __inline in Microsoft C */ #if defined(_MSC_VER) -#define inline __inline +#define __inline__ __inline #endif /* note that this is used for functions with large path counts, @@ -112,7 +112,7 @@ } } -static inline uint32_t hash (uint32_t key) { +static __inline__ uint32_t hash (uint32_t key) { /* this may benefit from a proper hash function */ return key%ARBITRARY_HASH_BIN_COUNT; } @@ -155,7 +155,7 @@ } /* Return a pointer to this path's specific path counter */ -static inline uint32_t* getPathCounter(uint32_t functionNumber, +static __inline__ uint32_t* getPathCounter(uint32_t functionNumber, uint32_t pathNumber) { pathHashTable_t* hashTable; pathHashEntry_t* hashEntry; From geek4civic at gmail.com Mon Nov 7 22:00:08 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 08 Nov 2011 04:00:08 -0000 Subject: [llvm-commits] [llvm] r144071 - /llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Message-ID: <20111108040008.15AB72A6C12C@llvm.org> Author: chapuni Date: Mon Nov 7 22:00:07 2011 New Revision: 144071 URL: http://llvm.org/viewvc/llvm-project?rev=144071&view=rev Log: PPCInstrInfo.cpp: Fix one "unused" warning. Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=144071&r1=144070&r2=144071&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Nov 7 22:00:07 2011 @@ -52,6 +52,7 @@ // Should use subtarget info to pick the right hazard recognizer. For // now, always return a PPC970 recognizer. const TargetInstrInfo *TII = TM->getInstrInfo(); + (void)TII; assert(TII && "No InstrInfo?"); unsigned Directive = TM->getSubtarget().getDarwinDirective(); From eli.friedman at gmail.com Mon Nov 7 22:11:17 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 7 Nov 2011 20:11:17 -0800 Subject: [llvm-commits] [PATCH-WIP] Fix for PR11305; need TableGen advice Message-ID: WIP patch to fix PR11305 attached. TableGen is exploding with the following assertion: Assertion failed: (Ops.size() >= NumSrcResults && "Didn't provide enough results"), function EmitResultCode, file /Volumes/storage/llvm/utils/TableGen/DAGISelMatcherGen.cpp, line 917. Any suggestions? I think this has something to do with the constructs like "[(set ECX, EFLAGS, (X86pcmpistri"... -Eli -------------- next part -------------- Index: X86InstrInfo.td =================================================================== --- X86InstrInfo.td (revision 144056) +++ X86InstrInfo.td (working copy) @@ -106,6 +106,20 @@ def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>; +def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, + SDTCisVT<1, i32>, + SDTCisVT<2, v16i8>, + SDTCisVT<3, v16i8>, + SDTCisVT<4, i8>]>; +def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, + SDTCisVT<1, i32>, + SDTCisVT<2, v16i8>, + SDTCisVT<3, i32>, + SDTCisVT<4, v16i8>, + SDTCisVT<5, i32>, + SDTCisVT<6, i8>]>; + + def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, [SDNPHasChain]>; def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE, @@ -241,6 +255,9 @@ def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; +def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>; +def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>; + //===----------------------------------------------------------------------===// // X86 Operand Definitions. // Index: X86ISelLowering.cpp =================================================================== --- X86ISelLowering.cpp (revision 144056) +++ X86ISelLowering.cpp (working copy) @@ -9589,7 +9589,83 @@ DAG.getConstant(NewIntNo, MVT::i32), Op.getOperand(1), ShAmt); } + case Intrinsic::x86_sse42_pcmpistria128: + case Intrinsic::x86_sse42_pcmpestria128: + case Intrinsic::x86_sse42_pcmpistric128: + case Intrinsic::x86_sse42_pcmpestric128: + case Intrinsic::x86_sse42_pcmpistrio128: + case Intrinsic::x86_sse42_pcmpestrio128: + case Intrinsic::x86_sse42_pcmpistris128: + case Intrinsic::x86_sse42_pcmpestris128: + case Intrinsic::x86_sse42_pcmpistriz128: + case Intrinsic::x86_sse42_pcmpestriz128: + { + unsigned Opcode = 0; + unsigned X86CC = 0; + switch (IntNo) { + case Intrinsic::x86_sse42_pcmpistria128: + Opcode = X86ISD::PCMPISTRI; + X86CC = X86::COND_A; + break; + case Intrinsic::x86_sse42_pcmpestria128: + Opcode = X86ISD::PCMPESTRI; + X86CC = X86::COND_A; + break; + case Intrinsic::x86_sse42_pcmpistric128: + Opcode = X86ISD::PCMPISTRI; + X86CC = X86::COND_B; + break; + case Intrinsic::x86_sse42_pcmpestric128: + Opcode = X86ISD::PCMPESTRI; + X86CC = X86::COND_B; + break; + case Intrinsic::x86_sse42_pcmpistrio128: + Opcode = X86ISD::PCMPISTRI; + X86CC = X86::COND_O; + break; + case Intrinsic::x86_sse42_pcmpestrio128: + Opcode = X86ISD::PCMPESTRI; + X86CC = X86::COND_O; + break; + case Intrinsic::x86_sse42_pcmpistris128: + Opcode = X86ISD::PCMPISTRI; + X86CC = X86::COND_S; + break; + case Intrinsic::x86_sse42_pcmpestris128: + Opcode = X86ISD::PCMPESTRI; + X86CC = X86::COND_S; + break; + case Intrinsic::x86_sse42_pcmpistriz128: + Opcode = X86ISD::PCMPISTRI; + X86CC = X86::COND_E; + break; + case Intrinsic::x86_sse42_pcmpestriz128: + Opcode = X86ISD::PCMPESTRI; + X86CC = X86::COND_E; + break; + } + SmallVector NewOps; + NewOps.append(Op->op_begin()+1, Op->op_end()); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); + SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size()); + SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, + DAG.getConstant(X86CC, MVT::i8), PCMP); + return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); } + case Intrinsic::x86_sse42_pcmpistri128: + case Intrinsic::x86_sse42_pcmpestri128: { + unsigned Opcode; + if (IntNo == Intrinsic::x86_sse42_pcmpistri128) + Opcode = X86ISD::PCMPISTRI; + else + Opcode = X86ISD::PCMPESTRI; + + SmallVector NewOps; + NewOps.append(Op->op_begin()+1, Op->op_end()); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); + return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size()); + } + } } SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, Index: X86InstrSSE.td =================================================================== --- X86InstrSSE.td (revision 144056) +++ X86InstrSSE.td (working copy) @@ -6734,81 +6734,44 @@ // Packed Compare Implicit Length Strings, Return Index let Defs = [ECX, EFLAGS] in { - multiclass SS42AI_pcmpistri { + multiclass SS42AI_pcmpistri { def rr : SS42AI<0x63, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2, i8imm:$src3), !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"), - [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)), - (implicit EFLAGS)]>, OpSize; + [(set ECX, EFLAGS, (X86pcmpistri VR128:$src1, VR128:$src2, + imm:$src3))]>, OpSize; def rm : SS42AI<0x63, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2, i8imm:$src3), !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"), - [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)), - (implicit EFLAGS)]>, OpSize; + [(set ECX, EFLAGS, (X86pcmpistri VR128:$src1, (load addr:$src2), + imm:$src3))]>, OpSize; } } -let Predicates = [HasAVX] in { -defm VPCMPISTRI : SS42AI_pcmpistri, - VEX; -defm VPCMPISTRIA : SS42AI_pcmpistri, - VEX; -defm VPCMPISTRIC : SS42AI_pcmpistri, - VEX; -defm VPCMPISTRIO : SS42AI_pcmpistri, - VEX; -defm VPCMPISTRIS : SS42AI_pcmpistri, - VEX; -defm VPCMPISTRIZ : SS42AI_pcmpistri, - VEX; -} +let Predicates = [HasAVX] in +defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX; +defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">; -defm PCMPISTRI : SS42AI_pcmpistri; -defm PCMPISTRIA : SS42AI_pcmpistri; -defm PCMPISTRIC : SS42AI_pcmpistri; -defm PCMPISTRIO : SS42AI_pcmpistri; -defm PCMPISTRIS : SS42AI_pcmpistri; -defm PCMPISTRIZ : SS42AI_pcmpistri; - // Packed Compare Explicit Length Strings, Return Index let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in { - multiclass SS42AI_pcmpestri { + multiclass SS42AI_pcmpestri { def rr : SS42AI<0x61, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src3, i8imm:$src5), !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"), - [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)), - (implicit EFLAGS)]>, OpSize; + [(set ECX, EFLAGS, (X86pcmpestri VR128:$src1, EAX, VR128:$src3, + EDX, imm:$src5))]>, OpSize; def rm : SS42AI<0x61, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src3, i8imm:$src5), !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"), - [(set ECX, - (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)), - (implicit EFLAGS)]>, OpSize; + [(set ECX, EFLAGS, (X86pcmpestri VR128:$src1, EAX, (load addr:$src3), + EDX, imm:$src5))]>, OpSize; } } -let Predicates = [HasAVX] in { -defm VPCMPESTRI : SS42AI_pcmpestri, - VEX; -defm VPCMPESTRIA : SS42AI_pcmpestri, - VEX; -defm VPCMPESTRIC : SS42AI_pcmpestri, - VEX; -defm VPCMPESTRIO : SS42AI_pcmpestri, - VEX; -defm VPCMPESTRIS : SS42AI_pcmpestri, - VEX; -defm VPCMPESTRIZ : SS42AI_pcmpestri, - VEX; -} +let Predicates = [HasAVX] in +defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX; +defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">; -defm PCMPESTRI : SS42AI_pcmpestri; -defm PCMPESTRIA : SS42AI_pcmpestri; -defm PCMPESTRIC : SS42AI_pcmpestri; -defm PCMPESTRIO : SS42AI_pcmpestri; -defm PCMPESTRIS : SS42AI_pcmpestri; -defm PCMPESTRIZ : SS42AI_pcmpestri; - //===----------------------------------------------------------------------===// // SSE4.2 - CRC Instructions //===----------------------------------------------------------------------===// Index: X86ISelLowering.h =================================================================== --- X86ISelLowering.h (revision 144056) +++ X86ISelLowering.h (working copy) @@ -309,6 +309,10 @@ SFENCE, LFENCE, + // PCMP*STRI + PCMPISTRI, + PCMPESTRI, + // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - // Atomic 64-bit binary operations. From isanbard at gmail.com Mon Nov 7 23:22:54 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 08 Nov 2011 05:22:54 -0000 Subject: [llvm-commits] [llvm] r144076 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20111108052254.6DDCC2A6C12C@llvm.org> Author: void Date: Mon Nov 7 23:22:54 2011 New Revision: 144076 URL: http://llvm.org/viewvc/llvm-project?rev=144076&view=rev Log: Add Eero to the list of external projects. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=144076&r1=144075&r2=144076&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Mon Nov 7 23:22:54 2011 @@ -350,6 +350,22 @@ +

Eero

+ +
+ +

Eero is a fully + header-and-binary-compatible dialect of Objective-C 2.0, implemented with a + patched version of the Clang/LLVM compiler. It features a streamlined syntax, + Python-like indentation, and new operators, for improved readability and + reduced code clutter. It also has new features such as limited forms of + operator overloading and namespaces, and strict (type-and-operator-safe) + enumerations. It is inspired by languages such as Smalltalk, Python, and + Ruby.

+ +
+ +

Glasgow Haskell Compiler (GHC)

From rjmccall at apple.com Tue Nov 8 00:53:05 2011 From: rjmccall at apple.com (John McCall) Date: Tue, 08 Nov 2011 06:53:05 -0000 Subject: [llvm-commits] [llvm] r144079 - in /llvm/trunk/tools/llvm-diff: DiffConsumer.cpp DifferenceEngine.cpp Message-ID: <20111108065305.3D1FA2A6C12C@llvm.org> Author: rjmccall Date: Tue Nov 8 00:53:04 2011 New Revision: 144079 URL: http://llvm.org/viewvc/llvm-project?rev=144079&view=rev Log: Fix the printing of constants. Patch by Stepan Dyatkovskiy! Modified: llvm/trunk/tools/llvm-diff/DiffConsumer.cpp llvm/trunk/tools/llvm-diff/DifferenceEngine.cpp Modified: llvm/trunk/tools/llvm-diff/DiffConsumer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-diff/DiffConsumer.cpp?rev=144079&r1=144078&r2=144079&view=diff ============================================================================== --- llvm/trunk/tools/llvm-diff/DiffConsumer.cpp (original) +++ llvm/trunk/tools/llvm-diff/DiffConsumer.cpp Tue Nov 8 00:53:04 2011 @@ -64,6 +64,10 @@ } return; } + if (dyn_cast(V)) { + out << *V; + return; + } unsigned N = contexts.size(); while (N > 0) { Modified: llvm/trunk/tools/llvm-diff/DifferenceEngine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-diff/DifferenceEngine.cpp?rev=144079&r1=144078&r2=144079&view=diff ============================================================================== --- llvm/trunk/tools/llvm-diff/DifferenceEngine.cpp (original) +++ llvm/trunk/tools/llvm-diff/DifferenceEngine.cpp Tue Nov 8 00:53:04 2011 @@ -327,7 +327,7 @@ if (LCase) { if (TryUnify) tryUnify(LCase, RI->getSuccessor(I)); LCases.erase(CaseValue); - } else if (!Difference) { + } else if (Complain || !Difference) { if (Complain) Engine.logf("right switch has extra case %r") << CaseValue; Difference = true; From nicholas at mxc.ca Tue Nov 8 02:38:53 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 08 Nov 2011 00:38:53 -0800 Subject: [llvm-commits] [llvm] r144079 - in /llvm/trunk/tools/llvm-diff: DiffConsumer.cpp DifferenceEngine.cpp In-Reply-To: <20111108065305.3D1FA2A6C12C@llvm.org> References: <20111108065305.3D1FA2A6C12C@llvm.org> Message-ID: <4EB8EA9D.2000401@mxc.ca> John McCall wrote: > Author: rjmccall > Date: Tue Nov 8 00:53:04 2011 > New Revision: 144079 > > URL: http://llvm.org/viewvc/llvm-project?rev=144079&view=rev > Log: > Fix the printing of constants. Patch by Stepan Dyatkovskiy! > > > Modified: > llvm/trunk/tools/llvm-diff/DiffConsumer.cpp > llvm/trunk/tools/llvm-diff/DifferenceEngine.cpp > > Modified: llvm/trunk/tools/llvm-diff/DiffConsumer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-diff/DiffConsumer.cpp?rev=144079&r1=144078&r2=144079&view=diff > ============================================================================== > --- llvm/trunk/tools/llvm-diff/DiffConsumer.cpp (original) > +++ llvm/trunk/tools/llvm-diff/DiffConsumer.cpp Tue Nov 8 00:53:04 2011 > @@ -64,6 +64,10 @@ > } > return; > } > + if (dyn_cast(V)) { Please use isa(V). Nick > + out<< *V; > + return; > + } > > unsigned N = contexts.size(); > while (N> 0) { > > Modified: llvm/trunk/tools/llvm-diff/DifferenceEngine.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-diff/DifferenceEngine.cpp?rev=144079&r1=144078&r2=144079&view=diff > ============================================================================== > --- llvm/trunk/tools/llvm-diff/DifferenceEngine.cpp (original) > +++ llvm/trunk/tools/llvm-diff/DifferenceEngine.cpp Tue Nov 8 00:53:04 2011 > @@ -327,7 +327,7 @@ > if (LCase) { > if (TryUnify) tryUnify(LCase, RI->getSuccessor(I)); > LCases.erase(CaseValue); > - } else if (!Difference) { > + } else if (Complain || !Difference) { > if (Complain) > Engine.logf("right switch has extra case %r")<< CaseValue; > Difference = true; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From benny.kra at googlemail.com Tue Nov 8 03:48:15 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 8 Nov 2011 10:48:15 +0100 Subject: [llvm-commits] [llvm] r144070 - /llvm/trunk/runtime/libprofile/PathProfiling.c In-Reply-To: <20111108035440.793A22A6C12C@llvm.org> References: <20111108035440.793A22A6C12C@llvm.org> Message-ID: <52CAFF9E-0641-4643-802F-1DDFAA02FAA8@googlemail.com> On 08.11.2011, at 04:54, NAKAMURA Takumi wrote: > Author: chapuni > Date: Mon Nov 7 21:54:40 2011 > New Revision: 144070 > > URL: http://llvm.org/viewvc/llvm-project?rev=144070&view=rev > Log: > runtime/libprofile/PathProfiling.c: Use __inline__ to appease clang -std=gnu89 -pedantic. > > FIXME: Should configure detect one? I think we can just drop the inline keywords here and let the compiler decide whether it wants to inline that function or not. An optimizer hint that's going to be unused most of the time is not worth that much complexity. -Ben > > Modified: > llvm/trunk/runtime/libprofile/PathProfiling.c > > Modified: llvm/trunk/runtime/libprofile/PathProfiling.c > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/runtime/libprofile/PathProfiling.c?rev=144070&r1=144069&r2=144070&view=diff > ============================================================================== > --- llvm/trunk/runtime/libprofile/PathProfiling.c (original) > +++ llvm/trunk/runtime/libprofile/PathProfiling.c Mon Nov 7 21:54:40 2011 > @@ -28,7 +28,7 @@ > > /* Must use __inline in Microsoft C */ > #if defined(_MSC_VER) > -#define inline __inline > +#define __inline__ __inline > #endif > > /* note that this is used for functions with large path counts, > @@ -112,7 +112,7 @@ > } > } > > -static inline uint32_t hash (uint32_t key) { > +static __inline__ uint32_t hash (uint32_t key) { > /* this may benefit from a proper hash function */ > return key%ARBITRARY_HASH_BIN_COUNT; > } > @@ -155,7 +155,7 @@ > } > > /* Return a pointer to this path's specific path counter */ > -static inline uint32_t* getPathCounter(uint32_t functionNumber, > +static __inline__ uint32_t* getPathCounter(uint32_t functionNumber, > uint32_t pathNumber) { > pathHashTable_t* hashTable; > pathHashEntry_t* hashEntry; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From geek4civic at gmail.com Tue Nov 8 04:08:05 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 8 Nov 2011 19:08:05 +0900 Subject: [llvm-commits] [llvm] r144070 - /llvm/trunk/runtime/libprofile/PathProfiling.c In-Reply-To: <52CAFF9E-0641-4643-802F-1DDFAA02FAA8@googlemail.com> References: <20111108035440.793A22A6C12C@llvm.org> <52CAFF9E-0641-4643-802F-1DDFAA02FAA8@googlemail.com> Message-ID: 2011/11/8 Benjamin Kramer : > I think we can just drop the inline keywords here and let the compiler decide whether it wants to inline that function or not. An optimizer hint that's going to be unused most of the time is not worth that much complexity. Yeah, that makes sense. At past, I asuumed "static" should be inlined with optzn. ;) ...Takumi From hfinkel at anl.gov Tue Nov 8 04:45:09 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 08 Nov 2011 04:45:09 -0600 Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass In-Reply-To: <1320191694.23036.1497.camel@sapling> References: <1319909412.23036.851.camel@sapling> <1319914924.23036.852.camel@sapling> <1319919418.23036.881.camel@sapling> <1319928991.23036.957.camel@sapling> <1320108633.23036.1266.camel@sapling> <1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling> <1320191694.23036.1497.camel@sapling> Message-ID: <1320749109.19359.76.camel@sapling> I've attached the latest version of my autovectorization patch. Working through the test suite has proved to be a productive experience ;) -- And almost all of the bugs that it revealed have now been fixed. There are still two programs that don't compile with vectorization turned on, and I'm working on those now, but in case anyone feels like playing with vectorization, this patch will probably work for you. The largest three performance speedups are: SingleSource/Benchmarks/BenchmarkGame/puzzle - 59.2% speedup SingleSource/UnitTests/Vector/multiplies - 57.7% speedup SingleSource/Benchmarks/Misc/flops-7 - 50.75% speedup The largest three performance slowdowns are: MultiSource/Benchmarks/MiBench/security-rijndael/security-rijndael - 114% slowdown MultiSource/Benchmarks/MiBench/network-patricia/network-patricia - 66.6% slowdown SingleSource/Benchmarks/Misc/flops-8 - 64.2% slowdown (from these, I've excluded tests that took less that 0.1 seconds to run). Largest three compile-time slowdowns: MultiSource/Benchmarks/MiBench/security-rijndael/security-rijndael - 1276% slowdown SingleSource/Benchmarks/Misc/salsa20 - 1000% slowdown MultiSource/Benchmarks/Trimaran/enc-3des/enc-3des - 508% slowdown Not everything slows down, MultiSource/Benchmarks/Prolangs-C ++/city/city, for example, compiles 10% faster with vectorization enabled; but, for the most part, things certainly take longer to compile with vectorization enabled. The average slowdown over all tests was 29%, the median was 11%. On the other hand, the average speedup over all tests was 5.2%, the median was 1.3%. Compared to previous patches, which had a minimum required chain length of 3 or 4, I've now made the default 6. While using a chain length of 4 worked well for targeted benchmarks, it caused an overall slowdown on almost all test-suite programs. Using a minimum length of 6 causes, on average, a speedup; so I think that is a better default choice. -Hal On Tue, 2011-11-01 at 18:54 -0500, Hal Finkel wrote: > On Tue, 2011-11-01 at 16:59 -0500, Hal Finkel wrote: > > On Tue, 2011-11-01 at 19:19 +0000, Tobias Grosser wrote: > > > On 11/01/2011 06:32 PM, Hal Finkel wrote: > > > > Any objections to me committing this? [And some relevant docs changes] I > > > > think that it is ready at this point. > > > > > > First of all. I think it is great to see work starting on an > > > autovectorizer for LLVM. Unfortunately I did not have time to test your > > > vectorizer pass intensively, but here my first comments: > > > > > > 1. This patch breaks the --enable-shared/BUILD_SHARED_LIBS build. The > > > following patch fixes this for cmake: > > > 0001-Add-vectorizer-to-libraries-used-by-Transforms-IPO.patch > > > > > > > Thanks! > > > > > Can you check the autoconf build with --enable-shared? > > > > I will check. > > This appears to work as it should. > > > > > > > > > 2. Did you run this pass on the llvm test-suite? Does your vectorizer > > > introduce any correctness regressions? What are the top 10 compile > > > time increases/decreases. How about run time? > > > > > > > I'll try to get this setup and post the results. > > > > > 3. I did not really test this intensively, but I had the feeling the > > > compile time increase for large basic blocks is quite a lot. > > > I still need to extract a test case. Any comments on the complexity > > > of your vectorizer? > > > > This may very will be true. As is, I would not recommend activating this > > pass by default (at -O3) because it is fairly slow and the resulting > > performance increase, while significant in many cases, is not large > > enough to, IMHO, justify the extra base compile-time increase. Ideally, > > this kind of vectorization should be the "vectorizer of last resort" -- > > the pass that tries really hard to squeeze the last little bit of > > vectorization possible out of the code. At the moment, it is all that we > > have, but I hope that will change. I've not yet done any real profiling, > > so I'll hold off on commenting about future performance improvements. > > > > Base complexity is a bit difficult, there are certainly a few stages, > > including that initial one, that are O(n^2), where n is the number of > > instructions in the block. The "connection-finding" stage should also be > > O(n^2) in practice, but is really iterating over instruction-user pairs > > and so could be worse in pathological cases. Note, however, that in the > > latter stages, that n^2 is not the number of instructions in the block, > > but rather the number of (unordered) candidate instruction pairs (which > > is going to be must less than the n^2 from just the number of > > instructions in the block). It should be possible to generate a > > compile-time scaling plot by taking a loop and compiling it with partial > > unrolling, looking at how the compile time changes with the unrolling > > limit; I'll try and so that. > > So for this test, I ran: > time opt -S -O3 -unroll-allow-partial -vectorize -o /dev/null q.ll > where q.ll contains the output from clang -O3 of the vbor function from > the benchmarks I've been posting recently. The first column is the value > of -unroll-threshold, the second column is the time with vectorization, > and the third column is the time without vectorization (time in seconds > for a release build). > > 100 0.030 0.000 > 200 0.130 0.030 > 300 0.770 0.030 > 400 1.240 0.040 > 500 1.280 0.050 > 600 9.450 0.060 > 700 29.300 0.060 > > I am not sure why the 400 and 500 times are so close. Obviously, it is > not linear ;) I am not sure that enumerating the possible pairings can > be done in a sub-quadratic way, but I will do some profiling and see if > I can make things better. To be fair, this test creates a kind of a > worse-case scenario: an increasingly large block of instructions, almost > all of which are potentially fusable. > > It may also be possible to design additional heuristics to help the > situation. For example, we might introduce a target chain length such > that if the vectorizer finds a chain of a given length, it selects it, > foregoing the remainder of the search for the selected starting > instruction. This kind of thing will require further research and > testing. > > -Hal > > > > > I'm writing a paper on the vectorizer, so within a few weeks there will > > be a very good description (complete with diagrams) :) > > > > > > > > I plan to look into your vectorizer during the next couple of > > > days/weeks, but will most probably not have the time to do this tonight. > > > Sorry. :-( > > > > Not a problem; it seems that I have some homework to do first ;) > > > > Thanks, > > Hal > > > > > > > > Cheers > > > Tobi > > > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_bb_vectorize-20111107.diff Type: text/x-patch Size: 79455 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111108/3b39956c/attachment-0001.bin From tobias at grosser.es Tue Nov 8 05:12:24 2011 From: tobias at grosser.es (Tobias Grosser) Date: Tue, 08 Nov 2011 12:12:24 +0100 Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass In-Reply-To: <1320749109.19359.76.camel@sapling> References: <1319909412.23036.851.camel@sapling> <1319914924.23036.852.camel@sapling> <1319919418.23036.881.camel@sapling> <1319928991.23036.957.camel@sapling> <1320108633.23036.1266.camel@sapling> <1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling> <1320191694.23036.1497.camel@sapling> <1320749109.19359.76.camel@sapling> Message-ID: <4EB90E98.4010805@grosser.es> On 11/08/2011 11:45 AM, Hal Finkel wrote: > I've attached the latest version of my autovectorization patch. > > Working through the test suite has proved to be a productive > experience ;) -- And almost all of the bugs that it revealed have now > been fixed. There are still two programs that don't compile with > vectorization turned on, and I'm working on those now, but in case > anyone feels like playing with vectorization, this patch will probably > work for you. Hey Hal, those are great news. Especially as the numbers seem to show that vectorization has a significant performance impact. What did you compare exactly. 'clang -O3' against 'clang -O3 -mllvm -vectorize'? > The largest three performance speedups are: > SingleSource/Benchmarks/BenchmarkGame/puzzle - 59.2% speedup > SingleSource/UnitTests/Vector/multiplies - 57.7% speedup > SingleSource/Benchmarks/Misc/flops-7 - 50.75% speedup > > The largest three performance slowdowns are: > MultiSource/Benchmarks/MiBench/security-rijndael/security-rijndael - > 114% slowdown > MultiSource/Benchmarks/MiBench/network-patricia/network-patricia - 66.6% > slowdown > SingleSource/Benchmarks/Misc/flops-8 - 64.2% slowdown > Interesting. Do you understand what causes these slowdowns? Can your heuristic be improved? > Largest three compile-time slowdowns: > MultiSource/Benchmarks/MiBench/security-rijndael/security-rijndael - > 1276% slowdown > SingleSource/Benchmarks/Misc/salsa20 - 1000% slowdown > MultiSource/Benchmarks/Trimaran/enc-3des/enc-3des - 508% slowdown Yes, that is a lot. Do you understand if this time is invested well (does it give significant speedups)? If I understood correctly it seems your vectorizer has quadratic complexity which may cause large slowdowns. Do you think it may be useful/possible to make it linear by introducing a constant upper bound somewhere? E.g. limiting it to 10/20/100 steps. Maybe we are lucky and most of the vectorization opportunities are close by (in some sense), such that we get most of the speedup by locking at a subset of the problem. > Not everything slows down, MultiSource/Benchmarks/Prolangs-C > ++/city/city, for example, compiles 10% faster with vectorization > enabled; but, for the most part, things certainly take longer to compile > with vectorization enabled. The average slowdown over all tests was 29%, > the median was 11%. On the other hand, the average speedup over all > tests was 5.2%, the median was 1.3%. Nice. I think this is a great start. > Compared to previous patches, which had a minimum required chain length > of 3 or 4, I've now made the default 6. While using a chain length of 4 > worked well for targeted benchmarks, it caused an overall slowdown on > almost all test-suite programs. Using a minimum length of 6 causes, on > average, a speedup; so I think that is a better default choice. I also try to understand if it is possible to use your vectorizer for Polly. My idea is to do some clever loop unrolling. Starting from this loop. for (int i = 0; i < 4; i++) A[i] += 1; A[i] = B[i] + 3; C[i] = A[i]; The classical unroller would create this code: A[0] += 1; A[0] = B[i] + 3; C[0] = A[i]; A[1] += 1; A[1] = B[i] + 3; C[1] = A[i]; A[2] += 1; A[2] = B[i] + 3; C[2] = A[i]; A[3] += 1; A[3] = B[i] + 3; C[3] = A[i]; However, in case I can prove this loop is parallel, I want to create this code: A[0] += 1; A[1] += 1; A[2] += 1; A[3] += 1; A[0] = B[i] + 3; A[1] = B[i] + 3; A[2] = B[i] + 3; A[3] = B[i] + 3; C[0] = A[i]; C[1] = A[i]; C[2] = A[i]; C[3] = A[i]; I assume this will allow the vectorization of test cases, that failed because of possible aliasing. However, I am more interested, if the execution order change could also improve the vectorization outcome or reduce compile time overhead of your vectorizer. Thanks for working on the vectorization Cheers Tobi From geek4civic at gmail.com Tue Nov 8 06:03:14 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 08 Nov 2011 12:03:14 -0000 Subject: [llvm-commits] [llvm] r144080 - /llvm/trunk/runtime/libprofile/PathProfiling.c Message-ID: <20111108120314.59B932A6C12C@llvm.org> Author: chapuni Date: Tue Nov 8 06:03:14 2011 New Revision: 144080 URL: http://llvm.org/viewvc/llvm-project?rev=144080&view=rev Log: PathProfiling.c: Get rid of using "inline". We may expect compiler shall optimize out "static" scope w/o "inline". Modified: llvm/trunk/runtime/libprofile/PathProfiling.c Modified: llvm/trunk/runtime/libprofile/PathProfiling.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/runtime/libprofile/PathProfiling.c?rev=144080&r1=144079&r2=144080&view=diff ============================================================================== --- llvm/trunk/runtime/libprofile/PathProfiling.c (original) +++ llvm/trunk/runtime/libprofile/PathProfiling.c Tue Nov 8 06:03:14 2011 @@ -26,11 +26,6 @@ #include #include -/* Must use __inline in Microsoft C */ -#if defined(_MSC_VER) -#define __inline__ __inline -#endif - /* note that this is used for functions with large path counts, but it is unlikely those paths will ALL be executed */ #define ARBITRARY_HASH_BIN_COUNT 100 @@ -112,7 +107,7 @@ } } -static __inline__ uint32_t hash (uint32_t key) { +static uint32_t hash (uint32_t key) { /* this may benefit from a proper hash function */ return key%ARBITRARY_HASH_BIN_COUNT; } @@ -155,7 +150,7 @@ } /* Return a pointer to this path's specific path counter */ -static __inline__ uint32_t* getPathCounter(uint32_t functionNumber, +static uint32_t* getPathCounter(uint32_t functionNumber, uint32_t pathNumber) { pathHashTable_t* hashTable; pathHashEntry_t* hashEntry; From elena.demikhovsky at intel.com Tue Nov 8 06:08:41 2011 From: elena.demikhovsky at intel.com (Demikhovsky, Elena) Date: Tue, 8 Nov 2011 14:08:41 +0200 Subject: [llvm-commits] AVX1 Code Generation - VSHUFP extension In-Reply-To: References: <7CB6AC5AED596245A99BF3213DE8F4AA02FFEA3063@hasmsx504.ger.corp.intel.com> Message-ID: <7CB6AC5AED596245A99BF3213DE8F4AA02FFF2B81B@hasmsx504.ger.corp.intel.com> Eli, Thank you for the review. I fixed the code. The input mask remains unchanged now. Please take a look. - Elena -----Original Message----- From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Monday, November 07, 2011 23:47 To: Demikhovsky, Elena Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] AVX1 Code Generation - VSHUFP extension On Mon, Nov 7, 2011 at 12:08 AM, Demikhovsky, Elena wrote: > Hello, > > I added several lines in X86 code generator that allow to choose VSHUFPS/VSHUFPD > instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask. > > I extended the existing lit test. > > Please review. +static bool isCommutedVSHUFPSY(SmallVectorImpl &Mask, EVT VT, + const X86Subtarget *Subtarget) { + + if ((VT.getSizeInBits() != 256) || (VT.getVectorNumElements() != 8)) + return false; + + CommuteVectorShuffleMask(Mask, VT); + return isVSHUFPSYMask(Mask, VT, Subtarget); +} It looks like this mutates the input Mask; I don't think you really want to do that. + // Try to swap operands in the node to match x86 shuffle ops + if (!V2IsUndef && isCommutedVSHUFPSY(M, VT, Subtarget)) { + // Now we need to commute operands. + SVOp = cast(CommuteVectorShuffle(SVOp, DAG)); This isn't consistent with the way other code in this function uses CommuteVectorShuffle. -Eli --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: vshufp1.diff Type: application/octet-stream Size: 3849 bytes Desc: vshufp1.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111108/b9773a41/attachment.obj From jfonseca at vmware.com Tue Nov 8 06:17:20 2011 From: jfonseca at vmware.com (Jose Fonseca) Date: Tue, 8 Nov 2011 04:17:20 -0800 (PST) Subject: [llvm-commits] [PATCH] Fix CRT selection logic when using CMake NMake generator. In-Reply-To: Message-ID: <954116651.284955.1320754640434.JavaMail.root@zimbra-prod-mbox-2.vmware.com> Thanks. Jose ----- Original Message ----- > Jose, applied in r143898, thank you! > > I believe it is trivial, too. > > ...Takumi > > 2011/11/5 Jose Fonseca : > > Ping? > > > > It's really trivial. > > > > Jose > > > > ----- Original Message ----- > >> > >> CMAKE_CONFIGURATION_TYPES is only set on Visual Studio generators. > >> ?For > >> NMake CMAKE_BUILD_TYPE is used instead. > >> --- > >> ?cmake/modules/ChooseMSVCCRT.cmake | ? ?4 ++-- > >> ?1 files changed, 2 insertions(+), 2 deletions(-) > >> > >> > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > > From bruno.cardoso at gmail.com Tue Nov 8 06:47:11 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 08 Nov 2011 12:47:11 -0000 Subject: [llvm-commits] [llvm] r144081 - in /llvm/trunk/lib/Target/Mips: MipsCodeEmitter.cpp MipsJITInfo.cpp Message-ID: <20111108124711.929C82A6C12C@llvm.org> Author: bruno Date: Tue Nov 8 06:47:11 2011 New Revision: 144081 URL: http://llvm.org/viewvc/llvm-project?rev=144081&view=rev Log: This patch handles unaligned loads and stores in Mips JIT. Mips backend implements unaligned loads and stores with assembler macro-instructions ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions instead of these macros. Since each unaligned load/store is expanded into two corresponding loads/stores where offset for second load/store is modified by +3 (for words) or +1 (for halfwords). Patch by Petar Jovanovic and Sasa Stankovic. Modified: llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp Modified: llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp?rev=144081&r1=144080&r2=144081&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsCodeEmitter.cpp Tue Nov 8 06:47:11 2011 @@ -108,6 +108,15 @@ unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const; + + int emitULW(const MachineInstr &MI); + int emitUSW(const MachineInstr &MI); + int emitULH(const MachineInstr &MI); + int emitULHu(const MachineInstr &MI); + int emitUSH(const MachineInstr &MI); + + void emitGlobalAddressUnaligned(const GlobalValue *GV, unsigned Reloc, + int Offset) const; }; } @@ -186,9 +195,15 @@ return MipsRegisterInfo::getRegisterNumbering(MO.getReg()); else if (MO.isImm()) return static_cast(MO.getImm()); - else if (MO.isGlobal()) - emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO), true); - else if (MO.isSymbol()) + else if (MO.isGlobal()) { + if (MI.getOpcode() == Mips::ULW || MI.getOpcode() == Mips::USW || + MI.getOpcode() == Mips::ULH || MI.getOpcode() == Mips::ULHu) + emitGlobalAddressUnaligned(MO.getGlobal(), getRelocation(MI, MO), 4); + else if (MI.getOpcode() == Mips::USH) + emitGlobalAddressUnaligned(MO.getGlobal(), getRelocation(MI, MO), 8); + else + emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO), true); + } else if (MO.isSymbol()) emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO)); else if (MO.isCPI()) emitConstPoolAddress(MO.getIndex(), getRelocation(MI, MO)); @@ -207,6 +222,14 @@ const_cast(GV), 0, MayNeedFarStub)); } +void MipsCodeEmitter::emitGlobalAddressUnaligned(const GlobalValue *GV, + unsigned Reloc, int Offset) const { + MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, + const_cast(GV), 0, false)); + MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset() + Offset, + Reloc, const_cast(GV), 0, false)); +} + void MipsCodeEmitter:: emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), @@ -230,6 +253,103 @@ Reloc, BB)); } +int MipsCodeEmitter::emitUSW(const MachineInstr &MI) { + unsigned src = getMachineOpValue(MI, MI.getOperand(0)); + unsigned base = getMachineOpValue(MI, MI.getOperand(1)); + unsigned offset = getMachineOpValue(MI, MI.getOperand(2)); + // swr src, offset(base) + // swl src, offset+3(base) + MCE.emitWordLE( + (0x2e << 26) | (base << 21) | (src << 16) | (offset & 0xffff)); + MCE.emitWordLE( + (0x2a << 26) | (base << 21) | (src << 16) | ((offset+3) & 0xffff)); + return 2; +} + +int MipsCodeEmitter::emitULW(const MachineInstr &MI) { + unsigned dst = getMachineOpValue(MI, MI.getOperand(0)); + unsigned base = getMachineOpValue(MI, MI.getOperand(1)); + unsigned offset = getMachineOpValue(MI, MI.getOperand(2)); + unsigned at = 1; + if (dst != base) { + // lwr dst, offset(base) + // lwl dst, offset+3(base) + MCE.emitWordLE( + (0x26 << 26) | (base << 21) | (dst << 16) | (offset & 0xffff)); + MCE.emitWordLE( + (0x22 << 26) | (base << 21) | (dst << 16) | ((offset+3) & 0xffff)); + return 2; + } else { + // lwr at, offset(base) + // lwl at, offset+3(base) + // addu dst, at, $zero + MCE.emitWordLE( + (0x26 << 26) | (base << 21) | (at << 16) | (offset & 0xffff)); + MCE.emitWordLE( + (0x22 << 26) | (base << 21) | (at << 16) | ((offset+3) & 0xffff)); + MCE.emitWordLE( + (0x0 << 26) | (at << 21) | (0x0 << 16) | (dst << 11) | (0x0 << 6) | 0x21); + return 3; + } +} + +int MipsCodeEmitter::emitUSH(const MachineInstr &MI) { + unsigned src = getMachineOpValue(MI, MI.getOperand(0)); + unsigned base = getMachineOpValue(MI, MI.getOperand(1)); + unsigned offset = getMachineOpValue(MI, MI.getOperand(2)); + unsigned at = 1; + // sb src, offset(base) + // srl at,src,8 + // sb at, offset+1(base) + MCE.emitWordLE( + (0x28 << 26) | (base << 21) | (src << 16) | (offset & 0xffff)); + MCE.emitWordLE( + (0x0 << 26) | (0x0 << 21) | (src << 16) | (at << 11) | (0x8 << 6) | 0x2); + MCE.emitWordLE( + (0x28 << 26) | (base << 21) | (at << 16) | ((offset+1) & 0xffff)); + return 3; +} + +int MipsCodeEmitter::emitULH(const MachineInstr &MI) { + unsigned dst = getMachineOpValue(MI, MI.getOperand(0)); + unsigned base = getMachineOpValue(MI, MI.getOperand(1)); + unsigned offset = getMachineOpValue(MI, MI.getOperand(2)); + unsigned at = 1; + // lbu at, offset(base) + // lb dst, offset+1(base) + // sll dst,dst,8 + // or dst,dst,at + MCE.emitWordLE( + (0x24 << 26) | (base << 21) | (at << 16) | (offset & 0xffff)); + MCE.emitWordLE( + (0x20 << 26) | (base << 21) | (dst << 16) | ((offset+1) & 0xffff)); + MCE.emitWordLE( + (0x0 << 26) | (0x0 << 21) | (dst << 16) | (dst << 11) | (0x8 << 6) | 0x0); + MCE.emitWordLE( + (0x0 << 26) | (dst << 21) | (at << 16) | (dst << 11) | (0x0 << 6) | 0x25); + return 4; +} + +int MipsCodeEmitter::emitULHu(const MachineInstr &MI) { + unsigned dst = getMachineOpValue(MI, MI.getOperand(0)); + unsigned base = getMachineOpValue(MI, MI.getOperand(1)); + unsigned offset = getMachineOpValue(MI, MI.getOperand(2)); + unsigned at = 1; + // lbu at, offset(base) + // lbu dst, offset+1(base) + // sll dst,dst,8 + // or dst,dst,at + MCE.emitWordLE( + (0x24 << 26) | (base << 21) | (at << 16) | (offset & 0xffff)); + MCE.emitWordLE( + (0x24 << 26) | (base << 21) | (dst << 16) | ((offset+1) & 0xffff)); + MCE.emitWordLE( + (0x0 << 26) | (0x0 << 21) | (dst << 16) | (dst << 11) | (0x8 << 6) | 0x0); + MCE.emitWordLE( + (0x0 << 26) | (dst << 21) | (at << 16) | (dst << 11) | (0x0 << 6) | 0x25); + return 4; +} + void MipsCodeEmitter::emitInstruction(const MachineInstr &MI) { DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); @@ -239,11 +359,27 @@ if ((MI.getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo) return; - ++NumEmitted; // Keep track of the # of mi's emitted switch (MI.getOpcode()) { + case Mips::USW: + NumEmitted += emitUSW(MI); + break; + case Mips::ULW: + NumEmitted += emitULW(MI); + break; + case Mips::ULH: + NumEmitted += emitULH(MI); + break; + case Mips::ULHu: + NumEmitted += emitULHu(MI); + break; + case Mips::USH: + NumEmitted += emitUSH(MI); + break; + default: emitWordLE(getBinaryCodeForInstr(MI)); + ++NumEmitted; // Keep track of the # of mi's emitted break; } Modified: llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp?rev=144081&r1=144080&r2=144081&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsJITInfo.cpp Tue Nov 8 06:47:11 2011 @@ -218,10 +218,16 @@ *((unsigned*) RelocPos) |= (unsigned) ResultPtr; break; - case Mips::reloc_mips_lo: - ResultPtr = ResultPtr & 0xffff; + case Mips::reloc_mips_lo: { + // Addend is needed for unaligned load/store instructions, where offset + // for the second load/store in the expanded instruction sequence must + // be modified by +1 or +3. Otherwise, Addend is 0. + int Addend = *((unsigned*) RelocPos) & 0xffff; + ResultPtr = (ResultPtr + Addend) & 0xffff; + *((unsigned*) RelocPos) &= 0xffff0000; *((unsigned*) RelocPos) |= (unsigned) ResultPtr; break; + } default: llvm_unreachable("ERROR: Unknown Mips relocation."); From bruno.cardoso at gmail.com Tue Nov 8 07:21:24 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 8 Nov 2011 11:21:24 -0200 Subject: [llvm-commits] AVX1 Code Generation - VSHUFP extension In-Reply-To: <7CB6AC5AED596245A99BF3213DE8F4AA02FFF2B81B@hasmsx504.ger.corp.intel.com> References: <7CB6AC5AED596245A99BF3213DE8F4AA02FFEA3063@hasmsx504.ger.corp.intel.com> <7CB6AC5AED596245A99BF3213DE8F4AA02FFF2B81B@hasmsx504.ger.corp.intel.com> Message-ID: Hi Elena, > I fixed the code. The input mask remains unchanged now. > Please take a look. A couple more comments: 1) Please change the comments to use "//" instead of "/**/". 2) Your patch is broken: contains the diff of the same file more than once. 3) No need to have 2 isCommutedVSHUFP*. Just have one function and check "ps" or "pd" using the number of elements using VT.getVectorNumElements() - but make sure to still check for 256-bits. 4) Why don't match when V2IsUndef? I suppose it's because you want the shuffle to be xformed to a "extract of the low part"+128_bit-shuffle later. If that's the case, add a comment saying that! Thanks -- Bruno Cardoso Lopes http://www.brunocardoso.cc From james.molloy at arm.com Tue Nov 8 08:15:20 2011 From: james.molloy at arm.com (James Molloy) Date: Tue, 8 Nov 2011 14:15:20 -0000 Subject: [llvm-commits] [patch][pr11029] fix for internal crash due to ExpandUnalignedLoad/Store not handling indexed loads correctly In-Reply-To: <000001cc9952$cc5fa510$651eef30$@beyls@arm.com> References: <000001cc93f5$98ab1040$ca0130c0$@beyls@arm.com> <000001cc9952$cc5fa510$651eef30$@beyls@arm.com> Message-ID: <000101cc9e20$d94c4c60$8be4e520$@molloy@arm.com> Hi, Could someone please code review this patch? It fixes PR11029, an internal fault. Once reviewed I can commit on Kristof's behalf, but I'm not experienced enough with SelectionDAG to make a good review. Cheers, James -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Kristof Beyls Sent: 02 November 2011 11:30 To: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [patch][pr11029] fix for internal crash due to ExpandUnalignedLoad/Store not handling indexed loads correctly ping > -----Original Message----- > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits- > bounces at cs.uiuc.edu] On Behalf Of Kristof Beyls > Sent: 26 October 2011 16:40 > To: llvm-commits at cs.uiuc.edu > Subject: [llvm-commits] [patch][pr11029] fix for internal crash due to > ExpandUnalignedLoad/Store not handling indexed loads correctly > > The attached patch fixes PR11029 ( > http://llvm.org/bugs/show_bug.cgi?id=11029 ). > > The root cause of the problem seems to be that ExpandUnalignedLoad and > ExpandUnalignedStore doesn't handle indexed loads or stores correctly. > > There seem to be 2 possible ways to fix this: > 1. Implement support for indexed loads/stores in the above functions. > 2. Don't generate indexed load/stores in cases where these will need to > be > expanded. > > The attached patch implements the second approach. The reasons for > going > with the second approach are: > * The generation of indexed loads/stores seems to be an optimization. > The > second approach chooses not to do the optimization when it's not > supported. > * There will not be a regression in code generation, since in the cases > that > the patch prohibits optimization, the compiler would crash or generate > incorrect code with a high probability. > * It's unclear whether generating indexed loads/stores for unaligned > loads/stores that need expanding would actually result in better > quality of > the generated code. > > Could someone review the patch and commit it if fine? > > Thanks, > > Kristof _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From hfinkel at anl.gov Tue Nov 8 08:36:03 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 08 Nov 2011 08:36:03 -0600 Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass In-Reply-To: <4EB90E98.4010805@grosser.es> References: <1319909412.23036.851.camel@sapling> <1319914924.23036.852.camel@sapling> <1319919418.23036.881.camel@sapling> <1319928991.23036.957.camel@sapling> <1320108633.23036.1266.camel@sapling> <1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling> <1320191694.23036.1497.camel@sapling> <1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es> Message-ID: <1320762963.19359.117.camel@sapling> On Tue, 2011-11-08 at 12:12 +0100, Tobias Grosser wrote: > On 11/08/2011 11:45 AM, Hal Finkel wrote: > > I've attached the latest version of my autovectorization patch. > > > > Working through the test suite has proved to be a productive > > experience ;) -- And almost all of the bugs that it revealed have now > > been fixed. There are still two programs that don't compile with > > vectorization turned on, and I'm working on those now, but in case > > anyone feels like playing with vectorization, this patch will probably > > work for you. > > Hey Hal, > > those are great news. Especially as the numbers seem to show that > vectorization has a significant performance impact. What did you compare > exactly. 'clang -O3' against 'clang -O3 -mllvm -vectorize'? Yes. [I've tested the current patch directly using opt -vectorize -unroll-allow-partial; for running the test suite I recompiled llvm/clang to hardcode the options as I wanted them]. > > > The largest three performance speedups are: > > SingleSource/Benchmarks/BenchmarkGame/puzzle - 59.2% speedup > > SingleSource/UnitTests/Vector/multiplies - 57.7% speedup > > SingleSource/Benchmarks/Misc/flops-7 - 50.75% speedup > > > > The largest three performance slowdowns are: > > MultiSource/Benchmarks/MiBench/security-rijndael/security-rijndael - > > 114% slowdown > > MultiSource/Benchmarks/MiBench/network-patricia/network-patricia - 66.6% > > slowdown > > SingleSource/Benchmarks/Misc/flops-8 - 64.2% slowdown > > > Interesting. Do you understand what causes these slowdowns? Can your > heuristic be improved? I've not specifically looked at these cases. Generally, I've observed slowdowns from the introduction of too many permutations per chain (the chain selection procedure can be changed to help this, and I'll work on that). Also, sometimes legalization of non-native vector operations creates inefficient code, and I'll also look at these cases in more detail. > > > Largest three compile-time slowdowns: > > MultiSource/Benchmarks/MiBench/security-rijndael/security-rijndael - > > 1276% slowdown > > SingleSource/Benchmarks/Misc/salsa20 - 1000% slowdown > > MultiSource/Benchmarks/Trimaran/enc-3des/enc-3des - 508% slowdown > > Yes, that is a lot. Do you understand if this time is invested well > (does it give significant speedups)? No, not always. Actually, the security-rijndael test not only takes the longest to vectorize, but it also shows the largest slowdown. This is certainly something that I'll investigate. > > If I understood correctly it seems your vectorizer has quadratic > complexity which may cause large slowdowns. Do you think it may be > useful/possible to make it linear by introducing a constant upper bound > somewhere? E.g. limiting it to 10/20/100 steps. Maybe we are lucky and > most of the vectorization opportunities are close by (in some sense), > such that we get most of the speedup by locking at a subset of the problem. Yes, I agree. That makes a lot of sense. What would be even better is if the loop unroller would intermix statements from the loops where possible instead of leaving it to the vectorizer to do all of the grouping after the fact. That, I fear, is a whole other project. > > > Not everything slows down, MultiSource/Benchmarks/Prolangs-C > > ++/city/city, for example, compiles 10% faster with vectorization > > enabled; but, for the most part, things certainly take longer to compile > > with vectorization enabled. The average slowdown over all tests was 29%, > > the median was 11%. On the other hand, the average speedup over all > > tests was 5.2%, the median was 1.3%. > Nice. I think this is a great start. Thanks! > > > Compared to previous patches, which had a minimum required chain length > > of 3 or 4, I've now made the default 6. While using a chain length of 4 > > worked well for targeted benchmarks, it caused an overall slowdown on > > almost all test-suite programs. Using a minimum length of 6 causes, on > > average, a speedup; so I think that is a better default choice. > > I also try to understand if it is possible to use your vectorizer for > Polly. My idea is to do some clever loop unrolling. > > Starting from this loop. > > for (int i = 0; i < 4; i++) > A[i] += 1; > A[i] = B[i] + 3; > C[i] = A[i]; > > The classical unroller would create this code: > > A[0] += 1; > A[0] = B[i] + 3; > C[0] = A[i]; > > A[1] += 1; > A[1] = B[i] + 3; > C[1] = A[i]; > > A[2] += 1; > A[2] = B[i] + 3; > C[2] = A[i]; > > A[3] += 1; > A[3] = B[i] + 3; > C[3] = A[i]; > > However, in case I can prove this loop is parallel, I want to create > this code: > > A[0] += 1; > A[1] += 1; > A[2] += 1; > A[3] += 1; > > A[0] = B[i] + 3; > A[1] = B[i] + 3; > A[2] = B[i] + 3; > A[3] = B[i] + 3; > > C[0] = A[i]; > C[1] = A[i]; > C[2] = A[i]; > C[3] = A[i]; > > I assume this will allow the vectorization of test cases, that failed > because of possible aliasing. However, I am more interested, if the > execution order change could also improve the vectorization outcome or > reduce compile time overhead of your vectorizer. Yes, this would certainly help. By the way, the current implementation, by default, it will create unaligned vector loads and stores, but these are generally broken up by the legalizer. This behavior can be suppressed using the -bb-vectorize-aligned-only flag. It would be nice if the loop unroller chose the unrolling factor to preserve the maximum available alignment, but I don't think that it currently does so. One problem with the current implementation is that it relies on GetPointerBaseWithConstantOffset to determine if two loads or stores share the same base address. This fails with partially-unrolled loops because it cannot "undo" all of the additions to the offset induction variable in order to understand that some of the loads and stores are really adjacent in memory. This is something that I think can be improved within the vectorizer itself, and I'm planning on doing some work on this in the future. Thanks for your feedback, Hal > > Thanks for working on the vectorization > Cheers > > Tobi > > > > > -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From elena.demikhovsky at intel.com Tue Nov 8 08:46:01 2011 From: elena.demikhovsky at intel.com (Demikhovsky, Elena) Date: Tue, 8 Nov 2011 16:46:01 +0200 Subject: [llvm-commits] AVX1 Code Generation - VSHUFP extension In-Reply-To: References: <7CB6AC5AED596245A99BF3213DE8F4AA02FFEA3063@hasmsx504.ger.corp.intel.com> <7CB6AC5AED596245A99BF3213DE8F4AA02FFF2B81B@hasmsx504.ger.corp.intel.com> Message-ID: <7CB6AC5AED596245A99BF3213DE8F4AA02FFF2B9F0@hasmsx504.ger.corp.intel.com> 3) I tried to make my code similar to existing. if I put one function the code will look like: if (!V2IsUndef && isCommutedVSHUFP(M, VT, Subtarget)) { SVOp = cast(CommuteVectorShuffle(SVOp, DAG)); V1 = SVOp->getOperand(0); V2 = SVOp->getOperand(1); unsigned TargetMask = (VT.getVectorNumElements() == 8) ? getShuffleVSHUFPSYImmediate(SVOp): getShuffleVSHUFPDYImmediate(SVOp); return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, TargetMask, DAG); } - Elena -----Original Message----- From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] Sent: Tuesday, November 08, 2011 15:21 To: Demikhovsky, Elena Cc: Eli Friedman; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] AVX1 Code Generation - VSHUFP extension Hi Elena, > I fixed the code. The input mask remains unchanged now. > Please take a look. A couple more comments: 1) Please change the comments to use "//" instead of "/**/". 2) Your patch is broken: contains the diff of the same file more than once. 3) No need to have 2 isCommutedVSHUFP*. Just have one function and check "ps" or "pd" using the number of elements using VT.getVectorNumElements() - but make sure to still check for 256-bits. 4) Why don't match when V2IsUndef? I suppose it's because you want the shuffle to be xformed to a "extract of the low part"+128_bit-shuffle later. If that's the case, add a comment saying that! Thanks -- Bruno Cardoso Lopes http://www.brunocardoso.cc --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. 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From baldrick at free.fr Tue Nov 8 08:46:46 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 08 Nov 2011 15:46:46 +0100 Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass In-Reply-To: <1320762963.19359.117.camel@sapling> References: <1319909412.23036.851.camel@sapling> <1319914924.23036.852.camel@sapling> <1319919418.23036.881.camel@sapling> <1319928991.23036.957.camel@sapling> <1320108633.23036.1266.camel@sapling> <1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling> <1320191694.23036.1497.camel@sapling> <1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling> Message-ID: <4EB940D6.2080208@free.fr> Hi Hal, > Generally, I've observed slowdowns from the introduction of too many > permutations per chain (the chain selection procedure can be changed to > help this, and I'll work on that). Also, sometimes legalization of > non-native vector operations creates inefficient code, and I'll also > look at these cases in more detail. the same problem applies when using LLVM to codegen the output of the GCC auto-vectorizer (you can do this using dragonegg): in some cases the code generators scalarize IR that maps directly to x86 instructions. There's a plan to have a codegen option output a message when it scalarizes something (probably this would be a private patch rather than something that would go into LLVM), and then systematically compile lots of code using the gcc auto-vectorizer and fix x86 until all such messages go away. Ciao, Duncan. From hfinkel at anl.gov Tue Nov 8 09:02:47 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 08 Nov 2011 09:02:47 -0600 Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass In-Reply-To: <4EB940D6.2080208@free.fr> References: <1319909412.23036.851.camel@sapling> <1319914924.23036.852.camel@sapling> <1319919418.23036.881.camel@sapling> <1319928991.23036.957.camel@sapling> <1320108633.23036.1266.camel@sapling> <1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling> <1320191694.23036.1497.camel@sapling> <1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling> <4EB940D6.2080208@free.fr> Message-ID: <1320764567.19359.124.camel@sapling> On Tue, 2011-11-08 at 15:46 +0100, Duncan Sands wrote: > Hi Hal, > > > Generally, I've observed slowdowns from the introduction of too many > > permutations per chain (the chain selection procedure can be changed to > > help this, and I'll work on that). Also, sometimes legalization of > > non-native vector operations creates inefficient code, and I'll also > > look at these cases in more detail. > > the same problem applies when using LLVM to codegen the output of the > GCC auto-vectorizer (you can do this using dragonegg): in some cases > the code generators scalarize IR that maps directly to x86 instructions. > There's a plan to have a codegen option output a message when it > scalarizes something (probably this would be a private patch rather than > something that would go into LLVM), and then systematically compile lots > of code using the gcc auto-vectorizer and fix x86 until all such messages > go away. This sounds like a great idea. I think that it would be perfectly appropriate to just add this to the general debug output. The base LLVM code generates more than O(#statements) debug output lines anyway, so it would not make it much more verbose than it already is. -Hal > > Ciao, Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From grosser at fim.uni-passau.de Tue Nov 8 09:41:03 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 08 Nov 2011 15:41:03 -0000 Subject: [llvm-commits] [polly] r144083 - in /polly/trunk: include/polly/ScopInfo.h lib/Analysis/ScopInfo.cpp Message-ID: <20111108154103.6DBA92A6C12C@llvm.org> Author: grosser Date: Tue Nov 8 09:41:03 2011 New Revision: 144083 URL: http://llvm.org/viewvc/llvm-project?rev=144083&view=rev Log: Use a map to store the dimension of the the parameters Modified: polly/trunk/include/polly/ScopInfo.h polly/trunk/lib/Analysis/ScopInfo.cpp Modified: polly/trunk/include/polly/ScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/ScopInfo.h?rev=144083&r1=144082&r2=144083&view=diff ============================================================================== --- polly/trunk/include/polly/ScopInfo.h (original) +++ polly/trunk/include/polly/ScopInfo.h Tue Nov 8 09:41:03 2011 @@ -38,6 +38,7 @@ class Type; } +struct isl_ctx; struct isl_map; struct isl_basic_map; struct isl_id; @@ -400,6 +401,13 @@ typedef SmallVector ParamVecType; ParamVecType Parameters; + /// The isl_ids that are used to represent the parameters + typedef std::map ParamIdType; + ParamIdType ParameterIds; + + // Isl context. + isl_ctx *IslCtx; + /// Constraints on parameters. isl_set *Context; Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144083&r1=144082&r2=144083&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Tue Nov 8 09:41:03 2011 @@ -846,21 +846,14 @@ //===----------------------------------------------------------------------===// /// Scop class implement -isl_id *Scop::getIdForParam(const SCEV *Parameter) const { - int i = 0; +__isl_give isl_id *Scop::getIdForParam(const SCEV *Parameter) const { + ParamIdType::const_iterator IdIter = ParameterIds.find(Parameter); - for (const_param_iterator PI = param_begin(), PE = param_end(); PI != PE; - ++PI) { - if (Parameter == *PI) { - std::string ParameterName = "p" + convertInt(i); - isl_id *id = isl_id_alloc(getIslCtx(), ParameterName.c_str(), - (void *) Parameter); - return id; - } - i++; - } + if (IdIter == ParameterIds.end()) + return NULL; - return NULL; + std::string ParameterName = "p" + convertInt(IdIter->second); + return isl_id_alloc(getIslCtx(), ParameterName.c_str(), (void *) Parameter); } void Scop::buildContext(isl_ctx *IslCtx, ParamSetType *ParamSet) { @@ -871,9 +864,8 @@ PI != PE; ++PI) { const SCEV *Parameter = *PI; Parameters.push_back(Parameter); - std::string ParameterName = "p" + convertInt(i); - isl_id *id = isl_id_alloc(IslCtx, ParameterName.c_str(), - (void *) Parameter); + ParameterIds.insert(std::pair(Parameter, i)); + isl_id *id = getIdForParam(Parameter); Space = isl_space_set_dim_id(Space, isl_dim_param, i, id); i++; } @@ -887,6 +879,7 @@ isl_ctx *Context) : SE(&ScalarEvolution), R(tempScop.getMaxRegion()), MaxLoopDepth(tempScop.getMaxLoopDepth()) { + IslCtx = Context; buildContext(Context, &tempScop.getParamSet()); SmallVector NestLoops; @@ -966,7 +959,7 @@ void Scop::dump() const { print(dbgs()); } -isl_ctx *Scop::getIslCtx() const { return isl_set_get_ctx(Context); } +isl_ctx *Scop::getIslCtx() const { return IslCtx; } ScalarEvolution *Scop::getSE() const { return SE; } From grosser at fim.uni-passau.de Tue Nov 8 09:41:08 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 08 Nov 2011 15:41:08 -0000 Subject: [llvm-commits] [polly] r144084 - in /polly/trunk: include/polly/ScopInfo.h lib/Analysis/ScopInfo.cpp Message-ID: <20111108154108.ECBBD2A6C12C@llvm.org> Author: grosser Date: Tue Nov 8 09:41:08 2011 New Revision: 144084 URL: http://llvm.org/viewvc/llvm-project?rev=144084&view=rev Log: ScopInfo: Realign parameters after the scop is built Modified: polly/trunk/include/polly/ScopInfo.h polly/trunk/lib/Analysis/ScopInfo.cpp Modified: polly/trunk/include/polly/ScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/ScopInfo.h?rev=144084&r1=144083&r2=144084&view=diff ============================================================================== --- polly/trunk/include/polly/ScopInfo.h (original) +++ polly/trunk/include/polly/ScopInfo.h Tue Nov 8 09:41:08 2011 @@ -154,6 +154,10 @@ /// @brief Set the updated access relation read from JSCOP file. void setNewAccessRelation(isl_map *newAccessRelation); + + /// @brief Align the parameters in the access relation to the scop context + void realignParams(); + /// @brief Print the MemoryAccess. /// /// @param OS The output stream the MemoryAccess is printed to. @@ -345,6 +349,9 @@ /// that all data used in the Scop is read after the Scop. bool isFinalRead() { return getBasicBlock() == NULL; } + /// @brief Align the parameters in the statement to the scop context + void realignParams(); + /// @brief Print the ScopStmt. /// /// @param OS The output stream the ScopStmt is printed to. @@ -540,6 +547,9 @@ const_reverse_iterator rend() const { return Stmts.rend(); } //@} + /// @brief Align the parameters in the statement to the scop context + void realignParams(); + /// @brief Print the static control part. /// /// @param OS The output stream the static control part is printed to. Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144084&r1=144083&r2=144084&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Tue Nov 8 09:41:08 2011 @@ -342,8 +342,10 @@ Statement->getBaseName()); AccessRelation = isl_map_set_tuple_name(AccessRelation, isl_dim_out, getBaseName().c_str()); +} - isl_space *ParamSpace = Statement->getParent()->getParamSpace(); +void MemoryAccess::realignParams() { + isl_space *ParamSpace = statement->getParent()->getParamSpace(); AccessRelation = isl_map_align_params(AccessRelation, ParamSpace); } @@ -587,6 +589,14 @@ } } +void ScopStmt::realignParams() { + for (memacc_iterator MI = memacc_begin(), ME = memacc_end(); MI != ME; ++MI) + (*MI)->realignParams(); + + Domain = isl_set_align_params(Domain, Parent.getParamSpace()); + Scattering = isl_map_align_params(Scattering, Parent.getParamSpace()); +} + __isl_give isl_set *ScopStmt::buildConditionSet(const Comparison &Comp) const { isl_pw_aff *L = SCEVAffinator::getPwAff(this, Comp.getLHS()->OriginalSCEV, 0); @@ -676,7 +686,6 @@ Space = isl_space_set_alloc(getIslCtx(), 0, getNumIterators()); Domain = isl_set_universe(Space); - Domain = isl_set_align_params(Domain, Parent.getParamSpace()); Domain = addLoopBoundsToDomain(Domain, tempScop); Domain = addConditionsToDomain(Domain, tempScop, CurRegion); Domain = isl_set_set_tuple_name(Domain, getBaseName()); @@ -717,7 +726,6 @@ std::string IterationDomainString = "{[i0] : i0 = 0}"; Domain = isl_set_read_from_str(getIslCtx(), IterationDomainString.c_str()); Domain = isl_set_set_tuple_name(Domain, getBaseName()); - Domain = isl_set_align_params(Domain, parent.getParamSpace()); // Build scattering. unsigned ScatSpace = Parent.getMaxLoopDepth() * 2 + 1; @@ -740,7 +748,6 @@ bmap = isl_basic_map_add_constraint(bmap, c); isl_int_clear(v); Scattering = isl_map_from_basic_map(bmap); - Scattering = isl_map_align_params(Scattering, parent.getParamSpace()); // Build memory accesses, use SetVector to keep the order of memory accesses // and prevent the same memory access inserted more than once. @@ -875,6 +882,11 @@ Context = isl_set_universe (Space); } +void Scop::realignParams() { + for (iterator I = begin(), E = end(); I != E; ++I) + (*I)->realignParams(); +} + Scop::Scop(TempScop &tempScop, LoopInfo &LI, ScalarEvolution &ScalarEvolution, isl_ctx *Context) : SE(&ScalarEvolution), R(tempScop.getMaxRegion()), @@ -892,6 +904,8 @@ buildScop(tempScop, getRegion(), NestLoops, Scatter, LI); Stmts.push_back(new ScopStmt(*this, Scatter)); + realignParams(); + assert(NestLoops.empty() && "NestLoops not empty at top level!"); } From grosser at fim.uni-passau.de Tue Nov 8 09:41:14 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 08 Nov 2011 15:41:14 -0000 Subject: [llvm-commits] [polly] r144085 - in /polly/trunk: include/polly/ScopInfo.h lib/Analysis/ScopInfo.cpp Message-ID: <20111108154114.3CA2C2A6C12C@llvm.org> Author: grosser Date: Tue Nov 8 09:41:13 2011 New Revision: 144085 URL: http://llvm.org/viewvc/llvm-project?rev=144085&view=rev Log: ScopInfo: Don't add common parameters during realignment to the context. Previously we built a context that contained already all parameter dimensions from the start. We now build a context without any parameter dimensions and extend the context as needed. All parameter dimensions are added during final realignment. Modified: polly/trunk/include/polly/ScopInfo.h polly/trunk/lib/Analysis/ScopInfo.cpp Modified: polly/trunk/include/polly/ScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/ScopInfo.h?rev=144085&r1=144084&r2=144085&view=diff ============================================================================== --- polly/trunk/include/polly/ScopInfo.h (original) +++ polly/trunk/include/polly/ScopInfo.h Tue Nov 8 09:41:13 2011 @@ -433,11 +433,11 @@ /// @return True if the basic block is trivial, otherwise false. static bool isTrivialBB(BasicBlock *BB, TempScop &tempScop); + /// @brief Add the parameters to the internal parameter set. + void initializeParameters(ParamSetType *ParamSet); + /// @brief Build the Context of the Scop. - /// - /// @param IslCtx The isl context to use. - /// @param ParamSet The list of all parameters in the SCoP. - void buildContext(isl_ctx *IslCtx, ParamSetType *ParamSet); + void buildContext(); /// Build the Scop and Statement with precalculate scop information. void buildScop(TempScop &TempScop, const Region &CurRegion, Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144085&r1=144084&r2=144085&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Tue Nov 8 09:41:13 2011 @@ -863,26 +863,36 @@ return isl_id_alloc(getIslCtx(), ParameterName.c_str(), (void *) Parameter); } -void Scop::buildContext(isl_ctx *IslCtx, ParamSetType *ParamSet) { - isl_space *Space = isl_space_params_alloc(IslCtx, ParamSet->size()); - +void Scop::initializeParameters(ParamSetType *ParamSet) { int i = 0; for (ParamSetType::iterator PI = ParamSet->begin(), PE = ParamSet->end(); PI != PE; ++PI) { const SCEV *Parameter = *PI; Parameters.push_back(Parameter); ParameterIds.insert(std::pair(Parameter, i)); - isl_id *id = getIdForParam(Parameter); - Space = isl_space_set_dim_id(Space, isl_dim_param, i, id); i++; } +} - // TODO: Insert relations between parameters. - // TODO: Insert constraints on parameters. +void Scop::buildContext() { + isl_space *Space = isl_space_params_alloc(IslCtx, 0); Context = isl_set_universe (Space); } void Scop::realignParams() { + // Add all parameters into a common model. + isl_space *Space = isl_space_params_alloc(IslCtx, Parameters.size()); + + for (ParamIdType::iterator PI = ParameterIds.begin(), PE = ParameterIds.end(); + PI != PE; ++PI) { + const SCEV *Parameter = PI->first; + isl_id *id = getIdForParam(Parameter); + Space = isl_space_set_dim_id(Space, isl_dim_param, PI->second, id); + } + + // Align the parameters of all data structures to the model. + Context = isl_set_align_params(Context, Space); + for (iterator I = begin(), E = end(); I != E; ++I) (*I)->realignParams(); } @@ -892,7 +902,8 @@ : SE(&ScalarEvolution), R(tempScop.getMaxRegion()), MaxLoopDepth(tempScop.getMaxLoopDepth()) { IslCtx = Context; - buildContext(Context, &tempScop.getParamSet()); + initializeParameters(&tempScop.getParamSet()); + buildContext(); SmallVector NestLoops; SmallVector Scatter; From grosser at fim.uni-passau.de Tue Nov 8 09:41:19 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 08 Nov 2011 15:41:19 -0000 Subject: [llvm-commits] [polly] r144086 - in /polly/trunk: include/polly/ScopInfo.h lib/Analysis/ScopInfo.cpp Message-ID: <20111108154119.960982A6C12C@llvm.org> Author: grosser Date: Tue Nov 8 09:41:19 2011 New Revision: 144086 URL: http://llvm.org/viewvc/llvm-project?rev=144086&view=rev Log: Remove const Modified: polly/trunk/include/polly/ScopInfo.h polly/trunk/lib/Analysis/ScopInfo.cpp Modified: polly/trunk/include/polly/ScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/ScopInfo.h?rev=144086&r1=144085&r2=144086&view=diff ============================================================================== --- polly/trunk/include/polly/ScopInfo.h (original) +++ polly/trunk/include/polly/ScopInfo.h Tue Nov 8 09:41:19 2011 @@ -261,14 +261,14 @@ /// Build the statment. //@{ - __isl_give isl_set *buildConditionSet(const Comparison &Cmp) const; + __isl_give isl_set *buildConditionSet(const Comparison &Cmp); __isl_give isl_set *addConditionsToDomain(__isl_take isl_set *Domain, TempScop &tempScop, - const Region &CurRegion) const; + const Region &CurRegion); __isl_give isl_set *addLoopBoundsToDomain(__isl_take isl_set *Domain, TempScop &tempScop) const; __isl_give isl_set *buildDomain(TempScop &tempScop, - const Region &CurRegion) const; + const Region &CurRegion); void buildScattering(SmallVectorImpl &Scatter); void buildAccesses(TempScop &tempScop, const Region &CurRegion); //@} Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144086&r1=144085&r2=144086&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Tue Nov 8 09:41:19 2011 @@ -597,7 +597,7 @@ Scattering = isl_map_align_params(Scattering, Parent.getParamSpace()); } -__isl_give isl_set *ScopStmt::buildConditionSet(const Comparison &Comp) const { +__isl_give isl_set *ScopStmt::buildConditionSet(const Comparison &Comp) { isl_pw_aff *L = SCEVAffinator::getPwAff(this, Comp.getLHS()->OriginalSCEV, 0); isl_pw_aff *R = SCEVAffinator::getPwAff(this, Comp.getRHS()->OriginalSCEV, 0); @@ -656,8 +656,7 @@ __isl_give isl_set *ScopStmt::addConditionsToDomain(__isl_take isl_set *Domain, TempScop &tempScop, - const Region &CurRegion) - const { + const Region &CurRegion) { const Region *TopRegion = tempScop.getMaxRegion().getParent(), *CurrentRegion = &CurRegion; const BasicBlock *BranchingBB = BB; @@ -679,7 +678,7 @@ } __isl_give isl_set *ScopStmt::buildDomain(TempScop &tempScop, - const Region &CurRegion) const { + const Region &CurRegion) { isl_space *Space; isl_set *Domain; From grosser at fim.uni-passau.de Tue Nov 8 09:41:28 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Tue, 08 Nov 2011 15:41:28 -0000 Subject: [llvm-commits] [polly] r144087 - in /polly/trunk: include/polly/ScopInfo.h include/polly/Support/SCEVValidator.h lib/Analysis/ScopDetection.cpp lib/Analysis/ScopInfo.cpp lib/Analysis/TempScopInfo.cpp lib/Support/SCEVValidator.cpp test/ScopInfo/20111108-Parameter-not-detected.ll Message-ID: <20111108154128.8800D1BE001@llvm.org> Author: grosser Date: Tue Nov 8 09:41:28 2011 New Revision: 144087 URL: http://llvm.org/viewvc/llvm-project?rev=144087&view=rev Log: Detect Parameters directly on the SCEV. Instead of using TempScop to find parameters, we detect them directly on the SCEV. This allows us to remove the TempScop parameter detection in a subsequent commit. This fixes a bug reported by Marcello Maggioni Added: polly/trunk/test/ScopInfo/20111108-Parameter-not-detected.ll Modified: polly/trunk/include/polly/ScopInfo.h polly/trunk/include/polly/Support/SCEVValidator.h polly/trunk/lib/Analysis/ScopDetection.cpp polly/trunk/lib/Analysis/ScopInfo.cpp polly/trunk/lib/Analysis/TempScopInfo.cpp polly/trunk/lib/Support/SCEVValidator.cpp Modified: polly/trunk/include/polly/ScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/ScopInfo.h?rev=144087&r1=144086&r2=144087&view=diff ============================================================================== --- polly/trunk/include/polly/ScopInfo.h (original) +++ polly/trunk/include/polly/ScopInfo.h Tue Nov 8 09:41:28 2011 @@ -266,7 +266,7 @@ TempScop &tempScop, const Region &CurRegion); __isl_give isl_set *addLoopBoundsToDomain(__isl_take isl_set *Domain, - TempScop &tempScop) const; + TempScop &tempScop); __isl_give isl_set *buildDomain(TempScop &tempScop, const Region &CurRegion); void buildScattering(SmallVectorImpl &Scatter); @@ -433,9 +433,6 @@ /// @return True if the basic block is trivial, otherwise false. static bool isTrivialBB(BasicBlock *BB, TempScop &tempScop); - /// @brief Add the parameters to the internal parameter set. - void initializeParameters(ParamSetType *ParamSet); - /// @brief Build the Context of the Scop. void buildContext(); @@ -470,6 +467,8 @@ /// @return The set containing the parameters used in this Scop. inline const ParamVecType &getParams() const { return Parameters; } + /// @brief Take a list of parameters and add the new ones to the scop. + void addParams(std::vector NewParameters); /// @brief Return the isl_id that represents a certain parameter. /// Modified: polly/trunk/include/polly/Support/SCEVValidator.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/Support/SCEVValidator.h?rev=144087&r1=144086&r2=144087&view=diff ============================================================================== --- polly/trunk/include/polly/Support/SCEVValidator.h (original) +++ polly/trunk/include/polly/Support/SCEVValidator.h Tue Nov 8 09:41:28 2011 @@ -12,6 +12,8 @@ #ifndef POLLY_SCEV_VALIDATOR_H #define POLLY_SCEV_VALIDATOR_H +#include + namespace llvm { class Region; class SCEV; @@ -22,6 +24,12 @@ namespace polly { bool isAffineExpr(const llvm::Region *R, const llvm::SCEV *Expression, llvm::ScalarEvolution &SE, llvm::Value **BaseAddress = 0); + std::vector getParamsInAffineExpr( + const llvm::Region *R, + const llvm::SCEV *Expression, + llvm::ScalarEvolution &SE, + llvm::Value **BaseAddress = 0); + } #endif Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=144087&r1=144086&r2=144087&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Tue Nov 8 09:41:28 2011 @@ -61,6 +61,8 @@ #define DEBUG_TYPE "polly-detect" #include "llvm/Support/Debug.h" +#include + using namespace llvm; using namespace polly; Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144087&r1=144086&r2=144087&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Tue Nov 8 09:41:28 2011 @@ -23,6 +23,7 @@ #include "polly/LinkAllPasses.h" #include "polly/Support/GICHelper.h" #include "polly/Support/ScopHelper.h" +#include "polly/Support/SCEVValidator.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/ScalarEvolutionExpressions.h" @@ -80,8 +81,18 @@ const Value *baseAddress; public: - static isl_pw_aff *getPwAff(const ScopStmt *stmt, const SCEV *scev, + static isl_pw_aff *getPwAff(ScopStmt *stmt, const SCEV *scev, const Value *baseAddress = 0) { + Scop *S = stmt->getParent(); + const Region *Reg = &S->getRegion(); + + if (baseAddress) { + Value *Base; + S->addParams(getParamsInAffineExpr(Reg, scev, *S->getSE(), &Base)); + } else { + S->addParams(getParamsInAffineExpr(Reg, scev, *S->getSE())); + } + SCEVAffinator Affinator(stmt, baseAddress); return Affinator.visit(scev); } @@ -598,7 +609,6 @@ } __isl_give isl_set *ScopStmt::buildConditionSet(const Comparison &Comp) { - isl_pw_aff *L = SCEVAffinator::getPwAff(this, Comp.getLHS()->OriginalSCEV, 0); isl_pw_aff *R = SCEVAffinator::getPwAff(this, Comp.getRHS()->OriginalSCEV, 0); @@ -626,7 +636,7 @@ } __isl_give isl_set *ScopStmt::addLoopBoundsToDomain(__isl_take isl_set *Domain, - TempScop &tempScop) const { + TempScop &tempScop) { isl_space *Space; isl_local_space *LocalSpace; @@ -852,6 +862,22 @@ //===----------------------------------------------------------------------===// /// Scop class implement + +void Scop::addParams(std::vector NewParameters) { + for (std::vector::iterator PI = NewParameters.begin(), + PE = NewParameters.end(); PI != PE; ++PI) { + const SCEV *Parameter = *PI; + + if (ParameterIds.find(Parameter) != ParameterIds.end()) + continue; + + int dimension = Parameters.size(); + + Parameters.push_back(Parameter); + ParameterIds[Parameter] = dimension; + } +} + __isl_give isl_id *Scop::getIdForParam(const SCEV *Parameter) const { ParamIdType::const_iterator IdIter = ParameterIds.find(Parameter); @@ -862,17 +888,6 @@ return isl_id_alloc(getIslCtx(), ParameterName.c_str(), (void *) Parameter); } -void Scop::initializeParameters(ParamSetType *ParamSet) { - int i = 0; - for (ParamSetType::iterator PI = ParamSet->begin(), PE = ParamSet->end(); - PI != PE; ++PI) { - const SCEV *Parameter = *PI; - Parameters.push_back(Parameter); - ParameterIds.insert(std::pair(Parameter, i)); - i++; - } -} - void Scop::buildContext() { isl_space *Space = isl_space_params_alloc(IslCtx, 0); Context = isl_set_universe (Space); @@ -880,7 +895,7 @@ void Scop::realignParams() { // Add all parameters into a common model. - isl_space *Space = isl_space_params_alloc(IslCtx, Parameters.size()); + isl_space *Space = isl_space_params_alloc(IslCtx, ParameterIds.size()); for (ParamIdType::iterator PI = ParameterIds.begin(), PE = ParameterIds.end(); PI != PE; ++PI) { @@ -901,7 +916,6 @@ : SE(&ScalarEvolution), R(tempScop.getMaxRegion()), MaxLoopDepth(tempScop.getMaxLoopDepth()) { IslCtx = Context; - initializeParameters(&tempScop.getParamSet()); buildContext(); SmallVector NestLoops; @@ -964,6 +978,14 @@ } OS.indent(4) << getContextStr() << "\n"; + + for (ParamVecType::const_iterator PI = Parameters.begin(), + PE = Parameters.end(); PI != PE; ++PI) { + const SCEV *Parameter = *PI; + int Dim = ParameterIds.find(Parameter)->second; + + OS.indent(4) << "p" << Dim << ": " << *Parameter << "\n"; + } } void Scop::printStatements(raw_ostream &OS) const { Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144087&r1=144086&r2=144087&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Tue Nov 8 09:41:28 2011 @@ -19,6 +19,7 @@ #include "polly/Support/AffineSCEVIterator.h" #include "polly/Support/GICHelper.h" #include "polly/Support/ScopHelper.h" +#include "polly/Support/SCEVValidator.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/RegionIterator.h" Modified: polly/trunk/lib/Support/SCEVValidator.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/SCEVValidator.cpp?rev=144087&r1=144086&r2=144087&view=diff ============================================================================== --- polly/trunk/lib/Support/SCEVValidator.cpp (original) +++ polly/trunk/lib/Support/SCEVValidator.cpp Tue Nov 8 09:41:28 2011 @@ -5,6 +5,8 @@ #include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/Analysis/RegionInfo.h" +#include + using namespace llvm; namespace SCEVType { @@ -13,14 +15,19 @@ struct ValidatorResult { SCEVType::TYPE type; + std::vector Parameters; ValidatorResult() : type(SCEVType::INVALID) {}; ValidatorResult(const ValidatorResult &vres) { type = vres.type; + Parameters = vres.Parameters; }; ValidatorResult(SCEVType::TYPE type) : type(type) {}; + ValidatorResult(SCEVType::TYPE type, const SCEV* Expr) : type(type) { + Parameters.push_back(Expr); + }; bool isConstant() { return type == SCEVType::INT || type == SCEVType::PARAM; @@ -37,6 +44,11 @@ bool isINT() { return type == SCEVType::INT; } + + void addParamsFrom(struct ValidatorResult &Source) { + Parameters.insert(Parameters.end(), Source.Parameters.begin(), + Source.Parameters.end()); + } }; /// Check if a SCEV is valid in a SCoP. @@ -63,7 +75,7 @@ // expression. If it is constant during Scop execution, we treat it as a // parameter, otherwise we bail out. if (Op.isConstant()) - return ValidatorResult(SCEVType::PARAM); + return ValidatorResult(SCEVType::PARAM, Expr); return ValidatorResult (SCEVType::INVALID); } @@ -75,7 +87,7 @@ // expression. If it is constant during Scop execution, we treat it as a // parameter, otherwise we bail out. if (Op.isConstant()) - return ValidatorResult (SCEVType::PARAM); + return ValidatorResult (SCEVType::PARAM, Expr); return ValidatorResult(SCEVType::INVALID); } @@ -98,6 +110,7 @@ return ValidatorResult(SCEVType::INVALID); Return.type = std::max(Return.type, Op.type); + Return.addParamsFrom(Op); } // TODO: Check for NSW and NUW. @@ -117,6 +130,7 @@ return ValidatorResult(SCEVType::INVALID); Return.type = Op.type; + Return.addParamsFrom(Op); } // TODO: Check for NSW and NUW. @@ -131,7 +145,7 @@ // expression. If the division is constant during Scop execution we treat it // as a parameter, otherwise we bail out. if (LHS.isConstant() && RHS.isConstant()) - return ValidatorResult(SCEVType::PARAM); + return ValidatorResult(SCEVType::PARAM, Expr); return ValidatorResult(SCEVType::INVALID); } @@ -151,13 +165,15 @@ if (Start.isIV()) return ValidatorResult(SCEVType::INVALID); else - return ValidatorResult(SCEVType::PARAM); + return ValidatorResult(SCEVType::PARAM, Expr); } if (!Recurrence.isINT()) return ValidatorResult(SCEVType::INVALID); - return ValidatorResult(SCEVType::IV); + ValidatorResult Result(SCEVType::IV); + Result.addParamsFrom(Start); + return Result; } struct ValidatorResult visitSMaxExpr(const SCEVSMaxExpr* Expr) { @@ -170,12 +186,15 @@ return ValidatorResult(SCEVType::INVALID); Return.type = std::max(Return.type, Op.type); + Return.addParamsFrom(Op); } return Return; } struct ValidatorResult visitUMaxExpr(const SCEVUMaxExpr* Expr) { + ValidatorResult Return(SCEVType::PARAM); + // We do not support unsigned operations. If 'Expr' is constant during Scop // execution we treat this as a parameter, otherwise we bail out. for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) { @@ -183,9 +202,11 @@ if (!Op.isConstant()) return ValidatorResult(SCEVType::INVALID); + + Return.addParamsFrom(Op); } - return ValidatorResult(SCEVType::PARAM); + return Return; } ValidatorResult visitUnknown(const SCEVUnknown* Expr) { @@ -208,7 +229,7 @@ if (BaseAddress) return ValidatorResult(SCEVType::PARAM); else - return ValidatorResult(SCEVType::PARAM); + return ValidatorResult(SCEVType::PARAM, Expr); } }; @@ -226,6 +247,22 @@ return Result.isValid(); } + + std::vector getParamsInAffineExpr(const Region *R, + const SCEV *Expr, + ScalarEvolution &SE, + Value **BaseAddress) { + if (isa(Expr)) + return std::vector(); + + if (BaseAddress) + *BaseAddress = NULL; + + SCEVValidator Validator(R, SE, BaseAddress); + ValidatorResult Result = Validator.visit(Expr); + + return Result.Parameters; + } } Added: polly/trunk/test/ScopInfo/20111108-Parameter-not-detected.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/20111108-Parameter-not-detected.ll?rev=144087&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/20111108-Parameter-not-detected.ll (added) +++ polly/trunk/test/ScopInfo/20111108-Parameter-not-detected.ll Tue Nov 8 09:41:28 2011 @@ -0,0 +1,56 @@ +; RUN: opt %loadPolly %defaultOpts -polly-scops -analyze < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +declare void @foo() + +define i32 @main(i8* %A) nounwind uwtable { +entry: + br label %for.cond + +for.cond: ; preds = %for.inc5, %entry + %indvar_out = phi i64 [ %indvar_out.next, %for.inc5 ], [ 0, %entry ] + call void @foo() + %tmp = add i64 %indvar_out, 2 + %exitcond5 = icmp ne i64 %indvar_out, 1023 + br i1 %exitcond5, label %for.body, label %for.end7 + +for.body: ; preds = %for.cond + br label %for.cond1 + +for.cond1: ; preds = %for.inc, %for.body + %indvar = phi i64 [ %indvar.next, %for.inc ], [ 0, %for.body ] + %exitcond = icmp ne i64 %indvar, 1023 + br i1 %exitcond, label %for.body3, label %for.end + +for.body3: ; preds = %for.cond1 + %tmp1 = add i64 %tmp, %indvar + %cmp4 = icmp sgt i64 %tmp1, 1000 + br i1 %cmp4, label %if.then, label %if.end + +if.then: ; preds = %for.body3 + %arrayidx = getelementptr i8* %A, i64 %indvar + store i8 5, i8* %arrayidx + br label %if.end + +if.end: ; preds = %if.end.single_exit + br label %for.inc + +for.inc: ; preds = %if.end + %indvar.next = add i64 %indvar, 1 + br label %for.cond1 + +for.end: ; preds = %for.cond1 + br label %for.inc5 + +for.inc5: ; preds = %for.end + %indvar_out.next = add i64 %indvar_out, 1 + br label %for.cond + +for.end7: ; preds = %for.cond + ret i32 0 +} + +; CHECK: Domain := +; CHECK: [p0] -> { Stmt_if_then[i0] : i0 >= 0 and i0 <= 1022 and i0 >= 1001 - p0 }; + From clattner at apple.com Tue Nov 8 12:17:32 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 08 Nov 2011 10:17:32 -0800 Subject: [llvm-commits] [llvm] r144034 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll In-Reply-To: <20111107225110.47D172A6C12C@llvm.org> References: <20111107225110.47D172A6C12C@llvm.org> Message-ID: <64700A7C-488A-43B3-AC47-1102DA3752AC@apple.com> On Nov 7, 2011, at 2:51 PM, Eli Friedman wrote: > Author: efriedma > Date: Mon Nov 7 16:51:10 2011 > New Revision: 144034 > > URL: http://llvm.org/viewvc/llvm-project?rev=144034&view=rev > Log: > Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization doesn't get confused by CSE later on. Fixes PR11318. Should there be a new SelectionDAG method that does both RAUW + RemoveDeadNode's? Should RAUW itself do this? -Chris > > > Added: > llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=144034&r1=144033&r2=144034&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 7 16:51:10 2011 > @@ -285,6 +285,7 @@ > Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), > ST->isVolatile(), ST->isNonTemporal(), Alignment); > DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); > + DAG.RemoveDeadNode(ST, DUL); > return; > } > // Do a (aligned) store to a stack slot, then copy from the stack slot > @@ -349,6 +350,7 @@ > DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], > Stores.size()); > DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); > + DAG.RemoveDeadNode(ST, DUL); > return; > } > assert(ST->getMemoryVT().isInteger() && > @@ -381,6 +383,7 @@ > SDValue Result = > DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); > DAG.ReplaceAllUsesWith(SDValue(ST, 0), Result, DUL); > + DAG.RemoveDeadNode(ST, DUL); > } > > /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. > @@ -1144,6 +1147,7 @@ > if (!ST->isTruncatingStore()) { > if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { > DAG.ReplaceAllUsesWith(ST, OptStore, this); > + DAG.RemoveDeadNode(ST, this); > break; > } > > @@ -1169,8 +1173,10 @@ > break; > case TargetLowering::Custom: > Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG); > - if (Tmp1.getNode()) > + if (Tmp1.getNode()) { > DAG.ReplaceAllUsesWith(SDValue(Node, 0), Tmp1, this); > + DAG.RemoveDeadNode(Node, this); > + } > break; > case TargetLowering::Promote: { > assert(VT.isVector() && "Unknown legal promote case!"); > @@ -1181,6 +1187,7 @@ > ST->getPointerInfo(), isVolatile, > isNonTemporal, Alignment); > DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); > + DAG.RemoveDeadNode(Node, this); > break; > } > } > @@ -1203,6 +1210,7 @@ > DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), > NVT, isVolatile, isNonTemporal, Alignment); > DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); > + DAG.RemoveDeadNode(Node, this); > } else if (StWidth & (StWidth - 1)) { > // If not storing a power-of-2 number of bits, expand as two stores. > assert(!StVT.isVector() && "Unsupported truncstore!"); > @@ -1258,6 +1266,7 @@ > // The order of the stores doesn't matter. > SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); > DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); > + DAG.RemoveDeadNode(Node, this); > } else { > if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || > Tmp2 != ST->getBasePtr()) > @@ -1280,6 +1289,7 @@ > DAG.ReplaceAllUsesWith(SDValue(Node, 0), > TLI.LowerOperation(SDValue(Node, 0), DAG), > this); > + DAG.RemoveDeadNode(Node, this); > break; > case TargetLowering::Expand: > assert(!StVT.isVector() && > @@ -1292,6 +1302,7 @@ > DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), > isVolatile, isNonTemporal, Alignment); > DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); > + DAG.RemoveDeadNode(Node, this); > break; > } > } > @@ -3361,6 +3372,7 @@ > DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), > &Scalars[0], Scalars.size()); > DAG.ReplaceAllUsesWith(SDValue(Node, 0), Result, this); > + DAG.RemoveDeadNode(Node, this); > break; > } > case ISD::GLOBAL_OFFSET_TABLE: > @@ -3377,8 +3389,10 @@ > } > > // Replace the original node with the legalized result. > - if (!Results.empty()) > + if (!Results.empty()) { > DAG.ReplaceAllUsesWith(Node, Results.data(), this); > + DAG.RemoveDeadNode(Node, this); > + } > } > > void SelectionDAGLegalize::PromoteNode(SDNode *Node) { > @@ -3512,8 +3526,10 @@ > } > > // Replace the original node with the legalized result. > - if (!Results.empty()) > + if (!Results.empty()) { > DAG.ReplaceAllUsesWith(Node, Results.data(), this); > + DAG.RemoveDeadNode(Node, this); > + } > } > > // SelectionDAG::Legalize - This is the entry point for the file. > > Added: llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll?rev=144034&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll (added) > +++ llvm/trunk/test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll Mon Nov 7 16:51:10 2011 > @@ -0,0 +1,14 @@ > +; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s > + > +; We don't really care what this outputs; just make sure it's somewhat sane. > +; CHECK: legalize_test > +; CHECK: vmovups > +define void @legalize_test(i32 %x, <8 x i32>* %p) nounwind { > +entry: > + %t1 = insertelement <8 x i32> , i32 %x, i32 0 > + %t2 = shufflevector <8 x i32> %t1, <8 x i32> zeroinitializer, <8 x i32> > + %int2float = sitofp <8 x i32> %t2 to <8 x float> > + %blendAsInt.i821 = bitcast <8 x float> %int2float to <8 x i32> > + store <8 x i32> %blendAsInt.i821, <8 x i32>* %p, align 4 > + ret void > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Tue Nov 8 12:22:25 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 08 Nov 2011 18:22:25 -0000 Subject: [llvm-commits] [llvm] r144095 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Message-ID: <20111108182226.05B002A6C12C@llvm.org> Author: echristo Date: Tue Nov 8 12:22:25 2011 New Revision: 144095 URL: http://llvm.org/viewvc/llvm-project?rev=144095&view=rev Log: Don't evaluate Data.size() on every iteration. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp?rev=144095&r1=144094&r2=144095&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Tue Nov 8 12:22:25 2011 @@ -43,7 +43,7 @@ } DwarfAccelTable::~DwarfAccelTable() { - for (size_t i = 0 ; i < Data.size(); ++i) + for (size_t i = 0, e = Data.size() ; i < e; ++i) delete Data[i]; } From tonic at nondot.org Tue Nov 8 12:28:35 2011 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 08 Nov 2011 18:28:35 -0000 Subject: [llvm-commits] [www] r144096 - /www/trunk/devmtg/2011-11/index.html Message-ID: <20111108182835.A41912A6C12C@llvm.org> Author: tbrethou Date: Tue Nov 8 12:28:35 2011 New Revision: 144096 URL: http://llvm.org/viewvc/llvm-project?rev=144096&view=rev Log: Update agenda with rooms, move a talk, add a speaker. Modified: www/trunk/devmtg/2011-11/index.html Modified: www/trunk/devmtg/2011-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=144096&r1=144095&r2=144096&view=diff ============================================================================== --- www/trunk/devmtg/2011-11/index.html (original) +++ www/trunk/devmtg/2011-11/index.html Tue Nov 8 12:28:35 2011 @@ -83,49 +83,49 @@ TimeTalkLocation -9:00 - 9:20Welcome
Chris Lattner, Apple Inc.Main Hall +9:00 - 9:20Welcome
Chris Lattner, Apple Inc.Ballroom Salon III/IV -9:20 - 10:05Integrating LLVM into FreeBSD
Brooks Davis, The FreeBSD ProjectMain Hall -Intel OpenCL SDK Vectorizer
Nadav Rotem, IntelSecond Hall +9:20 - 10:05Using clang in the Chromium project
Nico Weber, Hans Wennborg, GoogleBallroom Salon III/IV +Intel OpenCL SDK Vectorizer
Nadav Rotem, IntelBallroom Salon V/VI -10:05 - 10:50Clang MapReduce -- Automatic C++ Refactoring at Google Scale
Chandler Carruth, GoogleMain Hall -PTX Back-End: GPU Programming With LLVM
Justin Holewinski, Ohio StateSecond Hall -Improving LLVM Testing BOF
David BlaikieTBD +10:05 - 10:50Clang MapReduce -- Automatic C++ Refactoring at Google Scale
Chandler Carruth, GoogleBallroom Salon III/IV +PTX Back-End: GPU Programming With LLVM
Justin Holewinski, Ohio StateBallroom Salon V/VI +Improving LLVM Testing BOF
David BlaikieBallroom Salon II 10:50 - 11:05BreakTBD -11:05 - 11:50Extending Clang
Doug Gregor, Apple Inc.Main Hall -Porting LLVM to a Next Generation DSP
Taylor Simpson, QuICSecond Hall +11:05 - 11:50Extending Clang
Doug Gregor, Apple Inc.Ballroom Salon III/IV +Porting LLVM to a Next Generation DSP
Taylor Simpson, QuICBallroom Salon V/VI -11:50 - 12:35DXR: Semantic Code Browsing with Clang
Joshua Cranmer, MozillaMain Hall -LLVM MC In Practice
Jim Grosbach, Owen Anderson Apple Inc.Second Hall +11:50 - 12:35DXR: Semantic Code Browsing with Clang
Joshua Cranmer, MozillaBallroom Salon III/IV +LLVM MC In Practice
Jim Grosbach, Owen Anderson Apple Inc.Ballroom Salon V/VI 12:35 - 1:35LunchTBD -1:35 - 2:20Using clang in the Chromium project
Nico Weber, Hans Wennborg, GoogleMain Hall -Polly - First successful optimizations - How to proceed?
Tobias Grosser, ENS/INRIASecond Hall -MC Linkers BOF
Luba Tang, MediatekTBD - -2:20 - 3:05Android Renderscript
Stephen Hines, GoogleMain Hall -SKIR: Just-in-Time Compilation for Parallelism with LLVM
Jeff Fifield, University of ColoradoSecond Hall -Improving the Clang Driver BOF
James Molloy, ARMTBD +1:35 - 2:20Integrating LLVM into FreeBSD
Brooks Davis, The FreeBSD ProjectBallroom Salon III/IV +Polly - First successful optimizations - How to proceed?
Tobias Grosser, ENS/INRIABallroom Salon V/VI +MC Linkers BOF
Luba Tang, Mediateki, Shih-wei Liao, GoogleBallroom Salon II + +2:20 - 3:05Android Renderscript
Stephen Hines, GoogleBallroom Salon III/IV +SKIR: Just-in-Time Compilation for Parallelism with LLVM
Jeff Fifield, University of ColoradoBallroom Salon V/VI +Improving the Clang Driver BOF
James Molloy, ARMBallroom Salon II 3:05 - 3:45PostersTBD -LunarGLASS: A LLVM-based shader compiler stack
Michael Ilseman, LunarGTBD -Symbolic Testing of OpenCL Code
Peter Collingbourne, Imperial College LondonTBD -Code verification based on attributes annotation - Implementing custom attributes check using Clang
Michael Han, AutodeskTBD -Parfait - A Scalable Static Bug-Checking Tool Built on LLVM
Cristina Cifuentes, Nathan Keynes, Andrew Craik, Lian Li, Nathan Hawes, Andrew Browne, and Manuel Valdiviezo, Oracle LabsTBD - -3:45 - 4:30Register Allocation in LLVM 3.0
Jakob Olesen, AppleMain Hall -Exporting 3D scenes from Maya to WebGL using clang and LLVM
Jochen Wilhelmy, consultantSecond Hall - -4:30 - 5:15Super-optimizing LLVM IR
Duncan Sands, DeepBlueCapitalMain Hall -Finding races and memory errors with LLVM instrumentation
Konstantin Serebryany, GoogleSecond Hall -Bitcode Portability/Versioning BOF
Stephen Hines, David Sehr, GoogleTBD - -5:15 - 6:00Thread Safety Annotations in Clang
DeLesley Hutchins, GoogleMain Hall -Backend/Infrastructure Super BoF
Jim Grosbach, Apple Inc.Second Hall -Community Event Planning
David Kipping, QualcommTBD +LunarGLASS: A LLVM-based shader compiler stack
Michael Ilseman, LunarGBallroom Salon II +Symbolic Testing of OpenCL Code
Peter Collingbourne, Imperial College LondonBallroom Salon II +Code verification based on attributes annotation - Implementing custom attributes check using Clang
Michael Han, AutodeskBallroom Salon II +Parfait - A Scalable Static Bug-Checking Tool Built on LLVM
Cristina Cifuentes, Nathan Keynes, Andrew Craik, Lian Li, Nathan Hawes, Andrew Browne, and Manuel Valdiviezo, Oracle LabsBallroom Salon II + +3:45 - 4:30Register Allocation in LLVM 3.0
Jakob Olesen, AppleBallroom Salon III/IV +Exporting 3D scenes from Maya to WebGL using clang and LLVM
Jochen Wilhelmy, consultantBallroom Salon V/VI + +4:30 - 5:15Super-optimizing LLVM IR
Duncan Sands, DeepBlueCapitalBallroom Salon III/IV +Finding races and memory errors with LLVM instrumentation
Konstantin Serebryany, GoogleBallroom Salon V/VI +Bitcode Portability/Versioning BOF
Stephen Hines, David Sehr, GoogleBallroom Salon II + +5:15 - 6:00Thread Safety Annotations in Clang
DeLesley Hutchins, GoogleBallroom Salon III/IV +Backend/Infrastructure Super BoF
Jim Grosbach, Apple Inc.Ballroom Salon V/VI +Community Event Planning
David Kipping, QualcommBallroom Salon II 6:30 - 9:30Dinner (Il Fornaio - Separate registration required) From tonic at nondot.org Tue Nov 8 12:33:15 2011 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 08 Nov 2011 18:33:15 -0000 Subject: [llvm-commits] [www] r144097 - /www/trunk/devmtg/2011-11/index.html Message-ID: <20111108183315.16A842A6C12C@llvm.org> Author: tbrethou Date: Tue Nov 8 12:33:14 2011 New Revision: 144097 URL: http://llvm.org/viewvc/llvm-project?rev=144097&view=rev Log: Add hacking session blurb. Modified: www/trunk/devmtg/2011-11/index.html Modified: www/trunk/devmtg/2011-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=144097&r1=144096&r2=144097&view=diff ============================================================================== --- www/trunk/devmtg/2011-11/index.html (original) +++ www/trunk/devmtg/2011-11/index.html Tue Nov 8 12:33:14 2011 @@ -7,6 +7,7 @@
  • Registration
  • Funding Assistance
  • Location
    • +
  • Hacking Session
  • Agenda
  • Talk Abstracts
  • Poster Abstracts
    • @@ -77,12 +78,17 @@ Take Hwy CA-87 South (Guadalupe Parkway). Exit on Park Avenue. Turn left on Park Avenue. Turn right on Market Street. The hotel is one block ahead, on the corner of Market and San Carlos Street.

    +
    Hacking Session
    +

    +There will be a hacking session the day before the developer meeting. This hacking session will run from 2:00-6:30. More details to come. +

    +
    Agenda

    - + From tonic at nondot.org Tue Nov 8 12:37:07 2011 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 08 Nov 2011 18:37:07 -0000 Subject: [llvm-commits] [www] r144098 - /www/trunk/devmtg/2011-11/index.html Message-ID: <20111108183707.244B42A6C12C@llvm.org> Author: tbrethou Date: Tue Nov 8 12:37:06 2011 New Revision: 144098 URL: http://llvm.org/viewvc/llvm-project?rev=144098&view=rev Log: Oops, moved wrong talk. Updated schedule. Modified: www/trunk/devmtg/2011-11/index.html Modified: www/trunk/devmtg/2011-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=144098&r1=144097&r2=144098&view=diff ============================================================================== --- www/trunk/devmtg/2011-11/index.html (original) +++ www/trunk/devmtg/2011-11/index.html Tue Nov 8 12:37:06 2011 @@ -91,7 +91,7 @@ - + @@ -100,7 +100,8 @@ - + @@ -108,7 +109,7 @@ - + From echristo at apple.com Tue Nov 8 12:38:40 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 08 Nov 2011 18:38:40 -0000 Subject: [llvm-commits] [llvm] r144099 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Message-ID: <20111108183840.C477B2A6C12C@llvm.org> Author: echristo Date: Tue Nov 8 12:38:40 2011 New Revision: 144099 URL: http://llvm.org/viewvc/llvm-project?rev=144099&view=rev Log: A few more places where we can avoid multiple size queries. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp?rev=144099&r1=144098&r2=144099&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Tue Nov 8 12:38:40 2011 @@ -58,7 +58,7 @@ // First get the number of unique hashes. std::vector uniques; uniques.resize(Data.size()); - for (size_t i = 0; i < Data.size(); ++i) + for (size_t i = 0, e = Data.size(); i < e; ++i) uniques[i] = Data[i]->HashValue; std::sort(uniques.begin(), uniques.end()); std::vector::iterator p = @@ -94,7 +94,7 @@ // Compute bucket contents and final ordering. Buckets.resize(Header.bucket_count); - for (size_t i = 0; i < Data.size(); ++i) { + for (size_t i = 0, e = Data.size(); i < e; ++i) { uint32_t bucket = Data[i]->HashValue % Header.bucket_count; Buckets[bucket].push_back(Data[i]); Data[i]->Sym = Asm->GetTempSymbol(Prefix, i); @@ -132,7 +132,7 @@ // like a list of numbers of how many elements are in each bucket. void DwarfAccelTable::EmitBuckets(AsmPrinter *Asm) { unsigned index = 0; - for (size_t i = 0; i < Buckets.size(); ++i) { + for (size_t i = 0, e = Buckets.size(); i < e; ++i) { Asm->OutStreamer.AddComment("Bucket " + Twine(i)); if (Buckets[i].size() != 0) Asm->EmitInt32(index); @@ -145,7 +145,7 @@ // Walk through the buckets and emit the individual hashes for each // bucket. void DwarfAccelTable::EmitHashes(AsmPrinter *Asm) { - for (size_t i = 0; i < Buckets.size(); ++i) { + for (size_t i = 0, e = Buckets.size(); i < e; ++i) { for (HashList::const_iterator HI = Buckets[i].begin(), HE = Buckets[i].end(); HI != HE; ++HI) { Asm->OutStreamer.AddComment("Hash in Bucket " + Twine(i)); @@ -159,7 +159,7 @@ // beginning of the section. The non-section symbol will be output later // when we emit the actual data. void DwarfAccelTable::EmitOffsets(AsmPrinter *Asm, MCSymbol *SecBegin) { - for (size_t i = 0; i < Buckets.size(); ++i) { + for (size_t i = 0, e = Buckets.size(); i < e; ++i) { for (HashList::const_iterator HI = Buckets[i].begin(), HE = Buckets[i].end(); HI != HE; ++HI) { Asm->OutStreamer.AddComment("Offset in Bucket " + Twine(i)); @@ -178,7 +178,7 @@ // Terminate each HashData bucket with 0. void DwarfAccelTable::EmitData(AsmPrinter *Asm, DwarfDebug *D) { uint64_t PrevHash = UINT64_MAX; - for (size_t i = 0; i < Buckets.size(); ++i) { + for (size_t i = 0, e = Buckets.size(); i < e; ++i) { for (HashList::const_iterator HI = Buckets[i].begin(), HE = Buckets[i].end(); HI != HE; ++HI) { // Remember to emit the label for our offset. @@ -237,7 +237,7 @@ } O << "Buckets and Hashes: \n"; - for (size_t i = 0; i < Buckets.size(); ++i) + for (size_t i = 0, e = Buckets.size(); i < e; ++i) for (HashList::const_iterator HI = Buckets[i].begin(), HE = Buckets[i].end(); HI != HE; ++HI) (*HI)->print(O); From peter_cooper at apple.com Tue Nov 8 12:42:53 2011 From: peter_cooper at apple.com (Pete Cooper) Date: Tue, 08 Nov 2011 18:42:53 -0000 Subject: [llvm-commits] [llvm] r144100 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Target/XCore/ Message-ID: <20111108184254.96E262A6C12C@llvm.org> Author: pete Date: Tue Nov 8 12:42:53 2011 New Revision: 144100 URL: http://llvm.org/viewvc/llvm-project?rev=144100&view=rev Log: Added invariant field to the DAG.getLoad method and changed all calls. When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/MachineInstr.cpp llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h Tue Nov 8 12:42:53 2011 @@ -95,8 +95,10 @@ MOVolatile = 4, /// The memory access is non-temporal. MONonTemporal = 8, + /// The memory access is invariant. + MOInvariant = 16, // This is the number of bits we need to represent flags. - MOMaxBits = 4 + MOMaxBits = 5 }; /// MachineMemOperand - Construct an MachineMemOperand object with the @@ -141,6 +143,7 @@ bool isStore() const { return Flags & MOStore; } bool isVolatile() const { return Flags & MOVolatile; } bool isNonTemporal() const { return Flags & MONonTemporal; } + bool isInvariant() const { return Flags & MOInvariant; } /// refineAlignment - Update this MachineMemOperand to reflect the alignment /// of MMO, if it has a greater alignment. This must only be used when the Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Tue Nov 8 12:42:53 2011 @@ -650,7 +650,7 @@ /// SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, - bool isNonTemporal, unsigned Alignment, + bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo = 0); SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, @@ -663,8 +663,8 @@ EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, - bool isVolatile, bool isNonTemporal, unsigned Alignment, - const MDNode *TBAAInfo = 0); + bool isVolatile, bool isNonTemporal, bool isInvariant, + unsigned Alignment, const MDNode *TBAAInfo = 0); SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, SDValue Offset, Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Nov 8 12:42:53 2011 @@ -917,12 +917,13 @@ // with MachineMemOperand information. bool isVolatile() const { return (SubclassData >> 5) & 1; } bool isNonTemporal() const { return (SubclassData >> 6) & 1; } + bool isInvariant() const { return (SubclassData >> 7) & 1; } AtomicOrdering getOrdering() const { - return AtomicOrdering((SubclassData >> 7) & 15); + return AtomicOrdering((SubclassData >> 8) & 15); } SynchronizationScope getSynchScope() const { - return SynchronizationScope((SubclassData >> 11) & 1); + return SynchronizationScope((SubclassData >> 12) & 1); } /// Returns the SrcValue and offset that describes the location of the access @@ -993,8 +994,8 @@ "Ordering may not require more than 4 bits!"); assert((SynchScope & 1) == SynchScope && "SynchScope may not require more than 1 bit!"); - SubclassData |= Ordering << 7; - SubclassData |= SynchScope << 11; + SubclassData |= Ordering << 8; + SubclassData |= SynchScope << 12; assert(getOrdering() == Ordering && "Ordering encoding error!"); assert(getSynchScope() == SynchScope && "Synch-scope encoding error!"); Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Nov 8 12:42:53 2011 @@ -1253,6 +1253,7 @@ E = memoperands_end(); I != E; ++I) { if ((*I)->isVolatile()) return false; if ((*I)->isStore()) return false; + if ((*I)->isInvariant()) return true; if (const Value *V = (*I)->getValue()) { // A load from a constant PseudoSourceValue is invariant. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Nov 8 12:42:53 2011 @@ -4702,7 +4702,8 @@ if (ExtType == ISD::NON_EXTLOAD) Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), - LN0->isVolatile(), LN0->isNonTemporal(), NewAlign); + LN0->isVolatile(), LN0->isNonTemporal(), + LN0->isInvariant(), NewAlign); else Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), @@ -4931,7 +4932,7 @@ (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), LD1->getBasePtr(), LD1->getPointerInfo(), - false, false, Align); + false, false, false, Align); } return SDValue(); @@ -5001,7 +5002,7 @@ SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), LN0->getBasePtr(), LN0->getPointerInfo(), LN0->isVolatile(), LN0->isNonTemporal(), - OrigAlign); + LN0->isInvariant(), OrigAlign); AddToWorkList(N); CombineTo(N0.getNode(), DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), @@ -6219,7 +6220,7 @@ ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), BetterChain, Ptr, LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(), - LD->getAlignment()); + LD->isInvariant(), LD->getAlignment()); } else { ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), LD->getValueType(0), @@ -6483,7 +6484,7 @@ LD->getChain(), NewPtr, LD->getPointerInfo().getWithOffset(PtrOff), LD->isVolatile(), LD->isNonTemporal(), - NewAlign); + LD->isInvariant(), NewAlign); SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, DAG.getConstant(NewImm, NewVT)); SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), @@ -6543,7 +6544,7 @@ SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(), - false, false, LDAlign); + false, false, false, LDAlign); SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), NewLD, ST->getBasePtr(), @@ -6928,7 +6929,8 @@ return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), - LN0->isVolatile(), LN0->isNonTemporal(), Align); + LN0->isVolatile(), LN0->isNonTemporal(), + LN0->isInvariant(), Align); } return SDValue(); @@ -7497,7 +7499,7 @@ // FIXME: Discards pointer info. LLD->getChain(), Addr, MachinePointerInfo(), LLD->isVolatile(), LLD->isNonTemporal(), - LLD->getAlignment()); + LLD->isInvariant(), LLD->getAlignment()); } else { Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? RLD->getExtensionType() : LLD->getExtensionType(), @@ -7613,7 +7615,7 @@ AddToWorkList(CPIdx.getNode()); return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, MachinePointerInfo::getConstantPool(), false, - false, Alignment); + false, false, Alignment); } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Nov 8 12:42:53 2011 @@ -259,7 +259,7 @@ } SDValue Result = DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, - MachinePointerInfo::getConstantPool(), false, false, + MachinePointerInfo::getConstantPool(), false, false, false, Alignment); return Result; } @@ -315,7 +315,7 @@ // Load one integer register's worth from the stack slot. SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); // Store it to the final location. Remember the store. Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, ST->getPointerInfo().getWithOffset(Offset), @@ -403,7 +403,8 @@ // then bitconvert to floating point or vector. SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(), LD->isVolatile(), - LD->isNonTemporal(), LD->getAlignment()); + LD->isNonTemporal(), + LD->isInvariant(), LD->getAlignment()); SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); if (VT.isFloatingPoint() && LoadedVT != VT) Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); @@ -434,6 +435,7 @@ SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset), LD->isVolatile(), LD->isNonTemporal(), + LD->isInvariant(), MinAlign(LD->getAlignment(), Offset)); // Follow the load with a store to the stack slot. Remember the store. Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, @@ -570,7 +572,8 @@ false, false, 0); // Load the updated vector. return DAG.getLoad(VT, dl, Ch, StackPtr, - MachinePointerInfo::getFixedStack(SPFI), false, false, 0); + MachinePointerInfo::getFixedStack(SPFI), false, false, + false, 0); } @@ -911,7 +914,7 @@ Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(), - LD->getAlignment()); + LD->isInvariant(), LD->getAlignment()); Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1); Tmp4 = Tmp1.getValue(1); break; @@ -1086,7 +1089,7 @@ SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(), - LD->getAlignment()); + LD->isInvariant(), LD->getAlignment()); unsigned ExtendOp; switch (ExtType) { case ISD::EXTLOAD: @@ -1336,7 +1339,7 @@ if (Op.getValueType().isVector()) return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(), - false, false, 0); + false, false, false, 0); return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(), Vec.getValueType().getVectorElementType(), @@ -1384,7 +1387,7 @@ // Finally, load the updated vector. return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo, - false, false, 0); + false, false, false, 0); } SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { @@ -1434,7 +1437,8 @@ StoreChain = DAG.getEntryNode(); // Result is a load from the stack slot. - return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0); + return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, + false, false, false, 0); } SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { @@ -1463,7 +1467,7 @@ assert(FloatVT.isByteSized() && "Unsupported floating point type!"); // Load out a legal integer with the same sign bit as the float. SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } else { // Little endian SDValue LoadPtr = StackPtr; // The float may be wider than the integer we are going to load. Advance @@ -1474,7 +1478,7 @@ LoadPtr, DAG.getIntPtrConstant(ByteOffset)); // Load a legal integer containing the sign bit. SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); // Move the sign bit to the top bit of the loaded integer. unsigned BitShift = LoadTy.getSizeInBits() - (FloatVT.getSizeInBits() - 8 * ByteOffset); @@ -1616,7 +1620,7 @@ // Result is a load from the stack slot. if (SlotSize == DestSize) return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, - false, false, DestAlign); + false, false, false, DestAlign); assert(SlotSize < DestSize && "Unknown extension!"); return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, @@ -1639,7 +1643,7 @@ false, false, 0); return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(SPFI), - false, false, 0); + false, false, false, 0); } @@ -1713,7 +1717,7 @@ unsigned Alignment = cast(CPIdx)->getAlignment(); return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, MachinePointerInfo::getConstantPool(), - false, false, Alignment); + false, false, false, Alignment); } if (!MoreThanTwoValues) { @@ -1975,7 +1979,7 @@ // Remainder is loaded back from the stack frame. SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); Results.push_back(CallInfo.first); Results.push_back(Rem); } @@ -2024,7 +2028,7 @@ false, false, 0); // load the constructed double SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); // FP constant to bias correct the final result SDValue Bias = DAG.getConstantFP(isSigned ? BitsToDouble(0x4330000080000000ULL) : @@ -2164,7 +2168,7 @@ if (DestVT == MVT::f32) FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, MachinePointerInfo::getConstantPool(), - false, false, Alignment); + false, false, false, Alignment); else { SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx, @@ -2703,7 +2707,8 @@ unsigned Align = Node->getConstantOperandVal(3); SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, - MachinePointerInfo(V), false, false, 0); + MachinePointerInfo(V), + false, false, false, 0); SDValue VAList = VAListLoad; if (Align > TLI.getMinStackArgumentAlignment()) { @@ -2728,7 +2733,7 @@ MachinePointerInfo(V), false, false, 0); // Load the actual argument out of the pointer VAList Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), - false, false, 0)); + false, false, false, 0)); Results.push_back(Results[0].getValue(1)); break; } @@ -2739,7 +2744,7 @@ const Value *VS = cast(Node->getOperand(4))->getValue(); Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), Node->getOperand(2), MachinePointerInfo(VS), - false, false, 0); + false, false, false, 0); Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), MachinePointerInfo(VD), false, false, 0); Results.push_back(Tmp1); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Tue Nov 8 12:42:53 2011 @@ -479,8 +479,8 @@ if (L->getExtensionType() == ISD::NON_EXTLOAD) { NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl, L->getChain(), L->getBasePtr(), L->getOffset(), - L->getPointerInfo(), NVT, - L->isVolatile(), L->isNonTemporal(), L->getAlignment()); + L->getPointerInfo(), NVT, L->isVolatile(), + L->isNonTemporal(), false, L->getAlignment()); // Legalized the chain result - switch anything that used the old chain to // use the new one. ReplaceValueWith(SDValue(N, 1), NewL.getValue(1)); @@ -492,7 +492,7 @@ L->getMemoryVT(), dl, L->getChain(), L->getBasePtr(), L->getOffset(), L->getPointerInfo(), L->getMemoryVT(), L->isVolatile(), - L->isNonTemporal(), L->getAlignment()); + L->isNonTemporal(), false, L->getAlignment()); // Legalized the chain result - switch anything that used the old chain to // use the new one. ReplaceValueWith(SDValue(N, 1), NewL.getValue(1)); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Nov 8 12:42:53 2011 @@ -1778,6 +1778,7 @@ unsigned Alignment = N->getAlignment(); bool isVolatile = N->isVolatile(); bool isNonTemporal = N->isNonTemporal(); + bool isInvariant = N->isInvariant(); DebugLoc dl = N->getDebugLoc(); assert(NVT.isByteSized() && "Expanded type not byte sized!"); @@ -1808,7 +1809,7 @@ } else if (TLI.isLittleEndian()) { // Little-endian - low bits are at low addresses. Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), - isVolatile, isNonTemporal, Alignment); + isVolatile, isNonTemporal, isInvariant, Alignment); unsigned ExcessBits = N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); @@ -2310,7 +2311,7 @@ SplitInteger(CallInfo.first, Lo, Hi); SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2, DAG.getConstant(0, PtrVT), ISD::SETNE); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Tue Nov 8 12:42:53 2011 @@ -889,7 +889,7 @@ MachinePointerInfo(), false, false, 0); // Result is a load from the stack slot. return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } /// CustomLowerNode - Replace the node's results with custom code provided Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Tue Nov 8 12:42:53 2011 @@ -130,7 +130,8 @@ false, false, 0); // Load the first half from the stack slot. - Lo = DAG.getLoad(NOutVT, dl, Store, StackPtr, PtrInfo, false, false, 0); + Lo = DAG.getLoad(NOutVT, dl, Store, StackPtr, PtrInfo, + false, false, false, 0); // Increment the pointer to the other half. unsigned IncrementSize = NOutVT.getSizeInBits() / 8; @@ -140,7 +141,7 @@ // Load the second half from the stack slot. Hi = DAG.getLoad(NOutVT, dl, Store, StackPtr, PtrInfo.getWithOffset(IncrementSize), false, - false, MinAlign(Alignment, IncrementSize)); + false, false, MinAlign(Alignment, IncrementSize)); // Handle endianness of the load. if (TLI.isBigEndian()) @@ -212,11 +213,12 @@ unsigned Alignment = LD->getAlignment(); bool isVolatile = LD->isVolatile(); bool isNonTemporal = LD->isNonTemporal(); + bool isInvariant = LD->isInvariant(); assert(NVT.isByteSized() && "Expanded type not byte sized!"); Lo = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(), - isVolatile, isNonTemporal, Alignment); + isVolatile, isNonTemporal, isInvariant, Alignment); // Increment the pointer to the other half. unsigned IncrementSize = NVT.getSizeInBits() / 8; @@ -224,7 +226,7 @@ DAG.getIntPtrConstant(IncrementSize)); Hi = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(IncrementSize), - isVolatile, isNonTemporal, + isVolatile, isNonTemporal, isInvariant, MinAlign(Alignment, IncrementSize)); // Build a factor node to remember that this load is independent of the Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Nov 8 12:42:53 2011 @@ -194,7 +194,7 @@ N->getPointerInfo(), N->getMemoryVT().getVectorElementType(), N->isVolatile(), N->isNonTemporal(), - N->getOriginalAlignment()); + N->isInvariant(), N->getOriginalAlignment()); // Legalized the chain result - switch anything that used the old chain to // use the new one. @@ -677,7 +677,7 @@ // Load the Lo part from the stack slot. Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); // Increment the pointer to the other part. unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; @@ -686,7 +686,7 @@ // Load the Hi part from the stack slot. Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), - false, false, MinAlign(Alignment, IncrementSize)); + false, false, false, MinAlign(Alignment, IncrementSize)); } void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, @@ -713,20 +713,21 @@ unsigned Alignment = LD->getOriginalAlignment(); bool isVolatile = LD->isVolatile(); bool isNonTemporal = LD->isNonTemporal(); + bool isInvariant = LD->isInvariant(); EVT LoMemVT, HiMemVT; GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal, - Alignment); + isInvariant, Alignment); unsigned IncrementSize = LoMemVT.getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, LD->getPointerInfo().getWithOffset(IncrementSize), - HiMemVT, isVolatile, isNonTemporal, Alignment); + HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment); // Build a factor node to remember that this load is independent of the // other one. @@ -2276,6 +2277,7 @@ unsigned Align = LD->getAlignment(); bool isVolatile = LD->isVolatile(); bool isNonTemporal = LD->isNonTemporal(); + bool isInvariant = LD->isInvariant(); int LdWidth = LdVT.getSizeInBits(); int WidthDiff = WidenWidth - LdWidth; // Difference @@ -2285,7 +2287,7 @@ EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); int NewVTWidth = NewVT.getSizeInBits(); SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), - isVolatile, isNonTemporal, Align); + isVolatile, isNonTemporal, isInvariant, Align); LdChain.push_back(LdOp.getValue(1)); // Check if we can load the element with one instruction @@ -2332,7 +2334,8 @@ SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo().getWithOffset(Offset), isVolatile, - isNonTemporal, MinAlign(Align, Increment)); + isNonTemporal, isInvariant, + MinAlign(Align, Increment)); LdChain.push_back(LdOp.getValue(1)); LdOps.push_back(LdOp); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Nov 8 12:42:53 2011 @@ -475,7 +475,7 @@ /// static inline unsigned encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile, - bool isNonTemporal) { + bool isNonTemporal, bool isInvariant) { assert((ConvType & 3) == ConvType && "ConvType may not require more than 2 bits!"); assert((AM & 7) == AM && @@ -483,7 +483,8 @@ return ConvType | (AM << 2) | (isVolatile << 5) | - (isNonTemporal << 6); + (isNonTemporal << 6) | + (isInvariant << 7); } //===----------------------------------------------------------------------===// @@ -3568,7 +3569,7 @@ Value = DAG.getLoad(VT, dl, Chain, getMemBasePlusOffset(Src, SrcOff, DAG), SrcPtrInfo.getWithOffset(SrcOff), isVol, - false, SrcAlign); + false, false, SrcAlign); LoadValues.push_back(Value); LoadChains.push_back(Value.getValue(1)); SrcOff += VTSize; @@ -4144,7 +4145,7 @@ EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, - bool isVolatile, bool isNonTemporal, + bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo) { assert(Chain.getValueType() == MVT::Other && "Invalid chain type"); @@ -4156,6 +4157,8 @@ Flags |= MachineMemOperand::MOVolatile; if (isNonTemporal) Flags |= MachineMemOperand::MONonTemporal; + if (isInvariant) + Flags |= MachineMemOperand::MOInvariant; // If we don't have a PtrInfo, infer the trivial frame index case to simplify // clients. @@ -4202,7 +4205,8 @@ AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); ID.AddInteger(MemVT.getRawBits()); ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, MMO->isVolatile(), - MMO->isNonTemporal())); + MMO->isNonTemporal(), + MMO->isInvariant())); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { cast(E)->refineAlignment(MMO); @@ -4219,10 +4223,12 @@ SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, - unsigned Alignment, const MDNode *TBAAInfo) { + bool isInvariant, unsigned Alignment, + const MDNode *TBAAInfo) { SDValue Undef = getUNDEF(Ptr.getValueType()); return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, - PtrInfo, VT, isVolatile, isNonTemporal, Alignment, TBAAInfo); + PtrInfo, VT, isVolatile, isNonTemporal, isInvariant, Alignment, + TBAAInfo); } SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT, @@ -4232,7 +4238,7 @@ unsigned Alignment, const MDNode *TBAAInfo) { SDValue Undef = getUNDEF(Ptr.getValueType()); return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, - PtrInfo, MemVT, isVolatile, isNonTemporal, Alignment, + PtrInfo, MemVT, isVolatile, isNonTemporal, false, Alignment, TBAAInfo); } @@ -4245,8 +4251,8 @@ "Load is already a indexed load!"); return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), dl, LD->getChain(), Base, Offset, LD->getPointerInfo(), - LD->getMemoryVT(), - LD->isVolatile(), LD->isNonTemporal(), LD->getAlignment()); + LD->getMemoryVT(), LD->isVolatile(), LD->isNonTemporal(), + false, LD->getAlignment()); } SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, @@ -4288,7 +4294,7 @@ AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); ID.AddInteger(VT.getRawBits()); ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile(), - MMO->isNonTemporal())); + MMO->isNonTemporal(), MMO->isInvariant())); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { cast(E)->refineAlignment(MMO); @@ -4355,7 +4361,7 @@ AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); ID.AddInteger(SVT.getRawBits()); ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile(), - MMO->isNonTemporal())); + MMO->isNonTemporal(), MMO->isInvariant())); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { cast(E)->refineAlignment(MMO); @@ -5679,7 +5685,7 @@ MachineMemOperand *mmo) : SDNode(Opc, dl, VTs), MemoryVT(memvt), MMO(mmo) { SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(), - MMO->isNonTemporal()); + MMO->isNonTemporal(), MMO->isInvariant()); assert(isVolatile() == MMO->isVolatile() && "Volatile encoding error!"); assert(isNonTemporal() == MMO->isNonTemporal() && "Non-temporal encoding error!"); @@ -5692,7 +5698,7 @@ : SDNode(Opc, dl, VTs, Ops, NumOps), MemoryVT(memvt), MMO(mmo) { SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(), - MMO->isNonTemporal()); + MMO->isNonTemporal(), MMO->isInvariant()); assert(isVolatile() == MMO->isVolatile() && "Volatile encoding error!"); assert(memvt.getStoreSize() == MMO->getSize() && "Size mismatch!"); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Nov 8 12:42:53 2011 @@ -3175,6 +3175,7 @@ bool isVolatile = I.isVolatile(); bool isNonTemporal = I.getMetadata("nontemporal") != 0; + bool isInvariant = I.getMetadata("invariant.load") != 0; unsigned Alignment = I.getAlignment(); const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); @@ -3224,7 +3225,7 @@ DAG.getConstant(Offsets[i], PtrVT)); SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, A, MachinePointerInfo(SV, Offsets[i]), isVolatile, - isNonTemporal, Alignment, TBAAInfo); + isNonTemporal, isInvariant, Alignment, TBAAInfo); Values[i] = L; Chains[ChainI] = L.getValue(1); @@ -5264,7 +5265,7 @@ SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, Add, MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), - false, false, 1); + false, false, false, 1); Values[i] = L; Chains[i] = L.getValue(1); } @@ -5375,7 +5376,8 @@ SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, Ptr, MachinePointerInfo(PtrVal), false /*volatile*/, - false /*nontemporal*/, 1 /* align=1 */); + false /*nontemporal*/, + false /*isinvariant*/, 1 /* align=1 */); if (!ConstantMemory) Builder.PendingLoads.push_back(LoadVal.getValue(1)); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Nov 8 12:42:53 2011 @@ -2060,7 +2060,7 @@ unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, Lod->getPointerInfo().getWithOffset(bestOffset), - false, false, NewAlign); + false, false, false, NewAlign); return DAG.getSetCC(dl, VT, DAG.getNode(ISD::AND, dl, newVT, NewLoad, DAG.getConstant(bestMask.trunc(bestWidth), Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Nov 8 12:42:53 2011 @@ -1339,7 +1339,7 @@ SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(j, Load)); } @@ -1432,7 +1432,7 @@ Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), CPAddr, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); } else if (ExternalSymbolSDNode *S=dyn_cast(Callee)) { const char *Sym = S->getSymbol(); @@ -1447,7 +1447,7 @@ Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), CPAddr, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); } } else if (GlobalAddressSDNode *G = dyn_cast(Callee)) { const GlobalValue *GV = G->getGlobal(); @@ -1468,7 +1468,7 @@ Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), CPAddr, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); Callee = DAG.getNode(ARMISD::PIC_ADD, dl, getPointerTy(), Callee, PICLabel); @@ -1497,7 +1497,7 @@ Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), CPAddr, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); Callee = DAG.getNode(ARMISD::PIC_ADD, dl, getPointerTy(), Callee, PICLabel); @@ -1968,7 +1968,7 @@ CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); if (RelocM == Reloc::Static) return Result; SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); @@ -1992,7 +1992,7 @@ Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); SDValue Chain = Argument.getValue(1); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); @@ -2040,7 +2040,7 @@ Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); Chain = Offset.getValue(1); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); @@ -2048,7 +2048,7 @@ Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); } else { // local exec model ARMConstantPoolValue *CPV = @@ -2057,7 +2057,7 @@ Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); } // The address of the thread local variable is the add of the thread @@ -2095,13 +2095,14 @@ SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); SDValue Chain = Result.getValue(1); SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); if (!UseGOTOFF) Result = DAG.getLoad(PtrVT, dl, Chain, Result, - MachinePointerInfo::getGOT(), false, false, 0); + MachinePointerInfo::getGOT(), + false, false, false, 0); return Result; } @@ -2118,7 +2119,7 @@ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); } } @@ -2146,7 +2147,8 @@ DAG.getTargetGlobalAddress(GV, dl, PtrVT)); if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, - MachinePointerInfo::getGOT(), false, false, 0); + MachinePointerInfo::getGOT(), + false, false, false, 0); return Result; } @@ -2166,7 +2168,7 @@ SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); SDValue Chain = Result.getValue(1); if (RelocM == Reloc::PIC_) { @@ -2176,7 +2178,7 @@ if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(), - false, false, 0); + false, false, false, 0); return Result; } @@ -2198,7 +2200,7 @@ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); } @@ -2256,7 +2258,7 @@ SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); if (RelocM == Reloc::PIC_) { SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); @@ -2388,7 +2390,7 @@ SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, MachinePointerInfo::getFixedStack(FI), - false, false, 0); + false, false, false, 0); } else { Reg = MF.addLiveIn(NextVA.getLocReg(), RC); ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); @@ -2524,7 +2526,7 @@ SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, MachinePointerInfo::getFixedStack(FI), - false, false, 0); + false, false, false, 0); } else { ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); @@ -2615,7 +2617,7 @@ SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo::getFixedStack(FI), - false, false, 0)); + false, false, false, 0)); } lastInsIndex = index; } @@ -2850,7 +2852,7 @@ return DAG.getLoad(MVT::i32, Op.getDebugLoc(), Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(), - Ld->getAlignment()); + Ld->isInvariant(), Ld->getAlignment()); llvm_unreachable("Unknown VFP cmp argument!"); } @@ -2869,7 +2871,7 @@ Ld->getChain(), Ptr, Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(), - Ld->getAlignment()); + Ld->isInvariant(), Ld->getAlignment()); EVT PtrType = Ptr.getValueType(); unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); @@ -2879,7 +2881,7 @@ Ld->getChain(), NewPtr, Ld->getPointerInfo().getWithOffset(4), Ld->isVolatile(), Ld->isNonTemporal(), - NewAlign); + Ld->isInvariant(), NewAlign); return; } @@ -3003,13 +3005,14 @@ if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, MachinePointerInfo::getJumpTable(), - false, false, 0); + false, false, false, 0); Chain = Addr.getValue(1); Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); } else { Addr = DAG.getLoad(PTy, dl, Chain, Addr, - MachinePointerInfo::getJumpTable(), false, false, 0); + MachinePointerInfo::getJumpTable(), + false, false, false, 0); Chain = Addr.getValue(1); return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); } @@ -3179,7 +3182,7 @@ SDValue Offset = DAG.getConstant(4, MVT::i32); return DAG.getLoad(VT, dl, DAG.getEntryNode(), DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); } // Return LR, which contains the return address. Mark it an implicit live-in. @@ -3200,7 +3203,7 @@ while (Depth--) FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); return FrameAddr; } @@ -4595,7 +4598,8 @@ if (LoadSDNode *LD = dyn_cast(N)) return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), - LD->isNonTemporal(), LD->getAlignment()); + LD->isNonTemporal(), LD->isInvariant(), + LD->getAlignment()); // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will // have been legalized as a BITCAST from v4i32. if (N->getOpcode() == ISD::BITCAST) { @@ -7067,13 +7071,14 @@ SDValue BasePtr = LD->getBasePtr(); SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, LD->getPointerInfo(), LD->isVolatile(), - LD->isNonTemporal(), LD->getAlignment()); + LD->isNonTemporal(), LD->isInvariant(), + LD->getAlignment()); SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, DAG.getConstant(4, MVT::i32)); SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, LD->getPointerInfo(), LD->isVolatile(), - LD->isNonTemporal(), + LD->isNonTemporal(), LD->isInvariant(), std::min(4U, LD->getAlignment() / 2)); DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1)); Modified: llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp Tue Nov 8 12:42:53 2011 @@ -67,7 +67,7 @@ DAG.getNode(ISD::ADD, dl, MVT::i32, Src, DAG.getConstant(SrcOff, MVT::i32)), SrcPtrInfo.getWithOffset(SrcOff), isVolatile, - false, 0); + false, false, 0); TFOps[i] = Loads[i].getValue(1); SrcOff += VTSize; } @@ -105,7 +105,8 @@ Loads[i] = DAG.getLoad(VT, dl, Chain, DAG.getNode(ISD::ADD, dl, MVT::i32, Src, DAG.getConstant(SrcOff, MVT::i32)), - SrcPtrInfo.getWithOffset(SrcOff), false, false, 0); + SrcPtrInfo.getWithOffset(SrcOff), + false, false, false, 0); TFOps[i] = Loads[i].getValue(1); ++i; SrcOff += VTSize; Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Tue Nov 8 12:42:53 2011 @@ -216,7 +216,7 @@ HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl, CurDAG->getEntryNode(), CGPoolOffset, MachinePointerInfo::getConstantPool(), - false, false, Alignment)); + false, false, false, Alignment)); CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue()); if (SDNode *N = SelectCode(Dummy.getValue().getNode())) return N; Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Tue Nov 8 12:42:53 2011 @@ -667,7 +667,7 @@ // Do the load as a i128 to allow possible shifting SDValue low = DAG.getLoad(MVT::i128, dl, the_chain, basePtr, lowMemPtr, - LN->isVolatile(), LN->isNonTemporal(), 16); + LN->isVolatile(), LN->isNonTemporal(), false, 16); // When the size is not greater than alignment we get all data with just // one load @@ -704,7 +704,8 @@ basePtr, DAG.getConstant(16, PtrVT)), highMemPtr, - LN->isVolatile(), LN->isNonTemporal(), 16); + LN->isVolatile(), LN->isNonTemporal(), false, + 16); the_chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, low.getValue(1), high.getValue(1)); @@ -859,7 +860,8 @@ // Load the lower part of the memory to which to store. SDValue low = DAG.getLoad(vecVT, dl, the_chain, basePtr, - lowMemPtr, SN->isVolatile(), SN->isNonTemporal(), 16); + lowMemPtr, SN->isVolatile(), SN->isNonTemporal(), + false, 16); // if we don't need to store over the 16 byte boundary, one store suffices if (alignment >= StVT.getSizeInBits()/8) { @@ -959,7 +961,8 @@ DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, DAG.getConstant( 16, PtrVT)), highMemPtr, - SN->isVolatile(), SN->isNonTemporal(), 16); + SN->isVolatile(), SN->isNonTemporal(), + false, 16); the_chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, low.getValue(1), hi.getValue(1)); @@ -1194,7 +1197,7 @@ int FI = MFI->CreateFixedObject(ObjSize, ArgOffset, true); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); ArgOffset += StackSlotSize; } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Tue Nov 8 12:42:53 2011 @@ -951,7 +951,7 @@ SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo::getFixedStack(FI), - false, false, 0)); + false, false, false, 0)); } } Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Tue Nov 8 12:42:53 2011 @@ -371,7 +371,7 @@ SDValue FIN = DAG.getFrameIndex(FI, MVT::i16); InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, MachinePointerInfo::getFixedStack(FI), - false, false, 0)); + false, false, false, 0)); } } @@ -907,13 +907,13 @@ return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), DAG.getNode(ISD::ADD, dl, getPointerTy(), FrameAddr, Offset), - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); } // Just load the return address. SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), - RetAddrFI, MachinePointerInfo(), false, false, 0); + RetAddrFI, MachinePointerInfo(), false, false, false, 0); } SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, @@ -929,7 +929,7 @@ while (Depth--) FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); return FrameAddr; } Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Nov 8 12:42:53 2011 @@ -1402,7 +1402,7 @@ GA = DAG.getNode(MipsISD::WrapperPIC, dl, ValTy, GA); SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); // On functions and global targets not internal linked only // a load from got/GP is necessary for PIC to work. if (!HasGotOfst) @@ -1438,7 +1438,7 @@ MipsII::MO_ABS_LO); SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), BAGOTOffset, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset); return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); } @@ -1485,7 +1485,7 @@ MipsII::MO_GOTTPREL); Offset = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), TGA, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } else { // Local Exec TLS Model SDVTList VTs = DAG.getVTList(MVT::i32); @@ -1524,7 +1524,7 @@ JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI); HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, @@ -1568,7 +1568,7 @@ CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP); SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), CP, MachinePointerInfo::getConstantPool(), - false, false, 0); + false, false, false, 0); SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), N->getOffset(), MipsII::MO_ABS_LO); SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); @@ -1831,8 +1831,8 @@ DAG.getConstant(Offset, MVT::i32)); SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, MachinePointerInfo(), - false, false, std::min(ByValAlign, - (unsigned )4)); + false, false, false, std::min(ByValAlign, + (unsigned )4)); MemOpChains.push_back(LoadVal.getValue(1)); unsigned DstReg = O32IntRegs[LocMemOffset / 4]; RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); @@ -2119,7 +2119,7 @@ Callee = DAG.getNode(MipsISD::WrapperPIC, dl, getPointerTy(), Callee); SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, MachinePointerInfo::getGOT(), - false, false, 0); + false, false, false, 0); // Use GOT+LO if callee has internal linkage. if (CalleeLo.getNode()) { @@ -2350,7 +2350,7 @@ SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, MachinePointerInfo::getFixedStack(LastFI), - false, false, 0)); + false, false, false, 0)); } } Modified: llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXSelectionDAGInfo.cpp Tue Nov 8 12:42:53 2011 @@ -70,7 +70,7 @@ DAG.getNode(ISD::ADD, dl, PointerType, Src, DAG.getConstant(SrcOff, PointerType)), SrcPtrInfo.getWithOffset(SrcOff), isVolatile, - false, 0); + false, false, 0); TFOps[i] = Loads[i].getValue(1); SrcOff += VTSize; } @@ -108,7 +108,8 @@ Loads[i] = DAG.getLoad(VT, dl, Chain, DAG.getNode(ISD::ADD, dl, PointerType, Src, DAG.getConstant(SrcOff, PointerType)), - SrcPtrInfo.getWithOffset(SrcOff), false, false, 0); + SrcPtrInfo.getWithOffset(SrcOff), false, false, + false, 0); TFOps[i] = Loads[i].getValue(1); ++i; SrcOff += VTSize; Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Nov 8 12:42:53 2011 @@ -1223,7 +1223,7 @@ // extra load to get the address of the global. if (MOHiFlag & PPCII::MO_NLP_FLAG) Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); return Ptr; } @@ -1319,11 +1319,13 @@ // areas SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, + false, 0); InChain = OverflowArea.getValue(1); SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, + false, 0); InChain = RegSaveArea.getValue(1); // select overflow_area if index > 8 @@ -1372,7 +1374,8 @@ MachinePointerInfo(), MVT::i32, false, false, 0); - return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), false, false, 0); + return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), + false, false, false, 0); } SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, @@ -1721,7 +1724,7 @@ SDValue FIN = DAG.getFrameIndex(FI, PtrVT); InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo(), - false, false, 0)); + false, false, false, 0)); } } @@ -2138,7 +2141,7 @@ isImmutable); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } InVals.push_back(ArgVal); @@ -2443,7 +2446,7 @@ EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; LROpOut = getReturnAddrFrameIndex(DAG); LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); Chain = SDValue(LROpOut.getNode(), 1); // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack @@ -2451,7 +2454,7 @@ if (isDarwinABI) { FPOpOut = getFramePointerFrameIndex(DAG); FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); Chain = SDValue(FPOpOut.getNode(), 1); } } @@ -3212,7 +3215,7 @@ if (GPR_idx != NumGPRs) { SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); ArgOffset += PtrByteSize; @@ -3250,7 +3253,8 @@ // Float varargs are always shadowed in available integer registers if (GPR_idx != NumGPRs) { SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, + false, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } @@ -3259,7 +3263,7 @@ PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } @@ -3308,7 +3312,7 @@ if (VR_idx != NumVRs) { SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); } @@ -3319,7 +3323,7 @@ SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, DAG.getConstant(i, PtrVT)); SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } @@ -3483,7 +3487,7 @@ // Load the old link SP. SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); // Restore the stack pointer. Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); @@ -3674,7 +3678,7 @@ FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, DAG.getConstant(4, FIPtr.getValueType())); return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, @@ -3718,7 +3722,7 @@ Ops, 4, MVT::i64, MMO); // Load the value as a double. SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); // FCFID it and return it. SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); @@ -3770,7 +3774,7 @@ SDValue Four = DAG.getConstant(4, PtrVT); SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); // Transform as necessary SDValue CWD1 = @@ -4441,7 +4445,7 @@ false, false, 0); // Load it out. return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { @@ -5729,13 +5733,13 @@ return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), DAG.getNode(ISD::ADD, dl, getPointerTy(), FrameAddr, Offset), - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); } // Just load the return address off the stack. SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), - RetAddrFI, MachinePointerInfo(), false, false, 0); + RetAddrFI, MachinePointerInfo(), false, false, false, 0); } SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, @@ -5758,7 +5762,8 @@ PtrVT); while (Depth--) FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), - FrameAddr, MachinePointerInfo(), false, false, 0); + FrameAddr, MachinePointerInfo(), false, false, + false, 0); return FrameAddr; } Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Tue Nov 8 12:42:53 2011 @@ -175,7 +175,7 @@ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); InVals.push_back(Arg); continue; } @@ -197,7 +197,7 @@ SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } else { unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), &SP::IntRegsRegClass); @@ -237,7 +237,7 @@ SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo(), - false,false, 0); + false,false, false, 0); InVals.push_back(Load); continue; } @@ -248,7 +248,7 @@ SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); int FI2 = MF.getFrameInfo()->CreateFixedObject(4, Offset+4, true); @@ -256,7 +256,7 @@ SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); SDValue WholeValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); @@ -273,7 +273,7 @@ if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } else { ISD::LoadExtType LoadOp = ISD::SEXTLOAD; // Sparc is big endian, so add an offset based on the ObjectVT. @@ -467,13 +467,13 @@ false, false, 0); // Sparc is big-endian, so the high part comes first. SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); // Increment the pointer to the other half. StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getIntPtrConstant(4)); // Load the low part. SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); @@ -897,7 +897,7 @@ SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, GlobalBase, RelAddr); return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), - AbsAddr, MachinePointerInfo(), false, false, 0); + AbsAddr, MachinePointerInfo(), false, false, false, 0); } SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, @@ -918,7 +918,7 @@ SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, GlobalBase, RelAddr); return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), - AbsAddr, MachinePointerInfo(), false, false, 0); + AbsAddr, MachinePointerInfo(), false, false, false, 0); } static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { @@ -1026,7 +1026,7 @@ const Value *SV = cast(Node->getOperand(2))->getValue(); DebugLoc dl = Node->getDebugLoc(); SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, - MachinePointerInfo(SV), false, false, 0); + MachinePointerInfo(SV), false, false, false, 0); // Increment the pointer, VAList, to the next vaarg SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, DAG.getConstant(VT.getSizeInBits()/8, @@ -1038,11 +1038,11 @@ // f64 load. if (VT != MVT::f64) return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); // Otherwise, load it as i64, then do a bitconvert. SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); // Bit-Convert the value to f64. SDValue Ops[2] = { @@ -1103,7 +1103,7 @@ FrameAddr = DAG.getLoad(MVT::i32, dl, Chain, Ptr, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); } } return FrameAddr; @@ -1135,7 +1135,7 @@ RetAddr = DAG.getLoad(MVT::i32, dl, Chain, Ptr, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); } } return RetAddr; Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Nov 8 12:42:53 2011 @@ -1707,7 +1707,7 @@ SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); return DAG.getLoad(ValVT, dl, Chain, FIN, MachinePointerInfo::getFixedStack(FI), - false, false, 0); + false, false, false, 0); } } @@ -1810,7 +1810,7 @@ // If value is passed via pointer - do a load. if (VA.getLocInfo() == CCValAssign::Indirect) ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); InVals.push_back(ArgValue); } @@ -2009,7 +2009,7 @@ // Load the "old" Return address. OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); return SDValue(OutRetAddr.getNode(), 1); } @@ -2371,7 +2371,7 @@ if (ExtraLoad) Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, MachinePointerInfo::getGOT(), - false, false, 0); + false, false, false, 0); } } else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { unsigned char OpFlags = 0; @@ -4982,7 +4982,7 @@ EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(StartOffset), - false, false, 0); + false, false, false, 0); // Canonicalize it to a v4i32 or v8i32 shuffle. SmallVector Mask; @@ -5047,11 +5047,12 @@ if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), LDBase->getPointerInfo(), - LDBase->isVolatile(), LDBase->isNonTemporal(), 0); + LDBase->isVolatile(), LDBase->isNonTemporal(), + LDBase->isInvariant(), 0); return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), LDBase->getPointerInfo(), LDBase->isVolatile(), LDBase->isNonTemporal(), - LDBase->getAlignment()); + LDBase->isInvariant(), LDBase->getAlignment()); } else if (NumElems == 4 && LastLoadedElt == 1 && DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); @@ -7304,7 +7305,7 @@ // load. if (isGlobalStubReference(OpFlag)) Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, - MachinePointerInfo::getGOT(), false, false, 0); + MachinePointerInfo::getGOT(), false, false, false, 0); return Result; } @@ -7372,7 +7373,7 @@ // load. if (isGlobalStubReference(OpFlags)) Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, - MachinePointerInfo::getGOT(), false, false, 0); + MachinePointerInfo::getGOT(), false, false, false, 0); // If there was a non-zero offset that we didn't fold, create an explicit // addition for it. @@ -7451,7 +7452,8 @@ SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0), - MachinePointerInfo(Ptr), false, false, 0); + MachinePointerInfo(Ptr), + false, false, false, 0); unsigned char OperandFlags = 0; // Most TLS accesses are not RIP relative, even on x86-64. One exception is @@ -7477,7 +7479,7 @@ if (model == TLSModel::InitialExec) Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, - MachinePointerInfo::getGOT(), false, false, 0); + MachinePointerInfo::getGOT(), false, false, false, 0); // The address of the thread local variable is the add of the thread // pointer with the offset of the variable. @@ -7701,7 +7703,7 @@ Op.getValueType(), MMO); Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, MachinePointerInfo::getFixedStack(SSFI), - false, false, 0); + false, false, false, 0); } return Result; @@ -7775,12 +7777,12 @@ SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, MachinePointerInfo::getConstantPool(), - false, false, 16); + false, false, false, 16); SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, MachinePointerInfo::getConstantPool(), - false, false, 16); + false, false, false, 16); SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); // Add the halves; easiest way is to swap them into another reg first. @@ -8012,7 +8014,8 @@ // Load the result. return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), - FIST, StackSlot, MachinePointerInfo(), false, false, 0); + FIST, StackSlot, MachinePointerInfo(), + false, false, false, 0); } SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, @@ -8023,7 +8026,8 @@ // Load the result. return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), - FIST, StackSlot, MachinePointerInfo(), false, false, 0); + FIST, StackSlot, MachinePointerInfo(), + false, false, false, 0); } SDValue X86TargetLowering::LowerFABS(SDValue Op, @@ -8050,7 +8054,7 @@ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, MachinePointerInfo::getConstantPool(), - false, false, 16); + false, false, false, 16); return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); } @@ -8077,7 +8081,7 @@ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, MachinePointerInfo::getConstantPool(), - false, false, 16); + false, false, false, 16); if (VT.isVector()) { return DAG.getNode(ISD::BITCAST, dl, VT, DAG.getNode(ISD::XOR, dl, MVT::v2i64, @@ -8126,7 +8130,7 @@ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, MachinePointerInfo::getConstantPool(), - false, false, 16); + false, false, false, 16); SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); // Shift sign bit right or left if the two operands have different types. @@ -8155,7 +8159,7 @@ CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, MachinePointerInfo::getConstantPool(), - false, false, 16); + false, false, false, 16); SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); // Or the value with the sign bit. @@ -9282,7 +9286,7 @@ Chain, VAARG, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { @@ -9608,13 +9612,13 @@ return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), DAG.getNode(ISD::ADD, dl, getPointerTy(), FrameAddr, Offset), - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); } // Just load the return address. SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), - RetAddrFI, MachinePointerInfo(), false, false, 0); + RetAddrFI, MachinePointerInfo(), false, false, false, 0); } SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { @@ -9629,7 +9633,7 @@ while (Depth--) FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); return FrameAddr; } @@ -9861,7 +9865,7 @@ // Load FP Control Word from stack slot SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, - MachinePointerInfo(), false, false, 0); + MachinePointerInfo(), false, false, false, 0); // Transform as necessary SDValue CWD1 = @@ -10201,7 +10205,7 @@ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, MachinePointerInfo::getConstantPool(), - false, false, 16); + false, false, false, 16); Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); @@ -10223,7 +10227,7 @@ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, MachinePointerInfo::getConstantPool(), - false, false, 16); + false, false, false, 16); // r = pblendv(r, psllw(r & (char16)15, 4), a); M = DAG.getNode(ISD::AND, dl, VT, R, M); @@ -10238,7 +10242,7 @@ CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, MachinePointerInfo::getConstantPool(), - false, false, 16); + false, false, false, 16); // r = pblendv(r, psllw(r & (char16)63, 2), a); M = DAG.getNode(ISD::AND, dl, VT, R, M); @@ -10739,7 +10743,8 @@ EVT VT = N->getValueType(0); // Return a load from the stack slot. Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, - MachinePointerInfo(), false, false, 0)); + MachinePointerInfo(), + false, false, false, 0)); } return; } @@ -12807,7 +12812,7 @@ // Load the scalar. SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, ScalarAddr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); // Replace the exact with the load. DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); @@ -13837,7 +13842,8 @@ SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), Ld->isVolatile(), - Ld->isNonTemporal(), Ld->getAlignment()); + Ld->isNonTemporal(), Ld->isInvariant(), + Ld->getAlignment()); // Insert the word loaded into a vector. SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, @@ -14033,7 +14039,8 @@ EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), Ld->isVolatile(), - Ld->isNonTemporal(), Ld->getAlignment()); + Ld->isNonTemporal(), Ld->isInvariant(), + Ld->getAlignment()); SDValue NewChain = NewLd.getValue(1); if (TokenFactorIndex != -1) { Ops.push_back(NewChain); @@ -14054,10 +14061,11 @@ SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(), - Ld->getAlignment()); + Ld->isInvariant(), Ld->getAlignment()); SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, Ld->getPointerInfo().getWithOffset(4), Ld->isVolatile(), Ld->isNonTemporal(), + Ld->isInvariant(), MinAlign(Ld->getAlignment(), 4)); SDValue NewChain = LoLd.getValue(1); Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=144100&r1=144099&r2=144100&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Nov 8 12:42:53 2011 @@ -427,7 +427,7 @@ // return DAG.getLoad(getPointerTy(), DL, Chain, BasePtr, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } // Lower to // ldw low, base[offset >> 2] @@ -444,9 +444,11 @@ SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, HighOffset); SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain, - LowAddr, MachinePointerInfo(), false, false, 0); + LowAddr, MachinePointerInfo(), + false, false, false, 0); SDValue High = DAG.getLoad(getPointerTy(), DL, Chain, - HighAddr, MachinePointerInfo(), false, false, 0); + HighAddr, MachinePointerInfo(), + false, false, false, 0); SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift); SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift); SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted); @@ -761,7 +763,7 @@ EVT VT = Node->getValueType(0); SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0), Node->getOperand(1), MachinePointerInfo(V), - false, false, 0); + false, false, false, 0); // Increment the pointer, VAList, to the next vararg SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList, DAG.getConstant(VT.getSizeInBits(), @@ -771,7 +773,7 @@ MachinePointerInfo(V), false, false, 0); // Load the actual argument out of the pointer VAList return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); } SDValue XCoreTargetLowering:: @@ -1146,7 +1148,7 @@ SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, MachinePointerInfo::getFixedStack(FI), - false, false, 0)); + false, false, false, 0)); } } From tonic at nondot.org Tue Nov 8 12:55:57 2011 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 08 Nov 2011 18:55:57 -0000 Subject: [llvm-commits] [www] r144101 - /www/trunk/devmtg/2011-09-16/index.html Message-ID: <20111108185557.E2BFA2A6C12C@llvm.org> Author: tbrethou Date: Tue Nov 8 12:55:57 2011 New Revision: 144101 URL: http://llvm.org/viewvc/llvm-project?rev=144101&view=rev Log: Add videos. Modified: www/trunk/devmtg/2011-09-16/index.html Modified: www/trunk/devmtg/2011-09-16/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-09-16/index.html?rev=144101&r1=144100&r2=144101&view=diff ============================================================================== --- www/trunk/devmtg/2011-09-16/index.html (original) +++ www/trunk/devmtg/2011-09-16/index.html Tue Nov 8 12:55:57 2011 @@ -46,6 +46,8 @@
    TimeTalkLocation
    8:00 - 9:00Light BreakfastTBD
    9:00 - 9:20Welcome
    Chris Lattner, Apple Inc.    		Ballroom Salon III/IV
    9:20 - 10:05Using clang in the Chromium project
    Nico Weber, Hans Wennborg, Google    		Ballroom Salon III/IV
    8:00 - 9:00Light BreakfastTBD
    9:00 - 9:20Welcome
    Chris Lattner, Apple Inc.    		Ballroom Salon III/IV
    9:20 - 10:05Using clang in the Chromium project
    Nico Weber, Hans Wennborg, Google    		Ballroom Salon III/IV
    9:20 - 10:05Extending Clang
    Doug Gregor, Apple Inc.    		Ballroom Salon III/IV
    Intel OpenCL SDK Vectorizer
    Nadav Rotem, Intel    		Ballroom Salon V/VI
    10:05 - 10:50Clang MapReduce -- Automatic C++ Refactoring at Google Scale
    Chandler Carruth, Google    		Ballroom Salon III/IV
    10:50 - 11:05BreakTBD
    11:05 - 11:50Extending Clang
    Doug Gregor, Apple Inc.    		Ballroom Salon III/IV
    11:05 - 11:50Integrating LLVM into FreeBSD
    Brooks Davis, The FreeBSD Proje +ct    		Ballroom Salon III/IV
    Porting LLVM to a Next Generation DSP
    Taylor Simpson, QuIC    		Ballroom Salon V/VI
    11:50 - 12:35DXR: Semantic Code Browsing with Clang
    Joshua Cranmer, Mozilla    		Ballroom Salon III/IV
    12:35 - 1:35LunchTBD
    1:35 - 2:20Integrating LLVM into FreeBSD
    Brooks Davis, The FreeBSD Project    		Ballroom Salon III/IV
    1:35 - 2:20Using clang in the Chromium project
    Nico Weber, Hans Wennborg, Google    		Ballroom Salon III/IV
    Polly - First successful optimizations - How to proceed?
    Tobias Grosser, ENS/INRIA    		Ballroom Salon V/VI
    MC Linkers BOF
    Luba Tang, Mediateki, Shih-wei Liao, Google    		Ballroom Salon II
    [ Slides ] +

    [Video] (Computer) +
    [Video] (Mobile)

    		 Handling Multi-Versioning in LLVM: Code Tracking and Cloning
    @@ -56,6 +58,8 @@
    [ Slides ] +

    [Video] (Computer) +
    [Video] (Mobile)

    		 More Target Independent LLVM Bitcode
    @@ -66,6 +70,8 @@
    [ Slides ] +

    [Video] (Computer) +
    [Video] (Mobile)

    		 Jet: A Language and Heterogeneous Compiler for Fluid Simulations
    @@ -76,6 +82,8 @@
    [ Slides ] +

    [Video] (Computer) +
    [Video] (Mobile)

    		 LLVM+ARM: Status of ARM platform support in LLVM and more
    From lhames at gmail.com Tue Nov 8 12:56:23 2011 From: lhames at gmail.com (Lang Hames) Date: Tue, 08 Nov 2011 18:56:23 -0000 Subject: [llvm-commits] [llvm] r144102 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2011-10-26-memset-inline.ll Message-ID: <20111108185624.03DF42A6C12C@llvm.org> Author: lhames Date: Tue Nov 8 12:56:23 2011 New Revision: 144102 URL: http://llvm.org/viewvc/llvm-project?rev=144102&view=rev Log: Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-inline.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=144102&r1=144101&r2=144102&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Nov 8 12:56:23 2011 @@ -4564,6 +4564,16 @@ SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { switch (V.getOpcode()) { default: break; + case ISD::Constant: { + const ConstantSDNode *CV = cast(V.getNode()); + assert(CV != 0 && "Const value should be ConstSDNode."); + const APInt &CVal = CV->getAPIntValue(); + APInt NewVal = CVal & Mask; + if (NewVal != CVal) { + return DAG.getConstant(NewVal, V.getValueType()); + } + break; + } case ISD::OR: case ISD::XOR: // If the LHS or RHS don't contribute bits to the or, drop them. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=144102&r1=144101&r2=144102&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Nov 8 12:56:23 2011 @@ -8171,6 +8171,13 @@ } } + // Lowering to i32/i16 if the size permits. + if (Size >= 4) { + return MVT::i32; + } else if (Size >= 2) { + return MVT::i16; + } + // Let the target-independent logic figure it out. return MVT::Other; } Modified: llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-inline.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-inline.ll?rev=144102&r1=144101&r2=144102&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-inline.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-inline.ll Tue Nov 8 12:56:23 2011 @@ -1,14 +1,17 @@ ; Make sure short memsets on ARM lower to stores, even when optimizing for size. -; RUN: llc -march=arm < %s | FileCheck %s +; RUN: llc -march=arm < %s | FileCheck %s -check-prefix=CHECK-GENERIC +; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s -check-prefix=CHECK-UNALIGNED target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target triple = "thumbv7-apple-ios5.0.0" -; CHECK: strb -; CHECK-NEXT: strb -; CHECK-NEXT: strb -; CHECK-NEXT: strb -; CHECK-NEXT: strb +; CHECK-GENERIC: strb +; CHECK-GENERIT-NEXT: strb +; CHECK-GENERIT-NEXT: strb +; CHECK-GENERIT-NEXT: strb +; CHECK-GENERIT-NEXT: strb +; CHECK-UNALIGNED: strb +; CHECK-UNALIGNED-NEXT: str define void @foo(i8* nocapture %c) nounwind optsize { entry: call void @llvm.memset.p0i8.i64(i8* %c, i8 -1, i64 5, i32 1, i1 false) From tonic at nondot.org Tue Nov 8 13:00:43 2011 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 08 Nov 2011 19:00:43 -0000 Subject: [llvm-commits] [www] r144103 - /www/trunk/devmtg/2011-11/index.html Message-ID: <20111108190043.8D36E2A6C12D@llvm.org> Author: tbrethou Date: Tue Nov 8 13:00:43 2011 New Revision: 144103 URL: http://llvm.org/viewvc/llvm-project?rev=144103&view=rev Log: Add break and food room. Modified: www/trunk/devmtg/2011-11/index.html Modified: www/trunk/devmtg/2011-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=144103&r1=144102&r2=144103&view=diff ============================================================================== --- www/trunk/devmtg/2011-11/index.html (original) +++ www/trunk/devmtg/2011-11/index.html Tue Nov 8 13:00:43 2011 @@ -88,7 +88,7 @@ - + @@ -98,7 +98,7 @@ - + @@ -117,7 +117,7 @@ - + From peter_cooper at apple.com Tue Nov 8 13:06:53 2011 From: peter_cooper at apple.com (Pete Cooper) Date: Tue, 08 Nov 2011 19:06:53 -0000 Subject: [llvm-commits] [llvm] r144104 - /llvm/trunk/test/CodeGen/X86/hoist-invariant-load.ll Message-ID: <20111108190653.798C42A6C12F@llvm.org> Author: pete Date: Tue Nov 8 13:06:53 2011 New Revision: 144104 URL: http://llvm.org/viewvc/llvm-project?rev=144104&view=rev Log: Adding test for machine-licm operating on invariant load instructions Added: llvm/trunk/test/CodeGen/X86/hoist-invariant-load.ll Added: llvm/trunk/test/CodeGen/X86/hoist-invariant-load.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hoist-invariant-load.ll?rev=144104&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/hoist-invariant-load.ll (added) +++ llvm/trunk/test/CodeGen/X86/hoist-invariant-load.ll Tue Nov 8 13:06:53 2011 @@ -0,0 +1,29 @@ +; RUN: llc < %s -stats -O2 |& grep "1 machine-licm" + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.2" + +@"\01L_OBJC_METH_VAR_NAME_" = internal global [4 x i8] c"foo\00", section "__TEXT,__objc_methname,cstring_literals", align 1 +@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip" +@"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] [i32 0, i32 16], section "__DATA, __objc_imageinfo, regular, no_dead_strip" + at llvm.used = appending global [3 x i8*] [i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*)], section "llvm.metadata" + +define void @test(i8* %x) uwtable ssp { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %0 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", align 8, !invariant.load !0 + %call = tail call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %x, i8* %0) + %inc = add i32 %i.01, 1 + %exitcond = icmp eq i32 %inc, 10000 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} + +declare i8* @objc_msgSend(i8*, i8*, ...) nonlazybind + +!0 = metadata !{} From echristo at apple.com Tue Nov 8 13:16:01 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 08 Nov 2011 19:16:01 -0000 Subject: [llvm-commits] [llvm] r144105 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20111108191601.997092A6C12E@llvm.org> Author: echristo Date: Tue Nov 8 13:16:01 2011 New Revision: 144105 URL: http://llvm.org/viewvc/llvm-project?rev=144105&view=rev Log: Add the base ObjC method name to the names lookup table as well. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=144105&r1=144104&r2=144105&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Nov 8 13:16:01 2011 @@ -552,6 +552,10 @@ return; } +static StringRef getObjCMethodName(StringRef In) { + return In.slice(In.find(' ') + 1, In.find(']')); +} + /// construct SubprogramDIE - Construct subprogram DIE. void DwarfDebug::constructSubprogramDIE(CompileUnit *TheCU, const MDNode *N) { @@ -599,6 +603,8 @@ TheCU->addAccelObjC(Class, SubprogramDie); if (Category != "") TheCU->addAccelObjC(Category, SubprogramDie); + // Also add the base method name to the name table. + TheCU->addAccelName(getObjCMethodName(SP.getName()), SubprogramDie); } return; From tonic at nondot.org Tue Nov 8 13:19:11 2011 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 08 Nov 2011 19:19:11 -0000 Subject: [llvm-commits] [www] r144106 - /www/trunk/devmtg/2011-11/index.html Message-ID: <20111108191911.9E7112A6C12E@llvm.org> Author: tbrethou Date: Tue Nov 8 13:19:11 2011 New Revision: 144106 URL: http://llvm.org/viewvc/llvm-project?rev=144106&view=rev Log: Fix typo. Modified: www/trunk/devmtg/2011-11/index.html Modified: www/trunk/devmtg/2011-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=144106&r1=144105&r2=144106&view=diff ============================================================================== --- www/trunk/devmtg/2011-11/index.html (original) +++ www/trunk/devmtg/2011-11/index.html Tue Nov 8 13:19:11 2011 @@ -111,7 +111,7 @@ - + From tobias at grosser.es Tue Nov 8 13:24:55 2011 From: tobias at grosser.es (Tobias Grosser) Date: Tue, 08 Nov 2011 20:24:55 +0100 Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass In-Reply-To: <1320762963.19359.117.camel@sapling> References: <1319909412.23036.851.camel@sapling> <1319914924.23036.852.camel@sapling> <1319919418.23036.881.camel@sapling> <1319928991.23036.957.camel@sapling> <1320108633.23036.1266.camel@sapling> <1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling> <1320191694.23036.1497.camel@sapling> <1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling> Message-ID: <4EB98207.2070807@grosser.es> On 11/08/2011 03:36 PM, Hal Finkel wrote: > On Tue, 2011-11-08 at 12:12 +0100, Tobias Grosser wrote: >> On 11/08/2011 11:45 AM, Hal Finkel wrote: >>> I've attached the latest version of my autovectorization patch. >>> >>> Working through the test suite has proved to be a productive >>> experience ;) -- And almost all of the bugs that it revealed have now >>> been fixed. There are still two programs that don't compile with >>> vectorization turned on, and I'm working on those now, but in case >>> anyone feels like playing with vectorization, this patch will probably >>> work for you. >> >> Hey Hal, >> >> those are great news. Especially as the numbers seem to show that >> vectorization has a significant performance impact. What did you compare >> exactly. 'clang -O3' against 'clang -O3 -mllvm -vectorize'? > > Yes. [I've tested the current patch directly using opt -vectorize > -unroll-allow-partial; for running the test suite I recompiled > llvm/clang to hardcode the options as I wanted them]. You should not need to hack clang. As shown above, you should be able to pass '-vectorize' to the optimizer by using '-mllvm -vectorize' in your CFLAGS. Did you run the test suite at -O3? Also I think it would be interesting to compare for the test-suite the performance of 'clang -O3 -mllvm -unroll-allow-partial' with 'clang -O3 -mllvm -unroll-allow-partial -mllvm -vectorize'. It will show how much of the runtime overhead is due to the unrolling (produces more code that needs to be optimized) and which part is due to vectorization. The same counts for the speedup. How much is caused by unrolling and how much is actually caused by your pass. >>> The largest three performance speedups are: >>> SingleSource/Benchmarks/BenchmarkGame/puzzle - 59.2% speedup >>> SingleSource/UnitTests/Vector/multiplies - 57.7% speedup >>> SingleSource/Benchmarks/Misc/flops-7 - 50.75% speedup >>> >>> The largest three performance slowdowns are: >>> MultiSource/Benchmarks/MiBench/security-rijndael/security-rijndael - >>> 114% slowdown >>> MultiSource/Benchmarks/MiBench/network-patricia/network-patricia - 66.6% >>> slowdown >>> SingleSource/Benchmarks/Misc/flops-8 - 64.2% slowdown >>> >> Interesting. Do you understand what causes these slowdowns? Can your >> heuristic be improved? > > I've not specifically looked at these cases. > > Generally, I've observed slowdowns from the introduction of too many > permutations per chain (the chain selection procedure can be changed to > help this, and I'll work on that). Also, sometimes legalization of > non-native vector operations creates inefficient code, and I'll also > look at these cases in more detail. Sure. That sounds reasonable. I am confident you can improve this gradually. >> If I understood correctly it seems your vectorizer has quadratic >> complexity which may cause large slowdowns. Do you think it may be >> useful/possible to make it linear by introducing a constant upper bound >> somewhere? E.g. limiting it to 10/20/100 steps. Maybe we are lucky and >> most of the vectorization opportunities are close by (in some sense), >> such that we get most of the speedup by locking at a subset of the problem. > > Yes, I agree. That makes a lot of sense. > > What would be even better is if the loop unroller would intermix > statements from the loops where possible instead of leaving it to the > vectorizer to do all of the grouping after the fact. That, I fear, is a > whole other project. First, I do not understand the 'even better' here. To me it would be great if on one hand the vectorizer could be constrained, such that the compile time is predictable. And on the other hand, we could make the loop unroller create code in a way such that the constrained vectorizer still performs the relevant transformations. Also, what do you mean with 'if the loop unroller would intermix statements from the loops where possible'. Are you referring to the grouped unrolling as shown in my the last mail? >>> Compared to previous patches, which had a minimum required chain length >>> of 3 or 4, I've now made the default 6. While using a chain length of 4 >>> worked well for targeted benchmarks, it caused an overall slowdown on >>> almost all test-suite programs. Using a minimum length of 6 causes, on >>> average, a speedup; so I think that is a better default choice. >> >> I also try to understand if it is possible to use your vectorizer for >> Polly. My idea is to do some clever loop unrolling. >> >> Starting from this loop. >> >> for (int i = 0; i< 4; i++) >> A[i] += 1; >> A[i] = B[i] + 3; >> C[i] = A[i]; >> >> The classical unroller would create this code: >> >> A[0] += 1; >> A[0] = B[i] + 3; >> C[0] = A[i]; >> >> A[1] += 1; >> A[1] = B[i] + 3; >> C[1] = A[i]; >> >> A[2] += 1; >> A[2] = B[i] + 3; >> C[2] = A[i]; >> >> A[3] += 1; >> A[3] = B[i] + 3; >> C[3] = A[i]; >> >> However, in case I can prove this loop is parallel, I want to create >> this code: >> >> A[0] += 1; >> A[1] += 1; >> A[2] += 1; >> A[3] += 1; >> >> A[0] = B[i] + 3; >> A[1] = B[i] + 3; >> A[2] = B[i] + 3; >> A[3] = B[i] + 3; >> >> C[0] = A[i]; >> C[1] = A[i]; >> C[2] = A[i]; >> C[3] = A[i]; >> >> I assume this will allow the vectorization of test cases, that failed >> because of possible aliasing. However, I am more interested, if the >> execution order change could also improve the vectorization outcome or >> reduce compile time overhead of your vectorizer. > > Yes, this would certainly help. In which way? How much? Would it be possible to restrict the vectorizer such that it's complexity is linear, while at the same time we can ensure it will still vectorize code that is 'group unrolled' (which means unrolled in the way shown above? > By the way, the current implementation, by default, it will create > unaligned vector loads and stores, but these are generally broken up by > the legalizer. This behavior can be suppressed using the > -bb-vectorize-aligned-only flag. It would be nice if the loop unroller > chose the unrolling factor to preserve the maximum available alignment, > but I don't think that it currently does so. I don't know, but it sounds like a good thing to do. > One problem with the current implementation is that it relies on > GetPointerBaseWithConstantOffset to determine if two loads or stores > share the same base address. This fails with partially-unrolled loops > because it cannot "undo" all of the additions to the offset induction > variable in order to understand that some of the loads and stores are > really adjacent in memory. This is something that I think can be > improved within the vectorizer itself, and I'm planning on doing some > work on this in the future. Here you may also want to look into ScalarEvolution. Basically two loads access adjacent memory if the difference of the scalar evolution of the two load addresses is equal to sizeof(element_type). ScalarEvolution should be a lot more general than GetPointerBaseWithConstantOffset(). Cheers Tobi From peter_cooper at apple.com Tue Nov 8 13:30:01 2011 From: peter_cooper at apple.com (Pete Cooper) Date: Tue, 08 Nov 2011 19:30:01 -0000 Subject: [llvm-commits] [llvm] r144107 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/hoist-invariant-load.ll Message-ID: <20111108193001.282A72A6C12C@llvm.org> Author: pete Date: Tue Nov 8 13:30:00 2011 New Revision: 144107 URL: http://llvm.org/viewvc/llvm-project?rev=144107&view=rev Log: LICM pass now understands invariant load metadata. Nothing generates this yet so it will currently never get used in real tests Added: llvm/trunk/test/Transforms/LICM/hoist-invariant-load.ll Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=144107&r1=144106&r2=144107&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Tue Nov 8 13:30:00 2011 @@ -369,6 +369,8 @@ // in the same alias set as something that ends up being modified. if (AA->pointsToConstantMemory(LI->getOperand(0))) return true; + if (LI->getMetadata(LI->getContext().getMDKindID("invariant.load"))) + return true; // Don't hoist loads which have may-aliased stores in loop. uint64_t Size = 0; Added: llvm/trunk/test/Transforms/LICM/hoist-invariant-load.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/hoist-invariant-load.ll?rev=144107&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LICM/hoist-invariant-load.ll (added) +++ llvm/trunk/test/Transforms/LICM/hoist-invariant-load.ll Tue Nov 8 13:30:00 2011 @@ -0,0 +1,39 @@ +; RUN: opt < %s -licm -stats -S |& grep "1 licm" + +@"\01L_OBJC_METH_VAR_NAME_" = internal global [4 x i8] c"foo\00", section "__TEXT,__objc_methname,cstring_literals", align 1 +@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip" +@"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] [i32 0, i32 16], section "__DATA, __objc_imageinfo, regular, no_dead_strip" + at llvm.used = appending global [3 x i8*] [i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*)], section "llvm.metadata" + +define void @test(i8* %x) uwtable ssp { +entry: + %x.addr = alloca i8*, align 8 + %i = alloca i32, align 4 + store i8* %x, i8** %x.addr, align 8 + store i32 0, i32* %i, align 4 + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %0 = load i32* %i, align 4 + %cmp = icmp ult i32 %0, 10000 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + %1 = load i8** %x.addr, align 8 + %2 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_", !invariant.load !0 + %call = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %1, i8* %2) + br label %for.inc + +for.inc: ; preds = %for.body + %3 = load i32* %i, align 4 + %inc = add i32 %3, 1 + store i32 %inc, i32* %i, align 4 + br label %for.cond + +for.end: ; preds = %for.cond + ret void +} + +declare i8* @objc_msgSend(i8*, i8*, ...) nonlazybind + +!0 = metadata !{} From eli.friedman at gmail.com Tue Nov 8 13:50:00 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 8 Nov 2011 11:50:00 -0800 Subject: [llvm-commits] [zorg] r143963 - /zorg/trunk/buildbot/osuosl/master/config/builders.py In-Reply-To: <20111107170050.E01A12A6C12C@llvm.org> References: <20111107170050.E01A12A6C12C@llvm.org> Message-ID: On Mon, Nov 7, 2011 at 9:00 AM, Duncan Sands wrote: > Author: baldrick > Date: Mon Nov ?7 11:00:50 2011 > New Revision: 143963 > > URL: http://llvm.org/viewvc/llvm-project?rev=143963&view=rev > Log: > Recent gcc miscompiles these - they are expected to fail. > > Modified: > ? ?zorg/trunk/buildbot/osuosl/master/config/builders.py > > Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py > URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=143963&r1=143962&r2=143963&view=diff > ============================================================================== > --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) > +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Nov ?7 11:00:50 2011 > @@ -146,6 +146,8 @@ > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?gxxincludedir='/usr/include/c++/4.2.1')}, > > ?clang_i386_linux_xfails = [ > + ? ?'GCC.MultiSource/Applications/siod/siod', > + ? ?'GCC.MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame', > ? ? 'GCCAS.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', > ? ? 'Bytecode.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', > ? ? 'LLC.MultiSource/Applications/oggenc/oggenc', It looks like the same failures are showing up at http://lab.llvm.org:8011/builders/clang-x86_64-debian-fnt/builds/1175/steps/make.test-suite/logs/fail.GCC . Mind fixing that bot as well? -Eli From bigcheesegs at gmail.com Tue Nov 8 13:52:32 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 08 Nov 2011 19:52:32 -0000 Subject: [llvm-commits] [llvm] r144111 - /llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp Message-ID: <20111108195232.CAB282A6C12C@llvm.org> Author: mspencer Date: Tue Nov 8 13:52:32 2011 New Revision: 144111 URL: http://llvm.org/viewvc/llvm-project?rev=144111&view=rev Log: MC/COFF: Correctly emit the size of an empty string table. Modified: llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp Modified: llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp?rev=144111&r1=144110&r2=144111&view=diff ============================================================================== --- llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/WinCOFFObjectWriter.cpp Tue Nov 8 13:52:32 2011 @@ -281,6 +281,7 @@ // The string table data begins with the length of the entire string table // including the length header. Allocate space for this header. Data.resize(4); + update_length(); } size_t StringTable::size() const { From baldrick at free.fr Tue Nov 8 14:20:22 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 08 Nov 2011 21:20:22 +0100 Subject: [llvm-commits] [zorg] r143963 - /zorg/trunk/buildbot/osuosl/master/config/builders.py In-Reply-To: References: <20111107170050.E01A12A6C12C@llvm.org> Message-ID: <4EB98F06.7080105@free.fr> Hi Eli, >> --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) >> +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Nov 7 11:00:50 2011 >> @@ -146,6 +146,8 @@ >> gxxincludedir='/usr/include/c++/4.2.1')}, >> >> clang_i386_linux_xfails = [ >> + 'GCC.MultiSource/Applications/siod/siod', >> + 'GCC.MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame', >> 'GCCAS.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', >> 'Bytecode.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', >> 'LLC.MultiSource/Applications/oggenc/oggenc', > > It looks like the same failures are showing up at > http://lab.llvm.org:8011/builders/clang-x86_64-debian-fnt/builds/1175/steps/make.test-suite/logs/fail.GCC > . Mind fixing that bot as well? it's the same bot. This change didn't fix it - not sure why. Ciao, Duncan. From stoklund at 2pi.dk Tue Nov 8 14:57:04 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 08 Nov 2011 20:57:04 -0000 Subject: [llvm-commits] [llvm] r144117 - /llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Message-ID: <20111108205704.CF63B2A6C12C@llvm.org> Author: stoklund Date: Tue Nov 8 14:57:04 2011 New Revision: 144117 URL: http://llvm.org/viewvc/llvm-project?rev=144117&view=rev Log: Clear old DomainValue after merging. The old value may still be referenced by some live-out list, and we don't wan't to collapse those instructions twice. This fixes the "Can only swizzle VMOVD" assertion in some armv7 SPEC builds. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144117&r1=144116&r2=144117&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Tue Nov 8 14:57:04 2011 @@ -266,6 +266,11 @@ A->AvailableDomains = common; A->Dist = std::max(A->Dist, B->Dist); A->Instrs.append(B->Instrs.begin(), B->Instrs.end()); + + // Clear the old DomainValue so we won't try to swizzle instructions twice. + B->Instrs.clear(); + B->AvailableDomains = 0; + for (unsigned rx = 0; rx != NumRegs; ++rx) if (LiveRegs[rx] == B) SetLiveReg(rx, A); @@ -283,7 +288,7 @@ LiveOutMap::const_iterator fi = LiveOuts.find(*pi); if (fi == LiveOuts.end()) continue; DomainValue *pdv = fi->second[rx]; - if (!pdv) continue; + if (!pdv || !pdv->AvailableDomains) continue; if (!LiveRegs || !LiveRegs[rx]) { SetLiveReg(rx, pdv); continue; From eli.friedman at gmail.com Tue Nov 8 15:08:03 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 08 Nov 2011 21:08:03 -0000 Subject: [llvm-commits] [llvm] r144121 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/InstSimplify/compare.ll Message-ID: <20111108210803.0FF082A6C12C@llvm.org> Author: efriedma Date: Tue Nov 8 15:08:02 2011 New Revision: 144121 URL: http://llvm.org/viewvc/llvm-project?rev=144121&view=rev Log: Fix code to match comment. Fixes PR11340, a regression from r143209. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp llvm/trunk/test/Transforms/InstSimplify/compare.ll Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=144121&r1=144120&r2=144121&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Tue Nov 8 15:08:02 2011 @@ -1612,7 +1612,7 @@ Lower = (-Upper) + 1; } else if (match(LHS, m_UDiv(m_ConstantInt(CI2), m_Value()))) { // 'udiv CI2, x' produces [0, CI2]. - Upper = CI2->getValue(); + Upper = CI2->getValue() + 1; } else if (match(LHS, m_UDiv(m_Value(), m_ConstantInt(CI2)))) { // 'udiv x, CI2' produces [0, UINT_MAX / CI2]. APInt NegOne = APInt::getAllOnesValue(Width); Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=144121&r1=144120&r2=144121&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original) +++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Tue Nov 8 15:08:02 2011 @@ -342,6 +342,16 @@ ; CHECK: ret i1 false } +; PR11340 +define i1 @udiv6(i32 %X) nounwind { +; CHECK: @udiv6 + %A = udiv i32 1, %X + %C = icmp eq i32 %A, 0 + ret i1 %C +; CHECK: ret i1 %C +} + + define i1 @sdiv1(i32 %X) { ; CHECK: @sdiv1 %A = sdiv i32 %X, 1000000 From mcrosier at apple.com Tue Nov 8 15:12:00 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 08 Nov 2011 21:12:00 -0000 Subject: [llvm-commits] [llvm] r144122 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20111108211200.EEF201BE001@llvm.org> Author: mcrosier Date: Tue Nov 8 15:12:00 2011 New Revision: 144122 URL: http://llvm.org/viewvc/llvm-project?rev=144122&view=rev Log: ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. No functional change intended. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144122&r1=144121&r2=144122&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Nov 8 15:12:00 2011 @@ -90,7 +90,7 @@ ARMFunctionInfo *AFI; // Convenience variables to avoid some queries. - bool isThumb; + bool isThumb2; LLVMContext *Context; public: @@ -101,7 +101,7 @@ TLI(*TM.getTargetLowering()) { Subtarget = &TM.getSubtarget(); AFI = funcInfo.MF->getInfo(); - isThumb = AFI->isThumbFunction(); + isThumb2 = AFI->isThumbFunction(); Context = &funcInfo.Fn->getContext(); } @@ -553,7 +553,7 @@ const ConstantInt *CI = cast(C); if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { EVT SrcVT = MVT::i32; - unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16; + unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; unsigned ImmReg = createResultReg(TLI.getRegClassFor(SrcVT)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ImmReg) @@ -575,7 +575,7 @@ } unsigned Idx = MCP.getConstantPoolIndex(C, Align); - if (isThumb) + if (isThumb2) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::t2LDRpci), DestReg) .addConstantPoolIndex(Idx)); @@ -596,7 +596,7 @@ Reloc::Model RelocM = TM.getRelocationModel(); // TODO: Need more magic for ARM PIC. - if (!isThumb && (RelocM == Reloc::PIC_)) return 0; + if (!isThumb2 && (RelocM == Reloc::PIC_)) return 0; // MachineConstantPool wants an explicit alignment. unsigned Align = TD.getPrefTypeAlignment(GV->getType()); @@ -616,7 +616,7 @@ // Load value. MachineInstrBuilder MIB; unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); - if (isThumb) { + if (isThumb2) { unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) .addConstantPoolIndex(Idx); @@ -633,7 +633,7 @@ if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) { unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); - if (isThumb) + if (isThumb2) MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::t2LDRi12), NewDestReg) .addReg(DestReg) @@ -681,7 +681,7 @@ if (SI != FuncInfo.StaticAllocaMap.end()) { TargetRegisterClass* RC = TLI.getRegClassFor(VT); unsigned ResultReg = createResultReg(RC); - unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; + unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addFrameIndex(SI->second) @@ -864,10 +864,10 @@ // put the alloca address into a register, set the base type back to // register and continue. This should almost never happen. if (needsLowering && Addr.BaseType == Address::FrameIndexBase) { - TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass : + TargetRegisterClass *RC = isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; unsigned ResultReg = createResultReg(RC); - unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; + unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addFrameIndex(Addr.Base.FI) @@ -908,7 +908,7 @@ MIB.addFrameIndex(FI); // ARM halfword load/stores need an additional operand. - if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0); + if (!isThumb2 && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0); MIB.addImm(Addr.Offset); MIB.addMemOperand(MMO); @@ -917,7 +917,7 @@ MIB.addReg(Addr.Base.Reg); // ARM halfword load/stores need an additional operand. - if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0); + if (!isThumb2 && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0); MIB.addImm(Addr.Offset); } @@ -933,15 +933,15 @@ // This is mostly going to be Neon/vector support. default: return false; case MVT::i16: - Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH; + Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH; RC = ARM::GPRRegisterClass; break; case MVT::i8: - Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12; + Opc = isThumb2 ? ARM::t2LDRBi12 : ARM::LDRBi12; RC = ARM::GPRRegisterClass; break; case MVT::i32: - Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12; + Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; RC = ARM::GPRRegisterClass; break; case MVT::f32: @@ -990,22 +990,22 @@ // This is mostly going to be Neon/vector support. default: return false; case MVT::i1: { - unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass : + unsigned Res = createResultReg(isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass); - unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri; + unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), Res) .addReg(SrcReg).addImm(1)); SrcReg = Res; } // Fallthrough here. case MVT::i8: - StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12; + StrOpc = isThumb2 ? ARM::t2STRBi12 : ARM::STRBi12; break; case MVT::i16: - StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH; + StrOpc = isThumb2 ? ARM::t2STRHi12 : ARM::STRH; break; case MVT::i32: - StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12; + StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12; break; case MVT::f32: if (!Subtarget->hasVFP2()) return false; @@ -1129,7 +1129,7 @@ if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned())) return false; - unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; + unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); FastEmitBranch(FBB, DL); @@ -1140,7 +1140,7 @@ MVT SourceVT; if (TI->hasOneUse() && TI->getParent() == I->getParent() && (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) { - unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri; + unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; unsigned OpReg = getRegForValue(TI->getOperand(0)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc)) @@ -1152,7 +1152,7 @@ CCMode = ARMCC::EQ; } - unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; + unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); @@ -1178,7 +1178,7 @@ // Regardless, the compare has been done in the predecessor block, // and it left a value for us in a virtual register. Ergo, we test // the one-bit value left in the virtual register. - unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri; + unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc)) .addReg(CmpReg).addImm(1)); @@ -1188,7 +1188,7 @@ CCMode = ARMCC::EQ; } - unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; + unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); FastEmitBranch(FBB, DL); @@ -1223,7 +1223,7 @@ needsExt = true; // Intentional fall-through. case MVT::i32: - CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr; + CmpOpc = isThumb2 ? ARM::t2CMPrr : ARM::CMPrr; break; } @@ -1272,8 +1272,8 @@ // Now set a register based on the comparison. Explicitly set the predicates // here. - unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi; - TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass + unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; + TargetRegisterClass *RC = isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass; unsigned DestReg = createResultReg(RC); Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0); @@ -1418,11 +1418,11 @@ unsigned Op2Reg = getRegForValue(I->getOperand(2)); if (Op2Reg == 0) return false; - unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri; + unsigned CmpOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) .addReg(CondReg).addImm(1)); unsigned ResultReg = createResultReg(RC); - unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr; + unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg) .addReg(Op1Reg).addReg(Op2Reg) .addImm(ARMCC::EQ).addReg(ARM::CPSR); @@ -1788,7 +1788,7 @@ MRI.addLiveOut(VA.getLocReg()); } - unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET; + unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET; AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(RetOpc))); return true; @@ -1798,7 +1798,7 @@ // Darwin needs the r9 versions of the opcodes. bool isDarwin = Subtarget->isTargetDarwin(); - if (isThumb) { + if (isThumb2) { return isDarwin ? ARM::tBLr9 : ARM::tBL; } else { return isDarwin ? ARM::BLr9 : ARM::BL; @@ -1864,7 +1864,7 @@ // TODO: Turn this into the table of arm call ops. MachineInstrBuilder MIB; unsigned CallOpc = ARMSelectCallOp(NULL); - if(isThumb) + if(isThumb2) // Explicitly adding the predicate here. MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))) @@ -1979,7 +1979,7 @@ MachineInstrBuilder MIB; unsigned CallOpc = ARMSelectCallOp(GV); // Explicitly adding the predicate here. - if(isThumb) + if(isThumb2) // Explicitly adding the predicate here. MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))) @@ -2040,20 +2040,20 @@ case MVT::i16: if (!Subtarget->hasV6Ops()) return 0; if (isZExt) - Opc = isThumb ? ARM::t2UXTH : ARM::UXTH; + Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH; else - Opc = isThumb ? ARM::t2SXTH : ARM::SXTH; + Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; break; case MVT::i8: if (!Subtarget->hasV6Ops()) return 0; if (isZExt) - Opc = isThumb ? ARM::t2UXTB : ARM::UXTB; + Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB; else - Opc = isThumb ? ARM::t2SXTB : ARM::SXTB; + Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB; break; case MVT::i1: if (isZExt) { - Opc = isThumb ? ARM::t2ANDri : ARM::ANDri; + Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; isBoolZext = true; break; } From evan.cheng at apple.com Tue Nov 8 15:21:10 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 08 Nov 2011 21:21:10 -0000 Subject: [llvm-commits] [llvm] r144123 - in /llvm/trunk: lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/ldrd.ll Message-ID: <20111108212110.3F2AF2A6C12C@llvm.org> Author: evancheng Date: Tue Nov 8 15:21:09 2011 New Revision: 144123 URL: http://llvm.org/viewvc/llvm-project?rev=144123&view=rev Log: Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/trunk/test/CodeGen/ARM/ldrd.ll Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=144123&r1=144122&r2=144123&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Nov 8 15:21:09 2011 @@ -62,6 +62,7 @@ const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; + const ARMSubtarget *STI; ARMFunctionInfo *AFI; RegScavenger *RS; bool isThumb2; @@ -1071,11 +1072,17 @@ unsigned Opcode = MI->getOpcode(); if (Opcode == ARM::LDRD || Opcode == ARM::STRD || Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) { + const MachineOperand &BaseOp = MI->getOperand(2); + unsigned BaseReg = BaseOp.getReg(); unsigned EvenReg = MI->getOperand(0).getReg(); unsigned OddReg = MI->getOperand(1).getReg(); unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false); unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false); - if ((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum) + // ARM errata 602117: LDRD with base in list may result in incorrect base + // register when interrupted or faulted. + bool Errata602117 = EvenReg == BaseReg && STI->getCPUString() == "cortex-m3"; + if (!Errata602117 && + ((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum)) return false; MachineBasicBlock::iterator NewBBI = MBBI; @@ -1087,8 +1094,6 @@ bool OddDeadKill = isLd ? MI->getOperand(1).isDead() : MI->getOperand(1).isKill(); bool OddUndef = MI->getOperand(1).isUndef(); - const MachineOperand &BaseOp = MI->getOperand(2); - unsigned BaseReg = BaseOp.getReg(); bool BaseKill = BaseOp.isKill(); bool BaseUndef = BaseOp.isUndef(); bool OffKill = isT2 ? false : MI->getOperand(3).isKill(); @@ -1380,6 +1385,7 @@ AFI = Fn.getInfo(); TII = TM.getInstrInfo(); TRI = TM.getRegisterInfo(); + STI = &TM.getSubtarget(); RS = new RegScavenger(); isThumb2 = AFI->isThumb2Function(); Modified: llvm/trunk/test/CodeGen/ARM/ldrd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ldrd.ll?rev=144123&r1=144122&r2=144123&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ldrd.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ldrd.ll Tue Nov 8 15:21:09 2011 @@ -1,21 +1,22 @@ -; RUN: llc < %s -mtriple=armv6-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V6 -; RUN: llc < %s -mtriple=armv5-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V5 -; RUN: llc < %s -mtriple=armv6-eabi -regalloc=linearscan | FileCheck %s -check-prefix=EABI -; rdar://r6949835 +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast | FileCheck %s -check-prefix=A8 +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast | FileCheck %s -check-prefix=M3 +; rdar://6949835 -; Magic ARM pair hints works best with linearscan. +; Magic ARM pair hints works best with linearscan / fast. + +; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base +; register when interrupted or faulted. @b = external global i64* define i64 @t(i64 %a) nounwind readonly { entry: -;V6: ldrd r2, r3, [r2] - -;V5: ldr r{{[0-9]+}}, [r2] -;V5: ldr r{{[0-9]+}}, [r2, #4] +; A8: t: +; A8: ldrd r2, r3, [r2] -;EABI: ldr r{{[0-9]+}}, [r2] -;EABI: ldr r{{[0-9]+}}, [r2, #4] +; M3: t: +; M3-NOT: ldrd +; M3: ldm.w r2, {r2, r3} %0 = load i64** @b, align 4 %1 = load i64* %0, align 4 From echristo at apple.com Tue Nov 8 15:26:02 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 08 Nov 2011 13:26:02 -0800 Subject: [llvm-commits] [llvm] r144122 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp In-Reply-To: <20111108211200.EEF201BE001@llvm.org> References: <20111108211200.EEF201BE001@llvm.org> Message-ID: On Nov 8, 2011, at 1:12 PM, Chad Rosier wrote: > ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. > No functional change intended. That's what this code is there for: // Darwin and thumb1 only for now. const ARMSubtarget *Subtarget = &TM.getSubtarget(); if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() && !DisableARMFastISel) I guess for most of those a thumb2 check is probably better anyhow though, since we use mostly t2 instructions. Thanks! -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111108/5710e8f7/attachment.html From gohman at apple.com Tue Nov 8 15:29:07 2011 From: gohman at apple.com (Dan Gohman) Date: Tue, 08 Nov 2011 21:29:07 -0000 Subject: [llvm-commits] [llvm] r144124 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll Message-ID: <20111108212907.581732A6C12C@llvm.org> Author: djg Date: Tue Nov 8 15:29:06 2011 New Revision: 144124 URL: http://llvm.org/viewvc/llvm-project?rev=144124&view=rev Log: Add a hack to the scheduler to disable pseudo-two-address dependencies in basic blocks containing calls. This works around a problem in which these artificial dependencies can get tied up in calling seqeunce scheduling in a way that makes the graph unschedulable with the current approach of using artificial physical register dependencies for calling sequences. This fixes PR11314. Added: llvm/trunk/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=144124&r1=144123&r2=144124&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Nov 8 15:29:06 2011 @@ -1666,7 +1666,7 @@ protected: bool canClobber(const SUnit *SU, const SUnit *Op); - void AddPseudoTwoAddrDeps(); + void AddPseudoTwoAddrDeps(const TargetInstrInfo *TII); void PrescheduleNodesWithMultipleUses(); void CalculateSethiUllmanNumbers(); }; @@ -2628,7 +2628,7 @@ void RegReductionPQBase::initNodes(std::vector &sunits) { SUnits = &sunits; // Add pseudo dependency edges for two-address nodes. - AddPseudoTwoAddrDeps(); + AddPseudoTwoAddrDeps(TII); // Reroute edges to nodes with multiple uses. if (!TracksRegPressure) PrescheduleNodesWithMultipleUses(); @@ -2855,7 +2855,17 @@ /// one that has a CopyToReg use (more likely to be a loop induction update). /// If both are two-address, but one is commutable while the other is not /// commutable, favor the one that's not commutable. -void RegReductionPQBase::AddPseudoTwoAddrDeps() { +void RegReductionPQBase::AddPseudoTwoAddrDeps(const TargetInstrInfo *TII) { + // If the graph contains any calls, disable this optimization. + // FIXME: This is a kludge to work around the fact that the artificial edges + // can combine with the way call sequences use physical register dependencies + // to model their resource usage to create unschedulable graphs. + for (unsigned i = 0, e = SUnits->size(); i != e; ++i) + for (SDNode *Node = (*SUnits)[i].getNode(); Node; Node = Node->getGluedNode()) + if (Node->isMachineOpcode() && + Node->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) + return; + for (unsigned i = 0, e = SUnits->size(); i != e; ++i) { SUnit *SU = &(*SUnits)[i]; if (!SU->isTwoAddress) Modified: llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll?rev=144124&r1=144123&r2=144124&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll (original) +++ llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll Tue Nov 8 15:29:06 2011 @@ -3,15 +3,9 @@ ; This testcase shouldn't need to spill the -1 value, ; so it should just use pcmpeqd to materialize an all-ones vector. -; For i386, cp load of -1 are folded. -; With -regalloc=greedy, the live range is split before spilling, so the first -; pcmpeq doesn't get folded as a constant pool load. - -; I386-NOT: pcmpeqd -; I386: orps LCPI0_2, %xmm +; I386: pcmpeqd ; I386-NOT: pcmpeqd -; I386: orps LCPI0_2, %xmm ; X86-64: pcmpeqd ; X86-64-NOT: pcmpeqd Added: llvm/trunk/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll?rev=144124&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll (added) +++ llvm/trunk/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll Tue Nov 8 15:29:06 2011 @@ -0,0 +1,16 @@ +; RUN: llc -march=x86 -mcpu=pentium4 -mtriple=i686-none-linux < %s +; PR11314 + +; Make sure the scheduler's hack to insert artificial dependencies to optimize +; two-address instruction scheduling doesn't interfere with the scheduler's +; hack to model call sequences as artificial physical registers. + +define inreg { i64, i64 } @sscanf(i32 inreg %base.1.i) nounwind { +entry: + %conv38.i92.i = sext i32 %base.1.i to i64 + %rem.i93.i = urem i64 10, %conv38.i92.i + %div.i94.i = udiv i64 10, %conv38.i92.i + %a = insertvalue { i64, i64 } undef, i64 %rem.i93.i, 0 + %b = insertvalue { i64, i64 } %a, i64 %div.i94.i, 1 + ret { i64, i64 } %b +} From mcrosier at apple.com Tue Nov 8 15:52:06 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 08 Nov 2011 13:52:06 -0800 Subject: [llvm-commits] [llvm] r144122 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp In-Reply-To: References: <20111108211200.EEF201BE001@llvm.org> Message-ID: <7B5CEA23-8CE7-4F90-9516-EAF99F06315F@apple.com> On Nov 8, 2011, at 1:26 PM, Eric Christopher wrote: > > On Nov 8, 2011, at 1:12 PM, Chad Rosier wrote: > >> ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. >> No functional change intended. > > > That's what this code is there for: > > // Darwin and thumb1 only for now. Shouldn't this read: // Darwin and non-thumb1 for now? > const ARMSubtarget *Subtarget = &TM.getSubtarget(); > if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() && > !DisableARMFastISel) > > I guess for most of those a thumb2 check is probably better anyhow though, since we use mostly t2 instructions. That was exactly my reasoning. Most, if not all, thumb instructions are encoded as thumb2, so I prefer this naming. I doubt we'll be adding support for thumb1 unless there's a performance advantage. > Thanks! > > -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111108/8d30427f/attachment-0001.html From echristo at apple.com Tue Nov 8 15:54:16 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 08 Nov 2011 13:54:16 -0800 Subject: [llvm-commits] [llvm] r144122 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp In-Reply-To: <7B5CEA23-8CE7-4F90-9516-EAF99F06315F@apple.com> References: <20111108211200.EEF201BE001@llvm.org> <7B5CEA23-8CE7-4F90-9516-EAF99F06315F@apple.com> Message-ID: On Nov 8, 2011, at 1:52 PM, Chad Rosier wrote: > > On Nov 8, 2011, at 1:26 PM, Eric Christopher wrote: > >> >> On Nov 8, 2011, at 1:12 PM, Chad Rosier wrote: >> >>> ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. >>> No functional change intended. >> >> >> That's what this code is there for: >> >> // Darwin and thumb1 only for now. > > Shouldn't this read: // Darwin and non-thumb1 for now? > Uh. Yep :) >> const ARMSubtarget *Subtarget = &TM.getSubtarget(); >> if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() && >> !DisableARMFastISel) >> >> I guess for most of those a thumb2 check is probably better anyhow though, since we use mostly t2 instructions. > > That was exactly my reasoning. Most, if not all, thumb instructions are encoded as thumb2, so I prefer this naming. I doubt we'll be adding support for thumb1 unless there's a performance advantage. It's icky :) There are additional contortions for thumb1 on some instructions :) -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111108/68299653/attachment.html From echristo at apple.com Tue Nov 8 15:56:23 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 08 Nov 2011 21:56:23 -0000 Subject: [llvm-commits] [llvm] r144130 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfCompileUnit.cpp DwarfDebug.cpp Message-ID: <20111108215623.59AF82A6C12C@llvm.org> Author: echristo Date: Tue Nov 8 15:56:23 2011 New Revision: 144130 URL: http://llvm.org/viewvc/llvm-project?rev=144130&view=rev Log: Also add the linkage name to the name accelerator tables if it exists and is different than the normal name. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=144130&r1=144129&r2=144130&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Tue Nov 8 15:56:23 2011 @@ -1131,6 +1131,11 @@ if (addToAccelTable) addAccelName(GV.getName(), VariableDIE); + // If the linkage name is different than the name, go ahead and output + // that as well into the name table. + if (GV.getLinkageName() != "" && GV.getName() != GV.getLinkageName()) + addAccelName(GV.getLinkageName(), VariableDIE); + return; } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=144130&r1=144129&r2=144130&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Nov 8 15:56:23 2011 @@ -441,8 +441,15 @@ if (DS.isSubprogram()) TheCU->addPubTypes(DISubprogram(DS)); - if (DS.isSubprogram() && !Scope->isAbstractScope()) - TheCU->addAccelName(DISubprogram(DS).getName(), ScopeDIE); + if (DS.isSubprogram() && !Scope->isAbstractScope()) { + DISubprogram SP = DISubprogram(DS); + TheCU->addAccelName(SP.getName(), ScopeDIE); + + // If the linkage name is different than the name, go ahead and output + // that as well into the name table. + if (SP.getLinkageName() != "" && SP.getName() != SP.getLinkageName()) + TheCU->addAccelName(SP.getLinkageName(), ScopeDIE); + } return ScopeDIE; } @@ -596,6 +603,11 @@ // Add to Accel Names TheCU->addAccelName(SP.getName(), SubprogramDie); + // If the linkage name is different than the name, go ahead and output + // that as well into the name table. + if (SP.getLinkageName() != "" && SP.getName() != SP.getLinkageName()) + TheCU->addAccelName(SP.getLinkageName(), SubprogramDie); + // If this is an Objective-C selector name add it to the ObjC accelerator too. if (isObjCClass(SP.getName())) { StringRef Class, Category; From stoklund at 2pi.dk Tue Nov 8 15:57:44 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 08 Nov 2011 21:57:44 -0000 Subject: [llvm-commits] [llvm] r144131 - /llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Message-ID: <20111108215744.BD7D92A6C12C@llvm.org> Author: stoklund Date: Tue Nov 8 15:57:44 2011 New Revision: 144131 URL: http://llvm.org/viewvc/llvm-project?rev=144131&view=rev Log: Handle reference counts in one function: release(). This new function will decrement the reference count, and collapse a domain value when the last reference is gone. This simplifies DomainValue reference counting, and decouples it from the LiveRegs array. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144131&r1=144130&r2=144131&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Tue Nov 8 15:57:44 2011 @@ -139,7 +139,7 @@ // DomainValue allocation. DomainValue *Alloc(int domain = -1); - void Recycle(DomainValue*); + void release(DomainValue*); // LiveRegs manipulations. void SetLiveReg(int rx, DomainValue *DV); @@ -176,10 +176,19 @@ return dv; } -void ExeDepsFix::Recycle(DomainValue *dv) { - assert(dv && "Cannot recycle NULL"); - dv->clear(); - Avail.push_back(dv); +/// release - Release a reference to DV. When the last reference is released, +/// collapse if needed. +void ExeDepsFix::release(DomainValue *DV) { + assert(DV && DV->Refs && "Bad DomainValue"); + if (--DV->Refs) + return; + + // There are no more DV references. Collapse any contained instructions. + if (DV->AvailableDomains && !DV->isCollapsed()) + Collapse(DV, DV->getFirstDomain()); + + DV->clear(); + Avail.push_back(DV); } /// Set LiveRegs[rx] = dv, updating reference counts. @@ -192,10 +201,8 @@ if (LiveRegs[rx] == dv) return; - if (LiveRegs[rx]) { - assert(LiveRegs[rx]->Refs && "Bad refcount"); - if (--LiveRegs[rx]->Refs == 0) Recycle(LiveRegs[rx]); - } + if (LiveRegs[rx]) + release(LiveRegs[rx]); LiveRegs[rx] = dv; if (dv) ++dv->Refs; } @@ -205,12 +212,8 @@ assert(unsigned(rx) < NumRegs && "Invalid index"); if (!LiveRegs || !LiveRegs[rx]) return; - // Before killing the last reference to an open DomainValue, collapse it to - // the first available domain. - if (LiveRegs[rx]->Refs == 1 && !LiveRegs[rx]->isCollapsed()) - Collapse(LiveRegs[rx], LiveRegs[rx]->getFirstDomain()); - else - SetLiveReg(rx, 0); + release(LiveRegs[rx]); + LiveRegs[rx] = 0; } /// Force register rx into domain. From stoklund at 2pi.dk Tue Nov 8 15:57:47 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 08 Nov 2011 21:57:47 -0000 Subject: [llvm-commits] [llvm] r144132 - /llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Message-ID: <20111108215747.74D612A6C12C@llvm.org> Author: stoklund Date: Tue Nov 8 15:57:47 2011 New Revision: 144132 URL: http://llvm.org/viewvc/llvm-project?rev=144132&view=rev Log: Rename all methods to follow style guide. No functional change. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144132&r1=144131&r2=144132&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Tue Nov 8 15:57:47 2011 @@ -135,18 +135,18 @@ private: // Register mapping. - int RegIndex(unsigned Reg); + int regIndex(unsigned Reg); // DomainValue allocation. - DomainValue *Alloc(int domain = -1); + DomainValue *alloc(int domain = -1); void release(DomainValue*); // LiveRegs manipulations. - void SetLiveReg(int rx, DomainValue *DV); - void Kill(int rx); - void Force(int rx, unsigned domain); - void Collapse(DomainValue *dv, unsigned domain); - bool Merge(DomainValue *A, DomainValue *B); + void setLiveReg(int rx, DomainValue *DV); + void kill(int rx); + void force(int rx, unsigned domain); + void collapse(DomainValue *dv, unsigned domain); + bool merge(DomainValue *A, DomainValue *B); void enterBasicBlock(MachineBasicBlock*); void leaveBasicBlock(MachineBasicBlock*); @@ -161,12 +161,12 @@ /// Translate TRI register number to an index into our smaller tables of /// interesting registers. Return -1 for boring registers. -int ExeDepsFix::RegIndex(unsigned Reg) { +int ExeDepsFix::regIndex(unsigned Reg) { assert(Reg < AliasMap.size() && "Invalid register"); return AliasMap[Reg]; } -DomainValue *ExeDepsFix::Alloc(int domain) { +DomainValue *ExeDepsFix::alloc(int domain) { DomainValue *dv = Avail.empty() ? new(Allocator.Allocate()) DomainValue : Avail.pop_back_val(); @@ -185,14 +185,14 @@ // There are no more DV references. Collapse any contained instructions. if (DV->AvailableDomains && !DV->isCollapsed()) - Collapse(DV, DV->getFirstDomain()); + collapse(DV, DV->getFirstDomain()); DV->clear(); Avail.push_back(DV); } /// Set LiveRegs[rx] = dv, updating reference counts. -void ExeDepsFix::SetLiveReg(int rx, DomainValue *dv) { +void ExeDepsFix::setLiveReg(int rx, DomainValue *dv) { assert(unsigned(rx) < NumRegs && "Invalid index"); if (!LiveRegs) { LiveRegs = new DomainValue*[NumRegs]; @@ -208,7 +208,7 @@ } // Kill register rx, recycle or collapse any DomainValue. -void ExeDepsFix::Kill(int rx) { +void ExeDepsFix::kill(int rx) { assert(unsigned(rx) < NumRegs && "Invalid index"); if (!LiveRegs || !LiveRegs[rx]) return; @@ -217,30 +217,30 @@ } /// Force register rx into domain. -void ExeDepsFix::Force(int rx, unsigned domain) { +void ExeDepsFix::force(int rx, unsigned domain) { assert(unsigned(rx) < NumRegs && "Invalid index"); DomainValue *dv; if (LiveRegs && (dv = LiveRegs[rx])) { if (dv->isCollapsed()) dv->addDomain(domain); else if (dv->hasDomain(domain)) - Collapse(dv, domain); + collapse(dv, domain); else { // This is an incompatible open DomainValue. Collapse it to whatever and // force the new value into domain. This costs a domain crossing. - Collapse(dv, dv->getFirstDomain()); + collapse(dv, dv->getFirstDomain()); assert(LiveRegs[rx] && "Not live after collapse?"); LiveRegs[rx]->addDomain(domain); } } else { // Set up basic collapsed DomainValue. - SetLiveReg(rx, Alloc(domain)); + setLiveReg(rx, alloc(domain)); } } /// Collapse open DomainValue into given domain. If there are multiple /// registers using dv, they each get a unique collapsed DomainValue. -void ExeDepsFix::Collapse(DomainValue *dv, unsigned domain) { +void ExeDepsFix::collapse(DomainValue *dv, unsigned domain) { assert(dv->hasDomain(domain) && "Cannot collapse"); // Collapse all the instructions. @@ -252,12 +252,12 @@ if (LiveRegs && dv->Refs > 1) for (unsigned rx = 0; rx != NumRegs; ++rx) if (LiveRegs[rx] == dv) - SetLiveReg(rx, Alloc(domain)); + setLiveReg(rx, alloc(domain)); } /// Merge - All instructions and registers in B are moved to A, and B is /// released. -bool ExeDepsFix::Merge(DomainValue *A, DomainValue *B) { +bool ExeDepsFix::merge(DomainValue *A, DomainValue *B) { assert(!A->isCollapsed() && "Cannot merge into collapsed"); assert(!B->isCollapsed() && "Cannot merge from collapsed"); if (A == B) @@ -276,7 +276,7 @@ for (unsigned rx = 0; rx != NumRegs; ++rx) if (LiveRegs[rx] == B) - SetLiveReg(rx, A); + setLiveReg(rx, A); return true; } @@ -284,7 +284,7 @@ // Try to coalesce live-out registers from predecessors. for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(), e = MBB->livein_end(); i != e; ++i) { - int rx = RegIndex(*i); + int rx = regIndex(*i); if (rx < 0) continue; for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(), pe = MBB->pred_end(); pi != pe; ++pi) { @@ -293,7 +293,7 @@ DomainValue *pdv = fi->second[rx]; if (!pdv || !pdv->AvailableDomains) continue; if (!LiveRegs || !LiveRegs[rx]) { - SetLiveReg(rx, pdv); + setLiveReg(rx, pdv); continue; } @@ -302,15 +302,15 @@ // We are already collapsed, but predecessor is not. Force him. unsigned domain = LiveRegs[rx]->getFirstDomain(); if (!pdv->isCollapsed() && pdv->hasDomain(domain)) - Collapse(pdv, domain); + collapse(pdv, domain); continue; } // Currently open, merge in predecessor. if (!pdv->isCollapsed()) - Merge(LiveRegs[rx], pdv); + merge(LiveRegs[rx], pdv); else - Force(rx, pdv->getFirstDomain()); + force(rx, pdv->getFirstDomain()); } } } @@ -344,19 +344,19 @@ e = mi->getDesc().getNumOperands(); i != e; ++i) { MachineOperand &mo = mi->getOperand(i); if (!mo.isReg()) continue; - int rx = RegIndex(mo.getReg()); + int rx = regIndex(mo.getReg()); if (rx < 0) continue; - Force(rx, domain); + force(rx, domain); } // Kill all defs and force them. for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { MachineOperand &mo = mi->getOperand(i); if (!mo.isReg()) continue; - int rx = RegIndex(mo.getReg()); + int rx = regIndex(mo.getReg()); if (rx < 0) continue; - Kill(rx); - Force(rx, domain); + kill(rx); + force(rx, domain); } } @@ -373,7 +373,7 @@ e = mi->getDesc().getNumOperands(); i != e; ++i) { MachineOperand &mo = mi->getOperand(i); if (!mo.isReg()) continue; - int rx = RegIndex(mo.getReg()); + int rx = regIndex(mo.getReg()); if (rx < 0) continue; if (DomainValue *dv = LiveRegs[rx]) { // Bitmask of domains that dv and available have in common. @@ -390,7 +390,7 @@ else // Open DomainValue is not compatible with instruction. It is useless // now. - Kill(rx); + kill(rx); } } @@ -410,7 +410,7 @@ DomainValue *dv = LiveRegs[rx]; // This useless DomainValue could have been missed above. if (!dv->getCommonDomains(available)) { - Kill(*i); + kill(*i); continue; } // sorted, uniqued insert. @@ -438,17 +438,17 @@ } DomainValue *latest = doms.pop_back_val(); - if (Merge(dv, latest)) continue; + if (merge(dv, latest)) continue; // If latest didn't merge, it is useless now. Kill all registers using it. for (SmallVector::iterator i=used.begin(), e=used.end(); i != e; ++i) if (LiveRegs[*i] == latest) - Kill(*i); + kill(*i); } // dv is the DomainValue we are going to use for this instruction. if (!dv) - dv = Alloc(); + dv = alloc(); dv->Dist = Distance; dv->AvailableDomains = available; dv->Instrs.push_back(mi); @@ -457,11 +457,11 @@ for (unsigned i = 0, e = mi->getDesc().getNumOperands(); i != e; ++i) { MachineOperand &mo = mi->getOperand(i); if (!mo.isReg()) continue; - int rx = RegIndex(mo.getReg()); + int rx = regIndex(mo.getReg()); if (rx < 0) continue; if (!LiveRegs || !LiveRegs[rx] || (mo.isDef() && LiveRegs[rx]!=dv)) { - Kill(rx); - SetLiveReg(rx, dv); + kill(rx); + setLiveReg(rx, dv); } } } @@ -471,9 +471,9 @@ for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { MachineOperand &mo = mi->getOperand(i); if (!mo.isReg()) continue; - int rx = RegIndex(mo.getReg()); + int rx = regIndex(mo.getReg()); if (rx < 0) continue; - Kill(rx); + kill(rx); } } @@ -529,7 +529,7 @@ LiveRegs = FI->second; for (unsigned i = 0, e = NumRegs; i != e; ++i) if (LiveRegs[i]) - Kill(i); + kill(i); delete[] LiveRegs; } LiveOuts.clear(); From eli.friedman at gmail.com Tue Nov 8 16:03:03 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 8 Nov 2011 14:03:03 -0800 Subject: [llvm-commits] [llvm] r144123 - in /llvm/trunk: lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/ldrd.ll In-Reply-To: <20111108212110.3F2AF2A6C12C@llvm.org> References: <20111108212110.3F2AF2A6C12C@llvm.org> Message-ID: On Tue, Nov 8, 2011 at 1:21 PM, Evan Cheng wrote: > Author: evancheng > Date: Tue Nov ?8 15:21:09 2011 > New Revision: 144123 > > URL: http://llvm.org/viewvc/llvm-project?rev=144123&view=rev > Log: > Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. > > Modified: > ? ?llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp > ? ?llvm/trunk/test/CodeGen/ARM/ldrd.ll > > Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=144123&r1=144122&r2=144123&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Nov ?8 15:21:09 2011 > @@ -62,6 +62,7 @@ > > ? ? const TargetInstrInfo *TII; > ? ? const TargetRegisterInfo *TRI; > + ? ?const ARMSubtarget *STI; > ? ? ARMFunctionInfo *AFI; > ? ? RegScavenger *RS; > ? ? bool isThumb2; > @@ -1071,11 +1072,17 @@ > ? unsigned Opcode = MI->getOpcode(); > ? if (Opcode == ARM::LDRD || Opcode == ARM::STRD || > ? ? ? Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) { > + ? ?const MachineOperand &BaseOp = MI->getOperand(2); > + ? ?unsigned BaseReg = BaseOp.getReg(); > ? ? unsigned EvenReg = MI->getOperand(0).getReg(); > ? ? unsigned OddReg ?= MI->getOperand(1).getReg(); > ? ? unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false); > ? ? unsigned OddRegNum ?= TRI->getDwarfRegNum(OddReg, false); > - ? ?if ((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum) > + ? ?// ARM errata 602117: LDRD with base in list may result in incorrect base > + ? ?// register when interrupted or faulted. > + ? ?bool Errata602117 = EvenReg == BaseReg && STI->getCPUString() == "cortex-m3"; Err, checking getCPUString() seems like a hack; shouldn't this be a subtarget feature? -Eli From stoklund at 2pi.dk Tue Nov 8 16:05:17 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 08 Nov 2011 22:05:17 -0000 Subject: [llvm-commits] [llvm] r144133 - /llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Message-ID: <20111108220518.0C16E2A6C12C@llvm.org> Author: stoklund Date: Tue Nov 8 16:05:17 2011 New Revision: 144133 URL: http://llvm.org/viewvc/llvm-project?rev=144133&view=rev Log: Call release() directly when cleaning up the remaining DomainValues. There is no need to involve the LiveRegs array and kill() any longer. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144133&r1=144132&r2=144133&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Tue Nov 8 16:05:17 2011 @@ -525,12 +525,10 @@ if (FI == LiveOuts.end()) continue; assert(FI->second && "Null entry"); - // The DomainValue is collapsed when the last reference is killed. - LiveRegs = FI->second; for (unsigned i = 0, e = NumRegs; i != e; ++i) - if (LiveRegs[i]) - kill(i); - delete[] LiveRegs; + if (FI->second[i]) + release(FI->second[i]); + delete[] FI->second; } LiveOuts.clear(); Avail.clear(); From evan.cheng at apple.com Tue Nov 8 16:15:25 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 08 Nov 2011 14:15:25 -0800 Subject: [llvm-commits] [llvm] r144123 - in /llvm/trunk: lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/ldrd.ll In-Reply-To: References: <20111108212110.3F2AF2A6C12C@llvm.org> Message-ID: <2FB2AEE3-7586-44D4-9FFC-B0751FBDAA6C@apple.com> On Nov 8, 2011, at 2:03 PM, Eli Friedman wrote: > On Tue, Nov 8, 2011 at 1:21 PM, Evan Cheng wrote: >> Author: evancheng >> Date: Tue Nov 8 15:21:09 2011 >> New Revision: 144123 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=144123&view=rev >> Log: >> Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp >> llvm/trunk/test/CodeGen/ARM/ldrd.ll >> >> Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=144123&r1=144122&r2=144123&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Nov 8 15:21:09 2011 >> @@ -62,6 +62,7 @@ >> >> const TargetInstrInfo *TII; >> const TargetRegisterInfo *TRI; >> + const ARMSubtarget *STI; >> ARMFunctionInfo *AFI; >> RegScavenger *RS; >> bool isThumb2; >> @@ -1071,11 +1072,17 @@ >> unsigned Opcode = MI->getOpcode(); >> if (Opcode == ARM::LDRD || Opcode == ARM::STRD || >> Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) { >> + const MachineOperand &BaseOp = MI->getOperand(2); >> + unsigned BaseReg = BaseOp.getReg(); >> unsigned EvenReg = MI->getOperand(0).getReg(); >> unsigned OddReg = MI->getOperand(1).getReg(); >> unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false); >> unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false); >> - if ((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum) >> + // ARM errata 602117: LDRD with base in list may result in incorrect base >> + // register when interrupted or faulted. >> + bool Errata602117 = EvenReg == BaseReg && STI->getCPUString() == "cortex-m3"; > > Err, checking getCPUString() seems like a hack; shouldn't this be a > subtarget feature? That would make sense if this particular cpu has more than one subtarget features. As it is, I don't see the point. We're using a lot of subtarget bits already. Evan > > -Eli From isanbard at gmail.com Tue Nov 8 16:23:44 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 08 Nov 2011 22:23:44 -0000 Subject: [llvm-commits] [llvm] r144138 - /llvm/trunk/lib/MC/MCDwarf.cpp Message-ID: <20111108222344.218E72A6C12C@llvm.org> Author: void Date: Tue Nov 8 16:23:43 2011 New Revision: 144138 URL: http://llvm.org/viewvc/llvm-project?rev=144138&view=rev Log: Emit the compact unwind *if* we have a compact unwind encoding. *headdesk* Modified: llvm/trunk/lib/MC/MCDwarf.cpp Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=144138&r1=144137&r2=144138&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Tue Nov 8 16:23:43 2011 @@ -1020,7 +1020,7 @@ if (IsEH && MOFI->getCompactUnwindSection()) for (unsigned i = 0, n = Streamer.getNumFrameInfos(); i < n; ++i) { const MCDwarfFrameInfo &Frame = Streamer.getFrameInfo(i); - if (!Frame.CompactUnwindEncoding) + if (Frame.CompactUnwindEncoding) Emitter.EmitCompactUnwind(Streamer, Frame); } From bruno.cardoso at gmail.com Tue Nov 8 16:26:47 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 08 Nov 2011 22:26:47 -0000 Subject: [llvm-commits] [llvm] r144139 - in /llvm/trunk/lib/Target/Mips: InstPrinter/MipsInstPrinter.cpp MipsAsmPrinter.cpp MipsMCInstLower.cpp MipsMCInstLower.h Message-ID: <20111108222647.CB0811BE001@llvm.org> Author: bruno Date: Tue Nov 8 16:26:47 2011 New Revision: 144139 URL: http://llvm.org/viewvc/llvm-project?rev=144139&view=rev Log: Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts. Patch by Jack Carter. Modified: llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Modified: llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp?rev=144139&r1=144138&r2=144139&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp Tue Nov 8 16:26:47 2011 @@ -13,8 +13,10 @@ #define DEBUG_TYPE "asm-printer" #include "MipsInstPrinter.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSymbol.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -74,6 +76,52 @@ printAnnotation(O, Annot); } +static void printExpr(const MCExpr *Expr, raw_ostream &OS) { + int Offset = 0; + const MCSymbolRefExpr *SRE; + + if (const MCBinaryExpr *BE = dyn_cast(Expr)) { + SRE = dyn_cast(BE->getLHS()); + const MCConstantExpr *CE = dyn_cast(BE->getRHS()); + assert(SRE && CE && "Binary expression must be sym+const."); + Offset = CE->getValue(); + } + else if (!(SRE = dyn_cast(Expr))) + assert(false && "Unexpected MCExpr type."); + + MCSymbolRefExpr::VariantKind Kind = SRE->getKind(); + + switch (Kind) { + default: assert(0 && "Invalid kind!"); + case MCSymbolRefExpr::VK_None: break; + case MCSymbolRefExpr::VK_Mips_GPREL: OS << "%gp_rel("; break; + case MCSymbolRefExpr::VK_Mips_GOT_CALL: OS << "%call16("; break; + case MCSymbolRefExpr::VK_Mips_GOT: OS << "%got("; break; + case MCSymbolRefExpr::VK_Mips_ABS_HI: OS << "%hi("; break; + case MCSymbolRefExpr::VK_Mips_ABS_LO: OS << "%lo("; break; + case MCSymbolRefExpr::VK_Mips_TLSGD: OS << "%tlsgd("; break; + case MCSymbolRefExpr::VK_Mips_GOTTPREL: OS << "%gottprel("; break; + case MCSymbolRefExpr::VK_Mips_TPREL_HI: OS << "%tprel_hi("; break; + case MCSymbolRefExpr::VK_Mips_TPREL_LO: OS << "%tprel_lo("; break; + case MCSymbolRefExpr::VK_Mips_GPOFF_HI: OS << "%hi(%neg(%gp_rel("; break; + case MCSymbolRefExpr::VK_Mips_GPOFF_LO: OS << "%lo(%neg(%gp_rel("; break; + case MCSymbolRefExpr::VK_Mips_GOT_DISP: OS << "%got_disp("; break; + case MCSymbolRefExpr::VK_Mips_GOT_PAGE: OS << "%got_page("; break; + case MCSymbolRefExpr::VK_Mips_GOT_OFST: OS << "%got_ofst("; break; + } + + OS << SRE->getSymbol(); + + if (Offset) { + if (Offset > 0) + OS << '+'; + OS << Offset; + } + + if (Kind != MCSymbolRefExpr::VK_None) + OS << ')'; +} + void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); @@ -88,7 +136,7 @@ } assert(Op.isExpr() && "unknown operand kind in printOperand"); - O << *Op.getExpr(); + printExpr(Op.getExpr(), O); } void MipsInstPrinter::printUnsignedImm(const MCInst *MI, int opNum, Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=144139&r1=144138&r2=144139&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Tue Nov 8 16:26:47 2011 @@ -13,13 +13,17 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "mips-asm-printer" -#include "MipsAsmPrinter.h" #include "Mips.h" +#include "MipsAsmPrinter.h" #include "MipsInstrInfo.h" #include "MipsMachineFunction.h" #include "MipsMCInstLower.h" #include "MipsMCSymbolRefExpr.h" #include "InstPrinter/MipsInstPrinter.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/Twine.h" +#include "llvm/Analysis/DebugInfo.h" #include "llvm/BasicBlock.h" #include "llvm/Instructions.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -27,19 +31,17 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/Instructions.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/ADT/SmallString.h" -#include "llvm/ADT/Twine.h" -#include "llvm/Support/TargetRegistry.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/Analysis/DebugInfo.h" using namespace llvm; @@ -50,6 +52,12 @@ Opc == Mips::USW_P8 || Opc == Mips::USH_P8; } +static bool isDirective(unsigned Opc) { + return Opc == Mips::MACRO || Opc == Mips::NOMACRO || + Opc == Mips::REORDER || Opc == Mips::NOREORDER || + Opc == Mips::ATMACRO || Opc == Mips::NOAT; +} + void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { SmallString<128> Str; raw_svector_ostream OS(Str); @@ -62,8 +70,12 @@ MipsMCInstLower MCInstLowering(Mang, *MF, *this); unsigned Opc = MI->getOpcode(); MCInst TmpInst0; + SmallVector MCInsts; MCInstLowering.Lower(MI, TmpInst0); - + + if (!OutStreamer.hasRawTextSupport() && isDirective(Opc)) + return; + // Enclose unaligned load or store with .macro & .nomacro directives. if (isUnalignedLoadStore(Opc)) { MCInst Directive; @@ -75,6 +87,23 @@ return; } + if (!OutStreamer.hasRawTextSupport()) { + // Lower CPLOAD and CPRESTORE + if (Opc == Mips::CPLOAD) { + MCInstLowering.LowerCPLOAD(MI, MCInsts); + for (SmallVector::iterator I = MCInsts.begin(); + I != MCInsts.end(); ++I) + OutStreamer.EmitInstruction(*I); + return; + } + + if (Opc == Mips::CPRESTORE) { + MCInstLowering.LowerCPRESTORE(MI, TmpInst0); + OutStreamer.EmitInstruction(TmpInst0); + return; + } + } + OutStreamer.EmitInstruction(TmpInst0); } @@ -191,7 +220,8 @@ unsigned returnReg = RI.getRARegister(); unsigned stackSize = MF->getFrameInfo()->getStackSize(); - OutStreamer.EmitRawText("\t.frame\t$" + + if (OutStreamer.hasRawTextSupport()) + OutStreamer.EmitRawText("\t.frame\t$" + StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() + "," + Twine(stackSize) + ",$" + StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower()); @@ -212,7 +242,8 @@ } void MipsAsmPrinter::EmitFunctionEntryLabel() { - OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName())); + if (OutStreamer.hasRawTextSupport()) + OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName())); OutStreamer.EmitLabel(CurrentFnSym); } @@ -221,10 +252,12 @@ void MipsAsmPrinter::EmitFunctionBodyStart() { emitFrameDirective(); - SmallString<128> Str; - raw_svector_ostream OS(Str); - printSavedRegsBitmask(OS); - OutStreamer.EmitRawText(OS.str()); + if (OutStreamer.hasRawTextSupport()) { + SmallString<128> Str; + raw_svector_ostream OS(Str); + printSavedRegsBitmask(OS); + OutStreamer.EmitRawText(OS.str()); + } } /// EmitFunctionBodyEnd - Targets can override this to emit stuff after @@ -233,12 +266,13 @@ // There are instruction for this macros, but they must // always be at the function end, and we can't emit and // break with BB logic. - OutStreamer.EmitRawText(StringRef("\t.set\tmacro")); - OutStreamer.EmitRawText(StringRef("\t.set\treorder")); - OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName())); + if (OutStreamer.hasRawTextSupport()) { + OutStreamer.EmitRawText(StringRef("\t.set\tmacro")); + OutStreamer.EmitRawText(StringRef("\t.set\treorder")); + OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName())); + } } - /// isBlockOnlyReachableByFallthough - Return true if the basic block has /// exactly one predecessor and the control transfer mechanism between /// the predecessor and this block is a fall-through. @@ -419,18 +453,22 @@ // FIXME: Use SwitchSection. // Tell the assembler which ABI we are using - OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString())); + if (OutStreamer.hasRawTextSupport()) + OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString())); // TODO: handle O64 ABI - if (Subtarget->isABI_EABI()) { - if (Subtarget->isGP32bit()) - OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32")); - else - OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64")); + if (OutStreamer.hasRawTextSupport()) { + if (Subtarget->isABI_EABI()) { + if (Subtarget->isGP32bit()) + OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32")); + else + OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64")); + } } // return to previous section - OutStreamer.EmitRawText(StringRef("\t.previous")); + if (OutStreamer.hasRawTextSupport()) + OutStreamer.EmitRawText(StringRef("\t.previous")); } MachineLocation Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=144139&r1=144138&r2=144139&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Tue Nov 8 16:26:47 2011 @@ -12,14 +12,14 @@ // //===----------------------------------------------------------------------===// -#include "MipsMCInstLower.h" #include "MipsAsmPrinter.h" #include "MipsInstrInfo.h" -#include "MipsMCSymbolRefExpr.h" +#include "MipsMCInstLower.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/Target/Mangler.h" using namespace llvm; @@ -31,26 +31,26 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO, MachineOperandType MOTy, unsigned Offset) const { - MipsMCSymbolRefExpr::VariantKind Kind; + MCSymbolRefExpr::VariantKind Kind; const MCSymbol *Symbol; switch(MO.getTargetFlags()) { default: assert(0 && "Invalid target flag!"); - case MipsII::MO_NO_FLAG: Kind = MipsMCSymbolRefExpr::VK_Mips_None; break; - case MipsII::MO_GPREL: Kind = MipsMCSymbolRefExpr::VK_Mips_GPREL; break; - case MipsII::MO_GOT_CALL: Kind = MipsMCSymbolRefExpr::VK_Mips_GOT_CALL; break; - case MipsII::MO_GOT: Kind = MipsMCSymbolRefExpr::VK_Mips_GOT; break; - case MipsII::MO_ABS_HI: Kind = MipsMCSymbolRefExpr::VK_Mips_ABS_HI; break; - case MipsII::MO_ABS_LO: Kind = MipsMCSymbolRefExpr::VK_Mips_ABS_LO; break; - case MipsII::MO_TLSGD: Kind = MipsMCSymbolRefExpr::VK_Mips_TLSGD; break; - case MipsII::MO_GOTTPREL: Kind = MipsMCSymbolRefExpr::VK_Mips_GOTTPREL; break; - case MipsII::MO_TPREL_HI: Kind = MipsMCSymbolRefExpr::VK_Mips_TPREL_HI; break; - case MipsII::MO_TPREL_LO: Kind = MipsMCSymbolRefExpr::VK_Mips_TPREL_LO; break; - case MipsII::MO_GPOFF_HI: Kind = MipsMCSymbolRefExpr::VK_Mips_GPOFF_HI; break; - case MipsII::MO_GPOFF_LO: Kind = MipsMCSymbolRefExpr::VK_Mips_GPOFF_LO; break; - case MipsII::MO_GOT_DISP: Kind = MipsMCSymbolRefExpr::VK_Mips_GOT_DISP; break; - case MipsII::MO_GOT_PAGE: Kind = MipsMCSymbolRefExpr::VK_Mips_GOT_PAGE; break; - case MipsII::MO_GOT_OFST: Kind = MipsMCSymbolRefExpr::VK_Mips_GOT_OFST; break; + case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break; + case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break; + case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break; + case MipsII::MO_GOT: Kind = MCSymbolRefExpr::VK_Mips_GOT; break; + case MipsII::MO_ABS_HI: Kind = MCSymbolRefExpr::VK_Mips_ABS_HI; break; + case MipsII::MO_ABS_LO: Kind = MCSymbolRefExpr::VK_Mips_ABS_LO; break; + case MipsII::MO_TLSGD: Kind = MCSymbolRefExpr::VK_Mips_TLSGD; break; + case MipsII::MO_GOTTPREL: Kind = MCSymbolRefExpr::VK_Mips_GOTTPREL; break; + case MipsII::MO_TPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_TPREL_HI; break; + case MipsII::MO_TPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_TPREL_LO; break; + case MipsII::MO_GPOFF_HI: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_HI; break; + case MipsII::MO_GPOFF_LO: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_LO; break; + case MipsII::MO_GOT_DISP: Kind = MCSymbolRefExpr::VK_Mips_GOT_DISP; break; + case MipsII::MO_GOT_PAGE: Kind = MCSymbolRefExpr::VK_Mips_GOT_PAGE; break; + case MipsII::MO_GOT_OFST: Kind = MCSymbolRefExpr::VK_Mips_GOT_OFST; break; } switch (MOTy) { @@ -84,10 +84,67 @@ llvm_unreachable(""); } - return MCOperand::CreateExpr(MipsMCSymbolRefExpr::Create(Kind, Symbol, Offset, - Ctx)); + const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, Ctx); + + if (!Offset) + return MCOperand::CreateExpr(MCSym); + + // Assume offset is never negative. + assert(Offset > 0); + + const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx); + const MCBinaryExpr *AddExpr = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, Ctx); + return MCOperand::CreateExpr(AddExpr); } +// Lower ".cpload $reg" to +// "lui $gp, %hi(_gp_disp)" +// "addiu $gp, $gp, %lo(_gp_disp)" +// "addu $gp. $gp, $reg" +void MipsMCInstLower::LowerCPLOAD(const MachineInstr *MI, + SmallVector& MCInsts) { + MCInst Lui, Addiu, Addu; + StringRef SymName("_gp_disp"); + const MCSymbol *Symbol = Ctx.GetOrCreateSymbol(SymName); + const MCSymbolRefExpr *MCSym; + + // lui $gp, %hi(_gp_disp) + Lui.setOpcode(Mips::LUi); + Lui.addOperand(MCOperand::CreateReg(Mips::GP)); + MCSym = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_Mips_ABS_HI, Ctx); + Lui.addOperand(MCOperand::CreateExpr(MCSym)); + MCInsts.push_back(Lui); + + // addiu $gp, $gp, %lo(_gp_disp) + Addiu.setOpcode(Mips::ADDiu); + Addiu.addOperand(MCOperand::CreateReg(Mips::GP)); + Addiu.addOperand(MCOperand::CreateReg(Mips::GP)); + MCSym = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_Mips_ABS_LO, Ctx); + Addiu.addOperand(MCOperand::CreateExpr(MCSym)); + MCInsts.push_back(Addiu); + + // addu $gp. $gp, $reg + Addu.setOpcode(Mips::ADDu); + Addu.addOperand(MCOperand::CreateReg(Mips::GP)); + Addu.addOperand(MCOperand::CreateReg(Mips::GP)); + const MachineOperand &MO = MI->getOperand(0); + assert(MO.isReg() && "CPLOAD's operand must be a register."); + Addu.addOperand(MCOperand::CreateReg(MO.getReg())); + MCInsts.push_back(Addu); +} + +// Lower ".cprestore offset" to "sw $gp, offset($sp)". +void MipsMCInstLower::LowerCPRESTORE(const MachineInstr *MI, MCInst &OutMI) { + OutMI.clear(); + OutMI.setOpcode(Mips::SW); + OutMI.addOperand(MCOperand::CreateReg(Mips::GP)); + OutMI.addOperand(MCOperand::CreateReg(Mips::SP)); + const MachineOperand &MO = MI->getOperand(0); + assert(MO.isImm() && "CPRESTORE's operand must be an immediate."); + OutMI.addOperand(MCOperand::CreateImm(MO.getImm())); +} + + MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO) const { MachineOperandType MOTy = MO.getType(); Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.h?rev=144139&r1=144138&r2=144139&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.h (original) +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Tue Nov 8 16:26:47 2011 @@ -9,6 +9,7 @@ #ifndef MIPSMCINSTLOWER_H #define MIPSMCINSTLOWER_H +#include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/Support/Compiler.h" @@ -34,6 +35,8 @@ MipsMCInstLower(Mangler *mang, const MachineFunction &MF, MipsAsmPrinter &asmprinter); void Lower(const MachineInstr *MI, MCInst &OutMI) const; + void LowerCPLOAD(const MachineInstr *MI, SmallVector& MCInsts); + void LowerCPRESTORE(const MachineInstr *MI, MCInst &OutMI); private: MCOperand LowerSymbolOperand(const MachineOperand &MO, MachineOperandType MOTy, unsigned Offset) const; From hfinkel at anl.gov Tue Nov 8 16:29:50 2011 From: hfinkel at anl.gov (Hal Finkel) Date: Tue, 08 Nov 2011 16:29:50 -0600 Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass In-Reply-To: <4EB98207.2070807@grosser.es> References: <1319909412.23036.851.camel@sapling> <1319914924.23036.852.camel@sapling> <1319919418.23036.881.camel@sapling> <1319928991.23036.957.camel@sapling> <1320108633.23036.1266.camel@sapling> <1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling> <1320191694.23036.1497.camel@sapling> <1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling> <4EB98207.2070807@grosser.es> Message-ID: <1320791390.19359.262.camel@sapling> On Tue, 2011-11-08 at 20:24 +0100, Tobias Grosser wrote: > On 11/08/2011 03:36 PM, Hal Finkel wrote: > > On Tue, 2011-11-08 at 12:12 +0100, Tobias Grosser wrote: > >> On 11/08/2011 11:45 AM, Hal Finkel wrote: > >>> I've attached the latest version of my autovectorization patch. > >>> > >>> Working through the test suite has proved to be a productive > >>> experience ;) -- And almost all of the bugs that it revealed have now > >>> been fixed. There are still two programs that don't compile with > >>> vectorization turned on, and I'm working on those now, but in case > >>> anyone feels like playing with vectorization, this patch will probably > >>> work for you. > >> > >> Hey Hal, > >> > >> those are great news. Especially as the numbers seem to show that > >> vectorization has a significant performance impact. What did you compare > >> exactly. 'clang -O3' against 'clang -O3 -mllvm -vectorize'? > > > > Yes. [I've tested the current patch directly using opt -vectorize > > -unroll-allow-partial; for running the test suite I recompiled > > llvm/clang to hardcode the options as I wanted them]. > > You should not need to hack clang. As shown above, you should be able to > pass '-vectorize' to the optimizer by using '-mllvm -vectorize' in your > CFLAGS. Did you run the test suite at -O3? That's good to know. Yes, it was run at -O3. > > Also I think it would be interesting to compare for the test-suite the > performance of > 'clang -O3 -mllvm -unroll-allow-partial' with > 'clang -O3 -mllvm -unroll-allow-partial -mllvm -vectorize'. It will show > how much of the runtime overhead is due to the unrolling (produces more > code that needs to be optimized) and which part is due to vectorization. > The same counts for the speedup. How much is caused by > unrolling and how much is actually caused by your pass. Just turning on partial unrolling yields, on average, a 4.7% slowdown (0% median), and a 28.6% increase in compile time (21.8% median). > > >>> The largest three performance speedups are: > >>> SingleSource/Benchmarks/BenchmarkGame/puzzle - 59.2% speedup With just partial unrolling: 64.8% speedup > >>> SingleSource/UnitTests/Vector/multiplies - 57.7% speedup With just partial unrolling: 58.2% speedup > >>> SingleSource/Benchmarks/Misc/flops-7 - 50.75% speedup With just partial unrolling: 11.8% speedup > >>> > >>> The largest three performance slowdowns are: > >>> MultiSource/Benchmarks/MiBench/security-rijndael/security-rijndael - > >>> 114% slowdown With just partial unrolling: 0% slowdown (47.8% slowdown in compile time) > >>> MultiSource/Benchmarks/MiBench/network-patricia/network-patricia - 66.6% > >>> slowdown With just partial unrolling: 8.3% speedup > >>> SingleSource/Benchmarks/Misc/flops-8 - 64.2% slowdown With just partial unrolling: 8.3% speedup > >>> Here are the top-3 lists comparing vectorization with partial unrolling to just with partial unrolling: Top speedups: SingleSource/Benchmarks/Misc/flops-7 - 44.1% speedup SingleSource/Benchmarks/Misc/flops-1 - 42.3% speedup MultiSource/Applications/sqlite3/sqlite3 - 42.3% speedup Top slowdowns: MultiSource/Benchmarks/MiBench/security-rijndael/security-rijndael - 114% slowdown MultiSource/Benchmarks/MiBench/network-patricia/network-patricia - 81.8% slowdown SingleSource/Benchmarks/Misc/flops-8 - 79% slowdown Top compile-time slowdowns: MultiSource/Benchmarks/MiBench/security-rijndael/security-rijndael - 832% slowdown SingleSource/Benchmarks/Misc/salsa20 - 600% slowdown MultiSource/Benchmarks/Trimaran/enc-3des/enc-3des - 263% slowdown For this comparison, however (unlike comparing to plain -O3), there are a significant number of compile-time speedups (I guess that this is because vectorization can reduce the number of instructions processed by later passes). Top compile-time speedups: SingleSource/Benchmarks/Stanford/Oscar - 46% speedup SingleSource/Regression/C/bigstack - 45% speedup SingleSource/Benchmarks/BenchmarkGame/fannkuch - 45% speedup > >> Interesting. Do you understand what causes these slowdowns? Can your > >> heuristic be improved? > > > > I've not specifically looked at these cases. > > > > Generally, I've observed slowdowns from the introduction of too many > > permutations per chain (the chain selection procedure can be changed to > > help this, and I'll work on that). Also, sometimes legalization of > > non-native vector operations creates inefficient code, and I'll also > > look at these cases in more detail. > Sure. That sounds reasonable. I am confident you can improve this gradually. > > >> If I understood correctly it seems your vectorizer has quadratic > >> complexity which may cause large slowdowns. Do you think it may be > >> useful/possible to make it linear by introducing a constant upper bound > >> somewhere? E.g. limiting it to 10/20/100 steps. Maybe we are lucky and > >> most of the vectorization opportunities are close by (in some sense), > >> such that we get most of the speedup by locking at a subset of the problem. > > > > Yes, I agree. That makes a lot of sense. > > > > What would be even better is if the loop unroller would intermix > > statements from the loops where possible instead of leaving it to the > > vectorizer to do all of the grouping after the fact. That, I fear, is a > > whole other project. > > First, I do not understand the 'even better' here. To me it would be > great if on one hand the vectorizer could be constrained, such that the > compile time is predictable. And on the other hand, we could make the > loop unroller create code in a way such that the constrained vectorizer > still performs the relevant transformations. I was not clear; I meant that imposing a cut off is likely to work, but it would work even better if the loop unroller produced code more-conducive to vectorization. > > Also, what do you mean with 'if the loop unroller would intermix > statements from the loops where possible'. Are you referring to the > grouped unrolling as shown in my the last mail? Yes. Also, the code necessary to take advantage of grouped unrolling already exists in the vectorizer. Enabling the flag -bb-vectorize-fast-dep causes the vectorizer to stop searching for instruction pairings after the first use of an instruction. > > > >>> Compared to previous patches, which had a minimum required chain length > >>> of 3 or 4, I've now made the default 6. While using a chain length of 4 > >>> worked well for targeted benchmarks, it caused an overall slowdown on > >>> almost all test-suite programs. Using a minimum length of 6 causes, on > >>> average, a speedup; so I think that is a better default choice. > >> > >> I also try to understand if it is possible to use your vectorizer for > >> Polly. My idea is to do some clever loop unrolling. > >> > >> Starting from this loop. > >> > >> for (int i = 0; i< 4; i++) > >> A[i] += 1; > >> A[i] = B[i] + 3; > >> C[i] = A[i]; > >> > >> The classical unroller would create this code: > >> > >> A[0] += 1; > >> A[0] = B[i] + 3; > >> C[0] = A[i]; > >> > >> A[1] += 1; > >> A[1] = B[i] + 3; > >> C[1] = A[i]; > >> > >> A[2] += 1; > >> A[2] = B[i] + 3; > >> C[2] = A[i]; > >> > >> A[3] += 1; > >> A[3] = B[i] + 3; > >> C[3] = A[i]; > >> > >> However, in case I can prove this loop is parallel, I want to create > >> this code: > >> > >> A[0] += 1; > >> A[1] += 1; > >> A[2] += 1; > >> A[3] += 1; > >> > >> A[0] = B[i] + 3; > >> A[1] = B[i] + 3; > >> A[2] = B[i] + 3; > >> A[3] = B[i] + 3; > >> > >> C[0] = A[i]; > >> C[1] = A[i]; > >> C[2] = A[i]; > >> C[3] = A[i]; > >> > >> I assume this will allow the vectorization of test cases, that failed > >> because of possible aliasing. However, I am more interested, if the > >> execution order change could also improve the vectorization outcome or > >> reduce compile time overhead of your vectorizer. > > > > Yes, this would certainly help. > > In which way? How much? Would it be possible to restrict the vectorizer > such that it's complexity is linear, while at the same time we can > ensure it will still vectorize code that is 'group unrolled' (which > means unrolled in the way shown above? It would help because we could stop the pairing search after an instructions first use; and that is significantly faster and generates many fewer potential pairings that need to be considered by the later stages. Exactly "how much" it would help I can't yet answer; I'd need to construct actual benchmarks for that. If you have some group-unrolled code, then it will be simple to test: just pass -bb-vectorize-fast-dep. > > > By the way, the current implementation, by default, it will create > > unaligned vector loads and stores, but these are generally broken up by > > the legalizer. This behavior can be suppressed using the > > -bb-vectorize-aligned-only flag. It would be nice if the loop unroller > > chose the unrolling factor to preserve the maximum available alignment, > > but I don't think that it currently does so. > I don't know, but it sounds like a good thing to do. > > > One problem with the current implementation is that it relies on > > GetPointerBaseWithConstantOffset to determine if two loads or stores > > share the same base address. This fails with partially-unrolled loops > > because it cannot "undo" all of the additions to the offset induction > > variable in order to understand that some of the loads and stores are > > really adjacent in memory. This is something that I think can be > > improved within the vectorizer itself, and I'm planning on doing some > > work on this in the future. > Here you may also want to look into ScalarEvolution. Basically two loads > access adjacent memory if the difference of the scalar evolution of the > two load addresses is equal to sizeof(element_type). ScalarEvolution > should be a lot more general than GetPointerBaseWithConstantOffset(). Thanks! That sounds great; I'll have to look at that. -Hal > > Cheers > Tobi -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory From clattner at apple.com Tue Nov 8 16:32:03 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 08 Nov 2011 14:32:03 -0800 Subject: [llvm-commits] [llvm] r144123 - in /llvm/trunk: lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/ldrd.ll In-Reply-To: <2FB2AEE3-7586-44D4-9FFC-B0751FBDAA6C@apple.com> References: <20111108212110.3F2AF2A6C12C@llvm.org> <2FB2AEE3-7586-44D4-9FFC-B0751FBDAA6C@apple.com> Message-ID: On Nov 8, 2011, at 2:15 PM, Evan Cheng wrote: >>> unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false); >>> unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false); >>> - if ((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum) >>> + // ARM errata 602117: LDRD with base in list may result in incorrect base >>> + // register when interrupted or faulted. >>> + bool Errata602117 = EvenReg == BaseReg && STI->getCPUString() == "cortex-m3"; >> >> Err, checking getCPUString() seems like a hack; shouldn't this be a >> subtarget feature? > > That would make sense if this particular cpu has more than one subtarget features. As it is, I don't see the point. We're using a lot of subtarget bits already. Please at least make it be a STI->isFoo() method. -Chris From stoklund at 2pi.dk Tue Nov 8 17:26:00 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 08 Nov 2011 23:26:00 -0000 Subject: [llvm-commits] [llvm] r144147 - /llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Message-ID: <20111108232600.BCD0E2A6C12C@llvm.org> Author: stoklund Date: Tue Nov 8 17:26:00 2011 New Revision: 144147 URL: http://llvm.org/viewvc/llvm-project?rev=144147&view=rev Log: Track reference count independently from clear(). This allows clear() to be called on a DomainValue with references. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144147&r1=144146&r2=144147&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Tue Nov 8 17:26:00 2011 @@ -92,10 +92,10 @@ return CountTrailingZeros_32(AvailableDomains); } - DomainValue() { clear(); } + DomainValue() : Refs(0) { clear(); } void clear() { - Refs = AvailableDomains = Dist = 0; + AvailableDomains = Dist = 0; Instrs.clear(); } }; @@ -173,6 +173,7 @@ dv->Dist = Distance; if (domain >= 0) dv->addDomain(domain); + assert(dv->Refs == 0 && "Reference count wasn't cleared"); return dv; } @@ -271,8 +272,7 @@ A->Instrs.append(B->Instrs.begin(), B->Instrs.end()); // Clear the old DomainValue so we won't try to swizzle instructions twice. - B->Instrs.clear(); - B->AvailableDomains = 0; + B->clear(); for (unsigned rx = 0; rx != NumRegs; ++rx) if (LiveRegs[rx] == B) From bigcheesegs at gmail.com Tue Nov 8 17:34:07 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 08 Nov 2011 23:34:07 -0000 Subject: [llvm-commits] [llvm] r144148 - /llvm/trunk/lib/Object/COFFObjectFile.cpp Message-ID: <20111108233407.8C49A2A6C12C@llvm.org> Author: mspencer Date: Tue Nov 8 17:34:07 2011 New Revision: 144148 URL: http://llvm.org/viewvc/llvm-project?rev=144148&view=rev Log: Object/COFF: Fix PE reading. Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=144148&r1=144147&r2=144148&view=diff ============================================================================== --- llvm/trunk/lib/Object/COFFObjectFile.cpp (original) +++ llvm/trunk/lib/Object/COFFObjectFile.cpp Tue Nov 8 17:34:07 2011 @@ -345,7 +345,7 @@ // data, as there's nothing that says that is not allowed. uintptr_t con_start = uintptr_t(base()) + sec->PointerToRawData; uintptr_t con_end = con_start + sec->SizeOfRawData; - if (con_end >= uintptr_t(Data->getBufferEnd())) + if (con_end > uintptr_t(Data->getBufferEnd())) return object_error::parse_failed; Result = StringRef(reinterpret_cast(con_start), sec->SizeOfRawData); @@ -424,7 +424,12 @@ } COFFObjectFile::COFFObjectFile(MemoryBuffer *Object, error_code &ec) - : ObjectFile(Binary::isCOFF, Object, ec) { + : ObjectFile(Binary::isCOFF, Object, ec) + , Header(0) + , SectionTable(0) + , SymbolTable(0) + , StringTable(0) + , StringTableSize(0) { // Check that we at least have enough room for a header. if (!checkSize(Data, ec, sizeof(coff_file_header))) return; @@ -437,7 +442,7 @@ // PE/COFF, seek through MS-DOS compatibility stub and 4-byte // PE signature to find 'normal' COFF header. if (!checkSize(Data, ec, 0x3c + 8)) return; - HeaderStart += *reinterpret_cast(base() + 0x3c); + HeaderStart = *reinterpret_cast(base() + 0x3c); // Check the PE header. ("PE\0\0") if (std::memcmp(base() + HeaderStart, "PE\0\0", 4) != 0) { ec = object_error::parse_failed; @@ -459,28 +464,30 @@ Header->NumberOfSections * sizeof(coff_section))) return; - SymbolTable = - reinterpret_cast(base() - + Header->PointerToSymbolTable); - if (!checkAddr(Data, ec, uintptr_t(SymbolTable), - Header->NumberOfSymbols * sizeof(coff_symbol))) - return; + if (Header->PointerToSymbolTable != 0) { + SymbolTable = + reinterpret_cast(base() + + Header->PointerToSymbolTable); + if (!checkAddr(Data, ec, uintptr_t(SymbolTable), + Header->NumberOfSymbols * sizeof(coff_symbol))) + return; - // Find string table. - StringTable = reinterpret_cast(base()) - + Header->PointerToSymbolTable - + Header->NumberOfSymbols * sizeof(coff_symbol); - if (!checkAddr(Data, ec, uintptr_t(StringTable), sizeof(ulittle32_t))) - return; + // Find string table. + StringTable = reinterpret_cast(base()) + + Header->PointerToSymbolTable + + Header->NumberOfSymbols * sizeof(coff_symbol); + if (!checkAddr(Data, ec, uintptr_t(StringTable), sizeof(ulittle32_t))) + return; - StringTableSize = *reinterpret_cast(StringTable); - if (!checkAddr(Data, ec, uintptr_t(StringTable), StringTableSize)) - return; - // Check that the string table is null terminated if has any in it. - if (StringTableSize < 4 - || (StringTableSize > 4 && StringTable[StringTableSize - 1] != 0)) { - ec = object_error::parse_failed; - return; + StringTableSize = *reinterpret_cast(StringTable); + if (!checkAddr(Data, ec, uintptr_t(StringTable), StringTableSize)) + return; + // Check that the string table is null terminated if has any in it. + if (StringTableSize < 4 + || (StringTableSize > 4 && StringTable[StringTableSize - 1] != 0)) { + ec = object_error::parse_failed; + return; + } } ec = object_error::success; From stoklund at 2pi.dk Tue Nov 8 18:06:18 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 09 Nov 2011 00:06:18 -0000 Subject: [llvm-commits] [llvm] r144149 - /llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Message-ID: <20111109000618.D52812A6C12C@llvm.org> Author: stoklund Date: Tue Nov 8 18:06:18 2011 New Revision: 144149 URL: http://llvm.org/viewvc/llvm-project?rev=144149&view=rev Log: Link to the live DomainValue after merging. When merging two uncollapsed DomainValues, place a link to the active DomainValue from the passive DomainValue. This allows old stale references to the passive DomainValue to be updated to point to the active DomainValue. The new resolve() function finds the active DomainValue and updates the pointer. This change makes old live-out lists more useful since they may contain uncollapsed DomainValues that have since been merged into other DomainValues. Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144149&r1=144148&r2=144149&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Tue Nov 8 18:06:18 2011 @@ -60,6 +60,11 @@ // Position of the last defining instruction. unsigned Dist; + // Pointer to the next DomainValue in a chain. When two DomainValues are + // merged, Victim.Next is set to point to Victor, so old DomainValue + // references can be updated by folowing the chain. + DomainValue *Next; + // Twiddleable instructions using or defining these registers. SmallVector Instrs; @@ -94,8 +99,10 @@ DomainValue() : Refs(0) { clear(); } + // Clear this DomainValue and point to next which has all its data. void clear() { AvailableDomains = Dist = 0; + Next = 0; Instrs.clear(); } }; @@ -139,7 +146,12 @@ // DomainValue allocation. DomainValue *alloc(int domain = -1); + DomainValue *retain(DomainValue *DV) { + if (DV) ++DV->Refs; + return DV; + } void release(DomainValue*); + DomainValue *resolve(DomainValue*&); // LiveRegs manipulations. void setLiveReg(int rx, DomainValue *DV); @@ -174,22 +186,46 @@ if (domain >= 0) dv->addDomain(domain); assert(dv->Refs == 0 && "Reference count wasn't cleared"); + assert(!dv->Next && "Chained DomainValue shouldn't have been recycled"); return dv; } /// release - Release a reference to DV. When the last reference is released, /// collapse if needed. void ExeDepsFix::release(DomainValue *DV) { - assert(DV && DV->Refs && "Bad DomainValue"); - if (--DV->Refs) - return; - - // There are no more DV references. Collapse any contained instructions. - if (DV->AvailableDomains && !DV->isCollapsed()) - collapse(DV, DV->getFirstDomain()); + while (DV) { + assert(DV->Refs && "Bad DomainValue"); + if (--DV->Refs) + return; + + // There are no more DV references. Collapse any contained instructions. + if (DV->AvailableDomains && !DV->isCollapsed()) + collapse(DV, DV->getFirstDomain()); + + DomainValue *Next = DV->Next; + DV->clear(); + Avail.push_back(DV); + // Also release the next DomainValue in the chain. + DV = Next; + } +} - DV->clear(); - Avail.push_back(DV); +/// resolve - Follow the chain of dead DomainValues until a live DomainValue is +/// reached. Update the referenced pointer when necessary. +DomainValue *ExeDepsFix::resolve(DomainValue *&DVRef) { + DomainValue *DV = DVRef; + if (!DV || !DV->Next) + return DV; + + // DV has a chain. Find the end. + do DV = DV->Next; + while (DV->Next); + + // Update DVRef to point to DV. + retain(DV); + release(DVRef); + DVRef = DV; + return DV; } /// Set LiveRegs[rx] = dv, updating reference counts. @@ -204,8 +240,7 @@ return; if (LiveRegs[rx]) release(LiveRegs[rx]); - LiveRegs[rx] = dv; - if (dv) ++dv->Refs; + LiveRegs[rx] = retain(dv); } // Kill register rx, recycle or collapse any DomainValue. @@ -273,6 +308,8 @@ // Clear the old DomainValue so we won't try to swizzle instructions twice. B->clear(); + // All uses of B are referred to A. + B->Next = retain(A); for (unsigned rx = 0; rx != NumRegs; ++rx) if (LiveRegs[rx] == B) @@ -290,8 +327,8 @@ pe = MBB->pred_end(); pi != pe; ++pi) { LiveOutMap::const_iterator fi = LiveOuts.find(*pi); if (fi == LiveOuts.end()) continue; - DomainValue *pdv = fi->second[rx]; - if (!pdv || !pdv->AvailableDomains) continue; + DomainValue *pdv = resolve(fi->second[rx]); + if (!pdv) continue; if (!LiveRegs || !LiveRegs[rx]) { setLiveReg(rx, pdv); continue; From stoklund at 2pi.dk Tue Nov 8 19:06:56 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 09 Nov 2011 01:06:56 -0000 Subject: [llvm-commits] [llvm] r144151 - in /llvm/trunk: lib/CodeGen/ExecutionDepsFix.cpp test/CodeGen/X86/sse-domains.ll Message-ID: <20111109010656.BE19A2A6C12C@llvm.org> Author: stoklund Date: Tue Nov 8 19:06:56 2011 New Revision: 144151 URL: http://llvm.org/viewvc/llvm-project?rev=144151&view=rev Log: Collapse DomainValues across loop back-edges. During the initial RPO traversal of the basic blocks, remember the ones that are incomplete because of back-edges from predecessors that haven't been visited yet. After the initial RPO, revisit all those loop headers so the incoming DomainValues on the back-edges can be properly collapsed. This will properly fix execution domains on software pipelined code, like the included test case. Added: llvm/trunk/test/CodeGen/X86/sse-domains.ll Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144151&r1=144150&r2=144151&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original) +++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Tue Nov 8 19:06:56 2011 @@ -160,7 +160,7 @@ void collapse(DomainValue *dv, unsigned domain); bool merge(DomainValue *A, DomainValue *B); - void enterBasicBlock(MachineBasicBlock*); + bool enterBasicBlock(MachineBasicBlock*); void leaveBasicBlock(MachineBasicBlock*); void visitInstr(MachineInstr*); void visitGenericInstr(MachineInstr*); @@ -317,7 +317,13 @@ return true; } -void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) { +// enterBasicBlock - Set up LiveRegs by merging predecessor live-out values. +// Return true if some predecessor hasn't been processed yet (like on a loop +// back-edge). +bool ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) { + // Detect back-edges from predecessors we haven't processed yet. + bool seenBackEdge = false; + // Try to coalesce live-out registers from predecessors. for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(), e = MBB->livein_end(); i != e; ++i) { @@ -326,7 +332,12 @@ for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(), pe = MBB->pred_end(); pi != pe; ++pi) { LiveOutMap::const_iterator fi = LiveOuts.find(*pi); - if (fi == LiveOuts.end()) continue; + if (fi == LiveOuts.end()) { + seenBackEdge = true; + continue; + } + if (!fi->second) + continue; DomainValue *pdv = resolve(fi->second[rx]); if (!pdv) continue; if (!LiveRegs || !LiveRegs[rx]) { @@ -350,12 +361,19 @@ force(rx, pdv->getFirstDomain()); } } + return seenBackEdge; } void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) { // Save live registers at end of MBB - used by enterBasicBlock(). - if (LiveRegs) - LiveOuts.insert(std::make_pair(MBB, LiveRegs)); + // Also use LiveOuts as a visited set to detect back-edges. + if (!LiveOuts.insert(std::make_pair(MBB, LiveRegs)).second && LiveRegs) { + // Insertion failed, this must be the second pass. + // Release all the DomainValues instead of keeping them. + for (unsigned i = 0, e = NumRegs; i != e; ++i) + release(LiveRegs[i]); + delete[] LiveRegs; + } LiveRegs = 0; } @@ -545,23 +563,32 @@ MachineBasicBlock *Entry = MF->begin(); ReversePostOrderTraversal RPOT(Entry); + SmallVector Loops; for (ReversePostOrderTraversal::rpo_iterator MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) { MachineBasicBlock *MBB = *MBBI; - enterBasicBlock(MBB); + if (enterBasicBlock(MBB)) + Loops.push_back(MBB); for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) visitInstr(I); leaveBasicBlock(MBB); } + // Visit all the loop blocks again in order to merge DomainValues from + // back-edges. + for (unsigned i = 0, e = Loops.size(); i != e; ++i) { + MachineBasicBlock *MBB = Loops[i]; + enterBasicBlock(MBB); + leaveBasicBlock(MBB); + } + // Clear the LiveOuts vectors and collapse any remaining DomainValues. for (ReversePostOrderTraversal::rpo_iterator MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) { LiveOutMap::const_iterator FI = LiveOuts.find(*MBBI); - if (FI == LiveOuts.end()) + if (FI == LiveOuts.end() || !FI->second) continue; - assert(FI->second && "Null entry"); for (unsigned i = 0, e = NumRegs; i != e; ++i) if (FI->second[i]) release(FI->second[i]); Added: llvm/trunk/test/CodeGen/X86/sse-domains.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-domains.ll?rev=144151&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse-domains.ll (added) +++ llvm/trunk/test/CodeGen/X86/sse-domains.ll Tue Nov 8 19:06:56 2011 @@ -0,0 +1,45 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7" + +; CHECK: f +; +; This function contains load / store / and operations that all can execute in +; any domain. The only domain-specific operation is the %add = shl... operation +; which is <4 x i32>. +; +; The paddd instruction can only influence the other operations through the loop +; back-edge. Check that everything is still moved into the integer domain. + +define void @f(<4 x i32>* nocapture %p, i32 %n) nounwind uwtable ssp { +entry: + br label %while.body + +; Materialize a zeroinitializer and a constant-pool load in the integer domain. +; The order is not important. +; CHECK: pxor +; CHECK: movdqa + +; The instructions in the loop must all be integer domain as well. +; CHECK: while.body +; CHECK: pand +; CHECK: movdqa +; CHECK: movdqa +; Finally, the controlling integer-only instruction. +; CHECK: paddd +while.body: + %p.addr.04 = phi <4 x i32>* [ %incdec.ptr, %while.body ], [ %p, %entry ] + %n.addr.03 = phi i32 [ %dec, %while.body ], [ %n, %entry ] + %x.02 = phi <4 x i32> [ %add, %while.body ], [ zeroinitializer, %entry ] + %dec = add nsw i32 %n.addr.03, -1 + %and = and <4 x i32> %x.02, + %incdec.ptr = getelementptr inbounds <4 x i32>* %p.addr.04, i64 1 + store <4 x i32> %and, <4 x i32>* %p.addr.04, align 16 + %0 = load <4 x i32>* %incdec.ptr, align 16 + %add = shl <4 x i32> %0, + %tobool = icmp eq i32 %dec, 0 + br i1 %tobool, label %while.end, label %while.body + +while.end: + ret void +} From eli.friedman at gmail.com Tue Nov 8 19:26:41 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 8 Nov 2011 17:26:41 -0800 Subject: [llvm-commits] [llvm] r144034 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/2011-11-07-LegalizeBuildVector.ll In-Reply-To: <64700A7C-488A-43B3-AC47-1102DA3752AC@apple.com> References: <20111107225110.47D172A6C12C@llvm.org> <64700A7C-488A-43B3-AC47-1102DA3752AC@apple.com> Message-ID: On Tue, Nov 8, 2011 at 10:17 AM, Chris Lattner wrote: > > On Nov 7, 2011, at 2:51 PM, Eli Friedman wrote: > >> Author: efriedma >> Date: Mon Nov ?7 16:51:10 2011 >> New Revision: 144034 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=144034&view=rev >> Log: >> Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization doesn't get confused by CSE later on. ?Fixes PR11318. > > Should there be a new SelectionDAG method that does both RAUW + RemoveDeadNode's? ?Should RAUW itself do this? It looks like all the users of RAUW subsequently delete the node in question. I just noticed, though, that apparently we don't generally guarantee that a node will have no uses after a RAUW. So some additional changes might be necessary here anyway. -Eli From evan.cheng at apple.com Tue Nov 8 19:57:04 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 09 Nov 2011 01:57:04 -0000 Subject: [llvm-commits] [llvm] r144154 - in /llvm/trunk/lib/Target/ARM: ARMLoadStoreOptimizer.cpp ARMSubtarget.h Message-ID: <20111109015704.3F6D22A6C12C@llvm.org> Author: evancheng Date: Tue Nov 8 19:57:03 2011 New Revision: 144154 URL: http://llvm.org/viewvc/llvm-project?rev=144154&view=rev Log: Hide cpu name checking in ARMSubtarget. Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=144154&r1=144153&r2=144154&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Nov 8 19:57:03 2011 @@ -1080,7 +1080,7 @@ unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false); // ARM errata 602117: LDRD with base in list may result in incorrect base // register when interrupted or faulted. - bool Errata602117 = EvenReg == BaseReg && STI->getCPUString() == "cortex-m3"; + bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3(); if (!Errata602117 && ((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum)) return false; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=144154&r1=144153&r2=144154&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Nov 8 19:57:03 2011 @@ -191,6 +191,7 @@ bool isCortexA8() const { return ARMProcFamily == CortexA8; } bool isCortexA9() const { return ARMProcFamily == CortexA9; } + bool isCortexM3() const { return CPUString == "cortex-m3"; } bool hasARMOps() const { return !NoARM; } From mcrosier at apple.com Tue Nov 8 21:22:02 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 09 Nov 2011 03:22:02 -0000 Subject: [llvm-commits] [llvm] r144163 - in /llvm/trunk: lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel-cmp-imm.ll Message-ID: <20111109032202.E6F4A2A6C12C@llvm.org> Author: mcrosier Date: Tue Nov 8 21:22:02 2011 New Revision: 144163 URL: http://llvm.org/viewvc/llvm-project?rev=144163&view=rev Log: Add support for encoding immediates in icmp and fcmp. Hopefully, this will remove a fair number of unnecessary materialized constants. rdar://10412592 Added: llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144163&r1=144162&r2=144163&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Nov 8 21:22:02 2011 @@ -1206,16 +1206,42 @@ if (isFloat && !Subtarget->hasVFP2()) return false; + // Check to see if the 2nd operand is a constant that we can encode directly + // in the compare. + uint64_t Imm; + int EncodedImm = 0; + bool EncodeImm = false; + bool isNegativeImm = false; + if (const ConstantInt *ConstInt = dyn_cast(Src2Value)) { + if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || + SrcVT == MVT::i1) { + const APInt &CIVal = ConstInt->getValue(); + + isNegativeImm = CIVal.isNegative(); + Imm = (isNegativeImm) ? (-CIVal).getZExtValue() : CIVal.getZExtValue(); + EncodedImm = (int)Imm; + EncodeImm = isThumb2 ? (ARM_AM::getT2SOImmVal(EncodedImm) != -1) : + (ARM_AM::getSOImmVal(EncodedImm) != -1); + } + } else if (const ConstantFP *ConstFP = dyn_cast(Src2Value)) { + if (SrcVT == MVT::f32 || SrcVT == MVT::f64) + if (ConstFP->isZero() && !ConstFP->isNegative()) + EncodeImm = true; + } + unsigned CmpOpc; + bool isICmp = true; bool needsExt = false; switch (SrcVT.getSimpleVT().SimpleTy) { default: return false; // TODO: Verify compares. case MVT::f32: - CmpOpc = ARM::VCMPES; + isICmp = false; + CmpOpc = EncodeImm ? ARM::VCMPEZS : ARM::VCMPES; break; case MVT::f64: - CmpOpc = ARM::VCMPED; + isICmp = false; + CmpOpc = EncodeImm ? ARM::VCMPEZD : ARM::VCMPED; break; case MVT::i1: case MVT::i8: @@ -1223,30 +1249,56 @@ needsExt = true; // Intentional fall-through. case MVT::i32: - CmpOpc = isThumb2 ? ARM::t2CMPrr : ARM::CMPrr; + if (isThumb2) { + if (!EncodeImm) + CmpOpc = ARM::t2CMPrr; + else + CmpOpc = isNegativeImm ? ARM::t2CMNzri : ARM::t2CMPri; + } else { + if (!EncodeImm) + CmpOpc = ARM::CMPrr; + else + CmpOpc = isNegativeImm ? ARM::CMNzri : ARM::CMPri; + } break; } unsigned SrcReg1 = getRegForValue(Src1Value); if (SrcReg1 == 0) return false; - unsigned SrcReg2 = getRegForValue(Src2Value); - if (SrcReg2 == 0) return false; + unsigned SrcReg2; + if (!EncodeImm) { + SrcReg2 = getRegForValue(Src2Value); + if (SrcReg2 == 0) return false; + } // We have i1, i8, or i16, we need to either zero extend or sign extend. if (needsExt) { unsigned ResultReg; - EVT DestVT = MVT::i32; - ResultReg = ARMEmitIntExt(SrcVT, SrcReg1, DestVT, isZExt); + ResultReg = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); if (ResultReg == 0) return false; SrcReg1 = ResultReg; - ResultReg = ARMEmitIntExt(SrcVT, SrcReg2, DestVT, isZExt); - if (ResultReg == 0) return false; - SrcReg2 = ResultReg; + if (!EncodeImm) { + ResultReg = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); + if (ResultReg == 0) return false; + SrcReg2 = ResultReg; + } } - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) - .addReg(SrcReg1).addReg(SrcReg2)); + if (!EncodeImm) { + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(CmpOpc)) + .addReg(SrcReg1).addReg(SrcReg2)); + } else { + MachineInstrBuilder MIB; + MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) + .addReg(SrcReg1); + + // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0. + if (isICmp) + MIB.addImm(EncodedImm); + AddOptionalDefs(MIB); + } // For floating point we need to move the result to a comparison register // that we can then use for branches. Added: llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll?rev=144163&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll (added) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll Tue Nov 8 21:22:02 2011 @@ -0,0 +1,214 @@ +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB + +define void @t1a(float %a) uwtable ssp { +entry: +; ARM: t1a +; THUMB: t1a + %cmp = fcmp oeq float %a, 0.000000e+00 +; ARM: vcmpe.f32 s0, #0 +; THUMB: vcmpe.f32 s0, #0 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +declare void @foo() + +; Shouldn't be able to encode -0.0 imm. +define void @t1b(float %a) uwtable ssp { +entry: +; ARM: t1b +; THUMB: t1b + %cmp = fcmp oeq float %a, -0.000000e+00 +; ARM: vldr.32 +; ARM: vcmpe.f32 s0, s1 +; THUMB: vldr.32 +; THUMB: vcmpe.f32 s0, s1 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t2a(double %a) uwtable ssp { +entry: +; ARM: t2a +; THUMB: t2a + %cmp = fcmp oeq double %a, 0.000000e+00 +; ARM: vcmpe.f64 d16, #0 +; THUMB: vcmpe.f64 d16, #0 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +; Shouldn't be able to encode -0.0 imm. +define void @t2b(double %a) uwtable ssp { +entry: +; ARM: t2b +; THUMB: t2b + %cmp = fcmp oeq double %a, -0.000000e+00 +; ARM: vldr.64 +; ARM: vcmpe.f64 d16, d17 +; THUMB: vldr.64 +; THUMB: vcmpe.f64 d16, d17 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t4(i8 signext %a) uwtable ssp { +entry: +; ARM: t4 +; THUMB: t4 + %cmp = icmp eq i8 %a, -1 +; ARM: cmn r0, #1 +; THUMB: cmn.w r0, #1 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t5(i8 zeroext %a) uwtable ssp { +entry: +; ARM: t5 +; THUMB: t5 + %cmp = icmp eq i8 %a, 1 +; ARM: cmp r0, #1 +; THUMB: cmp r0, #1 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t6(i16 signext %a) uwtable ssp { +entry: +; ARM: t6 +; THUMB: t6 + %cmp = icmp eq i16 %a, -1 +; ARM: cmn r0, #1 +; THUMB: cmn.w r0, #1 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t7(i16 zeroext %a) uwtable ssp { +entry: +; ARM: t7 +; THUMB: t7 + %cmp = icmp eq i16 %a, 1 +; ARM: cmp r0, #1 +; THUMB: cmp r0, #1 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t8(i32 %a) uwtable ssp { +entry: +; ARM: t8 +; THUMB: t8 + %cmp = icmp eq i32 %a, -1 +; ARM: cmn r0, #1 +; THUMB: cmn.w r0, #1 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t9(i32 %a) uwtable ssp { +entry: +; ARM: t9 +; THUMB: t9 + %cmp = icmp eq i32 %a, 1 +; ARM: cmp r0, #1 +; THUMB: cmp r0, #1 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t10(i32 %a) uwtable ssp { +entry: +; ARM: t10 +; THUMB: t10 + %cmp = icmp eq i32 %a, 384 +; ARM: cmp r0, #384 +; THUMB: cmp.w r0, #384 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t11(i32 %a) uwtable ssp { +entry: +; ARM: t11 +; THUMB: t11 + %cmp = icmp eq i32 %a, 4096 +; ARM: cmp r0, #4096 +; THUMB: cmp.w r0, #4096 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} From rjmccall at apple.com Tue Nov 8 21:26:50 2011 From: rjmccall at apple.com (John McCall) Date: Wed, 09 Nov 2011 03:26:50 -0000 Subject: [llvm-commits] [llvm] r144164 - /llvm/trunk/tools/llvm-diff/DiffConsumer.cpp Message-ID: <20111109032650.AA2CA2A6C12C@llvm.org> Author: rjmccall Date: Tue Nov 8 21:26:50 2011 New Revision: 144164 URL: http://llvm.org/viewvc/llvm-project?rev=144164&view=rev Log: Use isa<> instead of dyn_cast<> as suggested by Nick. Should've read the patch a bit closer, sorry. Modified: llvm/trunk/tools/llvm-diff/DiffConsumer.cpp Modified: llvm/trunk/tools/llvm-diff/DiffConsumer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-diff/DiffConsumer.cpp?rev=144164&r1=144163&r2=144164&view=diff ============================================================================== --- llvm/trunk/tools/llvm-diff/DiffConsumer.cpp (original) +++ llvm/trunk/tools/llvm-diff/DiffConsumer.cpp Tue Nov 8 21:26:50 2011 @@ -64,7 +64,7 @@ } return; } - if (dyn_cast(V)) { + if (isa(V)) { out << *V; return; } From eli.friedman at gmail.com Tue Nov 8 22:16:01 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 09 Nov 2011 04:16:01 -0000 Subject: [llvm-commits] [llvm] r144166 - /llvm/trunk/include/llvm/Analysis/LoopInfo.h Message-ID: <20111109041601.418022A6C12C@llvm.org> Author: efriedma Date: Tue Nov 8 22:16:01 2011 New Revision: 144166 URL: http://llvm.org/viewvc/llvm-project?rev=144166&view=rev Log: Enhance verifyLoop so that it can reliably verify that every block in a loop is reachable from the loop header. Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=144166&r1=144165&r2=144166&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Tue Nov 8 22:16:01 2011 @@ -416,14 +416,26 @@ #ifndef NDEBUG assert(!Blocks.empty() && "Loop header is missing"); + // Setup for using a depth-first iterator to visit every block in the loop. + SmallVector ExitBBs; + getExitBlocks(ExitBBs); + llvm::SmallPtrSet VisitSet; + VisitSet.insert(ExitBBs.begin(), ExitBBs.end()); + df_ext_iterator > + BI = df_ext_begin(getHeader(), VisitSet), + BE = df_ext_end(getHeader(), VisitSet); + + // Keep track of the number of BBs visited. + unsigned NumVisited = 0; + // Sort the blocks vector so that we can use binary search to do quick // lookups. SmallVector LoopBBs(block_begin(), block_end()); std::sort(LoopBBs.begin(), LoopBBs.end()); // Check the individual blocks. - for (block_iterator I = block_begin(), E = block_end(); I != E; ++I) { - BlockT *BB = *I; + for ( ; BI != BE; ++BI) { + BlockT *BB = *BI; bool HasInsideLoopSuccs = false; bool HasInsideLoopPreds = false; SmallVector OutsideLoopPreds; @@ -440,7 +452,7 @@ for (typename InvBlockTraits::ChildIteratorType PI = InvBlockTraits::child_begin(BB), PE = InvBlockTraits::child_end(BB); PI != PE; ++PI) { - typename InvBlockTraits::NodeType *N = *PI; + BlockT *N = *PI; if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), N)) HasInsideLoopPreds = true; else @@ -464,8 +476,12 @@ assert(HasInsideLoopSuccs && "Loop block has no in-loop successors!"); assert(BB != getHeader()->getParent()->begin() && "Loop contains function entry block!"); + + NumVisited++; } + assert(NumVisited == getNumBlocks() && "Unreachable block in loop"); + // Check the subloops. for (iterator I = begin(), E = end(); I != E; ++I) // Each block in each subloop should be contained within this loop. From echristo at apple.com Tue Nov 8 23:24:07 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 09 Nov 2011 05:24:07 -0000 Subject: [llvm-commits] [llvm] r144169 - in /llvm/trunk: include/llvm/MC/MCObjectFileInfo.h lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp lib/CodeGen/AsmPrinter/DwarfCompileUnit.h lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/AsmPrinter/DwarfDebug.h lib/MC/MCObjectFileInfo.cpp Message-ID: <20111109052407.E9A1F2A6C12C@llvm.org> Author: echristo Date: Tue Nov 8 23:24:07 2011 New Revision: 144169 URL: http://llvm.org/viewvc/llvm-project?rev=144169&view=rev Log: Remove the pubnames section, no one consumes it. Modified: llvm/trunk/include/llvm/MC/MCObjectFileInfo.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h llvm/trunk/lib/MC/MCObjectFileInfo.cpp Modified: llvm/trunk/include/llvm/MC/MCObjectFileInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectFileInfo.h?rev=144169&r1=144168&r2=144169&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCObjectFileInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCObjectFileInfo.h Tue Nov 8 23:24:07 2011 @@ -96,7 +96,6 @@ const MCSection *DwarfInfoSection; const MCSection *DwarfLineSection; const MCSection *DwarfFrameSection; - const MCSection *DwarfPubNamesSection; const MCSection *DwarfPubTypesSection; const MCSection *DwarfDebugInlineSection; const MCSection *DwarfStrSection; @@ -211,7 +210,6 @@ const MCSection *getDwarfInfoSection() const { return DwarfInfoSection; } const MCSection *getDwarfLineSection() const { return DwarfLineSection; } const MCSection *getDwarfFrameSection() const { return DwarfFrameSection; } - const MCSection *getDwarfPubNamesSection() const{return DwarfPubNamesSection;} const MCSection *getDwarfPubTypesSection() const{return DwarfPubTypesSection;} const MCSection *getDwarfDebugInlineSection() const { return DwarfDebugInlineSection; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=144169&r1=144168&r2=144169&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Tue Nov 8 23:24:07 2011 @@ -1076,11 +1076,9 @@ addType(VariableDIE, GTy); // Add scoping info. - if (!GV.isLocalToUnit()) { + if (!GV.isLocalToUnit()) addUInt(VariableDIE, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1); - // Expose as global. - addGlobal(GV.getName(), VariableDIE); - } + // Add line number info. addSourceLine(VariableDIE, GV); // Add to context owner. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=144169&r1=144168&r2=144169&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Tue Nov 8 23:24:07 2011 @@ -56,10 +56,6 @@ /// descriptors to debug information entries using a DIEEntry proxy. DenseMap MDNodeToDIEEntryMap; - /// Globals - A map of globally visible named entities for this unit. - /// - StringMap Globals; - /// GlobalTypes - A map of globally visible types for this unit. /// StringMap GlobalTypes; @@ -86,7 +82,6 @@ // Accessors. unsigned getID() const { return ID; } DIE* getCUDie() const { return CUDie.get(); } - const StringMap &getGlobals() const { return Globals; } const StringMap &getGlobalTypes() const { return GlobalTypes; } const StringMap &getAccelNames() const { return AccelNames; } @@ -100,10 +95,6 @@ /// bool hasContent() const { return !CUDie->getChildren().empty(); } - /// addGlobal - Add a new global entity to the compile unit. - /// - void addGlobal(StringRef Name, DIE *Die) { Globals[Name] = Die; } - /// addGlobalType - Add a new global type to the compile unit. /// void addGlobalType(DIType Ty); Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=144169&r1=144168&r2=144169&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Nov 8 23:24:07 2011 @@ -597,9 +597,6 @@ // Add to context owner. TheCU->addToContextOwner(SubprogramDie, SP.getContext()); - // Expose as global. - TheCU->addGlobal(SP.getName(), SubprogramDie); - // Add to Accel Names TheCU->addAccelName(SP.getName(), SubprogramDie); @@ -823,9 +820,6 @@ emitAccelTypes(); } - // Emit info into a debug pubnames section. - emitDebugPubNames(); - // Emit info into a debug pubtypes section. emitDebugPubTypes(); @@ -1567,7 +1561,6 @@ EmitSectionSym(Asm, TLOF.getDwarfLineSection(), "section_line"); EmitSectionSym(Asm, TLOF.getDwarfLocSection()); - EmitSectionSym(Asm, TLOF.getDwarfPubNamesSection()); EmitSectionSym(Asm, TLOF.getDwarfPubTypesSection()); DwarfStrSectionSym = EmitSectionSym(Asm, TLOF.getDwarfStrSection(), "section_str"); @@ -1871,57 +1864,6 @@ AT.Emit(Asm, SectionBegin, this); } -/// emitDebugPubNames - Emit visible names into a debug pubnames section. -/// -void DwarfDebug::emitDebugPubNames() { - for (DenseMap::iterator I = CUMap.begin(), - E = CUMap.end(); I != E; ++I) { - CompileUnit *TheCU = I->second; - // Start the dwarf pubnames section. - Asm->OutStreamer.SwitchSection( - Asm->getObjFileLowering().getDwarfPubNamesSection()); - - Asm->OutStreamer.AddComment("Length of Public Names Info"); - Asm->EmitLabelDifference( - Asm->GetTempSymbol("pubnames_end", TheCU->getID()), - Asm->GetTempSymbol("pubnames_begin", TheCU->getID()), 4); - - Asm->OutStreamer.EmitLabel(Asm->GetTempSymbol("pubnames_begin", - TheCU->getID())); - - Asm->OutStreamer.AddComment("DWARF Version"); - Asm->EmitInt16(dwarf::DWARF_VERSION); - - Asm->OutStreamer.AddComment("Offset of Compilation Unit Info"); - Asm->EmitSectionOffset(Asm->GetTempSymbol("info_begin", TheCU->getID()), - DwarfInfoSectionSym); - - Asm->OutStreamer.AddComment("Compilation Unit Length"); - Asm->EmitLabelDifference(Asm->GetTempSymbol("info_end", TheCU->getID()), - Asm->GetTempSymbol("info_begin", TheCU->getID()), - 4); - - const StringMap &Globals = TheCU->getGlobals(); - for (StringMap::const_iterator - GI = Globals.begin(), GE = Globals.end(); GI != GE; ++GI) { - const char *Name = GI->getKeyData(); - DIE *Entity = GI->second; - - Asm->OutStreamer.AddComment("DIE offset"); - Asm->EmitInt32(Entity->getOffset()); - - if (Asm->isVerbose()) - Asm->OutStreamer.AddComment("External Name"); - Asm->OutStreamer.EmitBytes(StringRef(Name, strlen(Name)+1), 0); - } - - Asm->OutStreamer.AddComment("End Mark"); - Asm->EmitInt32(0); - Asm->OutStreamer.EmitLabel(Asm->GetTempSymbol("pubnames_end", - TheCU->getID())); - } -} - void DwarfDebug::emitDebugPubTypes() { for (DenseMap::iterator I = CUMap.begin(), E = CUMap.end(); I != E; ++I) { Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=144169&r1=144168&r2=144169&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Tue Nov 8 23:24:07 2011 @@ -380,12 +380,9 @@ void emitAccelNamespaces(); /// emitAccelTypes() - Emit type dies into a hashed accelerator table. + /// void emitAccelTypes(); - /// emitDebugPubNames - Emit visible names into a debug pubnames section. - /// - void emitDebugPubNames(); - /// emitDebugPubTypes - Emit visible types into a debug pubtypes section. /// void emitDebugPubTypes(); Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=144169&r1=144168&r2=144169&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original) +++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Tue Nov 8 23:24:07 2011 @@ -186,10 +186,6 @@ Ctx->getMachOSection("__DWARF", "__debug_frame", MCSectionMachO::S_ATTR_DEBUG, SectionKind::getMetadata()); - DwarfPubNamesSection = - Ctx->getMachOSection("__DWARF", "__debug_pubnames", - MCSectionMachO::S_ATTR_DEBUG, - SectionKind::getMetadata()); DwarfPubTypesSection = Ctx->getMachOSection("__DWARF", "__debug_pubtypes", MCSectionMachO::S_ATTR_DEBUG, @@ -365,9 +361,6 @@ DwarfFrameSection = Ctx->getELFSection(".debug_frame", ELF::SHT_PROGBITS, 0, SectionKind::getMetadata()); - DwarfPubNamesSection = - Ctx->getELFSection(".debug_pubnames", ELF::SHT_PROGBITS, 0, - SectionKind::getMetadata()); DwarfPubTypesSection = Ctx->getELFSection(".debug_pubtypes", ELF::SHT_PROGBITS, 0, SectionKind::getMetadata()); @@ -453,11 +446,6 @@ COFF::IMAGE_SCN_MEM_DISCARDABLE | COFF::IMAGE_SCN_MEM_READ, SectionKind::getMetadata()); - DwarfPubNamesSection = - Ctx->getCOFFSection(".debug_pubnames", - COFF::IMAGE_SCN_MEM_DISCARDABLE | - COFF::IMAGE_SCN_MEM_READ, - SectionKind::getMetadata()); DwarfPubTypesSection = Ctx->getCOFFSection(".debug_pubtypes", COFF::IMAGE_SCN_MEM_DISCARDABLE | From dpatel at apple.com Wed Nov 9 00:20:50 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 09 Nov 2011 06:20:50 -0000 Subject: [llvm-commits] [llvm] r144172 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Message-ID: <20111109062050.0BDC52A6C12C@llvm.org> Author: dpatel Date: Wed Nov 9 00:20:49 2011 New Revision: 144172 URL: http://llvm.org/viewvc/llvm-project?rev=144172&view=rev Log: Remove extra ';' Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h?rev=144172&r1=144171&r2=144172&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.h Wed Nov 9 00:20:49 2011 @@ -96,7 +96,7 @@ TableHeader (uint32_t data_len) : magic (MagicHash), version (1), hash_function (eHashFunctionDJB), bucket_count (0), hashes_count (0), header_data_len (data_len) - {}; + {} #ifndef NDEBUG void print(raw_ostream &O) { @@ -140,7 +140,7 @@ AtomType type; // enum AtomType uint16_t form; // DWARF DW_FORM_ defines - Atom(AtomType type, uint16_t form) : type(type), form(form) {}; + Atom(AtomType type, uint16_t form) : type(type), form(form) {} static const char * AtomTypeString(enum AtomType); #ifndef NDEBUG void print(raw_ostream &O) { From nicholas at mxc.ca Wed Nov 9 01:11:37 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 09 Nov 2011 07:11:37 -0000 Subject: [llvm-commits] [llvm] r144173 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/trip-count12.ll Message-ID: <20111109071137.D6E922A6C12C@llvm.org> Author: nicholas Date: Wed Nov 9 01:11:37 2011 New Revision: 144173 URL: http://llvm.org/viewvc/llvm-project?rev=144173&view=rev Log: Don't forget to check FlagNW when determining whether an AddRecExpr will wrap or not. Patch by Brendon Cahoon! Added: llvm/trunk/test/Analysis/ScalarEvolution/trip-count12.ll Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=144173&r1=144172&r2=144173&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Nov 9 01:11:37 2011 @@ -6228,8 +6228,9 @@ return getCouldNotCompute(); // Check to see if we have a flag which makes analysis easy. - bool NoWrap = isSigned ? AddRec->getNoWrapFlags(SCEV::FlagNSW) : - AddRec->getNoWrapFlags(SCEV::FlagNUW); + bool NoWrap = isSigned ? + AddRec->getNoWrapFlags((SCEV::NoWrapFlags)(SCEV::FlagNSW | SCEV::FlagNW)) : + AddRec->getNoWrapFlags((SCEV::NoWrapFlags)(SCEV::FlagNUW | SCEV::FlagNW)); if (AddRec->isAffine()) { unsigned BitWidth = getTypeSizeInBits(AddRec->getType()); Added: llvm/trunk/test/Analysis/ScalarEvolution/trip-count12.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/trip-count12.ll?rev=144173&view=auto ============================================================================== --- llvm/trunk/test/Analysis/ScalarEvolution/trip-count12.ll (added) +++ llvm/trunk/test/Analysis/ScalarEvolution/trip-count12.ll Wed Nov 9 01:11:37 2011 @@ -0,0 +1,35 @@ +; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s + +; CHECK: Determining loop execution counts for: @test +; CHECK: Loop %for.body: backedge-taken count is ((-2 + %len) /u 2) +; CHECK: Loop %for.body: max backedge-taken count is 1073741823 + +define zeroext i16 @test(i16* nocapture %p, i32 %len) nounwind readonly { +entry: + %cmp2 = icmp sgt i32 %len, 1 + br i1 %cmp2, label %for.body.preheader, label %for.end + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body, %for.body.preheader + %p.addr.05 = phi i16* [ %incdec.ptr, %for.body ], [ %p, %for.body.preheader ] + %len.addr.04 = phi i32 [ %sub, %for.body ], [ %len, %for.body.preheader ] + %res.03 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] + %incdec.ptr = getelementptr inbounds i16* %p.addr.05, i32 1 + %0 = load i16* %p.addr.05, align 2 + %conv = zext i16 %0 to i32 + %add = add i32 %conv, %res.03 + %sub = add nsw i32 %len.addr.04, -2 + %cmp = icmp sgt i32 %sub, 1 + br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge + +for.cond.for.end_crit_edge: ; preds = %for.body + %extract.t = trunc i32 %add to i16 + br label %for.end + +for.end: ; preds = %for.cond.for.end_crit_edge, %entry + %res.0.lcssa.off0 = phi i16 [ %extract.t, %for.cond.for.end_crit_edge ], [ 0, %entry ] + ret i16 %res.0.lcssa.off0 +} + From craig.topper at gmail.com Wed Nov 9 01:28:55 2011 From: craig.topper at gmail.com (Craig Topper) Date: Wed, 09 Nov 2011 07:28:55 -0000 Subject: [llvm-commits] [llvm] r144174 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx2-arith.ll Message-ID: <20111109072855.8FAA62A6C12F@llvm.org> Author: ctopper Date: Wed Nov 9 01:28:55 2011 New Revision: 144174 URL: http://llvm.org/viewvc/llvm-project?rev=144174&view=rev Log: Add AVX2 instruction lowering for add, sub, and mul. Added: llvm/trunk/test/CodeGen/X86/avx2-arith.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144174&r1=144173&r2=144174&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Nov 9 01:28:55 2011 @@ -1031,25 +1031,42 @@ setOperationAction(ISD::SELECT, MVT::v4i64, Custom); setOperationAction(ISD::SELECT, MVT::v8f32, Custom); - setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); - setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); - setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); - setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); - - setOperationAction(ISD::ADD, MVT::v4i64, Custom); - setOperationAction(ISD::ADD, MVT::v8i32, Custom); - setOperationAction(ISD::ADD, MVT::v16i16, Custom); - setOperationAction(ISD::ADD, MVT::v32i8, Custom); - - setOperationAction(ISD::SUB, MVT::v4i64, Custom); - setOperationAction(ISD::SUB, MVT::v8i32, Custom); - setOperationAction(ISD::SUB, MVT::v16i16, Custom); - setOperationAction(ISD::SUB, MVT::v32i8, Custom); - - setOperationAction(ISD::MUL, MVT::v4i64, Custom); - setOperationAction(ISD::MUL, MVT::v8i32, Custom); - setOperationAction(ISD::MUL, MVT::v16i16, Custom); - // Don't lower v32i8 because there is no 128-bit byte mul + setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); + setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); + setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); + setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); + + if (Subtarget->hasAVX2()) { + setOperationAction(ISD::ADD, MVT::v4i64, Legal); + setOperationAction(ISD::ADD, MVT::v8i32, Legal); + setOperationAction(ISD::ADD, MVT::v16i16, Legal); + setOperationAction(ISD::ADD, MVT::v32i8, Legal); + + setOperationAction(ISD::SUB, MVT::v4i64, Legal); + setOperationAction(ISD::SUB, MVT::v8i32, Legal); + setOperationAction(ISD::SUB, MVT::v16i16, Legal); + setOperationAction(ISD::SUB, MVT::v32i8, Legal); + + setOperationAction(ISD::MUL, MVT::v4i64, Custom); + setOperationAction(ISD::MUL, MVT::v8i32, Legal); + setOperationAction(ISD::MUL, MVT::v16i16, Legal); + // Don't lower v32i8 because there is no 128-bit byte mul + } else { + setOperationAction(ISD::ADD, MVT::v4i64, Custom); + setOperationAction(ISD::ADD, MVT::v8i32, Custom); + setOperationAction(ISD::ADD, MVT::v16i16, Custom); + setOperationAction(ISD::ADD, MVT::v32i8, Custom); + + setOperationAction(ISD::SUB, MVT::v4i64, Custom); + setOperationAction(ISD::SUB, MVT::v8i32, Custom); + setOperationAction(ISD::SUB, MVT::v16i16, Custom); + setOperationAction(ISD::SUB, MVT::v32i8, Custom); + + setOperationAction(ISD::MUL, MVT::v4i64, Custom); + setOperationAction(ISD::MUL, MVT::v8i32, Custom); + setOperationAction(ISD::MUL, MVT::v16i16, Custom); + // Don't lower v32i8 because there is no 128-bit byte mul + } // Custom lower several nodes for 256-bit types. for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; @@ -10004,12 +10021,55 @@ EVT VT = Op.getValueType(); // Decompose 256-bit ops into smaller 128-bit ops. - if (VT.getSizeInBits() == 256) + if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) return Lower256IntArith(Op, DAG); - assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); DebugLoc dl = Op.getDebugLoc(); + SDValue A = Op.getOperand(0); + SDValue B = Op.getOperand(1); + + if (VT == MVT::v4i64) { + assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2"); + + // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32); + // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32); + // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b ); + // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi ); + // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b ); + // + // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 ); + // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 ); + // return AloBlo + AloBhi + AhiBlo; + + SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, + DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), + A, DAG.getConstant(32, MVT::i32)); + SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, + DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), + B, DAG.getConstant(32, MVT::i32)); + SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, + DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), + A, B); + SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, + DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), + A, Bhi); + SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, + DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), + Ahi, B); + AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, + DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), + AloBhi, DAG.getConstant(32, MVT::i32)); + AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, + DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), + AhiBlo, DAG.getConstant(32, MVT::i32)); + SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); + Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); + return Res; + } + + assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); + // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); @@ -10020,9 +10080,6 @@ // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); // return AloBlo + AloBhi + AhiBlo; - SDValue A = Op.getOperand(0); - SDValue B = Op.getOperand(1); - SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), A, DAG.getConstant(32, MVT::i32)); Added: llvm/trunk/test/CodeGen/X86/avx2-arith.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-arith.ll?rev=144174&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx2-arith.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx2-arith.ll Wed Nov 9 01:28:55 2011 @@ -0,0 +1,76 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s + +; CHECK: vpaddq %ymm +define <4 x i64> @vpaddq(<4 x i64> %i, <4 x i64> %j) nounwind readnone { + %x = add <4 x i64> %i, %j + ret <4 x i64> %x +} + +; CHECK: vpaddd %ymm +define <8 x i32> @vpaddd(<8 x i32> %i, <8 x i32> %j) nounwind readnone { + %x = add <8 x i32> %i, %j + ret <8 x i32> %x +} + +; CHECK: vpaddw %ymm +define <16 x i16> @vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { + %x = add <16 x i16> %i, %j + ret <16 x i16> %x +} + +; CHECK: vpaddb %ymm +define <32 x i8> @vpaddb(<32 x i8> %i, <32 x i8> %j) nounwind readnone { + %x = add <32 x i8> %i, %j + ret <32 x i8> %x +} + +; CHECK: vpsubq %ymm +define <4 x i64> @vpsubq(<4 x i64> %i, <4 x i64> %j) nounwind readnone { + %x = sub <4 x i64> %i, %j + ret <4 x i64> %x +} + +; CHECK: vpsubd %ymm +define <8 x i32> @vpsubd(<8 x i32> %i, <8 x i32> %j) nounwind readnone { + %x = sub <8 x i32> %i, %j + ret <8 x i32> %x +} + +; CHECK: vpsubw %ymm +define <16 x i16> @vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { + %x = sub <16 x i16> %i, %j + ret <16 x i16> %x +} + +; CHECK: vpsubb %ymm +define <32 x i8> @vpsubb(<32 x i8> %i, <32 x i8> %j) nounwind readnone { + %x = sub <32 x i8> %i, %j + ret <32 x i8> %x +} + +; CHECK: vpmulld %ymm +define <8 x i32> @vpmulld(<8 x i32> %i, <8 x i32> %j) nounwind readnone { + %x = mul <8 x i32> %i, %j + ret <8 x i32> %x +} + +; CHECK: vpmullw %ymm +define <16 x i16> @vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { + %x = mul <16 x i16> %i, %j + ret <16 x i16> %x +} + +; CHECK: vpmuludq %ymm +; CHECK-NEXT: vpsrlq $32, %ymm +; CHECK-NEXT: vpmuludq %ymm +; CHECK-NEXT: vpsllq $32, %ymm +; CHECK-NEXT: vpaddq %ymm +; CHECK-NEXT: vpsrlq $32, %ymm +; CHECK-NEXT: vpmuludq %ymm +; CHECK-NEXT: vpsllq $32, %ymm +; CHECK-NEXT: vpaddq %ymm +define <4 x i64> @mul-v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone { + %x = mul <4 x i64> %i, %j + ret <4 x i64> %x +} + From craig.topper at gmail.com Wed Nov 9 02:06:14 2011 From: craig.topper at gmail.com (Craig Topper) Date: Wed, 09 Nov 2011 08:06:14 -0000 Subject: [llvm-commits] [llvm] r144176 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx2-cmp.ll Message-ID: <20111109080614.2BF912A6C12C@llvm.org> Author: ctopper Date: Wed Nov 9 02:06:13 2011 New Revision: 144176 URL: http://llvm.org/viewvc/llvm-project?rev=144176&view=rev Log: Add instruction selection for AVX2 integer comparisons. Added: llvm/trunk/test/CodeGen/X86/avx2-cmp.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144176&r1=144175&r2=144176&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Nov 9 02:06:13 2011 @@ -8560,8 +8560,7 @@ UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); - } - else if (SetCCOpcode == ISD::SETONE) { + } else if (SetCCOpcode == ISD::SETONE) { SDValue ORD, NEQ; ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); @@ -8574,7 +8573,7 @@ } // Break 256-bit integer vector compare into smaller ones. - if (!isFP && VT.getSizeInBits() == 256) + if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) return Lower256IntVSETCC(Op, DAG); // We are handling one of the integer comparisons here. Since SSE only has @@ -8583,12 +8582,12 @@ unsigned Opc = 0, EQOpc = 0, GTOpc = 0; bool Swap = false, Invert = false, FlipSigns = false; - switch (VT.getSimpleVT().SimpleTy) { + switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { default: break; - case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; - case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; - case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; - case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; + case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; + case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; + case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; + case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; } switch (SetCCOpcode) { Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144176&r1=144175&r2=144176&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Nov 9 02:06:13 2011 @@ -3917,6 +3917,32 @@ VR256, memopv4i64, i256mem, 0, 0>, VEX_4V; defm VPCMPGTDY : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_avx2_pcmpgt_d, VR256, memopv4i64, i256mem, 0, 0>, VEX_4V; + + def : Pat<(v32i8 (X86pcmpeqb VR256:$src1, VR256:$src2)), + (VPCMPEQBYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v32i8 (X86pcmpeqb VR256:$src1, (memop addr:$src2))), + (VPCMPEQBYrm VR256:$src1, addr:$src2)>; + def : Pat<(v16i16 (X86pcmpeqw VR256:$src1, VR256:$src2)), + (VPCMPEQWYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v16i16 (X86pcmpeqw VR256:$src1, (memop addr:$src2))), + (VPCMPEQWYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8i32 (X86pcmpeqd VR256:$src1, VR256:$src2)), + (VPCMPEQDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (X86pcmpeqd VR256:$src1, (memop addr:$src2))), + (VPCMPEQDYrm VR256:$src1, addr:$src2)>; + + def : Pat<(v32i8 (X86pcmpgtb VR256:$src1, VR256:$src2)), + (VPCMPGTBYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v32i8 (X86pcmpgtb VR256:$src1, (memop addr:$src2))), + (VPCMPGTBYrm VR256:$src1, addr:$src2)>; + def : Pat<(v16i16 (X86pcmpgtw VR256:$src1, VR256:$src2)), + (VPCMPGTWYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v16i16 (X86pcmpgtw VR256:$src1, (memop addr:$src2))), + (VPCMPGTWYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8i32 (X86pcmpgtd VR256:$src1, VR256:$src2)), + (VPCMPGTDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (X86pcmpgtd VR256:$src1, (memop addr:$src2))), + (VPCMPGTDYrm VR256:$src1, addr:$src2)>; } let Constraints = "$src1 = $dst" in { @@ -6325,6 +6351,11 @@ int_x86_avx2_pmaxu_w>, VEX_4V; defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq", int_x86_avx2_pmul_dq>, VEX_4V; + + def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, VR256:$src2)), + (VPCMPEQQYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, (memop addr:$src2))), + (VPCMPEQQYrm VR256:$src1, addr:$src2)>; } let Constraints = "$src1 = $dst" in { @@ -6647,6 +6678,11 @@ let Predicates = [HasAVX2] in { defm VPCMPGTQ : SS42I_binop_rm_int_y<0x37, "vpcmpgtq", int_x86_avx2_pcmpgt_q>, VEX_4V; + + def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, VR256:$src2)), + (VPCMPGTQYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, (memop addr:$src2))), + (VPCMPGTQYrm VR256:$src1, addr:$src2)>; } let Constraints = "$src1 = $dst" in Added: llvm/trunk/test/CodeGen/X86/avx2-cmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-cmp.ll?rev=144176&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx2-cmp.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx2-cmp.ll Wed Nov 9 02:06:13 2011 @@ -0,0 +1,58 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s + +; CHECK: vpcmpgtd %ymm +define <8 x i32> @int256-cmp(<8 x i32> %i, <8 x i32> %j) nounwind readnone { + %bincmp = icmp slt <8 x i32> %i, %j + %x = sext <8 x i1> %bincmp to <8 x i32> + ret <8 x i32> %x +} + +; CHECK: vpcmpgtq %ymm +define <4 x i64> @v4i64-cmp(<4 x i64> %i, <4 x i64> %j) nounwind readnone { + %bincmp = icmp slt <4 x i64> %i, %j + %x = sext <4 x i1> %bincmp to <4 x i64> + ret <4 x i64> %x +} + +; CHECK: vpcmpgtw %ymm +define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone { + %bincmp = icmp slt <16 x i16> %i, %j + %x = sext <16 x i1> %bincmp to <16 x i16> + ret <16 x i16> %x +} + +; CHECK: vpcmpgtb %ymm +define <32 x i8> @v32i8-cmp(<32 x i8> %i, <32 x i8> %j) nounwind readnone { + %bincmp = icmp slt <32 x i8> %i, %j + %x = sext <32 x i1> %bincmp to <32 x i8> + ret <32 x i8> %x +} + +; CHECK: vpcmpeqd %ymm +define <8 x i32> @int256-cmpeq(<8 x i32> %i, <8 x i32> %j) nounwind readnone { + %bincmp = icmp eq <8 x i32> %i, %j + %x = sext <8 x i1> %bincmp to <8 x i32> + ret <8 x i32> %x +} + +; CHECK: vpcmpeqq %ymm +define <4 x i64> @v4i64-cmpeq(<4 x i64> %i, <4 x i64> %j) nounwind readnone { + %bincmp = icmp eq <4 x i64> %i, %j + %x = sext <4 x i1> %bincmp to <4 x i64> + ret <4 x i64> %x +} + +; CHECK: vpcmpeqw %ymm +define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone { + %bincmp = icmp eq <16 x i16> %i, %j + %x = sext <16 x i1> %bincmp to <16 x i16> + ret <16 x i16> %x +} + +; CHECK: vpcmpeqb %ymm +define <32 x i8> @v32i8-cmpeq(<32 x i8> %i, <32 x i8> %j) nounwind readnone { + %bincmp = icmp eq <32 x i8> %i, %j + %x = sext <32 x i1> %bincmp to <32 x i8> + ret <32 x i8> %x +} + From geek4civic at gmail.com Wed Nov 9 02:30:43 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 09 Nov 2011 08:30:43 -0000 Subject: [llvm-commits] [llvm] r144178 - /llvm/trunk/unittests/ExecutionEngine/JIT/MultiJITTest.cpp Message-ID: <20111109083043.CE2692A6C12D@llvm.org> Author: chapuni Date: Wed Nov 9 02:30:43 2011 New Revision: 144178 URL: http://llvm.org/viewvc/llvm-project?rev=144178&view=rev Log: unittests/MultiJITTest.cpp: Tweak how to check symbol value for Win32 --enable-shared. getPointerToNamedFunction might be indirect jump on Win32 --enable-shared. FF 25 : jmp *(pointer to IAT) Modified: llvm/trunk/unittests/ExecutionEngine/JIT/MultiJITTest.cpp Modified: llvm/trunk/unittests/ExecutionEngine/JIT/MultiJITTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ExecutionEngine/JIT/MultiJITTest.cpp?rev=144178&r1=144177&r2=144178&view=diff ============================================================================== --- llvm/trunk/unittests/ExecutionEngine/JIT/MultiJITTest.cpp (original) +++ llvm/trunk/unittests/ExecutionEngine/JIT/MultiJITTest.cpp Wed Nov 9 02:30:43 2011 @@ -160,8 +160,21 @@ EXPECT_EQ(getPointerToNamedFunction("foo2"), foo2); // Symbol search - EXPECT_EQ((intptr_t)getPointerToNamedFunction("getPointerToNamedFunction"), - (intptr_t)&getPointerToNamedFunction); + intptr_t + sa = (intptr_t)getPointerToNamedFunction("getPointerToNamedFunction"); + EXPECT_TRUE(sa != 0); + intptr_t fa = (intptr_t)&getPointerToNamedFunction; + EXPECT_TRUE(fa != 0); +#ifdef __i386__ + // getPointerToNamedFunction might be indirect jump on Win32 --enable-shared. + // FF 25 : jmp *(pointer to IAT) + if (sa != fa && memcmp((char *)fa, "\xFF\x25", 2) == 0) { + fa = *(intptr_t *)(fa + 2); // Address to IAT + EXPECT_TRUE(fa != 0); + fa = *(intptr_t *)fa; // Bound value of IAT + } +#endif + EXPECT_TRUE(sa == fa); } #endif // !defined(__arm__) From craig.topper at gmail.com Wed Nov 9 03:37:22 2011 From: craig.topper at gmail.com (Craig Topper) Date: Wed, 09 Nov 2011 09:37:22 -0000 Subject: [llvm-commits] [llvm] r144179 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86TargetMachine.cpp test/CodeGen/X86/avx2-logic.ll Message-ID: <20111109093722.2EB652A6C12C@llvm.org> Author: ctopper Date: Wed Nov 9 03:37:21 2011 New Revision: 144179 URL: http://llvm.org/viewvc/llvm-project?rev=144179&view=rev Log: Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions. Added: llvm/trunk/test/CodeGen/X86/avx2-logic.ll Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=144179&r1=144178&r2=144179&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Nov 9 03:37:21 2011 @@ -3367,6 +3367,14 @@ { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }, + { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, + { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, + { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, + { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, + { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, + { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, + { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, + { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, }; // FIXME: Some shuffle and unpack instructions have equivalents in different Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=144179&r1=144178&r2=144179&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Wed Nov 9 03:37:21 2011 @@ -135,10 +135,18 @@ bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { bool ShouldPrint = false; - if (OptLevel != CodeGenOpt::None && - (Subtarget.hasSSE2() || Subtarget.hasAVX())) { - PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass)); - ShouldPrint = true; + if (OptLevel != CodeGenOpt::None) { + if (Subtarget.hasXMMInt()) { + PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass)); + ShouldPrint = true; + } + if (Subtarget.hasAVX2()) { + // FIXME this should be turned on for just AVX, but the pass doesn't check + // that instructions are valid before replacing them and there are AVX2 + // integer instructions in the table. + PM.add(createExecutionDependencyFixPass(&X86::VR256RegClass)); + ShouldPrint = true; + } } if (Subtarget.hasAVX() && UseVZeroUpper) { Added: llvm/trunk/test/CodeGen/X86/avx2-logic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-logic.ll?rev=144179&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx2-logic.ll (added) +++ llvm/trunk/test/CodeGen/X86/avx2-logic.ll Wed Nov 9 03:37:21 2011 @@ -0,0 +1,38 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s + +; CHECK: vpandn %ymm +define <4 x i64> @vpandn(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp { +entry: + ; Force the execution domain with an add. + %a2 = add <4 x i64> %a, + %y = xor <4 x i64> %a2, + %x = and <4 x i64> %a, %y + ret <4 x i64> %x +} + +; CHECK: vpand %ymm +define <4 x i64> @vpand(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp { +entry: + ; Force the execution domain with an add. + %a2 = add <4 x i64> %a, + %x = and <4 x i64> %a2, %b + ret <4 x i64> %x +} + +; CHECK: vpor %ymm +define <4 x i64> @vpor(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp { +entry: + ; Force the execution domain with an add. + %a2 = add <4 x i64> %a, + %x = or <4 x i64> %a2, %b + ret <4 x i64> %x +} + +; CHECK: vpxor %ymm +define <4 x i64> @vpxor(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp { +entry: + ; Force the execution domain with an add. + %a2 = add <4 x i64> %a, + %x = xor <4 x i64> %a2, %b + ret <4 x i64> %x +} From baldrick at free.fr Wed Nov 9 04:43:17 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 09 Nov 2011 10:43:17 -0000 Subject: [llvm-commits] [zorg] r144180 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20111109104317.6D4EB2A6C12D@llvm.org> Author: baldrick Date: Wed Nov 9 04:43:16 2011 New Revision: 144180 URL: http://llvm.org/viewvc/llvm-project?rev=144180&view=rev Log: Recent gcc miscompiles siod and consumer-lame. I added the XFAIL to the wrong list: move it to the right one. Chandler fixed the include path issue which was breaking tramp3d-v4, so un-XFAIL it. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=144180&r1=144179&r2=144180&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Wed Nov 9 04:43:16 2011 @@ -146,31 +146,24 @@ gxxincludedir='/usr/include/c++/4.2.1')}, clang_i386_linux_xfails = [ - 'GCC.MultiSource/Applications/siod/siod', - 'GCC.MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame', - 'GCCAS.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', - 'Bytecode.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', 'LLC.MultiSource/Applications/oggenc/oggenc', 'LLC.MultiSource/Benchmarks/VersaBench/bmm/bmm', 'LLC.MultiSource/Benchmarks/VersaBench/dbms/dbms', - 'LLC.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', 'LLC.SingleSource/Benchmarks/Misc-C++/Large/sphereflake', 'LLC.SingleSource/Regression/C++/EH/ConditionalExpr', 'LLC_compile.MultiSource/Applications/oggenc/oggenc', 'LLC_compile.MultiSource/Benchmarks/VersaBench/bmm/bmm', 'LLC_compile.MultiSource/Benchmarks/VersaBench/dbms/dbms', - 'LLC_compile.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', 'LLC_compile.SingleSource/Benchmarks/Misc-C++/Large/sphereflake', 'LLC_compile.SingleSource/Regression/C++/EH/ConditionalExpr', ] clang_x86_64_linux_xfails = [ - 'GCCAS.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', - 'Bytecode.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', + 'GCC.MultiSource/Applications/siod/siod', + 'GCC.MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame', 'LLC.SingleSource/Regression/C++/EH/ConditionalExpr', 'LLC.SingleSource/UnitTests/Vector/SSE/sse.expandfft', 'LLC.SingleSource/UnitTests/Vector/SSE/sse.stepfft', - 'LLC_compile.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', 'LLC_compile.SingleSource/Regression/C++/EH/ConditionalExpr', 'LLC_compile.SingleSource/UnitTests/Vector/SSE/sse.expandfft', 'LLC_compile.SingleSource/UnitTests/Vector/SSE/sse.stepfft', From baldrick at free.fr Wed Nov 9 04:46:28 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 09 Nov 2011 11:46:28 +0100 Subject: [llvm-commits] [zorg] r143963 - /zorg/trunk/buildbot/osuosl/master/config/builders.py In-Reply-To: References: <20111107170050.E01A12A6C12C@llvm.org> Message-ID: <4EBA5A04.2040205@free.fr> Hi Eli, I modified the wrong list; I've fixed it now. Ciao, Duncan. On 11/08/11 20:50, Eli Friedman wrote: > On Mon, Nov 7, 2011 at 9:00 AM, Duncan Sands wrote: >> Author: baldrick >> Date: Mon Nov 7 11:00:50 2011 >> New Revision: 143963 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=143963&view=rev >> Log: >> Recent gcc miscompiles these - they are expected to fail. >> >> Modified: >> zorg/trunk/buildbot/osuosl/master/config/builders.py >> >> Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py >> URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=143963&r1=143962&r2=143963&view=diff >> ============================================================================== >> --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) >> +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Nov 7 11:00:50 2011 >> @@ -146,6 +146,8 @@ >> gxxincludedir='/usr/include/c++/4.2.1')}, >> >> clang_i386_linux_xfails = [ >> + 'GCC.MultiSource/Applications/siod/siod', >> + 'GCC.MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame', >> 'GCCAS.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', >> 'Bytecode.MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4', >> 'LLC.MultiSource/Applications/oggenc/oggenc', > > It looks like the same failures are showing up at > http://lab.llvm.org:8011/builders/clang-x86_64-debian-fnt/builds/1175/steps/make.test-suite/logs/fail.GCC > . Mind fixing that bot as well? > > -Eli From wmatyjewicz at fastmail.fm Wed Nov 9 06:00:39 2011 From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz) Date: Wed, 09 Nov 2011 12:00:39 -0000 Subject: [llvm-commits] [llvm] r144183 - in /llvm/trunk/bindings/ocaml: Makefile.ocaml llvm/Makefile Message-ID: <20111109120039.466122A6C12D@llvm.org> Author: wmat Date: Wed Nov 9 06:00:39 2011 New Revision: 144183 URL: http://llvm.org/viewvc/llvm-project?rev=144183&view=rev Log: Minor fixes in Makefiles for the OCaml bindings: 1. Interface files (.mli) are installed before compiled interface files (.cmi) to preserve timestamp relation. 2. install-meta should use $(OcamlDir) instead of $(ObjDir). 3. Declared some targets as .PHONY. Patch by Christophe Raffalli. Modified: llvm/trunk/bindings/ocaml/Makefile.ocaml llvm/trunk/bindings/ocaml/llvm/Makefile Modified: llvm/trunk/bindings/ocaml/Makefile.ocaml URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/Makefile.ocaml?rev=144183&r1=144182&r2=144183&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/Makefile.ocaml (original) +++ llvm/trunk/bindings/ocaml/Makefile.ocaml Wed Nov 9 06:00:39 2011 @@ -238,14 +238,14 @@ # Also install the .mli's (headers) as documentation. install-cmis: $(OutputsCMI) $(OcamlHeaders) $(Verb) $(MKDIR) $(PROJ_libocamldir) - $(Verb) for i in $(OutputsCMI:$(OcamlDir)/%=%); do \ - $(EchoCmd) "Installing $(BuildMode) $(PROJ_libocamldir)/$$i"; \ - $(DataInstall) $(OcamlDir)/$$i "$(PROJ_libocamldir)/$$i"; \ - done $(Verb) for i in $(OcamlHeaders:$(ObjDir)/%=%); do \ $(EchoCmd) "Installing $(BuildMode) $(PROJ_libocamldir)/$$i"; \ $(DataInstall) $(ObjDir)/$$i "$(PROJ_libocamldir)/$$i"; \ done + $(Verb) for i in $(OutputsCMI:$(OcamlDir)/%=%); do \ + $(EchoCmd) "Installing $(BuildMode) $(PROJ_libocamldir)/$$i"; \ + $(DataInstall) $(OcamlDir)/$$i "$(PROJ_libocamldir)/$$i"; \ + done uninstall-cmis:: $(Verb) for i in $(OutputsCMI:$(OcamlDir)/%=%); do \ Modified: llvm/trunk/bindings/ocaml/llvm/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/llvm/Makefile?rev=144183&r1=144182&r2=144183&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/llvm/Makefile (original) +++ llvm/trunk/bindings/ocaml/llvm/Makefile Wed Nov 9 06:00:39 2011 @@ -30,11 +30,13 @@ $(OcamlDir)/META.llvm: META.llvm $(Verb) $(CP) -f $< $@ -install-meta:: $(ObjDir)/META.llvm +install-meta:: $(OcamlDir)/META.llvm $(Echo) "Install $(BuildMode) $(DestMETA)" $(Verb) $(MKDIR) $(PROJ_libocamldir) - $(Verb) $(DataInstall) META.llvm "$(DestMETA)" + $(Verb) $(DataInstall) $< "$(DestMETA)" uninstall-meta:: $(Echo) "Uninstalling $(DestMETA)" -$(Verb) $(RM) -f "$(DestMETA)" + +.PHONY: copy-meta install-meta uninstall-meta From benny.kra at googlemail.com Wed Nov 9 06:12:04 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 09 Nov 2011 12:12:04 -0000 Subject: [llvm-commits] [llvm] r144184 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20111109121204.8245B2A6C12D@llvm.org> Author: d0k Date: Wed Nov 9 06:12:04 2011 New Revision: 144184 URL: http://llvm.org/viewvc/llvm-project?rev=144184&view=rev Log: Take advantage of the zero byte in StringMap when emitting dwarf stringpool entries. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=144184&r1=144183&r2=144184&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Nov 9 06:12:04 2011 @@ -1937,8 +1937,9 @@ Asm->OutStreamer.EmitLabel(Entries[i].second->getValue().first); // Emit the string itself. - Asm->OutStreamer.EmitBytes(Entries[i].second->getKey(), 0/*addrspace*/); - Asm->OutStreamer.EmitZeros(1, 0); + Asm->OutStreamer.EmitBytes(StringRef(Entries[i].second->getKeyData(), + Entries[i].second->getKeyLength()+1), + 0/*addrspace*/); } } From benny.kra at googlemail.com Wed Nov 9 07:19:15 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 09 Nov 2011 13:19:15 -0000 Subject: [llvm-commits] [llvm] r144186 - /llvm/trunk/lib/MC/MCDwarf.cpp Message-ID: <20111109131915.8FA702A6C12D@llvm.org> Author: d0k Date: Wed Nov 9 07:19:15 2011 New Revision: 144186 URL: http://llvm.org/viewvc/llvm-project?rev=144186&view=rev Log: Simplify code. No functionality change. Modified: llvm/trunk/lib/MC/MCDwarf.cpp Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=144186&r1=144185&r2=144186&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Wed Nov 9 07:19:15 2011 @@ -371,10 +371,7 @@ // it with DW_LNS_advance_line. if (Temp >= DWARF2_LINE_RANGE) { OS << char(dwarf::DW_LNS_advance_line); - SmallString<32> Tmp; - raw_svector_ostream OSE(Tmp); - MCObjectWriter::EncodeSLEB128(LineDelta, OSE); - OS << OSE.str(); + MCObjectWriter::EncodeSLEB128(LineDelta, OS); LineDelta = 0; Temp = 0 - DWARF2_LINE_BASE; @@ -410,10 +407,7 @@ // Otherwise use DW_LNS_advance_pc. OS << char(dwarf::DW_LNS_advance_pc); - SmallString<32> Tmp; - raw_svector_ostream OSE(Tmp); - MCObjectWriter::EncodeULEB128(AddrDelta, OSE); - OS << OSE.str(); + MCObjectWriter::EncodeULEB128(AddrDelta, OS); if (NeedCopy) OS << char(dwarf::DW_LNS_copy); From nadav.rotem at intel.com Wed Nov 9 07:21:28 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Wed, 09 Nov 2011 13:21:28 -0000 Subject: [llvm-commits] [llvm] r144187 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx2-logic.ll Message-ID: <20111109132128.E321E2A6C12D@llvm.org> Author: nadav Date: Wed Nov 9 07:21:28 2011 New Revision: 144187 URL: http://llvm.org/viewvc/llvm-project?rev=144187&view=rev Log: Add AVX2 support for vselect of v32i8 Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx2-logic.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144187&r1=144186&r2=144187&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Nov 9 07:21:28 2011 @@ -1050,6 +1050,8 @@ setOperationAction(ISD::MUL, MVT::v4i64, Custom); setOperationAction(ISD::MUL, MVT::v8i32, Legal); setOperationAction(ISD::MUL, MVT::v16i16, Legal); + + setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); // Don't lower v32i8 because there is no 128-bit byte mul } else { setOperationAction(ISD::ADD, MVT::v4i64, Custom); Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144187&r1=144186&r2=144187&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Nov 9 07:21:28 2011 @@ -6568,6 +6568,12 @@ (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>; } +let Predicates = [HasAVX2] in { + def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1), + (v32i8 VR256:$src2))), + (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>; +} + /// SS41I_ternary_int - SSE 4.1 ternary operator let Uses = [XMM0], Constraints = "$src1 = $dst" in { multiclass SS41I_ternary_int opc, string OpcodeStr, Intrinsic IntId> { Modified: llvm/trunk/test/CodeGen/X86/avx2-logic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-logic.ll?rev=144187&r1=144186&r2=144187&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx2-logic.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx2-logic.ll Wed Nov 9 07:21:28 2011 @@ -1,6 +1,8 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s +; CHECK: vpandn ; CHECK: vpandn %ymm +; CHECK: ret define <4 x i64> @vpandn(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp { entry: ; Force the execution domain with an add. @@ -10,7 +12,9 @@ ret <4 x i64> %x } +; CHECK: vpand ; CHECK: vpand %ymm +; CHECK: ret define <4 x i64> @vpand(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp { entry: ; Force the execution domain with an add. @@ -19,7 +23,9 @@ ret <4 x i64> %x } +; CHECK: vpor ; CHECK: vpor %ymm +; CHECK: ret define <4 x i64> @vpor(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp { entry: ; Force the execution domain with an add. @@ -28,7 +34,9 @@ ret <4 x i64> %x } +; CHECK: vpxor ; CHECK: vpxor %ymm +; CHECK: ret define <4 x i64> @vpxor(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp { entry: ; Force the execution domain with an add. @@ -36,3 +44,14 @@ %x = xor <4 x i64> %a2, %b ret <4 x i64> %x } + + + +; CHECK: vpblendvb +; CHECK: vpblendvb %ymm +; CHECK: ret +define <32 x i8> @vpblendvb(<32 x i8> %x, <32 x i8> %y) { + %min_is_x = icmp ult <32 x i8> %x, %y + %min = select <32 x i1> %min_is_x, <32 x i8> %x, <32 x i8> %y + ret <32 x i8> %min +} From baldrick at free.fr Wed Nov 9 08:20:48 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 09 Nov 2011 14:20:48 -0000 Subject: [llvm-commits] [llvm] r144188 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll Message-ID: <20111109142048.965491BE001@llvm.org> Author: baldrick Date: Wed Nov 9 08:20:48 2011 New Revision: 144188 URL: http://llvm.org/viewvc/llvm-project?rev=144188&view=rev Log: Speculatively revert commit 144124 (djg) in the hope that the 32 bit dragonegg self-host buildbot will recover (it is complaining about object files differing between different build stages). Original commit message: Add a hack to the scheduler to disable pseudo-two-address dependencies in basic blocks containing calls. This works around a problem in which these artificial dependencies can get tied up in calling seqeunce scheduling in a way that makes the graph unschedulable with the current approach of using artificial physical register dependencies for calling sequences. This fixes PR11314. Removed: llvm/trunk/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=144188&r1=144187&r2=144188&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Nov 9 08:20:48 2011 @@ -1666,7 +1666,7 @@ protected: bool canClobber(const SUnit *SU, const SUnit *Op); - void AddPseudoTwoAddrDeps(const TargetInstrInfo *TII); + void AddPseudoTwoAddrDeps(); void PrescheduleNodesWithMultipleUses(); void CalculateSethiUllmanNumbers(); }; @@ -2628,7 +2628,7 @@ void RegReductionPQBase::initNodes(std::vector &sunits) { SUnits = &sunits; // Add pseudo dependency edges for two-address nodes. - AddPseudoTwoAddrDeps(TII); + AddPseudoTwoAddrDeps(); // Reroute edges to nodes with multiple uses. if (!TracksRegPressure) PrescheduleNodesWithMultipleUses(); @@ -2855,17 +2855,7 @@ /// one that has a CopyToReg use (more likely to be a loop induction update). /// If both are two-address, but one is commutable while the other is not /// commutable, favor the one that's not commutable. -void RegReductionPQBase::AddPseudoTwoAddrDeps(const TargetInstrInfo *TII) { - // If the graph contains any calls, disable this optimization. - // FIXME: This is a kludge to work around the fact that the artificial edges - // can combine with the way call sequences use physical register dependencies - // to model their resource usage to create unschedulable graphs. - for (unsigned i = 0, e = SUnits->size(); i != e; ++i) - for (SDNode *Node = (*SUnits)[i].getNode(); Node; Node = Node->getGluedNode()) - if (Node->isMachineOpcode() && - Node->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) - return; - +void RegReductionPQBase::AddPseudoTwoAddrDeps() { for (unsigned i = 0, e = SUnits->size(); i != e; ++i) { SUnit *SU = &(*SUnits)[i]; if (!SU->isTwoAddress) Modified: llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll?rev=144188&r1=144187&r2=144188&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll (original) +++ llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll Wed Nov 9 08:20:48 2011 @@ -3,9 +3,15 @@ ; This testcase shouldn't need to spill the -1 value, ; so it should just use pcmpeqd to materialize an all-ones vector. +; For i386, cp load of -1 are folded. -; I386: pcmpeqd +; With -regalloc=greedy, the live range is split before spilling, so the first +; pcmpeq doesn't get folded as a constant pool load. + +; I386-NOT: pcmpeqd +; I386: orps LCPI0_2, %xmm ; I386-NOT: pcmpeqd +; I386: orps LCPI0_2, %xmm ; X86-64: pcmpeqd ; X86-64-NOT: pcmpeqd Removed: llvm/trunk/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll?rev=144187&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll (original) +++ llvm/trunk/test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll (removed) @@ -1,16 +0,0 @@ -; RUN: llc -march=x86 -mcpu=pentium4 -mtriple=i686-none-linux < %s -; PR11314 - -; Make sure the scheduler's hack to insert artificial dependencies to optimize -; two-address instruction scheduling doesn't interfere with the scheduler's -; hack to model call sequences as artificial physical registers. - -define inreg { i64, i64 } @sscanf(i32 inreg %base.1.i) nounwind { -entry: - %conv38.i92.i = sext i32 %base.1.i to i64 - %rem.i93.i = urem i64 10, %conv38.i92.i - %div.i94.i = udiv i64 10, %conv38.i92.i - %a = insertvalue { i64, i64 } undef, i64 %rem.i93.i, 0 - %b = insertvalue { i64, i64 } %a, i64 %div.i94.i, 1 - ret { i64, i64 } %b -} From elena.demikhovsky at intel.com Wed Nov 9 08:41:50 2011 From: elena.demikhovsky at intel.com (Demikhovsky, Elena) Date: Wed, 9 Nov 2011 16:41:50 +0200 Subject: [llvm-commits] AVX1 Code Generation - VSHUFP extension References: <7CB6AC5AED596245A99BF3213DE8F4AA02FFEA3063@hasmsx504.ger.corp.intel.com> <7CB6AC5AED596245A99BF3213DE8F4AA02FFF2B81B@hasmsx504.ger.corp.intel.com> Message-ID: <7CB6AC5AED596245A99BF3213DE8F4AA02FFF96817@hasmsx504.ger.corp.intel.com> Hi, I fixed the comments, I put 2 functions isCommutedVSHUFP() together. If this patch is good, please commit it. Thank you. - Elena -----Original Message----- From: Demikhovsky, Elena Sent: Tuesday, November 08, 2011 16:46 To: 'Bruno Cardoso Lopes' Cc: Eli Friedman; llvm-commits at cs.uiuc.edu Subject: RE: [llvm-commits] AVX1 Code Generation - VSHUFP extension 3) I tried to make my code similar to existing. if I put one function the code will look like: if (!V2IsUndef && isCommutedVSHUFP(M, VT, Subtarget)) { SVOp = cast(CommuteVectorShuffle(SVOp, DAG)); V1 = SVOp->getOperand(0); V2 = SVOp->getOperand(1); unsigned TargetMask = (VT.getVectorNumElements() == 8) ? getShuffleVSHUFPSYImmediate(SVOp): getShuffleVSHUFPDYImmediate(SVOp); return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, TargetMask, DAG); } - Elena -----Original Message----- From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] Sent: Tuesday, November 08, 2011 15:21 To: Demikhovsky, Elena Cc: Eli Friedman; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] AVX1 Code Generation - VSHUFP extension Hi Elena, > I fixed the code. The input mask remains unchanged now. > Please take a look. A couple more comments: 1) Please change the comments to use "//" instead of "/**/". 2) Your patch is broken: contains the diff of the same file more than once. 3) No need to have 2 isCommutedVSHUFP*. Just have one function and check "ps" or "pd" using the number of elements using VT.getVectorNumElements() - but make sure to still check for 256-bits. 4) Why don't match when V2IsUndef? I suppose it's because you want the shuffle to be xformed to a "extract of the low part"+128_bit-shuffle later. If that's the case, add a comment saying that! Thanks -- Bruno Cardoso Lopes http://www.brunocardoso.cc --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: vshufp2.diff Type: application/octet-stream Size: 3073 bytes Desc: vshufp2.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/c8c45ef0/attachment.obj From bruno.cardoso at gmail.com Wed Nov 9 10:43:06 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 9 Nov 2011 14:43:06 -0200 Subject: [llvm-commits] AVX1 Code Generation - VSHUFP extension In-Reply-To: <7CB6AC5AED596245A99BF3213DE8F4AA02FFF96817@hasmsx504.ger.corp.intel.com> References: <7CB6AC5AED596245A99BF3213DE8F4AA02FFEA3063@hasmsx504.ger.corp.intel.com> <7CB6AC5AED596245A99BF3213DE8F4AA02FFF2B81B@hasmsx504.ger.corp.intel.com> <7CB6AC5AED596245A99BF3213DE8F4AA02FFF96817@hasmsx504.ger.corp.intel.com> Message-ID: Hi, > I fixed the comments, I put 2 functions isCommutedVSHUFP() together. > > If this patch is good, please commit it. Looks great! Just one more fix: +static void CommuteVectorShuffleMask(SmallVectorImpl &Mask, EVT VT); + + + +/// isCommutedVSHUFP() - Return true if swapping operands will +/// allow to use the "vshufpd" or "vshufps" instruction +/// for 256-bit vectors + +static bool isCommutedVSHUFPMask(const SmallVectorImpl &Mask, EVT VT, + const X86Subtarget *Subtarget) { Please move the function definition up so you don't need to use a declaration, and make the comment above tied to the function (no newline between them). -- Bruno Cardoso Lopes http://www.brunocardoso.cc From echristo at apple.com Wed Nov 9 11:04:30 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 09 Nov 2011 09:04:30 -0800 Subject: [llvm-commits] [llvm] r144184 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp In-Reply-To: <20111109121204.8245B2A6C12D@llvm.org> References: <20111109121204.8245B2A6C12D@llvm.org> Message-ID: On Nov 9, 2011, at 4:12 AM, Benjamin Kramer wrote: > Take advantage of the zero byte in StringMap when emitting dwarf stringpool entries. Tricky :) Feel like putting a comment about that in there? -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/8b587565/attachment.html From grosser at fim.uni-passau.de Wed Nov 9 11:44:03 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 17:44:03 -0000 Subject: [llvm-commits] [polly] r144192 - /polly/trunk/www/get_started.html Message-ID: <20111109174403.79F041BE001@llvm.org> Author: grosser Date: Wed Nov 9 11:44:03 2011 New Revision: 144192 URL: http://llvm.org/viewvc/llvm-project?rev=144192&view=rev Log: www: Fix install location of cloog in the installation guide. Modified: polly/trunk/www/get_started.html Modified: polly/trunk/www/get_started.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/get_started.html?rev=144192&r1=144191&r2=144192&view=diff ============================================================================== --- polly/trunk/www/get_started.html (original) +++ polly/trunk/www/get_started.html Wed Nov 9 11:44:03 2011 @@ -59,7 +59,7 @@

    Set the directory layout:

     export CLOOG_SRC=${BASE}/cloog_src
-export CLOOG_INSTALL=${LLVM_SRC}/cloog_install
+export CLOOG_INSTALL=${BASE}/cloog_install

    First installation

    From benny.kra at googlemail.com Wed Nov 9 12:16:11 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 09 Nov 2011 18:16:11 -0000 Subject: [llvm-commits] [llvm] r144194 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20111109181611.683FA1BE002@llvm.org> Author: d0k Date: Wed Nov 9 12:16:11 2011 New Revision: 144194 URL: http://llvm.org/viewvc/llvm-project?rev=144194&view=rev Log: Add comments. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=144194&r1=144193&r2=144194&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Nov 9 12:16:11 2011 @@ -1901,6 +1901,7 @@ Asm->EmitInt32(Entity->getOffset()); if (Asm->isVerbose()) Asm->OutStreamer.AddComment("External Name"); + // Emit the name with a terminating null byte. Asm->OutStreamer.EmitBytes(StringRef(Name, GI->getKeyLength()+1), 0); } @@ -1936,7 +1937,7 @@ // Emit a label for reference from debug information entries. Asm->OutStreamer.EmitLabel(Entries[i].second->getValue().first); - // Emit the string itself. + // Emit the string itself with a terminating null byte. Asm->OutStreamer.EmitBytes(StringRef(Entries[i].second->getKeyData(), Entries[i].second->getKeyLength()+1), 0/*addrspace*/); From daniel at zuster.org Wed Nov 9 12:48:22 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 09 Nov 2011 18:48:22 -0000 Subject: [llvm-commits] [llvm] r144197 - /llvm/trunk/Makefile.rules Message-ID: <20111109184822.8FA061BE001@llvm.org> Author: ddunbar Date: Wed Nov 9 12:48:22 2011 New Revision: 144197 URL: http://llvm.org/viewvc/llvm-project?rev=144197&view=rev Log: build/Make: Fix some missing dependencies on the llvm-build generation step. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=144197&r1=144196&r2=144197&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Wed Nov 9 12:48:22 2011 @@ -86,12 +86,18 @@ # # Note that this target gets its real dependencies generated for us by # llvm-build. -$(LLVMBuildMakeFrag): +# +# We include a dependency on this Makefile to ensure that changes to the +# generation command get picked up. +$(LLVMBuildMakeFrag): $(PROJ_SRC_ROOT)/Makefile.rules $(Echo) Constructing LLVMBuild project information. $(Verb) $(LLVMBuildTool) \ --write-library-table $(LLVMConfigLibraryDependenciesInc) \ --write-make-fragment $(LLVMBuildMakeFrag) +# For completeness, let Make know how the extra files are generated. +$(LLVMConfigLibraryDependenciesInc): $(LLVMBuildMakeFrag) + # Include the generated Makefile fragment. # # We currently only include the dependencies for the fragment itself if we are From echristo at apple.com Wed Nov 9 12:53:37 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 09 Nov 2011 18:53:37 -0000 Subject: [llvm-commits] [llvm] r144198 - /llvm/trunk/include/llvm/Analysis/DebugInfo.h Message-ID: <20111109185337.737CF1BE001@llvm.org> Author: echristo Date: Wed Nov 9 12:53:37 2011 New Revision: 144198 URL: http://llvm.org/viewvc/llvm-project?rev=144198&view=rev Log: Fix typo. Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=144198&r1=144197&r2=144198&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Wed Nov 9 12:53:37 2011 @@ -816,7 +816,7 @@ /// addGlobalVariable - Add global variable into GVs. bool addGlobalVariable(DIGlobalVariable DIG); - // addSubprogram - Add subprgoram into SPs. + // addSubprogram - Add subprogram into SPs. bool addSubprogram(DISubprogram SP); /// addType - Add type into Tys. From pdox at google.com Wed Nov 9 13:11:23 2011 From: pdox at google.com (David Meyer) Date: Wed, 9 Nov 2011 11:11:23 -0800 Subject: [llvm-commits] [llvm] r144188 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll In-Reply-To: <20111109142048.965491BE001@llvm.org> References: <20111109142048.965491BE001@llvm.org> Message-ID: :( Without this fix, our integration bot asserts while doing bootstrap build (compiling llvm again with clang). From daniel at zuster.org Wed Nov 9 13:14:51 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 09 Nov 2011 19:14:51 -0000 Subject: [llvm-commits] [llvm] r144201 - /llvm/trunk/tools/llvm-config-2/llvm-config.cpp Message-ID: <20111109191451.76CA01BE001@llvm.org> Author: ddunbar Date: Wed Nov 9 13:14:51 2011 New Revision: 144201 URL: http://llvm.org/viewvc/llvm-project?rev=144201&view=rev Log: llvm-config-2: Switch to using real library dependency table. - Also, fix a refacto that left extra "all" component in list (this is now defined in the groups explicitly) - Reapply of r143879 now that Make should see needed deps. Modified: llvm/trunk/tools/llvm-config-2/llvm-config.cpp Modified: llvm/trunk/tools/llvm-config-2/llvm-config.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config-2/llvm-config.cpp?rev=144201&r1=144200&r2=144201&view=diff ============================================================================== --- llvm/trunk/tools/llvm-config-2/llvm-config.cpp (original) +++ llvm/trunk/tools/llvm-config-2/llvm-config.cpp Wed Nov 9 13:14:51 2011 @@ -43,15 +43,7 @@ // // Not all components define a library, we also use "library groups" as a way to // create entries for pseudo groups like x86 or all-targets. -// -// FIXME: Include real component table. -struct AvailableComponent { - const char *Name; - const char *Library; - const char *RequiredLibraries[1]; -} AvailableComponents[1] = { - { "all", 0, { } } -}; +#include "LibraryDependencies.inc" /// \brief Traverse a single component adding to the topological ordering in /// \arg RequiredLibs. @@ -264,7 +256,6 @@ } else if (Arg == "--libfiles") { PrintLibFiles = true; } else if (Arg == "--components") { - OS << "all"; for (unsigned j = 0; j != array_lengthof(AvailableComponents); ++j) { OS << ' '; OS << AvailableComponents[j].Name; From daniel at zuster.org Wed Nov 9 13:23:15 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 09 Nov 2011 19:23:15 -0000 Subject: [llvm-commits] [llvm] r144202 - /llvm/trunk/tools/llvm-config/llvm-config.in.in Message-ID: <20111109192315.E50531BE001@llvm.org> Author: ddunbar Date: Wed Nov 9 13:23:15 2011 New Revision: 144202 URL: http://llvm.org/viewvc/llvm-project?rev=144202&view=rev Log: llvm-config: Drop 'backend' pseudo-component. We don't support/qualify the CBE enough to have this be useful. Modified: llvm/trunk/tools/llvm-config/llvm-config.in.in Modified: llvm/trunk/tools/llvm-config/llvm-config.in.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/llvm-config.in.in?rev=144202&r1=144201&r2=144202&view=diff ============================================================================== --- llvm/trunk/tools/llvm-config/llvm-config.in.in (original) +++ llvm/trunk/tools/llvm-config/llvm-config.in.in Wed Nov 9 13:23:15 2011 @@ -197,7 +197,6 @@ --build-mode Print build mode of LLVM tree (e.g. Debug or Release). Typical components: all All LLVM libraries (default). - backend Either a native backend or the C backend. engine Either a native JIT or a bitcode interpreter. __EOD__ exit(1); @@ -344,7 +343,6 @@ # Add virtual entries. $NAME_MAP{'native'} = have_native_backend() ? [$ARCH] : []; $NAME_MAP{'nativecodegen'} = have_native_backend() ? [$ARCH.'codegen'] : []; - $NAME_MAP{'backend'} = have_native_backend() ? ['native'] : ['cbackend']; $NAME_MAP{'engine'} = find_best_engine; $NAME_MAP{'all-targets'} = \@all_targets; $NAME_MAP{'all'} = [name_map_entries]; # Must be last. From isanbard at gmail.com Wed Nov 9 13:33:57 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 09 Nov 2011 19:33:57 -0000 Subject: [llvm-commits] [llvm] r144204 - /llvm/trunk/docs/LangRef.html Message-ID: <20111109193357.128E31BE001@llvm.org> Author: void Date: Wed Nov 9 13:33:56 2011 New Revision: 144204 URL: http://llvm.org/viewvc/llvm-project?rev=144204&view=rev Log: Reformat the quote and tag the math stuff with tags. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=144204&r1=144203&r2=144204&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Wed Nov 9 13:33:56 2011 @@ -2976,12 +2976,15 @@ point type. It expresses the maximum relative error of the result of that instruction, in ULPs. ULP is defined as follows:

    -

    -If x is a real number that lies between two finite consecutive floating-point -numbers a and b, without being equal to one of them, then ulp(x) = |b - a|, -otherwise ulp(x) is the distance between the two non-equal finite -floating-point numbers nearest x. Moreover, ulp(NaN) is NaN. -

    +
    + +

    If x is a real number that lies between two finite consecutive + floating-point numbers a and b, without being equal to one + of them, then ulp(x) = |b - a|, otherwise ulp(x) is the + distance between the two non-equal finite floating-point numbers nearest + x. Moreover, ulp(NaN) is NaN.

    + +

    The maximum relative error may be any rational number. The metadata node shall consist of a pair of unsigned integers respectively representing From mcrosier at apple.com Wed Nov 9 14:06:13 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 09 Nov 2011 20:06:13 -0000 Subject: [llvm-commits] [llvm] r144209 - /llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll Message-ID: <20111109200613.C00701BE001@llvm.org> Author: mcrosier Date: Wed Nov 9 14:06:13 2011 New Revision: 144209 URL: http://llvm.org/viewvc/llvm-project?rev=144209&view=rev Log: Use REs to remove dependencies on the register allocation order. Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll?rev=144209&r1=144208&r2=144209&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll Wed Nov 9 14:06:13 2011 @@ -6,8 +6,8 @@ ; ARM: t1a ; THUMB: t1a %cmp = fcmp oeq float %a, 0.000000e+00 -; ARM: vcmpe.f32 s0, #0 -; THUMB: vcmpe.f32 s0, #0 +; ARM: vcmpe.f32 s{{[0-9]+}}, #0 +; THUMB: vcmpe.f32 s{{[0-9]+}}, #0 br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -27,9 +27,9 @@ ; THUMB: t1b %cmp = fcmp oeq float %a, -0.000000e+00 ; ARM: vldr.32 -; ARM: vcmpe.f32 s0, s1 +; ARM: vcmpe.f32 s{{[0-9]+}}, s{{[0-9]+}} ; THUMB: vldr.32 -; THUMB: vcmpe.f32 s0, s1 +; THUMB: vcmpe.f32 s{{[0-9]+}}, s{{[0-9]+}} br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -45,8 +45,8 @@ ; ARM: t2a ; THUMB: t2a %cmp = fcmp oeq double %a, 0.000000e+00 -; ARM: vcmpe.f64 d16, #0 -; THUMB: vcmpe.f64 d16, #0 +; ARM: vcmpe.f64 d{{[0-9]+}}, #0 +; THUMB: vcmpe.f64 d{{[0-9]+}}, #0 br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -64,9 +64,9 @@ ; THUMB: t2b %cmp = fcmp oeq double %a, -0.000000e+00 ; ARM: vldr.64 -; ARM: vcmpe.f64 d16, d17 +; ARM: vcmpe.f64 d{{[0-9]+}}, d{{[0-9]+}} ; THUMB: vldr.64 -; THUMB: vcmpe.f64 d16, d17 +; THUMB: vcmpe.f64 d{{[0-9]+}}, d{{[0-9]+}} br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -82,8 +82,8 @@ ; ARM: t4 ; THUMB: t4 %cmp = icmp eq i8 %a, -1 -; ARM: cmn r0, #1 -; THUMB: cmn.w r0, #1 +; ARM: cmn r{{[0-9]}}, #1 +; THUMB: cmn.w r{{[0-9]}}, #1 br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -99,8 +99,8 @@ ; ARM: t5 ; THUMB: t5 %cmp = icmp eq i8 %a, 1 -; ARM: cmp r0, #1 -; THUMB: cmp r0, #1 +; ARM: cmp r{{[0-9]}}, #1 +; THUMB: cmp r{{[0-9]}}, #1 br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -116,8 +116,8 @@ ; ARM: t6 ; THUMB: t6 %cmp = icmp eq i16 %a, -1 -; ARM: cmn r0, #1 -; THUMB: cmn.w r0, #1 +; ARM: cmn r{{[0-9]}}, #1 +; THUMB: cmn.w r{{[0-9]}}, #1 br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -133,8 +133,8 @@ ; ARM: t7 ; THUMB: t7 %cmp = icmp eq i16 %a, 1 -; ARM: cmp r0, #1 -; THUMB: cmp r0, #1 +; ARM: cmp r{{[0-9]}}, #1 +; THUMB: cmp r{{[0-9]}}, #1 br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -150,8 +150,8 @@ ; ARM: t8 ; THUMB: t8 %cmp = icmp eq i32 %a, -1 -; ARM: cmn r0, #1 -; THUMB: cmn.w r0, #1 +; ARM: cmn r{{[0-9]}}, #1 +; THUMB: cmn.w r{{[0-9]}}, #1 br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -167,8 +167,8 @@ ; ARM: t9 ; THUMB: t9 %cmp = icmp eq i32 %a, 1 -; ARM: cmp r0, #1 -; THUMB: cmp r0, #1 +; ARM: cmp r{{[0-9]}}, #1 +; THUMB: cmp r{{[0-9]}}, #1 br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -184,8 +184,8 @@ ; ARM: t10 ; THUMB: t10 %cmp = icmp eq i32 %a, 384 -; ARM: cmp r0, #384 -; THUMB: cmp.w r0, #384 +; ARM: cmp r{{[0-9]}}, #384 +; THUMB: cmp.w r{{[0-9]}}, #384 br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -201,8 +201,8 @@ ; ARM: t11 ; THUMB: t11 %cmp = icmp eq i32 %a, 4096 -; ARM: cmp r0, #4096 -; THUMB: cmp.w r0, #4096 +; ARM: cmp r{{[0-9]}}, #4096 +; THUMB: cmp.w r{{[0-9]}}, #4096 br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry From dpatel at apple.com Wed Nov 9 15:11:02 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 09 Nov 2011 21:11:02 -0000 Subject: [llvm-commits] [llvm] r144211 - in /llvm/trunk/lib/Target: PowerPC/PPCAsmPrinter.cpp X86/X86AsmPrinter.h Message-ID: <20111109211102.B940F1BE001@llvm.org> Author: dpatel Date: Wed Nov 9 15:11:02 2011 New Revision: 144211 URL: http://llvm.org/viewvc/llvm-project?rev=144211&view=rev Log: Remove unnecessary include. Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp llvm/trunk/lib/Target/X86/X86AsmPrinter.h Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=144211&r1=144210&r2=144211&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Wed Nov 9 15:11:02 2011 @@ -50,7 +50,6 @@ #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/ADT/StringSet.h" #include "llvm/ADT/SmallString.h" #include "InstPrinter/PPCInstPrinter.h" using namespace llvm; Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.h?rev=144211&r1=144210&r2=144211&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmPrinter.h (original) +++ llvm/trunk/lib/Target/X86/X86AsmPrinter.h Wed Nov 9 15:11:02 2011 @@ -17,7 +17,6 @@ #include "X86.h" #include "X86MachineFunctionInfo.h" #include "X86TargetMachine.h" -#include "llvm/ADT/StringSet.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/ValueTypes.h" From ahatanaka at mips.com Wed Nov 9 15:19:22 2011 From: ahatanaka at mips.com (Hatanaka, Akira) Date: Wed, 9 Nov 2011 21:19:22 +0000 Subject: [llvm-commits] [PATCH][Review request] IEEE quad software emulation library call Message-ID: <95DD8BA8AA50B14BBFB86A1D541FA3809EAB2E46@exchdb03.mips.com> This patch adds code needed for expanding basic IEEE quad operations (add, sub, etc.) into software emulation library calls. -------------- next part -------------- An HTML attachment was scrubbed... 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Name: f128.patch Type: text/x-patch Size: 38391 bytes Desc: f128.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/ab949fe7/attachment.bin From nadav.rotem at intel.com Wed Nov 9 15:22:13 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Wed, 09 Nov 2011 21:22:13 -0000 Subject: [llvm-commits] [llvm] r144212 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx2-logic.ll Message-ID: <20111109212214.1BF721BE001@llvm.org> Author: nadav Date: Wed Nov 9 15:22:13 2011 New Revision: 144212 URL: http://llvm.org/viewvc/llvm-project?rev=144212&view=rev Log: AVX2: Add patterns for variable shift operations Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx2-logic.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144212&r1=144211&r2=144212&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Nov 9 15:22:13 2011 @@ -1052,6 +1052,18 @@ setOperationAction(ISD::MUL, MVT::v16i16, Legal); setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); + + setOperationAction(ISD::SHL, MVT::v4i32, Legal); + setOperationAction(ISD::SHL, MVT::v2i64, Legal); + setOperationAction(ISD::SRL, MVT::v4i32, Legal); + setOperationAction(ISD::SRL, MVT::v2i64, Legal); + setOperationAction(ISD::SRA, MVT::v4i32, Legal); + + setOperationAction(ISD::SHL, MVT::v8i32, Legal); + setOperationAction(ISD::SHL, MVT::v4i64, Legal); + setOperationAction(ISD::SRL, MVT::v8i32, Legal); + setOperationAction(ISD::SRL, MVT::v4i64, Legal); + setOperationAction(ISD::SRA, MVT::v8i32, Legal); // Don't lower v32i8 because there is no 128-bit byte mul } else { setOperationAction(ISD::ADD, MVT::v4i64, Custom); Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144212&r1=144211&r2=144212&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Nov 9 15:22:13 2011 @@ -7689,3 +7689,31 @@ VEX_W; defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", memopv4i32, memopv8i32, int_x86_avx2_psrav_d, int_x86_avx2_psrav_d_256>; + + +let Predicates = [HasAVX2] in { + def : Pat<(v4i32 (shl (v4i32 VR128:$src1), (v4i32 VR128:$src2))), + (VPSLLVDrr VR128:$src1, VR128:$src2)>; + def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (v2i64 VR128:$src2))), + (VPSLLVQrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (srl (v4i32 VR128:$src1), (v4i32 VR128:$src2))), + (VPSRLVDrr VR128:$src1, VR128:$src2)>; + def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (v2i64 VR128:$src2))), + (VPSRLVQrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (sra (v4i32 VR128:$src1), (v4i32 VR128:$src2))), + (VPSRAVDrr VR128:$src1, VR128:$src2)>; + + def : Pat<(v8i32 (shl (v8i32 VR256:$src1), (v8i32 VR256:$src2))), + (VPSLLVDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (v4i64 VR256:$src2))), + (VPSLLVQYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (srl (v8i32 VR256:$src1), (v8i32 VR256:$src2))), + (VPSRLVDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (v4i64 VR256:$src2))), + (VPSRLVQYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (sra (v8i32 VR256:$src1), (v8i32 VR256:$src2))), + (VPSRAVDYrr VR256:$src1, VR256:$src2)>; +} + + + Modified: llvm/trunk/test/CodeGen/X86/avx2-logic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-logic.ll?rev=144212&r1=144211&r2=144212&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx2-logic.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx2-logic.ll Wed Nov 9 15:22:13 2011 @@ -45,8 +45,6 @@ ret <4 x i64> %x } - - ; CHECK: vpblendvb ; CHECK: vpblendvb %ymm ; CHECK: ret @@ -55,3 +53,76 @@ %min = select <32 x i1> %min_is_x, <32 x i8> %x, <32 x i8> %y ret <32 x i8> %min } + + +; CHECK: variable_shl0 +; CHECK: psllvd +; CHECK: ret +define <4 x i32> @variable_shl0(<4 x i32> %x, <4 x i32> %y) { + %k = shl <4 x i32> %x, %y + ret <4 x i32> %k +} +; CHECK: variable_shl1 +; CHECK: psllvd +; CHECK: ret +define <8 x i32> @variable_shl1(<8 x i32> %x, <8 x i32> %y) { + %k = shl <8 x i32> %x, %y + ret <8 x i32> %k +} +; CHECK: variable_shl2 +; CHECK: psllvq +; CHECK: ret +define <2 x i64> @variable_shl2(<2 x i64> %x, <2 x i64> %y) { + %k = shl <2 x i64> %x, %y + ret <2 x i64> %k +} +; CHECK: variable_shl3 +; CHECK: psllvq +; CHECK: ret +define <4 x i64> @variable_shl3(<4 x i64> %x, <4 x i64> %y) { + %k = shl <4 x i64> %x, %y + ret <4 x i64> %k +} +; CHECK: variable_srl0 +; CHECK: psrlvd +; CHECK: ret +define <4 x i32> @variable_srl0(<4 x i32> %x, <4 x i32> %y) { + %k = lshr <4 x i32> %x, %y + ret <4 x i32> %k +} +; CHECK: variable_srl1 +; CHECK: psrlvd +; CHECK: ret +define <8 x i32> @variable_srl1(<8 x i32> %x, <8 x i32> %y) { + %k = lshr <8 x i32> %x, %y + ret <8 x i32> %k +} +; CHECK: variable_srl2 +; CHECK: psrlvq +; CHECK: ret +define <2 x i64> @variable_srl2(<2 x i64> %x, <2 x i64> %y) { + %k = lshr <2 x i64> %x, %y + ret <2 x i64> %k +} +; CHECK: variable_srl3 +; CHECK: psrlvq +; CHECK: ret +define <4 x i64> @variable_srl3(<4 x i64> %x, <4 x i64> %y) { + %k = lshr <4 x i64> %x, %y + ret <4 x i64> %k +} + +; CHECK: variable_sra0 +; CHECK: psravd +; CHECK: ret +define <4 x i32> @variable_sra0(<4 x i32> %x, <4 x i32> %y) { + %k = ashr <4 x i32> %x, %y + ret <4 x i32> %k +} +; CHECK: variable_sra1 +; CHECK: psravd +; CHECK: ret +define <8 x i32> @variable_sra1(<8 x i32> %x, <8 x i32> %y) { + %k = ashr <8 x i32> %x, %y + ret <8 x i32> %k +} From mcrosier at apple.com Wed Nov 9 15:30:12 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 09 Nov 2011 21:30:12 -0000 Subject: [llvm-commits] [llvm] r144213 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20111109213012.74FFA1BE001@llvm.org> Author: mcrosier Date: Wed Nov 9 15:30:12 2011 New Revision: 144213 URL: http://llvm.org/viewvc/llvm-project?rev=144213&view=rev Log: The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12. rdar://10418009 Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144213&r1=144212&r2=144213&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Nov 9 15:30:12 2011 @@ -846,9 +846,17 @@ switch (VT.getSimpleVT().SimpleTy) { default: assert(false && "Unhandled load/store type!"); + case MVT::i16: + if (isThumb2) + // Integer loads/stores handle 12-bit offsets. + needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset); + else + // ARM i16 integer loads/stores handle +/-imm8 offsets. + if (Addr.Offset > 255 || Addr.Offset < -255) + needsLowering = true; + break; case MVT::i1: case MVT::i8: - case MVT::i16: case MVT::i32: // Integer loads/stores handle 12-bit offsets. needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset); @@ -932,14 +940,14 @@ switch (VT.getSimpleVT().SimpleTy) { // This is mostly going to be Neon/vector support. default: return false; - case MVT::i16: - Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH; - RC = ARM::GPRRegisterClass; - break; case MVT::i8: Opc = isThumb2 ? ARM::t2LDRBi12 : ARM::LDRBi12; RC = ARM::GPRRegisterClass; break; + case MVT::i16: + Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH; + RC = ARM::GPRRegisterClass; + break; case MVT::i32: Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; RC = ARM::GPRRegisterClass; From eli.friedman at gmail.com Wed Nov 9 15:42:28 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 9 Nov 2011 13:42:28 -0800 Subject: [llvm-commits] [PATCH][Review request] IEEE quad software emulation library call In-Reply-To: <95DD8BA8AA50B14BBFB86A1D541FA3809EAB2E46@exchdb03.mips.com> References: <95DD8BA8AA50B14BBFB86A1D541FA3809EAB2E46@exchdb03.mips.com> Message-ID: On Wed, Nov 9, 2011 at 1:19 PM, Hatanaka, Akira wrote: > This patch adds code needed for expanding basic IEEE quad operations (add, > sub, etc.) into software emulation library calls. - RTLIB::FLOOR_F80,RTLIB::FLOOR_PPCF128), + RTLIB::FLOOR_F80,RTLIB::FLOOR_F128, + RTLIB::FLOOR_PPCF128), Whitespace, here and a couple other places nearby. + // f128 type is really two f64's. + if (!isTypeLegal(MVT::f128)) { + NumRegistersForVT[MVT::f128] = 2*NumRegistersForVT[MVT::f64]; + RegisterTypeForVT[MVT::f128] = MVT::f64; + TransformToType[MVT::f128] = MVT::f64; + ValueTypeActions.setTypeAction(MVT::f128, TypeExpandFloat); + } This looks wrong; I'm pretty sure we should be softening these (to i128), not splitting into two f64's. What else, if anything, is actually needed to make an f128 add work? -Eli From baldrick at free.fr Wed Nov 9 15:53:51 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 09 Nov 2011 22:53:51 +0100 Subject: [llvm-commits] [llvm] r144188 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll In-Reply-To: References: <20111109142048.965491BE001@llvm.org> Message-ID: <4EBAF66F.7030708@free.fr> On 09/11/11 20:11, David Meyer wrote: > :( > > Without this fix, our integration bot asserts while doing bootstrap > build (compiling llvm again with clang). I understand that Dan is fixing something. Unfortunately it breaks something else, and the LLVM rule is that changes should be reverted in that case. Hopefully Dan will identify the problem and reapply with a fix. Ciao, Duncan. From evan.cheng at apple.com Wed Nov 9 16:02:11 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 09 Nov 2011 14:02:11 -0800 Subject: [llvm-commits] [llvm] r144188 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll In-Reply-To: <4EBAF66F.7030708@free.fr> References: <20111109142048.965491BE001@llvm.org> <4EBAF66F.7030708@free.fr> Message-ID: <04A23D00-737D-4AFD-9D97-3958A728AFA2@apple.com> Are you sure this is the patch that caused the problem? It's disabling an optimization. Unless the patch is somehow introducing non-determinism, I find it hard to believe it's the problem. Evan On Nov 9, 2011, at 1:53 PM, Duncan Sands wrote: > On 09/11/11 20:11, David Meyer wrote: >> :( >> >> Without this fix, our integration bot asserts while doing bootstrap >> build (compiling llvm again with clang). > > I understand that Dan is fixing something. Unfortunately it breaks > something else, and the LLVM rule is that changes should be reverted > in that case. Hopefully Dan will identify the problem and reapply > with a fix. > > Ciao, Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Wed Nov 9 16:07:32 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 09 Nov 2011 23:07:32 +0100 Subject: [llvm-commits] [llvm] r144188 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll In-Reply-To: <04A23D00-737D-4AFD-9D97-3958A728AFA2@apple.com> References: <20111109142048.965491BE001@llvm.org> <4EBAF66F.7030708@free.fr> <04A23D00-737D-4AFD-9D97-3958A728AFA2@apple.com> Message-ID: <4EBAF9A4.4080901@free.fr> Hi Evan, > Are you sure this is the patch that caused the problem? It's disabling an optimization. Unless the patch is somehow introducing non-determinism, I find it hard to believe it's the problem. I agree it seems pretty unlikely, yet it seems to be the one: the buildbot recovered on this build: http://lab.llvm.org:8011/builders/dragonegg-i386-linux/builds/358 The commit list contains one commit: the reversion of Dan's patch. I speculatively reverted Dan's patch because while it seemed unlikely to be the culprit, I thought it more likely than the execution domain changes (since the builder targets i386) or Bill's compact unwind info changes (as the difference in the object files is due to register allocator changes and maybe blocks being moved around) which were the other possible culprits. Ciao, Duncan. > > Evan > > On Nov 9, 2011, at 1:53 PM, Duncan Sands wrote: > >> On 09/11/11 20:11, David Meyer wrote: >>> :( >>> >>> Without this fix, our integration bot asserts while doing bootstrap >>> build (compiling llvm again with clang). >> >> I understand that Dan is fixing something. Unfortunately it breaks >> something else, and the LLVM rule is that changes should be reverted >> in that case. Hopefully Dan will identify the problem and reapply >> with a fix. >> >> Ciao, Duncan. >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From ahatanaka at mips.com Wed Nov 9 16:16:44 2011 From: ahatanaka at mips.com (Hatanaka, Akira) Date: Wed, 9 Nov 2011 22:16:44 +0000 Subject: [llvm-commits] [PATCH][Review request] IEEE quad software emulation library call In-Reply-To: References: <95DD8BA8AA50B14BBFB86A1D541FA3809EAB2E46@exchdb03.mips.com>, Message-ID: <95DD8BA8AA50B14BBFB86A1D541FA3809EAB2E71@exchdb03.mips.com> I am not sure if I understand your first comment. Is it the trailing whitespace or incorrect indentation? When I open my patch in an editor, it looks like what you see in the following link: http://comments.gmane.org/gmane.comp.compilers.llvm.cvs/102510 I didn't find any tabs either. As for your second comment, I was copying what gcc-mips64 was doing. When I compile this code with gcc-mips64, typedef long double LD; LD g0, g1, g2; LD f0() { return g0 + g1; } I get this code: ld $2,%got_disp(g0)($28) ld $25,%call16(__addtf3)($28) ldc1 $f12,0($2) sd $31,8($sp) ldc1 $f13,8($2) ld $2,%got_disp(g1)($28) ldc1 $f14,0($2) .reloc 1f,R_MIPS_JALR,__addtf3 1: jalr $25 ldc1 $f15,8($2) So g0 is passed in (f12, f13) and g1 is passed in (f14, f15). These are all FP registers. Is the choice of register types platform dependent? llc emits the code I expect to see after applying this patch for add, sub, mul and div. I haven't made the changes needed for type conversions or fp constant operations. ________________________________________ From: Eli Friedman [eli.friedman at gmail.com] Sent: Wednesday, November 09, 2011 1:42 PM To: Hatanaka, Akira Cc: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [PATCH][Review request] IEEE quad software emulation library call On Wed, Nov 9, 2011 at 1:19 PM, Hatanaka, Akira wrote: > This patch adds code needed for expanding basic IEEE quad operations (add, > sub, etc.) into software emulation library calls. - RTLIB::FLOOR_F80,RTLIB::FLOOR_PPCF128), + RTLIB::FLOOR_F80,RTLIB::FLOOR_F128, + RTLIB::FLOOR_PPCF128), Whitespace, here and a couple other places nearby. + // f128 type is really two f64's. + if (!isTypeLegal(MVT::f128)) { + NumRegistersForVT[MVT::f128] = 2*NumRegistersForVT[MVT::f64]; + RegisterTypeForVT[MVT::f128] = MVT::f64; + TransformToType[MVT::f128] = MVT::f64; + ValueTypeActions.setTypeAction(MVT::f128, TypeExpandFloat); + } This looks wrong; I'm pretty sure we should be softening these (to i128), not splitting into two f64's. What else, if anything, is actually needed to make an f128 add work? -Eli From eli.friedman at gmail.com Wed Nov 9 16:25:13 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 09 Nov 2011 22:25:13 -0000 Subject: [llvm-commits] [llvm] r144216 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll Message-ID: <20111109222513.3B9EA1BE001@llvm.org> Author: efriedma Date: Wed Nov 9 16:25:12 2011 New Revision: 144216 URL: http://llvm.org/viewvc/llvm-project?rev=144216&view=rev Log: Add check so we don't try to perform an impossible transformation. Fixes issue from PR11319. Added: llvm/trunk/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=144216&r1=144215&r2=144216&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Nov 9 16:25:12 2011 @@ -1783,7 +1783,8 @@ case ISD::BITCAST: // If this is an FP->Int bitcast and if the sign bit is the only // thing demanded, turn this into a FGETSIGN. - if (!Op.getOperand(0).getValueType().isVector() && + if (!Op.getValueType().isVector() && + !Op.getOperand(0).getValueType().isVector() && NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && Op.getOperand(0).getValueType().isFloatingPoint()) { bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); Added: llvm/trunk/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll?rev=144216&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll Wed Nov 9 16:25:12 2011 @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; PR11319 + + at src1_v2i16 = global <2 x i16> + at res_v2i16 = global <2 x i16> + +declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind + +define void @test_neon_call_return_v2i16() { +; CHECK: test_neon_call_return_v2i16: + %1 = load <2 x i16>* @src1_v2i16 + %2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind + store <2 x i16> %2, <2 x i16>* @res_v2i16 + ret void +} From grosser at fim.uni-passau.de Wed Nov 9 16:34:19 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:34:19 -0000 Subject: [llvm-commits] [polly] r144220 - in /polly/trunk: lib/Analysis/TempScopInfo.cpp test/ScopInfo/bad_loop_1.ll test/ScopInfo/nest_loop_0.ll test/ScopInfo/static_known_0.ll Message-ID: <20111109223419.1234D1BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:34:18 2011 New Revision: 144220 URL: http://llvm.org/viewvc/llvm-project?rev=144220&view=rev Log: TempScopInfo: Remove unneeded construction of SCEVAffFunc Removed: polly/trunk/test/ScopInfo/bad_loop_1.ll polly/trunk/test/ScopInfo/nest_loop_0.ll polly/trunk/test/ScopInfo/static_known_0.ll Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144220&r1=144219&r2=144220&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Wed Nov 9 16:34:18 2011 @@ -283,13 +283,6 @@ const SCEV *BackedgeTakenCount = SE->getBackedgeTakenCount(L); LoopBounds[L] = BackedgeTakenCount; - // FIXME: Do not build TempSCEVAffFunc. It is not needed anywhere else - // and only build to register the parameters in this SCoP. We should - // move this functionality to the ScopDetection. - SCEVAffFunc Temp(SCEVAffFunc::Eq, BackedgeTakenCount); - buildAffineFunction(BackedgeTakenCount, Temp, Scop.getMaxRegion(), - Scop.getParamSet()); - Loop *OL = R.outermostLoopInRegion(L); unsigned LoopDepth = L->getLoopDepth() - OL->getLoopDepth() + 1; Removed: polly/trunk/test/ScopInfo/bad_loop_1.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/bad_loop_1.ll?rev=144219&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/bad_loop_1.ll (original) +++ polly/trunk/test/ScopInfo/bad_loop_1.ll (removed) @@ -1,56 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s | FileCheck %s -check-prefix=INDVAR -; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s | FileCheck %s - -;void f(long a[][128], long N, long M) { -; long i, j; -; for (j = 0; j < rnd(); ++j) -; for (i = 0; i < N; ++i) -; a[i][j] = 0; -;} - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define void @f([128 x i64]* nocapture %a, i64 %N, i64 %M) nounwind { -entry: - %0 = tail call i64 (...)* @rnd() nounwind ; [#uses=1] - %1 = icmp sgt i64 %0, 0 ; [#uses=1] - br i1 %1, label %bb.nph8, label %return - -bb.nph8: ; preds = %entry - %2 = icmp sgt i64 %N, 0 ; [#uses=1] - br i1 %2, label %bb2.preheader.us, label %bb2.preheader - -bb2.preheader.us: ; preds = %bb2.bb3_crit_edge.us, %bb.nph8 - %3 = phi i64 [ 0, %bb.nph8 ], [ %tmp, %bb2.bb3_crit_edge.us ] ; [#uses=2] - %tmp = add i64 %3, 1 ; [#uses=2] - br label %bb1.us - -bb1.us: ; preds = %bb1.us, %bb2.preheader.us - %i.06.us = phi i64 [ 0, %bb2.preheader.us ], [ %4, %bb1.us ] ; [#uses=2] - %scevgep = getelementptr [128 x i64]* %a, i64 %i.06.us, i64 %3 ; [#uses=1] - store i64 0, i64* %scevgep, align 8 - %4 = add nsw i64 %i.06.us, 1 ; [#uses=2] - %exitcond = icmp eq i64 %4, %N ; [#uses=1] - br i1 %exitcond, label %bb2.bb3_crit_edge.us, label %bb1.us - -bb2.bb3_crit_edge.us: ; preds = %bb1.us - %5 = tail call i64 (...)* @rnd() nounwind ; [#uses=1] - %6 = icmp sgt i64 %5, %tmp ; [#uses=1] - br i1 %6, label %bb2.preheader.us, label %return - -bb2.preheader: ; preds = %bb2.preheader, %bb.nph8 - %j.07 = phi i64 [ %tmp9, %bb2.preheader ], [ 0, %bb.nph8 ] ; [#uses=1] - %tmp9 = add i64 %j.07, 1 ; [#uses=2] - %7 = tail call i64 (...)* @rnd() nounwind ; [#uses=1] - %8 = icmp sgt i64 %7, %tmp9 ; [#uses=1] - br i1 %8, label %bb2.preheader, label %return - -return: ; preds = %bb2.preheader, %bb2.bb3_crit_edge.us, %entry - ret void -} - -declare i64 @rnd(...) - -; INDVAR: Scop: bb1.us => bb2.bb3_crit_edge.us Parameters: (%N, {0,+,1}<%bb2.preheader.us>, ), Max Loop Depth: 1 -; CHECK: Scop: bb1.us => bb2.bb3_crit_edge.us Parameters: (%N, {0,+,1}<%bb2.preheader.us>, ), Max Loop Depth: 1 Removed: polly/trunk/test/ScopInfo/nest_loop_0.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/nest_loop_0.ll?rev=144219&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/nest_loop_0.ll (original) +++ polly/trunk/test/ScopInfo/nest_loop_0.ll (removed) @@ -1,42 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s | FileCheck %s - -;void f(long a[][128], long N, long M) { -; long i, j; -; for (j = 0; j < M; ++j) -; for (i = 0; i < N; ++i) -; ... -;} - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define void @f([128 x i64]* nocapture %a, i64 %N, i64 %M) nounwind { -entry: - %0 = icmp sgt i64 %M, 0 ; [#uses=1] - %1 = icmp sgt i64 %N, 0 ; [#uses=1] - %or.cond = and i1 %0, %1 ; [#uses=1] - br i1 %or.cond, label %bb2.preheader, label %return - -bb1: ; preds = %bb2.preheader, %bb1 - %i.06 = phi i64 [ 0, %bb2.preheader ], [ %2, %bb1 ] ; [#uses=3] - %scevgep = getelementptr [128 x i64]* %a, i64 %i.06, i64 %4 ; [#uses=1] - %tmp = add i64 %i.06, %N ; [#uses=1] - store i64 %tmp, i64* %scevgep, align 8 - %2 = add nsw i64 %i.06, 1 ; [#uses=2] - %exitcond = icmp eq i64 %2, %N ; [#uses=1] - br i1 %exitcond, label %bb3, label %bb1 - -bb3: ; preds = %bb1 - %3 = add i64 %4, 1 ; [#uses=2] - %exitcond9 = icmp eq i64 %3, %M ; [#uses=1] - br i1 %exitcond9, label %return, label %bb2.preheader - -bb2.preheader: ; preds = %bb3, %entry - %4 = phi i64 [ %3, %bb3 ], [ 0, %entry ] ; [#uses=2] - br label %bb1 - -return: ; preds = %bb3, %entry - ret void -} - -; CHECK: Scop: bb2.preheader => return.single_exit Parameters: (%M, %N, ), Max Loop Depth: 2 Removed: polly/trunk/test/ScopInfo/static_known_0.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/static_known_0.ll?rev=144219&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/static_known_0.ll (original) +++ polly/trunk/test/ScopInfo/static_known_0.ll (removed) @@ -1,39 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s | FileCheck %s - - -;void f(long a[], long N) { -; long M = rnd(); -; long i; - -; for (i = 0; i < M; ++i) -; a[i] = i; - -; a[N] = 0; -;} - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define void @f(i64* nocapture %a, i64 %N) nounwind { -entry: - %0 = tail call i64 (...)* @rnd() nounwind ; [#uses=2] - %1 = icmp sgt i64 %0, 0 ; [#uses=1] - br i1 %1, label %bb, label %bb2 - -bb: ; preds = %bb, %entry - %2 = phi i64 [ 0, %entry ], [ %3, %bb ] ; [#uses=3] - %scevgep = getelementptr i64* %a, i64 %2 ; [#uses=1] - store i64 %2, i64* %scevgep, align 8 - %3 = add nsw i64 %2, 1 ; [#uses=2] - %exitcond = icmp eq i64 %3, %0 ; [#uses=1] - br i1 %exitcond, label %bb2, label %bb - -bb2: ; preds = %bb, %entry - %4 = getelementptr inbounds i64* %a, i64 %N ; [#uses=1] - store i64 0, i64* %4, align 8 - ret void -} - -declare i64 @rnd(...) - -; CHECK: Scop: bb => bb2.single_exit Parameters: (%0, ), Max Loop Depth: 1 From grosser at fim.uni-passau.de Wed Nov 9 16:34:24 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:34:24 -0000 Subject: [llvm-commits] [polly] r144221 - in /polly/trunk: lib/Analysis/TempScopInfo.cpp test/ScopInfo/Alias-4.ll test/ScopInfo/bug_2010_07_16.ll test/ScopInfo/simple_loop_0.ll test/ScopInfo/sum.ll Message-ID: <20111109223424.927F61BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:34:24 2011 New Revision: 144221 URL: http://llvm.org/viewvc/llvm-project?rev=144221&view=rev Log: TempScop: Remove more of the buildAffineFunction Removed: polly/trunk/test/ScopInfo/bug_2010_07_16.ll Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp polly/trunk/test/ScopInfo/Alias-4.ll polly/trunk/test/ScopInfo/simple_loop_0.ll polly/trunk/test/ScopInfo/sum.ll Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144221&r1=144220&r2=144221&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Wed Nov 9 16:34:24 2011 @@ -213,21 +213,11 @@ const SCEV *Var = I->first; // Extract the constant part if (isa(Var)) - // Add the translation component - FuncToBuild.TransComp = I->second; + ; else if (Var->getType()->isPointerTy()) { // Extract the base address const SCEVUnknown *BaseAddr = dyn_cast(Var); assert(BaseAddr && "Why we got a broken scev?"); FuncToBuild.BaseAddr = BaseAddr->getValue(); - } else { // Extract other affine components. - FuncToBuild.LnrTrans.insert(*I); - // Do not add the indvar to the parameter list. - if (!isIndVar(Var, R, *LI, *SE)) { - DEBUG(dbgs() << "Non indvar: "<< *Var << '\n'); - assert(isParameter(Var, R, *LI, *SE) - && "Find non affine function in scop!"); - Params.insert(Var); - } } } } Modified: polly/trunk/test/ScopInfo/Alias-4.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/Alias-4.ll?rev=144221&r1=144220&r2=144221&view=diff ============================================================================== --- polly/trunk/test/ScopInfo/Alias-4.ll (original) +++ polly/trunk/test/ScopInfo/Alias-4.ll Wed Nov 9 16:34:24 2011 @@ -1,5 +1,4 @@ ; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s -stats 2>&1 | not FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s | FileCheck %s -check-prefix=MAS ; ModuleID = '/tmp/webcompile/_22751_0.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" @@ -26,5 +25,3 @@ ; CHECK: Found base address alias -; MAS: Reads %b[4 * {0,+,1}<%bb> + 0] Refs: Must alias {%b, } May alias {}, -; MAS: Writes %a[4 * {0,+,1}<%bb> + 0] Refs: Must alias {%a, } May alias {}, Removed: polly/trunk/test/ScopInfo/bug_2010_07_16.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/bug_2010_07_16.ll?rev=144220&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/bug_2010_07_16.ll (original) +++ polly/trunk/test/ScopInfo/bug_2010_07_16.ll (removed) @@ -1,52 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s | FileCheck %s - -; ModuleID = '/home/ether/unexpected_parameter.ll' -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-unknown-linux-gnu" - -define void @mdct_sub48([2 x [576 x double]]* %mdct_freq) nounwind { -entry: - br label %bb54 - -bb4: ; preds = %bb54, %bb49 - br label %bb6 - -bb6: ; preds = %bb6, %bb4 - br i1 undef, label %bb6, label %bb48 - -bb24: ; preds = %bb48 - br i1 false, label %bb47, label %bb46 - -bb40: ; preds = %bb46 - %0 = load double* %scevgep74, align 8 ; [#uses=0] - %indvar.next62 = add i64 %indvar61, 1 ; [#uses=1] - br label %bb46 - -bb46: ; preds = %bb40, %bb24 - %indvar61 = phi i64 [ %indvar.next62, %bb40 ], [ 0, %bb24 ] ; [#uses=1] - %scevgep74 = getelementptr [2 x [576 x double]]* %mdct_freq, i64 0, i64 %indvar1, i64 0 ; [#uses=1] - store double undef, double* %scevgep74, align 8 - br i1 false, label %bb40, label %bb47 - -bb47: ; preds = %bb46, %bb24 - br label %bb48 - -bb48: ; preds = %bb47, %bb6 - br i1 false, label %bb24, label %bb49 - -bb49: ; preds = %bb48 - br i1 undef, label %bb4, label %bb53 - -bb53: ; preds = %bb49 - %indvar.next2 = add i64 %indvar1, 1 ; [#uses=1] - br label %bb54 - -bb54: ; preds = %bb53, %entry - %indvar1 = phi i64 [ %indvar.next2, %bb53 ], [ 0, %entry ] ; [#uses=2] - br i1 undef, label %bb4, label %return - -return: ; preds = %bb54 - ret void -} - -; CHECK: Scop: bb24 => bb48.region Parameters: ({0,+,1}<%bb54>, ), Max Loop Depth: 1 Modified: polly/trunk/test/ScopInfo/simple_loop_0.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/simple_loop_0.ll?rev=144221&r1=144220&r2=144221&view=diff ============================================================================== --- polly/trunk/test/ScopInfo/simple_loop_0.ll (original) +++ polly/trunk/test/ScopInfo/simple_loop_0.ll Wed Nov 9 16:34:24 2011 @@ -1,4 +1,3 @@ -; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s | FileCheck %s -check-prefix=WITHAF ; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s | FileCheck %s ;void f(long a[], long N) { @@ -32,10 +31,3 @@ } ; CHECK: Scop: bb => return Parameters: () -; WITHAF: Scop: bb => return Parameters: (), Max Loop Depth: 1 -; WITHAF: Bounds of Loop: bb: { 127 } -; WITHAF: BB: bb{ -; WITHAF: Reads %a[8 * {0,+,1}<%bb> + 0] -; WITHAF: Reads %a[8 * {0,+,1}<%bb> + 16] -; WITHAF: Writes %a[8 * {0,+,1}<%bb> + 0] -; WITHAF: } Modified: polly/trunk/test/ScopInfo/sum.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/sum.ll?rev=144221&r1=144220&r2=144221&view=diff ============================================================================== --- polly/trunk/test/ScopInfo/sum.ll (original) +++ polly/trunk/test/ScopInfo/sum.ll Wed Nov 9 16:34:24 2011 @@ -36,9 +36,3 @@ } ; CHECK: Bounds of Loop: bb: { (-2 + %n) } -; CHECK: BB: bb{ -; CHECK: Reads %k.05.reg2mem[0] Refs: Must alias {%k.05.reg2mem, } May alias {}, -; CHECK: Reads %a[8 * {0,+,1}<%bb> + 8] Refs: Must alias {%a, } May alias {}, -; CHECK: Writes %k.0.lcssa.reg2mem[0] Refs: Must alias {%k.0.lcssa.reg2mem, } May alias {}, -; CHECK: Writes %k.05.reg2mem[0] Refs: Must alias {%k.05.reg2mem, } May alias {}, -; CHECK: } From grosser at fim.uni-passau.de Wed Nov 9 16:34:28 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:34:28 -0000 Subject: [llvm-commits] [polly] r144222 - /polly/trunk/lib/Analysis/ScopInfo.cpp Message-ID: <20111109223428.3E4CD1BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:34:28 2011 New Revision: 144222 URL: http://llvm.org/viewvc/llvm-project?rev=144222&view=rev Log: ScopInfo: Use getParamsInAffineExpr to get the BaseAddress Modified: polly/trunk/lib/Analysis/ScopInfo.cpp Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144222&r1=144221&r2=144222&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Wed Nov 9 16:34:28 2011 @@ -82,18 +82,19 @@ public: static isl_pw_aff *getPwAff(ScopStmt *stmt, const SCEV *scev, - const Value *baseAddress = 0) { + bool isMemoryAccess = false) { Scop *S = stmt->getParent(); const Region *Reg = &S->getRegion(); - if (baseAddress) { - Value *Base; - S->addParams(getParamsInAffineExpr(Reg, scev, *S->getSE(), &Base)); + Value *BaseAddress = NULL; + + if (isMemoryAccess) { + S->addParams(getParamsInAffineExpr(Reg, scev, *S->getSE(), &BaseAddress)); } else { S->addParams(getParamsInAffineExpr(Reg, scev, *S->getSE())); } - SCEVAffinator Affinator(stmt, baseAddress); + SCEVAffinator Affinator(stmt, BaseAddress); return Affinator.visit(scev); } @@ -333,7 +334,7 @@ setBaseName(); isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, AffFunc.OriginalSCEV, - AffFunc.getBaseAddr()); + true); // Devide the access function by the size of the elements in the array. // @@ -609,8 +610,8 @@ } __isl_give isl_set *ScopStmt::buildConditionSet(const Comparison &Comp) { - isl_pw_aff *L = SCEVAffinator::getPwAff(this, Comp.getLHS()->OriginalSCEV, 0); - isl_pw_aff *R = SCEVAffinator::getPwAff(this, Comp.getRHS()->OriginalSCEV, 0); + isl_pw_aff *L = SCEVAffinator::getPwAff(this, Comp.getLHS()->OriginalSCEV); + isl_pw_aff *R = SCEVAffinator::getPwAff(this, Comp.getRHS()->OriginalSCEV); switch (Comp.getPred()) { case ICmpInst::ICMP_EQ: From grosser at fim.uni-passau.de Wed Nov 9 16:34:34 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:34:34 -0000 Subject: [llvm-commits] [polly] r144223 - in /polly/trunk: include/polly/TempScopInfo.h lib/Analysis/ScopInfo.cpp lib/Analysis/TempScopInfo.cpp test/ScopInfo/sum.ll Message-ID: <20111109223434.8E5E01BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:34:34 2011 New Revision: 144223 URL: http://llvm.org/viewvc/llvm-project?rev=144223&view=rev Log: Remove more of SCEVAffineFunc Removed: polly/trunk/test/ScopInfo/sum.ll Modified: polly/trunk/include/polly/TempScopInfo.h polly/trunk/lib/Analysis/ScopInfo.cpp polly/trunk/lib/Analysis/TempScopInfo.cpp Modified: polly/trunk/include/polly/TempScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/TempScopInfo.h?rev=144223&r1=144222&r2=144223&view=diff ============================================================================== --- polly/trunk/include/polly/TempScopInfo.h (original) +++ polly/trunk/include/polly/TempScopInfo.h Wed Nov 9 16:34:34 2011 @@ -317,17 +317,6 @@ // Clear the context. void clear(); - /// @brief Build an affine function from a SCEV expression. - /// - /// @param S The SCEV expression to be converted to affine - /// function. - /// @param Scop The Scope of this expression. - /// @param FuncToBuild The SCEVAffFunc to hold the result. - /// - void buildAffineFunction(const SCEV *S, SCEVAffFunc &FuncToBuild, - Region &R, ParamSetType &Params) const; - - /// @brief Build condition constrains to BBs in a valid Scop. /// /// @param BB The BasicBlock to build condition constrains Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144223&r1=144222&r2=144223&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Wed Nov 9 16:34:34 2011 @@ -82,19 +82,18 @@ public: static isl_pw_aff *getPwAff(ScopStmt *stmt, const SCEV *scev, - bool isMemoryAccess = false) { + Value **BaseAddress = NULL) { Scop *S = stmt->getParent(); const Region *Reg = &S->getRegion(); - Value *BaseAddress = NULL; - - if (isMemoryAccess) { - S->addParams(getParamsInAffineExpr(Reg, scev, *S->getSE(), &BaseAddress)); + if (BaseAddress) { + S->addParams(getParamsInAffineExpr(Reg, scev, *S->getSE(), BaseAddress)); } else { S->addParams(getParamsInAffineExpr(Reg, scev, *S->getSE())); } - SCEVAffinator Affinator(stmt, BaseAddress); + Value *Base = BaseAddress ? *BaseAddress : NULL; + SCEVAffinator Affinator(stmt, Base); return Affinator.visit(scev); } @@ -327,14 +326,15 @@ MemoryAccess::MemoryAccess(const SCEVAffFunc &AffFunc, ScopStmt *Statement) { newAccessRelation = NULL; - BaseAddr = AffFunc.getBaseAddr(); Type = AffFunc.isRead() ? Read : Write; statement = Statement; - setBaseName(); - + Value *TmpBaseAddress = NULL; isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, AffFunc.OriginalSCEV, - true); + &TmpBaseAddress); + BaseAddr = TmpBaseAddress; + + setBaseName(); // Devide the access function by the size of the elements in the array. // Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144223&r1=144222&r2=144223&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Wed Nov 9 16:34:34 2011 @@ -75,32 +75,6 @@ } void SCEVAffFunc::print(raw_ostream &OS, bool PrintInequality) const { - // Print BaseAddr. - if (isDataRef()) { - OS << (isRead() ? "Reads" : "Writes") << " "; - WriteAsOperand(OS, getBaseAddr(), false); - OS << "["; - } - - for (LnrTransSet::const_iterator I = LnrTrans.begin(), E = LnrTrans.end(); - I != E; ++I) - OS << *I->second << " * " << *I->first << " + "; - - if (TransComp) - OS << *TransComp; - - if (isDataRef()) - OS << "]"; - - if (!PrintInequality) - return; - - if (getType() == GE) - OS << " >= 0"; - else if (getType() == Eq) - OS << " == 0"; - else if (getType() == Ne) - OS << " != 0"; } void SCEVAffFunc::dump() const { @@ -152,74 +126,6 @@ void TempScop::printDetail(llvm::raw_ostream &OS, ScalarEvolution *SE, LoopInfo *LI, const Region *CurR, unsigned ind) const { - // Print the loop bounds, if the current region is a loop. - LoopBoundMapType::const_iterator at = LoopBounds.find(castToLoop(*CurR, *LI)); - if (at != LoopBounds.end()) { - OS.indent(ind) << "Bounds of Loop: " << at->first->getHeader()->getName() - << ":\t{ "; - OS << *(at->second); - OS << " }\n"; - ind += 2; - } - - // Iterate over the region nodes of this Scop to print the access functions - // and loop bounds. - for (Region::const_element_iterator I = CurR->element_begin(), - E = CurR->element_end(); I != E; ++I) { - if (I->isSubRegion()) { - Region *subR = I->getNodeAs(); - printDetail(OS, SE, LI, subR, ind + 2); - } else { - BasicBlock *BB = I->getNodeAs(); - - if (const AccFuncSetType *AccFunc = getAccessFunctions(BB)) { - OS.indent(ind) << "BB: " << BB->getName() << "{\n"; - - for (AccFuncSetType::const_iterator FI = AccFunc->begin(), - FE = AccFunc->end(); FI != FE; ++FI) { - const SCEVAffFunc &AF = FI->first; - const Value *Ptr = AF.getBaseAddr(); - - OS.indent(ind + 2) << AF << " Refs: "; - for (MayAliasSetInfo::const_alias_iterator - MI = MayASInfo->alias_begin(Ptr), ME = MayASInfo->alias_end(Ptr); - MI != ME; ++MI) { - MI->second->print(OS); - OS << ", "; - } - - OS << '\n'; - } - - OS.indent(ind) << "}\n"; - } - } - } -} - -void TempScopInfo::buildAffineFunction(const SCEV *S, SCEVAffFunc &FuncToBuild, - Region &R, ParamSetType &Params) const { - assert(S && "S can not be null!"); - - assert(!isa(S) - && "Un Expect broken affine function in Scop!"); - - for (AffineSCEVIterator I = affine_begin(S, SE), E = affine_end(); - I != E; ++I) { - // The constant part must be a SCEVConstant. - // TODO: support sizeof in coefficient. - assert(isa(I->second) && "Expect SCEVConst in coefficient!"); - - const SCEV *Var = I->first; - // Extract the constant part - if (isa(Var)) - ; - else if (Var->getType()->isPointerTy()) { // Extract the base address - const SCEVUnknown *BaseAddr = dyn_cast(Var); - assert(BaseAddr && "Why we got a broken scev?"); - FuncToBuild.BaseAddr = BaseAddr->getValue(); - } - } } void TempScopInfo::buildAccessFunctions(Region &R, ParamSetType &Parameter, @@ -244,8 +150,6 @@ const SCEV *AccessFunction = SE->getSCEV(getPointerOperand(Inst)); Functions.push_back( std::make_pair(SCEVAffFunc(Type, AccessFunction, Size), &Inst)); - - buildAffineFunction(AccessFunction, Functions.back().first, R, Parameter); } } Removed: polly/trunk/test/ScopInfo/sum.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/sum.ll?rev=144222&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/sum.ll (original) +++ polly/trunk/test/ScopInfo/sum.ll (removed) @@ -1,38 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -polly-prepare -polly-analyze-ir -analyze %s | FileCheck %s - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-linux-gnu" - -;long f(long a[], long n) { -; long i, k; -; k = 0; -; for (i = 1; i < n; ++i) { -; k += a[i]; -; } -; return k; -;} -define i64 @f(i64* nocapture %a, i64 %n) nounwind readonly { -entry: - %0 = icmp sgt i64 %n, 1 ; [#uses=1] - br i1 %0, label %bb.nph, label %bb2 - -bb.nph: ; preds = %entry - %tmp = add i64 %n, -1 ; [#uses=1] - br label %bb - -bb: ; preds = %bb, %bb.nph - %indvar = phi i64 [ 0, %bb.nph ], [ %tmp6, %bb ] ; [#uses=1] - %k.05 = phi i64 [ 0, %bb.nph ], [ %2, %bb ] ; [#uses=1] - %tmp6 = add i64 %indvar, 1 ; [#uses=3] - %scevgep = getelementptr i64* %a, i64 %tmp6 ; [#uses=1] - %1 = load i64* %scevgep, align 8 ; [#uses=1] - %2 = add nsw i64 %1, %k.05 ; [#uses=2] - %exitcond = icmp eq i64 %tmp6, %tmp ; [#uses=1] - br i1 %exitcond, label %bb2, label %bb - -bb2: ; preds = %bb, %entry - %k.0.lcssa = phi i64 [ 0, %entry ], [ %2, %bb ] ; [#uses=1] - ret i64 %k.0.lcssa -} - -; CHECK: Bounds of Loop: bb: { (-2 + %n) } From grosser at fim.uni-passau.de Wed Nov 9 16:34:39 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:34:39 -0000 Subject: [llvm-commits] [polly] r144224 - in /polly/trunk: lib/Analysis/TempScopInfo.cpp test/ScopInfo/cast.ll test/ScopInfo/indvar_out_of_loop_3.ll Message-ID: <20111109223439.8F59D1BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:34:39 2011 New Revision: 144224 URL: http://llvm.org/viewvc/llvm-project?rev=144224&view=rev Log: Remove unused code from SCEVAffFunc constructor Removed: polly/trunk/test/ScopInfo/cast.ll polly/trunk/test/ScopInfo/indvar_out_of_loop_3.ll Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144224&r1=144223&r2=144224&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Wed Nov 9 16:34:39 2011 @@ -40,50 +40,7 @@ ParamSetType &Params, LoopInfo *LI, ScalarEvolution *SE) : ElemBytes(0), FuncType(Type) { - assert(S && "S can not be null!"); - assert(!isa(S) && "Non affine function in Scop"); - OriginalSCEV = S; - - for (AffineSCEVIterator I = affine_begin(S, SE), E = affine_end(); - I != E; ++I) { - // The constant part must be a SCEVConstant. - // TODO: support sizeof in coefficient. - assert(isa(I->second) - && "Expected SCEVConst in coefficient!"); - - const SCEV *Var = I->first; - - if (isa(Var)) // Extract the constant part. - // Add the translation component. - TransComp = I->second; - else if (Var->getType()->isPointerTy()) { // Extract the base address. - const SCEVUnknown *Addr = dyn_cast(Var); - assert(Addr && "Broken SCEV detected!"); - BaseAddr = Addr->getValue(); - } else { // Extract other affine components. - LnrTrans.insert(*I); - - if (isIndVar(Var, R, *LI, *SE)) - continue; - - assert(isParameter(Var, R, *LI, *SE) - && "Found non affine function in Scop!"); - Params.insert(Var); - } - } -} - -void SCEVAffFunc::print(raw_ostream &OS, bool PrintInequality) const { -} - -void SCEVAffFunc::dump() const { - print(errs()); -} - -inline raw_ostream &operator<<(raw_ostream &OS, const SCEVAffFunc &AffFunc) { - AffFunc.print(OS); - return OS; } void Comparison::print(raw_ostream &OS) const { Removed: polly/trunk/test/ScopInfo/cast.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/cast.ll?rev=144223&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/cast.ll (original) +++ polly/trunk/test/ScopInfo/cast.ll (removed) @@ -1,52 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s | FileCheck %s -; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s | FileCheck %s -;void f(long a[], long N, long M) { -; long i, j, k; -; for (j = 0; j < M; ++j) -; ((long*)j)[(long)a] = j; - -; for (j = 0; j < N; ++j) -; a[j] = (char)(M + j); -;} - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define void @f(i64* %a, i64 %N, i64 %M) nounwind { -entry: - %0 = icmp sgt i64 %M, 0 ; [#uses=1] - br i1 %0, label %bb.nph8, label %bb4.loopexit - -bb.nph8: ; preds = %entry - %1 = ptrtoint i64* %a to i64 ; [#uses=1] - br label %bb - -bb: ; preds = %bb, %bb.nph8 - %2 = phi i64 [ 0, %bb.nph8 ], [ %5, %bb ] ; [#uses=3] - %3 = inttoptr i64 %2 to i64* ; [#uses=1] - %4 = getelementptr inbounds i64* %3, i64 %1 ; [#uses=1] - store i64 %2, i64* %4, align 8 - %5 = add nsw i64 %2, 1 ; [#uses=2] - %exitcond10 = icmp eq i64 %5, %M ; [#uses=1] - br i1 %exitcond10, label %bb4.loopexit, label %bb - -bb3: ; preds = %bb4.loopexit, %bb3 - %j.16 = phi i64 [ 0, %bb4.loopexit ], [ %7, %bb3 ] ; [#uses=3] - %scevgep = getelementptr i64* %a, i64 %j.16 ; [#uses=1] - %tmp = add i64 %j.16, %M ; [#uses=1] - %tmp9 = trunc i64 %tmp to i8 ; [#uses=1] - %6 = sext i8 %tmp9 to i64 ; [#uses=1] - store i64 %6, i64* %scevgep, align 8 - %7 = add nsw i64 %j.16, 1 ; [#uses=2] - %exitcond = icmp eq i64 %7, %N ; [#uses=1] - br i1 %exitcond, label %return, label %bb3 - -bb4.loopexit: ; preds = %bb, %entry - %8 = icmp sgt i64 %N, 0 ; [#uses=1] - br i1 %8, label %bb3, label %return - -return: ; preds = %bb4.loopexit, %bb3 - ret void -} - -; CHECK: Scop: bb4.loopexit => return Parameters: (%N, ), Max Loop Depth: 1 Removed: polly/trunk/test/ScopInfo/indvar_out_of_loop_3.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/indvar_out_of_loop_3.ll?rev=144223&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/indvar_out_of_loop_3.ll (original) +++ polly/trunk/test/ScopInfo/indvar_out_of_loop_3.ll (removed) @@ -1,53 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -polly-prepare -polly-analyze-ir -analyze %s | FileCheck %s - -;void f(long a[], long n, long m) { -; long i0, i1; -; for (i0 = 0; i0 < 2 * n + m; ++i0)//loop0 -; a[i0] = n; - -; for (i1 = 0; i1 < i0 + m; ++i1)//loop1 -; a[i1] += 2; -;} - - -; ModuleID = '/tmp/webcompile/_19162_0.bc' -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-linux-gnu" - -define void @_Z1fPlll(i64* nocapture %a, i64 %n, i64 %m) nounwind { -entry: - %0 = shl i64 %n, 1 ; [#uses=1] - %1 = add nsw i64 %0, %m ; [#uses=3] - %2 = icmp sgt i64 %1, 0 ; [#uses=1] - br i1 %2, label %bb, label %bb4.preheader - -bb: ; preds = %bb, %entry - %i0.07 = phi i64 [ %3, %bb ], [ 0, %entry ] ; [#uses=2] - %scevgep11 = getelementptr i64* %a, i64 %i0.07 ; [#uses=1] - store i64 %n, i64* %scevgep11, align 8 - %3 = add nsw i64 %i0.07, 1 ; [#uses=2] - %exitcond10 = icmp eq i64 %3, %1 ; [#uses=1] - br i1 %exitcond10, label %bb4.preheader, label %bb - -bb4.preheader: ; preds = %bb, %entry - %i0.0.lcssa = phi i64 [ 0, %entry ], [ %1, %bb ] ; [#uses=1] - %4 = add nsw i64 %i0.0.lcssa, %m ; [#uses=2] - %5 = icmp sgt i64 %4, 0 ; [#uses=1] - br i1 %5, label %bb3, label %return - -bb3: ; preds = %bb3, %bb4.preheader - %i1.06 = phi i64 [ %8, %bb3 ], [ 0, %bb4.preheader ] ; [#uses=2] - %scevgep = getelementptr i64* %a, i64 %i1.06 ; [#uses=2] - %6 = load i64* %scevgep, align 8 ; [#uses=1] - %7 = add nsw i64 %6, 2 ; [#uses=1] - store i64 %7, i64* %scevgep, align 8 - %8 = add nsw i64 %i1.06, 1 ; [#uses=2] - %exitcond = icmp eq i64 %8, %4 ; [#uses=1] - br i1 %exitcond, label %return, label %bb3 - -return: ; preds = %bb3, %bb4.preheader - ret void -} - - -; CHECK: Scop: entry.split => bb4.preheader.region Parameters: (%m, %n, ), Max Loop From grosser at fim.uni-passau.de Wed Nov 9 16:34:44 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:34:44 -0000 Subject: [llvm-commits] [polly] r144226 - in /polly/trunk: include/polly/TempScopInfo.h lib/Analysis/ScopInfo.cpp lib/Analysis/TempScopInfo.cpp Message-ID: <20111109223444.9711B1BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:34:44 2011 New Revision: 144226 URL: http://llvm.org/viewvc/llvm-project?rev=144226&view=rev Log: Remove SCEVAffFunc from polly::Comparison Modified: polly/trunk/include/polly/TempScopInfo.h polly/trunk/lib/Analysis/ScopInfo.cpp polly/trunk/lib/Analysis/TempScopInfo.cpp Modified: polly/trunk/include/polly/TempScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/TempScopInfo.h?rev=144226&r1=144225&r2=144226&view=diff ============================================================================== --- polly/trunk/include/polly/TempScopInfo.h (original) +++ polly/trunk/include/polly/TempScopInfo.h Wed Nov 9 16:34:44 2011 @@ -131,17 +131,17 @@ class Comparison { - SCEVAffFunc *LHS; - SCEVAffFunc *RHS; + const SCEV *LHS; + const SCEV *RHS; ICmpInst::Predicate Pred; public: - Comparison(SCEVAffFunc *lhs, SCEVAffFunc *rhs, ICmpInst::Predicate pred) - : LHS(lhs), RHS(rhs), Pred(pred) {} + Comparison(const SCEV *LHS, const SCEV *RHS, ICmpInst::Predicate Pred) + : LHS(LHS), RHS(RHS), Pred(Pred) {} - SCEVAffFunc *getLHS() const { return LHS; } - SCEVAffFunc *getRHS() const { return RHS; } + const SCEV *getLHS() const { return LHS; } + const SCEV *getRHS() const { return RHS; } ICmpInst::Predicate getPred() const { return Pred; } void print(raw_ostream &OS) const; Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144226&r1=144225&r2=144226&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Wed Nov 9 16:34:44 2011 @@ -610,8 +610,8 @@ } __isl_give isl_set *ScopStmt::buildConditionSet(const Comparison &Comp) { - isl_pw_aff *L = SCEVAffinator::getPwAff(this, Comp.getLHS()->OriginalSCEV); - isl_pw_aff *R = SCEVAffinator::getPwAff(this, Comp.getRHS()->OriginalSCEV); + isl_pw_aff *L = SCEVAffinator::getPwAff(this, Comp.getLHS()); + isl_pw_aff *R = SCEVAffinator::getPwAff(this, Comp.getRHS()); switch (Comp.getPred()) { case ICmpInst::ICMP_EQ: Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144226&r1=144225&r2=144226&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Wed Nov 9 16:34:44 2011 @@ -147,19 +147,16 @@ void TempScopInfo::buildAffineCondition(Value &V, bool inverted, Comparison **Comp, TempScop &Scop) const { - Region &R = Scop.getMaxRegion(); - ParamSetType &Params = Scop.getParamSet(); if (ConstantInt *C = dyn_cast(&V)) { // If this is always true condition, we will create 1 >= 0, // otherwise we will create 1 == 0. - SCEVAffFunc *AffLHS = new SCEVAffFunc(SE->getConstant(C->getType(), 0), - SCEVAffFunc::Eq, R, Params, LI, SE); - SCEVAffFunc *AffRHS = new SCEVAffFunc(SE->getConstant(C->getType(), 1), - SCEVAffFunc::Eq, R, Params, LI, SE); + const SCEV *LHS = SE->getConstant(C->getType(), 0); + const SCEV *RHS = SE->getConstant(C->getType(), 1); + if (C->isOne() == inverted) - *Comp = new Comparison(AffRHS, AffLHS, ICmpInst::ICMP_NE); + *Comp = new Comparison(RHS, LHS, ICmpInst::ICMP_NE); else - *Comp = new Comparison(AffLHS, AffLHS, ICmpInst::ICMP_EQ); + *Comp = new Comparison(LHS, LHS, ICmpInst::ICMP_EQ); return; } @@ -176,11 +173,6 @@ if (inverted) Pred = ICmpInst::getInversePredicate(Pred); - SCEVAffFunc *AffLHS = new SCEVAffFunc(LHS, SCEVAffFunc::Eq, R, Params, LI, - SE); - SCEVAffFunc *AffRHS = new SCEVAffFunc(RHS, SCEVAffFunc::Eq, R, Params, LI, - SE); - switch (Pred) { case ICmpInst::ICMP_UGT: case ICmpInst::ICMP_UGE: @@ -195,7 +187,7 @@ break; } - *Comp = new Comparison(AffLHS, AffRHS, Pred); + *Comp = new Comparison(LHS, RHS, Pred); } void TempScopInfo::buildCondition(BasicBlock *BB, BasicBlock *RegionEntry, From grosser at fim.uni-passau.de Wed Nov 9 16:34:49 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:34:49 -0000 Subject: [llvm-commits] [polly] r144227 - in /polly/trunk: include/polly/TempScopInfo.h lib/Analysis/TempScopInfo.cpp Message-ID: <20111109223449.24A281BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:34:48 2011 New Revision: 144227 URL: http://llvm.org/viewvc/llvm-project?rev=144227&view=rev Log: Remove more unused stuff from SCEVAffFunc Modified: polly/trunk/include/polly/TempScopInfo.h polly/trunk/lib/Analysis/TempScopInfo.cpp Modified: polly/trunk/include/polly/TempScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/TempScopInfo.h?rev=144227&r1=144226&r2=144227&view=diff ============================================================================== --- polly/trunk/include/polly/TempScopInfo.h (original) +++ polly/trunk/include/polly/TempScopInfo.h Wed Nov 9 16:34:48 2011 @@ -38,12 +38,6 @@ class SCEVAffFunc { // Temporary hack friend class TempScopInfo; - // The translation component - const SCEV *TransComp; - - // { Variable, Coefficient } - typedef std::map LnrTransSet; - LnrTransSet LnrTrans; public: // The scalar evolution expression from which we derived this affine @@ -56,12 +50,8 @@ // The type of the scev affine function enum SCEVAffFuncType { - None = 0, - ReadMem, // Or we could call it "Use" - WriteMem, // Or define - Eq, // == 0 - Ne, // != 0 - GE // >= 0 + ReadMem, + WriteMem }; private: @@ -77,58 +67,20 @@ /// condition type explicit SCEVAffFunc(SCEVAffFuncType Type, const SCEV *OriginalSCEV, unsigned elemBytes = 0) - : TransComp(0), OriginalSCEV(OriginalSCEV), BaseAddr(0), + : OriginalSCEV(OriginalSCEV), BaseAddr(0), ElemBytes(elemBytes), FuncType(Type) {} - /// @brief Construct a new SCEVAffFunc from a SCEV - /// - /// @param S The SCEV that should be translated. - /// @param Type The type of this affine function. - /// @param R The region in which the affine function is evaluated. - /// @param Param A set of parameters, where new parameters found in this - /// affine function will be added. - /// @param LI A pointer to a current LoopInfo analysis. - /// @param SE A pointer to a current ScalarEvolution analysis. - SCEVAffFunc(const SCEV *S, SCEVAffFuncType Type, Region &R, - ParamSetType &Param, LoopInfo *LI, ScalarEvolution *SE); - - // getCoeff - Get the Coefficient of a given variable. - const SCEV *getCoeff(const SCEV *Var) const { - LnrTransSet::const_iterator At = LnrTrans.find(Var); - return At == LnrTrans.end() ? 0 : At->second; - } - - const SCEV *getTransComp() const { - return TransComp; - } - enum SCEVAffFuncType getType() const { return FuncType; } - bool isDataRef() const { - return getType() == ReadMem || getType() == WriteMem; - } - unsigned getElemSizeInBytes() const { - assert(isDataRef() && "getElemSizeInBytes on the wrong type!"); return ElemBytes; } bool isRead() const { return FuncType == ReadMem; } const Value *getBaseAddr() const { return BaseAddr; } - - /// @brief Print the affine function. - /// - /// @param OS The output stream the affine function is printed to. - void print(raw_ostream &OS, bool PrintInequality = true) const; - void dump() const; }; -static inline raw_ostream& operator<<(raw_ostream &OS, const SCEVAffFunc &SAF){ - SAF.print(OS); - return OS; -} - class Comparison { const SCEV *LHS; Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144227&r1=144226&r2=144227&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Wed Nov 9 16:34:48 2011 @@ -36,13 +36,6 @@ //===----------------------------------------------------------------------===// /// Helper Class -SCEVAffFunc::SCEVAffFunc(const SCEV *S, SCEVAffFuncType Type, Region &R, - ParamSetType &Params, LoopInfo *LI, - ScalarEvolution *SE) - : ElemBytes(0), FuncType(Type) { - OriginalSCEV = S; -} - void Comparison::print(raw_ostream &OS) const { // Not yet implemented. } From grosser at fim.uni-passau.de Wed Nov 9 16:34:53 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:34:53 -0000 Subject: [llvm-commits] [polly] r144228 - in /polly/trunk: include/polly/ScopDetection.h lib/Analysis/ScopDetection.cpp Message-ID: <20111109223453.763551BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:34:53 2011 New Revision: 144228 URL: http://llvm.org/viewvc/llvm-project?rev=144228&view=rev Log: Do not check memory accesses additionally with isValidAffineFunction This check was necessary because of the use AffineSCEVIterator in TempScopInfo. As we removed this use recently it is not necessary any more. Modified: polly/trunk/include/polly/ScopDetection.h polly/trunk/lib/Analysis/ScopDetection.cpp Modified: polly/trunk/include/polly/ScopDetection.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/ScopDetection.h?rev=144228&r1=144227&r2=144228&view=diff ============================================================================== --- polly/trunk/include/polly/ScopDetection.h (original) +++ polly/trunk/include/polly/ScopDetection.h Wed Nov 9 16:34:53 2011 @@ -187,20 +187,6 @@ /// @return True if the BB contains only valid control flow. bool isValidCFG(BasicBlock &BB, DetectionContext &Context) const; - /// @brief Check if the SCEV expression is a valid affine function - /// - /// @param S The SCEV expression to be checked - /// @param RefRegion The reference scope to check SCEV, it help to find out - /// induction variables and parameters - /// @param BasePtr If S represents a memory access, BasePtr should contain - /// a valid memory location to which the base address of the - /// memory access will be stored. - /// - /// @return True if the SCEV expression is affine, false otherwise - /// - bool isValidAffineFunction(const SCEV *S, Region &RefRegion, - Value **BasePtr = 0) const; - /// @brief Is a loop valid with respect to a given region. /// /// @param L The loop to check. Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=144228&r1=144227&r2=144228&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Wed Nov 9 16:34:53 2011 @@ -123,74 +123,6 @@ return InvalidRegions.find(R)->second; } - -bool ScopDetection::isValidAffineFunction(const SCEV *S, Region &RefRegion, - Value **BasePtr) const { - assert(S && "S must not be null!"); - bool isMemoryAccess = (BasePtr != 0); - if (isMemoryAccess) *BasePtr = 0; - DEBUG(dbgs() << "Checking " << *S << " ... "); - - if (isa(S)) { - DEBUG(dbgs() << "Non Affine: SCEV could not be computed\n"); - return false; - } - - for (AffineSCEVIterator I = affine_begin(S, SE), E = affine_end(); I != E; - ++I) { - // The constant part must be a SCEVConstant. - // TODO: support sizeof in coefficient. - if (!isa(I->second)) { - DEBUG(dbgs() << "Non Affine: Right hand side is not constant\n"); - return false; - } - - const SCEV *Var = I->first; - - // A constant offset is affine. - if(isa(Var)) - continue; - - // Memory accesses are allowed to have a base pointer. - if (Var->getType()->isPointerTy()) { - if (!isMemoryAccess) { - DEBUG(dbgs() << "Non Affine: Pointer in non memory access\n"); - return false; - } - - assert(I->second->isOne() && "Only one as pointer coefficient allowed.\n"); - const SCEVUnknown *BaseAddr = dyn_cast(Var); - - if (!BaseAddr || isa(BaseAddr->getValue())){ - DEBUG(dbgs() << "Cannot handle base: " << *Var << "\n"); - return false; - } - - // BaseAddr must be invariant in Scop. - if (!isParameter(BaseAddr, RefRegion, *LI, *SE)) { - DEBUG(dbgs() << "Non Affine: Base address not invariant in SCoP\n"); - return false; - } - - assert(*BasePtr == 0 && "Found second base pointer.\n"); - *BasePtr = BaseAddr->getValue(); - continue; - } - - if (isParameter(Var, RefRegion, *LI, *SE) - || isIndVar(Var, RefRegion, *LI, *SE)) - continue; - - DEBUG(dbgs() << "Non Affine: " ; - Var->print(dbgs()); - dbgs() << " is neither parameter nor induction variable\n"); - return false; - } - - DEBUG(dbgs() << " is affine.\n"); - return !isMemoryAccess || (*BasePtr != 0); -} - bool ScopDetection::isValidCFG(BasicBlock &BB, DetectionContext &Context) const { Region &RefRegion = Context.CurRegion; @@ -284,12 +216,6 @@ if (!isAffineExpr(&Context.CurRegion, AccessFunction, *SE, &BasePtr)) INVALID(AffFunc, "Bad memory address " << *AccessFunction); - // FIXME: Also check with isValidAffineFunction, as for the moment it is - // protecting us to fail because of not supported features in TempScop. - // As soon as TempScop is fixed, this needs to be removed. - if (!isValidAffineFunction(AccessFunction, Context.CurRegion, &BasePtr)) - INVALID(AffFunc, "Access not supported in TempScop" << *AccessFunction); - // FIXME: Alias Analysis thinks IntToPtrInst aliases with alloca instructions // created by IndependentBlocks Pass. if (isa(BasePtr)) From grosser at fim.uni-passau.de Wed Nov 9 16:35:01 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:35:01 -0000 Subject: [llvm-commits] [polly] r144229 - in /polly/trunk: include/polly/Support/AffineSCEVIterator.h lib/Analysis/ScopDetection.cpp lib/Analysis/TempScopInfo.cpp lib/Support/AffSCEVItTester.cpp lib/Support/CMakeLists.txt test/AffineIterator/loop_static_bound.ll test/AffineIterator/no_tagetdata.ll test/AffineIterator/no_tagetdata_loop.ll test/AffineIterator/simple_0.ll test/AffineIterator/simple_1.ll test/AffineIterator/simple_loop.ll test/AffineIterator/simple_nest.ll Message-ID: <20111109223501.4F7FF1BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:35:00 2011 New Revision: 144229 URL: http://llvm.org/viewvc/llvm-project?rev=144229&view=rev Log: Remove AffineSCEVIterator We do not use it anymore. It was replaced by SCEVVisitors like the SCEVValidator. Removed: polly/trunk/include/polly/Support/AffineSCEVIterator.h polly/trunk/lib/Support/AffSCEVItTester.cpp polly/trunk/test/AffineIterator/loop_static_bound.ll polly/trunk/test/AffineIterator/no_tagetdata.ll polly/trunk/test/AffineIterator/no_tagetdata_loop.ll polly/trunk/test/AffineIterator/simple_0.ll polly/trunk/test/AffineIterator/simple_1.ll polly/trunk/test/AffineIterator/simple_loop.ll polly/trunk/test/AffineIterator/simple_nest.ll Modified: polly/trunk/lib/Analysis/ScopDetection.cpp polly/trunk/lib/Analysis/TempScopInfo.cpp polly/trunk/lib/Support/CMakeLists.txt Removed: polly/trunk/include/polly/Support/AffineSCEVIterator.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/Support/AffineSCEVIterator.h?rev=144228&view=auto ============================================================================== --- polly/trunk/include/polly/Support/AffineSCEVIterator.h (original) +++ polly/trunk/include/polly/Support/AffineSCEVIterator.h (removed) @@ -1,292 +0,0 @@ -//===-- AffineSCEVIterator.h - Iterate the SCEV in an affine way -*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// The iterator can be used to iterate over the affine component of the SCEV -// expression. -// -//===----------------------------------------------------------------------===// - -#ifndef AFFINE_SCEV_ITERATOR_H -#define AFFINE_SCEV_ITERATOR_H - -#include "llvm/Analysis/LoopInfo.h" -#include "llvm/Analysis/ScalarEvolution.h" -#include "llvm/Analysis/ScalarEvolutionExpressions.h" - -#include - -#include "llvm/ADT/SmallVector.h" - -using namespace llvm; - -namespace polly { - -/// @brief The itertor transform the scalar expressions to the form of sum of -/// (constant * variable)s, and return the variable/constant pairs one by one -/// on the fly. -/// -/// For example, we can write SCEV: -/// {{%x,+,sizeof(i32)}<%bb2.preheader>,+,(4 * sizeof(i32))}<%bb1> -/// in affine form: -/// (4 * sizeof(i32)) * %indvar + sizeof(i32) * %0 + 1 * %x + 0 * 1 -/// so we can get the follow pair from the iterator: -/// {%indvar, (4 * sizeof(i32))}, {%0, sizeof(i32)}, {%x, 1} and {1, 0} -/// where %indvar is the induction variable of loop %bb1 and %0 is the induction -/// variable of loop %bb2.preheader. -/// -/// In the returned pair, -/// The "first" field is the variable part, the "second" field constant part. -/// And the translation part of the expression will always return last. -/// -class AffineSCEVIterator : public std::iterator, ptrdiff_t>, - SCEVVisitor > - { - typedef std::iterator, ptrdiff_t> super; - - friend struct llvm::SCEVVisitor >; - - ScalarEvolution *SE; -public: - typedef super::value_type value_type; - typedef super::pointer ptr_type; - typedef AffineSCEVIterator Self; -private: - typedef SCEVNAryExpr::op_iterator scev_op_it; - - // The stack help us remember the SCEVs that not visit yet. - SmallVector visitStack; - - // The current value of this iterator. - value_type val; - - const SCEVConstant* getSCEVOne(const SCEV* S) const { - return cast(SE->getConstant(S->getType(), 1)); - } - - //===-------------------------------------------------------------------===// - /// Functions for SCEVVisitor. - /// - /// These function compute the constant part and variable part of the SCEV, - /// and return them in a std::pair, where the first field is the variable, - /// and the second field is the constant. - /// - value_type visitConstant(const SCEVConstant *S) { - return std::make_pair(getSCEVOne(S), S); - } - - value_type visitUnknown(const SCEVUnknown* S) { - Type *AllocTy; - Constant *FieldNo; - // We treat these as constant. - if (S->isSizeOf (AllocTy) || - S->isAlignOf (AllocTy) || - S->isOffsetOf(AllocTy, FieldNo)) - return std::make_pair(getSCEVOne(S), S); - - return std::make_pair(S, getSCEVOne(S)); - } - - value_type visitMulExpr(const SCEVMulExpr* S) { - SmallVector Coeffs, Variables; - - // Do not worry about the Constant * Variable * (Variable + Variable) - // MulExpr, we will never get a affine expression from it, so we just - // leave it there. - for (scev_op_it I = S->op_begin(), E = S->op_end(); I != E; ++I) { - // Get the constant part and the variable part of each operand. - value_type res = visit(*I); - - Coeffs.push_back(res.second); - Variables.push_back(res.first); - } - - // Get the constant part and variable part of this MulExpr by - // multiply them together. - const SCEV *Coeff = SE->getMulExpr(Coeffs); - // There maybe "sizeof" and others. - // TODO: Assert the allowed coeff type. - // assert(Coeff && "Expect Coeff to be a const!"); - - const SCEV *Var = SE->getMulExpr(Variables); - - return std::make_pair(Var, Coeff); - } - - value_type visitCastExpr(const SCEVCastExpr *S) { - return std::make_pair(S, getSCEVOne(S)); - } - - value_type visitTruncateExpr(const SCEVTruncateExpr *S) { - return visitCastExpr(S); - } - - value_type visitZeroExtendExpr(const SCEVZeroExtendExpr *S) { - return visitCastExpr(S); - } - - value_type visitSignExtendExpr(const SCEVSignExtendExpr *S) { - return visitCastExpr(S); - } - - value_type visitAddExpr(const SCEVAddExpr *S) { - // AddExpr will handled out in visit Next; - return std::make_pair(S, getSCEVOne(S)); - } - - value_type visitAddRecExpr(const SCEVAddRecExpr *S) { - // AddRecExpr will handled out in visit Next; - return std::make_pair(S, getSCEVOne(S)); - } - - value_type visitUDivExpr(const SCEVUDivExpr *S) { - return std::make_pair(S, getSCEVOne(S)); - } - - value_type visitSMaxExpr(const SCEVSMaxExpr *S) { - return std::make_pair(S, getSCEVOne(S)); - } - - value_type visitUMaxExpr(const SCEVUMaxExpr *S) { - return std::make_pair(S, getSCEVOne(S)); - } - - /// Get the next {variable, constant} pair of the SCEV. - value_type visitNext() { - value_type ret(0, 0); - - if (visitStack.empty()) - return ret; - const SCEV* nextS = visitStack.back(); - - if (const SCEVAddRecExpr *ARec = dyn_cast(nextS)){ - // Visiting the AddRec, check if its Affine; - PHINode *IV = ARec->getLoop()->getCanonicalInductionVariable(); - // Only decompose the AddRec, if the loop has a canonical induction - // variable. - if (ARec->isAffine() && IV != 0) { - ret = visit(ARec->getStepRecurrence(*SE)); - if (isa(ret.first)) { // If the step is constant. - const SCEV *Start = ARec->getStart(); - visitStack.back() = Start; - - // The AddRec is expect to be decomposed to - // - // | start + step * {1, +, 1} - // - // Now we get the {1, +, 1} part. - ret.first = SE->getSCEV(IV); - - // Push CouldNotCompute to take the place. - visitStack.push_back(SE->getCouldNotCompute()); - - return ret; - } - // The step is not a constant. Then this AddRec is not Affine or - // no canonical induction variable found. - // Fall through. - } - } - - // Get the constant part and variable part of the SCEV. - ret = visit(nextS); - - // If the reach the last constant - if (isa(ret.first) && (visitStack.size() != 1)) { - // Else, merge all constant component, we will output it at last. - visitStack.front() = SE->getAddExpr(visitStack.front(), ret.second); - //assert(isa(visitStack.front().first)); - // Pop the top constant, because it already merged into the bottom of the Stack - // and output it last. - visitStack.pop_back(); - // Try again. - return visitNext(); - } - // Not a constant or Stack not empty - // If ret is in (xxx) * AddExpr form, we will decompose the AddExpr - else if (const SCEVAddExpr *AddExpr = dyn_cast(ret.first)) { - // Pop the current SCEV, we will decompose it. - visitStack.pop_back(); - assert(AddExpr->getNumOperands() && "AddExpr without operand?"); - for (scev_op_it I = AddExpr->op_begin(), E = AddExpr->op_end(); I != E; ++I){ - visitStack.push_back(SE->getMulExpr(ret.second, *I)); - } - // Try again with the new SCEV. - return visitNext(); - } - - return ret; - } - -public: - - /// @brief Create the iterator from a SCEV and the ScalarEvolution analysis. - AffineSCEVIterator(const SCEV* S, ScalarEvolution *se ) : SE(se) { - // Dont iterate CouldNotCompute. - if (isa(S)) - return; - - Type *Ty = S->getType(); - - // Init the constant component. - visitStack.push_back(SE->getConstant(Ty, 0)); - - // Get the first affine component. - visitStack.push_back(S); - val = visitNext(); - } - - /// @brief Create an end iterator. - inline AffineSCEVIterator() {} - - inline bool operator==(const Self& x) const { - return visitStack == x.visitStack; - } - inline bool operator!=(const Self& x) const { return !operator==(x); } - - /// @brief Return the current (constant * variable) component of the SCEV. - /// - /// @return The "first" field of the pair is the variable part, - /// the "second" field of the pair is the constant part. - inline value_type operator*() const { - assert(val.first && val.second && "Cant dereference iterator!"); - return val; - } - - inline const value_type* operator->() const { - assert(val.first && val.second && "Cant dereference iterator!"); - return &val; - } - - inline Self& operator++() { // Preincrement - assert(!visitStack.empty() && "Cant ++ iterator!"); - // Pop the last SCEV. - visitStack.pop_back(); - val = visitNext(); - return *this; - } - - inline Self operator++(int) { // Postincrement - Self tmp = *this; ++*this; return tmp; - } -}; - -inline static AffineSCEVIterator affine_begin(const SCEV* S, ScalarEvolution *SE) { - return AffineSCEVIterator(S, SE); -} - -inline static AffineSCEVIterator affine_end() { - return AffineSCEVIterator(); -} - -} // end namespace polly -#endif Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=144229&r1=144228&r2=144229&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Wed Nov 9 16:35:00 2011 @@ -49,12 +49,13 @@ #include "polly/LinkAllPasses.h" #include "polly/Support/ScopHelper.h" #include "polly/Support/SCEVValidator.h" -#include "polly/Support/AffineSCEVIterator.h" #include "llvm/LLVMContext.h" #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/AliasAnalysis.h" +#include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/RegionIterator.h" +#include "llvm/Analysis/ScalarEvolution.h" #include "llvm/Support/CommandLine.h" #include "llvm/Assembly/Writer.h" Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144229&r1=144228&r2=144229&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Wed Nov 9 16:35:00 2011 @@ -16,7 +16,6 @@ #include "polly/TempScopInfo.h" #include "polly/LinkAllPasses.h" -#include "polly/Support/AffineSCEVIterator.h" #include "polly/Support/GICHelper.h" #include "polly/Support/ScopHelper.h" #include "polly/Support/SCEVValidator.h" @@ -25,6 +24,8 @@ #include "llvm/Analysis/RegionIterator.h" #include "llvm/Target/TargetData.h" #include "llvm/Assembly/Writer.h" +#include "llvm/Analysis/LoopInfo.h" +#include "llvm/Analysis/ScalarEvolution.h" #include "llvm/ADT/STLExtras.h" #define DEBUG_TYPE "polly-analyze-ir" Removed: polly/trunk/lib/Support/AffSCEVItTester.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/AffSCEVItTester.cpp?rev=144228&view=auto ============================================================================== --- polly/trunk/lib/Support/AffSCEVItTester.cpp (original) +++ polly/trunk/lib/Support/AffSCEVItTester.cpp (removed) @@ -1,121 +0,0 @@ -//===- AffSCEVItTester.cpp - Test the affine scev itertor. ----------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Test the affine scev itertor. -// -//===----------------------------------------------------------------------===// - - -#include "polly/Support/AffineSCEVIterator.h" - -#include "llvm/Analysis/LoopInfo.h" -#include "llvm/Analysis/Passes.h" -#include "llvm/Assembly/Writer.h" -#include "llvm/Support/InstIterator.h" -#include "llvm/Support/raw_ostream.h" - -#include - -using namespace llvm; -using namespace polly; - -static void printSCEVAffine(raw_ostream &OS, const SCEV* S, - ScalarEvolution *SE) { - - for (AffineSCEVIterator I = affine_begin(S, SE), E = affine_end(); - I != E; ++I) { - OS << *I->second << " * " << *I->first; - - // The constant part of the SCEV will always be the last one. - if (!isa(S)) - OS << " + "; - } -} - -namespace { -struct AffSCEVItTester : public FunctionPass { - static char ID; - - ScalarEvolution *SE; - LoopInfo *LI; - Function *F; - - explicit AffSCEVItTester() : FunctionPass(ID), SE(0), LI(0), F(0) {} - - virtual bool runOnFunction(Function &F) { - SE = &getAnalysis(); - LI = &getAnalysis(); - this->F = &F; - return false; - } - - virtual void print(raw_ostream &OS, const Module *M) const { - for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I) - if (SE->isSCEVable(I->getType())) { - OS << *I << '\n'; - OS << " --> "; - const SCEV *SV = SE->getSCEV(&*I); - - if (Loop *L = LI->getLoopFor(I->getParent())) - SV = SE->getSCEVAtScope(SV, L); - SV->print(OS); - OS << "\n"; - OS << "affine function --> "; - printSCEVAffine(OS, SV, SE); - OS << "\n"; - } - - for (LoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I) - PrintLoopInfo(OS, *I); - } - - void PrintLoopInfo(raw_ostream &OS, const Loop *L) const{ - // Print all inner loops first - for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I) - PrintLoopInfo(OS, *I); - - OS << "Loop "; - WriteAsOperand(OS, L->getHeader(), /*PrintType=*/false); - OS << ": "; - - if (SE->hasLoopInvariantBackedgeTakenCount(L)) { - const SCEV *SV = SE->getBackedgeTakenCount(L); - OS << "backedge-taken count is "; - printSCEVAffine(OS, SV, SE); - - OS << "\nloop count in scev "; - SV->print(OS); - OS << "\n"; - } - else { - OS << "Unpredictable\n"; - } - } - - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - AU.addRequired(); - AU.setPreservesAll(); - } -}; -} // end namespace - - -char AffSCEVItTester::ID = 0; - -RegisterPass B("print-scev-affine", - "Print the SCEV expressions in affine form.", - true, - true); - -namespace polly { -Pass *createAffSCEVItTesterPass() { - return new AffSCEVItTester(); -} -} Modified: polly/trunk/lib/Support/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/CMakeLists.txt?rev=144229&r1=144228&r2=144229&view=diff ============================================================================== --- polly/trunk/lib/Support/CMakeLists.txt (original) +++ polly/trunk/lib/Support/CMakeLists.txt Wed Nov 9 16:35:00 2011 @@ -1,5 +1,4 @@ add_polly_library(PollySupport - AffSCEVItTester.cpp GICHelper.cpp SCEVValidator.cpp ScopHelper.cpp Removed: polly/trunk/test/AffineIterator/loop_static_bound.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/AffineIterator/loop_static_bound.ll?rev=144228&view=auto ============================================================================== --- polly/trunk/test/AffineIterator/loop_static_bound.ll (original) +++ polly/trunk/test/AffineIterator/loop_static_bound.ll (removed) @@ -1,24 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -print-scev-affine -analyze < %s | FileCheck %s - -define void @f(i32* nocapture %a) nounwind { -entry: - %0 = tail call i32 (...)* @rnd() nounwind ; [#uses=2] -; CHECK: 1 * %0 + 0 * 1 - %1 = icmp sgt i32 %0, 0 ; [#uses=1] - br i1 %1, label %bb, label %return - -bb: ; preds = %bb, %entry - %i.03 = phi i32 [ 0, %entry ], [ %3, %bb ] ; [#uses=1] -; CHECK: 1 * {0,+,1}<%bb> + 0 * 1 - %2 = tail call i32 (...)* @rnd() nounwind ; [#uses=0] -; CHECK: 1 * %2 + 0 * 1 - %3 = add nsw i32 %i.03, 1 ; [#uses=2] -; CHECK: 1 * {0,+,1}<%bb> + 1 * 1 - %exitcond = icmp eq i32 %3, %0 ; [#uses=1] - br i1 %exitcond, label %return, label %bb - -return: ; preds = %bb, %entry - ret void -} - -declare i32 @rnd(...) Removed: polly/trunk/test/AffineIterator/no_tagetdata.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/AffineIterator/no_tagetdata.ll?rev=144228&view=auto ============================================================================== --- polly/trunk/test/AffineIterator/no_tagetdata.ll (original) +++ polly/trunk/test/AffineIterator/no_tagetdata.ll (removed) @@ -1,20 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -print-scev-affine -analyze < %s | FileCheck %s - -define i32 @f(i64 %a, i64 %b, i64 %c, [8 x i32]* nocapture %x) nounwind readonly { -entry: - %0 = shl i64 %a, 1 ; [#uses=1] - %1 = add nsw i64 %0, %b ; [#uses=1] -; CHECK: 1 * %b + 2 * %a + 0 * 1 - %2 = shl i64 %1, 1 ; [#uses=1] -; CHECK: 2 * %b + 4 * %a + 0 * 1 - %3 = add i64 %2, 2 ; [#uses=1] - %4 = mul i64 %a, 3 ; [#uses=1] - %5 = shl i64 %b, 2 ; [#uses=1] - %6 = add nsw i64 %4, 2 ; [#uses=1] - %7 = add nsw i64 %6, %c ; [#uses=1] - %8 = add nsw i64 %7, %5 ; [#uses=1] - %9 = getelementptr inbounds [8 x i32]* %x, i64 %3, i64 %8 ; [#uses=1] -; CHECK: 1 * %x + sizeof(i32) * %c + (35 * sizeof(i32)) * %a + (20 * sizeof(i32)) * %b + (18 * sizeof(i32)) * 1 - %10 = load i32* %9, align 4 ; [#uses=1] - ret i32 %10 -} Removed: polly/trunk/test/AffineIterator/no_tagetdata_loop.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/AffineIterator/no_tagetdata_loop.ll?rev=144228&view=auto ============================================================================== --- polly/trunk/test/AffineIterator/no_tagetdata_loop.ll (original) +++ polly/trunk/test/AffineIterator/no_tagetdata_loop.ll (removed) @@ -1,44 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -print-scev-affine -analyze < %s | FileCheck %s - -define void @f([8 x i32]* nocapture %x) nounwind { -entry: - br label %bb5.preheader - -bb2: ; preds = %bb3.preheader, %bb2 - %k.09 = phi i64 [ 0, %bb3.preheader ], [ %1, %bb2 ] ; [#uses=2] - %tmp19 = add i64 %k.09, %tmp18 ; [#uses=1] - %scevgep = getelementptr [8 x i32]* %x, i64 2, i64 %tmp19 ; [#uses=1] -; CHECK: sizeof(i32) * {0,+,1}<%bb2> + (20 * sizeof(i32)) * {0,+,1}<%bb3.preheader> + (35 * sizeof(i32)) * {0,+,1}<%bb5.preheader> + 1 * %x + (18 * sizeof(i32)) * 1 - %0 = tail call i32 (...)* @rnd() nounwind ; [#uses=1] - store i32 %0, i32* %scevgep, align 4 - %1 = add nsw i64 %k.09, 1 ; [#uses=2] - %exitcond = icmp eq i64 %1, 64 ; [#uses=1] - br i1 %exitcond, label %bb4, label %bb2 - -bb4: ; preds = %bb2 - %2 = add i64 %j.010, 1 ; [#uses=2] - %exitcond20 = icmp eq i64 %2, 64 ; [#uses=1] - br i1 %exitcond20, label %bb6, label %bb3.preheader - -bb3.preheader: ; preds = %bb5.preheader, %bb4 - %j.010 = phi i64 [ 0, %bb5.preheader ], [ %2, %bb4 ] ; [#uses=2] - %tmp21 = mul i64 %j.010, 20 ; [#uses=1] - %tmp18 = add i64 %tmp21, %tmp23 ; [#uses=1] - br label %bb2 - -bb6: ; preds = %bb4 - %3 = add i64 %i.012, 1 ; [#uses=2] - %exitcond25 = icmp eq i64 %3, 64 ; [#uses=1] - br i1 %exitcond25, label %return, label %bb5.preheader - -bb5.preheader: ; preds = %bb6, %entry - %i.012 = phi i64 [ 0, %entry ], [ %3, %bb6 ] ; [#uses=2] - %tmp = mul i64 %i.012, 35 ; [#uses=1] - %tmp23 = add i64 %tmp, 2 ; [#uses=1] - br label %bb3.preheader - -return: ; preds = %bb6 - ret void -} - -declare i32 @rnd(...) Removed: polly/trunk/test/AffineIterator/simple_0.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/AffineIterator/simple_0.ll?rev=144228&view=auto ============================================================================== --- polly/trunk/test/AffineIterator/simple_0.ll (original) +++ polly/trunk/test/AffineIterator/simple_0.ll (removed) @@ -1,20 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -print-scev-affine -analyze < %s | FileCheck %s - -define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d, i32* nocapture %x) nounwind readnone { -entry: - %0 = shl i32 %a, 1 ; [#uses=1] -; CHECK: 2 * %a + 0 * 1 - %1 = mul i32 %b, 3 ; [#uses=1] -; CHECK: 3 * %b + 0 * 1 - %2 = shl i32 %d, 2 ; [#uses=1] -; CHECK: 4 * %d + 0 * 1 - %3 = add nsw i32 %0, 5 ; [#uses=1] -; CHECK: 2 * %a + 5 * 1 - %4 = add nsw i32 %3, %c ; [#uses=1] -; CHECK: 1 * %c + 2 * %a + 5 * 1 - %5 = add nsw i32 %4, %1 ; [#uses=1] -; CHECK: 1 * %c + 3 * %b + 2 * %a + 5 * 1 - %6 = add nsw i32 %5, %2 ; [#uses=1] -; CHECK: 1 * %c + 4 * %d + 3 * %b + 2 * %a + 5 * 1 - ret i32 %6 -} Removed: polly/trunk/test/AffineIterator/simple_1.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/AffineIterator/simple_1.ll?rev=144228&view=auto ============================================================================== --- polly/trunk/test/AffineIterator/simple_1.ll (original) +++ polly/trunk/test/AffineIterator/simple_1.ll (removed) @@ -1,24 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -print-scev-affine -analyze < %s | FileCheck %s - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define i32 @f(i32 %a, i32 %b, i32 %c, i64 %d, i8 signext %e, i32 %f, i32 %g, i32 %h) nounwind readnone { -entry: - %0 = mul i32 %a, 3 ; [#uses=1] - %1 = mul i32 %b, 5 ; [#uses=1] - %2 = mul i32 %1, %c ; [#uses=1] -; CHECK: 5 * (%b * %c) + 0 * 1 - %3 = mul i32 %2, %f ; [#uses=1] -; CHECK: 5 * (%b * %c * %f) + 0 * 1 - %4 = sext i8 %e to i32 ; [#uses=1] - %5 = shl i32 %4, 2 ; [#uses=1] - %6 = trunc i64 %d to i32 ; [#uses=1] - %7 = mul i32 %6, %h ; [#uses=1] - %8 = add nsw i32 %0, %g ; [#uses=1] - %9 = add nsw i32 %8, %5 ; [#uses=1] - %10 = add nsw i32 %9, %3 ; [#uses=1] - %11 = add nsw i32 %10, %7 ; [#uses=1] -; CHECK: 1 * %g + 1 * ((trunc i64 %d to i32) * %h) + 5 * (%b * %c * %f) + 4 * (sext i8 %e to i32) + 3 * %a + 0 * 1 - ret i32 %11 -} Removed: polly/trunk/test/AffineIterator/simple_loop.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/AffineIterator/simple_loop.ll?rev=144228&view=auto ============================================================================== --- polly/trunk/test/AffineIterator/simple_loop.ll (original) +++ polly/trunk/test/AffineIterator/simple_loop.ll (removed) @@ -1,25 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -print-scev-affine -analyze < %s | FileCheck %s - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d, i32* nocapture %x) nounwind { -entry: - br label %bb - -bb: ; preds = %bb, %entry - %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %bb ] ; [#uses=3] -; CHECK: 1 * {0,+,1}<%bb> + 0 * 1 - %scevgep = getelementptr i32* %x, i64 %indvar ; [#uses=1] -; CHECK: 4 * {0,+,1}<%bb> + 1 * %x + 0 * 1 - %i.04 = trunc i64 %indvar to i32 ; [#uses=1] -; CHECK: 1 * {0,+,1}<%bb> + 0 * 1 - store i32 %i.04, i32* %scevgep, align 4 - %indvar.next = add i64 %indvar, 1 ; [#uses=2] -; CHECK: 1 * {0,+,1}<%bb> + 1 * 1 - %exitcond = icmp eq i64 %indvar.next, 64 ; [#uses=1] - br i1 %exitcond, label %bb2, label %bb - -bb2: ; preds = %bb - ret i32 %a -} Removed: polly/trunk/test/AffineIterator/simple_nest.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/AffineIterator/simple_nest.ll?rev=144228&view=auto ============================================================================== --- polly/trunk/test/AffineIterator/simple_nest.ll (original) +++ polly/trunk/test/AffineIterator/simple_nest.ll (removed) @@ -1,38 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -print-scev-affine -analyze < %s | FileCheck %s - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d, [4 x i32]* nocapture %x) nounwind { -entry: - br label %bb2.preheader - -bb1: ; preds = %bb2.preheader, %bb1 - %indvar = phi i64 [ 0, %bb2.preheader ], [ %indvar.next, %bb1 ] ; [#uses=3] -; CHECK: 1 * {0,+,1}<%bb1> + 0 * 1 - %scevgep = getelementptr [4 x i32]* %x, i64 %indvar, i64 %0 ; [#uses=1] -; CHECK: 16 * {0,+,1}<%bb1> + 4 * {0,+,1}<%bb2.preheader> + 1 * %x + 0 * 1 - %tmp = mul i64 %indvar, %0 ; [#uses=1] -; CHECK: 1 * {0,+,{0,+,1}<%bb2.preheader>}<%bb1> + 0 * 1 - %tmp13 = trunc i64 %tmp to i32 ; [#uses=1] -; CHECK: 1 * {0,+,{0,+,1}<%bb2.preheader>}<%bb1> + 0 * 1 - store i32 %tmp13, i32* %scevgep, align 4 - %indvar.next = add i64 %indvar, 1 ; [#uses=2] -; CHECK: 1 * {0,+,1}<%bb1> + 1 * 1 - %exitcond = icmp eq i64 %indvar.next, 64 ; [#uses=1] - br i1 %exitcond, label %bb3, label %bb1 - -bb3: ; preds = %bb1 - %indvar.next12 = add i64 %0, 1 ; [#uses=2] -; CHECK: 1 * {0,+,1}<%bb2.preheader> + 1 * 1 - %exitcond14 = icmp eq i64 %indvar.next12, 64 ; [#uses=1] - br i1 %exitcond14, label %bb5, label %bb2.preheader - -bb2.preheader: ; preds = %bb3, %entry - %0 = phi i64 [ 0, %entry ], [ %indvar.next12, %bb3 ] ; [#uses=3] -; CHECK: 1 * {0,+,1}<%bb2.preheader> + 0 * 1 - br label %bb1 - -bb5: ; preds = %bb3 - ret i32 %a -} From grosser at fim.uni-passau.de Wed Nov 9 16:35:05 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:35:05 -0000 Subject: [llvm-commits] [polly] r144230 - in /polly/trunk: include/polly/TempScopInfo.h lib/MayAliasSet.cpp Message-ID: <20111109223505.6EF2C1BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:35:05 2011 New Revision: 144230 URL: http://llvm.org/viewvc/llvm-project?rev=144230&view=rev Log: Further remove now invalid SCEVAffFunc features. This also removes the construction of MayAliasSets that became invalid when removing the use of SCEVAffFunc. Modified: polly/trunk/include/polly/TempScopInfo.h polly/trunk/lib/MayAliasSet.cpp Modified: polly/trunk/include/polly/TempScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/TempScopInfo.h?rev=144230&r1=144229&r2=144230&view=diff ============================================================================== --- polly/trunk/include/polly/TempScopInfo.h (original) +++ polly/trunk/include/polly/TempScopInfo.h Wed Nov 9 16:35:05 2011 @@ -36,9 +36,6 @@ /// /// A helper class for collect affine function information class SCEVAffFunc { - // Temporary hack - friend class TempScopInfo; - public: // The scalar evolution expression from which we derived this affine // expression. @@ -58,7 +55,6 @@ // The base address of the address SCEV, if the Value is a pointer, this is // an array access, otherwise, this is a value access. // And the Write/Read modifier - Value *BaseAddr; unsigned ElemBytes : 28; SCEVAffFuncType FuncType : 3; @@ -67,8 +63,7 @@ /// condition type explicit SCEVAffFunc(SCEVAffFuncType Type, const SCEV *OriginalSCEV, unsigned elemBytes = 0) - : OriginalSCEV(OriginalSCEV), BaseAddr(0), - ElemBytes(elemBytes), FuncType(Type) {} + : OriginalSCEV(OriginalSCEV), ElemBytes(elemBytes), FuncType(Type) {} enum SCEVAffFuncType getType() const { return FuncType; } @@ -77,8 +72,6 @@ } bool isRead() const { return FuncType == ReadMem; } - - const Value *getBaseAddr() const { return BaseAddr; } }; class Comparison { Modified: polly/trunk/lib/MayAliasSet.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/MayAliasSet.cpp?rev=144230&r1=144229&r2=144230&view=diff ============================================================================== --- polly/trunk/lib/MayAliasSet.cpp (original) +++ polly/trunk/lib/MayAliasSet.cpp Wed Nov 9 16:35:05 2011 @@ -44,49 +44,4 @@ } void MayAliasSetInfo::buildMayAliasSets(TempScop &Scop, AliasAnalysis &AA) { - AliasSetTracker AST(AA); - Region &MaxR = Scop.getMaxRegion(); - - // Find out all base pointers that appeared in Scop and build the Alias set. - // Note: We may build the alias sets while we are building access functions - // to obtain better performance. - for (Region::block_iterator I = MaxR.block_begin(), E = MaxR.block_end(); - I != E; ++I) { - BasicBlock *BB = I->getNodeAs(); - if (const AccFuncSetType *AFS = Scop.getAccessFunctions(BB)) { - for (AccFuncSetType::const_iterator AI = AFS->begin(), AE = AFS->end(); - AI != AE; ++AI) { - const SCEVAffFunc &AccFunc = AI->first; - Instruction *Inst = AI->second; - Value *BaseAddr = const_cast(AccFunc.getBaseAddr()); - - AST.add(BaseAddr, AliasAnalysis::UnknownSize, - Inst->getMetadata(LLVMContext::MD_tbaa)); - } - } - } - - // Build the may-alias set with the AliasSetTracker. - for (AliasSetTracker::iterator I = AST.begin(), E = AST.end(); I != E; ++I) { - AliasSet &AS = *I; - - // Ignore the dummy alias set. - if (AS.isForwardingAliasSet()) continue; - - // The most simple case: All pointers in the set must-alias each others. - if (AS.isMustAlias()) { - MayAliasSet *MayAS = new (MayASAllocator.Allocate()) MayAliasSet(); - - for (AliasSet::iterator PI = AS.begin(), PE = AS.end(); PI != PE; ++PI) { - Value *Ptr = PI.getPointer(); - - MayAS->addMustAliasPtr(Ptr); - BasePtrMap.insert(std::make_pair(Ptr, MayAS)); - } - - continue; - } - - assert(0 && "SCoPDetection pass should not allow May-Alias set!"); - } } From grosser at fim.uni-passau.de Wed Nov 9 16:35:10 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:35:10 -0000 Subject: [llvm-commits] [polly] r144231 - in /polly/trunk: include/polly/ScopInfo.h include/polly/TempScopInfo.h lib/Analysis/ScopInfo.cpp lib/Analysis/TempScopInfo.cpp Message-ID: <20111109223510.47FA51BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:35:09 2011 New Revision: 144231 URL: http://llvm.org/viewvc/llvm-project?rev=144231&view=rev Log: TempScop: Rename SCEVAffFunc to IRAccess The SCEVAffFunc is now only used to express memory accesses. Give it a proper name and rework the class such that this is obvious. Modified: polly/trunk/include/polly/ScopInfo.h polly/trunk/include/polly/TempScopInfo.h polly/trunk/lib/Analysis/ScopInfo.cpp polly/trunk/lib/Analysis/TempScopInfo.cpp Modified: polly/trunk/include/polly/ScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/ScopInfo.h?rev=144231&r1=144230&r2=144231&view=diff ============================================================================== --- polly/trunk/include/polly/ScopInfo.h (original) +++ polly/trunk/include/polly/ScopInfo.h Wed Nov 9 16:35:09 2011 @@ -48,6 +48,7 @@ namespace polly { +class IRAccess; class Scop; class ScopStmt; class ScopInfo; @@ -103,17 +104,17 @@ /// Updated access relation read from JSCOP file. isl_map *newAccessRelation; public: - // @brief Create an affine memory access. + // @brief Create a memory access from an access in LLVM-IR. // - // @param AffFunc The access function. - // @param Statement The Statement that contains this access. + // @param Access The memory access. + // @param Statement The statement that contains the access. // @param SE The ScalarEvolution analysis. - MemoryAccess(const SCEVAffFunc &AffFunc, ScopStmt *Statement); + MemoryAccess(const IRAccess &Access, ScopStmt *Statement); - // @brief Create a read all access. + // @brief Create a memory access that reads a complete memory object. // - // @param BaseAddress The base address of the memory accessed. - // @param Statement The Statement that contains this access. + // @param BaseAddress The base address of the memory object. + // @param Statement The statement that contains this access. MemoryAccess(const Value *BaseAddress, ScopStmt *Statement); ~MemoryAccess(); Modified: polly/trunk/include/polly/TempScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/TempScopInfo.h?rev=144231&r1=144230&r2=144231&view=diff ============================================================================== --- polly/trunk/include/polly/TempScopInfo.h (original) +++ polly/trunk/include/polly/TempScopInfo.h Wed Nov 9 16:35:09 2011 @@ -32,46 +32,30 @@ class MayAliasSetInfo; //===---------------------------------------------------------------------===// -/// @brief Affine function represent in llvm SCEV expressions. -/// -/// A helper class for collect affine function information -class SCEVAffFunc { +/// @brief A memory access described by a SCEV expression and the access type. +class IRAccess { public: - // The scalar evolution expression from which we derived this affine - // expression. - // - // We will use it to directly translation from scalar expressions to the - // corresponding isl objects. As soon as this finished, most of SCEVAffFunc - // can be removed. - const SCEV *OriginalSCEV; + // The SCEV of this memory access. + const SCEV *Scev; // The type of the scev affine function - enum SCEVAffFuncType { - ReadMem, - WriteMem - }; + enum TypeKind { READ, WRITE }; private: - // The base address of the address SCEV, if the Value is a pointer, this is - // an array access, otherwise, this is a value access. - // And the Write/Read modifier - unsigned ElemBytes : 28; - SCEVAffFuncType FuncType : 3; + unsigned ElemBytes; + TypeKind Type; public: - /// @brief Create a new SCEV affine function with memory access type or - /// condition type - explicit SCEVAffFunc(SCEVAffFuncType Type, const SCEV *OriginalSCEV, - unsigned elemBytes = 0) - : OriginalSCEV(OriginalSCEV), ElemBytes(elemBytes), FuncType(Type) {} + explicit IRAccess (TypeKind Type, const SCEV *Scev, unsigned elemBytes) + : Scev(Scev), ElemBytes(elemBytes), Type(Type) {} - enum SCEVAffFuncType getType() const { return FuncType; } + enum TypeKind getType() const { return Type; } - unsigned getElemSizeInBytes() const { - return ElemBytes; - } + const SCEV *getSCEV() const { return Scev; } + + unsigned getElemSizeInBytes() const { return ElemBytes; } - bool isRead() const { return FuncType == ReadMem; } + bool isRead() const { return Type == READ; } }; class Comparison { @@ -108,7 +92,7 @@ /// Mapping BBs to its condition constrains typedef std::map BBCondMapType; -typedef std::vector > AccFuncSetType; +typedef std::vector > AccFuncSetType; typedef std::map AccFuncMapType; //===---------------------------------------------------------------------===// Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144231&r1=144230&r2=144231&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Wed Nov 9 16:35:09 2011 @@ -324,13 +324,13 @@ return isl_basic_map_universe(Space); } -MemoryAccess::MemoryAccess(const SCEVAffFunc &AffFunc, ScopStmt *Statement) { +MemoryAccess::MemoryAccess(const IRAccess &Access, ScopStmt *Statement) { newAccessRelation = NULL; - Type = AffFunc.isRead() ? Read : Write; + Type = Access.isRead() ? Read : Write; statement = Statement; Value *TmpBaseAddress = NULL; - isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, AffFunc.OriginalSCEV, + isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, Access.getSCEV(), &TmpBaseAddress); BaseAddr = TmpBaseAddress; @@ -345,7 +345,7 @@ // again. isl_int v; isl_int_init(v); - isl_int_set_si(v, AffFunc.getElemSizeInBytes()); + isl_int_set_si(v, Access.getElemSizeInBytes()); Affine = isl_pw_aff_scale_down(Affine, v); isl_int_clear(v); Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144231&r1=144230&r2=144231&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Wed Nov 9 16:35:09 2011 @@ -87,20 +87,20 @@ Instruction &Inst = *I; if (isa(&Inst) || isa(&Inst)) { unsigned Size; - enum SCEVAffFunc::SCEVAffFuncType Type; + enum IRAccess::TypeKind Type; if (LoadInst *Load = dyn_cast(&Inst)) { Size = TD->getTypeStoreSize(Load->getType()); - Type = SCEVAffFunc::ReadMem; + Type = IRAccess::READ; } else { StoreInst *Store = cast(&Inst); Size = TD->getTypeStoreSize(Store->getValueOperand()->getType()); - Type = SCEVAffFunc::WriteMem; + Type = IRAccess::WRITE; } const SCEV *AccessFunction = SE->getSCEV(getPointerOperand(Inst)); - Functions.push_back( - std::make_pair(SCEVAffFunc(Type, AccessFunction, Size), &Inst)); + Functions.push_back(std::make_pair(IRAccess(Type, AccessFunction, Size), + &Inst)); } } From grosser at fim.uni-passau.de Wed Nov 9 16:35:15 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:35:15 -0000 Subject: [llvm-commits] [polly] r144232 - in /polly/trunk: include/polly/TempScopInfo.h lib/Analysis/TempScopInfo.cpp test/ScopInfo/simple_loop_0.ll Message-ID: <20111109223515.BFC691BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:35:15 2011 New Revision: 144232 URL: http://llvm.org/viewvc/llvm-project?rev=144232&view=rev Log: Remove unused parameters from TempScop Removed: polly/trunk/test/ScopInfo/simple_loop_0.ll Modified: polly/trunk/include/polly/TempScopInfo.h polly/trunk/lib/Analysis/TempScopInfo.cpp Modified: polly/trunk/include/polly/TempScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/TempScopInfo.h?rev=144232&r1=144231&r2=144232&view=diff ============================================================================== --- polly/trunk/include/polly/TempScopInfo.h (original) +++ polly/trunk/include/polly/TempScopInfo.h Wed Nov 9 16:35:15 2011 @@ -104,9 +104,6 @@ // The Region. Region &R; - // Parameters used in this Scop. - ParamSetType Params; - // The max loop depth of this Scop unsigned MaxLoopDepth; @@ -130,14 +127,6 @@ public: ~TempScop(); - /// @name Information about this Temporary Scop. - /// - //@{ - /// @brief Get the parameters used in this Scop. - /// - /// @return The parameters use in region. - ParamSetType &getParamSet() { return Params; } - /// @brief Get the maximum Region contained by this Scop. /// /// @return The maximum Region contained by this Scop. @@ -268,8 +257,7 @@ bool isReduction(BasicBlock &BB); - void buildAccessFunctions(Region &RefRegion, ParamSetType &Params, - BasicBlock &BB); + void buildAccessFunctions(Region &RefRegion, BasicBlock &BB); void buildLoopBounds(TempScop &Scop); Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144232&r1=144231&r2=144232&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Wed Nov 9 16:35:15 2011 @@ -63,13 +63,8 @@ } void TempScop::print(raw_ostream &OS, ScalarEvolution *SE, LoopInfo *LI) const { - OS << "Scop: " << R.getNameStr() << "\tParameters: ("; - // Print Parameters. - for (ParamSetType::const_iterator PI = Params.begin(), PE = Params.end(); - PI != PE; ++PI) - OS << **PI << ", "; - - OS << "), Max Loop Depth: "<< MaxLoopDepth <<"\n"; + OS << "Scop: " << R.getNameStr() << ", Max Loop Depth: "<< MaxLoopDepth + << "\n"; printDetail(OS, SE, LI, &R, 0); } @@ -79,8 +74,7 @@ unsigned ind) const { } -void TempScopInfo::buildAccessFunctions(Region &R, ParamSetType &Parameter, - BasicBlock &BB) { +void TempScopInfo::buildAccessFunctions(Region &R, BasicBlock &BB) { AccFuncSetType Functions; for (BasicBlock::iterator I = BB.begin(), E = --BB.end(); I != E; ++I) { @@ -226,7 +220,7 @@ for (Region::block_iterator I = R.block_begin(), E = R.block_end(); I != E; ++I) { BasicBlock *BB = I->getNodeAs(); - buildAccessFunctions(R, TScop->getParamSet(), *BB); + buildAccessFunctions(R, *BB); buildCondition(BB, R.getEntry(), *TScop); } Removed: polly/trunk/test/ScopInfo/simple_loop_0.ll URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/simple_loop_0.ll?rev=144231&view=auto ============================================================================== --- polly/trunk/test/ScopInfo/simple_loop_0.ll (original) +++ polly/trunk/test/ScopInfo/simple_loop_0.ll (removed) @@ -1,33 +0,0 @@ -; RUN: opt %loadPolly %defaultOpts -polly-analyze-ir -analyze %s | FileCheck %s - -;void f(long a[], long N) { -; long i; -; for (i = 0; i < 128; ++i) -; a[i] = a[i] - a[i + 2]; -;} - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-unknown-linux-gnu" - -define void @f(i64* nocapture %a, i64 %N) nounwind { -entry: - br label %bb - -bb: ; preds = %bb, %entry - %i.03 = phi i64 [ 0, %entry ], [ %3, %bb ] ; [#uses=3] - %scevgep = getelementptr i64* %a, i64 %i.03 ; [#uses=2] - %tmp = add i64 %i.03, 2 ; [#uses=1] - %scevgep4 = getelementptr i64* %a, i64 %tmp ; [#uses=1] - %0 = load i64* %scevgep, align 8 ; [#uses=1] - %1 = load i64* %scevgep4, align 8 ; [#uses=1] - %2 = sub i64 %0, %1 ; [#uses=1] - store i64 %2, i64* %scevgep, align 8 - %3 = add nsw i64 %i.03, 1 ; [#uses=2] - %exitcond = icmp eq i64 %3, 128 ; [#uses=1] - br i1 %exitcond, label %return, label %bb - -return: ; preds = %bb - ret void -} - -; CHECK: Scop: bb => return Parameters: () From grosser at fim.uni-passau.de Wed Nov 9 16:35:19 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 09 Nov 2011 22:35:19 -0000 Subject: [llvm-commits] [polly] r144233 - /polly/trunk/include/polly/TempScopInfo.h Message-ID: <20111109223519.A75A71BE001@llvm.org> Author: grosser Date: Wed Nov 9 16:35:19 2011 New Revision: 144233 URL: http://llvm.org/viewvc/llvm-project?rev=144233&view=rev Log: Remove unused function declaration Modified: polly/trunk/include/polly/TempScopInfo.h Modified: polly/trunk/include/polly/TempScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/TempScopInfo.h?rev=144233&r1=144232&r2=144233&view=diff ============================================================================== --- polly/trunk/include/polly/TempScopInfo.h (original) +++ polly/trunk/include/polly/TempScopInfo.h Wed Nov 9 16:35:19 2011 @@ -255,8 +255,6 @@ // of Scop. TempScop *buildTempScop(Region &R); - bool isReduction(BasicBlock &BB); - void buildAccessFunctions(Region &RefRegion, BasicBlock &BB); void buildLoopBounds(TempScop &Scop); From dmalyshev at accesssoftek.com Wed Nov 9 16:41:57 2011 From: dmalyshev at accesssoftek.com (Danil Malyshev) Date: Wed, 9 Nov 2011 14:41:57 -0800 Subject: [llvm-commits] MachOObjectFile fix functions In-Reply-To: References: <6AE1604EE3EC5F4296C096518C6B77EE1805B07349@mail.accesssoftek.com> <6AE1604EE3EC5F4296C096518C6B77EE1805C8FA97@mail.accesssoftek.com> Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE18123D6BC3@mail.accesssoftek.com> Hello Owen, > I don't like this. Getting symbol virtual addresses is one of the most common operations we do in, say, llvm-objdump.cpp or MachODump.cpp. I think this will make that code needlessly complex and non-obvious. Ok, I agree. > I don't particularly mind standardizing on this as the definition for "getOffset" methods, but it doesn't seem particularly useful to me either. Why require a two-stage lookup (section offset + symbol offset from section) rather than just defining it to return a file offset? The symbol iterator iterate all symbols from all sections, so it make sense if symbol.getOffset() will returns the file offset. But we get relocations only for selected section, so relocation.getOffset() should return offset from this section. In addition we can get section virtual address or section offset one time and use it for each relocation in this section. So, please find attached the changed patch which following changes: - getSymbolOffset(), getSymbolAddress(), getRelocationAddress() returns same result for ELFObjectFile, MachOObjectFile and COFFObjectFile. - added getRelocationOffset() - fixed MachOObjectFile::getSymbolSize() - fixed MachOObjectFile::getSymbolSection() - fixed MachOObjectFile::getSymbolOffset() for symbols without section data. Regards, Danil -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/bf8e37d7/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: ObjectFile_fix_functions-02.patch Type: application/octet-stream Size: 12453 bytes Desc: ObjectFile_fix_functions-02.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/bf8e37d7/attachment.obj From criswell at uiuc.edu Wed Nov 9 16:42:49 2011 From: criswell at uiuc.edu (John Criswell) Date: Wed, 09 Nov 2011 22:42:49 -0000 Subject: [llvm-commits] [poolalloc] r144234 - in /poolalloc/trunk: include/dsa/CStdLib.h lib/DSA/StdLibPass.cpp Message-ID: <20111109224249.8987E1BE001@llvm.org> Author: criswell Date: Wed Nov 9 16:42:49 2011 New Revision: 144234 URL: http://llvm.org/viewvc/llvm-project?rev=144234&view=rev Log: Have the DSA StdLib pass recognize the invalid free checking functions and pool_fgets(). Modified: poolalloc/trunk/include/dsa/CStdLib.h poolalloc/trunk/lib/DSA/StdLibPass.cpp Modified: poolalloc/trunk/include/dsa/CStdLib.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/CStdLib.h?rev=144234&r1=144233&r2=144234&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/CStdLib.h (original) +++ poolalloc/trunk/include/dsa/CStdLib.h Wed Nov 9 16:42:49 2011 @@ -45,6 +45,7 @@ { "pool_index", 1 }, { "pool_rindex", 1 }, { "pool_strcasestr", 2 }, + { "pool_fgets", 1 }, { 0, 0 } }; Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=144234&r1=144233&r2=144234&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Wed Nov 9 16:42:49 2011 @@ -83,6 +83,7 @@ #define NRET_YNARGS {0,1,0,0,0,0,0,0,0,0} #define YRET_YNARGS {1,1,0,0,0,0,0,0,0,0} #define YRET_NNYARGS {1,0,0,1,1,1,1,1,1,1} +#define YRET_YNYARGS {1,1,0,1,1,1,1,1,1,1} #define NRET_NNYARGS {0,0,0,1,1,1,1,1,1,1} #define YRET_NNYNARGS {1,0,0,1,0,0,0,0,0,0} #define NRET_NNNYARGS {0,0,0,0,1,1,1,1,1,1} @@ -260,6 +261,8 @@ {"fastlscheck", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckalign", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckalignui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"poolcheck_free", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"poolcheck_freeui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"funccheck", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"funccheckui", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, @@ -268,6 +271,8 @@ {"fastlscheck_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckalign_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"poolcheckalignui_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"poolcheck_free_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"poolcheck_freeui_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"funccheck_debug", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"funccheckui_debug",{NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, @@ -338,6 +343,9 @@ {"pool___fprintf_chk", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"pool___sprintf_chk", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"pool___snprintf_chk", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + + // Important C I/O functions + {"pool_fgets", {NRET_NNYARGS, YRET_YNYARGS, NRET_NARGS, NRET_NARGS, true}}, // Type Checks {"trackArgvType", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, From nicholas at mxc.ca Wed Nov 9 16:45:04 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 09 Nov 2011 22:45:04 -0000 Subject: [llvm-commits] [llvm] r144236 - /llvm/trunk/lib/Analysis/DIBuilder.cpp Message-ID: <20111109224504.83B8C1BE001@llvm.org> Author: nicholas Date: Wed Nov 9 16:45:04 2011 New Revision: 144236 URL: http://llvm.org/viewvc/llvm-project?rev=144236&view=rev Log: Fix typo in comment. Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=144236&r1=144235&r2=144236&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DIBuilder.cpp (original) +++ llvm/trunk/lib/Analysis/DIBuilder.cpp Wed Nov 9 16:45:04 2011 @@ -189,7 +189,7 @@ return DIType(MDNode::get(VMContext, Elts)); } -/// createQaulifiedType - Create debugging information entry for a qualified +/// createQualifiedType - Create debugging information entry for a qualified /// type, e.g. 'const int'. DIType DIBuilder::createQualifiedType(unsigned Tag, DIType FromTy) { // Qualified types are encoded in DIDerivedType format. From pdox at google.com Wed Nov 9 17:02:11 2011 From: pdox at google.com (David Meyer) Date: Wed, 9 Nov 2011 15:02:11 -0800 Subject: [llvm-commits] [llvm] r144188 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll In-Reply-To: <4EBAF9A4.4080901@free.fr> References: <20111109142048.965491BE001@llvm.org> <4EBAF66F.7030708@free.fr> <04A23D00-737D-4AFD-9D97-3958A728AFA2@apple.com> <4EBAF9A4.4080901@free.fr> Message-ID: Duncan, Is the patch itself really the problem, or is it just tickling another bug? If it's exposing a bug somewhere else, it seems counter-productive to revert this commit and pretend everything is OK. - pdox From eli.friedman at gmail.com Wed Nov 9 17:04:12 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 9 Nov 2011 15:04:12 -0800 Subject: [llvm-commits] [PATCH][Review request] IEEE quad software emulation library call In-Reply-To: <95DD8BA8AA50B14BBFB86A1D541FA3809EAB2E71@exchdb03.mips.com> References: <95DD8BA8AA50B14BBFB86A1D541FA3809EAB2E46@exchdb03.mips.com> <95DD8BA8AA50B14BBFB86A1D541FA3809EAB2E71@exchdb03.mips.com> Message-ID: On Wed, Nov 9, 2011 at 2:16 PM, Hatanaka, Akira wrote: > I am not sure if I understand your first comment. Is it the trailing whitespace or incorrect indentation? > When I open my patch in an editor, it looks like what you see in the following link: > > http://comments.gmane.org/gmane.comp.compilers.llvm.cvs/102510 > > I didn't find any tabs either. I was just referring to the missing space after the comma. Sorry about the confusion. > As for your second comment, I was copying what gcc-mips64 was doing. > When I compile this code with gcc-mips64, > > typedef long double LD; > LD g0, g1, g2; > > LD f0() { > ?return g0 + g1; > } > > I get this code: > > ? ? ? ?ld ? ? ?$2,%got_disp(g0)($28) > ? ? ? ?ld ? ? ?$25,%call16(__addtf3)($28) > ? ? ? ?ldc1 ? ?$f12,0($2) > ? ? ? ?sd ? ? ?$31,8($sp) > ? ? ? ?ldc1 ? ?$f13,8($2) > ? ? ? ?ld ? ? ?$2,%got_disp(g1)($28) > ? ? ? ?ldc1 ? ?$f14,0($2) > ? ? ? ?.reloc ?1f,R_MIPS_JALR,__addtf3 > 1: ? ? ?jalr ? ?$25 > ? ? ? ?ldc1 ? ?$f15,8($2) > > So g0 is passed in (f12, f13) and g1 is passed in (f14, f15). These are all FP registers. > Is the choice of register types platform dependent? Well, the fact that it's in two f64 registers is really a property of the calling convention, not a fundamental property of f128... unlike f128, ppcf128 is actually a pair of f64's, so it isn't really the best example to follow. I'm not sure the calling convention handling code can handle this properly at the moment, though... if nobody else has a suggestion, it's okay as-is, I guess, but at least add a comment to explain what is going on. > llc emits the code I expect to see after applying this patch for add, sub, mul and div. > I haven't made the changes needed for type conversions or fp constant operations. Okay. In that case, tests would be nice. :) -Eli From peter_cooper at apple.com Wed Nov 9 17:07:35 2011 From: peter_cooper at apple.com (Pete Cooper) Date: Wed, 09 Nov 2011 23:07:35 -0000 Subject: [llvm-commits] [llvm] r144239 - in /llvm/trunk: lib/Transforms/Scalar/DeadStoreElimination.cpp test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll Message-ID: <20111109230735.54DFF1BE001@llvm.org> Author: pete Date: Wed Nov 9 17:07:35 2011 New Revision: 144239 URL: http://llvm.org/viewvc/llvm-project?rev=144239&view=rev Log: DeadStoreElimination can now trim the size of a store if the end of the store is dead. Currently checks alignment and killing stores on a power of 2 boundary as this is likely to trim the size of the earlier store without breaking large vector stores into scalar ones. Fixes Added: llvm/trunk/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=144239&r1=144238&r2=144239&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Wed Nov 9 17:07:35 2011 @@ -241,6 +241,24 @@ } } + +/// isShortenable - Returns true if this instruction can be safely shortened in +/// length. +static bool isShortenable(Instruction *I) { + // Don't shorten stores for now + if (isa(I)) + return false; + + IntrinsicInst *II = cast(I); + switch (II->getIntrinsicID()) { + default: return false; + case Intrinsic::memset: + case Intrinsic::memcpy: + // Do shorten memory intrinsics. + return true; + } +} + /// getStoredPointerOperand - Return the pointer that is being written to. static Value *getStoredPointerOperand(Instruction *I) { if (StoreInst *SI = dyn_cast(I)) @@ -295,11 +313,24 @@ return false; } -/// isCompleteOverwrite - Return true if a store to the 'Later' location +namespace { + enum OverwriteResult + { + OverwriteComplete, + OverwriteEnd, + OverwriteUnknown + }; +} + +/// isOverwrite - Return 'OverwriteComplete' if a store to the 'Later' location /// completely overwrites a store to the 'Earlier' location. -static bool isCompleteOverwrite(const AliasAnalysis::Location &Later, - const AliasAnalysis::Location &Earlier, - AliasAnalysis &AA) { +/// 'OverwriteEnd' if the end of the 'Earlier' location is completely +/// overwritten by 'Later', or 'OverwriteUnknown' if nothing can be determined +static OverwriteResult isOverwrite(const AliasAnalysis::Location &Later, + const AliasAnalysis::Location &Earlier, + AliasAnalysis &AA, + int64_t& EarlierOff, + int64_t& LaterOff) { const Value *P1 = Earlier.Ptr->stripPointerCasts(); const Value *P2 = Later.Ptr->stripPointerCasts(); @@ -313,23 +344,24 @@ // If we have no TargetData information around, then the size of the store // is inferrable from the pointee type. If they are the same type, then // we know that the store is safe. - if (AA.getTargetData() == 0) - return Later.Ptr->getType() == Earlier.Ptr->getType(); - return false; + if (AA.getTargetData() == 0 && + Later.Ptr->getType() == Earlier.Ptr->getType()) + return OverwriteComplete; + + return OverwriteUnknown; } // Make sure that the Later size is >= the Earlier size. - if (Later.Size < Earlier.Size) - return false; - return true; + if (Later.Size >= Earlier.Size) + return OverwriteComplete; } // Otherwise, we have to have size information, and the later store has to be // larger than the earlier one. if (Later.Size == AliasAnalysis::UnknownSize || Earlier.Size == AliasAnalysis::UnknownSize || - Later.Size <= Earlier.Size || AA.getTargetData() == 0) - return false; + AA.getTargetData() == 0) + return OverwriteUnknown; // Check to see if the later store is to the entire object (either a global, // an alloca, or a byval argument). If so, then it clearly overwrites any @@ -342,26 +374,27 @@ // If we can't resolve the same pointers to the same object, then we can't // analyze them at all. if (UO1 != UO2) - return false; + return OverwriteUnknown; // If the "Later" store is to a recognizable object, get its size. if (isObjectPointerWithTrustworthySize(UO2)) { uint64_t ObjectSize = TD.getTypeAllocSize(cast(UO2->getType())->getElementType()); if (ObjectSize == Later.Size) - return true; + return OverwriteComplete; } // Okay, we have stores to two completely different pointers. Try to // decompose the pointer into a "base + constant_offset" form. If the base // pointers are equal, then we can reason about the two stores. - int64_t EarlierOff = 0, LaterOff = 0; + EarlierOff = 0; + LaterOff = 0; const Value *BP1 = GetPointerBaseWithConstantOffset(P1, EarlierOff, TD); const Value *BP2 = GetPointerBaseWithConstantOffset(P2, LaterOff, TD); // If the base pointers still differ, we have two completely different stores. if (BP1 != BP2) - return false; + return OverwriteUnknown; // The later store completely overlaps the earlier store if: // @@ -379,11 +412,25 @@ // // We have to be careful here as *Off is signed while *.Size is unsigned. if (EarlierOff >= LaterOff && + Later.Size > Earlier.Size && uint64_t(EarlierOff - LaterOff) + Earlier.Size <= Later.Size) - return true; + return OverwriteComplete; + + // The other interesting case is if the later store overwrites the end of + // the earlier store + // + // |--earlier--| + // |-- later --| + // + // In this case we may want to trim the size of earlier to avoid generating + // writes to addresses which will definitely be overwritten later + if (LaterOff > EarlierOff && + LaterOff < int64_t(EarlierOff + Earlier.Size) && + LaterOff + Later.Size >= EarlierOff + Earlier.Size) + return OverwriteEnd; // Otherwise, they don't completely overlap. - return false; + return OverwriteUnknown; } /// isPossibleSelfRead - If 'Inst' might be a self read (i.e. a noop copy of a @@ -507,22 +554,52 @@ // If we find a write that is a) removable (i.e., non-volatile), b) is // completely obliterated by the store to 'Loc', and c) which we know that // 'Inst' doesn't load from, then we can remove it. - if (isRemovable(DepWrite) && isCompleteOverwrite(Loc, DepLoc, *AA) && + if (isRemovable(DepWrite) && !isPossibleSelfRead(Inst, Loc, DepWrite, *AA)) { - DEBUG(dbgs() << "DSE: Remove Dead Store:\n DEAD: " - << *DepWrite << "\n KILLER: " << *Inst << '\n'); - - // Delete the store and now-dead instructions that feed it. - DeleteDeadInstruction(DepWrite, *MD); - ++NumFastStores; - MadeChange = true; + int64_t InstWriteOffset, DepWriteOffset; + OverwriteResult OR = isOverwrite(Loc, DepLoc, *AA, + DepWriteOffset, InstWriteOffset); + if (OR == OverwriteComplete) { + DEBUG(dbgs() << "DSE: Remove Dead Store:\n DEAD: " + << *DepWrite << "\n KILLER: " << *Inst << '\n'); - // DeleteDeadInstruction can delete the current instruction in loop - // cases, reset BBI. - BBI = Inst; - if (BBI != BB.begin()) - --BBI; - break; + // Delete the store and now-dead instructions that feed it. + DeleteDeadInstruction(DepWrite, *MD); + ++NumFastStores; + MadeChange = true; + + // DeleteDeadInstruction can delete the current instruction in loop + // cases, reset BBI. + BBI = Inst; + if (BBI != BB.begin()) + --BBI; + break; + } else if (OR == OverwriteEnd && isShortenable(DepWrite)) { + // TODO: base this on the target vector size so that if the earlier + // store was too small to get vector writes anyway then its likely + // a good idea to shorten it + // Power of 2 vector writes are probably always a bad idea to optimize + // as any store/memset/memcpy is likely using vector instructions so + // shortening it to not vector size is likely to be slower + MemIntrinsic* DepIntrinsic = cast(DepWrite); + unsigned DepWriteAlign = DepIntrinsic->getAlignment(); + if (llvm::isPowerOf2_64(InstWriteOffset) || + ((DepWriteAlign != 0) && InstWriteOffset % DepWriteAlign == 0)) { + + DEBUG(dbgs() << "DSE: Remove Dead Store:\n OW END: " + << *DepWrite << "\n KILLER (offset " + << InstWriteOffset << ", " + << DepLoc.Size << ")" + << *Inst << '\n'); + + Value* DepWriteLength = DepIntrinsic->getLength(); + Value* TrimmedLength = ConstantInt::get(DepWriteLength->getType(), + InstWriteOffset - + DepWriteOffset); + DepIntrinsic->setLength(TrimmedLength); + MadeChange = true; + } + } } // If this is a may-aliased store that is clobbering the store value, we Added: llvm/trunk/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll?rev=144239&view=auto ============================================================================== --- llvm/trunk/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll (added) +++ llvm/trunk/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll Wed Nov 9 17:07:35 2011 @@ -0,0 +1,78 @@ +; RUN: opt < %s -basicaa -dse -S | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +%struct.vec2 = type { <4 x i32>, <4 x i32> } +%struct.vec2plusi = type { <4 x i32>, <4 x i32>, i32 } + + at glob1 = global %struct.vec2 zeroinitializer, align 16 + at glob2 = global %struct.vec2plusi zeroinitializer, align 16 + +define void @write24to28(i32* nocapture %p) nounwind uwtable ssp { +; CHECK: @write24to28 +entry: + %arrayidx0 = getelementptr inbounds i32* %p, i64 1 + %p3 = bitcast i32* %arrayidx0 to i8* +; CHECK: call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 24, i32 4, i1 false) + call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 28, i32 4, i1 false) + %arrayidx1 = getelementptr inbounds i32* %p, i64 7 + store i32 1, i32* %arrayidx1, align 4 + ret void +} + +define void @write28to32(i32* nocapture %p) nounwind uwtable ssp { +; CHECK: @write28to32 +entry: + %p3 = bitcast i32* %p to i8* +; CHECK: call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 28, i32 4, i1 false) + call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 32, i32 4, i1 false) + %arrayidx1 = getelementptr inbounds i32* %p, i64 7 + store i32 1, i32* %arrayidx1, align 4 + ret void +} + +define void @dontwrite28to32memset(i32* nocapture %p) nounwind uwtable ssp { +; CHECK: @dontwrite28to32memset +entry: + %p3 = bitcast i32* %p to i8* +; CHECK: call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 32, i32 16, i1 false) + call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 32, i32 16, i1 false) + %arrayidx1 = getelementptr inbounds i32* %p, i64 7 + store i32 1, i32* %arrayidx1, align 4 + ret void +} + +define void @write32to36(%struct.vec2plusi* nocapture %p) nounwind uwtable ssp { +; CHECK: @write32to36 +entry: + %0 = bitcast %struct.vec2plusi* %p to i8* +; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2plusi* @glob2 to i8*), i64 32, i32 16, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2plusi* @glob2 to i8*), i64 36, i32 16, i1 false) + %c = getelementptr inbounds %struct.vec2plusi* %p, i64 0, i32 2 + store i32 1, i32* %c, align 4 + ret void +} + +define void @write16to32(%struct.vec2* nocapture %p) nounwind uwtable ssp { +; CHECK: @write16to32 +entry: + %0 = bitcast %struct.vec2* %p to i8* +; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2* @glob1 to i8*), i64 16, i32 16, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2* @glob1 to i8*), i64 32, i32 16, i1 false) + %c = getelementptr inbounds %struct.vec2* %p, i64 0, i32 1 + store <4 x i32> , <4 x i32>* %c, align 4 + ret void +} + +define void @dontwrite28to32memcpy(%struct.vec2* nocapture %p) nounwind uwtable ssp { +; CHECK: @dontwrite28to32memcpy +entry: + %0 = bitcast %struct.vec2* %p to i8* +; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2* @glob1 to i8*), i64 32, i32 16, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2* @glob1 to i8*), i64 32, i32 16, i1 false) + %arrayidx1 = getelementptr inbounds %struct.vec2* %p, i64 0, i32 0, i64 7 + store i32 1, i32* %arrayidx1, align 4 + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind From eli.friedman at gmail.com Wed Nov 9 17:36:02 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 09 Nov 2011 23:36:02 -0000 Subject: [llvm-commits] [llvm] r144241 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll Message-ID: <20111109233602.7676B1BE001@llvm.org> Author: efriedma Date: Wed Nov 9 17:36:02 2011 New Revision: 144241 URL: http://llvm.org/viewvc/llvm-project?rev=144241&view=rev Log: Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM. Added: llvm/trunk/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=144241&r1=144240&r2=144241&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Nov 9 17:36:02 2011 @@ -110,7 +110,12 @@ setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); - if (ElemTy != MVT::i32) { + if (ElemTy == MVT::i32) { + setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Custom); + setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Custom); + setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom); + setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom); + } else { setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); @@ -3018,7 +3023,20 @@ } } +static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) { + EVT VT = Op.getValueType(); + assert(VT.getVectorElementType() == MVT::i32 && "Unexpected custom lowering"); + + if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32) + return Op; + return DAG.UnrollVectorOp(Op.getNode()); +} + static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { + EVT VT = Op.getValueType(); + if (VT.isVector()) + return LowerVectorFP_TO_INT(Op, DAG); + DebugLoc dl = Op.getDebugLoc(); unsigned Opc; @@ -3040,6 +3058,12 @@ EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); + if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) { + if (VT.getVectorElementType() == MVT::f32) + return Op; + return DAG.UnrollVectorOp(Op.getNode()); + } + assert(Op.getOperand(0).getValueType() == MVT::v4i16 && "Invalid type for custom lowering!"); if (VT != MVT::v4f32) Added: llvm/trunk/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll?rev=144241&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll Wed Nov 9 17:36:02 2011 @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s + +define <2 x i32> @test1(<2 x double>* %A) { +; CHECK: test1 +; CHECK: vcvt.s32.f64 +; CHECK: vcvt.s32.f64 + %tmp1 = load <2 x double>* %A + %tmp2 = fptosi <2 x double> %tmp1 to <2 x i32> + ret <2 x i32> %tmp2 +} + +define <2 x i32> @test2(<2 x double>* %A) { +; CHECK: test2 +; CHECK: vcvt.u32.f64 +; CHECK: vcvt.u32.f64 + %tmp1 = load <2 x double>* %A + %tmp2 = fptoui <2 x double> %tmp1 to <2 x i32> + ret <2 x i32> %tmp2 +} + +define <2 x double> @test3(<2 x i32>* %A) { +; CHECK: test3 +; CHECK: vcvt.f64.s32 +; CHECK: vcvt.f64.s32 + %tmp1 = load <2 x i32>* %A + %tmp2 = sitofp <2 x i32> %tmp1 to <2 x double> + ret <2 x double> %tmp2 +} + +define <2 x double> @test4(<2 x i32>* %A) { +; CHECK: test4 +; CHECK: vcvt.f64.u32 +; CHECK: vcvt.f64.u32 + %tmp1 = load <2 x i32>* %A + %tmp2 = uitofp <2 x i32> %tmp1 to <2 x double> + ret <2 x double> %tmp2 +} From grosbach at apple.com Wed Nov 9 17:44:24 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 09 Nov 2011 23:44:24 -0000 Subject: [llvm-commits] [llvm] r144242 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s Message-ID: <20111109234424.1B5EB1BE001@llvm.org> Author: grosbach Date: Wed Nov 9 17:44:23 2011 New Revision: 144242 URL: http://llvm.org/viewvc/llvm-project?rev=144242&view=rev Log: Thumb2 assembly parsing STMDB w/ optional .w suffix. rdar://10422955 Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=144242&r1=144241&r2=144242&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Nov 9 17:44:23 2011 @@ -3971,6 +3971,12 @@ def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; +// STMDB/STMDB_UPD aliases w/ the optional .w suffix +def : t2InstAlias<"stmdb${p}.w $Rn, $regs", + (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>; +def : t2InstAlias<"stmdb${p}.w $Rn!, $regs", + (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>; + // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix def : t2InstAlias<"ldmdb${p}.w $Rn, $regs", (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>; Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=144242&r1=144241&r2=144242&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original) +++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Nov 9 17:44:23 2011 @@ -2303,11 +2303,13 @@ stmdb r4, {r5, r6} stmdb r5!, {r3, r8} stmea r5!, {r3, r8} + stmdb.w r5, {r0, r1} @ CHECK: stmdb r4, {r4, r5, r8, r9} @ encoding: [0x04,0xe9,0x30,0x03] @ CHECK: stmdb r4, {r5, r6} @ encoding: [0x04,0xe9,0x60,0x00] @ CHECK: stmdb r5!, {r3, r8} @ encoding: [0x25,0xe9,0x08,0x01] @ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] +@ CHECK: stmdb r5, {r0, r1} @ encoding: [0x05,0xe9,0x03,0x00] @------------------------------------------------------------------------------ From resistor at mac.com Wed Nov 9 17:56:06 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 09 Nov 2011 23:56:06 -0000 Subject: [llvm-commits] [llvm] r144243 - in /llvm/trunk/utils/TableGen: ARMDecoderEmitter.cpp ARMDecoderEmitter.h DisassemblerEmitter.cpp TableGen.cpp Message-ID: <20111109235606.88BC31BE001@llvm.org> Author: resistor Date: Wed Nov 9 17:56:06 2011 New Revision: 144243 URL: http://llvm.org/viewvc/llvm-project?rev=144243&view=rev Log: Remove the old-style ARM disassembler, which is no longer used. Removed: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp llvm/trunk/utils/TableGen/ARMDecoderEmitter.h Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp llvm/trunk/utils/TableGen/TableGen.cpp Removed: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=144242&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (removed) @@ -1,1790 +0,0 @@ -//===------------ ARMDecoderEmitter.cpp - Decoder Generator ---------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file is part of the ARM Disassembler. -// It contains the tablegen backend that emits the decoder functions for ARM and -// Thumb. The disassembler core includes the auto-generated file, invokes the -// decoder functions, and builds up the MCInst based on the decoded Opcode. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "arm-decoder-emitter" - -#include "ARMDecoderEmitter.h" -#include "CodeGenTarget.h" -#include "llvm/ADT/StringExtras.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/TableGen/Record.h" - -#include -#include -#include - -using namespace llvm; - -///////////////////////////////////////////////////// -// // -// Enums and Utilities for ARM Instruction Format // -// // -///////////////////////////////////////////////////// - -#define ARM_FORMATS \ - ENTRY(ARM_FORMAT_PSEUDO, 0) \ - ENTRY(ARM_FORMAT_MULFRM, 1) \ - ENTRY(ARM_FORMAT_BRFRM, 2) \ - ENTRY(ARM_FORMAT_BRMISCFRM, 3) \ - ENTRY(ARM_FORMAT_DPFRM, 4) \ - ENTRY(ARM_FORMAT_DPSOREGREGFRM, 5) \ - ENTRY(ARM_FORMAT_LDFRM, 6) \ - ENTRY(ARM_FORMAT_STFRM, 7) \ - ENTRY(ARM_FORMAT_LDMISCFRM, 8) \ - ENTRY(ARM_FORMAT_STMISCFRM, 9) \ - ENTRY(ARM_FORMAT_LDSTMULFRM, 10) \ - ENTRY(ARM_FORMAT_LDSTEXFRM, 11) \ - ENTRY(ARM_FORMAT_ARITHMISCFRM, 12) \ - ENTRY(ARM_FORMAT_SATFRM, 13) \ - ENTRY(ARM_FORMAT_EXTFRM, 14) \ - ENTRY(ARM_FORMAT_VFPUNARYFRM, 15) \ - ENTRY(ARM_FORMAT_VFPBINARYFRM, 16) \ - ENTRY(ARM_FORMAT_VFPCONV1FRM, 17) \ - ENTRY(ARM_FORMAT_VFPCONV2FRM, 18) \ - ENTRY(ARM_FORMAT_VFPCONV3FRM, 19) \ - ENTRY(ARM_FORMAT_VFPCONV4FRM, 20) \ - ENTRY(ARM_FORMAT_VFPCONV5FRM, 21) \ - ENTRY(ARM_FORMAT_VFPLDSTFRM, 22) \ - ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 23) \ - ENTRY(ARM_FORMAT_VFPMISCFRM, 24) \ - ENTRY(ARM_FORMAT_THUMBFRM, 25) \ - ENTRY(ARM_FORMAT_MISCFRM, 26) \ - ENTRY(ARM_FORMAT_NEONGETLNFRM, 27) \ - ENTRY(ARM_FORMAT_NEONSETLNFRM, 28) \ - ENTRY(ARM_FORMAT_NEONDUPFRM, 29) \ - ENTRY(ARM_FORMAT_NLdSt, 30) \ - ENTRY(ARM_FORMAT_N1RegModImm, 31) \ - ENTRY(ARM_FORMAT_N2Reg, 32) \ - ENTRY(ARM_FORMAT_NVCVT, 33) \ - ENTRY(ARM_FORMAT_NVecDupLn, 34) \ - ENTRY(ARM_FORMAT_N2RegVecShL, 35) \ - ENTRY(ARM_FORMAT_N2RegVecShR, 36) \ - ENTRY(ARM_FORMAT_N3Reg, 37) \ - ENTRY(ARM_FORMAT_N3RegVecSh, 38) \ - ENTRY(ARM_FORMAT_NVecExtract, 39) \ - ENTRY(ARM_FORMAT_NVecMulScalar, 40) \ - ENTRY(ARM_FORMAT_NVTBL, 41) \ - ENTRY(ARM_FORMAT_DPSOREGIMMFRM, 42) - -// ARM instruction format specifies the encoding used by the instruction. -#define ENTRY(n, v) n = v, -typedef enum { - ARM_FORMATS - ARM_FORMAT_NA -} ARMFormat; -#undef ENTRY - -// Converts enum to const char*. -static const char *stringForARMFormat(ARMFormat form) { -#define ENTRY(n, v) case n: return #n; - switch(form) { - ARM_FORMATS - case ARM_FORMAT_NA: - default: - return ""; - } -#undef ENTRY -} - -enum { - IndexModeNone = 0, - IndexModePre = 1, - IndexModePost = 2, - IndexModeUpd = 3 -}; - -///////////////////////// -// // -// Utility functions // -// // -///////////////////////// - -/// byteFromBitsInit - Return the byte value from a BitsInit. -/// Called from getByteField(). -static uint8_t byteFromBitsInit(BitsInit &init) { - int width = init.getNumBits(); - - assert(width <= 8 && "Field is too large for uint8_t!"); - - int index; - uint8_t mask = 0x01; - - uint8_t ret = 0; - - for (index = 0; index < width; index++) { - if (static_cast(init.getBit(index))->getValue()) - ret |= mask; - - mask <<= 1; - } - - return ret; -} - -static uint8_t getByteField(const Record &def, const char *str) { - BitsInit *bits = def.getValueAsBitsInit(str); - return byteFromBitsInit(*bits); -} - -static BitsInit &getBitsField(const Record &def, const char *str) { - BitsInit *bits = def.getValueAsBitsInit(str); - return *bits; -} - -/// sameStringExceptSuffix - Return true if the two strings differ only in RHS's -/// suffix. ("VST4d8", "VST4d8_UPD", "_UPD") as input returns true. -static -bool sameStringExceptSuffix(const StringRef LHS, const StringRef RHS, - const StringRef Suffix) { - - if (RHS.startswith(LHS) && RHS.endswith(Suffix)) - return RHS.size() == LHS.size() + Suffix.size(); - - return false; -} - -/// thumbInstruction - Determine whether we have a Thumb instruction. -/// See also ARMInstrFormats.td. -static bool thumbInstruction(uint8_t Form) { - return Form == ARM_FORMAT_THUMBFRM; -} - -// The set (BIT_TRUE, BIT_FALSE, BIT_UNSET) represents a ternary logic system -// for a bit value. -// -// BIT_UNFILTERED is used as the init value for a filter position. It is used -// only for filter processings. -typedef enum { - BIT_TRUE, // '1' - BIT_FALSE, // '0' - BIT_UNSET, // '?' - BIT_UNFILTERED // unfiltered -} bit_value_t; - -static bool ValueSet(bit_value_t V) { - return (V == BIT_TRUE || V == BIT_FALSE); -} -static bool ValueNotSet(bit_value_t V) { - return (V == BIT_UNSET); -} -static int Value(bit_value_t V) { - return ValueNotSet(V) ? -1 : (V == BIT_FALSE ? 0 : 1); -} -static bit_value_t bitFromBits(BitsInit &bits, unsigned index) { - if (BitInit *bit = dynamic_cast(bits.getBit(index))) - return bit->getValue() ? BIT_TRUE : BIT_FALSE; - - // The bit is uninitialized. - return BIT_UNSET; -} -// Prints the bit value for each position. -static void dumpBits(raw_ostream &o, BitsInit &bits) { - unsigned index; - - for (index = bits.getNumBits(); index > 0; index--) { - switch (bitFromBits(bits, index - 1)) { - case BIT_TRUE: - o << "1"; - break; - case BIT_FALSE: - o << "0"; - break; - case BIT_UNSET: - o << "_"; - break; - default: - assert(0 && "unexpected return value from bitFromBits"); - } - } -} - -// Enums for the available target names. -typedef enum { - TARGET_ARM = 0, - TARGET_THUMB -} TARGET_NAME_t; - -// FIXME: Possibly auto-detected? -#define BIT_WIDTH 32 - -// Forward declaration. -class ARMFilterChooser; - -// Representation of the instruction to work on. -typedef bit_value_t insn_t[BIT_WIDTH]; - -/// Filter - Filter works with FilterChooser to produce the decoding tree for -/// the ISA. -/// -/// It is useful to think of a Filter as governing the switch stmts of the -/// decoding tree in a certain level. Each case stmt delegates to an inferior -/// FilterChooser to decide what further decoding logic to employ, or in another -/// words, what other remaining bits to look at. The FilterChooser eventually -/// chooses a best Filter to do its job. -/// -/// This recursive scheme ends when the number of Opcodes assigned to the -/// FilterChooser becomes 1 or if there is a conflict. A conflict happens when -/// the Filter/FilterChooser combo does not know how to distinguish among the -/// Opcodes assigned. -/// -/// An example of a conflict is -/// -/// Conflict: -/// 111101000.00........00010000.... -/// 111101000.00........0001........ -/// 1111010...00........0001........ -/// 1111010...00.................... -/// 1111010......................... -/// 1111............................ -/// ................................ -/// VST4q8a 111101000_00________00010000____ -/// VST4q8b 111101000_00________00010000____ -/// -/// The Debug output shows the path that the decoding tree follows to reach the -/// the conclusion that there is a conflict. VST4q8a is a vst4 to double-spaced -/// even registers, while VST4q8b is a vst4 to double-spaced odd regsisters. -/// -/// The encoding info in the .td files does not specify this meta information, -/// which could have been used by the decoder to resolve the conflict. The -/// decoder could try to decode the even/odd register numbering and assign to -/// VST4q8a or VST4q8b, but for the time being, the decoder chooses the "a" -/// version and return the Opcode since the two have the same Asm format string. -class ARMFilter { -protected: - ARMFilterChooser *Owner; // points to the FilterChooser who owns this filter - unsigned StartBit; // the starting bit position - unsigned NumBits; // number of bits to filter - bool Mixed; // a mixed region contains both set and unset bits - - // Map of well-known segment value to the set of uid's with that value. - std::map > FilteredInstructions; - - // Set of uid's with non-constant segment values. - std::vector VariableInstructions; - - // Map of well-known segment value to its delegate. - std::map FilterChooserMap; - - // Number of instructions which fall under FilteredInstructions category. - unsigned NumFiltered; - - // Keeps track of the last opcode in the filtered bucket. - unsigned LastOpcFiltered; - - // Number of instructions which fall under VariableInstructions category. - unsigned NumVariable; - -public: - unsigned getNumFiltered() { return NumFiltered; } - unsigned getNumVariable() { return NumVariable; } - unsigned getSingletonOpc() { - assert(NumFiltered == 1); - return LastOpcFiltered; - } - // Return the filter chooser for the group of instructions without constant - // segment values. - ARMFilterChooser &getVariableFC() { - assert(NumFiltered == 1); - assert(FilterChooserMap.size() == 1); - return *(FilterChooserMap.find((unsigned)-1)->second); - } - - ARMFilter(const ARMFilter &f); - ARMFilter(ARMFilterChooser &owner, unsigned startBit, unsigned numBits, - bool mixed); - - ~ARMFilter(); - - // Divides the decoding task into sub tasks and delegates them to the - // inferior FilterChooser's. - // - // A special case arises when there's only one entry in the filtered - // instructions. In order to unambiguously decode the singleton, we need to - // match the remaining undecoded encoding bits against the singleton. - void recurse(); - - // Emit code to decode instructions given a segment or segments of bits. - void emit(raw_ostream &o, unsigned &Indentation); - - // Returns the number of fanout produced by the filter. More fanout implies - // the filter distinguishes more categories of instructions. - unsigned usefulness() const; -}; // End of class Filter - -// These are states of our finite state machines used in FilterChooser's -// filterProcessor() which produces the filter candidates to use. -typedef enum { - ATTR_NONE, - ATTR_FILTERED, - ATTR_ALL_SET, - ATTR_ALL_UNSET, - ATTR_MIXED -} bitAttr_t; - -/// ARMFilterChooser - FilterChooser chooses the best filter among a set of Filters -/// in order to perform the decoding of instructions at the current level. -/// -/// Decoding proceeds from the top down. Based on the well-known encoding bits -/// of instructions available, FilterChooser builds up the possible Filters that -/// can further the task of decoding by distinguishing among the remaining -/// candidate instructions. -/// -/// Once a filter has been chosen, it is called upon to divide the decoding task -/// into sub-tasks and delegates them to its inferior FilterChoosers for further -/// processings. -/// -/// It is useful to think of a Filter as governing the switch stmts of the -/// decoding tree. And each case is delegated to an inferior FilterChooser to -/// decide what further remaining bits to look at. -class ARMFilterChooser { - static TARGET_NAME_t TargetName; - -protected: - friend class ARMFilter; - - // Vector of codegen instructions to choose our filter. - const std::vector &AllInstructions; - - // Vector of uid's for this filter chooser to work on. - const std::vector Opcodes; - - // Vector of candidate filters. - std::vector Filters; - - // Array of bit values passed down from our parent. - // Set to all BIT_UNFILTERED's for Parent == NULL. - bit_value_t FilterBitValues[BIT_WIDTH]; - - // Links to the FilterChooser above us in the decoding tree. - ARMFilterChooser *Parent; - - // Index of the best filter from Filters. - int BestIndex; - -public: - static void setTargetName(TARGET_NAME_t tn) { TargetName = tn; } - - ARMFilterChooser(const ARMFilterChooser &FC) : - AllInstructions(FC.AllInstructions), Opcodes(FC.Opcodes), - Filters(FC.Filters), Parent(FC.Parent), BestIndex(FC.BestIndex) { - memcpy(FilterBitValues, FC.FilterBitValues, sizeof(FilterBitValues)); - } - - ARMFilterChooser(const std::vector &Insts, - const std::vector &IDs) : - AllInstructions(Insts), Opcodes(IDs), Filters(), Parent(NULL), - BestIndex(-1) { - for (unsigned i = 0; i < BIT_WIDTH; ++i) - FilterBitValues[i] = BIT_UNFILTERED; - - doFilter(); - } - - ARMFilterChooser(const std::vector &Insts, - const std::vector &IDs, - bit_value_t (&ParentFilterBitValues)[BIT_WIDTH], - ARMFilterChooser &parent) : - AllInstructions(Insts), Opcodes(IDs), Filters(), Parent(&parent), - BestIndex(-1) { - for (unsigned i = 0; i < BIT_WIDTH; ++i) - FilterBitValues[i] = ParentFilterBitValues[i]; - - doFilter(); - } - - // The top level filter chooser has NULL as its parent. - bool isTopLevel() { return Parent == NULL; } - - // This provides an opportunity for target specific code emission. - void emitTopHook(raw_ostream &o); - - // Emit the top level typedef and decodeInstruction() function. - void emitTop(raw_ostream &o, unsigned &Indentation); - - // This provides an opportunity for target specific code emission after - // emitTop(). - void emitBot(raw_ostream &o, unsigned &Indentation); - -protected: - // Populates the insn given the uid. - void insnWithID(insn_t &Insn, unsigned Opcode) const { - if (AllInstructions[Opcode]->isPseudo) - return; - - BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst"); - - for (unsigned i = 0; i < BIT_WIDTH; ++i) - Insn[i] = bitFromBits(Bits, i); - - // Set Inst{21} to 1 (wback) when IndexModeBits == IndexModeUpd. - Record *R = AllInstructions[Opcode]->TheDef; - if (R->getValue("IndexModeBits") && - getByteField(*R, "IndexModeBits") == IndexModeUpd) - Insn[21] = BIT_TRUE; - } - - // Returns the record name. - const std::string &nameWithID(unsigned Opcode) const { - return AllInstructions[Opcode]->TheDef->getName(); - } - - // Populates the field of the insn given the start position and the number of - // consecutive bits to scan for. - // - // Returns false if there exists any uninitialized bit value in the range. - // Returns true, otherwise. - bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit, - unsigned NumBits) const; - - /// dumpFilterArray - dumpFilterArray prints out debugging info for the given - /// filter array as a series of chars. - void dumpFilterArray(raw_ostream &o, bit_value_t (&filter)[BIT_WIDTH]); - - /// dumpStack - dumpStack traverses the filter chooser chain and calls - /// dumpFilterArray on each filter chooser up to the top level one. - void dumpStack(raw_ostream &o, const char *prefix); - - ARMFilter &bestFilter() { - assert(BestIndex != -1 && "BestIndex not set"); - return Filters[BestIndex]; - } - - // Called from Filter::recurse() when singleton exists. For debug purpose. - void SingletonExists(unsigned Opc); - - bool PositionFiltered(unsigned i) { - return ValueSet(FilterBitValues[i]); - } - - // Calculates the island(s) needed to decode the instruction. - // This returns a lit of undecoded bits of an instructions, for example, - // Inst{20} = 1 && Inst{3-0} == 0b1111 represents two islands of yet-to-be - // decoded bits in order to verify that the instruction matches the Opcode. - unsigned getIslands(std::vector &StartBits, - std::vector &EndBits, std::vector &FieldVals, - insn_t &Insn); - - // The purpose of this function is for the API client to detect possible - // Load/Store Coprocessor instructions. If the coprocessor number is of - // the instruction is either 10 or 11, the decoder should not report the - // instruction as LDC/LDC2/STC/STC2, but should match against Advanced SIMD or - // VFP instructions. - bool LdStCopEncoding1(unsigned Opc) { - const std::string &Name = nameWithID(Opc); - if (Name == "LDC_OFFSET" || Name == "LDC_OPTION" || - Name == "LDC_POST" || Name == "LDC_PRE" || - Name == "LDCL_OFFSET" || Name == "LDCL_OPTION" || - Name == "LDCL_POST" || Name == "LDCL_PRE" || - Name == "STC_OFFSET" || Name == "STC_OPTION" || - Name == "STC_POST" || Name == "STC_PRE" || - Name == "STCL_OFFSET" || Name == "STCL_OPTION" || - Name == "STCL_POST" || Name == "STCL_PRE") - return true; - else - return false; - } - - // Emits code to decode the singleton. Return true if we have matched all the - // well-known bits. - bool emitSingletonDecoder(raw_ostream &o, unsigned &Indentation,unsigned Opc); - - // Emits code to decode the singleton, and then to decode the rest. - void emitSingletonDecoder(raw_ostream &o, unsigned &Indentation, - ARMFilter &Best); - - // Assign a single filter and run with it. - void runSingleFilter(ARMFilterChooser &owner, unsigned startBit, - unsigned numBit, bool mixed); - - // reportRegion is a helper function for filterProcessor to mark a region as - // eligible for use as a filter region. - void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex, - bool AllowMixed); - - // FilterProcessor scans the well-known encoding bits of the instructions and - // builds up a list of candidate filters. It chooses the best filter and - // recursively descends down the decoding tree. - bool filterProcessor(bool AllowMixed, bool Greedy = true); - - // Decides on the best configuration of filter(s) to use in order to decode - // the instructions. A conflict of instructions may occur, in which case we - // dump the conflict set to the standard error. - void doFilter(); - - // Emits code to decode our share of instructions. Returns true if the - // emitted code causes a return, which occurs if we know how to decode - // the instruction at this level or the instruction is not decodeable. - bool emit(raw_ostream &o, unsigned &Indentation); -}; - -/////////////////////////// -// // -// Filter Implmenetation // -// // -/////////////////////////// - -ARMFilter::ARMFilter(const ARMFilter &f) : - Owner(f.Owner), StartBit(f.StartBit), NumBits(f.NumBits), Mixed(f.Mixed), - FilteredInstructions(f.FilteredInstructions), - VariableInstructions(f.VariableInstructions), - FilterChooserMap(f.FilterChooserMap), NumFiltered(f.NumFiltered), - LastOpcFiltered(f.LastOpcFiltered), NumVariable(f.NumVariable) { -} - -ARMFilter::ARMFilter(ARMFilterChooser &owner, unsigned startBit, unsigned numBits, - bool mixed) : Owner(&owner), StartBit(startBit), NumBits(numBits), - Mixed(mixed) { - assert(StartBit + NumBits - 1 < BIT_WIDTH); - - NumFiltered = 0; - LastOpcFiltered = 0; - NumVariable = 0; - - for (unsigned i = 0, e = Owner->Opcodes.size(); i != e; ++i) { - insn_t Insn; - - // Populates the insn given the uid. - Owner->insnWithID(Insn, Owner->Opcodes[i]); - - uint64_t Field; - // Scans the segment for possibly well-specified encoding bits. - bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits); - - if (ok) { - // The encoding bits are well-known. Lets add the uid of the - // instruction into the bucket keyed off the constant field value. - LastOpcFiltered = Owner->Opcodes[i]; - FilteredInstructions[Field].push_back(LastOpcFiltered); - ++NumFiltered; - } else { - // Some of the encoding bit(s) are unspecfied. This contributes to - // one additional member of "Variable" instructions. - VariableInstructions.push_back(Owner->Opcodes[i]); - ++NumVariable; - } - } - - assert((FilteredInstructions.size() + VariableInstructions.size() > 0) - && "Filter returns no instruction categories"); -} - -ARMFilter::~ARMFilter() { - std::map::iterator filterIterator; - for (filterIterator = FilterChooserMap.begin(); - filterIterator != FilterChooserMap.end(); - filterIterator++) { - delete filterIterator->second; - } -} - -// Divides the decoding task into sub tasks and delegates them to the -// inferior FilterChooser's. -// -// A special case arises when there's only one entry in the filtered -// instructions. In order to unambiguously decode the singleton, we need to -// match the remaining undecoded encoding bits against the singleton. -void ARMFilter::recurse() { - std::map >::const_iterator mapIterator; - - bit_value_t BitValueArray[BIT_WIDTH]; - // Starts by inheriting our parent filter chooser's filter bit values. - memcpy(BitValueArray, Owner->FilterBitValues, sizeof(BitValueArray)); - - unsigned bitIndex; - - if (VariableInstructions.size()) { - // Conservatively marks each segment position as BIT_UNSET. - for (bitIndex = 0; bitIndex < NumBits; bitIndex++) - BitValueArray[StartBit + bitIndex] = BIT_UNSET; - - // Delegates to an inferior filter chooser for further processing on this - // group of instructions whose segment values are variable. - FilterChooserMap.insert(std::pair( - (unsigned)-1, - new ARMFilterChooser(Owner->AllInstructions, - VariableInstructions, - BitValueArray, - *Owner) - )); - } - - // No need to recurse for a singleton filtered instruction. - // See also Filter::emit(). - if (getNumFiltered() == 1) { - //Owner->SingletonExists(LastOpcFiltered); - assert(FilterChooserMap.size() == 1); - return; - } - - // Otherwise, create sub choosers. - for (mapIterator = FilteredInstructions.begin(); - mapIterator != FilteredInstructions.end(); - mapIterator++) { - - // Marks all the segment positions with either BIT_TRUE or BIT_FALSE. - for (bitIndex = 0; bitIndex < NumBits; bitIndex++) { - if (mapIterator->first & (1ULL << bitIndex)) - BitValueArray[StartBit + bitIndex] = BIT_TRUE; - else - BitValueArray[StartBit + bitIndex] = BIT_FALSE; - } - - // Delegates to an inferior filter chooser for further processing on this - // category of instructions. - FilterChooserMap.insert(std::pair( - mapIterator->first, - new ARMFilterChooser(Owner->AllInstructions, - mapIterator->second, - BitValueArray, - *Owner) - )); - } -} - -// Emit code to decode instructions given a segment or segments of bits. -void ARMFilter::emit(raw_ostream &o, unsigned &Indentation) { - o.indent(Indentation) << "// Check Inst{"; - - if (NumBits > 1) - o << (StartBit + NumBits - 1) << '-'; - - o << StartBit << "} ...\n"; - - o.indent(Indentation) << "switch (fieldFromInstruction(insn, " - << StartBit << ", " << NumBits << ")) {\n"; - - std::map::iterator filterIterator; - - bool DefaultCase = false; - for (filterIterator = FilterChooserMap.begin(); - filterIterator != FilterChooserMap.end(); - filterIterator++) { - - // Field value -1 implies a non-empty set of variable instructions. - // See also recurse(). - if (filterIterator->first == (unsigned)-1) { - DefaultCase = true; - - o.indent(Indentation) << "default:\n"; - o.indent(Indentation) << " break; // fallthrough\n"; - - // Closing curly brace for the switch statement. - // This is unconventional because we want the default processing to be - // performed for the fallthrough cases as well, i.e., when the "cases" - // did not prove a decoded instruction. - o.indent(Indentation) << "}\n"; - - } else - o.indent(Indentation) << "case " << filterIterator->first << ":\n"; - - // We arrive at a category of instructions with the same segment value. - // Now delegate to the sub filter chooser for further decodings. - // The case may fallthrough, which happens if the remaining well-known - // encoding bits do not match exactly. - if (!DefaultCase) { ++Indentation; ++Indentation; } - - bool finished = filterIterator->second->emit(o, Indentation); - // For top level default case, there's no need for a break statement. - if (Owner->isTopLevel() && DefaultCase) - break; - if (!finished) - o.indent(Indentation) << "break;\n"; - - if (!DefaultCase) { --Indentation; --Indentation; } - } - - // If there is no default case, we still need to supply a closing brace. - if (!DefaultCase) { - // Closing curly brace for the switch statement. - o.indent(Indentation) << "}\n"; - } -} - -// Returns the number of fanout produced by the filter. More fanout implies -// the filter distinguishes more categories of instructions. -unsigned ARMFilter::usefulness() const { - if (VariableInstructions.size()) - return FilteredInstructions.size(); - else - return FilteredInstructions.size() + 1; -} - -////////////////////////////////// -// // -// Filterchooser Implementation // -// // -////////////////////////////////// - -// Define the symbol here. -TARGET_NAME_t ARMFilterChooser::TargetName; - -// This provides an opportunity for target specific code emission. -void ARMFilterChooser::emitTopHook(raw_ostream &o) { - if (TargetName == TARGET_ARM) { - // Emit code that references the ARMFormat data type. - o << "static const ARMFormat ARMFormats[] = {\n"; - for (unsigned i = 0, e = AllInstructions.size(); i != e; ++i) { - const Record &Def = *(AllInstructions[i]->TheDef); - const std::string &Name = Def.getName(); - if (Def.isSubClassOf("InstARM") || Def.isSubClassOf("InstThumb")) - o.indent(2) << - stringForARMFormat((ARMFormat)getByteField(Def, "Form")); - else - o << " ARM_FORMAT_NA"; - - o << ",\t// Inst #" << i << " = " << Name << '\n'; - } - o << " ARM_FORMAT_NA\t// Unreachable.\n"; - o << "};\n\n"; - } -} - -// Emit the top level typedef and decodeInstruction() function. -void ARMFilterChooser::emitTop(raw_ostream &o, unsigned &Indentation) { - // Run the target specific emit hook. - emitTopHook(o); - - switch (BIT_WIDTH) { - case 8: - o.indent(Indentation) << "typedef uint8_t field_t;\n"; - break; - case 16: - o.indent(Indentation) << "typedef uint16_t field_t;\n"; - break; - case 32: - o.indent(Indentation) << "typedef uint32_t field_t;\n"; - break; - case 64: - o.indent(Indentation) << "typedef uint64_t field_t;\n"; - break; - default: - assert(0 && "Unexpected instruction size!"); - } - - o << '\n'; - - o.indent(Indentation) << "static field_t " << - "fieldFromInstruction(field_t insn, unsigned startBit, unsigned numBits)\n"; - - o.indent(Indentation) << "{\n"; - - ++Indentation; ++Indentation; - o.indent(Indentation) << "assert(startBit + numBits <= " << BIT_WIDTH - << " && \"Instruction field out of bounds!\");\n"; - o << '\n'; - o.indent(Indentation) << "field_t fieldMask;\n"; - o << '\n'; - o.indent(Indentation) << "if (numBits == " << BIT_WIDTH << ")\n"; - - ++Indentation; ++Indentation; - o.indent(Indentation) << "fieldMask = (field_t)-1;\n"; - --Indentation; --Indentation; - - o.indent(Indentation) << "else\n"; - - ++Indentation; ++Indentation; - o.indent(Indentation) << "fieldMask = ((1 << numBits) - 1) << startBit;\n"; - --Indentation; --Indentation; - - o << '\n'; - o.indent(Indentation) << "return (insn & fieldMask) >> startBit;\n"; - --Indentation; --Indentation; - - o.indent(Indentation) << "}\n"; - - o << '\n'; - - o.indent(Indentation) <<"static uint16_t decodeInstruction(field_t insn) {\n"; - - ++Indentation; ++Indentation; - // Emits code to decode the instructions. - emit(o, Indentation); - - o << '\n'; - o.indent(Indentation) << "return 0;\n"; - --Indentation; --Indentation; - - o.indent(Indentation) << "}\n"; - - o << '\n'; -} - -// This provides an opportunity for target specific code emission after -// emitTop(). -void ARMFilterChooser::emitBot(raw_ostream &o, unsigned &Indentation) { - if (TargetName != TARGET_THUMB) return; - - // Emit code that decodes the Thumb ISA. - o.indent(Indentation) - << "static uint16_t decodeThumbInstruction(field_t insn) {\n"; - - ++Indentation; ++Indentation; - - // Emits code to decode the instructions. - emit(o, Indentation); - - o << '\n'; - o.indent(Indentation) << "return 0;\n"; - - --Indentation; --Indentation; - - o.indent(Indentation) << "}\n"; -} - -// Populates the field of the insn given the start position and the number of -// consecutive bits to scan for. -// -// Returns false if and on the first uninitialized bit value encountered. -// Returns true, otherwise. -bool ARMFilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn, - unsigned StartBit, unsigned NumBits) const { - Field = 0; - - for (unsigned i = 0; i < NumBits; ++i) { - if (Insn[StartBit + i] == BIT_UNSET) - return false; - - if (Insn[StartBit + i] == BIT_TRUE) - Field = Field | (1ULL << i); - } - - return true; -} - -/// dumpFilterArray - dumpFilterArray prints out debugging info for the given -/// filter array as a series of chars. -void ARMFilterChooser::dumpFilterArray(raw_ostream &o, - bit_value_t (&filter)[BIT_WIDTH]) { - unsigned bitIndex; - - for (bitIndex = BIT_WIDTH; bitIndex > 0; bitIndex--) { - switch (filter[bitIndex - 1]) { - case BIT_UNFILTERED: - o << "."; - break; - case BIT_UNSET: - o << "_"; - break; - case BIT_TRUE: - o << "1"; - break; - case BIT_FALSE: - o << "0"; - break; - } - } -} - -/// dumpStack - dumpStack traverses the filter chooser chain and calls -/// dumpFilterArray on each filter chooser up to the top level one. -void ARMFilterChooser::dumpStack(raw_ostream &o, const char *prefix) { - ARMFilterChooser *current = this; - - while (current) { - o << prefix; - dumpFilterArray(o, current->FilterBitValues); - o << '\n'; - current = current->Parent; - } -} - -// Called from Filter::recurse() when singleton exists. For debug purpose. -void ARMFilterChooser::SingletonExists(unsigned Opc) { - insn_t Insn0; - insnWithID(Insn0, Opc); - - errs() << "Singleton exists: " << nameWithID(Opc) - << " with its decoding dominating "; - for (unsigned i = 0; i < Opcodes.size(); ++i) { - if (Opcodes[i] == Opc) continue; - errs() << nameWithID(Opcodes[i]) << ' '; - } - errs() << '\n'; - - dumpStack(errs(), "\t\t"); - for (unsigned i = 0; i < Opcodes.size(); i++) { - const std::string &Name = nameWithID(Opcodes[i]); - - errs() << '\t' << Name << " "; - dumpBits(errs(), - getBitsField(*AllInstructions[Opcodes[i]]->TheDef, "Inst")); - errs() << '\n'; - } -} - -// Calculates the island(s) needed to decode the instruction. -// This returns a list of undecoded bits of an instructions, for example, -// Inst{20} = 1 && Inst{3-0} == 0b1111 represents two islands of yet-to-be -// decoded bits in order to verify that the instruction matches the Opcode. -unsigned ARMFilterChooser::getIslands(std::vector &StartBits, - std::vector &EndBits, std::vector &FieldVals, - insn_t &Insn) { - unsigned Num, BitNo; - Num = BitNo = 0; - - uint64_t FieldVal = 0; - - // 0: Init - // 1: Water (the bit value does not affect decoding) - // 2: Island (well-known bit value needed for decoding) - int State = 0; - int Val = -1; - - for (unsigned i = 0; i < BIT_WIDTH; ++i) { - Val = Value(Insn[i]); - bool Filtered = PositionFiltered(i); - switch (State) { - default: - assert(0 && "Unreachable code!"); - break; - case 0: - case 1: - if (Filtered || Val == -1) - State = 1; // Still in Water - else { - State = 2; // Into the Island - BitNo = 0; - StartBits.push_back(i); - FieldVal = Val; - } - break; - case 2: - if (Filtered || Val == -1) { - State = 1; // Into the Water - EndBits.push_back(i - 1); - FieldVals.push_back(FieldVal); - ++Num; - } else { - State = 2; // Still in Island - ++BitNo; - FieldVal = FieldVal | Val << BitNo; - } - break; - } - } - // If we are still in Island after the loop, do some housekeeping. - if (State == 2) { - EndBits.push_back(BIT_WIDTH - 1); - FieldVals.push_back(FieldVal); - ++Num; - } - - assert(StartBits.size() == Num && EndBits.size() == Num && - FieldVals.size() == Num); - return Num; -} - -// Emits code to decode the singleton. Return true if we have matched all the -// well-known bits. -bool ARMFilterChooser::emitSingletonDecoder(raw_ostream &o, unsigned &Indentation, - unsigned Opc) { - std::vector StartBits; - std::vector EndBits; - std::vector FieldVals; - insn_t Insn; - insnWithID(Insn, Opc); - - // This provides a good opportunity to check for possible Ld/St Coprocessor - // Opcode and escapes if the coproc # is either 10 or 11. It is a NEON/VFP - // instruction is disguise. - if (TargetName == TARGET_ARM && LdStCopEncoding1(Opc)) { - o.indent(Indentation); - // A8.6.51 & A8.6.188 - // If coproc = 0b101?, i.e, slice(insn, 11, 8) = 10 or 11, escape. - o << "if (fieldFromInstruction(insn, 9, 3) == 5) break; // fallthrough\n"; - } - - // Look for islands of undecoded bits of the singleton. - getIslands(StartBits, EndBits, FieldVals, Insn); - - unsigned Size = StartBits.size(); - unsigned I, NumBits; - - // If we have matched all the well-known bits, just issue a return. - if (Size == 0) { - o.indent(Indentation) << "return " << Opc << "; // " << nameWithID(Opc) - << '\n'; - return true; - } - - // Otherwise, there are more decodings to be done! - - // Emit code to match the island(s) for the singleton. - o.indent(Indentation) << "// Check "; - - for (I = Size; I != 0; --I) { - o << "Inst{" << EndBits[I-1] << '-' << StartBits[I-1] << "} "; - if (I > 1) - o << "&& "; - else - o << "for singleton decoding...\n"; - } - - o.indent(Indentation) << "if ("; - - for (I = Size; I != 0; --I) { - NumBits = EndBits[I-1] - StartBits[I-1] + 1; - o << "fieldFromInstruction(insn, " << StartBits[I-1] << ", " << NumBits - << ") == " << FieldVals[I-1]; - if (I > 1) - o << " && "; - else - o << ")\n"; - } - - o.indent(Indentation) << " return " << Opc << "; // " << nameWithID(Opc) - << '\n'; - - return false; -} - -// Emits code to decode the singleton, and then to decode the rest. -void ARMFilterChooser::emitSingletonDecoder(raw_ostream &o, - unsigned &Indentation, - ARMFilter &Best) { - - unsigned Opc = Best.getSingletonOpc(); - - emitSingletonDecoder(o, Indentation, Opc); - - // Emit code for the rest. - o.indent(Indentation) << "else\n"; - - Indentation += 2; - Best.getVariableFC().emit(o, Indentation); - Indentation -= 2; -} - -// Assign a single filter and run with it. Top level API client can initialize -// with a single filter to start the filtering process. -void ARMFilterChooser::runSingleFilter(ARMFilterChooser &owner, - unsigned startBit, - unsigned numBit, bool mixed) { - Filters.clear(); - ARMFilter F(*this, startBit, numBit, true); - Filters.push_back(F); - BestIndex = 0; // Sole Filter instance to choose from. - bestFilter().recurse(); -} - -// reportRegion is a helper function for filterProcessor to mark a region as -// eligible for use as a filter region. -void ARMFilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit, - unsigned BitIndex, bool AllowMixed) { - if (RA == ATTR_MIXED && AllowMixed) - Filters.push_back(ARMFilter(*this, StartBit, BitIndex - StartBit, true)); - else if (RA == ATTR_ALL_SET && !AllowMixed) - Filters.push_back(ARMFilter(*this, StartBit, BitIndex - StartBit, false)); -} - -// FilterProcessor scans the well-known encoding bits of the instructions and -// builds up a list of candidate filters. It chooses the best filter and -// recursively descends down the decoding tree. -bool ARMFilterChooser::filterProcessor(bool AllowMixed, bool Greedy) { - Filters.clear(); - BestIndex = -1; - unsigned numInstructions = Opcodes.size(); - - assert(numInstructions && "Filter created with no instructions"); - - // No further filtering is necessary. - if (numInstructions == 1) - return true; - - // Heuristics. See also doFilter()'s "Heuristics" comment when num of - // instructions is 3. - if (AllowMixed && !Greedy) { - assert(numInstructions == 3); - - for (unsigned i = 0; i < Opcodes.size(); ++i) { - std::vector StartBits; - std::vector EndBits; - std::vector FieldVals; - insn_t Insn; - - insnWithID(Insn, Opcodes[i]); - - // Look for islands of undecoded bits of any instruction. - if (getIslands(StartBits, EndBits, FieldVals, Insn) > 0) { - // Found an instruction with island(s). Now just assign a filter. - runSingleFilter(*this, StartBits[0], EndBits[0] - StartBits[0] + 1, - true); - return true; - } - } - } - - unsigned BitIndex, InsnIndex; - - // We maintain BIT_WIDTH copies of the bitAttrs automaton. - // The automaton consumes the corresponding bit from each - // instruction. - // - // Input symbols: 0, 1, and _ (unset). - // States: NONE, FILTERED, ALL_SET, ALL_UNSET, and MIXED. - // Initial state: NONE. - // - // (NONE) ------- [01] -> (ALL_SET) - // (NONE) ------- _ ----> (ALL_UNSET) - // (ALL_SET) ---- [01] -> (ALL_SET) - // (ALL_SET) ---- _ ----> (MIXED) - // (ALL_UNSET) -- [01] -> (MIXED) - // (ALL_UNSET) -- _ ----> (ALL_UNSET) - // (MIXED) ------ . ----> (MIXED) - // (FILTERED)---- . ----> (FILTERED) - - bitAttr_t bitAttrs[BIT_WIDTH]; - - // FILTERED bit positions provide no entropy and are not worthy of pursuing. - // Filter::recurse() set either BIT_TRUE or BIT_FALSE for each position. - for (BitIndex = 0; BitIndex < BIT_WIDTH; ++BitIndex) - if (FilterBitValues[BitIndex] == BIT_TRUE || - FilterBitValues[BitIndex] == BIT_FALSE) - bitAttrs[BitIndex] = ATTR_FILTERED; - else - bitAttrs[BitIndex] = ATTR_NONE; - - for (InsnIndex = 0; InsnIndex < numInstructions; ++InsnIndex) { - insn_t insn; - - insnWithID(insn, Opcodes[InsnIndex]); - - for (BitIndex = 0; BitIndex < BIT_WIDTH; ++BitIndex) { - switch (bitAttrs[BitIndex]) { - case ATTR_NONE: - if (insn[BitIndex] == BIT_UNSET) - bitAttrs[BitIndex] = ATTR_ALL_UNSET; - else - bitAttrs[BitIndex] = ATTR_ALL_SET; - break; - case ATTR_ALL_SET: - if (insn[BitIndex] == BIT_UNSET) - bitAttrs[BitIndex] = ATTR_MIXED; - break; - case ATTR_ALL_UNSET: - if (insn[BitIndex] != BIT_UNSET) - bitAttrs[BitIndex] = ATTR_MIXED; - break; - case ATTR_MIXED: - case ATTR_FILTERED: - break; - } - } - } - - // The regionAttr automaton consumes the bitAttrs automatons' state, - // lowest-to-highest. - // - // Input symbols: F(iltered), (all_)S(et), (all_)U(nset), M(ixed) - // States: NONE, ALL_SET, MIXED - // Initial state: NONE - // - // (NONE) ----- F --> (NONE) - // (NONE) ----- S --> (ALL_SET) ; and set region start - // (NONE) ----- U --> (NONE) - // (NONE) ----- M --> (MIXED) ; and set region start - // (ALL_SET) -- F --> (NONE) ; and report an ALL_SET region - // (ALL_SET) -- S --> (ALL_SET) - // (ALL_SET) -- U --> (NONE) ; and report an ALL_SET region - // (ALL_SET) -- M --> (MIXED) ; and report an ALL_SET region - // (MIXED) ---- F --> (NONE) ; and report a MIXED region - // (MIXED) ---- S --> (ALL_SET) ; and report a MIXED region - // (MIXED) ---- U --> (NONE) ; and report a MIXED region - // (MIXED) ---- M --> (MIXED) - - bitAttr_t RA = ATTR_NONE; - unsigned StartBit = 0; - - for (BitIndex = 0; BitIndex < BIT_WIDTH; BitIndex++) { - bitAttr_t bitAttr = bitAttrs[BitIndex]; - - assert(bitAttr != ATTR_NONE && "Bit without attributes"); - - switch (RA) { - case ATTR_NONE: - switch (bitAttr) { - case ATTR_FILTERED: - break; - case ATTR_ALL_SET: - StartBit = BitIndex; - RA = ATTR_ALL_SET; - break; - case ATTR_ALL_UNSET: - break; - case ATTR_MIXED: - StartBit = BitIndex; - RA = ATTR_MIXED; - break; - default: - assert(0 && "Unexpected bitAttr!"); - } - break; - case ATTR_ALL_SET: - switch (bitAttr) { - case ATTR_FILTERED: - reportRegion(RA, StartBit, BitIndex, AllowMixed); - RA = ATTR_NONE; - break; - case ATTR_ALL_SET: - break; - case ATTR_ALL_UNSET: - reportRegion(RA, StartBit, BitIndex, AllowMixed); - RA = ATTR_NONE; - break; - case ATTR_MIXED: - reportRegion(RA, StartBit, BitIndex, AllowMixed); - StartBit = BitIndex; - RA = ATTR_MIXED; - break; - default: - assert(0 && "Unexpected bitAttr!"); - } - break; - case ATTR_MIXED: - switch (bitAttr) { - case ATTR_FILTERED: - reportRegion(RA, StartBit, BitIndex, AllowMixed); - StartBit = BitIndex; - RA = ATTR_NONE; - break; - case ATTR_ALL_SET: - reportRegion(RA, StartBit, BitIndex, AllowMixed); - StartBit = BitIndex; - RA = ATTR_ALL_SET; - break; - case ATTR_ALL_UNSET: - reportRegion(RA, StartBit, BitIndex, AllowMixed); - RA = ATTR_NONE; - break; - case ATTR_MIXED: - break; - default: - assert(0 && "Unexpected bitAttr!"); - } - break; - case ATTR_ALL_UNSET: - assert(0 && "regionAttr state machine has no ATTR_UNSET state"); - case ATTR_FILTERED: - assert(0 && "regionAttr state machine has no ATTR_FILTERED state"); - } - } - - // At the end, if we're still in ALL_SET or MIXED states, report a region - switch (RA) { - case ATTR_NONE: - break; - case ATTR_FILTERED: - break; - case ATTR_ALL_SET: - reportRegion(RA, StartBit, BitIndex, AllowMixed); - break; - case ATTR_ALL_UNSET: - break; - case ATTR_MIXED: - reportRegion(RA, StartBit, BitIndex, AllowMixed); - break; - } - - // We have finished with the filter processings. Now it's time to choose - // the best performing filter. - BestIndex = 0; - bool AllUseless = true; - unsigned BestScore = 0; - - for (unsigned i = 0, e = Filters.size(); i != e; ++i) { - unsigned Usefulness = Filters[i].usefulness(); - - if (Usefulness) - AllUseless = false; - - if (Usefulness > BestScore) { - BestIndex = i; - BestScore = Usefulness; - } - } - - if (!AllUseless) - bestFilter().recurse(); - - return !AllUseless; -} // end of FilterChooser::filterProcessor(bool) - -// Decides on the best configuration of filter(s) to use in order to decode -// the instructions. A conflict of instructions may occur, in which case we -// dump the conflict set to the standard error. -void ARMFilterChooser::doFilter() { - unsigned Num = Opcodes.size(); - assert(Num && "FilterChooser created with no instructions"); - - // Heuristics: Use Inst{31-28} as the top level filter for ARM ISA. - if (TargetName == TARGET_ARM && Parent == NULL) { - runSingleFilter(*this, 28, 4, false); - return; - } - - // Try regions of consecutive known bit values first. - if (filterProcessor(false)) - return; - - // Then regions of mixed bits (both known and unitialized bit values allowed). - if (filterProcessor(true)) - return; - - // Heuristics to cope with conflict set {t2CMPrs, t2SUBSrr, t2SUBSrs} where - // no single instruction for the maximum ATTR_MIXED region Inst{14-4} has a - // well-known encoding pattern. In such case, we backtrack and scan for the - // the very first consecutive ATTR_ALL_SET region and assign a filter to it. - if (Num == 3 && filterProcessor(true, false)) - return; - - // If we come to here, the instruction decoding has failed. - // Set the BestIndex to -1 to indicate so. - BestIndex = -1; -} - -// Emits code to decode our share of instructions. Returns true if the -// emitted code causes a return, which occurs if we know how to decode -// the instruction at this level or the instruction is not decodeable. -bool ARMFilterChooser::emit(raw_ostream &o, unsigned &Indentation) { - if (Opcodes.size() == 1) - // There is only one instruction in the set, which is great! - // Call emitSingletonDecoder() to see whether there are any remaining - // encodings bits. - return emitSingletonDecoder(o, Indentation, Opcodes[0]); - - // Choose the best filter to do the decodings! - if (BestIndex != -1) { - ARMFilter &Best = bestFilter(); - if (Best.getNumFiltered() == 1) - emitSingletonDecoder(o, Indentation, Best); - else - bestFilter().emit(o, Indentation); - return false; - } - - // If we reach here, there is a conflict in decoding. Let's resolve the known - // conflicts! - if ((TargetName == TARGET_ARM || TargetName == TARGET_THUMB) && - Opcodes.size() == 2) { - // Resolve the known conflict sets: - // - // 1. source registers are identical => VMOVDneon; otherwise => VORRd - // 2. source registers are identical => VMOVQ; otherwise => VORRq - // 3. LDR, LDRcp => return LDR for now. - // FIXME: How can we distinguish between LDR and LDRcp? Do we need to? - // 4. tLDMIA, tLDMIA_UPD => Rn = Inst{10-8}, reglist = Inst{7-0}, - // wback = registers = 0 - // NOTE: (tLDM, tLDM_UPD) resolution must come before Advanced SIMD - // addressing mode resolution!!! - // 5. VLD[234]LN*/VST[234]LN* vs. VLD[234]LN*_UPD/VST[234]LN*_UPD conflicts - // are resolved returning the non-UPD versions of the instructions if the - // Rm field, i.e., Inst{3-0} is 0b1111. This is specified in A7.7.1 - // Advanced SIMD addressing mode. - const std::string &name1 = nameWithID(Opcodes[0]); - const std::string &name2 = nameWithID(Opcodes[1]); - if ((name1 == "VMOVDneon" && name2 == "VORRd") || - (name1 == "VMOVQ" && name2 == "VORRq")) { - // Inserting the opening curly brace for this case block. - --Indentation; --Indentation; - o.indent(Indentation) << "{\n"; - ++Indentation; ++Indentation; - - o.indent(Indentation) - << "field_t N = fieldFromInstruction(insn, 7, 1), " - << "M = fieldFromInstruction(insn, 5, 1);\n"; - o.indent(Indentation) - << "field_t Vn = fieldFromInstruction(insn, 16, 4), " - << "Vm = fieldFromInstruction(insn, 0, 4);\n"; - o.indent(Indentation) - << "return (N == M && Vn == Vm) ? " - << Opcodes[0] << " /* " << name1 << " */ : " - << Opcodes[1] << " /* " << name2 << " */ ;\n"; - - // Inserting the closing curly brace for this case block. - --Indentation; --Indentation; - o.indent(Indentation) << "}\n"; - ++Indentation; ++Indentation; - - return true; - } - if (name1 == "LDR" && name2 == "LDRcp") { - o.indent(Indentation) - << "return " << Opcodes[0] - << "; // Returning LDR for {LDR, LDRcp}\n"; - return true; - } - if (name1 == "tLDMIA" && name2 == "tLDMIA_UPD") { - // Inserting the opening curly brace for this case block. - --Indentation; --Indentation; - o.indent(Indentation) << "{\n"; - ++Indentation; ++Indentation; - - o.indent(Indentation) - << "unsigned Rn = fieldFromInstruction(insn, 8, 3), " - << "list = fieldFromInstruction(insn, 0, 8);\n"; - o.indent(Indentation) - << "return ((list >> Rn) & 1) == 0 ? " - << Opcodes[1] << " /* " << name2 << " */ : " - << Opcodes[0] << " /* " << name1 << " */ ;\n"; - - // Inserting the closing curly brace for this case block. - --Indentation; --Indentation; - o.indent(Indentation) << "}\n"; - ++Indentation; ++Indentation; - - return true; - } - if (sameStringExceptSuffix(name1, name2, "_UPD")) { - o.indent(Indentation) - << "return fieldFromInstruction(insn, 0, 4) == 15 ? " << Opcodes[0] - << " /* " << name1 << " */ : " << Opcodes[1] << "/* " << name2 - << " */ ; // Advanced SIMD addressing mode\n"; - return true; - } - - // Otherwise, it does not belong to the known conflict sets. - } - - // We don't know how to decode these instructions! Return 0 and dump the - // conflict set! - o.indent(Indentation) << "return 0;" << " // Conflict set: "; - for (int i = 0, N = Opcodes.size(); i < N; ++i) { - o << nameWithID(Opcodes[i]); - if (i < (N - 1)) - o << ", "; - else - o << '\n'; - } - - // Print out useful conflict information for postmortem analysis. - errs() << "Decoding Conflict:\n"; - - dumpStack(errs(), "\t\t"); - - for (unsigned i = 0; i < Opcodes.size(); i++) { - const std::string &Name = nameWithID(Opcodes[i]); - - errs() << '\t' << Name << " "; - dumpBits(errs(), - getBitsField(*AllInstructions[Opcodes[i]]->TheDef, "Inst")); - errs() << '\n'; - } - - return true; -} - - -//////////////////////////////////////////// -// // -// ARMDEBackend // -// (Helper class for ARMDecoderEmitter) // -// // -//////////////////////////////////////////// - -class ARMDecoderEmitter::ARMDEBackend { -public: - ARMDEBackend(ARMDecoderEmitter &frontend, RecordKeeper &Records) : - NumberedInstructions(), - Opcodes(), - Frontend(frontend), - Target(Records), - FC(NULL) - { - if (Target.getName() == "ARM") - TargetName = TARGET_ARM; - else { - errs() << "Target name " << Target.getName() << " not recognized\n"; - assert(0 && "Unknown target"); - } - - // Populate the instructions for our TargetName. - populateInstructions(); - } - - ~ARMDEBackend() { - if (FC) { - delete FC; - FC = NULL; - } - } - - void getInstructionsByEnumValue(std::vector - &NumberedInstructions) { - // We must emit the PHI opcode first... - std::string Namespace = Target.getInstNamespace(); - assert(!Namespace.empty() && "No instructions defined."); - - NumberedInstructions = Target.getInstructionsByEnumValue(); - } - - bool populateInstruction(const CodeGenInstruction &CGI, TARGET_NAME_t TN); - - void populateInstructions(); - - // Emits disassembler code for instruction decoding. This delegates to the - // FilterChooser instance to do the heavy lifting. - void emit(raw_ostream &o); - -protected: - std::vector NumberedInstructions; - std::vector Opcodes; - // Special case for the ARM chip, which supports ARM and Thumb ISAs. - // Opcodes2 will be populated with the Thumb opcodes. - std::vector Opcodes2; - ARMDecoderEmitter &Frontend; - CodeGenTarget Target; - ARMFilterChooser *FC; - - TARGET_NAME_t TargetName; -}; - -bool ARMDecoderEmitter:: -ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, - TARGET_NAME_t TN) { - const Record &Def = *CGI.TheDef; - const StringRef Name = Def.getName(); - uint8_t Form = getByteField(Def, "Form"); - - BitsInit &Bits = getBitsField(Def, "Inst"); - - // If all the bit positions are not specified; do not decode this instruction. - // We are bound to fail! For proper disassembly, the well-known encoding bits - // of the instruction must be fully specified. - // - // This also removes pseudo instructions from considerations of disassembly, - // which is a better design and less fragile than the name matchings. - if (Bits.allInComplete()) return false; - - // Ignore "asm parser only" instructions. - if (Def.getValueAsBit("isAsmParserOnly")) - return false; - - if (TN == TARGET_ARM) { - if (Form == ARM_FORMAT_PSEUDO) - return false; - if (thumbInstruction(Form)) - return false; - - // Tail calls are other patterns that generate existing instructions. - if (Name == "TCRETURNdi" || Name == "TCRETURNdiND" || - Name == "TCRETURNri" || Name == "TCRETURNriND" || - Name == "TAILJMPd" || Name == "TAILJMPdt" || - Name == "TAILJMPdND" || Name == "TAILJMPdNDt" || - Name == "TAILJMPr" || Name == "TAILJMPrND" || - Name == "MOVr_TC") - return false; - - // Delegate ADR disassembly to the more generic ADDri/SUBri instructions. - if (Name == "ADR") - return false; - - // - // The following special cases are for conflict resolutions. - // - - // A8-598: VEXT - // Vector Extract extracts elements from the bottom end of the second - // operand vector and the top end of the first, concatenates them and - // places the result in the destination vector. The elements of the - // vectors are treated as being 8-bit bitfields. There is no distinction - // between data types. The size of the operation can be specified in - // assembler as vext.size. If the value is 16, 32, or 64, the syntax is - // a pseudo-instruction for a VEXT instruction specifying the equivalent - // number of bytes. - // - // Variants VEXTd16, VEXTd32, VEXTd8, and VEXTdf are reduced to VEXTd8; - // variants VEXTq16, VEXTq32, VEXTq8, and VEXTqf are reduced to VEXTq8. - if (Name == "VEXTd16" || Name == "VEXTd32" || Name == "VEXTdf" || - Name == "VEXTq16" || Name == "VEXTq32" || Name == "VEXTqf") - return false; - } else if (TN == TARGET_THUMB) { - if (!thumbInstruction(Form)) - return false; - - // A8.6.25 BX. Use the generic tBX_Rm, ignore tBX_RET and tBX_RET_vararg. - if (Name == "tBX_RET" || Name == "tBX_RET_vararg") - return false; - - // Ignore tADR, prefer tADDrPCi. - if (Name == "tADR") - return false; - - // Delegate t2ADR disassembly to the more generic t2ADDri12/t2SUBri12 - // instructions. - if (Name == "t2ADR") - return false; - - // Ignore tADDrSP, tADDspr, and tPICADD, prefer the generic tADDhirr. - // Ignore t2SUBrSPs, prefer the t2SUB[S]r[r|s]. - // Ignore t2ADDrSPs, prefer the t2ADD[S]r[r|s]. - if (Name == "tADDrSP" || Name == "tADDspr" || Name == "tPICADD" || - Name == "t2SUBrSPs" || Name == "t2ADDrSPs") - return false; - - // FIXME: Use ldr.n to work around a Darwin assembler bug. - // Introduce a workaround with tLDRpciDIS opcode. - if (Name == "tLDRpci") - return false; - - // Ignore t2LDRDpci, prefer the generic t2LDRDi8, t2LDRD_PRE, t2LDRD_POST. - if (Name == "t2LDRDpci") - return false; - - // Resolve conflicts: - // - // t2LDMIA_RET conflict with t2LDM (ditto) - // tMOVCCi conflicts with tMOVi8 - // tMOVCCr conflicts with tMOVgpr2gpr - // tLDRcp conflicts with tLDRspi - // t2MOVCCi16 conflicts with tMOVi16 - if (Name == "t2LDMIA_RET" || - Name == "tMOVCCi" || Name == "tMOVCCr" || - Name == "tLDRcp" || - Name == "t2MOVCCi16") - return false; - } - - DEBUG({ - // Dumps the instruction encoding format. - switch (TargetName) { - case TARGET_ARM: - case TARGET_THUMB: - errs() << Name << " " << stringForARMFormat((ARMFormat)Form); - break; - } - - errs() << " "; - - // Dumps the instruction encoding bits. - dumpBits(errs(), Bits); - - errs() << '\n'; - - // Dumps the list of operand info. - for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) { - const CGIOperandList::OperandInfo &Info = CGI.Operands[i]; - const std::string &OperandName = Info.Name; - const Record &OperandDef = *Info.Rec; - - errs() << "\t" << OperandName << " (" << OperandDef.getName() << ")\n"; - } - }); - - return true; -} - -void ARMDecoderEmitter::ARMDEBackend::populateInstructions() { - getInstructionsByEnumValue(NumberedInstructions); - - unsigned numUIDs = NumberedInstructions.size(); - if (TargetName == TARGET_ARM) { - for (unsigned uid = 0; uid < numUIDs; uid++) { - // filter out intrinsics - if (!NumberedInstructions[uid]->TheDef->isSubClassOf("InstARM")) - continue; - - if (populateInstruction(*NumberedInstructions[uid], TargetName)) - Opcodes.push_back(uid); - } - - // Special handling for the ARM chip, which supports two modes of execution. - // This branch handles the Thumb opcodes. - for (unsigned uid = 0; uid < numUIDs; uid++) { - // filter out intrinsics - if (!NumberedInstructions[uid]->TheDef->isSubClassOf("InstARM") - && !NumberedInstructions[uid]->TheDef->isSubClassOf("InstThumb")) - continue; - - if (populateInstruction(*NumberedInstructions[uid], TARGET_THUMB)) - Opcodes2.push_back(uid); - } - - return; - } - - // For other targets. - for (unsigned uid = 0; uid < numUIDs; uid++) { - Record *R = NumberedInstructions[uid]->TheDef; - if (R->getValueAsString("Namespace") == "TargetOpcode") - continue; - - if (populateInstruction(*NumberedInstructions[uid], TargetName)) - Opcodes.push_back(uid); - } -} - -// Emits disassembler code for instruction decoding. This delegates to the -// FilterChooser instance to do the heavy lifting. -void ARMDecoderEmitter::ARMDEBackend::emit(raw_ostream &o) { - switch (TargetName) { - case TARGET_ARM: - Frontend.EmitSourceFileHeader("ARM/Thumb Decoders", o); - break; - default: - assert(0 && "Unreachable code!"); - } - - o << "#include \"llvm/Support/DataTypes.h\"\n"; - o << "#include \n"; - o << '\n'; - o << "namespace llvm {\n\n"; - - ARMFilterChooser::setTargetName(TargetName); - - switch (TargetName) { - case TARGET_ARM: { - // Emit common utility and ARM ISA decoder. - FC = new ARMFilterChooser(NumberedInstructions, Opcodes); - // Reset indentation level. - unsigned Indentation = 0; - FC->emitTop(o, Indentation); - delete FC; - - // Emit Thumb ISA decoder as well. - ARMFilterChooser::setTargetName(TARGET_THUMB); - FC = new ARMFilterChooser(NumberedInstructions, Opcodes2); - // Reset indentation level. - Indentation = 0; - FC->emitBot(o, Indentation); - break; - } - default: - assert(0 && "Unreachable code!"); - } - - o << "\n} // End llvm namespace \n"; -} - -///////////////////////// -// Backend interface // -///////////////////////// - -void ARMDecoderEmitter::initBackend() -{ - Backend = new ARMDEBackend(*this, Records); -} - -void ARMDecoderEmitter::run(raw_ostream &o) -{ - Backend->emit(o); -} - -void ARMDecoderEmitter::shutdownBackend() -{ - delete Backend; - Backend = NULL; -} Removed: llvm/trunk/utils/TableGen/ARMDecoderEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.h?rev=144242&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.h (original) +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.h (removed) @@ -1,49 +0,0 @@ -//===------------ ARMDecoderEmitter.h - Decoder Generator -------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file is part of the ARM Disassembler. -// It contains the tablegen backend declaration ARMDecoderEmitter. -// -//===----------------------------------------------------------------------===// - -#ifndef ARMDECODEREMITTER_H -#define ARMDECODEREMITTER_H - -#include "llvm/Support/DataTypes.h" -#include "llvm/TableGen/TableGenBackend.h" - -namespace llvm { - -class ARMDecoderEmitter : public TableGenBackend { - RecordKeeper &Records; -public: - ARMDecoderEmitter(RecordKeeper &R) : Records(R) { - initBackend(); - } - - ~ARMDecoderEmitter() { - shutdownBackend(); - } - - // run - Output the code emitter - void run(raw_ostream &o); - -private: - // Helper class for ARMDecoderEmitter. - class ARMDEBackend; - - ARMDEBackend *Backend; - - void initBackend(); - void shutdownBackend(); -}; - -} // end llvm namespace - -#endif Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=144243&r1=144242&r2=144243&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp Wed Nov 9 17:56:06 2011 @@ -11,7 +11,6 @@ #include "CodeGenTarget.h" #include "X86DisassemblerTables.h" #include "X86RecognizableInstr.h" -#include "ARMDecoderEmitter.h" #include "FixedLenDecoderEmitter.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=144243&r1=144242&r2=144243&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Nov 9 17:56:06 2011 @@ -23,7 +23,6 @@ #include "IntrinsicEmitter.h" #include "PseudoLoweringEmitter.h" #include "RegisterInfoEmitter.h" -#include "ARMDecoderEmitter.h" #include "SubtargetEmitter.h" #include "SetTheory.h" @@ -44,7 +43,6 @@ GenInstrInfo, GenAsmWriter, GenAsmMatcher, - GenARMDecoder, GenDisassembler, GenPseudoLowering, GenCallingConv, @@ -73,8 +71,6 @@ "Generate calling convention descriptions"), clEnumValN(GenAsmWriter, "gen-asm-writer", "Generate assembly writer"), - clEnumValN(GenARMDecoder, "gen-arm-decoder", - "Generate decoders for ARM/Thumb"), clEnumValN(GenDisassembler, "gen-disassembler", "Generate disassembler"), clEnumValN(GenPseudoLowering, "gen-pseudo-lowering", @@ -126,9 +122,6 @@ case GenAsmWriter: AsmWriterEmitter(Records).run(OS); break; - case GenARMDecoder: - ARMDecoderEmitter(Records).run(OS); - break; case GenAsmMatcher: AsmMatcherEmitter(Records).run(OS); break; From grosbach at apple.com Wed Nov 9 18:02:33 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 10 Nov 2011 00:02:33 -0000 Subject: [llvm-commits] [llvm] r144244 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20111110000233.E04341BE001@llvm.org> Author: grosbach Date: Wed Nov 9 18:02:33 2011 New Revision: 144244 URL: http://llvm.org/viewvc/llvm-project?rev=144244&view=rev Log: Tidy up. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=144244&r1=144243&r2=144244&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 9 18:02:33 2011 @@ -4990,18 +4990,6 @@ // USAX == USUBADDX def : MnemonicAlias<"usubaddx", "usax">; -// LDRSBT/LDRHT/LDRSHT post-index offset if optional. -// Note that the write-back output register is a dummy operand for MC (it's -// only meaningful for codegen), so we just pass zero here. -// FIXME: tblgen not cooperating with argument conversions. -//def : InstAlias<"ldrsbt${p} $Rt, $addr", -// (LDRSBTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0,pred:$p)>; -//def : InstAlias<"ldrht${p} $Rt, $addr", -// (LDRHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>; -//def : InstAlias<"ldrsht${p} $Rt, $addr", -// (LDRSHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>; - - // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like // for isel. def : ARMInstAlias<"mov${s}${p} $Rd, $imm", From resistor at mac.com Wed Nov 9 18:07:22 2011 From: resistor at mac.com (Owen Anderson) Date: Thu, 10 Nov 2011 00:07:22 -0000 Subject: [llvm-commits] [llvm] r144245 - /llvm/trunk/utils/TableGen/CMakeLists.txt Message-ID: <20111110000722.BDFB31BE001@llvm.org> Author: resistor Date: Wed Nov 9 18:07:22 2011 New Revision: 144245 URL: http://llvm.org/viewvc/llvm-project?rev=144245&view=rev Log: Remove this from the CMake build since I erased the file. Modified: llvm/trunk/utils/TableGen/CMakeLists.txt Modified: llvm/trunk/utils/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=144245&r1=144244&r2=144245&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CMakeLists.txt (original) +++ llvm/trunk/utils/TableGen/CMakeLists.txt Wed Nov 9 18:07:22 2011 @@ -3,7 +3,6 @@ set(LLVM_LINK_COMPONENTS Support) add_tablegen(llvm-tblgen LLVM - ARMDecoderEmitter.cpp AsmMatcherEmitter.cpp AsmWriterEmitter.cpp AsmWriterInst.cpp From stoklund at 2pi.dk Wed Nov 9 18:17:03 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 10 Nov 2011 00:17:03 -0000 Subject: [llvm-commits] [llvm] r144247 - in /llvm/trunk: lib/CodeGen/InlineSpiller.cpp test/CodeGen/X86/2011-11-09-FoldImpDefs.ll Message-ID: <20111110001703.815FA1BE001@llvm.org> Author: stoklund Date: Wed Nov 9 18:17:03 2011 New Revision: 144247 URL: http://llvm.org/viewvc/llvm-project?rev=144247&view=rev Log: Strip old implicit operands after foldMemoryOperand. The TII.foldMemoryOperand hook preserves implicit operands from the original instruction. This is not what we want when those implicit operands refer to the register being spilled. Implicit operands referring to other registers are preserved. This fixes PR11347. Added: llvm/trunk/test/CodeGen/X86/2011-11-09-FoldImpDefs.ll Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=144247&r1=144246&r2=144247&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original) +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Wed Nov 9 18:17:03 2011 @@ -1017,14 +1017,18 @@ const SmallVectorImpl &Ops, MachineInstr *LoadMI) { bool WasCopy = MI->isCopy(); + unsigned ImpReg = 0; + // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied // operands. SmallVector FoldOps; for (unsigned i = 0, e = Ops.size(); i != e; ++i) { unsigned Idx = Ops[i]; MachineOperand &MO = MI->getOperand(Idx); - if (MO.isImplicit()) + if (MO.isImplicit()) { + ImpReg = MO.getReg(); continue; + } // FIXME: Teach targets to deal with subregs. if (MO.getSubReg()) return false; @@ -1045,7 +1049,20 @@ if (!LoadMI) VRM.addSpillSlotUse(StackSlot, FoldMI); MI->eraseFromParent(); - DEBUG(dbgs() << "\tfolded: " << *FoldMI); + + // TII.foldMemoryOperand may have left some implicit operands on the + // instruction. Strip them. + if (ImpReg) + for (unsigned i = FoldMI->getNumOperands(); i; --i) { + MachineOperand &MO = FoldMI->getOperand(i - 1); + if (!MO.isReg() || !MO.isImplicit()) + break; + if (MO.getReg() == ImpReg) + FoldMI->RemoveOperand(i - 1); + } + + DEBUG(dbgs() << "\tfolded: " << LIS.getInstructionIndex(FoldMI) << '\t' + << *FoldMI); if (!WasCopy) ++NumFolded; else if (Ops.front() == 0) Added: llvm/trunk/test/CodeGen/X86/2011-11-09-FoldImpDefs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-11-09-FoldImpDefs.ll?rev=144247&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-11-09-FoldImpDefs.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-11-09-FoldImpDefs.ll Wed Nov 9 18:17:03 2011 @@ -0,0 +1,105 @@ +; RUN: llc < %s -verify-regalloc | FileCheck %s +; PR11347 +; +; This test case materializes the constant 1 in a register: +; +; %vreg19 = MOV32ri 1 +; +; Then rematerializes the instruction for a sub-register copy: +; 1168L %vreg14:sub_8bit = COPY %vreg19:sub_8bit, %vreg14; GR32:%vreg14,%vreg19 +; Considering merging %vreg19 with %vreg14 +; RHS = %vreg19 = [560d,656L:0)[720L,976d:0)[1088L,1168d:0) 0 at 560d +; LHS = %vreg14 = [16d,160L:0)[160L,256L:2)[256L,1088L:1)[1168d,1184L:3)[1184L,1344L:2) 0 at 16d-phikill 1 at 256L-phidef-phikill 2 at 1184L-phidef-phikill 3 at 1168d-phikill +; Remat: %vreg14 = MOV32ri 1, %vreg14, %vreg14; GR32:%vreg14 +; +; This rematerialized constant is feeding a PHI that is spilled, so the constant +; is written directly to a stack slot that gets the %esi function argument in +; another basic block: +; +; CHECK: %entry +; CHECK: movl %esi, [[FI:[0-9]+\(%rsp\)]] +; CHECK: %if.else24 +; CHECK: movl $1, [[FI]] +; CHECK: %lor.end9 +; CHECK: movl [[FI]], +; +; Those operands on the MOV32ri instruction confused the spiller +; because they were preserved by TII.foldMemoryOperand. It is quite rare to +; see a rematerialized instruction spill, it can only happen when it is feeding +; a PHI. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7" + + at g_193 = external global i32, align 4 + at g_103 = external global i32, align 4 + +declare i32 @func_21(i16 signext, i32) nounwind uwtable readnone ssp + +define i32 @func_25(i32 %p_27, i8 signext %p_28, i32 %p_30) noreturn nounwind uwtable ssp { +entry: + br label %for.cond + +for.cond28.for.cond.loopexit_crit_edge: ; preds = %for.cond28thread-pre-split + store i32 0, i32* @g_103, align 4 + br label %for.cond + +for.cond: ; preds = %for.cond28thread-pre-split, %for.cond28.for.cond.loopexit_crit_edge, %entry + %l_365.0 = phi i32 [ undef, %entry ], [ %and, %for.cond28.for.cond.loopexit_crit_edge ], [ %and, %for.cond28thread-pre-split ] + %l_288.0 = phi i32 [ undef, %entry ], [ %l_288.1.ph, %for.cond28.for.cond.loopexit_crit_edge ], [ %l_288.1.ph, %for.cond28thread-pre-split ] + %l_349.0 = phi i32 [ undef, %entry ], [ %xor, %for.cond28.for.cond.loopexit_crit_edge ], [ %xor, %for.cond28thread-pre-split ] + %p_28.addr.0 = phi i8 [ %p_28, %entry ], [ %p_28.addr.1.ph, %for.cond28.for.cond.loopexit_crit_edge ], [ %p_28.addr.1.ph, %for.cond28thread-pre-split ] + br i1 undef, label %for.cond31, label %lor.end + +lor.end: ; preds = %for.cond + %tobool3 = icmp eq i32 %l_349.0, 0 + br i1 %tobool3, label %for.cond31, label %if.then + +if.then: ; preds = %lor.end + br i1 undef, label %lor.rhs6, label %lor.end9 + +lor.rhs6: ; preds = %if.then + br label %lor.end9 + +lor.end9: ; preds = %lor.rhs6, %if.then + %and = and i32 %l_365.0, 1 + %conv11 = sext i8 %p_28.addr.0 to i32 + %xor = xor i32 %and, %conv11 + br i1 false, label %if.else, label %if.end + +if.else: ; preds = %lor.end9 + br label %if.end + +if.end: ; preds = %if.else, %lor.end9 + %l_395.0 = phi i32 [ 0, %if.else ], [ 1, %lor.end9 ] + %cmp14 = icmp ne i32 %and, %conv11 + %conv15 = zext i1 %cmp14 to i32 + br i1 %cmp14, label %if.then16, label %for.cond28thread-pre-split + +if.then16: ; preds = %if.end + %or17 = or i32 %l_288.0, 1 + %call18 = tail call i32 @func_39(i32 0, i32 %or17, i32 0, i32 0) nounwind + br i1 undef, label %if.else24, label %if.then20 + +if.then20: ; preds = %if.then16 + %conv21 = trunc i32 %l_395.0 to i16 + %call22 = tail call i32 @func_21(i16 signext %conv21, i32 undef) + br label %for.cond28thread-pre-split + +if.else24: ; preds = %if.then16 + store i32 %conv15, i32* @g_193, align 4 + %conv25 = trunc i32 %l_395.0 to i8 + br label %for.cond28thread-pre-split + +for.cond28thread-pre-split: ; preds = %if.else24, %if.then20, %if.end + %l_288.1.ph = phi i32 [ %l_288.0, %if.end ], [ %or17, %if.else24 ], [ %or17, %if.then20 ] + %p_28.addr.1.ph = phi i8 [ %p_28.addr.0, %if.end ], [ %conv25, %if.else24 ], [ %p_28.addr.0, %if.then20 ] + %.pr = load i32* @g_103, align 4 + %tobool2933 = icmp eq i32 %.pr, 0 + br i1 %tobool2933, label %for.cond, label %for.cond28.for.cond.loopexit_crit_edge + +for.cond31: ; preds = %for.cond31, %lor.end, %for.cond + br label %for.cond31 +} + +declare i32 @func_39(i32, i32, i32, i32) From resistor at mac.com Wed Nov 9 18:24:06 2011 From: resistor at mac.com (Owen Anderson) Date: Wed, 09 Nov 2011 16:24:06 -0800 Subject: [llvm-commits] MachOObjectFile fix functions In-Reply-To: <6AE1604EE3EC5F4296C096518C6B77EE18123D6BC3@mail.accesssoftek.com> References: <6AE1604EE3EC5F4296C096518C6B77EE1805B07349@mail.accesssoftek.com> <6AE1604EE3EC5F4296C096518C6B77EE1805C8FA97@mail.accesssoftek.com> <6AE1604EE3EC5F4296C096518C6B77EE18123D6BC3@mail.accesssoftek.com> Message-ID: Hey Danil, Glad to see we're converging on something everyone likes. On Nov 9, 2011, at 2:41 PM, Danil Malyshev wrote: > The symbol iterator iterate all symbols from all sections, so it make sense if symbol.getOffset() will returns the file offset. But we get relocations only for selected section, so relocation.getOffset() should return offset from this section. In addition we can get section virtual address or section offset one time and use it for each relocation in this section. I see your reasoning here, but it scares me a little bit to have methods with the same name that do different things. I think we should either rename them to be obviously different, or pick a consistent meaning for all of them. --Owen -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/fb017e2c/attachment.html From nlewycky at google.com Wed Nov 9 18:47:11 2011 From: nlewycky at google.com (Nick Lewycky) Date: Wed, 9 Nov 2011 16:47:11 -0800 Subject: [llvm-commits] don't emit debug info for all contexts Message-ID: This patch fixes PR11345, a case where we emit debug info for a class, just because we define a static member inside the class. This is implemented by changing getContextDescriptor() to use a newly refactored getTypeOrFwdDecl() method, instead of always requiring a full definition. Please review! In particular, this patch causes the code that emits pointers which used to always emit a new fwd-decl of the record type, to now use the full type if that type is already defined and emitted. I don't think this has any ill effects, but it's difficult to prove. Nick -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/500c24bf/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: pr11345-1.patch Type: text/x-patch Size: 5568 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/500c24bf/attachment.bin From daniel at zuster.org Wed Nov 9 18:49:43 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 10 Nov 2011 00:49:43 -0000 Subject: [llvm-commits] [llvm] r144249 - /llvm/trunk/utils/llvm-build/llvmbuild/main.py Message-ID: <20111110004943.32A901BE001@llvm.org> Author: ddunbar Date: Wed Nov 9 18:49:42 2011 New Revision: 144249 URL: http://llvm.org/viewvc/llvm-project?rev=144249&view=rev Log: llvm-build: Tidy up options. Modified: llvm/trunk/utils/llvm-build/llvmbuild/main.py Modified: llvm/trunk/utils/llvm-build/llvmbuild/main.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm-build/llvmbuild/main.py?rev=144249&r1=144248&r2=144249&view=diff ============================================================================== --- llvm/trunk/utils/llvm-build/llvmbuild/main.py (original) +++ llvm/trunk/utils/llvm-build/llvmbuild/main.py Wed Nov 9 18:49:42 2011 @@ -487,32 +487,41 @@ def main(): from optparse import OptionParser, OptionGroup parser = OptionParser("usage: %prog [options]") - parser.add_option("", "--source-root", dest="source_root", metavar="PATH", + + group = OptionGroup(parser, "Input Options") + group.add_option("", "--source-root", dest="source_root", metavar="PATH", help="Path to the LLVM source (inferred if not given)", action="store", default=None) - parser.add_option("", "--print-tree", dest="print_tree", - help="Print out the project component tree [%default]", - action="store_true", default=False) - parser.add_option("", "--write-llvmbuild", dest="write_llvmbuild", + group.add_option("", "--llvmbuild-source-root", + dest="llvmbuild_source_root", + help=( + "If given, an alternate path to search for LLVMBuild.txt files"), + action="store", default=None, metavar="PATH") + parser.add_option_group(group) + + group = OptionGroup(parser, "Output Options") + group.add_option("", "--print-tree", dest="print_tree", + help="Print out the project component tree [%default]", + action="store_true", default=False) + group.add_option("", "--write-llvmbuild", dest="write_llvmbuild", help="Write out the LLVMBuild.txt files to PATH", action="store", default=None, metavar="PATH") - parser.add_option("", "--write-library-table", - dest="write_library_table", metavar="PATH", - help="Write the C++ library dependency table to PATH", - action="store", default=None) - parser.add_option("", "--write-cmake-fragment", - dest="write_cmake_fragment", metavar="PATH", - help="Write the CMake project information to PATH", - action="store", default=None) - parser.add_option("", "--write-make-fragment", + group.add_option("", "--write-library-table", + dest="write_library_table", metavar="PATH", + help="Write the C++ library dependency table to PATH", + action="store", default=None) + group.add_option("", "--write-cmake-fragment", + dest="write_cmake_fragment", metavar="PATH", + help="Write the CMake project information to PATH", + action="store", default=None) + group.add_option("", "--write-make-fragment", dest="write_make_fragment", metavar="PATH", - help="Write the Makefile project information to PATH", + help="Write the Makefile project information to PATH", + action="store", default=None) + parser.add_option_group(group) action="store", default=None) - parser.add_option("", "--llvmbuild-source-root", - dest="llvmbuild_source_root", - help=( - "If given, an alternate path to search for LLVMBuild.txt files"), - action="store", default=None, metavar="PATH") + parser.add_option_group(group) + (opts, args) = parser.parse_args() # Determine the LLVM source path, if not given. From daniel at zuster.org Wed Nov 9 18:49:52 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 10 Nov 2011 00:49:52 -0000 Subject: [llvm-commits] [llvm] r144250 - in /llvm/trunk: docs/LLVMBuild.html lib/Target/ARM/LLVMBuild.txt lib/Target/CBackend/LLVMBuild.txt lib/Target/CellSPU/LLVMBuild.txt lib/Target/CppBackend/LLVMBuild.txt lib/Target/MBlaze/LLVMBuild.txt lib/Target/MSP430/LLVMBuild.txt lib/Target/Mips/LLVMBuild.txt lib/Target/PTX/LLVMBuild.txt lib/Target/PowerPC/LLVMBuild.txt lib/Target/Sparc/LLVMBuild.txt lib/Target/X86/LLVMBuild.txt lib/Target/XCore/LLVMBuild.txt utils/llvm-build/llvmbuild/componentinfo.py utils/llvm-build/llvmbuild/main.py Message-ID: <20111110004952.8C6471BE001@llvm.org> Author: ddunbar Date: Wed Nov 9 18:49:51 2011 New Revision: 144250 URL: http://llvm.org/viewvc/llvm-project?rev=144250&view=rev Log: llvm-build: Add an explicit component type to represent targets. - Gives us a place to hang target specific metadata (like whether the target has a JIT). Modified: llvm/trunk/docs/LLVMBuild.html llvm/trunk/lib/Target/ARM/LLVMBuild.txt llvm/trunk/lib/Target/CBackend/LLVMBuild.txt llvm/trunk/lib/Target/CellSPU/LLVMBuild.txt llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt llvm/trunk/lib/Target/MBlaze/LLVMBuild.txt llvm/trunk/lib/Target/MSP430/LLVMBuild.txt llvm/trunk/lib/Target/Mips/LLVMBuild.txt llvm/trunk/lib/Target/PTX/LLVMBuild.txt llvm/trunk/lib/Target/PowerPC/LLVMBuild.txt llvm/trunk/lib/Target/Sparc/LLVMBuild.txt llvm/trunk/lib/Target/X86/LLVMBuild.txt llvm/trunk/lib/Target/XCore/LLVMBuild.txt llvm/trunk/utils/llvm-build/llvmbuild/componentinfo.py llvm/trunk/utils/llvm-build/llvmbuild/main.py Modified: llvm/trunk/docs/LLVMBuild.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LLVMBuild.html?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/docs/LLVMBuild.html (original) +++ llvm/trunk/docs/LLVMBuild.html Wed Nov 9 18:49:51 2011 @@ -134,7 +134,7 @@ -

    LLVMBuild Format Reference

    +

    LLVMBuild Format Reference

    @@ -151,11 +151,12 @@ ; Properties are declared using '=' and are contained in the previous section. ; -; We support simple scalar values and list values, where items are separated by -; spaces. There is no support for quoting, and so property values may not contain -; spaces. +; We support simple string and boolean scalar values and list values, where +; items are separated by spaces. There is no support for quoting, and so +; property values may not contain spaces. property_name = property_value list_property_name = value_1 value_2 ... value_n +boolean_property_name = 1 (or 0)
    @@ -281,6 +282,21 @@ +
  • type = TargetGroup +

    TargetGroup components are an extension of LibraryGroups, specifically + for defining LLVM targets (which are handled specially in a few + places).

    + +

    The name of the component should always be the name of the target.

    + +

    Components with this type use the LibraryGroup properties in addition + to:

    +
      +
    • has_jit [optional] [boolean] +

      Whether this target supports JIT compilation.

      • +
    +
    • +
  • type = Tool

    Tool components define standalone command line tools which should be built from the source code in the component directory and linked.

    Modified: llvm/trunk/lib/Target/ARM/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/ARM/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,10 +16,11 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = ARM parent = Target add_to_library_groups = all-targets +has_jit = 1 [component_1] type = Library Modified: llvm/trunk/lib/Target/CBackend/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/CBackend/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = CBackend parent = Target add_to_library_groups = all-targets Modified: llvm/trunk/lib/Target/CellSPU/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/CellSPU/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = CellSPU parent = Target add_to_library_groups = all-targets Modified: llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = CppBackend parent = Target add_to_library_groups = all-targets Modified: llvm/trunk/lib/Target/MBlaze/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/MBlaze/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = MBlaze parent = Target add_to_library_groups = all-targets Modified: llvm/trunk/lib/Target/MSP430/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/MSP430/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = MSP430 parent = Target add_to_library_groups = all-targets Modified: llvm/trunk/lib/Target/Mips/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/Mips/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,10 +16,11 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = Mips parent = Target add_to_library_groups = all-targets +has_jit = 1 [component_1] type = Library Modified: llvm/trunk/lib/Target/PTX/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/PTX/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = PTX parent = Target add_to_library_groups = all-targets Modified: llvm/trunk/lib/Target/PowerPC/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/PowerPC/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,10 +16,11 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = PowerPC parent = Target add_to_library_groups = all-targets +has_jit = 1 [component_1] type = Library Modified: llvm/trunk/lib/Target/Sparc/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/Sparc/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = Sparc parent = Target add_to_library_groups = all-targets Modified: llvm/trunk/lib/Target/X86/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/X86/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,10 +16,11 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = X86 parent = Target add_to_library_groups = all-targets +has_jit = 1 [component_1] type = Library Modified: llvm/trunk/lib/Target/XCore/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/LLVMBuild.txt?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/XCore/LLVMBuild.txt Wed Nov 9 18:49:51 2011 @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [component_0] -type = LibraryGroup +type = TargetGroup name = XCore parent = Target add_to_library_groups = all-targets Modified: llvm/trunk/utils/llvm-build/llvmbuild/componentinfo.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm-build/llvmbuild/componentinfo.py?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/utils/llvm-build/llvmbuild/componentinfo.py (original) +++ llvm/trunk/utils/llvm-build/llvmbuild/componentinfo.py Wed Nov 9 18:49:51 2011 @@ -188,6 +188,60 @@ def get_llvmconfig_component_name(self): return self.name.lower() +class TargetGroupComponentInfo(ComponentInfo): + type_name = 'TargetGroup' + + @staticmethod + def parse(subpath, items): + kwargs = ComponentInfo.parse_items(items, has_dependencies = False) + kwargs['required_libraries'] = items.get_list('required_libraries') + kwargs['add_to_library_groups'] = items.get_list( + 'add_to_library_groups') + kwargs['has_jit'] = items.get_optional_bool('has_jit', False) + return TargetGroupComponentInfo(subpath, **kwargs) + + def __init__(self, subpath, name, parent, required_libraries = [], + add_to_library_groups = [], has_jit = False): + ComponentInfo.__init__(self, subpath, name, [], parent) + + # The names of the library components which are required when linking + # with this component. + self.required_libraries = list(required_libraries) + + # The names of the library group components this component should be + # considered part of. + self.add_to_library_groups = list(add_to_library_groups) + + # Whether or not this target supports the JIT. + self.has_jit = bool(has_jit) + + def get_component_references(self): + for r in ComponentInfo.get_component_references(self): + yield r + for r in self.required_libraries: + yield ('required library', r) + for r in self.add_to_library_groups: + yield ('library group', r) + + def get_llvmbuild_fragment(self): + result = StringIO.StringIO() + print >>result, 'type = %s' % self.type_name + print >>result, 'name = %s' % self.name + print >>result, 'parent = %s' % self.parent + if self.required_libraries: + print >>result, 'required_libraries = %s' % ' '.join( + self.required_libraries) + if self.add_to_library_groups: + print >>result, 'add_to_library_groups = %s' % ' '.join( + self.add_to_library_groups) + if self.has_jit: + print >>result, 'has_jit = %s' % ' '.join( + int(self.has_jit)) + return result.getvalue() + + def get_llvmconfig_component_name(self): + return self.name.lower() + class ToolComponentInfo(ComponentInfo): type_name = 'Tool' @@ -255,11 +309,27 @@ raise ParseError("missing value for required string: %r" % key) return value + def get_optional_bool(self, key, default = None): + value = self.get_optional_string(key) + if not value: + return default + if value not in ('0', '1'): + raise ParseError("invalid value(%r) for boolean property: %r" % ( + value, key)) + return bool(int(value)) + + def get_bool(self, key): + value = self.get_optional_bool(key) + if value is None: + raise ParseError("missing value for required boolean: %r" % key) + return value + _component_type_map = dict( (t.type_name, t) for t in (GroupComponentInfo, LibraryComponentInfo, LibraryGroupComponentInfo, - ToolComponentInfo, BuildToolComponentInfo)) + ToolComponentInfo, BuildToolComponentInfo, + TargetGroupComponentInfo)) def load_from_path(path, subpath): # Load the LLVMBuild.txt file as an .ini format file. parser = ConfigParser.RawConfigParser() Modified: llvm/trunk/utils/llvm-build/llvmbuild/main.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm-build/llvmbuild/main.py?rev=144250&r1=144249&r2=144250&view=diff ============================================================================== --- llvm/trunk/utils/llvm-build/llvmbuild/main.py (original) +++ llvm/trunk/utils/llvm-build/llvmbuild/main.py Wed Nov 9 18:49:51 2011 @@ -242,8 +242,8 @@ # dependencies for added library groups. entries = {} for c in self.ordered_component_infos: - # Only Library and LibraryGroup components are in the table. - if c.type_name not in ('Library', 'LibraryGroup'): + # Only certain components are in the table. + if c.type_name not in ('Library', 'LibraryGroup', 'TargetGroup'): continue # Compute the llvm-config "component name". For historical reasons, @@ -251,10 +251,10 @@ llvmconfig_component_name = c.get_llvmconfig_component_name() # Get the library name, or None for LibraryGroups. - if c.type_name == 'LibraryGroup': - library_name = None - else: + if c.type_name == 'Library': library_name = c.get_library_name() + else: + library_name = None # Get the component names of all the required libraries. required_llvmconfig_component_names = [ From daniel at zuster.org Wed Nov 9 18:49:56 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 10 Nov 2011 00:49:56 -0000 Subject: [llvm-commits] [llvm] r144251 - in /llvm/trunk/lib/Target: CBackend/LLVMBuild.txt CppBackend/LLVMBuild.txt Message-ID: <20111110004956.3204A1BE001@llvm.org> Author: ddunbar Date: Wed Nov 9 18:49:55 2011 New Revision: 144251 URL: http://llvm.org/viewvc/llvm-project?rev=144251&view=rev Log: llvm-build: Change CBackend and CppBackend to not use library_name. This will change the generated library .a file name once we fully switch over, but simplifies how we treat these targets without requiring more special casing (since their library group name and the codegen library name currently map to the same "llvm-config" style component name). Modified: llvm/trunk/lib/Target/CBackend/LLVMBuild.txt llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt Modified: llvm/trunk/lib/Target/CBackend/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/LLVMBuild.txt?rev=144251&r1=144250&r2=144251&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/CBackend/LLVMBuild.txt Wed Nov 9 18:49:55 2011 @@ -25,7 +25,6 @@ type = Library name = CBackendCodeGen parent = CBackend -library_name = CBackend required_libraries = Analysis CBackendInfo CodeGen Core MC Scalar Support Target TransformUtils add_to_library_groups = CBackend Modified: llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt?rev=144251&r1=144250&r2=144251&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt Wed Nov 9 18:49:55 2011 @@ -25,7 +25,6 @@ type = Library name = CppBackendCodeGen parent = CppBackend -library_name = CppBackend required_libraries = Core CppBackendInfo Support Target add_to_library_groups = CppBackend From daniel at zuster.org Wed Nov 9 18:49:59 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 10 Nov 2011 00:49:59 -0000 Subject: [llvm-commits] [llvm] r144252 - /llvm/trunk/utils/llvm-build/llvmbuild/main.py Message-ID: <20111110004959.196F71BE001@llvm.org> Author: ddunbar Date: Wed Nov 9 18:49:58 2011 New Revision: 144252 URL: http://llvm.org/viewvc/llvm-project?rev=144252&view=rev Log: llvm-build: Split out the validation logic. Modified: llvm/trunk/utils/llvm-build/llvmbuild/main.py Modified: llvm/trunk/utils/llvm-build/llvmbuild/main.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm-build/llvmbuild/main.py?rev=144252&r1=144251&r2=144252&view=diff ============================================================================== --- llvm/trunk/utils/llvm-build/llvmbuild/main.py (original) +++ llvm/trunk/utils/llvm-build/llvmbuild/main.py Wed Nov 9 18:49:58 2011 @@ -83,12 +83,26 @@ def __init__(self, source_root, component_infos): # Store our simple ivars. self.source_root = source_root - self.component_infos = component_infos + self.component_infos = list(component_infos) + self.component_info_map = None + self.ordered_component_infos = None + + def validate_components(self): + """validate_components() -> None + + Validate that the project components are well-defined. Among other + things, this checks that: + - Components have valid references. + - Components references do not form cycles. + + We also construct the map from component names to info, and the + topological ordering of components. + """ # Create the component info map and validate that component names are # unique. self.component_info_map = {} - for ci in component_infos: + for ci in self.component_infos: existing = self.component_info_map.get(ci.name) if existing is not None: # We found a duplicate component name, report it and error out. @@ -157,7 +171,7 @@ # out easily. If we don't, we should special case the check. self.ordered_component_infos = [] - components_to_visit = set(component_infos) + components_to_visit = set(self.component_infos) while components_to_visit: visit_component_info(iter(components_to_visit).next(), [], set()) @@ -544,6 +558,9 @@ project_info = LLVMProjectInfo.load_from_path( source_root, llvmbuild_source_root) + # Validate the project component info. + project_info.validate_components() + # Print the component tree, if requested. if opts.print_tree: project_info.print_tree() From daniel at zuster.org Wed Nov 9 18:50:07 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 10 Nov 2011 00:50:07 -0000 Subject: [llvm-commits] [llvm] r144253 - in /llvm/trunk: lib/Target/ lib/Target/ARM/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Target/XCore/ utils/llvm-build/llvmbuild/ Message-ID: <20111110005008.161901BE001@llvm.org> Author: ddunbar Date: Wed Nov 9 18:50:07 2011 New Revision: 144253 URL: http://llvm.org/viewvc/llvm-project?rev=144253&view=rev Log: llvm-build: Add --native-target and --enable-targets options, and add logic to handle defining the "magic" target related components (like native, nativecodegen, and engine). - We still require these components to be in the project (currently in lib/Target) so that we have a place to document them and hopefully make it more obvious that they are "magic". Modified: llvm/trunk/lib/Target/ARM/LLVMBuild.txt llvm/trunk/lib/Target/CBackend/LLVMBuild.txt llvm/trunk/lib/Target/CellSPU/LLVMBuild.txt llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt llvm/trunk/lib/Target/LLVMBuild.txt llvm/trunk/lib/Target/MBlaze/LLVMBuild.txt llvm/trunk/lib/Target/MSP430/LLVMBuild.txt llvm/trunk/lib/Target/Mips/LLVMBuild.txt llvm/trunk/lib/Target/PTX/LLVMBuild.txt llvm/trunk/lib/Target/PowerPC/LLVMBuild.txt llvm/trunk/lib/Target/Sparc/LLVMBuild.txt llvm/trunk/lib/Target/X86/LLVMBuild.txt llvm/trunk/lib/Target/XCore/LLVMBuild.txt llvm/trunk/utils/llvm-build/llvmbuild/componentinfo.py llvm/trunk/utils/llvm-build/llvmbuild/main.py Modified: llvm/trunk/lib/Target/ARM/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/ARM/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = ARM parent = Target -add_to_library_groups = all-targets has_jit = 1 [component_1] Modified: llvm/trunk/lib/Target/CBackend/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/CBackend/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = CBackend parent = Target -add_to_library_groups = all-targets [component_1] type = Library Modified: llvm/trunk/lib/Target/CellSPU/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/CellSPU/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = CellSPU parent = Target -add_to_library_groups = all-targets [component_1] type = Library Modified: llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/CppBackend/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = CppBackend parent = Target -add_to_library_groups = all-targets [component_1] type = Library Modified: llvm/trunk/lib/Target/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -21,20 +21,32 @@ parent = Libraries required_libraries = Core MC Support +; This is a convenient group we define (and expect targets to add to) which +; makes it easy for tools to include every target. [component_1] type = LibraryGroup name = all-targets parent = Libraries +; This is a special group whose required libraries are extended (by llvm-build) +; with the configured native target, if any. [component_2] type = LibraryGroup -name = native +name = Native parent = Libraries -required_libraries = X86 +; This is a special group whose required libraries are extended (by llvm-build) +; with the configured native code generator, if any. [component_3] type = LibraryGroup -name = nativecodegen +name = NativeCodeGen +parent = Libraries + +; This is a special group whose required libraries are extended (by llvm-build) +; with the best execution engine (the native JIT, if available, or the +; interpreter). +[component_4] +type = LibraryGroup +name = Engine parent = Libraries -required_libraries = X86CodeGen Modified: llvm/trunk/lib/Target/MBlaze/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/MBlaze/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = MBlaze parent = Target -add_to_library_groups = all-targets [component_1] type = Library Modified: llvm/trunk/lib/Target/MSP430/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/MSP430/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = MSP430 parent = Target -add_to_library_groups = all-targets [component_1] type = Library Modified: llvm/trunk/lib/Target/Mips/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/Mips/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = Mips parent = Target -add_to_library_groups = all-targets has_jit = 1 [component_1] Modified: llvm/trunk/lib/Target/PTX/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/PTX/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = PTX parent = Target -add_to_library_groups = all-targets [component_1] type = Library Modified: llvm/trunk/lib/Target/PowerPC/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/PowerPC/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = PowerPC parent = Target -add_to_library_groups = all-targets has_jit = 1 [component_1] Modified: llvm/trunk/lib/Target/Sparc/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/Sparc/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = Sparc parent = Target -add_to_library_groups = all-targets [component_1] type = Library Modified: llvm/trunk/lib/Target/X86/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/X86/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = X86 parent = Target -add_to_library_groups = all-targets has_jit = 1 [component_1] Modified: llvm/trunk/lib/Target/XCore/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/LLVMBuild.txt?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/XCore/LLVMBuild.txt Wed Nov 9 18:50:07 2011 @@ -19,7 +19,6 @@ type = TargetGroup name = XCore parent = Target -add_to_library_groups = all-targets [component_1] type = Library Modified: llvm/trunk/utils/llvm-build/llvmbuild/componentinfo.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm-build/llvmbuild/componentinfo.py?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/utils/llvm-build/llvmbuild/componentinfo.py (original) +++ llvm/trunk/utils/llvm-build/llvmbuild/componentinfo.py Wed Nov 9 18:50:07 2011 @@ -215,6 +215,10 @@ # Whether or not this target supports the JIT. self.has_jit = bool(has_jit) + # Whether or not this target is enabled. This is set in response to + # configuration parameters. + self.enabled = False + def get_component_references(self): for r in ComponentInfo.get_component_references(self): yield r Modified: llvm/trunk/utils/llvm-build/llvmbuild/main.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm-build/llvmbuild/main.py?rev=144253&r1=144252&r2=144253&view=diff ============================================================================== --- llvm/trunk/utils/llvm-build/llvmbuild/main.py (original) +++ llvm/trunk/utils/llvm-build/llvmbuild/main.py Wed Nov 9 18:50:07 2011 @@ -498,6 +498,105 @@ f.close() +def add_magic_target_components(parser, project, opts): + """add_magic_target_components(project, opts) -> None + + Add the "magic" target based components to the project, which can only be + determined based on the target configuration options. + + This currently is responsible for populating the required_libraries list of + the "Native", "NativeCodeGen", and "Engine" components. + """ + + # Determine the available targets. + available_targets = dict((ci.name,ci) + for ci in project.component_infos + if ci.type_name == 'TargetGroup') + + # Find the configured native target. + + # We handle a few special cases of target names here for historical + # reasons, as these are the names configure currently comes up with. + native_target_name = { 'x86' : 'X86', + 'x86_64' : 'X86', + 'Unknown' : None }.get(opts.native_target, + opts.native_target) + if native_target_name is None: + native_target = None + else: + native_target = available_targets.get(native_target_name) + if native_target is None: + parser.error("invalid native target: %r (not in project)" % ( + opts.native_target,)) + if native_target.type_name != 'TargetGroup': + parser.error("invalid native target: %r (not a target)" % ( + opts.native_target,)) + + # Find the list of targets to enable. + if opts.enable_targets is None: + enable_targets = available_targets.values() + else: + enable_targets = [] + for name in opts.enable_targets.split(): + target = available_targets.get(name) + if target is None: + parser.error("invalid target to enable: %r (not in project)" % ( + name,)) + if target.type_name != 'TargetGroup': + parser.error("invalid target to enable: %r (not a target)" % ( + name,)) + enable_targets.append(target) + + # Find the special library groups we are going to populate. We enforce that + # these appear in the project (instead of just adding them) so that they at + # least have an explicit representation in the project LLVMBuild files (and + # comments explaining how they are populated). + def find_special_group(name): + info = info_map.get(name) + if info is None: + fatal("expected project to contain special %r component" % ( + name,)) + + if info.type_name != 'LibraryGroup': + fatal("special component %r should be a LibraryGroup" % ( + name,)) + + if info.required_libraries: + fatal("special component %r must have empty %r list" % ( + name, 'required_libraries')) + if info.add_to_library_groups: + fatal("special component %r must have empty %r list" % ( + name, 'add_to_library_groups')) + + return info + + info_map = dict((ci.name, ci) for ci in project.component_infos) + all_targets = find_special_group('all-targets') + native_group = find_special_group('Native') + native_codegen_group = find_special_group('NativeCodeGen') + engine_group = find_special_group('Engine') + + # Set the enabled bit in all the target groups, and append to the + # all-targets list. + for ci in enable_targets: + all_targets.required_libraries.append(ci.name) + ci.enabled = True + + # If we have a native target, then that defines the native and + # native_codegen libraries. + if native_target and native_target.enabled: + native_group.required_libraries.append(native_target.name) + native_codegen_group.required_libraries.append( + '%sCodeGen' % native_target.name) + + # If we have a native target with a JIT, use that for the engine. Otherwise, + # use the interpreter. + if native_target and native_target.enabled and native_target.has_jit: + engine_group.required_libraries.append('JIT') + engine_group.required_libraries.append(native_group.name) + else: + engine_group.required_libraries.append('Interpreter') + def main(): from optparse import OptionParser, OptionGroup parser = OptionParser("usage: %prog [options]") @@ -533,6 +632,17 @@ help="Write the Makefile project information to PATH", action="store", default=None) parser.add_option_group(group) + + group = OptionGroup(parser, "Configuration Options") + group.add_option("", "--native-target", + dest="native_target", metavar="NAME", + help=("Treat the named target as the 'native' one, if " + "given [%default]"), + action="store", default=None) + group.add_option("", "--enable-targets", + dest="enable_targets", metavar="NAMES", + help=("Enable the given space separated list of targets, " + "or all targets if not present"), action="store", default=None) parser.add_option_group(group) @@ -558,6 +668,9 @@ project_info = LLVMProjectInfo.load_from_path( source_root, llvmbuild_source_root) + # Add the magic target based components. + add_magic_target_components(parser, project_info, opts) + # Validate the project component info. project_info.validate_components() From chandlerc at google.com Wed Nov 9 19:15:58 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 9 Nov 2011 17:15:58 -0800 Subject: [llvm-commits] [llvm] r144188 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll In-Reply-To: <20111109142048.965491BE001@llvm.org> References: <20111109142048.965491BE001@llvm.org> Message-ID: On Wed, Nov 9, 2011 at 6:20 AM, Duncan Sands wrote: > Author: baldrick > Date: Wed Nov 9 08:20:48 2011 > New Revision: 144188 > > URL: http://llvm.org/viewvc/llvm-project?rev=144188&view=rev > Log: > Speculatively revert commit 144124 (djg) in the hope that the 32 bit > dragonegg self-host buildbot will recover (it is complaining about object > files differing between different build stages). Original commit message: > > Add a hack to the scheduler to disable pseudo-two-address dependencies in > basic blocks containing calls. This works around a problem in which > these artificial dependencies can get tied up in calling seqeunce > scheduling in a way that makes the graph unschedulable with the current > approach of using artificial physical register dependencies for calling > sequences. This fixes PR11314. Evan, I'm told I should ping you, as this leaves us with a crash-on-valid regression checked in. Nick asked Dan to revert the underlying patch, and he said to ask you. I'm a bit concerned with the situation this leaves the tree in, as we have reverted a fix to a crasher regression in order to fix a stage2/stage3 regression. That doesn't really improve the state of mainline LLVM; if anything it makes it worse. What's the motivation for keeping r143660 checked in? We're trying to cut a release, and we can't because mainline is broken. We're not the only ones (or a local patch would work well), and generally this violates the spirit of the LLVM mainline: revert until green. This is particularly strange as Duncan has partially pursued the policy of revert when a patch causes a regression, and justified the revert on that policy, but we're now told we can't *finish* reverting until the regressions are gone... -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/53815709/attachment.html From daniel at zuster.org Wed Nov 9 19:16:48 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 10 Nov 2011 01:16:48 -0000 Subject: [llvm-commits] [llvm] r144255 - in /llvm/trunk: CMakeLists.txt Makefile.rules lib/Target/LLVMBuild.txt utils/llvm-build/llvmbuild/main.py Message-ID: <20111110011648.E092F1BE001@llvm.org> Author: ddunbar Date: Wed Nov 9 19:16:48 2011 New Revision: 144255 URL: http://llvm.org/viewvc/llvm-project?rev=144255&view=rev Log: build/Make & CMake: Pass the appropriate --native-target and --enable-targets options to llvm-build, so the all-targets etc. components are defined properly. Modified: llvm/trunk/CMakeLists.txt llvm/trunk/Makefile.rules llvm/trunk/lib/Target/LLVMBuild.txt llvm/trunk/utils/llvm-build/llvmbuild/main.py Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=144255&r1=144254&r2=144255&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Wed Nov 9 19:16:48 2011 @@ -236,6 +236,8 @@ message(STATUS "Constructing LLVMBuild project information") execute_process( COMMAND ${PYTHON_EXECUTABLE} ${LLVMBUILDTOOL} + --native-target "${LLVM_NATIVE_ARCH}" + --enable-targets "${LLVM_TARGETS_TO_BUILD}" --write-library-table ${LLVMCONFIGLIBRARYDEPENDENCIESINC} --write-cmake-fragment ${LLVMBUILDCMAKEFRAG} ERROR_VARIABLE LLVMBUILDOUTPUT Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=144255&r1=144254&r2=144255&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Wed Nov 9 19:16:48 2011 @@ -92,6 +92,8 @@ $(LLVMBuildMakeFrag): $(PROJ_SRC_ROOT)/Makefile.rules $(Echo) Constructing LLVMBuild project information. $(Verb) $(LLVMBuildTool) \ + --native-target "$(ARCH)" \ + --enable-targets "$(TARGETS_TO_BUILD)" \ --write-library-table $(LLVMConfigLibraryDependenciesInc) \ --write-make-fragment $(LLVMBuildMakeFrag) Modified: llvm/trunk/lib/Target/LLVMBuild.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/LLVMBuild.txt?rev=144255&r1=144254&r2=144255&view=diff ============================================================================== --- llvm/trunk/lib/Target/LLVMBuild.txt (original) +++ llvm/trunk/lib/Target/LLVMBuild.txt Wed Nov 9 19:16:48 2011 @@ -21,8 +21,9 @@ parent = Libraries required_libraries = Core MC Support -; This is a convenient group we define (and expect targets to add to) which -; makes it easy for tools to include every target. +; This is a special group whose required libraries are extended (by llvm-build) +; with every built target, which makes it easy for tools to include every +; target. [component_1] type = LibraryGroup name = all-targets Modified: llvm/trunk/utils/llvm-build/llvmbuild/main.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm-build/llvmbuild/main.py?rev=144255&r1=144254&r2=144255&view=diff ============================================================================== --- llvm/trunk/utils/llvm-build/llvmbuild/main.py (original) +++ llvm/trunk/utils/llvm-build/llvmbuild/main.py Wed Nov 9 19:16:48 2011 @@ -505,7 +505,7 @@ determined based on the target configuration options. This currently is responsible for populating the required_libraries list of - the "Native", "NativeCodeGen", and "Engine" components. + the "all-targets", "Native", "NativeCodeGen", and "Engine" components. """ # Determine the available targets. @@ -536,8 +536,14 @@ if opts.enable_targets is None: enable_targets = available_targets.values() else: + # We support both space separated and semi-colon separated lists. + if ' ' in opts.enable_targets: + enable_target_names = opts.enable_targets.split() + else: + enable_target_names = opts.enable_targets.split(';') + enable_targets = [] - for name in opts.enable_targets.split(): + for name in enable_target_names: target = available_targets.get(name) if target is None: parser.error("invalid target to enable: %r (not in project)" % ( @@ -641,8 +647,8 @@ action="store", default=None) group.add_option("", "--enable-targets", dest="enable_targets", metavar="NAMES", - help=("Enable the given space separated list of targets, " - "or all targets if not present"), + help=("Enable the given space or semi-colon separated " + "list of targets, or all targets if not present"), action="store", default=None) parser.add_option_group(group) From mcrosier at apple.com Wed Nov 9 19:30:39 2011 From: mcrosier at apple.com (Chad Rosier) Date: Thu, 10 Nov 2011 01:30:39 -0000 Subject: [llvm-commits] [llvm] r144258 - in /llvm/trunk: lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel-cmp-imm.ll Message-ID: <20111110013039.C21A41BE001@llvm.org> Author: mcrosier Date: Wed Nov 9 19:30:39 2011 New Revision: 144258 URL: http://llvm.org/viewvc/llvm-project?rev=144258&view=rev Log: For immediate encodings of icmp, zero or sign extend first. Then determine if the value is negative and flip the sign accordingly. rdar://10422026 Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144258&r1=144257&r2=144258&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Nov 9 19:30:39 2011 @@ -1216,7 +1216,6 @@ // Check to see if the 2nd operand is a constant that we can encode directly // in the compare. - uint64_t Imm; int EncodedImm = 0; bool EncodeImm = false; bool isNegativeImm = false; @@ -1224,10 +1223,11 @@ if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) { const APInt &CIVal = ConstInt->getValue(); - - isNegativeImm = CIVal.isNegative(); - Imm = (isNegativeImm) ? (-CIVal).getZExtValue() : CIVal.getZExtValue(); - EncodedImm = (int)Imm; + EncodedImm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue(); + if (EncodedImm < 0) { + isNegativeImm = true; + EncodedImm = -EncodedImm; + } EncodeImm = isThumb2 ? (ARM_AM::getT2SOImmVal(EncodedImm) != -1) : (ARM_AM::getSOImmVal(EncodedImm) != -1); } Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll?rev=144258&r1=144257&r2=144258&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll Wed Nov 9 19:30:39 2011 @@ -212,3 +212,20 @@ if.end: ; preds = %if.then, %entry ret void } + +define void @t12(i8 %a) uwtable ssp { +entry: +; ARM: t12 +; THUMB: t12 + %cmp = icmp ugt i8 %a, -113 +; ARM: cmp r{{[0-9]}}, #143 +; THUMB: cmp r{{[0-9]}}, #143 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} From dschuff at google.com Wed Nov 9 18:57:38 2011 From: dschuff at google.com (Derek Schuff) Date: Wed, 9 Nov 2011 16:57:38 -0800 Subject: [llvm-commits] Proposal/patch: Enable bitcode streaming Message-ID: Hello all, The following is a proposal (and a prototype patch) to enable bitcode streaming. The overall goal is to be able to overlap bitcode reading/download with compilation, a functionality useful obviously for pnacl and renderscript but also potentially for any situation where the interface between the frontend and backend is something other than a file. In the current state of the world, at a high level, there are 2 things keeping this from happening. The first is that BitcodeReader construction takes a MemoryBuffer which it expects to be filled with bitcode, and inside BitcodeReader, the BitstreamCursor (which is the primary interface to the bitcode itself) gets pointers to the bitcode in memory, and does all of its magic with pointer arithmetic. The second issue is that in BitcodeReader::ParseModule (which is run when right after the Module and BitcodeReader objects are created), the reader makes a pass over the entire bitcode file. This step does everything except read the function bodies, but it records the bit locations of each function for future materialization. High-level change description: This patch creates a class called BitcodeStream, which is a very simple interface with one method (GetBytes), which fetches the requested number of bytes from the stream, and writes them into the requested destination. This method may block the calling thread if there are not yet enough bytes available in the stream buffer (similarly to a stdin or socket read). The first issue above is addressed by introducing the BitstreamVector, an abstraction that wraps the bitcode in memory. Instead of using pointers, the BitstreamCursor uses indices and gets bitcode bytes by indexing (i.e. operator[] ) the BitstreamVector. When streaming is not used, the BitstreamVector itself keeps pointers to the start and end of the backing MemoryBuffer and the indexing operator is just a pointer dereference. For streaming use, the BitstreamVector has a BitcodeStream object. If a byte is requested that has not yet been fetched, it calls GetBytes to get more, until it has enough to return the requested byte. This model of allowing any byte to be requested and blocking the caller has the advantage that there is no structural/architectural change required at this lowest level, nor at the high level (A FunctionPassManager is used to iterate over all the functions and compile each one). The second issue is solved by 2 simple changes. The first is in ParseModule. Instead of a single pass over all the bitcode, ParseModule becomes resumable. ParseModule will do its normal handling for top-level records, type table blocks, metadata, etc, but if streaming is in use, it will save its state and return as soon as a function subblock is encountered (rather than saving its location and skipping over it). Each subsequent time it is called, it bookmarks and skips one function block. Later, when a function needs to be materialized, if the function body has been seen already, then materialization is the same as before. Otherwise, Materialize will keep calling ParseModule (each time bookmarking and skipping one function body) until the requested function is found. The one other change required to make this work simply is that the bitcode writer writes function bodies as the last subblock (currently the attachment metadata and value symbol table are written after the function bodies). The prototype patch is attached and can also be viewed online at http://codereview.chromium.org/8393017/ . Feedback is welcome, as well as guidance from the relevant code owners/reviewers regarding what the next step needs to be toward committing this. Thanks, -Derek -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/ec901d02/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: bitcode_streaming_r144247.diff Type: text/x-patch Size: 40098 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/ec901d02/attachment.bin From nlewycky at google.com Wed Nov 9 18:54:30 2011 From: nlewycky at google.com (Nick Lewycky) Date: Wed, 9 Nov 2011 16:54:30 -0800 Subject: [llvm-commits] don't emit debug info for all contexts In-Reply-To: References: Message-ID: [to cfe-commits, bcc llvm-commits] Sorry, got the wrong list. On 9 November 2011 16:47, Nick Lewycky wrote: > This patch fixes PR11345, a case where we emit debug info for a class, > just because we define a static member inside the class. This is > implemented by changing getContextDescriptor() to use a newly refactored > getTypeOrFwdDecl() method, instead of always requiring a full definition. > > Please review! In particular, this patch causes the code that emits > pointers which used to always emit a new fwd-decl of the record type, to > now use the full type if that type is already defined and emitted. I don't > think this has any ill effects, but it's difficult to prove. > > Nick > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/0f31ec6a/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: pr11345-1.patch Type: text/x-patch Size: 5568 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/0f31ec6a/attachment.bin From evan.cheng at apple.com Thu Nov 10 00:27:40 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 09 Nov 2011 22:27:40 -0800 Subject: [llvm-commits] [llvm] r144188 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll In-Reply-To: References: <20111109142048.965491BE001@llvm.org> Message-ID: On Nov 9, 2011, at 5:15 PM, Chandler Carruth wrote: > On Wed, Nov 9, 2011 at 6:20 AM, Duncan Sands wrote: > Author: baldrick > Date: Wed Nov 9 08:20:48 2011 > New Revision: 144188 > > URL: http://llvm.org/viewvc/llvm-project?rev=144188&view=rev > Log: > Speculatively revert commit 144124 (djg) in the hope that the 32 bit > dragonegg self-host buildbot will recover (it is complaining about object > files differing between different build stages). Original commit message: > > Add a hack to the scheduler to disable pseudo-two-address dependencies in > basic blocks containing calls. This works around a problem in which > these artificial dependencies can get tied up in calling seqeunce > scheduling in a way that makes the graph unschedulable with the current > approach of using artificial physical register dependencies for calling > sequences. This fixes PR11314. > > Evan, I'm told I should ping you, as this leaves us with a crash-on-valid regression checked in. Nick asked Dan to revert the underlying patch, and he said to ask you. > > I'm a bit concerned with the situation this leaves the tree in, as we have reverted a fix to a crasher regression in order to fix a stage2/stage3 regression. That doesn't really improve the state of mainline LLVM; if anything it makes it worse. > > What's the motivation for keeping r143660 checked in? We're trying to cut a release, and we can't because mainline is broken. We're not the only ones (or a local patch would work well), and generally this violates the spirit of the LLVM mainline: revert until green. > > This is particularly strange as Duncan has partially pursued the policy of revert when a patch causes a regression, and justified the revert on that policy, but we're now told we can't *finish* reverting until the regressions are gone... My proposal to Dan was rather than reverting r143660 + r144124 to get the buildbots green, keep them in an fix PR11314 in a different way. That is, I've given him the go ahead to disable the scheduler optimization. The chain of events is r143660 fixed some very nasty miscompilations. Unfortunately that caused PR11314. r144124 is a workaround for PR11314, which unfortunately caused the DragonEgg self-hosting issue. As far as we can determine reverting r144124 merely paper over some down stream bug. We really need to understand what's the real cause. So as you can see, reverting these patches don't really solve any real problem. Disabling the optimization should be as fast as the revert and it will allow everyone to continue to move forward. I'd expect the change should have been done already. Dan, what's holding it up? Evan -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/91506b18/attachment.html From chandlerc at google.com Thu Nov 10 00:43:12 2011 From: chandlerc at google.com (Chandler Carruth) Date: Wed, 9 Nov 2011 22:43:12 -0800 Subject: [llvm-commits] [llvm] r144188 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll In-Reply-To: References: <20111109142048.965491BE001@llvm.org> Message-ID: On Wed, Nov 9, 2011 at 10:27 PM, Evan Cheng wrote: > > On Nov 9, 2011, at 5:15 PM, Chandler Carruth wrote: > > On Wed, Nov 9, 2011 at 6:20 AM, Duncan Sands wrote: > >> Author: baldrick >> Date: Wed Nov 9 08:20:48 2011 >> New Revision: 144188 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=144188&view=rev >> Log: >> Speculatively revert commit 144124 (djg) in the hope that the 32 bit >> dragonegg self-host buildbot will recover (it is complaining about object >> files differing between different build stages). Original commit message: >> >> Add a hack to the scheduler to disable pseudo-two-address dependencies in >> basic blocks containing calls. This works around a problem in which >> these artificial dependencies can get tied up in calling seqeunce >> scheduling in a way that makes the graph unschedulable with the current >> approach of using artificial physical register dependencies for calling >> sequences. This fixes PR11314. > > > Evan, I'm told I should ping you, as this leaves us with a crash-on-valid > regression checked in. Nick asked Dan to revert the underlying patch, and > he said to ask you. > > I'm a bit concerned with the situation this leaves the tree in, as we have > reverted a fix to a crasher regression in order to fix a stage2/stage3 > regression. That doesn't really improve the state of mainline LLVM; if > anything it makes it worse. > > What's the motivation for keeping r143660 checked in? We're trying to cut > a release, and we can't because mainline is broken. We're not the only ones > (or a local patch would work well), and generally this violates the spirit > of the LLVM mainline: revert until green. > > This is particularly strange as Duncan has partially pursued the policy of > revert when a patch causes a regression, and justified the revert on that > policy, but we're now told we can't *finish* reverting until the > regressions are gone... > > > My proposal to Dan was rather than reverting r143660 + r144124 to get the > buildbots green, keep them in an fix PR11314 in a different way. That is, > I've given him the go ahead to disable the scheduler optimization. > > The chain of events is r143660 fixed some very nasty miscompilations. > Unfortunately that caused PR11314. r144124 is a workaround for PR11314, > which unfortunately caused the DragonEgg self-hosting issue. As far as we > can determine reverting r144124 merely paper over some down stream bug. We > really need to understand what's the real cause. > > So as you can see, reverting these patches don't really solve any real > problem. Disabling the optimization should be as fast as the revert and it > will allow everyone to continue to move forward. I'd expect the change > should have been done already. > Ah, thank you for the explanation! Makes the (quite tricky situation) much more clear. Thanks to both you and Dan for working so hard to get everything working! -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/32c1ebc6/attachment.html From nadav.rotem at intel.com Thu Nov 10 00:54:20 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Thu, 10 Nov 2011 06:54:20 -0000 Subject: [llvm-commits] [llvm] r144266 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20111110065420.EC86A1BE001@llvm.org> Author: nadav Date: Thu Nov 10 00:54:20 2011 New Revision: 144266 URL: http://llvm.org/viewvc/llvm-project?rev=144266&view=rev Log: AVX2: Add variable shift from memory. Note: These patterns only works in some cases because many times the load sd node is bitcasted from a load node of a different type. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144266&r1=144265&r2=144266&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Nov 10 00:54:20 2011 @@ -7692,6 +7692,7 @@ let Predicates = [HasAVX2] in { + def : Pat<(v4i32 (shl (v4i32 VR128:$src1), (v4i32 VR128:$src2))), (VPSLLVDrr VR128:$src1, VR128:$src2)>; def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (v2i64 VR128:$src2))), @@ -7702,7 +7703,6 @@ (VPSRLVQrr VR128:$src1, VR128:$src2)>; def : Pat<(v4i32 (sra (v4i32 VR128:$src1), (v4i32 VR128:$src2))), (VPSRAVDrr VR128:$src1, VR128:$src2)>; - def : Pat<(v8i32 (shl (v8i32 VR256:$src1), (v8i32 VR256:$src2))), (VPSLLVDYrr VR256:$src1, VR256:$src2)>; def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (v4i64 VR256:$src2))), @@ -7713,6 +7713,29 @@ (VPSRLVQYrr VR256:$src1, VR256:$src2)>; def : Pat<(v8i32 (sra (v8i32 VR256:$src1), (v8i32 VR256:$src2))), (VPSRAVDYrr VR256:$src1, VR256:$src2)>; + + def : Pat<(v4i32 (shl (v4i32 VR128:$src1),(loadv4i32 addr:$src2))), + (VPSLLVDrm VR128:$src1, addr:$src2)>; + def : Pat<(v4i32 (shl (v4i32 VR128:$src1),(loadv2i64 addr:$src2))), + (VPSLLVDrm VR128:$src1, addr:$src2)>; + def : Pat<(v2i64 (shl (v2i64 VR128:$src1),(loadv2i64 addr:$src2))), + (VPSLLVQrm VR128:$src1, addr:$src2)>; + def : Pat<(v4i32 (srl (v4i32 VR128:$src1),(loadv4i32 addr:$src2))), + (VPSRLVDrm VR128:$src1, addr:$src2)>; + def : Pat<(v2i64 (srl (v2i64 VR128:$src1),(loadv2i64 addr:$src2))), + (VPSRLVQrm VR128:$src1, addr:$src2)>; + def : Pat<(v4i32 (sra (v4i32 VR128:$src1),(loadv4i32 addr:$src2))), + (VPSRAVDrm VR128:$src1, addr:$src2)>; + def : Pat<(v8i32 (shl (v8i32 VR256:$src1),(loadv8i32 addr:$src2))), + (VPSLLVDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4i64 (shl (v4i64 VR256:$src1),(loadv4i64 addr:$src2))), + (VPSLLVQYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8i32 (srl (v8i32 VR256:$src1),(loadv8i32 addr:$src2))), + (VPSRLVDYrm VR256:$src1, addr:$src2)>; + def : Pat<(v4i64 (srl (v4i64 VR256:$src1),(loadv4i64 addr:$src2))), + (VPSRLVQYrm VR256:$src1, addr:$src2)>; + def : Pat<(v8i32 (sra (v8i32 VR256:$src1),(loadv8i32 addr:$src2))), + (VPSRAVDYrm VR256:$src1, addr:$src2)>; } From baldrick at free.fr Thu Nov 10 01:29:41 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 10 Nov 2011 08:29:41 +0100 Subject: [llvm-commits] [llvm] r144188 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll In-Reply-To: References: <20111109142048.965491BE001@llvm.org> <4EBAF66F.7030708@free.fr> <04A23D00-737D-4AFD-9D97-3958A728AFA2@apple.com> <4EBAF9A4.4080901@free.fr> Message-ID: <4EBB7D65.4020503@free.fr> Hi David, > Is the patch itself really the problem, or is it just tickling another bug? I don't know yet. > If it's exposing a bug somewhere else, it seems counter-productive to > revert this commit and pretend everything is OK. The reversion policy has nothing to do with "pretending everything is OK". Ciao, Duncan. From evan.cheng at apple.com Thu Nov 10 01:43:16 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 10 Nov 2011 07:43:16 -0000 Subject: [llvm-commits] [llvm] r144267 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/2006-05-11-InstrSched.ll test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll test/CodeGen/X86/change-compare-stride-1.ll test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/iv-users-in-other-loops.ll test/CodeGen/X86/lsr-loop-exit-cond.ll test/CodeGen/X86/lsr-reuse-trunc.ll test/CodeGen/X86/masked-iv-safe.ll test/CodeGen/X86/multiple-loop-post-inc.ll test/CodeGen/X86/sse2.ll test/CodeGen/X86/sse3.ll Message-ID: <20111110074316.A97871BE001@llvm.org> Author: evancheng Date: Thu Nov 10 01:43:16 2011 New Revision: 144267 URL: http://llvm.org/viewvc/llvm-project?rev=144267&view=rev Log: Use a bigger hammer to fix PR11314 by disabling the "forcing two-address instruction lower optimization" in the pre-RA scheduler. The optimization, rather the hack, was done before MI use-list was available. Now we should be able to implement it in a better way, perhaps in the two-address pass until a MI scheduler is available. Now that the scheduler has to backtrack to handle call sequences. Adding artificial scheduling constraints is just not safe. Furthermore, the hack is not taking all the other scheduling decisions into consideration so it's just as likely to pessimize code. So I view disabling this optimization goodness regardless of PR11314. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll llvm/trunk/test/CodeGen/X86/multiple-loop-post-inc.ll llvm/trunk/test/CodeGen/X86/sse2.ll llvm/trunk/test/CodeGen/X86/sse3.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Nov 10 01:43:16 2011 @@ -89,6 +89,9 @@ static cl::opt DisableSchedHeight( "disable-sched-height", cl::Hidden, cl::init(false), cl::desc("Disable scheduled-height priority in sched=list-ilp")); +static cl::opt Disable2AddrHack( + "disable-2addr-hack", cl::Hidden, cl::init(true), + cl::desc("Disable scheduler's two-address hack")); static cl::opt MaxReorderWindow( "max-sched-reorder", cl::Hidden, cl::init(6), @@ -2628,7 +2631,8 @@ void RegReductionPQBase::initNodes(std::vector &sunits) { SUnits = &sunits; // Add pseudo dependency edges for two-address nodes. - AddPseudoTwoAddrDeps(); + if (!Disable2AddrHack) + AddPseudoTwoAddrDeps(); // Reroute edges to nodes with multiple uses. if (!TracksRegPressure) PrescheduleNodesWithMultipleUses(); Modified: llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll (original) +++ llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll Thu Nov 10 01:43:16 2011 @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mattr=+sse2 -stats -realign-stack=0 |&\ -; RUN: grep {asm-printer} | grep 34 +; RUN: grep {asm-printer} | grep 35 target datalayout = "e-p:32:32" define void @foo(i32* %mc, i32* %bp, i32* %ms, i32* %xmb, i32* %mpp, i32* %tpmm, i32* %ip, i32* %tpim, i32* %dpp, i32* %tpdm, i32* %bpi, i32 %M) nounwind { Modified: llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll Thu Nov 10 01:43:16 2011 @@ -5,7 +5,6 @@ ; CHECK: pextrw $14 ; CHECK-NEXT: shrl $8 -; CHECK-NEXT: (%ebp) ; CHECK-NEXT: pinsrw define void @update(i8** %args_list) nounwind { Modified: llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll (original) +++ llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll Thu Nov 10 01:43:16 2011 @@ -3,6 +3,10 @@ ; Nested LSR is required to optimize this case. ; We do not expect to see this form of IR without -enable-iv-rewrite. +; xfailed for now because the scheduler two-address hack has been disabled. +; Now it's generating a leal -1 rather than a decq. +; XFAIL: * + define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind { ; CHECK: borf: ; CHECK-NOT: inc Modified: llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll (original) +++ llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll Thu Nov 10 01:43:16 2011 @@ -1,5 +1,7 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=linearscan | FileCheck --check-prefix=I386 %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck --check-prefix=X86-64 %s +; DISABLED: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=linearscan | FileCheck --check-prefix=I386 %s + +; i386 test has been disabled when scheduler 2-addr hack is disabled. ; This testcase shouldn't need to spill the -1 value, ; so it should just use pcmpeqd to materialize an all-ones vector. Modified: llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll (original) +++ llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll Thu Nov 10 01:43:16 2011 @@ -1,9 +1,8 @@ ; RUN: llc < %s -march=x86-64 -enable-lsr-nested -o %t ; RUN: not grep inc %t ; RUN: grep dec %t | count 2 -; RUN: grep addq %t | count 12 +; RUN: grep addq %t | count 10 ; RUN: not grep addb %t -; RUN: not grep leaq %t ; RUN: not grep leal %t ; RUN: not grep movq %t Modified: llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll (original) +++ llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll Thu Nov 10 01:43:16 2011 @@ -1,6 +1,7 @@ ; RUN: llc -march=x86-64 < %s | FileCheck %s ; CHECK: decq +; CHECK-NEXT: movl ( ; CHECK-NEXT: jne @Te0 = external global [256 x i32] ; <[256 x i32]*> [#uses=5] Modified: llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll (original) +++ llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll Thu Nov 10 01:43:16 2011 @@ -4,13 +4,14 @@ ; Full strength reduction wouldn't reduce register pressure, so LSR should ; stick with indexing here. +; FIXME: This is worse off from disabling of scheduler 2-address hack. ; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]] +; CHECK: leaq 4(%rax), %{{rcx|r9}} ; CHECK: cvtdq2ps ; CHECK: orps {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]] ; CHECK: movaps [[X4]], (%{{rdi|rcx}},%rax,4) -; CHECK: addq $4, %rax -; CHECK: cmpl %eax, (%{{rdx|r8}}) -; CHECK-NEXT: jg +; CHECK: cmpl %{{ecx|r9d}}, (%{{rdx|r8}}) +; CHECK: jg define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind { entry: Modified: llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll (original) +++ llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll Thu Nov 10 01:43:16 2011 @@ -3,10 +3,10 @@ ; RUN: not grep movz %t ; RUN: not grep sar %t ; RUN: not grep shl %t -; RUN: grep add %t | count 2 +; RUN: grep add %t | count 1 ; RUN: grep inc %t | count 4 ; RUN: grep dec %t | count 2 -; RUN: grep lea %t | count 2 +; RUN: grep lea %t | count 3 ; Optimize away zext-inreg and sext-inreg on the loop induction ; variable using trip-count information. Modified: llvm/trunk/test/CodeGen/X86/multiple-loop-post-inc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/multiple-loop-post-inc.ll?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/multiple-loop-post-inc.ll (original) +++ llvm/trunk/test/CodeGen/X86/multiple-loop-post-inc.ll Thu Nov 10 01:43:16 2011 @@ -1,6 +1,10 @@ ; RUN: llc -asm-verbose=false -disable-branch-fold -disable-code-place -disable-tail-duplicate -march=x86-64 < %s | FileCheck %s ; rdar://7236213 +; Xfailed now that scheduler 2-address hack is disabled a lea is generated. +; The code isn't any worse though. +; XFAIL: * + ; CodeGen shouldn't require any lea instructions inside the marked loop. ; It should properly set up post-increment uses and do coalescing for ; the induction variables. Modified: llvm/trunk/test/CodeGen/X86/sse2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2.ll?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse2.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse2.ll Thu Nov 10 01:43:16 2011 @@ -178,8 +178,8 @@ %tmp27 = shufflevector <4 x float> %tmp9, <4 x float> %tmp21, <4 x i32> < i32 0, i32 1, i32 4, i32 5 > ; <<4 x float>> [#uses=1] ret <4 x float> %tmp27 ; CHECK: test14: -; CHECK: addps [[X1:%xmm[0-9]+]], [[X0:%xmm[0-9]+]] -; CHECK: subps [[X1]], [[X2:%xmm[0-9]+]] +; CHECK: subps [[X1:%xmm[0-9]+]], [[X2:%xmm[0-9]+]] +; CHECK: addps [[X1]], [[X0:%xmm[0-9]+]] ; CHECK: movlhps [[X2]], [[X0]] } Modified: llvm/trunk/test/CodeGen/X86/sse3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=144267&r1=144266&r2=144267&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse3.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse3.ll Thu Nov 10 01:43:16 2011 @@ -226,15 +226,16 @@ } - +; FIXME: t15 is worse off from disabling of scheduler 2-address hack. define <8 x i16> @t15(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { entry: %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef > ret <8 x i16> %tmp8 ; X64: t15: -; X64: pextrw $7, %xmm0, %eax +; X64: movdqa %xmm0, %xmm2 ; X64: punpcklqdq %xmm1, %xmm0 ; X64: pshuflw $-128, %xmm0, %xmm0 +; X64: pextrw $7, %xmm2, %eax ; X64: pinsrw $2, %eax, %xmm0 ; X64: ret } @@ -247,12 +248,12 @@ %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > ret <16 x i8> %tmp9 ; X64: t16: -; X64: movdqa %xmm1, %xmm0 -; X64: pslldq $2, %xmm0 -; X64: pextrw $1, %xmm0, %eax -; X64: movd %xmm0, %ecx -; X64: pinsrw $0, %ecx, %xmm0 -; X64: pextrw $8, %xmm1, %ecx +; X64: movdqa %xmm1, %xmm2 +; X64: pslldq $2, %xmm2 +; X64: movd %xmm2, %eax +; X64: pinsrw $0, %eax, %xmm0 +; X64: pextrw $8, %xmm1, %eax +; X64: pextrw $1, %xmm2, %ecx ; X64: ret } From evan.cheng at apple.com Thu Nov 10 01:49:02 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 09 Nov 2011 23:49:02 -0800 Subject: [llvm-commits] [llvm] r144188 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/multiple-libcalls-and-twoaddr-deps-scheduling.ll In-Reply-To: References: <20111109142048.965491BE001@llvm.org> Message-ID: r144267 should fix PR11314. Let's see if DragonEgg is happy. Evan On Nov 9, 2011, at 10:43 PM, Chandler Carruth wrote: > On Wed, Nov 9, 2011 at 10:27 PM, Evan Cheng wrote: > > On Nov 9, 2011, at 5:15 PM, Chandler Carruth wrote: > >> On Wed, Nov 9, 2011 at 6:20 AM, Duncan Sands wrote: >> Author: baldrick >> Date: Wed Nov 9 08:20:48 2011 >> New Revision: 144188 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=144188&view=rev >> Log: >> Speculatively revert commit 144124 (djg) in the hope that the 32 bit >> dragonegg self-host buildbot will recover (it is complaining about object >> files differing between different build stages). Original commit message: >> >> Add a hack to the scheduler to disable pseudo-two-address dependencies in >> basic blocks containing calls. This works around a problem in which >> these artificial dependencies can get tied up in calling seqeunce >> scheduling in a way that makes the graph unschedulable with the current >> approach of using artificial physical register dependencies for calling >> sequences. This fixes PR11314. >> >> Evan, I'm told I should ping you, as this leaves us with a crash-on-valid regression checked in. Nick asked Dan to revert the underlying patch, and he said to ask you. >> >> I'm a bit concerned with the situation this leaves the tree in, as we have reverted a fix to a crasher regression in order to fix a stage2/stage3 regression. That doesn't really improve the state of mainline LLVM; if anything it makes it worse. >> >> What's the motivation for keeping r143660 checked in? We're trying to cut a release, and we can't because mainline is broken. We're not the only ones (or a local patch would work well), and generally this violates the spirit of the LLVM mainline: revert until green. >> >> This is particularly strange as Duncan has partially pursued the policy of revert when a patch causes a regression, and justified the revert on that policy, but we're now told we can't *finish* reverting until the regressions are gone... > > My proposal to Dan was rather than reverting r143660 + r144124 to get the buildbots green, keep them in an fix PR11314 in a different way. That is, I've given him the go ahead to disable the scheduler optimization. > > The chain of events is r143660 fixed some very nasty miscompilations. Unfortunately that caused PR11314. r144124 is a workaround for PR11314, which unfortunately caused the DragonEgg self-hosting issue. As far as we can determine reverting r144124 merely paper over some down stream bug. We really need to understand what's the real cause. > > So as you can see, reverting these patches don't really solve any real problem. Disabling the optimization should be as fast as the revert and it will allow everyone to continue to move forward. I'd expect the change should have been done already. > > Ah, thank you for the explanation! Makes the (quite tricky situation) much more clear. Thanks to both you and Dan for working so hard to get everything working! -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111109/6c56c621/attachment.html From elena.demikhovsky at intel.com Thu Nov 10 01:50:29 2011 From: elena.demikhovsky at intel.com (Demikhovsky, Elena) Date: Thu, 10 Nov 2011 09:50:29 +0200 Subject: [llvm-commits] AVX1 Code Generation - VSHUFP extension In-Reply-To: References: <7CB6AC5AED596245A99BF3213DE8F4AA02FFEA3063@hasmsx504.ger.corp.intel.com> <7CB6AC5AED596245A99BF3213DE8F4AA02FFF2B81B@hasmsx504.ger.corp.intel.com> <7CB6AC5AED596245A99BF3213DE8F4AA02FFF96817@hasmsx504.ger.corp.intel.com> Message-ID: <7CB6AC5AED596245A99BF3213DE8F4AA02FFF96C03@hasmsx504.ger.corp.intel.com> No problem. I attached the new patch. - Elena -----Original Message----- From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] Sent: Wednesday, November 09, 2011 18:43 To: Demikhovsky, Elena Cc: Eli Friedman; llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] AVX1 Code Generation - VSHUFP extension Hi, > I fixed the comments, I put 2 functions isCommutedVSHUFP() together. > > If this patch is good, please commit it. Looks great! Just one more fix: +static void CommuteVectorShuffleMask(SmallVectorImpl &Mask, EVT VT); + + + +/// isCommutedVSHUFP() - Return true if swapping operands will +/// allow to use the "vshufpd" or "vshufps" instruction +/// for 256-bit vectors + +static bool isCommutedVSHUFPMask(const SmallVectorImpl &Mask, EVT VT, + const X86Subtarget *Subtarget) { Please move the function definition up so you don't need to use a declaration, and make the comment above tied to the function (no newline between them). -- Bruno Cardoso Lopes http://www.brunocardoso.cc --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: vshufp3.diff Type: application/octet-stream Size: 4284 bytes Desc: vshufp3.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20111110/a21d3db1/attachment.obj From baldrick at free.fr Thu Nov 10 05:13:49 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 10 Nov 2011 12:13:49 +0100 Subject: [llvm-commits] [llvm] r144267 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp test/CodeGen/X86/2006-05-11-InstrSched.ll test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll test/CodeGen/X86/change-compare-stride-1.ll test/CodeGen/X86/fold-pcmpeqd-0.ll test/CodeGen/X86/iv-users-in-other-loops.ll test/CodeGen/X86/lsr-loop-exit-cond.ll test/CodeGen/X86/lsr-reuse-trunc.ll test/CodeGen/X86/masked-iv-safe.ll test/CodeGen/X86/multiple-loop-post-inc.ll test/CodeGen/X86/sse2.ll test/CodeGen/X86/sse3.ll In-Reply-To: <20111110074316.A97871BE001@llvm.org> References: <20111110074316.A97871BE001@llvm.org> Message-ID: <4EBBB1ED.8000105@free.fr> Hi Evan, this also broke the buildbot http://lab.llvm.org:8011/builders/dragonegg-i386-linux/builds/365 I'm trying to work out what is wrong. Ciao, Duncan. On 10/11/11 08:43, Evan Cheng wrote: > Author: evancheng > Date: Thu Nov 10 01:43:16 2011 > New Revision: 144267 > > URL: http://llvm.org/viewvc/llvm-project?rev=144267&view=rev > Log: > Use a bigger hammer to fix PR11314 by disabling the "forcing two-address > instruction lower optimization" in the pre-RA scheduler. > > The optimization, rather the hack, was done before MI use-list was available. > Now we should be able to implement it in a better way, perhaps in the > two-address pass until a MI scheduler is available. > > Now that the scheduler has to backtrack to handle call sequences. Adding > artificial scheduling constraints is just not safe. Furthermore, the hack > is not taking all the other scheduling decisions into consideration so it's just > as likely to pessimize code. So I view disabling this optimization goodness > regardless of PR11314. > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp > llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll > llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll > llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll > llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll > llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll > llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll > llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll > llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll > llvm/trunk/test/CodeGen/X86/multiple-loop-post-inc.ll > llvm/trunk/test/CodeGen/X86/sse2.ll > llvm/trunk/test/CodeGen/X86/sse3.ll > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Nov 10 01:43:16 2011 > @@ -89,6 +89,9 @@ > static cl::opt DisableSchedHeight( > "disable-sched-height", cl::Hidden, cl::init(false), > cl::desc("Disable scheduled-height priority in sched=list-ilp")); > +static cl::opt Disable2AddrHack( > + "disable-2addr-hack", cl::Hidden, cl::init(true), > + cl::desc("Disable scheduler's two-address hack")); > > static cl::opt MaxReorderWindow( > "max-sched-reorder", cl::Hidden, cl::init(6), > @@ -2628,7 +2631,8 @@ > void RegReductionPQBase::initNodes(std::vector &sunits) { > SUnits =&sunits; > // Add pseudo dependency edges for two-address nodes. > - AddPseudoTwoAddrDeps(); > + if (!Disable2AddrHack) > + AddPseudoTwoAddrDeps(); > // Reroute edges to nodes with multiple uses. > if (!TracksRegPressure) > PrescheduleNodesWithMultipleUses(); > > Modified: llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2006-05-11-InstrSched.ll Thu Nov 10 01:43:16 2011 > @@ -1,5 +1,5 @@ > ; RUN: llc< %s -march=x86 -mtriple=i386-linux-gnu -mattr=+sse2 -stats -realign-stack=0 |&\ > -; RUN: grep {asm-printer} | grep 34 > +; RUN: grep {asm-printer} | grep 35 > > target datalayout = "e-p:32:32" > define void @foo(i32* %mc, i32* %bp, i32* %ms, i32* %xmb, i32* %mpp, i32* %tpmm, i32* %ip, i32* %tpim, i32* %dpp, i32* %tpdm, i32* %bpi, i32 %M) nounwind { > > Modified: llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll Thu Nov 10 01:43:16 2011 > @@ -5,7 +5,6 @@ > > ; CHECK: pextrw $14 > ; CHECK-NEXT: shrl $8 > -; CHECK-NEXT: (%ebp) > ; CHECK-NEXT: pinsrw > > define void @update(i8** %args_list) nounwind { > > Modified: llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll (original) > +++ llvm/trunk/test/CodeGen/X86/change-compare-stride-1.ll Thu Nov 10 01:43:16 2011 > @@ -3,6 +3,10 @@ > ; Nested LSR is required to optimize this case. > ; We do not expect to see this form of IR without -enable-iv-rewrite. > > +; xfailed for now because the scheduler two-address hack has been disabled. > +; Now it's generating a leal -1 rather than a decq. > +; XFAIL: * > + > define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind { > ; CHECK: borf: > ; CHECK-NOT: inc > > Modified: llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll (original) > +++ llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll Thu Nov 10 01:43:16 2011 > @@ -1,5 +1,7 @@ > -; RUN: llc< %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=linearscan | FileCheck --check-prefix=I386 %s > ; RUN: llc< %s -mtriple=x86_64-apple-darwin | FileCheck --check-prefix=X86-64 %s > +; DISABLED: llc< %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=linearscan | FileCheck --check-prefix=I386 %s > + > +; i386 test has been disabled when scheduler 2-addr hack is disabled. > > ; This testcase shouldn't need to spill the -1 value, > ; so it should just use pcmpeqd to materialize an all-ones vector. > > Modified: llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll (original) > +++ llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll Thu Nov 10 01:43:16 2011 > @@ -1,9 +1,8 @@ > ; RUN: llc< %s -march=x86-64 -enable-lsr-nested -o %t > ; RUN: not grep inc %t > ; RUN: grep dec %t | count 2 > -; RUN: grep addq %t | count 12 > +; RUN: grep addq %t | count 10 > ; RUN: not grep addb %t > -; RUN: not grep leaq %t > ; RUN: not grep leal %t > ; RUN: not grep movq %t > > > Modified: llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll (original) > +++ llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll Thu Nov 10 01:43:16 2011 > @@ -1,6 +1,7 @@ > ; RUN: llc -march=x86-64< %s | FileCheck %s > > ; CHECK: decq > +; CHECK-NEXT: movl ( > ; CHECK-NEXT: jne > > @Te0 = external global [256 x i32] ;<[256 x i32]*> [#uses=5] > > Modified: llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll (original) > +++ llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll Thu Nov 10 01:43:16 2011 > @@ -4,13 +4,14 @@ > ; Full strength reduction wouldn't reduce register pressure, so LSR should > ; stick with indexing here. > > +; FIXME: This is worse off from disabling of scheduler 2-address hack. > ; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]] > +; CHECK: leaq 4(%rax), %{{rcx|r9}} > ; CHECK: cvtdq2ps > ; CHECK: orps {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]] > ; CHECK: movaps [[X4]], (%{{rdi|rcx}},%rax,4) > -; CHECK: addq $4, %rax > -; CHECK: cmpl %eax, (%{{rdx|r8}}) > -; CHECK-NEXT: jg > +; CHECK: cmpl %{{ecx|r9d}}, (%{{rdx|r8}}) > +; CHECK: jg > > define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind { > entry: > > Modified: llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll (original) > +++ llvm/trunk/test/CodeGen/X86/masked-iv-safe.ll Thu Nov 10 01:43:16 2011 > @@ -3,10 +3,10 @@ > ; RUN: not grep movz %t > ; RUN: not grep sar %t > ; RUN: not grep shl %t > -; RUN: grep add %t | count 2 > +; RUN: grep add %t | count 1 > ; RUN: grep inc %t | count 4 > ; RUN: grep dec %t | count 2 > -; RUN: grep lea %t | count 2 > +; RUN: grep lea %t | count 3 > > ; Optimize away zext-inreg and sext-inreg on the loop induction > ; variable using trip-count information. > > Modified: llvm/trunk/test/CodeGen/X86/multiple-loop-post-inc.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/multiple-loop-post-inc.ll?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/multiple-loop-post-inc.ll (original) > +++ llvm/trunk/test/CodeGen/X86/multiple-loop-post-inc.ll Thu Nov 10 01:43:16 2011 > @@ -1,6 +1,10 @@ > ; RUN: llc -asm-verbose=false -disable-branch-fold -disable-code-place -disable-tail-duplicate -march=x86-64< %s | FileCheck %s > ; rdar://7236213 > > +; Xfailed now that scheduler 2-address hack is disabled a lea is generated. > +; The code isn't any worse though. > +; XFAIL: * > + > ; CodeGen shouldn't require any lea instructions inside the marked loop. > ; It should properly set up post-increment uses and do coalescing for > ; the induction variables. > > Modified: llvm/trunk/test/CodeGen/X86/sse2.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2.ll?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/sse2.ll (original) > +++ llvm/trunk/test/CodeGen/X86/sse2.ll Thu Nov 10 01:43:16 2011 > @@ -178,8 +178,8 @@ > %tmp27 = shufflevector<4 x float> %tmp9,<4 x float> %tmp21,<4 x i32> < i32 0, i32 1, i32 4, i32 5> ;<<4 x float>> [#uses=1] > ret<4 x float> %tmp27 > ; CHECK: test14: > -; CHECK: addps [[X1:%xmm[0-9]+]], [[X0:%xmm[0-9]+]] > -; CHECK: subps [[X1]], [[X2:%xmm[0-9]+]] > +; CHECK: subps [[X1:%xmm[0-9]+]], [[X2:%xmm[0-9]+]] > +; CHECK: addps [[X1]], [[X0:%xmm[0-9]+]] > ; CHECK: movlhps [[X2]], [[X0]] > } > > > Modified: llvm/trunk/test/CodeGen/X86/sse3.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=144267&r1=144266&r2=144267&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/sse3.ll (original) > +++ llvm/trunk/test/CodeGen/X86/sse3.ll Thu Nov 10 01:43:16 2011 > @@ -226,15 +226,16 @@ > } > > > - > +; FIXME: t15 is worse off from disabling of scheduler 2-address hack. > define<8 x i16> @t15(<8 x i16> %T0,<8 x i16> %T1) nounwind readnone { > entry: > %tmp8 = shufflevector<8 x i16> %T0,<8 x i16> %T1,<8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef> > ret<8 x i16> %tmp8 > ; X64: t15: > -; X64: pextrw $7, %xmm0, %eax > +; X64: movdqa %xmm0, %xmm2 > ; X64: punpcklqdq %xmm1, %xmm0 > ; X64: pshuflw $-128, %xmm0, %xmm0 > +; X64: pextrw $7, %xmm2, %eax > ; X64: pinsrw $2, %eax, %xmm0 > ; X64: ret > } > @@ -247,12 +248,12 @@ > %tmp9 = shufflevector<16 x i8> %tmp8,<16 x i8> %T0,<16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef> > ret<16 x i8> %tmp9 > ; X64: t16: > -; X64: movdqa %xmm1, %xmm0 > -; X64: pslldq $2, %xmm0 > -; X64: pextrw $1, %xmm0, %eax > -; X64: movd %xmm0, %ecx > -; X64: pinsrw $0, %ecx, %xmm0 > -; X64: pextrw $8, %xmm1, %ecx > +; X64: movdqa %xmm1, %xmm2 > +; X64: pslldq $2, %xmm2 > +; X64: movd %xmm2, %eax > +; X64: pinsrw $0, %eax, %xmm0 > +; X64: pextrw $8, %xmm1, %eax > +; X64: pextrw $1, %xmm2, %ecx > ; X64: ret > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosser at fim.uni-passau.de Thu Nov 10 06:44:50 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 12:44:50 -0000 Subject: [llvm-commits] [polly] r144278 - /polly/trunk/lib/Analysis/ScopDetection.cpp Message-ID: <20111110124450.5A5C22A6C12E@llvm.org> Author: grosser Date: Thu Nov 10 06:44:50 2011 New Revision: 144278 URL: http://llvm.org/viewvc/llvm-project?rev=144278&view=rev Log: ScopDetect: Use getPointerBase to get the base pointer Previously we allowed in access functions only a single SCEVUnknown, which later became the base address. We now use getPointerBase() to derive the base address and all remaining unknowns are handled as parameters. This allows us to handle cases like A[b+c]; Modified: polly/trunk/lib/Analysis/ScopDetection.cpp Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=144278&r1=144277&r2=144278&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Thu Nov 10 06:44:50 2011 @@ -56,6 +56,7 @@ #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/RegionIterator.h" #include "llvm/Analysis/ScalarEvolution.h" +#include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/Support/CommandLine.h" #include "llvm/Assembly/Writer.h" @@ -213,10 +214,26 @@ DetectionContext &Context) const { Value *Ptr = getPointerOperand(Inst), *BasePtr; const SCEV *AccessFunction = SE->getSCEV(Ptr); + const SCEVUnknown *BasePointer; + const Value *BaseValue; - if (!isAffineExpr(&Context.CurRegion, AccessFunction, *SE, &BasePtr)) + BasePointer = dyn_cast(SE->getPointerBase(AccessFunction)); + + if (!BasePointer) + INVALID(AffFunc, "No base pointer"); + + BaseValue = BasePointer->getValue(); + + if (isa(BaseValue)) + INVALID(AffFunc, "Undefined base pointer"); + + AccessFunction = SE->getMinusSCEV(AccessFunction, BasePointer); + + if (!isAffineExpr(&Context.CurRegion, AccessFunction, *SE)) INVALID(AffFunc, "Bad memory address " << *AccessFunction); + BasePtr = BasePointer->getValue(); + // FIXME: Alias Analysis thinks IntToPtrInst aliases with alloca instructions // created by IndependentBlocks Pass. if (isa(BasePtr)) From grosser at fim.uni-passau.de Thu Nov 10 06:44:55 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 12:44:55 -0000 Subject: [llvm-commits] [polly] r144279 - in /polly/trunk: include/polly/TempScopInfo.h lib/Analysis/ScopInfo.cpp lib/Analysis/TempScopInfo.cpp Message-ID: <20111110124455.DC10F2A6C12E@llvm.org> Author: grosser Date: Thu Nov 10 06:44:55 2011 New Revision: 144279 URL: http://llvm.org/viewvc/llvm-project?rev=144279&view=rev Log: Use getBasePtr in TempScop/ScopInfo Modified: polly/trunk/include/polly/TempScopInfo.h polly/trunk/lib/Analysis/ScopInfo.cpp polly/trunk/lib/Analysis/TempScopInfo.cpp Modified: polly/trunk/include/polly/TempScopInfo.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/TempScopInfo.h?rev=144279&r1=144278&r2=144279&view=diff ============================================================================== --- polly/trunk/include/polly/TempScopInfo.h (original) +++ polly/trunk/include/polly/TempScopInfo.h Thu Nov 10 06:44:55 2011 @@ -35,8 +35,9 @@ /// @brief A memory access described by a SCEV expression and the access type. class IRAccess { public: - // The SCEV of this memory access. - const SCEV *Scev; + const Value *BaseAddress; + + const SCEV *Offset; // The type of the scev affine function enum TypeKind { READ, WRITE }; @@ -46,12 +47,16 @@ TypeKind Type; public: - explicit IRAccess (TypeKind Type, const SCEV *Scev, unsigned elemBytes) - : Scev(Scev), ElemBytes(elemBytes), Type(Type) {} + explicit IRAccess (TypeKind Type, const Value *BaseAddress, + const SCEV *Offset, unsigned elemBytes) + : BaseAddress(BaseAddress), Offset(Offset), + ElemBytes(elemBytes), Type(Type) {} enum TypeKind getType() const { return Type; } - const SCEV *getSCEV() const { return Scev; } + const Value *getBase() const { return BaseAddress; } + + const SCEV *getOffset() const { return Offset; } unsigned getElemSizeInBytes() const { return ElemBytes; } Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144279&r1=144278&r2=144279&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Thu Nov 10 06:44:55 2011 @@ -329,10 +329,8 @@ Type = Access.isRead() ? Read : Write; statement = Statement; - Value *TmpBaseAddress = NULL; - isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, Access.getSCEV(), - &TmpBaseAddress); - BaseAddr = TmpBaseAddress; + isl_pw_aff *Affine = SCEVAffinator::getPwAff(Statement, Access.getOffset()); + BaseAddr = Access.getBase(); setBaseName(); Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144279&r1=144278&r2=144279&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Thu Nov 10 06:44:55 2011 @@ -26,6 +26,7 @@ #include "llvm/Assembly/Writer.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/ScalarEvolution.h" +#include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/ADT/STLExtras.h" #define DEBUG_TYPE "polly-analyze-ir" @@ -93,7 +94,13 @@ } const SCEV *AccessFunction = SE->getSCEV(getPointerOperand(Inst)); - Functions.push_back(std::make_pair(IRAccess(Type, AccessFunction, Size), + const SCEVUnknown *BasePointer = + static_cast(SE->getPointerBase(AccessFunction)); + + AccessFunction = SE->getMinusSCEV(AccessFunction, BasePointer); + Functions.push_back(std::make_pair(IRAccess(Type, + BasePointer->getValue(), + AccessFunction, Size), &Inst)); } } From grosser at fim.uni-passau.de Thu Nov 10 06:45:07 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 12:45:07 -0000 Subject: [llvm-commits] [polly] r144281 - /polly/trunk/lib/RegisterPasses.cpp Message-ID: <20111110124507.89A482A6C12F@llvm.org> Author: grosser Date: Thu Nov 10 06:45:07 2011 New Revision: 144281 URL: http://llvm.org/viewvc/llvm-project?rev=144281&view=rev Log: Add a workaround to fix SCoPs rejected because of 'region not simple' Modified: polly/trunk/lib/RegisterPasses.cpp Modified: polly/trunk/lib/RegisterPasses.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/RegisterPasses.cpp?rev=144281&r1=144280&r2=144281&view=diff ============================================================================== --- polly/trunk/lib/RegisterPasses.cpp (original) +++ polly/trunk/lib/RegisterPasses.cpp Thu Nov 10 06:45:07 2011 @@ -114,10 +114,19 @@ PM.add(polly::createCodePreparationPass()); PM.add(polly::createRegionSimplifyPass()); - // FIXME: Needed as RegionSimplifyPass destroys the canonical form of - // induction variables (It changes the order of the operands in the - // PHI nodes). + // FIXME: The next two passes should not be necessary here. They are currently + // because of two problems: + // + // 1. The RegionSimplifyPass destroys the canonical form of induction + // variables,as it produces PHI nodes with incorrectly ordered + // operands. To fix this we run IndVarSimplify. + // + // 2. IndVarSimplify does not preserve the region information and + // the regioninfo pass does currently not recover simple regions. + // As a result we need to run the RegionSimplify pass again to + // recover them PM.add(llvm::createIndVarSimplifyPass()); + PM.add(polly::createRegionSimplifyPass()); if (PollyViewer) PM.add(polly::createDOTViewerPass()); From grosser at fim.uni-passau.de Thu Nov 10 06:45:03 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 12:45:03 -0000 Subject: [llvm-commits] [polly] r144280 - in /polly/trunk: include/polly/Support/SCEVValidator.h lib/Analysis/ScopDetection.cpp lib/Analysis/ScopInfo.cpp lib/Analysis/TempScopInfo.cpp lib/Support/SCEVValidator.cpp Message-ID: <20111110124503.941EA2A6C12E@llvm.org> Author: grosser Date: Thu Nov 10 06:45:03 2011 New Revision: 144280 URL: http://llvm.org/viewvc/llvm-project?rev=144280&view=rev Log: Reuse the old BaseAddress checking in SCEVValidator to make sure that no base address is part of the access function. Also remove unused special cases that were necessery when the base address was still contained in the access function Modified: polly/trunk/include/polly/Support/SCEVValidator.h polly/trunk/lib/Analysis/ScopDetection.cpp polly/trunk/lib/Analysis/ScopInfo.cpp polly/trunk/lib/Analysis/TempScopInfo.cpp polly/trunk/lib/Support/SCEVValidator.cpp Modified: polly/trunk/include/polly/Support/SCEVValidator.h URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/Support/SCEVValidator.h?rev=144280&r1=144279&r2=144280&view=diff ============================================================================== --- polly/trunk/include/polly/Support/SCEVValidator.h (original) +++ polly/trunk/include/polly/Support/SCEVValidator.h Thu Nov 10 06:45:03 2011 @@ -23,12 +23,13 @@ namespace polly { bool isAffineExpr(const llvm::Region *R, const llvm::SCEV *Expression, - llvm::ScalarEvolution &SE, llvm::Value **BaseAddress = 0); + llvm::ScalarEvolution &SE, + const llvm::Value *BaseAddress = 0); std::vector getParamsInAffineExpr( const llvm::Region *R, const llvm::SCEV *Expression, llvm::ScalarEvolution &SE, - llvm::Value **BaseAddress = 0); + const llvm::Value *BaseAddress = 0); } Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=144280&r1=144279&r2=144280&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Thu Nov 10 06:45:03 2011 @@ -212,10 +212,10 @@ bool ScopDetection::isValidMemoryAccess(Instruction &Inst, DetectionContext &Context) const { - Value *Ptr = getPointerOperand(Inst), *BasePtr; + Value *Ptr = getPointerOperand(Inst); const SCEV *AccessFunction = SE->getSCEV(Ptr); const SCEVUnknown *BasePointer; - const Value *BaseValue; + Value *BaseValue; BasePointer = dyn_cast(SE->getPointerBase(AccessFunction)); @@ -229,23 +229,21 @@ AccessFunction = SE->getMinusSCEV(AccessFunction, BasePointer); - if (!isAffineExpr(&Context.CurRegion, AccessFunction, *SE)) + if (!isAffineExpr(&Context.CurRegion, AccessFunction, *SE, BaseValue)) INVALID(AffFunc, "Bad memory address " << *AccessFunction); - BasePtr = BasePointer->getValue(); - // FIXME: Alias Analysis thinks IntToPtrInst aliases with alloca instructions // created by IndependentBlocks Pass. - if (isa(BasePtr)) - INVALID(Other, "Find bad intToptr prt: " << *BasePtr); + if (isa(BaseValue)) + INVALID(Other, "Find bad intToptr prt: " << *BaseValue); // Check if the base pointer of the memory access does alias with // any other pointer. This cannot be handled at the moment. AliasSet &AS = - Context.AST.getAliasSetForPointer(BasePtr, AliasAnalysis::UnknownSize, + Context.AST.getAliasSetForPointer(BaseValue, AliasAnalysis::UnknownSize, Inst.getMetadata(LLVMContext::MD_tbaa)); if (!AS.isMustAlias()) { - DEBUG(dbgs() << "Bad pointer alias found:" << *BasePtr << "\nAS:\n" << AS); + DEBUG(dbgs() << "Bad pointer alias found:" << *BaseValue << "\nAS:\n" << AS); // STATSCOP triggers an assertion if we are in verifying mode. // This is generally good to check that we do not change the SCoP after we Modified: polly/trunk/lib/Analysis/ScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144280&r1=144279&r2=144280&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/ScopInfo.cpp Thu Nov 10 06:45:03 2011 @@ -76,24 +76,14 @@ int NbLoopSpaces; const Scop *scop; - /// baseAdress is set if we analyze a memory access. It holds the base address - /// of this memory access. - const Value *baseAddress; - public: - static isl_pw_aff *getPwAff(ScopStmt *stmt, const SCEV *scev, - Value **BaseAddress = NULL) { + static isl_pw_aff *getPwAff(ScopStmt *stmt, const SCEV *scev) { Scop *S = stmt->getParent(); const Region *Reg = &S->getRegion(); - if (BaseAddress) { - S->addParams(getParamsInAffineExpr(Reg, scev, *S->getSE(), BaseAddress)); - } else { - S->addParams(getParamsInAffineExpr(Reg, scev, *S->getSE())); - } + S->addParams(getParamsInAffineExpr(Reg, scev, *S->getSE())); - Value *Base = BaseAddress ? *BaseAddress : NULL; - SCEVAffinator Affinator(stmt, Base); + SCEVAffinator Affinator(stmt); return Affinator.visit(scev); } @@ -117,11 +107,10 @@ return SCEVVisitor::visit(scev); } - SCEVAffinator(const ScopStmt *stmt, const Value *baseAddress) : + SCEVAffinator(const ScopStmt *stmt) : ctx(stmt->getIslCtx()), NbLoopSpaces(stmt->getNumIterators()), - scop(stmt->getParent()), - baseAddress(baseAddress) {}; + scop(stmt->getParent()) {} __isl_give isl_pw_aff *visitConstant(const SCEVConstant *Constant) { ConstantInt *Value = Constant->getValue(); @@ -248,22 +237,14 @@ isl_space *Space; - /// If baseAddress is set, we ignore its Value object in the scev and do not - /// add it to the isl_pw_aff. This is because it is regarded as defining the - /// name of an array, in contrast to its array subscript. - if (baseAddress != Value) { - isl_id *ID = isl_id_alloc(ctx, Value->getNameStr().c_str(), Value); - Space = isl_space_set_alloc(ctx, 1, NbLoopSpaces); - Space = isl_space_set_dim_id(Space, isl_dim_param, 0, ID); - } else { - Space = isl_space_set_alloc(ctx, 0, NbLoopSpaces); - } + isl_id *ID = isl_id_alloc(ctx, Value->getNameStr().c_str(), Value); + Space = isl_space_set_alloc(ctx, 1, NbLoopSpaces); + Space = isl_space_set_dim_id(Space, isl_dim_param, 0, ID); isl_set *Domain = isl_set_universe(isl_space_copy(Space)); isl_aff *Affine = isl_aff_zero_on_domain(isl_local_space_from_space(Space)); - if (baseAddress != Value) - Affine = isl_aff_add_coefficient_si(Affine, isl_dim_param, 0, 1); + Affine = isl_aff_add_coefficient_si(Affine, isl_dim_param, 0, 1); return isl_pw_aff_alloc(Domain, Affine); } Modified: polly/trunk/lib/Analysis/TempScopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/TempScopInfo.cpp?rev=144280&r1=144279&r2=144280&view=diff ============================================================================== --- polly/trunk/lib/Analysis/TempScopInfo.cpp (original) +++ polly/trunk/lib/Analysis/TempScopInfo.cpp Thu Nov 10 06:45:03 2011 @@ -95,7 +95,9 @@ const SCEV *AccessFunction = SE->getSCEV(getPointerOperand(Inst)); const SCEVUnknown *BasePointer = - static_cast(SE->getPointerBase(AccessFunction)); + dyn_cast(SE->getPointerBase(AccessFunction)); + + assert(BasePointer && "Could not find base pointer"); AccessFunction = SE->getMinusSCEV(AccessFunction, BasePointer); Functions.push_back(std::make_pair(IRAccess(Type, Modified: polly/trunk/lib/Support/SCEVValidator.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/SCEVValidator.cpp?rev=144280&r1=144279&r2=144280&view=diff ============================================================================== --- polly/trunk/lib/Support/SCEVValidator.cpp (original) +++ polly/trunk/lib/Support/SCEVValidator.cpp Thu Nov 10 06:45:03 2011 @@ -57,11 +57,11 @@ private: const Region *R; ScalarEvolution &SE; - Value **BaseAddress; + const Value *BaseAddress; public: SCEVValidator(const Region *R, ScalarEvolution &SE, - Value **BaseAddress) : R(R), SE(SE), + const Value *BaseAddress) : R(R), SE(SE), BaseAddress(BaseAddress) {}; struct ValidatorResult visitConstant(const SCEVConstant *Constant) { @@ -215,33 +215,23 @@ if (isa(V)) return ValidatorResult(SCEVType::INVALID); - if (BaseAddress) { - if (*BaseAddress) - return ValidatorResult(SCEVType::INVALID); - else - *BaseAddress = V; - } - if (Instruction *I = dyn_cast(Expr->getValue())) if (R->contains(I)) return ValidatorResult(SCEVType::INVALID); - if (BaseAddress) - return ValidatorResult(SCEVType::PARAM); - else - return ValidatorResult(SCEVType::PARAM, Expr); + if (BaseAddress == V) + return ValidatorResult(SCEVType::INVALID); + + return ValidatorResult(SCEVType::PARAM, Expr); } }; namespace polly { bool isAffineExpr(const Region *R, const SCEV *Expr, ScalarEvolution &SE, - Value **BaseAddress) { + const Value *BaseAddress) { if (isa(Expr)) return false; - if (BaseAddress) - *BaseAddress = NULL; - SCEVValidator Validator(R, SE, BaseAddress); ValidatorResult Result = Validator.visit(Expr); @@ -251,13 +241,10 @@ std::vector getParamsInAffineExpr(const Region *R, const SCEV *Expr, ScalarEvolution &SE, - Value **BaseAddress) { + const Value *BaseAddress) { if (isa(Expr)) return std::vector(); - if (BaseAddress) - *BaseAddress = NULL; - SCEVValidator Validator(R, SE, BaseAddress); ValidatorResult Result = Validator.visit(Expr); From grosser at fim.uni-passau.de Thu Nov 10 06:45:11 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 12:45:11 -0000 Subject: [llvm-commits] [polly] r144282 - /polly/trunk/lib/Analysis/ScopDetection.cpp Message-ID: <20111110124511.629022A6C12E@llvm.org> Author: grosser Date: Thu Nov 10 06:45:11 2011 New Revision: 144282 URL: http://llvm.org/viewvc/llvm-project?rev=144282&view=rev Log: ScopDetection: Improve formatting of error message and simplify some code Modified: polly/trunk/lib/Analysis/ScopDetection.cpp Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=144282&r1=144281&r2=144282&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Thu Nov 10 06:45:11 2011 @@ -170,14 +170,13 @@ || isa(ICmp->getOperand(1))) INVALID(AffFunc, "undef operand in branch at BB: " + BB.getNameStr()); - const SCEV *ScevLHS = SE->getSCEV(ICmp->getOperand(0)); - const SCEV *ScevRHS = SE->getSCEV(ICmp->getOperand(1)); + const SCEV *LHS = SE->getSCEV(ICmp->getOperand(0)); + const SCEV *RHS = SE->getSCEV(ICmp->getOperand(1)); - bool affineLHS = isAffineExpr(&Context.CurRegion, ScevLHS, *SE); - bool affineRHS = isAffineExpr(&Context.CurRegion, ScevRHS, *SE); - - if (!affineLHS || !affineRHS) - INVALID(AffFunc, "Non affine branch in BB: " + BB.getNameStr()); + if (!isAffineExpr(&Context.CurRegion, LHS, *SE) || + !isAffineExpr(&Context.CurRegion, RHS, *SE)) + INVALID(AffFunc, "Non affine branch in BB '" << BB.getNameStr() + << "' with LHS: " << *LHS << " and RHS: " << *RHS); } // Allow loop exit conditions. From grosser at fim.uni-passau.de Thu Nov 10 06:45:15 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 12:45:15 -0000 Subject: [llvm-commits] [polly] r144283 - /polly/trunk/lib/Analysis/ScopDetection.cpp Message-ID: <20111110124515.4D68C2A6C12E@llvm.org> Author: grosser Date: Thu Nov 10 06:45:15 2011 New Revision: 144283 URL: http://llvm.org/viewvc/llvm-project?rev=144283&view=rev Log: ScopDetect: Clean the last failure message properly Modified: polly/trunk/lib/Analysis/ScopDetection.cpp Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=144283&r1=144282&r2=144283&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Thu Nov 10 06:45:15 2011 @@ -397,6 +397,8 @@ void ScopDetection::findScops(Region &R) { DetectionContext Context(R, *AA, false /*verifying*/); + LastFailure = ""; + if (isValidRegion(Context)) { ++ValidRegion; ValidRegions.insert(&R); From grosser at fim.uni-passau.de Thu Nov 10 06:47:21 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 12:47:21 -0000 Subject: [llvm-commits] [polly] r144284 - /polly/trunk/lib/Analysis/ScopDetection.cpp Message-ID: <20111110124721.B76332A6C12E@llvm.org> Author: grosser Date: Thu Nov 10 06:47:21 2011 New Revision: 144284 URL: http://llvm.org/viewvc/llvm-project?rev=144284&view=rev Log: ScopDetect: Use INVALID macro to fail in case of aliasing This simplifies the code and also makes the error message available to the graphviz scop viewer. Modified: polly/trunk/lib/Analysis/ScopDetection.cpp Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=144284&r1=144283&r2=144284&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Thu Nov 10 06:47:21 2011 @@ -241,22 +241,8 @@ AliasSet &AS = Context.AST.getAliasSetForPointer(BaseValue, AliasAnalysis::UnknownSize, Inst.getMetadata(LLVMContext::MD_tbaa)); - if (!AS.isMustAlias()) { - DEBUG(dbgs() << "Bad pointer alias found:" << *BaseValue << "\nAS:\n" << AS); - - // STATSCOP triggers an assertion if we are in verifying mode. - // This is generally good to check that we do not change the SCoP after we - // run the SCoP detection and consequently to ensure that we can still - // represent that SCoP. However, in case of aliasing this does not work. - // The independent blocks pass may create memory references which seem to - // alias, if -basicaa is not available. They actually do not. As we do not - // not know this and we would fail here if we verify it. - if (!Context.Verifying) { - STATSCOP(Alias); - } - - return false; - } + if (!AS.isMustAlias()) + INVALID(Alias, "Possible aliasing found for value: " << *BaseValue); return true; } From grosser at fim.uni-passau.de Thu Nov 10 06:47:26 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 12:47:26 -0000 Subject: [llvm-commits] [polly] r144285 - in /polly/trunk: lib/Analysis/ScopDetection.cpp www/example_load_Polly_into_clang.html Message-ID: <20111110124726.7BB7C2A6C12E@llvm.org> Author: grosser Date: Thu Nov 10 06:47:26 2011 New Revision: 144285 URL: http://llvm.org/viewvc/llvm-project?rev=144285&view=rev Log: ScopDetection: Add flag to ignore possible aliasing Modified: polly/trunk/lib/Analysis/ScopDetection.cpp polly/trunk/www/example_load_Polly_into_clang.html Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=144285&r1=144284&r2=144285&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Thu Nov 10 06:47:26 2011 @@ -74,6 +74,10 @@ cl::value_desc("The function name to detect scops in"), cl::ValueRequired, cl::init("")); +static cl::opt +IgnoreAliasing("polly-ignore-aliasing", + cl::desc("Ignore possible aliasing of the array bases"), + cl::Hidden, cl::init(false)); //===----------------------------------------------------------------------===// // Statistics. @@ -241,7 +245,7 @@ AliasSet &AS = Context.AST.getAliasSetForPointer(BaseValue, AliasAnalysis::UnknownSize, Inst.getMetadata(LLVMContext::MD_tbaa)); - if (!AS.isMustAlias()) + if (!AS.isMustAlias() && !IgnoreAliasing) INVALID(Alias, "Possible aliasing found for value: " << *BaseValue); return true; Modified: polly/trunk/www/example_load_Polly_into_clang.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/example_load_Polly_into_clang.html?rev=144285&r1=144284&r2=144285&view=diff ============================================================================== --- polly/trunk/www/example_load_Polly_into_clang.html (original) +++ polly/trunk/www/example_load_Polly_into_clang.html Thu Nov 10 06:47:26 2011 @@ -91,6 +91,14 @@ By default both optimizers perform tiling, if possible. In case this is not wanted the option '-polly-no-tiling' can be used to disable it. (This option works for both optimizers). + +

    Ignore possible aliasing

    +By default we only detect scops, if we can prove that the different array bases +can not alias. This is the correct thing to do if optimizing automatically. +However, this may yield to a low scop coverage as without special user +annotations like 'restrict' the absence of aliasing can often not be proven. +When optimizing code where we know no aliasing can happen, we may want to remove +this restriction. From grosser at fim.uni-passau.de Thu Nov 10 07:21:43 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 13:21:43 -0000 Subject: [llvm-commits] [polly] r144286 - /polly/trunk/lib/Analysis/ScopDetection.cpp Message-ID: <20111110132143.54A912A6C12E@llvm.org> Author: grosser Date: Thu Nov 10 07:21:43 2011 New Revision: 144286 URL: http://llvm.org/viewvc/llvm-project?rev=144286&view=rev Log: ScopDetection: Do not verify Aliasing This does not work reliable and is probably not needed. I accidentally changed this in this recent commit: commit a0bcd63c6ffa81616cf8c6663a87588803f7d91c Author: grosser Date: Thu Nov 10 12:47:21 2011 +0000 ScopDetect: Use INVALID macro to fail in case of aliasing This simplifies the code and also makes the error message available to the graphviz scop viewer. git-svn-id: https://llvm.org/svn/llvm-project/polly/trunk at 144284 Modified: polly/trunk/lib/Analysis/ScopDetection.cpp Modified: polly/trunk/lib/Analysis/ScopDetection.cpp URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=144286&r1=144285&r2=144286&view=diff ============================================================================== --- polly/trunk/lib/Analysis/ScopDetection.cpp (original) +++ polly/trunk/lib/Analysis/ScopDetection.cpp Thu Nov 10 07:21:43 2011 @@ -88,9 +88,6 @@ "Number of bad regions for Scop: "\ DESC) -#define STATSCOP(NAME); assert(!Context.Verifying && #NAME); \ - if (!Context.Verifying) ++Bad##NAME##ForScop; - #define INVALID(NAME, MESSAGE) \ do { \ std::string Buf; \ @@ -100,7 +97,23 @@ LastFailure = Buf; \ DEBUG(dbgs() << MESSAGE); \ DEBUG(dbgs() << "\n"); \ - STATSCOP(NAME); \ + assert(!Context.Verifying && #NAME); \ + if (!Context.Verifying) ++Bad##NAME##ForScop; \ + return false; \ + } while (0); + + +#define INVALID_NOVERIFY(NAME, MESSAGE) \ + do { \ + std::string Buf; \ + raw_string_ostream fmt(Buf); \ + fmt << MESSAGE; \ + fmt.flush(); \ + LastFailure = Buf; \ + DEBUG(dbgs() << MESSAGE); \ + DEBUG(dbgs() << "\n"); \ + /* DISABLED: assert(!Context.Verifying && #NAME); */ \ + if (!Context.Verifying) ++Bad##NAME##ForScop; \ return false; \ } while (0); @@ -245,8 +258,17 @@ AliasSet &AS = Context.AST.getAliasSetForPointer(BaseValue, AliasAnalysis::UnknownSize, Inst.getMetadata(LLVMContext::MD_tbaa)); + + // INVALID triggers an assertion in verifying mode, if it detects that a SCoP + // was detected by SCoP detection and that this SCoP was invalidated by a pass + // that stated it would preserve the SCoPs. + // We disable this check as the independent blocks pass may create memory + // references which seem to alias, if -basicaa is not available. They actually + // do not, but as we can not proof this without -basicaa we would fail. We + // disable this check to not cause irrelevant verification failures. if (!AS.isMustAlias() && !IgnoreAliasing) - INVALID(Alias, "Possible aliasing found for value: " << *BaseValue); + INVALID_NOVERIFY(Alias, + "Possible aliasing found for value: " << *BaseValue); return true; } From grosser at fim.uni-passau.de Thu Nov 10 08:00:01 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 14:00:01 -0000 Subject: [llvm-commits] [polly] r144287 - /polly/trunk/www/example_load_Polly_into_clang.html Message-ID: <20111110140001.186742A6C12E@llvm.org> Author: grosser Date: Thu Nov 10 08:00:00 2011 New Revision: 144287 URL: http://llvm.org/viewvc/llvm-project?rev=144287&view=rev Log: www: Highlight command line flags Modified: polly/trunk/www/example_load_Polly_into_clang.html Modified: polly/trunk/www/example_load_Polly_into_clang.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/example_load_Polly_into_clang.html?rev=144287&r1=144286&r2=144287&view=diff ============================================================================== --- polly/trunk/www/example_load_Polly_into_clang.html (original) +++ polly/trunk/www/example_load_Polly_into_clang.html Thu Nov 10 08:00:00 2011 @@ -22,8 +22,8 @@ database and consider reporting the bug.

    Compiling code with Polly

    -To compile code with Polly you only need to add '-Xclang -load -Xclang -${POLLY_BUILD_DIR}/lib/LLVMPolly.so' to your command line or your CFLAGS and +To compile code with Polly you only need to add -Xclang -load -Xclang +${POLLY_BUILD_DIR}/lib/LLVMPolly.so to your command line or your CFLAGS and Polly is automatically executed at -O3.

    @@ -36,14 +36,14 @@

    Automatic OpenMP code generation

    To automatically detect parallel loops and generate OpenMP code for them you -also need to add '-mllvm -enable-polly-openmp -lgomp' to your CFLAGS. +also need to add -mllvm -enable-polly-openmp -lgomp to your CFLAGS. 
    clang -Xclang -load -Xclang ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 -mllvm -enable-polly-openmp -lgomp file.c

    Automatic Vector code generation

    -Automatic vector code generation can be enabled by adding '-mllvm --enable-polly-vector' to your CFLAGS. +Automatic vector code generation can be enabled by adding -mllvm +-enable-polly-vector to your CFLAGS. 
    clang -Xclang -load -Xclang ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 -mllvm -enable-polly-vector file.c
    @@ -51,24 +51,24 @@ Polly supports further options that are mainly useful for the development or the -analysis of Polly. The relevant options can be -added to clang by appending '-mllvm -option-name' to the CFLAGS or the clang +analysis of Polly. The relevant options can be added to clang by appending +-mllvm -option-name to the CFLAGS or the clang command line.

    Limit Polly to a single function

    To limit the execution of Polly to a single function, use the option -'-polly-detect-only=functionname'. +-polly-detect-only=functionname.

    Disable LLVM-IR generation

    Polly normally regenerates LLVM-IR from the Polyhedral representation. To only see the effects of the preparing transformation, but to disable Polly code -generation add the option 'polly-no-codegen'. +generation add the option polly-no-codegen.

    Graphical view of the SCoPs

    Polly can use graphviz to show the SCoPs it detects in a program. The relevant -options are '-polly-show', '-polly-show-only', '-polly-dot' and -'-polly-dot-only'. The 'show' options automatically run dotty or another +options are -polly-show, -polly-show-only, -polly-dot and +-polly-dot-only. The 'show' options automatically run dotty or another graphviz viewer to show the scops graphically. The 'dot' options store for each function a dot file that highlights the detected SCoPs. If 'only' is appended at the end of the option, the basic blocks are shown without the statements the @@ -76,8 +76,8 @@

    Disable the polyhedral optimizer

    -Polly automatically runs a polyhedral optimizer to optimize the schedules. To -disable it add the option '-polly-no-optimizer'. +Polly automatically runs by default a polyhedral optimizer to optimize the +schedules. -polly-no-optimizer disables this optimizer.

    Use the PoCC optimizer

    Polly uses by default the isl scheduling optimizer, a new implementation of the @@ -85,20 +85,20 @@ default is that it does not require any additional libraries or tools to be installed. As the new scheduler may still have some bugs and because being able to compare is good in general, it is possible to switch the used optimizer -back to PoCC. For this add the option '-polly-use-pocc'. +back to PoCC. For this add the option -polly-use-pocc.

    Disable tiling in the optimizer

    By default both optimizers perform tiling, if possible. In case this is not -wanted the option '-polly-no-tiling' can be used to disable it. (This option -works for both optimizers). +wanted the option -polly-no-tiling can be used to disable it. (This +option disables tiling for both optimizers).

    Ignore possible aliasing

    By default we only detect scops, if we can prove that the different array bases -can not alias. This is the correct thing to do if optimizing automatically. -However, this may yield to a low scop coverage as without special user -annotations like 'restrict' the absence of aliasing can often not be proven. -When optimizing code where we know no aliasing can happen, we may want to remove -this restriction. +can not alias. This is correct do if we optimize automatically. However, +without special user annotations like 'restrict' we can often not prove that +no aliasing is possible. In case the user knows no aliasing can happen in the +code the -polly-ignore-aliasing can be used to disable the check for +possible aliasing. From grosser at fim.uni-passau.de Thu Nov 10 08:00:04 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 14:00:04 -0000 Subject: [llvm-commits] [polly] r144288 - /polly/trunk/www/index.html Message-ID: <20111110140004.8C02A2A6C12E@llvm.org> Author: grosser Date: Thu Nov 10 08:00:04 2011 New Revision: 144288 URL: http://llvm.org/viewvc/llvm-project?rev=144288&view=rev Log: www: Add some news about Polly Modified: polly/trunk/www/index.html Modified: polly/trunk/www/index.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/index.html?rev=144288&r1=144287&r2=144288&view=diff ============================================================================== --- polly/trunk/www/index.html (original) +++ polly/trunk/www/index.html Thu Nov 10 08:00:04 2011 @@ -36,6 +36,18 @@
      +
    • November 2011 - Talk at the + LLVM Developer Meeting 2011 +
      • +
    • November 2011 - New SCEV parser (Support for parameters in array + subscript as well as max/min/signextend) +
      • +
    • October 2011 - Support for the isl scheduler (similar to Pluto, but + part of isl. At the moment it still has performance issues). +
      • +
    • August 2011 - Use Polly as + clang plugin +
    • July 2011 - Add Polly builder to the LLVM Buildbots
      • From grosser at fim.uni-passau.de Thu Nov 10 08:01:53 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 10 Nov 2011 14:01:53 -0000 Subject: [llvm-commits] [polly] r144289 - /polly/trunk/www/menu.html.incl Message-ID: <20111110140153.DA4A32A6C12E@llvm.org> Author: grosser Date: Thu Nov 10 08:01:53 2011 New Revision: 144289 URL: http://llvm.org/viewvc/llvm-project?rev=144289&view=rev Log: www: Remove link to LLVM for upper left corner. This confused a lot of people Modified: polly/trunk/www/menu.html.incl Modified: polly/trunk/www/menu.html.incl URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/menu.html.incl?rev=144289&r1=144288&r2=144289&view=diff ============================================================================== --- polly/trunk/www/menu.html.incl (original) +++ polly/trunk/www/menu.html.incl Thu Nov 10 08:01:53 2011 @@ -1,12 +1,8 @@
    • TimeTalkLocation
    8:00 - 9:00Light BreakfastTBD
    8:00 - 9:00BreakfastBallroom Foyer
    9:00 - 9:20Welcome
    Chris Lattner, Apple Inc.    		Ballroom Salon III/IV
    9:20 - 10:05Extending Clang
    Doug Gregor, Apple Inc.    		Ballroom Salon III/IV
    PTX Back-End: GPU Programming With LLVM
    Justin Holewinski, Ohio State    		Ballroom Salon V/VI
    Improving LLVM Testing BOF
    David Blaikie    		Ballroom Salon II
    10:50 - 11:05BreakTBD
    10:50 - 11:05BreakBallroom Foyer
    11:05 - 11:50Integrating LLVM into FreeBSD
    Brooks Davis, The FreeBSD Proje ct    		Ballroom Salon III/IV
    SKIR: Just-in-Time Compilation for Parallelism with LLVM
    Jeff Fifield, University of Colorado    		Ballroom Salon V/VI
    Improving the Clang Driver BOF
    James Molloy, ARM    		Ballroom Salon II
    3:05 - 3:45PostersTBD
    3:05 - 3:45PostersBallroom Foyer
    LunarGLASS: A LLVM-based shader compiler stack
    Michael Ilseman, LunarG    		Ballroom Salon II
    Symbolic Testing of OpenCL Code
    Peter Collingbourne, Imperial College London    		Ballroom Salon II
    Code verification based on attributes annotation - Implementing custom attributes check using Clang
    Michael Han, Autodesk    		Ballroom Salon II
    1:35 - 2:20Using clang in the Chromium project
    Nico Weber, Hans Wennborg, Google    		Ballroom Salon III/IV
    Polly - First successful optimizations - How to proceed?
    Tobias Grosser, ENS/INRIA    		Ballroom Salon V/VI
    MC Linkers BOF
    Luba Tang, Mediateki, Shih-wei Liao, Google    		Ballroom Salon II
    MC Linkers BOF
    Luba Tang, Mediatek, Shih-wei Liao, Google    		Ballroom Salon II
    2:20 - 3:05Android Renderscript
    Stephen Hines, Google    		Ballroom Salon III/IV
    SKIR: Just-in-Time Compilation for Parallelism with LLVM
    Jeff Fifield, University of Colorado    		Ballroom Salon V/VI