From craig.topper at gmail.com  Mon Nov 14 00:46:21 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Mon, 14 Nov 2011 06:46:21 -0000
Subject: [llvm-commits] [llvm] r144522 - in /llvm/trunk/lib/Target/X86:
 X86ISelLowering.cpp X86InstrSSE.td
Message-ID: <20111114064621.5825B2A6C131@llvm.org>

Author: ctopper
Date: Mon Nov 14 00:46:21 2011
New Revision: 144522

URL: http://llvm.org/viewvc/llvm-project?rev=144522&view=rev
Log:
Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144522&r1=144521&r2=144522&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Nov 14 00:46:21 2011
@@ -6623,7 +6623,6 @@
   EVT VT = Op.getValueType();
   DebugLoc dl = Op.getDebugLoc();
   unsigned NumElems = VT.getVectorNumElements();
-  bool isMMX = VT.getSizeInBits() == 64;
   bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
   bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
   bool V1IsSplat = false;
@@ -6632,9 +6631,7 @@
   MachineFunction &MF = DAG.getMachineFunction();
   bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
 
-  // Shuffle operations on MMX not supported.
-  if (isMMX)
-    return Op;
+  assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
 
   // Vector shuffle lowering takes 3 steps:
   //
@@ -6646,7 +6643,7 @@
   //    so the shuffle can be broken into other shuffles and the legalizer can
   //    try the lowering again.
   //
-  // The general ideia is that no vector_shuffle operation should be left to
+  // The general idea is that no vector_shuffle operation should be left to
   // be matched during isel, all of them must be converted to a target specific
   // node here.
 

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144522&r1=144521&r2=144522&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Nov 14 00:46:21 2011
@@ -80,8 +80,9 @@
 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
                                       string OpcodeStr, X86MemOperand x86memop,
                                       list<dag> pat_rr, list<dag> pat_rm,
-                                      bit Is2Addr = 1> {
-  let isCommutable = 1 in
+                                      bit Is2Addr = 1,
+                                      bit rr_hasSideEffects = 0> {
+  let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
     def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
        !if(Is2Addr,
            !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
@@ -2629,7 +2630,7 @@
   defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
        !strconcat(OpcodeStr, "ps"), f128mem, [],
        [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
-                                 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
+                                 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
 
   defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
        !strconcat(OpcodeStr, "pd"), f128mem,
@@ -2926,12 +2927,15 @@
 
 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
+  let neverHasSideEffects = 1 in {
   def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
                !strconcat(OpcodeStr,
                           "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+  let mayLoad = 1 in
   def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
                !strconcat(OpcodeStr,
                           "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+  }
   def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
                (ins VR128:$src1, sdmem:$src2),
                !strconcat(OpcodeStr,
@@ -3799,14 +3803,15 @@
                          (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
                          "psrldq\t{$src2, $dst|$dst, $src2}", []>;
     // PSRADQri doesn't exist in SSE[1-3].
-  }
-  def PANDNrr : PDI<0xDF, MRMSrcReg,
-                    (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
-                    "pandn\t{$src2, $dst|$dst, $src2}", []>;
+    def PANDNrr : PDI<0xDF, MRMSrcReg,
+                      (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+                      "pandn\t{$src2, $dst|$dst, $src2}", []>;
 
-  def PANDNrm : PDI<0xDF, MRMSrcMem,
-                    (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
-                    "pandn\t{$src2, $dst|$dst, $src2}", []>;
+    let mayLoad = 1 in
+    def PANDNrm : PDI<0xDF, MRMSrcMem,
+                      (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
+                      "pandn\t{$src2, $dst|$dst, $src2}", []>;
+  }
 }
 } // Constraints = "$src1 = $dst"
 
@@ -5348,6 +5353,7 @@
 //===---------------------------------------------------------------------===//
 
 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
+  let neverHasSideEffects = 1 in {
   def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
       (ins VR128:$src1, VR128:$src2, i8imm:$src3),
       !if(Is2Addr,
@@ -5355,6 +5361,7 @@
         !strconcat(asm,
                   "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
       []>, OpSize;
+  let mayLoad = 1 in
   def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
       (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
       !if(Is2Addr,
@@ -5362,19 +5369,23 @@
         !strconcat(asm,
                   "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
       []>, OpSize;
+  }
 }
 
 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
+  let neverHasSideEffects = 1 in {
   def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
       (ins VR256:$src1, VR256:$src2, i8imm:$src3),
       !strconcat(asm,
                  "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
       []>, OpSize;
+  let mayLoad = 1 in
   def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
       (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
       !strconcat(asm,
                  "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
       []>, OpSize;
+  }
 }
 
 let Predicates = [HasAVX] in
@@ -5721,6 +5732,7 @@
                   "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
                  [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
                  OpSize;
+  let neverHasSideEffects = 1, mayStore = 1 in
   def mr : SS4AIi8<opc, MRMDestMem, (outs),
                  (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
                  !strconcat(OpcodeStr,
@@ -5743,6 +5755,7 @@
 
 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
+  let neverHasSideEffects = 1, mayStore = 1 in
   def mr : SS4AIi8<opc, MRMDestMem, (outs),
                  (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
                  !strconcat(OpcodeStr,
@@ -6720,19 +6733,21 @@
   defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
 }
 
-let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
+let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
   def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
       (ins VR128:$src1, VR128:$src2, i8imm:$src3),
       "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
+  let mayLoad = 1 in
   def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
       (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
       "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
 }
 
-let Defs = [XMM0, EFLAGS] in {
+let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
   def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
       (ins VR128:$src1, VR128:$src2, i8imm:$src3),
       "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
+  let mayLoad = 1 in
   def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
       (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
       "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
@@ -6756,19 +6771,21 @@
 }
 
 let Predicates = [HasAVX],
-    Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
+    Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
   def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
       (ins VR128:$src1, VR128:$src3, i8imm:$src5),
       "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
+  let mayLoad = 1 in
   def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
       (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
       "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
 }
 
-let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
+let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
   def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
       (ins VR128:$src1, VR128:$src3, i8imm:$src5),
       "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
+  let mayLoad = 1 in
   def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
       (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
       "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
@@ -7071,12 +7088,14 @@
 //===----------------------------------------------------------------------===//
 
 // Carry-less Multiplication instructions
+let neverHasSideEffects = 1 in {
 let Constraints = "$src1 = $dst" in {
 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
            (ins VR128:$src1, VR128:$src2, i8imm:$src3),
            "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
            []>;
 
+let mayLoad = 1 in
 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
            (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
            "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
@@ -7089,10 +7108,12 @@
            "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
            []>;
 
+let mayLoad = 1 in
 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
            (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
            "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
            []>;
+}
 
 
 multiclass pclmul_alias<string asm, int immop> {



From chandlerc at gmail.com  Mon Nov 14 00:51:49 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 14 Nov 2011 06:51:49 -0000
Subject: [llvm-commits] [llvm] r144523 -
 /llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
Message-ID: <20111114065149.98EF22A6C131@llvm.org>

Author: chandlerc
Date: Mon Nov 14 00:51:49 2011
New Revision: 144523

URL: http://llvm.org/viewvc/llvm-project?rev=144523&view=rev
Log:
Add a cautionary note to this API. It was not at all obvious to me how
expensive the most useful interface to this analysis is.

Fun story -- it's also not correct. That's getting fixed in another
patch.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h

Modified: llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h?rev=144523&r1=144522&r2=144523&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h Mon Nov 14 00:51:49 2011
@@ -62,6 +62,9 @@
   // Return a probability as a fraction between 0 (0% probability) and
   // 1 (100% probability), however the value is never equal to 0, and can be 1
   // only iff SRC block has only one successor.
+  // NB: This routine's complexity is linear on the number of successors of
+  // Src. Querying sequentially for each successor's probability is a quadratic
+  // query pattern.
   BranchProbability getEdgeProbability(MachineBasicBlock *Src,
                                        MachineBasicBlock *Dst) const;
 



From matthewbg at google.com  Mon Nov 14 02:13:08 2011
From: matthewbg at google.com (Matt Beaumont-Gay)
Date: Mon, 14 Nov 2011 00:13:08 -0800
Subject: [llvm-commits] [llvm] r144473 -
	/llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll
In-Reply-To: <20111112223937.CE6BE2A6C130@llvm.org>
References: <20111112223937.CE6BE2A6C130@llvm.org>
Message-ID: <CAOL_hqDaK0pAdBhKO=khYBRrS0jfirVu68h2UqKjJYz2HScUag@mail.gmail.com>

On Sat, Nov 12, 2011 at 14:39, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
> Author: stoklund
> Date: Sat Nov 12 16:39:37 2011
> New Revision: 144473
>
> URL: http://llvm.org/viewvc/llvm-project?rev=144473&view=rev
> Log:
> RAGreedy is better about hinting now.
>
> Or maybe we are just getting lucky.
>
> Modified:
> ? ?llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll
>
> Modified: llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll?rev=144473&r1=144472&r2=144473&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll Sat Nov 12 16:39:37 2011
> @@ -1,4 +1,4 @@
> -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s
> +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-post-ra | FileCheck %s
>
> ?; The ARM magic hinting works best with linear scan.

Stale comment?


From craig.topper at gmail.com  Mon Nov 14 02:07:55 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Mon, 14 Nov 2011 08:07:55 -0000
Subject: [llvm-commits] [llvm] r144525 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Message-ID: <20111114080755.E102A2A6C131@llvm.org>

Author: ctopper
Date: Mon Nov 14 02:07:55 2011
New Revision: 144525

URL: http://llvm.org/viewvc/llvm-project?rev=144525&view=rev
Log:
Add AVX2 version of instructions to load folding tables. Also add a bunch of missing SSE/AVX instructions.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=144525&r1=144524&r2=144525&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Nov 14 02:07:55 2011
@@ -456,6 +456,9 @@
     { X86::MOVZX64rr16,     X86::MOVZX64rm16,         0 },
     { X86::MOVZX64rr32,     X86::MOVZX64rm32,         0 },
     { X86::MOVZX64rr8,      X86::MOVZX64rm8,          0 },
+    { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
+    { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
+    { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
@@ -508,6 +511,9 @@
     { X86::VMOVZDI2PDIrr,   X86::VMOVZDI2PDIrm,       0 },
     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
+    { X86::VPABSBrr128,     X86::VPABSBrm128,         TB_ALIGN_16 },
+    { X86::VPABSDrr128,     X86::VPABSDrm128,         TB_ALIGN_16 },
+    { X86::VPABSWrr128,     X86::VPABSWrm128,         TB_ALIGN_16 },
     { X86::VPSHUFDri,       X86::VPSHUFDmi,           TB_ALIGN_16 },
     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          TB_ALIGN_16 },
     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          TB_ALIGN_16 },
@@ -526,7 +532,14 @@
     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_16 },
     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
-    { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 }
+    { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
+    // AVX2 foldable instructions
+    { X86::VPABSBrr256,     X86::VPABSBrm256,         TB_ALIGN_16 },
+    { X86::VPABSDrr256,     X86::VPABSDrm256,         TB_ALIGN_16 },
+    { X86::VPABSWrr256,     X86::VPABSWrm256,         TB_ALIGN_16 },
+    { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          TB_ALIGN_16 },
+    { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         TB_ALIGN_16 },
+    { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         TB_ALIGN_16 }
   };
 
   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
@@ -652,6 +665,7 @@
     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
     { X86::MINSSrr,         X86::MINSSrm,       0 },
     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
+    { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
     { X86::MULSDrr,         X86::MULSDrm,       0 },
@@ -664,30 +678,44 @@
     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
+    { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
+    { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
+    { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
+    { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
+    { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
+    { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
+    { X86::PHADDDrr128,     X86::PHADDDrm128,   TB_ALIGN_16 },
+    { X86::PHADDWrr128,     X86::PHADDWrm128,   TB_ALIGN_16 },
+    { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
+    { X86::PHSUBDrr128,     X86::PHSUBDrm128,   TB_ALIGN_16 },
+    { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
+    { X86::PHSUBWrr128,     X86::PHSUBWrm128,   TB_ALIGN_16 },
     { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
+    { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
+    { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
@@ -695,6 +723,10 @@
     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
+    { X86::PSHUFBrr128,     X86::PSHUFBrm128,   TB_ALIGN_16 },
+    { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
+    { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
+    { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
@@ -816,6 +848,7 @@
     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
+    { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        TB_ALIGN_16 },
     { X86::VMULPDrr,          X86::VMULPDrm,           TB_ALIGN_16 },
     { X86::VMULPSrr,          X86::VMULPSrm,           TB_ALIGN_16 },
     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
@@ -824,28 +857,44 @@
     { X86::VORPSrr,           X86::VORPSrm,            TB_ALIGN_16 },
     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        TB_ALIGN_16 },
     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        TB_ALIGN_16 },
+    { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        TB_ALIGN_16 },
     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        TB_ALIGN_16 },
     { X86::VPADDBrr,          X86::VPADDBrm,           TB_ALIGN_16 },
     { X86::VPADDDrr,          X86::VPADDDrm,           TB_ALIGN_16 },
     { X86::VPADDQrr,          X86::VPADDQrm,           TB_ALIGN_16 },
     { X86::VPADDSBrr,         X86::VPADDSBrm,          TB_ALIGN_16 },
     { X86::VPADDSWrr,         X86::VPADDSWrm,          TB_ALIGN_16 },
+    { X86::VPADDUSBrr,        X86::VPADDUSBrm,         TB_ALIGN_16 },
+    { X86::VPADDUSWrr,        X86::VPADDUSWrm,         TB_ALIGN_16 },
     { X86::VPADDWrr,          X86::VPADDWrm,           TB_ALIGN_16 },
+    { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      TB_ALIGN_16 },
     { X86::VPANDNrr,          X86::VPANDNrm,           TB_ALIGN_16 },
     { X86::VPANDrr,           X86::VPANDrm,            TB_ALIGN_16 },
+    { X86::VPAVGBrr,          X86::VPAVGBrm,           TB_ALIGN_16 },
+    { X86::VPAVGWrr,          X86::VPAVGWrm,           TB_ALIGN_16 },
     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         TB_ALIGN_16 },
     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         TB_ALIGN_16 },
+    { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         TB_ALIGN_16 },
     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         TB_ALIGN_16 },
     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         TB_ALIGN_16 },
     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         TB_ALIGN_16 },
+    { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         TB_ALIGN_16 },
     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         TB_ALIGN_16 },
+    { X86::VPHADDDrr128,      X86::VPHADDDrm128,       TB_ALIGN_16 },
+    { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      TB_ALIGN_16 },
+    { X86::VPHADDWrr128,      X86::VPHADDWrm128,       TB_ALIGN_16 },
+    { X86::VPHSUBDrr128,      X86::VPHSUBDrm128,       TB_ALIGN_16 },
+    { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      TB_ALIGN_16 },
+    { X86::VPHSUBWrr128,      X86::VPHSUBWrm128,       TB_ALIGN_16 },
     { X86::VPINSRWrri,        X86::VPINSRWrmi,         TB_ALIGN_16 },
+    { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    TB_ALIGN_16 },
     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         TB_ALIGN_16 },
     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          TB_ALIGN_16 },
     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          TB_ALIGN_16 },
     { X86::VPMINSWrr,         X86::VPMINSWrm,          TB_ALIGN_16 },
     { X86::VPMINUBrr,         X86::VPMINUBrm,          TB_ALIGN_16 },
     { X86::VPMULDQrr,         X86::VPMULDQrm,          TB_ALIGN_16 },
+    { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     TB_ALIGN_16 },
     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         TB_ALIGN_16 },
     { X86::VPMULHWrr,         X86::VPMULHWrm,          TB_ALIGN_16 },
     { X86::VPMULLDrr,         X86::VPMULLDrm,          TB_ALIGN_16 },
@@ -853,6 +902,10 @@
     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         TB_ALIGN_16 },
     { X86::VPORrr,            X86::VPORrm,             TB_ALIGN_16 },
     { X86::VPSADBWrr,         X86::VPSADBWrm,          TB_ALIGN_16 },
+    { X86::VPSHUFBrr128,      X86::VPSHUFBrm128,       TB_ALIGN_16 },
+    { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       TB_ALIGN_16 },
+    { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       TB_ALIGN_16 },
+    { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       TB_ALIGN_16 },
     { X86::VPSLLDrr,          X86::VPSLLDrm,           TB_ALIGN_16 },
     { X86::VPSLLQrr,          X86::VPSLLQrm,           TB_ALIGN_16 },
     { X86::VPSLLWrr,          X86::VPSLLWrm,           TB_ALIGN_16 },
@@ -886,7 +939,91 @@
     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        TB_ALIGN_16 },
     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        TB_ALIGN_16 },
     { X86::VXORPDrr,          X86::VXORPDrm,           TB_ALIGN_16 },
-    { X86::VXORPSrr,          X86::VXORPSrm,           TB_ALIGN_16 }
+    { X86::VXORPSrr,          X86::VXORPSrm,           TB_ALIGN_16 },
+    // AVX2 foldable instructions
+    { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       TB_ALIGN_16 },
+    { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       TB_ALIGN_16 },
+    { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       TB_ALIGN_16 },
+    { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       TB_ALIGN_16 },
+    { X86::VPADDBYrr,         X86::VPADDBYrm,          TB_ALIGN_16 },
+    { X86::VPADDDYrr,         X86::VPADDDYrm,          TB_ALIGN_16 },
+    { X86::VPADDQYrr,         X86::VPADDQYrm,          TB_ALIGN_16 },
+    { X86::VPADDSBYrr,        X86::VPADDSBYrm,         TB_ALIGN_16 },
+    { X86::VPADDSWYrr,        X86::VPADDSWYrm,         TB_ALIGN_16 },
+    { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        TB_ALIGN_16 },
+    { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        TB_ALIGN_16 },
+    { X86::VPADDWYrr,         X86::VPADDWYrm,          TB_ALIGN_16 },
+    { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      TB_ALIGN_16 },
+    { X86::VPANDNYrr,         X86::VPANDNYrm,          TB_ALIGN_16 },
+    { X86::VPANDYrr,          X86::VPANDYrm,           TB_ALIGN_16 },
+    { X86::VPAVGBYrr,         X86::VPAVGBYrm,          TB_ALIGN_16 },
+    { X86::VPAVGWYrr,         X86::VPAVGWYrm,          TB_ALIGN_16 },
+    { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        TB_ALIGN_16 },
+    { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        TB_ALIGN_16 },
+    { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        TB_ALIGN_16 },
+    { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        TB_ALIGN_16 },
+    { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        TB_ALIGN_16 },
+    { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        TB_ALIGN_16 },
+    { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        TB_ALIGN_16 },
+    { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        TB_ALIGN_16 },
+    { X86::VPHADDDrr256,      X86::VPHADDDrm256,       TB_ALIGN_16 },
+    { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      TB_ALIGN_16 },
+    { X86::VPHADDWrr256,      X86::VPHADDWrm256,       TB_ALIGN_16 },
+    { X86::VPHSUBDrr256,      X86::VPHSUBDrm256,       TB_ALIGN_16 },
+    { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      TB_ALIGN_16 },
+    { X86::VPHSUBWrr256,      X86::VPHSUBWrm256,       TB_ALIGN_16 },
+    { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    TB_ALIGN_16 },
+    { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        TB_ALIGN_16 },
+    { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         TB_ALIGN_16 },
+    { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         TB_ALIGN_16 },
+    { X86::VPMINSWYrr,        X86::VPMINSWYrm,         TB_ALIGN_16 },
+    { X86::VPMINUBYrr,        X86::VPMINUBYrm,         TB_ALIGN_16 },
+    { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       TB_ALIGN_16 },
+    { X86::VPMULDQYrr,        X86::VPMULDQYrm,         TB_ALIGN_16 },
+    { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     TB_ALIGN_16 },
+    { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        TB_ALIGN_16 },
+    { X86::VPMULHWYrr,        X86::VPMULHWYrm,         TB_ALIGN_16 },
+    { X86::VPMULLDYrr,        X86::VPMULLDYrm,         TB_ALIGN_16 },
+    { X86::VPMULLWYrr,        X86::VPMULLWYrm,         TB_ALIGN_16 },
+    { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        TB_ALIGN_16 },
+    { X86::VPORYrr,           X86::VPORYrm,            TB_ALIGN_16 },
+    { X86::VPSADBWYrr,        X86::VPSADBWYrm,         TB_ALIGN_16 },
+    { X86::VPSHUFBrr256,      X86::VPSHUFBrm256,       TB_ALIGN_16 },
+    { X86::VPSIGNBrr256,      X86::VPSIGNBrm256,       TB_ALIGN_16 },
+    { X86::VPSIGNWrr256,      X86::VPSIGNWrm256,       TB_ALIGN_16 },
+    { X86::VPSIGNDrr256,      X86::VPSIGNDrm256,       TB_ALIGN_16 },
+    { X86::VPSLLDYrr,         X86::VPSLLDYrm,          TB_ALIGN_16 },
+    { X86::VPSLLQYrr,         X86::VPSLLQYrm,          TB_ALIGN_16 },
+    { X86::VPSLLWYrr,         X86::VPSLLWYrm,          TB_ALIGN_16 },
+    { X86::VPSLLVDrr,         X86::VPSLLVDrm,          TB_ALIGN_16 },
+    { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         TB_ALIGN_16 },
+    { X86::VPSLLVQrr,         X86::VPSLLVQrm,          TB_ALIGN_16 },
+    { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         TB_ALIGN_16 },
+    { X86::VPSRADYrr,         X86::VPSRADYrm,          TB_ALIGN_16 },
+    { X86::VPSRAWYrr,         X86::VPSRAWYrm,          TB_ALIGN_16 },
+    { X86::VPSRAVDrr,         X86::VPSRAVDrm,          TB_ALIGN_16 },
+    { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         TB_ALIGN_16 },
+    { X86::VPSRLDYrr,         X86::VPSRLDYrm,          TB_ALIGN_16 },
+    { X86::VPSRLQYrr,         X86::VPSRLQYrm,          TB_ALIGN_16 },
+    { X86::VPSRLWYrr,         X86::VPSRLWYrm,          TB_ALIGN_16 },
+    { X86::VPSRLVDrr,         X86::VPSRLVDrm,          TB_ALIGN_16 },
+    { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         TB_ALIGN_16 },
+    { X86::VPSRLVQrr,         X86::VPSRLVQrm,          TB_ALIGN_16 },
+    { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         TB_ALIGN_16 },
+    { X86::VPSUBBYrr,         X86::VPSUBBYrm,          TB_ALIGN_16 },
+    { X86::VPSUBDYrr,         X86::VPSUBDYrm,          TB_ALIGN_16 },
+    { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         TB_ALIGN_16 },
+    { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         TB_ALIGN_16 },
+    { X86::VPSUBWYrr,         X86::VPSUBWYrm,          TB_ALIGN_16 },
+    { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      TB_ALIGN_16 },
+    { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      TB_ALIGN_16 },
+    { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     TB_ALIGN_16 },
+    { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      TB_ALIGN_16 },
+    { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      TB_ALIGN_16 },
+    { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      TB_ALIGN_16 },
+    { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     TB_ALIGN_16 },
+    { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      TB_ALIGN_16 },
+    { X86::VPXORYrr,          X86::VPXORYrm,           TB_ALIGN_16 },
     // FIXME: add AVX 256-bit foldable instructions
   };
 



From chandlerc at gmail.com  Mon Nov 14 02:50:16 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 14 Nov 2011 08:50:16 -0000
Subject: [llvm-commits] [llvm] r144526 - in /llvm/trunk:
 include/llvm/CodeGen/MachineBranchProbabilityInfo.h
 lib/CodeGen/MachineBranchProbabilityInfo.cpp
 test/CodeGen/X86/block-placement.ll
Message-ID: <20111114085016.857ED2A6C131@llvm.org>

Author: chandlerc
Date: Mon Nov 14 02:50:16 2011
New Revision: 144526

URL: http://llvm.org/viewvc/llvm-project?rev=144526&view=rev
Log:
Fix an overflow bug in MachineBranchProbabilityInfo. This pass relied on
the sum of the edge weights not overflowing uint32, and crashed when
they did. This is generally safe as BranchProbabilityInfo tries to
provide this guarantee. However, the CFG can get modified during codegen
in a way that grows the *sum* of the edge weights. This doesn't seem
unreasonable (imagine just adding more blocks all with the default
weight of 16), but it is hard to come up with a case that actually
triggers 32-bit overflow. Fortuately, the single-source GCC build is
good at this. The solution isn't very pretty, but its no worse than the
previous code. We're already summing all of the edge weights on each
query, we can sum them, check for an overflow, compute a scale, and sum
them again.

I've included a *greatly* reduced test case out of the GCC source that
triggers it. It's a pretty lame test, as it clearly is just barely
triggering the overflow. I'd like to have something that is much more
definitive, but I don't understand the fundamental pattern that triggers
an explosion in the edge weight sums.

The buggy code is duplicated within this file. I'll colapse them into
a single implementation in a subsequent commit.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
    llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp
    llvm/trunk/test/CodeGen/X86/block-placement.ll

Modified: llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h?rev=144526&r1=144525&r2=144526&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h Mon Nov 14 02:50:16 2011
@@ -34,8 +34,10 @@
   // weight to just "inherit" the non-zero weight of an adjacent successor.
   static const uint32_t DEFAULT_WEIGHT = 16;
 
-  // Get sum of the block successors' weights.
-  uint32_t getSumForBlock(MachineBasicBlock *MBB) const;
+  // Get sum of the block successors' weights, potentially scaling them to fit
+  // within 32-bits. If scaling is required, sets Scale based on the necessary
+  // adjustment. Any edge weights used with the sum should be divided by Scale.
+  uint32_t getSumForBlock(MachineBasicBlock *MBB, uint32_t &Scale) const;
 
 public:
   static char ID;

Modified: llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp?rev=144526&r1=144525&r2=144526&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp Mon Nov 14 02:50:16 2011
@@ -27,19 +27,34 @@
 char MachineBranchProbabilityInfo::ID = 0;
 
 uint32_t MachineBranchProbabilityInfo::
-getSumForBlock(MachineBasicBlock *MBB) const {
-  uint32_t Sum = 0;
-
+getSumForBlock(MachineBasicBlock *MBB, uint32_t &Scale) const {
+  // First we compute the sum with 64-bits of precision, ensuring that cannot
+  // overflow by bounding the number of weights considered. Hopefully no one
+  // actually needs 2^32 successors.
+  assert(MBB->succ_size() < UINT32_MAX);
+  uint64_t Sum = 0;
+  Scale = 1;
   for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
        E = MBB->succ_end(); I != E; ++I) {
-    MachineBasicBlock *Succ = *I;
-    uint32_t Weight = getEdgeWeight(MBB, Succ);
-    uint32_t PrevSum = Sum;
-
+    uint32_t Weight = getEdgeWeight(MBB, *I);
     Sum += Weight;
-    assert(Sum > PrevSum); (void) PrevSum;
   }
 
+  // If the computed sum fits in 32-bits, we're done.
+  if (Sum <= UINT32_MAX)
+    return Sum;
+
+  // Otherwise, compute the scale necessary to cause the weights to fit, and
+  // re-sum with that scale applied.
+  assert((Sum / UINT32_MAX) < UINT32_MAX);
+  Scale = (Sum / UINT32_MAX) + 1;
+  Sum = 0;
+  for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
+       E = MBB->succ_end(); I != E; ++I) {
+    uint32_t Weight = getEdgeWeight(MBB, *I);
+    Sum += Weight / Scale;
+  }
+  assert(Sum <= UINT32_MAX);
   return Sum;
 }
 
@@ -89,8 +104,9 @@
 BranchProbability
 MachineBranchProbabilityInfo::getEdgeProbability(MachineBasicBlock *Src,
                                                  MachineBasicBlock *Dst) const {
-  uint32_t N = getEdgeWeight(Src, Dst);
-  uint32_t D = getSumForBlock(Src);
+  uint32_t Scale = 1;
+  uint32_t D = getSumForBlock(Src, Scale);
+  uint32_t N = getEdgeWeight(Src, Dst) / Scale;
 
   return BranchProbability(N, D);
 }

Modified: llvm/trunk/test/CodeGen/X86/block-placement.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=144526&r1=144525&r2=144526&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/block-placement.ll (original)
+++ llvm/trunk/test/CodeGen/X86/block-placement.ll Mon Nov 14 02:50:16 2011
@@ -271,3 +271,54 @@
   %ptr2 = load i32** undef, align 4
   br label %loop.body3
 }
+
+define i32 @problematic_switch() {
+; This function's CFG caused overlow in the machine branch probability
+; calculation, triggering asserts. Make sure we don't crash on it.
+; CHECK: problematic_switch
+
+entry:
+  switch i32 undef, label %exit [
+    i32 879, label %bogus
+    i32 877, label %step
+    i32 876, label %step
+    i32 875, label %step
+    i32 874, label %step
+    i32 873, label %step
+    i32 872, label %step
+    i32 868, label %step
+    i32 867, label %step
+    i32 866, label %step
+    i32 861, label %step
+    i32 860, label %step
+    i32 856, label %step
+    i32 855, label %step
+    i32 854, label %step
+    i32 831, label %step
+    i32 830, label %step
+    i32 829, label %step
+    i32 828, label %step
+    i32 815, label %step
+    i32 814, label %step
+    i32 811, label %step
+    i32 806, label %step
+    i32 805, label %step
+    i32 804, label %step
+    i32 803, label %step
+    i32 802, label %step
+    i32 801, label %step
+    i32 800, label %step
+    i32 799, label %step
+    i32 798, label %step
+    i32 797, label %step
+    i32 796, label %step
+    i32 795, label %step
+  ]
+bogus:
+  unreachable
+step:
+  br label %exit
+exit:
+  %merge = phi i32 [ 3, %step ], [ 6, %entry ]
+  ret i32 %merge
+}



From chandlerc at gmail.com  Mon Nov 14 02:55:59 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 14 Nov 2011 08:55:59 -0000
Subject: [llvm-commits] [llvm] r144527 - in /llvm/trunk:
 include/llvm/CodeGen/MachineBranchProbabilityInfo.h
 lib/CodeGen/MachineBranchProbabilityInfo.cpp
Message-ID: <20111114085600.04B5C2A6C131@llvm.org>

Author: chandlerc
Date: Mon Nov 14 02:55:59 2011
New Revision: 144527

URL: http://llvm.org/viewvc/llvm-project?rev=144527&view=rev
Log:
Reuse the logic in getEdgeProbability within getHotSucc in order to
correctly handle blocks whose successor weights sum to more than
UINT32_MAX. This is slightly less efficient, but the entire thing is
already linear on the number of successors. Calling it within any hot
routine is a mistake, and indeed no one is calling it. It also
simplifies the code.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
    llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h?rev=144527&r1=144526&r2=144527&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h Mon Nov 14 02:55:59 2011
@@ -59,6 +59,7 @@
   bool isEdgeHot(MachineBasicBlock *Src, MachineBasicBlock *Dst) const;
 
   // Return a hot successor for the block BB or null if there isn't one.
+  // NB: This routine's complexity is linear on the number of successors.
   MachineBasicBlock *getHotSucc(MachineBasicBlock *MBB) const;
 
   // Return a probability as a fraction between 0 (0% probability) and

Modified: llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp?rev=144527&r1=144526&r2=144527&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp Mon Nov 14 02:55:59 2011
@@ -76,26 +76,18 @@
 
 MachineBasicBlock *
 MachineBranchProbabilityInfo::getHotSucc(MachineBasicBlock *MBB) const {
-  uint32_t Sum = 0;
   uint32_t MaxWeight = 0;
   MachineBasicBlock *MaxSucc = 0;
-
   for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
        E = MBB->succ_end(); I != E; ++I) {
-    MachineBasicBlock *Succ = *I;
-    uint32_t Weight = getEdgeWeight(MBB, Succ);
-    uint32_t PrevSum = Sum;
-
-    Sum += Weight;
-    assert(Sum > PrevSum); (void) PrevSum;
-
+    uint32_t Weight = getEdgeWeight(MBB, *I);
     if (Weight > MaxWeight) {
       MaxWeight = Weight;
-      MaxSucc = Succ;
+      MaxSucc = *I;
     }
   }
 
-  if (BranchProbability(MaxWeight, Sum) >= BranchProbability(4, 5))
+  if (getEdgeProbability(MBB, MaxSucc) >= BranchProbability(4, 5))
     return MaxSucc;
 
   return 0;



From benny.kra at googlemail.com  Mon Nov 14 03:11:50 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 14 Nov 2011 10:11:50 +0100
Subject: [llvm-commits] [llvm] r144527 - in /llvm/trunk:
 include/llvm/CodeGen/MachineBranchProbabilityInfo.h
 lib/CodeGen/MachineBranchProbabilityInfo.cpp
In-Reply-To: <20111114085600.04B5C2A6C131@llvm.org>
References: <20111114085600.04B5C2A6C131@llvm.org>
Message-ID: <6720255668642743212@unknownmsgid>

On 14.11.2011, at 10:00, Chandler Carruth <chandlerc at gmail.com> wrote:

> Author: chandlerc
> Date: Mon Nov 14 02:55:59 2011
> New Revision: 144527
>
> URL: http://llvm.org/viewvc/llvm-project?rev=144527&view=rev
> Log:
> Reuse the logic in getEdgeProbability within getHotSucc in order to
> correctly handle blocks whose successor weights sum to more than
> UINT32_MAX. This is slightly less efficient, but the entire thing is
> already linear on the number of successors. Calling it within any hot
> routine is a mistake, and indeed no one is calling it. It also
> simplifies the code.

Does this problem also exist in the non-machine BPI version of getHotSucc?

>
> Modified:
>    llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
>    llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h?rev=144527&r1=144526&r2=144527&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h Mon Nov 14 02:55:59 2011
> @@ -59,6 +59,7 @@
>   bool isEdgeHot(MachineBasicBlock *Src, MachineBasicBlock *Dst) const;
>
>   // Return a hot successor for the block BB or null if there isn't one.
> +  // NB: This routine's complexity is linear on the number of successors.
>   MachineBasicBlock *getHotSucc(MachineBasicBlock *MBB) const;
>
>   // Return a probability as a fraction between 0 (0% probability) and
>
> Modified: llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp?rev=144527&r1=144526&r2=144527&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp Mon Nov 14 02:55:59 2011
> @@ -76,26 +76,18 @@
>
> MachineBasicBlock *
> MachineBranchProbabilityInfo::getHotSucc(MachineBasicBlock *MBB) const {
> -  uint32_t Sum = 0;
>   uint32_t MaxWeight = 0;
>   MachineBasicBlock *MaxSucc = 0;
> -
>   for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
>        E = MBB->succ_end(); I != E; ++I) {
> -    MachineBasicBlock *Succ = *I;
> -    uint32_t Weight = getEdgeWeight(MBB, Succ);
> -    uint32_t PrevSum = Sum;
> -
> -    Sum += Weight;
> -    assert(Sum > PrevSum); (void) PrevSum;
> -
> +    uint32_t Weight = getEdgeWeight(MBB, *I);
>     if (Weight > MaxWeight) {
>       MaxWeight = Weight;
> -      MaxSucc = Succ;
> +      MaxSucc = *I;
>     }
>   }
>
> -  if (BranchProbability(MaxWeight, Sum) >= BranchProbability(4, 5))
> +  if (getEdgeProbability(MBB, MaxSucc) >= BranchProbability(4, 5))
>     return MaxSucc;
>
>   return 0;
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

From grosser at fim.uni-passau.de  Mon Nov 14 03:09:23 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Mon, 14 Nov 2011 09:09:23 -0000
Subject: [llvm-commits] [llvm] r144528 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111114090923.8AC612A6C131@llvm.org>

Author: grosser
Date: Mon Nov 14 03:09:23 2011
New Revision: 144528

URL: http://llvm.org/viewvc/llvm-project?rev=144528&view=rev
Log:
Add Polly to release notes

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=144528&r1=144527&r2=144528&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Nov 14 03:09:23 2011
@@ -509,6 +509,22 @@
 </div>
 
 <!--=========================================================================-->
+<h3>Polly</h3>
+
+<div>
+
+<p><a href="http://polly.grosser.es">Polly</a> is an advanced data-locality
+   optimizer and automatic parallelizer. It uses an advanced, mathematical
+   model to calculate detailed data dependency information which it uses to
+   optimize the loop structure of a program. Polly can speed up sequential code
+   by improving memory locality and consequently the cache use. Furthermore,
+   Polly is able to expose different kind of parallelism which it exploits by
+   introducing (basic) OpenMP and SIMD code. A mid-term goal of Polly is to
+   automatically create optimized GPU code.</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>Portable OpenCL (pocl)</h3>
 
 <div>



From grosser at fim.uni-passau.de  Mon Nov 14 03:09:27 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Mon, 14 Nov 2011 09:09:27 -0000
Subject: [llvm-commits] [llvm] r144529 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111114090927.1E9352A6C131@llvm.org>

Author: grosser
Date: Mon Nov 14 03:09:26 2011
New Revision: 144529

URL: http://llvm.org/viewvc/llvm-project?rev=144529&view=rev
Log:
Add clang_complete to release notes

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=144529&r1=144528&r2=144529&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Nov 14 03:09:26 2011
@@ -341,6 +341,18 @@
 </div>
 
 <!--=========================================================================-->
+<h3>clang_complete for VIM</h3>
+
+<div>
+
+<p><a href="https://github.com/Rip-Rip/clang_complete">clang_complete</a> is a
+   VIM plugin, that provides accurate C/C++ autocompletion using the clang front
+   end. The development version of clang complete, can directly use libclang
+   which can maintain a cache to speed up auto completion.</p>
+
+</div>
+
+<!--=========================================================================-->
 <h3>clReflect</h3>
 
 <div>



From chandlerc at gmail.com  Mon Nov 14 03:12:57 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 14 Nov 2011 09:12:57 -0000
Subject: [llvm-commits] [llvm] r144530 - in /llvm/trunk:
 include/llvm/CodeGen/MachineBranchProbabilityInfo.h
 lib/CodeGen/MachineBlockPlacement.cpp
Message-ID: <20111114091258.082252A6C131@llvm.org>

Author: chandlerc
Date: Mon Nov 14 03:12:57 2011
New Revision: 144530

URL: http://llvm.org/viewvc/llvm-project?rev=144530&view=rev
Log:
Under the hood, MBPI is doing a linear scan of every successor every
time it is queried to compute the probability of a single successor.
This makes computing the probability of every successor of a block in
sequence... really really slow. ;] This switches to a linear walk of the
successors rather than a quadratic one. One of several quadratic
behaviors slowing this pass down.

I'm not really thrilled with moving the sum code into the public
interface of MBPI, but I don't (at the moment) have ideas for a better
interface. My direction I'm thinking in for a better interface is to
have MBPI actually retain much more state and make *all* of these
queries cheap. That's a lot of work, and would require invasive changes.
Until then, this seems like the least bad (ie, least quadratic)
solution. Suggestions welcome.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
    llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h?rev=144530&r1=144529&r2=144530&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h Mon Nov 14 03:12:57 2011
@@ -34,11 +34,6 @@
   // weight to just "inherit" the non-zero weight of an adjacent successor.
   static const uint32_t DEFAULT_WEIGHT = 16;
 
-  // Get sum of the block successors' weights, potentially scaling them to fit
-  // within 32-bits. If scaling is required, sets Scale based on the necessary
-  // adjustment. Any edge weights used with the sum should be divided by Scale.
-  uint32_t getSumForBlock(MachineBasicBlock *MBB, uint32_t &Scale) const;
-
 public:
   static char ID;
 
@@ -55,6 +50,11 @@
   // DEFAULT_WEIGHT.
   uint32_t getEdgeWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst) const;
 
+  // Get sum of the block successors' weights, potentially scaling them to fit
+  // within 32-bits. If scaling is required, sets Scale based on the necessary
+  // adjustment. Any edge weights used with the sum should be divided by Scale.
+  uint32_t getSumForBlock(MachineBasicBlock *MBB, uint32_t &Scale) const;
+
   // A 'Hot' edge is an edge which probability is >= 80%.
   bool isEdgeHot(MachineBasicBlock *Src, MachineBasicBlock *Dst) const;
 

Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=144530&r1=144529&r2=144530&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Mon Nov 14 03:12:57 2011
@@ -334,7 +334,15 @@
   const BranchProbability HotProb(4, 5); // 80%
 
   MachineBasicBlock *BestSucc = 0;
-  BranchProbability BestProb = BranchProbability::getZero();
+  // FIXME: Due to the performance of the probability and weight routines in
+  // the MBPI analysis, we manually compute probabilities using the edge
+  // weights. This is suboptimal as it means that the somewhat subtle
+  // definition of edge weight semantics is encoded here as well. We should
+  // improve the MBPI interface to effeciently support query patterns such as
+  // this.
+  uint32_t BestWeight = 0;
+  uint32_t WeightScale = 0;
+  uint32_t SumWeight = MBPI->getSumForBlock(BB, WeightScale);
   DEBUG(dbgs() << "Attempting merge from: " << getBlockName(BB) << "\n");
   for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
                                         SE = BB->succ_end();
@@ -347,7 +355,8 @@
       continue;
     }
 
-    BranchProbability SuccProb = MBPI->getEdgeProbability(BB, *SI);
+    uint32_t SuccWeight = MBPI->getEdgeWeight(BB, *SI);
+    BranchProbability SuccProb(SuccWeight / WeightScale, SumWeight);
 
     // Only consider successors which are either "hot", or wouldn't violate
     // any CFG constraints.
@@ -360,10 +369,10 @@
                  << " (prob)"
                  << (SuccChain.LoopPredecessors != 0 ? " (CFG break)" : "")
                  << "\n");
-    if (BestSucc && BestProb >= SuccProb)
+    if (BestSucc && BestWeight >= SuccWeight)
       continue;
     BestSucc = *SI;
-    BestProb = SuccProb;
+    BestWeight = SuccWeight;
   }
   return BestSucc;
 }



From chandlerc at gmail.com  Mon Nov 14 03:32:41 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 14 Nov 2011 01:32:41 -0800
Subject: [llvm-commits] [llvm] r144527 - in /llvm/trunk:
 include/llvm/CodeGen/MachineBranchProbabilityInfo.h
 lib/CodeGen/MachineBranchProbabilityInfo.cpp
In-Reply-To: <6720255668642743212@unknownmsgid>
References: <20111114085600.04B5C2A6C131@llvm.org>
	<6720255668642743212@unknownmsgid>
Message-ID: <CAGCO0KjKv3P3OUm1au9VUV9A5e8a6BT3U9NrCgoF9-8p7_8Jxw@mail.gmail.com>

On Mon, Nov 14, 2011 at 1:11 AM, Benjamin Kramer
<benny.kra at googlemail.com>wrote:

> On 14.11.2011, at 10:00, Chandler Carruth <chandlerc at gmail.com> wrote:
>
> > Author: chandlerc
> > Date: Mon Nov 14 02:55:59 2011
> > New Revision: 144527
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=144527&view=rev
> > Log:
> > Reuse the logic in getEdgeProbability within getHotSucc in order to
> > correctly handle blocks whose successor weights sum to more than
> > UINT32_MAX. This is slightly less efficient, but the entire thing is
> > already linear on the number of successors. Calling it within any hot
> > routine is a mistake, and indeed no one is calling it. It also
> > simplifies the code.
>
> Does this problem also exist in the non-machine BPI version of getHotSucc?
>

At a fundamental level, yes. But I'm not sure we really care.

At the IR level, we *compute* the branch probabilities. If the structure of
the program is changed radically, we *recompute* them rather than updating
them in-place. The computation (in the BPI analysis pass) is careful to
eagerly scale weights down such that the sum doesn't overflow. So the
assertion (and the lack of code to handle it) seem fine there.

At the machine code level, we are updating the weights of the edges in the
few places where they are mutated. That's what causes trouble. My suspicion
is critical edge splitting, but I've not dug too deeply into it.

So essentially, I don't think the IR-level code is really subject to the
bug, despite having the same inability to cope with overflow.
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From jay.foad at gmail.com  Mon Nov 14 03:45:14 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Mon, 14 Nov 2011 09:45:14 +0000
Subject: [llvm-commits] [PATCH] PR889: devirtualize Value::printCustom
Message-ID: <CANd1uZkGs+3ba7BCFJgnBA0MDEt16SNN1um2Qjgq0RRRMkgWjg@mail.gmail.com>

http://llvm.org/bugs/show_bug.cgi?id=889

As a small step towards the goal of PR889 "Eliminate Virtual Methods
In VMCore To Make Value Objects Smaller", this patch eliminates the
virtual method Value::printCustom.

As I mentioned in the PR, this is complicated because we don't want to
introduce a library dependency from AsmWriter (which is in LLVMCore)
to PseudoSourceValue (which is in LLVMCodeGen). The approach I took is
to refactor PseudoSourceValue a bit so that the printCustom method is
trivial, and can be moved out of the .cpp file and into an inline
function in the .h file.

Dan, I've CC'ed you because it looks like you introduced both
PseudoSourceValue and the printCustom mechanism.

Tested with "make check". OK to commit?

Thanks,
Jay.
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From chandlerc at gmail.com  Mon Nov 14 03:46:33 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 14 Nov 2011 09:46:33 -0000
Subject: [llvm-commits] [llvm] r144531 -
	/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
Message-ID: <20111114094633.466D02A6C131@llvm.org>

Author: chandlerc
Date: Mon Nov 14 03:46:33 2011
New Revision: 144531

URL: http://llvm.org/viewvc/llvm-project?rev=144531&view=rev
Log:
Begin chipping away at one of the biggest quadratic-ish behaviors in
this pass. We're leaving already merged blocks on the worklist, and
scanning them again and again only to determine each time through that
indeed they aren't viable. We can instead remove them once we're going
to have to scan the worklist. This is the easy way to implement removing
them. If this remains on the profile (as I somewhat suspect it will), we
can get a lot more clever here, as the worklist's order is essentially
irrelevant. We can use swapping and fold the two loops to reduce
overhead even when there are many blocks on the worklist but only a few
of them are removed.

Modified:
    llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp

Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=144531&r1=144530&r2=144531&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Mon Nov 14 03:46:33 2011
@@ -377,6 +377,23 @@
   return BestSucc;
 }
 
+namespace {
+/// \brief Predicate struct to detect blocks already placed.
+class IsBlockPlaced {
+  const BlockChain &PlacedChain;
+  const BlockToChainMapType &BlockToChain;
+
+public:
+  IsBlockPlaced(const BlockChain &PlacedChain,
+                const BlockToChainMapType &BlockToChain)
+      : PlacedChain(PlacedChain), BlockToChain(BlockToChain) {}
+
+  bool operator()(MachineBasicBlock *BB) const {
+    return BlockToChain.lookup(BB) == &PlacedChain;
+  }
+};
+}
+
 /// \brief Select the best block from a worklist.
 ///
 /// This looks through the provided worklist as a list of candidate basic
@@ -390,13 +407,20 @@
 MachineBasicBlock *MachineBlockPlacement::selectBestCandidateBlock(
     BlockChain &Chain, SmallVectorImpl<MachineBasicBlock *> &WorkList,
     const BlockFilterSet *BlockFilter) {
+  // Once we need to walk the worklist looking for a candidate, cleanup the
+  // worklist of already placed entries.
+  // FIXME: If this shows up on profiles, it could be folded (at the cost of
+  // some code complexity) into the loop below.
+  WorkList.erase(std::remove_if(WorkList.begin(), WorkList.end(),
+                                IsBlockPlaced(Chain, BlockToChain)),
+                 WorkList.end());
+
   MachineBasicBlock *BestBlock = 0;
   BlockFrequency BestFreq;
   for (SmallVectorImpl<MachineBasicBlock *>::iterator WBI = WorkList.begin(),
                                                       WBE = WorkList.end();
        WBI != WBE; ++WBI) {
-    if (BlockFilter && !BlockFilter->count(*WBI))
-      continue;
+    assert(!BlockFilter || BlockFilter->count(*WBI));
     BlockChain &SuccChain = *BlockToChain[*WBI];
     if (&SuccChain == &Chain) {
       DEBUG(dbgs() << "    " << getBlockName(*WBI)



From chandlerc at google.com  Mon Nov 14 03:53:37 2011
From: chandlerc at google.com (Chandler Carruth)
Date: Mon, 14 Nov 2011 01:53:37 -0800
Subject: [llvm-commits] [PATCH] PR889: devirtualize Value::printCustom
In-Reply-To: <CANd1uZkGs+3ba7BCFJgnBA0MDEt16SNN1um2Qjgq0RRRMkgWjg@mail.gmail.com>
References: <CANd1uZkGs+3ba7BCFJgnBA0MDEt16SNN1um2Qjgq0RRRMkgWjg@mail.gmail.com>
Message-ID: <CAGCO0Kgagyg7=aD8kStnPSfiuxUnRskKM1BfOkNiQ=kB8x8uiw@mail.gmail.com>

On Mon, Nov 14, 2011 at 1:45 AM, Jay Foad <jay.foad at gmail.com> wrote:

> http://llvm.org/bugs/show_bug.cgi?id=889
>
> As a small step towards the goal of PR889 "Eliminate Virtual Methods
> In VMCore To Make Value Objects Smaller", this patch eliminates the
> virtual method Value::printCustom.
>
> As I mentioned in the PR, this is complicated because we don't want to
> introduce a library dependency from AsmWriter (which is in LLVMCore)
> to PseudoSourceValue (which is in LLVMCodeGen). The approach I took is
> to refactor PseudoSourceValue a bit so that the printCustom method is
> trivial, and can be moved out of the .cpp file and into an inline
> function in the .h file.
>

I don't think this is an acceptable way to approach this. You're still
adding a dependency on CodeGen to VMCore. You've just wrapped it up into a
header file dependency instead of a link-time dependency. I think this is
likely to make our already troublesome layering story significantly worse.
VMCore should not know of or need anything CodeGen. If this routine does,
there is some deeper design issue that needs to be resolved.
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From chandlerc at gmail.com  Mon Nov 14 04:55:54 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 14 Nov 2011 10:55:54 -0000
Subject: [llvm-commits] [llvm] r144532 -
	/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
Message-ID: <20111114105554.6661C2A6C131@llvm.org>

Author: chandlerc
Date: Mon Nov 14 04:55:53 2011
New Revision: 144532

URL: http://llvm.org/viewvc/llvm-project?rev=144532&view=rev
Log:
Remove an over-eager assert that was firing on one of the ARM regression
tests when I forcibly enabled block placement.

It is apparantly possible for an unanalyzable block to fallthrough to
a non-loop block. I don't actually beleive this is correct, I believe
that 'canFallThrough' is returning true needlessly for the code
construct, and I've left a bit of a FIXME on the verification code to
try to track down why this is coming up.

Anyways, removing the assert doesn't degrade the correctness of the algorithm.

Modified:
    llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp

Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=144532&r1=144531&r2=144532&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Mon Nov 14 04:55:53 2011
@@ -492,9 +492,9 @@
     if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond) && BB->canFallThrough()) {
       MachineFunction::iterator I(BB), NextI(llvm::next(I));
       // Ensure that the layout successor is a viable block, as we know that
-      // fallthrough is a possibility.
+      // fallthrough is a possibility. Note that this may not be a valid block
+      // in the loop, but we allow that to cope with degenerate situations.
       assert(NextI != BB->getParent()->end());
-      assert(!BlockFilter || BlockFilter->count(NextI));
       BestSucc = NextI;
     }
 
@@ -594,7 +594,10 @@
     for (BlockChain::iterator BCI = LoopChain.begin(), BCE = LoopChain.end();
          BCI != BCE; ++BCI)
       if (!LoopBlockSet.erase(*BCI)) {
-        BadLoop = true;
+        // We don't mark the loop as bad here because there are real situations
+        // where this can occur. For example, with an unanalyzable fallthrough
+        // from a loop block to a non-loop block.
+        // FIXME: Such constructs shouldn't exist. Track them down and fix them.
         dbgs() << "Loop chain contains a block not contained by the loop!\n"
                << "  Loop header:  " << getBlockName(*L.block_begin()) << "\n"
                << "  Chain header: " << getBlockName(*LoopChain.begin()) << "\n"



From chandlerc at gmail.com  Mon Nov 14 04:57:24 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Mon, 14 Nov 2011 10:57:24 -0000
Subject: [llvm-commits] [llvm] r144533 -
	/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
Message-ID: <20111114105724.1F5ED2A6C131@llvm.org>

Author: chandlerc
Date: Mon Nov 14 04:57:23 2011
New Revision: 144533

URL: http://llvm.org/viewvc/llvm-project?rev=144533&view=rev
Log:
It helps to deallocate memory as well as allocate it. =] This actually
cleans up all the chains allocated during the processing of each
function so that for very large inputs we don't just grow memory usage
without bound.

Modified:
    llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp

Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=144533&r1=144532&r2=144533&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Mon Nov 14 04:57:23 2011
@@ -766,6 +766,7 @@
   AlignLoops(F);
 
   BlockToChain.clear();
+  ChainAllocator.DestroyAll();
 
   // We always return true as we have no way to track whether the final order
   // differs from the original order.



From jay.foad at gmail.com  Mon Nov 14 10:07:46 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Mon, 14 Nov 2011 16:07:46 +0000
Subject: [llvm-commits] [PATCH] PR889: devirtualize Value::printCustom
In-Reply-To: <CAGCO0Kgagyg7=aD8kStnPSfiuxUnRskKM1BfOkNiQ=kB8x8uiw@mail.gmail.com>
References: <CANd1uZkGs+3ba7BCFJgnBA0MDEt16SNN1um2Qjgq0RRRMkgWjg@mail.gmail.com>
	<CAGCO0Kgagyg7=aD8kStnPSfiuxUnRskKM1BfOkNiQ=kB8x8uiw@mail.gmail.com>
Message-ID: <CANd1uZmO4JhwQGZaXFcX2e2Z+F9vfrbSqP9L0i3op_zVkdS2tg@mail.gmail.com>

On 14 November 2011 09:53, Chandler Carruth <chandlerc at google.com> wrote:
> I don't think this is an acceptable way to approach this. You're still
> adding a dependency on CodeGen to VMCore. You've just wrapped it up into a
> header file dependency instead of a link-time dependency. I think this is
> likely to make our already troublesome layering story significantly worse.
> VMCore should not know of or need anything CodeGen.

VMCore defines a class hierarchy rooted at Value. CodeGen wants to
extend that hierarchy with a new subclass, PseudoSourceValue. All
these classes of value want to be able print themselves (for use in
debugging dumps if nothing else). If this is to be done without VMCore
knowing anything about CodeGen then a virtual method seems like a very
good way of doing it.

The point of the PR is that we want to do away with virtual methods to
save space, because we won't need a vtable pointer in each object.
Instead we can do manual dispatch on the object's ValueID. But I can't
think of a good way for independent libraries (like CodeGen) to hook
into this dispatch mechanism. Maybe they could register themselves
with VMCore, saying "I want to extend the Value hierarchy with a new
class with this ID"; but that doesn't sound like it would be very
clean or efficient.

So unless anyone has any bright ideas, it seems to me that this PR is
fundamentally at odds with LLVM's "already troublesome layering
story".

Jay.

From rafael.espindola at gmail.com  Mon Nov 14 10:55:02 2011
From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=)
Date: Mon, 14 Nov 2011 11:55:02 -0500
Subject: [llvm-commits] pr11367
Message-ID: <CAG3jReJHN2jo=Mv97jR9Ep2jywLTbMPyvF03y6Q_ffU6m0S8wA@mail.gmail.com>

I was thinking a bit about pr11367. The most direct way to solve it is
keeping the list open until the linker is done adding files, but maybe
there is a better way.

What was the intended use case of lazy linking? Speeding up LTO? If
so, it might be better to drop these function at the end of
-std-compile-opts and change back the linker to keeping everything.
The advantages would be

* llvm-link is again just a IL version of cat
* LTO is even faster, as we avoid writing to disk the functions that
we currently drop when reading in.

It is true that we would drop more available_externally functions.
Right now if we drop them or not depends on the file order.

Both the current solution and the dropping them in -std-compile-opts
could also introduce a regression compared to the old way where an
available_externally function in one file would be available for use
in any other file. I don't think this would be a problem in practise.
Any translation unit that uses an inline function is likely to see its
definition.

Cheers,
Rafael

From daniel at zuster.org  Mon Nov 14 11:17:46 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 14 Nov 2011 17:17:46 -0000
Subject: [llvm-commits] [llvm] r144535 - /llvm/trunk/Makefile.rules
Message-ID: <20111114171746.29EC82A6C131@llvm.org>

Author: ddunbar
Date: Mon Nov 14 11:17:45 2011
New Revision: 144535

URL: http://llvm.org/viewvc/llvm-project?rev=144535&view=rev
Log:
build/Make: Switch over to using llvm-config-2 for dependencies one more (hopefully last) time, now that it also builds as a build tool.

Modified:
    llvm/trunk/Makefile.rules

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=144535&r1=144534&r2=144535&view=diff
==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Mon Nov 14 11:17:45 2011
@@ -527,7 +527,11 @@
     LLVM_TBLGEN   := $(LLVMToolDir)/llvm-tblgen$(EXEEXT)
   endif
 endif
-LLVM_CONFIG := $(LLVMToolDir)/llvm-config
+ifeq ($(LLVM_CROSS_COMPILING),1)
+  LLVM_CONFIG := $(BuildLLVMToolDir)/llvm-config-2$(BUILD_EXEEXT)
+else
+  LLVM_CONFIG := $(LLVMToolDir)/llvm-config-2$(EXEEXT)
+endif
 ifndef LLVMLD
 LLVMLD    := $(LLVMToolDir)/llvm-ld$(EXEEXT)
 endif



From benny.kra at googlemail.com  Mon Nov 14 11:22:45 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 14 Nov 2011 17:22:45 -0000
Subject: [llvm-commits] [llvm] r144536 - in /llvm/trunk:
 include/llvm/Transforms/Utils/SSAUpdater.h
 include/llvm/Transforms/Utils/SSAUpdaterImpl.h
 include/llvm/Transforms/Utils/SimplifyIndVar.h
 lib/Transforms/Utils/SSAUpdater.cpp
Message-ID: <20111114172245.72CB82A6C131@llvm.org>

Author: d0k
Date: Mon Nov 14 11:22:45 2011
New Revision: 144536

URL: http://llvm.org/viewvc/llvm-project?rev=144536&view=rev
Log:
Make headers standalone, move a virtual method out of line.

Modified:
    llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h
    llvm/trunk/include/llvm/Transforms/Utils/SSAUpdaterImpl.h
    llvm/trunk/include/llvm/Transforms/Utils/SimplifyIndVar.h
    llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp

Modified: llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h?rev=144536&r1=144535&r2=144536&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h (original)
+++ llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h Mon Nov 14 11:22:45 2011
@@ -14,16 +14,18 @@
 #ifndef LLVM_TRANSFORMS_UTILS_SSAUPDATER_H
 #define LLVM_TRANSFORMS_UTILS_SSAUPDATER_H
 
+#include "llvm/ADT/StringRef.h"
+
 namespace llvm {
-  class Value;
   class BasicBlock;
-  class Use;
-  class PHINode;
+  class Instruction;
+  class LoadInst;
   template<typename T> class SmallVectorImpl;
   template<typename T> class SSAUpdaterTraits;
-  class DbgDeclareInst;
-  class DIBuilder;
-  class BumpPtrAllocator;
+  class PHINode;
+  class Type;
+  class Use;
+  class Value;
 
 /// SSAUpdater - This class updates SSA form for a set of values defined in
 /// multiple blocks.  This is used when code duplication or another unstructured
@@ -137,12 +139,7 @@
   /// passed into the run method).  Clients should implement this with a more
   /// efficient version if possible.
   virtual bool isInstInList(Instruction *I,
-                            const SmallVectorImpl<Instruction*> &Insts) const {
-    for (unsigned i = 0, e = Insts.size(); i != e; ++i)
-      if (Insts[i] == I)
-        return true;
-    return false;
-  }
+                            const SmallVectorImpl<Instruction*> &Insts) const;
   
   /// doExtraRewritesBeforeFinalDeletion - This hook is invoked after all the
   /// stores are found and inserted as available values, but 

Modified: llvm/trunk/include/llvm/Transforms/Utils/SSAUpdaterImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/SSAUpdaterImpl.h?rev=144536&r1=144535&r2=144536&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Utils/SSAUpdaterImpl.h (original)
+++ llvm/trunk/include/llvm/Transforms/Utils/SSAUpdaterImpl.h Mon Nov 14 11:22:45 2011
@@ -15,8 +15,16 @@
 #ifndef LLVM_TRANSFORMS_UTILS_SSAUPDATERIMPL_H
 #define LLVM_TRANSFORMS_UTILS_SSAUPDATERIMPL_H
 
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/Allocator.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ValueHandle.h"
+
 namespace llvm {
 
+class CastInst;
+class PHINode;
 template<typename T> class SSAUpdaterTraits;
 
 template<typename UpdaterT>

Modified: llvm/trunk/include/llvm/Transforms/Utils/SimplifyIndVar.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/SimplifyIndVar.h?rev=144536&r1=144535&r2=144536&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Utils/SimplifyIndVar.h (original)
+++ llvm/trunk/include/llvm/Transforms/Utils/SimplifyIndVar.h Mon Nov 14 11:22:45 2011
@@ -17,17 +17,18 @@
 #define LLVM_TRANSFORMS_UTILS_SIMPLIFYINDVAR_H
 
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ValueHandle.h"
 
 namespace llvm {
 
 extern cl::opt<bool> DisableIVRewrite;
 
+class CastInst;
+class IVUsers;
 class Loop;
-class LoopInfo;
-class DominatorTree;
-class ScalarEvolution;
 class LPPassManager;
-class IVUsers;
+class PHINode;
+class ScalarEvolution;
 
 /// Interface for visiting interesting IV users that are recognized but not
 /// simplified by this utility.

Modified: llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp?rev=144536&r1=144535&r2=144536&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp Mon Nov 14 11:22:45 2011
@@ -518,3 +518,10 @@
     User->eraseFromParent();
   }
 }
+
+bool
+LoadAndStorePromoter::isInstInList(Instruction *I,
+                                   const SmallVectorImpl<Instruction*> &Insts)
+                                   const {
+  return std::find(Insts.begin(), Insts.end(), I) != Insts.end();
+}



From benny.kra at googlemail.com  Mon Nov 14 11:45:03 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 14 Nov 2011 17:45:03 -0000
Subject: [llvm-commits] [llvm] r144537 - in /llvm/trunk/include/llvm:
 Analysis/InlineCost.h Assembly/AssemblyAnnotationWriter.h
 CodeGen/FastISel.h CodeGen/MachineBlockFrequencyInfo.h
 CodeGen/MachineMemOperand.h MC/MCAsmLayout.h
Message-ID: <20111114174503.BB6102A6C131@llvm.org>

Author: d0k
Date: Mon Nov 14 11:45:03 2011
New Revision: 144537

URL: http://llvm.org/viewvc/llvm-project?rev=144537&view=rev
Log:
Make headers standalone.

Modified:
    llvm/trunk/include/llvm/Analysis/InlineCost.h
    llvm/trunk/include/llvm/Assembly/AssemblyAnnotationWriter.h
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h
    llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
    llvm/trunk/include/llvm/MC/MCAsmLayout.h

Modified: llvm/trunk/include/llvm/Analysis/InlineCost.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/InlineCost.h?rev=144537&r1=144536&r2=144537&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/InlineCost.h (original)
+++ llvm/trunk/include/llvm/Analysis/InlineCost.h Mon Nov 14 11:45:03 2011
@@ -14,18 +14,16 @@
 #ifndef LLVM_ANALYSIS_INLINECOST_H
 #define LLVM_ANALYSIS_INLINECOST_H
 
-#include <cassert>
-#include <climits>
-#include <vector>
+#include "llvm/Function.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/ValueMap.h"
 #include "llvm/Analysis/CodeMetrics.h"
+#include <cassert>
+#include <climits>
+#include <vector>
 
 namespace llvm {
 
-  class Value;
-  class Function;
-  class BasicBlock;
   class CallSite;
   template<class PtrType, unsigned SmallSize>
   class SmallPtrSet;

Modified: llvm/trunk/include/llvm/Assembly/AssemblyAnnotationWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Assembly/AssemblyAnnotationWriter.h?rev=144537&r1=144536&r2=144537&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Assembly/AssemblyAnnotationWriter.h (original)
+++ llvm/trunk/include/llvm/Assembly/AssemblyAnnotationWriter.h Mon Nov 14 11:45:03 2011
@@ -22,6 +22,7 @@
 class Function;
 class BasicBlock;
 class Instruction;
+class Value;
 class raw_ostream;
 class formatted_raw_ostream;
 

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=144537&r1=144536&r2=144537&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Mon Nov 14 11:45:03 2011
@@ -21,9 +21,11 @@
 namespace llvm {
 
 class AllocaInst;
+class Constant;
 class ConstantFP;
 class FunctionLoweringInfo;
 class Instruction;
+class LoadInst;
 class MachineBasicBlock;
 class MachineConstantPool;
 class MachineFunction;
@@ -36,7 +38,8 @@
 class TargetMachine;
 class TargetRegisterClass;
 class TargetRegisterInfo;
-class LoadInst;
+class User;
+class Value;
 
 /// FastISel - This is a fast-path instruction selection class that
 /// generates poor code and doesn't support illegal types or non-trivial

Modified: llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h?rev=144537&r1=144536&r2=144537&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h Mon Nov 14 11:45:03 2011
@@ -20,6 +20,7 @@
 
 namespace llvm {
 
+class MachineBasicBlock;
 class MachineBranchProbabilityInfo;
 template<class BlockT, class FunctionT, class BranchProbInfoT>
 class BlockFrequencyImpl;
@@ -28,7 +29,8 @@
 /// machine basic block frequencies.
 class MachineBlockFrequencyInfo : public MachineFunctionPass {
 
-  BlockFrequencyImpl<MachineBasicBlock, MachineFunction, MachineBranchProbabilityInfo> *MBFI;
+  BlockFrequencyImpl<MachineBasicBlock, MachineFunction,
+                     MachineBranchProbabilityInfo> *MBFI;
 
 public:
   static char ID;

Modified: llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h?rev=144537&r1=144536&r2=144537&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h Mon Nov 14 11:45:03 2011
@@ -22,6 +22,7 @@
 
 class Value;
 class FoldingSetNodeID;
+class MDNode;
 class raw_ostream;
 
 /// MachinePointerInfo - This class contains a discriminated union of

Modified: llvm/trunk/include/llvm/MC/MCAsmLayout.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmLayout.h?rev=144537&r1=144536&r2=144537&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmLayout.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmLayout.h Mon Nov 14 11:45:03 2011
@@ -10,6 +10,7 @@
 #ifndef LLVM_MC_MCASMLAYOUT_H
 #define LLVM_MC_MCASMLAYOUT_H
 
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
 
 namespace llvm {



From grosbach at apple.com  Mon Nov 14 11:52:47 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 14 Nov 2011 17:52:47 -0000
Subject: [llvm-commits] [llvm] r144538 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20111114175247.AC6422A6C131@llvm.org>

Author: grosbach
Date: Mon Nov 14 11:52:47 2011
New Revision: 144538

URL: http://llvm.org/viewvc/llvm-project?rev=144538&view=rev
Log:
Tidy up. 80 column.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144538&r1=144537&r2=144538&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Nov 14 11:52:47 2011
@@ -714,7 +714,7 @@
   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
   bool isPostIdxReg() const {
-    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
+    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
   }
   bool isMemNoOffset(bool alignOK = false) const {
     if (!isMemory())
@@ -1101,7 +1101,8 @@
 
   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 3 && "Invalid number of operands!");
-    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
+    assert(isRegShiftedReg() &&
+           "addRegShiftedRegOperands() on non RegShiftedReg!");
     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
     Inst.addOperand(MCOperand::CreateImm(
@@ -1110,7 +1111,8 @@
 
   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
-    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
+    assert(isRegShiftedImm() &&
+           "addRegShiftedImmOperands() on non RegShiftedImm!");
     Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
     Inst.addOperand(MCOperand::CreateImm(
       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
@@ -1426,8 +1428,9 @@
 
   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 3 && "Invalid number of operands!");
-    unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
-                                     Memory.ShiftImm, Memory.ShiftType);
+    unsigned Val =
+      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
+                        Memory.ShiftImm, Memory.ShiftType);
     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
     Inst.addOperand(MCOperand::CreateImm(Val));



From stoklund at 2pi.dk  Mon Nov 14 12:03:05 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 14 Nov 2011 18:03:05 -0000
Subject: [llvm-commits] [llvm] r144542 -
	/llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll
Message-ID: <20111114180306.05F0F2A6C131@llvm.org>

Author: stoklund
Date: Mon Nov 14 12:03:05 2011
New Revision: 144542

URL: http://llvm.org/viewvc/llvm-project?rev=144542&view=rev
Log:
Delete stale comment.

Modified:
    llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll

Modified: llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll?rev=144542&r1=144541&r2=144542&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/memcpy-inline.ll Mon Nov 14 12:03:05 2011
@@ -1,6 +1,5 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-post-ra | FileCheck %s
 
-; The ARM magic hinting works best with linear scan.
 ; CHECK: ldrd
 ; CHECK: strd
 ; CHECK: ldrb



From tonic at nondot.org  Mon Nov 14 12:21:16 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Mon, 14 Nov 2011 10:21:16 -0800
Subject: [llvm-commits] pr11367
In-Reply-To: <CAG3jReJHN2jo=Mv97jR9Ep2jywLTbMPyvF03y6Q_ffU6m0S8wA@mail.gmail.com>
References: <CAG3jReJHN2jo=Mv97jR9Ep2jywLTbMPyvF03y6Q_ffU6m0S8wA@mail.gmail.com>
Message-ID: <B1289D79-A496-43C2-A644-564033AF3EF2@nondot.org>


On Nov 14, 2011, at 8:55 AM, Rafael Esp?ndola wrote:

> I was thinking a bit about pr11367. The most direct way to solve it is
> keeping the list open until the linker is done adding files, but maybe
> there is a better way.
> 
> What was the intended use case of lazy linking? Speeding up LTO?

I implemented lazy linking for an outside project where I want to link with a bc library and only link in the functions that are used.  We use the LinkModules() API directly. I talked to Chris about this and he wanted LTO to take advantage of this as well, so it seemed like a win for both.

> If
> so, it might be better to drop these function at the end of
> -std-compile-opts and change back the linker to keeping everything.
> The advantages would be

I really don't want to run the optimizer on everything when the linker can easily do this.

> 
> * llvm-link is again just a IL version of cat

I'm sure this can be up for debate as what llvm-link is really supposed to do. I don't want to remove this functionality from the API. If its decided that llvm-link is really catting IR files together, then its better to make an option to turn it off (for llvm-link if it chooses) and have it on by default.

-Tanya

> * LTO is even faster, as we avoid writing to disk the functions that
> we currently drop when reading in.
> 
> It is true that we would drop more available_externally functions.
> Right now if we drop them or not depends on the file order.
> 
> Both the current solution and the dropping them in -std-compile-opts
> could also introduce a regression compared to the old way where an
> available_externally function in one file would be available for use
> in any other file. I don't think this would be a problem in practise.
> Any translation unit that uses an inline function is likely to see its
> definition.
> 
> Cheers,
> Rafael



From bob.wilson at apple.com  Mon Nov 14 12:21:07 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 14 Nov 2011 18:21:07 -0000
Subject: [llvm-commits] [llvm] r144543 - /llvm/trunk/lib/MC/MCDwarf.cpp
Message-ID: <20111114182107.C69A62A6C131@llvm.org>

Author: bwilson
Date: Mon Nov 14 12:21:07 2011
New Revision: 144543

URL: http://llvm.org/viewvc/llvm-project?rev=144543&view=rev
Log:
Disable generation of compact unwind encodings.  <rdar://problem/10441578>

This still seems to be causing some failures.  It needs more testing before
it gets enabled again.

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=144543&r1=144542&r2=144543&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Mon Nov 14 12:21:07 2011
@@ -1011,7 +1011,8 @@
   // Emit the compact unwind info if available.
   // FIXME: This emits both the compact unwind and the old CIE/FDE
   //        information. Only one of those is needed.
-  if (IsEH && MOFI->getCompactUnwindSection())
+  // FIXME: Disable. This seems to still be causing failures.
+  if (false && IsEH && MOFI->getCompactUnwindSection())
     for (unsigned i = 0, n = Streamer.getNumFrameInfos(); i < n; ++i) {
       const MCDwarfFrameInfo &Frame = Streamer.getFrameInfo(i);
       if (Frame.CompactUnwindEncoding)



From clattner at apple.com  Mon Nov 14 12:38:28 2011
From: clattner at apple.com (Chris Lattner)
Date: Mon, 14 Nov 2011 10:38:28 -0800
Subject: [llvm-commits] [PATCH] PR889: devirtualize Value::printCustom
In-Reply-To: <CANd1uZmO4JhwQGZaXFcX2e2Z+F9vfrbSqP9L0i3op_zVkdS2tg@mail.gmail.com>
References: <CANd1uZkGs+3ba7BCFJgnBA0MDEt16SNN1um2Qjgq0RRRMkgWjg@mail.gmail.com>
	<CAGCO0Kgagyg7=aD8kStnPSfiuxUnRskKM1BfOkNiQ=kB8x8uiw@mail.gmail.com>
	<CANd1uZmO4JhwQGZaXFcX2e2Z+F9vfrbSqP9L0i3op_zVkdS2tg@mail.gmail.com>
Message-ID: <28388F1A-D44C-4218-A157-A177E2D114FB@apple.com>


On Nov 14, 2011, at 8:07 AM, Jay Foad wrote:

> On 14 November 2011 09:53, Chandler Carruth <chandlerc at google.com> wrote:
>> I don't think this is an acceptable way to approach this. You're still
>> adding a dependency on CodeGen to VMCore. You've just wrapped it up into a
>> header file dependency instead of a link-time dependency. I think this is
>> likely to make our already troublesome layering story significantly worse.
>> VMCore should not know of or need anything CodeGen.
> 
> VMCore defines a class hierarchy rooted at Value. CodeGen wants to
> extend that hierarchy with a new subclass, PseudoSourceValue. All
> these classes of value want to be able print themselves (for use in
> debugging dumps if nothing else). If this is to be done without VMCore
> knowing anything about CodeGen then a virtual method seems like a very
> good way of doing it.
> 
> The point of the PR is that we want to do away with virtual methods to
> save space, because we won't need a vtable pointer in each object.
> Instead we can do manual dispatch on the object's ValueID. But I can't
> think of a good way for independent libraries (like CodeGen) to hook
> into this dispatch mechanism. Maybe they could register themselves
> with VMCore, saying "I want to extend the Value hierarchy with a new
> class with this ID"; but that doesn't sound like it would be very
> clean or efficient.
> 
> So unless anyone has any bright ideas, it seems to me that this PR is
> fundamentally at odds with LLVM's "already troublesome layering
> story".

The "right" way to fix this is to eliminate PseudoSourceValue, which has always been a disgusting hack.  Places in codegen that can uses PseudoSourceValue (e.g. the SDLoadNode and memoperands) should use a discriminated union of "Value* and SomeMachineLocationType".  PseudoSourceValue never should have happened in the first place.

-Chris


From clattner at apple.com  Mon Nov 14 12:40:42 2011
From: clattner at apple.com (Chris Lattner)
Date: Mon, 14 Nov 2011 10:40:42 -0800
Subject: [llvm-commits] pr11367
In-Reply-To: <B1289D79-A496-43C2-A644-564033AF3EF2@nondot.org>
References: <CAG3jReJHN2jo=Mv97jR9Ep2jywLTbMPyvF03y6Q_ffU6m0S8wA@mail.gmail.com>
	<B1289D79-A496-43C2-A644-564033AF3EF2@nondot.org>
Message-ID: <AEE31309-99DD-47C3-912A-2674D658E6A7@apple.com>

MHO is that mainline is behaving correctly.  We don't want LTO or llvm-link to keep all bitcode files around in memory to support a theoretical use case.

-Chris

On Nov 14, 2011, at 10:21 AM, Tanya Lattner wrote:

> 
> On Nov 14, 2011, at 8:55 AM, Rafael Esp?ndola wrote:
> 
>> I was thinking a bit about pr11367. The most direct way to solve it is
>> keeping the list open until the linker is done adding files, but maybe
>> there is a better way.
>> 
>> What was the intended use case of lazy linking? Speeding up LTO?
> 
> I implemented lazy linking for an outside project where I want to link with a bc library and only link in the functions that are used.  We use the LinkModules() API directly. I talked to Chris about this and he wanted LTO to take advantage of this as well, so it seemed like a win for both.
> 
>> If
>> so, it might be better to drop these function at the end of
>> -std-compile-opts and change back the linker to keeping everything.
>> The advantages would be
> 
> I really don't want to run the optimizer on everything when the linker can easily do this.
> 
>> 
>> * llvm-link is again just a IL version of cat
> 
> I'm sure this can be up for debate as what llvm-link is really supposed to do. I don't want to remove this functionality from the API. If its decided that llvm-link is really catting IR files together, then its better to make an option to turn it off (for llvm-link if it chooses) and have it on by default.
> 
> -Tanya
> 
>> * LTO is even faster, as we avoid writing to disk the functions that
>> we currently drop when reading in.
>> 
>> It is true that we would drop more available_externally functions.
>> Right now if we drop them or not depends on the file order.
>> 
>> Both the current solution and the dropping them in -std-compile-opts
>> could also introduce a regression compared to the old way where an
>> available_externally function in one file would be available for use
>> in any other file. I don't think this would be a problem in practise.
>> Any translation unit that uses an inline function is likely to see its
>> definition.
>> 
>> Cheers,
>> Rafael
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From stoklund at 2pi.dk  Mon Nov 14 12:45:39 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 14 Nov 2011 18:45:39 -0000
Subject: [llvm-commits] [llvm] r144547 - in /llvm/trunk:
 lib/CodeGen/LiveIntervalAnalysis.cpp
 test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
Message-ID: <20111114184539.2FD1D2A6C131@llvm.org>

Author: stoklund
Date: Mon Nov 14 12:45:38 2011
New Revision: 144547

URL: http://llvm.org/viewvc/llvm-project?rev=144547&view=rev
Log:
Fix early-clobber handling in shrinkToUses.

I broke this in r144515, it affected most ARM testers.

<rdar://problem/10441389>

Added:
    llvm/trunk/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=144547&r1=144546&r2=144547&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Mon Nov 14 12:45:38 2011
@@ -659,7 +659,9 @@
     if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
       continue;
     SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
-    VNInfo *VNI = li->getVNInfoAt(Idx.getBaseIndex());
+    // Note: This intentionally picks up the wrong VNI in case of an EC redef.
+    // See below.
+    VNInfo *VNI = li->getVNInfoBefore(Idx);
     if (!VNI) {
       // This shouldn't happen: readsVirtualRegister returns true, but there is
       // no live value. It is likely caused by a target getting <undef> flags
@@ -669,10 +671,11 @@
                     << *li << '\n');
       continue;
     }
-    if (VNI->def == Idx.getRegSlot(true)) {
-      // Special case: An early-clobber tied operand reads and writes the
-      // register one slot early.
-      Idx = Idx.getRegSlot(true);
+    // Special case: An early-clobber tied operand reads and writes the
+    // register one slot early.  The getVNInfoBefore call above would have
+    // picked up the value defined by UseMI.  Adjust the kill slot and value.
+    if (SlotIndex::isSameInstr(VNI->def, Idx)) {
+      Idx = VNI->def;
       VNI = li->getVNInfoBefore(Idx);
       assert(VNI && "Early-clobber tied value not available");
     }
@@ -687,13 +690,6 @@
     if (VNI->isUnused())
       continue;
     NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
-
-    // A use tied to an early-clobber def ends at the load slot and isn't caught
-    // above. Catch it here instead. This probably only ever happens for inline
-    // assembly.
-    if (VNI->def.isEarlyClobber())
-      if (VNInfo *UVNI = li->getVNInfoBefore(VNI->def))
-        WorkList.push_back(std::make_pair(VNI->def, UVNI));
   }
 
   // Keep track of the PHIs that are in use.

Added: llvm/trunk/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll?rev=144547&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll Mon Nov 14 12:45:38 2011
@@ -0,0 +1,62 @@
+; RUN: llc < %s -mcpu=cortex-a8 -verify-regalloc
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
+target triple = "thumbv7-apple-ios"
+
+; This test calls shrinkToUses with an early-clobber redefined live range during
+; spilling.
+;
+;   Shrink: %vreg47,1.158257e-02 = [384r,400e:0)[400e,420r:1)  0 at 384r 1 at 400e
+;
+; The early-clobber instruction is an str:
+;
+;   %vreg12<earlyclobber,def> = t2STR_PRE %vreg6, %vreg12, 32, pred:14, pred:%noreg
+;
+; This tests that shrinkToUses handles the EC redef correctly.
+
+%struct.Transform_Struct.0.11.12.17.43.46.56.58.60 = type { [4 x [4 x double]] }
+
+define void @Compute_Axis_Rotation_Transform(%struct.Transform_Struct.0.11.12.17.43.46.56.58.60* nocapture %transform, double* nocapture %V1, double %angle) nounwind {
+entry:
+  store double 1.000000e+00, double* null, align 4
+  %arrayidx5.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 1
+  store double 0.000000e+00, double* %arrayidx5.1.i, align 4
+  %arrayidx5.2.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 0, i32 2
+  store double 0.000000e+00, double* %arrayidx5.2.i, align 4
+  %arrayidx5.114.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 0
+  store double 0.000000e+00, double* %arrayidx5.114.i, align 4
+  %arrayidx5.1.1.i = getelementptr inbounds %struct.Transform_Struct.0.11.12.17.43.46.56.58.60* %transform, i32 0, i32 0, i32 1, i32 1
+  store double 1.000000e+00, double* %arrayidx5.1.1.i, align 4
+  store double 0.000000e+00, double* null, align 4
+  store double 1.000000e+00, double* null, align 4
+  store double 0.000000e+00, double* null, align 4
+  %call = tail call double @cos(double %angle) nounwind readnone
+  %call1 = tail call double @sin(double %angle) nounwind readnone
+  %0 = load double* %V1, align 4
+  %arrayidx2 = getelementptr inbounds double* %V1, i32 1
+  %1 = load double* %arrayidx2, align 4
+  %mul = fmul double %0, %1
+  %sub = fsub double 1.000000e+00, %call
+  %mul3 = fmul double %mul, %sub
+  %2 = load double* undef, align 4
+  %mul5 = fmul double %2, %call1
+  %add = fadd double %mul3, %mul5
+  store double %add, double* %arrayidx5.1.i, align 4
+  %3 = load double* %V1, align 4
+  %mul11 = fmul double %3, undef
+  %mul13 = fmul double %mul11, %sub
+  %4 = load double* %arrayidx2, align 4
+  %mul15 = fmul double %4, %call1
+  %sub16 = fsub double %mul13, %mul15
+  store double %sub16, double* %arrayidx5.2.i, align 4
+  %5 = load double* %V1, align 4
+  %6 = load double* %arrayidx2, align 4
+  %mul22 = fmul double %5, %6
+  %mul24 = fmul double %mul22, %sub
+  %sub27 = fsub double %mul24, undef
+  store double %sub27, double* %arrayidx5.114.i, align 4
+  ret void
+}
+
+declare double @cos(double) nounwind readnone
+
+declare double @sin(double) nounwind readnone



From ahatanaka at mips.com  Mon Nov 14 12:56:20 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Mon, 14 Nov 2011 18:56:20 -0000
Subject: [llvm-commits] [llvm] r144549 - in /llvm/trunk/lib/Target/Mips:
 MipsFrameLowering.cpp MipsISelLowering.cpp MipsMachineFunction.h
Message-ID: <20111114185620.6E4CB2A6C131@llvm.org>

Author: ahatanak
Date: Mon Nov 14 12:56:20 2011
New Revision: 144549

URL: http://llvm.org/viewvc/llvm-project?rev=144549&view=rev
Log:
Remove variable that keeps the size of area used to save byval or variable
argument registers on the callee's stack frame, along with functions that set
and get it.
    
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.


Modified:
    llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsMachineFunction.h

Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?rev=144549&r1=144548&r2=144549&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Mon Nov 14 12:56:20 2011
@@ -163,7 +163,6 @@
     (MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) :
     MipsFI->getMaxCallFrameSize();
   unsigned StackSize = AlignOffset(LocalVarAreaOffset, StackAlign) +
-    AlignOffset(MipsFI->getRegSaveAreaSize(), StackAlign) +
     AlignOffset(MFI->getStackSize(), StackAlign);
 
    // Update stack size

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=144549&r1=144548&r2=144549&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Nov 14 12:56:20 2011
@@ -2459,7 +2459,6 @@
   if (IsRegLoc) {
     Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg());
     FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8;
-    MipsFI->setRegSaveAreaSize(-FOOffset);
   }
   else
     FOOffset = VA.getLocMemOffset();

Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.h?rev=144549&r1=144548&r2=144549&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMachineFunction.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Mon Nov 14 12:56:20 2011
@@ -51,16 +51,12 @@
   mutable int DynAllocFI; // Frame index of dynamically allocated stack area.   
   unsigned MaxCallFrameSize;
 
-  // Size of area on callee's stack frame which is used to save va_arg or 
-  // byval arguments passed in registers.
-  unsigned RegSaveAreaSize;
-
 public:
   MipsFunctionInfo(MachineFunction& MF)
   : MF(MF), SRetReturnReg(0), GlobalBaseReg(0),
     VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)),
     OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), DynAllocFI(0),
-    MaxCallFrameSize(0), RegSaveAreaSize(0)
+    MaxCallFrameSize(0)
   {}
 
   bool isInArgFI(int FI) const {
@@ -104,11 +100,6 @@
 
   unsigned getMaxCallFrameSize() const { return MaxCallFrameSize; }
   void setMaxCallFrameSize(unsigned S) { MaxCallFrameSize = S; }
-
-  unsigned getRegSaveAreaSize() const { return RegSaveAreaSize; }
-  void setRegSaveAreaSize(unsigned S) {
-    if (RegSaveAreaSize < S) RegSaveAreaSize = S;
-  }
 };
 
 } // end of namespace llvm



From peckw at wesleypeck.com  Mon Nov 14 12:56:41 2011
From: peckw at wesleypeck.com (Wesley Peck)
Date: Mon, 14 Nov 2011 18:56:41 -0000
Subject: [llvm-commits] [llvm] r144550 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111114185641.AC52E2A6C131@llvm.org>

Author: peckw
Date: Mon Nov 14 12:56:41 2011
New Revision: 144550

URL: http://llvm.org/viewvc/llvm-project?rev=144550&view=rev
Log:
Add release notes for the MicroBlaze backend.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=144550&r1=144549&r2=144550&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Nov 14 12:56:41 2011
@@ -977,6 +977,11 @@
 
   <p>PPC32/ELF va_arg was implemented.</p>
   <p>PPC32 initial support for .o file writing was implemented.</p>
+  <p>MicroBlaze scheduling itineraries were added that model the
+     3-stage and the 5-stage pipeline architectures. The 3-stage
+     pipeline model can be selected with <code>-mcpu=mblaze3</code> 
+     and the 5-stage pipeline model can be selected with 
+     <code>-mcpu=mblaze5</code>.</p>
   
 <ul>
 <!--



From justin.holewinski at gmail.com  Mon Nov 14 12:58:20 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Mon, 14 Nov 2011 18:58:20 -0000
Subject: [llvm-commits] [llvm] r144551 -
	/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
Message-ID: <20111114185820.8380E2A6C131@llvm.org>

Author: jholewinski
Date: Mon Nov 14 12:58:20 2011
New Revision: 144551

URL: http://llvm.org/viewvc/llvm-project?rev=144551&view=rev
Log:
PTX: Let LLVM use loads/stores for all mem* intrinsics, instead of relying on custom implementations.

Modified:
    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=144551&r1=144550&r2=144551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Mon Nov 14 12:58:20 2011
@@ -47,6 +47,11 @@
   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
   setMinFunctionAlignment(2);
 
+  // Let LLVM use loads/stores for all mem* operations
+  maxStoresPerMemcpy  = 4096;
+  maxStoresPerMemmove = 4096;
+  maxStoresPerMemset  = 4096;
+
   ////////////////////////////////////
   /////////// Expansion //////////////
   ////////////////////////////////////



From evan.cheng at apple.com  Mon Nov 14 13:08:42 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 14 Nov 2011 11:08:42 -0800
Subject: [llvm-commits] PATCH: custom lowering of x86 dec instruction
In-Reply-To: <2F2AA15F-4BC0-4F51-B018-3BD3ADE3CF78@apple.com>
References: <2F2AA15F-4BC0-4F51-B018-3BD3ADE3CF78@apple.com>
Message-ID: <2595EBA1-CE20-4BA6-8E64-4C958231A04B@apple.com>


On Nov 11, 2011, at 5:59 PM, Peter Cooper wrote:

> Hi
> 
> Please review the attached patch to custom lower a load->dec->store sequence for 64-bit integers on x86.
> 
> This is required because tablegen currently doesn't have a way to specify that a store pattern (DEC64m in this case) sets the EFLAGS register with a value that is usable by anything reading EFLAGS from the add -1 in the pattern.  
> 
> I've also changed code in EmitTest to allow stores to read from the EFLAGS setting instruction as they won't clobber the flags but this then allows EmitTest to avoid generating an explicit compare instruction.

Bummer. Do you have any idea how much effort it would take to implement this?

+    //OPC_CheckPredicate, 1, // Predicate_nontemporalstore
+    if (StoreNode->isNonTemporal())
+      break;
+
+    LoadSDNode *LoadNode = cast<LoadSDNode>(Chain.getNode());
+    if (LoadNode->getOperand(1) != Address ||
+        LoadNode->getOperand(2) != Undef)
+      break;
+
+    //OPC_CheckPredicate, 2, // Predicate_unindexedload
+    if (LoadNode->getAddressingMode() != ISD::UNINDEXED)
+      break;
+
+    // OPC_CheckPredicate, 3, // Predicate_load
+    if (LoadNode->getExtensionType() != ISD::NON_EXTLOAD)
+      break;
+
+    //OPC_CheckPredicate, 4, // Predicate_unindexedstore
+    if (StoreNode->getAddressingMode() != ISD::UNINDEXED)
+      break;
+
+    //OPC_CheckPredicate, 5, // Predicate_store
+    if (StoreNode->isTruncatingStore())
+      break;

These can be replaced by checks for ISD::isNormalLoad() and ISD::isNormalStore().

+    SDValue ReadsFromStoreChain(StoreNode, 0);
+    SDValue ReadsFromDecChain(Result, 1);
+    
+    ReplaceUses(ReadsFromStoreChain, ReadsFromDecChain);
+    
+    SDValue ReadsFromOldDecEFLAGS(StoredVal.getNode(), 1);
+    SDValue ReadsFromNewDecEFLAGS(Result, 0);
+    
+    ReplaceUses(ReadsFromOldDecEFLAGS, ReadsFromNewDecEFLAGS);

These can be simplified. Something like:
ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));

Evan

> 
> Thanks,
> Pete
> 
> <6172640.patch>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From dschuff at google.com  Mon Nov 14 12:54:11 2011
From: dschuff at google.com (Derek Schuff)
Date: Mon, 14 Nov 2011 10:54:11 -0800
Subject: [llvm-commits] Proposal/patch: Enable bitcode streaming
In-Reply-To: <CAAEAhvci4uJmsT4b1ibkG57qmzAesDdPQejmhAVLEmFd_FzyOg@mail.gmail.com>
References: <CAAEAhvci4uJmsT4b1ibkG57qmzAesDdPQejmhAVLEmFd_FzyOg@mail.gmail.com>
Message-ID: <CAAEAhvdtqnOFQhXfWc68tOvPHK0xCEDKYzpFL_tRw2Gu0qFdyQ@mail.gmail.com>

Ping?
Could someone take a look at this? (or, have I sent it to the wrong
place/not marked it properly?)

On Wed, Nov 9, 2011 at 4:57 PM, Derek Schuff <dschuff at google.com> wrote:

> Hello all,
> The following is a proposal (and a prototype patch) to enable bitcode
> streaming. The overall goal is to be able to overlap bitcode
> reading/download with compilation, a functionality useful obviously for
> pnacl and renderscript but also potentially for any situation where the
> interface between the frontend and backend is something other than a file.
>
> In the current state of the world, at a high level, there are 2 things
> keeping this from happening. The first is that BitcodeReader construction
> takes a MemoryBuffer which it expects to be filled with bitcode, and inside
> BitcodeReader, the BitstreamCursor (which is the primary interface to the
> bitcode itself) gets pointers to the bitcode in memory, and does all of its
> magic with pointer arithmetic. The second issue is that in
> BitcodeReader::ParseModule (which is run when right after the Module and
> BitcodeReader objects are created), the reader makes a pass over the entire
> bitcode file. This step does everything except read the function bodies,
> but it records the bit locations of each function for future
> materialization.
>
> High-level change description:
> This patch creates a class called BitcodeStream, which is a very simple
> interface with one method (GetBytes), which fetches the requested number of
> bytes from the stream, and writes them into the requested destination. This
> method may block the calling thread if there are not yet enough bytes
> available in the stream buffer (similarly to a stdin or socket read).
>
> The first issue above is addressed by introducing the BitstreamVector, an
> abstraction that wraps the bitcode in memory. Instead of using pointers,
> the BitstreamCursor uses indices and gets bitcode bytes by indexing (i.e.
> operator[] ) the BitstreamVector. When streaming is not used, the
> BitstreamVector itself keeps pointers to the start and end of the backing
> MemoryBuffer and the indexing operator is just a pointer dereference. For
> streaming use, the BitstreamVector has a BitcodeStream object. If a byte is
> requested that has not yet been fetched, it calls GetBytes to get more,
> until it has enough to return the requested byte.
> This model of allowing any byte to be requested and blocking the caller
> has the advantage that there is no structural/architectural change required
> at this lowest level, nor at the high level (A FunctionPassManager is used
> to iterate over all the functions and compile each one).
>
> The second issue is solved by 2 simple changes. The first is in
> ParseModule. Instead of a single pass over all the bitcode, ParseModule
> becomes resumable.  ParseModule will do its normal handling for top-level
> records, type table blocks, metadata, etc, but if streaming is in use, it
> will save its state and return as soon as a function subblock is
> encountered (rather than saving its location and skipping over it). Each
> subsequent time it is called, it bookmarks and skips one function block.
> Later, when a function needs to be materialized, if the function body has
> been seen already, then materialization is the same as before. Otherwise,
> Materialize will keep calling ParseModule (each time bookmarking and
> skipping one function body) until the requested function is found. The one
> other change required to make this work simply is that the bitcode writer
> writes function bodies as the last subblock (currently the attachment
> metadata and value symbol table are written after the function bodies).
>
> The prototype patch is attached and can also be viewed online at
> http://codereview.chromium.org/8393017/ . Feedback is welcome, as well as
> guidance from the relevant code owners/reviewers regarding what the next
> step needs to be toward committing this.
>
> Thanks,
> -Derek
>
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From benny.kra at googlemail.com  Mon Nov 14 13:12:20 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 14 Nov 2011 19:12:20 -0000
Subject: [llvm-commits] [llvm] r144555 - in /llvm/trunk:
 include/llvm/Constants.h lib/VMCore/Constants.cpp
Message-ID: <20111114191220.F0BB32A6C131@llvm.org>

Author: d0k
Date: Mon Nov 14 13:12:20 2011
New Revision: 144555

URL: http://llvm.org/viewvc/llvm-project?rev=144555&view=rev
Log:
Fold ConstantVector::isAllOnesValue into Constant::isAllOnesValue and simplify it.

Modified:
    llvm/trunk/include/llvm/Constants.h
    llvm/trunk/lib/VMCore/Constants.cpp

Modified: llvm/trunk/include/llvm/Constants.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=144555&r1=144554&r2=144555&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Constants.h (original)
+++ llvm/trunk/include/llvm/Constants.h Mon Nov 14 13:12:20 2011
@@ -475,12 +475,6 @@
   inline VectorType *getType() const {
     return reinterpret_cast<VectorType*>(Value::getType());
   }
-  
-  /// This function will return true iff every element in this vector constant
-  /// is set to all ones.
-  /// @returns true iff this constant's emements are all set to all ones.
-  /// @brief Determine if the value is all ones.
-  bool isAllOnesValue() const;
 
   /// getSplatValue - If this is a splat constant, meaning that all of the
   /// elements have the same value, return that value. Otherwise return NULL.

Modified: llvm/trunk/lib/VMCore/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=144555&r1=144554&r2=144555&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Constants.cpp (original)
+++ llvm/trunk/lib/VMCore/Constants.cpp Mon Nov 14 13:12:20 2011
@@ -71,12 +71,14 @@
   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(this))
     return CFP->getValueAPF().bitcastToAPInt().isAllOnesValue();
 
-  // Check for constant vectors
+  // Check for constant vectors which are splats of -1 values.
   if (const ConstantVector *CV = dyn_cast<ConstantVector>(this))
-    return CV->isAllOnesValue();
+    if (Constant *Splat = CV->getSplatValue())
+      return Splat->isAllOnesValue();
 
   return false;
 }
+
 // Constructor to create a '0' constant of arbitrary type...
 Constant *Constant::getNullValue(Type *Ty) {
   switch (Ty->getTypeID()) {
@@ -1071,26 +1073,6 @@
   destroyConstantImpl();
 }
 
-/// This function will return true iff every element in this vector constant
-/// is set to all ones.
-/// @returns true iff this constant's elements are all set to all ones.
-/// @brief Determine if the value is all ones.
-bool ConstantVector::isAllOnesValue() const {
-  // Check out first element.
-  const Constant *Elt = getOperand(0);
-  const ConstantInt *CI = dyn_cast<ConstantInt>(Elt);
-  const ConstantFP *CF = dyn_cast<ConstantFP>(Elt);
-
-  // Then make sure all remaining elements point to the same value.
-  for (unsigned I = 1, E = getNumOperands(); I < E; ++I)
-    if (getOperand(I) != Elt)
-      return false;
-  
-  // First value is all-ones.
-  return (CI && CI->isAllOnesValue()) || 
-         (CF && CF->isAllOnesValue());
-}
-
 /// getSplatValue - If this is a splat constant, where all of the
 /// elements have the same value, return that value. Otherwise return null.
 Constant *ConstantVector::getSplatValue() const {



From ahatanaka at mips.com  Mon Nov 14 13:06:14 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Mon, 14 Nov 2011 19:06:14 -0000
Subject: [llvm-commits] [llvm] r144554 -
	/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
Message-ID: <20111114190614.685422A6C131@llvm.org>

Author: ahatanak
Date: Mon Nov 14 13:06:14 2011
New Revision: 144554

URL: http://llvm.org/viewvc/llvm-project?rev=144554&view=rev
Log:
32-to-64-bit extended load.


Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=144554&r1=144553&r2=144554&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Nov 14 13:06:14 2011
@@ -219,11 +219,16 @@
 def : Pat<(i64 imm:$imm),
           (ORi64 (LUi64 (HI16 imm:$imm)), (LO16 imm:$imm))>;
 
-// zextloadi32_u
-def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64_P8 addr:$a), 0), 0)>,
-      Requires<[IsN64]>;
-def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64 addr:$a), 0), 0)>,
-      Requires<[NotN64]>;
+// extended loads
+let Predicates = [NotN64] in {
+  def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64 addr:$a), 0), 0)>;
+  def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64 addr:$a), 0), 0)>;
+}
+let Predicates = [IsN64] in {
+  def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64_P8 addr:$a), 0), 0)>;
+  def : Pat<(zextloadi32_u addr:$a), 
+            (DSRL32 (DSLL32 (ULW64_P8 addr:$a), 0), 0)>;
+}
 
 // hi/lo relocs
 def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>;



From matt.pharr at gmail.com  Mon Nov 14 13:24:30 2011
From: matt.pharr at gmail.com (Matt Pharr)
Date: Mon, 14 Nov 2011 11:24:30 -0800
Subject: [llvm-commits] pr11367
In-Reply-To: <AEE31309-99DD-47C3-912A-2674D658E6A7@apple.com>
References: <CAG3jReJHN2jo=Mv97jR9Ep2jywLTbMPyvF03y6Q_ffU6m0S8wA@mail.gmail.com>
	<B1289D79-A496-43C2-A644-564033AF3EF2@nondot.org>
	<AEE31309-99DD-47C3-912A-2674D658E6A7@apple.com>
Message-ID: <1CF650DE-6A87-445E-8F76-A3034E121D98@gmail.com>

It's not a completely theoretical use case: the ispc compiler depended on the old behavior from LinkModules() ("link everything in the provided modules together, and don't be clever about skipping stuff that seems to not be used"), and the lazy linking change broke that.

I've since worked around this API change with a somewhat ugly hack, but it seems to me that the basic functionality of having the ability to easily cat modules together is worth having around.  I don't have an opinion about what llvm-link should do, but I do believe that the APIs should still provide this functionality somehow.  (One possibility being the patch I sent to llvm-dev a week or so ago.)

Thanks,
-matt

On Nov 14, 2011, at 10:40 AM, Chris Lattner wrote:

> MHO is that mainline is behaving correctly.  We don't want LTO or llvm-link to keep all bitcode files around in memory to support a theoretical use case.
> 
> -Chris
> 
> On Nov 14, 2011, at 10:21 AM, Tanya Lattner wrote:
> 
>> 
>> On Nov 14, 2011, at 8:55 AM, Rafael Esp?ndola wrote:
>> 
>>> I was thinking a bit about pr11367. The most direct way to solve it is
>>> keeping the list open until the linker is done adding files, but maybe
>>> there is a better way.
>>> 
>>> What was the intended use case of lazy linking? Speeding up LTO?
>> 
>> I implemented lazy linking for an outside project where I want to link with a bc library and only link in the functions that are used.  We use the LinkModules() API directly. I talked to Chris about this and he wanted LTO to take advantage of this as well, so it seemed like a win for both.
>> 
>>> If
>>> so, it might be better to drop these function at the end of
>>> -std-compile-opts and change back the linker to keeping everything.
>>> The advantages would be
>> 
>> I really don't want to run the optimizer on everything when the linker can easily do this.
>> 
>>> 
>>> * llvm-link is again just a IL version of cat
>> 
>> I'm sure this can be up for debate as what llvm-link is really supposed to do. I don't want to remove this functionality from the API. If its decided that llvm-link is really catting IR files together, then its better to make an option to turn it off (for llvm-link if it chooses) and have it on by default.
>> 
>> -Tanya
>> 
>>> * LTO is even faster, as we avoid writing to disk the functions that
>>> we currently drop when reading in.
>>> 
>>> It is true that we would drop more available_externally functions.
>>> Right now if we drop them or not depends on the file order.
>>> 
>>> Both the current solution and the dropping them in -std-compile-opts
>>> could also introduce a regression compared to the old way where an
>>> available_externally function in one file would be available for use
>>> in any other file. I don't think this would be a problem in practise.
>>> Any translation unit that uses an inline function is likely to see its
>>> definition.
>>> 
>>> Cheers,
>>> Rafael
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 



From ahatanaka at mips.com  Mon Nov 14 13:01:09 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Mon, 14 Nov 2011 19:01:09 -0000
Subject: [llvm-commits] [llvm] r144552 -
	/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
Message-ID: <20111114190109.8B9C82A6C131@llvm.org>

Author: ahatanak
Date: Mon Nov 14 13:01:09 2011
New Revision: 144552

URL: http://llvm.org/viewvc/llvm-project?rev=144552&view=rev
Log:
Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=144552&r1=144551&r2=144552&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Nov 14 13:01:09 2011
@@ -2621,24 +2621,40 @@
     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
   }
 
-  if (isVarArg && IsO32) {
+  if (isVarArg) {
+    unsigned NumOfRegs = IsO32 ? 4 : 8;
+    const unsigned *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
+    unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs);
+    int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot.
+    TargetRegisterClass *RC
+      = IsO32 ? Mips::CPURegsRegisterClass : Mips::CPU64RegsRegisterClass;
+    unsigned RegSize = RC->getSize();
+    int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize;
+
+    // Offset of the first variable argument from stack pointer.
+    int FirstVaArgOffset;
+
+    if (IsO32 || (Idx == NumOfRegs)) {
+      FirstVaArgOffset =
+        (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize;
+    } else
+      FirstVaArgOffset = RegSlotOffset;
+
     // Record the frame index of the first variable argument
     // which is a value necessary to VASTART.
-    unsigned NextStackOffset = CCInfo.getNextStackOffset();
-    assert(NextStackOffset % 4 == 0 &&
-           "NextStackOffset must be aligned to 4-byte boundaries.");
-    LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
+    LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true);
     MipsFI->setVarArgsFrameIndex(LastFI);
 
-    // If NextStackOffset is smaller than o32's 16-byte reserved argument area,
-    // copy the integer registers that have not been used for argument passing
-    // to the caller's stack frame.
-    for (; NextStackOffset < 16; NextStackOffset += 4) {
-      TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
-      unsigned Idx = NextStackOffset / 4;
-      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC);
-      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
-      LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
+    // Copy the integer registers that have not been used for argument passing
+    // to the argument register save area. For O32, the save area is allocated
+    // in the caller's stack frame, while for N32/64, it is allocated in the
+    // callee's stack frame.
+    for (int StackOffset = RegSlotOffset;
+         Idx < NumOfRegs; ++Idx, StackOffset += RegSize) {
+      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC);
+      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
+                                            MVT::getIntegerVT(RegSize * 8));
+      LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true);
       SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
       OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
                                        MachinePointerInfo(),



From peter_cooper at apple.com  Mon Nov 14 13:38:42 2011
From: peter_cooper at apple.com (Pete Cooper)
Date: Mon, 14 Nov 2011 19:38:42 -0000
Subject: [llvm-commits] [llvm] r144557 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/vector-variable-idx2.ll
Message-ID: <20111114193842.8A5472A6C131@llvm.org>

Author: pete
Date: Mon Nov 14 13:38:42 2011
New Revision: 144557

URL: http://llvm.org/viewvc/llvm-project?rev=144557&view=rev
Log:
Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered

Constant idx case is still done in tablegen but other cases are then expanded

Fixes <rdar://problem/10435460>

Added:
    llvm/trunk/test/CodeGen/X86/vector-variable-idx2.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144557&r1=144556&r2=144557&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Nov 14 13:38:42 2011
@@ -944,9 +944,11 @@
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
 
+    // FIXME: these should be Legal but thats only for the case where
+    // the index is constant.  For now custom expand to deal with that
     if (Subtarget->is64Bit()) {
-      setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2i64, Legal);
-      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
+      setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2i64, Custom);
+      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
     }
   }
 
@@ -6963,8 +6965,8 @@
                                               Op.getOperand(0)),
                                               Op.getOperand(1));
     return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
-  } else if (VT == MVT::i32) {
-    // ExtractPS works with constant index.
+  } else if (VT == MVT::i32 || VT == MVT::i64) {
+    // ExtractPS/pextrq works with constant index.
     if (isa<ConstantSDNode>(Op.getOperand(1)))
       return Op;
   }
@@ -7103,7 +7105,8 @@
     // Create this as a scalar to vector..
     N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
     return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
-  } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
+  } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 
+             isa<ConstantSDNode>(N2)) {
     // PINSR* works with constant index.
     return Op;
   }

Added: llvm/trunk/test/CodeGen/X86/vector-variable-idx2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-variable-idx2.ll?rev=144557&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-variable-idx2.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vector-variable-idx2.ll Mon Nov 14 13:38:42 2011
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse41
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin11.0.0"
+
+define i64 @__builtin_ia32_vec_ext_v2di(<2 x i64> %a, i32 %i) nounwind {
+  %1 = alloca <2 x i64>, align 16
+  %2 = alloca i32, align 4
+  store <2 x i64> %a, <2 x i64>* %1, align 16
+  store i32 %i, i32* %2, align 4
+  %3 = load <2 x i64>* %1, align 16
+  %4 = load i32* %2, align 4
+  %5 = extractelement <2 x i64> %3, i32 %4
+  ret i64 %5
+}
+
+define <2 x i64> @__builtin_ia32_vec_int_v2di(<2 x i64> %a, i32 %i) nounwind {
+  %1 = alloca <2 x i64>, align 16
+  %2 = alloca i32, align 4
+  store <2 x i64> %a, <2 x i64>* %1, align 16
+  store i32 %i, i32* %2, align 4
+  %3 = load <2 x i64>* %1, align 16
+  %4 = load i32* %2, align 4
+  %5 = insertelement <2 x i64> %3, i64 1, i32 %4
+  ret <2 x i64> %5
+}



From peter_cooper at apple.com  Mon Nov 14 13:42:35 2011
From: peter_cooper at apple.com (Peter Cooper)
Date: Mon, 14 Nov 2011 11:42:35 -0800
Subject: [llvm-commits] PATCH: custom lowering of x86 dec instruction
In-Reply-To: <2595EBA1-CE20-4BA6-8E64-4C958231A04B@apple.com>
References: <2F2AA15F-4BC0-4F51-B018-3BD3ADE3CF78@apple.com>
	<2595EBA1-CE20-4BA6-8E64-4C958231A04B@apple.com>
Message-ID: <3ABE47D8-9C05-4183-9B24-24F0959229E2@apple.com>

Thanks for the comments Evan.  I'll apply the changes you suggested.

I have an idea for a tablegen fix but it would involve adding a new keyword so for example instead of doing "implicit EFLAGS" you could do "transferrable EFLAGS" which means anything that reads EFLAGS from the nodes in the matched tree would now read them from the new node.

However, there's then issues with identifying which node in the pattern had the transferrable EFLAGS and ensuring it can't be applied to cases which define multiple result nodes, but yeah, it could be done.

Pete

On Nov 14, 2011, at 11:08 AM, Evan Cheng wrote:

> 
> On Nov 11, 2011, at 5:59 PM, Peter Cooper wrote:
> 
>> Hi
>> 
>> Please review the attached patch to custom lower a load->dec->store sequence for 64-bit integers on x86.
>> 
>> This is required because tablegen currently doesn't have a way to specify that a store pattern (DEC64m in this case) sets the EFLAGS register with a value that is usable by anything reading EFLAGS from the add -1 in the pattern.  
>> 
>> I've also changed code in EmitTest to allow stores to read from the EFLAGS setting instruction as they won't clobber the flags but this then allows EmitTest to avoid generating an explicit compare instruction.
> 
> Bummer. Do you have any idea how much effort it would take to implement this?
> 
> +    //OPC_CheckPredicate, 1, // Predicate_nontemporalstore
> +    if (StoreNode->isNonTemporal())
> +      break;
> +
> +    LoadSDNode *LoadNode = cast<LoadSDNode>(Chain.getNode());
> +    if (LoadNode->getOperand(1) != Address ||
> +        LoadNode->getOperand(2) != Undef)
> +      break;
> +
> +    //OPC_CheckPredicate, 2, // Predicate_unindexedload
> +    if (LoadNode->getAddressingMode() != ISD::UNINDEXED)
> +      break;
> +
> +    // OPC_CheckPredicate, 3, // Predicate_load
> +    if (LoadNode->getExtensionType() != ISD::NON_EXTLOAD)
> +      break;
> +
> +    //OPC_CheckPredicate, 4, // Predicate_unindexedstore
> +    if (StoreNode->getAddressingMode() != ISD::UNINDEXED)
> +      break;
> +
> +    //OPC_CheckPredicate, 5, // Predicate_store
> +    if (StoreNode->isTruncatingStore())
> +      break;
> 
> These can be replaced by checks for ISD::isNormalLoad() and ISD::isNormalStore().
> 
> +    SDValue ReadsFromStoreChain(StoreNode, 0);
> +    SDValue ReadsFromDecChain(Result, 1);
> +    
> +    ReplaceUses(ReadsFromStoreChain, ReadsFromDecChain);
> +    
> +    SDValue ReadsFromOldDecEFLAGS(StoredVal.getNode(), 1);
> +    SDValue ReadsFromNewDecEFLAGS(Result, 0);
> +    
> +    ReplaceUses(ReadsFromOldDecEFLAGS, ReadsFromNewDecEFLAGS);
> 
> These can be simplified. Something like:
> ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
> 
> Evan
> 
>> 
>> Thanks,
>> Pete
>> 
>> <6172640.patch>_______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 


From ahatanaka at mips.com  Mon Nov 14 13:02:54 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Mon, 14 Nov 2011 19:02:54 -0000
Subject: [llvm-commits] [llvm] r144553 - in /llvm/trunk/lib/Target/Mips:
 MipsCallingConv.td MipsISelLowering.cpp
Message-ID: <20111114190254.B6F662A6C131@llvm.org>

Author: ahatanak
Date: Mon Nov 14 13:02:54 2011
New Revision: 144553

URL: http://llvm.org/viewvc/llvm-project?rev=144553&view=rev
Log:
AnalyzeCallOperands function for N32/64.

N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.


Modified:
    llvm/trunk/lib/Target/Mips/MipsCallingConv.td
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsCallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCallingConv.td?rev=144553&r1=144552&r2=144553&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsCallingConv.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsCallingConv.td Mon Nov 14 13:02:54 2011
@@ -64,6 +64,25 @@
   CCIfType<[f32], CCAssignToStack<4, 8>>
 ]>;
 
+// N32/64 variable arguments.
+// All arguments are passed in integer registers.
+def CC_MipsN_VarArg : CallingConv<[
+   // Handles byval parameters.
+  CCIfByVal<CCCustom<"CC_Mips64Byval">>,
+ 
+  // Promote i8/i16/i32 arguments to i64.
+  CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
+
+  CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
+                                      T0_64, T1_64, T2_64, T3_64]>>,
+
+  CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
+
+  // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
+  CCIfType<[i64, f64], CCAssignToStack<8, 8>>,
+  CCIfType<[f32], CCAssignToStack<4, 8>>
+]>;
+
 def RetCC_MipsN : CallingConv<[
   // FIXME: Handle complex and float double return values.
 

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=144553&r1=144552&r2=144553&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Nov 14 13:02:54 2011
@@ -1918,6 +1918,30 @@
 
 #include "MipsGenCallingConv.inc"
 
+static void
+AnalyzeMips64CallOperands(CCState CCInfo,
+                          const SmallVectorImpl<ISD::OutputArg> &Outs) {
+  unsigned NumOps = Outs.size();
+  for (unsigned i = 0; i != NumOps; ++i) {
+    MVT ArgVT = Outs[i].VT;
+    ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
+    bool R;
+
+    if (Outs[i].IsFixed)
+      R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
+    else
+      R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
+      
+#ifndef NDEBUG
+    if (R) {
+      dbgs() << "Call operand #" << i << " has unhandled type "
+             << EVT(ArgVT).getEVTString();
+#endif
+      llvm_unreachable(0);
+    }
+  }
+}
+
 //===----------------------------------------------------------------------===//
 //                  Call Calling Convention Implementation
 //===----------------------------------------------------------------------===//
@@ -2138,6 +2162,8 @@
 
   if (IsO32)
     CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
+  else if (HasMips64)
+    AnalyzeMips64CallOperands(CCInfo, Outs);
   else
     CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
 



From evan.cheng at apple.com  Mon Nov 14 13:48:55 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 14 Nov 2011 19:48:55 -0000
Subject: [llvm-commits] [llvm] r144559 - in /llvm/trunk:
 lib/CodeGen/TwoAddressInstructionPass.cpp
 test/CodeGen/X86/iv-users-in-other-loops.ll
 test/CodeGen/X86/lsr-reuse-trunc.ll test/CodeGen/X86/sse3.ll
Message-ID: <20111114194856.004232A6C131@llvm.org>

Author: evancheng
Date: Mon Nov 14 13:48:55 2011
New Revision: 144559

URL: http://llvm.org/viewvc/llvm-project?rev=144559&view=rev
Log:
Teach two-address pass to re-schedule two-address instructions (or the kill
instructions of the two-address operands) in order to avoid inserting copies.
This fixes the few regressions introduced when the two-address hack was
disabled (without regressing the improvements).
rdar://10422688

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll
    llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll
    llvm/trunk/test/CodeGen/X86/sse3.ll

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=144559&r1=144558&r2=144559&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon Nov 14 13:48:55 2011
@@ -36,6 +36,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
@@ -56,11 +57,14 @@
 STATISTIC(Num3AddrSunk,        "Number of 3-address instructions sunk");
 STATISTIC(NumReMats,           "Number of instructions re-materialized");
 STATISTIC(NumDeletes,          "Number of dead instructions deleted");
+STATISTIC(NumReSchedUps,       "Number of instructions re-scheduled up");
+STATISTIC(NumReSchedDowns,     "Number of instructions re-scheduled down");
 
 namespace {
   class TwoAddressInstructionPass : public MachineFunctionPass {
     const TargetInstrInfo *TII;
     const TargetRegisterInfo *TRI;
+    const InstrItineraryData *InstrItins;
     MachineRegisterInfo *MRI;
     LiveVariables *LV;
     AliasAnalysis *AA;
@@ -120,6 +124,18 @@
                            MachineBasicBlock::iterator &nmi,
                            MachineFunction::iterator &mbbi, unsigned Dist);
 
+    bool isDefTooClose(unsigned Reg, unsigned Dist,
+                       MachineInstr *MI, MachineBasicBlock *MBB);
+
+    bool RescheduleMIBelowKill(MachineBasicBlock *MBB,
+                               MachineBasicBlock::iterator &mi,
+                               MachineBasicBlock::iterator &nmi,
+                               unsigned Reg);
+    bool RescheduleKillAboveMI(MachineBasicBlock *MBB,
+                               MachineBasicBlock::iterator &mi,
+                               MachineBasicBlock::iterator &nmi,
+                               unsigned Reg);
+
     bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
                                  MachineBasicBlock::iterator &nmi,
                                  MachineFunction::iterator &mbbi,
@@ -467,6 +483,32 @@
   return false;
 }
 
+/// findLocalKill - Look for an instruction below MI in the MBB that kills the
+/// specified register. Returns null if there are any other Reg use between the
+/// instructions.
+static
+MachineInstr *findLocalKill(unsigned Reg, MachineBasicBlock *MBB,
+                            MachineInstr *MI, MachineRegisterInfo *MRI,
+                            DenseMap<MachineInstr*, unsigned> &DistanceMap) {
+  MachineInstr *KillMI = 0;
+  for (MachineRegisterInfo::use_nodbg_iterator
+         UI = MRI->use_nodbg_begin(Reg),
+         UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
+    MachineInstr *UseMI = &*UI;
+    if (UseMI == MI || UseMI->getParent() != MBB)
+      continue;
+    DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
+    if (DI != DistanceMap.end())
+      continue;
+    if (!UI.getOperand().isKill())
+      return 0;
+    assert(!KillMI && "More than one local kills?");
+    KillMI = UseMI;
+  }
+
+  return KillMI;
+}
+
 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
 /// use, return the use instruction if it's a copy or a two-address use.
 static
@@ -852,6 +894,285 @@
   return true;
 }
 
+/// RescheduleMIBelowKill - If there is one more local instruction that reads
+/// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
+/// instruction in order to eliminate the need for the copy.
+bool
+TwoAddressInstructionPass::RescheduleMIBelowKill(MachineBasicBlock *MBB,
+                                     MachineBasicBlock::iterator &mi,
+                                     MachineBasicBlock::iterator &nmi,
+                                     unsigned Reg) {
+  MachineInstr *MI = &*mi;
+  DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 
+  if (DI == DistanceMap.end())
+    // Must be created from unfolded load. Don't waste time trying this.
+    return false;
+
+  MachineInstr *KillMI = findLocalKill(Reg, MBB, mi, MRI, DistanceMap);
+  if (!KillMI || KillMI->isCopy() || KillMI->isCopyLike())
+    // Don't mess with copies, they may be coalesced later.
+    return false;
+
+  const MCInstrDesc &MCID = KillMI->getDesc();
+  if (MCID.hasUnmodeledSideEffects() || MCID.isCall() || MCID.isBranch() ||
+      MCID.isTerminator())
+    // Don't move pass calls, etc.
+    return false;
+
+  unsigned DstReg;
+  if (isTwoAddrUse(*KillMI, Reg, DstReg))
+    return false;
+
+  bool SeenStore;
+  if (!MI->isSafeToMove(TII, AA, SeenStore))
+    return false;
+
+  if (TII->getInstrLatency(InstrItins, MI) > 1)
+    // FIXME: Needs more sophisticated heuristics.
+    return false;
+
+  SmallSet<unsigned, 2> Uses;
+  SmallSet<unsigned, 2> Defs;
+  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    const MachineOperand &MO = MI->getOperand(i);
+    if (!MO.isReg())
+      continue;
+    unsigned MOReg = MO.getReg();
+    if (!MOReg)
+      continue;
+    if (MO.isDef())
+      Defs.insert(MOReg);
+    else
+      Uses.insert(MOReg);
+  }
+
+  // Move the copies connected to MI down as well.
+  MachineBasicBlock::iterator From = MI;
+  MachineBasicBlock::iterator To = llvm::next(From);
+  while (To->isCopy() && Defs.count(To->getOperand(1).getReg())) {
+    Defs.insert(To->getOperand(0).getReg());
+    ++To;
+  }
+
+  // Check if the reschedule will not break depedencies.
+  unsigned NumVisited = 0;
+  MachineBasicBlock::iterator KillPos = KillMI;
+  ++KillPos;
+  for (MachineBasicBlock::iterator I = To; I != KillPos; ++I) {
+    MachineInstr *OtherMI = I;
+    // DBG_VALUE cannot be counted against the limit.
+    if (OtherMI->isDebugValue())
+      continue;
+    if (NumVisited > 10)  // FIXME: Arbitrary limit to reduce compile time cost.
+      return false;
+    ++NumVisited;
+    const MCInstrDesc &OMCID = OtherMI->getDesc();
+    if (OMCID.hasUnmodeledSideEffects() || OMCID.isCall() || OMCID.isBranch() ||
+        OMCID.isTerminator())
+      // Don't move pass calls, etc.
+      return false;
+    for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
+      const MachineOperand &MO = OtherMI->getOperand(i);
+      if (!MO.isReg())
+        continue;
+      unsigned MOReg = MO.getReg();
+      if (!MOReg)
+        continue;
+      if (MO.isDef()) {
+        if (Uses.count(MOReg))
+          // Physical register use would be clobbered.
+          return false;
+        if (!MO.isDead() && Defs.count(MOReg))
+          // May clobber a physical register def.
+          // FIXME: This may be too conservative. It's ok if the instruction
+          // is sunken completely below the use.
+          return false;
+      } else {
+        if (Defs.count(MOReg))
+          return false;
+        if (MOReg != Reg && MO.isKill() && Uses.count(MOReg))
+          // Don't want to extend other live ranges and update kills.
+          return false;
+      }
+    }
+  }
+
+  // Move debug info as well.
+  if (From != MBB->begin()) {
+    while (llvm::prior(From)->isDebugValue())
+      --From;
+  }
+
+  // Copies following MI may have been moved as well.
+  nmi = To;
+  MBB->splice(KillPos, MBB, From, To);
+  DistanceMap.erase(DI);
+
+  if (LV) {
+    // Update live variables
+    LV->removeVirtualRegisterKilled(Reg, KillMI);
+    LV->addVirtualRegisterKilled(Reg, MI);
+  } else {
+    for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
+      MachineOperand &MO = KillMI->getOperand(i);
+      if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
+        continue;
+      MO.setIsKill(false);
+    }
+    MI->addRegisterKilled(Reg, 0);
+  }
+
+  return true;
+}
+
+/// isDefTooClose - Return true if the re-scheduling will put the given
+/// instruction too close to the defs of its register dependencies.
+bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
+                                              MachineInstr *MI,
+                                              MachineBasicBlock *MBB) {
+  for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
+         DE = MRI->def_end(); DI != DE; ++DI) {
+    MachineInstr *DefMI = &*DI;
+    if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike())
+      continue;
+    if (DefMI == MI)
+      return true; // MI is defining something KillMI uses
+    DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI);
+    if (DDI == DistanceMap.end())
+      return true;  // Below MI
+    unsigned DefDist = DDI->second;
+    assert(Dist > DefDist && "Visited def already?");
+    if (TII->getInstrLatency(InstrItins, DefMI) > (int)(Dist - DefDist))
+      return true;
+  }
+  return false;
+}
+
+/// RescheduleKillAboveMI - If there is one more local instruction that reads
+/// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
+/// current two-address instruction in order to eliminate the need for the
+/// copy.
+bool
+TwoAddressInstructionPass::RescheduleKillAboveMI(MachineBasicBlock *MBB,
+                                     MachineBasicBlock::iterator &mi,
+                                     MachineBasicBlock::iterator &nmi,
+                                     unsigned Reg) {
+  MachineInstr *MI = &*mi;
+  DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
+  if (DI == DistanceMap.end())
+    // Must be created from unfolded load. Don't waste time trying this.
+    return false;
+
+  MachineInstr *KillMI = findLocalKill(Reg, MBB, mi, MRI, DistanceMap);
+  if (!KillMI || KillMI->isCopy() || KillMI->isCopyLike())
+    // Don't mess with copies, they may be coalesced later.
+    return false;
+
+  unsigned DstReg;
+  if (isTwoAddrUse(*KillMI, Reg, DstReg))
+    return false;
+
+  bool SeenStore;
+  if (!KillMI->isSafeToMove(TII, AA, SeenStore))
+    return false;
+
+  SmallSet<unsigned, 2> Uses;
+  SmallSet<unsigned, 2> Kills;
+  SmallSet<unsigned, 2> Defs;
+  SmallSet<unsigned, 2> LiveDefs;
+  for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
+    const MachineOperand &MO = KillMI->getOperand(i);
+    if (!MO.isReg())
+      continue;
+    unsigned MOReg = MO.getReg();
+    if (MO.isUse()) {
+      if (!MOReg)
+        continue;
+      if (isDefTooClose(MOReg, DI->second, MI, MBB))
+        return false;
+      Uses.insert(MOReg);
+      if (MO.isKill() && MOReg != Reg)
+        Kills.insert(MOReg);
+    } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
+      Defs.insert(MOReg);
+      if (!MO.isDead())
+        LiveDefs.insert(MOReg);
+    }
+  }
+
+  // Check if the reschedule will not break depedencies.
+  unsigned NumVisited = 0;
+  MachineBasicBlock::iterator KillPos = KillMI;
+  for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
+    MachineInstr *OtherMI = I;
+    // DBG_VALUE cannot be counted against the limit.
+    if (OtherMI->isDebugValue())
+      continue;
+    if (NumVisited > 10)  // FIXME: Arbitrary limit to reduce compile time cost.
+      return false;
+    ++NumVisited;
+    const MCInstrDesc &MCID = OtherMI->getDesc();
+    if (MCID.hasUnmodeledSideEffects() || MCID.isCall() || MCID.isBranch() ||
+        MCID.isTerminator())
+      // Don't move pass calls, etc.
+      return false;
+    for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
+      const MachineOperand &MO = OtherMI->getOperand(i);
+      if (!MO.isReg())
+        continue;
+      unsigned MOReg = MO.getReg();
+      if (!MOReg)
+        continue;
+      if (MO.isUse()) {
+        if (Defs.count(MOReg))
+          // Moving KillMI can clobber the physical register if the def has
+          // not been seen.
+          return false;
+        if (Kills.count(MOReg))
+          // Don't want to extend other live ranges and update kills.
+          return false;
+      } else {
+        if (Uses.count(MOReg))
+          return false;
+        if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
+            LiveDefs.count(MOReg))
+          return false;
+        // Physical register def is seen.
+        Defs.erase(MOReg);
+      }
+    }
+  }
+
+  // Move the old kill above MI, don't forget to move debug info as well.
+  MachineBasicBlock::iterator InsertPos = mi;
+  if (InsertPos != MBB->begin())
+    while (llvm::prior(InsertPos)->isDebugValue())
+      --InsertPos;
+  MachineBasicBlock::iterator From = KillMI;
+  MachineBasicBlock::iterator To = llvm::next(From);
+  while (llvm::prior(From)->isDebugValue())
+    --From;
+  MBB->splice(InsertPos, MBB, From, To);
+
+  nmi = llvm::prior(mi); // Backtrack so we process the moved instruction.
+  DistanceMap.erase(DI);
+
+  if (LV) {
+    // Update live variables
+    LV->removeVirtualRegisterKilled(Reg, KillMI);
+    LV->addVirtualRegisterKilled(Reg, MI);
+  } else {
+    for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
+      MachineOperand &MO = KillMI->getOperand(i);
+      if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
+        continue;
+      MO.setIsKill(false);
+    }
+    MI->addRegisterKilled(Reg, 0);
+  }
+  return true;
+}
+
 /// TryInstructionTransform - For the case where an instruction has a single
 /// pair of tied register operands, attempt some transformations that may
 /// either eliminate the tied operands or improve the opportunities for
@@ -863,17 +1184,18 @@
                         MachineFunction::iterator &mbbi,
                         unsigned SrcIdx, unsigned DstIdx, unsigned Dist,
                         SmallPtrSet<MachineInstr*, 8> &Processed) {
-  const MCInstrDesc &MCID = mi->getDesc();
-  unsigned regA = mi->getOperand(DstIdx).getReg();
-  unsigned regB = mi->getOperand(SrcIdx).getReg();
+  MachineInstr &MI = *mi;
+  const MCInstrDesc &MCID = MI.getDesc();
+  unsigned regA = MI.getOperand(DstIdx).getReg();
+  unsigned regB = MI.getOperand(SrcIdx).getReg();
 
   assert(TargetRegisterInfo::isVirtualRegister(regB) &&
          "cannot make instruction into two-address form");
 
   // If regA is dead and the instruction can be deleted, just delete
   // it so it doesn't clobber regB.
-  bool regBKilled = isKilled(*mi, regB, MRI, TII);
-  if (!regBKilled && mi->getOperand(DstIdx).isDead() &&
+  bool regBKilled = isKilled(MI, regB, MRI, TII);
+  if (!regBKilled && MI.getOperand(DstIdx).isDead() &&
       DeleteUnusedInstr(mi, nmi, mbbi, Dist)) {
     ++NumDeletes;
     return true; // Done with this instruction.
@@ -885,20 +1207,20 @@
   unsigned regCIdx = ~0U;
   bool TryCommute = false;
   bool AggressiveCommute = false;
-  if (MCID.isCommutable() && mi->getNumOperands() >= 3 &&
-      TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
+  if (MCID.isCommutable() && MI.getNumOperands() >= 3 &&
+      TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
     if (SrcIdx == SrcOp1)
       regCIdx = SrcOp2;
     else if (SrcIdx == SrcOp2)
       regCIdx = SrcOp1;
 
     if (regCIdx != ~0U) {
-      regC = mi->getOperand(regCIdx).getReg();
-      if (!regBKilled && isKilled(*mi, regC, MRI, TII))
+      regC = MI.getOperand(regCIdx).getReg();
+      if (!regBKilled && isKilled(MI, regC, MRI, TII))
         // If C dies but B does not, swap the B and C operands.
         // This makes the live ranges of A and C joinable.
         TryCommute = true;
-      else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) {
+      else if (isProfitableToCommute(regB, regC, &MI, mbbi, Dist)) {
         TryCommute = true;
         AggressiveCommute = true;
       }
@@ -913,6 +1235,13 @@
     return false;
   }
 
+  // If there is one more use of regB later in the same MBB, consider
+  // re-schedule this MI below it.
+  if (RescheduleMIBelowKill(mbbi, mi, nmi, regB)) {
+    ++NumReSchedDowns;
+    return true;
+  }
+
   if (TargetRegisterInfo::isVirtualRegister(regA))
     ScanUses(regA, &*mbbi, Processed);
 
@@ -928,6 +1257,13 @@
     }
   }
 
+  // If there is one more use of regB later in the same MBB, consider
+  // re-schedule it before this MI if it's legal.
+  if (RescheduleKillAboveMI(mbbi, mi, nmi, regB)) {
+    ++NumReSchedUps;
+    return true;
+  }
+
   // If this is an instruction with a load folded into it, try unfolding
   // the load, e.g. avoid this:
   //   movq %rdx, %rcx
@@ -940,7 +1276,7 @@
     // Determine if a load can be unfolded.
     unsigned LoadRegIndex;
     unsigned NewOpc =
-      TII->getOpcodeAfterMemoryUnfold(mi->getOpcode(),
+      TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
                                       /*UnfoldLoad=*/true,
                                       /*UnfoldStore=*/false,
                                       &LoadRegIndex);
@@ -950,12 +1286,12 @@
         MachineFunction &MF = *mbbi->getParent();
 
         // Unfold the load.
-        DEBUG(dbgs() << "2addr:   UNFOLDING: " << *mi);
+        DEBUG(dbgs() << "2addr:   UNFOLDING: " << MI);
         const TargetRegisterClass *RC =
           TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI);
         unsigned Reg = MRI->createVirtualRegister(RC);
         SmallVector<MachineInstr *, 2> NewMIs;
-        if (!TII->unfoldMemoryOperand(MF, mi, Reg,
+        if (!TII->unfoldMemoryOperand(MF, &MI, Reg,
                                       /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
                                       NewMIs)) {
           DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
@@ -986,21 +1322,21 @@
           // Success, or at least we made an improvement. Keep the unfolded
           // instructions and discard the original.
           if (LV) {
-            for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
-              MachineOperand &MO = mi->getOperand(i);
+            for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
+              MachineOperand &MO = MI.getOperand(i);
               if (MO.isReg() && 
                   TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
                 if (MO.isUse()) {
                   if (MO.isKill()) {
                     if (NewMIs[0]->killsRegister(MO.getReg()))
-                      LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[0]);
+                      LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
                     else {
                       assert(NewMIs[1]->killsRegister(MO.getReg()) &&
                              "Kill missing after load unfold!");
-                      LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[1]);
+                      LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
                     }
                   }
-                } else if (LV->removeVirtualRegisterDead(MO.getReg(), mi)) {
+                } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
                   if (NewMIs[1]->registerDefIsDead(MO.getReg()))
                     LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
                   else {
@@ -1013,7 +1349,7 @@
             }
             LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
           }
-          mi->eraseFromParent();
+          MI.eraseFromParent();
           mi = NewMIs[1];
           if (TransformSuccess)
             return true;
@@ -1040,6 +1376,7 @@
   MRI = &MF.getRegInfo();
   TII = TM.getInstrInfo();
   TRI = TM.getRegisterInfo();
+  InstrItins = TM.getInstrItineraryData();
   LV = getAnalysisIfAvailable<LiveVariables>();
   AA = &getAnalysis<AliasAnalysis>();
 

Modified: llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll?rev=144559&r1=144558&r2=144559&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll (original)
+++ llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll Mon Nov 14 13:48:55 2011
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86-64 -enable-lsr-nested -o %t
 ; RUN: not grep inc %t
 ; RUN: grep dec %t | count 2
-; RUN: grep addq %t | count 10
+; RUN: grep addq %t | count 12
 ; RUN: not grep addb %t
 ; RUN: not grep leal %t
 ; RUN: not grep movq %t

Modified: llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll?rev=144559&r1=144558&r2=144559&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll Mon Nov 14 13:48:55 2011
@@ -4,14 +4,13 @@
 ; Full strength reduction wouldn't reduce register pressure, so LSR should
 ; stick with indexing here.
 
-; FIXME: This is worse off from disabling of scheduler 2-address hack.
 ; CHECK: movaps        (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]]
-; CHECK: leaq  4(%rax), %{{rcx|r9}}
 ; CHECK: cvtdq2ps
 ; CHECK: orps          {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]]
 ; CHECK: movaps        [[X4]], (%{{rdi|rcx}},%rax,4)
-; CHECK: cmpl  %{{ecx|r9d}}, (%{{rdx|r8}})
-; CHECK: jg
+; CHECK: addq  $4, %rax
+; CHECK: cmpl  %eax, (%{{rdx|r8}})
+; CHECK-NEXT: jg
 
 define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind {
 entry:

Modified: llvm/trunk/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=144559&r1=144558&r2=144559&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3.ll Mon Nov 14 13:48:55 2011
@@ -164,12 +164,12 @@
         store <4 x i16> %6, <4 x i16>* @g2, align 8
         ret void
 ; X64: 	t10:
-; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %eax
-; X64: 		movlhps [[X1:%xmm[0-9]+]]
-; X64: 		pshuflw	$8, [[X1]], [[X2:%xmm[0-9]+]]
-; X64: 		pinsrw	$2, %eax, [[X2]]
+; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %ecx
 ; X64: 		pextrw	$6, [[X0]], %eax
-; X64: 		pinsrw	$3, %eax, [[X2]]
+; X64: 		movlhps [[X0]], [[X0]]
+; X64: 		pshuflw	$8, [[X0]], [[X0]]
+; X64: 		pinsrw	$2, %ecx, [[X0]]
+; X64: 		pinsrw	$3, %eax, [[X0]]
 }
 
 
@@ -232,10 +232,9 @@
         %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
         ret <8 x i16> %tmp8
 ; X64: 	t15:
-; X64:          movdqa %xmm0, %xmm2
+; X64: 		pextrw	$7, %xmm0, %eax
 ; X64: 		punpcklqdq	%xmm1, %xmm0
 ; X64: 		pshuflw	$-128, %xmm0, %xmm0
-; X64: 		pextrw	$7, %xmm2, %eax
 ; X64: 		pinsrw	$2, %eax, %xmm0
 ; X64: 		ret
 }
@@ -248,12 +247,11 @@
         %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0,  <16 x i32> < i32 0, i32 1, i32 2, i32 17,  i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
         ret <16 x i8> %tmp9
 ; X64: 	t16:
-; X64: 		movdqa	%xmm1, %xmm2
-; X64: 		pslldq	$2, %xmm2
-; X64: 		movd	%xmm2, %eax
-; X64: 		pinsrw	$0, %eax, %xmm0
-; X64: 		pextrw	$8, %xmm1, %eax
-; X64: 		pextrw	$1, %xmm2, %ecx
+; X64: 		pextrw	$8, %xmm0, %eax
+; X64: 		pslldq	$2, %xmm0
+; X64: 		movd	%xmm0, %ecx
+; X64: 		pextrw	$1, %xmm0, %edx
+; X64: 		pinsrw	$0, %ecx, %xmm0
 ; X64: 		ret
 }
 



From benny.kra at googlemail.com  Mon Nov 14 13:51:48 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Mon, 14 Nov 2011 19:51:48 -0000
Subject: [llvm-commits] [llvm] r144560 -
	/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
Message-ID: <20111114195148.B48922A6C131@llvm.org>

Author: d0k
Date: Mon Nov 14 13:51:48 2011
New Revision: 144560

URL: http://llvm.org/viewvc/llvm-project?rev=144560&view=rev
Log:
Unbreak Release builds.

Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=144560&r1=144559&r2=144560&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Nov 14 13:51:48 2011
@@ -1932,8 +1932,8 @@
     else
       R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
       
-#ifndef NDEBUG
     if (R) {
+#ifndef NDEBUG
       dbgs() << "Call operand #" << i << " has unhandled type "
              << EVT(ArgVT).getEVTString();
 #endif



From tlinth at codeaurora.org  Mon Nov 14 13:47:16 2011
From: tlinth at codeaurora.org (Tony Linthicum)
Date: Mon, 14 Nov 2011 13:47:16 -0600
Subject: [llvm-commits] Patch: new backend for Hexagon processor
Message-ID: <4EC17044.7050807@codeaurora.org>

Hi folks,

I have attached two patches that implement a new backend for Qualcomm's 
VLIW processor, Hexagon. As was suggested, I've broken the contribution 
up into 3 patches: one for llvm changes, one containing new files from 
lib/Target/Hexgon, and one for clang (contained in another e-mail to 
cfe-commits).

I had previously tested the patches with both test-suite and test 
(including a few new Hexagon specific tests) and it passed cleanly.  I 
pulled again on Friday and picked up the new build changes and while I 
have added Hexagon to this mechanism and successfully built, there seems 
to be a problem with generating Hexagon code now.  I will be working on 
correcting this problem, but in the mean time I wanted to go ahead and 
send these patches to begin the review process.

These patches are, obviously, not my work alone.  In addition to myself, 
other members of my team will likely be responding to any questions that 
come up.

Thanks!

Tony

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
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From tlinth at codeaurora.org  Mon Nov 14 13:56:55 2011
From: tlinth at codeaurora.org (Tony Linthicum)
Date: Mon, 14 Nov 2011 13:56:55 -0600
Subject: [llvm-commits] Patch: new backend for Hexagon processor
Message-ID: <4EC17287.3090708@codeaurora.org>

Hi folks,

I have attached two patches that implement a new backend for Qualcomm's 
VLIW processor, Hexagon. As was suggested, I've broken the contribution 
up into 3 patches: one for llvm changes, one containing new files from 
lib/Target/Hexgon, and one for clang (contained in another e-mail to 
cfe-commits).

I had previously tested the patches with both test-suite and test 
(including a few new Hexagon specific tests) and it passed cleanly.  I 
pulled again on Friday and picked up the new build changes and while I 
have added Hexagon to this mechanism and successfully built, there seems 
to be a problem with generating Hexagon code now.  I will be working on 
correcting this problem, but in the mean time I wanted to go ahead and 
send these patches to begin the review process.

I've sent these compressed with bzip2.  If that is inconvenient for 
anyone wishing to review the patches, please let me know and I'll send 
them to you in another format.

These patches are, obviously, not my work alone.  In addition to myself, 
other members of my team will likely be responding to any questions that 
come up.

Thanks!

Tony
-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
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From mcrosier at apple.com  Mon Nov 14 14:22:27 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Mon, 14 Nov 2011 20:22:27 -0000
Subject: [llvm-commits] [llvm] r144565 - in /llvm/trunk:
 lib/Target/ARM/ARMFastISel.cpp
 test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
Message-ID: <20111114202227.8F25C2A6C131@llvm.org>

Author: mcrosier
Date: Mon Nov 14 14:22:27 2011
New Revision: 144565

URL: http://llvm.org/viewvc/llvm-project?rev=144565&view=rev
Log:
Add support for Thumb load/stores with negative offsets.
rdar://10412592


Added:
    llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144565&r1=144564&r2=144565&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Nov 14 14:22:27 2011
@@ -870,12 +870,17 @@
     case MVT::i8:
     case MVT::i16:
     case MVT::i32:
-      if (!useAM3)
+      if (!useAM3) {
         // Integer loads/stores handle 12-bit offsets.
         needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
-      else
+        // Handle negative offsets.
+        if (isThumb2)
+          needsLowering = !(needsLowering && Subtarget->hasV6T2Ops() &&
+                            Addr.Offset < 0 && Addr.Offset > -256);
+      } else {
         // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
         needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
+      }
       break;
     case MVT::f32:
     case MVT::f64:
@@ -967,24 +972,42 @@
     default: return false;
     case MVT::i1:
     case MVT::i8:
-      if (isZExt) {
-        Opc = isThumb2 ? ARM::t2LDRBi12 : ARM::LDRBi12;
+      if (isThumb2) {
+        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
+          Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
+        else
+          Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
       } else {
-        Opc = isThumb2 ? ARM::t2LDRSBi12 : ARM::LDRSB;
-        if (!isThumb2) useAM3 = true;
+        if (isZExt) {
+          Opc = ARM::LDRBi12;
+        } else {
+          Opc = ARM::LDRSB;
+          useAM3 = true;
+        }
       }
       RC = ARM::GPRRegisterClass;
       break;
     case MVT::i16:
-      if (isZExt)
-        Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH;
-      else
-        Opc = isThumb2 ? ARM::t2LDRSHi12 : ARM::LDRSH;
-      if (!isThumb2) useAM3 = true;
+      if (isThumb2) {
+        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
+          Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
+        else
+          Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
+      } else {
+        Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
+        useAM3 = true;
+      }
       RC = ARM::GPRRegisterClass;
       break;
     case MVT::i32:
-      Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
+      if (isThumb2) {
+        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
+          Opc = ARM::t2LDRi8;
+        else
+          Opc = ARM::t2LDRi12;
+      } else {
+        Opc = ARM::LDRi12;
+      }
       RC = ARM::GPRRegisterClass;
       break;
     case MVT::f32:
@@ -1045,14 +1068,35 @@
       SrcReg = Res;
     } // Fallthrough here.
     case MVT::i8:
-      StrOpc = isThumb2 ? ARM::t2STRBi12 : ARM::STRBi12;
+      if (isThumb2) {
+        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
+          StrOpc = ARM::t2STRBi8;
+        else
+          StrOpc = ARM::t2STRBi12;
+      } else {
+        StrOpc = ARM::STRBi12;
+      }
       break;
     case MVT::i16:
-      StrOpc = isThumb2 ? ARM::t2STRHi12 : ARM::STRH;
-      if (!isThumb2) useAM3 = true;
+      if (isThumb2) {
+        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
+          StrOpc = ARM::t2STRHi8;
+        else
+          StrOpc = ARM::t2STRHi12;
+      } else {
+        StrOpc = ARM::STRH;
+        useAM3 = true;
+      }
       break;
     case MVT::i32:
-      StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
+      if (isThumb2) {
+        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
+          StrOpc = ARM::t2STRi8;
+        else
+          StrOpc = ARM::t2STRi12;
+      } else {
+        StrOpc = ARM::STRi12;
+      }
       break;
     case MVT::f32:
       if (!Subtarget->hasVFP2()) return false;

Added: llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll?rev=144565&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll Mon Nov 14 14:22:27 2011
@@ -0,0 +1,168 @@
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
+
+define i32 @t1(i32* nocapture %ptr) nounwind readonly {
+entry:
+; THUMB: t1
+  %add.ptr = getelementptr inbounds i32* %ptr, i32 -1
+  %0 = load i32* %add.ptr, align 4, !tbaa !0
+; THUMB: ldr r{{[0-9]}}, [r0, #-4]
+  ret i32 %0
+}
+
+define i32 @t2(i32* nocapture %ptr) nounwind readonly {
+entry:
+; THUMB: t2
+  %add.ptr = getelementptr inbounds i32* %ptr, i32 -63
+  %0 = load i32* %add.ptr, align 4, !tbaa !0
+; THUMB: ldr r{{[0-9]}}, [r0, #-252]
+  ret i32 %0
+}
+
+define i32 @t3(i32* nocapture %ptr) nounwind readonly {
+entry:
+; THUMB: t3
+  %add.ptr = getelementptr inbounds i32* %ptr, i32 -64
+  %0 = load i32* %add.ptr, align 4, !tbaa !0
+; THUMB: ldr r{{[0-9]}}, [r0]
+  ret i32 %0
+}
+
+define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
+entry:
+; THUMB: t4
+  %add.ptr = getelementptr inbounds i16* %ptr, i32 -1
+  %0 = load i16* %add.ptr, align 2, !tbaa !3
+; THUMB: ldrh r{{[0-9]}}, [r0, #-2]
+  ret i16 %0
+}
+
+define zeroext i16 @t5(i16* nocapture %ptr) nounwind readonly {
+entry:
+; THUMB: t5
+  %add.ptr = getelementptr inbounds i16* %ptr, i32 -127
+  %0 = load i16* %add.ptr, align 2, !tbaa !3
+; THUMB: ldrh r{{[0-9]}}, [r0, #-254]
+  ret i16 %0
+}
+
+define zeroext i16 @t6(i16* nocapture %ptr) nounwind readonly {
+entry:
+; THUMB: t6
+  %add.ptr = getelementptr inbounds i16* %ptr, i32 -128
+  %0 = load i16* %add.ptr, align 2, !tbaa !3
+; THUMB: ldrh r{{[0-9]}}, [r0]
+  ret i16 %0
+}
+
+define zeroext i8 @t7(i8* nocapture %ptr) nounwind readonly {
+entry:
+; THUMB: t7
+  %add.ptr = getelementptr inbounds i8* %ptr, i32 -1
+  %0 = load i8* %add.ptr, align 1, !tbaa !1
+; THUMB: ldrb r{{[0-9]}}, [r0, #-1]
+  ret i8 %0
+}
+
+define zeroext i8 @t8(i8* nocapture %ptr) nounwind readonly {
+entry:
+; THUMB: t8
+  %add.ptr = getelementptr inbounds i8* %ptr, i32 -255
+  %0 = load i8* %add.ptr, align 1, !tbaa !1
+; THUMB: ldrb r{{[0-9]}}, [r0, #-255]
+  ret i8 %0
+}
+
+define zeroext i8 @t9(i8* nocapture %ptr) nounwind readonly {
+entry:
+; THUMB: t9
+  %add.ptr = getelementptr inbounds i8* %ptr, i32 -256
+  %0 = load i8* %add.ptr, align 1, !tbaa !1
+; THUMB: ldrb r{{[0-9]}}, [r0]
+  ret i8 %0
+}
+
+define void @t10(i32* nocapture %ptr) nounwind {
+entry:
+; THUMB: t10
+  %add.ptr = getelementptr inbounds i32* %ptr, i32 -1
+  store i32 0, i32* %add.ptr, align 4, !tbaa !0
+; THUMB: str r{{[0-9]}}, [r0, #-4]
+  ret void
+}
+
+define void @t11(i32* nocapture %ptr) nounwind {
+entry:
+; THUMB: t11
+  %add.ptr = getelementptr inbounds i32* %ptr, i32 -63
+  store i32 0, i32* %add.ptr, align 4, !tbaa !0
+; THUMB: str r{{[0-9]}}, [r0, #-252]
+  ret void
+}
+
+define void @t12(i32* nocapture %ptr) nounwind {
+entry:
+; THUMB: t12
+  %add.ptr = getelementptr inbounds i32* %ptr, i32 -64
+  store i32 0, i32* %add.ptr, align 4, !tbaa !0
+; THUMB: str r{{[0-9]}}, [r0]
+  ret void
+}
+
+define void @t13(i16* nocapture %ptr) nounwind {
+entry:
+; THUMB: t13
+  %add.ptr = getelementptr inbounds i16* %ptr, i32 -1
+  store i16 0, i16* %add.ptr, align 2, !tbaa !3
+; THUMB: strh r{{[0-9]}}, [r0, #-2]
+  ret void
+}
+
+define void @t14(i16* nocapture %ptr) nounwind {
+entry:
+; THUMB: t14
+  %add.ptr = getelementptr inbounds i16* %ptr, i32 -127
+  store i16 0, i16* %add.ptr, align 2, !tbaa !3
+; THUMB: strh r{{[0-9]}}, [r0, #-254]
+  ret void
+}
+
+define void @t15(i16* nocapture %ptr) nounwind {
+entry:
+; THUMB: t15
+  %add.ptr = getelementptr inbounds i16* %ptr, i32 -128
+  store i16 0, i16* %add.ptr, align 2, !tbaa !3
+; THUMB: strh r{{[0-9]}}, [r0]
+  ret void
+}
+
+define void @t16(i8* nocapture %ptr) nounwind {
+entry:
+; THUMB: t16
+  %add.ptr = getelementptr inbounds i8* %ptr, i32 -1
+  store i8 0, i8* %add.ptr, align 1, !tbaa !1
+; THUMB: strb r{{[0-9]}}, [r0, #-1]
+  ret void
+}
+
+define void @t17(i8* nocapture %ptr) nounwind {
+entry:
+; THUMB: t17
+  %add.ptr = getelementptr inbounds i8* %ptr, i32 -255
+  store i8 0, i8* %add.ptr, align 1, !tbaa !1
+; THUMB: strb r{{[0-9]}}, [r0, #-255]
+  ret void
+}
+
+define void @t18(i8* nocapture %ptr) nounwind {
+entry:
+; THUMB: t18
+  %add.ptr = getelementptr inbounds i8* %ptr, i32 -256
+  store i8 0, i8* %add.ptr, align 1, !tbaa !1
+; THUMB: strb r{{[0-9]}}, [r0]
+  ret void
+}
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
+!3 = metadata !{metadata !"short", metadata !1}



From rafael.espindola at gmail.com  Mon Nov 14 14:33:13 2011
From: rafael.espindola at gmail.com (=?UTF-8?Q?Rafael_Esp=C3=ADndola?=)
Date: Mon, 14 Nov 2011 15:33:13 -0500
Subject: [llvm-commits] [patch][pr11202] Handle BB with address taken
 being deleted from codegen
In-Reply-To: <4EA5C453.5050203@mozilla.com>
References: <4EA5C453.5050203@mozilla.com>
Message-ID: <CAG3jReKvN5EXLpuxd11Ym4SHmOhvncFV7sAFcY0BQC79zyan_g@mail.gmail.com>

Both Eli and Joshua pointed out that having to manually call
UpdateForDeletedMachineBlock was error prone.

Eli suggested keeping track of which symbols are used and print the
missing ones at the end. This patch implements this. One nice property
is that it works both for IL and machine code. One problem is that the
labels are printed at the end of the file, not at the start of the
function they would be in. Not sure if that is real problem.

The handling of RAUW still depends on the callback, but fortunately I
don't think we RAUW machine basic blocks.

Cheers,
Rafael
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From evan.cheng at apple.com  Mon Nov 14 14:35:52 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 14 Nov 2011 20:35:52 -0000
Subject: [llvm-commits] [llvm] r144566 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_shuffle-39.ll
Message-ID: <20111114203552.BED6A2A6C131@llvm.org>

Author: evancheng
Date: Mon Nov 14 14:35:52 2011
New Revision: 144566

URL: http://llvm.org/viewvc/llvm-project?rev=144566&view=rev
Log:
Add a missing pattern for X86ISD::MOVLPD. rdar://10436044

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144566&r1=144565&r2=144566&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Nov 14 14:35:52 2011
@@ -520,6 +520,8 @@
   // is during lowering, where it's not possible to recognize the fold cause
   // it has two uses through a bitcast. One use disappears at isel time and the
   // fold opportunity reappears.
+  def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
+            (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
   def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
             (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
   def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
@@ -647,6 +649,9 @@
   // is during lowering, where it's not possible to recognize the fold cause
   // it has two uses through a bitcast. One use disappears at isel time and the
   // fold opportunity reappears.
+  def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
+            (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
+                                                   sub_sd))>;
   def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
             (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
                                                    sub_sd))>;

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll?rev=144566&r1=144565&r2=144566&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll Mon Nov 14 14:35:52 2011
@@ -49,3 +49,21 @@
   store double %2, double* %0
   ret void
 }
+
+; rdar://10436044
+define <2 x double> @t3() nounwind readonly {
+bb:
+; CHECK: t3:
+; CHECK: punpcklqdq %xmm1, %xmm0
+; CHECK: movq (%rax), %xmm1
+; CHECK: movsd %xmm1, %xmm0
+  %tmp0 = load i128* null, align 1
+  %tmp1 = load <2 x i32>* undef, align 8
+  %tmp2 = bitcast i128 %tmp0 to <16 x i8>
+  %tmp3 = bitcast <2 x i32> %tmp1 to i64
+  %tmp4 = insertelement <2 x i64> undef, i64 %tmp3, i32 0
+  %tmp5 = bitcast <16 x i8> %tmp2 to <2 x double>
+  %tmp6 = bitcast <2 x i64> %tmp4 to <2 x double>
+  %tmp7 = shufflevector <2 x double> %tmp5, <2 x double> %tmp6, <2 x i32> <i32 2, i32 1>
+  ret <2 x double> %tmp7
+}



From nicholas at mxc.ca  Mon Nov 14 14:50:16 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 14 Nov 2011 20:50:16 -0000
Subject: [llvm-commits] [llvm] r144567 - in /llvm/trunk:
 include/llvm/Support/ManagedStatic.h include/llvm/Support/Valgrind.h
 lib/Support/ManagedStatic.cpp lib/Support/Valgrind.cpp
 unittests/Support/ManagedStatic.cpp
Message-ID: <20111114205017.10FE92A6C131@llvm.org>

Author: nicholas
Date: Mon Nov 14 14:50:16 2011
New Revision: 144567

URL: http://llvm.org/viewvc/llvm-project?rev=144567&view=rev
Log:
Add support for tsan annotations (thread sanitizer, a valgrind-based tool).
These annotations are disabled entirely when either ENABLE_THREADS is off, or
building a release build. When enabled, they add calls to functions with no
statements to ManagedStatic's getters.

Use these annotations to inform tsan that the race used inside ManagedStatic
initialization is actually benign. Thanks to Kostya Serebryany for helping
write this patch!

Added:
    llvm/trunk/unittests/Support/ManagedStatic.cpp
Modified:
    llvm/trunk/include/llvm/Support/ManagedStatic.h
    llvm/trunk/include/llvm/Support/Valgrind.h
    llvm/trunk/lib/Support/ManagedStatic.cpp
    llvm/trunk/lib/Support/Valgrind.cpp

Modified: llvm/trunk/include/llvm/Support/ManagedStatic.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ManagedStatic.h?rev=144567&r1=144566&r2=144567&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ManagedStatic.h (original)
+++ llvm/trunk/include/llvm/Support/ManagedStatic.h Mon Nov 14 14:50:16 2011
@@ -16,6 +16,7 @@
 
 #include "llvm/Support/Atomic.h"
 #include "llvm/Support/Threading.h"
+#include "llvm/Support/Valgrind.h"
 
 namespace llvm {
 
@@ -65,6 +66,7 @@
     void* tmp = Ptr;
     if (llvm_is_multithreaded()) sys::MemoryFence();
     if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::call);
+    TsanHappensAfter(this);
 
     return *static_cast<C*>(Ptr);
   }
@@ -72,6 +74,7 @@
     void* tmp = Ptr;
     if (llvm_is_multithreaded()) sys::MemoryFence();
     if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::call);
+    TsanHappensAfter(this);
 
     return static_cast<C*>(Ptr);
   }
@@ -79,6 +82,7 @@
     void* tmp = Ptr;
     if (llvm_is_multithreaded()) sys::MemoryFence();
     if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::call);
+    TsanHappensAfter(this);
 
     return *static_cast<C*>(Ptr);
   }
@@ -86,6 +90,7 @@
     void* tmp = Ptr;
     if (llvm_is_multithreaded()) sys::MemoryFence();
     if (!tmp) RegisterManagedStatic(object_creator<C>, object_deleter<C>::call);
+    TsanHappensAfter(this);
 
     return static_cast<C*>(Ptr);
   }

Modified: llvm/trunk/include/llvm/Support/Valgrind.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Valgrind.h?rev=144567&r1=144566&r2=144567&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/Valgrind.h (original)
+++ llvm/trunk/include/llvm/Support/Valgrind.h Mon Nov 14 14:50:16 2011
@@ -16,8 +16,25 @@
 #ifndef LLVM_SYSTEM_VALGRIND_H
 #define LLVM_SYSTEM_VALGRIND_H
 
+#include "llvm/Support/Compiler.h"
+#include "llvm/Config/config.h"
 #include <stddef.h>
 
+#if ENABLE_THREADS != 0 && !defined(NDEBUG)
+// tsan (Thread Sanitizer) is a valgrind-based tool that detects these exact
+// functions by name.
+extern "C" {
+LLVM_ATTRIBUTE_NOINLINE void AnnotateHappensAfter(const char *file, int line,
+                                                  const volatile void *cv);
+LLVM_ATTRIBUTE_NOINLINE void AnnotateHappensBefore(const char *file, int line,
+                                                   const volatile void *cv);
+LLVM_ATTRIBUTE_NOINLINE void AnnotateIgnoreWritesBegin(const char *file,
+                                                       int line);
+LLVM_ATTRIBUTE_NOINLINE void AnnotateIgnoreWritesEnd(const char *file,
+                                                     int line);
+}
+#endif
+
 namespace llvm {
 namespace sys {
   // True if Valgrind is controlling this process.
@@ -26,6 +43,34 @@
   // Discard valgrind's translation of code in the range [Addr .. Addr + Len).
   // Otherwise valgrind may continue to execute the old version of the code.
   void ValgrindDiscardTranslations(const void *Addr, size_t Len);
+
+#if ENABLE_THREADS != 0 && !defined(NDEBUG)
+  // Thread Sanitizer is a valgrind tool that finds races in code.
+  // See http://code.google.com/p/data-race-test/wiki/DynamicAnnotations .
+
+  // This marker is used to define a happens-before arc. The race detector will
+  // infer an arc from the begin to the end when they share the same pointer
+  // argument.
+  #define TsanHappensBefore(cv) \
+    AnnotateHappensBefore(__FILE__, __LINE__, cv)
+
+  // This marker defines the destination of a happens-before arc.
+  #define TsanHappensAfter(cv) \
+    AnnotateHappensAfter(__FILE__, __LINE__, cv)
+
+  // Ignore any races on writes between here and the next TsanIgnoreWritesEnd.
+  #define TsanIgnoreWritesBegin() \
+    AnnotateIgnoreWritesBegin(__FILE__, __LINE__)
+
+  // Resume checking for racy writes.
+  #define TsanIgnoreWritesEnd() \
+    AnnotateIgnoreWritesEnd(__FILE__, __LINE__)
+#else
+  #define TsanHappensBefore(cv)
+  #define TsanHappensAfter(cv)
+  #define TsanIgnoreWritesBegin()
+  #define TsanIgnoreWritesEnd()
+#endif
 }
 }
 

Modified: llvm/trunk/lib/Support/ManagedStatic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/ManagedStatic.cpp?rev=144567&r1=144566&r2=144567&view=diff
==============================================================================
--- llvm/trunk/lib/Support/ManagedStatic.cpp (original)
+++ llvm/trunk/lib/Support/ManagedStatic.cpp Mon Nov 14 14:50:16 2011
@@ -27,8 +27,15 @@
     if (Ptr == 0) {
       void* tmp = Creator ? Creator() : 0;
 
+      TsanHappensBefore(this);
       sys::MemoryFence();
+
+      // This write is racy against the first read in the ManagedStatic
+      // accessors. The race is benign because it does a second read after a
+      // memory fence, at which point it isn't possible to get a partial value.
+      TsanIgnoreWritesBegin();
       Ptr = tmp;
+      TsanIgnoreWritesEnd();
       DeleterFn = Deleter;
       
       // Add to list of managed statics.
@@ -72,4 +79,3 @@
 
   if (llvm_is_multithreaded()) llvm_stop_multithreaded();
 }
-

Modified: llvm/trunk/lib/Support/Valgrind.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Valgrind.cpp?rev=144567&r1=144566&r2=144567&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Valgrind.cpp (original)
+++ llvm/trunk/lib/Support/Valgrind.cpp Mon Nov 14 14:50:16 2011
@@ -52,3 +52,14 @@
 }
 
 #endif  // !HAVE_VALGRIND_VALGRIND_H
+
+// These functions require no implementation, tsan just looks at the arguments
+// they're called with.
+extern "C" {
+void AnnotateHappensBefore(const char *file, int line,
+                           const volatile void *cv) {}
+void AnnotateHappensAfter(const char *file, int line,
+                          const volatile void *cv) {}
+void AnnotateIgnoreWritesBegin(const char *file, int line) {}
+void AnnotateIgnoreWritesEnd(const char *file, int line) {}
+}

Added: llvm/trunk/unittests/Support/ManagedStatic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/ManagedStatic.cpp?rev=144567&view=auto
==============================================================================
--- llvm/trunk/unittests/Support/ManagedStatic.cpp (added)
+++ llvm/trunk/unittests/Support/ManagedStatic.cpp Mon Nov 14 14:50:16 2011
@@ -0,0 +1,39 @@
+//===- llvm/unittest/Support/ManagedStatic.cpp - ManagedStatic tests ------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+#include "llvm/Support/ManagedStatic.h"
+#include "llvm/Support/Threading.h"
+#include <pthread.h>
+
+#include "gtest/gtest.h"
+
+using namespace llvm;
+
+namespace {
+
+namespace test1 {
+  llvm::ManagedStatic<int> ms;
+  void *helper(void*) {
+    *ms;
+    return NULL;
+  }
+}
+
+TEST(Initialize, MultipleThreads) {
+  // Run this test under tsan: http://code.google.com/p/data-race-test/
+
+  llvm_start_multithreaded();
+  pthread_t t1, t2;
+  pthread_create(&t1, NULL, test1::helper, NULL);
+  pthread_create(&t2, NULL, test1::helper, NULL);
+  pthread_join(t1, NULL);
+  pthread_join(t2, NULL);
+  llvm_stop_multithreaded();
+}
+
+} // anonymous namespace



From eli.friedman at gmail.com  Mon Nov 14 14:54:36 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 14 Nov 2011 12:54:36 -0800
Subject: [llvm-commits] Patch: new backend for Hexagon processor
In-Reply-To: <4EC17287.3090708@codeaurora.org>
References: <4EC17287.3090708@codeaurora.org>
Message-ID: <CAJdarcFKL91HwSttsQTcd8FkSaoT7Tz8Jxw1JBmESLo=kjOrpQ@mail.gmail.com>

On Mon, Nov 14, 2011 at 11:56 AM, Tony Linthicum <tlinth at codeaurora.org> wrote:
> Hi folks,
>
> I have attached two patches that implement a new backend for Qualcomm's VLIW
> processor, Hexagon. As was suggested, I've broken the contribution up into 3
> patches: one for llvm changes, one containing new files from
> lib/Target/Hexgon, and one for clang (contained in another e-mail to
> cfe-commits).
>
> I had previously tested the patches with both test-suite and test (including
> a few new Hexagon specific tests) and it passed cleanly. ?I pulled again on
> Friday and picked up the new build changes and while I have added Hexagon to
> this mechanism and successfully built, there seems to be a problem with
> generating Hexagon code now. ?I will be working on correcting this problem,
> but in the mean time I wanted to go ahead and send these patches to begin
> the review process.
>
> I've sent these compressed with bzip2. ?If that is inconvenient for anyone
> wishing to review the patches, please let me know and I'll send them to you
> in another format.
>
> These patches are, obviously, not my work alone. ?In addition to myself,
> other members of my team will likely be responding to any questions that
> come up.
>
> Thanks!

Just took a look over the LLVM changes outside your target.

You have a *lot* of builtins, but there isn't really much to say about
that, beyond "do all these builtins represent something which can't be
represented in IR otherwise?".

--- a/include/llvm/InitializePasses.h
+++ b/include/llvm/InitializePasses.h
@@ -233,6 +233,7 @@ void initializeVerifierPass(PassRegistry&);
 void initializeVirtRegMapPass(PassRegistry&);
 void initializeInstSimplifierPass(PassRegistry&);

+void initializeHexagonHardwareLoopsPass(PassRegistry&);
 }

 #endif

This change shouldn't be necessary; only target-independent passes
need to be listed here, IIRC.

Your changes to add Data128bitsDirective etc. seem a bit confused...
".uleb128" is not a 128-bit integer in the sense you're using it.
Also, please separate out the MC changes into a separate patch;
they're interesting changes mixed into a bunch of mechanical changes,
and it would be nice to have more eyes on them.

-Eli


From eli.friedman at gmail.com  Mon Nov 14 15:03:37 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Mon, 14 Nov 2011 13:03:37 -0800
Subject: [llvm-commits] [patch][pr11202] Handle BB with address taken
 being deleted from codegen
In-Reply-To: <CAG3jReKvN5EXLpuxd11Ym4SHmOhvncFV7sAFcY0BQC79zyan_g@mail.gmail.com>
References: <4EA5C453.5050203@mozilla.com>
	<CAG3jReKvN5EXLpuxd11Ym4SHmOhvncFV7sAFcY0BQC79zyan_g@mail.gmail.com>
Message-ID: <CAJdarcFUC+d4mBZjxCC4HWHYEnoH-EnVyHafTirx-iC4H17EHg@mail.gmail.com>

2011/11/14 Rafael Esp?ndola <rafael.espindola at gmail.com>:
> Both Eli and Joshua pointed out that having to manually call
> UpdateForDeletedMachineBlock was error prone.
>
> Eli suggested keeping track of which symbols are used and print the
> missing ones at the end. This patch implements this. One nice property
> is that it works both for IL and machine code. One problem is that the
> labels are printed at the end of the file, not at the start of the
> function they would be in. Not sure if that is real problem.

Might be an issue: we could end up with bad relocations if the labels
end up in the wrong section.

> The handling of RAUW still depends on the callback, but fortunately I
> don't think we RAUW machine basic blocks.

MBB's don't have use lists; not sure what RAUW'ing one would mean.

-Eli


From evan.cheng at apple.com  Mon Nov 14 15:02:09 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 14 Nov 2011 21:02:09 -0000
Subject: [llvm-commits] [llvm] r144568 -
	/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
Message-ID: <20111114210209.79C882A6C131@llvm.org>

Author: evancheng
Date: Mon Nov 14 15:02:09 2011
New Revision: 144568

URL: http://llvm.org/viewvc/llvm-project?rev=144568&view=rev
Log:
At -O0, multiple uses of a virtual registers in the same BB are being marked
"kill". This looks like a bug upstream. Since that's going to take some time
to understand, loosen the assertion and disable the optimization when
multiple kills are seen.

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=144568&r1=144567&r2=144568&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon Nov 14 15:02:09 2011
@@ -502,7 +502,8 @@
       continue;
     if (!UI.getOperand().isKill())
       return 0;
-    assert(!KillMI && "More than one local kills?");
+    if (KillMI)
+      return 0;  // -O0 kill markers cannot be trusted?
     KillMI = UseMI;
   }
 



From evan.cheng at apple.com  Mon Nov 14 15:11:15 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 14 Nov 2011 21:11:15 -0000
Subject: [llvm-commits] [llvm] r144569 -
	/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
Message-ID: <20111114211115.902312A6C131@llvm.org>

Author: evancheng
Date: Mon Nov 14 15:11:15 2011
New Revision: 144569

URL: http://llvm.org/viewvc/llvm-project?rev=144569&view=rev
Log:
Avoid dereferencing off the beginning of lists.

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=144569&r1=144568&r2=144569&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon Nov 14 15:11:15 2011
@@ -999,10 +999,8 @@
   }
 
   // Move debug info as well.
-  if (From != MBB->begin()) {
-    while (llvm::prior(From)->isDebugValue())
-      --From;
-  }
+  while (From != MBB->begin() && llvm::prior(From)->isDebugValue())
+    --From;
 
   // Copies following MI may have been moved as well.
   nmi = To;
@@ -1146,9 +1144,8 @@
 
   // Move the old kill above MI, don't forget to move debug info as well.
   MachineBasicBlock::iterator InsertPos = mi;
-  if (InsertPos != MBB->begin())
-    while (llvm::prior(InsertPos)->isDebugValue())
-      --InsertPos;
+  while (InsertPos != MBB->begin() && llvm::prior(InsertPos)->isDebugValue())
+    --InsertPos;
   MachineBasicBlock::iterator From = KillMI;
   MachineBasicBlock::iterator To = llvm::next(From);
   while (llvm::prior(From)->isDebugValue())



From tlinth at codeaurora.org  Mon Nov 14 15:36:45 2011
From: tlinth at codeaurora.org (Tony Linthicum)
Date: Mon, 14 Nov 2011 15:36:45 -0600
Subject: [llvm-commits] Patch: new backend for Hexagon processor
In-Reply-To: <CAJdarcFKL91HwSttsQTcd8FkSaoT7Tz8Jxw1JBmESLo=kjOrpQ@mail.gmail.com>
References: <4EC17287.3090708@codeaurora.org>
	<CAJdarcFKL91HwSttsQTcd8FkSaoT7Tz8Jxw1JBmESLo=kjOrpQ@mail.gmail.com>
Message-ID: <4EC189ED.7090406@codeaurora.org>

On 11/14/2011 2:54 PM, Eli Friedman wrote:

>
> Just took a look over the LLVM changes outside your target.
>
> You have a *lot* of builtins, but there isn't really much to say about
> that, beyond "do all these builtins represent something which can't be
> represented in IR otherwise?".
>

See my response to your e-mail on cfe-commits.

> Also, please separate out the MC changes into a separate patch;
> they're interesting changes mixed into a bunch of mechanical changes,
> and it would be nice to have more eyes on them.
>

No problem.  I'll get that sent out by tomorrow.

Thanks.

Tony


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.

From nicholas at mxc.ca  Mon Nov 14 16:10:23 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 14 Nov 2011 22:10:23 -0000
Subject: [llvm-commits] [llvm] r144574 -
	/llvm/trunk/unittests/Support/ManagedStatic.cpp
Message-ID: <20111114221023.53AF02A6C131@llvm.org>

Author: nicholas
Date: Mon Nov 14 16:10:23 2011
New Revision: 144574

URL: http://llvm.org/viewvc/llvm-project?rev=144574&view=rev
Log:
Fix Windows build, don't try to #include <pthread.h> when we know it's not
available.

Modified:
    llvm/trunk/unittests/Support/ManagedStatic.cpp

Modified: llvm/trunk/unittests/Support/ManagedStatic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/ManagedStatic.cpp?rev=144574&r1=144573&r2=144574&view=diff
==============================================================================
--- llvm/trunk/unittests/Support/ManagedStatic.cpp (original)
+++ llvm/trunk/unittests/Support/ManagedStatic.cpp Mon Nov 14 16:10:23 2011
@@ -8,7 +8,10 @@
 //===----------------------------------------------------------------------===//
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Threading.h"
+#include "llvm/Config/config.h"
+#ifdef HAVE_PTHREAD_H
 #include <pthread.h>
+#endif
 
 #include "gtest/gtest.h"
 
@@ -16,6 +19,7 @@
 
 namespace {
 
+#ifdef HAVE_PTHREAD_H
 namespace test1 {
   llvm::ManagedStatic<int> ms;
   void *helper(void*) {
@@ -35,5 +39,6 @@
   pthread_join(t2, NULL);
   llvm_stop_multithreaded();
 }
+#endif
 
 } // anonymous namespace



From grosbach at apple.com  Mon Nov 14 16:28:39 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 14 Nov 2011 22:28:39 -0000
Subject: [llvm-commits] [llvm] r144575 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrVFP.td
Message-ID: <20111114222839.BC5E12A6C131@llvm.org>

Author: grosbach
Date: Mon Nov 14 16:28:39 2011
New Revision: 144575

URL: http://llvm.org/viewvc/llvm-project?rev=144575&view=rev
Log:
ARM assembly parsing type suffix options for VLDR/VSTR.

rdar://10435076

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=144575&r1=144574&r2=144575&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 14 16:28:39 2011
@@ -1991,3 +1991,22 @@
 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
   list<Predicate> Predicates = [HasNEON,UseNEONForFP];
 }
+
+// VFP/NEON Instruction aliases for type suffices.
+class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
+  InstAlias<!strconcat(opc, dt, asm), Result>;
+multiclass VFPDT32InstAlias<string opc, string asm, dag Result> {
+  def I32 : VFPDataTypeInstAlias<opc, ".i32", asm, Result>;
+  def S32 : VFPDataTypeInstAlias<opc, ".s32", asm, Result>;
+  def U32 : VFPDataTypeInstAlias<opc, ".u32", asm, Result>;
+  def F32 : VFPDataTypeInstAlias<opc, ".f32", asm, Result>;
+  def F   : VFPDataTypeInstAlias<opc, ".f",   asm, Result>;
+}
+multiclass VFPDT64InstAlias<string opc, string asm, dag Result> {
+  def I64 : VFPDataTypeInstAlias<opc, ".i64", asm, Result>;
+  def S64 : VFPDataTypeInstAlias<opc, ".s64", asm, Result>;
+  def U64 : VFPDataTypeInstAlias<opc, ".u64", asm, Result>;
+  def F64 : VFPDataTypeInstAlias<opc, ".f64", asm, Result>;
+  def D   : VFPDataTypeInstAlias<opc, ".d",   asm, Result>;
+}
+

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=144575&r1=144574&r2=144575&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Nov 14 16:28:39 2011
@@ -1172,3 +1172,12 @@
                     (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
 def : VFP2InstAlias<"vstr$p $Sd, $addr",
                     (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
+// The suffix can also by typed.
+defm : VFPDT32InstAlias<"vldr$p", "$Sd, $addr",
+                        (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
+defm : VFPDT32InstAlias<"vstr$p", "$Sd, $addr",
+                        (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
+defm : VFPDT64InstAlias<"vldr$p", "$Dd, $addr",
+                        (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
+defm : VFPDT64InstAlias<"vstr$p", "$Dd, $addr",
+                        (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;



From spop at codeaurora.org  Mon Nov 14 16:36:47 2011
From: spop at codeaurora.org (Sebastian Pop)
Date: Mon, 14 Nov 2011 16:36:47 -0600
Subject: [llvm-commits] Patch: new backend for Hexagon processor
In-Reply-To: <4EC17044.7050807@codeaurora.org>
References: <4EC17044.7050807@codeaurora.org>
Message-ID: <CAE5reQL4vD5jw3fQOYDhFZD4JVZhy+L__jV1PrysySQbyu6fKA@mail.gmail.com>

Hi Tony,

I see that there are quite some #if 0 sections left.
Could you please remove this dead code?

Thanks,
Sebastian
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

From mcrosier at apple.com  Mon Nov 14 16:34:49 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Mon, 14 Nov 2011 22:34:49 -0000
Subject: [llvm-commits] [llvm] r144576 - in /llvm/trunk:
 lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
Message-ID: <20111114223449.35BCF2A6C131@llvm.org>

Author: mcrosier
Date: Mon Nov 14 16:34:48 2011
New Revision: 144576

URL: http://llvm.org/viewvc/llvm-project?rev=144576&view=rev
Log:
Fix a performance regression from r144565. Positive offsets were being lowered
into registers, rather then encoded directly in the load/store.

Added:
    llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144576&r1=144575&r2=144576&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Nov 14 16:34:48 2011
@@ -874,9 +874,9 @@
         // Integer loads/stores handle 12-bit offsets.
         needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
         // Handle negative offsets.
-        if (isThumb2)
-          needsLowering = !(needsLowering && Subtarget->hasV6T2Ops() &&
-                            Addr.Offset < 0 && Addr.Offset > -256);
+        if (needsLowering && isThumb2)
+          needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
+                            Addr.Offset > -256);
       } else {
         // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
         needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);

Added: llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll?rev=144576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll Mon Nov 14 16:34:48 2011
@@ -0,0 +1,55 @@
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
+
+define i32 @t1(i32* nocapture %ptr) nounwind readonly {
+entry:
+; ARM: t1
+  %add.ptr = getelementptr inbounds i32* %ptr, i32 1
+  %0 = load i32* %add.ptr, align 4
+; ARM: ldr r{{[0-9]}}, [r0, #4]
+  ret i32 %0
+}
+
+define i32 @t2(i32* nocapture %ptr) nounwind readonly {
+entry:
+; ARM: t2
+  %add.ptr = getelementptr inbounds i32* %ptr, i32 63
+  %0 = load i32* %add.ptr, align 4
+; ARM: ldr.w r{{[0-9]}}, [r0, #252]
+  ret i32 %0
+}
+
+define zeroext i16 @t3(i16* nocapture %ptr) nounwind readonly {
+entry:
+; ARM: t3
+  %add.ptr = getelementptr inbounds i16* %ptr, i16 1
+  %0 = load i16* %add.ptr, align 4
+; ARM: ldrh r{{[0-9]}}, [r0, #2]
+  ret i16 %0
+}
+
+define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
+entry:
+; ARM: t4
+  %add.ptr = getelementptr inbounds i16* %ptr, i16 63
+  %0 = load i16* %add.ptr, align 4
+; ARM: ldrh.w r{{[0-9]}}, [r0, #126]
+  ret i16 %0
+}
+
+define zeroext i8 @t5(i8* nocapture %ptr) nounwind readonly {
+entry:
+; ARM: t5
+  %add.ptr = getelementptr inbounds i8* %ptr, i8 1
+  %0 = load i8* %add.ptr, align 4
+; ARM: ldrb r{{[0-9]}}, [r0, #1]
+  ret i8 %0
+}
+
+define zeroext i8 @t6(i8* nocapture %ptr) nounwind readonly {
+entry:
+; ARM: t6
+  %add.ptr = getelementptr inbounds i8* %ptr, i8 63
+  %0 = load i8* %add.ptr, align 4
+; ARM: ldrb.w r{{[0-9]}}, [r0, #63]
+  ret i8 %0
+}
\ No newline at end of file



From mcrosier at apple.com  Mon Nov 14 16:46:17 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Mon, 14 Nov 2011 22:46:17 -0000
Subject: [llvm-commits] [llvm] r144578 - in /llvm/trunk:
 lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel-intrinsic.ll
Message-ID: <20111114224617.545982A6C131@llvm.org>

Author: mcrosier
Date: Mon Nov 14 16:46:17 2011
New Revision: 144578

URL: http://llvm.org/viewvc/llvm-project?rev=144578&view=rev
Log:
Add support for inlining small memcpys.
rdar://10412592

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
    llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144578&r1=144577&r2=144578&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Nov 14 16:46:17 2011
@@ -185,6 +185,9 @@
     bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
     bool ARMComputeAddress(const Value *Obj, Address &Addr);
     void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
+    bool ARMIsMemXferSmall(uint64_t Len);
+    bool ARMTryEmitSmallMemXfer(Address Dest, Address Src, uint64_t Len,
+                                bool isMemCpy);
     unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
     unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
     unsigned ARMMaterializeInt(const Constant *C, EVT VT);
@@ -2193,18 +2196,76 @@
   return true;
 }
 
+bool ARMFastISel::ARMIsMemXferSmall(uint64_t Len) {
+  return Len <= 16;
+}
+
+bool ARMFastISel::ARMTryEmitSmallMemXfer(Address Dest, Address Src, uint64_t Len,
+                                         bool isMemCpy) {
+  // FIXME: Memmove's require a little more care because their source and
+  // destination may overlap.
+  if (!isMemCpy)
+    return false;
+
+  // Make sure we don't bloat code by inlining very large memcpy's.
+  if (!ARMIsMemXferSmall(Len))
+    return false;
+
+  // We don't care about alignment here since we just emit integer accesses.
+  while (Len) {
+    MVT VT;
+    if (Len >= 4)
+      VT = MVT::i32;
+    else if (Len >= 2)
+      VT = MVT::i16;
+    else {
+      assert(Len == 1);
+      VT = MVT::i8;
+    }
+
+    bool RV;
+    unsigned ResultReg;
+    RV = ARMEmitLoad(VT, ResultReg, Src);
+    assert (RV = true && "Should be able to handle this load.");
+    RV = ARMEmitStore(VT, ResultReg, Dest);
+    assert (RV = true && "Should be able to handle this store.");
+
+    unsigned Size = VT.getSizeInBits()/8;
+    Len -= Size;
+    Dest.Offset += Size;
+    Src.Offset += Size;
+  }
+
+  return true;
+}
+
 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
   // FIXME: Handle more intrinsics.
   switch (I.getIntrinsicID()) {
   default: return false;
   case Intrinsic::memcpy:
   case Intrinsic::memmove: {
-    // FIXME: Small memcpy/memmove's are common enough that we want to do them
-    // without a call if possible.
     const MemTransferInst &MTI = cast<MemTransferInst>(I);
     // Don't handle volatile.
     if (MTI.isVolatile())
       return false;
+
+    // Disable inlining for memmove before calls to ComputeAddress.  Otherwise,
+    // we would emit dead code because we don't currently handle memmoves.
+    bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
+    if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
+      // Small memcpy/memmove's are common enough that we want to do them
+      // without a call if possible.
+      uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
+      if (ARMIsMemXferSmall(Len)) {
+        Address Dest, Src;
+        if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
+            !ARMComputeAddress(MTI.getRawSource(), Src))
+          return false;
+        if (ARMTryEmitSmallMemXfer(Dest, Src, Len, isMemCpy))
+          return true;
+      }
+    }
     
     if (!MTI.getLength()->getType()->isIntegerTy(32))
       return false;

Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll?rev=144578&r1=144577&r2=144578&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-intrinsic.ll Mon Nov 14 16:46:17 2011
@@ -33,7 +33,7 @@
 ; ARM: ldr r0, [r0]
 ; ARM: add r1, r0, #4
 ; ARM: add r0, r0, #16
-; ARM: movw r2, #10
+; ARM: movw r2, #17
 ; ARM: str r0, [sp]                @ 4-byte Spill
 ; ARM: mov r0, r1
 ; ARM: ldr r1, [sp]                @ 4-byte Reload
@@ -43,11 +43,11 @@
 ; THUMB: ldr r0, [r0]
 ; THUMB: adds r1, r0, #4
 ; THUMB: adds r0, #16
-; THUMB: movs r2, #10
+; THUMB: movs r2, #17
 ; THUMB: movt r2, #0
 ; THUMB: mov r0, r1
 ; THUMB: bl _memcpy
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 17, i32 1, i1 false)
   ret void
 }
 
@@ -75,4 +75,32 @@
   ret void
 }
 
+define void @t4() nounwind ssp {
+; ARM: t4
+; ARM: ldr r0, LCPI3_0
+; ARM: ldr r0, [r0]
+; ARM: ldr r1, LCPI3_1
+; ARM: ldr r1, [r1]
+; ARM: ldr r2, [r1, #16]
+; ARM: str r2, [r0, #4]
+; ARM: ldr r2, [r1, #20]
+; ARM: str r2, [r0, #8]
+; ARM: ldrh r1, [r1, #24]
+; ARM: strh r1, [r0, #12]
+; ARM: bx lr
+; THUMB: ldr.n r0, LCPI3_0
+; THUMB: ldr r0, [r0]
+; THUMB: ldr.n r1, LCPI3_1
+; THUMB: ldr r1, [r1]
+; THUMB: ldr r2, [r1, #16]
+; THUMB: str r2, [r0, #4]
+; THUMB: ldr r2, [r1, #20]
+; THUMB: str r2, [r0, #8]
+; THUMB: ldrh r1, [r1, #24]
+; THUMB: strh r1, [r0, #12]
+; THUMB: bx lr
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 4), i8* getelementptr inbounds ([60 x i8]* @temp, i32 0, i32 16), i32 10, i32 1, i1 false)
+  ret void
+}
+
 declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind



From mcrosier at apple.com  Mon Nov 14 16:48:33 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Mon, 14 Nov 2011 22:48:33 -0000
Subject: [llvm-commits] [llvm] r144579 -
	/llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
Message-ID: <20111114224834.0472B2A6C131@llvm.org>

Author: mcrosier
Date: Mon Nov 14 16:48:33 2011
New Revision: 144579

URL: http://llvm.org/viewvc/llvm-project?rev=144579&view=rev
Log:
Add newline to end of file.  Thanks, Eli.

Modified:
    llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll

Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll?rev=144579&r1=144578&r2=144579&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll Mon Nov 14 16:48:33 2011
@@ -52,4 +52,4 @@
   %0 = load i8* %add.ptr, align 4
 ; ARM: ldrb.w r{{[0-9]}}, [r0, #63]
   ret i8 %0
-}
\ No newline at end of file
+}



From nicholas at mxc.ca  Mon Nov 14 16:49:42 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 14 Nov 2011 22:49:42 -0000
Subject: [llvm-commits] [llvm] r144580 - in /llvm/trunk:
 include/llvm/Analysis/CaptureTracking.h
 include/llvm/Analysis/MemoryDependenceAnalysis.h
 lib/Analysis/CaptureTracking.cpp lib/Analysis/MemoryDependenceAnalysis.cpp
 test/Transforms/GVN/rle.ll
Message-ID: <20111114224942.B52192A6C131@llvm.org>

Author: nicholas
Date: Mon Nov 14 16:49:42 2011
New Revision: 144580

URL: http://llvm.org/viewvc/llvm-project?rev=144580&view=rev
Log:
Refactor capture tracking (which already had a couple flags for whether returns
and stores capture) to permit the caller to see each capture point and decide
whether to continue looking.

Use this inside memdep to do an analysis that basicaa won't do. This lets us
solve another devirtualization case, fixing PR8908!

Modified:
    llvm/trunk/include/llvm/Analysis/CaptureTracking.h
    llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
    llvm/trunk/lib/Analysis/CaptureTracking.cpp
    llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
    llvm/trunk/test/Transforms/GVN/rle.ll

Modified: llvm/trunk/include/llvm/Analysis/CaptureTracking.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CaptureTracking.h?rev=144580&r1=144579&r2=144580&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/CaptureTracking.h (original)
+++ llvm/trunk/include/llvm/Analysis/CaptureTracking.h Mon Nov 14 16:49:42 2011
@@ -14,9 +14,14 @@
 #ifndef LLVM_ANALYSIS_CAPTURETRACKING_H
 #define LLVM_ANALYSIS_CAPTURETRACKING_H
 
-namespace llvm {
-  class Value;
+#include "llvm/Constants.h"
+#include "llvm/Instructions.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/CallSite.h"
 
+namespace llvm {
   /// PointerMayBeCaptured - Return true if this pointer value may be captured
   /// by the enclosing function (which is required to exist).  This routine can
   /// be expensive, so consider caching the results.  The boolean ReturnCaptures
@@ -28,6 +33,132 @@
                             bool ReturnCaptures,
                             bool StoreCaptures);
 
+  /// PointerMayBeCaptured - Visit the value and the values derived from it and
+  /// find values which appear to be capturing the pointer value. This feeds
+  /// results into and is controlled by the templated CaptureTracker object:
+  ///
+  /// struct YourCaptureTracker {
+  ///   /// tooManyUses - The depth of traversal has breached a limit.
+  ///   /// The tracker should conservatively assume that the value is captured.
+  ///   void tooManyUses();
+  ///
+  ///   /// shouldExplore - This is the use of a value derived from the pointer.
+  ///   /// Return false to prune the search (ie., assume that none of its users
+  ///   /// could possibly capture) return false. To search it, return true.
+  ///   ///
+  ///   /// Also, U->getUser() is guaranteed to be an Instruction.
+  ///   bool shouldExplore(Use *U);
+  ///
+  ///   /// captured - The instruction I captured the pointer. Return true to
+  ///   /// stop the traversal or false to continue looking for more capturing
+  ///   /// instructions.
+  ///   bool captured(Instruction *I);
+  ///
+  ///   /// Provide your own getters for the state.
+  /// };
+  template<typename CaptureTracker>
+  void PointerMayBeCaptured(const Value *V, CaptureTracker &Tracker);
 } // end namespace llvm
 
+template<typename CaptureTracker>
+void llvm::PointerMayBeCaptured(const llvm::Value *V, CaptureTracker &Tracker) {
+  assert(V->getType()->isPointerTy() && "Capture is for pointers only!");
+  SmallVector<Use*, 20> Worklist;
+  SmallSet<Use*, 20> Visited;
+  int Count = 0;
+
+  for (Value::const_use_iterator UI = V->use_begin(), UE = V->use_end();
+       UI != UE; ++UI) {
+    // If there are lots of uses, conservatively say that the value
+    // is captured to avoid taking too much compile time.
+    if (Count++ >= 20)
+      return Tracker.tooManyUses();
+
+    Use *U = &UI.getUse();
+    if (!Tracker.shouldExplore(U)) continue;
+    Visited.insert(U);
+    Worklist.push_back(U);
+  }
+
+  while (!Worklist.empty()) {
+    Use *U = Worklist.pop_back_val();
+    Instruction *I = cast<Instruction>(U->getUser());
+    V = U->get();
+
+    switch (I->getOpcode()) {
+    case Instruction::Call:
+    case Instruction::Invoke: {
+      CallSite CS(I);
+      // Not captured if the callee is readonly, doesn't return a copy through
+      // its return value and doesn't unwind (a readonly function can leak bits
+      // by throwing an exception or not depending on the input value).
+      if (CS.onlyReadsMemory() && CS.doesNotThrow() && I->getType()->isVoidTy())
+        break;
+
+      // Not captured if only passed via 'nocapture' arguments.  Note that
+      // calling a function pointer does not in itself cause the pointer to
+      // be captured.  This is a subtle point considering that (for example)
+      // the callee might return its own address.  It is analogous to saying
+      // that loading a value from a pointer does not cause the pointer to be
+      // captured, even though the loaded value might be the pointer itself
+      // (think of self-referential objects).
+      CallSite::arg_iterator B = CS.arg_begin(), E = CS.arg_end();
+      for (CallSite::arg_iterator A = B; A != E; ++A)
+        if (A->get() == V && !CS.paramHasAttr(A - B + 1, Attribute::NoCapture))
+          // The parameter is not marked 'nocapture' - captured.
+          if (Tracker.captured(I))
+            return;
+      break;
+    }
+    case Instruction::Load:
+      // Loading from a pointer does not cause it to be captured.
+      break;
+    case Instruction::VAArg:
+      // "va-arg" from a pointer does not cause it to be captured.
+      break;
+    case Instruction::Store:
+      if (V == I->getOperand(0))
+        // Stored the pointer - conservatively assume it may be captured.
+        if (Tracker.captured(I))
+          return;
+      // Storing to the pointee does not cause the pointer to be captured.
+      break;
+    case Instruction::BitCast:
+    case Instruction::GetElementPtr:
+    case Instruction::PHI:
+    case Instruction::Select:
+      // The original value is not captured via this if the new value isn't.
+      for (Instruction::use_iterator UI = I->use_begin(), UE = I->use_end();
+           UI != UE; ++UI) {
+        Use *U = &UI.getUse();
+        if (Visited.insert(U))
+          if (Tracker.shouldExplore(U))
+            Worklist.push_back(U);
+      }
+      break;
+    case Instruction::ICmp:
+      // Don't count comparisons of a no-alias return value against null as
+      // captures. This allows us to ignore comparisons of malloc results
+      // with null, for example.
+      if (isNoAliasCall(V->stripPointerCasts()))
+        if (ConstantPointerNull *CPN =
+              dyn_cast<ConstantPointerNull>(I->getOperand(1)))
+          if (CPN->getType()->getAddressSpace() == 0)
+            break;
+      // Otherwise, be conservative. There are crazy ways to capture pointers
+      // using comparisons.
+      if (Tracker.captured(I))
+        return;
+      break;
+    default:
+      // Something else - be conservative and say it is captured.
+      if (Tracker.captured(I))
+        return;
+      break;
+    }
+  }
+
+  // All uses examined.
+}
+
 #endif

Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h?rev=144580&r1=144579&r2=144580&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h (original)
+++ llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Mon Nov 14 16:49:42 2011
@@ -324,6 +324,7 @@
     /// Current AA implementation, just a cache.
     AliasAnalysis *AA;
     TargetData *TD;
+    DominatorTree *DT;
     OwningPtr<PredIteratorCache> PredCache;
   public:
     MemoryDependenceAnalysis();
@@ -430,6 +431,9 @@
 
     void RemoveCachedNonLocalPointerDependencies(ValueIsLoadPair P);
     
+    AliasAnalysis::ModRefResult
+    getModRefInfo(const Instruction *Inst, const AliasAnalysis::Location &Loc);
+
     /// verifyRemoved - Verify that the specified instruction does not occur
     /// in our internal data structures.
     void verifyRemoved(Instruction *Inst) const;

Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=144580&r1=144579&r2=144580&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Mon Nov 14 16:49:42 2011
@@ -17,24 +17,30 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Analysis/CaptureTracking.h"
-#include "llvm/Constants.h"
-#include "llvm/Instructions.h"
-#include "llvm/Value.h"
-#include "llvm/Analysis/AliasAnalysis.h"
-#include "llvm/ADT/SmallSet.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/Support/CallSite.h"
 using namespace llvm;
 
-/// As its comment mentions, PointerMayBeCaptured can be expensive.
-/// However, it's not easy for BasicAA to cache the result, because
-/// it's an ImmutablePass. To work around this, bound queries at a
-/// fixed number of uses.
-///
-/// TODO: Write a new FunctionPass AliasAnalysis so that it can keep
-/// a cache. Then we can move the code from BasicAliasAnalysis into
-/// that path, and remove this threshold.
-static int const Threshold = 20;
+namespace {
+  struct SimpleCaptureTracker {
+    explicit SimpleCaptureTracker(bool ReturnCaptures)
+      : ReturnCaptures(ReturnCaptures), Captured(false) {}
+
+    void tooManyUses() { Captured = true; }
+
+    bool shouldExplore(Use *U) { return true; }
+
+    bool captured(Instruction *I) {
+      if (isa<ReturnInst>(I) && !ReturnCaptures)
+	return false;
+
+      Captured = true;
+      return true;
+    }
+
+    bool ReturnCaptures;
+
+    bool Captured;
+  };
+}
 
 /// PointerMayBeCaptured - Return true if this pointer value may be captured
 /// by the enclosing function (which is required to exist).  This routine can
@@ -45,104 +51,13 @@
 /// counts as capturing it or not.
 bool llvm::PointerMayBeCaptured(const Value *V,
                                 bool ReturnCaptures, bool StoreCaptures) {
-  assert(V->getType()->isPointerTy() && "Capture is for pointers only!");
-  SmallVector<Use*, Threshold> Worklist;
-  SmallSet<Use*, Threshold> Visited;
-  int Count = 0;
-
-  for (Value::const_use_iterator UI = V->use_begin(), UE = V->use_end();
-       UI != UE; ++UI) {
-    // If there are lots of uses, conservatively say that the value
-    // is captured to avoid taking too much compile time.
-    if (Count++ >= Threshold)
-      return true;
-
-    Use *U = &UI.getUse();
-    Visited.insert(U);
-    Worklist.push_back(U);
-  }
-
-  while (!Worklist.empty()) {
-    Use *U = Worklist.pop_back_val();
-    Instruction *I = cast<Instruction>(U->getUser());
-    V = U->get();
-
-    switch (I->getOpcode()) {
-    case Instruction::Call:
-    case Instruction::Invoke: {
-      CallSite CS(I);
-      // Not captured if the callee is readonly, doesn't return a copy through
-      // its return value and doesn't unwind (a readonly function can leak bits
-      // by throwing an exception or not depending on the input value).
-      if (CS.onlyReadsMemory() && CS.doesNotThrow() && I->getType()->isVoidTy())
-        break;
-
-      // Not captured if only passed via 'nocapture' arguments.  Note that
-      // calling a function pointer does not in itself cause the pointer to
-      // be captured.  This is a subtle point considering that (for example)
-      // the callee might return its own address.  It is analogous to saying
-      // that loading a value from a pointer does not cause the pointer to be
-      // captured, even though the loaded value might be the pointer itself
-      // (think of self-referential objects).
-      CallSite::arg_iterator B = CS.arg_begin(), E = CS.arg_end();
-      for (CallSite::arg_iterator A = B; A != E; ++A)
-        if (A->get() == V && !CS.paramHasAttr(A - B + 1, Attribute::NoCapture))
-          // The parameter is not marked 'nocapture' - captured.
-          return true;
-      // Only passed via 'nocapture' arguments, or is the called function - not
-      // captured.
-      break;
-    }
-    case Instruction::Load:
-      // Loading from a pointer does not cause it to be captured.
-      break;
-    case Instruction::VAArg:
-      // "va-arg" from a pointer does not cause it to be captured.
-      break;
-    case Instruction::Ret:
-      if (ReturnCaptures)
-        return true;
-      break;
-    case Instruction::Store:
-      if (V == I->getOperand(0))
-        // Stored the pointer - conservatively assume it may be captured.
-        // TODO: If StoreCaptures is not true, we could do Fancy analysis
-        // to determine whether this store is not actually an escape point.
-        // In that case, BasicAliasAnalysis should be updated as well to
-        // take advantage of this.
-        return true;
-      // Storing to the pointee does not cause the pointer to be captured.
-      break;
-    case Instruction::BitCast:
-    case Instruction::GetElementPtr:
-    case Instruction::PHI:
-    case Instruction::Select:
-      // The original value is not captured via this if the new value isn't.
-      for (Instruction::use_iterator UI = I->use_begin(), UE = I->use_end();
-           UI != UE; ++UI) {
-        Use *U = &UI.getUse();
-        if (Visited.insert(U))
-          Worklist.push_back(U);
-      }
-      break;
-    case Instruction::ICmp:
-      // Don't count comparisons of a no-alias return value against null as
-      // captures. This allows us to ignore comparisons of malloc results
-      // with null, for example.
-      if (isNoAliasCall(V->stripPointerCasts()))
-        if (ConstantPointerNull *CPN =
-              dyn_cast<ConstantPointerNull>(I->getOperand(1)))
-          if (CPN->getType()->getAddressSpace() == 0)
-            break;
-      // Otherwise, be conservative. There are crazy ways to capture pointers
-      // using comparisons.
-      return true;
-    default:
-      // Something else - be conservative and say it is captured.
-      return true;
-    }
-  }
-
-  // All uses examined - not captured.
-  return false;
+  // TODO: If StoreCaptures is not true, we could do Fancy analysis
+  // to determine whether this store is not actually an escape point.
+  // In that case, BasicAliasAnalysis should be updated as well to
+  // take advantage of this.
+  (void)StoreCaptures;
+
+  SimpleCaptureTracker SCT(ReturnCaptures);
+  PointerMayBeCaptured(V, SCT);
+  return SCT.Captured;
 }

Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=144580&r1=144579&r2=144580&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Mon Nov 14 16:49:42 2011
@@ -22,6 +22,7 @@
 #include "llvm/Function.h"
 #include "llvm/LLVMContext.h"
 #include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/CaptureTracking.h"
 #include "llvm/Analysis/Dominators.h"
 #include "llvm/Analysis/InstructionSimplify.h"
 #include "llvm/Analysis/MemoryBuiltins.h"
@@ -91,6 +92,7 @@
 bool MemoryDependenceAnalysis::runOnFunction(Function &) {
   AA = &getAnalysis<AliasAnalysis>();
   TD = getAnalysisIfAvailable<TargetData>();
+  DT = getAnalysisIfAvailable<DominatorTree>();
   if (PredCache == 0)
     PredCache.reset(new PredIteratorCache());
   return false;
@@ -331,6 +333,82 @@
   return 0;
 }
 
+namespace {
+  /// Only find pointer captures which happen before the given instruction. Uses
+  /// the dominator tree to determine whether one instruction is before another.
+  struct CapturesBefore {
+    CapturesBefore(const Instruction *I, DominatorTree *DT)
+      : BeforeHere(I), DT(DT), Captured(false) {}
+
+    void tooManyUses() { Captured = true; }
+
+    bool shouldExplore(Use *U) {
+      Instruction *I = cast<Instruction>(U->getUser());
+      if (BeforeHere != I && DT->dominates(BeforeHere, I))
+        return false;
+      return true;
+    }
+
+    bool captured(Instruction *I) {
+      if (BeforeHere != I && DT->dominates(BeforeHere, I))
+        return false;
+      Captured = true;
+      return true;
+    }
+
+    const Instruction *BeforeHere;
+    DominatorTree *DT;
+
+    bool Captured;
+  };
+}
+
+AliasAnalysis::ModRefResult
+MemoryDependenceAnalysis::getModRefInfo(const Instruction *Inst,
+                                        const AliasAnalysis::Location &MemLoc) {
+  AliasAnalysis::ModRefResult MR = AA->getModRefInfo(Inst, MemLoc);
+  if (MR != AliasAnalysis::ModRef) return MR;
+
+  // FIXME: this is really just shoring-up a deficiency in alias analysis.
+  // BasicAA isn't willing to spend linear time determining whether an alloca
+  // was captured before or after this particular call, while we are. However,
+  // with a smarter AA in place, this test is just wasting compile time.
+  if (!DT) return AliasAnalysis::ModRef;
+  const Value *Object = GetUnderlyingObject(MemLoc.Ptr, TD);
+  if (!isIdentifiedObject(Object) || isa<GlobalVariable>(Object))
+    return AliasAnalysis::ModRef;
+  ImmutableCallSite CS(Inst);
+  if (!CS.getInstruction()) return AliasAnalysis::ModRef;
+
+  CapturesBefore CB(Inst, DT);
+  llvm::PointerMayBeCaptured(Object, CB);
+
+  if (isa<Constant>(Object) || CS.getInstruction() == Object || CB.Captured)
+    return AliasAnalysis::ModRef;
+
+  unsigned ArgNo = 0;
+  for (ImmutableCallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end();
+       CI != CE; ++CI, ++ArgNo) {
+    // Only look at the no-capture or byval pointer arguments.  If this
+    // pointer were passed to arguments that were neither of these, then it
+    // couldn't be no-capture.
+    if (!(*CI)->getType()->isPointerTy() ||
+        (!CS.paramHasAttr(ArgNo+1, Attribute::NoCapture) &&
+         !CS.paramHasAttr(ArgNo+1, Attribute::ByVal)))
+      continue;
+
+    // If this is a no-capture pointer argument, see if we can tell that it
+    // is impossible to alias the pointer we're checking.  If not, we have to
+    // assume that the call could touch the pointer, even though it doesn't
+    // escape.
+    if (!AA->isNoAlias(AliasAnalysis::Location(*CI),
+                       AliasAnalysis::Location(Object))) {
+      return AliasAnalysis::ModRef;
+    }
+  }
+  return AliasAnalysis::NoModRef;
+}
+
 /// getPointerDependencyFrom - Return the instruction on which a memory
 /// location depends.  If isLoad is true, this routine ignores may-aliases with
 /// read-only operations.  If isLoad is false, this routine ignores may-aliases
@@ -478,7 +556,7 @@
     }
 
     // See if this instruction (e.g. a call or vaarg) mod/ref's the pointer.
-    switch (AA->getModRefInfo(Inst, MemLoc)) {
+    switch (getModRefInfo(Inst, MemLoc)) {
     case AliasAnalysis::NoModRef:
       // If the call has no effect on the queried pointer, just ignore it.
       continue;

Modified: llvm/trunk/test/Transforms/GVN/rle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/rle.ll?rev=144580&r1=144579&r2=144580&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/GVN/rle.ll (original)
+++ llvm/trunk/test/Transforms/GVN/rle.ll Mon Nov 14 16:49:42 2011
@@ -642,3 +642,28 @@
 
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
 
+;;===----------------------------------------------------------------------===;;
+;; Load -> Store dependency which isn't interfered with by a call that happens
+;; before the pointer was captured.
+;;===----------------------------------------------------------------------===;;
+
+%class.X = type { [8 x i8] }
+
+ at _ZTV1X = weak_odr constant [5 x i8*] zeroinitializer
+ at _ZTV1Y = weak_odr constant [5 x i8*] zeroinitializer
+
+declare void @use()
+declare void @use3(i8***, i8**)
+
+; PR8908
+define void @test_escape1() nounwind {
+  %x = alloca i8**, align 8
+  store i8** getelementptr inbounds ([5 x i8*]* @_ZTV1X, i64 0, i64 2), i8*** %x, align 8
+  call void @use() nounwind
+  %DEAD = load i8*** %x, align 8
+  call void @use3(i8*** %x, i8** %DEAD) nounwind
+  ret void
+; CHECK: test_escape1
+; CHECK-NOT: DEAD
+; CHECK: ret
+}



From grosbach at apple.com  Mon Nov 14 17:03:21 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 14 Nov 2011 23:03:21 -0000
Subject: [llvm-commits] [llvm] r144583 - in /llvm/trunk: lib/Target/ARM/
 test/CodeGen/ARM/ test/CodeGen/Thumb2/ test/MC/ARM/
 test/MC/Disassembler/ARM/
Message-ID: <20111114230322.471222A6C131@llvm.org>

Author: grosbach
Date: Mon Nov 14 17:03:21 2011
New Revision: 144583

URL: http://llvm.org/viewvc/llvm-project?rev=144583&view=rev
Log:
ARM VLDR/VSTR instructions don't need a size suffix.

Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
    llvm/trunk/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
    llvm/trunk/test/CodeGen/ARM/2009-09-24-spill-align.ll
    llvm/trunk/test/CodeGen/ARM/2010-05-21-BuildVector.ll
    llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
    llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll
    llvm/trunk/test/CodeGen/ARM/fp.ll
    llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll
    llvm/trunk/test/CodeGen/ARM/fpmem.ll
    llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll
    llvm/trunk/test/CodeGen/ARM/neon_ld1.ll
    llvm/trunk/test/CodeGen/ARM/reg_sequence.ll
    llvm/trunk/test/CodeGen/ARM/subreg-remat.ll
    llvm/trunk/test/CodeGen/ARM/vbsl-constant.ll
    llvm/trunk/test/CodeGen/ARM/vdup.ll
    llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll
    llvm/trunk/test/CodeGen/ARM/vext.ll
    llvm/trunk/test/CodeGen/ARM/widen-vmovs.ll
    llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll
    llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll
    llvm/trunk/test/MC/ARM/simple-fp-encoding.s
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
    llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 14 17:03:21 2011
@@ -1996,6 +1996,7 @@
 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
   InstAlias<!strconcat(opc, dt, asm), Result>;
 multiclass VFPDT32InstAlias<string opc, string asm, dag Result> {
+  def _32 : VFPDataTypeInstAlias<opc, ".32",  asm, Result>;
   def I32 : VFPDataTypeInstAlias<opc, ".i32", asm, Result>;
   def S32 : VFPDataTypeInstAlias<opc, ".s32", asm, Result>;
   def U32 : VFPDataTypeInstAlias<opc, ".u32", asm, Result>;
@@ -2003,6 +2004,7 @@
   def F   : VFPDataTypeInstAlias<opc, ".f",   asm, Result>;
 }
 multiclass VFPDT64InstAlias<string opc, string asm, dag Result> {
+  def _64 : VFPDataTypeInstAlias<opc, ".64",  asm, Result>;
   def I64 : VFPDataTypeInstAlias<opc, ".i64", asm, Result>;
   def S64 : VFPDataTypeInstAlias<opc, ".s64", asm, Result>;
   def U64 : VFPDataTypeInstAlias<opc, ".u64", asm, Result>;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Nov 14 17:03:21 2011
@@ -69,11 +69,11 @@
 let canFoldAsLoad = 1, isReMaterializable = 1 in {
 
 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
-                 IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
+                 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
                  [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
 
 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
-                 IIC_fpLoad32, "vldr", ".32\t$Sd, $addr",
+                 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
                  [(set SPR:$Sd, (load addrmode5:$addr))]> {
   // Some single precision VFP instructions may be executed on both NEON and VFP
   // pipelines.
@@ -83,11 +83,11 @@
 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
 
 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
-                 IIC_fpStore64, "vstr", ".64\t$Dd, $addr",
+                 IIC_fpStore64, "vstr", "\t$Dd, $addr",
                  [(store (f64 DPR:$Dd), addrmode5:$addr)]>;
 
 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
-                 IIC_fpStore32, "vstr", ".32\t$Sd, $addr",
+                 IIC_fpStore32, "vstr", "\t$Sd, $addr",
                  [(store SPR:$Sd, addrmode5:$addr)]> {
   // Some single precision VFP instructions may be executed on both NEON and VFP
   // pipelines.
@@ -1163,21 +1163,12 @@
 
 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
 
-// The size suffix is optional for VLDR/VSTR
-def : VFP2InstAlias<"vldr$p $Dd, $addr",
-                    (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
-def : VFP2InstAlias<"vldr$p $Sd, $addr",
-                    (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
-def : VFP2InstAlias<"vstr$p $Dd, $addr",
-                    (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
-def : VFP2InstAlias<"vstr$p $Sd, $addr",
-                    (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
-// The suffix can also by typed.
-defm : VFPDT32InstAlias<"vldr$p", "$Sd, $addr",
+// VLDR/VSTR accept an optional type suffix.
+defm : VFPDT32InstAlias<"vldr${p}", "$Sd, $addr",
                         (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
-defm : VFPDT32InstAlias<"vstr$p", "$Sd, $addr",
+defm : VFPDT32InstAlias<"vstr${p}", "$Sd, $addr",
                         (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
-defm : VFPDT64InstAlias<"vldr$p", "$Dd, $addr",
+defm : VFPDT64InstAlias<"vldr${p}", "$Dd, $addr",
                         (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
-defm : VFPDT64InstAlias<"vstr$p", "$Dd, $addr",
+defm : VFPDT64InstAlias<"vstr${p}", "$Dd, $addr",
                         (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;

Modified: llvm/trunk/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll Mon Nov 14 17:03:21 2011
@@ -9,7 +9,7 @@
   br i1 %4, label %bb1, label %bb2
 
 bb1:
-;CHECK: vstrhi.64
+;CHECK: vstrhi
   store double %1, double* %y
   br label %bb2
 

Modified: llvm/trunk/test/CodeGen/ARM/2009-09-24-spill-align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-24-spill-align.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-09-24-spill-align.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-09-24-spill-align.ll Mon Nov 14 17:03:21 2011
@@ -6,7 +6,7 @@
   %arg0_poly16x4_t = alloca <4 x i16>             ; <<4 x i16>*> [#uses=1]
   %out_poly16_t = alloca i16                      ; <i16*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-; CHECK: vldr.64
+; CHECK: vldr
   %0 = load <4 x i16>* %arg0_poly16x4_t, align 8  ; <<4 x i16>> [#uses=1]
   %1 = extractelement <4 x i16> %0, i32 1         ; <i16> [#uses=1]
   store i16 %1, i16* %out_poly16_t, align 2

Modified: llvm/trunk/test/CodeGen/ARM/2010-05-21-BuildVector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-05-21-BuildVector.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-05-21-BuildVector.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2010-05-21-BuildVector.ll Mon Nov 14 17:03:21 2011
@@ -10,28 +10,28 @@
   %4 = ashr i32 %3, 30
   %.sum = add i32 %4, 4
   %5 = getelementptr inbounds float* %table, i32 %.sum
-;CHECK: vldr.32 s
+;CHECK: vldr s
   %6 = load float* %5, align 4
   %tmp11 = insertelement <4 x float> undef, float %6, i32 0
   %7 = shl i32 %packedValue, 18
   %8 = ashr i32 %7, 30
   %.sum12 = add i32 %8, 4
   %9 = getelementptr inbounds float* %table, i32 %.sum12
-;CHECK: vldr.32 s
+;CHECK: vldr s
   %10 = load float* %9, align 4
   %tmp9 = insertelement <4 x float> %tmp11, float %10, i32 1
   %11 = shl i32 %packedValue, 20
   %12 = ashr i32 %11, 30
   %.sum13 = add i32 %12, 4
   %13 = getelementptr inbounds float* %table, i32 %.sum13
-;CHECK: vldr.32 s
+;CHECK: vldr s
   %14 = load float* %13, align 4
   %tmp7 = insertelement <4 x float> %tmp9, float %14, i32 2
   %15 = shl i32 %packedValue, 22
   %16 = ashr i32 %15, 30
   %.sum14 = add i32 %16, 4
   %17 = getelementptr inbounds float* %table, i32 %.sum14
-;CHECK: vldr.32 s
+;CHECK: vldr s
   %18 = load float* %17, align 4
   %tmp5 = insertelement <4 x float> %tmp7, float %18, i32 3
   %19 = fmul <4 x float> %tmp5, %2

Modified: llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll Mon Nov 14 17:03:21 2011
@@ -1,7 +1,7 @@
 ; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s
 
 ; Should trigger a NEON store.
-; CHECK: vstr.64
+; CHECK: vstr
 define void @f_0_12(i8* nocapture %c) nounwind optsize {
 entry:
   call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false)

Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-cmp-imm.ll Mon Nov 14 17:03:21 2011
@@ -26,9 +26,9 @@
 ; ARM: t1b
 ; THUMB: t1b
   %cmp = fcmp oeq float %a, -0.000000e+00
-; ARM: vldr.32
+; ARM: vldr
 ; ARM: vcmpe.f32 s{{[0-9]+}}, s{{[0-9]+}}
-; THUMB: vldr.32
+; THUMB: vldr
 ; THUMB: vcmpe.f32 s{{[0-9]+}}, s{{[0-9]+}}
   br i1 %cmp, label %if.then, label %if.end
 
@@ -63,9 +63,9 @@
 ; ARM: t2b
 ; THUMB: t2b
   %cmp = fcmp oeq double %a, -0.000000e+00
-; ARM: vldr.64
+; ARM: vldr
 ; ARM: vcmpe.f64 d{{[0-9]+}}, d{{[0-9]+}}
-; THUMB: vldr.64
+; THUMB: vldr
 ; THUMB: vcmpe.f64 d{{[0-9]+}}, d{{[0-9]+}}
   br i1 %cmp, label %if.then, label %if.end
 

Modified: llvm/trunk/test/CodeGen/ARM/fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp.ll Mon Nov 14 17:03:21 2011
@@ -42,7 +42,7 @@
 
 define double @h(double* %v) {
 ;CHECK: h:
-;CHECK: vldr.64
+;CHECK: vldr
 ;CHECK-NEXT: vmov
 entry:
         %tmp = load double* %v          ; <double> [#uses=1]

Modified: llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll Mon Nov 14 17:03:21 2011
@@ -14,8 +14,8 @@
 ; FINITE: beq
 
 ; NAN: t1:
-; NAN: vldr.32 s0,
-; NAN: vldr.32 s1,
+; NAN: vldr s0,
+; NAN: vldr s1,
 ; NAN: vcmpe.f32 s1, s0
 ; NAN: vmrs apsr_nzcv, fpscr
 ; NAN: beq

Modified: llvm/trunk/test/CodeGen/ARM/fpmem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpmem.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpmem.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpmem.ll Mon Nov 14 17:03:21 2011
@@ -8,7 +8,7 @@
 
 define float @f2(float* %v, float %u) {
 ; CHECK: f2:
-; CHECK: vldr.32{{.*}}[
+; CHECK: vldr{{.*}}[
         %tmp = load float* %v           ; <float> [#uses=1]
         %tmp1 = fadd float %tmp, %u              ; <float> [#uses=1]
         ret float %tmp1
@@ -16,7 +16,7 @@
 
 define float @f2offset(float* %v, float %u) {
 ; CHECK: f2offset:
-; CHECK: vldr.32{{.*}}, #4]
+; CHECK: vldr{{.*}}, #4]
         %addr = getelementptr float* %v, i32 1
         %tmp = load float* %addr
         %tmp1 = fadd float %tmp, %u
@@ -25,7 +25,7 @@
 
 define float @f2noffset(float* %v, float %u) {
 ; CHECK: f2noffset:
-; CHECK: vldr.32{{.*}}, #-4]
+; CHECK: vldr{{.*}}, #-4]
         %addr = getelementptr float* %v, i32 -1
         %tmp = load float* %addr
         %tmp1 = fadd float %tmp, %u
@@ -34,7 +34,7 @@
 
 define void @f3(float %a, float %b, float* %v) {
 ; CHECK: f3:
-; CHECK: vstr.32{{.*}}[
+; CHECK: vstr{{.*}}[
         %tmp = fadd float %a, %b         ; <float> [#uses=1]
         store float %tmp, float* %v
         ret void

Modified: llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll Mon Nov 14 17:03:21 2011
@@ -4,9 +4,9 @@
 ; constant offset addressing, so that each of the following stores
 ; uses the same register.
 
-; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #32]
-; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #64]
-; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #96]
+; CHECK: vstr s{{.*}}, [{{(r[0-9]+)|(lr)}}, #32]
+; CHECK: vstr s{{.*}}, [{{(r[0-9]+)|(lr)}}, #64]
+; CHECK: vstr s{{.*}}, [{{(r[0-9]+)|(lr)}}, #96]
 
 ; We can also save a register in the outer loop, but that requires
 ; performing LSR on the outer loop.

Modified: llvm/trunk/test/CodeGen/ARM/neon_ld1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/neon_ld1.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/neon_ld1.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/neon_ld1.ll Mon Nov 14 17:03:21 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=arm -mattr=+neon | grep vldr.64 | count 4
-; RUN: llc < %s -march=arm -mattr=+neon | grep vstr.64
+; RUN: llc < %s -march=arm -mattr=+neon | grep vldr | count 4
+; RUN: llc < %s -march=arm -mattr=+neon | grep vstr
 ; RUN: llc < %s -march=arm -mattr=+neon | grep vmov
 
 define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind {

Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Mon Nov 14 17:03:21 2011
@@ -155,7 +155,7 @@
 
 define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
 ; CHECK:        t6:
-; CHECK:        vldr.64
+; CHECK:        vldr
 ; CHECK:        vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]]
 ; CHECK-NEXT:   vld2.8 {d[[D1]][1], d[[D0]][1]}
   %tmp1 = load <8 x i8>* %B                       ; <<8 x i8>> [#uses=2]
@@ -240,7 +240,7 @@
 ; PR7157
 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
 ; CHECK:        t9:
-; CHECK:        vldr.64
+; CHECK:        vldr
 ; CHECK-NOT:    vmov d{{.*}}, d16
 ; CHECK:        vmov.i32 d17
 ; CHECK-NEXT:   vstmia r0, {d16, d17}

Modified: llvm/trunk/test/CodeGen/ARM/subreg-remat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/subreg-remat.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/subreg-remat.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/subreg-remat.ll Mon Nov 14 17:03:21 2011
@@ -12,13 +12,13 @@
 ;
 ; CHECK: f1
 ; CHECK: vmov    s1, r0
-; CHECK: vldr.32 s0, LCPI
+; CHECK: vldr s0, LCPI
 ; The vector must be spilled:
-; CHECK: vstr.64 d0,
+; CHECK: vstr d0,
 ; CHECK: asm clobber d0
 ; And reloaded after the asm:
-; CHECK: vldr.64 [[D16:d[0-9]+]],
-; CHECK: vstr.64 [[D16]], [r1]
+; CHECK: vldr [[D16:d[0-9]+]],
+; CHECK: vstr [[D16]], [r1]
 define void @f1(float %x, <2 x float>* %p) {
   %v1 = insertelement <2 x float> undef, float %x, i32 1
   %v2 = insertelement <2 x float> %v1, float 0x400921FB60000000, i32 0
@@ -37,13 +37,13 @@
 ; virtual register.  It doesn't read the old value.
 ;
 ; CHECK: f2
-; CHECK: vldr.32 s0, LCPI
+; CHECK: vldr s0, LCPI
 ; The vector must not be spilled:
-; CHECK-NOT: vstr.64
+; CHECK-NOT: vstr
 ; CHECK: asm clobber d0
 ; But instead rematerialize after the asm:
-; CHECK: vldr.32 [[S0:s[0-9]+]], LCPI
-; CHECK: vstr.64 [[D0:d[0-9]+]], [r0]
+; CHECK: vldr [[S0:s[0-9]+]], LCPI
+; CHECK: vstr [[D0:d[0-9]+]], [r0]
 define void @f2(<2 x float>* %p) {
   %v2 = insertelement <2 x float> undef, float 0x400921FB60000000, i32 0
   %y = call double asm sideeffect "asm clobber $0", "=w,0,~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15},~{d16},~{d17},~{d18},~{d19},~{d20},~{d21},~{d22},~{d23},~{d24},~{d25},~{d26},~{d27},~{d28},~{d29},~{d30},~{d31}"(<2 x float> %v2) nounwind

Modified: llvm/trunk/test/CodeGen/ARM/vbsl-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbsl-constant.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vbsl-constant.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vbsl-constant.ll Mon Nov 14 17:03:21 2011
@@ -2,8 +2,8 @@
 
 define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ;CHECK: v_bsli8:
-;CHECK: vldr.64
-;CHECK: vldr.64
+;CHECK: vldr
+;CHECK: vldr
 ;CHECK: vbsl
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -16,8 +16,8 @@
 
 define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ;CHECK: v_bsli16:
-;CHECK: vldr.64
-;CHECK: vldr.64
+;CHECK: vldr
+;CHECK: vldr
 ;CHECK: vbsl
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -30,8 +30,8 @@
 
 define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ;CHECK: v_bsli32:
-;CHECK: vldr.64
-;CHECK: vldr.64
+;CHECK: vldr
+;CHECK: vldr
 ;CHECK: vbsl
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -44,9 +44,9 @@
 
 define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
 ;CHECK: v_bsli64:
-;CHECK: vldr.64
-;CHECK: vldr.64
-;CHECK: vldr.64
+;CHECK: vldr
+;CHECK: vldr
+;CHECK: vldr
 ;CHECK: vbsl
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B

Modified: llvm/trunk/test/CodeGen/ARM/vdup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vdup.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vdup.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vdup.ll Mon Nov 14 17:03:21 2011
@@ -254,7 +254,7 @@
 ;CHECK: redundantVdup:
 ;CHECK: vmov.i8
 ;CHECK-NOT: vdup.8
-;CHECK: vstr.64
+;CHECK: vstr
 define void @redundantVdup(<8 x i8>* %ptr) nounwind {
   %1 = insertelement <8 x i8> undef, i8 -128, i32 0
   %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer

Modified: llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vector-DAGCombine.ll Mon Nov 14 17:03:21 2011
@@ -80,7 +80,7 @@
 ; so they are not split up into i32 values.  Radar 8755338.
 define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind {
 ; CHECK: i64_buildvector
-; CHECK: vldr.64
+; CHECK: vldr
   %t0 = load i64* %ptr, align 4
   %t1 = insertelement <2 x i64> undef, i64 %t0, i32 0
   store <2 x i64> %t1, <2 x i64>* %vp
@@ -89,7 +89,7 @@
 
 define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind {
 ; CHECK: i64_insertelement
-; CHECK: vldr.64
+; CHECK: vldr
   %t0 = load i64* %ptr, align 4
   %vec = load <2 x i64>* %vp
   %t1 = insertelement <2 x i64> %vec, i64 %t0, i32 0
@@ -99,7 +99,7 @@
 
 define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind {
 ; CHECK: i64_extractelement
-; CHECK: vstr.64
+; CHECK: vstr
   %vec = load <2 x i64>* %vp
   %t1 = extractelement <2 x i64> %vec, i32 0
   store i64 %t1, i64* %ptr

Modified: llvm/trunk/test/CodeGen/ARM/vext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vext.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vext.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vext.ll Mon Nov 14 17:03:21 2011
@@ -138,7 +138,7 @@
 ; Make sure this doesn't crash
 define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
 ; CHECK: test_elem_mismatch:
-; CHECK: vstr.64
+; CHECK: vstr
   %tmp0 = load <2 x i64>* %src, align 16
   %tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
   %tmp2 = extractelement <4 x i32> %tmp1, i32 0

Modified: llvm/trunk/test/CodeGen/ARM/widen-vmovs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/widen-vmovs.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/widen-vmovs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/widen-vmovs.ll Mon Nov 14 17:03:21 2011
@@ -3,7 +3,7 @@
 
 ; The 0.0 constant is loaded from the constant pool and kept in a register.
 ; CHECK: %entry
-; CHECK: vldr.32 s
+; CHECK: vldr s
 ; The float loop variable is initialized with a vmovs from the constant register.
 ; The vmovs is first widened to a vmovd, and then converted to a vorr because of the v2f32 vadd.f32.
 ; CHECK: vorr [[DL:d[0-9]+]], [[DN:d[0-9]+]]

Modified: llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll Mon Nov 14 17:03:21 2011
@@ -5,7 +5,7 @@
 entry:
 ; -- The loop following the load should only use a single add-literation
 ;    instruction.
-; CHECK: ldr.64
+; CHECK: vldr
 ; CHECK: adds r{{[0-9]+.*}}#1
 ; CHECK-NOT: adds
 ; CHECK: subsections_via_symbols

Modified: llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll Mon Nov 14 17:03:21 2011
@@ -23,7 +23,7 @@
   %4 = insertelement <2 x double> %2, double %V.0.ph, i32 1 ; <<2 x double>> [#uses=2]
 ; Constant pool load followed by add.
 ; Then clobber the loaded register, not the sum.
-; CHECK: vldr.64 [[LDR:d.*]],
+; CHECK: vldr [[LDR:d.*]],
 ; CHECK: LPC0_0:
 ; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]]
 ; CHECK-NOT: vmov.f64 [[ADD]]

Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Mon Nov 14 17:03:21 2011
@@ -172,52 +172,52 @@
 @ CHECK: vmov r0, r1, d16            @ encoding: [0x30,0x0b,0x51,0xec]
         vmov    r0, r1, d16
 
-@ CHECK: vldr.64 d17, [r0]           @ encoding: [0x00,0x1b,0xd0,0xed]
-@ CHECK: vldr.32 s0, [lr]            @ encoding: [0x00,0x0a,0x9e,0xed]
-@ CHECK: vldr.64 d0, [lr]            @ encoding: [0x00,0x0b,0x9e,0xed]
+@ CHECK: vldr d17, [r0]           @ encoding: [0x00,0x1b,0xd0,0xed]
+@ CHECK: vldr s0, [lr]            @ encoding: [0x00,0x0a,0x9e,0xed]
+@ CHECK: vldr d0, [lr]            @ encoding: [0x00,0x0b,0x9e,0xed]
 
         vldr.64	d17, [r0]
-	vldr s0, [lr]
-	vldr d0, [lr]
+	vldr.i32 s0, [lr]
+	vldr.d d0, [lr]
 
-@ CHECK: vldr.64 d1, [r2, #32]       @ encoding: [0x08,0x1b,0x92,0xed]
-@ CHECK: vldr.64 d1, [r2, #-32]      @ encoding: [0x08,0x1b,0x12,0xed]
+@ CHECK: vldr d1, [r2, #32]       @ encoding: [0x08,0x1b,0x92,0xed]
+@ CHECK: vldr d1, [r2, #-32]      @ encoding: [0x08,0x1b,0x12,0xed]
         vldr.64	d1, [r2, #32]
-        vldr.64	d1, [r2, #-32]
+        vldr.f64	d1, [r2, #-32]
 
-@ CHECK: vldr.64 d2, [r3]            @ encoding: [0x00,0x2b,0x93,0xed]
+@ CHECK: vldr d2, [r3]            @ encoding: [0x00,0x2b,0x93,0xed]
         vldr.64 d2, [r3]
 
-@ CHECK: vldr.64 d3, [pc]            @ encoding: [0x00,0x3b,0x9f,0xed]
-@ CHECK: vldr.64 d3, [pc]            @ encoding: [0x00,0x3b,0x9f,0xed]
-@ CHECK: vldr.64 d3, [pc, #-0]            @ encoding: [0x00,0x3b,0x1f,0xed]
+@ CHECK: vldr d3, [pc]            @ encoding: [0x00,0x3b,0x9f,0xed]
+@ CHECK: vldr d3, [pc]            @ encoding: [0x00,0x3b,0x9f,0xed]
+@ CHECK: vldr d3, [pc, #-0]            @ encoding: [0x00,0x3b,0x1f,0xed]
         vldr.64 d3, [pc]
         vldr.64 d3, [pc,#0]
         vldr.64 d3, [pc,#-0]
 
-@ CHECK: vldr.32 s13, [r0]           @ encoding: [0x00,0x6a,0xd0,0xed]
+@ CHECK: vldr s13, [r0]           @ encoding: [0x00,0x6a,0xd0,0xed]
         vldr.32	s13, [r0]
 
-@ CHECK: vldr.32 s1, [r2, #32]       @ encoding: [0x08,0x0a,0xd2,0xed]
-@ CHECK: vldr.32 s1, [r2, #-32]      @ encoding: [0x08,0x0a,0x52,0xed]
+@ CHECK: vldr s1, [r2, #32]       @ encoding: [0x08,0x0a,0xd2,0xed]
+@ CHECK: vldr s1, [r2, #-32]      @ encoding: [0x08,0x0a,0x52,0xed]
         vldr.32	s1, [r2, #32]
         vldr.32	s1, [r2, #-32]
 
-@ CHECK: vldr.32 s2, [r3]            @ encoding: [0x00,0x1a,0x93,0xed]
+@ CHECK: vldr s2, [r3]            @ encoding: [0x00,0x1a,0x93,0xed]
         vldr.32 s2, [r3]
 
-@ CHECK: vldr.32 s5, [pc]            @ encoding: [0x00,0x2a,0xdf,0xed]
-@ CHECK: vldr.32 s5, [pc]            @ encoding: [0x00,0x2a,0xdf,0xed]
-@ CHECK: vldr.32 s5, [pc, #-0]            @ encoding: [0x00,0x2a,0x5f,0xed]
+@ CHECK: vldr s5, [pc]            @ encoding: [0x00,0x2a,0xdf,0xed]
+@ CHECK: vldr s5, [pc]            @ encoding: [0x00,0x2a,0xdf,0xed]
+@ CHECK: vldr s5, [pc, #-0]            @ encoding: [0x00,0x2a,0x5f,0xed]
         vldr.32 s5, [pc]
         vldr.32 s5, [pc,#0]
         vldr.32 s5, [pc,#-0]
 
-@ CHECK: vstr.64 d4, [r1]            @ encoding: [0x00,0x4b,0x81,0xed]
-@ CHECK: vstr.64 d4, [r1, #24]       @ encoding: [0x06,0x4b,0x81,0xed]
-@ CHECK: vstr.64 d4, [r1, #-24]      @ encoding: [0x06,0x4b,0x01,0xed]
-@ CHECK: vstr.32 s0, [lr]            @ encoding: [0x00,0x0a,0x8e,0xed]
-@ CHECK: vstr.64 d0, [lr]            @ encoding: [0x00,0x0b,0x8e,0xed]
+@ CHECK: vstr d4, [r1]            @ encoding: [0x00,0x4b,0x81,0xed]
+@ CHECK: vstr d4, [r1, #24]       @ encoding: [0x06,0x4b,0x81,0xed]
+@ CHECK: vstr d4, [r1, #-24]      @ encoding: [0x06,0x4b,0x01,0xed]
+@ CHECK: vstr s0, [lr]            @ encoding: [0x00,0x0a,0x8e,0xed]
+@ CHECK: vstr d0, [lr]            @ encoding: [0x00,0x0b,0x8e,0xed]
 
         vstr.64 d4, [r1]
         vstr.64 d4, [r1, #24]
@@ -225,9 +225,9 @@
 	vstr s0, [lr]
 	vstr d0, [lr]
 
-@ CHECK: vstr.32 s4, [r1]            @ encoding: [0x00,0x2a,0x81,0xed]
-@ CHECK: vstr.32 s4, [r1, #24]       @ encoding: [0x06,0x2a,0x81,0xed]
-@ CHECK: vstr.32 s4, [r1, #-24]      @ encoding: [0x06,0x2a,0x01,0xed]
+@ CHECK: vstr s4, [r1]            @ encoding: [0x00,0x2a,0x81,0xed]
+@ CHECK: vstr s4, [r1, #24]       @ encoding: [0x06,0x2a,0x81,0xed]
+@ CHECK: vstr s4, [r1, #-24]      @ encoding: [0x06,0x2a,0x01,0xed]
         vstr.32 s4, [r1]
         vstr.32 s4, [r1, #24]
         vstr.32 s4, [r1, #-24]

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Mon Nov 14 17:03:21 2011
@@ -215,7 +215,7 @@
 # CHECK:	vldmdb	r2!, {s7, s8, s9, s10, s11}
 0x05 0x3a 0x72 0xed
 
-# CHECK:	vldr.32	s23, [r2, #660]
+# CHECK:	vldr	s23, [r2, #660]
 0xa5 0xba 0xd2 0xed
 
 # CHECK:	strtvc	r5, [r3], r0, lsr #20

Modified: llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt?rev=144583&r1=144582&r2=144583&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt Mon Nov 14 17:03:21 2011
@@ -152,46 +152,46 @@
 # CHECK: vmov    r0, r1, d16
 
 0x00 0x1b 0xd0 0xed
-# CHECK: vldr.64	d17, [r0]
+# CHECK: vldr	d17, [r0]
 
 0x08 0x1b 0x92 0xed
 0x08 0x1b 0x12 0xed
-# CHECK: vldr.64	d1, [r2, #32]
-# CHECK: vldr.64	d1, [r2, #-32]
+# CHECK: vldr	d1, [r2, #32]
+# CHECK: vldr	d1, [r2, #-32]
 
 0x00 0x2b 0x93 0xed
-# CHECK: vldr.64 d2, [r3]
+# CHECK: vldr d2, [r3]
 
 0x00 0x3b 0x9f 0xed
-# CHECK: vldr.64 d3, [pc]
+# CHECK: vldr d3, [pc]
 
 0x00 0x6a 0xd0 0xed
-# CHECK: vldr.32	s13, [r0]
+# CHECK: vldr	s13, [r0]
 
 0x08 0x0a 0xd2 0xed
 0x08 0x0a 0x52 0xed
-# CHECK: vldr.32	s1, [r2, #32]
-# CHECK: vldr.32	s1, [r2, #-32]
+# CHECK: vldr	s1, [r2, #32]
+# CHECK: vldr	s1, [r2, #-32]
 
 0x00 0x1a 0x93 0xed
-# CHECK: vldr.32 s2, [r3]
+# CHECK: vldr s2, [r3]
 
 0x00 0x2a 0xdf 0xed
-# CHECK: vldr.32 s5, [pc]
+# CHECK: vldr s5, [pc]
 
 0x00 0x4b 0x81 0xed
 0x06 0x4b 0x81 0xed
 0x06 0x4b 0x01 0xed
-# CHECK: vstr.64 d4, [r1]
-# CHECK: vstr.64 d4, [r1, #24]
-# CHECK: vstr.64 d4, [r1, #-24]
+# CHECK: vstr d4, [r1]
+# CHECK: vstr d4, [r1, #24]
+# CHECK: vstr d4, [r1, #-24]
 
 0x00 0x2a 0x81 0xed
 0x06 0x2a 0x81 0xed
 0x06 0x2a 0x01 0xed
-# CHECK: vstr.32 s4, [r1]
-# CHECK: vstr.32 s4, [r1, #24]
-# CHECK: vstr.32 s4, [r1, #-24]
+# CHECK: vstr s4, [r1]
+# CHECK: vstr s4, [r1, #24]
+# CHECK: vstr s4, [r1, #-24]
 
 0x0c 0x2b 0x91 0xec
 0x06 0x1a 0x91 0xec



From mcrosier at apple.com  Mon Nov 14 17:04:10 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Mon, 14 Nov 2011 23:04:10 -0000
Subject: [llvm-commits] [llvm] r144585 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20111114230410.2161D2A6C131@llvm.org>

Author: mcrosier
Date: Mon Nov 14 17:04:09 2011
New Revision: 144585

URL: http://llvm.org/viewvc/llvm-project?rev=144585&view=rev
Log:
Supporting inline memmove isn't going to be worthwhile.  The only way to avoid
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144585&r1=144584&r2=144585&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Nov 14 17:04:09 2011
@@ -185,9 +185,8 @@
     bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
     bool ARMComputeAddress(const Value *Obj, Address &Addr);
     void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
-    bool ARMIsMemXferSmall(uint64_t Len);
-    bool ARMTryEmitSmallMemXfer(Address Dest, Address Src, uint64_t Len,
-                                bool isMemCpy);
+    bool ARMIsMemCpySmall(uint64_t Len);
+    bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len);
     unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
     unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
     unsigned ARMMaterializeInt(const Constant *C, EVT VT);
@@ -2196,19 +2195,13 @@
   return true;
 }
 
-bool ARMFastISel::ARMIsMemXferSmall(uint64_t Len) {
+bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
   return Len <= 16;
 }
 
-bool ARMFastISel::ARMTryEmitSmallMemXfer(Address Dest, Address Src, uint64_t Len,
-                                         bool isMemCpy) {
-  // FIXME: Memmove's require a little more care because their source and
-  // destination may overlap.
-  if (!isMemCpy)
-    return false;
-
+bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len) {
   // Make sure we don't bloat code by inlining very large memcpy's.
-  if (!ARMIsMemXferSmall(Len))
+  if (!ARMIsMemCpySmall(Len))
     return false;
 
   // We don't care about alignment here since we just emit integer accesses.
@@ -2254,15 +2247,15 @@
     // we would emit dead code because we don't currently handle memmoves.
     bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
     if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
-      // Small memcpy/memmove's are common enough that we want to do them
-      // without a call if possible.
+      // Small memcpy's are common enough that we want to do them without a call
+      // if possible.
       uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
-      if (ARMIsMemXferSmall(Len)) {
+      if (ARMIsMemCpySmall(Len)) {
         Address Dest, Src;
         if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
             !ARMComputeAddress(MTI.getRawSource(), Src))
           return false;
-        if (ARMTryEmitSmallMemXfer(Dest, Src, Len, isMemCpy))
+        if (ARMTryEmitSmallMemCpy(Dest, Src, Len))
           return true;
       }
     }



From gkistanova at gmail.com  Mon Nov 14 17:04:17 2011
From: gkistanova at gmail.com (Galina Kistanova)
Date: Mon, 14 Nov 2011 23:04:17 -0000
Subject: [llvm-commits] [zorg] r144586 -
	/zorg/trunk/zorg/buildbot/changes/llvmpoller.py
Message-ID: <20111114230417.62A392A6C131@llvm.org>

Author: gkistanova
Date: Mon Nov 14 17:04:17 2011
New Revision: 144586

URL: http://llvm.org/viewvc/llvm-project?rev=144586&view=rev
Log:
Add categories to changes.

Modified:
    zorg/trunk/zorg/buildbot/changes/llvmpoller.py

Modified: zorg/trunk/zorg/buildbot/changes/llvmpoller.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/changes/llvmpoller.py?rev=144586&r1=144585&r2=144586&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/changes/llvmpoller.py (original)
+++ zorg/trunk/zorg/buildbot/changes/llvmpoller.py Mon Nov 14 17:04:17 2011
@@ -210,6 +210,16 @@
     def create_changes(self, new_logentries):
         changes = []
 
+        categories = {
+            'llvm'         : 'llvm',
+            'cfe'          : 'clang',
+            'polly'        : 'polly',
+            'llvm-gcc-4.2' : 'llvm-gcc',
+            'compiler-rt'  : 'compiler-rt',
+            'dragonegg'    : 'dragonegg',
+            'lldb'         : 'lldb'
+            }
+
         for el in new_logentries:
             revision = str(el.getAttribute("revision"))
 
@@ -272,7 +282,7 @@
                                   revision=revision,
                                   branch=branch,
                                   revlink=revlink,
-                                  category=self.category,
+                                  category=categories.get(project, None),
                                   repository=self.svnurl,
                                   project=project)
                     changes.append(chdict)



From grosbach at apple.com  Mon Nov 14 17:11:19 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 14 Nov 2011 23:11:19 -0000
Subject: [llvm-commits] [llvm] r144587 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td
 test/MC/ARM/neon-bitwise-encoding.s
Message-ID: <20111114231119.85F1B2A6C131@llvm.org>

Author: grosbach
Date: Mon Nov 14 17:11:19 2011
New Revision: 144587

URL: http://llvm.org/viewvc/llvm-project?rev=144587&view=rev
Log:
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.

rdar://10435076

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=144587&r1=144586&r2=144587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 14 17:11:19 2011
@@ -1995,6 +1995,20 @@
 // VFP/NEON Instruction aliases for type suffices.
 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
   InstAlias<!strconcat(opc, dt, asm), Result>;
+multiclass VFPDT8InstAlias<string opc, string asm, dag Result> {
+  def _8 : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
+  def I8 : VFPDataTypeInstAlias<opc, ".i8", asm, Result>;
+  def S8 : VFPDataTypeInstAlias<opc, ".s8", asm, Result>;
+  def U8 : VFPDataTypeInstAlias<opc, ".u8", asm, Result>;
+  def F8 : VFPDataTypeInstAlias<opc, ".p8", asm, Result>;
+}
+multiclass VFPDT16InstAlias<string opc, string asm, dag Result> {
+  def _16 : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
+  def I16 : VFPDataTypeInstAlias<opc, ".i16", asm, Result>;
+  def S16 : VFPDataTypeInstAlias<opc, ".s16", asm, Result>;
+  def U16 : VFPDataTypeInstAlias<opc, ".u16", asm, Result>;
+  def F16 : VFPDataTypeInstAlias<opc, ".p16", asm, Result>;
+}
 multiclass VFPDT32InstAlias<string opc, string asm, dag Result> {
   def _32 : VFPDataTypeInstAlias<opc, ".32",  asm, Result>;
   def I32 : VFPDataTypeInstAlias<opc, ".i32", asm, Result>;
@@ -2011,4 +2025,9 @@
   def F64 : VFPDataTypeInstAlias<opc, ".f64", asm, Result>;
   def D   : VFPDataTypeInstAlias<opc, ".d",   asm, Result>;
 }
-
+multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
+  defm : VFPDT8InstAlias<opc, asm, Result>;
+  defm : VFPDT16InstAlias<opc, asm, Result>;
+  defm : VFPDT32InstAlias<opc, asm, Result>;
+  defm : VFPDT64InstAlias<opc, asm, Result>;
+}

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=144587&r1=144586&r2=144587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 14 17:11:19 2011
@@ -5179,3 +5179,21 @@
 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
+
+
+//===----------------------------------------------------------------------===//
+// Assembler aliases
+//
+
+defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
+                         (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
+defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
+                         (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
+defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
+                         (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
+defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
+                         (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
+defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
+                         (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
+defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
+                         (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=144587&r1=144586&r2=144587&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Mon Nov 14 17:11:19 2011
@@ -53,3 +53,180 @@
 
 @ CHECK: vbsl	d18, d17, d16           @ encoding: [0xb0,0x21,0x51,0xf3]
 @ CHECK: vbsl	q8, q10, q9             @ encoding: [0xf2,0x01,0x54,0xf3]
+
+
+@ Size suffices are optional.
+        veor q4, q7, q3
+        veor.8 q4, q7, q3
+        veor.16 q4, q7, q3
+        veor.32 q4, q7, q3
+        veor.64 q4, q7, q3
+
+        veor.i8 q4, q7, q3
+        veor.i16 q4, q7, q3
+        veor.i32 q4, q7, q3
+        veor.i64 q4, q7, q3
+
+        veor.s8 q4, q7, q3
+        veor.s16 q4, q7, q3
+        veor.s32 q4, q7, q3
+        veor.s64 q4, q7, q3
+
+        veor.u8 q4, q7, q3
+        veor.u16 q4, q7, q3
+        veor.u32 q4, q7, q3
+        veor.u64 q4, q7, q3
+
+        veor.p8 q4, q7, q3
+        veor.p16 q4, q7, q3
+        veor.f32 q4, q7, q3
+        veor.f64 q4, q7, q3
+
+        veor.f q4, q7, q3
+        veor.d q4, q7, q3
+
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+@ CHECK: veor	q4, q7, q3              @ encoding: [0x56,0x81,0x0e,0xf3]
+
+
+        vand d4, d7, d3
+        vand.8 d4, d7, d3
+        vand.16 d4, d7, d3
+        vand.32 d4, d7, d3
+        vand.64 d4, d7, d3
+
+        vand.i8 d4, d7, d3
+        vand.i16 d4, d7, d3
+        vand.i32 d4, d7, d3
+        vand.i64 d4, d7, d3
+
+        vand.s8 d4, d7, d3
+        vand.s16 d4, d7, d3
+        vand.s32 d4, d7, d3
+        vand.s64 d4, d7, d3
+
+        vand.u8 d4, d7, d3
+        vand.u16 d4, d7, d3
+        vand.u32 d4, d7, d3
+        vand.u64 d4, d7, d3
+
+        vand.p8 d4, d7, d3
+        vand.p16 d4, d7, d3
+        vand.f32 d4, d7, d3
+        vand.f64 d4, d7, d3
+
+        vand.f d4, d7, d3
+        vand.d d4, d7, d3
+
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+@ CHECK: vand	d4, d7, d3              @ encoding: [0x13,0x41,0x07,0xf2]
+
+        vorr d4, d7, d3
+        vorr.8 d4, d7, d3
+        vorr.16 d4, d7, d3
+        vorr.32 d4, d7, d3
+        vorr.64 d4, d7, d3
+
+        vorr.i8 d4, d7, d3
+        vorr.i16 d4, d7, d3
+        vorr.i32 d4, d7, d3
+        vorr.i64 d4, d7, d3
+
+        vorr.s8 d4, d7, d3
+        vorr.s16 d4, d7, d3
+        vorr.s32 q4, q7, q3
+        vorr.s64 q4, q7, q3
+
+        vorr.u8 q4, q7, q3
+        vorr.u16 q4, q7, q3
+        vorr.u32 q4, q7, q3
+        vorr.u64 q4, q7, q3
+
+        vorr.p8 q4, q7, q3
+        vorr.p16 q4, q7, q3
+        vorr.f32 q4, q7, q3
+        vorr.f64 q4, q7, q3
+
+        vorr.f q4, q7, q3
+        vorr.d q4, q7, q3
+
+@ CHECK: vorr	d4, d7, d3              @ encoding: [0x13,0x41,0x27,0xf2]
+@ CHECK: vorr	d4, d7, d3              @ encoding: [0x13,0x41,0x27,0xf2]
+@ CHECK: vorr	d4, d7, d3              @ encoding: [0x13,0x41,0x27,0xf2]
+@ CHECK: vorr	d4, d7, d3              @ encoding: [0x13,0x41,0x27,0xf2]
+@ CHECK: vorr	d4, d7, d3              @ encoding: [0x13,0x41,0x27,0xf2]
+
+@ CHECK: vorr	d4, d7, d3              @ encoding: [0x13,0x41,0x27,0xf2]
+@ CHECK: vorr	d4, d7, d3              @ encoding: [0x13,0x41,0x27,0xf2]
+@ CHECK: vorr	d4, d7, d3              @ encoding: [0x13,0x41,0x27,0xf2]
+@ CHECK: vorr	d4, d7, d3              @ encoding: [0x13,0x41,0x27,0xf2]
+
+@ CHECK: vorr	d4, d7, d3              @ encoding: [0x13,0x41,0x27,0xf2]
+@ CHECK: vorr	d4, d7, d3              @ encoding: [0x13,0x41,0x27,0xf2]
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]
+@ CHECK: vorr	q4, q7, q3              @ encoding: [0x56,0x81,0x2e,0xf2]



From grosbach at apple.com  Mon Nov 14 17:20:14 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 14 Nov 2011 23:20:14 -0000
Subject: [llvm-commits] [llvm] r144588 -
	/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
Message-ID: <20111114232014.B6FE82A6C131@llvm.org>

Author: grosbach
Date: Mon Nov 14 17:20:14 2011
New Revision: 144588

URL: http://llvm.org/viewvc/llvm-project?rev=144588&view=rev
Log:
Split out the plain '.{8|16|32|64}' suffix handling.

Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=144588&r1=144587&r2=144588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 14 17:20:14 2011
@@ -1995,36 +1995,52 @@
 // VFP/NEON Instruction aliases for type suffices.
 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
   InstAlias<!strconcat(opc, dt, asm), Result>;
-multiclass VFPDT8InstAlias<string opc, string asm, dag Result> {
-  def _8 : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
+multiclass VFPDT8ReqInstAlias<string opc, string asm, dag Result> {
   def I8 : VFPDataTypeInstAlias<opc, ".i8", asm, Result>;
   def S8 : VFPDataTypeInstAlias<opc, ".s8", asm, Result>;
   def U8 : VFPDataTypeInstAlias<opc, ".u8", asm, Result>;
   def F8 : VFPDataTypeInstAlias<opc, ".p8", asm, Result>;
 }
-multiclass VFPDT16InstAlias<string opc, string asm, dag Result> {
-  def _16 : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
+// VFPDT8ReqInstAlias plus plain ".8"
+multiclass VFPDT8InstAlias<string opc, string asm, dag Result> {
+  def _8 : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
+  defm : VFPDT8ReqInstAlias<opc, asm, Result>;
+}
+multiclass VFPDT16ReqInstAlias<string opc, string asm, dag Result> {
   def I16 : VFPDataTypeInstAlias<opc, ".i16", asm, Result>;
   def S16 : VFPDataTypeInstAlias<opc, ".s16", asm, Result>;
   def U16 : VFPDataTypeInstAlias<opc, ".u16", asm, Result>;
   def F16 : VFPDataTypeInstAlias<opc, ".p16", asm, Result>;
 }
-multiclass VFPDT32InstAlias<string opc, string asm, dag Result> {
-  def _32 : VFPDataTypeInstAlias<opc, ".32",  asm, Result>;
+// VFPDT16ReqInstAlias plus plain ".16"
+multiclass VFPDT16InstAlias<string opc, string asm, dag Result> {
+  def _16 : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
+  defm : VFPDT16ReqInstAlias<opc, asm, Result>;
+}
+multiclass VFPDT32ReqInstAlias<string opc, string asm, dag Result> {
   def I32 : VFPDataTypeInstAlias<opc, ".i32", asm, Result>;
   def S32 : VFPDataTypeInstAlias<opc, ".s32", asm, Result>;
   def U32 : VFPDataTypeInstAlias<opc, ".u32", asm, Result>;
   def F32 : VFPDataTypeInstAlias<opc, ".f32", asm, Result>;
   def F   : VFPDataTypeInstAlias<opc, ".f",   asm, Result>;
 }
-multiclass VFPDT64InstAlias<string opc, string asm, dag Result> {
-  def _64 : VFPDataTypeInstAlias<opc, ".64",  asm, Result>;
+// VFPDT32ReqInstAlias plus plain ".32"
+multiclass VFPDT32InstAlias<string opc, string asm, dag Result> {
+  def _32 : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
+  defm : VFPDT32ReqInstAlias<opc, asm, Result>;
+}
+multiclass VFPDT64ReqInstAlias<string opc, string asm, dag Result> {
   def I64 : VFPDataTypeInstAlias<opc, ".i64", asm, Result>;
   def S64 : VFPDataTypeInstAlias<opc, ".s64", asm, Result>;
   def U64 : VFPDataTypeInstAlias<opc, ".u64", asm, Result>;
   def F64 : VFPDataTypeInstAlias<opc, ".f64", asm, Result>;
   def D   : VFPDataTypeInstAlias<opc, ".d",   asm, Result>;
 }
+// VFPDT64ReqInstAlias plus plain ".64"
+multiclass VFPDT64InstAlias<string opc, string asm, dag Result> {
+  def _64 : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
+  defm : VFPDT64ReqInstAlias<opc, asm, Result>;
+}
 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
   defm : VFPDT8InstAlias<opc, asm, Result>;
   defm : VFPDT16InstAlias<opc, asm, Result>;



From grosbach at apple.com  Mon Nov 14 17:21:09 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 14 Nov 2011 23:21:09 -0000
Subject: [llvm-commits] [llvm] r144589 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20111114232109.609C82A6C131@llvm.org>

Author: grosbach
Date: Mon Nov 14 17:21:09 2011
New Revision: 144589

URL: http://llvm.org/viewvc/llvm-project?rev=144589&view=rev
Log:
Add explanatory comment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=144589&r1=144588&r2=144589&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 14 17:21:09 2011
@@ -5185,6 +5185,7 @@
 // Assembler aliases
 //
 
+// VAND/VEOR/VORR accept but do not require a type suffix.
 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
                          (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",



From grosbach at apple.com  Mon Nov 14 17:32:59 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 14 Nov 2011 23:32:59 -0000
Subject: [llvm-commits] [llvm] r144592 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-vld-encoding.s
Message-ID: <20111114233259.B23062A6C131@llvm.org>

Author: grosbach
Date: Mon Nov 14 17:32:59 2011
New Revision: 144592

URL: http://llvm.org/viewvc/llvm-project?rev=144592&view=rev
Log:
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.

rdar://10435076

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-vld-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=144592&r1=144591&r2=144592&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 14 17:32:59 2011
@@ -5198,3 +5198,44 @@
                          (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
                          (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
+
+// VLD1 requires a size suffix, but also accepts type specific variants.
+// Load one D register.
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d8 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d16 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d32 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d64 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
+
+// Load two D registers.
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1q8 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1q16 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1q32 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1q64 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
+
+// Load three D registers.
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d8T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d16T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d32T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d64T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
+
+// Load four D registers.
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d8Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d16Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d32Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
+                          (VLD1d64Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=144592&r1=144591&r2=144592&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Mon Nov 14 17:32:59 2011
@@ -223,3 +223,31 @@
 
 @ CHECK: vld1.8	{d6, d7}, [r9]          @ encoding: [0x0f,0x6a,0x29,0xf4]
 @ CHECK: vld1.8	{d6, d7, d8, d9}, [r9]  @ encoding: [0x0f,0x62,0x29,0xf4]
+
+
+@ Spot-check additional size-suffix aliases.
+        vld1.8 {d2}, [r2]
+        vld1.p8 {d2}, [r2]
+        vld1.u8 {d2}, [r2]
+
+        vld1.8 {q2}, [r2]
+        vld1.p8 {q2}, [r2]
+        vld1.u8 {q2}, [r2]
+        vld1.f32 {q2}, [r2]
+
+        vld1.u8 {d2, d3, d4}, [r2]
+        vld1.i32 {d2, d3, d4}, [r2]
+        vld1.f64 {d2, d3, d4}, [r2]
+
+@ CHECK: vld1.8	{d2}, [r2]              @ encoding: [0x0f,0x27,0x22,0xf4]
+@ CHECK: vld1.8	{d2}, [r2]              @ encoding: [0x0f,0x27,0x22,0xf4]
+@ CHECK: vld1.8	{d2}, [r2]              @ encoding: [0x0f,0x27,0x22,0xf4]
+
+@ CHECK: vld1.8	{d4, d5}, [r2]          @ encoding: [0x0f,0x4a,0x22,0xf4]
+@ CHECK: vld1.8	{d4, d5}, [r2]          @ encoding: [0x0f,0x4a,0x22,0xf4]
+@ CHECK: vld1.8	{d4, d5}, [r2]          @ encoding: [0x0f,0x4a,0x22,0xf4]
+@ CHECK: vld1.32 {d4, d5}, [r2]         @ encoding: [0x8f,0x4a,0x22,0xf4]
+
+@ CHECK: vld1.8	{d2, d3, d4}, [r2]      @ encoding: [0x0f,0x26,0x22,0xf4]
+@ CHECK: vld1.32 {d2, d3, d4}, [r2]     @ encoding: [0x8f,0x26,0x22,0xf4]
+@ CHECK: vld1.64 {d2, d3, d4}, [r2]     @ encoding: [0xcf,0x26,0x22,0xf4]



From grosbach at apple.com  Mon Nov 14 17:43:46 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 14 Nov 2011 23:43:46 -0000
Subject: [llvm-commits] [llvm] r144593 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-vst-encoding.s
Message-ID: <20111114234346.D3FF52A6C131@llvm.org>

Author: grosbach
Date: Mon Nov 14 17:43:46 2011
New Revision: 144593

URL: http://llvm.org/viewvc/llvm-project?rev=144593&view=rev
Log:
ARM parsing datatype suffix variants for non-writeback VST1 instructions.

rdar://10435076

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-vst-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=144593&r1=144592&r2=144593&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 14 17:43:46 2011
@@ -5239,3 +5239,47 @@
                           (VLD1d32Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
                           (VLD1d64Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
+
+// VST1 requires a size suffix, but also accepts type specific variants.
+// Load one D register.
+defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+                          (VST1d8 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+                          (VST1d16 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+                          (VST1d32 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+                          (VST1d64 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
+
+// Load two D registers.
+defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+                          (VST1q8 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+                          (VST1q16 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+                          (VST1q32 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+                          (VST1q64 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
+
+// FIXME: The three and four register VST1 instructions haven't been moved
+// to the VecList* encoding yet, so we can't do assembly parsing support
+// for them. Uncomment these when that happens.
+// Load three D registers.
+//defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+//                          (VST1d8T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
+//defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+//                          (VST1d16T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
+//defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+//                          (VST1d32T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
+//defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+//                          (VST1d64T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
+
+// Load four D registers.
+//defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+//                          (VST1d8Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
+//defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+//                          (VST1d16Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
+//defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+//                          (VST1d32Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
+//defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
+//                          (VST1d64Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/neon-vst-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vst-encoding.s?rev=144593&r1=144592&r2=144593&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-vst-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-vst-encoding.s Mon Nov 14 17:43:46 2011
@@ -111,3 +111,24 @@
 @ FIXME: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf4]
 @ FIXME: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf4]
 @ FIXME: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf4]
+
+
+@ Spot-check additional size-suffix aliases.
+
+        vst1.8 {d2}, [r2]
+        vst1.p8 {d2}, [r2]
+        vst1.u8 {d2}, [r2]
+
+        vst1.8 {q2}, [r2]
+        vst1.p8 {q2}, [r2]
+        vst1.u8 {q2}, [r2]
+        vst1.f32 {q2}, [r2]
+
+@ CHECK: vst1.8	{d2}, [r2]              @ encoding: [0x0f,0x27,0x02,0xf4]
+@ CHECK: vst1.8	{d2}, [r2]              @ encoding: [0x0f,0x27,0x02,0xf4]
+@ CHECK: vst1.8	{d2}, [r2]              @ encoding: [0x0f,0x27,0x02,0xf4]
+
+@ CHECK: vst1.8	{d4, d5}, [r2]          @ encoding: [0x0f,0x4a,0x02,0xf4]
+@ CHECK: vst1.8	{d4, d5}, [r2]          @ encoding: [0x0f,0x4a,0x02,0xf4]
+@ CHECK: vst1.8	{d4, d5}, [r2]          @ encoding: [0x0f,0x4a,0x02,0xf4]
+@ CHECK: vst1.32 {d4, d5}, [r2]         @ encoding: [0x8f,0x4a,0x02,0xf4]



From nicholas at mxc.ca  Mon Nov 14 18:14:04 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 15 Nov 2011 00:14:04 -0000
Subject: [llvm-commits] [llvm] r144596 - in /llvm/trunk:
 include/llvm/Support/Compiler.h lib/Support/Valgrind.cpp
Message-ID: <20111115001404.E1D172A6C131@llvm.org>

Author: nicholas
Date: Mon Nov 14 18:14:04 2011
New Revision: 144596

URL: http://llvm.org/viewvc/llvm-project?rev=144596&view=rev
Log:
Fix linking for some users who already have tsan enabled code and are trying to
link it against llvm code, by making our definitions weak. "Some users."

Modified:
    llvm/trunk/include/llvm/Support/Compiler.h
    llvm/trunk/lib/Support/Valgrind.cpp

Modified: llvm/trunk/include/llvm/Support/Compiler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Compiler.h?rev=144596&r1=144595&r2=144596&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/Compiler.h (original)
+++ llvm/trunk/include/llvm/Support/Compiler.h Mon Nov 14 18:14:04 2011
@@ -62,11 +62,18 @@
 #endif
 
 #if (__GNUC__ >= 4)
+#define LLVM_ATTRIBUTE_WEAK __attribute__((__weak__))
+#else
+#define LLVM_ATTRIBUTE_WEAK
+#endif
+
+#if (__GNUC__ >= 4)
 #define BUILTIN_EXPECT(EXPR, VALUE) __builtin_expect((EXPR), (VALUE))
 #else
 #define BUILTIN_EXPECT(EXPR, VALUE) (EXPR)
 #endif
 
+
 // C++ doesn't support 'extern template' of template specializations.  GCC does,
 // but requires __extension__ before it.  In the header, use this:
 //   EXTERN_TEMPLATE_INSTANTIATION(class foo<bar>);

Modified: llvm/trunk/lib/Support/Valgrind.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Valgrind.cpp?rev=144596&r1=144595&r2=144596&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Valgrind.cpp (original)
+++ llvm/trunk/lib/Support/Valgrind.cpp Mon Nov 14 18:14:04 2011
@@ -56,10 +56,10 @@
 // These functions require no implementation, tsan just looks at the arguments
 // they're called with.
 extern "C" {
-void AnnotateHappensBefore(const char *file, int line,
-                           const volatile void *cv) {}
-void AnnotateHappensAfter(const char *file, int line,
-                          const volatile void *cv) {}
-void AnnotateIgnoreWritesBegin(const char *file, int line) {}
-void AnnotateIgnoreWritesEnd(const char *file, int line) {}
+LLVM_ATTRIBUTE_WEAK void AnnotateHappensBefore(const char *file, int line,
+                                               const volatile void *cv) {}
+LLVM_ATTRIBUTE_WEAK void AnnotateHappensAfter(const char *file, int line,
+                                              const volatile void *cv) {}
+LLVM_ATTRIBUTE_WEAK void AnnotateIgnoreWritesBegin(const char *file, int line){}
+LLVM_ATTRIBUTE_WEAK void AnnotateIgnoreWritesEnd(const char *file, int line) {}
 }



From rafael.espindola at gmail.com  Mon Nov 14 18:29:28 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Mon, 14 Nov 2011 19:29:28 -0500
Subject: [llvm-commits] pr11367
In-Reply-To: <75EF0083-6033-42D0-B6E0-9025E93D576B@nondot.org>
References: <CAG3jReJHN2jo=Mv97jR9Ep2jywLTbMPyvF03y6Q_ffU6m0S8wA@mail.gmail.com>
	<B1289D79-A496-43C2-A644-564033AF3EF2@nondot.org>
	<CAG3jReKHb0UwX_66=64n3T8TyS0eOn6OKyko__rBs6AHmz64KQ@mail.gmail.com>
	<75EF0083-6033-42D0-B6E0-9025E93D576B@nondot.org>
Message-ID: <4EC1B268.3030307@gmail.com>

 >> Do you think Matt's patch is OK?
> 
> I'm not the owner of the linker, so I don't really have final say
> here. I think Chris is the only person thats really maintained it
> recently. Peter Collingbourne also seems to be involved since he did
> the LTO changes. I'm not sure what their final opinion is here.
> 
> Obviously, if the default path is the lazy linking (assuming its the
> one most used and beneficial to the majority) then I don't personally
> have a problem. Since LTO now uses it, I assume it would be the
> default.

Well, we should probably not be writing something to just drop it when
we read it, so LTO should be unaffected. Which means I am fine with any
default :-)

CCing the list again so that Chris and Peter see it.

> -Tanya

Cheers,
Rafael

From grosbach at apple.com  Mon Nov 14 19:05:12 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 01:05:12 -0000
Subject: [llvm-commits] [llvm] r144598 -
	/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
Message-ID: <20111115010512.A63C32A6C131@llvm.org>

Author: grosbach
Date: Mon Nov 14 19:05:12 2011
New Revision: 144598

URL: http://llvm.org/viewvc/llvm-project?rev=144598&view=rev
Log:
Tidy up. Formatting.

Modified:
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=144598&r1=144597&r2=144598&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Mon Nov 14 19:05:12 2011
@@ -245,7 +245,7 @@
   if (!Ops[DestOp.first].Constraints[DestOp.second].isNone())
     throw "Operand '" + DestOpName + "' cannot have multiple constraints!";
   Ops[DestOp.first].Constraints[DestOp.second] =
-  CGIOperandList::ConstraintInfo::getTied(FlatOpNo);
+    CGIOperandList::ConstraintInfo::getTied(FlatOpNo);
 }
 
 static void ParseConstraints(const std::string &CStr, CGIOperandList &Ops) {



From dpatel at apple.com  Mon Nov 14 19:11:58 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 15 Nov 2011 01:11:58 -0000
Subject: [llvm-commits] [llvm] r144599 -
	/llvm/trunk/docs/ObjCPropertyDebugInfo.html
Message-ID: <20111115011158.5C3A52A6C131@llvm.org>

Author: dpatel
Date: Mon Nov 14 19:11:58 2011
New Revision: 144599

URL: http://llvm.org/viewvc/llvm-project?rev=144599&view=rev
Log:
Document debug info support  for objective-c properties.

Added:
    llvm/trunk/docs/ObjCPropertyDebugInfo.html

Added: llvm/trunk/docs/ObjCPropertyDebugInfo.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ObjCPropertyDebugInfo.html?rev=144599&view=auto
==============================================================================
--- llvm/trunk/docs/ObjCPropertyDebugInfo.html (added)
+++ llvm/trunk/docs/ObjCPropertyDebugInfo.html Mon Nov 14 19:11:58 2011
@@ -0,0 +1,237 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
+                      "http://www.w3.org/TR/html4/strict.dtd">
+<html>
+<head>
+  <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
+  <title>Debugging Information Extension for Objective C Properties</title>
+  <link rel="stylesheet" href="llvm.css" type="text/css">
+</head>
+<body>
+
+<h1>
+  Debugging Information Extension for Objective C Properties
+</h1>
+
+<ol>
+  <li><a href="#introduction">Introduction</a></li>
+  <li><a href="#proposal">Proposal</a></li>
+  <li><a href="#newattributes">New DWARF Attributes</a></li>
+  <li><a href="#newconstants">New DWARF Constants</a></li>
+
+</ol>
+
+<div class="doc_author">
+  <p>Written by Jim Ingham and Devang Patel </p>
+</div>
+
+<!-- *********************************************************************** -->
+<h2>
+  <a name="introduction">Introduction</a>
+</h2>
+<!-- *********************************************************************** -->
+
+<div>
+<p>Objective C provides a simpler way to declare and define accessor methods 
+using declared properties. The language provides features to declare a 
+property and to let compiler synthesize accessor methods.
+</p>
+
+<p>The debugger lets developer inspect Objective C interfaces and their 
+instance variables and class variables. However, the debugger does not know 
+anything about the properties defined in Objective C interfaces. The debugger
+consumes information generated by compiler in DWARF format. The format does 
+not support encoding of Objective C properties. This proposal describes DWARF
+extensions to encode Objective C properties, which the debugger can use to let
+developers inspect Objective C properties.
+</p>
+
+</div>
+
+
+<!-- *********************************************************************** -->
+<h2>
+  <a name="proposal">Proposal</a>
+</h2>
+<!-- *********************************************************************** -->
+
+<div>
+<p>Objective C properties are always backed by an instance variable. The 
+instance variables backing properties are identified using 
+DW_AT_APPLE_property_name attribute. The instance variables with this 
+attribute may not have data location attributes. The location of instance 
+variables is determined by debugger only after consulting Objective C runtime.
+</p>
+
+<div class="doc_code">
+<pre>
+ at interface I1 { 
+  int n2;
+} 
+
+ at property p1; 
+ at property p2; 
+ at end
+
+ at implementation I1 
+ at synthesize p1; 
+ at synthesize p2 = n2; 
+ at end
+
+
+TAG_structure_type [7] * 
+  AT_APPLE_runtime_class( 0x10 )
+  AT_name( "I1" )
+  AT_decl_file( "Objc_Property.m" ) 
+  AT_decl_line( 3 )
+
+  TAG_member [8] 
+    AT_name( "p1" )
+    AT_APPLE_property_name(???p1???) 
+    AT_type( {0x00000147} ( int ) )
+
+  TAG_member [8] 
+    AT_name( "n2" )
+    AT_APPLE_property_name(???p2???) 
+    AT_type( {0x00000147} ( int ) )
+</pre>
+</div>
+
+<p> Developers can decorate a property with attributes which are encoded using 
+DW_AT_APPLE_property_attribute.
+</p>
+
+<div class="doc_code">
+<pre>
+ at property (readonly, nonatomic) int pr;
+
+
+TAG_member [8] 
+  AT_name(???pr???) 
+  AT_APPLE_property_name(???pr???) 
+  AT_type ( {0x00000147} (int) ) 
+  AT_APPLE_property_attribute (DW_APPLE_PROPERTY_readonly, DW_APPLE_PROPERTY_nonatomic)
+</pre>
+</div>
+
+<p> The setter and getter method names are attached to the property using 
+DW_AT_APPLE_property_setter and DW_AT_APPLE_property_getter attributes.
+</p>
+<div class="doc_code">
+<pre>
+ at interface I1 
+ at property (setter=myOwnP3Setter:) int p3; 
+-(void)myOwnP3Setter:(int)a; 
+ at end
+
+ at implementation I1 
+ at synthesize p3;
+-(void)myOwnP3Setter:(int)a{ } 
+ at end
+
+0x000003bd: TAG_structure_type [7] * 
+              AT_APPLE_runtime_class( 0x10 )
+              AT_name( "I1" )
+              AT_decl_file( "Objc_Property.m" ) 
+              AT_decl_line( 3 )
+0x000003f3: TAG_member [8] 
+              AT_name( "p3" ) 
+              AT_APPLE_property_name(???p3???) 
+              AT_APPLE_property_setter(???myOwnP3Setter:???)
+              AT_type( {0x00000147} ( int ) )
+</pre>
+</div>
+
+</div>
+
+<!-- *********************************************************************** -->
+<h2>
+  <a name="newattributes">New DWARF Attributes</a>
+</h2>
+<!-- *********************************************************************** -->
+
+<div>
+<table border="1" cellspacing="0">
+  <tr>
+    <th width=200 >Attribute</th>
+    <th width=200 >Value</th>
+    <th width=200 >Classes</th>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_property_name</td>
+    <td width=200 >0x3fe8</td>
+    <td width=200 >String</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_property_getter</td>
+    <td width=200 >0x3fe9</td>
+    <td width=200 >String</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_property_setter</td>
+    <td width=200 >0x3fea</td>
+    <td width=200 >String</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_property_attribute</td>
+    <td width=200 >0x3feb</td>
+    <td width=200 >Constant</td>
+  </tr>
+</table>
+
+</div>
+
+<!-- *********************************************************************** -->
+<h2>
+  <a name="newconstants">New DWARF Constants</a>
+</h2>
+<!-- *********************************************************************** -->
+
+<div>
+<table border="1" cellspacing="0">
+  <tr>
+    <th width=200 >Name</th>
+    <th width=200 >Value</th>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_readonly</td>
+    <td width=200 >0x1</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_readwrite</td>
+    <td width=200 >0x2</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_assign</td>
+    <td width=200 >0x4</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_retain</td>
+    <td width=200 >0x8</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_copy</td>
+    <td width=200 >0x10</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_nonatomic</td>
+    <td width=200 >0x20</td>
+  </tr>
+</table>
+
+</div>
+
+<!-- *********************************************************************** -->
+
+<hr>
+<address>
+  <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
+  src="http://jigsaw.w3.org/css-validator/images/vcss-blue" alt="Valid CSS"></a>
+  <a href="http://validator.w3.org/check/referer"><img
+  src="http://www.w3.org/Icons/valid-html401-blue" alt="Valid HTML 4.01"></a>
+
+  <a href="http://llvm.org/">LLVM Compiler Infrastructure</a><br>
+  Last modified: $Date: 2011-11-14 $
+</address>
+
+</body>
+</html>



From dpatel at apple.com  Mon Nov 14 19:14:37 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 15 Nov 2011 01:14:37 -0000
Subject: [llvm-commits] [llvm] r144600 - /llvm/trunk/docs/index.html
Message-ID: <20111115011437.85FCD2A6C131@llvm.org>

Author: dpatel
Date: Mon Nov 14 19:14:37 2011
New Revision: 144600

URL: http://llvm.org/viewvc/llvm-project?rev=144600&view=rev
Log:
Add ObjCPropertyDebugInfo.html

Modified:
    llvm/trunk/docs/index.html

Modified: llvm/trunk/docs/index.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/index.html?rev=144600&r1=144599&r2=144600&view=diff
==============================================================================
--- llvm/trunk/docs/index.html (original)
+++ llvm/trunk/docs/index.html Mon Nov 14 19:14:37 2011
@@ -212,6 +212,9 @@
 <li><a href="BranchWeightMetadata.html">Branch Weight Metadata</a> - Provides
 information about Branch Prediction Information.</li>
 
+<li><a href="ObjCPropertyDebugInfo.html">Objective C Property Debug Info</a> 
+- Debugging information extension for Objective C Property.</li>
+
 </ul>
 
 <!--=======================================================================-->



From stoklund at 2pi.dk  Mon Nov 14 19:15:25 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 15 Nov 2011 01:15:25 -0000
Subject: [llvm-commits] [llvm] r144601 -
	/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
Message-ID: <20111115011525.697722A6C131@llvm.org>

Author: stoklund
Date: Mon Nov 14 19:15:25 2011
New Revision: 144601

URL: http://llvm.org/viewvc/llvm-project?rev=144601&view=rev
Log:
Track register ages more accurately.

Keep track of the last instruction to define each register individually
instead of per DomainValue.  This lets us track more accurately when a
register was last written.

Also track register ages across basic blocks.  When entering a new
basic block, use the least stale predecessor def as a worst case
estimate for register age.

The register age is used to arbitrate between conflicting domains. The
most recently defined register wins.

Modified:
    llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp

Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144601&r1=144600&r2=144601&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Mon Nov 14 19:15:25 2011
@@ -45,7 +45,7 @@
 /// DomainValue for each register, but it may contain multiple execution
 /// domains. A register value is initially created in a single execution
 /// domain, but if we were forced to pay the penalty of a domain crossing, we
-/// keep track of the fact the the register is now available in multiple
+/// keep track of the fact that the register is now available in multiple
 /// domains.
 namespace {
 struct DomainValue {
@@ -57,9 +57,6 @@
   // domains where the register is available for free.
   unsigned AvailableDomains;
 
-  // Position of the last defining instruction.
-  unsigned Dist;
-
   // Pointer to the next DomainValue in a chain.  When two DomainValues are
   // merged, Victim.Next is set to point to Victor, so old DomainValue
   // references can be updated by folowing the chain.
@@ -101,7 +98,7 @@
 
   // Clear this DomainValue and point to next which has all its data.
   void clear() {
-    AvailableDomains = Dist = 0;
+    AvailableDomains = 0;
     Next = 0;
     Instrs.clear();
   }
@@ -109,6 +106,21 @@
 }
 
 namespace {
+/// LiveReg - Information about a live register.
+struct LiveReg {
+  /// Value currently in this register, or NULL when no value is being tracked.
+  /// This counts as a DomainValue reference.
+  DomainValue *Value;
+
+  /// Instruction that defined this register, relative to the beginning of the
+  /// current basic block.  When a LiveReg is used to represent a live-out
+  /// register, this value is relative to the end of the basic block, so it
+  /// will be a negative number.
+  int Def;
+};
+} // anonynous namespace
+
+namespace {
 class ExeDepsFix : public MachineFunctionPass {
   static char ID;
   SpecificBumpPtrAllocator<DomainValue> Allocator;
@@ -120,10 +132,17 @@
   const TargetRegisterInfo *TRI;
   std::vector<int> AliasMap;
   const unsigned NumRegs;
-  DomainValue **LiveRegs;
-  typedef DenseMap<MachineBasicBlock*,DomainValue**> LiveOutMap;
+  LiveReg *LiveRegs;
+  typedef DenseMap<MachineBasicBlock*, LiveReg*> LiveOutMap;
   LiveOutMap LiveOuts;
-  unsigned Distance;
+
+  /// Current instruction number.
+  /// The first instruction in each basic block is 0.
+  int CurInstr;
+
+  /// True when the current block has a predecessor that hasn't been visited
+  /// yet.
+  bool SeenUnknownBackEdge;
 
 public:
   ExeDepsFix(const TargetRegisterClass *rc)
@@ -160,10 +179,10 @@
   void collapse(DomainValue *dv, unsigned domain);
   bool merge(DomainValue *A, DomainValue *B);
 
-  bool enterBasicBlock(MachineBasicBlock*);
+  void enterBasicBlock(MachineBasicBlock*);
   void leaveBasicBlock(MachineBasicBlock*);
   void visitInstr(MachineInstr*);
-  void visitGenericInstr(MachineInstr*);
+  void processDefs(MachineInstr*, bool Kill);
   void visitSoftInstr(MachineInstr*, unsigned mask);
   void visitHardInstr(MachineInstr*, unsigned domain);
 };
@@ -182,7 +201,6 @@
   DomainValue *dv = Avail.empty() ?
                       new(Allocator.Allocate()) DomainValue :
                       Avail.pop_back_val();
-  dv->Dist = Distance;
   if (domain >= 0)
     dv->addDomain(domain);
   assert(dv->Refs == 0 && "Reference count wasn't cleared");
@@ -231,32 +249,31 @@
 /// Set LiveRegs[rx] = dv, updating reference counts.
 void ExeDepsFix::setLiveReg(int rx, DomainValue *dv) {
   assert(unsigned(rx) < NumRegs && "Invalid index");
-  if (!LiveRegs) {
-    LiveRegs = new DomainValue*[NumRegs];
-    std::fill(LiveRegs, LiveRegs+NumRegs, (DomainValue*)0);
-  }
+  assert(LiveRegs && "Must enter basic block first.");
 
-  if (LiveRegs[rx] == dv)
+  if (LiveRegs[rx].Value == dv)
     return;
-  if (LiveRegs[rx])
-    release(LiveRegs[rx]);
-  LiveRegs[rx] = retain(dv);
+  if (LiveRegs[rx].Value)
+    release(LiveRegs[rx].Value);
+  LiveRegs[rx].Value = retain(dv);
 }
 
 // Kill register rx, recycle or collapse any DomainValue.
 void ExeDepsFix::kill(int rx) {
   assert(unsigned(rx) < NumRegs && "Invalid index");
-  if (!LiveRegs || !LiveRegs[rx]) return;
+  assert(LiveRegs && "Must enter basic block first.");
+  if (!LiveRegs[rx].Value)
+    return;
 
-  release(LiveRegs[rx]);
-  LiveRegs[rx] = 0;
+  release(LiveRegs[rx].Value);
+  LiveRegs[rx].Value = 0;
 }
 
 /// Force register rx into domain.
 void ExeDepsFix::force(int rx, unsigned domain) {
   assert(unsigned(rx) < NumRegs && "Invalid index");
-  DomainValue *dv;
-  if (LiveRegs && (dv = LiveRegs[rx])) {
+  assert(LiveRegs && "Must enter basic block first.");
+  if (DomainValue *dv = LiveRegs[rx].Value) {
     if (dv->isCollapsed())
       dv->addDomain(domain);
     else if (dv->hasDomain(domain))
@@ -265,8 +282,8 @@
       // This is an incompatible open DomainValue. Collapse it to whatever and
       // force the new value into domain. This costs a domain crossing.
       collapse(dv, dv->getFirstDomain());
-      assert(LiveRegs[rx] && "Not live after collapse?");
-      LiveRegs[rx]->addDomain(domain);
+      assert(LiveRegs[rx].Value && "Not live after collapse?");
+      LiveRegs[rx].Value->addDomain(domain);
     }
   } else {
     // Set up basic collapsed DomainValue.
@@ -287,7 +304,7 @@
   // If there are multiple users, give them new, unique DomainValues.
   if (LiveRegs && dv->Refs > 1)
     for (unsigned rx = 0; rx != NumRegs; ++rx)
-      if (LiveRegs[rx] == dv)
+      if (LiveRegs[rx].Value == dv)
         setLiveReg(rx, alloc(domain));
 }
 
@@ -303,7 +320,6 @@
   if (!common)
     return false;
   A->AvailableDomains = common;
-  A->Dist = std::max(A->Dist, B->Dist);
   A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
 
   // Clear the old DomainValue so we won't try to swizzle instructions twice.
@@ -312,66 +328,103 @@
   B->Next = retain(A);
 
   for (unsigned rx = 0; rx != NumRegs; ++rx)
-    if (LiveRegs[rx] == B)
+    if (LiveRegs[rx].Value == B)
       setLiveReg(rx, A);
   return true;
 }
 
 // enterBasicBlock - Set up LiveRegs by merging predecessor live-out values.
-// Return true if some predecessor hasn't been processed yet (like on a loop
-// back-edge).
-bool ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
+void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
   // Detect back-edges from predecessors we haven't processed yet.
-  bool seenBackEdge = false;
+  SeenUnknownBackEdge = false;
 
-  // Try to coalesce live-out registers from predecessors.
-  for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(),
+  // Reset instruction counter in each basic block.
+  CurInstr = 0;
+
+  // Set up LiveRegs to represent registers entering MBB.
+  if (!LiveRegs)
+    LiveRegs = new LiveReg[NumRegs];
+
+  // Default values are 'nothing happened a long time ago'.
+  for (unsigned rx = 0; rx != NumRegs; ++rx) {
+    LiveRegs[rx].Value = 0;
+    LiveRegs[rx].Def = -(1 << 20);
+  }
+
+  // This is the entry block.
+  if (MBB->pred_empty()) {
+    for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(),
          e = MBB->livein_end(); i != e; ++i) {
-    int rx = regIndex(*i);
-    if (rx < 0) continue;
-    for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
-           pe = MBB->pred_end(); pi != pe; ++pi) {
-      LiveOutMap::const_iterator fi = LiveOuts.find(*pi);
-      if (fi == LiveOuts.end()) {
-        seenBackEdge = true;
+      int rx = regIndex(*i);
+      if (rx < 0)
         continue;
-      }
-      if (!fi->second)
+      // Treat function live-ins as if they were defined just before the first
+      // instruction.  Usually, function arguments are set up immediately
+      // before the call.
+      LiveRegs[rx].Def = -1;
+    }
+    DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
+    return;
+  }
+
+  // Try to coalesce live-out registers from predecessors.
+  for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
+       pe = MBB->pred_end(); pi != pe; ++pi) {
+    LiveOutMap::const_iterator fi = LiveOuts.find(*pi);
+    if (fi == LiveOuts.end()) {
+      SeenUnknownBackEdge = true;
+      continue;
+    }
+    assert(fi->second && "Can't have NULL entries");
+
+    for (unsigned rx = 0; rx != NumRegs; ++rx) {
+      // Use the most recent predecessor def for each register.
+      LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def);
+
+      DomainValue *pdv = resolve(fi->second[rx].Value);
+      if (!pdv)
         continue;
-      DomainValue *pdv = resolve(fi->second[rx]);
-      if (!pdv) continue;
-      if (!LiveRegs || !LiveRegs[rx]) {
+      if (!LiveRegs[rx].Value) {
         setLiveReg(rx, pdv);
         continue;
       }
 
       // We have a live DomainValue from more than one predecessor.
-      if (LiveRegs[rx]->isCollapsed()) {
+      if (LiveRegs[rx].Value->isCollapsed()) {
         // We are already collapsed, but predecessor is not. Force him.
-        unsigned domain = LiveRegs[rx]->getFirstDomain();
-        if (!pdv->isCollapsed() && pdv->hasDomain(domain))
-          collapse(pdv, domain);
+        unsigned Domain = LiveRegs[rx].Value->getFirstDomain();
+        if (!pdv->isCollapsed() && pdv->hasDomain(Domain))
+          collapse(pdv, Domain);
         continue;
       }
 
       // Currently open, merge in predecessor.
       if (!pdv->isCollapsed())
-        merge(LiveRegs[rx], pdv);
+        merge(LiveRegs[rx].Value, pdv);
       else
         force(rx, pdv->getFirstDomain());
     }
   }
-  return seenBackEdge;
+  DEBUG(dbgs() << "BB#" << MBB->getNumber()
+        << (SeenUnknownBackEdge ? ": incomplete\n" : ": all preds known\n"));
 }
 
 void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) {
+  assert(LiveRegs && "Must enter basic block first.");
   // Save live registers at end of MBB - used by enterBasicBlock().
   // Also use LiveOuts as a visited set to detect back-edges.
-  if (!LiveOuts.insert(std::make_pair(MBB, LiveRegs)).second && LiveRegs) {
+  bool First = LiveOuts.insert(std::make_pair(MBB, LiveRegs)).second;
+
+  if (First) {
+    // LiveRegs was inserted in LiveOuts.  Adjust all defs to be relative to
+    // the end of this block instead of the beginning.
+    for (unsigned i = 0, e = NumRegs; i != e; ++i)
+      LiveRegs[i].Def -= CurInstr;
+  } else {
     // Insertion failed, this must be the second pass.
     // Release all the DomainValues instead of keeping them.
     for (unsigned i = 0, e = NumRegs; i != e; ++i)
-      release(LiveRegs[i]);
+      release(LiveRegs[i].Value);
     delete[] LiveRegs;
   }
   LiveRegs = 0;
@@ -380,15 +433,52 @@
 void ExeDepsFix::visitInstr(MachineInstr *MI) {
   if (MI->isDebugValue())
     return;
-  ++Distance;
-  std::pair<uint16_t, uint16_t> domp = TII->getExecutionDomain(MI);
-  if (domp.first)
-    if (domp.second)
-      visitSoftInstr(MI, domp.second);
+
+  // Update instructions with explicit execution domains.
+  std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(MI);
+  if (DomP.first) {
+    if (DomP.second)
+      visitSoftInstr(MI, DomP.second);
     else
-      visitHardInstr(MI, domp.first);
-  else if (LiveRegs)
-    visitGenericInstr(MI);
+      visitHardInstr(MI, DomP.first);
+  }
+
+  // Process defs to track register ages, and kill values clobbered by generic
+  // instructions.
+  processDefs(MI, !DomP.first);
+}
+
+// Update def-ages for registers defined by MI.
+// If Kill is set, also kill off DomainValues clobbered by the defs.
+void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
+  assert(!MI->isDebugValue() && "Won't process debug values");
+  const MCInstrDesc &MCID = MI->getDesc();
+  for (unsigned i = 0,
+         e = MCID.isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
+         i != e; ++i) {
+    MachineOperand &MO = MI->getOperand(i);
+    if (!MO.isReg())
+      continue;
+    if (MO.isImplicit())
+      break;
+    if (MO.isUse())
+      continue;
+    int rx = regIndex(MO.getReg());
+    if (rx < 0)
+      continue;
+
+    // This instruction explicitly defines rx.
+    DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
+                 << '\t' << *MI);
+
+    LiveRegs[rx].Def = CurInstr;
+
+    // Kill off domains redefined by generic instructions.
+    if (Kill)
+      kill(rx);
+  }
+
+  ++CurInstr;
 }
 
 // A hard instruction only works in one domain. All input registers will be
@@ -430,7 +520,7 @@
       if (!mo.isReg()) continue;
       int rx = regIndex(mo.getReg());
       if (rx < 0) continue;
-      if (DomainValue *dv = LiveRegs[rx]) {
+      if (DomainValue *dv = LiveRegs[rx].Value) {
         // Bitmask of domains that dv and available have in common.
         unsigned common = dv->getCommonDomains(available);
         // Is it possible to use this collapsed register for free?
@@ -459,52 +549,53 @@
 
   // Kill off any remaining uses that don't match available, and build a list of
   // incoming DomainValues that we want to merge.
-  SmallVector<DomainValue*,4> doms;
+  SmallVector<LiveReg, 4> Regs;
   for (SmallVector<int, 4>::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
     int rx = *i;
-    DomainValue *dv = LiveRegs[rx];
+    const LiveReg &LR = LiveRegs[rx];
     // This useless DomainValue could have been missed above.
-    if (!dv->getCommonDomains(available)) {
-      kill(*i);
+    if (!LR.Value->getCommonDomains(available)) {
+      kill(rx);
       continue;
     }
-    // sorted, uniqued insert.
-    bool inserted = false;
-    for (SmallVector<DomainValue*,4>::iterator i = doms.begin(), e = doms.end();
-           i != e && !inserted; ++i) {
-      if (dv == *i)
-        inserted = true;
-      else if (dv->Dist < (*i)->Dist) {
-        inserted = true;
-        doms.insert(i, dv);
+    // Sorted insertion.
+    bool Inserted = false;
+    for (SmallVector<LiveReg, 4>::iterator i = Regs.begin(), e = Regs.end();
+           i != e && !Inserted; ++i) {
+      if (LR.Def < i->Def) {
+        Inserted = true;
+        Regs.insert(i, LR);
       }
     }
-    if (!inserted)
-      doms.push_back(dv);
+    if (!Inserted)
+      Regs.push_back(LR);
   }
 
   // doms are now sorted in order of appearance. Try to merge them all, giving
   // priority to the latest ones.
   DomainValue *dv = 0;
-  while (!doms.empty()) {
+  while (!Regs.empty()) {
     if (!dv) {
-      dv = doms.pop_back_val();
+      dv = Regs.pop_back_val().Value;
       continue;
     }
 
-    DomainValue *latest = doms.pop_back_val();
-    if (merge(dv, latest)) continue;
+    DomainValue *Latest = Regs.pop_back_val().Value;
+    // Skip already merged values.
+    if (Latest == dv || Latest->Next)
+      continue;
+    if (merge(dv, Latest))
+      continue;
 
     // If latest didn't merge, it is useless now. Kill all registers using it.
     for (SmallVector<int,4>::iterator i=used.begin(), e=used.end(); i != e; ++i)
-      if (LiveRegs[*i] == latest)
+      if (LiveRegs[*i].Value == Latest)
         kill(*i);
   }
 
   // dv is the DomainValue we are going to use for this instruction.
   if (!dv)
     dv = alloc();
-  dv->Dist = Distance;
   dv->AvailableDomains = available;
   dv->Instrs.push_back(mi);
 
@@ -514,32 +605,23 @@
     if (!mo.isReg()) continue;
     int rx = regIndex(mo.getReg());
     if (rx < 0) continue;
-    if (!LiveRegs || !LiveRegs[rx] || (mo.isDef() && LiveRegs[rx]!=dv)) {
+    if (!LiveRegs[rx].Value || (mo.isDef() && LiveRegs[rx].Value != dv)) {
       kill(rx);
       setLiveReg(rx, dv);
     }
   }
 }
 
-void ExeDepsFix::visitGenericInstr(MachineInstr *mi) {
-  // Process explicit defs, kill any relevant registers redefined.
-  for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
-    MachineOperand &mo = mi->getOperand(i);
-    if (!mo.isReg()) continue;
-    int rx = regIndex(mo.getReg());
-    if (rx < 0) continue;
-    kill(rx);
-  }
-}
-
 bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
   MF = &mf;
   TII = MF->getTarget().getInstrInfo();
   TRI = MF->getTarget().getRegisterInfo();
   LiveRegs = 0;
-  Distance = 0;
   assert(NumRegs == RC->getNumRegs() && "Bad regclass");
 
+  DEBUG(dbgs() << "********** FIX EXECUTION DEPENDENCIES: "
+               << RC->getName() << " **********\n");
+
   // If no relevant registers are used in the function, we can skip it
   // completely.
   bool anyregs = false;
@@ -567,7 +649,8 @@
   for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
          MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
     MachineBasicBlock *MBB = *MBBI;
-    if (enterBasicBlock(MBB))
+    enterBasicBlock(MBB);
+    if (SeenUnknownBackEdge)
       Loops.push_back(MBB);
     for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
         ++I)
@@ -590,8 +673,8 @@
     if (FI == LiveOuts.end() || !FI->second)
       continue;
     for (unsigned i = 0, e = NumRegs; i != e; ++i)
-      if (FI->second[i])
-        release(FI->second[i]);
+      if (FI->second[i].Value)
+        release(FI->second[i].Value);
     delete[] FI->second;
   }
   LiveOuts.clear();



From stoklund at 2pi.dk  Mon Nov 14 19:15:30 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 15 Nov 2011 01:15:30 -0000
Subject: [llvm-commits] [llvm] r144602 - in /llvm/trunk:
 include/llvm/Target/TargetInstrInfo.h lib/CodeGen/ExecutionDepsFix.cpp
 lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86InstrInfo.h
 test/CodeGen/X86/sse-domains.ll
Message-ID: <20111115011530.9497C2A6C131@llvm.org>

Author: stoklund
Date: Mon Nov 14 19:15:30 2011
New Revision: 144602

URL: http://llvm.org/viewvc/llvm-project?rev=144602&view=rev
Log:
Break false dependencies before partial register updates.

Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.

The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.

The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.

Modified:
    llvm/trunk/include/llvm/Target/TargetInstrInfo.h
    llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/test/CodeGen/X86/sse-domains.ll

Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=144602&r1=144601&r2=144602&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Nov 14 19:15:30 2011
@@ -718,6 +718,74 @@
   ///
   virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
 
+
+  /// getPartialRegUpdateClearance - Returns the preferred minimum clearance
+  /// before an instruction with an unwanted partial register update.
+  ///
+  /// Some instructions only write part of a register, and implicitly need to
+  /// read the other parts of the register.  This may cause unwanted stalls
+  /// preventing otherwise unrelated instructions from executing in parallel in
+  /// an out-of-order CPU.
+  ///
+  /// For example, the x86 instruction cvtsi2ss writes its result to bits
+  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
+  /// the instruction needs to wait for the old value of the register to become
+  /// available:
+  ///
+  ///   addps %xmm1, %xmm0
+  ///   movaps %xmm0, (%rax)
+  ///   cvtsi2ss %rbx, %xmm0
+  ///
+  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
+  /// instruction before it can issue, even though the high bits of %xmm0
+  /// probably aren't needed.
+  ///
+  /// This hook returns the preferred clearance before MI, measured in
+  /// instructions.  Other defs of MI's operand OpNum are avoided in the last N
+  /// instructions before MI.  It should only return a positive value for
+  /// unwanted dependencies.  If the old bits of the defined register have
+  /// useful values, or if MI is determined to otherwise read the dependency,
+  /// the hook should return 0.
+  ///
+  /// The unwanted dependency may be handled by:
+  ///
+  /// 1. Allocating the same register for an MI def and use.  That makes the
+  ///    unwanted dependency identical to a required dependency.
+  ///
+  /// 2. Allocating a register for the def that has no defs in the previous N
+  ///    instructions.
+  ///
+  /// 3. Calling breakPartialRegDependency() with the same arguments.  This
+  ///    allows the target to insert a dependency breaking instruction.
+  ///
+  virtual unsigned
+  getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
+                               const TargetRegisterInfo *TRI) const {
+    // The default implementation returns 0 for no partial register dependency.
+    return 0;
+  }
+
+  /// breakPartialRegDependency - Insert a dependency-breaking instruction
+  /// before MI to eliminate an unwanted dependency on OpNum.
+  ///
+  /// If it wasn't possible to avoid a def in the last N instructions before MI
+  /// (see getPartialRegUpdateClearance), this hook will be called to break the
+  /// unwanted dependency.
+  ///
+  /// On x86, an xorps instruction can be used as a dependency breaker:
+  ///
+  ///   addps %xmm1, %xmm0
+  ///   movaps %xmm0, (%rax)
+  ///   xorps %xmm0, %xmm0
+  ///   cvtsi2ss %rbx, %xmm0
+  ///
+  /// An <imp-kill> operand should be added to MI if an instruction was
+  /// inserted.  This ties the instructions together in the post-ra scheduler.
+  ///
+  virtual void
+  breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
+                            const TargetRegisterInfo *TRI) const {}
+
 private:
   int CallFrameSetupOpcode, CallFrameDestroyOpcode;
 };

Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144602&r1=144601&r2=144602&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Mon Nov 14 19:15:30 2011
@@ -471,11 +471,34 @@
     DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
                  << '\t' << *MI);
 
+    // How many instructions since rx was last written?
+    unsigned Clearance = CurInstr - LiveRegs[rx].Def;
     LiveRegs[rx].Def = CurInstr;
 
     // Kill off domains redefined by generic instructions.
     if (Kill)
       kill(rx);
+
+    // Verify clearance before partial register updates.
+    unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI);
+    if (!Pref)
+      continue;
+    DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);
+    if (Pref > Clearance) {
+      DEBUG(dbgs() << ": Break dependency.\n");
+      TII->breakPartialRegDependency(MI, i, TRI);
+      continue;
+    }
+
+    // The current clearance seems OK, but we may be ignoring a def from a
+    // back-edge.
+    if (!SeenUnknownBackEdge || Pref <= unsigned(CurInstr)) {
+      DEBUG(dbgs() << ": OK.\n");
+      continue;
+    }
+
+    // A def from an unprocessed back-edge may make us break this dependency.
+    DEBUG(dbgs() << ": Wait for back-edge to resolve.\n");
   }
 
   ++CurInstr;
@@ -663,6 +686,10 @@
   for (unsigned i = 0, e = Loops.size(); i != e; ++i) {
     MachineBasicBlock *MBB = Loops[i];
     enterBasicBlock(MBB);
+    for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
+        ++I)
+      if (!I->isDebugValue())
+        processDefs(I, false);
     leaveBasicBlock(MBB);
   }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=144602&r1=144601&r2=144602&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Nov 14 19:15:30 2011
@@ -2761,6 +2761,10 @@
 ///
 static bool hasPartialRegUpdate(unsigned Opcode) {
   switch (Opcode) {
+  case X86::CVTSI2SSrr:
+  case X86::CVTSI2SS64rr:
+  case X86::CVTSI2SDrr:
+  case X86::CVTSI2SD64rr:
   case X86::CVTSD2SSrr:
   case X86::Int_CVTSD2SSrr:
   case X86::CVTSS2SDrr:
@@ -2789,6 +2793,54 @@
   return false;
 }
 
+/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
+/// instructions we would like before a partial register update.
+unsigned X86InstrInfo::
+getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
+                             const TargetRegisterInfo *TRI) const {
+  if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
+    return 0;
+
+  // If MI is marked as reading Reg, the partial register update is wanted.
+  const MachineOperand &MO = MI->getOperand(0);
+  unsigned Reg = MO.getReg();
+  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
+    if (MO.readsReg() || MI->readsVirtualRegister(Reg))
+      return 0;
+  } else {
+    if (MI->readsRegister(Reg, TRI))
+      return 0;
+  }
+
+  // If any of the preceding 16 instructions are reading Reg, insert a
+  // dependency breaking instruction.  The magic number is based on a few
+  // Nehalem experiments.
+  return 16;
+}
+
+void X86InstrInfo::
+breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
+                          const TargetRegisterInfo *TRI) const {
+  unsigned Reg = MI->getOperand(OpNum).getReg();
+  if (X86::VR128RegClass.contains(Reg)) {
+    // These instructions are all floating point domain, so xorps is the best
+    // choice.
+    bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
+    unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
+    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
+      .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
+  } else if (X86::VR256RegClass.contains(Reg)) {
+    // Use vxorps to clear the full ymm register.
+    // It wants to read and write the xmm sub-register.
+    unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
+    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
+      .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
+      .addReg(Reg, RegState::ImplicitDefine);
+  } else
+    return;
+  MI->addRegisterKilled(Reg, TRI, true);
+}
+
 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
                                                   MachineInstr *MI,
                                            const SmallVectorImpl<unsigned> &Ops,

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=144602&r1=144601&r2=144602&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Mon Nov 14 19:15:30 2011
@@ -345,6 +345,11 @@
 
   void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
 
+  unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
+                                        const TargetRegisterInfo *TRI) const;
+  void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
+                                 const TargetRegisterInfo *TRI) const;
+
   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
                                       MachineInstr* MI,
                                       unsigned OpNum,

Modified: llvm/trunk/test/CodeGen/X86/sse-domains.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-domains.ll?rev=144602&r1=144601&r2=144602&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-domains.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-domains.ll Mon Nov 14 19:15:30 2011
@@ -43,3 +43,44 @@
 while.end:
   ret void
 }
+
+; CHECK: f2
+;
+; This loop contains two cvtsi2ss instructions that update the same xmm
+; register.  Verify that the execution dependency fix pass breaks those
+; dependencies by inserting xorps instructions.
+;
+; If the register allocator chooses different registers for the two cvtsi2ss
+; instructions, they are still dependent on themselves.
+; CHECK: xorps [[XMM1:%xmm[0-9]+]]
+; CHECK: , [[XMM1]]
+; CHECK: cvtsi2ss %{{.*}}, [[XMM1]]
+; CHECK: xorps [[XMM2:%xmm[0-9]+]]
+; CHECK: , [[XMM2]]
+; CHECK: cvtsi2ss %{{.*}}, [[XMM2]]
+;
+define float @f2(i32 %m) nounwind uwtable readnone ssp {
+entry:
+  %tobool3 = icmp eq i32 %m, 0
+  br i1 %tobool3, label %for.end, label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %m.addr.07 = phi i32 [ %dec, %for.body ], [ %m, %entry ]
+  %s1.06 = phi float [ %add, %for.body ], [ 0.000000e+00, %entry ]
+  %s2.05 = phi float [ %add2, %for.body ], [ 0.000000e+00, %entry ]
+  %n.04 = phi i32 [ %inc, %for.body ], [ 1, %entry ]
+  %conv = sitofp i32 %n.04 to float
+  %add = fadd float %s1.06, %conv
+  %conv1 = sitofp i32 %m.addr.07 to float
+  %add2 = fadd float %s2.05, %conv1
+  %inc = add nsw i32 %n.04, 1
+  %dec = add nsw i32 %m.addr.07, -1
+  %tobool = icmp eq i32 %dec, 0
+  br i1 %tobool, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  %s1.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
+  %s2.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add2, %for.body ]
+  %sub = fsub float %s1.0.lcssa, %s2.0.lcssa
+  ret float %sub
+}



From nicholas at mxc.ca  Mon Nov 14 19:23:23 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 15 Nov 2011 01:23:23 -0000
Subject: [llvm-commits] [llvm] r144603 - in /llvm/trunk:
 include/llvm/Support/Valgrind.h lib/Support/Valgrind.cpp
Message-ID: <20111115012323.356B52A6C131@llvm.org>

Author: nicholas
Date: Mon Nov 14 19:23:22 2011
New Revision: 144603

URL: http://llvm.org/viewvc/llvm-project?rev=144603&view=rev
Log:
Move WEAK marking to the declaration.

Modified:
    llvm/trunk/include/llvm/Support/Valgrind.h
    llvm/trunk/lib/Support/Valgrind.cpp

Modified: llvm/trunk/include/llvm/Support/Valgrind.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Valgrind.h?rev=144603&r1=144602&r2=144603&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/Valgrind.h (original)
+++ llvm/trunk/include/llvm/Support/Valgrind.h Mon Nov 14 19:23:22 2011
@@ -24,14 +24,12 @@
 // tsan (Thread Sanitizer) is a valgrind-based tool that detects these exact
 // functions by name.
 extern "C" {
-LLVM_ATTRIBUTE_NOINLINE void AnnotateHappensAfter(const char *file, int line,
-                                                  const volatile void *cv);
-LLVM_ATTRIBUTE_NOINLINE void AnnotateHappensBefore(const char *file, int line,
-                                                   const volatile void *cv);
-LLVM_ATTRIBUTE_NOINLINE void AnnotateIgnoreWritesBegin(const char *file,
-                                                       int line);
-LLVM_ATTRIBUTE_NOINLINE void AnnotateIgnoreWritesEnd(const char *file,
-                                                     int line);
+LLVM_ATTRIBUTE_WEAK void AnnotateHappensAfter(const char *file, int line,
+                                              const volatile void *cv);
+LLVM_ATTRIBUTE_WEAK void AnnotateHappensBefore(const char *file, int line,
+                                               const volatile void *cv);
+LLVM_ATTRIBUTE_WEAK void AnnotateIgnoreWritesBegin(const char *file, int line);
+LLVM_ATTRIBUTE_WEAK void AnnotateIgnoreWritesEnd(const char *file, int line);
 }
 #endif
 

Modified: llvm/trunk/lib/Support/Valgrind.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Valgrind.cpp?rev=144603&r1=144602&r2=144603&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Valgrind.cpp (original)
+++ llvm/trunk/lib/Support/Valgrind.cpp Mon Nov 14 19:23:22 2011
@@ -56,10 +56,10 @@
 // These functions require no implementation, tsan just looks at the arguments
 // they're called with.
 extern "C" {
-LLVM_ATTRIBUTE_WEAK void AnnotateHappensBefore(const char *file, int line,
-                                               const volatile void *cv) {}
-LLVM_ATTRIBUTE_WEAK void AnnotateHappensAfter(const char *file, int line,
-                                              const volatile void *cv) {}
-LLVM_ATTRIBUTE_WEAK void AnnotateIgnoreWritesBegin(const char *file, int line){}
-LLVM_ATTRIBUTE_WEAK void AnnotateIgnoreWritesEnd(const char *file, int line) {}
+void AnnotateHappensBefore(const char *file, int line,
+                           const volatile void *cv) {}
+void AnnotateHappensAfter(const char *file, int line,
+                          const volatile void *cv) {}
+void AnnotateIgnoreWritesBegin(const char *file, int line) {}
+void AnnotateIgnoreWritesEnd(const char *file, int line) {}
 }



From grosbach at apple.com  Mon Nov 14 19:46:57 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 01:46:57 -0000
Subject: [llvm-commits] [llvm] r144606 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td utils/TableGen/AsmWriterEmitter.cpp
 utils/TableGen/CodeGenInstruction.cpp
Message-ID: <20111115014657.617422A6C131@llvm.org>

Author: grosbach
Date: Mon Nov 14 19:46:57 2011
New Revision: 144606

URL: http://llvm.org/viewvc/llvm-project?rev=144606&view=rev
Log:
ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.

rdar://10435076

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=144606&r1=144605&r2=144606&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 14 19:46:57 2011
@@ -5209,6 +5209,15 @@
                           (VLD1d32 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
                           (VLD1d64 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
+//        with writeback, fixed stride
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+          (VLD1d8wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+          (VLD1d16wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+          (VLD1d32wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+          (VLD1d64wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
 
 // Load two D registers.
 defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
@@ -5219,6 +5228,15 @@
                           (VLD1q32 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
                           (VLD1q64 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
+//        with writeback, fixed stride
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+          (VLD1q8wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+          (VLD1q16wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+          (VLD1q32wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+          (VLD1q64wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
 
 // Load three D registers.
 defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
@@ -5229,6 +5247,20 @@
                           (VLD1d32T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
                           (VLD1d64T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
+//        with writeback, fixed stride
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+                          (VLD1d8Twb_fixed VecListThreeD:$Vd, zero_reg,
+                                           addrmode6:$Rn, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+                          (VLD1d16Twb_fixed VecListThreeD:$Vd, zero_reg,
+                                            addrmode6:$Rn, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+                          (VLD1d32Twb_fixed VecListThreeD:$Vd, zero_reg,
+                                            addrmode6:$Rn, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+                          (VLD1d64Twb_fixed VecListThreeD:$Vd, zero_reg,
+                                            addrmode6:$Rn, pred:$p)>;
+
 
 // Load four D registers.
 defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
@@ -5239,9 +5271,22 @@
                           (VLD1d32Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
                           (VLD1d64Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
+//        with writeback, fixed stride
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+                          (VLD1d8Qwb_fixed VecListFourD:$Vd, zero_reg,
+                                           addrmode6:$Rn, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+                          (VLD1d16Qwb_fixed VecListFourD:$Vd, zero_reg,
+                                            addrmode6:$Rn, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+                          (VLD1d32Qwb_fixed VecListFourD:$Vd, zero_reg,
+                                            addrmode6:$Rn, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
+                          (VLD1d64Qwb_fixed VecListFourD:$Vd, zero_reg,
+                                            addrmode6:$Rn, pred:$p)>;
 
 // VST1 requires a size suffix, but also accepts type specific variants.
-// Load one D register.
+// Store one D register.
 defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
                           (VST1d8 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
 defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
@@ -5250,8 +5295,17 @@
                           (VST1d32 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
 defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
                           (VST1d64 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
+//        with writeback, fixed stride
+defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
+          (VST1d8wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
+          (VST1d16wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
+          (VST1d32wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
+          (VST1d64wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
 
-// Load two D registers.
+// Store two D registers.
 defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
                           (VST1q8 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
 defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
@@ -5260,6 +5314,15 @@
                           (VST1q32 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
 defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
                           (VST1q64 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
+//        with writeback, fixed stride
+defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
+          (VST1q8wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
+          (VST1q16wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
+          (VST1q32wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
+          (VST1q64wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
 
 // FIXME: The three and four register VST1 instructions haven't been moved
 // to the VecList* encoding yet, so we can't do assembly parsing support

Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=144606&r1=144605&r2=144606&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Mon Nov 14 19:46:57 2011
@@ -900,6 +900,13 @@
           IAP->addCond(Cond);
           break;
         case CodeGenInstAlias::ResultOperand::K_Reg:
+          // If this is zero_reg, something's playing tricks we're not
+          // equipped to handle.
+          if (!CGA->ResultOperands[i].getRegister()) {
+            CantHandle = true;
+            break;
+          }
+
           Cond = std::string("MI->getOperand(") +
             llvm::utostr(i) + ").getReg() == " + Target.getName() +
             "::" + CGA->ResultOperands[i].getRegister()->getName();

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=144606&r1=144605&r2=144606&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Mon Nov 14 19:46:57 2011
@@ -468,9 +468,13 @@
   if (ADI && ADI->getDef()->getName() == "zero_reg") {
 
     // Check if this is an optional def.
-    if (!InstOpRec->isSubClassOf("OptionalDefOperand"))
-      throw TGError(Loc, "reg0 used for result that is not an "
-                    "OptionalDefOperand!");
+    // Tied operands where the source is a sub-operand of a complex operand
+    // need to represent both operands in the alias destination instruction.
+    // Allow zero_reg for the tied portion. This can and should go away once
+    // the MC representation of things doesn't use tied operands at all.
+    //if (!InstOpRec->isSubClassOf("OptionalDefOperand"))
+    //  throw TGError(Loc, "reg0 used for result that is not an "
+    //                "OptionalDefOperand!");
 
     ResOp = ResultOperand(static_cast<Record*>(0));
     return true;
@@ -537,8 +541,11 @@
   unsigned AliasOpNo = 0;
   for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
 
-    // Tied registers don't have an entry in the result dag.
-    if (ResultInst->Operands[i].getTiedRegister() != -1)
+    // Tied registers don't have an entry in the result dag unless they're part
+    // of a complex operand, in which case we include them anyways, as we
+    // don't have any other way to specify the whole operand.
+    if (ResultInst->Operands[i].MINumOperands == 1 &&
+        ResultInst->Operands[i].getTiedRegister() != -1)
       continue;
 
     if (AliasOpNo >= Result->getNumArgs())



From evan.cheng at apple.com  Mon Nov 14 20:12:34 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 15 Nov 2011 02:12:34 -0000
Subject: [llvm-commits] [llvm] r144608 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h
 lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vmov.ll
 test/CodeGen/Thumb2/machine-licm.ll utils/TableGen/EDEmitter.cpp
Message-ID: <20111115021234.90AAC2A6C131@llvm.org>

Author: evancheng
Date: Mon Nov 14 20:12:34 2011
New Revision: 144608

URL: http://llvm.org/viewvc/llvm-project?rev=144608&view=rev
Log:
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
integer variants. rdar://10437054

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.h
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/CodeGen/ARM/vmov.ll
    llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=144608&r1=144607&r2=144608&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Nov 14 20:12:34 2011
@@ -912,6 +912,7 @@
   case ARMISD::VGETLANEs:     return "ARMISD::VGETLANEs";
   case ARMISD::VMOVIMM:       return "ARMISD::VMOVIMM";
   case ARMISD::VMVNIMM:       return "ARMISD::VMVNIMM";
+  case ARMISD::VMOVFPIMM:     return "ARMISD::VMOVFPIMM";
   case ARMISD::VDUP:          return "ARMISD::VDUP";
   case ARMISD::VDUPLANE:      return "ARMISD::VDUPLANE";
   case ARMISD::VEXT:          return "ARMISD::VEXT";
@@ -3986,6 +3987,16 @@
         SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
         return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
       }
+
+      // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
+      if (VT == MVT::v2f32 || VT == MVT::v4f32) {
+        ConstantFPSDNode *C = cast<ConstantFPSDNode>(Op.getOperand(0));
+        int ImmVal = ARM_AM::getFP32Imm(C->getValueAPF());
+        if (ImmVal != -1) {
+          SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
+          return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
+        }
+      }
     }
   }
 

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=144608&r1=144607&r2=144608&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Nov 14 20:12:34 2011
@@ -146,6 +146,9 @@
       VMOVIMM,
       VMVNIMM,
 
+      // Vector move f32 immediate:
+      VMOVFPIMM,
+
       // Vector duplicate:
       VDUP,
       VDUPLANE,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=144608&r1=144607&r2=144608&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Nov 14 20:12:34 2011
@@ -39,6 +39,10 @@
   let PrintMethod = "printNEONModImmOperand";
   let ParserMatchClass = nImmVMOVI32AsmOperand;
 }
+def nImmVMOVF32 : Operand<i32> {
+  let PrintMethod = "printFPImmOperand";
+  let ParserMatchClass = FPImmOperand;
+}
 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
 def nImmSplatI64 : Operand<i32> {
   let PrintMethod = "printNEONModImmOperand";
@@ -173,6 +177,7 @@
 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
 def NEONvmovImm   : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
 def NEONvmvnImm   : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
+def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
 
 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
                                            SDTCisVT<2, i32>]>;
@@ -4513,6 +4518,15 @@
                          (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
                          "vmov", "i64", "$Vd, $SIMM", "",
                          [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
+
+def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
+                         (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
+                         "vmov", "f32", "$Vd, $SIMM", "",
+                         [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
+def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
+                         (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
+                         "vmov", "f32", "$Vd, $SIMM", "",
+                         [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
 } // isReMaterializable
 
 //   VMOV     : Vector Get Lane (move scalar to ARM core register)

Modified: llvm/trunk/test/CodeGen/ARM/vmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmov.ll?rev=144608&r1=144607&r2=144608&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vmov.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vmov.ll Mon Nov 14 20:12:34 2011
@@ -353,3 +353,21 @@
   store <4 x i16> %tmp2, <4 x i16>* %b, align 8
   ret void
 }
+
+; Use vmov.f32 to materialize f32 immediate splats
+; rdar://10437054
+define void @v_mov_v2f32(<2 x float>* nocapture %p) nounwind {
+entry:
+;CHECK: v_mov_v2f32:
+;CHECK: vmov.f32 d{{.*}}, #-1.600000e+01
+  store <2 x float> <float -1.600000e+01, float -1.600000e+01>, <2 x float>* %p, align 4
+  ret void
+}
+
+define void @v_mov_v4f32(<4 x float>* nocapture %p) nounwind {
+entry:
+;CHECK: v_mov_v4f32:
+;CHECK: vmov.f32 q{{.*}}, #3.100000e+01
+  store <4 x float> <float 3.100000e+01, float 3.100000e+01, float 3.100000e+01, float 3.100000e+01>, <4 x float>* %p, align 4
+  ret void
+}

Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=144608&r1=144607&r2=144608&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Mon Nov 14 20:12:34 2011
@@ -51,12 +51,11 @@
 define void @t2(i8* %ptr1, i8* %ptr2) nounwind {
 entry:
 ; CHECK: t2:
-; CHECK: mov.w [[R3:r[0-9]+]], #1065353216
-; CHECK: vdup.32 q{{.*}}, [[R3]]
+; CHECK: vmov.f32 q{{.*}}, #1.000000e+00
   br i1 undef, label %bb1, label %bb2
 
 bb1:
-; CHECK-NEXT: %bb1
+; CHECK: %bb1
   %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]
   %tmp1 = shl i32 %indvar, 2
   %gep1 = getelementptr i8* %ptr1, i32 %tmp1

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=144608&r1=144607&r2=144608&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Nov 14 20:12:34 2011
@@ -607,6 +607,7 @@
   IMM("nImmSplatI32");
   IMM("nImmSplatI64");
   IMM("nImmVMOVI32");
+  IMM("nImmVMOVF32");
   IMM("imm0_7");
   IMM("imm0_15");
   IMM("imm0_255");



From stoklund at 2pi.dk  Mon Nov 14 20:29:48 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 15 Nov 2011 02:29:48 -0000
Subject: [llvm-commits] [llvm] r144611 - in /llvm/trunk/test/CodeGen/X86:
	isint.ll uint64-to-float.ll
Message-ID: <20111115022948.6E1AB2A6C131@llvm.org>

Author: stoklund
Date: Mon Nov 14 20:29:48 2011
New Revision: 144611

URL: http://llvm.org/viewvc/llvm-project?rev=144611&view=rev
Log:
Allow for depencendy-breaking instructions before cvt*.

This should unbreak clang-x86_64-darwin10-RA, but I can't actually
reproduce the failure.

Modified:
    llvm/trunk/test/CodeGen/X86/isint.ll
    llvm/trunk/test/CodeGen/X86/uint64-to-float.ll

Modified: llvm/trunk/test/CodeGen/X86/isint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/isint.ll?rev=144611&r1=144610&r2=144611&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/isint.ll (original)
+++ llvm/trunk/test/CodeGen/X86/isint.ll Mon Nov 14 20:29:48 2011
@@ -19,7 +19,7 @@
 define void @isint_branch(double %d) nounwind {
 ; CHECK: cvt
   %i = fptosi double %d to i32
-; CHECK-NEXT: cvt
+; CHECK: cvt
   %e = sitofp i32 %i to double
 ; CHECK: ucomisd
   %c = fcmp oeq double %d, %e

Modified: llvm/trunk/test/CodeGen/X86/uint64-to-float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/uint64-to-float.ll?rev=144611&r1=144610&r2=144611&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/uint64-to-float.ll (original)
+++ llvm/trunk/test/CodeGen/X86/uint64-to-float.ll Mon Nov 14 20:29:48 2011
@@ -38,7 +38,7 @@
 ; CHECK-NEXT: jns LBB0_2
 ; CHECK: cvtsi2ss
 ; CHECK: LBB0_2
-; CHECK-NEXT: cvtsi2ss
+; CHECK: cvtsi2ss
 define float @test(i64 %a) {
 entry:
   %b = uitofp i64 %a to float



From stoklund at 2pi.dk  Mon Nov 14 21:17:01 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 15 Nov 2011 03:17:01 -0000
Subject: [llvm-commits] [llvm] r144613 -
	/llvm/trunk/test/CodeGen/X86/isint.ll
Message-ID: <20111115031701.F3AE22A6C131@llvm.org>

Author: stoklund
Date: Mon Nov 14 21:17:01 2011
New Revision: 144613

URL: http://llvm.org/viewvc/llvm-project?rev=144613&view=rev
Log:
Really fix test.

Modified:
    llvm/trunk/test/CodeGen/X86/isint.ll

Modified: llvm/trunk/test/CodeGen/X86/isint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/isint.ll?rev=144613&r1=144612&r2=144613&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/isint.ll (original)
+++ llvm/trunk/test/CodeGen/X86/isint.ll Mon Nov 14 21:17:01 2011
@@ -4,7 +4,7 @@
 ; CHECK-NOT: xor
 ; CHECK: cvt
   %i = fptosi double %d to i32
-; CHECK-NEXT: cvt
+; CHECK: cvt
   %e = sitofp i32 %i to double
 ; CHECK: cmpeqsd
   %c = fcmp oeq double %d, %e



From geek4civic at gmail.com  Mon Nov 14 23:24:26 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 15 Nov 2011 05:24:26 -0000
Subject: [llvm-commits] [llvm] r144621 -
	/llvm/trunk/include/llvm/Support/Compiler.h
Message-ID: <20111115052426.F10CE2A6C131@llvm.org>

Author: chapuni
Date: Mon Nov 14 23:24:26 2011
New Revision: 144621

URL: http://llvm.org/viewvc/llvm-project?rev=144621&view=rev
Log:
include/llvm/Support/Compiler.h: Invalidate LLVM_ATTRIBUTE_WEAK on cygming for now.

It triggers generating insane executables with both binutils-2.19.1(msysgit) and 2.22.51.20111013(cygwin).

Modified:
    llvm/trunk/include/llvm/Support/Compiler.h

Modified: llvm/trunk/include/llvm/Support/Compiler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Compiler.h?rev=144621&r1=144620&r2=144621&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/Compiler.h (original)
+++ llvm/trunk/include/llvm/Support/Compiler.h Mon Nov 14 23:24:26 2011
@@ -61,7 +61,7 @@
 #define LLVM_ATTRIBUTE_READONLY
 #endif
 
-#if (__GNUC__ >= 4)
+#if (__GNUC__ >= 4) && !defined(__MINGW32__) && !defined(__CYGWIN__)
 #define LLVM_ATTRIBUTE_WEAK __attribute__((__weak__))
 #else
 #define LLVM_ATTRIBUTE_WEAK



From nicholas at mxc.ca  Mon Nov 14 23:53:47 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 14 Nov 2011 21:53:47 -0800
Subject: [llvm-commits] [llvm] r144621
	-	/llvm/trunk/include/llvm/Support/Compiler.h
In-Reply-To: <20111115052426.F10CE2A6C131@llvm.org>
References: <20111115052426.F10CE2A6C131@llvm.org>
Message-ID: <4EC1FE6B.5030802@mxc.ca>

NAKAMURA Takumi wrote:
> Author: chapuni
> Date: Mon Nov 14 23:24:26 2011
> New Revision: 144621
>
> URL: http://llvm.org/viewvc/llvm-project?rev=144621&view=rev
> Log:
> include/llvm/Support/Compiler.h: Invalidate LLVM_ATTRIBUTE_WEAK on cygming for now.
>
> It triggers generating insane executables with both binutils-2.19.1(msysgit) and 2.22.51.20111013(cygwin).

Thanks for diagnosing this for me!!

Nick

>
> Modified:
>      llvm/trunk/include/llvm/Support/Compiler.h
>
> Modified: llvm/trunk/include/llvm/Support/Compiler.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Compiler.h?rev=144621&r1=144620&r2=144621&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/Compiler.h (original)
> +++ llvm/trunk/include/llvm/Support/Compiler.h Mon Nov 14 23:24:26 2011
> @@ -61,7 +61,7 @@
>   #define LLVM_ATTRIBUTE_READONLY
>   #endif
>
> -#if (__GNUC__>= 4)
> +#if (__GNUC__>= 4)&&  !defined(__MINGW32__)&&  !defined(__CYGWIN__)
>   #define LLVM_ATTRIBUTE_WEAK __attribute__((__weak__))
>   #else
>   #define LLVM_ATTRIBUTE_WEAK
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From craig.topper at gmail.com  Mon Nov 14 23:55:35 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Tue, 15 Nov 2011 05:55:35 -0000
Subject: [llvm-commits] [llvm] r144622 - in /llvm/trunk:
 lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86TargetMachine.cpp
 test/CodeGen/X86/avx-intrinsics-x86.ll test/CodeGen/X86/avx-logic.ll
Message-ID: <20111115055535.EB06B2A6C131@llvm.org>

Author: ctopper
Date: Mon Nov 14 23:55:35 2011
New Revision: 144622

URL: http://llvm.org/viewvc/llvm-project?rev=144622&view=rev
Log:
Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
    llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll
    llvm/trunk/test/CodeGen/X86/avx-logic.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=144622&r1=144621&r2=144622&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Nov 14 23:55:35 2011
@@ -3555,7 +3555,11 @@
   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
-  { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
+  { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
+};
+
+static const unsigned ReplaceableInstrsAVX2[][3] = {
+  //PackedSingle       PackedDouble       PackedInt
   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
@@ -3563,31 +3567,37 @@
   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
-  { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
+  { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    }
 };
 
 // FIXME: Some shuffle and unpack instructions have equivalents in different
 // domains, but they require a bit more work than just switching opcodes.
 
-static const unsigned *lookup(unsigned opcode, unsigned domain) {
+static const unsigned *lookup(unsigned opcode, unsigned domain, bool hasAVX2) {
   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
     if (ReplaceableInstrs[i][domain-1] == opcode)
       return ReplaceableInstrs[i];
+  if (domain != 3 || hasAVX2) // only use PackedInt domain if AVX2 is enabled
+    for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
+      if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
+        return ReplaceableInstrsAVX2[i];
   return 0;
 }
 
 std::pair<uint16_t, uint16_t>
 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
+  bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
   return std::make_pair(domain,
-                        domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
+                  domain && lookup(MI->getOpcode(), domain, hasAVX2) ? 0xe : 0);
 }
 
 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
   assert(Domain>0 && Domain<4 && "Invalid execution domain");
   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
   assert(dom && "Not an SSE instruction");
-  const unsigned *table = lookup(MI->getOpcode(), dom);
+  bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
+  const unsigned *table = lookup(MI->getOpcode(), dom, hasAVX2);
   assert(table && "Cannot change domain");
   MI->setDesc(get(table[Domain-1]));
 }

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=144622&r1=144621&r2=144622&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Nov 14 23:55:35 2011
@@ -140,10 +140,7 @@
       PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
       ShouldPrint = true;
     }
-    if (Subtarget.hasAVX2()) {
-      // FIXME this should be turned on for just AVX, but the pass doesn't check
-      // that instructions are valid before replacing them and there are AVX2
-      // integer instructions in the table.
+    if (Subtarget.hasAVX()) {
       PM.add(createExecutionDependencyFixPass(&X86::VR256RegClass));
       ShouldPrint = true;
     }

Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=144622&r1=144621&r2=144622&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Mon Nov 14 23:55:35 2011
@@ -2021,7 +2021,9 @@
 
 define <32 x i8> @test_x86_avx_loadu_dq_256(i8* %a0) {
   ; CHECK: vmovdqu
-  %res = call <32 x i8> @llvm.x86.avx.loadu.dq.256(i8* %a0) ; <<32 x i8>> [#uses=1]
+  %a1 = call <32 x i8> @llvm.x86.avx.loadu.dq.256(i8* %a0) ; <<32 x i8>> [#uses=1]
+  ; add operation forces the execution domain.
+  %res = add <32 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ret <32 x i8> %res
 }
 declare <32 x i8> @llvm.x86.avx.loadu.dq.256(i8*) nounwind readonly
@@ -2029,7 +2031,9 @@
 
 define <4 x double> @test_x86_avx_loadu_pd_256(i8* %a0) {
   ; CHECK: vmovupd
-  %res = call <4 x double> @llvm.x86.avx.loadu.pd.256(i8* %a0) ; <<4 x double>> [#uses=1]
+  %a1 = call <4 x double> @llvm.x86.avx.loadu.pd.256(i8* %a0) ; <<4 x double>> [#uses=1]
+  ; add operation forces the execution domain.
+  %res = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0>
   ret <4 x double> %res
 }
 declare <4 x double> @llvm.x86.avx.loadu.pd.256(i8*) nounwind readonly
@@ -2157,7 +2161,9 @@
 
 define void @test_x86_avx_movnt_dq_256(i8* %a0, <4 x i64> %a1) {
   ; CHECK: vmovntdq
-  call void @llvm.x86.avx.movnt.dq.256(i8* %a0, <4 x i64> %a1)
+  ; add operation forces the execution domain.
+  %a2 = add <4 x i64> %a1, <i64 1, i64 1, i64 1, i64 1>
+  call void @llvm.x86.avx.movnt.dq.256(i8* %a0, <4 x i64> %a2)
   ret void
 }
 declare void @llvm.x86.avx.movnt.dq.256(i8*, <4 x i64>) nounwind
@@ -2165,7 +2171,8 @@
 
 define void @test_x86_avx_movnt_pd_256(i8* %a0, <4 x double> %a1) {
   ; CHECK: vmovntpd
-  call void @llvm.x86.avx.movnt.pd.256(i8* %a0, <4 x double> %a1)
+  %a2 = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0>
+  call void @llvm.x86.avx.movnt.pd.256(i8* %a0, <4 x double> %a2)
   ret void
 }
 declare void @llvm.x86.avx.movnt.pd.256(i8*, <4 x double>) nounwind
@@ -2258,7 +2265,9 @@
 
 define void @test_x86_avx_storeu_dq_256(i8* %a0, <32 x i8> %a1) {
   ; CHECK: vmovdqu
-  call void @llvm.x86.avx.storeu.dq.256(i8* %a0, <32 x i8> %a1)
+  ; add operation forces the execution domain.
+  %a2 = add <32 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  call void @llvm.x86.avx.storeu.dq.256(i8* %a0, <32 x i8> %a2)
   ret void
 }
 declare void @llvm.x86.avx.storeu.dq.256(i8*, <32 x i8>) nounwind
@@ -2266,7 +2275,9 @@
 
 define void @test_x86_avx_storeu_pd_256(i8* %a0, <4 x double> %a1) {
   ; CHECK: vmovupd
-  call void @llvm.x86.avx.storeu.pd.256(i8* %a0, <4 x double> %a1)
+  ; add operation forces the execution domain.
+  %a2 = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0>
+  call void @llvm.x86.avx.storeu.pd.256(i8* %a0, <4 x double> %a2)
   ret void
 }
 declare void @llvm.x86.avx.storeu.pd.256(i8*, <4 x double>) nounwind

Modified: llvm/trunk/test/CodeGen/X86/avx-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-logic.ll?rev=144622&r1=144621&r2=144622&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-logic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-logic.ll Mon Nov 14 23:55:35 2011
@@ -7,7 +7,9 @@
   %1 = bitcast <4 x double> %y to <4 x i64>
   %and.i = and <4 x i64> %0, %1
   %2 = bitcast <4 x i64> %and.i to <4 x double>
-  ret <4 x double> %2
+  ; add forces execution domain
+  %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %3
 }
 
 ; CHECK: vandpd LCP{{.*}}(%rip)
@@ -16,7 +18,9 @@
   %0 = bitcast <4 x double> %y to <4 x i64>
   %and.i = and <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
   %1 = bitcast <4 x i64> %and.i to <4 x double>
-  ret <4 x double> %1
+  ; add forces execution domain
+  %2 = fadd <4 x double> %1, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %2
 }
 
 ; CHECK: vandps
@@ -45,7 +49,9 @@
   %1 = bitcast <4 x double> %y to <4 x i64>
   %xor.i = xor <4 x i64> %0, %1
   %2 = bitcast <4 x i64> %xor.i to <4 x double>
-  ret <4 x double> %2
+  ; add forces execution domain
+  %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %3
 }
 
 ; CHECK: vxorpd LCP{{.*}}(%rip)
@@ -54,7 +60,9 @@
   %0 = bitcast <4 x double> %y to <4 x i64>
   %xor.i = xor <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
   %1 = bitcast <4 x i64> %xor.i to <4 x double>
-  ret <4 x double> %1
+  ; add forces execution domain
+  %2 = fadd <4 x double> %1, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %2
 }
 
 ; CHECK: vxorps
@@ -83,7 +91,9 @@
   %1 = bitcast <4 x double> %y to <4 x i64>
   %or.i = or <4 x i64> %0, %1
   %2 = bitcast <4 x i64> %or.i to <4 x double>
-  ret <4 x double> %2
+  ; add forces execution domain
+  %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %3
 }
 
 ; CHECK: vorpd LCP{{.*}}(%rip)
@@ -92,7 +102,9 @@
   %0 = bitcast <4 x double> %y to <4 x i64>
   %or.i = or <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507>
   %1 = bitcast <4 x i64> %or.i to <4 x double>
-  ret <4 x double> %1
+  ; add forces execution domain
+  %2 = fadd <4 x double> %1, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %2
 }
 
 ; CHECK: vorps
@@ -122,7 +134,9 @@
   %1 = bitcast <4 x double> %y to <4 x i64>
   %and.i = and <4 x i64> %1, %neg.i
   %2 = bitcast <4 x i64> %and.i to <4 x double>
-  ret <4 x double> %2
+  ; add forces execution domain
+  %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %3
 }
 
 ; CHECK: vandnpd (%
@@ -134,7 +148,9 @@
   %1 = bitcast <4 x double> %tmp2 to <4 x i64>
   %and.i = and <4 x i64> %1, %neg.i
   %2 = bitcast <4 x i64> %and.i to <4 x double>
-  ret <4 x double> %2
+  ; add forces execution domain
+  %3 = fadd <4 x double> %2, <double 0x0, double 0x0, double 0x0, double 0x0>
+  ret <4 x double> %3
 }
 
 ; CHECK: vandnps



From chandlerc at gmail.com  Tue Nov 15 00:26:43 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Tue, 15 Nov 2011 06:26:43 -0000
Subject: [llvm-commits] [llvm] r144627 - in /llvm/trunk:
 lib/CodeGen/MachineBlockPlacement.cpp test/CodeGen/X86/block-placement.ll
Message-ID: <20111115062643.555672A6C131@llvm.org>

Author: chandlerc
Date: Tue Nov 15 00:26:43 2011
New Revision: 144627

URL: http://llvm.org/viewvc/llvm-project?rev=144627&view=rev
Log:
Rather than trying to use the loop block sequence *or* the function
block sequence when recovering from unanalyzable control flow
constructs, *always* use the function sequence. I'm not sure why I ever
went down the path of trying to use the loop sequence, it is
fundamentally not the correct sequence to use. We're trying to preserve
the incoming layout in the cases of unreasonable control flow, and that
is only encoded at the function level. We already have a filter to
select *exactly* the sub-set of blocks within the function that we're
trying to form into a chain.

The resulting code layout is also significantly better because of this.
In several places we were ending up with completely unreasonable control
flow constructs due to the ordering chosen by the loop structure for its
internal storage. This change removes a completely wasteful vector of
basic blocks, saving memory allocation in the common case even though it
costs us CPU in the fairly rare case of unnatural loops. Finally, it
fixes the latest crasher reduced out of GCC's single source. Thanks
again to Benjamin Kramer for the reduction, my bugpoint skills failed at
it.

Modified:
    llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
    llvm/trunk/test/CodeGen/X86/block-placement.ll

Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=144627&r1=144626&r2=144627&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Tue Nov 15 00:26:43 2011
@@ -214,11 +214,12 @@
   MachineBasicBlock *selectBestCandidateBlock(
       BlockChain &Chain, SmallVectorImpl<MachineBasicBlock *> &WorkList,
       const BlockFilterSet *BlockFilter);
-  MachineBasicBlock *getFirstUnplacedBlock(const BlockChain &PlacedChain,
-                                           ArrayRef<MachineBasicBlock *> Blocks,
-                                           unsigned &PrevUnplacedBlockIdx);
+  MachineBasicBlock *getFirstUnplacedBlock(
+      MachineFunction &F,
+      const BlockChain &PlacedChain,
+      MachineFunction::iterator &PrevUnplacedBlockIt,
+      const BlockFilterSet *BlockFilter);
   void buildChain(MachineBasicBlock *BB, BlockChain &Chain,
-                  ArrayRef<MachineBasicBlock *> Blocks,
                   SmallVectorImpl<MachineBasicBlock *> &BlockWorkList,
                   const BlockFilterSet *BlockFilter = 0);
   void buildLoopChains(MachineFunction &F, MachineLoop &L);
@@ -444,18 +445,20 @@
 ///
 /// This routine is called when we are unable to use the CFG to walk through
 /// all of the basic blocks and form a chain due to unnatural loops in the CFG.
-/// We walk through the sequence of blocks, starting from the
-/// LastUnplacedBlockIdx. We update this index to avoid re-scanning the entire
-/// sequence on repeated calls to this routine.
+/// We walk through the function's blocks in order, starting from the
+/// LastUnplacedBlockIt. We update this iterator on each call to avoid
+/// re-scanning the entire sequence on repeated calls to this routine.
 MachineBasicBlock *MachineBlockPlacement::getFirstUnplacedBlock(
-    const BlockChain &PlacedChain,
-    ArrayRef<MachineBasicBlock *> Blocks,
-    unsigned &PrevUnplacedBlockIdx) {
-  for (unsigned i = PrevUnplacedBlockIdx, e = Blocks.size(); i != e; ++i) {
-    MachineBasicBlock *BB = Blocks[i];
-    if (BlockToChain[BB] != &PlacedChain) {
-      PrevUnplacedBlockIdx = i;
-      return BB;
+    MachineFunction &F, const BlockChain &PlacedChain,
+    MachineFunction::iterator &PrevUnplacedBlockIt,
+    const BlockFilterSet *BlockFilter) {
+  for (MachineFunction::iterator I = PrevUnplacedBlockIt, E = F.end(); I != E;
+       ++I) {
+    if (BlockFilter && !BlockFilter->count(I))
+      continue;
+    if (BlockToChain[I] != &PlacedChain) {
+      PrevUnplacedBlockIt = I;
+      return I;
     }
   }
   return 0;
@@ -464,14 +467,14 @@
 void MachineBlockPlacement::buildChain(
     MachineBasicBlock *BB,
     BlockChain &Chain,
-    ArrayRef<MachineBasicBlock *> Blocks,
     SmallVectorImpl<MachineBasicBlock *> &BlockWorkList,
     const BlockFilterSet *BlockFilter) {
   assert(BB);
   assert(BlockToChain[BB] == &Chain);
   assert(*Chain.begin() == BB);
   SmallVector<MachineOperand, 4> Cond; // For AnalyzeBranch.
-  unsigned PrevUnplacedBlockIdx = 0;
+  MachineFunction &F = *BB->getParent();
+  MachineFunction::iterator PrevUnplacedBlockIt = F.begin();
 
   MachineBasicBlock *LoopHeaderBB = BB;
   markChainSuccessors(Chain, LoopHeaderBB, BlockWorkList, BlockFilter);
@@ -510,7 +513,8 @@
       BestSucc = selectBestCandidateBlock(Chain, BlockWorkList, BlockFilter);
 
     if (!BestSucc) {
-      BestSucc = getFirstUnplacedBlock(Chain, Blocks, PrevUnplacedBlockIdx);
+      BestSucc = getFirstUnplacedBlock(F, Chain, PrevUnplacedBlockIt,
+                                       BlockFilter);
       if (!BestSucc)
         break;
 
@@ -579,8 +583,7 @@
       BlockWorkList.push_back(*BI);
   }
 
-  buildChain(*L.block_begin(), LoopChain, L.getBlocks(), BlockWorkList,
-             &LoopBlockSet);
+  buildChain(*L.block_begin(), LoopChain, BlockWorkList, &LoopBlockSet);
 
   DEBUG({
     // Crash at the end so we get all of the debugging output first.
@@ -630,17 +633,11 @@
        ++LI)
     buildLoopChains(F, **LI);
 
-  // We need a vector of blocks so that buildChain can handle unnatural CFG
-  // constructs by searching for unplaced blocks and just concatenating them.
-  SmallVector<MachineBasicBlock *, 16> Blocks;
-  Blocks.reserve(F.size());
-
   SmallVector<MachineBasicBlock *, 16> BlockWorkList;
 
   SmallPtrSet<BlockChain *, 4> UpdatedPreds;
   for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) {
     MachineBasicBlock *BB = &*FI;
-    Blocks.push_back(BB);
     BlockChain &Chain = *BlockToChain[BB];
     if (!UpdatedPreds.insert(&Chain))
       continue;
@@ -663,7 +660,7 @@
   }
 
   BlockChain &FunctionChain = *BlockToChain[&F.front()];
-  buildChain(&F.front(), FunctionChain, Blocks, BlockWorkList);
+  buildChain(&F.front(), FunctionChain, BlockWorkList);
 
   typedef SmallPtrSet<MachineBasicBlock *, 16> FunctionBlockSetType;
   DEBUG({

Modified: llvm/trunk/test/CodeGen/X86/block-placement.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=144627&r1=144626&r2=144627&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/block-placement.ll (original)
+++ llvm/trunk/test/CodeGen/X86/block-placement.ll Tue Nov 15 00:26:43 2011
@@ -241,8 +241,8 @@
 ; CHECK: unnatural_cfg1
 ; CHECK: %entry
 ; CHECK: %loop.body1
-; CHECK: %loop.body3
 ; CHECK: %loop.body2
+; CHECK: %loop.body3
 
 entry:
   br label %loop.header
@@ -272,6 +272,77 @@
   br label %loop.body3
 }
 
+define void @unnatural_cfg2() {
+; Test that we can handle a loop with a nested natural loop *and* an unnatural
+; loop. This was reduced from a crash on block placement when run over
+; single-source GCC.
+; CHECK: unnatural_cfg2
+; CHECK: %entry
+; CHECK: %loop.header
+; CHECK: %loop.body1
+; CHECK: %loop.body2
+; CHECK: %loop.body3
+; CHECK: %loop.inner1.begin
+; The end block is folded with %loop.body3...
+; CHECK-NOT: %loop.inner1.end
+; CHECK: %loop.body4
+; CHECK: %loop.inner2.begin
+; The loop.inner2.end block is folded
+; CHECK: %bail
+
+entry:
+  br label %loop.header
+
+loop.header:
+  %comp0 = icmp eq i32* undef, null
+  br i1 %comp0, label %bail, label %loop.body1
+
+loop.body1:
+  %val0 = load i32** undef, align 4
+  br i1 undef, label %loop.body2, label %loop.inner1.begin
+
+loop.body2:
+  br i1 undef, label %loop.body4, label %loop.body3
+
+loop.body3:
+  %ptr1 = getelementptr inbounds i32* %val0, i32 0
+  %castptr1 = bitcast i32* %ptr1 to i32**
+  %val1 = load i32** %castptr1, align 4
+  br label %loop.inner1.begin
+
+loop.inner1.begin:
+  %valphi = phi i32* [ %val2, %loop.inner1.end ], [ %val1, %loop.body3 ], [ %val0, %loop.body1 ]
+  %castval = bitcast i32* %valphi to i32*
+  %comp1 = icmp eq i32 undef, 48
+  br i1 %comp1, label %loop.inner1.end, label %loop.body4
+
+loop.inner1.end:
+  %ptr2 = getelementptr inbounds i32* %valphi, i32 0
+  %castptr2 = bitcast i32* %ptr2 to i32**
+  %val2 = load i32** %castptr2, align 4
+  br label %loop.inner1.begin
+
+loop.body4.dead:
+  br label %loop.body4
+
+loop.body4:
+  %comp2 = icmp ult i32 undef, 3
+  br i1 %comp2, label %loop.inner2.begin, label %loop.end
+
+loop.inner2.begin:
+  br i1 false, label %loop.end, label %loop.inner2.end
+
+loop.inner2.end:
+  %comp3 = icmp eq i32 undef, 1769472
+  br i1 %comp3, label %loop.end, label %loop.inner2.begin
+
+loop.end:
+  br label %loop.header
+
+bail:
+  unreachable
+}
+
 define i32 @problematic_switch() {
 ; This function's CFG caused overlow in the machine branch probability
 ; calculation, triggering asserts. Make sure we don't crash on it.



From evan.cheng at apple.com  Tue Nov 15 00:26:51 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 15 Nov 2011 06:26:51 -0000
Subject: [llvm-commits] [llvm] r144628 -
	/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
Message-ID: <20111115062651.71B0F2A6C131@llvm.org>

Author: evancheng
Date: Tue Nov 15 00:26:51 2011
New Revision: 144628

URL: http://llvm.org/viewvc/llvm-project?rev=144628&view=rev
Log:
Set SeenStore to true to prevent loads from being moved; also eliminates a non-deterministic behavior.

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=144628&r1=144627&r2=144628&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Nov 15 00:26:51 2011
@@ -924,7 +924,7 @@
   if (isTwoAddrUse(*KillMI, Reg, DstReg))
     return false;
 
-  bool SeenStore;
+  bool SeenStore = true;
   if (!MI->isSafeToMove(TII, AA, SeenStore))
     return false;
 
@@ -1071,7 +1071,7 @@
   if (isTwoAddrUse(*KillMI, Reg, DstReg))
     return false;
 
-  bool SeenStore;
+  bool SeenStore = true;
   if (!KillMI->isSafeToMove(TII, AA, SeenStore))
     return false;
 



From craig.topper at gmail.com  Tue Nov 15 00:39:01 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Tue, 15 Nov 2011 06:39:01 -0000
Subject: [llvm-commits] [llvm] r144629 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Message-ID: <20111115063901.8D0552A6C131@llvm.org>

Author: ctopper
Date: Tue Nov 15 00:39:01 2011
New Revision: 144629

URL: http://llvm.org/viewvc/llvm-project?rev=144629&view=rev
Log:
Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=144629&r1=144628&r2=144629&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Nov 15 00:39:01 2011
@@ -3573,14 +3573,17 @@
 // FIXME: Some shuffle and unpack instructions have equivalents in different
 // domains, but they require a bit more work than just switching opcodes.
 
-static const unsigned *lookup(unsigned opcode, unsigned domain, bool hasAVX2) {
+static const unsigned *lookup(unsigned opcode, unsigned domain) {
   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
     if (ReplaceableInstrs[i][domain-1] == opcode)
       return ReplaceableInstrs[i];
-  if (domain != 3 || hasAVX2) // only use PackedInt domain if AVX2 is enabled
-    for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
-      if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
-        return ReplaceableInstrsAVX2[i];
+  return 0;
+}
+
+static const unsigned *lookupAVX2(unsigned opcode, unsigned domain) {
+  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
+    if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
+      return ReplaceableInstrsAVX2[i];
   return 0;
 }
 
@@ -3588,16 +3591,21 @@
 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
   bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
-  return std::make_pair(domain,
-                  domain && lookup(MI->getOpcode(), domain, hasAVX2) ? 0xe : 0);
+  uint16_t validDomains = 0;
+  if (domain && lookup(MI->getOpcode(), domain))
+    validDomains = 0xe;
+  else if (domain && lookupAVX2(MI->getOpcode(), domain))
+    validDomains = hasAVX2 ? 0xe : 0x6;
+  return std::make_pair(domain, validDomains);
 }
 
 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
   assert(Domain>0 && Domain<4 && "Invalid execution domain");
   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
   assert(dom && "Not an SSE instruction");
-  bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
-  const unsigned *table = lookup(MI->getOpcode(), dom, hasAVX2);
+  const unsigned *table = lookup(MI->getOpcode(), dom);
+  if (!table) // try the other table
+    table = lookupAVX2(MI->getOpcode(), dom);
   assert(table && "Cannot change domain");
   MI->setDesc(get(table[Domain-1]));
 }



From stoklund at 2pi.dk  Tue Nov 15 00:54:12 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 14 Nov 2011 22:54:12 -0800
Subject: [llvm-commits] [llvm] r144622 - in /llvm/trunk:
	lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86TargetMachine.cpp
	test/CodeGen/X86/avx-intrinsics-x86.ll test/CodeGen/X86/avx-logic.ll
In-Reply-To: <20111115055535.EB06B2A6C131@llvm.org>
References: <20111115055535.EB06B2A6C131@llvm.org>
Message-ID: <947DF93D-22AD-4681-8F76-82A9EEC2A9AA@2pi.dk>


On Nov 14, 2011, at 9:55 PM, Craig Topper wrote:

> --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Nov 14 23:55:35 2011
> @@ -140,10 +140,7 @@
>       PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
>       ShouldPrint = true;
>     }
> -    if (Subtarget.hasAVX2()) {
> -      // FIXME this should be turned on for just AVX, but the pass doesn't check
> -      // that instructions are valid before replacing them and there are AVX2
> -      // integer instructions in the table.
> +    if (Subtarget.hasAVX()) {
>       PM.add(createExecutionDependencyFixPass(&X86::VR256RegClass));
>       ShouldPrint = true;
>     }

Perhaps you could change this back to the simpler (Subtarget.hasSSE2() || Subtarget.hasAVX())?

It doesn't make a difference if you pass the VR128 or VR256 register class. The pass collapses aliases anyway.

/jakob

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From stoklund at 2pi.dk  Tue Nov 15 01:13:03 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 15 Nov 2011 07:13:03 -0000
Subject: [llvm-commits] [llvm] r144630 - in /llvm/trunk/test/CodeGen/X86:
	isint.ll uint64-to-float.ll
Message-ID: <20111115071303.5708D2A6C131@llvm.org>

Author: stoklund
Date: Tue Nov 15 01:13:03 2011
New Revision: 144630

URL: http://llvm.org/viewvc/llvm-project?rev=144630&view=rev
Log:
Revert r144611 and r144613.

These tests are actually correct, clang was miscompiling ExeDepsFix::processUses.

Evan fixed the miscompilation in r144628.

Modified:
    llvm/trunk/test/CodeGen/X86/isint.ll
    llvm/trunk/test/CodeGen/X86/uint64-to-float.ll

Modified: llvm/trunk/test/CodeGen/X86/isint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/isint.ll?rev=144630&r1=144629&r2=144630&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/isint.ll (original)
+++ llvm/trunk/test/CodeGen/X86/isint.ll Tue Nov 15 01:13:03 2011
@@ -4,7 +4,7 @@
 ; CHECK-NOT: xor
 ; CHECK: cvt
   %i = fptosi double %d to i32
-; CHECK: cvt
+; CHECK-NEXT: cvt
   %e = sitofp i32 %i to double
 ; CHECK: cmpeqsd
   %c = fcmp oeq double %d, %e
@@ -19,7 +19,7 @@
 define void @isint_branch(double %d) nounwind {
 ; CHECK: cvt
   %i = fptosi double %d to i32
-; CHECK: cvt
+; CHECK-NEXT: cvt
   %e = sitofp i32 %i to double
 ; CHECK: ucomisd
   %c = fcmp oeq double %d, %e

Modified: llvm/trunk/test/CodeGen/X86/uint64-to-float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/uint64-to-float.ll?rev=144630&r1=144629&r2=144630&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/uint64-to-float.ll (original)
+++ llvm/trunk/test/CodeGen/X86/uint64-to-float.ll Tue Nov 15 01:13:03 2011
@@ -38,7 +38,7 @@
 ; CHECK-NEXT: jns LBB0_2
 ; CHECK: cvtsi2ss
 ; CHECK: LBB0_2
-; CHECK: cvtsi2ss
+; CHECK-NEXT: cvtsi2ss
 define float @test(i64 %a) {
 entry:
   %b = uitofp i64 %a to float



From jay.foad at gmail.com  Tue Nov 15 01:24:32 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 15 Nov 2011 07:24:32 -0000
Subject: [llvm-commits] [llvm] r144631 - in /llvm/trunk/lib/Target:
 ARM/ARMFastISel.cpp ARM/ARMISelLowering.cpp CellSPU/SPUISelDAGToDAG.cpp
 MSP430/MSP430ISelLowering.cpp PowerPC/PPCISelLowering.cpp
 X86/X86ISelLowering.cpp X86/X86InstrBuilder.h X86/X86InstrInfo.cpp
Message-ID: <20111115072433.17C5B2A6C131@llvm.org>

Author: foad
Date: Tue Nov 15 01:24:32 2011
New Revision: 144631

URL: http://llvm.org/viewvc/llvm-project?rev=144631&view=rev
Log:
Remove some unnecessary includes of PseudoSourceValue.h.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
    llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrBuilder.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144631&r1=144630&r2=144631&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Nov 15 01:24:32 2011
@@ -37,7 +37,6 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Support/CallSite.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=144631&r1=144630&r2=144631&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Nov 15 01:24:32 2011
@@ -40,7 +40,6 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/Target/TargetOptions.h"

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=144631&r1=144630&r2=144631&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Tue Nov 15 01:24:32 2011
@@ -22,7 +22,6 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Constants.h"

Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=144631&r1=144630&r2=144631&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Tue Nov 15 01:24:32 2011
@@ -29,7 +29,6 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/CodeGen/ValueTypes.h"

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=144631&r1=144630&r2=144631&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Nov 15 01:24:32 2011
@@ -23,7 +23,6 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/CallingConv.h"

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144631&r1=144630&r2=144631&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Nov 15 01:24:32 2011
@@ -35,7 +35,6 @@
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"

Modified: llvm/trunk/lib/Target/X86/X86InstrBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrBuilder.h?rev=144631&r1=144630&r2=144631&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrBuilder.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrBuilder.h Tue Nov 15 01:24:32 2011
@@ -27,7 +27,6 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 
 namespace llvm {
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=144631&r1=144630&r2=144631&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Nov 15 01:24:32 2011
@@ -25,7 +25,6 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"



From jay.foad at gmail.com  Tue Nov 15 01:34:52 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 15 Nov 2011 07:34:52 -0000
Subject: [llvm-commits] [llvm] r144632 - in /llvm/trunk/lib/Target:
 ARM/ARMBaseInstrInfo.cpp ARM/Thumb1InstrInfo.cpp ARM/Thumb2InstrInfo.cpp
 MSP430/MSP430InstrInfo.cpp PowerPC/PPCInstrInfo.cpp
Message-ID: <20111115073452.D63762A6C131@llvm.org>

Author: foad
Date: Tue Nov 15 01:34:52 2011
New Revision: 144632

URL: http://llvm.org/viewvc/llvm-project?rev=144632&view=rev
Log:
Make use of MachinePointerInfo::getFixedStack. This removes all mention
of PseudoSourceValue from lib/Target/.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
    llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=144632&r1=144631&r2=144632&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Nov 15 01:34:52 2011
@@ -28,7 +28,6 @@
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/Support/BranchProbability.h"
@@ -710,8 +709,7 @@
   unsigned Align = MFI.getObjectAlignment(FI);
 
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(MachinePointerInfo(
-                                         PseudoSourceValue::getFixedStack(FI)),
+    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
                             MachineMemOperand::MOStore,
                             MFI.getObjectSize(FI),
                             Align);
@@ -862,7 +860,7 @@
   unsigned Align = MFI.getObjectAlignment(FI);
   MachineMemOperand *MMO =
     MF.getMachineMemOperand(
-                    MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+                    MachinePointerInfo::getFixedStack(FI),
                             MachineMemOperand::MOLoad,
                             MFI.getObjectSize(FI),
                             Align);

Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=144632&r1=144631&r2=144632&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Tue Nov 15 01:34:52 2011
@@ -18,7 +18,6 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/ADT/SmallVector.h"
 #include "Thumb1InstrInfo.h"
 
@@ -60,8 +59,7 @@
     MachineFunction &MF = *MBB.getParent();
     MachineFrameInfo &MFI = *MF.getFrameInfo();
     MachineMemOperand *MMO =
-      MF.getMachineMemOperand(
-                    MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+      MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
                               MachineMemOperand::MOStore,
                               MFI.getObjectSize(FI),
                               MFI.getObjectAlignment(FI));
@@ -89,8 +87,7 @@
     MachineFunction &MF = *MBB.getParent();
     MachineFrameInfo &MFI = *MF.getFrameInfo();
     MachineMemOperand *MMO =
-      MF.getMachineMemOperand(
-                    MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+      MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
                               MachineMemOperand::MOLoad,
                               MFI.getObjectSize(FI),
                               MFI.getObjectAlignment(FI));

Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=144632&r1=144631&r2=144632&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Tue Nov 15 01:34:52 2011
@@ -20,7 +20,6 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/CommandLine.h"
 
@@ -130,8 +129,7 @@
     MachineFunction &MF = *MBB.getParent();
     MachineFrameInfo &MFI = *MF.getFrameInfo();
     MachineMemOperand *MMO =
-      MF.getMachineMemOperand(
-                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+      MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
                               MachineMemOperand::MOStore,
                               MFI.getObjectSize(FI),
                               MFI.getObjectAlignment(FI));
@@ -158,8 +156,7 @@
     MachineFunction &MF = *MBB.getParent();
     MachineFrameInfo &MFI = *MF.getFrameInfo();
     MachineMemOperand *MMO =
-      MF.getMachineMemOperand(
-                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+      MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
                               MachineMemOperand::MOLoad,
                               MFI.getObjectSize(FI),
                               MFI.getObjectAlignment(FI));

Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=144632&r1=144631&r2=144632&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Tue Nov 15 01:34:52 2011
@@ -19,7 +19,6 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
@@ -43,8 +42,7 @@
   MachineFrameInfo &MFI = *MF.getFrameInfo();
 
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(
-              MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
+    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
                             MachineMemOperand::MOStore,
                             MFI.getObjectSize(FrameIdx),
                             MFI.getObjectAlignment(FrameIdx));
@@ -72,8 +70,7 @@
   MachineFrameInfo &MFI = *MF.getFrameInfo();
 
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(
-              MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
+    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
                             MachineMemOperand::MOLoad,
                             MFI.getObjectSize(FrameIdx),
                             MFI.getObjectAlignment(FrameIdx));

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=144632&r1=144631&r2=144632&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Nov 15 01:34:52 2011
@@ -22,7 +22,6 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -501,8 +500,7 @@
 
   const MachineFrameInfo &MFI = *MF.getFrameInfo();
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(
-                MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
+    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
                             MachineMemOperand::MOStore,
                             MFI.getObjectSize(FrameIdx),
                             MFI.getObjectAlignment(FrameIdx));
@@ -623,8 +621,7 @@
 
   const MachineFrameInfo &MFI = *MF.getFrameInfo();
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(
-                MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
+    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
                             MachineMemOperand::MOLoad,
                             MFI.getObjectSize(FrameIdx),
                             MFI.getObjectAlignment(FrameIdx));



From jay.foad at gmail.com  Tue Nov 15 01:50:05 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 15 Nov 2011 07:50:05 -0000
Subject: [llvm-commits] [llvm] r144633 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20111115075005.948FE2A6C131@llvm.org>

Author: foad
Date: Tue Nov 15 01:50:05 2011
New Revision: 144633

URL: http://llvm.org/viewvc/llvm-project?rev=144633&view=rev
Log:
Fix typo in comment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=144633&r1=144632&r2=144633&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 15 01:50:05 2011
@@ -1555,7 +1555,7 @@
 }
 
 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
-// (These psuedos use a hand-written selection code).
+// (These pseudos use a hand-written selection code).
 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
 def ATOMOR6432   : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
                               (ins GPR:$addr, GPR:$src1, GPR:$src2),



From jay.foad at gmail.com  Tue Nov 15 01:50:46 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 15 Nov 2011 07:50:46 -0000
Subject: [llvm-commits] [llvm] r144634 - in
 /llvm/trunk/lib/CodeGen/SelectionDAG: DAGCombiner.cpp
 LegalizeIntegerTypes.cpp LegalizeTypesGeneric.cpp LegalizeVectorTypes.cpp
 SelectionDAG.cpp SelectionDAGBuilder.cpp SelectionDAGPrinter.cpp
Message-ID: <20111115075046.865C32A6C131@llvm.org>

Author: foad
Date: Tue Nov 15 01:50:46 2011
New Revision: 144634

URL: http://llvm.org/viewvc/llvm-project?rev=144634&view=rev
Log:
Remove some unnecessary includes of PseudoSourceValue.h.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=144634&r1=144633&r2=144634&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Nov 15 01:50:46 2011
@@ -22,7 +22,6 @@
 #include "llvm/LLVMContext.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetLowering.h"

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=144634&r1=144633&r2=144634&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Nov 15 01:50:46 2011
@@ -20,7 +20,6 @@
 
 #include "LegalizeTypes.h"
 #include "llvm/DerivedTypes.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=144634&r1=144633&r2=144634&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Tue Nov 15 01:50:46 2011
@@ -21,7 +21,6 @@
 
 #include "LegalizeTypes.h"
 #include "llvm/Target/TargetData.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 using namespace llvm;
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=144634&r1=144633&r2=144634&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Nov 15 01:50:46 2011
@@ -21,7 +21,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "LegalizeTypes.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=144634&r1=144633&r2=144634&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Nov 15 01:50:46 2011
@@ -28,7 +28,6 @@
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetLowering.h"

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=144634&r1=144633&r2=144634&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Nov 15 01:50:46 2011
@@ -41,7 +41,6 @@
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/Analysis/DebugInfo.h"
 #include "llvm/Target/TargetData.h"

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=144634&r1=144633&r2=144634&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Tue Nov 15 01:50:46 2011
@@ -19,7 +19,6 @@
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Analysis/DebugInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetMachine.h"



From jay.foad at gmail.com  Tue Nov 15 01:51:13 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 15 Nov 2011 07:51:13 -0000
Subject: [llvm-commits] [llvm] r144635 -
	/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
Message-ID: <20111115075113.E24582A6C131@llvm.org>

Author: foad
Date: Tue Nov 15 01:51:13 2011
New Revision: 144635

URL: http://llvm.org/viewvc/llvm-project?rev=144635&view=rev
Log:
Make use of MachinePointerInfo::getFixedStack.

Modified:
    llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp

Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=144635&r1=144634&r2=144635&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Tue Nov 15 01:51:13 2011
@@ -296,8 +296,7 @@
     const MachineFrameInfo &MFI = *MF.getFrameInfo();
     assert(MFI.getObjectOffset(FI) != -1);
     MachineMemOperand *MMO =
-      MF.getMachineMemOperand(
-                    MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
+      MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
                               Flags, MFI.getObjectSize(FI),
                               MFI.getObjectAlignment(FI));
     NewMI->addMemOperand(MF, MMO);



From stoklund at 2pi.dk  Tue Nov 15 02:20:43 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 15 Nov 2011 08:20:43 -0000
Subject: [llvm-commits] [llvm] r144636 -
	/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
Message-ID: <20111115082043.AB2412A6C131@llvm.org>

Author: stoklund
Date: Tue Nov 15 02:20:43 2011
New Revision: 144636

URL: http://llvm.org/viewvc/llvm-project?rev=144636&view=rev
Log:
Check all overlaps when looking for used registers.

A function using any RC alias is enough to enable the ExeDepsFix pass.

Modified:
    llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp

Modified: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp?rev=144636&r1=144635&r2=144636&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp (original)
+++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp Tue Nov 15 02:20:43 2011
@@ -650,10 +650,11 @@
   bool anyregs = false;
   for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
        I != E; ++I)
-    if (MF->getRegInfo().isPhysRegUsed(*I)) {
-      anyregs = true;
-      break;
-    }
+    for (const unsigned *AI = TRI->getOverlaps(*I); *AI; ++AI)
+      if (MF->getRegInfo().isPhysRegUsed(*AI)) {
+        anyregs = true;
+        break;
+      }
   if (!anyregs) return false;
 
   // Initialize the AliasMap on the first use.



From jay.foad at gmail.com  Tue Nov 15 02:29:45 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 15 Nov 2011 08:29:45 +0000
Subject: [llvm-commits] [PATCH] PR889: devirtualize Value::printCustom
In-Reply-To: <28388F1A-D44C-4218-A157-A177E2D114FB@apple.com>
References: <CANd1uZkGs+3ba7BCFJgnBA0MDEt16SNN1um2Qjgq0RRRMkgWjg@mail.gmail.com>
	<CAGCO0Kgagyg7=aD8kStnPSfiuxUnRskKM1BfOkNiQ=kB8x8uiw@mail.gmail.com>
	<CANd1uZmO4JhwQGZaXFcX2e2Z+F9vfrbSqP9L0i3op_zVkdS2tg@mail.gmail.com>
	<28388F1A-D44C-4218-A157-A177E2D114FB@apple.com>
Message-ID: <CANd1uZm+riB-S+xg=n58nwSAovJoEt0q0e+2+Ty5gJ3U3Grjaw@mail.gmail.com>

On 14 November 2011 18:38, Chris Lattner <clattner at apple.com> wrote:
> The "right" way to fix this is to eliminate PseudoSourceValue, which has always been a disgusting hack. ?Places in codegen that can uses PseudoSourceValue (e.g. the SDLoadNode and memoperands)

LoadSDNode has-a MachineMemOperand, which has-a MachinePointerInfo,
which is the (only?) thing that can refer to PseudoSourceValues.

> should use a discriminated union of "Value* and SomeMachineLocationType".

I assume you're not talking about (MC's) MachineLocation here, but
about some new machine location type yet to be invented.

Jay.


From grosser at fim.uni-passau.de  Tue Nov 15 05:38:37 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Tue, 15 Nov 2011 11:38:37 -0000
Subject: [llvm-commits] [polly] r144638 - in /polly/trunk:
 include/polly/LinkAllPasses.h lib/Exchange/JSONExporter.cpp
 lib/RegisterPasses.cpp www/example_load_Polly_into_clang.html
Message-ID: <20111115113837.1A12E2A6C131@llvm.org>

Author: grosser
Date: Tue Nov 15 05:38:36 2011
New Revision: 144638

URL: http://llvm.org/viewvc/llvm-project?rev=144638&view=rev
Log:
Make JScop export/reimport accessible from clang

Modified:
    polly/trunk/include/polly/LinkAllPasses.h
    polly/trunk/lib/Exchange/JSONExporter.cpp
    polly/trunk/lib/RegisterPasses.cpp
    polly/trunk/www/example_load_Polly_into_clang.html

Modified: polly/trunk/include/polly/LinkAllPasses.h
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/LinkAllPasses.h?rev=144638&r1=144637&r2=144638&view=diff
==============================================================================
--- polly/trunk/include/polly/LinkAllPasses.h (original)
+++ polly/trunk/include/polly/LinkAllPasses.h Tue Nov 15 05:38:36 2011
@@ -112,6 +112,8 @@
   void initializeCodeGenerationPass(llvm::PassRegistry&);
   void initializeCodePreparationPass(llvm::PassRegistry&);
   void initializeIndependentBlocksPass(llvm::PassRegistry&);
+  void initializeJSONExporterPass(llvm::PassRegistry&);
+  void initializeJSONImporterPass(llvm::PassRegistry&);
   void initializeIslScheduleOptimizerPass(llvm::PassRegistry&);
 #ifdef SCOPLIB_FOUND
   void initializePoccPass(llvm::PassRegistry&);

Modified: polly/trunk/lib/Exchange/JSONExporter.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/JSONExporter.cpp?rev=144638&r1=144637&r2=144638&view=diff
==============================================================================
--- polly/trunk/lib/Exchange/JSONExporter.cpp (original)
+++ polly/trunk/lib/Exchange/JSONExporter.cpp Tue Nov 15 05:38:36 2011
@@ -167,10 +167,13 @@
   AU.addRequired<ScopInfo>();
 }
 
-static RegisterPass<JSONExporter> A("polly-export-jscop",
-                                    "Polly - Export Scops as JSON"
-                                    " (Writes a .jscop file for each Scop)"
-                                    );
+INITIALIZE_PASS_BEGIN(JSONExporter, "polly-export-jscop",
+                      "Polly - Export Scops as JSON"
+                      " (Writes a .jscop file for each Scop)", false, false)
+INITIALIZE_PASS_DEPENDENCY(Dependences)
+INITIALIZE_PASS_END(JSONExporter, "polly-export-jscop",
+                    "Polly - Export Scops as JSON"
+                    " (Writes a .jscop file for each Scop)", false, false)
 
 Pass *polly::createJSONExporterPass() {
   return new JSONExporter();
@@ -304,10 +307,13 @@
   AU.addRequired<Dependences>();
 }
 
-static RegisterPass<JSONImporter> B("polly-import-jscop",
-                                    "Polly - Import Scops from JSON"
-                                    " (Reads a .jscop file for each Scop)"
-                                    );
+INITIALIZE_PASS_BEGIN(JSONImporter, "polly-import-jscop",
+                      "Polly - Import Scops from JSON"
+                      " (Reads a .jscop file for each Scop)", false, false)
+INITIALIZE_PASS_DEPENDENCY(Dependences)
+INITIALIZE_PASS_END(JSONImporter, "polly-import-jscop",
+                    "Polly - Import Scops from JSON"
+                    " (Reads a .jscop file for each Scop)", false, false)
 
 Pass *polly::createJSONImporterPass() {
   return new JSONImporter();

Modified: polly/trunk/lib/RegisterPasses.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/RegisterPasses.cpp?rev=144638&r1=144637&r2=144638&view=diff
==============================================================================
--- polly/trunk/lib/RegisterPasses.cpp (original)
+++ polly/trunk/lib/RegisterPasses.cpp Tue Nov 15 05:38:36 2011
@@ -41,6 +41,14 @@
        cl::desc("Use the PoCC optimizer instead of the one in isl"), cl::Hidden,
        cl::init(false));
 static cl::opt<bool>
+ImportJScop("polly-run-import-jscop",
+            cl::desc("Export the JScop description of the detected Scops"),
+            cl::Hidden, cl::init(false));
+static cl::opt<bool>
+ExportJScop("polly-run-export-jscop",
+            cl::desc("Export the JScop description of the detected Scops"),
+            cl::Hidden, cl::init(false));
+static cl::opt<bool>
 PollyViewer("polly-show",
        cl::desc("Enable the Polly DOT viewer in -O3"), cl::Hidden,
        cl::value_desc("Run the Polly DOT viewer at -O3"),
@@ -69,6 +77,8 @@
   initializeCodePreparationPass(Registry);
   initializeDependencesPass(Registry);
   initializeIndependentBlocksPass(Registry);
+  initializeJSONExporterPass(Registry);
+  initializeJSONImporterPass(Registry);
   initializeIslScheduleOptimizerPass(Registry);
 #ifdef SCOPLIB_FOUND
   initializePoccPass(Registry);
@@ -137,6 +147,9 @@
   if (PollyOnlyPrinter)
     PM.add(polly::createDOTOnlyPrinterPass());
 
+  if (ImportJScop)
+    PM.add(polly::createJSONImporterPass());
+
   if (!DisableScheduler) {
     if (!UsePocc)
       PM.add(polly::createIslScheduleOptimizerPass());
@@ -150,9 +163,12 @@
       PM.add(polly::createIslScheduleOptimizerPass());
 #endif
     }
-
   }
 
+  if (ExportJScop)
+    PM.add(polly::createJSONExporterPass());
+
+
   if (!DisableCodegen)
     PM.add(polly::createCodeGenerationPass());
 }

Modified: polly/trunk/www/example_load_Polly_into_clang.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/example_load_Polly_into_clang.html?rev=144638&r1=144637&r2=144638&view=diff
==============================================================================
--- polly/trunk/www/example_load_Polly_into_clang.html (original)
+++ polly/trunk/www/example_load_Polly_into_clang.html Tue Nov 15 05:38:36 2011
@@ -99,6 +99,11 @@
 no aliasing is possible. In case the user knows no aliasing can happen in the
 code the <b>-polly-ignore-aliasing</b> can be used to disable the check for
 possible aliasing.
+
+<h3>Importing and exporting JScop files</h3>
+The flags <b>-polly-run-import-jscop</b> and <b>-polly-run-export-jscop</b>
+allow the export and reimport of the polyhedral representation that Polly
+generates for the Scops.
 </div>
 </body>
 </html>



From grosser at fim.uni-passau.de  Tue Nov 15 05:38:44 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Tue, 15 Nov 2011 11:38:44 -0000
Subject: [llvm-commits] [polly] r144639 - in /polly/trunk:
 include/polly/ScopInfo.h lib/Analysis/ScopInfo.cpp
 lib/Exchange/JSONExporter.cpp
Message-ID: <20111115113844.4F3BC2A6C131@llvm.org>

Author: grosser
Date: Tue Nov 15 05:38:44 2011
New Revision: 144639

URL: http://llvm.org/viewvc/llvm-project?rev=144639&view=rev
Log:
JScop: Allow to update the context

Modified:
    polly/trunk/include/polly/ScopInfo.h
    polly/trunk/lib/Analysis/ScopInfo.cpp
    polly/trunk/lib/Exchange/JSONExporter.cpp

Modified: polly/trunk/include/polly/ScopInfo.h
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/ScopInfo.h?rev=144639&r1=144638&r2=144639&view=diff
==============================================================================
--- polly/trunk/include/polly/ScopInfo.h (original)
+++ polly/trunk/include/polly/ScopInfo.h Tue Nov 15 05:38:44 2011
@@ -547,6 +547,8 @@
   const_reverse_iterator rend()   const { return Stmts.rend();   }
   //@}
 
+  void setContext(isl_set* NewContext);
+
   /// @brief Align the parameters in the statement to the scop context
   void realignParams();
 

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144639&r1=144638&r2=144639&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Tue Nov 15 05:38:44 2011
@@ -843,6 +843,12 @@
 //===----------------------------------------------------------------------===//
 /// Scop class implement
 
+void Scop::setContext(__isl_take isl_set* NewContext) {
+  NewContext = isl_set_align_params(NewContext, isl_set_get_space(Context));
+  isl_set_free(Context);
+  Context = NewContext;
+}
+
 void Scop::addParams(std::vector<const SCEV*> NewParameters) {
   for (std::vector<const SCEV*>::iterator PI = NewParameters.begin(),
        PE = NewParameters.end(); PI != PE; ++PI) {

Modified: polly/trunk/lib/Exchange/JSONExporter.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/JSONExporter.cpp?rev=144639&r1=144638&r2=144639&view=diff
==============================================================================
--- polly/trunk/lib/Exchange/JSONExporter.cpp (original)
+++ polly/trunk/lib/Exchange/JSONExporter.cpp Tue Nov 15 05:38:44 2011
@@ -228,6 +228,19 @@
     return false;
   }
 
+  isl_set *OldContext = S->getContext();
+  isl_set *NewContext = isl_set_read_from_str(S->getIslCtx(),
+                                              jscop["context"].asCString());
+
+  for (unsigned i = 0; i < isl_set_dim(OldContext, isl_dim_param); i++) {
+    isl_id *id = isl_set_get_dim_id(OldContext, isl_dim_param, i);
+    NewContext = isl_set_set_dim_id(NewContext, isl_dim_param, i, id);
+
+  }
+
+  isl_set_free(OldContext);
+  S->setContext(NewContext);
+
   StatementToIslMapTy &NewScattering = *(new StatementToIslMapTy());
 
   int index = 0;



From grosser at fim.uni-passau.de  Tue Nov 15 05:38:47 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Tue, 15 Nov 2011 11:38:47 -0000
Subject: [llvm-commits] [polly] r144640 - /polly/trunk/lib/Cloog.cpp
Message-ID: <20111115113847.CC2112A6C131@llvm.org>

Author: grosser
Date: Tue Nov 15 05:38:47 2011
New Revision: 144640

URL: http://llvm.org/viewvc/llvm-project?rev=144640&view=rev
Log:
Cloog: Copy parameter names from isl data structures

Modified:
    polly/trunk/lib/Cloog.cpp

Modified: polly/trunk/lib/Cloog.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Cloog.cpp?rev=144640&r1=144639&r2=144640&view=diff
==============================================================================
--- polly/trunk/lib/Cloog.cpp (original)
+++ polly/trunk/lib/Cloog.cpp Tue Nov 15 05:38:47 2011
@@ -179,6 +179,18 @@
 CloogInput *Cloog::buildCloogInput() {
   CloogDomain *Context = cloog_domain_from_isl_set(S->getContext());
   CloogUnionDomain *Statements = buildCloogUnionDomain();
+
+  isl_set *ScopContext = S->getContext();
+
+  for (unsigned i = 0; i < isl_set_dim(ScopContext, isl_dim_param); i++) {
+    isl_id *id = isl_set_get_dim_id(ScopContext, isl_dim_param, i);
+    Statements = cloog_union_domain_set_name(Statements, CLOOG_PARAM, i,
+                                             isl_id_get_name(id));
+    isl_id_free(id);
+  }
+
+  isl_set_free(ScopContext);
+
   CloogInput *Input = cloog_input_alloc(Context, Statements);
   return Input;
 }



From grosser at fim.uni-passau.de  Tue Nov 15 05:38:55 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Tue, 15 Nov 2011 11:38:55 -0000
Subject: [llvm-commits] [polly] r144641 - in /polly/trunk:
 lib/Analysis/ScopInfo.cpp test/CodeGen/loop_with_condition_2.ll
 test/CodeGen/single_loop_param.ll
 test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll
 test/ScopInfo/20111108-Parameter-not-detected.ll
 test/ScopInfo/loop_carry.ll
Message-ID: <20111115113855.4EBE72A6C131@llvm.org>

Author: grosser
Date: Tue Nov 15 05:38:55 2011
New Revision: 144641

URL: http://llvm.org/viewvc/llvm-project?rev=144641&view=rev
Log:
ScopInfo: Use names of simple parameters to name the isl parameter dimensions.

Parameters can be complex SCEV expressions, but they can also be single scalar
values. If a parameters is such a simple scalar value and the value is named,
use this name to name the isl parameter dimensions.

Modified:
    polly/trunk/lib/Analysis/ScopInfo.cpp
    polly/trunk/test/CodeGen/loop_with_condition_2.ll
    polly/trunk/test/CodeGen/single_loop_param.ll
    polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll
    polly/trunk/test/ScopInfo/20111108-Parameter-not-detected.ll
    polly/trunk/test/ScopInfo/loop_carry.ll

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144641&r1=144640&r2=144641&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Tue Nov 15 05:38:55 2011
@@ -870,7 +870,16 @@
   if (IdIter == ParameterIds.end())
     return NULL;
 
-  std::string ParameterName = "p" + convertInt(IdIter->second);
+  std::string ParameterName;
+
+  if (const SCEVUnknown *ValueParameter = dyn_cast<SCEVUnknown>(Parameter)) {
+    Value *Val = ValueParameter->getValue();
+    ParameterName = Val->getNameStr();
+  }
+
+  if (ParameterName == "" || ParameterName.substr(0, 2) == "p_")
+    ParameterName = "p_" + convertInt(IdIter->second);
+
   return isl_id_alloc(getIslCtx(), ParameterName.c_str(), (void *) Parameter);
 }
 

Modified: polly/trunk/test/CodeGen/loop_with_condition_2.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/loop_with_condition_2.ll?rev=144641&r1=144640&r2=144641&view=diff
==============================================================================
--- polly/trunk/test/CodeGen/loop_with_condition_2.ll (original)
+++ polly/trunk/test/CodeGen/loop_with_condition_2.ll Tue Nov 15 05:38:55 2011
@@ -132,11 +132,11 @@
 
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
 
-; CHECK: for (c2=0;c2<=min(1023,M+1024);c2++) {
+; CHECK: for (c2=0;c2<=min(1023,m+1024);c2++) {
 ; CHECK:     Stmt_if_then(c2);
 ; CHECK:       Stmt_if_end(c2);
 ; CHECK: }
-; CHECK: for (c2=max(0,M+1025);c2<=1023;c2++) {
+; CHECK: for (c2=max(0,m+1025);c2<=1023;c2++) {
 ; CHECK:     Stmt_if_else(c2);
 ; CHECK:       Stmt_if_end(c2);
 ; CHECK: }

Modified: polly/trunk/test/CodeGen/single_loop_param.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/CodeGen/single_loop_param.ll?rev=144641&r1=144640&r2=144641&view=diff
==============================================================================
--- polly/trunk/test/CodeGen/single_loop_param.ll (original)
+++ polly/trunk/test/CodeGen/single_loop_param.ll Tue Nov 15 05:38:55 2011
@@ -70,8 +70,8 @@
 
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
 
-; CHECK: if (M >= 1) {
-; CHECK:     for (c2=0;c2<=M-1;c2++) {
+; CHECK: if (n >= 1) {
+; CHECK:     for (c2=0;c2<=n-1;c2++) {
 ; CHECK:           Stmt_bb2(c2);
 ; CHECK:             }
 ; CHECK: }

Modified: polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll?rev=144641&r1=144640&r2=144641&view=diff
==============================================================================
--- polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll (original)
+++ polly/trunk/test/ScheduleOptimizer/2011-08-25-crash_in_vectorizer.ll Tue Nov 15 05:38:55 2011
@@ -29,18 +29,18 @@
   ret void
 }
 
-; CHECK: if (M >= 1) {
-; CHECK:     for (c1=0;c1<=M-1;c1+=32) {
-; CHECK:           for (c2=c1;c2<=min(M-1,c1+31);c2++) {
+; CHECK: if (p_0 >= 1) {
+; CHECK:     for (c1=0;c1<=p_0-1;c1+=32) {
+; CHECK:           for (c2=c1;c2<=min(c1+31,p_0-1);c2++) {
 ; CHECK:                   Stmt_bb2(c2);
 ; CHECK:           }
 ; CHECK:     }
 ; CHECK: }
 
-; VECTOR: if (M >= 1) {
-; VECTOR:   for (c1=0;c1<=M-1;c1+=32) {
-; VECTOR:     for (c2=-4*floord(-c1,4);c2<=min(M-1,c1+31);c2+=4) {
-; VECTOR:       for (c3=c2;c3<=min(M-1,c2+3);c3++) {
+; VECTOR: if (p_0 >= 1) {
+; VECTOR:   for (c1=0;c1<=p_0-1;c1+=32) {
+; VECTOR:     for (c2=-4*floord(-c1,4);c2<=min(c1+31,p_0-1);c2+=4) {
+; VECTOR:       for (c3=c2;c3<=min(c2+3,p_0-1);c3++) {
 ; VECTOR:         Stmt_bb2(c3);
 ; VECTOR:       }
 ; VECTOR:     }

Modified: polly/trunk/test/ScopInfo/20111108-Parameter-not-detected.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/20111108-Parameter-not-detected.ll?rev=144641&r1=144640&r2=144641&view=diff
==============================================================================
--- polly/trunk/test/ScopInfo/20111108-Parameter-not-detected.ll (original)
+++ polly/trunk/test/ScopInfo/20111108-Parameter-not-detected.ll Tue Nov 15 05:38:55 2011
@@ -52,5 +52,5 @@
 }
 
 ; CHECK: Domain :=
-; CHECK: [p0] -> { Stmt_if_then[i0] : i0 >= 0 and i0 <= 1022 and i0 >= 1001 - p0 };
+; CHECK: [p_0] -> { Stmt_if_then[i0] : i0 >= 0 and i0 <= 1022 and i0 >= 1001 - p_0 };
 

Modified: polly/trunk/test/ScopInfo/loop_carry.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/loop_carry.ll?rev=144641&r1=144640&r2=144641&view=diff
==============================================================================
--- polly/trunk/test/ScopInfo/loop_carry.ll (original)
+++ polly/trunk/test/ScopInfo/loop_carry.ll Tue Nov 15 05:38:55 2011
@@ -47,46 +47,46 @@
 }
 
 ; CHECK: Context:
-; CHECK: [p0] -> { : }
+; CHECK: [n] -> { : }
 ; CHECK:     Statements {
 ; CHECK:     	Stmt_bb_nph
 ; CHECK:             Domain :=
-; CHECK:                 [p0] -> { Stmt_bb_nph[] : p0 >= 2 };
+; CHECK:                 [n] -> { Stmt_bb_nph[] : n >= 2 };
 ; CHECK:             Scattering :=
-; CHECK:                 [p0] -> { Stmt_bb_nph[] -> scattering[0, 0, 0] };
+; CHECK:                 [n] -> { Stmt_bb_nph[] -> scattering[0, 0, 0] };
 ; CHECK:             ReadAccess :=
-; CHECK:                 [p0] -> { Stmt_bb_nph[] -> MemRef_a[0] };
+; CHECK:                 [n] -> { Stmt_bb_nph[] -> MemRef_a[0] };
 ; CHECK:             WriteAccess :=
-; CHECK:                 [p0] -> { Stmt_bb_nph[] -> MemRef_k_05_reg2mem[0] };
+; CHECK:                 [n] -> { Stmt_bb_nph[] -> MemRef_k_05_reg2mem[0] };
 ; CHECK:             WriteAccess :=
-; CHECK:                 [p0] -> { Stmt_bb_nph[] -> MemRef__reg2mem[0] };
+; CHECK:                 [n] -> { Stmt_bb_nph[] -> MemRef__reg2mem[0] };
 ; CHECK:     	Stmt_bb
 ; CHECK:             Domain :=
-; CHECK:                 [p0] -> { Stmt_bb[i0] : i0 >= 0 and i0 <= -2 + p0 and p0 >= 2 };
+; CHECK:                 [n] -> { Stmt_bb[i0] : i0 >= 0 and i0 <= -2 + n and n >= 2 };
 ; CHECK:             Scattering :=
-; CHECK:                 [p0] -> { Stmt_bb[i0] -> scattering[1, i0, 0] };
+; CHECK:                 [n] -> { Stmt_bb[i0] -> scattering[1, i0, 0] };
 ; CHECK:             ReadAccess :=
-; CHECK:                 [p0] -> { Stmt_bb[i0] -> MemRef__reg2mem[0] };
+; CHECK:                 [n] -> { Stmt_bb[i0] -> MemRef__reg2mem[0] };
 ; CHECK:             ReadAccess :=
-; CHECK:                 [p0] -> { Stmt_bb[i0] -> MemRef_k_05_reg2mem[0] };
+; CHECK:                 [n] -> { Stmt_bb[i0] -> MemRef_k_05_reg2mem[0] };
 ; CHECK:             WriteAccess :=
-; CHECK:                 [p0] -> { Stmt_bb[i0] -> MemRef_a[1 + i0] };
+; CHECK:                 [n] -> { Stmt_bb[i0] -> MemRef_a[1 + i0] };
 ; CHECK:             ReadAccess :=
-; CHECK:                 [p0] -> { Stmt_bb[i0] -> MemRef_a[2 + 2i0] };
+; CHECK:                 [n] -> { Stmt_bb[i0] -> MemRef_a[2 + 2i0] };
 ; CHECK:             ReadAccess :=
-; CHECK:                 [p0] -> { Stmt_bb[i0] -> MemRef_a[4 + i0] };
+; CHECK:                 [n] -> { Stmt_bb[i0] -> MemRef_a[4 + i0] };
 ; CHECK:             WriteAccess :=
-; CHECK:                 [p0] -> { Stmt_bb[i0] -> MemRef_k_05_reg2mem[0] };
+; CHECK:                 [n] -> { Stmt_bb[i0] -> MemRef_k_05_reg2mem[0] };
 ; CHECK:             WriteAccess :=
-; CHECK:                 [p0] -> { Stmt_bb[i0] -> MemRef__reg2mem[0] };
+; CHECK:                 [n] -> { Stmt_bb[i0] -> MemRef__reg2mem[0] };
 ; CHECK:     	FinalRead
 ; CHECK:             Domain :=
-; CHECK:                 [p0] -> { FinalRead[0] };
+; CHECK:                 [n] -> { FinalRead[0] };
 ; CHECK:             Scattering :=
-; CHECK:                 [p0] -> { FinalRead[i0] -> scattering[200000000, o1, o2] };
+; CHECK:                 [n] -> { FinalRead[i0] -> scattering[200000000, o1, o2] };
 ; CHECK:             ReadAccess :=
-; CHECK:                 [p0] -> { FinalRead[i0] -> MemRef_a[o0] };
+; CHECK:                 [n] -> { FinalRead[i0] -> MemRef_a[o0] };
 ; CHECK:             ReadAccess :=
-; CHECK:                 [p0] -> { FinalRead[i0] -> MemRef_k_05_reg2mem[o0] };
+; CHECK:                 [n] -> { FinalRead[i0] -> MemRef_k_05_reg2mem[o0] };
 ; CHECK:             ReadAccess :=
 ; CHECK:                 -> { FinalRead[i0] -> MemRef__reg2mem[o0] };



From grosser at fim.uni-passau.de  Tue Nov 15 05:38:59 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Tue, 15 Nov 2011 11:38:59 -0000
Subject: [llvm-commits] [polly] r144642 -
	/polly/trunk/lib/Exchange/JSONExporter.cpp
Message-ID: <20111115113859.603292A6C131@llvm.org>

Author: grosser
Date: Tue Nov 15 05:38:59 2011
New Revision: 144642

URL: http://llvm.org/viewvc/llvm-project?rev=144642&view=rev
Log:
JSONImporter: Fix parameter ids when importing new access functions

The new isl_id support for parmeters created problems when importing new
access functions. Even though the parameters had the same names,
they were mapped to different ids and where therefore incompatible.
We copy the ids now from the old parameter dimensions. This fixes the
problem.

Modified:
    polly/trunk/lib/Exchange/JSONExporter.cpp

Modified: polly/trunk/lib/Exchange/JSONExporter.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/JSONExporter.cpp?rev=144642&r1=144641&r2=144642&view=diff
==============================================================================
--- polly/trunk/lib/Exchange/JSONExporter.cpp (original)
+++ polly/trunk/lib/Exchange/JSONExporter.cpp Tue Nov 15 05:38:59 2011
@@ -285,6 +285,25 @@
       isl_map *newAccessMap = isl_map_read_from_str(S->getIslCtx(),
                                                     accesses.asCString());
       isl_map *currentAccessMap = (*MI)->getAccessRelation();
+
+      if (isl_map_dim(newAccessMap, isl_dim_param) !=
+          isl_map_dim(currentAccessMap, isl_dim_param)) {
+        errs() << "JScop file changes the number of parameter dimensions\n";
+        isl_map_free(currentAccessMap);
+        isl_map_free(newAccessMap);
+        return false;
+
+      }
+
+      // We need to copy the isl_ids for the parameter dimensions to the new
+      // map. Without doing this the current map would have different
+      // ids then the new one, even though both are named identically.
+      for (unsigned i = 0; i < isl_map_dim(currentAccessMap, isl_dim_param);
+           i++) {
+        isl_id *id = isl_map_get_dim_id(currentAccessMap, isl_dim_param, i);
+        newAccessMap = isl_map_set_dim_id(newAccessMap, isl_dim_param, i, id);
+      }
+
       if (!isl_map_has_equal_space(currentAccessMap, newAccessMap)) {
         errs() << "JScop file contains access function with incompatible "
                << "dimensions\n";



From grosser at fim.uni-passau.de  Tue Nov 15 05:39:03 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Tue, 15 Nov 2011 11:39:03 -0000
Subject: [llvm-commits] [polly] r144643 -
	/polly/trunk/lib/Exchange/ScopLib.cpp
Message-ID: <20111115113903.2D4002A6C131@llvm.org>

Author: grosser
Date: Tue Nov 15 05:39:02 2011
New Revision: 144643

URL: http://llvm.org/viewvc/llvm-project?rev=144643&view=rev
Log:
ScopLib: Fix export/import after parameters are now tagged with isl_ids.

Modified:
    polly/trunk/lib/Exchange/ScopLib.cpp

Modified: polly/trunk/lib/Exchange/ScopLib.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/ScopLib.cpp?rev=144643&r1=144642&r2=144643&view=diff
==============================================================================
--- polly/trunk/lib/Exchange/ScopLib.cpp (original)
+++ polly/trunk/lib/Exchange/ScopLib.cpp Tue Nov 15 05:39:02 2011
@@ -641,6 +641,20 @@
 
   isl_ctx *ctx = PollyStmt->getParent()->getIslCtx();
   isl_space *Space = isl_dim_alloc(ctx, NbParam, NbIterators, NbScattering);
+
+  isl_space *ParamSpace = PollyStmt->getParent()->getParamSpace();
+
+  // We need to copy the isl_ids for the parameter dimensions to the new
+  // map. Without doing this the current map would have different
+  // ids then the new one, even though both are named identically.
+  for (unsigned i = 0; i < isl_space_dim(Space, isl_dim_param);
+       i++) {
+    isl_id *id = isl_space_get_dim_id(ParamSpace, isl_dim_param, i);
+    Space = isl_space_set_dim_id(Space, isl_dim_param, i, id);
+  }
+
+  isl_space_free(ParamSpace);
+
   Space = isl_space_set_tuple_name(Space, isl_dim_out, "scattering");
   Space = isl_space_set_tuple_name(Space, isl_dim_in, PollyStmt->getBaseName());
 
@@ -663,6 +677,14 @@
 
 typedef Dependences::StatementToIslMapTy StatementToIslMapTy;
 
+void freeStmtToIslMap(StatementToIslMapTy *Map) {
+  for (StatementToIslMapTy::iterator MI = Map->begin(), ME = Map->end();
+       MI != ME; ++MI)
+    isl_map_free(MI->second);
+
+  delete (Map);
+}
+
 /// @brief Read the new scattering from the scoplib description.
 ///
 /// @S      The Scop to update
@@ -690,7 +712,7 @@
 
     if (!stmt) {
       errs() << "Not enough statements available in OpenScop file\n";
-      delete &NewScattering;
+      freeStmtToIslMap(&NewScattering);
       return NULL;
     }
 
@@ -701,7 +723,7 @@
 
   if (stmt) {
     errs() << "Too many statements in OpenScop file\n";
-    delete &NewScattering;
+    freeStmtToIslMap(&NewScattering);
     return NULL;
   }
 
@@ -720,6 +742,7 @@
     return false;
 
   if (!D->isValidScattering(NewScattering)) {
+    freeStmtToIslMap(NewScattering);
     errs() << "OpenScop file contains a scattering that changes the "
       << "dependences. Use -disable-polly-legality to continue anyways\n";
     return false;
@@ -730,9 +753,10 @@
     ScopStmt *Stmt = *SI;
 
     if (NewScattering->find(Stmt) != NewScattering->end())
-      Stmt->setScattering((*NewScattering)[Stmt]);
+      Stmt->setScattering(isl_map_copy((*NewScattering)[Stmt]));
   }
 
+  freeStmtToIslMap(NewScattering);
   return true;
 }
 }



From rafael.espindola at gmail.com  Tue Nov 15 09:05:43 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Tue, 15 Nov 2011 10:05:43 -0500
Subject: [llvm-commits] [llvm] r144267 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 test/CodeGen/X86/2006-05-11-InstrSched.ll
 test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
 test/CodeGen/X86/change-compare-stride-1.ll
 test/CodeGen/X86/fold-pcmpeqd-0.ll
 test/CodeGen/X86/iv-users-in-other-loops.ll
 test/CodeGen/X86/lsr-loop-exit-cond.ll test/CodeGen/X86/lsr-reuse-trunc.ll
 test/CodeGen/X86/masked-iv-safe.ll
 test/CodeGen/X86/multiple-loop-post-inc.ll test/CodeGen/X86/sse2.ll
 test/CodeGen/X86/sse3.ll
In-Reply-To: <4EBC9D90.50805@free.fr>
References: <20111110074316.A97871BE001@llvm.org> <4EBBB1ED.8000105@free.fr>
	<9FD603CE-74CE-4B7A-AC1D-87466E187F82@apple.com>
	<4EBC9D90.50805@free.fr>
Message-ID: <4EC27FC7.4020205@gmail.com>

On 11/10/2011 10:59 PM, Duncan Sands wrote:
> Hi Evan,
> 
>> That's really bizarre. It's obviously exposing a unrelated bug. Thanks for looking into this.
> 
> I think this is a case of PR11200: the code generators make decisions based on
> floating point computations.  On i386, GCC uses the floating point stack, while
> LLVM uses xmm registers, when building LLVM.  This results in codegen sometimes
> making different decisions due to different rounding.

Can't we just use -msse when building stage1 or do a bootstrap4?

> I've disabled the part of the dragonegg bootstrap that compares object files
> produced by GCC compiled LLVM with those produced by LLVM compiled LLVM as a
> workaround.
> 
> Ciao, Duncan.

Cheers,
Rafael

From benny.kra at googlemail.com  Tue Nov 15 10:26:39 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 15 Nov 2011 16:26:39 -0000
Subject: [llvm-commits] [llvm] r144647 - in /llvm/trunk:
 include/llvm/CodeGen/EdgeBundles.h include/llvm/Support/GraphWriter.h
 lib/Analysis/CFGPrinter.cpp lib/CodeGen/EdgeBundles.cpp
 lib/CodeGen/MachineFunction.cpp lib/CodeGen/ScheduleDAGPrinter.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
Message-ID: <20111115162639.533842A6C131@llvm.org>

Author: d0k
Date: Tue Nov 15 10:26:38 2011
New Revision: 144647

URL: http://llvm.org/viewvc/llvm-project?rev=144647&view=rev
Log:
Twinify GraphWriter a little bit.

Modified:
    llvm/trunk/include/llvm/CodeGen/EdgeBundles.h
    llvm/trunk/include/llvm/Support/GraphWriter.h
    llvm/trunk/lib/Analysis/CFGPrinter.cpp
    llvm/trunk/lib/CodeGen/EdgeBundles.cpp
    llvm/trunk/lib/CodeGen/MachineFunction.cpp
    llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/EdgeBundles.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/EdgeBundles.h?rev=144647&r1=144646&r2=144647&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/EdgeBundles.h (original)
+++ llvm/trunk/include/llvm/CodeGen/EdgeBundles.h Tue Nov 15 10:26:38 2011
@@ -18,6 +18,7 @@
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/IntEqClasses.h"
+#include "llvm/ADT/Twine.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 
 namespace llvm {
@@ -61,7 +62,7 @@
 /// Specialize WriteGraph, the standard implementation won't work.
 raw_ostream &WriteGraph(raw_ostream &O, const EdgeBundles &G,
                         bool ShortNames = false,
-                        const std::string &Title = "");
+                        const Twine &Title = "");
 
 } // end namespace llvm
 

Modified: llvm/trunk/include/llvm/Support/GraphWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/GraphWriter.h?rev=144647&r1=144646&r2=144647&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/GraphWriter.h (original)
+++ llvm/trunk/include/llvm/Support/GraphWriter.h Tue Nov 15 10:26:38 2011
@@ -296,26 +296,26 @@
 template<typename GraphType>
 raw_ostream &WriteGraph(raw_ostream &O, const GraphType &G,
                         bool ShortNames = false,
-                        const std::string &Title = "") {
+                        const Twine &Title = "") {
   // Start the graph emission process...
   GraphWriter<GraphType> W(O, G, ShortNames);
 
   // Emit the graph.
-  W.writeGraph(Title);
+  W.writeGraph(Title.str());
 
   return O;
 }
 
 template<typename GraphType>
-sys::Path WriteGraph(const GraphType &G, const std::string &Name,
-                     bool ShortNames = false, const std::string &Title = "") {
+sys::Path WriteGraph(const GraphType &G, const Twine &Name,
+                     bool ShortNames = false, const Twine &Title = "") {
   std::string ErrMsg;
   sys::Path Filename = sys::Path::GetTemporaryDirectory(&ErrMsg);
   if (Filename.isEmpty()) {
     errs() << "Error: " << ErrMsg << "\n";
     return Filename;
   }
-  Filename.appendComponent(Name + ".dot");
+  Filename.appendComponent((Name + ".dot").str());
   if (Filename.makeUnique(true,&ErrMsg)) {
     errs() << "Error: " << ErrMsg << "\n";
     return sys::Path();
@@ -341,8 +341,8 @@
 /// then cleanup.  For use from the debugger.
 ///
 template<typename GraphType>
-void ViewGraph(const GraphType &G, const std::string &Name,
-               bool ShortNames = false, const std::string &Title = "",
+void ViewGraph(const GraphType &G, const Twine &Name,
+               bool ShortNames = false, const Twine &Title = "",
                GraphProgram::Name Program = GraphProgram::DOT) {
   sys::Path Filename = llvm::WriteGraph(G, Name, ShortNames, Title);
 

Modified: llvm/trunk/lib/Analysis/CFGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CFGPrinter.cpp?rev=144647&r1=144646&r2=144647&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/CFGPrinter.cpp (original)
+++ llvm/trunk/lib/Analysis/CFGPrinter.cpp Tue Nov 15 10:26:38 2011
@@ -143,7 +143,7 @@
 /// being a 'dot' and 'gv' program in your path.
 ///
 void Function::viewCFG() const {
-  ViewGraph(this, "cfg" + getNameStr());
+  ViewGraph(this, "cfg" + getName());
 }
 
 /// viewCFGOnly - This function is meant for use from the debugger.  It works
@@ -152,7 +152,7 @@
 /// his can make the graph smaller.
 ///
 void Function::viewCFGOnly() const {
-  ViewGraph(this, "cfg" + getNameStr(), true);
+  ViewGraph(this, "cfg" + getName(), true);
 }
 
 FunctionPass *llvm::createCFGPrinterPass () {

Modified: llvm/trunk/lib/CodeGen/EdgeBundles.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/EdgeBundles.cpp?rev=144647&r1=144646&r2=144647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/EdgeBundles.cpp (original)
+++ llvm/trunk/lib/CodeGen/EdgeBundles.cpp Tue Nov 15 10:26:38 2011
@@ -77,7 +77,7 @@
 /// Specialize WriteGraph, the standard implementation won't work.
 raw_ostream &llvm::WriteGraph(raw_ostream &O, const EdgeBundles &G,
                               bool ShortNames,
-                              const std::string &Title) {
+                              const Twine &Title) {
   const MachineFunction *MF = G.getMachineFunction();
 
   O << "digraph {\n";

Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=144647&r1=144646&r2=144647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Nov 15 10:26:38 2011
@@ -368,7 +368,7 @@
 void MachineFunction::viewCFG() const
 {
 #ifndef NDEBUG
-  ViewGraph(this, "mf" + getFunction()->getNameStr());
+  ViewGraph(this, "mf" + getFunction()->getName());
 #else
   errs() << "MachineFunction::viewCFG is only available in debug builds on "
          << "systems with Graphviz or gv!\n";
@@ -378,7 +378,7 @@
 void MachineFunction::viewCFGOnly() const
 {
 #ifndef NDEBUG
-  ViewGraph(this, "mf" + getFunction()->getNameStr(), true);
+  ViewGraph(this, "mf" + getFunction()->getName(), true);
 #else
   errs() << "MachineFunction::viewCFGOnly is only available in debug builds on "
          << "systems with Graphviz or gv!\n";

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp?rev=144647&r1=144646&r2=144647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGPrinter.cpp Tue Nov 15 10:26:38 2011
@@ -86,12 +86,12 @@
 // This code is only for debugging!
 #ifndef NDEBUG
   if (BB->getBasicBlock())
-    ViewGraph(this, "dag." + MF.getFunction()->getNameStr(), false,
-              "Scheduling-Units Graph for " + MF.getFunction()->getNameStr() + 
-              ":" + BB->getBasicBlock()->getNameStr());
+    ViewGraph(this, "dag." + MF.getFunction()->getName(), false,
+              "Scheduling-Units Graph for " + MF.getFunction()->getName() +
+              ":" + BB->getBasicBlock()->getName());
   else
-    ViewGraph(this, "dag." + MF.getFunction()->getNameStr(), false,
-              "Scheduling-Units Graph for " + MF.getFunction()->getNameStr());
+    ViewGraph(this, "dag." + MF.getFunction()->getName(), false,
+              "Scheduling-Units Graph for " + MF.getFunction()->getName());
 #else
   errs() << "ScheduleDAG::viewGraph is only available in debug builds on "
          << "systems with Graphviz or gv!\n";

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=144647&r1=144646&r2=144647&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Tue Nov 15 10:26:38 2011
@@ -147,7 +147,7 @@
 void SelectionDAG::viewGraph(const std::string &Title) {
 // This code is only for debugging!
 #ifndef NDEBUG
-  ViewGraph(this, "dag." + getMachineFunction().getFunction()->getNameStr(),
+  ViewGraph(this, "dag." + getMachineFunction().getFunction()->getName(),
             false, Title);
 #else
   errs() << "SelectionDAG::viewGraph is only available in debug builds on "



From benny.kra at googlemail.com  Tue Nov 15 10:27:03 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 15 Nov 2011 16:27:03 -0000
Subject: [llvm-commits] [llvm] r144648 - in /llvm/trunk:
 include/llvm/Analysis/ lib/Analysis/ lib/CodeGen/ lib/CodeGen/SelectionDAG/
 lib/ExecutionEngine/Interpreter/ lib/ExecutionEngine/JIT/
 lib/Transforms/IPO/ lib/Transforms/InstCombine/
 lib/Transforms/Instrumentation/ lib/VMCore/ tools/bugpoint/
 tools/llvm-prof/ tools/opt/
Message-ID: <20111115162704.C55002A6C131@llvm.org>

Author: d0k
Date: Tue Nov 15 10:27:03 2011
New Revision: 144648

URL: http://llvm.org/viewvc/llvm-project?rev=144648&view=rev
Log:
Remove all remaining uses of Value::getNameStr().

Modified:
    llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h
    llvm/trunk/include/llvm/Analysis/CFGPrinter.h
    llvm/trunk/include/llvm/Analysis/DOTGraphTraitsPass.h
    llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
    llvm/trunk/lib/Analysis/CFGPrinter.cpp
    llvm/trunk/lib/Analysis/PathProfileVerifier.cpp
    llvm/trunk/lib/Analysis/ProfileEstimatorPass.cpp
    llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp
    llvm/trunk/lib/Analysis/ProfileVerifierPass.cpp
    llvm/trunk/lib/Analysis/SparsePropagation.cpp
    llvm/trunk/lib/Analysis/Trace.cpp
    llvm/trunk/lib/CodeGen/GCMetadata.cpp
    llvm/trunk/lib/CodeGen/MachineFunction.cpp
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp
    llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp
    llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
    llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
    llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp
    llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
    llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
    llvm/trunk/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp
    llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp
    llvm/trunk/lib/VMCore/Value.cpp
    llvm/trunk/tools/bugpoint/ExtractFunction.cpp
    llvm/trunk/tools/llvm-prof/llvm-prof.cpp
    llvm/trunk/tools/opt/PrintSCC.cpp
    llvm/trunk/tools/opt/opt.cpp

Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h (original)
+++ llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h Tue Nov 15 10:27:03 2011
@@ -24,7 +24,6 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include <vector>
-#include <sstream>
 #include <string>
 
 namespace llvm {
@@ -52,15 +51,16 @@
   const uint32_t EntryFreq;
 
   std::string getBlockName(BasicBlock *BB) const {
-    return BB->getNameStr();
+    return BB->getName().str();
   }
 
   std::string getBlockName(MachineBasicBlock *MBB) const {
-    std::stringstream ss;
+    std::string str;
+    raw_string_ostream ss(str);
     ss << "BB#" << MBB->getNumber();
 
     if (const BasicBlock *BB = MBB->getBasicBlock())
-      ss << " derived from LLVM BB " << BB->getNameStr();
+      ss << " derived from LLVM BB " << BB->getName();
 
     return ss.str();
   }

Modified: llvm/trunk/include/llvm/Analysis/CFGPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CFGPrinter.h?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/CFGPrinter.h (original)
+++ llvm/trunk/include/llvm/Analysis/CFGPrinter.h Tue Nov 15 10:27:03 2011
@@ -29,13 +29,13 @@
   DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
 
   static std::string getGraphName(const Function *F) {
-    return "CFG for '" + F->getNameStr() + "' function";
+    return "CFG for '" + F->getName().str() + "' function";
   }
 
   static std::string getSimpleNodeLabel(const BasicBlock *Node,
                                         const Function *) {
     if (!Node->getName().empty())
-      return Node->getNameStr(); 
+      return Node->getName().str();
 
     std::string Str;
     raw_string_ostream OS(Str);

Modified: llvm/trunk/include/llvm/Analysis/DOTGraphTraitsPass.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DOTGraphTraitsPass.h?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DOTGraphTraitsPass.h (original)
+++ llvm/trunk/include/llvm/Analysis/DOTGraphTraitsPass.h Tue Nov 15 10:27:03 2011
@@ -31,7 +31,7 @@
     std::string Title, GraphName;
     Graph = &getAnalysis<Analysis>();
     GraphName = DOTGraphTraits<Analysis*>::getGraphName(Graph);
-    Title = GraphName + " for '" + F.getNameStr() + "' function";
+    Title = GraphName + " for '" + F.getName().str() + "' function";
     ViewGraph(Graph, Name, Simple, Title);
 
     return false;
@@ -55,7 +55,7 @@
 
   virtual bool runOnFunction(Function &F) {
     Analysis *Graph;
-    std::string Filename = Name + "." + F.getNameStr() + ".dot";
+    std::string Filename = Name + "." + F.getName().str() + ".dot";
     errs() << "Writing '" << Filename << "'...";
 
     std::string ErrorInfo;
@@ -64,7 +64,7 @@
 
     std::string Title, GraphName;
     GraphName = DOTGraphTraits<Analysis*>::getGraphName(Graph);
-    Title = GraphName + " for '" + F.getNameStr() + "' function";
+    Title = GraphName + " for '" + F.getName().str() + "' function";
 
     if (ErrorInfo.empty())
       WriteGraph(File, Graph, Simple, Title);

Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Tue Nov 15 10:27:03 2011
@@ -480,8 +480,8 @@
 void BranchProbabilityInfo::
 setEdgeWeight(const BasicBlock *Src, const BasicBlock *Dst, uint32_t Weight) {
   Weights[std::make_pair(Src, Dst)] = Weight;
-  DEBUG(dbgs() << "set edge " << Src->getNameStr() << " -> "
-               << Dst->getNameStr() << " weight to " << Weight
+  DEBUG(dbgs() << "set edge " << Src->getName() << " -> "
+               << Dst->getName() << " weight to " << Weight
                << (isEdgeHot(Src, Dst) ? " [is HOT now]\n" : "\n"));
 }
 
@@ -501,7 +501,7 @@
                                             const BasicBlock *Dst) const {
 
   const BranchProbability Prob = getEdgeProbability(Src, Dst);
-  OS << "edge " << Src->getNameStr() << " -> " << Dst->getNameStr()
+  OS << "edge " << Src->getName() << " -> " << Dst->getName()
      << " probability is " << Prob
      << (isEdgeHot(Src, Dst) ? " [HOT edge]\n" : "\n");
 

Modified: llvm/trunk/lib/Analysis/CFGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CFGPrinter.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/CFGPrinter.cpp (original)
+++ llvm/trunk/lib/Analysis/CFGPrinter.cpp Tue Nov 15 10:27:03 2011
@@ -77,7 +77,7 @@
     }
 
     virtual bool runOnFunction(Function &F) {
-      std::string Filename = "cfg." + F.getNameStr() + ".dot";
+      std::string Filename = "cfg." + F.getName().str() + ".dot";
       errs() << "Writing '" << Filename << "'...";
       
       std::string ErrorInfo;
@@ -111,7 +111,7 @@
     }
     
     virtual bool runOnFunction(Function &F) {
-      std::string Filename = "cfg." + F.getNameStr() + ".dot";
+      std::string Filename = "cfg." + F.getName().str() + ".dot";
       errs() << "Writing '" << Filename << "'...";
 
       std::string ErrorInfo;

Modified: llvm/trunk/lib/Analysis/PathProfileVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/PathProfileVerifier.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/PathProfileVerifier.cpp (original)
+++ llvm/trunk/lib/Analysis/PathProfileVerifier.cpp Tue Nov 15 10:27:03 2011
@@ -137,22 +137,22 @@
         BasicBlock* source = nextEdge->getSource();
         BasicBlock* target = nextEdge->getTarget();
         unsigned duplicateNumber = nextEdge->getDuplicateNumber();
-        DEBUG(dbgs () << source->getNameStr() << " --{" << duplicateNumber
-              << "}--> " << target->getNameStr());
+        DEBUG(dbgs() << source->getName() << " --{" << duplicateNumber
+                     << "}--> " << target->getName());
 
         // Ensure all the referenced edges exist
         // TODO: make this a separate function
         if( !arrayMap.count(source) ) {
-          errs() << "  error [" << F->getNameStr() << "()]: source '"
-                 << source->getNameStr()
+          errs() << "  error [" << F->getName() << "()]: source '"
+                 << source->getName()
                  << "' does not exist in the array map.\n";
         } else if( !arrayMap[source].count(target) ) {
-          errs() << "  error [" << F->getNameStr() << "()]: target '"
-                 << target->getNameStr()
+          errs() << "  error [" << F->getName() << "()]: target '"
+                 << target->getName()
                  << "' does not exist in the array map.\n";
         } else if( !arrayMap[source][target].count(duplicateNumber) ) {
-          errs() << "  error [" << F->getNameStr() << "()]: edge "
-                 << source->getNameStr() << " -> " << target->getNameStr()
+          errs() << "  error [" << F->getName() << "()]: edge "
+                 << source->getName() << " -> " << target->getName()
                  << " duplicate number " << duplicateNumber
                  << " does not exist in the array map.\n";
         } else {

Modified: llvm/trunk/lib/Analysis/ProfileEstimatorPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileEstimatorPass.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ProfileEstimatorPass.cpp (original)
+++ llvm/trunk/lib/Analysis/ProfileEstimatorPass.cpp Tue Nov 15 10:27:03 2011
@@ -332,7 +332,7 @@
   // Clear Minimal Edges.
   MinimalWeight.clear();
 
-  DEBUG(dbgs() << "Working on function " << F.getNameStr() << "\n");
+  DEBUG(dbgs() << "Working on function " << F.getName() << "\n");
 
   // Since the entry block is the first one and has no predecessors, the edge
   // (0,entry) is inserted with the starting weight of 1.

Modified: llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp (original)
+++ llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp Tue Nov 15 10:27:03 2011
@@ -160,7 +160,7 @@
     ReadCount = 0;
     for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
       if (F->isDeclaration()) continue;
-      DEBUG(dbgs()<<"Working on "<<F->getNameStr()<<"\n");
+      DEBUG(dbgs() << "Working on " << F->getName() << "\n");
       readEdge(getEdge(0,&F->getEntryBlock()), Counters);
       for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
         TerminatorInst *TI = BB->getTerminator();
@@ -181,7 +181,7 @@
     ReadCount = 0;
     for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
       if (F->isDeclaration()) continue;
-      DEBUG(dbgs()<<"Working on "<<F->getNameStr()<<"\n");
+      DEBUG(dbgs() << "Working on " << F->getName() << "\n");
       readEdge(getEdge(0,&F->getEntryBlock()), Counters);
       for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
         TerminatorInst *TI = BB->getTerminator();

Modified: llvm/trunk/lib/Analysis/ProfileVerifierPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileVerifierPass.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ProfileVerifierPass.cpp (original)
+++ llvm/trunk/lib/Analysis/ProfileVerifierPass.cpp Tue Nov 15 10:27:03 2011
@@ -125,8 +125,8 @@
         outCount++;
       }
     }
-    dbgs() << "Block " << BB->getNameStr()                << " in " 
-           << BB->getParent()->getNameStr()               << ":"
+    dbgs() << "Block " << BB->getName()                   << " in "
+           << BB->getParent()->getName()                  << ":"
            << "BBWeight="  << format("%20.20g",BBWeight)  << ","
            << "inWeight="  << format("%20.20g",inWeight)  << ","
            << "inCount="   << inCount                     << ","
@@ -143,8 +143,8 @@
 
   template<class FType, class BType>
   void ProfileVerifierPassT<FType, BType>::debugEntry (DetailedBlockInfo *DI) {
-    dbgs() << "TROUBLE: Block " << DI->BB->getNameStr()       << " in "
-           << DI->BB->getParent()->getNameStr()               << ":"
+    dbgs() << "TROUBLE: Block " << DI->BB->getName()          << " in "
+           << DI->BB->getParent()->getName()                  << ":"
            << "BBWeight="  << format("%20.20g",DI->BBWeight)  << ","
            << "inWeight="  << format("%20.20g",DI->inWeight)  << ","
            << "inCount="   << DI->inCount                     << ","
@@ -201,13 +201,13 @@
     double EdgeWeight = PI->getEdgeWeight(E);
     if (EdgeWeight == ProfileInfoT<FType, BType>::MissingValue) {
       dbgs() << "Edge " << E << " in Function " 
-             << ProfileInfoT<FType, BType>::getFunction(E)->getNameStr() << ": ";
+             << ProfileInfoT<FType, BType>::getFunction(E)->getName() << ": ";
       ASSERTMESSAGE("Edge has missing value");
       return 0;
     } else {
       if (EdgeWeight < 0) {
         dbgs() << "Edge " << E << " in Function " 
-               << ProfileInfoT<FType, BType>::getFunction(E)->getNameStr() << ": ";
+               << ProfileInfoT<FType, BType>::getFunction(E)->getName() << ": ";
         ASSERTMESSAGE("Edge has negative value");
       }
       return EdgeWeight;
@@ -220,8 +220,8 @@
                                                       DetailedBlockInfo *DI) {
     if (Error) {
       DEBUG(debugEntry(DI));
-      dbgs() << "Block " << DI->BB->getNameStr() << " in Function " 
-             << DI->BB->getParent()->getNameStr() << ": ";
+      dbgs() << "Block " << DI->BB->getName() << " in Function "
+             << DI->BB->getParent()->getName() << ": ";
       ASSERTMESSAGE(Message);
     }
     return;

Modified: llvm/trunk/lib/Analysis/SparsePropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/SparsePropagation.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/SparsePropagation.cpp (original)
+++ llvm/trunk/lib/Analysis/SparsePropagation.cpp Tue Nov 15 10:27:03 2011
@@ -327,13 +327,13 @@
 }
 
 void SparseSolver::Print(Function &F, raw_ostream &OS) const {
-  OS << "\nFUNCTION: " << F.getNameStr() << "\n";
+  OS << "\nFUNCTION: " << F.getName() << "\n";
   for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
     if (!BBExecutable.count(BB))
       OS << "INFEASIBLE: ";
     OS << "\t";
     if (BB->hasName())
-      OS << BB->getNameStr() << ":\n";
+      OS << BB->getName() << ":\n";
     else
       OS << "; anon bb\n";
     for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {

Modified: llvm/trunk/lib/Analysis/Trace.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Trace.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/Trace.cpp (original)
+++ llvm/trunk/lib/Analysis/Trace.cpp Tue Nov 15 10:27:03 2011
@@ -34,7 +34,7 @@
 ///
 void Trace::print(raw_ostream &O) const {
   Function *F = getFunction();
-  O << "; Trace from function " << F->getNameStr() << ", blocks:\n";
+  O << "; Trace from function " << F->getName() << ", blocks:\n";
   for (const_iterator i = begin(), e = end(); i != e; ++i) {
     O << "; ";
     WriteAsOperand(O, *i, true, getModule());

Modified: llvm/trunk/lib/CodeGen/GCMetadata.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GCMetadata.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GCMetadata.cpp (original)
+++ llvm/trunk/lib/CodeGen/GCMetadata.cpp Tue Nov 15 10:27:03 2011
@@ -156,12 +156,12 @@
   
   GCFunctionInfo *FD = &getAnalysis<GCModuleInfo>().getFunctionInfo(F);
   
-  OS << "GC roots for " << FD->getFunction().getNameStr() << ":\n";
+  OS << "GC roots for " << FD->getFunction().getName() << ":\n";
   for (GCFunctionInfo::roots_iterator RI = FD->roots_begin(),
                                       RE = FD->roots_end(); RI != RE; ++RI)
     OS << "\t" << RI->Num << "\t" << RI->StackOffset << "[sp]\n";
   
-  OS << "GC safe points for " << FD->getFunction().getNameStr() << ":\n";
+  OS << "GC safe points for " << FD->getFunction().getName() << ":\n";
   for (GCFunctionInfo::iterator PI = FD->begin(),
                                 PE = FD->end(); PI != PE; ++PI) {
     

Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Nov 15 10:27:03 2011
@@ -335,7 +335,7 @@
   DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
 
     static std::string getGraphName(const MachineFunction *F) {
-      return "CFG for '" + F->getFunction()->getNameStr() + "' function";
+      return "CFG for '" + F->getFunction()->getName().str() + "' function";
     }
 
     std::string getNodeLabel(const MachineBasicBlock *Node,

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Nov 15 10:27:03 2011
@@ -320,7 +320,7 @@
     MF->print(*OS, Indexes);
   }
   *OS << "*** Bad machine code: " << msg << " ***\n"
-      << "- function:    " << MF->getFunction()->getNameStr() << "\n";
+      << "- function:    " << MF->getFunction()->getName() << "\n";
 }
 
 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {

Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Tue Nov 15 10:27:03 2011
@@ -248,8 +248,8 @@
       static int bbcnt = 0;
       if (bbcnt++ % DebugDiv != DebugMod)
         continue;
-      dbgs() << "*** DEBUG scheduling " << Fn.getFunction()->getNameStr() <<
-        ":BB#" << MBB->getNumber() << " ***\n";
+      dbgs() << "*** DEBUG scheduling " << Fn.getFunction()->getName()
+             << ":BB#" << MBB->getNumber() << " ***\n";
     }
 #endif
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Nov 15 10:27:03 2011
@@ -476,8 +476,8 @@
 #endif
   {
     BlockNumber = FuncInfo->MBB->getNumber();
-    BlockName = MF->getFunction()->getNameStr() + ":" +
-                FuncInfo->MBB->getBasicBlock()->getNameStr();
+    BlockName = MF->getFunction()->getName().str() + ":" +
+                FuncInfo->MBB->getBasicBlock()->getName().str();
   }
   DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
         << " '" << BlockName << "'\n"; CurDAG->dump());

Modified: llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp (original)
+++ llvm/trunk/lib/CodeGen/ShrinkWrapping.cpp Tue Nov 15 10:27:03 2011
@@ -158,7 +158,7 @@
   // via --shrink-wrap-func=<funcname>.
 #ifndef NDEBUG
   if (ShrinkWrapFunc != "") {
-    std::string MFName = MF->getFunction()->getNameStr();
+    std::string MFName = MF->getFunction()->getName().str();
     ShrinkWrapThisFunction = (MFName == ShrinkWrapFunc);
   }
 #endif
@@ -1045,7 +1045,7 @@
     return "";
 
   if (MBB->getBasicBlock())
-    return MBB->getBasicBlock()->getNameStr();
+    return MBB->getBasicBlock()->getName().str();
 
   std::ostringstream name;
   name << "_MBB_" << MBB->getNumber();

Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Tue Nov 15 10:27:03 2011
@@ -358,9 +358,9 @@
                                           TAA, TAAParsed, StubSize);
   if (!ErrorCode.empty()) {
     // If invalid, report the error with report_fatal_error.
-    report_fatal_error("Global variable '" + GV->getNameStr() +
-                      "' has an invalid section specifier '" + GV->getSection()+
-                      "': " + ErrorCode + ".");
+    report_fatal_error("Global variable '" + GV->getName() +
+                       "' has an invalid section specifier '" +
+                       GV->getSection() + "': " + ErrorCode + ".");
     // Fall back to dropping it into the data section.
     return DataSection;
   }
@@ -379,9 +379,9 @@
   // to reject it here.
   if (S->getTypeAndAttributes() != TAA || S->getStubSize() != StubSize) {
     // If invalid, report the error with report_fatal_error.
-    report_fatal_error("Global variable '" + GV->getNameStr() +
-                      "' section type or attributes does not match previous"
-                      " section specifier");
+    report_fatal_error("Global variable '" + GV->getName() +
+                       "' section type or attributes does not match previous"
+                       " section specifier");
   }
 
   return S;

Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Tue Nov 15 10:27:03 2011
@@ -94,15 +94,16 @@
   FunctionType *FT = F->getFunctionType();
   for (unsigned i = 0, e = FT->getNumContainedTypes(); i != e; ++i)
     ExtName += getTypeID(FT->getContainedType(i));
-  ExtName + "_" + F->getNameStr();
+  ExtName += "_" + F->getName().str();
 
   sys::ScopedLock Writer(*FunctionsLock);
   ExFunc FnPtr = FuncNames[ExtName];
   if (FnPtr == 0)
-    FnPtr = FuncNames["lle_X_" + F->getNameStr()];
+    FnPtr = FuncNames["lle_X_" + F->getName().str()];
   if (FnPtr == 0)  // Try calling a generic function... if it exists...
     FnPtr = (ExFunc)(intptr_t)
-      sys::DynamicLibrary::SearchForAddressOfSymbol("lle_X_"+F->getNameStr());
+      sys::DynamicLibrary::SearchForAddressOfSymbol("lle_X_" +
+                                                    F->getName().str());
   if (FnPtr != 0)
     ExportedFunctions->insert(std::make_pair(F, FnPtr));  // Cache for later
   return FnPtr;

Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp Tue Nov 15 10:27:03 2011
@@ -118,7 +118,7 @@
   if (JITEmitDebugInfoToDisk) {
     std::string Filename;
     raw_string_ostream O2(Filename);
-    O2 << "/tmp/llvm_function_" << I.FnStart << "_" << F->getNameStr() << ".o";
+    O2 << "/tmp/llvm_function_" << I.FnStart << "_" << F->getName() << ".o";
     O2.flush();
     std::string Errors;
     raw_fd_ostream O3(Filename.c_str(), Errors);

Modified: llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Tue Nov 15 10:27:03 2011
@@ -74,7 +74,7 @@
 
       std::string getDescription() const {
         return std::string((IsArg ? "Argument #" : "Return value #"))
-               + utostr(Idx) + " of function " + F->getNameStr();
+               + utostr(Idx) + " of function " + F->getName().str();
       }
     };
 

Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Tue Nov 15 10:27:03 2011
@@ -1902,7 +1902,7 @@
   MadeIRChange = false;
   
   DEBUG(errs() << "\n\nINSTCOMBINE ITERATION #" << Iteration << " on "
-        << F.getNameStr() << "\n");
+               << F.getName() << "\n");
 
   {
     // Do a depth-first traversal of the function, populate the worklist with

Modified: llvm/trunk/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp Tue Nov 15 10:27:03 2011
@@ -69,7 +69,7 @@
                                     BasicBlock* b,
                                     unsigned i) {
   DEBUG(dbgs() << "--Edge Counter for " << (e) << " in " \
-               << ((b)?(b)->getNameStr():"0") << " (# " << (i) << ")\n");
+               << ((b)?(b)->getName():"0") << " (# " << (i) << ")\n");
 }
 
 bool OptimalEdgeProfiler::runOnModule(Module &M) {
@@ -127,7 +127,7 @@
   unsigned i = 0;
   for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
     if (F->isDeclaration()) continue;
-    DEBUG(dbgs() << "Working on " << F->getNameStr() << "\n");
+    DEBUG(dbgs() << "Working on " << F->getName() << "\n");
 
     // Calculate a Maximum Spanning Tree with the edge weights determined by
     // ProfileEstimator. ProfileEstimator also assign weights to the virtual

Modified: llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/PathProfiling.cpp Tue Nov 15 10:27:03 2011
@@ -665,7 +665,7 @@
 // Generate a .dot graph to represent the DAG and pathNumbers
 void BLInstrumentationDag::generateDotGraph() {
   std::string errorInfo;
-  std::string functionName = getFunction().getNameStr();
+  std::string functionName = getFunction().getName().str();
   std::string filename = "pathdag." + functionName + ".dot";
 
   DEBUG (dbgs() << "Writing '" << filename << "'...\n");
@@ -750,7 +750,8 @@
 // Sets the Value of the pathNumber.  Used by the instrumentation code.
 void BLInstrumentationNode::setStartingPathNumber(Value* pathNumber) {
   DEBUG(dbgs() << "  SPN-" << getName() << " <-- " << (pathNumber ?
-                                                       pathNumber->getNameStr() : "unused") << "\n");
+                                                       pathNumber->getName() :
+                                                       "unused") << "\n");
   _startingPathNumber = pathNumber;
 }
 
@@ -760,7 +761,7 @@
 
 void BLInstrumentationNode::setEndingPathNumber(Value* pathNumber) {
   DEBUG(dbgs() << "  EPN-" << getName() << " <-- "
-        << (pathNumber ? pathNumber->getNameStr() : "unused") << "\n");
+               << (pathNumber ? pathNumber->getName() : "unused") << "\n");
   _endingPathNumber = pathNumber;
 }
 
@@ -1239,9 +1240,9 @@
       insertPoint++;
 
     DEBUG(dbgs() << "\nInstrumenting method call block '"
-          << node->getBlock()->getNameStr() << "'\n");
+                 << node->getBlock()->getName() << "'\n");
     DEBUG(dbgs() << "   Path number initialized: "
-          << ((node->getStartingPathNumber()) ? "yes" : "no") << "\n");
+                 << ((node->getStartingPathNumber()) ? "yes" : "no") << "\n");
 
     Value* newpn;
     if( node->getStartingPathNumber() ) {
@@ -1370,7 +1371,7 @@
     if (F->isDeclaration())
       continue;
 
-    DEBUG(dbgs() << "Function: " << F->getNameStr() << "\n");
+    DEBUG(dbgs() << "Function: " << F->getName() << "\n");
     functionNumber++;
 
     // set function number

Modified: llvm/trunk/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Value.cpp (original)
+++ llvm/trunk/lib/VMCore/Value.cpp Tue Nov 15 10:27:03 2011
@@ -66,7 +66,7 @@
   // a <badref>
   //
   if (!use_empty()) {
-    dbgs() << "While deleting: " << *VTy << " %" << getNameStr() << "\n";
+    dbgs() << "While deleting: " << *VTy << " %" << getName() << "\n";
     for (use_iterator I = use_begin(), E = use_end(); I != E; ++I)
       dbgs() << "Use still stuck around after Def is destroyed:"
            << **I << "\n";
@@ -554,7 +554,7 @@
   // All callbacks, weak references, and assertingVHs should be dropped by now.
   if (V->HasValueHandle) {
 #ifndef NDEBUG      // Only in +Asserts mode...
-    dbgs() << "While deleting: " << *V->getType() << " %" << V->getNameStr()
+    dbgs() << "While deleting: " << *V->getType() << " %" << V->getName()
            << "\n";
     if (pImpl->ValueHandles[V]->getKind() == Assert)
       llvm_unreachable("An asserting value handle still pointed to this"
@@ -617,8 +617,8 @@
       case Tracking:
       case Weak:
         dbgs() << "After RAUW from " << *Old->getType() << " %"
-          << Old->getNameStr() << " to " << *New->getType() << " %"
-          << New->getNameStr() << "\n";
+               << Old->getName() << " to " << *New->getType() << " %"
+               << New->getName() << "\n";
         llvm_unreachable("A tracking or weak value handle still pointed to the"
                          " old value!\n");
       default:

Modified: llvm/trunk/tools/bugpoint/ExtractFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ExtractFunction.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/tools/bugpoint/ExtractFunction.cpp (original)
+++ llvm/trunk/tools/bugpoint/ExtractFunction.cpp Tue Nov 15 10:27:03 2011
@@ -340,7 +340,7 @@
     // If the BB doesn't have a name, give it one so we have something to key
     // off of.
     if (!BB->hasName()) BB->setName("tmpbb");
-    BlocksToNotExtractFile.os() << BB->getParent()->getNameStr() << " "
+    BlocksToNotExtractFile.os() << BB->getParent()->getName() << " "
                                 << BB->getName() << "\n";
   }
   BlocksToNotExtractFile.os().close();

Modified: llvm/trunk/tools/llvm-prof/llvm-prof.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-prof/llvm-prof.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-prof/llvm-prof.cpp (original)
+++ llvm/trunk/tools/llvm-prof/llvm-prof.cpp Tue Nov 15 10:27:03 2011
@@ -200,9 +200,9 @@
     }
 
     outs() << format("%3d", i+1) << ". "
-      << format("%5.2g", FunctionCounts[i].second) << "/"
-      << format("%g", TotalExecutions) << " "
-      << FunctionCounts[i].first->getNameStr() << "\n";
+           << format("%5.2g", FunctionCounts[i].second) << "/"
+           << format("%g", TotalExecutions) << " "
+           << FunctionCounts[i].first->getName() << "\n";
   }
 
   std::set<Function*> FunctionsToPrint;
@@ -225,12 +225,12 @@
   for (unsigned i = 0; i != BlocksToPrint; ++i) {
     if (Counts[i].second == 0) break;
     Function *F = Counts[i].first->getParent();
-    outs() << format("%3d", i+1) << ". " 
-      << format("%5g", Counts[i].second/(double)TotalExecutions*100) << "% "
-      << format("%5.0f", Counts[i].second) << "/"
-      << format("%g", TotalExecutions) << "\t"
-      << F->getNameStr() << "() - "
-       << Counts[i].first->getNameStr() << "\n";
+    outs() << format("%3d", i+1) << ". "
+           << format("%5g", Counts[i].second/(double)TotalExecutions*100)<<"% "
+           << format("%5.0f", Counts[i].second) << "/"
+           << format("%g", TotalExecutions) << "\t"
+           << F->getName() << "() - "
+           << Counts[i].first->getName() << "\n";
     FunctionsToPrint.insert(F);
   }
 

Modified: llvm/trunk/tools/opt/PrintSCC.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/PrintSCC.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/tools/opt/PrintSCC.cpp (original)
+++ llvm/trunk/tools/opt/PrintSCC.cpp Tue Nov 15 10:27:03 2011
@@ -101,8 +101,8 @@
     errs() << "\nSCC #" << ++sccNum << " : ";
     for (std::vector<CallGraphNode*>::const_iterator I = nextSCC.begin(),
            E = nextSCC.end(); I != E; ++I)
-      errs() << ((*I)->getFunction() ? (*I)->getFunction()->getNameStr()
-                 : std::string("external node")) << ", ";
+      errs() << ((*I)->getFunction() ? (*I)->getFunction()->getName()
+                                     : "external node") << ", ";
     if (nextSCC.size() == 1 && SCCI.hasLoop())
       errs() << " (Has self-loop).";
   }

Modified: llvm/trunk/tools/opt/opt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=144648&r1=144647&r2=144648&view=diff
==============================================================================
--- llvm/trunk/tools/opt/opt.cpp (original)
+++ llvm/trunk/tools/opt/opt.cpp Tue Nov 15 10:27:03 2011
@@ -291,8 +291,8 @@
   virtual bool runOnRegion(Region *R, RGPassManager &RGM) {
     if (!Quiet) {
       Out << "Printing analysis '" << PassToPrint->getPassName() << "' for "
-        << "region: '" << R->getNameStr() << "' in function '"
-        << R->getEntry()->getParent()->getNameStr() << "':\n";
+          << "region: '" << R->getNameStr() << "' in function '"
+          << R->getEntry()->getParent()->getName() << "':\n";
     }
     // Get and print pass...
    getAnalysisID<Pass>(PassToPrint->getTypeInfo()).print(Out,



From grosbach at apple.com  Tue Nov 15 10:46:22 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 16:46:22 -0000
Subject: [llvm-commits] [llvm] r144649 - in /llvm/trunk/lib/MC:
 ELFObjectWriter.cpp ELFObjectWriter.h MCELFStreamer.cpp MCModule.cpp
 MCObjectFileInfo.cpp
Message-ID: <20111115164622.8599F2A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 10:46:22 2011
New Revision: 144649

URL: http://llvm.org/viewvc/llvm-project?rev=144649&view=rev
Log:
Tidy up. 80 columns.

Modified:
    llvm/trunk/lib/MC/ELFObjectWriter.cpp
    llvm/trunk/lib/MC/ELFObjectWriter.h
    llvm/trunk/lib/MC/MCELFStreamer.cpp
    llvm/trunk/lib/MC/MCModule.cpp
    llvm/trunk/lib/MC/MCObjectFileInfo.cpp

Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=144649&r1=144648&r2=144649&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Tue Nov 15 10:46:22 2011
@@ -1579,8 +1579,8 @@
   return Type;
 }
 
-void
-PPCELFObjectWriter::adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) {
+void PPCELFObjectWriter::
+adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) {
   switch ((unsigned)Fixup.getKind()) {
     case PPC::fixup_ppc_ha16:
     case PPC::fixup_ppc_lo16:

Modified: llvm/trunk/lib/MC/ELFObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=144649&r1=144648&r2=144649&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.h (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.h Tue Nov 15 10:46:22 2011
@@ -240,33 +240,38 @@
       F.getContents() += StringRef(buf, 8);
     }
 
-    virtual void WriteHeader(uint64_t SectionDataSize, unsigned NumberOfSections);
+    virtual void WriteHeader(uint64_t SectionDataSize,
+                             unsigned NumberOfSections);
 
     /// Default e_flags = 0
     virtual void WriteEFlags() { Write32(0); }
 
-    virtual void WriteSymbolEntry(MCDataFragment *SymtabF, MCDataFragment *ShndxF,
-                          uint64_t name, uint8_t info,
-                          uint64_t value, uint64_t size,
-                          uint8_t other, uint32_t shndx,
-                          bool Reserved);
+    virtual void WriteSymbolEntry(MCDataFragment *SymtabF,
+                                  MCDataFragment *ShndxF,
+                                  uint64_t name, uint8_t info,
+                                  uint64_t value, uint64_t size,
+                                  uint8_t other, uint32_t shndx,
+                                  bool Reserved);
 
     virtual void WriteSymbol(MCDataFragment *SymtabF,  MCDataFragment *ShndxF,
                      ELFSymbolData &MSD,
                      const MCAsmLayout &Layout);
 
     typedef DenseMap<const MCSectionELF*, uint32_t> SectionIndexMapTy;
-    virtual void WriteSymbolTable(MCDataFragment *SymtabF, MCDataFragment *ShndxF,
-                          const MCAssembler &Asm,
-                          const MCAsmLayout &Layout,
-                          const SectionIndexMapTy &SectionIndexMap);
-
-    virtual void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
-                                  const MCFragment *Fragment, const MCFixup &Fixup,
+    virtual void WriteSymbolTable(MCDataFragment *SymtabF,
+                                  MCDataFragment *ShndxF,
+                                  const MCAssembler &Asm,
+                                  const MCAsmLayout &Layout,
+                                  const SectionIndexMapTy &SectionIndexMap);
+
+    virtual void RecordRelocation(const MCAssembler &Asm,
+                                  const MCAsmLayout &Layout,
+                                  const MCFragment *Fragment,
+                                  const MCFixup &Fixup,
                                   MCValue Target, uint64_t &FixedValue);
 
     virtual uint64_t getSymbolIndexInSymbolTable(const MCAssembler &Asm,
-                                         const MCSymbol *S);
+                                                 const MCSymbol *S);
 
     // Map from a group section to the signature symbol
     typedef DenseMap<const MCSectionELF*, const MCSymbol*> GroupMapTy;
@@ -347,7 +352,8 @@
     virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
                                   bool IsPCRel, bool IsRelocWithSymbol,
                                   int64_t Addend) = 0;
-    virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) { }
+    virtual void adjustFixupOffset(const MCFixup &Fixup,
+                                   uint64_t &RelocOffset) {}
   };
 
   //===- X86ELFObjectWriter -------------------------------------------===//

Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=144649&r1=144648&r2=144649&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCELFStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCELFStreamer.cpp Tue Nov 15 10:46:22 2011
@@ -205,10 +205,10 @@
 
   if (MCELF::GetBinding(SD) == ELF_STB_Local) {
     const MCSection *Section = getAssembler().getContext().getELFSection(".bss",
-                                                                    ELF::SHT_NOBITS,
-                                                                    ELF::SHF_WRITE |
-                                                                    ELF::SHF_ALLOC,
-                                                                    SectionKind::getBSS());
+                                                         ELF::SHT_NOBITS,
+                                                         ELF::SHF_WRITE |
+                                                         ELF::SHF_ALLOC,
+                                                         SectionKind::getBSS());
     Symbol->setSection(*Section);
 
     struct LocalCommon L = {&SD, Size, ByteAlignment};

Modified: llvm/trunk/lib/MC/MCModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCModule.cpp?rev=144649&r1=144648&r2=144649&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCModule.cpp (original)
+++ llvm/trunk/lib/MC/MCModule.cpp Tue Nov 15 10:46:22 2011
@@ -1,4 +1,4 @@
-//===- lib/MC/MCModule.cpp - MCModule implementation --------------------------===//
+//===- lib/MC/MCModule.cpp - MCModule implementation ----------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //

Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=144649&r1=144648&r2=144649&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Tue Nov 15 10:46:22 2011
@@ -56,8 +56,8 @@
 
   TLSThreadInitSection
     = Ctx->getMachOSection("__DATA", "__thread_init",
-                           MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS,
-                           SectionKind::getDataRel());
+                          MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS,
+                          SectionKind::getDataRel());
 
   CStringSection // .cstring
     = Ctx->getMachOSection("__TEXT", "__cstring",
@@ -221,8 +221,8 @@
 void MCObjectFileInfo::InitELFMCObjectFileInfo(Triple T) {
   if (T.getArch() == Triple::x86) {
     PersonalityEncoding = (RelocM == Reloc::PIC_)
-      ? dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
-      : dwarf::DW_EH_PE_absptr;
+     ? dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
+     : dwarf::DW_EH_PE_absptr;
     LSDAEncoding = (RelocM == Reloc::PIC_)
       ? dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
       : dwarf::DW_EH_PE_absptr;
@@ -230,8 +230,8 @@
       ? dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
       : dwarf::DW_EH_PE_absptr;
     TTypeEncoding = (RelocM == Reloc::PIC_)
-      ? dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
-      : dwarf::DW_EH_PE_absptr;
+     ? dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
+     : dwarf::DW_EH_PE_absptr;
   } else if (T.getArch() == Triple::x86_64) {
     FDECFIEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
 



From clattner at apple.com  Tue Nov 15 11:43:33 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 15 Nov 2011 09:43:33 -0800
Subject: [llvm-commits] [PATCH] PR889: devirtualize Value::printCustom
In-Reply-To: <CANd1uZm+riB-S+xg=n58nwSAovJoEt0q0e+2+Ty5gJ3U3Grjaw@mail.gmail.com>
References: <CANd1uZkGs+3ba7BCFJgnBA0MDEt16SNN1um2Qjgq0RRRMkgWjg@mail.gmail.com>
	<CAGCO0Kgagyg7=aD8kStnPSfiuxUnRskKM1BfOkNiQ=kB8x8uiw@mail.gmail.com>
	<CANd1uZmO4JhwQGZaXFcX2e2Z+F9vfrbSqP9L0i3op_zVkdS2tg@mail.gmail.com>
	<28388F1A-D44C-4218-A157-A177E2D114FB@apple.com>
	<CANd1uZm+riB-S+xg=n58nwSAovJoEt0q0e+2+Ty5gJ3U3Grjaw@mail.gmail.com>
Message-ID: <85F11A88-37FF-45DE-97D0-CB44D23B8EE6@apple.com>


On Nov 15, 2011, at 12:29 AM, Jay Foad wrote:

> On 14 November 2011 18:38, Chris Lattner <clattner at apple.com> wrote:
>> The "right" way to fix this is to eliminate PseudoSourceValue, which has always been a disgusting hack.  Places in codegen that can uses PseudoSourceValue (e.g. the SDLoadNode and memoperands)
> 
> LoadSDNode has-a MachineMemOperand, which has-a MachinePointerInfo,
> which is the (only?) thing that can refer to PseudoSourceValues.

Aha, so we're already making progress there :).

>> should use a discriminated union of "Value* and SomeMachineLocationType".
> 
> I assume you're not talking about (MC's) MachineLocation here, but
> about some new machine location type yet to be invented.

Right.  Now that you've forced me to actually look at the code ;-) I see that we're well placed for this.  Basically MachinePointerInfo becomes a PointerUnion<const Value*, SomethingElse*> where the SomethingElse pointers are pointers to singletons that represent the stack and other things that PseudoSourceValue references.

My recollection is that the Value* is used for alias queries and for printing stuff out with verbose asm.  MachinePointerInfo should just get helper methods that check for the special cases, then bounce on to the standard AliasAnalysis interface if it has a real Value*.

-Chris

From clattner at apple.com  Tue Nov 15 11:45:48 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 15 Nov 2011 09:45:48 -0800
Subject: [llvm-commits] pr11367
In-Reply-To: <1CF650DE-6A87-445E-8F76-A3034E121D98@gmail.com>
References: <CAG3jReJHN2jo=Mv97jR9Ep2jywLTbMPyvF03y6Q_ffU6m0S8wA@mail.gmail.com>
	<B1289D79-A496-43C2-A644-564033AF3EF2@nondot.org>
	<AEE31309-99DD-47C3-912A-2674D658E6A7@apple.com>
	<1CF650DE-6A87-445E-8F76-A3034E121D98@gmail.com>
Message-ID: <34B7AD23-CF92-4485-B2BB-ED55C9C5F628@apple.com>


On Nov 14, 2011, at 11:24 AM, Matt Pharr wrote:

> It's not a completely theoretical use case: the ispc compiler depended on the old behavior from LinkModules() ("link everything in the provided modules together, and don't be clever about skipping stuff that seems to not be used"), and the lazy linking change broke that.

Why?  Can you explain the use case?

-Chris

From grosbach at apple.com  Tue Nov 15 11:49:59 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 17:49:59 -0000
Subject: [llvm-commits] [llvm] r144650 -
	/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Message-ID: <20111115175000.0EBE12A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 11:49:59 2011
New Revision: 144650

URL: http://llvm.org/viewvc/llvm-project?rev=144650&view=rev
Log:
ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.

rdar://10435076

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=144650&r1=144649&r2=144650&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 15 11:49:59 2011
@@ -5232,6 +5232,19 @@
           (VLD1d32wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
           (VLD1d64wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
+//        with writeback, register stride
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+          (VLD1d8wb_register  VecListOneD:$Vd, zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+          (VLD1d16wb_register VecListOneD:$Vd, zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+          (VLD1d32wb_register VecListOneD:$Vd, zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+          (VLD1d64wb_register VecListOneD:$Vd, zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, pred:$p)>;
 
 // Load two D registers.
 defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
@@ -5251,6 +5264,19 @@
           (VLD1q32wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
           (VLD1q64wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
+//        with writeback, register stride
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+          (VLD1q8wb_register  VecListTwoD:$Vd, zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+          (VLD1q16wb_register VecListTwoD:$Vd, zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+          (VLD1q32wb_register VecListTwoD:$Vd, zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+          (VLD1q64wb_register VecListTwoD:$Vd, zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, pred:$p)>;
 
 // Load three D registers.
 defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
@@ -5274,6 +5300,19 @@
 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
                           (VLD1d64Twb_fixed VecListThreeD:$Vd, zero_reg,
                                             addrmode6:$Rn, pred:$p)>;
+//        with writeback, register stride
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+                        (VLD1d8Twb_register VecListThreeD:$Vd, zero_reg,
+                                            addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+                        (VLD1d16Twb_register VecListThreeD:$Vd, zero_reg,
+                                             addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+                        (VLD1d32Twb_register VecListThreeD:$Vd, zero_reg,
+                                             addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+                        (VLD1d64Twb_register VecListThreeD:$Vd, zero_reg,
+                                             addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
 
 
 // Load four D registers.
@@ -5298,6 +5337,19 @@
 defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
                           (VLD1d64Qwb_fixed VecListFourD:$Vd, zero_reg,
                                             addrmode6:$Rn, pred:$p)>;
+//        with writeback, register stride
+defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+                       (VLD1d8Qwb_register VecListFourD:$Vd, zero_reg,
+                                           addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+                       (VLD1d16Qwb_register VecListFourD:$Vd, zero_reg,
+                                            addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+                       (VLD1d32Qwb_register VecListFourD:$Vd, zero_reg,
+                                            addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
+                       (VLD1d64Qwb_register VecListFourD:$Vd, zero_reg,
+                                            addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
 
 // VST1 requires a size suffix, but also accepts type specific variants.
 // Store one D register.
@@ -5318,6 +5370,19 @@
           (VST1d32wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
 defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
           (VST1d64wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
+//        with writeback, register stride
+defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
+          (VST1d8wb_register  zero_reg, addrmode6:$Rn, rGPR:$Rm,
+                              VecListOneD:$Vd, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
+          (VST1d16wb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
+                              VecListOneD:$Vd, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
+          (VST1d32wb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
+                              VecListOneD:$Vd, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
+          (VST1d64wb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
+                              VecListOneD:$Vd, pred:$p)>;
 
 // Store two D registers.
 defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
@@ -5337,6 +5402,19 @@
           (VST1q32wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
 defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
           (VST1q64wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
+//        with writeback, register stride
+defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
+          (VST1q8wb_register  zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
+          (VST1q16wb_register zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
+          (VST1q32wb_register zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>;
+defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
+          (VST1q64wb_register zero_reg, addrmode6:$Rn,
+                              rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>;
 
 // FIXME: The three and four register VST1 instructions haven't been moved
 // to the VecList* encoding yet, so we can't do assembly parsing support



From clattner at apple.com  Tue Nov 15 11:53:39 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 15 Nov 2011 09:53:39 -0800
Subject: [llvm-commits] [llvm] r144600 - /llvm/trunk/docs/index.html
In-Reply-To: <20111115011437.85FCD2A6C131@llvm.org>
References: <20111115011437.85FCD2A6C131@llvm.org>
Message-ID: <17583FD5-F653-485D-9255-19A42D71BFFB@apple.com>


On Nov 14, 2011, at 5:14 PM, Devang Patel wrote:

> Author: dpatel
> Date: Mon Nov 14 19:14:37 2011
> New Revision: 144600
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=144600&view=rev
> Log:
> Add ObjCPropertyDebugInfo.html

Hi Devang,

Can this be merged into some other document, like the SourceLevelDebugging doc?

-Chris

> 
> Modified:
>    llvm/trunk/docs/index.html
> 
> Modified: llvm/trunk/docs/index.html
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/index.html?rev=144600&r1=144599&r2=144600&view=diff
> ==============================================================================
> --- llvm/trunk/docs/index.html (original)
> +++ llvm/trunk/docs/index.html Mon Nov 14 19:14:37 2011
> @@ -212,6 +212,9 @@
> <li><a href="BranchWeightMetadata.html">Branch Weight Metadata</a> - Provides
> information about Branch Prediction Information.</li>
> 
> +<li><a href="ObjCPropertyDebugInfo.html">Objective C Property Debug Info</a> 
> +- Debugging information extension for Objective C Property.</li>
> +
> </ul>
> 
> <!--=======================================================================-->
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From dpatel at apple.com  Tue Nov 15 12:06:28 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 15 Nov 2011 10:06:28 -0800
Subject: [llvm-commits] [llvm] r144600 - /llvm/trunk/docs/index.html
In-Reply-To: <17583FD5-F653-485D-9255-19A42D71BFFB@apple.com>
References: <20111115011437.85FCD2A6C131@llvm.org>
	<17583FD5-F653-485D-9255-19A42D71BFFB@apple.com>
Message-ID: <04027E85-8C4F-4DCD-AAF7-68CE8C9C036F@apple.com>

Hi Chris,

On Nov 15, 2011, at 9:53 AM, Chris Lattner wrote:

> On Nov 14, 2011, at 5:14 PM, Devang Patel wrote:
> 
>> Author: dpatel
>> Date: Mon Nov 14 19:14:37 2011
>> New Revision: 144600
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=144600&view=rev
>> Log:
>> Add ObjCPropertyDebugInfo.html
> 
> Hi Devang,
> 
> Can this be merged into some other document, like the SourceLevelDebugging doc?
> 

SourceLevelDebugging is meant for clang+llvm developers. Where as lldb developers are also targeted by this doc and I also expect to see a doc on recent accelerator tables work where audience is llvm+lldb developers.

If you still think SourceLevelDebugging is appropriate then I'll merge them.
-
Devang

> -Chris
> 
>> 
>> Modified:
>>   llvm/trunk/docs/index.html
>> 
>> Modified: llvm/trunk/docs/index.html
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/index.html?rev=144600&r1=144599&r2=144600&view=diff
>> ==============================================================================
>> --- llvm/trunk/docs/index.html (original)
>> +++ llvm/trunk/docs/index.html Mon Nov 14 19:14:37 2011
>> @@ -212,6 +212,9 @@
>> <li><a href="BranchWeightMetadata.html">Branch Weight Metadata</a> - Provides
>> information about Branch Prediction Information.</li>
>> 
>> +<li><a href="ObjCPropertyDebugInfo.html">Objective C Property Debug Info</a> 
>> +- Debugging information extension for Objective C Property.</li>
>> +
>> </ul>
>> 
>> <!--=======================================================================-->
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 


From benny.kra at googlemail.com  Tue Nov 15 12:13:17 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 15 Nov 2011 18:13:17 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r144652 - in /llvm-gcc-4.2/trunk/gcc:
 llvm-backend.cpp llvm-convert.cpp
Message-ID: <20111115181317.C504B2A6C131@llvm.org>

Author: d0k
Date: Tue Nov 15 12:13:17 2011
New Revision: 144652

URL: http://llvm.org/viewvc/llvm-project?rev=144652&view=rev
Log:
Remove uses of Value::getNameStr from llvm-gcc.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=144652&r1=144651&r2=144652&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Tue Nov 15 12:13:17 2011
@@ -1649,13 +1649,9 @@
   }
 
   if (TheDebugInfo) {
-    std::string Name = GV->getNameStr();
-    const char LPrefix[] = "\01L_OBJC_";
-    const char lPrefix[] = "\01l_OBJC_";
-
     if (flag_objc_abi == -1 || flag_objc_abi == 0 ||
-        (strncmp(Name.c_str(), LPrefix, sizeof(LPrefix) - 1) != 0 &&
-         strncmp(Name.c_str(), lPrefix, sizeof(lPrefix) - 1) != 0))
+        (!GV->getName().startswith("\01L_OBJC_") &&
+         !GV->getName().startswith("\01l_OBJC_")))
       TheDebugInfo->EmitGlobalVariable(GV, decl);
   }
 

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=144652&r1=144651&r2=144652&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Nov 15 12:13:17 2011
@@ -3615,7 +3615,7 @@
 Value *TreeToLLVM::EmitABS_EXPR(tree exp) {
   Value *Op = Emit(TREE_OPERAND(exp, 0), 0);
   if (!Op->getType()->isFloatingPointTy()) {
-    Value *OpN = Builder.CreateNeg(Op, (Op->getNameStr()+"neg").c_str());
+    Value *OpN = Builder.CreateNeg(Op, Op->getName() + "neg");
     ICmpInst::Predicate pred = TYPE_UNSIGNED(TREE_TYPE(TREE_OPERAND(exp, 0))) ?
       ICmpInst::ICMP_UGE : ICmpInst::ICMP_SGE;
     Value *Cmp = Builder.CreateICmp(pred, Op,
@@ -3689,8 +3689,7 @@
               cast<VectorType>(Ty)->getElementType()->isFloatingPointTy())) {
     Op = BitCastToType(Op, getSuitableBitCastIntType(Ty));
   }
-  return BitCastToType(Builder.CreateNot(Op,
-                                         (Op->getNameStr()+"not").c_str()),Ty);
+  return BitCastToType(Builder.CreateNot(Op, Op->getName() + "not", Ty);
 }
 
 Value *TreeToLLVM::EmitTRUTH_NOT_EXPR(tree exp) {
@@ -3698,7 +3697,7 @@
   if (V->getType() != Type::getInt1Ty(Context))
     V = Builder.CreateICmpNE(V,
           Constant::getNullValue(V->getType()), "toBool");
-  V = Builder.CreateNot(V, (V->getNameStr()+"not").c_str());
+  V = Builder.CreateNot(V, V->getName() + "not");
   return CastToUIntType(V, ConvertType(TREE_TYPE(exp)));
 }
 
@@ -3914,7 +3913,7 @@
   Value *RHS = Emit(TREE_OPERAND(exp, 1), 0);
   if (RHS->getType() != LHS->getType())
     RHS = Builder.CreateIntCast(RHS, LHS->getType(), false,
-                                (RHS->getNameStr()+".cast").c_str());
+                                RHS->getName() + ".cast");
 
   return Builder.CreateBinOp((Instruction::BinaryOps)Opc, LHS, RHS);
 }
@@ -3927,13 +3926,12 @@
     Type *Ty =
       IntegerType::get(Context,
                        TYPE_PRECISION(TREE_TYPE (TREE_OPERAND (exp, 0))));
-    In = Builder.CreatePtrToInt(In, Ty,
-                                (In->getNameStr()+".cast").c_str());
+    In = Builder.CreatePtrToInt(In, Ty, In->getName() + ".cast");
   }
 
   if (Amt->getType() != In->getType())
     Amt = Builder.CreateIntCast(Amt, In->getType(), false,
-                                (Amt->getNameStr()+".cast").c_str());
+                                Amt->getName() + ".cast");
 
   Value *TypeSize =
     ConstantInt::get(In->getType(),
@@ -4175,11 +4173,11 @@
     // Calculate |LHS| ...
     Value *MinusLHS = Builder.CreateNeg(LHS);
     Value *AbsLHS = Builder.CreateSelect(LHSIsPositive, LHS, MinusLHS,
-                                         (LHS->getNameStr()+".abs").c_str());
+                                         LHS->getName() + ".abs");
     // ... and |RHS|
     Value *MinusRHS = Builder.CreateNeg(RHS);
     Value *AbsRHS = Builder.CreateSelect(RHSIsPositive, RHS, MinusRHS,
-                                         (RHS->getNameStr()+".abs").c_str());
+                                         RHS->getName() + ".abs");
 
     // Calculate AbsRDiv = (|LHS| + (|RHS| UDiv 2)) UDiv |RHS|.
     Value *HalfAbsRHS = Builder.CreateUDiv(AbsRHS, Two);



From benny.kra at googlemail.com  Tue Nov 15 12:13:19 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 15 Nov 2011 18:13:19 -0000
Subject: [llvm-commits] [dragonegg] r144653 - in /dragonegg/trunk:
 include/dragonegg/Debug.h src/Convert.cpp src/Debug.cpp
Message-ID: <20111115181319.C61D32A6C131@llvm.org>

Author: d0k
Date: Tue Nov 15 12:13:19 2011
New Revision: 144653

URL: http://llvm.org/viewvc/llvm-project?rev=144653&view=rev
Log:
Remove uses of Value::getNameStr from DragonEgg.

Modified:
    dragonegg/trunk/include/dragonegg/Debug.h
    dragonegg/trunk/src/Convert.cpp
    dragonegg/trunk/src/Debug.cpp

Modified: dragonegg/trunk/include/dragonegg/Debug.h
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Debug.h?rev=144653&r1=144652&r2=144653&view=diff
==============================================================================
--- dragonegg/trunk/include/dragonegg/Debug.h (original)
+++ dragonegg/trunk/include/dragonegg/Debug.h Tue Nov 15 12:13:19 2011
@@ -307,7 +307,7 @@
 
   /// EmitDeclare - Constructs the debug code for allocation of a new variable.
   /// region - "llvm.dbg.declare."
-  void EmitDeclare(tree_node *decl, unsigned Tag, const char *Name,
+  void EmitDeclare(tree_node *decl, unsigned Tag, StringRef Name,
                    tree_node *type, Value *AI, LLVMBuilder &Builder);
 
   /// EmitStopPoint - Emit a call to llvm.dbg.stoppoint to indicate a change of

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=144653&r1=144652&r2=144653&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Tue Nov 15 12:13:19 2011
@@ -1862,12 +1862,10 @@
   if (EmitDebugInfo()) {
     if (DECL_NAME(decl)) {
       TheDebugInfo->EmitDeclare(decl, dwarf::DW_TAG_auto_variable,
-                                AI->getNameStr().c_str(), TREE_TYPE(decl), AI,
-                                Builder);
+                                AI->getName(), TREE_TYPE(decl), AI, Builder);
     } else if (TREE_CODE(decl) == RESULT_DECL) {
       TheDebugInfo->EmitDeclare(decl, dwarf::DW_TAG_return_variable,
-                                AI->getNameStr().c_str(), TREE_TYPE(decl), AI,
-                                Builder);
+                                AI->getName(), TREE_TYPE(decl), AI, Builder);
     }
   }
 }

Modified: dragonegg/trunk/src/Debug.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Debug.cpp?rev=144653&r1=144652&r2=144653&view=diff
==============================================================================
--- dragonegg/trunk/src/Debug.cpp (original)
+++ dragonegg/trunk/src/Debug.cpp Tue Nov 15 12:13:19 2011
@@ -372,7 +372,7 @@
 }
 
 /// EmitDeclare - Constructs the debug code for allocation of a new variable.
-void DebugInfo::EmitDeclare(tree decl, unsigned Tag, const char *Name,
+void DebugInfo::EmitDeclare(tree decl, unsigned Tag, StringRef Name,
                             tree type, Value *AI, LLVMBuilder &Builder) {
 
   // Ignore compiler generated temporaries.



From ahatanaka at mips.com  Tue Nov 15 12:20:08 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Tue, 15 Nov 2011 18:20:08 -0000
Subject: [llvm-commits] [llvm] r144654 - in /llvm/trunk/lib/Target/Mips:
 CMakeLists.txt MipsAsmPrinter.cpp
Message-ID: <20111115182008.AFE902A6C131@llvm.org>

Author: ahatanak
Date: Tue Nov 15 12:20:08 2011
New Revision: 144654

URL: http://llvm.org/viewvc/llvm-project?rev=144654&view=rev
Log:
Remove MipsMCSymbolRefExpr.


Modified:
    llvm/trunk/lib/Target/Mips/CMakeLists.txt
    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=144654&r1=144653&r2=144654&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Tue Nov 15 12:20:08 2011
@@ -22,7 +22,6 @@
   MipsISelLowering.cpp
   MipsFrameLowering.cpp
   MipsMCInstLower.cpp
-  MipsMCSymbolRefExpr.cpp
   MipsRegisterInfo.cpp
   MipsSubtarget.cpp
   MipsTargetMachine.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=144654&r1=144653&r2=144654&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Tue Nov 15 12:20:08 2011
@@ -18,7 +18,6 @@
 #include "MipsInstrInfo.h"
 #include "MipsMachineFunction.h"
 #include "MipsMCInstLower.h"
-#include "MipsMCSymbolRefExpr.h"
 #include "InstPrinter/MipsInstPrinter.h"
 #include "MCTargetDesc/MipsBaseInfo.h"
 #include "llvm/ADT/SmallString.h"



From ahatanaka at mips.com  Tue Nov 15 12:22:49 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Tue, 15 Nov 2011 18:22:49 -0000
Subject: [llvm-commits] [llvm] r144655 - in /llvm/trunk/lib/Target/Mips:
 MipsMCSymbolRefExpr.cpp MipsMCSymbolRefExpr.h
Message-ID: <20111115182249.327DE2A6C131@llvm.org>

Author: ahatanak
Date: Tue Nov 15 12:22:48 2011
New Revision: 144655

URL: http://llvm.org/viewvc/llvm-project?rev=144655&view=rev
Log:
Delete files.

Removed:
    llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.cpp
    llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.h

Removed: llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.cpp?rev=144654&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.cpp (removed)
@@ -1,70 +0,0 @@
-//===-- MipsMCSymbolRefExpr.cpp - Mips specific MC expression classes -----===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "mipsmcsymbolrefexpr"
-#include "MipsMCSymbolRefExpr.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCSymbol.h"
-using namespace llvm;
-
-const MipsMCSymbolRefExpr*
-MipsMCSymbolRefExpr::Create(VariantKind Kind, const MCSymbol *Symbol,
-                            int Offset, MCContext &Ctx) {
-  return new (Ctx) MipsMCSymbolRefExpr(Kind, Symbol, Offset);
-}
-
-void MipsMCSymbolRefExpr::PrintImpl(raw_ostream &OS) const {
-  switch (Kind) {
-  default: assert(0 && "Invalid kind!");
-  case VK_Mips_None:     break;
-  case VK_Mips_GPREL:    OS << "%gp_rel("; break;
-  case VK_Mips_GOT_CALL: OS << "%call16("; break;
-  case VK_Mips_GOT:      OS << "%got(";    break;
-  case VK_Mips_ABS_HI:   OS << "%hi(";     break;
-  case VK_Mips_ABS_LO:   OS << "%lo(";     break;
-  case VK_Mips_TLSGD:    OS << "%tlsgd(";  break;
-  case VK_Mips_GOTTPREL: OS << "%gottprel("; break;
-  case VK_Mips_TPREL_HI: OS << "%tprel_hi("; break;
-  case VK_Mips_TPREL_LO: OS << "%tprel_lo("; break;
-  case VK_Mips_GPOFF_HI: OS << "%hi(%neg(%gp_rel("; break;
-  case VK_Mips_GPOFF_LO: OS << "%lo(%neg(%gp_rel("; break;
-  case VK_Mips_GOT_DISP: OS << "%got_disp("; break;
-  case VK_Mips_GOT_PAGE: OS << "%got_page("; break;
-  case VK_Mips_GOT_OFST: OS << "%got_ofst("; break;
-  }
-
-  OS << *Symbol;
-
-  if (Offset) {
-    if (Offset > 0)
-      OS << '+';
-    OS << Offset;
-  }
-
-  if (Kind == VK_Mips_GPOFF_HI || Kind == VK_Mips_GPOFF_LO)
-    OS << ")))";
-  else if (Kind != VK_Mips_None)
-    OS << ')';
-}
-
-bool
-MipsMCSymbolRefExpr::EvaluateAsRelocatableImpl(MCValue &Res,
-                                              const MCAsmLayout *Layout) const {
-  return false;
-}
-
-void MipsMCSymbolRefExpr::AddValueSymbols(MCAssembler *Asm) const {
-  Asm->getOrCreateSymbolData(*Symbol);
-}
-
-const MCSection *MipsMCSymbolRefExpr::FindAssociatedSection() const {
-  return Symbol->isDefined() ? &Symbol->getSection() : NULL;
-}
-  

Removed: llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.h?rev=144654&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.h (removed)
@@ -1,67 +0,0 @@
-//===-- MipsMCSymbolRefExpr.h - Mips specific MCSymbolRefExpr class -------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef MIPSMCSYMBOLREFEXPR_H
-#define MIPSMCSYMBOLREFEXPR_H
-#include "llvm/MC/MCExpr.h"
-
-namespace llvm {
-
-class MipsMCSymbolRefExpr : public MCTargetExpr {
-public:
-  enum VariantKind {
-    VK_Mips_None,
-    VK_Mips_GPREL,
-    VK_Mips_GOT_CALL,
-    VK_Mips_GOT,
-    VK_Mips_ABS_HI,
-    VK_Mips_ABS_LO,
-    VK_Mips_TLSGD,
-    VK_Mips_GOTTPREL,
-    VK_Mips_TPREL_HI,
-    VK_Mips_TPREL_LO,
-    VK_Mips_GPOFF_HI,
-    VK_Mips_GPOFF_LO,
-    VK_Mips_GOT_DISP,
-    VK_Mips_GOT_PAGE,
-    VK_Mips_GOT_OFST
-  };
-
-private:
-  const VariantKind Kind;
-  const MCSymbol *Symbol;
-  int Offset;
-
-  explicit MipsMCSymbolRefExpr(VariantKind _Kind, const MCSymbol *_Symbol,
-                               int _Offset)
-    : Kind(_Kind), Symbol(_Symbol), Offset(_Offset) {}
-  
-public:
-  static const MipsMCSymbolRefExpr *Create(VariantKind Kind,
-                                           const MCSymbol *Symbol, int Offset,
-                                           MCContext &Ctx);
-
-  void PrintImpl(raw_ostream &OS) const;
-  bool EvaluateAsRelocatableImpl(MCValue &Res,
-                                 const MCAsmLayout *Layout) const;
-  void AddValueSymbols(MCAssembler *) const;
-  const MCSection *FindAssociatedSection() const;
-
-  static bool classof(const MCExpr *E) {
-    return E->getKind() == MCExpr::Target;
-  }
-
-  static bool classof(const MipsMCSymbolRefExpr *) { return true; }
-
-  int getOffset() const { return Offset; }
-  void setOffset(int O) { Offset = O; }
-};
-} // end namespace llvm
-
-#endif



From benny.kra at googlemail.com  Tue Nov 15 12:30:06 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 15 Nov 2011 18:30:06 -0000
Subject: [llvm-commits] [llvm] r144656 - in /llvm/trunk:
 include/llvm/Analysis/RegionInfo.h lib/Analysis/RegionInfo.cpp
Message-ID: <20111115183006.976C42A6C131@llvm.org>

Author: d0k
Date: Tue Nov 15 12:30:06 2011
New Revision: 144656

URL: http://llvm.org/viewvc/llvm-project?rev=144656&view=rev
Log:
Missed some users of Value::getNameStr.

Modified:
    llvm/trunk/include/llvm/Analysis/RegionInfo.h
    llvm/trunk/lib/Analysis/RegionInfo.cpp

Modified: llvm/trunk/include/llvm/Analysis/RegionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/RegionInfo.h?rev=144656&r1=144655&r2=144656&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/RegionInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/RegionInfo.h Tue Nov 15 12:30:06 2011
@@ -681,7 +681,7 @@
   if (Node.isSubRegion())
     return OS << Node.getNodeAs<Region>()->getNameStr();
   else
-    return OS << Node.getNodeAs<BasicBlock>()->getNameStr();
+    return OS << Node.getNodeAs<BasicBlock>()->getName();
 }
 } // End llvm namespace
 #endif

Modified: llvm/trunk/lib/Analysis/RegionInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/RegionInfo.cpp?rev=144656&r1=144655&r2=144656&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/RegionInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/RegionInfo.cpp Tue Nov 15 12:30:06 2011
@@ -186,18 +186,16 @@
     raw_string_ostream OS(entryName);
 
     WriteAsOperand(OS, getEntry(), false);
-    entryName = OS.str();
   } else
-    entryName = getEntry()->getNameStr();
+    entryName = getEntry()->getName();
 
   if (getExit()) {
     if (getExit()->getName().empty()) {
       raw_string_ostream OS(exitName);
 
       WriteAsOperand(OS, getExit(), false);
-      exitName = OS.str();
     } else
-      exitName = getExit()->getNameStr();
+      exitName = getExit()->getName();
   } else
     exitName = "<Function Return>";
 



From benny.kra at googlemail.com  Tue Nov 15 12:30:13 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 15 Nov 2011 18:30:13 -0000
Subject: [llvm-commits] [llvm] r144657 - in /llvm/trunk:
	include/llvm/Value.h lib/VMCore/Value.cpp
Message-ID: <20111115183013.1709E2A6C131@llvm.org>

Author: d0k
Date: Tue Nov 15 12:30:12 2011
New Revision: 144657

URL: http://llvm.org/viewvc/llvm-project?rev=144657&view=rev
Log:
Remove Value::getNameStr. It has been deprecated for a while and provides no additional value over getName().

Modified:
    llvm/trunk/include/llvm/Value.h
    llvm/trunk/lib/VMCore/Value.cpp

Modified: llvm/trunk/include/llvm/Value.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Value.h?rev=144657&r1=144656&r2=144657&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Value.h (original)
+++ llvm/trunk/include/llvm/Value.h Tue Nov 15 12:30:12 2011
@@ -117,19 +117,8 @@
   /// getName() - Return a constant reference to the value's name. This is cheap
   /// and guaranteed to return the same reference as long as the value is not
   /// modified.
-  ///
-  /// This is currently guaranteed to return a StringRef for which data() points
-  /// to a valid null terminated string. The use of StringRef.data() is 
-  /// deprecated here, however, and clients should not rely on it. If such 
-  /// behavior is needed, clients should use expensive getNameStr(), or switch 
-  /// to an interface that does not depend on null termination.
   StringRef getName() const;
 
-  /// getNameStr() - Return the name of the specified value, *constructing a
-  /// string* to hold it.  This is guaranteed to construct a string and is very
-  /// expensive, clients should use getName() unless necessary.
-  std::string getNameStr() const;
-
   /// setName() - Change the name of the value, choosing a new unique name if
   /// the provided name is taken.
   ///

Modified: llvm/trunk/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=144657&r1=144656&r2=144657&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Value.cpp (original)
+++ llvm/trunk/lib/VMCore/Value.cpp Tue Nov 15 12:30:12 2011
@@ -156,10 +156,6 @@
   return Name->getKey();
 }
 
-std::string Value::getNameStr() const {
-  return getName().str();
-}
-
 void Value::setName(const Twine &NewName) {
   // Fast path for common IRBuilder case of setName("") when there is no name.
   if (NewName.isTriviallyEmpty() && !hasName())



From daniel at zuster.org  Tue Nov 15 12:34:17 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 15 Nov 2011 18:34:17 -0000
Subject: [llvm-commits] [compiler-rt] r144658 - in
 /compiler-rt/trunk/make/platform: clang_darwin.mk darwin_fat.mk
 multi_arch.mk
Message-ID: <20111115183417.A61BF2A6C131@llvm.org>

Author: ddunbar
Date: Tue Nov 15 12:34:17 2011
New Revision: 144658

URL: http://llvm.org/viewvc/llvm-project?rev=144658&view=rev
Log:
build: Change default CC to be clang instead of gcc.

Modified:
    compiler-rt/trunk/make/platform/clang_darwin.mk
    compiler-rt/trunk/make/platform/darwin_fat.mk
    compiler-rt/trunk/make/platform/multi_arch.mk

Modified: compiler-rt/trunk/make/platform/clang_darwin.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=144658&r1=144657&r2=144658&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin.mk (original)
+++ compiler-rt/trunk/make/platform/clang_darwin.mk Tue Nov 15 12:34:17 2011
@@ -67,7 +67,7 @@
 
 ###
 
-CC := gcc
+CC := clang
 
 # Forcibly strip off any -arch, as that totally breaks our universal support.
 override CC := $(subst -arch ,-arch_,$(CC))

Modified: compiler-rt/trunk/make/platform/darwin_fat.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/darwin_fat.mk?rev=144658&r1=144657&r2=144658&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/darwin_fat.mk (original)
+++ compiler-rt/trunk/make/platform/darwin_fat.mk Tue Nov 15 12:34:17 2011
@@ -37,7 +37,7 @@
 #   <Option Name>.<Arch Name> := ...
 #   <Option Name>.<Config Name>.<Arch Name> := ...
 
-CC := gcc
+CC := clang
 
 CFLAGS := -Wall -Werror
 CFLAGS.Debug := $(CFLAGS) -g

Modified: compiler-rt/trunk/make/platform/multi_arch.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/multi_arch.mk?rev=144658&r1=144657&r2=144658&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/multi_arch.mk (original)
+++ compiler-rt/trunk/make/platform/multi_arch.mk Tue Nov 15 12:34:17 2011
@@ -5,8 +5,7 @@
 Arch := i386
 Arch.m64 := x86_64
 
-CC := gcc
-CC.m32 := clang
+CC := clang
 
 CFLAGS := -Wall -Werror
 CFLAGS.m32 := $(CFLAGS) -m32 -O3



From daniel at zuster.org  Tue Nov 15 12:34:23 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 15 Nov 2011 18:34:23 -0000
Subject: [llvm-commits] [compiler-rt] r144659 -
	/compiler-rt/trunk/make/platform/darwin_fat.mk
Message-ID: <20111115183423.19FBA2A6C131@llvm.org>

Author: ddunbar
Date: Tue Nov 15 12:34:22 2011
New Revision: 144659

URL: http://llvm.org/viewvc/llvm-project?rev=144659&view=rev
Log:
build/darwin_fat: Drop ppc from default arch list, ppc targets are no longer supported by modern toolchains.

Modified:
    compiler-rt/trunk/make/platform/darwin_fat.mk

Modified: compiler-rt/trunk/make/platform/darwin_fat.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/darwin_fat.mk?rev=144659&r1=144658&r2=144659&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/darwin_fat.mk (original)
+++ compiler-rt/trunk/make/platform/darwin_fat.mk Tue Nov 15 12:34:22 2011
@@ -24,7 +24,7 @@
 Description := Target for building universal libraries for Darwin.
 
 Configs := Debug Release Profile
-UniversalArchs := i386 ppc x86_64
+UniversalArchs := i386 x86_64
 
 # Platform Options
 #



From daniel at zuster.org  Tue Nov 15 12:34:44 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 15 Nov 2011 18:34:44 -0000
Subject: [llvm-commits] [compiler-rt] r144660 - /compiler-rt/trunk/lib/
Message-ID: <20111115183445.9A4AB2A6C131@llvm.org>

Author: ddunbar
Date: Tue Nov 15 12:34:44 2011
New Revision: 144660

URL: http://llvm.org/viewvc/llvm-project?rev=144660&view=rev
Log:
lib: Integrate abi.h into int_lib.h, there aren't good enough reasons for this extra complexity.

Removed:
    compiler-rt/trunk/lib/abi.h
Modified:
    compiler-rt/trunk/lib/absvdi2.c
    compiler-rt/trunk/lib/absvsi2.c
    compiler-rt/trunk/lib/adddf3.c
    compiler-rt/trunk/lib/addsf3.c
    compiler-rt/trunk/lib/addvdi3.c
    compiler-rt/trunk/lib/addvsi3.c
    compiler-rt/trunk/lib/ashldi3.c
    compiler-rt/trunk/lib/ashrdi3.c
    compiler-rt/trunk/lib/clzdi2.c
    compiler-rt/trunk/lib/clzsi2.c
    compiler-rt/trunk/lib/cmpdi2.c
    compiler-rt/trunk/lib/ctzdi2.c
    compiler-rt/trunk/lib/ctzsi2.c
    compiler-rt/trunk/lib/divdf3.c
    compiler-rt/trunk/lib/divdi3.c
    compiler-rt/trunk/lib/divmoddi4.c
    compiler-rt/trunk/lib/divmodsi4.c
    compiler-rt/trunk/lib/divsf3.c
    compiler-rt/trunk/lib/divsi3.c
    compiler-rt/trunk/lib/extendsfdf2.c
    compiler-rt/trunk/lib/ffsdi2.c
    compiler-rt/trunk/lib/fixdfdi.c
    compiler-rt/trunk/lib/fixdfsi.c
    compiler-rt/trunk/lib/fixsfdi.c
    compiler-rt/trunk/lib/fixsfsi.c
    compiler-rt/trunk/lib/fixunsdfdi.c
    compiler-rt/trunk/lib/fixunsdfsi.c
    compiler-rt/trunk/lib/fixunssfdi.c
    compiler-rt/trunk/lib/fixunssfsi.c
    compiler-rt/trunk/lib/floatdidf.c
    compiler-rt/trunk/lib/floatdisf.c
    compiler-rt/trunk/lib/floatsidf.c
    compiler-rt/trunk/lib/floatsisf.c
    compiler-rt/trunk/lib/floatundidf.c
    compiler-rt/trunk/lib/floatundisf.c
    compiler-rt/trunk/lib/floatunsidf.c
    compiler-rt/trunk/lib/floatunsisf.c
    compiler-rt/trunk/lib/fp_lib.h
    compiler-rt/trunk/lib/int_lib.h
    compiler-rt/trunk/lib/lshrdi3.c
    compiler-rt/trunk/lib/moddi3.c
    compiler-rt/trunk/lib/modsi3.c
    compiler-rt/trunk/lib/muldf3.c
    compiler-rt/trunk/lib/muldi3.c
    compiler-rt/trunk/lib/mulsf3.c
    compiler-rt/trunk/lib/negdf2.c
    compiler-rt/trunk/lib/negsf2.c
    compiler-rt/trunk/lib/negvdi2.c
    compiler-rt/trunk/lib/negvsi2.c
    compiler-rt/trunk/lib/paritydi2.c
    compiler-rt/trunk/lib/paritysi2.c
    compiler-rt/trunk/lib/popcountdi2.c
    compiler-rt/trunk/lib/popcountsi2.c
    compiler-rt/trunk/lib/powidf2.c
    compiler-rt/trunk/lib/powisf2.c
    compiler-rt/trunk/lib/subdf3.c
    compiler-rt/trunk/lib/subsf3.c
    compiler-rt/trunk/lib/subvdi3.c
    compiler-rt/trunk/lib/subvsi3.c
    compiler-rt/trunk/lib/truncdfsf2.c
    compiler-rt/trunk/lib/ucmpdi2.c
    compiler-rt/trunk/lib/udivdi3.c
    compiler-rt/trunk/lib/udivmoddi4.c
    compiler-rt/trunk/lib/udivmodsi4.c
    compiler-rt/trunk/lib/udivsi3.c
    compiler-rt/trunk/lib/umoddi3.c
    compiler-rt/trunk/lib/umodsi3.c

Removed: compiler-rt/trunk/lib/abi.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/abi.h?rev=144659&view=auto
==============================================================================
--- compiler-rt/trunk/lib/abi.h (original)
+++ compiler-rt/trunk/lib/abi.h (removed)
@@ -1,23 +0,0 @@
-/* ===------ abi.h - configuration header for compiler-rt  -----------------===
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- * ===----------------------------------------------------------------------===
- *
- * This file is a configuration header for compiler-rt.
- * This file is not part of the interface of this library.
- *
- * ===----------------------------------------------------------------------===
- */
-
-#if __ARM_EABI__
-# define ARM_EABI_FNALIAS(aeabi_name, name)         \
-  void __aeabi_##aeabi_name() __attribute__((alias("__" #name)));
-# define COMPILER_RT_ABI __attribute__((pcs("aapcs")))
-#else
-# define ARM_EABI_FNALIAS(aeabi_name, name)
-# define COMPILER_RT_ABI
-#endif

Modified: compiler-rt/trunk/lib/absvdi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/absvdi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/absvdi2.c (original)
+++ compiler-rt/trunk/lib/absvdi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  *===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 #include <stdlib.h>

Modified: compiler-rt/trunk/lib/absvsi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/absvsi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/absvsi2.c (original)
+++ compiler-rt/trunk/lib/absvsi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 #include <stdlib.h>

Modified: compiler-rt/trunk/lib/adddf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/adddf3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/adddf3.c (original)
+++ compiler-rt/trunk/lib/adddf3.c Tue Nov 15 12:34:44 2011
@@ -12,8 +12,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "abi.h"
-
 #define DOUBLE_PRECISION
 #include "fp_lib.h"
 

Modified: compiler-rt/trunk/lib/addsf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/addsf3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/addsf3.c (original)
+++ compiler-rt/trunk/lib/addsf3.c Tue Nov 15 12:34:44 2011
@@ -12,8 +12,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "abi.h"
-
 #define SINGLE_PRECISION
 #include "fp_lib.h"
 

Modified: compiler-rt/trunk/lib/addvdi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/addvdi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/addvdi3.c (original)
+++ compiler-rt/trunk/lib/addvdi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 #include <stdlib.h>

Modified: compiler-rt/trunk/lib/addvsi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/addvsi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/addvsi3.c (original)
+++ compiler-rt/trunk/lib/addvsi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 #include <stdlib.h>

Modified: compiler-rt/trunk/lib/ashldi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ashldi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ashldi3.c (original)
+++ compiler-rt/trunk/lib/ashldi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/ashrdi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ashrdi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ashrdi3.c (original)
+++ compiler-rt/trunk/lib/ashrdi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/clzdi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/clzdi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/clzdi2.c (original)
+++ compiler-rt/trunk/lib/clzdi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/clzsi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/clzsi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/clzsi2.c (original)
+++ compiler-rt/trunk/lib/clzsi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/cmpdi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/cmpdi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/cmpdi2.c (original)
+++ compiler-rt/trunk/lib/cmpdi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/ctzdi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ctzdi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ctzdi2.c (original)
+++ compiler-rt/trunk/lib/ctzdi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/ctzsi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ctzsi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ctzsi2.c (original)
+++ compiler-rt/trunk/lib/ctzsi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/divdf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divdf3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divdf3.c (original)
+++ compiler-rt/trunk/lib/divdf3.c Tue Nov 15 12:34:44 2011
@@ -15,7 +15,6 @@
 // underflow with correct rounding.
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define DOUBLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/divdi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divdi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divdi3.c (original)
+++ compiler-rt/trunk/lib/divdi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/divmoddi4.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divmoddi4.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divmoddi4.c (original)
+++ compiler-rt/trunk/lib/divmoddi4.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/divmodsi4.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divmodsi4.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divmodsi4.c (original)
+++ compiler-rt/trunk/lib/divmodsi4.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/divsf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divsf3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divsf3.c (original)
+++ compiler-rt/trunk/lib/divsf3.c Tue Nov 15 12:34:44 2011
@@ -15,7 +15,6 @@
 // underflow with correct rounding.
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define SINGLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/divsi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divsi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divsi3.c (original)
+++ compiler-rt/trunk/lib/divsi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/extendsfdf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/extendsfdf2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/extendsfdf2.c (original)
+++ compiler-rt/trunk/lib/extendsfdf2.c Tue Nov 15 12:34:44 2011
@@ -41,7 +41,7 @@
 #include <stdint.h>
 #include <limits.h>
 
-#include "abi.h"
+#include "int_lib.h"
 
 typedef float src_t;
 typedef uint32_t src_rep_t;

Modified: compiler-rt/trunk/lib/ffsdi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ffsdi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ffsdi2.c (original)
+++ compiler-rt/trunk/lib/ffsdi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/fixdfdi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fixdfdi.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/fixdfdi.c (original)
+++ compiler-rt/trunk/lib/fixdfdi.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/fixdfsi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fixdfsi.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/fixdfsi.c (original)
+++ compiler-rt/trunk/lib/fixdfsi.c Tue Nov 15 12:34:44 2011
@@ -12,7 +12,6 @@
 // conversion is undefined for out of range values in the C standard.
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define DOUBLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/fixsfdi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fixsfdi.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/fixsfdi.c (original)
+++ compiler-rt/trunk/lib/fixsfdi.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/fixsfsi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fixsfsi.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/fixsfsi.c (original)
+++ compiler-rt/trunk/lib/fixsfsi.c Tue Nov 15 12:34:44 2011
@@ -12,7 +12,6 @@
 // conversion is undefined for out of range values in the C standard.
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define SINGLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/fixunsdfdi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fixunsdfdi.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/fixunsdfdi.c (original)
+++ compiler-rt/trunk/lib/fixunsdfdi.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/fixunsdfsi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fixunsdfsi.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/fixunsdfsi.c (original)
+++ compiler-rt/trunk/lib/fixunsdfsi.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/fixunssfdi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fixunssfdi.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/fixunssfdi.c (original)
+++ compiler-rt/trunk/lib/fixunssfdi.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 /* Returns: convert a to a unsigned long long, rounding toward zero.

Modified: compiler-rt/trunk/lib/fixunssfsi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fixunssfsi.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/fixunssfsi.c (original)
+++ compiler-rt/trunk/lib/fixunssfsi.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/floatdidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatdidf.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatdidf.c (original)
+++ compiler-rt/trunk/lib/floatdidf.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  *===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 #include <float.h>

Modified: compiler-rt/trunk/lib/floatdisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatdisf.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatdisf.c (original)
+++ compiler-rt/trunk/lib/floatdisf.c Tue Nov 15 12:34:44 2011
@@ -12,7 +12,6 @@
  *===----------------------------------------------------------------------===
  */
 
-#include "abi.h"
 #include <float.h>
 
 /* Returns: convert a to a float, rounding toward even.*/

Modified: compiler-rt/trunk/lib/floatsidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatsidf.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatsidf.c (original)
+++ compiler-rt/trunk/lib/floatsidf.c Tue Nov 15 12:34:44 2011
@@ -12,7 +12,6 @@
 // mode.
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define DOUBLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/floatsisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatsisf.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatsisf.c (original)
+++ compiler-rt/trunk/lib/floatsisf.c Tue Nov 15 12:34:44 2011
@@ -12,7 +12,6 @@
 // mode.
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define SINGLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/floatundidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatundidf.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatundidf.c (original)
+++ compiler-rt/trunk/lib/floatundidf.c Tue Nov 15 12:34:44 2011
@@ -12,7 +12,6 @@
  * ===----------------------------------------------------------------------===
  */
 
-#include "abi.h"
 #include <float.h>
 
 /* Returns: convert a to a double, rounding toward even. */

Modified: compiler-rt/trunk/lib/floatundisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatundisf.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatundisf.c (original)
+++ compiler-rt/trunk/lib/floatundisf.c Tue Nov 15 12:34:44 2011
@@ -12,7 +12,6 @@
  *===----------------------------------------------------------------------===
  */
 
-#include "abi.h"
 #include <float.h>
 
 /* Returns: convert a to a float, rounding toward even. */

Modified: compiler-rt/trunk/lib/floatunsidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatunsidf.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatunsidf.c (original)
+++ compiler-rt/trunk/lib/floatunsidf.c Tue Nov 15 12:34:44 2011
@@ -12,7 +12,6 @@
 // mode.
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define DOUBLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/floatunsisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatunsisf.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatunsisf.c (original)
+++ compiler-rt/trunk/lib/floatunsisf.c Tue Nov 15 12:34:44 2011
@@ -12,7 +12,6 @@
 // mode.
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define SINGLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/fp_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fp_lib.h?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/fp_lib.h (original)
+++ compiler-rt/trunk/lib/fp_lib.h Tue Nov 15 12:34:44 2011
@@ -24,6 +24,7 @@
 #include <stdint.h>
 #include <stdbool.h>
 #include <limits.h>
+#include "int_lib.h"
 
 #if defined SINGLE_PRECISION
 

Modified: compiler-rt/trunk/lib/int_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_lib.h?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_lib.h (original)
+++ compiler-rt/trunk/lib/int_lib.h Tue Nov 15 12:34:44 2011
@@ -16,6 +16,17 @@
 #ifndef INT_LIB_H
 #define INT_LIB_H
 
+/* ABI macro definitions */
+
+#if __ARM_EABI__
+# define ARM_EABI_FNALIAS(aeabi_name, name)         \
+  void __aeabi_##aeabi_name() __attribute__((alias("__" #name)));
+# define COMPILER_RT_ABI __attribute__((pcs("aapcs")))
+#else
+# define ARM_EABI_FNALIAS(aeabi_name, name)
+# define COMPILER_RT_ABI
+#endif
+
 /* Assumption:  signed integral is 2's complement */
 /* Assumption:  right shift of signed negative is arithmetic shift */
 

Modified: compiler-rt/trunk/lib/lshrdi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/lshrdi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/lshrdi3.c (original)
+++ compiler-rt/trunk/lib/lshrdi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/moddi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/moddi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/moddi3.c (original)
+++ compiler-rt/trunk/lib/moddi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/modsi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/modsi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/modsi3.c (original)
+++ compiler-rt/trunk/lib/modsi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/muldf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/muldf3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/muldf3.c (original)
+++ compiler-rt/trunk/lib/muldf3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
 // with the IEEE-754 default rounding (to nearest, ties to even).
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define DOUBLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/muldi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/muldi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/muldi3.c (original)
+++ compiler-rt/trunk/lib/muldi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/mulsf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulsf3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulsf3.c (original)
+++ compiler-rt/trunk/lib/mulsf3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
 // with the IEEE-754 default rounding (to nearest, ties to even).
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define SINGLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/negdf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negdf2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/negdf2.c (original)
+++ compiler-rt/trunk/lib/negdf2.c Tue Nov 15 12:34:44 2011
@@ -10,7 +10,6 @@
 // This file implements double-precision soft-float negation.
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define DOUBLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/negsf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negsf2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/negsf2.c (original)
+++ compiler-rt/trunk/lib/negsf2.c Tue Nov 15 12:34:44 2011
@@ -10,7 +10,6 @@
 // This file implements single-precision soft-float negation.
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define SINGLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/negvdi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negvdi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/negvdi2.c (original)
+++ compiler-rt/trunk/lib/negvdi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 #include <stdlib.h>

Modified: compiler-rt/trunk/lib/negvsi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negvsi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/negvsi2.c (original)
+++ compiler-rt/trunk/lib/negvsi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 #include <stdlib.h>

Modified: compiler-rt/trunk/lib/paritydi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/paritydi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/paritydi2.c (original)
+++ compiler-rt/trunk/lib/paritydi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/paritysi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/paritysi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/paritysi2.c (original)
+++ compiler-rt/trunk/lib/paritysi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/popcountdi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/popcountdi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/popcountdi2.c (original)
+++ compiler-rt/trunk/lib/popcountdi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/popcountsi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/popcountsi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/popcountsi2.c (original)
+++ compiler-rt/trunk/lib/popcountsi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/powidf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/powidf2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/powidf2.c (original)
+++ compiler-rt/trunk/lib/powidf2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/powisf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/powisf2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/powisf2.c (original)
+++ compiler-rt/trunk/lib/powisf2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/subdf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/subdf3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/subdf3.c (original)
+++ compiler-rt/trunk/lib/subdf3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
 // IEEE-754 default rounding (to nearest, ties to even).
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define DOUBLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/subsf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/subsf3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/subsf3.c (original)
+++ compiler-rt/trunk/lib/subsf3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
 // IEEE-754 default rounding (to nearest, ties to even).
 //
 //===----------------------------------------------------------------------===//
-#include "abi.h"
 
 #define SINGLE_PRECISION
 #include "fp_lib.h"

Modified: compiler-rt/trunk/lib/subvdi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/subvdi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/subvdi3.c (original)
+++ compiler-rt/trunk/lib/subvdi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 #include <stdlib.h>

Modified: compiler-rt/trunk/lib/subvsi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/subvsi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/subvsi3.c (original)
+++ compiler-rt/trunk/lib/subvsi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 #include <stdlib.h>

Modified: compiler-rt/trunk/lib/truncdfsf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/truncdfsf2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/truncdfsf2.c (original)
+++ compiler-rt/trunk/lib/truncdfsf2.c Tue Nov 15 12:34:44 2011
@@ -41,7 +41,7 @@
 #include <limits.h>
 #include <stdbool.h>
 
-#include "abi.h"
+#include "int_lib.h"
 
 typedef double src_t;
 typedef uint64_t src_rep_t;

Modified: compiler-rt/trunk/lib/ucmpdi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ucmpdi2.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ucmpdi2.c (original)
+++ compiler-rt/trunk/lib/ucmpdi2.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/udivdi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/udivdi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/udivdi3.c (original)
+++ compiler-rt/trunk/lib/udivdi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/udivmoddi4.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/udivmoddi4.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/udivmoddi4.c (original)
+++ compiler-rt/trunk/lib/udivmoddi4.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/udivmodsi4.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/udivmodsi4.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/udivmodsi4.c (original)
+++ compiler-rt/trunk/lib/udivmodsi4.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/udivsi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/udivsi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/udivsi3.c (original)
+++ compiler-rt/trunk/lib/udivsi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/umoddi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/umoddi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/umoddi3.c (original)
+++ compiler-rt/trunk/lib/umoddi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/umodsi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/umodsi3.c?rev=144660&r1=144659&r2=144660&view=diff
==============================================================================
--- compiler-rt/trunk/lib/umodsi3.c (original)
+++ compiler-rt/trunk/lib/umodsi3.c Tue Nov 15 12:34:44 2011
@@ -11,7 +11,6 @@
  *
  * ===----------------------------------------------------------------------===
  */
-#include "abi.h"
 
 #include "int_lib.h"
 



From daniel at zuster.org  Tue Nov 15 12:34:57 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 15 Nov 2011 18:34:57 -0000
Subject: [llvm-commits] [compiler-rt] r144662 - /compiler-rt/trunk/.gitignore
Message-ID: <20111115183457.7B2402A6C132@llvm.org>

Author: ddunbar
Date: Tue Nov 15 12:34:57 2011
New Revision: 144662

URL: http://llvm.org/viewvc/llvm-project?rev=144662&view=rev
Log:
git: Tweak .gitignore to ignore defined platform build directories.
 - We should probably sink the platform build dirs into a common top-level dir.

Modified:
    compiler-rt/trunk/.gitignore

Modified: compiler-rt/trunk/.gitignore
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/.gitignore?rev=144662&r1=144661&r2=144662&view=diff
==============================================================================
--- compiler-rt/trunk/.gitignore (original)
+++ compiler-rt/trunk/.gitignore Tue Nov 15 12:34:57 2011
@@ -1,4 +1,4 @@
 *~
-Debug
-Release
-Profile
+darwin_fat
+clang_darwin
+multi_arch



From daniel at zuster.org  Tue Nov 15 12:34:53 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 15 Nov 2011 18:34:53 -0000
Subject: [llvm-commits] [compiler-rt] r144661 -
	/compiler-rt/trunk/make/platform/clang_darwin.mk
Message-ID: <20111115183453.8E9D32A6C131@llvm.org>

Author: ddunbar
Date: Tue Nov 15 12:34:53 2011
New Revision: 144661

URL: http://llvm.org/viewvc/llvm-project?rev=144661&view=rev
Log:
build/clang_darwin: Set CC before trying to run CheckArches.

Modified:
    compiler-rt/trunk/make/platform/clang_darwin.mk

Modified: compiler-rt/trunk/make/platform/clang_darwin.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=144661&r1=144660&r2=144661&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin.mk (original)
+++ compiler-rt/trunk/make/platform/clang_darwin.mk Tue Nov 15 12:34:53 2011
@@ -22,6 +22,8 @@
 
 ###
 
+CC := clang
+
 Configs :=
 UniversalArchs :=
 
@@ -67,8 +69,6 @@
 
 ###
 
-CC := clang
-
 # Forcibly strip off any -arch, as that totally breaks our universal support.
 override CC := $(subst -arch ,-arch_,$(CC))
 override CC := $(patsubst -arch_%,,$(CC))



From ahatanaka at mips.com  Tue Nov 15 12:38:36 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Tue, 15 Nov 2011 18:38:36 -0000
Subject: [llvm-commits] [llvm] r144663 - /llvm/trunk/lib/MC/MCExpr.cpp
Message-ID: <20111115183836.0A5E52A6C131@llvm.org>

Author: ahatanak
Date: Tue Nov 15 12:38:35 2011
New Revision: 144663

URL: http://llvm.org/viewvc/llvm-project?rev=144663&view=rev
Log:
Remove function printMipsSymbolRef.


Modified:
    llvm/trunk/lib/MC/MCExpr.cpp

Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=144663&r1=144662&r2=144663&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Tue Nov 15 12:38:35 2011
@@ -26,38 +26,6 @@
 }
 }
 
-static bool printMipsSymbolRef(const MCSymbolRefExpr &SRE,
-                               const MCSymbol &Sym, raw_ostream &OS) {
-  MCSymbolRefExpr::VariantKind Kind= SRE.getKind();
-
-  switch (Kind) {
-  default:
-    return false;
-  case MCSymbolRefExpr::VK_Mips_None:     break;
-  case MCSymbolRefExpr::VK_Mips_GPREL:    OS << "%gp_rel("; break;
-  case MCSymbolRefExpr::VK_Mips_GOT_CALL: OS << "%call16("; break;
-  case MCSymbolRefExpr::VK_Mips_GOT:      OS << "%got(";    break;
-  case MCSymbolRefExpr::VK_Mips_ABS_HI:   OS << "%hi(";     break;
-  case MCSymbolRefExpr::VK_Mips_ABS_LO:   OS << "%lo(";     break;
-  case MCSymbolRefExpr::VK_Mips_TLSGD:    OS << "%tlsgd(";  break;
-  case MCSymbolRefExpr::VK_Mips_GOTTPREL: OS << "%gottprel("; break;
-  case MCSymbolRefExpr::VK_Mips_TPREL_HI: OS << "%tprel_hi("; break;
-  case MCSymbolRefExpr::VK_Mips_TPREL_LO: OS << "%tprel_lo("; break;
-  case MCSymbolRefExpr::VK_Mips_GPOFF_HI: OS << "%hi(%neg(%gp_rel("; break;
-  case MCSymbolRefExpr::VK_Mips_GPOFF_LO: OS << "%lo(%neg(%gp_rel("; break;
-  case MCSymbolRefExpr::VK_Mips_GOT_DISP: OS << "%got_disp("; break;
-  case MCSymbolRefExpr::VK_Mips_GOT_PAGE: OS << "%got_page("; break;
-  case MCSymbolRefExpr::VK_Mips_GOT_OFST: OS << "%got_ofst("; break;
-  }
-
-  OS << Sym;
-
-  if (Kind != MCSymbolRefExpr::VK_Mips_None)
-    OS << ')';
-
-  return true;
-}
-
 void MCExpr::print(raw_ostream &OS) const {
   switch (getKind()) {
   case MCExpr::Target:
@@ -73,9 +41,6 @@
     // absolute names.
     bool UseParens = Sym.getName()[0] == '$';
 
-    if (printMipsSymbolRef(SRE, Sym, OS))
-      return;
-
     if (SRE.getKind() == MCSymbolRefExpr::VK_PPC_DARWIN_HA16 ||
         SRE.getKind() == MCSymbolRefExpr::VK_PPC_DARWIN_LO16) {
       OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind());



From ahatanaka at mips.com  Tue Nov 15 12:42:25 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Tue, 15 Nov 2011 18:42:25 -0000
Subject: [llvm-commits] [llvm] r144664 -
	/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
Message-ID: <20111115184225.999C62A6C131@llvm.org>

Author: ahatanak
Date: Tue Nov 15 12:42:25 2011
New Revision: 144664

URL: http://llvm.org/viewvc/llvm-project?rev=144664&view=rev
Log:
Simplify function PassByValArg64.

Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=144664&r1=144663&r2=144664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Nov 15 12:42:25 2011
@@ -2063,6 +2063,7 @@
   bool IsRegLoc = VA.isRegLoc();
   unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
   unsigned LocMemOffset = 0;
+  unsigned MemCpySize = ByValSize;
 
   if (!IsRegLoc)
     LocMemOffset = VA.getLocMemOffset();
@@ -2082,9 +2083,13 @@
       RegsToPass.push_back(std::make_pair(*Reg, LoadVal));
     }
 
+    // Return if the struct has been fully copied. 
+    if (!(MemCpySize = ByValSize - Offset))
+      return;
+
     // If there is an argument register available, copy the remainder of the
     // byval argument with sub-doubleword loads and shifts.
-    if ((Reg != RegEnd) && (ByValSize != Offset)) {
+    if (Reg != RegEnd) {
       assert((ByValSize < Offset + 8) &&
              "Size of the remainder should be smaller than 8-byte.");
       SDValue Val;
@@ -2119,19 +2124,18 @@
     }
   }
 
-  unsigned MemCpySize = ByValSize - Offset;
-  if (MemCpySize) {
-    // Create a fixed object on stack at offset LocMemOffset and copy
-    // remainder of byval arg to it with memcpy.
-    SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
-                              DAG.getConstant(Offset, PtrTy));
-    LastFI = MFI->CreateFixedObject(MemCpySize, LocMemOffset, true);
-    SDValue Dst = DAG.getFrameIndex(LastFI, PtrTy);
-    ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
-                               DAG.getConstant(MemCpySize, PtrTy), Alignment,
-                               /*isVolatile=*/false, /*AlwaysInline=*/false,
-                               MachinePointerInfo(0), MachinePointerInfo(0));
-  }
+  assert(MemCpySize && "MemCpySize must not be zero.");
+
+  // Create a fixed object on stack at offset LocMemOffset and copy
+  // remainder of byval arg to it with memcpy.
+  SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
+                            DAG.getConstant(Offset, PtrTy));
+  LastFI = MFI->CreateFixedObject(MemCpySize, LocMemOffset, true);
+  SDValue Dst = DAG.getFrameIndex(LastFI, PtrTy);
+  ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
+                             DAG.getConstant(MemCpySize, PtrTy), Alignment,
+                             /*isVolatile=*/false, /*AlwaysInline=*/false,
+                             MachinePointerInfo(0), MachinePointerInfo(0));
 }
 
 /// LowerCall - functions arguments are copied from virtual regs to



From ahatanaka at mips.com  Tue Nov 15 12:44:44 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Tue, 15 Nov 2011 18:44:44 -0000
Subject: [llvm-commits] [llvm] r144665 -
	/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
Message-ID: <20111115184444.BEBBC2A6C131@llvm.org>

Author: ahatanak
Date: Tue Nov 15 12:44:44 2011
New Revision: 144665

URL: http://llvm.org/viewvc/llvm-project?rev=144665&view=rev
Log:
Set nomacro before emitting the sequence of instructions that set global pointer
register.

Modified:
    llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?rev=144665&r1=144664&r2=144665&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Tue Nov 15 12:44:44 2011
@@ -169,13 +169,14 @@
   MFI->setStackSize(StackSize); 
   
   BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
 
   // Emit instructions that set $gp using the the value of $t9.
   // O32 uses the directive .cpload while N32/64 requires three instructions to
   // do this.  
   // TODO: Do not emit these instructions if no instructions use $gp.
   if (isPIC && STI.isABI_O32())
-    BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD))
+    BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::CPLOAD))
       .addReg(RegInfo->getPICCallReg());
   else if (STI.isABI_N64() || (isPIC && STI.isABI_N32())) {
     //  lui     $28,%hi(%neg(%gp_rel(fname)))
@@ -189,8 +190,6 @@
       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
   }
 
-  BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
-
   // No need to allocate space on the stack.
   if (StackSize == 0 && !MFI->adjustsStack()) return;
 



From ahatanaka at mips.com  Tue Nov 15 12:53:55 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Tue, 15 Nov 2011 18:53:55 -0000
Subject: [llvm-commits] [llvm] r144666 - in /llvm/trunk/lib/Target/Mips:
 MipsFrameLowering.cpp MipsRegisterInfo.cpp
Message-ID: <20111115185355.4B5242A6C131@llvm.org>

Author: ahatanak
Date: Tue Nov 15 12:53:55 2011
New Revision: 144666

URL: http://llvm.org/viewvc/llvm-project?rev=144666&view=rev
Log:
Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit
registers and instructions when ABI is N64.

Modified:
    llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?rev=144666&r1=144665&r2=144666&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Tue Nov 15 12:53:55 2011
@@ -152,6 +152,9 @@
   bool ATUsed;
   unsigned GP = STI.isABI_N64() ? Mips::GP_64 : Mips::GP;
   unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
+  unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
+  unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
+  unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
   unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
   unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
   unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
@@ -198,10 +201,8 @@
   MachineLocation DstML, SrcML;
 
   // Adjust stack : addi sp, sp, (-imm)
-  ATUsed = expandRegLargeImmPair(Mips::SP, -StackSize, NewReg, NewImm, MBB,
-                                 MBBI);
-  BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
-    .addReg(NewReg).addImm(NewImm);
+  ATUsed = expandRegLargeImmPair(SP, -StackSize, NewReg, NewImm, MBB, MBBI);
+  BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(NewReg).addImm(NewImm);
 
   // FIXME: change this when mips goes MC".
   if (ATUsed)
@@ -261,14 +262,13 @@
   // if framepointer enabled, set it to point to the stack pointer.
   if (hasFP(MF)) {
     // Insert instruction "move $fp, $sp" at this location.    
-    BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
-      .addReg(Mips::SP).addReg(Mips::ZERO);
+    BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
 
     // emit ".cfi_def_cfa_register $fp" 
     MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
     BuildMI(MBB, MBBI, dl,
             TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
-    DstML = MachineLocation(Mips::FP);
+    DstML = MachineLocation(FP);
     SrcML = MachineLocation(MachineLocation::VirtualFP);
     Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML));
   }
@@ -292,6 +292,11 @@
   const MipsInstrInfo &TII =
     *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
   DebugLoc dl = MBBI->getDebugLoc();
+  unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
+  unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
+  unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
+  unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
+  unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
 
   // Get the number of bytes from FrameInfo
   unsigned StackSize = MFI->getStackSize();
@@ -309,16 +314,13 @@
       --I;
 
     // Insert instruction "move $sp, $fp" at this location.
-    BuildMI(MBB, I, dl, TII.get(Mips::ADDu), Mips::SP)
-      .addReg(Mips::FP).addReg(Mips::ZERO);
+    BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
   }
 
   // adjust stack  : insert addi sp, sp, (imm)
   if (StackSize) {
-    ATUsed = expandRegLargeImmPair(Mips::SP, StackSize, NewReg, NewImm, MBB,
-                                   MBBI);
-    BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
-      .addReg(NewReg).addImm(NewImm);
+    ATUsed = expandRegLargeImmPair(SP, StackSize, NewReg, NewImm, MBB, MBBI);
+    BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(NewReg).addImm(NewImm);
 
     // FIXME: change this when mips goes MC".
     if (ATUsed)
@@ -330,13 +332,15 @@
 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
                                      RegScavenger *RS) const {
   MachineRegisterInfo& MRI = MF.getRegInfo();
+  unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
+  unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
 
   // FIXME: remove this code if register allocator can correctly mark
   //        $fp and $ra used or unused.
 
   // Mark $fp and $ra as used or unused.
   if (hasFP(MF))
-    MRI.setPhysRegUsed(Mips::FP);
+    MRI.setPhysRegUsed(FP);
 
   // The register allocator might determine $ra is used after seeing 
   // instruction "jr $ra", but we do not want PrologEpilogInserter to insert
@@ -344,7 +348,7 @@
   // To correct this, $ra is explicitly marked unused if there is no
   // function call.
   if (MF.getFrameInfo()->hasCalls())
-    MRI.setPhysRegUsed(Mips::RA);
+    MRI.setPhysRegUsed(RA);
   else
-    MRI.setPhysRegUnused(Mips::RA);
+    MRI.setPhysRegUnused(RA);
 }

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=144666&r1=144665&r2=144666&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Tue Nov 15 12:53:55 2011
@@ -285,7 +285,7 @@
 
   if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
       (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
-    FrameReg = Mips::SP;
+    FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
   else
     FrameReg = getFrameRegister(MF); 
   
@@ -334,8 +334,10 @@
 unsigned MipsRegisterInfo::
 getFrameRegister(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
+  bool IsN64 = Subtarget.isABI_N64();
 
-  return TFI->hasFP(MF) ? Mips::FP : Mips::SP;
+  return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
+                          (IsN64 ? Mips::SP_64 : Mips::SP);
 }
 
 unsigned MipsRegisterInfo::



From daniel at zuster.org  Tue Nov 15 12:56:13 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 15 Nov 2011 18:56:13 -0000
Subject: [llvm-commits] [compiler-rt] r144668 - in /compiler-rt/trunk/lib:
	int_lib.h int_types.h
Message-ID: <20111115185613.62F232A6C131@llvm.org>

Author: ddunbar
Date: Tue Nov 15 12:56:13 2011
New Revision: 144668

URL: http://llvm.org/viewvc/llvm-project?rev=144668&view=rev
Log:
lib: Split out int_types.h, for readability.

Added:
    compiler-rt/trunk/lib/int_types.h
      - copied, changed from r144662, compiler-rt/trunk/lib/int_lib.h
Modified:
    compiler-rt/trunk/lib/int_lib.h

Modified: compiler-rt/trunk/lib/int_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_lib.h?rev=144668&r1=144667&r2=144668&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_lib.h (original)
+++ compiler-rt/trunk/lib/int_lib.h Tue Nov 15 12:56:13 2011
@@ -48,120 +48,7 @@
 #define INFINITY HUGE_VAL
 #endif /* INFINITY */
 
-typedef      int si_int;
-typedef unsigned su_int;
-
-typedef          long long di_int;
-typedef unsigned long long du_int;
-
-typedef union
-{
-    di_int all;
-    struct
-    {
-#if _YUGA_LITTLE_ENDIAN
-        su_int low;
-        si_int high;
-#else
-        si_int high;
-        su_int low;
-#endif /* _YUGA_LITTLE_ENDIAN */
-    }s;
-} dwords;
-
-typedef union
-{
-    du_int all;
-    struct
-    {
-#if _YUGA_LITTLE_ENDIAN
-        su_int low;
-        su_int high;
-#else
-        su_int high;
-        su_int low;
-#endif /* _YUGA_LITTLE_ENDIAN */
-    }s;
-} udwords;
-
-#if __x86_64
-
-typedef int      ti_int __attribute__ ((mode (TI)));
-typedef unsigned tu_int __attribute__ ((mode (TI)));
-
-typedef union
-{
-    ti_int all;
-    struct
-    {
-#if _YUGA_LITTLE_ENDIAN
-        du_int low;
-        di_int high;
-#else
-        di_int high;
-        du_int low;
-#endif /* _YUGA_LITTLE_ENDIAN */
-    }s;
-} twords;
-
-typedef union
-{
-    tu_int all;
-    struct
-    {
-#if _YUGA_LITTLE_ENDIAN
-        du_int low;
-        du_int high;
-#else
-        du_int high;
-        du_int low;
-#endif /* _YUGA_LITTLE_ENDIAN */
-    }s;
-} utwords;
-
-static inline ti_int make_ti(di_int h, di_int l) {
-    twords r;
-    r.s.high = h;
-    r.s.low = l;
-    return r.all;
-}
-
-static inline tu_int make_tu(du_int h, du_int l) {
-    utwords r;
-    r.s.high = h;
-    r.s.low = l;
-    return r.all;
-}
-
-#endif /* __x86_64 */
-
-typedef union
-{
-    su_int u;
-    float f;
-} float_bits;
-
-typedef union
-{
-    udwords u;
-    double  f;
-} double_bits;
-
-typedef struct
-{
-#if _YUGA_LITTLE_ENDIAN
-    udwords low;
-    udwords high;
-#else
-    udwords high;
-    udwords low;
-#endif /* _YUGA_LITTLE_ENDIAN */
-} uqwords;
-
-typedef union
-{
-    uqwords     u;
-    long double f;
-} long_double_bits;
+/* Include the commonly used internal type definitions. */
+#include "int_types.h"
 
 #endif /* INT_LIB_H */

Copied: compiler-rt/trunk/lib/int_types.h (from r144662, compiler-rt/trunk/lib/int_lib.h)
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_types.h?p2=compiler-rt/trunk/lib/int_types.h&p1=compiler-rt/trunk/lib/int_lib.h&r1=144662&r2=144668&rev=144668&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_lib.h (original)
+++ compiler-rt/trunk/lib/int_types.h Tue Nov 15 12:56:13 2011
@@ -7,46 +7,18 @@
  *
  * ===----------------------------------------------------------------------===
  *
- * This file is a configuration header for compiler-rt.
  * This file is not part of the interface of this library.
  *
+ * This file defines various standard types, most importantly a number of unions
+ * used to access parts of larger types.
+ *
  * ===----------------------------------------------------------------------===
  */
 
-#ifndef INT_LIB_H
-#define INT_LIB_H
-
-/* ABI macro definitions */
-
-#if __ARM_EABI__
-# define ARM_EABI_FNALIAS(aeabi_name, name)         \
-  void __aeabi_##aeabi_name() __attribute__((alias("__" #name)));
-# define COMPILER_RT_ABI __attribute__((pcs("aapcs")))
-#else
-# define ARM_EABI_FNALIAS(aeabi_name, name)
-# define COMPILER_RT_ABI
-#endif
-
-/* Assumption:  signed integral is 2's complement */
-/* Assumption:  right shift of signed negative is arithmetic shift */
+#ifndef INT_TYPES_H
+#define INT_TYPES_H
 
-#include <limits.h>
-#include <stdint.h>
 #include "endianness.h"
-#include <math.h>
-
-/* If compiling for kernel use, call panic() instead of abort(). */
-#ifdef KERNEL_USE
-extern void panic (const char *, ...);
-#define compilerrt_abort() \
-  panic("%s:%d: abort in %s", __FILE__, __LINE__, __FUNCTION__)
-#else
-#define compilerrt_abort() abort()
-#endif
-
-#if !defined(INFINITY) && defined(HUGE_VAL)
-#define INFINITY HUGE_VAL
-#endif /* INFINITY */
 
 typedef      int si_int;
 typedef unsigned su_int;
@@ -164,4 +136,5 @@
     long double f;
 } long_double_bits;
 
-#endif /* INT_LIB_H */
+#endif /* INT_TYPES_H */
+



From daniel at zuster.org  Tue Nov 15 12:56:21 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 15 Nov 2011 18:56:21 -0000
Subject: [llvm-commits] [compiler-rt] r144669 - in /compiler-rt/trunk/lib:
 endianness.h int_endianness.h int_lib.h int_types.h
Message-ID: <20111115185621.70F3E2A6C132@llvm.org>

Author: ddunbar
Date: Tue Nov 15 12:56:21 2011
New Revision: 144669

URL: http://llvm.org/viewvc/llvm-project?rev=144669&view=rev
Log:
lib: Rename endianness.h to int_endianness.h (for consistency) and tidy up a bit.

Added:
    compiler-rt/trunk/lib/int_endianness.h
      - copied, changed from r144668, compiler-rt/trunk/lib/endianness.h
Removed:
    compiler-rt/trunk/lib/endianness.h
Modified:
    compiler-rt/trunk/lib/int_lib.h
    compiler-rt/trunk/lib/int_types.h

Removed: compiler-rt/trunk/lib/endianness.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/endianness.h?rev=144668&view=auto
==============================================================================
--- compiler-rt/trunk/lib/endianness.h (original)
+++ compiler-rt/trunk/lib/endianness.h (removed)
@@ -1,94 +0,0 @@
-/* ===-- endianness.h - configuration header for compiler-rt ---------------===
- *
- *		       The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- * ===----------------------------------------------------------------------===
- *
- * This file is a configuration header for compiler-rt.
- * This file is not part of the interface of this library.
- *
- * ===----------------------------------------------------------------------===
- */
-
-#ifndef ENDIANNESS_H
-#define ENDIANNESS_H
-
-/*
- * Known limitations:
- *   Middle endian systems are not handled currently.
- */
-
-#if defined(__SVR4) && defined(__sun)
-#include <sys/byteorder.h>
-
-#if _BYTE_ORDER == _BIG_ENDIAN
-#define _YUGA_LITTLE_ENDIAN 0
-#define _YUGA_BIG_ENDIAN    1
-#elif _BYTE_ORDER == _LITTLE_ENDIAN 
-#define _YUGA_LITTLE_ENDIAN 1
-#define _YUGA_BIG_ENDIAN    0
-#endif /* _BYTE_ORDER */
-
-#endif /* Solaris and AuroraUX. */
-
-/* .. */
-
-#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
-#include <sys/endian.h>
-
-#if _BYTE_ORDER == _BIG_ENDIAN
-#define _YUGA_LITTLE_ENDIAN 0
-#define _YUGA_BIG_ENDIAN    1
-#elif _BYTE_ORDER == _LITTLE_ENDIAN
-#define _YUGA_LITTLE_ENDIAN 1
-#define _YUGA_BIG_ENDIAN    0
-#endif /* _BYTE_ORDER */
-
-#endif /* *BSD */
-
-/* .. */
-
-/* Mac OSX has __BIG_ENDIAN__ or __LITTLE_ENDIAN__ automatically set by the compiler (at least with GCC) */
-#if defined(__APPLE__) && defined(__MACH__) || defined(__ellcc__ )
-
-#ifdef __BIG_ENDIAN__
-#if __BIG_ENDIAN__
-#define _YUGA_LITTLE_ENDIAN 0
-#define _YUGA_BIG_ENDIAN    1
-#endif
-#endif /* __BIG_ENDIAN__ */
-
-#ifdef __LITTLE_ENDIAN__
-#if __LITTLE_ENDIAN__
-#define _YUGA_LITTLE_ENDIAN 1
-#define _YUGA_BIG_ENDIAN    0
-#endif
-#endif /* __LITTLE_ENDIAN__ */
-
-#endif /* Mac OSX */
-
-/* .. */
-
-#if defined(__linux__)
-#include <endian.h>
-
-#if __BYTE_ORDER == __BIG_ENDIAN
-#define _YUGA_LITTLE_ENDIAN 0
-#define _YUGA_BIG_ENDIAN    1
-#elif __BYTE_ORDER == __LITTLE_ENDIAN
-#define _YUGA_LITTLE_ENDIAN 1
-#define _YUGA_BIG_ENDIAN    0
-#endif /* __BYTE_ORDER */
-
-#endif /* GNU/Linux */
-
-/* . */
-
-#if !defined(_YUGA_LITTLE_ENDIAN) || !defined(_YUGA_BIG_ENDIAN)
-#error Unable to determine endian
-#endif /* Check we found an endianness correctly. */
-
-#endif /* ENDIANNESS_H */

Copied: compiler-rt/trunk/lib/int_endianness.h (from r144668, compiler-rt/trunk/lib/endianness.h)
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_endianness.h?p2=compiler-rt/trunk/lib/int_endianness.h&p1=compiler-rt/trunk/lib/endianness.h&r1=144668&r2=144669&rev=144669&view=diff
==============================================================================
--- compiler-rt/trunk/lib/endianness.h (original)
+++ compiler-rt/trunk/lib/int_endianness.h Tue Nov 15 12:56:21 2011
@@ -1,4 +1,4 @@
-/* ===-- endianness.h - configuration header for compiler-rt ---------------===
+/* ===-- int_endianness.h - configuration header for compiler-rt ------------===
  *
  *		       The LLVM Compiler Infrastructure
  *
@@ -13,13 +13,8 @@
  * ===----------------------------------------------------------------------===
  */
 
-#ifndef ENDIANNESS_H
-#define ENDIANNESS_H
-
-/*
- * Known limitations:
- *   Middle endian systems are not handled currently.
- */
+#ifndef INT_ENDIANNESS_H
+#define INT_ENDIANNESS_H
 
 #if defined(__SVR4) && defined(__sun)
 #include <sys/byteorder.h>
@@ -91,4 +86,4 @@
 #error Unable to determine endian
 #endif /* Check we found an endianness correctly. */
 
-#endif /* ENDIANNESS_H */
+#endif /* INT_ENDIANNESS_H */

Modified: compiler-rt/trunk/lib/int_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_lib.h?rev=144669&r1=144668&r2=144669&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_lib.h (original)
+++ compiler-rt/trunk/lib/int_lib.h Tue Nov 15 12:56:21 2011
@@ -16,6 +16,10 @@
 #ifndef INT_LIB_H
 #define INT_LIB_H
 
+/* Assumption: Signed integral is 2's complement. */
+/* Assumption: Right shift of signed negative is arithmetic shift. */
+/* Assumption: Endianness is little or big (not mixed). */
+
 /* ABI macro definitions */
 
 #if __ARM_EABI__
@@ -27,12 +31,8 @@
 # define COMPILER_RT_ABI
 #endif
 
-/* Assumption:  signed integral is 2's complement */
-/* Assumption:  right shift of signed negative is arithmetic shift */
-
 #include <limits.h>
 #include <stdint.h>
-#include "endianness.h"
 #include <math.h>
 
 /* If compiling for kernel use, call panic() instead of abort(). */

Modified: compiler-rt/trunk/lib/int_types.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_types.h?rev=144669&r1=144668&r2=144669&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_types.h (original)
+++ compiler-rt/trunk/lib/int_types.h Tue Nov 15 12:56:21 2011
@@ -18,7 +18,7 @@
 #ifndef INT_TYPES_H
 #define INT_TYPES_H
 
-#include "endianness.h"
+#include "int_endianness.h"
 
 typedef      int si_int;
 typedef unsigned su_int;



From daniel at zuster.org  Tue Nov 15 13:02:22 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 15 Nov 2011 19:02:22 -0000
Subject: [llvm-commits] [compiler-rt] r144671 - in /compiler-rt/trunk/lib:
 enable_execute_stack.c extendsfdf2.c floatdidf.c floatundidf.c
 gcc_personality_v0.c int_lib.h trampoline_setup.c truncdfsf2.c
Message-ID: <20111115190222.EA7102A6C131@llvm.org>

Author: ddunbar
Date: Tue Nov 15 13:02:22 2011
New Revision: 144671

URL: http://llvm.org/viewvc/llvm-project?rev=144671&view=rev
Log:
lib: Include stdbool.h in int_lib.h, and eliminate duplicate includes from a number of source files.

Modified:
    compiler-rt/trunk/lib/enable_execute_stack.c
    compiler-rt/trunk/lib/extendsfdf2.c
    compiler-rt/trunk/lib/floatdidf.c
    compiler-rt/trunk/lib/floatundidf.c
    compiler-rt/trunk/lib/gcc_personality_v0.c
    compiler-rt/trunk/lib/int_lib.h
    compiler-rt/trunk/lib/trampoline_setup.c
    compiler-rt/trunk/lib/truncdfsf2.c

Modified: compiler-rt/trunk/lib/enable_execute_stack.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/enable_execute_stack.c?rev=144671&r1=144670&r2=144671&view=diff
==============================================================================
--- compiler-rt/trunk/lib/enable_execute_stack.c (original)
+++ compiler-rt/trunk/lib/enable_execute_stack.c Tue Nov 15 13:02:22 2011
@@ -8,7 +8,8 @@
  * ===----------------------------------------------------------------------===
  */
 
-#include <stdint.h>
+#include "int_lib.h"
+
 #include <sys/mman.h>
 
 /* #include "config.h"

Modified: compiler-rt/trunk/lib/extendsfdf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/extendsfdf2.c?rev=144671&r1=144670&r2=144671&view=diff
==============================================================================
--- compiler-rt/trunk/lib/extendsfdf2.c (original)
+++ compiler-rt/trunk/lib/extendsfdf2.c Tue Nov 15 13:02:22 2011
@@ -38,9 +38,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include <stdint.h>
-#include <limits.h>
-
 #include "int_lib.h"
 
 typedef float src_t;

Modified: compiler-rt/trunk/lib/floatdidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatdidf.c?rev=144671&r1=144670&r2=144671&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatdidf.c (original)
+++ compiler-rt/trunk/lib/floatdidf.c Tue Nov 15 13:02:22 2011
@@ -29,7 +29,6 @@
 /* Support for systems that have hardware floating-point; we'll set the inexact flag
  * as a side-effect of this computation.
  */
-#include <stdint.h>
 
 COMPILER_RT_ABI double
 __floatdidf(di_int a)

Modified: compiler-rt/trunk/lib/floatundidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatundidf.c?rev=144671&r1=144670&r2=144671&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatundidf.c (original)
+++ compiler-rt/trunk/lib/floatundidf.c Tue Nov 15 13:02:22 2011
@@ -31,7 +31,6 @@
  * as a side-effect of this computation.
  */
 
-#include <stdint.h>
 
 COMPILER_RT_ABI double
 __floatundidf(du_int a)

Modified: compiler-rt/trunk/lib/gcc_personality_v0.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/gcc_personality_v0.c?rev=144671&r1=144670&r2=144671&view=diff
==============================================================================
--- compiler-rt/trunk/lib/gcc_personality_v0.c (original)
+++ compiler-rt/trunk/lib/gcc_personality_v0.c Tue Nov 15 13:02:22 2011
@@ -9,7 +9,6 @@
  *
  */
 
-#include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 

Modified: compiler-rt/trunk/lib/int_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_lib.h?rev=144671&r1=144670&r2=144671&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_lib.h (original)
+++ compiler-rt/trunk/lib/int_lib.h Tue Nov 15 13:02:22 2011
@@ -33,6 +33,7 @@
 
 #include <limits.h>
 #include <stdint.h>
+#include <stdbool.h>
 #include <math.h>
 
 /* If compiling for kernel use, call panic() instead of abort(). */

Modified: compiler-rt/trunk/lib/trampoline_setup.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/trampoline_setup.c?rev=144671&r1=144670&r2=144671&view=diff
==============================================================================
--- compiler-rt/trunk/lib/trampoline_setup.c (original)
+++ compiler-rt/trunk/lib/trampoline_setup.c Tue Nov 15 13:02:22 2011
@@ -8,7 +8,6 @@
  * ===----------------------------------------------------------------------===
  */
 
-#include <stdint.h>
 #include <stdlib.h>
 
 #include "int_lib.h"

Modified: compiler-rt/trunk/lib/truncdfsf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/truncdfsf2.c?rev=144671&r1=144670&r2=144671&view=diff
==============================================================================
--- compiler-rt/trunk/lib/truncdfsf2.c (original)
+++ compiler-rt/trunk/lib/truncdfsf2.c Tue Nov 15 13:02:22 2011
@@ -37,10 +37,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include <stdint.h>
-#include <limits.h>
-#include <stdbool.h>
-
 #include "int_lib.h"
 
 typedef double src_t;



From benny.kra at googlemail.com  Tue Nov 15 13:04:18 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 15 Nov 2011 19:04:18 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r144673 -
	/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <20111115190418.67F352A6C131@llvm.org>

Author: d0k
Date: Tue Nov 15 13:04:18 2011
New Revision: 144673

URL: http://llvm.org/viewvc/llvm-project?rev=144673&view=rev
Log:
Add missing paren.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=144673&r1=144672&r2=144673&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Nov 15 13:04:18 2011
@@ -3689,7 +3689,7 @@
               cast<VectorType>(Ty)->getElementType()->isFloatingPointTy())) {
     Op = BitCastToType(Op, getSuitableBitCastIntType(Ty));
   }
-  return BitCastToType(Builder.CreateNot(Op, Op->getName() + "not", Ty);
+  return BitCastToType(Builder.CreateNot(Op, Op->getName() + "not"), Ty);
 }
 
 Value *TreeToLLVM::EmitTRUTH_NOT_EXPR(tree exp) {



From atrick at apple.com  Tue Nov 15 13:07:36 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 15 Nov 2011 11:07:36 -0800
Subject: [llvm-commits] [llvm] r144526 - in /llvm/trunk:
 include/llvm/CodeGen/MachineBranchProbabilityInfo.h
 lib/CodeGen/MachineBranchProbabilityInfo.cpp
 test/CodeGen/X86/block-placement.ll
In-Reply-To: <20111114085016.857ED2A6C131@llvm.org>
References: <20111114085016.857ED2A6C131@llvm.org>
Message-ID: <9D91BDCD-A9D7-464F-956B-1EDCA4689E55@apple.com>

On Nov 14, 2011, at 12:50 AM, Chandler Carruth wrote:

> Author: chandlerc
> Date: Mon Nov 14 02:50:16 2011
> New Revision: 144526
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=144526&view=rev
> Log:
> Fix an overflow bug in MachineBranchProbabilityInfo. This pass relied on
> the sum of the edge weights not overflowing uint32, and crashed when
> they did. This is generally safe as BranchProbabilityInfo tries to
> provide this guarantee. However, the CFG can get modified during codegen
> in a way that grows the *sum* of the edge weights. This doesn't seem
> unreasonable (imagine just adding more blocks all with the default
> weight of 16), but it is hard to come up with a case that actually
> triggers 32-bit overflow. Fortuately, the single-source GCC build is
> good at this. The solution isn't very pretty, but its no worse than the
> previous code. We're already summing all of the edge weights on each
> query, we can sum them, check for an overflow, compute a scale, and sum
> them again.
> 
> I've included a *greatly* reduced test case out of the GCC source that
> triggers it. It's a pretty lame test, as it clearly is just barely
> triggering the overflow. I'd like to have something that is much more
> definitive, but I don't understand the fundamental pattern that triggers
> an explosion in the edge weight sums.
> 
> The buggy code is duplicated within this file. I'll colapse them into
> a single implementation in a subsequent commit.

When we discussed this design, we wanted that scaling to happen when edges are added. Hence the original assert checking for overflow. But, as you know, none of the CFG update logic was implemented. Your approach seems fine though, since it's a simple check and rarely hit. But did you consider handling this within addSuccessor? If we did that, we would ned weight_iterator to be const_iterator as well.

-Andy

> 
> Modified:
>    llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
>    llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp
>    llvm/trunk/test/CodeGen/X86/block-placement.ll
> 
> Modified: llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h?rev=144526&r1=144525&r2=144526&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineBranchProbabilityInfo.h Mon Nov 14 02:50:16 2011
> @@ -34,8 +34,10 @@
>   // weight to just "inherit" the non-zero weight of an adjacent successor.
>   static const uint32_t DEFAULT_WEIGHT = 16;
> 
> -  // Get sum of the block successors' weights.
> -  uint32_t getSumForBlock(MachineBasicBlock *MBB) const;
> +  // Get sum of the block successors' weights, potentially scaling them to fit
> +  // within 32-bits. If scaling is required, sets Scale based on the necessary
> +  // adjustment. Any edge weights used with the sum should be divided by Scale.
> +  uint32_t getSumForBlock(MachineBasicBlock *MBB, uint32_t &Scale) const;
> 
> public:
>   static char ID;
> 
> Modified: llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp?rev=144526&r1=144525&r2=144526&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineBranchProbabilityInfo.cpp Mon Nov 14 02:50:16 2011
> @@ -27,19 +27,34 @@
> char MachineBranchProbabilityInfo::ID = 0;
> 
> uint32_t MachineBranchProbabilityInfo::
> -getSumForBlock(MachineBasicBlock *MBB) const {
> -  uint32_t Sum = 0;
> -
> +getSumForBlock(MachineBasicBlock *MBB, uint32_t &Scale) const {
> +  // First we compute the sum with 64-bits of precision, ensuring that cannot
> +  // overflow by bounding the number of weights considered. Hopefully no one
> +  // actually needs 2^32 successors.
> +  assert(MBB->succ_size() < UINT32_MAX);
> +  uint64_t Sum = 0;
> +  Scale = 1;
>   for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
>        E = MBB->succ_end(); I != E; ++I) {
> -    MachineBasicBlock *Succ = *I;
> -    uint32_t Weight = getEdgeWeight(MBB, Succ);
> -    uint32_t PrevSum = Sum;
> -
> +    uint32_t Weight = getEdgeWeight(MBB, *I);
>     Sum += Weight;
> -    assert(Sum > PrevSum); (void) PrevSum;
>   }
> 
> +  // If the computed sum fits in 32-bits, we're done.
> +  if (Sum <= UINT32_MAX)
> +    return Sum;
> +
> +  // Otherwise, compute the scale necessary to cause the weights to fit, and
> +  // re-sum with that scale applied.
> +  assert((Sum / UINT32_MAX) < UINT32_MAX);
> +  Scale = (Sum / UINT32_MAX) + 1;
> +  Sum = 0;
> +  for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
> +       E = MBB->succ_end(); I != E; ++I) {
> +    uint32_t Weight = getEdgeWeight(MBB, *I);
> +    Sum += Weight / Scale;
> +  }
> +  assert(Sum <= UINT32_MAX);
>   return Sum;
> }
> 
> @@ -89,8 +104,9 @@
> BranchProbability
> MachineBranchProbabilityInfo::getEdgeProbability(MachineBasicBlock *Src,
>                                                  MachineBasicBlock *Dst) const {
> -  uint32_t N = getEdgeWeight(Src, Dst);
> -  uint32_t D = getSumForBlock(Src);
> +  uint32_t Scale = 1;
> +  uint32_t D = getSumForBlock(Src, Scale);
> +  uint32_t N = getEdgeWeight(Src, Dst) / Scale;
> 
>   return BranchProbability(N, D);
> }
> 
> Modified: llvm/trunk/test/CodeGen/X86/block-placement.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=144526&r1=144525&r2=144526&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/block-placement.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/block-placement.ll Mon Nov 14 02:50:16 2011
> @@ -271,3 +271,54 @@
>   %ptr2 = load i32** undef, align 4
>   br label %loop.body3
> }
> +
> +define i32 @problematic_switch() {
> +; This function's CFG caused overlow in the machine branch probability
> +; calculation, triggering asserts. Make sure we don't crash on it.
> +; CHECK: problematic_switch
> +
> +entry:
> +  switch i32 undef, label %exit [
> +    i32 879, label %bogus
> +    i32 877, label %step
> +    i32 876, label %step
> +    i32 875, label %step
> +    i32 874, label %step
> +    i32 873, label %step
> +    i32 872, label %step
> +    i32 868, label %step
> +    i32 867, label %step
> +    i32 866, label %step
> +    i32 861, label %step
> +    i32 860, label %step
> +    i32 856, label %step
> +    i32 855, label %step
> +    i32 854, label %step
> +    i32 831, label %step
> +    i32 830, label %step
> +    i32 829, label %step
> +    i32 828, label %step
> +    i32 815, label %step
> +    i32 814, label %step
> +    i32 811, label %step
> +    i32 806, label %step
> +    i32 805, label %step
> +    i32 804, label %step
> +    i32 803, label %step
> +    i32 802, label %step
> +    i32 801, label %step
> +    i32 800, label %step
> +    i32 799, label %step
> +    i32 798, label %step
> +    i32 797, label %step
> +    i32 796, label %step
> +    i32 795, label %step
> +  ]
> +bogus:
> +  unreachable
> +step:
> +  br label %exit
> +exit:
> +  %merge = phi i32 [ 3, %step ], [ 6, %entry ]
> +  ret i32 %merge
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From rafael.espindola at gmail.com  Tue Nov 15 13:08:46 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 15 Nov 2011 19:08:46 -0000
Subject: [llvm-commits] [llvm] r144674 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/pr11202.ll
Message-ID: <20111115190846.7A5902A6C131@llvm.org>

Author: rafael
Date: Tue Nov 15 13:08:46 2011
New Revision: 144674

URL: http://llvm.org/viewvc/llvm-project?rev=144674&view=rev
Log:
We currently use a callback to handle an IL pass deleting a BB that still
has a reference to it. Unfortunately, that doesn't work for codegen passes
since we don't get notified of MBB's being deleted (the original BB stays).

Use that fact to our advantage and after printing a function, check if
any of the IL BBs corresponds to a symbol that was not printed. This fixes
pr11202.

Added:
    llvm/trunk/test/CodeGen/X86/pr11202.ll
Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=144674&r1=144673&r2=144674&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Nov 15 13:08:46 2011
@@ -736,6 +736,18 @@
       OutStreamer.EmitRawText(StringRef("\tnop\n"));
   }
 
+  const Function *F = MF->getFunction();
+  for (Function::const_iterator i = F->begin(), e = F->end(); i != e; ++i) {
+    const BasicBlock *BB = i;
+    if (!BB->hasAddressTaken())
+      continue;
+    MCSymbol *Sym = GetBlockAddressSymbol(BB);
+    if (Sym->isDefined())
+      continue;
+    OutStreamer.AddComment("Address of block that was removed by CodeGen");
+    OutStreamer.EmitLabel(Sym);
+  }
+
   // Emit target-specific gunk after the function body.
   EmitFunctionBodyEnd();
 

Added: llvm/trunk/test/CodeGen/X86/pr11202.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr11202.ll?rev=144674&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr11202.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr11202.ll Tue Nov 15 13:08:46 2011
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
+
+ at bb = constant [1 x i8*] [i8* blockaddress(@main, %l2)]
+
+define void @main() {
+entry:
+  br label %l1
+
+l1:                                               ; preds = %l2, %entry
+  %a = zext i1 false to i32
+  br label %l2
+
+l2:                                               ; preds = %l1
+  %b = zext i1 false to i32
+  br label %l1
+}
+
+; CHECK: .Ltmp1:                                 # Address of block that was removed by CodeGen
+; CHECK: .quad	.Ltmp1



From dpatel at apple.com  Tue Nov 15 13:14:21 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 15 Nov 2011 11:14:21 -0800
Subject: [llvm-commits] [llvm] r144559 - in /llvm/trunk:
 lib/CodeGen/TwoAddressInstructionPass.cpp
 test/CodeGen/X86/iv-users-in-other-loops.ll
 test/CodeGen/X86/lsr-reuse-trunc.ll test/CodeGen/X86/sse3.ll
In-Reply-To: <20111114194856.004232A6C131@llvm.org>
References: <20111114194856.004232A6C131@llvm.org>
Message-ID: <095E4976-FE2F-4C0C-87C4-B3831AD06D82@apple.com>

Evan,

On Nov 14, 2011, at 11:48 AM, Evan Cheng wrote:

> Author: evancheng
> Date: Mon Nov 14 13:48:55 2011
> New Revision: 144559
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=144559&view=rev
> Log:
> Teach two-address pass to re-schedule two-address instructions (or the kill
> instructions of the two-address operands) in order to avoid inserting copies.
> This fixes the few regressions introduced when the two-address hack was
> disabled (without regressing the improvements).
> rdar://10422688
> 

This is causing MultiSource/Applications/oggenc/oggenc.exec (and few other) test failure on clang-i386-Os-g buildbot. Please investigate.
Thanks!
-
Devang

> Modified:
>    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
>    llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll
>    llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll
>    llvm/trunk/test/CodeGen/X86/sse3.ll
> 
> Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=144559&r1=144558&r2=144559&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
> +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon Nov 14 13:48:55 2011
> @@ -36,6 +36,7 @@
> #include "llvm/CodeGen/MachineInstrBuilder.h"
> #include "llvm/CodeGen/MachineRegisterInfo.h"
> #include "llvm/Analysis/AliasAnalysis.h"
> +#include "llvm/MC/MCInstrItineraries.h"
> #include "llvm/Target/TargetRegisterInfo.h"
> #include "llvm/Target/TargetInstrInfo.h"
> #include "llvm/Target/TargetMachine.h"
> @@ -56,11 +57,14 @@
> STATISTIC(Num3AddrSunk,        "Number of 3-address instructions sunk");
> STATISTIC(NumReMats,           "Number of instructions re-materialized");
> STATISTIC(NumDeletes,          "Number of dead instructions deleted");
> +STATISTIC(NumReSchedUps,       "Number of instructions re-scheduled up");
> +STATISTIC(NumReSchedDowns,     "Number of instructions re-scheduled down");
> 
> namespace {
>   class TwoAddressInstructionPass : public MachineFunctionPass {
>     const TargetInstrInfo *TII;
>     const TargetRegisterInfo *TRI;
> +    const InstrItineraryData *InstrItins;
>     MachineRegisterInfo *MRI;
>     LiveVariables *LV;
>     AliasAnalysis *AA;
> @@ -120,6 +124,18 @@
>                            MachineBasicBlock::iterator &nmi,
>                            MachineFunction::iterator &mbbi, unsigned Dist);
> 
> +    bool isDefTooClose(unsigned Reg, unsigned Dist,
> +                       MachineInstr *MI, MachineBasicBlock *MBB);
> +
> +    bool RescheduleMIBelowKill(MachineBasicBlock *MBB,
> +                               MachineBasicBlock::iterator &mi,
> +                               MachineBasicBlock::iterator &nmi,
> +                               unsigned Reg);
> +    bool RescheduleKillAboveMI(MachineBasicBlock *MBB,
> +                               MachineBasicBlock::iterator &mi,
> +                               MachineBasicBlock::iterator &nmi,
> +                               unsigned Reg);
> +
>     bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
>                                  MachineBasicBlock::iterator &nmi,
>                                  MachineFunction::iterator &mbbi,
> @@ -467,6 +483,32 @@
>   return false;
> }
> 
> +/// findLocalKill - Look for an instruction below MI in the MBB that kills the
> +/// specified register. Returns null if there are any other Reg use between the
> +/// instructions.
> +static
> +MachineInstr *findLocalKill(unsigned Reg, MachineBasicBlock *MBB,
> +                            MachineInstr *MI, MachineRegisterInfo *MRI,
> +                            DenseMap<MachineInstr*, unsigned> &DistanceMap) {
> +  MachineInstr *KillMI = 0;
> +  for (MachineRegisterInfo::use_nodbg_iterator
> +         UI = MRI->use_nodbg_begin(Reg),
> +         UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
> +    MachineInstr *UseMI = &*UI;
> +    if (UseMI == MI || UseMI->getParent() != MBB)
> +      continue;
> +    DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
> +    if (DI != DistanceMap.end())
> +      continue;
> +    if (!UI.getOperand().isKill())
> +      return 0;
> +    assert(!KillMI && "More than one local kills?");
> +    KillMI = UseMI;
> +  }
> +
> +  return KillMI;
> +}
> +
> /// findOnlyInterestingUse - Given a register, if has a single in-basic block
> /// use, return the use instruction if it's a copy or a two-address use.
> static
> @@ -852,6 +894,285 @@
>   return true;
> }
> 
> +/// RescheduleMIBelowKill - If there is one more local instruction that reads
> +/// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
> +/// instruction in order to eliminate the need for the copy.
> +bool
> +TwoAddressInstructionPass::RescheduleMIBelowKill(MachineBasicBlock *MBB,
> +                                     MachineBasicBlock::iterator &mi,
> +                                     MachineBasicBlock::iterator &nmi,
> +                                     unsigned Reg) {
> +  MachineInstr *MI = &*mi;
> +  DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 
> +  if (DI == DistanceMap.end())
> +    // Must be created from unfolded load. Don't waste time trying this.
> +    return false;
> +
> +  MachineInstr *KillMI = findLocalKill(Reg, MBB, mi, MRI, DistanceMap);
> +  if (!KillMI || KillMI->isCopy() || KillMI->isCopyLike())
> +    // Don't mess with copies, they may be coalesced later.
> +    return false;
> +
> +  const MCInstrDesc &MCID = KillMI->getDesc();
> +  if (MCID.hasUnmodeledSideEffects() || MCID.isCall() || MCID.isBranch() ||
> +      MCID.isTerminator())
> +    // Don't move pass calls, etc.
> +    return false;
> +
> +  unsigned DstReg;
> +  if (isTwoAddrUse(*KillMI, Reg, DstReg))
> +    return false;
> +
> +  bool SeenStore;
> +  if (!MI->isSafeToMove(TII, AA, SeenStore))
> +    return false;
> +
> +  if (TII->getInstrLatency(InstrItins, MI) > 1)
> +    // FIXME: Needs more sophisticated heuristics.
> +    return false;
> +
> +  SmallSet<unsigned, 2> Uses;
> +  SmallSet<unsigned, 2> Defs;
> +  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
> +    const MachineOperand &MO = MI->getOperand(i);
> +    if (!MO.isReg())
> +      continue;
> +    unsigned MOReg = MO.getReg();
> +    if (!MOReg)
> +      continue;
> +    if (MO.isDef())
> +      Defs.insert(MOReg);
> +    else
> +      Uses.insert(MOReg);
> +  }
> +
> +  // Move the copies connected to MI down as well.
> +  MachineBasicBlock::iterator From = MI;
> +  MachineBasicBlock::iterator To = llvm::next(From);
> +  while (To->isCopy() && Defs.count(To->getOperand(1).getReg())) {
> +    Defs.insert(To->getOperand(0).getReg());
> +    ++To;
> +  }
> +
> +  // Check if the reschedule will not break depedencies.
> +  unsigned NumVisited = 0;
> +  MachineBasicBlock::iterator KillPos = KillMI;
> +  ++KillPos;
> +  for (MachineBasicBlock::iterator I = To; I != KillPos; ++I) {
> +    MachineInstr *OtherMI = I;
> +    // DBG_VALUE cannot be counted against the limit.
> +    if (OtherMI->isDebugValue())
> +      continue;
> +    if (NumVisited > 10)  // FIXME: Arbitrary limit to reduce compile time cost.
> +      return false;
> +    ++NumVisited;
> +    const MCInstrDesc &OMCID = OtherMI->getDesc();
> +    if (OMCID.hasUnmodeledSideEffects() || OMCID.isCall() || OMCID.isBranch() ||
> +        OMCID.isTerminator())
> +      // Don't move pass calls, etc.
> +      return false;
> +    for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
> +      const MachineOperand &MO = OtherMI->getOperand(i);
> +      if (!MO.isReg())
> +        continue;
> +      unsigned MOReg = MO.getReg();
> +      if (!MOReg)
> +        continue;
> +      if (MO.isDef()) {
> +        if (Uses.count(MOReg))
> +          // Physical register use would be clobbered.
> +          return false;
> +        if (!MO.isDead() && Defs.count(MOReg))
> +          // May clobber a physical register def.
> +          // FIXME: This may be too conservative. It's ok if the instruction
> +          // is sunken completely below the use.
> +          return false;
> +      } else {
> +        if (Defs.count(MOReg))
> +          return false;
> +        if (MOReg != Reg && MO.isKill() && Uses.count(MOReg))
> +          // Don't want to extend other live ranges and update kills.
> +          return false;
> +      }
> +    }
> +  }
> +
> +  // Move debug info as well.
> +  if (From != MBB->begin()) {
> +    while (llvm::prior(From)->isDebugValue())
> +      --From;
> +  }
> +
> +  // Copies following MI may have been moved as well.
> +  nmi = To;
> +  MBB->splice(KillPos, MBB, From, To);
> +  DistanceMap.erase(DI);
> +
> +  if (LV) {
> +    // Update live variables
> +    LV->removeVirtualRegisterKilled(Reg, KillMI);
> +    LV->addVirtualRegisterKilled(Reg, MI);
> +  } else {
> +    for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
> +      MachineOperand &MO = KillMI->getOperand(i);
> +      if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
> +        continue;
> +      MO.setIsKill(false);
> +    }
> +    MI->addRegisterKilled(Reg, 0);
> +  }
> +
> +  return true;
> +}
> +
> +/// isDefTooClose - Return true if the re-scheduling will put the given
> +/// instruction too close to the defs of its register dependencies.
> +bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
> +                                              MachineInstr *MI,
> +                                              MachineBasicBlock *MBB) {
> +  for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
> +         DE = MRI->def_end(); DI != DE; ++DI) {
> +    MachineInstr *DefMI = &*DI;
> +    if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike())
> +      continue;
> +    if (DefMI == MI)
> +      return true; // MI is defining something KillMI uses
> +    DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI);
> +    if (DDI == DistanceMap.end())
> +      return true;  // Below MI
> +    unsigned DefDist = DDI->second;
> +    assert(Dist > DefDist && "Visited def already?");
> +    if (TII->getInstrLatency(InstrItins, DefMI) > (int)(Dist - DefDist))
> +      return true;
> +  }
> +  return false;
> +}
> +
> +/// RescheduleKillAboveMI - If there is one more local instruction that reads
> +/// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
> +/// current two-address instruction in order to eliminate the need for the
> +/// copy.
> +bool
> +TwoAddressInstructionPass::RescheduleKillAboveMI(MachineBasicBlock *MBB,
> +                                     MachineBasicBlock::iterator &mi,
> +                                     MachineBasicBlock::iterator &nmi,
> +                                     unsigned Reg) {
> +  MachineInstr *MI = &*mi;
> +  DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
> +  if (DI == DistanceMap.end())
> +    // Must be created from unfolded load. Don't waste time trying this.
> +    return false;
> +
> +  MachineInstr *KillMI = findLocalKill(Reg, MBB, mi, MRI, DistanceMap);
> +  if (!KillMI || KillMI->isCopy() || KillMI->isCopyLike())
> +    // Don't mess with copies, they may be coalesced later.
> +    return false;
> +
> +  unsigned DstReg;
> +  if (isTwoAddrUse(*KillMI, Reg, DstReg))
> +    return false;
> +
> +  bool SeenStore;
> +  if (!KillMI->isSafeToMove(TII, AA, SeenStore))
> +    return false;
> +
> +  SmallSet<unsigned, 2> Uses;
> +  SmallSet<unsigned, 2> Kills;
> +  SmallSet<unsigned, 2> Defs;
> +  SmallSet<unsigned, 2> LiveDefs;
> +  for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
> +    const MachineOperand &MO = KillMI->getOperand(i);
> +    if (!MO.isReg())
> +      continue;
> +    unsigned MOReg = MO.getReg();
> +    if (MO.isUse()) {
> +      if (!MOReg)
> +        continue;
> +      if (isDefTooClose(MOReg, DI->second, MI, MBB))
> +        return false;
> +      Uses.insert(MOReg);
> +      if (MO.isKill() && MOReg != Reg)
> +        Kills.insert(MOReg);
> +    } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
> +      Defs.insert(MOReg);
> +      if (!MO.isDead())
> +        LiveDefs.insert(MOReg);
> +    }
> +  }
> +
> +  // Check if the reschedule will not break depedencies.
> +  unsigned NumVisited = 0;
> +  MachineBasicBlock::iterator KillPos = KillMI;
> +  for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
> +    MachineInstr *OtherMI = I;
> +    // DBG_VALUE cannot be counted against the limit.
> +    if (OtherMI->isDebugValue())
> +      continue;
> +    if (NumVisited > 10)  // FIXME: Arbitrary limit to reduce compile time cost.
> +      return false;
> +    ++NumVisited;
> +    const MCInstrDesc &MCID = OtherMI->getDesc();
> +    if (MCID.hasUnmodeledSideEffects() || MCID.isCall() || MCID.isBranch() ||
> +        MCID.isTerminator())
> +      // Don't move pass calls, etc.
> +      return false;
> +    for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
> +      const MachineOperand &MO = OtherMI->getOperand(i);
> +      if (!MO.isReg())
> +        continue;
> +      unsigned MOReg = MO.getReg();
> +      if (!MOReg)
> +        continue;
> +      if (MO.isUse()) {
> +        if (Defs.count(MOReg))
> +          // Moving KillMI can clobber the physical register if the def has
> +          // not been seen.
> +          return false;
> +        if (Kills.count(MOReg))
> +          // Don't want to extend other live ranges and update kills.
> +          return false;
> +      } else {
> +        if (Uses.count(MOReg))
> +          return false;
> +        if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
> +            LiveDefs.count(MOReg))
> +          return false;
> +        // Physical register def is seen.
> +        Defs.erase(MOReg);
> +      }
> +    }
> +  }
> +
> +  // Move the old kill above MI, don't forget to move debug info as well.
> +  MachineBasicBlock::iterator InsertPos = mi;
> +  if (InsertPos != MBB->begin())
> +    while (llvm::prior(InsertPos)->isDebugValue())
> +      --InsertPos;
> +  MachineBasicBlock::iterator From = KillMI;
> +  MachineBasicBlock::iterator To = llvm::next(From);
> +  while (llvm::prior(From)->isDebugValue())
> +    --From;
> +  MBB->splice(InsertPos, MBB, From, To);
> +
> +  nmi = llvm::prior(mi); // Backtrack so we process the moved instruction.
> +  DistanceMap.erase(DI);
> +
> +  if (LV) {
> +    // Update live variables
> +    LV->removeVirtualRegisterKilled(Reg, KillMI);
> +    LV->addVirtualRegisterKilled(Reg, MI);
> +  } else {
> +    for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
> +      MachineOperand &MO = KillMI->getOperand(i);
> +      if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
> +        continue;
> +      MO.setIsKill(false);
> +    }
> +    MI->addRegisterKilled(Reg, 0);
> +  }
> +  return true;
> +}
> +
> /// TryInstructionTransform - For the case where an instruction has a single
> /// pair of tied register operands, attempt some transformations that may
> /// either eliminate the tied operands or improve the opportunities for
> @@ -863,17 +1184,18 @@
>                         MachineFunction::iterator &mbbi,
>                         unsigned SrcIdx, unsigned DstIdx, unsigned Dist,
>                         SmallPtrSet<MachineInstr*, 8> &Processed) {
> -  const MCInstrDesc &MCID = mi->getDesc();
> -  unsigned regA = mi->getOperand(DstIdx).getReg();
> -  unsigned regB = mi->getOperand(SrcIdx).getReg();
> +  MachineInstr &MI = *mi;
> +  const MCInstrDesc &MCID = MI.getDesc();
> +  unsigned regA = MI.getOperand(DstIdx).getReg();
> +  unsigned regB = MI.getOperand(SrcIdx).getReg();
> 
>   assert(TargetRegisterInfo::isVirtualRegister(regB) &&
>          "cannot make instruction into two-address form");
> 
>   // If regA is dead and the instruction can be deleted, just delete
>   // it so it doesn't clobber regB.
> -  bool regBKilled = isKilled(*mi, regB, MRI, TII);
> -  if (!regBKilled && mi->getOperand(DstIdx).isDead() &&
> +  bool regBKilled = isKilled(MI, regB, MRI, TII);
> +  if (!regBKilled && MI.getOperand(DstIdx).isDead() &&
>       DeleteUnusedInstr(mi, nmi, mbbi, Dist)) {
>     ++NumDeletes;
>     return true; // Done with this instruction.
> @@ -885,20 +1207,20 @@
>   unsigned regCIdx = ~0U;
>   bool TryCommute = false;
>   bool AggressiveCommute = false;
> -  if (MCID.isCommutable() && mi->getNumOperands() >= 3 &&
> -      TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
> +  if (MCID.isCommutable() && MI.getNumOperands() >= 3 &&
> +      TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
>     if (SrcIdx == SrcOp1)
>       regCIdx = SrcOp2;
>     else if (SrcIdx == SrcOp2)
>       regCIdx = SrcOp1;
> 
>     if (regCIdx != ~0U) {
> -      regC = mi->getOperand(regCIdx).getReg();
> -      if (!regBKilled && isKilled(*mi, regC, MRI, TII))
> +      regC = MI.getOperand(regCIdx).getReg();
> +      if (!regBKilled && isKilled(MI, regC, MRI, TII))
>         // If C dies but B does not, swap the B and C operands.
>         // This makes the live ranges of A and C joinable.
>         TryCommute = true;
> -      else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) {
> +      else if (isProfitableToCommute(regB, regC, &MI, mbbi, Dist)) {
>         TryCommute = true;
>         AggressiveCommute = true;
>       }
> @@ -913,6 +1235,13 @@
>     return false;
>   }
> 
> +  // If there is one more use of regB later in the same MBB, consider
> +  // re-schedule this MI below it.
> +  if (RescheduleMIBelowKill(mbbi, mi, nmi, regB)) {
> +    ++NumReSchedDowns;
> +    return true;
> +  }
> +
>   if (TargetRegisterInfo::isVirtualRegister(regA))
>     ScanUses(regA, &*mbbi, Processed);
> 
> @@ -928,6 +1257,13 @@
>     }
>   }
> 
> +  // If there is one more use of regB later in the same MBB, consider
> +  // re-schedule it before this MI if it's legal.
> +  if (RescheduleKillAboveMI(mbbi, mi, nmi, regB)) {
> +    ++NumReSchedUps;
> +    return true;
> +  }
> +
>   // If this is an instruction with a load folded into it, try unfolding
>   // the load, e.g. avoid this:
>   //   movq %rdx, %rcx
> @@ -940,7 +1276,7 @@
>     // Determine if a load can be unfolded.
>     unsigned LoadRegIndex;
>     unsigned NewOpc =
> -      TII->getOpcodeAfterMemoryUnfold(mi->getOpcode(),
> +      TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
>                                       /*UnfoldLoad=*/true,
>                                       /*UnfoldStore=*/false,
>                                       &LoadRegIndex);
> @@ -950,12 +1286,12 @@
>         MachineFunction &MF = *mbbi->getParent();
> 
>         // Unfold the load.
> -        DEBUG(dbgs() << "2addr:   UNFOLDING: " << *mi);
> +        DEBUG(dbgs() << "2addr:   UNFOLDING: " << MI);
>         const TargetRegisterClass *RC =
>           TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI);
>         unsigned Reg = MRI->createVirtualRegister(RC);
>         SmallVector<MachineInstr *, 2> NewMIs;
> -        if (!TII->unfoldMemoryOperand(MF, mi, Reg,
> +        if (!TII->unfoldMemoryOperand(MF, &MI, Reg,
>                                       /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
>                                       NewMIs)) {
>           DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
> @@ -986,21 +1322,21 @@
>           // Success, or at least we made an improvement. Keep the unfolded
>           // instructions and discard the original.
>           if (LV) {
> -            for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
> -              MachineOperand &MO = mi->getOperand(i);
> +            for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
> +              MachineOperand &MO = MI.getOperand(i);
>               if (MO.isReg() && 
>                   TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
>                 if (MO.isUse()) {
>                   if (MO.isKill()) {
>                     if (NewMIs[0]->killsRegister(MO.getReg()))
> -                      LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[0]);
> +                      LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
>                     else {
>                       assert(NewMIs[1]->killsRegister(MO.getReg()) &&
>                              "Kill missing after load unfold!");
> -                      LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[1]);
> +                      LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
>                     }
>                   }
> -                } else if (LV->removeVirtualRegisterDead(MO.getReg(), mi)) {
> +                } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
>                   if (NewMIs[1]->registerDefIsDead(MO.getReg()))
>                     LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
>                   else {
> @@ -1013,7 +1349,7 @@
>             }
>             LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
>           }
> -          mi->eraseFromParent();
> +          MI.eraseFromParent();
>           mi = NewMIs[1];
>           if (TransformSuccess)
>             return true;
> @@ -1040,6 +1376,7 @@
>   MRI = &MF.getRegInfo();
>   TII = TM.getInstrInfo();
>   TRI = TM.getRegisterInfo();
> +  InstrItins = TM.getInstrItineraryData();
>   LV = getAnalysisIfAvailable<LiveVariables>();
>   AA = &getAnalysis<AliasAnalysis>();
> 
> 
> Modified: llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll?rev=144559&r1=144558&r2=144559&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll Mon Nov 14 13:48:55 2011
> @@ -1,7 +1,7 @@
> ; RUN: llc < %s -march=x86-64 -enable-lsr-nested -o %t
> ; RUN: not grep inc %t
> ; RUN: grep dec %t | count 2
> -; RUN: grep addq %t | count 10
> +; RUN: grep addq %t | count 12
> ; RUN: not grep addb %t
> ; RUN: not grep leal %t
> ; RUN: not grep movq %t
> 
> Modified: llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll?rev=144559&r1=144558&r2=144559&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll Mon Nov 14 13:48:55 2011
> @@ -4,14 +4,13 @@
> ; Full strength reduction wouldn't reduce register pressure, so LSR should
> ; stick with indexing here.
> 
> -; FIXME: This is worse off from disabling of scheduler 2-address hack.
> ; CHECK: movaps        (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]]
> -; CHECK: leaq  4(%rax), %{{rcx|r9}}
> ; CHECK: cvtdq2ps
> ; CHECK: orps          {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]]
> ; CHECK: movaps        [[X4]], (%{{rdi|rcx}},%rax,4)
> -; CHECK: cmpl  %{{ecx|r9d}}, (%{{rdx|r8}})
> -; CHECK: jg
> +; CHECK: addq  $4, %rax
> +; CHECK: cmpl  %eax, (%{{rdx|r8}})
> +; CHECK-NEXT: jg
> 
> define void @vvfloorf(float* nocapture %y, float* nocapture %x, i32* nocapture %n) nounwind {
> entry:
> 
> Modified: llvm/trunk/test/CodeGen/X86/sse3.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=144559&r1=144558&r2=144559&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/sse3.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/sse3.ll Mon Nov 14 13:48:55 2011
> @@ -164,12 +164,12 @@
>         store <4 x i16> %6, <4 x i16>* @g2, align 8
>         ret void
> ; X64: 	t10:
> -; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %eax
> -; X64: 		movlhps [[X1:%xmm[0-9]+]]
> -; X64: 		pshuflw	$8, [[X1]], [[X2:%xmm[0-9]+]]
> -; X64: 		pinsrw	$2, %eax, [[X2]]
> +; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %ecx
> ; X64: 		pextrw	$6, [[X0]], %eax
> -; X64: 		pinsrw	$3, %eax, [[X2]]
> +; X64: 		movlhps [[X0]], [[X0]]
> +; X64: 		pshuflw	$8, [[X0]], [[X0]]
> +; X64: 		pinsrw	$2, %ecx, [[X0]]
> +; X64: 		pinsrw	$3, %eax, [[X0]]
> }
> 
> 
> @@ -232,10 +232,9 @@
>         %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
>         ret <8 x i16> %tmp8
> ; X64: 	t15:
> -; X64:          movdqa %xmm0, %xmm2
> +; X64: 		pextrw	$7, %xmm0, %eax
> ; X64: 		punpcklqdq	%xmm1, %xmm0
> ; X64: 		pshuflw	$-128, %xmm0, %xmm0
> -; X64: 		pextrw	$7, %xmm2, %eax
> ; X64: 		pinsrw	$2, %eax, %xmm0
> ; X64: 		ret
> }
> @@ -248,12 +247,11 @@
>         %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0,  <16 x i32> < i32 0, i32 1, i32 2, i32 17,  i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
>         ret <16 x i8> %tmp9
> ; X64: 	t16:
> -; X64: 		movdqa	%xmm1, %xmm2
> -; X64: 		pslldq	$2, %xmm2
> -; X64: 		movd	%xmm2, %eax
> -; X64: 		pinsrw	$0, %eax, %xmm0
> -; X64: 		pextrw	$8, %xmm1, %eax
> -; X64: 		pextrw	$1, %xmm2, %ecx
> +; X64: 		pextrw	$8, %xmm0, %eax
> +; X64: 		pslldq	$2, %xmm0
> +; X64: 		movd	%xmm0, %ecx
> +; X64: 		pextrw	$1, %xmm0, %edx
> +; X64: 		pinsrw	$0, %ecx, %xmm0
> ; X64: 		ret
> }
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From benny.kra at googlemail.com  Tue Nov 15 13:12:09 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 15 Nov 2011 19:12:09 -0000
Subject: [llvm-commits] [llvm] r144675 - in /llvm/trunk:
 include/llvm/Transforms/Utils/BuildLibCalls.h
 lib/Transforms/Scalar/SimplifyLibCalls.cpp
 lib/Transforms/Utils/BuildLibCalls.cpp
Message-ID: <20111115191209.AC5C42A6C131@llvm.org>

Author: d0k
Date: Tue Nov 15 13:12:09 2011
New Revision: 144675

URL: http://llvm.org/viewvc/llvm-project?rev=144675&view=rev
Log:
StringRefize and simplify.

Modified:
    llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h
    llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
    llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp

Modified: llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h?rev=144675&r1=144674&r2=144675&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h (original)
+++ llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h Tue Nov 15 13:12:09 2011
@@ -68,7 +68,7 @@
   /// 'Op' and returns one value with the same type.  If 'Op' is a long double,
   /// 'l' is added as the suffix of name, if 'Op' is a float, we add a 'f'
   /// suffix.
-  Value *EmitUnaryFloatFnCall(Value *Op, const char *Name, IRBuilder<> &B,
+  Value *EmitUnaryFloatFnCall(Value *Op, StringRef Name, IRBuilder<> &B,
                               const AttrListPtr &Attrs);
 
   /// EmitPutChar - Emit a call to the putchar function.  This assumes that Char

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=144675&r1=144674&r2=144675&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Tue Nov 15 13:12:09 2011
@@ -963,8 +963,7 @@
 
     // floor((double)floatval) -> (double)floorf(floatval)
     Value *V = Cast->getOperand(0);
-    V = EmitUnaryFloatFnCall(V, Callee->getName().data(), B,
-                             Callee->getAttributes());
+    V = EmitUnaryFloatFnCall(V, Callee->getName(), B, Callee->getAttributes());
     return B.CreateFPExt(V, B.getDoubleTy());
   }
 };

Modified: llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp?rev=144675&r1=144674&r2=144675&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp Tue Nov 15 13:12:09 2011
@@ -15,11 +15,12 @@
 #include "llvm/Type.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
+#include "llvm/Intrinsics.h"
+#include "llvm/LLVMContext.h"
 #include "llvm/Module.h"
 #include "llvm/Support/IRBuilder.h"
 #include "llvm/Target/TargetData.h"
-#include "llvm/LLVMContext.h"
-#include "llvm/Intrinsics.h"
+#include "llvm/ADT/SmallString.h"
 
 using namespace llvm;
 
@@ -206,19 +207,16 @@
 /// 'floor').  This function is known to take a single of type matching 'Op' and
 /// returns one value with the same type.  If 'Op' is a long double, 'l' is
 /// added as the suffix of name, if 'Op' is a float, we add a 'f' suffix.
-Value *llvm::EmitUnaryFloatFnCall(Value *Op, const char *Name,
-                                  IRBuilder<> &B, const AttrListPtr &Attrs) {
-  char NameBuffer[20];
+Value *llvm::EmitUnaryFloatFnCall(Value *Op, StringRef Name, IRBuilder<> &B,
+                                  const AttrListPtr &Attrs) {
+  SmallString<20> NameBuffer;
   if (!Op->getType()->isDoubleTy()) {
     // If we need to add a suffix, copy into NameBuffer.
-    unsigned NameLen = strlen(Name);
-    assert(NameLen < sizeof(NameBuffer)-2);
-    memcpy(NameBuffer, Name, NameLen);
+    NameBuffer += Name;
     if (Op->getType()->isFloatTy())
-      NameBuffer[NameLen] = 'f';  // floorf
+      NameBuffer += 'f'; // floorf
     else
-      NameBuffer[NameLen] = 'l';  // floorl
-    NameBuffer[NameLen+1] = 0;
+      NameBuffer += 'l'; // floorl
     Name = NameBuffer;
   }
 



From atrick at apple.com  Tue Nov 15 13:29:34 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 15 Nov 2011 11:29:34 -0800
Subject: [llvm-commits] [llvm] r144527 - in /llvm/trunk:
 include/llvm/CodeGen/MachineBranchProbabilityInfo.h
 lib/CodeGen/MachineBranchProbabilityInfo.cpp
In-Reply-To: <CAGCO0KjKv3P3OUm1au9VUV9A5e8a6BT3U9NrCgoF9-8p7_8Jxw@mail.gmail.com>
References: <20111114085600.04B5C2A6C131@llvm.org>
	<6720255668642743212@unknownmsgid>
	<CAGCO0KjKv3P3OUm1au9VUV9A5e8a6BT3U9NrCgoF9-8p7_8Jxw@mail.gmail.com>
Message-ID: <07EED45E-CF33-41FB-84E4-CFEBD9979982@apple.com>

On Nov 14, 2011, at 1:32 AM, Chandler Carruth wrote:

> On Mon, Nov 14, 2011 at 1:11 AM, Benjamin Kramer <benny.kra at googlemail.com> wrote:
> On 14.11.2011, at 10:00, Chandler Carruth <chandlerc at gmail.com> wrote:
> 
> > Author: chandlerc
> > Date: Mon Nov 14 02:55:59 2011
> > New Revision: 144527
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=144527&view=rev
> > Log:
> > Reuse the logic in getEdgeProbability within getHotSucc in order to
> > correctly handle blocks whose successor weights sum to more than
> > UINT32_MAX. This is slightly less efficient, but the entire thing is
> > already linear on the number of successors. Calling it within any hot
> > routine is a mistake, and indeed no one is calling it. It also
> > simplifies the code.
> 
> Does this problem also exist in the non-machine BPI version of getHotSucc?
> 
> At a fundamental level, yes. But I'm not sure we really care.
> 
> At the IR level, we *compute* the branch probabilities. If the structure of the program is changed radically, we *recompute* them rather than updating them in-place. The computation (in the BPI analysis pass) is careful to eagerly scale weights down such that the sum doesn't overflow. So the assertion (and the lack of code to handle it) seem fine there.
> 
> At the machine code level, we are updating the weights of the edges in the few places where they are mutated. That's what causes trouble. My suspicion is critical edge splitting, but I've not dug too deeply into it.
> 
> So essentially, I don't think the IR-level code is really subject to the bug, despite having the same inability to cope with overflow.

Assuming the sum of edges doesn't overflow is not a bug, it's a very deliberate design feature. Preserving the analysis across CFG updates wasn't implemented, and the "bug" that Chandler is suffering from is that we enabled this code implying it was sufficiently implemented without any safeguards or even documenting the limitations.

Scaling the edges was part of the original design, but it was supposed to happen in setEdgeWeight, not getEdgeWeight. The weights are currently only set by the static estimator, so we didn't need an intelligent API. For general CFG manipulation, we definitely need a wrapper around setEdgeWeight that scales the edges automatically.

-Andy

> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From grosbach at apple.com  Tue Nov 15 13:29:45 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 19:29:45 -0000
Subject: [llvm-commits] [llvm] r144679 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20111115192945.68A872A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 13:29:45 2011
New Revision: 144679

URL: http://llvm.org/viewvc/llvm-project?rev=144679&view=rev
Log:
Thumb2 assembly parsing for mul.w in IT block fix.

When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144679&r1=144678&r2=144679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 15 13:29:45 2011
@@ -4098,6 +4098,7 @@
       // remove the cc_out operand.
       (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
        !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
+       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
        !inITBlock() ||
        (static_cast<ARMOperand*>(Operands[3])->getReg() !=
         static_cast<ARMOperand*>(Operands[5])->getReg() &&

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=144679&r1=144678&r2=144679&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Nov 15 13:29:45 2011
@@ -1228,12 +1228,16 @@
         mul r3, r4, r6
         it eq
         muleq r3, r4, r5
+        it le
+        mulle r4, r4, r8
 
 @ CHECK: muls	r3, r4, r3              @ encoding: [0x63,0x43]
 @ CHECK: mul	r3, r4, r3              @ encoding: [0x04,0xfb,0x03,0xf3]
 @ CHECK: mul	r3, r4, r6              @ encoding: [0x04,0xfb,0x06,0xf3]
 @ CHECK: it	eq                      @ encoding: [0x08,0xbf]
 @ CHECK: muleq	r3, r4, r5              @ encoding: [0x04,0xfb,0x05,0xf3]
+@ CHECK: it	le                      @ encoding: [0xd8,0xbf]
+@ CHECK: mulle	r4, r4, r8              @ encoding: [0x04,0xfb,0x08,0xf4]
 
 
 @------------------------------------------------------------------------------



From resistor at mac.com  Tue Nov 15 13:55:00 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 15 Nov 2011 19:55:00 -0000
Subject: [llvm-commits] [llvm] r144683 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp
 test/MC/Disassembler/ARM/neon.txt
Message-ID: <20111115195500.EF7812A6C131@llvm.org>

Author: resistor
Date: Tue Nov 15 13:55:00 2011
New Revision: 144683

URL: http://llvm.org/viewvc/llvm-project?rev=144683&view=rev
Log:
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/neon.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=144683&r1=144682&r2=144683&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 15 13:55:00 2011
@@ -4815,6 +4815,7 @@
                      v4f32, v4i32, uint_to_fp>;
 
 //   VCVT     : Vector Convert Between Floating-Point and Fixed-Point.
+let DecoderMethod = "DecodeVCVTD" in {
 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
                         v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
@@ -4823,7 +4824,9 @@
                         v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
                         v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
+}
 
+let DecoderMethod = "DecodeVCVTQ" in {
 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
                         v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
@@ -4832,6 +4835,7 @@
                         v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
                         v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
+}
 
 //   VCVT     : Vector Convert Between Half-Precision and Single-Precision.
 def  VCVTf2h  : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=144683&r1=144682&r2=144683&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Nov 15 13:55:00 2011
@@ -179,8 +179,6 @@
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
-                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
@@ -251,6 +249,11 @@
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
+                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
+                                uint64_t Address, const void *Decoder);
+
 
 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
                                uint64_t Address, const void *Decoder);
@@ -1921,12 +1924,6 @@
 }
 
 
-static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
-                                 uint64_t Address, const void *Decoder) {
-  Inst.addOperand(MCOperand::CreateImm(64 - Val));
-  return MCDisassembler::Success;
-}
-
 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
                                    uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
@@ -4085,3 +4082,60 @@
 
   return S;
 }
+
+static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
+                                uint64_t Address, const void *Decoder) {
+  unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
+  Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
+  unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
+  Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
+  unsigned imm = fieldFromInstruction32(Insn, 16, 6);
+  unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
+
+  DecodeStatus S = MCDisassembler::Success;
+
+  // VMOVv2f32 is ambiguous with these decodings.
+  if (!(imm & 0x38 && cmode == 0xF)) {
+    Inst.setOpcode(ARM::VMOVv2f32);
+    return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
+  }
+
+  if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
+
+  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::CreateImm(64 - imm));
+
+  return S;
+}
+
+static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
+                                uint64_t Address, const void *Decoder) {
+  unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
+  Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
+  unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
+  Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
+  unsigned imm = fieldFromInstruction32(Insn, 16, 6);
+  unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
+
+  DecodeStatus S = MCDisassembler::Success;
+
+  // VMOVv4f32 is ambiguous with these decodings.
+  if (!(imm & 0x38) && cmode == 0xF) {
+    Inst.setOpcode(ARM::VMOVv4f32);
+    return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
+  }
+
+  if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
+
+  if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::CreateImm(64 - imm));
+
+  return S;
+}
+

Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=144683&r1=144682&r2=144683&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Tue Nov 15 13:55:00 2011
@@ -1863,3 +1863,9 @@
 # CHECK: vld1.32	{d22, d23, d24, d25}, [pc, :64]!
 0x9d 0xaa 0x41 0xf4
 # CHECK: vst1.32	{d26, d27}, [r1, :64]!
+
+0x10 0x0f 0x83 0xf2
+0x50 0x0f 0x83 0xf2
+# CHECK: vmov.f32	d0, #1.600000e+01
+# CHECK: vmov.f32	q0, #1.600000e+01
+



From grosbach at apple.com  Tue Nov 15 13:55:17 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 19:55:17 -0000
Subject: [llvm-commits] [llvm] r144684 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrThumb2.td AsmParser/ARMAsmParser.cpp
Message-ID: <20111115195517.1C0532A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 13:55:16 2011
New Revision: 144684

URL: http://llvm.org/viewvc/llvm-project?rev=144684&view=rev
Log:
Thumb2 two-operand 'mul' instruction wide encoding parsing.

rdar://10449724

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=144684&r1=144683&r2=144684&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Nov 15 13:55:16 2011
@@ -4084,3 +4084,8 @@
 // for isel.
 def : t2InstAlias<"mov${p} $Rd, $imm",
                   (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
+
+
+// Wide 'mul' encoding can be specified with only two operands.
+def : t2InstAlias<"mul${p} $Rn, $Rm",
+                  (t2MUL rGPR:$Rn, rGPR:$Rn, rGPR:$Rm, pred:$p)>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144684&r1=144683&r2=144684&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 15 13:55:16 2011
@@ -4106,6 +4106,20 @@
         static_cast<ARMOperand*>(Operands[4])->getReg())))
     return true;
 
+  // Also check the 'mul' syntax variant that doesn't specify an explicit
+  // destination register.
+  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
+      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
+      static_cast<ARMOperand*>(Operands[3])->isReg() &&
+      static_cast<ARMOperand*>(Operands[4])->isReg() &&
+      // If the registers aren't low regs  or the cc_out operand is zero
+      // outside of an IT block, we have to use the 32-bit encoding, so
+      // remove the cc_out operand.
+      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
+       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
+       !inITBlock()))
+    return true;
+
 
 
   // Register-register 'add/sub' for thumb does not have a cc_out operand



From grosbach at apple.com  Tue Nov 15 13:56:17 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 19:56:17 -0000
Subject: [llvm-commits] [llvm] r144685 -
	/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Message-ID: <20111115195617.804962A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 13:56:17 2011
New Revision: 144685

URL: http://llvm.org/viewvc/llvm-project?rev=144685&view=rev
Log:
Testcase for r144684.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=144685&r1=144684&r2=144685&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Nov 15 13:56:17 2011
@@ -1230,6 +1230,7 @@
         muleq r3, r4, r5
         it le
         mulle r4, r4, r8
+        mul r6, r5
 
 @ CHECK: muls	r3, r4, r3              @ encoding: [0x63,0x43]
 @ CHECK: mul	r3, r4, r3              @ encoding: [0x04,0xfb,0x03,0xf3]
@@ -1238,6 +1239,7 @@
 @ CHECK: muleq	r3, r4, r5              @ encoding: [0x04,0xfb,0x05,0xf3]
 @ CHECK: it	le                      @ encoding: [0xd8,0xbf]
 @ CHECK: mulle	r4, r4, r8              @ encoding: [0x04,0xfb,0x08,0xf4]
+@ CHECK: mul	r6, r6, r5              @ encoding: [0x06,0xfb,0x05,0xf6]
 
 
 @------------------------------------------------------------------------------



From grosbach at apple.com  Tue Nov 15 14:02:06 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 20:02:06 -0000
Subject: [llvm-commits] [llvm] r144688 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/basic-arm-instructions.s
Message-ID: <20111115200206.A74EA2A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 14:02:06 2011
New Revision: 144688

URL: http://llvm.org/viewvc/llvm-project?rev=144688&view=rev
Log:
ARM assembly parsing for two-operand form of 'mul' instruction.

Ongoing rdar://10435114.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=144688&r1=144687&r2=144688&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 15 14:02:06 2011
@@ -5023,3 +5023,7 @@
 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
                         (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
                              cc_out:$s)>;
+
+// 'mul' instruction can be specified with only two operands.
+def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",
+                   (MUL rGPR:$Rn, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=144688&r1=144687&r2=144688&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Nov 15 14:02:06 2011
@@ -1001,11 +1001,13 @@
         muls r5, r6, r7
         mulgt r5, r6, r7
         mulsle r5, r6, r7
+        mul r11, r5
 
 @ CHECK: mul	r5, r6, r7              @ encoding: [0x96,0x07,0x05,0xe0]
 @ CHECK: muls	r5, r6, r7              @ encoding: [0x96,0x07,0x15,0xe0]
 @ CHECK: mulgt	r5, r6, r7              @ encoding: [0x96,0x07,0x05,0xc0]
 @ CHECK: mulsle	r5, r6, r7              @ encoding: [0x96,0x07,0x15,0xd0]
+@ CHECK: mul	r11, r11, r5            @ encoding: [0x9b,0x05,0x0b,0xe0]
 
 
 @------------------------------------------------------------------------------



From grosbach at apple.com  Tue Nov 15 14:14:51 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 20:14:51 -0000
Subject: [llvm-commits] [llvm] r144689 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrVFP.td test/MC/ARM/simple-fp-encoding.s
Message-ID: <20111115201451.E7C1C2A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 14:14:51 2011
New Revision: 144689

URL: http://llvm.org/viewvc/llvm-project?rev=144689&view=rev
Log:
ARM assembly parsing for two-operand form of 'mul' instruction.

rdar://10449856.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
    llvm/trunk/test/MC/ARM/simple-fp-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=144689&r1=144688&r2=144689&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 15 14:14:51 2011
@@ -1172,3 +1172,9 @@
                         (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
 defm : VFPDT64InstAlias<"vstr${p}", "$Dd, $addr",
                         (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
+
+// VMUL has a two-operand form (implied destination operand)
+def : VFP2InstAlias<"vmul${p}.f64 $Dn, $Dm",
+                    (VMULD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
+def : VFP2InstAlias<"vmul${p}.f32 $Sn, $Sm",
+                    (VMULS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=144689&r1=144688&r2=144689&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Tue Nov 15 14:14:51 2011
@@ -21,9 +21,15 @@
 @ CHECK: vmul.f64 d16, d17, d16      @ encoding: [0xa0,0x0b,0x61,0xee]
         vmul.f64        d16, d17, d16
 
+@ CHECK: vmul.f64	d20, d20, d17   @ encoding: [0xa1,0x4b,0x64,0xee]
+	vmul.f64  d20, d17
+
 @ CHECK: vmul.f32 s0, s1, s0         @ encoding: [0x80,0x0a,0x20,0xee]
         vmul.f32        s0, s1, s0
 
+@ CHECK: vmul.f32	s11, s11, s21   @ encoding: [0xaa,0x5a,0x65,0xee]
+	vmul.f32  s11, s21
+
 @ CHECK: vnmul.f64 d16, d17, d16     @ encoding: [0xe0,0x0b,0x61,0xee]
         vnmul.f64       d16, d17, d16
 



From grosbach at apple.com  Tue Nov 15 14:29:42 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 20:29:42 -0000
Subject: [llvm-commits] [llvm] r144691 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrVFP.td test/MC/ARM/simple-fp-encoding.s
Message-ID: <20111115202942.D24142A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 14:29:42 2011
New Revision: 144691

URL: http://llvm.org/viewvc/llvm-project?rev=144691&view=rev
Log:
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.

Yet more of rdar://10435076.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
    llvm/trunk/test/MC/ARM/simple-fp-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=144691&r1=144690&r2=144691&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 15 14:29:42 2011
@@ -1178,3 +1178,14 @@
                     (VMULD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
 def : VFP2InstAlias<"vmul${p}.f32 $Sn, $Sm",
                     (VMULS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
+
+// VMOV can accept optional .f32/.f64 suffix.
+def : VFP2InstAlias<"vmov${p}.f32 $Rt, $Sn",
+                    (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
+def : VFP2InstAlias<"vmov${p}.f32 $Sn, $Rt",
+                    (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
+
+def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
+                    (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
+def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
+                    (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=144691&r1=144690&r2=144691&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Tue Nov 15 14:29:42 2011
@@ -133,6 +133,16 @@
         vmovne  s0, r0
         vmoveq  s0, r1
 
+        vmov.f32 r1, s2
+        vmov.f32 s4, r3
+        vmov.f64 r1, r5, d2
+        vmov.f64 d4, r3, r9
+
+@ CHECK: vmov	r1, s2                  @ encoding: [0x10,0x1a,0x11,0xee]
+@ CHECK: vmov	s4, r3                  @ encoding: [0x10,0x3a,0x02,0xee]
+@ CHECK: vmov	r1, r5, d2              @ encoding: [0x12,0x1b,0x55,0xec]
+@ CHECK: vmov	d4, r3, r9              @ encoding: [0x14,0x3b,0x49,0xec]
+
 @ CHECK: vmrs r0, fpscr              @ encoding: [0x10,0x0a,0xf1,0xee]
         vmrs    r0, fpscr
 @ CHECK: vmrs  r0, fpexc             @ encoding: [0x10,0x0a,0xf8,0xee]



From resistor at mac.com  Tue Nov 15 14:30:41 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 15 Nov 2011 20:30:41 -0000
Subject: [llvm-commits] [llvm] r144692 -
	/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Message-ID: <20111115203041.9157E2A6C131@llvm.org>

Author: resistor
Date: Tue Nov 15 14:30:41 2011
New Revision: 144692

URL: http://llvm.org/viewvc/llvm-project?rev=144692&view=rev
Log:
Fix a misplaced paren bug.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=144692&r1=144691&r2=144692&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Nov 15 14:30:41 2011
@@ -4095,7 +4095,7 @@
   DecodeStatus S = MCDisassembler::Success;
 
   // VMOVv2f32 is ambiguous with these decodings.
-  if (!(imm & 0x38 && cmode == 0xF)) {
+  if (!(imm & 0x38) && cmode == 0xF) {
     Inst.setOpcode(ARM::VMOVv2f32);
     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
   }



From eli.friedman at gmail.com  Tue Nov 15 14:41:55 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 15 Nov 2011 12:41:55 -0800
Subject: [llvm-commits] Proposal/patch: Enable bitcode streaming
In-Reply-To: <CAAEAhvdtqnOFQhXfWc68tOvPHK0xCEDKYzpFL_tRw2Gu0qFdyQ@mail.gmail.com>
References: <CAAEAhvci4uJmsT4b1ibkG57qmzAesDdPQejmhAVLEmFd_FzyOg@mail.gmail.com>
	<CAAEAhvdtqnOFQhXfWc68tOvPHK0xCEDKYzpFL_tRw2Gu0qFdyQ@mail.gmail.com>
Message-ID: <CAJdarcFBAY7Lec7cGYyziDhmNZ37dobf_RuBWFtSp6ZYazYJoA@mail.gmail.com>

On Mon, Nov 14, 2011 at 10:54 AM, Derek Schuff <dschuff at google.com> wrote:
> Ping?
> Could someone take a look at this? (or, have I sent it to the wrong
> place/not marked it properly?)

This is the right place; not sure why nobody has responded.

-Eli

> On Wed, Nov 9, 2011 at 4:57 PM, Derek Schuff <dschuff at google.com> wrote:
>>
>> Hello all,
>> The following is a proposal (and a prototype patch) to enable bitcode
>> streaming. The overall goal is to be able to overlap bitcode
>> reading/download with compilation, a functionality useful obviously for
>> pnacl and renderscript but also potentially for any situation where the
>> interface between the frontend and backend is something other than a file.
>> In the current state of the world, at a high level, there are 2 things
>> keeping this from happening. The first is that BitcodeReader construction
>> takes a MemoryBuffer which it expects to be filled with bitcode, and inside
>> BitcodeReader, the BitstreamCursor (which is the primary interface to the
>> bitcode itself) gets pointers to the bitcode in memory, and does all of its
>> magic with pointer arithmetic. The second issue is that in
>> BitcodeReader::ParseModule (which is run when right after the Module and
>> BitcodeReader objects are created), the reader makes a pass over the entire
>> bitcode file. This step does everything except read the function bodies, but
>> it records the bit locations of each function for future materialization.
>> High-level change description:
>> This patch creates a class called BitcodeStream, which is a very simple
>> interface with one method (GetBytes), which fetches the requested number of
>> bytes from the stream, and writes them into the requested destination. This
>> method may block the calling thread if there are not yet enough bytes
>> available in the stream buffer (similarly to a stdin or socket read).
>> The first issue above is addressed by introducing the BitstreamVector, an
>> abstraction that wraps the bitcode in memory. Instead of using pointers, the
>> BitstreamCursor uses indices and gets bitcode bytes by indexing (i.e.
>> operator[] ) the BitstreamVector. When streaming is not used, the
>> BitstreamVector itself keeps pointers to the start and end of the backing
>> MemoryBuffer and the indexing operator is just a pointer dereference. For
>> streaming use, the BitstreamVector has a BitcodeStream object. If a byte is
>> requested that has not yet been fetched, it calls GetBytes to get more,
>> until it has enough to return the requested byte.
>> This model of allowing any byte to be requested and blocking the caller
>> has the advantage that there is no structural/architectural change required
>> at this lowest level, nor at the high level (A FunctionPassManager is used
>> to iterate over all the functions and compile each one).
>> The second issue is solved by 2 simple changes. The first is in
>> ParseModule. Instead of a single pass over all the bitcode, ParseModule
>> becomes resumable. ?ParseModule will do its normal handling for top-level
>> records, type table blocks, metadata, etc, but if streaming is in use, it
>> will save its state and return as soon as a function subblock is encountered
>> (rather than saving its location and skipping over it). Each subsequent time
>> it is called, it bookmarks and skips one function block. Later, when a
>> function needs to be materialized, if the function body has been seen
>> already, then materialization is the same as before. Otherwise, Materialize
>> will keep calling ParseModule (each time bookmarking and skipping one
>> function body) until the requested function is found. The one other change
>> required to make this work simply is that the bitcode writer writes function
>> bodies as the last subblock (currently the attachment metadata and value
>> symbol table are written after the function bodies).
>> The prototype patch is attached and can also be viewed online at
>> http://codereview.chromium.org/8393017/ . Feedback is welcome, as well as
>> guidance from the relevant code owners/reviewers regarding what the next
>> step needs to be toward committing this.
>> Thanks,
>> -Derek
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>


From baldrick at free.fr  Tue Nov 15 14:46:18 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 15 Nov 2011 21:46:18 +0100
Subject: [llvm-commits] [llvm] r144267 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 test/CodeGen/X86/2006-05-11-InstrSched.ll
 test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
 test/CodeGen/X86/change-compare-stride-1.ll
 test/CodeGen/X86/fold-pcmpeqd-0.ll
 test/CodeGen/X86/iv-users-in-other-loops.ll
 test/CodeGen/X86/lsr-loop-exit-cond.ll test/CodeGen/X86/lsr-reuse-trunc.ll
 test/CodeGen/X86/masked-iv-safe.ll
 test/CodeGen/X86/multiple-loop-post-inc.ll test/CodeGen/X86/sse2.ll
 test/CodeGen/X86/sse3.ll
In-Reply-To: <4EC27FC7.4020205@gmail.com>
References: <20111110074316.A97871BE001@llvm.org>
	<4EBBB1ED.8000105@free.fr>	<9FD603CE-74CE-4B7A-AC1D-87466E187F82@apple.com>	<4EBC9D90.50805@free.fr>
	<4EC27FC7.4020205@gmail.com>
Message-ID: <4EC2CF9A.2090606@free.fr>

Hi Rafael,

>>> That's really bizarre. It's obviously exposing a unrelated bug. Thanks for looking into this.
>>
>> I think this is a case of PR11200: the code generators make decisions based on
>> floating point computations.  On i386, GCC uses the floating point stack, while
>> LLVM uses xmm registers, when building LLVM.  This results in codegen sometimes
>> making different decisions due to different rounding.
>
> Can't we just use -msse when building stage1 or do a bootstrap4?

alternatively, maybe all floating point computations should be removed from the
code generator.

Ciao, Duncan.

>
>> I've disabled the part of the dragonegg bootstrap that compares object files
>> produced by GCC compiled LLVM with those produced by LLVM compiled LLVM as a
>> workaround.
>>
>> Ciao, Duncan.
>
> Cheers,
> Rafael
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From grosbach at apple.com  Tue Nov 15 14:49:46 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 20:49:46 -0000
Subject: [llvm-commits] [llvm] r144694 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-shuffle-encoding.s
Message-ID: <20111115204946.480182A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 14:49:46 2011
New Revision: 144694

URL: http://llvm.org/viewvc/llvm-project?rev=144694&view=rev
Log:
ARM alternate size suffices for VTRN instructions.

rdar://10435076

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=144694&r1=144693&r2=144694&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 15 14:49:46 2011
@@ -5442,3 +5442,19 @@
 //                          (VST1d32Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
 //defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
 //                          (VST1d64Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
+
+
+// VTRN instructions data type suffix aliases for more-specific types.
+defm : VFPDT8ReqInstAlias <"vtrn${p}", "$Dd, $Dm",
+                          (VTRNd8 DPR:$Dd, DPR:$Dm, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vtrn${p}", "$Dd, $Dm",
+                          (VTRNd16 DPR:$Dd, DPR:$Dm, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vtrn${p}", "$Dd, $Dm",
+                          (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
+
+defm : VFPDT8ReqInstAlias <"vtrn${p}", "$Qd, $Qm",
+                          (VTRNq8 QPR:$Qd, QPR:$Qm, pred:$p)>;
+defm : VFPDT16ReqInstAlias<"vtrn${p}", "$Qd, $Qm",
+                          (VTRNq16 QPR:$Qd, QPR:$Qm, pred:$p)>;
+defm : VFPDT32ReqInstAlias<"vtrn${p}", "$Qd, $Qm",
+                          (VTRNq32 QPR:$Qd, QPR:$Qm, pred:$p)>;

Modified: llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s?rev=144694&r1=144693&r2=144694&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-shuffle-encoding.s Tue Nov 15 14:49:46 2011
@@ -44,3 +44,63 @@
 	vzip.16	q9, q8
 @ CHECK: vzip.32	q9, q8                  @ encoding: [0xe0,0x21,0xfa,0xf3]
 	vzip.32	q9, q8
+
+
+@ VTRN alternate size suffices
+
+        vtrn.8 d3, d9
+        vtrn.i8 d3, d9
+        vtrn.u8 d3, d9
+        vtrn.p8 d3, d9
+        vtrn.16 d3, d9
+        vtrn.i16 d3, d9
+        vtrn.u16 d3, d9
+        vtrn.p16 d3, d9
+        vtrn.32 d3, d9
+        vtrn.i32 d3, d9
+        vtrn.u32 d3, d9
+        vtrn.f32 d3, d9
+        vtrn.f d3, d9
+
+        vtrn.8 q14, q6
+        vtrn.i8 q14, q6
+        vtrn.u8 q14, q6
+        vtrn.p8 q14, q6
+        vtrn.16 q14, q6
+        vtrn.i16 q14, q6
+        vtrn.u16 q14, q6
+        vtrn.p16 q14, q6
+        vtrn.32 q14, q6
+        vtrn.i32 q14, q6
+        vtrn.u32 q14, q6
+        vtrn.f32 q14, q6
+        vtrn.f q14, q6
+
+@ CHECK: vtrn.8	d3, d9                  @ encoding: [0x89,0x30,0xb2,0xf3]
+@ CHECK: vtrn.8	d3, d9                  @ encoding: [0x89,0x30,0xb2,0xf3]
+@ CHECK: vtrn.8	d3, d9                  @ encoding: [0x89,0x30,0xb2,0xf3]
+@ CHECK: vtrn.8	d3, d9                  @ encoding: [0x89,0x30,0xb2,0xf3]
+@ CHECK: vtrn.16	d3, d9          @ encoding: [0x89,0x30,0xb6,0xf3]
+@ CHECK: vtrn.16	d3, d9          @ encoding: [0x89,0x30,0xb6,0xf3]
+@ CHECK: vtrn.16	d3, d9          @ encoding: [0x89,0x30,0xb6,0xf3]
+@ CHECK: vtrn.16	d3, d9          @ encoding: [0x89,0x30,0xb6,0xf3]
+@ CHECK: vtrn.32	d3, d9          @ encoding: [0x89,0x30,0xba,0xf3]
+@ CHECK: vtrn.32	d3, d9          @ encoding: [0x89,0x30,0xba,0xf3]
+@ CHECK: vtrn.32	d3, d9          @ encoding: [0x89,0x30,0xba,0xf3]
+@ CHECK: vtrn.32	d3, d9          @ encoding: [0x89,0x30,0xba,0xf3]
+@ CHECK: vtrn.32	d3, d9          @ encoding: [0x89,0x30,0xba,0xf3]
+
+@ CHECK: vtrn.8	q14, q6                 @ encoding: [0xcc,0xc0,0xf2,0xf3]
+@ CHECK: vtrn.8	q14, q6                 @ encoding: [0xcc,0xc0,0xf2,0xf3]
+@ CHECK: vtrn.8	q14, q6                 @ encoding: [0xcc,0xc0,0xf2,0xf3]
+@ CHECK: vtrn.8	q14, q6                 @ encoding: [0xcc,0xc0,0xf2,0xf3]
+@ CHECK: vtrn.16	q14, q6         @ encoding: [0xcc,0xc0,0xf6,0xf3]
+@ CHECK: vtrn.16	q14, q6         @ encoding: [0xcc,0xc0,0xf6,0xf3]
+@ CHECK: vtrn.16	q14, q6         @ encoding: [0xcc,0xc0,0xf6,0xf3]
+@ CHECK: vtrn.16	q14, q6         @ encoding: [0xcc,0xc0,0xf6,0xf3]
+@ CHECK: vtrn.32	q14, q6         @ encoding: [0xcc,0xc0,0xfa,0xf3]
+@ CHECK: vtrn.32	q14, q6         @ encoding: [0xcc,0xc0,0xfa,0xf3]
+@ CHECK: vtrn.32	q14, q6         @ encoding: [0xcc,0xc0,0xfa,0xf3]
+@ CHECK: vtrn.32	q14, q6         @ encoding: [0xcc,0xc0,0xfa,0xf3]
+@ CHECK: vtrn.32	q14, q6         @ encoding: [0xcc,0xc0,0xfa,0xf3]
+



From grosbach at apple.com  Tue Nov 15 15:01:30 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 21:01:30 -0000
Subject: [llvm-commits] [llvm] r144695 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20111115210130.6141E2A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 15:01:30 2011
New Revision: 144695

URL: http://llvm.org/viewvc/llvm-project?rev=144695&view=rev
Log:
Fix typo.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144695&r1=144694&r2=144695&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 15 15:01:30 2011
@@ -2366,7 +2366,7 @@
   case ARM::Q6:  return ARM::D12;
   case ARM::Q7:  return ARM::D14;
   case ARM::Q8:  return ARM::D16;
-  case ARM::Q9:  return ARM::D19;
+  case ARM::Q9:  return ARM::D18;
   case ARM::Q10: return ARM::D20;
   case ARM::Q11: return ARM::D22;
   case ARM::Q12: return ARM::D24;



From dpatel at apple.com  Tue Nov 15 15:03:58 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 15 Nov 2011 21:03:58 -0000
Subject: [llvm-commits] [llvm] r144696 -
	/llvm/trunk/lib/CodeGen/RegAllocFast.cpp
Message-ID: <20111115210358.88D4E2A6C131@llvm.org>

Author: dpatel
Date: Tue Nov 15 15:03:58 2011
New Revision: 144696

URL: http://llvm.org/viewvc/llvm-project?rev=144696&view=rev
Log:
Insert modified DBG_VALUE into LiveDbgValueMap. 

Modified:
    llvm/trunk/lib/CodeGen/RegAllocFast.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=144696&r1=144695&r2=144696&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Nov 15 15:03:58 2011
@@ -815,7 +815,6 @@
           if (!MO.isReg()) continue;
           unsigned Reg = MO.getReg();
           if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
-          LiveDbgValueMap[Reg].push_back(MI);
           LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
           if (LRI != LiveVirtRegs.end())
             setPhysReg(MI, i, LRI->second.PhysReg);
@@ -849,6 +848,7 @@
               }
             }
           }
+          LiveDbgValueMap[Reg].push_back(MI);
         }
       }
       // Next instruction.



From grosbach at apple.com  Tue Nov 15 15:18:36 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 21:18:36 -0000
Subject: [llvm-commits] [llvm] r144698 -
	/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
Message-ID: <20111115211836.306A12A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 15:18:35 2011
New Revision: 144698

URL: http://llvm.org/viewvc/llvm-project?rev=144698&view=rev
Log:
ARM size suffix on VFP single-precision 'vmov' is optional.

rdar://10435114

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=144698&r1=144697&r2=144698&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 15 15:18:35 2011
@@ -1189,3 +1189,8 @@
                     (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
                     (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
+
+// VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
+// VMOVD does.
+def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
+                    (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;



From spop at codeaurora.org  Tue Nov 15 15:24:05 2011
From: spop at codeaurora.org (Sebastian Pop)
Date: Tue, 15 Nov 2011 15:24:05 -0600
Subject: [llvm-commits] [polly] r142770 -
	/polly/trunk/lib/ScheduleOptimizer.cpp
In-Reply-To: <20111023205926.E87883524006@llvm.org>
References: <20111023205926.E87883524006@llvm.org>
Message-ID: <CAE5reQ+UF36qOyoP_fCEqaMmnneskrFtTHzApucqEBS=x6Amqg@mail.gmail.com>

On Sun, Oct 23, 2011 at 3:59 PM, Tobias Grosser
<grosser at fim.uni-passau.de> wrote:
> Author: grosser
> Date: Sun Oct 23 15:59:26 2011
> New Revision: 142770
>
> URL: http://llvm.org/viewvc/llvm-project?rev=142770&view=rev
> Log:
> ScheduleOptimizer: Allow to disable tiling
>
> Modified:
> ? ?polly/trunk/lib/ScheduleOptimizer.cpp
>
> Modified: polly/trunk/lib/ScheduleOptimizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=142770&r1=142769&r2=142770&view=diff
> ==============================================================================
> --- polly/trunk/lib/ScheduleOptimizer.cpp (original)
> +++ polly/trunk/lib/ScheduleOptimizer.cpp Sun Oct 23 15:59:26 2011
> @@ -38,6 +38,11 @@
> ?using namespace polly;
>
> ?static cl::opt<bool>
> +DisableTiling("polly-no-tiling",
> + ? ? ? ? cl::desc("Disable tiling in the isl scheduler"), cl::Hidden,
> + ? ? ? ? cl::init(false));
> +
> +static cl::opt<bool>
> ?Prevector("enable-schedule-prevector",
> ? ? ? ? ?cl::desc("Enable the prevectorization in the scheduler"), cl::Hidden,
> ? ? ? ? ?cl::value_desc("Prevectorization enabled"),
> @@ -202,14 +207,17 @@
> ? isl_union_map *tileUnionMap;
>
> ? partialSchedule = isl_band_get_partial_schedule(band);
> - ?ctx = isl_union_map_get_ctx(partialSchedule);
> - ?Space= isl_union_map_get_space(partialSchedule);
> - ?scheduleDimensions = isl_band_n_member(band);
> -
> - ?tileMap = getTileMap(ctx, scheduleDimensions, Space);
> - ?tileUnionMap = isl_union_map_from_map(isl_map_from_basic_map(tileMap));
> - ?tileUnionMap = isl_union_map_align_params(tileUnionMap, Space);
> - ?partialSchedule = isl_union_map_apply_range(partialSchedule, tileUnionMap);

Could you please rewrite this with an early return like this?

if (DisableTiling)
  return partialSchedule;

See http://llvm.org/docs/CodingStandards.html#hl_earlyexit

> +
> + ?if (!DisableTiling) {
> + ? ?ctx = isl_union_map_get_ctx(partialSchedule);
> + ? ?Space= isl_union_map_get_space(partialSchedule);
> + ? ?scheduleDimensions = isl_band_n_member(band);
> +
> + ? ?tileMap = getTileMap(ctx, scheduleDimensions, Space);
> + ? ?tileUnionMap = isl_union_map_from_map(isl_map_from_basic_map(tileMap));
> + ? ?tileUnionMap = isl_union_map_align_params(tileUnionMap, Space);
> + ? ?partialSchedule = isl_union_map_apply_range(partialSchedule, tileUnionMap);
> + ?}
>
> ? return partialSchedule;
> ?}
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Sebastian Pop
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum


From ahatanaka at mips.com  Tue Nov 15 15:33:05 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Tue, 15 Nov 2011 21:33:05 -0000
Subject: [llvm-commits] [llvm] r144699 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111115213305.46A802A6C131@llvm.org>

Author: ahatanak
Date: Tue Nov 15 15:33:05 2011
New Revision: 144699

URL: http://llvm.org/viewvc/llvm-project?rev=144699&view=rev
Log:
Update section "MIPS Target Improvements" in the llvm 3.0 release notes.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=144699&r1=144698&r2=144699&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Nov 15 15:33:05 2011
@@ -970,6 +970,27 @@
   
 <!--=========================================================================-->
 <h3>
+<a name="MIPS">MIPS Target Improvements</a>
+</h3>
+
+<div>
+
+<p>New features and major changes in the MIPS target include:</p>
+
+<ul>
+  <li>Most MIPS32r1 and r2 instructions are now supported.</li>
+  <li>LE/BE MIPS32r1/r2 has been tested extensively.</li>
+  <li>O32 ABI has been fully tested.</li>
+  <li>MIPS backend has migrated to using the MC infrastructure for assembly printing. Initial support for direct object code emission has been implemented too.</li>
+  <li>Delay slot filler has been updated. Now it tries to fill delay slots with useful instructions instead of always filling them with NOPs.</li> 
+  <li>Support for old-style JIT is complete.</li>
+  <li>Support for old architectures (MIPS1 and MIPS2) has been removed.</li>
+  <li>Initial support for MIPS64 has been added.</li>
+</ul>
+</div>
+  
+<!--=========================================================================-->
+<h3>
 <a name="OtherTS">Other Target Specific Improvements</a>
 </h3>
 



From spop at codeaurora.org  Tue Nov 15 15:42:00 2011
From: spop at codeaurora.org (Sebastian Pop)
Date: Tue, 15 Nov 2011 15:42:00 -0600
Subject: [llvm-commits] [polly] r142773 - in /polly/trunk:
 lib/RegisterPasses.cpp www/example_load_Polly_into_clang.html
In-Reply-To: <20111023205935.E768C3524009@llvm.org>
References: <20111023205935.E768C3524009@llvm.org>
Message-ID: <CAE5reQJWZXMetPsxqtyLuK7Y_PZAFCmduBDNZ0syoMs+8h5z3w@mail.gmail.com>

On Sun, Oct 23, 2011 at 3:59 PM, Tobias Grosser
<grosser at fim.uni-passau.de> wrote:
> Author: grosser
> Date: Sun Oct 23 15:59:35 2011
> New Revision: 142773
>
> URL: http://llvm.org/viewvc/llvm-project?rev=142773&view=rev
> Log:
> Add an option to run the PoCC optimizer
>
> Modified:
> ? ?polly/trunk/lib/RegisterPasses.cpp
> ? ?polly/trunk/www/example_load_Polly_into_clang.html
>
> Modified: polly/trunk/lib/RegisterPasses.cpp
> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/RegisterPasses.cpp?rev=142773&r1=142772&r2=142773&view=diff
> ==============================================================================
> --- polly/trunk/lib/RegisterPasses.cpp (original)
> +++ polly/trunk/lib/RegisterPasses.cpp Sun Oct 23 15:59:35 2011
> @@ -37,6 +37,10 @@
> ? ? ? ?cl::desc("Disable Polly Code Generation"), cl::Hidden,
> ? ? ? ?cl::init(false));
> ?static cl::opt<bool>
> +UsePocc("polly-use-pocc",
> + ? ? ? cl::desc("Use the PoCC optimizer instead of the one in isl"), cl::Hidden,
> + ? ? ? cl::init(false));
> +static cl::opt<bool>
> ?PollyViewer("polly-show",
> ? ? ? ?cl::desc("Enable the Polly DOT viewer in -O3"), cl::Hidden,
> ? ? ? ?cl::value_desc("Run the Polly DOT viewer at -O3"),
> @@ -124,8 +128,21 @@
> ? if (PollyOnlyPrinter)
> ? ? PM.add(polly::createDOTOnlyPrinterPass());
>
> - ?if (!DisableScheduler)
> - ? ?PM.add(polly::createIslScheduleOptimizerPass());
> + ?if (!DisableScheduler) {

Could you please avoid double negation: what about declaring
a bool EnableScheduler and then use that?

> + ? ?if (!UsePocc)
> + ? ? ?PM.add(polly::createIslScheduleOptimizerPass());
> + ? ?else {

Also here, please use the positive condition to avoid the negation:

if (UsePocc) {
  #ifdef SCOPLIB_FOUND
  etc.
} else {
  PM.add(polly::createIslScheduleOptimizerPass());
}

> +#ifdef SCOPLIB_FOUND
> + ? ? ?PM.add(polly::createPoccPass());
> +#else
> + ? ? ?errs() << "Polly is compiled without scoplib support. As scoplib is "
> + ? ? ? ? ? ? << "required to run PoCC, PoCC is also not available. Falling "
> + ? ? ? ? ? ? << "back to the isl optimizer.\n";
> + ? ? ?PM.add(polly::createIslScheduleOptimizerPass());
> +#endif
> + ? ?}
> +
> + ?}
>
> ? if (!DisableCodegen)
> ? ? PM.add(polly::createCodeGenerationPass());
>
> Modified: polly/trunk/www/example_load_Polly_into_clang.html
> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/example_load_Polly_into_clang.html?rev=142773&r1=142772&r2=142773&view=diff
> ==============================================================================
> --- polly/trunk/www/example_load_Polly_into_clang.html (original)
> +++ polly/trunk/www/example_load_Polly_into_clang.html Sun Oct 23 15:59:35 2011
> @@ -67,6 +67,13 @@
> ?Polly automatically runs a polyhedral optimizer to optimize the schedules. To
> ?disable it add the option '-polly-no-optimizer'.
>
> +<h3>Use the PoCC optimizer</h3>
> +Polly uses by default the isl scheduling optimizer, a new implementation of the
> +well known Pluto algorithm. The main reason for the isl scheduler being the
> +default is that it does not require any additional libraries or tools to be
> +installed. As the new scheduler may still have some bugs and because being
> +able to compare is good in general, it is possible to switch the used optimizer
> +back to PoCC. For this add the option '-polly-use-pocc'.
>
> ?</div>
> ?</body>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Sebastian Pop
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum


From grosbach at apple.com  Tue Nov 15 15:45:56 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 21:45:56 -0000
Subject: [llvm-commits] [llvm] r144701 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20111115214556.1CB8D2A6C131@llvm.org>

Author: grosbach
Date: Tue Nov 15 15:45:55 2011
New Revision: 144701

URL: http://llvm.org/viewvc/llvm-project?rev=144701&view=rev
Log:
ARM enclosing curly braces optional on one-register VLD/VST instruction lists.

'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144701&r1=144700&r2=144701&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 15 15:45:55 2011
@@ -2487,10 +2487,31 @@
 // parse a vector register list
 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
-  if(Parser.getTok().isNot(AsmToken::LCurly))
+  SMLoc S = Parser.getTok().getLoc();
+  // As an extension (to match gas), support a plain D register or Q register
+  // (without encosing curly braces) as a single or double entry list,
+  // respectively.
+  if (Parser.getTok().is(AsmToken::Identifier)) {
+    int Reg = tryParseRegister();
+    if (Reg == -1)
+      return MatchOperand_NoMatch;
+    SMLoc E = Parser.getTok().getLoc();
+    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
+      Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, S, E));
+      return MatchOperand_Success;
+    }
+    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
+      Reg = getDRegFromQReg(Reg);
+      Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, S, E));
+      return MatchOperand_Success;
+    }
+    Error(S, "vector register expected");
+    return MatchOperand_ParseFail;
+  }
+
+  if (Parser.getTok().isNot(AsmToken::LCurly))
     return MatchOperand_NoMatch;
 
-  SMLoc S = Parser.getTok().getLoc();
   Parser.Lex(); // Eat '{' token.
   SMLoc RegLoc = Parser.getTok().getLoc();
 



From peter_cooper at apple.com  Tue Nov 15 15:57:53 2011
From: peter_cooper at apple.com (Pete Cooper)
Date: Tue, 15 Nov 2011 21:57:53 -0000
Subject: [llvm-commits] [llvm] r144705 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp
 test/CodeGen/X86/dec-eflags-lower.ll
Message-ID: <20111115215753.791CE2A6C131@llvm.org>

Author: pete
Date: Tue Nov 15 15:57:53 2011
New Revision: 144705

URL: http://llvm.org/viewvc/llvm-project?rev=144705&view=rev
Log:
Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
by later instructions.

Only done for DEC64m right now.

Fixes <rdar://problem/6172640>

Added:
    llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=144705&r1=144704&r2=144705&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Nov 15 15:57:53 2011
@@ -948,6 +948,11 @@
     if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
       return NULL;
 
+    // unfolding an x86 DEC64m operation results in store, dec, load which
+    // can't be handled here so quit
+    if (NewNodes.size() == 3)
+      return NULL;
+
     DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n");
     assert(NewNodes.size() == 2 && "Expected a load folding node!");
 

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=144705&r1=144704&r2=144705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Nov 15 15:57:53 2011
@@ -2216,6 +2216,63 @@
     }
     break;
   }
+  case ISD::STORE: {
+    StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
+    SDValue Chain = StoreNode->getOperand(0);
+    SDValue StoredVal = StoreNode->getOperand(1);
+    SDValue Address = StoreNode->getOperand(2);
+    SDValue Undef = StoreNode->getOperand(3);
+
+    if (StoreNode->getMemOperand()->getSize() != 8 ||
+        Undef->getOpcode() != ISD::UNDEF ||
+        Chain->getOpcode() != ISD::LOAD ||
+        StoredVal->getOpcode() != X86ISD::DEC ||
+        StoredVal.getResNo() != 0 ||
+        StoredVal->getOperand(0).getNode() != Chain.getNode())
+      break;
+
+    //OPC_CheckPredicate, 1, // Predicate_nontemporalstore
+    if (StoreNode->isNonTemporal())
+      break;
+
+    LoadSDNode *LoadNode = cast<LoadSDNode>(Chain.getNode());
+    if (LoadNode->getOperand(1) != Address ||
+        LoadNode->getOperand(2) != Undef)
+      break;
+
+    if (!ISD::isNormalLoad(LoadNode))
+      break;
+
+    if (!ISD::isNormalStore(StoreNode))
+      break;
+
+    // check load chain has only one use (from the store)
+    if (!Chain.hasOneUse())
+      break;
+
+    // Merge the input chains if they are not intra-pattern references.
+    SDValue InputChain = LoadNode->getOperand(0);
+
+    SDValue Base, Scale, Index, Disp, Segment;
+    if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
+                    Base, Scale, Index, Disp, Segment))
+      break;
+
+    MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
+    MemOp[0] = StoreNode->getMemOperand();
+    MemOp[1] = LoadNode->getMemOperand();
+    const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
+    MachineSDNode *Result = CurDAG->getMachineNode(X86::DEC64m,
+                                                   Node->getDebugLoc(),
+                                                   MVT::i32, MVT::Other, Ops,
+                                                   array_lengthof(Ops));
+    Result->setMemRefs(MemOp, MemOp + 2);
+
+    ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
+    ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
+
+    return Result;
+  }
   }
 
   SDNode *ResNode = SelectCode(Node);

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144705&r1=144704&r2=144705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Nov 15 15:57:53 2011
@@ -8263,8 +8263,10 @@
     // climbing the DAG back to the root, and it doesn't seem to be worth the
     // effort.
     for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
-           UE = Op.getNode()->use_end(); UI != UE; ++UI)
-      if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
+         UE = Op.getNode()->use_end(); UI != UE; ++UI)
+      if (UI->getOpcode() != ISD::CopyToReg &&
+          UI->getOpcode() != ISD::SETCC &&
+          UI->getOpcode() != ISD::STORE)
         goto default_case;
 
     if (ConstantSDNode *C =

Added: llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll?rev=144705&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll (added)
+++ llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll Tue Nov 15 15:57:53 2011
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+%struct.obj = type { i64 }
+
+define void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
+entry:
+; CHECK: decq	(%rdi)
+; CHECK-NEXT: je
+  %refcnt = getelementptr inbounds %struct.obj* %o, i64 0, i32 0
+  %0 = load i64* %refcnt, align 8, !tbaa !0
+  %dec = add i64 %0, -1
+  store i64 %dec, i64* %refcnt, align 8, !tbaa !0
+  %tobool = icmp eq i64 %dec, 0
+  br i1 %tobool, label %if.end, label %return
+
+if.end:                                           ; preds = %entry
+  %1 = bitcast %struct.obj* %o to i8*
+  tail call void @free(i8* %1)
+  br label %return
+
+return:                                           ; preds = %entry, %if.end
+  ret void
+}
+
+declare void @free(i8* nocapture) nounwind
+
+!0 = metadata !{metadata !"long", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}



From grosbach at apple.com  Tue Nov 15 16:03:22 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 14:03:22 -0800
Subject: [llvm-commits] [llvm] r144475 - in /llvm/trunk:
 include/llvm/CodeGen/LinkAllCodegenComponents.h
 include/llvm/CodeGen/Passes.h lib/CodeGen/CMakeLists.txt
 lib/CodeGen/Passes.cpp lib/CodeGen/RegAllocLinearScan.cpp
In-Reply-To: <20111112223945.759071BE001@llvm.org>
References: <20111112223945.759071BE001@llvm.org>
Message-ID: <BFFAB602-9A0D-42C9-8E90-CB2E1E00CE13@apple.com>

And there was much rejoicing! It's been a long time coming. Grats on making it happen.

-j

On Nov 12, 2011, at 2:39 PM, Jakob Stoklund Olesen wrote:

> Author: stoklund
> Date: Sat Nov 12 16:39:45 2011
> New Revision: 144475
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=144475&view=rev
> Log:
> Delete the linear scan register allocator.
> 
> RegAllocGreedy has been the default for six months now.
> 
> Deleting RegAllocLinearScan makes it possible to also delete
> VirtRegRewriter and clean up the spiller code.
> 
> Removed:
>    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
> Modified:
>    llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
>    llvm/trunk/include/llvm/CodeGen/Passes.h
>    llvm/trunk/lib/CodeGen/CMakeLists.txt
>    llvm/trunk/lib/CodeGen/Passes.cpp
> 
> Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=144475&r1=144474&r2=144475&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Sat Nov 12 16:39:45 2011
> @@ -35,7 +35,6 @@
> 
>       (void) llvm::createFastRegisterAllocator();
>       (void) llvm::createBasicRegisterAllocator();
> -      (void) llvm::createLinearScanRegisterAllocator();
>       (void) llvm::createGreedyRegisterAllocator();
>       (void) llvm::createDefaultPBQPRegisterAllocator();
> 
> 
> Modified: llvm/trunk/include/llvm/CodeGen/Passes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=144475&r1=144474&r2=144475&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/Passes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/Passes.h Sat Nov 12 16:39:45 2011
> @@ -118,11 +118,6 @@
>   ///
>   FunctionPass *createGreedyRegisterAllocator();
> 
> -  /// LinearScanRegisterAllocation Pass - This pass implements the linear scan
> -  /// register allocation algorithm, a global register allocator.
> -  ///
> -  FunctionPass *createLinearScanRegisterAllocator();
> -
>   /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
>   /// Quadratic Prograaming (PBQP) based register allocator.
>   ///
> 
> Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=144475&r1=144474&r2=144475&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original)
> +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Sat Nov 12 16:39:45 2011
> @@ -70,7 +70,6 @@
>   RegAllocBasic.cpp
>   RegAllocFast.cpp
>   RegAllocGreedy.cpp
> -  RegAllocLinearScan.cpp
>   RegAllocPBQP.cpp
>   RegisterClassInfo.cpp
>   RegisterCoalescer.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/Passes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Passes.cpp?rev=144475&r1=144474&r2=144475&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/Passes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/Passes.cpp Sat Nov 12 16:39:45 2011
> @@ -55,11 +55,6 @@
>     RegisterRegAlloc::setDefault(RegAlloc);
>   }
> 
> -  // This forces linking of the linear scan register allocator,
> -  // so -regalloc=linearscan still works in clang.
> -  if (Ctor == createLinearScanRegisterAllocator)
> -    return createLinearScanRegisterAllocator();
> -
>   if (Ctor != createDefaultRegisterAllocator)
>     return Ctor();
> 
> 
> Removed: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=144474&view=auto
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (removed)
> @@ -1,1543 +0,0 @@
> -//===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
> -//
> -//                     The LLVM Compiler Infrastructure
> -//
> -// This file is distributed under the University of Illinois Open Source
> -// License. See LICENSE.TXT for details.
> -//
> -//===----------------------------------------------------------------------===//
> -//
> -// This file implements a linear scan register allocator.
> -//
> -//===----------------------------------------------------------------------===//
> -
> -#define DEBUG_TYPE "regalloc"
> -#include "LiveDebugVariables.h"
> -#include "LiveRangeEdit.h"
> -#include "VirtRegMap.h"
> -#include "VirtRegRewriter.h"
> -#include "RegisterClassInfo.h"
> -#include "Spiller.h"
> -#include "llvm/Analysis/AliasAnalysis.h"
> -#include "llvm/Function.h"
> -#include "llvm/CodeGen/CalcSpillWeights.h"
> -#include "llvm/CodeGen/LiveIntervalAnalysis.h"
> -#include "llvm/CodeGen/MachineFunctionPass.h"
> -#include "llvm/CodeGen/MachineInstr.h"
> -#include "llvm/CodeGen/MachineLoopInfo.h"
> -#include "llvm/CodeGen/MachineRegisterInfo.h"
> -#include "llvm/CodeGen/Passes.h"
> -#include "llvm/CodeGen/RegAllocRegistry.h"
> -#include "llvm/Target/TargetRegisterInfo.h"
> -#include "llvm/Target/TargetMachine.h"
> -#include "llvm/Target/TargetOptions.h"
> -#include "llvm/Target/TargetInstrInfo.h"
> -#include "llvm/ADT/EquivalenceClasses.h"
> -#include "llvm/ADT/SmallSet.h"
> -#include "llvm/ADT/Statistic.h"
> -#include "llvm/ADT/STLExtras.h"
> -#include "llvm/Support/Debug.h"
> -#include "llvm/Support/ErrorHandling.h"
> -#include "llvm/Support/raw_ostream.h"
> -#include <algorithm>
> -#include <queue>
> -#include <memory>
> -#include <cmath>
> -
> -using namespace llvm;
> -
> -STATISTIC(NumIters     , "Number of iterations performed");
> -STATISTIC(NumBacktracks, "Number of times we had to backtrack");
> -STATISTIC(NumCoalesce,   "Number of copies coalesced");
> -STATISTIC(NumDowngrade,  "Number of registers downgraded");
> -
> -static cl::opt<bool>
> -NewHeuristic("new-spilling-heuristic",
> -             cl::desc("Use new spilling heuristic"),
> -             cl::init(false), cl::Hidden);
> -
> -static cl::opt<bool>
> -TrivCoalesceEnds("trivial-coalesce-ends",
> -                  cl::desc("Attempt trivial coalescing of interval ends"),
> -                  cl::init(false), cl::Hidden);
> -
> -static cl::opt<bool>
> -AvoidWAWHazard("avoid-waw-hazard",
> -               cl::desc("Avoid write-write hazards for some register classes"),
> -               cl::init(false), cl::Hidden);
> -
> -static RegisterRegAlloc
> -linearscanRegAlloc("linearscan", "linear scan register allocator",
> -                   createLinearScanRegisterAllocator);
> -
> -namespace {
> -  // When we allocate a register, add it to a fixed-size queue of
> -  // registers to skip in subsequent allocations. This trades a small
> -  // amount of register pressure and increased spills for flexibility in
> -  // the post-pass scheduler.
> -  //
> -  // Note that in a the number of registers used for reloading spills
> -  // will be one greater than the value of this option.
> -  //
> -  // One big limitation of this is that it doesn't differentiate between
> -  // different register classes. So on x86-64, if there is xmm register
> -  // pressure, it can caused fewer GPRs to be held in the queue.
> -  static cl::opt<unsigned>
> -  NumRecentlyUsedRegs("linearscan-skip-count",
> -                      cl::desc("Number of registers for linearscan to remember"
> -                               "to skip."),
> -                      cl::init(0),
> -                      cl::Hidden);
> -
> -  struct RALinScan : public MachineFunctionPass {
> -    static char ID;
> -    RALinScan() : MachineFunctionPass(ID) {
> -      initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
> -      initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
> -      initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
> -      initializeRegisterCoalescerPass(
> -        *PassRegistry::getPassRegistry());
> -      initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
> -      initializeLiveStacksPass(*PassRegistry::getPassRegistry());
> -      initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
> -      initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
> -      initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
> -      initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
> -      
> -      // Initialize the queue to record recently-used registers.
> -      if (NumRecentlyUsedRegs > 0)
> -        RecentRegs.resize(NumRecentlyUsedRegs, 0);
> -      RecentNext = RecentRegs.begin();
> -      avoidWAW_ = 0;
> -    }
> -
> -    typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
> -    typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
> -  private:
> -    /// RelatedRegClasses - This structure is built the first time a function is
> -    /// compiled, and keeps track of which register classes have registers that
> -    /// belong to multiple classes or have aliases that are in other classes.
> -    EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
> -    DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
> -
> -    // NextReloadMap - For each register in the map, it maps to the another
> -    // register which is defined by a reload from the same stack slot and
> -    // both reloads are in the same basic block.
> -    DenseMap<unsigned, unsigned> NextReloadMap;
> -
> -    // DowngradedRegs - A set of registers which are being "downgraded", i.e.
> -    // un-favored for allocation.
> -    SmallSet<unsigned, 8> DowngradedRegs;
> -
> -    // DowngradeMap - A map from virtual registers to physical registers being
> -    // downgraded for the virtual registers.
> -    DenseMap<unsigned, unsigned> DowngradeMap;
> -
> -    MachineFunction* mf_;
> -    MachineRegisterInfo* mri_;
> -    const TargetMachine* tm_;
> -    const TargetRegisterInfo* tri_;
> -    const TargetInstrInfo* tii_;
> -    BitVector allocatableRegs_;
> -    BitVector reservedRegs_;
> -    LiveIntervals* li_;
> -    MachineLoopInfo *loopInfo;
> -    RegisterClassInfo RegClassInfo;
> -
> -    /// handled_ - Intervals are added to the handled_ set in the order of their
> -    /// start value.  This is uses for backtracking.
> -    std::vector<LiveInterval*> handled_;
> -
> -    /// fixed_ - Intervals that correspond to machine registers.
> -    ///
> -    IntervalPtrs fixed_;
> -
> -    /// active_ - Intervals that are currently being processed, and which have a
> -    /// live range active for the current point.
> -    IntervalPtrs active_;
> -
> -    /// inactive_ - Intervals that are currently being processed, but which have
> -    /// a hold at the current point.
> -    IntervalPtrs inactive_;
> -
> -    typedef std::priority_queue<LiveInterval*,
> -                                SmallVector<LiveInterval*, 64>,
> -                                greater_ptr<LiveInterval> > IntervalHeap;
> -    IntervalHeap unhandled_;
> -
> -    /// regUse_ - Tracks register usage.
> -    SmallVector<unsigned, 32> regUse_;
> -    SmallVector<unsigned, 32> regUseBackUp_;
> -
> -    /// vrm_ - Tracks register assignments.
> -    VirtRegMap* vrm_;
> -
> -    std::auto_ptr<VirtRegRewriter> rewriter_;
> -
> -    std::auto_ptr<Spiller> spiller_;
> -
> -    // The queue of recently-used registers.
> -    SmallVector<unsigned, 4> RecentRegs;
> -    SmallVector<unsigned, 4>::iterator RecentNext;
> -
> -    // Last write-after-write register written.
> -    unsigned avoidWAW_;
> -
> -    // Record that we just picked this register.
> -    void recordRecentlyUsed(unsigned reg) {
> -      assert(reg != 0 && "Recently used register is NOREG!");
> -      if (!RecentRegs.empty()) {
> -        *RecentNext++ = reg;
> -        if (RecentNext == RecentRegs.end())
> -          RecentNext = RecentRegs.begin();
> -      }
> -    }
> -
> -  public:
> -    virtual const char* getPassName() const {
> -      return "Linear Scan Register Allocator";
> -    }
> -
> -    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
> -      AU.setPreservesCFG();
> -      AU.addRequired<AliasAnalysis>();
> -      AU.addPreserved<AliasAnalysis>();
> -      AU.addRequired<LiveIntervals>();
> -      AU.addPreserved<SlotIndexes>();
> -      if (StrongPHIElim)
> -        AU.addRequiredID(StrongPHIEliminationID);
> -      // Make sure PassManager knows which analyses to make available
> -      // to coalescing and which analyses coalescing invalidates.
> -      AU.addRequiredTransitiveID(RegisterCoalescerPassID);
> -      AU.addRequired<CalculateSpillWeights>();
> -      AU.addRequiredID(LiveStacksID);
> -      AU.addPreservedID(LiveStacksID);
> -      AU.addRequired<MachineLoopInfo>();
> -      AU.addPreserved<MachineLoopInfo>();
> -      AU.addRequired<VirtRegMap>();
> -      AU.addPreserved<VirtRegMap>();
> -      AU.addRequired<LiveDebugVariables>();
> -      AU.addPreserved<LiveDebugVariables>();
> -      AU.addRequiredID(MachineDominatorsID);
> -      AU.addPreservedID(MachineDominatorsID);
> -      MachineFunctionPass::getAnalysisUsage(AU);
> -    }
> -
> -    /// runOnMachineFunction - register allocate the whole function
> -    bool runOnMachineFunction(MachineFunction&);
> -
> -    // Determine if we skip this register due to its being recently used.
> -    bool isRecentlyUsed(unsigned reg) const {
> -      return reg == avoidWAW_ ||
> -       std::find(RecentRegs.begin(), RecentRegs.end(), reg) != RecentRegs.end();
> -    }
> -
> -  private:
> -    /// linearScan - the linear scan algorithm
> -    void linearScan();
> -
> -    /// initIntervalSets - initialize the interval sets.
> -    ///
> -    void initIntervalSets();
> -
> -    /// processActiveIntervals - expire old intervals and move non-overlapping
> -    /// ones to the inactive list.
> -    void processActiveIntervals(SlotIndex CurPoint);
> -
> -    /// processInactiveIntervals - expire old intervals and move overlapping
> -    /// ones to the active list.
> -    void processInactiveIntervals(SlotIndex CurPoint);
> -
> -    /// hasNextReloadInterval - Return the next liveinterval that's being
> -    /// defined by a reload from the same SS as the specified one.
> -    LiveInterval *hasNextReloadInterval(LiveInterval *cur);
> -
> -    /// DowngradeRegister - Downgrade a register for allocation.
> -    void DowngradeRegister(LiveInterval *li, unsigned Reg);
> -
> -    /// UpgradeRegister - Upgrade a register for allocation.
> -    void UpgradeRegister(unsigned Reg);
> -
> -    /// assignRegOrStackSlotAtInterval - assign a register if one
> -    /// is available, or spill.
> -    void assignRegOrStackSlotAtInterval(LiveInterval* cur);
> -
> -    void updateSpillWeights(std::vector<float> &Weights,
> -                            unsigned reg, float weight,
> -                            const TargetRegisterClass *RC);
> -
> -    /// findIntervalsToSpill - Determine the intervals to spill for the
> -    /// specified interval. It's passed the physical registers whose spill
> -    /// weight is the lowest among all the registers whose live intervals
> -    /// conflict with the interval.
> -    void findIntervalsToSpill(LiveInterval *cur,
> -                            std::vector<std::pair<unsigned,float> > &Candidates,
> -                            unsigned NumCands,
> -                            SmallVector<LiveInterval*, 8> &SpillIntervals);
> -
> -    /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
> -    /// try to allocate the definition to the same register as the source,
> -    /// if the register is not defined during the life time of the interval.
> -    /// This eliminates a copy, and is used to coalesce copies which were not
> -    /// coalesced away before allocation either due to dest and src being in
> -    /// different register classes or because the coalescer was overly
> -    /// conservative.
> -    unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
> -
> -    ///
> -    /// Register usage / availability tracking helpers.
> -    ///
> -
> -    void initRegUses() {
> -      regUse_.resize(tri_->getNumRegs(), 0);
> -      regUseBackUp_.resize(tri_->getNumRegs(), 0);
> -    }
> -
> -    void finalizeRegUses() {
> -#ifndef NDEBUG
> -      // Verify all the registers are "freed".
> -      bool Error = false;
> -      for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
> -        if (regUse_[i] != 0) {
> -          dbgs() << tri_->getName(i) << " is still in use!\n";
> -          Error = true;
> -        }
> -      }
> -      if (Error)
> -        llvm_unreachable(0);
> -#endif
> -      regUse_.clear();
> -      regUseBackUp_.clear();
> -    }
> -
> -    void addRegUse(unsigned physReg) {
> -      assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
> -             "should be physical register!");
> -      ++regUse_[physReg];
> -      for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
> -        ++regUse_[*as];
> -    }
> -
> -    void delRegUse(unsigned physReg) {
> -      assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
> -             "should be physical register!");
> -      assert(regUse_[physReg] != 0);
> -      --regUse_[physReg];
> -      for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
> -        assert(regUse_[*as] != 0);
> -        --regUse_[*as];
> -      }
> -    }
> -
> -    bool isRegAvail(unsigned physReg) const {
> -      assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
> -             "should be physical register!");
> -      return regUse_[physReg] == 0;
> -    }
> -
> -    void backUpRegUses() {
> -      regUseBackUp_ = regUse_;
> -    }
> -
> -    void restoreRegUses() {
> -      regUse_ = regUseBackUp_;
> -    }
> -
> -    ///
> -    /// Register handling helpers.
> -    ///
> -
> -    /// getFreePhysReg - return a free physical register for this virtual
> -    /// register interval if we have one, otherwise return 0.
> -    unsigned getFreePhysReg(LiveInterval* cur);
> -    unsigned getFreePhysReg(LiveInterval* cur,
> -                            const TargetRegisterClass *RC,
> -                            unsigned MaxInactiveCount,
> -                            SmallVector<unsigned, 256> &inactiveCounts,
> -                            bool SkipDGRegs);
> -
> -    /// getFirstNonReservedPhysReg - return the first non-reserved physical
> -    /// register in the register class.
> -    unsigned getFirstNonReservedPhysReg(const TargetRegisterClass *RC) {
> -      ArrayRef<unsigned> O = RegClassInfo.getOrder(RC);
> -      assert(!O.empty() && "All registers reserved?!");
> -      return O.front();
> -    }
> -
> -    void ComputeRelatedRegClasses();
> -
> -    template <typename ItTy>
> -    void printIntervals(const char* const str, ItTy i, ItTy e) const {
> -      DEBUG({
> -          if (str)
> -            dbgs() << str << " intervals:\n";
> -
> -          for (; i != e; ++i) {
> -            dbgs() << '\t' << *i->first << " -> ";
> -
> -            unsigned reg = i->first->reg;
> -            if (TargetRegisterInfo::isVirtualRegister(reg))
> -              reg = vrm_->getPhys(reg);
> -
> -            dbgs() << tri_->getName(reg) << '\n';
> -          }
> -        });
> -    }
> -  };
> -  char RALinScan::ID = 0;
> -}
> -
> -INITIALIZE_PASS_BEGIN(RALinScan, "linearscan-regalloc",
> -                      "Linear Scan Register Allocator", false, false)
> -INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
> -INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
> -INITIALIZE_PASS_DEPENDENCY(CalculateSpillWeights)
> -INITIALIZE_PASS_DEPENDENCY(LiveStacks)
> -INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
> -INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
> -INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
> -INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
> -INITIALIZE_PASS_END(RALinScan, "linearscan-regalloc",
> -                    "Linear Scan Register Allocator", false, false)
> -
> -void RALinScan::ComputeRelatedRegClasses() {
> -  // First pass, add all reg classes to the union, and determine at least one
> -  // reg class that each register is in.
> -  bool HasAliases = false;
> -  for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
> -       E = tri_->regclass_end(); RCI != E; ++RCI) {
> -    RelatedRegClasses.insert(*RCI);
> -    for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
> -         I != E; ++I) {
> -      HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
> -
> -      const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
> -      if (PRC) {
> -        // Already processed this register.  Just make sure we know that
> -        // multiple register classes share a register.
> -        RelatedRegClasses.unionSets(PRC, *RCI);
> -      } else {
> -        PRC = *RCI;
> -      }
> -    }
> -  }
> -
> -  // Second pass, now that we know conservatively what register classes each reg
> -  // belongs to, add info about aliases.  We don't need to do this for targets
> -  // without register aliases.
> -  if (HasAliases)
> -    for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
> -         I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
> -         I != E; ++I)
> -      for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS) {
> -        const TargetRegisterClass *AliasClass = 
> -          OneClassForEachPhysReg.lookup(*AS);
> -        if (AliasClass)
> -          RelatedRegClasses.unionSets(I->second, AliasClass);
> -      }
> -}
> -
> -/// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
> -/// allocate the definition the same register as the source register if the
> -/// register is not defined during live time of the interval. If the interval is
> -/// killed by a copy, try to use the destination register. This eliminates a
> -/// copy. This is used to coalesce copies which were not coalesced away before
> -/// allocation either due to dest and src being in different register classes or
> -/// because the coalescer was overly conservative.
> -unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
> -  unsigned Preference = vrm_->getRegAllocPref(cur.reg);
> -  if ((Preference && Preference == Reg) || !cur.containsOneValue())
> -    return Reg;
> -
> -  // We cannot handle complicated live ranges. Simple linear stuff only.
> -  if (cur.ranges.size() != 1)
> -    return Reg;
> -
> -  const LiveRange &range = cur.ranges.front();
> -
> -  VNInfo *vni = range.valno;
> -  if (vni->isUnused() || !vni->def.isValid())
> -    return Reg;
> -
> -  unsigned CandReg;
> -  {
> -    MachineInstr *CopyMI;
> -    if ((CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
> -      // Defined by a copy, try to extend SrcReg forward
> -      CandReg = CopyMI->getOperand(1).getReg();
> -    else if (TrivCoalesceEnds &&
> -            (CopyMI = li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
> -             CopyMI->isCopy() && cur.reg == CopyMI->getOperand(1).getReg())
> -      // Only used by a copy, try to extend DstReg backwards
> -      CandReg = CopyMI->getOperand(0).getReg();
> -    else
> -      return Reg;
> -
> -    // If the target of the copy is a sub-register then don't coalesce.
> -    if(CopyMI->getOperand(0).getSubReg())
> -      return Reg;
> -  }
> -
> -  if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
> -    if (!vrm_->isAssignedReg(CandReg))
> -      return Reg;
> -    CandReg = vrm_->getPhys(CandReg);
> -  }
> -  if (Reg == CandReg)
> -    return Reg;
> -
> -  const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
> -  if (!RC->contains(CandReg))
> -    return Reg;
> -
> -  if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
> -    return Reg;
> -
> -  // Try to coalesce.
> -  DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
> -        << '\n');
> -  vrm_->clearVirt(cur.reg);
> -  vrm_->assignVirt2Phys(cur.reg, CandReg);
> -
> -  ++NumCoalesce;
> -  return CandReg;
> -}
> -
> -bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
> -  mf_ = &fn;
> -  mri_ = &fn.getRegInfo();
> -  tm_ = &fn.getTarget();
> -  tri_ = tm_->getRegisterInfo();
> -  tii_ = tm_->getInstrInfo();
> -  allocatableRegs_ = tri_->getAllocatableSet(fn);
> -  reservedRegs_ = tri_->getReservedRegs(fn);
> -  li_ = &getAnalysis<LiveIntervals>();
> -  loopInfo = &getAnalysis<MachineLoopInfo>();
> -  RegClassInfo.runOnMachineFunction(fn);
> -
> -  // We don't run the coalescer here because we have no reason to
> -  // interact with it.  If the coalescer requires interaction, it
> -  // won't do anything.  If it doesn't require interaction, we assume
> -  // it was run as a separate pass.
> -
> -  // If this is the first function compiled, compute the related reg classes.
> -  if (RelatedRegClasses.empty())
> -    ComputeRelatedRegClasses();
> -
> -  // Also resize register usage trackers.
> -  initRegUses();
> -
> -  vrm_ = &getAnalysis<VirtRegMap>();
> -  if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
> -
> -  spiller_.reset(createSpiller(*this, *mf_, *vrm_));
> -
> -  initIntervalSets();
> -
> -  linearScan();
> -
> -  // Rewrite spill code and update the PhysRegsUsed set.
> -  rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
> -
> -  // Write out new DBG_VALUE instructions.
> -  getAnalysis<LiveDebugVariables>().emitDebugValues(vrm_);
> -
> -  assert(unhandled_.empty() && "Unhandled live intervals remain!");
> -
> -  finalizeRegUses();
> -
> -  fixed_.clear();
> -  active_.clear();
> -  inactive_.clear();
> -  handled_.clear();
> -  NextReloadMap.clear();
> -  DowngradedRegs.clear();
> -  DowngradeMap.clear();
> -  spiller_.reset(0);
> -
> -  return true;
> -}
> -
> -/// initIntervalSets - initialize the interval sets.
> -///
> -void RALinScan::initIntervalSets()
> -{
> -  assert(unhandled_.empty() && fixed_.empty() &&
> -         active_.empty() && inactive_.empty() &&
> -         "interval sets should be empty on initialization");
> -
> -  handled_.reserve(li_->getNumIntervals());
> -
> -  for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
> -    if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
> -      if (!i->second->empty() && allocatableRegs_.test(i->second->reg)) {
> -        mri_->setPhysRegUsed(i->second->reg);
> -        fixed_.push_back(std::make_pair(i->second, i->second->begin()));
> -      }
> -    } else {
> -      if (i->second->empty()) {
> -        assignRegOrStackSlotAtInterval(i->second);
> -      }
> -      else
> -        unhandled_.push(i->second);
> -    }
> -  }
> -}
> -
> -void RALinScan::linearScan() {
> -  // linear scan algorithm
> -  DEBUG({
> -      dbgs() << "********** LINEAR SCAN **********\n"
> -             << "********** Function: "
> -             << mf_->getFunction()->getName() << '\n';
> -      printIntervals("fixed", fixed_.begin(), fixed_.end());
> -    });
> -
> -  while (!unhandled_.empty()) {
> -    // pick the interval with the earliest start point
> -    LiveInterval* cur = unhandled_.top();
> -    unhandled_.pop();
> -    ++NumIters;
> -    DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
> -
> -    assert(!cur->empty() && "Empty interval in unhandled set.");
> -
> -    processActiveIntervals(cur->beginIndex());
> -    processInactiveIntervals(cur->beginIndex());
> -
> -    assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
> -           "Can only allocate virtual registers!");
> -
> -    // Allocating a virtual register. try to find a free
> -    // physical register or spill an interval (possibly this one) in order to
> -    // assign it one.
> -    assignRegOrStackSlotAtInterval(cur);
> -
> -    DEBUG({
> -        printIntervals("active", active_.begin(), active_.end());
> -        printIntervals("inactive", inactive_.begin(), inactive_.end());
> -      });
> -  }
> -
> -  // Expire any remaining active intervals
> -  while (!active_.empty()) {
> -    IntervalPtr &IP = active_.back();
> -    unsigned reg = IP.first->reg;
> -    DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
> -    assert(TargetRegisterInfo::isVirtualRegister(reg) &&
> -           "Can only allocate virtual registers!");
> -    reg = vrm_->getPhys(reg);
> -    delRegUse(reg);
> -    active_.pop_back();
> -  }
> -
> -  // Expire any remaining inactive intervals
> -  DEBUG({
> -      for (IntervalPtrs::reverse_iterator
> -             i = inactive_.rbegin(); i != inactive_.rend(); ++i)
> -        dbgs() << "\tinterval " << *i->first << " expired\n";
> -    });
> -  inactive_.clear();
> -
> -  // Add live-ins to every BB except for entry. Also perform trivial coalescing.
> -  MachineFunction::iterator EntryMBB = mf_->begin();
> -  SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
> -  for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
> -    LiveInterval &cur = *i->second;
> -    unsigned Reg = 0;
> -    bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
> -    if (isPhys)
> -      Reg = cur.reg;
> -    else if (vrm_->isAssignedReg(cur.reg))
> -      Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
> -    if (!Reg)
> -      continue;
> -    // Ignore splited live intervals.
> -    if (!isPhys && vrm_->getPreSplitReg(cur.reg))
> -      continue;
> -
> -    for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
> -         I != E; ++I) {
> -      const LiveRange &LR = *I;
> -      if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
> -        for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
> -          if (LiveInMBBs[i] != EntryMBB) {
> -            assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
> -                   "Adding a virtual register to livein set?");
> -            LiveInMBBs[i]->addLiveIn(Reg);
> -          }
> -        LiveInMBBs.clear();
> -      }
> -    }
> -  }
> -
> -  DEBUG(dbgs() << *vrm_);
> -
> -  // Look for physical registers that end up not being allocated even though
> -  // register allocator had to spill other registers in its register class.
> -  if (!vrm_->FindUnusedRegisters(li_))
> -    return;
> -}
> -
> -/// processActiveIntervals - expire old intervals and move non-overlapping ones
> -/// to the inactive list.
> -void RALinScan::processActiveIntervals(SlotIndex CurPoint)
> -{
> -  DEBUG(dbgs() << "\tprocessing active intervals:\n");
> -
> -  for (unsigned i = 0, e = active_.size(); i != e; ++i) {
> -    LiveInterval *Interval = active_[i].first;
> -    LiveInterval::iterator IntervalPos = active_[i].second;
> -    unsigned reg = Interval->reg;
> -
> -    IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
> -
> -    if (IntervalPos == Interval->end()) {     // Remove expired intervals.
> -      DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
> -      assert(TargetRegisterInfo::isVirtualRegister(reg) &&
> -             "Can only allocate virtual registers!");
> -      reg = vrm_->getPhys(reg);
> -      delRegUse(reg);
> -
> -      // Pop off the end of the list.
> -      active_[i] = active_.back();
> -      active_.pop_back();
> -      --i; --e;
> -
> -    } else if (IntervalPos->start > CurPoint) {
> -      // Move inactive intervals to inactive list.
> -      DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
> -      assert(TargetRegisterInfo::isVirtualRegister(reg) &&
> -             "Can only allocate virtual registers!");
> -      reg = vrm_->getPhys(reg);
> -      delRegUse(reg);
> -      // add to inactive.
> -      inactive_.push_back(std::make_pair(Interval, IntervalPos));
> -
> -      // Pop off the end of the list.
> -      active_[i] = active_.back();
> -      active_.pop_back();
> -      --i; --e;
> -    } else {
> -      // Otherwise, just update the iterator position.
> -      active_[i].second = IntervalPos;
> -    }
> -  }
> -}
> -
> -/// processInactiveIntervals - expire old intervals and move overlapping
> -/// ones to the active list.
> -void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
> -{
> -  DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
> -
> -  for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
> -    LiveInterval *Interval = inactive_[i].first;
> -    LiveInterval::iterator IntervalPos = inactive_[i].second;
> -    unsigned reg = Interval->reg;
> -
> -    IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
> -
> -    if (IntervalPos == Interval->end()) {       // remove expired intervals.
> -      DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
> -
> -      // Pop off the end of the list.
> -      inactive_[i] = inactive_.back();
> -      inactive_.pop_back();
> -      --i; --e;
> -    } else if (IntervalPos->start <= CurPoint) {
> -      // move re-activated intervals in active list
> -      DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
> -      assert(TargetRegisterInfo::isVirtualRegister(reg) &&
> -             "Can only allocate virtual registers!");
> -      reg = vrm_->getPhys(reg);
> -      addRegUse(reg);
> -      // add to active
> -      active_.push_back(std::make_pair(Interval, IntervalPos));
> -
> -      // Pop off the end of the list.
> -      inactive_[i] = inactive_.back();
> -      inactive_.pop_back();
> -      --i; --e;
> -    } else {
> -      // Otherwise, just update the iterator position.
> -      inactive_[i].second = IntervalPos;
> -    }
> -  }
> -}
> -
> -/// updateSpillWeights - updates the spill weights of the specifed physical
> -/// register and its weight.
> -void RALinScan::updateSpillWeights(std::vector<float> &Weights,
> -                                   unsigned reg, float weight,
> -                                   const TargetRegisterClass *RC) {
> -  SmallSet<unsigned, 4> Processed;
> -  SmallSet<unsigned, 4> SuperAdded;
> -  SmallVector<unsigned, 4> Supers;
> -  Weights[reg] += weight;
> -  Processed.insert(reg);
> -  for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
> -    Weights[*as] += weight;
> -    Processed.insert(*as);
> -    if (tri_->isSubRegister(*as, reg) &&
> -        SuperAdded.insert(*as) &&
> -        RC->contains(*as)) {
> -      Supers.push_back(*as);
> -    }
> -  }
> -
> -  // If the alias is a super-register, and the super-register is in the
> -  // register class we are trying to allocate. Then add the weight to all
> -  // sub-registers of the super-register even if they are not aliases.
> -  // e.g. allocating for GR32, bh is not used, updating bl spill weight.
> -  //      bl should get the same spill weight otherwise it will be chosen
> -  //      as a spill candidate since spilling bh doesn't make ebx available.
> -  for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
> -    for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
> -      if (!Processed.count(*sr))
> -        Weights[*sr] += weight;
> -  }
> -}
> -
> -static
> -RALinScan::IntervalPtrs::iterator
> -FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
> -  for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
> -       I != E; ++I)
> -    if (I->first == LI) return I;
> -  return IP.end();
> -}
> -
> -static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V,
> -                                    SlotIndex Point){
> -  for (unsigned i = 0, e = V.size(); i != e; ++i) {
> -    RALinScan::IntervalPtr &IP = V[i];
> -    LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
> -                                                IP.second, Point);
> -    if (I != IP.first->begin()) --I;
> -    IP.second = I;
> -  }
> -}
> -
> -/// getConflictWeight - Return the number of conflicts between cur
> -/// live interval and defs and uses of Reg weighted by loop depthes.
> -static
> -float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
> -                        MachineRegisterInfo *mri_,
> -                        MachineLoopInfo *loopInfo) {
> -  float Conflicts = 0;
> -  for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
> -         E = mri_->reg_end(); I != E; ++I) {
> -    MachineInstr *MI = &*I;
> -    if (cur->liveAt(li_->getInstructionIndex(MI))) {
> -      unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
> -      Conflicts += std::pow(10.0f, (float)loopDepth);
> -    }
> -  }
> -  return Conflicts;
> -}
> -
> -/// findIntervalsToSpill - Determine the intervals to spill for the
> -/// specified interval. It's passed the physical registers whose spill
> -/// weight is the lowest among all the registers whose live intervals
> -/// conflict with the interval.
> -void RALinScan::findIntervalsToSpill(LiveInterval *cur,
> -                            std::vector<std::pair<unsigned,float> > &Candidates,
> -                            unsigned NumCands,
> -                            SmallVector<LiveInterval*, 8> &SpillIntervals) {
> -  // We have figured out the *best* register to spill. But there are other
> -  // registers that are pretty good as well (spill weight within 3%). Spill
> -  // the one that has fewest defs and uses that conflict with cur.
> -  float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
> -  SmallVector<LiveInterval*, 8> SLIs[3];
> -
> -  DEBUG({
> -      dbgs() << "\tConsidering " << NumCands << " candidates: ";
> -      for (unsigned i = 0; i != NumCands; ++i)
> -        dbgs() << tri_->getName(Candidates[i].first) << " ";
> -      dbgs() << "\n";
> -    });
> -
> -  // Calculate the number of conflicts of each candidate.
> -  for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
> -    unsigned Reg = i->first->reg;
> -    unsigned PhysReg = vrm_->getPhys(Reg);
> -    if (!cur->overlapsFrom(*i->first, i->second))
> -      continue;
> -    for (unsigned j = 0; j < NumCands; ++j) {
> -      unsigned Candidate = Candidates[j].first;
> -      if (tri_->regsOverlap(PhysReg, Candidate)) {
> -        if (NumCands > 1)
> -          Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
> -        SLIs[j].push_back(i->first);
> -      }
> -    }
> -  }
> -
> -  for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
> -    unsigned Reg = i->first->reg;
> -    unsigned PhysReg = vrm_->getPhys(Reg);
> -    if (!cur->overlapsFrom(*i->first, i->second-1))
> -      continue;
> -    for (unsigned j = 0; j < NumCands; ++j) {
> -      unsigned Candidate = Candidates[j].first;
> -      if (tri_->regsOverlap(PhysReg, Candidate)) {
> -        if (NumCands > 1)
> -          Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
> -        SLIs[j].push_back(i->first);
> -      }
> -    }
> -  }
> -
> -  // Which is the best candidate?
> -  unsigned BestCandidate = 0;
> -  float MinConflicts = Conflicts[0];
> -  for (unsigned i = 1; i != NumCands; ++i) {
> -    if (Conflicts[i] < MinConflicts) {
> -      BestCandidate = i;
> -      MinConflicts = Conflicts[i];
> -    }
> -  }
> -
> -  std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
> -            std::back_inserter(SpillIntervals));
> -}
> -
> -namespace {
> -  struct WeightCompare {
> -  private:
> -    const RALinScan &Allocator;
> -
> -  public:
> -    WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}
> -
> -    typedef std::pair<unsigned, float> RegWeightPair;
> -    bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
> -      return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
> -    }
> -  };
> -}
> -
> -static bool weightsAreClose(float w1, float w2) {
> -  if (!NewHeuristic)
> -    return false;
> -
> -  float diff = w1 - w2;
> -  if (diff <= 0.02f)  // Within 0.02f
> -    return true;
> -  return (diff / w2) <= 0.05f;  // Within 5%.
> -}
> -
> -LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
> -  DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
> -  if (I == NextReloadMap.end())
> -    return 0;
> -  return &li_->getInterval(I->second);
> -}
> -
> -void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
> -  for (const unsigned *AS = tri_->getOverlaps(Reg); *AS; ++AS) {
> -    bool isNew = DowngradedRegs.insert(*AS);
> -    (void)isNew; // Silence compiler warning.
> -    assert(isNew && "Multiple reloads holding the same register?");
> -    DowngradeMap.insert(std::make_pair(li->reg, *AS));
> -  }
> -  ++NumDowngrade;
> -}
> -
> -void RALinScan::UpgradeRegister(unsigned Reg) {
> -  if (Reg) {
> -    DowngradedRegs.erase(Reg);
> -    for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
> -      DowngradedRegs.erase(*AS);
> -  }
> -}
> -
> -namespace {
> -  struct LISorter {
> -    bool operator()(LiveInterval* A, LiveInterval* B) {
> -      return A->beginIndex() < B->beginIndex();
> -    }
> -  };
> -}
> -
> -/// assignRegOrStackSlotAtInterval - assign a register if one is available, or
> -/// spill.
> -void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
> -  const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
> -  DEBUG(dbgs() << "\tallocating current interval from "
> -               << RC->getName() << ": ");
> -
> -  // This is an implicitly defined live interval, just assign any register.
> -  if (cur->empty()) {
> -    unsigned physReg = vrm_->getRegAllocPref(cur->reg);
> -    if (!physReg)
> -      physReg = getFirstNonReservedPhysReg(RC);
> -    DEBUG(dbgs() <<  tri_->getName(physReg) << '\n');
> -    // Note the register is not really in use.
> -    vrm_->assignVirt2Phys(cur->reg, physReg);
> -    return;
> -  }
> -
> -  backUpRegUses();
> -
> -  std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
> -  SlotIndex StartPosition = cur->beginIndex();
> -  const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
> -
> -  // If start of this live interval is defined by a move instruction and its
> -  // source is assigned a physical register that is compatible with the target
> -  // register class, then we should try to assign it the same register.
> -  // This can happen when the move is from a larger register class to a smaller
> -  // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
> -  if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
> -    VNInfo *vni = cur->begin()->valno;
> -    if (!vni->isUnused() && vni->def.isValid()) {
> -      MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
> -      if (CopyMI && CopyMI->isCopy()) {
> -        unsigned DstSubReg = CopyMI->getOperand(0).getSubReg();
> -        unsigned SrcReg = CopyMI->getOperand(1).getReg();
> -        unsigned SrcSubReg = CopyMI->getOperand(1).getSubReg();
> -        unsigned Reg = 0;
> -        if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
> -          Reg = SrcReg;
> -        else if (vrm_->isAssignedReg(SrcReg))
> -          Reg = vrm_->getPhys(SrcReg);
> -        if (Reg) {
> -          if (SrcSubReg)
> -            Reg = tri_->getSubReg(Reg, SrcSubReg);
> -          if (DstSubReg)
> -            Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
> -          if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
> -            mri_->setRegAllocationHint(cur->reg, 0, Reg);
> -        }
> -      }
> -    }
> -  }
> -
> -  // For every interval in inactive we overlap with, mark the
> -  // register as not free and update spill weights.
> -  for (IntervalPtrs::const_iterator i = inactive_.begin(),
> -         e = inactive_.end(); i != e; ++i) {
> -    unsigned Reg = i->first->reg;
> -    assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
> -           "Can only allocate virtual registers!");
> -    const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
> -    // If this is not in a related reg class to the register we're allocating,
> -    // don't check it.
> -    if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
> -        cur->overlapsFrom(*i->first, i->second-1)) {
> -      Reg = vrm_->getPhys(Reg);
> -      addRegUse(Reg);
> -      SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
> -    }
> -  }
> -
> -  // Speculatively check to see if we can get a register right now.  If not,
> -  // we know we won't be able to by adding more constraints.  If so, we can
> -  // check to see if it is valid.  Doing an exhaustive search of the fixed_ list
> -  // is very bad (it contains all callee clobbered registers for any functions
> -  // with a call), so we want to avoid doing that if possible.
> -  unsigned physReg = getFreePhysReg(cur);
> -  unsigned BestPhysReg = physReg;
> -  if (physReg) {
> -    // We got a register.  However, if it's in the fixed_ list, we might
> -    // conflict with it.  Check to see if we conflict with it or any of its
> -    // aliases.
> -    SmallSet<unsigned, 8> RegAliases;
> -    for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
> -      RegAliases.insert(*AS);
> -
> -    bool ConflictsWithFixed = false;
> -    for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
> -      IntervalPtr &IP = fixed_[i];
> -      if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
> -        // Okay, this reg is on the fixed list.  Check to see if we actually
> -        // conflict.
> -        LiveInterval *I = IP.first;
> -        if (I->endIndex() > StartPosition) {
> -          LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
> -          IP.second = II;
> -          if (II != I->begin() && II->start > StartPosition)
> -            --II;
> -          if (cur->overlapsFrom(*I, II)) {
> -            ConflictsWithFixed = true;
> -            break;
> -          }
> -        }
> -      }
> -    }
> -
> -    // Okay, the register picked by our speculative getFreePhysReg call turned
> -    // out to be in use.  Actually add all of the conflicting fixed registers to
> -    // regUse_ so we can do an accurate query.
> -    if (ConflictsWithFixed) {
> -      // For every interval in fixed we overlap with, mark the register as not
> -      // free and update spill weights.
> -      for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
> -        IntervalPtr &IP = fixed_[i];
> -        LiveInterval *I = IP.first;
> -
> -        const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
> -        if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
> -            I->endIndex() > StartPosition) {
> -          LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
> -          IP.second = II;
> -          if (II != I->begin() && II->start > StartPosition)
> -            --II;
> -          if (cur->overlapsFrom(*I, II)) {
> -            unsigned reg = I->reg;
> -            addRegUse(reg);
> -            SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
> -          }
> -        }
> -      }
> -
> -      // Using the newly updated regUse_ object, which includes conflicts in the
> -      // future, see if there are any registers available.
> -      physReg = getFreePhysReg(cur);
> -    }
> -  }
> -
> -  // Restore the physical register tracker, removing information about the
> -  // future.
> -  restoreRegUses();
> -
> -  // If we find a free register, we are done: assign this virtual to
> -  // the free physical register and add this interval to the active
> -  // list.
> -  if (physReg) {
> -    DEBUG(dbgs() <<  tri_->getName(physReg) << '\n');
> -    assert(RC->contains(physReg) && "Invalid candidate");
> -    vrm_->assignVirt2Phys(cur->reg, physReg);
> -    addRegUse(physReg);
> -    active_.push_back(std::make_pair(cur, cur->begin()));
> -    handled_.push_back(cur);
> -
> -    // Remember physReg for avoiding a write-after-write hazard in the next
> -    // instruction.
> -    if (AvoidWAWHazard &&
> -        tri_->avoidWriteAfterWrite(mri_->getRegClass(cur->reg)))
> -      avoidWAW_ = physReg;
> -
> -    // "Upgrade" the physical register since it has been allocated.
> -    UpgradeRegister(physReg);
> -    if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
> -      // "Downgrade" physReg to try to keep physReg from being allocated until
> -      // the next reload from the same SS is allocated.
> -      mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
> -      DowngradeRegister(cur, physReg);
> -    }
> -    return;
> -  }
> -  DEBUG(dbgs() << "no free registers\n");
> -
> -  // Compile the spill weights into an array that is better for scanning.
> -  std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
> -  for (std::vector<std::pair<unsigned, float> >::iterator
> -       I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
> -    updateSpillWeights(SpillWeights, I->first, I->second, RC);
> -
> -  // for each interval in active, update spill weights.
> -  for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
> -       i != e; ++i) {
> -    unsigned reg = i->first->reg;
> -    assert(TargetRegisterInfo::isVirtualRegister(reg) &&
> -           "Can only allocate virtual registers!");
> -    reg = vrm_->getPhys(reg);
> -    updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
> -  }
> -
> -  DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
> -
> -  // Find a register to spill.
> -  float minWeight = HUGE_VALF;
> -  unsigned minReg = 0;
> -
> -  bool Found = false;
> -  std::vector<std::pair<unsigned,float> > RegsWeights;
> -  ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
> -  if (!minReg || SpillWeights[minReg] == HUGE_VALF)
> -    for (unsigned i = 0; i != Order.size(); ++i) {
> -      unsigned reg = Order[i];
> -      float regWeight = SpillWeights[reg];
> -      // Skip recently allocated registers and reserved registers.
> -      if (minWeight > regWeight && !isRecentlyUsed(reg))
> -        Found = true;
> -      RegsWeights.push_back(std::make_pair(reg, regWeight));
> -    }
> -
> -  // If we didn't find a register that is spillable, try aliases?
> -  if (!Found) {
> -    for (unsigned i = 0; i != Order.size(); ++i) {
> -      unsigned reg = Order[i];
> -      // No need to worry about if the alias register size < regsize of RC.
> -      // We are going to spill all registers that alias it anyway.
> -      for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
> -        RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
> -    }
> -  }
> -
> -  // Sort all potential spill candidates by weight.
> -  std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
> -  minReg = RegsWeights[0].first;
> -  minWeight = RegsWeights[0].second;
> -  if (minWeight == HUGE_VALF) {
> -    // All registers must have inf weight. Just grab one!
> -    minReg = BestPhysReg ? BestPhysReg : getFirstNonReservedPhysReg(RC);
> -    if (cur->weight == HUGE_VALF ||
> -        li_->getApproximateInstructionCount(*cur) == 0) {
> -      // Spill a physical register around defs and uses.
> -      if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
> -        // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
> -        // in fixed_. Reset them.
> -        for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
> -          IntervalPtr &IP = fixed_[i];
> -          LiveInterval *I = IP.first;
> -          if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
> -            IP.second = I->advanceTo(I->begin(), StartPosition);
> -        }
> -
> -        DowngradedRegs.clear();
> -        assignRegOrStackSlotAtInterval(cur);
> -      } else {
> -        assert(false && "Ran out of registers during register allocation!");
> -        report_fatal_error("Ran out of registers during register allocation!");
> -      }
> -      return;
> -    }
> -  }
> -
> -  // Find up to 3 registers to consider as spill candidates.
> -  unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
> -  while (LastCandidate > 1) {
> -    if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
> -      break;
> -    --LastCandidate;
> -  }
> -
> -  DEBUG({
> -      dbgs() << "\t\tregister(s) with min weight(s): ";
> -
> -      for (unsigned i = 0; i != LastCandidate; ++i)
> -        dbgs() << tri_->getName(RegsWeights[i].first)
> -               << " (" << RegsWeights[i].second << ")\n";
> -    });
> -
> -  // If the current has the minimum weight, we need to spill it and
> -  // add any added intervals back to unhandled, and restart
> -  // linearscan.
> -  if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
> -    DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
> -    SmallVector<LiveInterval*, 8> added;
> -    LiveRangeEdit LRE(*cur, added);
> -    spiller_->spill(LRE);
> -
> -    std::sort(added.begin(), added.end(), LISorter());
> -    if (added.empty())
> -      return;  // Early exit if all spills were folded.
> -
> -    // Merge added with unhandled.  Note that we have already sorted
> -    // intervals returned by addIntervalsForSpills by their starting
> -    // point.
> -    // This also update the NextReloadMap. That is, it adds mapping from a
> -    // register defined by a reload from SS to the next reload from SS in the
> -    // same basic block.
> -    MachineBasicBlock *LastReloadMBB = 0;
> -    LiveInterval *LastReload = 0;
> -    int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
> -    for (unsigned i = 0, e = added.size(); i != e; ++i) {
> -      LiveInterval *ReloadLi = added[i];
> -      if (ReloadLi->weight == HUGE_VALF &&
> -          li_->getApproximateInstructionCount(*ReloadLi) == 0) {
> -        SlotIndex ReloadIdx = ReloadLi->beginIndex();
> -        MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
> -        int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
> -        if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
> -          // Last reload of same SS is in the same MBB. We want to try to
> -          // allocate both reloads the same register and make sure the reg
> -          // isn't clobbered in between if at all possible.
> -          assert(LastReload->beginIndex() < ReloadIdx);
> -          NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
> -        }
> -        LastReloadMBB = ReloadMBB;
> -        LastReload = ReloadLi;
> -        LastReloadSS = ReloadSS;
> -      }
> -      unhandled_.push(ReloadLi);
> -    }
> -    return;
> -  }
> -
> -  ++NumBacktracks;
> -
> -  // Push the current interval back to unhandled since we are going
> -  // to re-run at least this iteration. Since we didn't modify it it
> -  // should go back right in the front of the list
> -  unhandled_.push(cur);
> -
> -  assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
> -         "did not choose a register to spill?");
> -
> -  // We spill all intervals aliasing the register with
> -  // minimum weight, rollback to the interval with the earliest
> -  // start point and let the linear scan algorithm run again
> -  SmallVector<LiveInterval*, 8> spillIs;
> -
> -  // Determine which intervals have to be spilled.
> -  findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
> -
> -  // Set of spilled vregs (used later to rollback properly)
> -  SmallSet<unsigned, 8> spilled;
> -
> -  // The earliest start of a Spilled interval indicates up to where
> -  // in handled we need to roll back
> -  assert(!spillIs.empty() && "No spill intervals?");
> -  SlotIndex earliestStart = spillIs[0]->beginIndex();
> -
> -  // Spill live intervals of virtual regs mapped to the physical register we
> -  // want to clear (and its aliases).  We only spill those that overlap with the
> -  // current interval as the rest do not affect its allocation. we also keep
> -  // track of the earliest start of all spilled live intervals since this will
> -  // mark our rollback point.
> -  SmallVector<LiveInterval*, 8> added;
> -  while (!spillIs.empty()) {
> -    LiveInterval *sli = spillIs.back();
> -    spillIs.pop_back();
> -    DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
> -    if (sli->beginIndex() < earliestStart)
> -      earliestStart = sli->beginIndex();
> -    LiveRangeEdit LRE(*sli, added, 0, &spillIs);
> -    spiller_->spill(LRE);
> -    spilled.insert(sli->reg);
> -  }
> -
> -  // Include any added intervals in earliestStart.
> -  for (unsigned i = 0, e = added.size(); i != e; ++i) {
> -    SlotIndex SI = added[i]->beginIndex();
> -    if (SI < earliestStart)
> -      earliestStart = SI;
> -  }
> -
> -  DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
> -
> -  // Scan handled in reverse order up to the earliest start of a
> -  // spilled live interval and undo each one, restoring the state of
> -  // unhandled.
> -  while (!handled_.empty()) {
> -    LiveInterval* i = handled_.back();
> -    // If this interval starts before t we are done.
> -    if (!i->empty() && i->beginIndex() < earliestStart)
> -      break;
> -    DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
> -    handled_.pop_back();
> -
> -    // When undoing a live interval allocation we must know if it is active or
> -    // inactive to properly update regUse_ and the VirtRegMap.
> -    IntervalPtrs::iterator it;
> -    if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
> -      active_.erase(it);
> -      assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
> -      if (!spilled.count(i->reg))
> -        unhandled_.push(i);
> -      delRegUse(vrm_->getPhys(i->reg));
> -      vrm_->clearVirt(i->reg);
> -    } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
> -      inactive_.erase(it);
> -      assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
> -      if (!spilled.count(i->reg))
> -        unhandled_.push(i);
> -      vrm_->clearVirt(i->reg);
> -    } else {
> -      assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
> -             "Can only allocate virtual registers!");
> -      vrm_->clearVirt(i->reg);
> -      unhandled_.push(i);
> -    }
> -
> -    DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
> -    if (ii == DowngradeMap.end())
> -      // It interval has a preference, it must be defined by a copy. Clear the
> -      // preference now since the source interval allocation may have been
> -      // undone as well.
> -      mri_->setRegAllocationHint(i->reg, 0, 0);
> -    else {
> -      UpgradeRegister(ii->second);
> -    }
> -  }
> -
> -  // Rewind the iterators in the active, inactive, and fixed lists back to the
> -  // point we reverted to.
> -  RevertVectorIteratorsTo(active_, earliestStart);
> -  RevertVectorIteratorsTo(inactive_, earliestStart);
> -  RevertVectorIteratorsTo(fixed_, earliestStart);
> -
> -  // Scan the rest and undo each interval that expired after t and
> -  // insert it in active (the next iteration of the algorithm will
> -  // put it in inactive if required)
> -  for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
> -    LiveInterval *HI = handled_[i];
> -    if (!HI->expiredAt(earliestStart) &&
> -        HI->expiredAt(cur->beginIndex())) {
> -      DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
> -      active_.push_back(std::make_pair(HI, HI->begin()));
> -      assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
> -      addRegUse(vrm_->getPhys(HI->reg));
> -    }
> -  }
> -
> -  // Merge added with unhandled.
> -  // This also update the NextReloadMap. That is, it adds mapping from a
> -  // register defined by a reload from SS to the next reload from SS in the
> -  // same basic block.
> -  MachineBasicBlock *LastReloadMBB = 0;
> -  LiveInterval *LastReload = 0;
> -  int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
> -  std::sort(added.begin(), added.end(), LISorter());
> -  for (unsigned i = 0, e = added.size(); i != e; ++i) {
> -    LiveInterval *ReloadLi = added[i];
> -    if (ReloadLi->weight == HUGE_VALF &&
> -        li_->getApproximateInstructionCount(*ReloadLi) == 0) {
> -      SlotIndex ReloadIdx = ReloadLi->beginIndex();
> -      MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
> -      int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
> -      if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
> -        // Last reload of same SS is in the same MBB. We want to try to
> -        // allocate both reloads the same register and make sure the reg
> -        // isn't clobbered in between if at all possible.
> -        assert(LastReload->beginIndex() < ReloadIdx);
> -        NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
> -      }
> -      LastReloadMBB = ReloadMBB;
> -      LastReload = ReloadLi;
> -      LastReloadSS = ReloadSS;
> -    }
> -    unhandled_.push(ReloadLi);
> -  }
> -}
> -
> -unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
> -                                   const TargetRegisterClass *RC,
> -                                   unsigned MaxInactiveCount,
> -                                   SmallVector<unsigned, 256> &inactiveCounts,
> -                                   bool SkipDGRegs) {
> -  unsigned FreeReg = 0;
> -  unsigned FreeRegInactiveCount = 0;
> -
> -  std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
> -  // Resolve second part of the hint (if possible) given the current allocation.
> -  unsigned physReg = Hint.second;
> -  if (TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
> -    physReg = vrm_->getPhys(physReg);
> -
> -  ArrayRef<unsigned> Order;
> -  if (Hint.first)
> -    Order = tri_->getRawAllocationOrder(RC, Hint.first, physReg, *mf_);
> -  else
> -    Order = RegClassInfo.getOrder(RC);
> -
> -  assert(!Order.empty() && "No allocatable register in this register class!");
> -
> -  // Scan for the first available register.
> -  for (unsigned i = 0; i != Order.size(); ++i) {
> -    unsigned Reg = Order[i];
> -    // Ignore "downgraded" registers.
> -    if (SkipDGRegs && DowngradedRegs.count(Reg))
> -      continue;
> -    // Skip reserved registers.
> -    if (reservedRegs_.test(Reg))
> -      continue;
> -    // Skip recently allocated registers.
> -    if (isRegAvail(Reg) && (!SkipDGRegs || !isRecentlyUsed(Reg))) {
> -      FreeReg = Reg;
> -      if (FreeReg < inactiveCounts.size())
> -        FreeRegInactiveCount = inactiveCounts[FreeReg];
> -      else
> -        FreeRegInactiveCount = 0;
> -      break;
> -    }
> -  }
> -
> -  // If there are no free regs, or if this reg has the max inactive count,
> -  // return this register.
> -  if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
> -    // Remember what register we picked so we can skip it next time.
> -    if (FreeReg != 0) recordRecentlyUsed(FreeReg);
> -    return FreeReg;
> -  }
> -
> -  // Continue scanning the registers, looking for the one with the highest
> -  // inactive count.  Alkis found that this reduced register pressure very
> -  // slightly on X86 (in rev 1.94 of this file), though this should probably be
> -  // reevaluated now.
> -  for (unsigned i = 0; i != Order.size(); ++i) {
> -    unsigned Reg = Order[i];
> -    // Ignore "downgraded" registers.
> -    if (SkipDGRegs && DowngradedRegs.count(Reg))
> -      continue;
> -    // Skip reserved registers.
> -    if (reservedRegs_.test(Reg))
> -      continue;
> -    if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
> -        FreeRegInactiveCount < inactiveCounts[Reg] &&
> -        (!SkipDGRegs || !isRecentlyUsed(Reg))) {
> -      FreeReg = Reg;
> -      FreeRegInactiveCount = inactiveCounts[Reg];
> -      if (FreeRegInactiveCount == MaxInactiveCount)
> -        break;    // We found the one with the max inactive count.
> -    }
> -  }
> -
> -  // Remember what register we picked so we can skip it next time.
> -  recordRecentlyUsed(FreeReg);
> -
> -  return FreeReg;
> -}
> -
> -/// getFreePhysReg - return a free physical register for this virtual register
> -/// interval if we have one, otherwise return 0.
> -unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
> -  SmallVector<unsigned, 256> inactiveCounts;
> -  unsigned MaxInactiveCount = 0;
> -
> -  const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
> -  const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
> -
> -  for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
> -       i != e; ++i) {
> -    unsigned reg = i->first->reg;
> -    assert(TargetRegisterInfo::isVirtualRegister(reg) &&
> -           "Can only allocate virtual registers!");
> -
> -    // If this is not in a related reg class to the register we're allocating,
> -    // don't check it.
> -    const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
> -    if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
> -      reg = vrm_->getPhys(reg);
> -      if (inactiveCounts.size() <= reg)
> -        inactiveCounts.resize(reg+1);
> -      ++inactiveCounts[reg];
> -      MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
> -    }
> -  }
> -
> -  // If copy coalescer has assigned a "preferred" register, check if it's
> -  // available first.
> -  unsigned Preference = vrm_->getRegAllocPref(cur->reg);
> -  if (Preference) {
> -    DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
> -    if (isRegAvail(Preference) &&
> -        RC->contains(Preference))
> -      return Preference;
> -  }
> -
> -  unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
> -                                    true);
> -  if (FreeReg)
> -    return FreeReg;
> -  return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
> -}
> -
> -FunctionPass* llvm::createLinearScanRegisterAllocator() {
> -  return new RALinScan();
> -}
> 
> 
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From sabre at nondot.org  Tue Nov 15 16:13:27 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 15 Nov 2011 22:13:27 -0000
Subject: [llvm-commits] [llvm] r144708 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111115221327.EAD6A2A6C132@llvm.org>

Author: lattner
Date: Tue Nov 15 16:13:27 2011
New Revision: 144708

URL: http://llvm.org/viewvc/llvm-project?rev=144708&view=rev
Log:
some notes.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=144708&r1=144707&r2=144708&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Nov 15 16:13:27 2011
@@ -712,6 +712,34 @@
 
 <p>LLVM 3.0 includes several major new capabilities:</p>
   
+<!-- Near dead:
+   Analysis/RegionInfo.h + Dom Frontiers
+   SparseBitVector: used in LiveVar.
+ 
+ -->
+  
+<!--
+ Type system rewrite.
+ Better performance for Neon code in clang due to SRoA improvements.
+ New regalloc on by default. Lin scan going away in 3.1
+ PGO / builtin_expect improvements (summary needed)
+ Big EH rewrite.
+ AVX support, assembler, compiler and disassembler.
+ IndVar improvements: andy
+ PTX backend improvements: Justin
+ llvm-rtdyld & MC JIT: JimG
+ InstAliases now automatically used in the asmprinter where they are shorter.
+ Integrated assembler on by default for arm/thumb?
+ PostOrder Dominator frontiers were removed.
+ Line Profiling / gcov support
+ EH and debug information produced with CFI directives, yielding smaller executables: http://blog.mozilla.com/respindola/2011/05/12/cfi-directives/
+ X86-64 generates smaller and faster code at -O0 (fast isel improvements)
+ Better code generation for Cortex-A9
+ Many APIs take ArrayRef's now.
+ Pass manager extension API.
+ 
+ -->
+  
 <ul>
 
 <!--



From grosbach at apple.com  Tue Nov 15 16:14:41 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 22:14:41 -0000
Subject: [llvm-commits] [llvm] r144709 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20111115221441.5DCDA2A6C132@llvm.org>

Author: grosbach
Date: Tue Nov 15 16:14:41 2011
New Revision: 144709

URL: http://llvm.org/viewvc/llvm-project?rev=144709&view=rev
Log:
ARM accept an immediate offset in memory operands w/o the '#'.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144709&r1=144708&r2=144709&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 15 16:14:41 2011
@@ -3559,9 +3559,12 @@
   }
 
   // If we have a '#', it's an immediate offset, else assume it's a register
-  // offset.
-  if (Parser.getTok().is(AsmToken::Hash)) {
-    Parser.Lex(); // Eat the '#'.
+  // offset. Be friendly and also accept a plain integer (without a leading
+  // hash) for gas compatibility.
+  if (Parser.getTok().is(AsmToken::Hash) ||
+      Parser.getTok().is(AsmToken::Integer)) {
+    if (Parser.getTok().is(AsmToken::Hash))
+      Parser.Lex(); // Eat the '#'.
     E = Parser.getTok().getLoc();
 
     bool isNegative = getParser().getTok().is(AsmToken::Minus);



From grosbach at apple.com  Tue Nov 15 16:15:10 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 22:15:10 -0000
Subject: [llvm-commits] [llvm] r144710 -
	/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
Message-ID: <20111115221510.7B8302A6C132@llvm.org>

Author: grosbach
Date: Tue Nov 15 16:15:10 2011
New Revision: 144710

URL: http://llvm.org/viewvc/llvm-project?rev=144710&view=rev
Log:
ARM VFP assembly parsing for VADD and VSUB two-operand forms.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=144710&r1=144709&r2=144710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Nov 15 16:15:10 2011
@@ -1178,6 +1178,16 @@
                     (VMULD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
 def : VFP2InstAlias<"vmul${p}.f32 $Sn, $Sm",
                     (VMULS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
+// VADD has a two-operand form (implied destination operand)
+def : VFP2InstAlias<"vadd${p}.f64 $Dn, $Dm",
+                    (VADDD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
+def : VFP2InstAlias<"vadd${p}.f32 $Sn, $Sm",
+                    (VADDS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
+// VSUB has a two-operand form (implied destination operand)
+def : VFP2InstAlias<"vsub${p}.f64 $Dn, $Dm",
+                    (VSUBD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
+def : VFP2InstAlias<"vsub${p}.f32 $Sn, $Sm",
+                    (VSUBS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
 
 // VMOV can accept optional .f32/.f64 suffix.
 def : VFP2InstAlias<"vmov${p}.f32 $Rt, $Sn",



From sabre at nondot.org  Tue Nov 15 16:23:46 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 15 Nov 2011 22:23:46 -0000
Subject: [llvm-commits] [llvm] r144711 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111115222347.06AEF2A6C132@llvm.org>

Author: lattner
Date: Tue Nov 15 16:23:46 2011
New Revision: 144711

URL: http://llvm.org/viewvc/llvm-project?rev=144711&view=rev
Log:
add PTX backend info

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=144711&r1=144710&r2=144711&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Nov 15 16:23:46 2011
@@ -995,6 +995,7 @@
 -->
 </ul>
 </div>
+
   
 <!--=========================================================================-->
 <h3>
@@ -1016,7 +1017,30 @@
   <li>Initial support for MIPS64 has been added.</li>
 </ul>
 </div>
+
+<!--=========================================================================-->
+<h3>
+  <a name="PTX">PTX Target Improvements</a>
+</h3>
+
+<div>
+  
+  <p>
+  The PTX back-end is still experimental, but is fairly usable for compute kernels
+  in LLVM 3.0.  Most scalar arithmetic is implemented, as well as intrinsics to
+  access the special PTX registers and sync instructions.  The major missing
+  pieces are texture/sampler support and some vector operations.</p>
+  
+  <p>That said, the backend is already being used for domain-specific languages
+  and works well with the <a href="http://www.pcc.me.uk/~peter/libclc/">libclc
+    library</a> to supply OpenCL built-ins.  With it, you can use Clang to compile
+  OpenCL code into PTX and execute it by loading the resulting PTX as a binary
+  blob using the nVidia OpenCL library.  It has been tested with several OpenCL
+  programs, including some from the nVidia GPU Computing SDK, and the performance
+  is on par with the nVidia compiler.</p>
   
+</div>
+
 <!--=========================================================================-->
 <h3>
 <a name="OtherTS">Other Target Specific Improvements</a>



From dschuff at google.com  Tue Nov 15 16:25:31 2011
From: dschuff at google.com (Derek Schuff)
Date: Tue, 15 Nov 2011 14:25:31 -0800
Subject: [llvm-commits] Proposal/patch: Enable bitcode streaming
In-Reply-To: <CAJdarcFBAY7Lec7cGYyziDhmNZ37dobf_RuBWFtSp6ZYazYJoA@mail.gmail.com>
References: <CAAEAhvci4uJmsT4b1ibkG57qmzAesDdPQejmhAVLEmFd_FzyOg@mail.gmail.com>
	<CAAEAhvdtqnOFQhXfWc68tOvPHK0xCEDKYzpFL_tRw2Gu0qFdyQ@mail.gmail.com>
	<CAJdarcFBAY7Lec7cGYyziDhmNZ37dobf_RuBWFtSp6ZYazYJoA@mail.gmail.com>
Message-ID: <CAAEAhvdo7nXmZUOywa=S_1_N1f6JhpYt-w=ednrZixADufLjDA@mail.gmail.com>

Thanks. hopefully someone will soon.

I need to add one amendment to the above description:
Since the container for bitcode doesn't really act all that much like a
vector, I renamed it to BitstreamBytes, and the way to get the bitcode
bytes is just a getByte/getWord method rather than operator[]. Otherwise
the description still applies.



On Tue, Nov 15, 2011 at 12:41 PM, Eli Friedman <eli.friedman at gmail.com>wrote:

> On Mon, Nov 14, 2011 at 10:54 AM, Derek Schuff <dschuff at google.com> wrote:
> > Ping?
> > Could someone take a look at this? (or, have I sent it to the wrong
> > place/not marked it properly?)
>
> This is the right place; not sure why nobody has responded.
>
> -Eli
>
> > On Wed, Nov 9, 2011 at 4:57 PM, Derek Schuff <dschuff at google.com> wrote:
> >>
> >> Hello all,
> >> The following is a proposal (and a prototype patch) to enable bitcode
> >> streaming. The overall goal is to be able to overlap bitcode
> >> reading/download with compilation, a functionality useful obviously for
> >> pnacl and renderscript but also potentially for any situation where the
> >> interface between the frontend and backend is something other than a
> file.
> >> In the current state of the world, at a high level, there are 2 things
> >> keeping this from happening. The first is that BitcodeReader
> construction
> >> takes a MemoryBuffer which it expects to be filled with bitcode, and
> inside
> >> BitcodeReader, the BitstreamCursor (which is the primary interface to
> the
> >> bitcode itself) gets pointers to the bitcode in memory, and does all of
> its
> >> magic with pointer arithmetic. The second issue is that in
> >> BitcodeReader::ParseModule (which is run when right after the Module and
> >> BitcodeReader objects are created), the reader makes a pass over the
> entire
> >> bitcode file. This step does everything except read the function
> bodies, but
> >> it records the bit locations of each function for future
> materialization.
> >> High-level change description:
> >> This patch creates a class called BitcodeStream, which is a very simple
> >> interface with one method (GetBytes), which fetches the requested
> number of
> >> bytes from the stream, and writes them into the requested destination.
> This
> >> method may block the calling thread if there are not yet enough bytes
> >> available in the stream buffer (similarly to a stdin or socket read).
> >> The first issue above is addressed by introducing the BitstreamVector,
> an
> >> abstraction that wraps the bitcode in memory. Instead of using
> pointers, the
> >> BitstreamCursor uses indices and gets bitcode bytes by indexing (i.e.
> >> operator[] ) the BitstreamVector. When streaming is not used, the
> >> BitstreamVector itself keeps pointers to the start and end of the
> backing
> >> MemoryBuffer and the indexing operator is just a pointer dereference.
> For
> >> streaming use, the BitstreamVector has a BitcodeStream object. If a
> byte is
> >> requested that has not yet been fetched, it calls GetBytes to get more,
> >> until it has enough to return the requested byte.
> >> This model of allowing any byte to be requested and blocking the caller
> >> has the advantage that there is no structural/architectural change
> required
> >> at this lowest level, nor at the high level (A FunctionPassManager is
> used
> >> to iterate over all the functions and compile each one).
> >> The second issue is solved by 2 simple changes. The first is in
> >> ParseModule. Instead of a single pass over all the bitcode, ParseModule
> >> becomes resumable.  ParseModule will do its normal handling for
> top-level
> >> records, type table blocks, metadata, etc, but if streaming is in use,
> it
> >> will save its state and return as soon as a function subblock is
> encountered
> >> (rather than saving its location and skipping over it). Each subsequent
> time
> >> it is called, it bookmarks and skips one function block. Later, when a
> >> function needs to be materialized, if the function body has been seen
> >> already, then materialization is the same as before. Otherwise,
> Materialize
> >> will keep calling ParseModule (each time bookmarking and skipping one
> >> function body) until the requested function is found. The one other
> change
> >> required to make this work simply is that the bitcode writer writes
> function
> >> bodies as the last subblock (currently the attachment metadata and value
> >> symbol table are written after the function bodies).
> >> The prototype patch is attached and can also be viewed online at
> >> http://codereview.chromium.org/8393017/ . Feedback is welcome, as well
> as
> >> guidance from the relevant code owners/reviewers regarding what the next
> >> step needs to be toward committing this.
> >> Thanks,
> >> -Derek
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >
> >
>
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From clattner at apple.com  Tue Nov 15 16:29:24 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 15 Nov 2011 14:29:24 -0800
Subject: [llvm-commits] [llvm] r144600 - /llvm/trunk/docs/index.html
In-Reply-To: <04027E85-8C4F-4DCD-AAF7-68CE8C9C036F@apple.com>
References: <20111115011437.85FCD2A6C131@llvm.org>
	<17583FD5-F653-485D-9255-19A42D71BFFB@apple.com>
	<04027E85-8C4F-4DCD-AAF7-68CE8C9C036F@apple.com>
Message-ID: <BA28389A-EC10-4249-8FC5-7A9B67715E34@apple.com>

On Nov 15, 2011, at 10:06 AM, Devang Patel wrote:
>> 
>> Can this be merged into some other document, like the SourceLevelDebugging doc?
>> 
> 
> SourceLevelDebugging is meant for clang+llvm developers. Where as lldb developers are also targeted by this doc and I also expect to see a doc on recent accelerator tables work where audience is llvm+lldb developers.
> 
> If you still think SourceLevelDebugging is appropriate then I'll merge them.

Yes, please make a new major "LLVM Dwarf Extensions" section in Source Level Debugging.  Thanks!

-Chris


From grosbach at apple.com  Tue Nov 15 16:27:54 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 22:27:54 -0000
Subject: [llvm-commits] [llvm] r144713 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/basic-arm-instructions.s
Message-ID: <20111115222754.68E9B2A6C132@llvm.org>

Author: grosbach
Date: Tue Nov 15 16:27:54 2011
New Revision: 144713

URL: http://llvm.org/viewvc/llvm-project?rev=144713&view=rev
Log:
ARM assembly parsing two operand forms for shift instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=144713&r1=144712&r2=144713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 15 16:27:54 2011
@@ -5023,6 +5023,16 @@
 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
                         (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
                              cc_out:$s)>;
+// shifter instructions also support a two-operand form.
+def : ARMInstAlias<"asr${s}${p} $Rm, $imm",
+                   (ASRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
+def : ARMInstAlias<"lsr${s}${p} $Rm, $imm",
+                   (LSRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
+def : ARMInstAlias<"lsl${s}${p} $Rm, $imm",
+                   (LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
+def : ARMInstAlias<"ror${s}${p} $Rm, $imm",
+                   (RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
+
 
 // 'mul' instruction can be specified with only two operands.
 def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=144713&r1=144712&r2=144713&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Tue Nov 15 16:27:54 2011
@@ -262,10 +262,12 @@
 	asr r2, r4, #32
 	asr r2, r4, #2
 	asr r2, r4, #0
+	asr r4, #2
 
 @ CHECK: asr	r2, r4, #32             @ encoding: [0x44,0x20,0xa0,0xe1]
 @ CHECK: asr	r2, r4, #2              @ encoding: [0x44,0x21,0xa0,0xe1]
 @ CHECK: mov	r2, r4                  @ encoding: [0x04,0x20,0xa0,0xe1]
+@ CHECK: asr	r4, r4, #2              @ encoding: [0x44,0x41,0xa0,0xe1]
 
 
 @------------------------------------------------------------------------------
@@ -794,10 +796,12 @@
 	lsl r2, r4, #31
 	lsl r2, r4, #1
 	lsl r2, r4, #0
+	lsl r4, #1
 
 @ CHECK: lsl	r2, r4, #31             @ encoding: [0x84,0x2f,0xa0,0xe1]
 @ CHECK: lsl	r2, r4, #1              @ encoding: [0x84,0x20,0xa0,0xe1]
 @ CHECK: mov	r2, r4                  @ encoding: [0x04,0x20,0xa0,0xe1]
+@ CHECK: lsl	r4, r4, #1              @ encoding: [0x84,0x40,0xa0,0xe1]
 
 
 @------------------------------------------------------------------------------
@@ -806,10 +810,12 @@
 	lsr r2, r4, #32
 	lsr r2, r4, #2
 	lsr r2, r4, #0
+	lsr r4, #2
 
 @ CHECK: lsr	r2, r4, #32             @ encoding: [0x24,0x20,0xa0,0xe1]
 @ CHECK: lsr	r2, r4, #2              @ encoding: [0x24,0x21,0xa0,0xe1]
 @ CHECK: mov	r2, r4                  @ encoding: [0x04,0x20,0xa0,0xe1]
+@ CHECK: lsr	r4, r4, #2              @ encoding: [0x24,0x41,0xa0,0xe1]
 
 
 @------------------------------------------------------------------------------
@@ -1346,10 +1352,12 @@
 	ror r2, r4, #31
 	ror r2, r4, #1
 	ror r2, r4, #0
+	ror r4, #1
 
 @ CHECK: ror	r2, r4, #31             @ encoding: [0xe4,0x2f,0xa0,0xe1]
 @ CHECK: ror	r2, r4, #1              @ encoding: [0xe4,0x20,0xa0,0xe1]
 @ CHECK: mov	r2, r4                  @ encoding: [0x04,0x20,0xa0,0xe1]
+@ CHECK: ror	r4, r4, #1              @ encoding: [0xe4,0x40,0xa0,0xe1]
 
 
 @------------------------------------------------------------------------------



From geek4civic at gmail.com  Tue Nov 15 16:30:37 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 15 Nov 2011 22:30:37 -0000
Subject: [llvm-commits] [llvm] r144714 -
	/llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll
Message-ID: <20111115223038.100DD2A6C132@llvm.org>

Author: chapuni
Date: Tue Nov 15 16:30:37 2011
New Revision: 144714

URL: http://llvm.org/viewvc/llvm-project?rev=144714&view=rev
Log:
test/CodeGen/X86/dec-eflags-lower.ll: Relax expression for win32 x64.

Modified:
    llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll

Modified: llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll?rev=144714&r1=144713&r2=144714&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll Tue Nov 15 16:30:37 2011
@@ -4,7 +4,7 @@
 
 define void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
 entry:
-; CHECK: decq	(%rdi)
+; CHECK: decq	(%{{rdi|rcx}})
 ; CHECK-NEXT: je
   %refcnt = getelementptr inbounds %struct.obj* %o, i64 0, i32 0
   %0 = load i64* %refcnt, align 8, !tbaa !0



From sabre at nondot.org  Tue Nov 15 16:40:14 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 15 Nov 2011 22:40:14 -0000
Subject: [llvm-commits] [llvm] r144716 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20111115224014.69D592A6C132@llvm.org>

Author: lattner
Date: Tue Nov 15 16:40:14 2011
New Revision: 144716

URL: http://llvm.org/viewvc/llvm-project?rev=144716&view=rev
Log:
add ImmutableSet/Map dox, patch by Caitlin Sadowski!

Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=144716&r1=144715&r2=144716&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Tue Nov 15 16:40:14 2011
@@ -85,7 +85,8 @@
       <li><a href="#dss_set">&lt;set&gt;</a></li>
       <li><a href="#dss_setvector">"llvm/ADT/SetVector.h"</a></li>
       <li><a href="#dss_uniquevector">"llvm/ADT/UniqueVector.h"</a></li>
-      <li><a href="#dss_otherset">Other Set-Like ContainerOptions</a></li>
+      <li><a href="#dss_immutableset">"llvm/ADT/ImmutableSet.h"</a></li>
+      <li><a href="#dss_otherset">Other Set-Like Container Options</a></li>
     </ul></li>
     <li><a href="#ds_map">Map-Like Containers (std::map, DenseMap, etc)</a>
     <ul>
@@ -97,6 +98,7 @@
       <li><a href="#dss_intervalmap">"llvm/ADT/IntervalMap.h"</a></li>
       <li><a href="#dss_map">&lt;map&gt;</a></li>
       <li><a href="#dss_inteqclasses">"llvm/ADT/IntEqClasses.h"</a></li>
+      <li><a href="#dss_immutablemap">"llvm/ADT/ImmutableMap.h"</a></li>
       <li><a href="#dss_othermap">Other Map-Like Container Options</a></li>
     </ul></li>
     <li><a href="#ds_bit">BitVector-like containers</a>
@@ -1608,6 +1610,29 @@
 
 </div>
 
+<!-- _______________________________________________________________________ -->
+<h4>
+  <a name="dss_immutableset">"llvm/ADT/ImmutableSet.h"</a>
+</h4>
+
+<div>
+
+<p>
+ImmutableSet is an immutable (functional) set implementation based on an AVL
+tree.
+Adding or removing elements is done through a Factory object and results in the
+creation of a new ImmutableSet object.
+If an ImmutableSet already exists with the given contents, then the existing one
+is returned; equality is compared with a FoldingSetNodeID.
+The time and space complexity of add or remove operations is logarithmic in the
+size of the original set.
+
+<p>
+There is no method for returning an element of the set, you can only check for
+membership.
+
+</div>
+
 
 <!-- _______________________________________________________________________ -->
 <h4>
@@ -1814,6 +1839,25 @@
 
 <!-- _______________________________________________________________________ -->
 <h4>
+  <a name="dss_immutablemap">"llvm/ADT/ImmutableMap.h"</a>
+</h4>
+
+<div>
+
+<p>
+ImmutableMap is an immutable (functional) map implementation based on an AVL
+tree.
+Adding or removing elements is done through a Factory object and results in the
+creation of a new ImmutableMap object.
+If an ImmutableMap already exists with the given key set, then the existing one
+is returned; equality is compared with a FoldingSetNodeID.
+The time and space complexity of add or remove operations is logarithmic in the
+size of the original map.
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<h4>
   <a name="dss_othermap">Other Map-Like Container Options</a>
 </h4>
 



From sabre at nondot.org  Tue Nov 15 16:48:24 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 15 Nov 2011 22:48:24 -0000
Subject: [llvm-commits] [llvm] r144719 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111115224824.A63D42A6C132@llvm.org>

Author: lattner
Date: Tue Nov 15 16:48:24 2011
New Revision: 144719

URL: http://llvm.org/viewvc/llvm-project?rev=144719&view=rev
Log:
jakob fixed X87 inline asm!

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=144719&r1=144718&r2=144719&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Nov 15 16:48:24 2011
@@ -970,6 +970,10 @@
 
 <ul>
 
+  <li>The X86 backend now supports
+    all <a href="http://llvm.org/PR879">inline assembly that uses the X86
+      floating point stack</a>.</li>
+  
   <li>The CRC32 intrinsics have been renamed.  The intrinsics were previously
       <code>@llvm.x86.sse42.crc32.[8|16|32]</code>
       and <code>@llvm.x86.sse42.crc64.[8|64]</code>. They have been renamed to
@@ -1264,10 +1268,6 @@
 <div>
 
 <ul>
-  <li>The X86 backend does not yet support
-      all <a href="http://llvm.org/PR879">inline assembly that uses the X86
-      floating point stack</a>.  It supports the 'f' and 't' constraints, but
-      not 'u'.</li>
 
   <li>The X86-64 backend does not yet support the LLVM IR instruction
       <tt>va_arg</tt>. Currently, front-ends support variadic argument



From nadav.rotem at intel.com  Tue Nov 15 16:50:38 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Tue, 15 Nov 2011 22:50:38 -0000
Subject: [llvm-commits] [llvm] r144720 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-vbroadcast.ll
Message-ID: <20111115225038.1DAF52A6C132@llvm.org>

Author: nadav
Date: Tue Nov 15 16:50:37 2011
New Revision: 144720

URL: http://llvm.org/viewvc/llvm-project?rev=144720&view=rev
Log:
AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code.
 

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144720&r1=144719&r2=144720&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Nov 15 16:50:37 2011
@@ -5110,6 +5110,84 @@
   return SDValue();
 }
 
+/// isVectorBroadcast - Check if the node chain is suitable to be xformed to
+/// a vbroadcast node. We support two patterns:
+/// 1. A splat BUILD_VECTOR which uses a single scalar load.
+/// 2. A splat shuffle which uses a scalar_to_vector node which comes from
+/// a scalar load.
+/// The scalar load node is returned when a pattern is found, 
+/// or SDValue() otherwise. 
+static SDValue isVectorBroadcast(SDValue &Op) {
+  EVT VT = Op.getValueType();
+  SDValue V = Op;
+
+  if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
+    V = V.getOperand(0);
+
+  //A suspected load to be broadcasted.
+  SDValue Ld;
+
+  switch (V.getOpcode()) {
+    default:
+      // Unknown pattern found.
+      return SDValue();
+
+    case ISD::BUILD_VECTOR: {
+      // The BUILD_VECTOR node must be a splat.
+      if (!isSplatVector(V.getNode())) 
+        return SDValue();
+
+      Ld = V.getOperand(0);
+    
+      // The suspected load node has several users. Make sure that all 
+      // of its users are from the BUILD_VECTOR node.
+      if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 
+        return SDValue();
+      break; 
+    }
+
+    case ISD::VECTOR_SHUFFLE: {
+      ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
+
+      // Shuffles must have a splat mask where the first element is
+      // broadcasted.
+      if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 
+        return SDValue();
+
+      SDValue Sc = Op.getOperand(0);
+      if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 
+        return SDValue();
+
+      Ld = Sc.getOperand(0);
+
+      // The scalar_to_vector node and the suspected
+      // load node must have exactly one user.
+      if (!Sc.hasOneUse() || !Ld.hasOneUse())
+        return SDValue();
+      break;
+    }
+  }
+  
+  // The scalar source must be a normal load.
+  if (!ISD::isNormalLoad(Ld.getNode())) 
+    return SDValue();
+  
+  bool Is256 = VT.getSizeInBits() == 256;
+  bool Is128 = VT.getSizeInBits() == 128;
+  unsigned ScalarSize = Ld.getValueType().getSizeInBits();
+
+  // VBroadcast to YMM
+  if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
+    return Ld;
+
+  // VBroadcast to XMM
+  if (Is128 && (ScalarSize == 32))
+    return Ld;
+
+  // Unsupported broadcast.
+  return SDValue();
+}
+
 SDValue
 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
   DebugLoc dl = Op.getDebugLoc();
@@ -5138,6 +5216,10 @@
     return getOnesVector(Op.getValueType(), DAG, dl);
   }
 
+  SDValue LD = isVectorBroadcast(Op);
+  if (Subtarget->hasAVX() && LD.getNode())
+      return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
+
   unsigned EVTBits = ExtVT.getSizeInBits();
 
   unsigned NumZero  = 0;
@@ -6506,52 +6588,6 @@
   return 0;
 }
 
-/// isVectorBroadcast - Check if the node chain is suitable to be xformed to
-/// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
-/// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
-static bool isVectorBroadcast(SDValue &Op) {
-  EVT VT = Op.getValueType();
-  bool Is256 = VT.getSizeInBits() == 256;
-
-  assert((VT.getSizeInBits() == 128 || Is256) &&
-         "Unsupported type for vbroadcast node");
-
-  SDValue V = Op;
-  if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
-    V = V.getOperand(0);
-
-  if (Is256 && !(V.hasOneUse() &&
-                 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
-                 V.getOperand(0).getOpcode() == ISD::UNDEF))
-    return false;
-
-  if (Is256)
-    V = V.getOperand(1);
-
-  if (!V.hasOneUse())
-    return false;
-
-  // Check the source scalar_to_vector type. 256-bit broadcasts are
-  // supported for 32/64-bit sizes, while 128-bit ones are only supported
-  // for 32-bit scalars.
-  if (V.getOpcode() != ISD::SCALAR_TO_VECTOR)
-    return false;
-
-  unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
-  if (ScalarSize != 32 && ScalarSize != 64)
-    return false;
-  if (!Is256 && ScalarSize == 64)
-    return false;
-
-  V = V.getOperand(0);
-  if (!MayFoldLoad(V))
-    return false;
-
-  // Return the load node
-  Op = V;
-  return true;
-}
-
 static
 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
                                const TargetLowering &TLI,
@@ -6577,8 +6613,9 @@
       return Op;
 
     // Use vbroadcast whenever the splat comes from a foldable load
-    if (Subtarget->hasAVX() && isVectorBroadcast(V1))
-      return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
+    SDValue LD = isVectorBroadcast(Op);
+    if (Subtarget->hasAVX() && LD.getNode())
+      return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
 
     // Handle splats by matching through known shuffle masks
     if ((Size == 128 && NumElem <= 4) ||

Modified: llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll?rev=144720&r1=144719&r2=144720&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll Tue Nov 15 16:50:37 2011
@@ -1,7 +1,4 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
-; XFAIL: *
-
-; xfail this file for now because of PR8156, when it gets solved merge this with avx-splat.ll
 
 ; CHECK: vbroadcastsd (%
 define <4 x i64> @A(i64* %ptr) nounwind uwtable readnone ssp {



From echristo at apple.com  Tue Nov 15 16:55:12 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 15 Nov 2011 14:55:12 -0800
Subject: [llvm-commits] [llvm] r144600 - /llvm/trunk/docs/index.html
In-Reply-To: <BA28389A-EC10-4249-8FC5-7A9B67715E34@apple.com>
References: <20111115011437.85FCD2A6C131@llvm.org>
	<17583FD5-F653-485D-9255-19A42D71BFFB@apple.com>
	<04027E85-8C4F-4DCD-AAF7-68CE8C9C036F@apple.com>
	<BA28389A-EC10-4249-8FC5-7A9B67715E34@apple.com>
Message-ID: <71AB53E3-1E82-4452-8D7C-E462456413CF@apple.com>


On Nov 15, 2011, at 2:29 PM, Chris Lattner wrote:

> On Nov 15, 2011, at 10:06 AM, Devang Patel wrote:
>>> 
>>> Can this be merged into some other document, like the SourceLevelDebugging doc?
>>> 
>> 
>> SourceLevelDebugging is meant for clang+llvm developers. Where as lldb developers are also targeted by this doc and I also expect to see a doc on recent accelerator tables work where audience is llvm+lldb developers.
>> 
>> If you still think SourceLevelDebugging is appropriate then I'll merge them.
> 
> Yes, please make a new major "LLVM Dwarf Extensions" section in Source Level Debugging.  Thanks!

Good idea. I'll throw the other spec in there when I get it a bit more cleaned up.

-eric

From nadav.rotem at intel.com  Tue Nov 15 16:54:21 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Tue, 15 Nov 2011 22:54:21 -0000
Subject: [llvm-commits] [llvm] r144721 -
	/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <20111115225421.886D72A6C132@llvm.org>

Author: nadav
Date: Tue Nov 15 16:54:21 2011
New Revision: 144721

URL: http://llvm.org/viewvc/llvm-project?rev=144721&view=rev
Log:
Fix MSVC warnings by adding a cast. 

Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=144721&r1=144720&r2=144721&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Nov 15 16:54:21 2011
@@ -3827,8 +3827,8 @@
       // Remove any extra phis created by processing inner loops.
       SmallVector<WeakVH, 16> DeadInsts;
       SCEVExpander Rewriter(SE, "lsr");
-      Changed |= Rewriter.replaceCongruentIVs(L, &DT, DeadInsts);
-      Changed |= DeleteTriviallyDeadInstructions(DeadInsts);
+      Changed |= (bool)Rewriter.replaceCongruentIVs(L, &DT, DeadInsts);
+      Changed |= (bool)DeleteTriviallyDeadInstructions(DeadInsts);
     }
     DEBUG(dbgs() << "LSR skipping outer loop " << *L << "\n");
     return;
@@ -3880,8 +3880,8 @@
     // Remove any extra phis created by processing inner loops.
     SmallVector<WeakVH, 16> DeadInsts;
     SCEVExpander Rewriter(SE, "lsr");
-    Changed |= Rewriter.replaceCongruentIVs(L, &DT, DeadInsts);
-    Changed |= DeleteTriviallyDeadInstructions(DeadInsts);
+    Changed |= (bool)Rewriter.replaceCongruentIVs(L, &DT, DeadInsts);
+    Changed |= (bool)DeleteTriviallyDeadInstructions(DeadInsts);
   }
 }
 



From grosbach at apple.com  Tue Nov 15 16:54:42 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 22:54:42 -0000
Subject: [llvm-commits] [llvm] r144722 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrFormats.td ARMInstrNEON.td
Message-ID: <20111115225442.B77752A6C132@llvm.org>

Author: grosbach
Date: Tue Nov 15 16:54:42 2011
New Revision: 144722

URL: http://llvm.org/viewvc/llvm-project?rev=144722&view=rev
Log:
ARM assembly parsing for data type suffices on NEON VMOV aliases.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=144722&r1=144721&r2=144722&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Nov 15 16:54:42 2011
@@ -2041,9 +2041,26 @@
   def _64 : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
   defm : VFPDT64ReqInstAlias<opc, asm, Result>;
 }
+multiclass VFPDT64NoF64ReqInstAlias<string opc, string asm, dag Result> {
+  def I64 : VFPDataTypeInstAlias<opc, ".i64", asm, Result>;
+  def S64 : VFPDataTypeInstAlias<opc, ".s64", asm, Result>;
+  def U64 : VFPDataTypeInstAlias<opc, ".u64", asm, Result>;
+  def D   : VFPDataTypeInstAlias<opc, ".d",   asm, Result>;
+}
+// VFPDT64ReqInstAlias plus plain ".64"
+multiclass VFPDT64NoF64InstAlias<string opc, string asm, dag Result> {
+  def _64 : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
+  defm : VFPDT64ReqInstAlias<opc, asm, Result>;
+}
 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
   defm : VFPDT8InstAlias<opc, asm, Result>;
   defm : VFPDT16InstAlias<opc, asm, Result>;
   defm : VFPDT32InstAlias<opc, asm, Result>;
   defm : VFPDT64InstAlias<opc, asm, Result>;
 }
+multiclass VFPDTAnyNoF64InstAlias<string opc, string asm, dag Result> {
+  defm : VFPDT8InstAlias<opc, asm, Result>;
+  defm : VFPDT16InstAlias<opc, asm, Result>;
+  defm : VFPDT32InstAlias<opc, asm, Result>;
+  defm : VFPDT64NoF64InstAlias<opc, asm, Result>;
+}

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=144722&r1=144721&r2=144722&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Nov 15 16:54:42 2011
@@ -4469,6 +4469,10 @@
                 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
 def : InstAlias<"vmov${p} $Vd, $Vm",
                 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
+defm : VFPDTAnyNoF64InstAlias<"vmov${p}", "$Vd, $Vm",
+                              (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
+defm : VFPDTAnyNoF64InstAlias<"vmov${p}", "$Vd, $Vm",
+                              (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
 
 //   VMOV     : Vector Move (Immediate)
 



From dpatel at apple.com  Tue Nov 15 16:59:54 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 15 Nov 2011 22:59:54 -0000
Subject: [llvm-commits] [llvm] r144724 - in /llvm/trunk/docs:
 ObjCPropertyDebugInfo.html SourceLevelDebugging.html index.html
Message-ID: <20111115225954.8424C2A6C132@llvm.org>

Author: dpatel
Date: Tue Nov 15 16:59:54 2011
New Revision: 144724

URL: http://llvm.org/viewvc/llvm-project?rev=144724&view=rev
Log:
Merge ObjCPropertyDebugInfo.html  into SourceLevelDebugging.html

Removed:
    llvm/trunk/docs/ObjCPropertyDebugInfo.html
Modified:
    llvm/trunk/docs/SourceLevelDebugging.html
    llvm/trunk/docs/index.html

Removed: llvm/trunk/docs/ObjCPropertyDebugInfo.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ObjCPropertyDebugInfo.html?rev=144723&view=auto
==============================================================================
--- llvm/trunk/docs/ObjCPropertyDebugInfo.html (original)
+++ llvm/trunk/docs/ObjCPropertyDebugInfo.html (removed)
@@ -1,237 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
-                      "http://www.w3.org/TR/html4/strict.dtd">
-<html>
-<head>
-  <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
-  <title>Debugging Information Extension for Objective C Properties</title>
-  <link rel="stylesheet" href="llvm.css" type="text/css">
-</head>
-<body>
-
-<h1>
-  Debugging Information Extension for Objective C Properties
-</h1>
-
-<ol>
-  <li><a href="#introduction">Introduction</a></li>
-  <li><a href="#proposal">Proposal</a></li>
-  <li><a href="#newattributes">New DWARF Attributes</a></li>
-  <li><a href="#newconstants">New DWARF Constants</a></li>
-
-</ol>
-
-<div class="doc_author">
-  <p>Written by Jim Ingham and Devang Patel </p>
-</div>
-
-<!-- *********************************************************************** -->
-<h2>
-  <a name="introduction">Introduction</a>
-</h2>
-<!-- *********************************************************************** -->
-
-<div>
-<p>Objective C provides a simpler way to declare and define accessor methods 
-using declared properties. The language provides features to declare a 
-property and to let compiler synthesize accessor methods.
-</p>
-
-<p>The debugger lets developer inspect Objective C interfaces and their 
-instance variables and class variables. However, the debugger does not know 
-anything about the properties defined in Objective C interfaces. The debugger
-consumes information generated by compiler in DWARF format. The format does 
-not support encoding of Objective C properties. This proposal describes DWARF
-extensions to encode Objective C properties, which the debugger can use to let
-developers inspect Objective C properties.
-</p>
-
-</div>
-
-
-<!-- *********************************************************************** -->
-<h2>
-  <a name="proposal">Proposal</a>
-</h2>
-<!-- *********************************************************************** -->
-
-<div>
-<p>Objective C properties are always backed by an instance variable. The 
-instance variables backing properties are identified using 
-DW_AT_APPLE_property_name attribute. The instance variables with this 
-attribute may not have data location attributes. The location of instance 
-variables is determined by debugger only after consulting Objective C runtime.
-</p>
-
-<div class="doc_code">
-<pre>
- at interface I1 { 
-  int n2;
-} 
-
- at property p1; 
- at property p2; 
- at end
-
- at implementation I1 
- at synthesize p1; 
- at synthesize p2 = n2; 
- at end
-
-
-TAG_structure_type [7] * 
-  AT_APPLE_runtime_class( 0x10 )
-  AT_name( "I1" )
-  AT_decl_file( "Objc_Property.m" ) 
-  AT_decl_line( 3 )
-
-  TAG_member [8] 
-    AT_name( "p1" )
-    AT_APPLE_property_name(???p1???) 
-    AT_type( {0x00000147} ( int ) )
-
-  TAG_member [8] 
-    AT_name( "n2" )
-    AT_APPLE_property_name(???p2???) 
-    AT_type( {0x00000147} ( int ) )
-</pre>
-</div>
-
-<p> Developers can decorate a property with attributes which are encoded using 
-DW_AT_APPLE_property_attribute.
-</p>
-
-<div class="doc_code">
-<pre>
- at property (readonly, nonatomic) int pr;
-
-
-TAG_member [8] 
-  AT_name(???pr???) 
-  AT_APPLE_property_name(???pr???) 
-  AT_type ( {0x00000147} (int) ) 
-  AT_APPLE_property_attribute (DW_APPLE_PROPERTY_readonly, DW_APPLE_PROPERTY_nonatomic)
-</pre>
-</div>
-
-<p> The setter and getter method names are attached to the property using 
-DW_AT_APPLE_property_setter and DW_AT_APPLE_property_getter attributes.
-</p>
-<div class="doc_code">
-<pre>
- at interface I1 
- at property (setter=myOwnP3Setter:) int p3; 
--(void)myOwnP3Setter:(int)a; 
- at end
-
- at implementation I1 
- at synthesize p3;
--(void)myOwnP3Setter:(int)a{ } 
- at end
-
-0x000003bd: TAG_structure_type [7] * 
-              AT_APPLE_runtime_class( 0x10 )
-              AT_name( "I1" )
-              AT_decl_file( "Objc_Property.m" ) 
-              AT_decl_line( 3 )
-0x000003f3: TAG_member [8] 
-              AT_name( "p3" ) 
-              AT_APPLE_property_name(???p3???) 
-              AT_APPLE_property_setter(???myOwnP3Setter:???)
-              AT_type( {0x00000147} ( int ) )
-</pre>
-</div>
-
-</div>
-
-<!-- *********************************************************************** -->
-<h2>
-  <a name="newattributes">New DWARF Attributes</a>
-</h2>
-<!-- *********************************************************************** -->
-
-<div>
-<table border="1" cellspacing="0">
-  <tr>
-    <th width=200 >Attribute</th>
-    <th width=200 >Value</th>
-    <th width=200 >Classes</th>
-  </tr>
-  <tr>
-    <td width=200 >DW_AT_APPLE_property_name</td>
-    <td width=200 >0x3fe8</td>
-    <td width=200 >String</td>
-  </tr>
-  <tr>
-    <td width=200 >DW_AT_APPLE_property_getter</td>
-    <td width=200 >0x3fe9</td>
-    <td width=200 >String</td>
-  </tr>
-  <tr>
-    <td width=200 >DW_AT_APPLE_property_setter</td>
-    <td width=200 >0x3fea</td>
-    <td width=200 >String</td>
-  </tr>
-  <tr>
-    <td width=200 >DW_AT_APPLE_property_attribute</td>
-    <td width=200 >0x3feb</td>
-    <td width=200 >Constant</td>
-  </tr>
-</table>
-
-</div>
-
-<!-- *********************************************************************** -->
-<h2>
-  <a name="newconstants">New DWARF Constants</a>
-</h2>
-<!-- *********************************************************************** -->
-
-<div>
-<table border="1" cellspacing="0">
-  <tr>
-    <th width=200 >Name</th>
-    <th width=200 >Value</th>
-  </tr>
-  <tr>
-    <td width=200 >DW_AT_APPLE_PROPERTY_readonly</td>
-    <td width=200 >0x1</td>
-  </tr>
-  <tr>
-    <td width=200 >DW_AT_APPLE_PROPERTY_readwrite</td>
-    <td width=200 >0x2</td>
-  </tr>
-  <tr>
-    <td width=200 >DW_AT_APPLE_PROPERTY_assign</td>
-    <td width=200 >0x4</td>
-  </tr>
-  <tr>
-    <td width=200 >DW_AT_APPLE_PROPERTY_retain</td>
-    <td width=200 >0x8</td>
-  </tr>
-  <tr>
-    <td width=200 >DW_AT_APPLE_PROPERTY_copy</td>
-    <td width=200 >0x10</td>
-  </tr>
-  <tr>
-    <td width=200 >DW_AT_APPLE_PROPERTY_nonatomic</td>
-    <td width=200 >0x20</td>
-  </tr>
-</table>
-
-</div>
-
-<!-- *********************************************************************** -->
-
-<hr>
-<address>
-  <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
-  src="http://jigsaw.w3.org/css-validator/images/vcss-blue" alt="Valid CSS"></a>
-  <a href="http://validator.w3.org/check/referer"><img
-  src="http://www.w3.org/Icons/valid-html401-blue" alt="Valid HTML 4.01"></a>
-
-  <a href="http://llvm.org/">LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2011-11-14 $
-</address>
-
-</body>
-</html>

Modified: llvm/trunk/docs/SourceLevelDebugging.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=144724&r1=144723&r2=144724&view=diff
==============================================================================
--- llvm/trunk/docs/SourceLevelDebugging.html (original)
+++ llvm/trunk/docs/SourceLevelDebugging.html Tue Nov 15 16:59:54 2011
@@ -53,6 +53,19 @@
     <li><a href="#ccxx_composite_types">C/C++ struct/union types</a></li>
     <li><a href="#ccxx_enumeration_types">C/C++ enumeration types</a></li>
   </ol></li>
+  <li><a href="#llvmdwarfextension">LLVM Dwarf Extensions</a>
+    <ol>
+      <li><a href="#objcproperty">Debugging Information Extension 
+	  for Objective C Properties</a></li>
+      <ul>
+	<li><a href="#objcpropertyintroduction">Introduction</a></li>
+	<li><a href="#objcpropertyproposal">Proposal</a></li>
+	<li><a href="#objcpropertynewattributes">New DWARF Attributes</a></li>
+	<li><a href="#objcpropertynewconstants">New DWARF Constants</a></li>
+      </ul>
+
+    </ol>
+  </li>
 </ul>
 </td>
 <td class="right">
@@ -1803,6 +1816,217 @@
 
 </div>
 
+
+<!-- *********************************************************************** -->
+<h2>
+  <a name="llvmdwarfextension">Debugging information format</a>
+</h2>
+<!-- *********************************************************************** -->
+<div>
+<!-- ======================================================================= -->
+<h3>
+  <a name="objcproperty">Debugging Information Extension for Objective C
+Properties</a></li>
+</h3>
+<div>
+<!-- *********************************************************************** -->
+<h4>
+  <a name="objcpropertyintroduction">Introduction</a>
+</h4>
+<!-- *********************************************************************** -->
+
+<div>
+<p>Objective C provides a simpler way to declare and define accessor methods 
+using declared properties. The language provides features to declare a 
+property and to let compiler synthesize accessor methods.
+</p>
+
+<p>The debugger lets developer inspect Objective C interfaces and their 
+instance variables and class variables. However, the debugger does not know 
+anything about the properties defined in Objective C interfaces. The debugger
+consumes information generated by compiler in DWARF format. The format does 
+not support encoding of Objective C properties. This proposal describes DWARF
+extensions to encode Objective C properties, which the debugger can use to let
+developers inspect Objective C properties.
+</p>
+
+</div>
+
+
+<!-- *********************************************************************** -->
+<h4>
+  <a name="objcpropertyproposal">Proposal</a>
+</h4>
+<!-- *********************************************************************** -->
+
+<div>
+<p>Objective C properties are always backed by an instance variable. The 
+instance variables backing properties are identified using 
+DW_AT_APPLE_property_name attribute. The instance variables with this 
+attribute may not have data location attributes. The location of instance 
+variables is determined by debugger only after consulting Objective C runtime.
+</p>
+
+<div class="doc_code">
+<pre>
+ at interface I1 { 
+  int n2;
+} 
+
+ at property p1; 
+ at property p2; 
+ at end
+
+ at implementation I1 
+ at synthesize p1; 
+ at synthesize p2 = n2; 
+ at end
+
+
+TAG_structure_type [7] * 
+  AT_APPLE_runtime_class( 0x10 )
+  AT_name( "I1" )
+  AT_decl_file( "Objc_Property.m" ) 
+  AT_decl_line( 3 )
+
+  TAG_member [8] 
+    AT_name( "p1" )
+    AT_APPLE_property_name(???p1???) 
+    AT_type( {0x00000147} ( int ) )
+
+  TAG_member [8] 
+    AT_name( "n2" )
+    AT_APPLE_property_name(???p2???) 
+    AT_type( {0x00000147} ( int ) )
+</pre>
+</div>
+
+<p> Developers can decorate a property with attributes which are encoded using 
+DW_AT_APPLE_property_attribute.
+</p>
+
+<div class="doc_code">
+<pre>
+ at property (readonly, nonatomic) int pr;
+
+
+TAG_member [8] 
+  AT_name(???pr???) 
+  AT_APPLE_property_name(???pr???) 
+  AT_type ( {0x00000147} (int) ) 
+  AT_APPLE_property_attribute (DW_APPLE_PROPERTY_readonly, DW_APPLE_PROPERTY_nonatomic)
+</pre>
+</div>
+
+<p> The setter and getter method names are attached to the property using 
+DW_AT_APPLE_property_setter and DW_AT_APPLE_property_getter attributes.
+</p>
+<div class="doc_code">
+<pre>
+ at interface I1 
+ at property (setter=myOwnP3Setter:) int p3; 
+-(void)myOwnP3Setter:(int)a; 
+ at end
+
+ at implementation I1 
+ at synthesize p3;
+-(void)myOwnP3Setter:(int)a{ } 
+ at end
+
+0x000003bd: TAG_structure_type [7] * 
+              AT_APPLE_runtime_class( 0x10 )
+              AT_name( "I1" )
+              AT_decl_file( "Objc_Property.m" ) 
+              AT_decl_line( 3 )
+0x000003f3: TAG_member [8] 
+              AT_name( "p3" ) 
+              AT_APPLE_property_name(???p3???) 
+              AT_APPLE_property_setter(???myOwnP3Setter:???)
+              AT_type( {0x00000147} ( int ) )
+</pre>
+</div>
+
+</div>
+
+<!-- *********************************************************************** -->
+<h4>
+  <a name="objcpropertynewattributes">New DWARF Attributes</a>
+</h4>
+<!-- *********************************************************************** -->
+
+<div>
+<table border="1" cellspacing="0">
+  <tr>
+    <th width=200 >Attribute</th>
+    <th width=200 >Value</th>
+    <th width=200 >Classes</th>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_property_name</td>
+    <td width=200 >0x3fe8</td>
+    <td width=200 >String</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_property_getter</td>
+    <td width=200 >0x3fe9</td>
+    <td width=200 >String</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_property_setter</td>
+    <td width=200 >0x3fea</td>
+    <td width=200 >String</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_property_attribute</td>
+    <td width=200 >0x3feb</td>
+    <td width=200 >Constant</td>
+  </tr>
+</table>
+
+</div>
+
+<!-- *********************************************************************** -->
+<h4>
+  <a name="objcpropertynewconstants">New DWARF Constants</a>
+</h4>
+<!-- *********************************************************************** -->
+
+<div>
+<table border="1" cellspacing="0">
+  <tr>
+    <th width=200 >Name</th>
+    <th width=200 >Value</th>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_readonly</td>
+    <td width=200 >0x1</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_readwrite</td>
+    <td width=200 >0x2</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_assign</td>
+    <td width=200 >0x4</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_retain</td>
+    <td width=200 >0x8</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_copy</td>
+    <td width=200 >0x10</td>
+  </tr>
+  <tr>
+    <td width=200 >DW_AT_APPLE_PROPERTY_nonatomic</td>
+    <td width=200 >0x20</td>
+  </tr>
+</table>
+
+</div>
+</div>
+</div>
+
 <!-- *********************************************************************** -->
 
 <hr>

Modified: llvm/trunk/docs/index.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/index.html?rev=144724&r1=144723&r2=144724&view=diff
==============================================================================
--- llvm/trunk/docs/index.html (original)
+++ llvm/trunk/docs/index.html Tue Nov 15 16:59:54 2011
@@ -212,9 +212,6 @@
 <li><a href="BranchWeightMetadata.html">Branch Weight Metadata</a> - Provides
 information about Branch Prediction Information.</li>
 
-<li><a href="ObjCPropertyDebugInfo.html">Objective C Property Debug Info</a> 
-- Debugging information extension for Objective C Property.</li>
-
 </ul>
 
 <!--=======================================================================-->



From dpatel at apple.com  Tue Nov 15 17:02:45 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 15 Nov 2011 15:02:45 -0800
Subject: [llvm-commits] [llvm] r144600 - /llvm/trunk/docs/index.html
In-Reply-To: <BA28389A-EC10-4249-8FC5-7A9B67715E34@apple.com>
References: <20111115011437.85FCD2A6C131@llvm.org>
	<17583FD5-F653-485D-9255-19A42D71BFFB@apple.com>
	<04027E85-8C4F-4DCD-AAF7-68CE8C9C036F@apple.com>
	<BA28389A-EC10-4249-8FC5-7A9B67715E34@apple.com>
Message-ID: <E2C1C4A2-AF5F-471D-9EDD-CABF95CD4EEA@apple.com>


On Nov 15, 2011, at 2:29 PM, Chris Lattner wrote:

> On Nov 15, 2011, at 10:06 AM, Devang Patel wrote:
>>> 
>>> Can this be merged into some other document, like the SourceLevelDebugging doc?
>>> 
>> 
>> SourceLevelDebugging is meant for clang+llvm developers. Where as lldb developers are also targeted by this doc and I also expect to see a doc on recent accelerator tables work where audience is llvm+lldb developers.
>> 
>> If you still think SourceLevelDebugging is appropriate then I'll merge them.
> 
> Yes, please make a new major "LLVM Dwarf Extensions" section in Source Level Debugging.  Thanks!

Sure. done. r144724.
-
Devang


From tonic at nondot.org  Tue Nov 15 17:15:55 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Tue, 15 Nov 2011 23:15:55 -0000
Subject: [llvm-commits] [www] r144726 - /www/trunk/index.html
Message-ID: <20111115231555.31B5D2A6C132@llvm.org>

Author: tbrethou
Date: Tue Nov 15 17:15:54 2011
New Revision: 144726

URL: http://llvm.org/viewvc/llvm-project?rev=144726&view=rev
Log:
Update release schedule.

Modified:
    www/trunk/index.html

Modified: www/trunk/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=144726&r1=144725&r2=144726&view=diff
==============================================================================
--- www/trunk/index.html (original)
+++ www/trunk/index.html Tue Nov 15 17:15:54 2011
@@ -141,15 +141,11 @@
 <div class="www_sectiontitle">Upcoming Releases</div>
 
 <div class="www_text">
-<p><b>LLVM 3.0 Release: Tentative Schedule</b></p>
+<p><b>LLVM 3.0 Release: Current Schedule</b></p>
 <ul>
-  <li><b>October 14th</b> &mdash; Create 3.0 branch</li>
-  <li><b>October 16th</b> &mdash; First round of testing starts</li>
-  <li><b>October 23rd</b> &mdash; First round of testing ends / Bug fixing begins</li>
-  <li><b>October 30th</b> &mdash; Second round of testing starts</li>
-  <li><b>November 6th</b> &mdash; Second round of testing ends / Bug fixing begins</li>
-  <li><b>November 13th</b> &mdash; Finalization of binaries</li>
-  <li><b>November 16th</b> &mdash; Release!</li>
+  <li><b>November 16th</b> &mdash; Fourth round of testing begins.</li>
+  <li><b>November 28th</b> &mdash; Fourth round testing ends. Finalize binaries.
+  <li><b>November 30th</b> &mdash; Release!</li>
 </ul>
 </div>
 



From tlinth at codeaurora.org  Tue Nov 15 17:19:28 2011
From: tlinth at codeaurora.org (Tony Linthicum)
Date: Tue, 15 Nov 2011 17:19:28 -0600
Subject: [llvm-commits] Patch: new backend for Hexagon processor
In-Reply-To: <CAJdarcFKL91HwSttsQTcd8FkSaoT7Tz8Jxw1JBmESLo=kjOrpQ@mail.gmail.com>
References: <4EC17287.3090708@codeaurora.org>
	<CAJdarcFKL91HwSttsQTcd8FkSaoT7Tz8Jxw1JBmESLo=kjOrpQ@mail.gmail.com>
Message-ID: <4EC2F380.7010509@codeaurora.org>

On 11/14/2011 2:54 PM, Eli Friedman wrote:

>
> --- a/include/llvm/InitializePasses.h
> +++ b/include/llvm/InitializePasses.h
> @@ -233,6 +233,7 @@ void initializeVerifierPass(PassRegistry&);
>   void initializeVirtRegMapPass(PassRegistry&);
>   void initializeInstSimplifierPass(PassRegistry&);
>
> +void initializeHexagonHardwareLoopsPass(PassRegistry&);
>   }
>
>   #endif
>
> This change shouldn't be necessary; only target-independent passes
> need to be listed here, IIRC.
>

We are in the process of fixing this and will update with a new patch in 
a day or two.

> Your changes to add Data128bitsDirective etc. seem a bit confused...
> ".uleb128" is not a 128-bit integer in the sense you're using it.

Sorry about that.  It's a hack to fix an exception handling issue and we 
didn't intend to send it out.  I've removed it in the attached patches. 
  We will submit a proper fix at a later date.

> Also, please separate out the MC changes into a separate patch;
> they're interesting changes mixed into a bunch of mechanical changes,
> and it would be nice to have more eyes on them.

Done.  Please let me know if you'd like any further breakdown of the 
patches.

Thanks!

Tony


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
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From grosbach at apple.com  Tue Nov 15 17:19:15 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 15 Nov 2011 23:19:15 -0000
Subject: [llvm-commits] [llvm] r144727 - in /llvm/trunk:
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-vld-encoding.s
Message-ID: <20111115231915.5DA712A6C132@llvm.org>

Author: grosbach
Date: Tue Nov 15 17:19:15 2011
New Revision: 144727

URL: http://llvm.org/viewvc/llvm-project?rev=144727&view=rev
Log:
ARM assembly parsing for register range syntax for VLD/VST register lists.

For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/neon-vld-encoding.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144727&r1=144726&r2=144727&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 15 17:19:15 2011
@@ -2420,7 +2420,7 @@
   while (Parser.getTok().is(AsmToken::Comma) ||
          Parser.getTok().is(AsmToken::Minus)) {
     if (Parser.getTok().is(AsmToken::Minus)) {
-      Parser.Lex(); // Eat the comma.
+      Parser.Lex(); // Eat the minus.
       SMLoc EndLoc = Parser.getTok().getLoc();
       int EndReg = tryParseRegister();
       if (EndReg == -1)
@@ -2530,7 +2530,39 @@
     ++Count;
   }
 
-  while (Parser.getTok().is(AsmToken::Comma)) {
+  while (Parser.getTok().is(AsmToken::Comma) ||
+         Parser.getTok().is(AsmToken::Minus)) {
+    if (Parser.getTok().is(AsmToken::Minus)) {
+      Parser.Lex(); // Eat the minus.
+      SMLoc EndLoc = Parser.getTok().getLoc();
+      int EndReg = tryParseRegister();
+      if (EndReg == -1) {
+        Error(EndLoc, "register expected");
+        return MatchOperand_ParseFail;
+      }
+      // Allow Q regs and just interpret them as the two D sub-registers.
+      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
+        EndReg = getDRegFromQReg(EndReg) + 1;
+      // If the register is the same as the start reg, there's nothing
+      // more to do.
+      if (Reg == EndReg)
+        continue;
+      // The register must be in the same register class as the first.
+      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
+        Error(EndLoc, "invalid register in register list");
+        return MatchOperand_ParseFail;
+      }
+      // Ranges must go from low to high.
+      if (Reg > EndReg) {
+        Error(EndLoc, "bad range in register list");
+        return MatchOperand_ParseFail;
+      }
+
+      // Add all the registers in the range to the register list.
+      Count += EndReg - Reg;
+      Reg = EndReg;
+      continue;
+    }
     Parser.Lex(); // Eat the comma.
     RegLoc = Parser.getTok().getLoc();
     int OldReg = Reg;

Modified: llvm/trunk/test/MC/ARM/neon-vld-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vld-encoding.s?rev=144727&r1=144726&r2=144727&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-vld-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-vld-encoding.s Tue Nov 15 17:19:15 2011
@@ -251,3 +251,11 @@
 @ CHECK: vld1.8	{d2, d3, d4}, [r2]      @ encoding: [0x0f,0x26,0x22,0xf4]
 @ CHECK: vld1.32 {d2, d3, d4}, [r2]     @ encoding: [0x8f,0x26,0x22,0xf4]
 @ CHECK: vld1.64 {d2, d3, d4}, [r2]     @ encoding: [0xcf,0x26,0x22,0xf4]
+
+
+@ Register lists can use the range syntax, just like VLDM
+	vld1.f64 {d2-d5}, [r2,:128]!
+	vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
+
+@ CHECK: vld1.64 {d2, d3, d4, d5}, [r2, :128]! @ encoding: [0xed,0x22,0x22,0xf4]
+@ CHECK: vld1.64 {d2, d3, d4, d5}, [r2, :128]! @ encoding: [0xed,0x22,0x22,0xf4]



From mcrosier at apple.com  Tue Nov 15 17:34:05 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Tue, 15 Nov 2011 23:34:05 -0000
Subject: [llvm-commits] [llvm] r144730 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <20111115233405.787E32A6C132@llvm.org>

Author: mcrosier
Date: Tue Nov 15 17:34:05 2011
New Revision: 144730

URL: http://llvm.org/viewvc/llvm-project?rev=144730&view=rev
Log:
GEPs with all zero indices are trivially coalesced by fast-isel.  For example,

%arrayidx135 = getelementptr inbounds [4 x [4 x [4 x [4 x i32]]]]* %M0, i32 0, i64 0
%arrayidx136 = getelementptr inbounds [4 x [4 x [4 x i32]]]* %arrayidx135, i32 0, i64 %idxprom134

Prior to this commit, the GEP instruction that defines %arrayidx136 thought that 
%arrayidx135 was a trivial kill.  The GEP that defines %arrayidx135 doesn't 
generate any code and thus %M0 gets folded into the second GEP.  Thus, we need
to look through GEPs with all zero indices.
rdar://10443319

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=144730&r1=144729&r2=144730&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Nov 15 17:34:05 2011
@@ -96,6 +96,11 @@
         !hasTrivialKill(Cast->getOperand(0)))
       return false;
 
+  // GEPs with all zero indices are trivially coalesced by fast-isel.
+  if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I))
+    if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0)))
+      return false;
+
   // Only instructions with a single use in the same basic block are considered
   // to have trivial kills.
   return I->hasOneUse() &&



From hfinkel at anl.gov  Tue Nov 15 17:38:58 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Tue, 15 Nov 2011 17:38:58 -0600
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <4EBDB1BF.7090006@grosser.es>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
	<1319919418.23036.881.camel@sapling>
	<1319928991.23036.957.camel@sapling>
	<1320108633.23036.1266.camel@sapling>
	<1320172356.23036.1298.camel@sapling>
	<4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling>
	<1320191694.23036.1497.camel@sapling>
	<1320749109.19359.76.camel@sapling>
	<4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling>
	<4EB98207.2070807@grosser.es> <1320791390.19359.262.camel@sapling>
	<4EBC4B0F.6010609@grosser.es> <1321050998.19359.539.camel@sapling>
	<4EBDA7F9.9080709@grosser.es> <1321053083.19359.550.camel@sapling>
	<4EBDB1BF.7090006@grosser.es>
Message-ID: <1321400339.19359.782.camel@sapling>

Tobias,

I've attached the latest version of my autovectorization patch. I was
able to add support for using the ScalarEvolution analysis for
load/store pairing (thanks for your help!). This led to a modest
performance increase and a modest compile-time increase. This version
also has a cutoff as you suggested (although the default value is set
high (4000 instructions between pairs) because setting it lower led to
performance regressions in both run time and compile time).

At this point there seem to be no unexpected test-suite compile
failures. Some of the tests, however, do seem to compute the wrong
output. I've yet to determine whether this is due to bad instruction
fusing or some error in a later stage. I'll try running the failing
tests in the interpreter and/or on another platform.

Thanks again,
Hal

On Sat, 2011-11-12 at 00:37 +0100, Tobias Grosser wrote:
> On 11/12/2011 12:11 AM, Hal Finkel wrote:
> > On Fri, 2011-11-11 at 23:55 +0100, Tobias Grosser wrote:
> >> On 11/11/2011 11:36 PM, Hal Finkel wrote:
> >>> On Thu, 2011-11-10 at 23:07 +0100, Tobias Grosser wrote:
> >>>> On 11/08/2011 11:29 PM, Hal Finkel wrote: Talking about this I
> >>>> looked again into ScalarEvolution.
> >>>>
> >>>> To analyze a load, you would do:
> >>>>
> >>>> LoadInst *Load = ... Value *Pointer = Load->getPointer(); const
> >>>> SCEV *PointerSCEV = SE->getSCEV(Pointer); const SCEVUnknown
> >>>> *PointerBase =
> >>>> dyn_cast<SCEVUnknown>(SE->getPointerBase(PointerSCEV));
> >>>>
> >>>> if (!PointerBase) return 'Analysis failed'
> >>>>
> >>>> const Value *BaseValue = PointerBase->getValue();
> >>>>
> >>>> You get the offset between two load addresses with
> >>>> SE->getMinusSCEV(). The size of an element is
> >>>> SE->getSizeOfExpr().
> >>>>
> >>>
> >>> The AliasAnalysis class has a set of interfaces that can be used
> >>> to preserve the analysis even when some things are changed. Does
> >>> ScalarEvolution have a similar capability?
> >>
> >> You can state that your pass preserves ScalarEvolution. In this
> >> case all analysis results are by default preserved and it is your
> >> job to invalidate the scalar evolution for the loops/values where
> >> it needs to be recalculated.
> >>
> >> The relevant functions are
> >>
> >> ScalarEvolution::forgetValue(Value *)
> >
> > Since the vectorization pass is currently just a basic-block pass, I
> > think that I should need only forgetValue, right? I suppose that I
> > would call that on all of the values that are fused.
> 
> You call it on all the values/instructions that are removed and for
> those where the result calculated has changed.
> 
> > Also, using getPointerBase to get the base pointer seems simple
> > enough, but how should I use getMinusSCEV to get the offset.
> 
> This should give you the offset from the base pointer:
> 
> LoadInst *Load = ...
> Value *Pointer = Load->getPointer();
> const SCEV *PointerSCEV = SE->getSCEV(Pointer);
> const SCEVUnknown *PointerBase =
> 	dyn_cast<SCEVUnknown>(SE->getPointerBase(PointerSCEV));
> 
> if (!PointerBase)
>    return 'Analysis failed'
> 
> const SCEV *OffsetFromBase = SE->getMinusSCEV(Pointer, PointerBase);
> 
> > Should I call it on each load pointer and its base pointer, or
> > between the two load pointers once I know that they share the same
> > base.
> That depends what you want.
> 
> > And once I do that, how do I get the offset (if known). I see the
> > get[Uns|S]ignedRange functions, but if there is a way to directly get
> > a constant value, then that would be more straightforward.
> 
> I assume you want to know if two load addresses are either identical, 
> have stride one (have a offset of +1) or some other more complicated stuff.
> 
> What might work is the following (entirely untested):
> 
> LoadInst *LoadOne = ...
> LoadInst *LoadTwo = ...
> 
> Value *PointerOne = LoadOne->getPointer();
> Value *PointerTwo = LoadTwo->getPointer();
> 
> const SCEV *PointerOneSCEV = SE->getSCEV(PointerOne);
> const SCEV *PointerTwoSCEV = SE->getSCEV(PointerTwo);
> 
> // If this is a trivial offset we get something like 1*sizeof(long)
> const SCEV *Offset = SE->getMinusSCEV(PointerOneSCEV, PointerTwoSCEV);
> 
> // Now we devide it by the element size
> Type *AllocTy = LoadOne->getType()->getAllocTy();
> const SCEV *TypeOfSCEV = SE->getSizeOfExpr(AllocTy);
> const SCEV *OffsetInElements = SE->getUDivExpr(Offset, TypeOfSCEV);
> 
> if (const SCEVConstant *IntOffsetSCEV
> 	= dyn_cast<SCEVConstant>(OffsetInElements)) {
>    ConstantInt *IntOffset = IntOffsetSCEV->getValue()
>    return IntOffset;
> } else {
>    return "This seems to be a complicated offset";
> }
> 
> const SCEV *OffsetInElements = SE->getUDivExpr(Offset, TypeOfSCEV);
> 
> Let me know if this or something similar worked.
> Tobi
> 
> 
> 
> 
> 
> 
> 
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory
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From echristo at apple.com  Tue Nov 15 17:37:17 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 15 Nov 2011 23:37:17 -0000
Subject: [llvm-commits] [llvm] r144731 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp
Message-ID: <20111115233717.D4A032A6C132@llvm.org>

Author: echristo
Date: Tue Nov 15 17:37:17 2011
New Revision: 144731

URL: http://llvm.org/viewvc/llvm-project?rev=144731&view=rev
Log:
Stabilize the output of the dwarf accelerator tables. Fixes a comparison
failure during bootstrap with it turned on.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp?rev=144731&r1=144730&r2=144731&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp Tue Nov 15 17:37:17 2011
@@ -60,7 +60,7 @@
   uniques.resize(Data.size());
   for (size_t i = 0, e = Data.size(); i < e; ++i)
     uniques[i] = Data[i]->HashValue;
-  std::sort(uniques.begin(), uniques.end());
+  std::stable_sort(uniques.begin(), uniques.end());
   std::vector<uint32_t>::iterator p =
     std::unique(uniques.begin(), uniques.end());
   uint32_t num = std::distance(uniques.begin(), p);
@@ -73,6 +73,15 @@
   Header.hashes_count = num;
 }
 
+namespace {
+  // DIESorter - comparison predicate that sorts DIEs by their offset.
+  struct DIESorter {
+    bool operator()(DIE *A, DIE *B) const {
+      return A->getOffset() < B->getOffset();
+    }
+  };
+}
+
 void DwarfAccelTable::FinalizeTable(AsmPrinter *Asm, const char *Prefix) {
   // Create the individual hash data outputs.
   for (StringMap<DIEArray>::iterator
@@ -80,7 +89,7 @@
     struct HashData *Entry = new HashData((*EI).getKeyData());
 
     // Unique the entries.
-    std::sort((*EI).second.begin(), (*EI).second.end());
+    std::stable_sort((*EI).second.begin(), (*EI).second.end(), DIESorter());
     (*EI).second.erase(std::unique((*EI).second.begin(), (*EI).second.end()),
                        (*EI).second.end());
 



From tonic at nondot.org  Tue Nov 15 17:48:33 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Tue, 15 Nov 2011 23:48:33 -0000
Subject: [llvm-commits] [www] r144732 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20111115234833.F1EF22A6C132@llvm.org>

Author: tbrethou
Date: Tue Nov 15 17:48:33 2011
New Revision: 144732

URL: http://llvm.org/viewvc/llvm-project?rev=144732&view=rev
Log:
Update agenda with correct rooms. Update blurb on hacking session.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=144732&r1=144731&r2=144732&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Tue Nov 15 17:48:33 2011
@@ -80,7 +80,10 @@
 
 <div class="www_sectiontitle" id="hacking">Hacking Session</div>
 <p>
-There will be a hacking session the day before the developer meeting. This hacking session will run from 2:00-6:30. More details to come.
+There will be a hacking session the day before the Developer Meeting. This hacking session will run from 2:00 till late. Refreshments and networking provided. Bring your code and laptop. If people are flying in the night before for the Dev Meeting, or available after work, let them know and have them join us.</p>
+<p>
+San Jose Marriott
+Room 2500
 </p>
 
 <div class="www_sectiontitle" id="agenda">Agenda</div>
@@ -92,47 +95,47 @@
 <tr class="alt"><td>9:00 - 9:20</td><td><b>Welcome</b><br>Chris Lattner, <i>Apple Inc.</i></td><td>Ballroom Salon III/IV</td></tr>
 
 <tr><td rowspan=2>9:20 - 10:05</td><td><b><a href="#talk4">Extending Clang</a></b><br>Doug Gregor, <i>Apple Inc.</i></td><td>Ballroom Salon III/IV</td></tr>
-<tr><td><b><a href="#talk13">Intel OpenCL SDK Vectorizer</a></b><br>Nadav Rotem, <i>Intel</i></td><td>Ballroom Salon V/VI</td></tr>
+<tr><td><b><a href="#talk13">Intel OpenCL SDK Vectorizer</a></b><br>Nadav Rotem, <i>Intel</i></td><td>Ballroom Salon I/II</td></tr>
 
 <tr class="alt"><td rowspan=3>10:05 - 10:50</td><td><b><a href="#talk2">Clang MapReduce -- Automatic C++ Refactoring at Google Scale</a></b><br>Chandler Carruth, <i>Google</i></td><td>Ballroom Salon III/IV</td></tr>
-<tr class="alt"><td><b><a href="#talk11">PTX Back-End: GPU Programming With LLVM</a></b><br>Justin Holewinski, <i>Ohio State</i></td><td>Ballroom Salon V/VI</td></tr>
-<tr class="alt"><td><b>Improving LLVM Testing BOF</b><br>David Blaikie<i></i></td><td>Ballroom Salon II</td></tr>
+<tr class="alt"><td><b><a href="#talk11">PTX Back-End: GPU Programming With LLVM</a></b><br>Justin Holewinski, <i>Ohio State</i></td><td>Ballroom Salon I/II</td></tr>
+<tr class="alt"><td><b>Improving LLVM Testing BOF</b><br>David Blaikie<i></i></td><td>Ballroom Salon VI</td></tr>
 
 <tr><td>10:50 - 11:05</td><td>Break</td><td>Ballroom Foyer</td></tr>
 
 <tr class="alt"><td rowspan=2>11:05 - 11:50</td><td><b><a href="#talk1">Integrating LLVM into FreeBSD</a></b><br>Brooks Davis, <i>The FreeBSD Proje
 ct</i></td><td>Ballroom Salon III/IV</td></tr>
-<tr class="alt"><td><b><a href="#talk16">Porting LLVM to a Next Generation DSP</a></b><br>Taylor Simpson, <i>QuIC</i></td><td>Ballroom Salon V/VI</td></tr>
+<tr class="alt"><td><b><a href="#talk16">Porting LLVM to a Next Generation DSP</a></b><br>Taylor Simpson, <i>QuIC</i></td><td>Ballroom Salon I/II</td></tr>
 
 <tr><td rowspan=2>11:50 - 12:35</td><td><b><a href="#talk10">DXR: Semantic Code Browsing with Clang</a></b><br>Joshua Cranmer, <i>Mozilla</i></td><td>Ballroom Salon III/IV</td></tr>
-<tr><td><b><a href="#talk8">LLVM MC In Practice</a></b><br>Jim Grosbach, Owen Anderson <i>Apple Inc.</i></td><td>Ballroom Salon V/VI</td></tr>
+<tr><td><b><a href="#talk8">LLVM MC In Practice</a></b><br>Jim Grosbach, Owen Anderson <i>Apple Inc.</i></td><td>Ballroom Salon I/II</td></tr>
 
-<tr class="alt"><td>12:35 - 1:35</td><td>Lunch</td><td>TBD</td></tr>
+<tr class="alt"><td>12:35 - 1:35</td><td>Lunch</td><td>Ballroom Foyer (overflow Salon V)</td></tr>
 
 <tr><td rowspan=3>1:35 - 2:20</td><td><b><a href="#talk14">Using clang in the Chromium project</a></b><br>Nico Weber, Hans Wennborg, <i>Google</i></td><td>Ballroom Salon III/IV</td></tr>
-<tr><td><b><a href="#talk17">Polly - First successful optimizations - How to proceed?</a></b><br>Tobias Grosser, <i>ENS/INRIA</i></td><td>Ballroom Salon V/VI</td></tr>
-<tr><td><b>MC Linkers BOF</b><br>Luba Tang, <i>Mediatek</i>, Shih-wei Liao, <i>Google</i></td><td>Ballroom Salon II</td></tr>
+<tr><td><b><a href="#talk17">Polly - First successful optimizations - How to proceed?</a></b><br>Tobias Grosser, <i>ENS/INRIA</i></td><td>Ballroom Salon I/II</td></tr>
+<tr><td><b>MC Linkers BOF</b><br>Luba Tang, <i>Mediatek</i>, Shih-wei Liao, <i>Google</i></td><td>Ballroom Salon VI</td></tr>
 
 <tr class="alt"><td rowspan=3>2:20 - 3:05</td><td><b><a href="#talk15">Android Renderscript</a></b><br>Stephen Hines, <i>Google</i></td><td>Ballroom Salon III/IV</td></tr>
-<tr class="alt"><td><b><a href="#talk7">SKIR: Just-in-Time Compilation for Parallelism with LLVM</a></b><br>Jeff Fifield, <i>University of Colorado</i></td><td>Ballroom Salon V/VI</td></tr>
-<tr class="alt"><td><b>Improving the Clang Driver BOF</b><br>James Molloy, <i>ARM</i></td><td>Ballroom Salon II</td></tr>
+<tr class="alt"><td><b><a href="#talk7">SKIR: Just-in-Time Compilation for Parallelism with LLVM</a></b><br>Jeff Fifield, <i>University of Colorado</i></td><td>Ballroom Salon I/II</td></tr>
+<tr class="alt"><td><b>Improving the Clang Driver BOF</b><br>James Molloy, <i>ARM</i></td><td>Ballroom Salon VI</td></tr>
 
 <tr><td rowspan=5>3:05 - 3:45</td><td><b>Posters</b></td><td>Ballroom Foyer</td></tr>
-<tr><td><b><a href="#poster3">LunarGLASS: A LLVM-based shader compiler stack</a></b><br>Michael Ilseman, <i>LunarG</i></td><td>Ballroom Salon II</td></tr>
-<tr><td><b><a href="#poster4">Symbolic Testing of OpenCL Code</a></b><br>Peter Collingbourne, <i>Imperial College London</i></td><td>Ballroom Salon II</td></tr>
-<tr><td><b><a href="#poster2">Code verification based on attributes annotation - Implementing custom attributes check using Clang</a></b><br>Michael Han, <i>Autodesk</i></td><td>Ballroom Salon II</td></tr>
-<tr><td><b><a href="#poster1">Parfait - A Scalable Static Bug-Checking Tool Built on LLVM</a></b><br>Cristina Cifuentes, Nathan Keynes, Andrew Craik, Lian Li, Nathan Hawes, Andrew Browne, and Manuel Valdiviezo, <i>Oracle Labs</i></td><td>Ballroom Salon II</td></tr>
+<tr><td><b><a href="#poster3">LunarGLASS: A LLVM-based shader compiler stack</a></b><br>Michael Ilseman, <i>LunarG</i></td><td></td></tr>
+<tr><td><b><a href="#poster4">Symbolic Testing of OpenCL Code</a></b><br>Peter Collingbourne, <i>Imperial College London</i></td><td></td></tr>
+<tr><td><b><a href="#poster2">Code verification based on attributes annotation - Implementing custom attributes check using Clang</a></b><br>Michael Han, <i>Autodesk</i></td><td></td></tr>
+<tr><td><b><a href="#poster1">Parfait - A Scalable Static Bug-Checking Tool Built on LLVM</a></b><br>Cristina Cifuentes, Nathan Keynes, Andrew Craik, Lian Li, Nathan Hawes, Andrew Browne, and Manuel Valdiviezo, <i>Oracle Labs</i></td><td></td></tr>
 
 <tr class="alt"><td rowspan=2>3:45 - 4:30</td><td><b><a href="#talk6">Register Allocation in LLVM 3.0</a></b><br>Jakob Olesen, <i>Apple</i></td><td>Ballroom Salon III/IV</td></tr>
-<tr class="alt"><td><b><a href="#talk9">Exporting 3D scenes from Maya to WebGL using clang and LLVM</a></b><br>Jochen Wilhelmy, <i>consultant</i></td><td>Ballroom Salon V/VI</td></tr>
+<tr class="alt"><td><b><a href="#talk9">Exporting 3D scenes from Maya to WebGL using clang and LLVM</a></b><br>Jochen Wilhelmy, <i>consultant</i></td><td>Ballroom Salon I/II</td></tr>
 
 <tr><td rowspan=3>4:30 - 5:15</td><td><b><a href="#talk5">Super-optimizing LLVM IR</a></b><br>Duncan Sands, <i>DeepBlueCapital</i></td><td>Ballroom Salon III/IV</td></tr>
-<tr><td><b><a href="#talk12">Finding races and memory errors with LLVM instrumentation</a></b><br>Konstantin Serebryany, <i>Google</i></td><td>Ballroom Salon V/VI</td></tr>
-<tr><td><b>Bitcode Portability/Versioning BOF</b><br>Stephen Hines, David Sehr, <i>Google</i></td><td>Ballroom Salon II</td></tr>
+<tr><td><b><a href="#talk12">Finding races and memory errors with LLVM instrumentation</a></b><br>Konstantin Serebryany, <i>Google</i></td><td>Ballroom Salon I/II</td></tr>
+<tr><td><b>Bitcode Portability/Versioning BOF</b><br>Stephen Hines, David Sehr, <i>Google</i></td><td>Ballroom Salon VI</td></tr>
 
 <tr class="alt"><td rowspan=3>5:15 - 6:00</td><td><b><a href="#talk3">Thread Safety Annotations in Clang</a></b><br>DeLesley Hutchins, <i>Google</i></td><td>Ballroom Salon III/IV</td></tr>
-<tr class="alt"><td><b>Backend/Infrastructure Super BoF</b><br>Jim Grosbach, <i>Apple Inc.</i></td><td>Ballroom Salon V/VI</td></tr>
-<tr class="alt"><td><b>Community Event Planning</b><br>David Kipping, <i>Qualcomm</i></td><td>Ballroom Salon II</td></tr>
+<tr class="alt"><td><b>Backend/Infrastructure Super BoF</b><br>Jim Grosbach, <i>Apple Inc.</i></td><td>Ballroom Salon I/II</td></tr>
+<tr class="alt"><td><b>Community Event Planning</b><br>David Kipping, <i>Qualcomm</i></td><td>Ballroom Salon VI</td></tr>
 
 <tr><td>6:30 - 9:30</td><td>Dinner (Il Fornaio - Separate registration required)</td><td></td></tr>
 </table>



From tonic at nondot.org  Tue Nov 15 17:52:33 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Tue, 15 Nov 2011 23:52:33 -0000
Subject: [llvm-commits] [www] r144733 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20111115235233.1CABA2A6C132@llvm.org>

Author: tbrethou
Date: Tue Nov 15 17:52:32 2011
New Revision: 144733

URL: http://llvm.org/viewvc/llvm-project?rev=144733&view=rev
Log:
Update dinner details.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=144733&r1=144732&r2=144733&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Tue Nov 15 17:52:32 2011
@@ -299,7 +299,7 @@
 
 <div class="www_sectiontitle" id="dinner">Dinner</div>
 <p>Dinner attendance is capped at 140 and you must select this option during the registration process in order to attend.</p>
-<p>Dinner will be held after the meeting has concluded. The exact start time will be set once the meeting agenda is formalized. Dinner will be held at Il Fornaio which is within walking distance of the Marriott.
+<p>Dinner will be held after the meeting from 6:30-9:30. Dinner will be held at Il Fornaio which is across the street from the Marriott.
 </p>
 
 <p>



From stoklund at 2pi.dk  Tue Nov 15 17:53:19 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 15 Nov 2011 23:53:19 -0000
Subject: [llvm-commits] [llvm] r144734 -
	/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
Message-ID: <20111115235319.288382A6C132@llvm.org>

Author: stoklund
Date: Tue Nov 15 17:53:18 2011
New Revision: 144734

URL: http://llvm.org/viewvc/llvm-project?rev=144734&view=rev
Log:
Enable -widen-vmovs by default.

This will widen 32-bit register vmov instructions to 64-bit when
possible.  The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.

The copies are only widened if they are marked as clobbering the whole
D-register.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=144734&r1=144733&r2=144734&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Nov 15 17:53:18 2011
@@ -46,7 +46,7 @@
                cl::desc("Enable ARM 2-addr to 3-addr conv"));
 
 static cl::opt<bool>
-WidenVMOVS("widen-vmovs", cl::Hidden,
+WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
            cl::desc("Widen ARM vmovs to vmovd when possible"));
 
 /// ARM_MLxEntry - Record information about MLA / MLS instructions.



From tonic at nondot.org  Tue Nov 15 17:54:24 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Tue, 15 Nov 2011 23:54:24 -0000
Subject: [llvm-commits] [www] r144735 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20111115235424.3210B2A6C132@llvm.org>

Author: tbrethou
Date: Tue Nov 15 17:54:23 2011
New Revision: 144735

URL: http://llvm.org/viewvc/llvm-project?rev=144735&view=rev
Log:
Update company names.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=144735&r1=144734&r2=144735&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Tue Nov 15 17:54:23 2011
@@ -92,9 +92,9 @@
 <tr><th>Time</th><th>Talk</th><th>Location</th></tr>
 
 <tr><td>8:00 - 9:00</td><td>Breakfast</td><td>Ballroom Foyer</td></tr>
-<tr class="alt"><td>9:00 - 9:20</td><td><b>Welcome</b><br>Chris Lattner, <i>Apple Inc.</i></td><td>Ballroom Salon III/IV</td></tr>
+<tr class="alt"><td>9:00 - 9:20</td><td><b>Welcome</b><br>Chris Lattner, <i>Apple</i></td><td>Ballroom Salon III/IV</td></tr>
 
-<tr><td rowspan=2>9:20 - 10:05</td><td><b><a href="#talk4">Extending Clang</a></b><br>Doug Gregor, <i>Apple Inc.</i></td><td>Ballroom Salon III/IV</td></tr>
+<tr><td rowspan=2>9:20 - 10:05</td><td><b><a href="#talk4">Extending Clang</a></b><br>Doug Gregor, <i>Apple</i></td><td>Ballroom Salon III/IV</td></tr>
 <tr><td><b><a href="#talk13">Intel OpenCL SDK Vectorizer</a></b><br>Nadav Rotem, <i>Intel</i></td><td>Ballroom Salon I/II</td></tr>
 
 <tr class="alt"><td rowspan=3>10:05 - 10:50</td><td><b><a href="#talk2">Clang MapReduce -- Automatic C++ Refactoring at Google Scale</a></b><br>Chandler Carruth, <i>Google</i></td><td>Ballroom Salon III/IV</td></tr>
@@ -108,7 +108,7 @@
 <tr class="alt"><td><b><a href="#talk16">Porting LLVM to a Next Generation DSP</a></b><br>Taylor Simpson, <i>QuIC</i></td><td>Ballroom Salon I/II</td></tr>
 
 <tr><td rowspan=2>11:50 - 12:35</td><td><b><a href="#talk10">DXR: Semantic Code Browsing with Clang</a></b><br>Joshua Cranmer, <i>Mozilla</i></td><td>Ballroom Salon III/IV</td></tr>
-<tr><td><b><a href="#talk8">LLVM MC In Practice</a></b><br>Jim Grosbach, Owen Anderson <i>Apple Inc.</i></td><td>Ballroom Salon I/II</td></tr>
+<tr><td><b><a href="#talk8">LLVM MC In Practice</a></b><br>Jim Grosbach, Owen Anderson <i>Apple</i></td><td>Ballroom Salon I/II</td></tr>
 
 <tr class="alt"><td>12:35 - 1:35</td><td>Lunch</td><td>Ballroom Foyer (overflow Salon V)</td></tr>
 
@@ -134,7 +134,7 @@
 <tr><td><b>Bitcode Portability/Versioning BOF</b><br>Stephen Hines, David Sehr, <i>Google</i></td><td>Ballroom Salon VI</td></tr>
 
 <tr class="alt"><td rowspan=3>5:15 - 6:00</td><td><b><a href="#talk3">Thread Safety Annotations in Clang</a></b><br>DeLesley Hutchins, <i>Google</i></td><td>Ballroom Salon III/IV</td></tr>
-<tr class="alt"><td><b>Backend/Infrastructure Super BoF</b><br>Jim Grosbach, <i>Apple Inc.</i></td><td>Ballroom Salon I/II</td></tr>
+<tr class="alt"><td><b>Backend/Infrastructure Super BoF</b><br>Jim Grosbach, <i>Apple</i></td><td>Ballroom Salon I/II</td></tr>
 <tr class="alt"><td><b>Community Event Planning</b><br>David Kipping, <i>Qualcomm</i></td><td>Ballroom Salon VI</td></tr>
 
 <tr><td>6:30 - 9:30</td><td>Dinner (Il Fornaio - Separate registration required)</td><td></td></tr>
@@ -186,7 +186,7 @@
 
 <p> 
 <b><a id="talk8">LLVM MC In Practice</a></b><br>
-<i>Jim Grosbach, Owen Anderson -  Apple Inc.</i><br>
+<i>Jim Grosbach, Owen Anderson -  Apple</i><br>
 Overview of projects and new developments in the LLVM MC layer, with emphasis on the MCJIT, binary analysis, ARM integrated assembler and ARM disassembler.
 </p>
  



From tonic at nondot.org  Tue Nov 15 18:09:42 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Wed, 16 Nov 2011 00:09:42 -0000
Subject: [llvm-commits] [www] r144737 - /www/trunk/devmtg/2011-11/index.html
Message-ID: <20111116000942.C044B2A6C132@llvm.org>

Author: tbrethou
Date: Tue Nov 15 18:09:42 2011
New Revision: 144737

URL: http://llvm.org/viewvc/llvm-project?rev=144737&view=rev
Log:
Fix typo.

Modified:
    www/trunk/devmtg/2011-11/index.html

Modified: www/trunk/devmtg/2011-11/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2011-11/index.html?rev=144737&r1=144736&r2=144737&view=diff
==============================================================================
--- www/trunk/devmtg/2011-11/index.html (original)
+++ www/trunk/devmtg/2011-11/index.html Tue Nov 15 18:09:42 2011
@@ -103,8 +103,7 @@
 
 <tr><td>10:50 - 11:05</td><td>Break</td><td>Ballroom Foyer</td></tr>
 
-<tr class="alt"><td rowspan=2>11:05 - 11:50</td><td><b><a href="#talk1">Integrating LLVM into FreeBSD</a></b><br>Brooks Davis, <i>The FreeBSD Proje
-ct</i></td><td>Ballroom Salon III/IV</td></tr>
+<tr class="alt"><td rowspan=2>11:05 - 11:50</td><td><b><a href="#talk1">Integrating LLVM into FreeBSD</a></b><br>Brooks Davis, <i>The FreeBSD Project</i></td><td>Ballroom Salon III/IV</td></tr>
 <tr class="alt"><td><b><a href="#talk16">Porting LLVM to a Next Generation DSP</a></b><br>Taylor Simpson, <i>QuIC</i></td><td>Ballroom Salon I/II</td></tr>
 
 <tr><td rowspan=2>11:50 - 12:35</td><td><b><a href="#talk10">DXR: Semantic Code Browsing with Clang</a></b><br>Joshua Cranmer, <i>Mozilla</i></td><td>Ballroom Salon III/IV</td></tr>



From daniel at zuster.org  Tue Nov 15 18:20:30 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 00:20:30 -0000
Subject: [llvm-commits] [compiler-rt] r144738 -
	/compiler-rt/trunk/make/platform/darwin_bni.mk
Message-ID: <20111116002030.2900C2A6C132@llvm.org>

Author: ddunbar
Date: Tue Nov 15 18:20:29 2011
New Revision: 144738

URL: http://llvm.org/viewvc/llvm-project?rev=144738&view=rev
Log:
build/darwin_bni: Add a consistency check.

Modified:
    compiler-rt/trunk/make/platform/darwin_bni.mk

Modified: compiler-rt/trunk/make/platform/darwin_bni.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/darwin_bni.mk?rev=144738&r1=144737&r2=144738&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/darwin_bni.mk (original)
+++ compiler-rt/trunk/make/platform/darwin_bni.mk Tue Nov 15 18:20:29 2011
@@ -6,6 +6,9 @@
 # We override this with RC_ARCHS because B&I may want to build on an ARCH we
 # haven't explicitly defined support for. If all goes well, this will just work
 # and the resulting lib will just have generic versions for anything unknown.
+ifndef RC_ARCHS
+$(error "unexpected build of 'darwin_bni' platform without RC_ARCHS set")
+endif
 UniversalArchs := $(RC_ARCHS)
 
 ifneq (,$(SDKROOT))



From daniel at zuster.org  Tue Nov 15 18:20:36 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 00:20:36 -0000
Subject: [llvm-commits] [compiler-rt] r144739 - in /compiler-rt/trunk/lib:
 floatdidf.c floatdisf.c floattidf.c floattisf.c floattixf.c floatundidf.c
 floatundisf.c floatuntidf.c floatuntisf.c floatuntixf.c int_lib.h
Message-ID: <20111116002036.575202A6C132@llvm.org>

Author: ddunbar
Date: Tue Nov 15 18:20:36 2011
New Revision: 144739

URL: http://llvm.org/viewvc/llvm-project?rev=144739&view=rev
Log:
lib: Include float.h in int_lib.h, and eliminate duplicate includes from a number of source files.

Modified:
    compiler-rt/trunk/lib/floatdidf.c
    compiler-rt/trunk/lib/floatdisf.c
    compiler-rt/trunk/lib/floattidf.c
    compiler-rt/trunk/lib/floattisf.c
    compiler-rt/trunk/lib/floattixf.c
    compiler-rt/trunk/lib/floatundidf.c
    compiler-rt/trunk/lib/floatundisf.c
    compiler-rt/trunk/lib/floatuntidf.c
    compiler-rt/trunk/lib/floatuntisf.c
    compiler-rt/trunk/lib/floatuntixf.c
    compiler-rt/trunk/lib/int_lib.h

Modified: compiler-rt/trunk/lib/floatdidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatdidf.c?rev=144739&r1=144738&r2=144739&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatdidf.c (original)
+++ compiler-rt/trunk/lib/floatdidf.c Tue Nov 15 18:20:36 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <float.h>
 
 /* Returns: convert a to a double, rounding toward even. */
 

Modified: compiler-rt/trunk/lib/floatdisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatdisf.c?rev=144739&r1=144738&r2=144739&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatdisf.c (original)
+++ compiler-rt/trunk/lib/floatdisf.c Tue Nov 15 18:20:36 2011
@@ -12,8 +12,6 @@
  *===----------------------------------------------------------------------===
  */
 
-#include <float.h>
-
 /* Returns: convert a to a float, rounding toward even.*/
 
 /* Assumption: float is a IEEE 32 bit floating point type 

Modified: compiler-rt/trunk/lib/floattidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floattidf.c?rev=144739&r1=144738&r2=144739&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floattidf.c (original)
+++ compiler-rt/trunk/lib/floattidf.c Tue Nov 15 18:20:36 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <float.h>
 
 /* Returns: convert a to a double, rounding toward even.*/
 

Modified: compiler-rt/trunk/lib/floattisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floattisf.c?rev=144739&r1=144738&r2=144739&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floattisf.c (original)
+++ compiler-rt/trunk/lib/floattisf.c Tue Nov 15 18:20:36 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <float.h>
 
 /* Returns: convert a to a float, rounding toward even. */
 

Modified: compiler-rt/trunk/lib/floattixf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floattixf.c?rev=144739&r1=144738&r2=144739&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floattixf.c (original)
+++ compiler-rt/trunk/lib/floattixf.c Tue Nov 15 18:20:36 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <float.h>
 
 /* Returns: convert a to a long double, rounding toward even. */
 

Modified: compiler-rt/trunk/lib/floatundidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatundidf.c?rev=144739&r1=144738&r2=144739&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatundidf.c (original)
+++ compiler-rt/trunk/lib/floatundidf.c Tue Nov 15 18:20:36 2011
@@ -12,8 +12,6 @@
  * ===----------------------------------------------------------------------===
  */
 
-#include <float.h>
-
 /* Returns: convert a to a double, rounding toward even. */
 
 /* Assumption: double is a IEEE 64 bit floating point type 

Modified: compiler-rt/trunk/lib/floatundisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatundisf.c?rev=144739&r1=144738&r2=144739&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatundisf.c (original)
+++ compiler-rt/trunk/lib/floatundisf.c Tue Nov 15 18:20:36 2011
@@ -12,8 +12,6 @@
  *===----------------------------------------------------------------------===
  */
 
-#include <float.h>
-
 /* Returns: convert a to a float, rounding toward even. */
 
 /* Assumption: float is a IEEE 32 bit floating point type 

Modified: compiler-rt/trunk/lib/floatuntidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatuntidf.c?rev=144739&r1=144738&r2=144739&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatuntidf.c (original)
+++ compiler-rt/trunk/lib/floatuntidf.c Tue Nov 15 18:20:36 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <float.h>
 
 /* Returns: convert a to a double, rounding toward even. */
 

Modified: compiler-rt/trunk/lib/floatuntisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatuntisf.c?rev=144739&r1=144738&r2=144739&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatuntisf.c (original)
+++ compiler-rt/trunk/lib/floatuntisf.c Tue Nov 15 18:20:36 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <float.h>
 
 /* Returns: convert a to a float, rounding toward even. */
 

Modified: compiler-rt/trunk/lib/floatuntixf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatuntixf.c?rev=144739&r1=144738&r2=144739&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatuntixf.c (original)
+++ compiler-rt/trunk/lib/floatuntixf.c Tue Nov 15 18:20:36 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <float.h>
 
 /* Returns: convert a to a long double, rounding toward even. */
 

Modified: compiler-rt/trunk/lib/int_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_lib.h?rev=144739&r1=144738&r2=144739&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_lib.h (original)
+++ compiler-rt/trunk/lib/int_lib.h Tue Nov 15 18:20:36 2011
@@ -31,9 +31,13 @@
 # define COMPILER_RT_ABI
 #endif
 
+/* Include the standard compiler builtin headers we use functionality from. */
 #include <limits.h>
 #include <stdint.h>
 #include <stdbool.h>
+#include <float.h>
+
+/* Include the system math.h, which we use in a number of places. */
 #include <math.h>
 
 /* If compiling for kernel use, call panic() instead of abort(). */



From daniel at zuster.org  Tue Nov 15 18:20:40 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 00:20:40 -0000
Subject: [llvm-commits] [compiler-rt] r144740 -
	/compiler-rt/trunk/make/platform/darwin_bni.mk
Message-ID: <20111116002040.64AD82A6C132@llvm.org>

Author: ddunbar
Date: Tue Nov 15 18:20:40 2011
New Revision: 144740

URL: http://llvm.org/viewvc/llvm-project?rev=144740&view=rev
Log:
build/darwin_bni: Remove consistency check I added, I forgot we always load
every platform (even if it isn't being built).

Modified:
    compiler-rt/trunk/make/platform/darwin_bni.mk

Modified: compiler-rt/trunk/make/platform/darwin_bni.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/darwin_bni.mk?rev=144740&r1=144739&r2=144740&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/darwin_bni.mk (original)
+++ compiler-rt/trunk/make/platform/darwin_bni.mk Tue Nov 15 18:20:40 2011
@@ -6,9 +6,6 @@
 # We override this with RC_ARCHS because B&I may want to build on an ARCH we
 # haven't explicitly defined support for. If all goes well, this will just work
 # and the resulting lib will just have generic versions for anything unknown.
-ifndef RC_ARCHS
-$(error "unexpected build of 'darwin_bni' platform without RC_ARCHS set")
-endif
 UniversalArchs := $(RC_ARCHS)
 
 ifneq (,$(SDKROOT))



From kcc at google.com  Tue Nov 15 18:31:12 2011
From: kcc at google.com (Kostya Serebryany)
Date: Tue, 15 Nov 2011 16:31:12 -0800
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <CAN=P9piQT4=7vbGKfW+8zV7fff-7rjASxGH_AGDt=a3iLYrsmA@mail.gmail.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
	<1137D6EF-A4A8-4C7B-AAA7-831E5E36124F@apple.com>
	<CAN=P9pjg6r7r-csthwB0or1Y5h1GFXxdn4Tpj_jdtkn9SsDfcA@mail.gmail.com>
	<CAN=P9ph7ED02yrX_vvWu7AUgphRpU_4TcAPCmBoM9dQ1gVvGOA@mail.gmail.com>
	<CAN=P9piQT4=7vbGKfW+8zV7fff-7rjASxGH_AGDt=a3iLYrsmA@mail.gmail.com>
Message-ID: <CAN=P9pjf5V0mO=rPzR3Xt2RbW1iTaui748WFr4fBUAKXiE93tw@mail.gmail.com>

Hello,

Here is the fresh AddressSanitizer patch for your consideration.
This is LLVM-only patch.
If/when it is submitted, clang changes and the run-time library will
follow.
http://codereview.appspot.com/5393042/

Thanks,

--kcc

On Thu, Sep 15, 2011 at 1:31 PM, Kostya Serebryany <kcc at google.com> wrote:

> Hi,
>
> I haven't heard any more comments.
> Eric Christopher confirmed that the only concern is having the
> instrumentation pass w/o the run-time library.
> I do want to contribute run-time as well.
> How do we proceed?
>
> Let me describe the whole thing once more.
>
> AddressSanitizer finds
>   - Out-of-bounds accesses to heap, stack and globals
>   - Use-after-free (heap)
> The slowdown is typically within 2x:
> http://code.google.com/p/address-sanitizer/wiki/PerformanceNumbers
> It also has an experimental feature to detect use-after-return (stack).
>
> The tool currently works on x86 Linux and Mac, both 32- and 64- bits.
> The Linux port is absolutely stable (one can browse the web using
> instrumented Chromium for hours).
> The Mac port is slightly less stable (Chromium tests work, but the browser
> hiccups infrequently).
>
> The tool consists of two parts: instrumentation pass (~1KLOC) and run-time
> library (~3KLOC).
>
> The instrumentation pass being reviewed in this mail thread only supports
> detection of heap bugs.
> Other parts (~400 more LOC) will add stack, globals, and blacklisting.
>
> The run-time library replaces malloc/free/etc, intercepts other libc
> functions (e.g. pthread_create) and does error reporting.
> The library and test code uses google coding conventions.
> The integration tests use gtest.
>
> I'd like to have the run-time available as part of LLVM, and I would agree
> on any reasonable way of doing so in the following order of preference:
>   - use svn:externals to point to the existing repository at
> http://code.google.com/p/address-sanitizer/source/checkout
>   - copy the code to LLVM repository and periodically take the fresh
> versions from c.g.c repository.
>   - use the LLVM repository as the primary repository (here I am concerned
> with the tool chain: we are too used to the features provided by c.g.c.)
> Please suggest what suits LLVM the most.
>
> Thanks,
>
> --kcc
>
>
> On Mon, Sep 12, 2011 at 11:48 AM, Kostya Serebryany <kcc at google.com>wrote:
>
>> FYI
>> I've added noreturn attribute to the __asan_report_error call. It doesn't
>> cause compile problems in cpu2006 any more.
>> The good news is that the slowdown (compared to assembly with ud2) on
>> cpu2006 ranges between 1% and 8%.
>> And we may recover from it if __asan_report_error does not cause stack
>> frame to be created in leaf functions.
>>
>> --kcc
>>
>>
>> On Fri, Sep 9, 2011 at 12:48 PM, Kostya Serebryany <kcc at google.com>wrote:
>>
>>>
>>>
>>> On Thu, Sep 8, 2011 at 5:38 PM, Eric Christopher <echristo at apple.com>wrote:
>>>
>>>>
>>>> On Sep 8, 2011, at 5:14 PM, Kostya Serebryany wrote:
>>>>
>>>>
>>>>
>>>> On Thu, Sep 8, 2011 at 4:43 PM, Eric Christopher <echristo at apple.com>wrote:
>>>>
>>>>>
>>>>> On Sep 8, 2011, at 4:35 PM, Chandler Carruth wrote:
>>>>>
>>>>> > FYI,
>>>>> >
>>>>> > I've looked again at this patch recently, and talked to several
>>>>> others about it...
>>>>> >
>>>>> > I think there are some big issues with the implementation, bit I
>>>>> think they could probably be addressed. The one that I see the most is the
>>>>> x86 assembly just being dumped as a blob. I think that really needs to be
>>>>> resolved before this can move forward.
>>>>> >
>>>>> > It seems like this should be do-able in some way with the llvm.trap
>>>>> intrinsic. If anything, we might need another intrinsic or an extension of
>>>>> llvm.trap that allows feeding the SIGILL signal handler the data arguments
>>>>> it needs; I'd need to read up on exactly what is required for that to
>>>>> figure out how best to represent that in IR, but it shouldn't be that hard.
>>>>> >
>>>>> > That said, maybe to improve the discussion of the patch and make
>>>>> reviewing it easier, you could just switch to emitting the call to the
>>>>> runtime library function in all cases? That should be a strictly simpler
>>>>> patch, and then how to improve performance by avoiding the runtime call can
>>>>> be a followup.
>>>>> >
>>>>>
>>>>> This encompasses most of my concerns with the patch.
>>>>>
>>>>> > Maybe others could comment on other implementation issues? I'm sadly
>>>>> not an expert at LLVM...
>>>>>
>>>>> In a glance I didn't see a lot, but the other bits were somewhat
>>>>> hiding it. How about when we get a new patch we can take a bit more of a
>>>>> look at it.
>>>>>
>>>>
>>>> I dropped the assembly part and updated the patch at
>>>> http://codereview.appspot.com/4867059/ (also in attachment).
>>>> We can figure out how to make it more efficient later (something
>>>> like llvm.trap intrinsic with a parameter).
>>>>
>>>> This patch is 570 LOC plus few lines of trivial changes and a test.
>>>> It implements only basic functionality: detection of out-of-bounds and
>>>> use-after-free in heap.
>>>>
>>>> The complete version of LLVM pass is ~1000 LOC (
>>>> http://code.google.com/p/address-sanitizer/source/browse/trunk/llvm/AddressSanitizer.cpp
>>>> ).
>>>> It also handles out-of-bounds for stack and global objects and
>>>> (recently added) stack use-after-return bugs.
>>>>
>>>>
>>>> Some somewhat trivial issues:
>>>>
>>>> a) Please go ahead and hide the non-user visible flags.
>>>>
>>> done
>>>
>>>>
>>>> b) Not a big fan of this style of avoid 80-col wrap:
>>>>
>>>> +Instruction *AddressSanitizer::generateCrashCode(
>>>> +    IRBuilder<> &IRB, Value *Addr, int TelltaleValue) {
>>>>
>>> done
>>>
>>>>
>>>> c) +  // which will be lowered to a cusom assembly.
>>>>
>>>> s/cusom/custom
>>>>
>>>> d)
>>>>
>>>> +  if (TypeSize != 8 && TypeSize != 16 &&
>>>> +      TypeSize != 32 && TypeSize != 64 && TypeSize != 128) {
>>>> +    // TODO(kcc): do something better.
>>>> +    return;
>>>> +  }
>>>>
>>>> What's the reason behind this?
>>>>
>>>
>>> Changed the comment.
>>>
>>>
>>>>
>>>> Perhaps not so trivial:
>>>>
>>>> a) Where are the asan_* functions? Where are they supposed to live?
>>>>
>>>> I'll probably have more, but it's a start and the discussion on the
>>>> library functions probably should happen sooner rather than later.
>>>>
>>>> -eric
>>>>
>>>
>>>
>>
>
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From clattner at apple.com  Tue Nov 15 18:33:28 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 15 Nov 2011 16:33:28 -0800
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <CAN=P9pjf5V0mO=rPzR3Xt2RbW1iTaui748WFr4fBUAKXiE93tw@mail.gmail.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
	<1137D6EF-A4A8-4C7B-AAA7-831E5E36124F@apple.com>
	<CAN=P9pjg6r7r-csthwB0or1Y5h1GFXxdn4Tpj_jdtkn9SsDfcA@mail.gmail.com>
	<CAN=P9ph7ED02yrX_vvWu7AUgphRpU_4TcAPCmBoM9dQ1gVvGOA@mail.gmail.com>
	<CAN=P9piQT4=7vbGKfW+8zV7fff-7rjASxGH_AGDt=a3iLYrsmA@mail.gmail.com>
	<CAN=P9pjf5V0mO=rPzR3Xt2RbW1iTaui748WFr4fBUAKXiE93tw@mail.gmail.com>
Message-ID: <36A55DEE-6AB5-4975-820C-FA3774485E46@apple.com>


On Nov 15, 2011, at 4:31 PM, Kostya Serebryany wrote:

> Hello, 
> 
> Here is the fresh AddressSanitizer patch for your consideration. 
> This is LLVM-only patch. 
> If/when it is submitted, clang changes and the run-time library will follow. 
> http://codereview.appspot.com/5393042/

Hi Kostya,

This can certainly be improved, but I think it is fine to check it into mainline.  Please do!

-Chris

> 
> Thanks, 
> 
> --kcc 
> 
> On Thu, Sep 15, 2011 at 1:31 PM, Kostya Serebryany <kcc at google.com> wrote:
> Hi, 
> 
> I haven't heard any more comments. 
> Eric Christopher confirmed that the only concern is having the instrumentation pass w/o the run-time library. 
> I do want to contribute run-time as well. 
> How do we proceed? 
> 
> Let me describe the whole thing once more. 
> 
> AddressSanitizer finds 
>   - Out-of-bounds accesses to heap, stack and globals
>   - Use-after-free (heap)
> The slowdown is typically within 2x: http://code.google.com/p/address-sanitizer/wiki/PerformanceNumbers
> It also has an experimental feature to detect use-after-return (stack). 
> 
> The tool currently works on x86 Linux and Mac, both 32- and 64- bits. 
> The Linux port is absolutely stable (one can browse the web using instrumented Chromium for hours). 
> The Mac port is slightly less stable (Chromium tests work, but the browser hiccups infrequently).
> 
> The tool consists of two parts: instrumentation pass (~1KLOC) and run-time library (~3KLOC). 
> 
> The instrumentation pass being reviewed in this mail thread only supports detection of heap bugs. 
> Other parts (~400 more LOC) will add stack, globals, and blacklisting. 
> 
> The run-time library replaces malloc/free/etc, intercepts other libc functions (e.g. pthread_create) and does error reporting.
> The library and test code uses google coding conventions.
> The integration tests use gtest.
> 
> I'd like to have the run-time available as part of LLVM, and I would agree on any reasonable way of doing so in the following order of preference:
>   - use svn:externals to point to the existing repository at http://code.google.com/p/address-sanitizer/source/checkout
>   - copy the code to LLVM repository and periodically take the fresh versions from c.g.c repository. 
>   - use the LLVM repository as the primary repository (here I am concerned with the tool chain: we are too used to the features provided by c.g.c.)
> Please suggest what suits LLVM the most.
> 
> Thanks, 
> 
> --kcc 
> 
> 
> On Mon, Sep 12, 2011 at 11:48 AM, Kostya Serebryany <kcc at google.com> wrote:
> FYI
> I've added noreturn attribute to the __asan_report_error call. It doesn't cause compile problems in cpu2006 any more. 
> The good news is that the slowdown (compared to assembly with ud2) on cpu2006 ranges between 1% and 8%. 
> And we may recover from it if __asan_report_error does not cause stack frame to be created in leaf functions. 
> 
> --kcc 
> 
> 
> On Fri, Sep 9, 2011 at 12:48 PM, Kostya Serebryany <kcc at google.com> wrote:
> 
> 
> On Thu, Sep 8, 2011 at 5:38 PM, Eric Christopher <echristo at apple.com> wrote:
> 
> On Sep 8, 2011, at 5:14 PM, Kostya Serebryany wrote:
> 
>> 
>> 
>> On Thu, Sep 8, 2011 at 4:43 PM, Eric Christopher <echristo at apple.com> wrote:
>> 
>> On Sep 8, 2011, at 4:35 PM, Chandler Carruth wrote:
>> 
>> > FYI,
>> >
>> > I've looked again at this patch recently, and talked to several others about it...
>> >
>> > I think there are some big issues with the implementation, bit I think they could probably be addressed. The one that I see the most is the x86 assembly just being dumped as a blob. I think that really needs to be resolved before this can move forward.
>> >
>> > It seems like this should be do-able in some way with the llvm.trap intrinsic. If anything, we might need another intrinsic or an extension of llvm.trap that allows feeding the SIGILL signal handler the data arguments it needs; I'd need to read up on exactly what is required for that to figure out how best to represent that in IR, but it shouldn't be that hard.
>> >
>> > That said, maybe to improve the discussion of the patch and make reviewing it easier, you could just switch to emitting the call to the runtime library function in all cases? That should be a strictly simpler patch, and then how to improve performance by avoiding the runtime call can be a followup.
>> >
>> 
>> This encompasses most of my concerns with the patch.
>> 
>> > Maybe others could comment on other implementation issues? I'm sadly not an expert at LLVM...
>> 
>> In a glance I didn't see a lot, but the other bits were somewhat hiding it. How about when we get a new patch we can take a bit more of a look at it.
>> 
>> I dropped the assembly part and updated the patch at http://codereview.appspot.com/4867059/ (also in attachment).
>> We can figure out how to make it more efficient later (something like llvm.trap intrinsic with a parameter).
>> 
>> This patch is 570 LOC plus few lines of trivial changes and a test.
>> It implements only basic functionality: detection of out-of-bounds and use-after-free in heap.
>> 
>> The complete version of LLVM pass is ~1000 LOC (http://code.google.com/p/address-sanitizer/source/browse/trunk/llvm/AddressSanitizer.cpp).
>> It also handles out-of-bounds for stack and global objects and (recently added) stack use-after-return bugs. 
> 
> Some somewhat trivial issues:
> 
> a) Please go ahead and hide the non-user visible flags.
> done 
> 
> b) Not a big fan of this style of avoid 80-col wrap:
> 
> +Instruction *AddressSanitizer::generateCrashCode(
> +    IRBuilder<> &IRB, Value *Addr, int TelltaleValue) {
> done 
> 
> c) +  // which will be lowered to a cusom assembly.
> 
> s/cusom/custom
> 
> d) 
> 
> +  if (TypeSize != 8 && TypeSize != 16 &&
> +      TypeSize != 32 && TypeSize != 64 && TypeSize != 128) {
> +    // TODO(kcc): do something better.
> +    return;
> +  }
> 
> What's the reason behind this?
> 
> Changed the comment.
>  
> 
> Perhaps not so trivial:
> 
> a) Where are the asan_* functions? Where are they supposed to live?
> 
> I'll probably have more, but it's a start and the discussion on the library functions probably should happen sooner rather than later.
> 
> -eric
> 
> 
> 
> 
> <issue5393042_3001.diff>

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From mcrosier at apple.com  Tue Nov 15 18:32:21 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 16 Nov 2011 00:32:21 -0000
Subject: [llvm-commits] [llvm] r144743 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20111116003221.108DC2A6C132@llvm.org>

Author: mcrosier
Date: Tue Nov 15 18:32:20 2011
New Revision: 144743

URL: http://llvm.org/viewvc/llvm-project?rev=144743&view=rev
Log:
Add FIXME comment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144743&r1=144742&r2=144743&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Nov 15 18:32:20 2011
@@ -1303,6 +1303,8 @@
   int Imm = 0;
   bool UseImm = false;
   bool isNegativeImm = false;
+  // FIXME: At -O0 we don't have anything that canonicalizes operand order.
+  // Thus, Src1Value may be a ConstantInt, but we're missing it.
   if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
     if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
         SrcVT == MVT::i1) {



From clattner at apple.com  Tue Nov 15 18:37:28 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 15 Nov 2011 16:37:28 -0800
Subject: [llvm-commits] Proposal/patch: Enable bitcode streaming
In-Reply-To: <CAAEAhvci4uJmsT4b1ibkG57qmzAesDdPQejmhAVLEmFd_FzyOg@mail.gmail.com>
References: <CAAEAhvci4uJmsT4b1ibkG57qmzAesDdPQejmhAVLEmFd_FzyOg@mail.gmail.com>
Message-ID: <7A6CF9E2-C5B7-45D4-AE10-185BA8EC3BD7@apple.com>

Hi Derek,

Have you measured the performance impact of this patch on the non-streaming case?  How much slower does "llvm-dis -disable-output foo.bc" go (with a release build)?

-Chris

On Nov 9, 2011, at 4:57 PM, Derek Schuff wrote:

> Hello all,
> The following is a proposal (and a prototype patch) to enable bitcode streaming. The overall goal is to be able to overlap bitcode reading/download with compilation, a functionality useful obviously for pnacl and renderscript but also potentially for any situation where the interface between the frontend and backend is something other than a file. 
> 
> In the current state of the world, at a high level, there are 2 things keeping this from happening. The first is that BitcodeReader construction takes a MemoryBuffer which it expects to be filled with bitcode, and inside BitcodeReader, the BitstreamCursor (which is the primary interface to the bitcode itself) gets pointers to the bitcode in memory, and does all of its magic with pointer arithmetic. The second issue is that in BitcodeReader::ParseModule (which is run when right after the Module and BitcodeReader objects are created), the reader makes a pass over the entire bitcode file. This step does everything except read the function bodies, but it records the bit locations of each function for future materialization.
> 
> High-level change description:
> This patch creates a class called BitcodeStream, which is a very simple interface with one method (GetBytes), which fetches the requested number of bytes from the stream, and writes them into the requested destination. This method may block the calling thread if there are not yet enough bytes available in the stream buffer (similarly to a stdin or socket read).
> 
> The first issue above is addressed by introducing the BitstreamVector, an abstraction that wraps the bitcode in memory. Instead of using pointers, the BitstreamCursor uses indices and gets bitcode bytes by indexing (i.e. operator[] ) the BitstreamVector. When streaming is not used, the BitstreamVector itself keeps pointers to the start and end of the backing MemoryBuffer and the indexing operator is just a pointer dereference. For streaming use, the BitstreamVector has a BitcodeStream object. If a byte is requested that has not yet been fetched, it calls GetBytes to get more, until it has enough to return the requested byte.
> This model of allowing any byte to be requested and blocking the caller has the advantage that there is no structural/architectural change required at this lowest level, nor at the high level (A FunctionPassManager is used to iterate over all the functions and compile each one).
> 
> The second issue is solved by 2 simple changes. The first is in ParseModule. Instead of a single pass over all the bitcode, ParseModule becomes resumable.  ParseModule will do its normal handling for top-level records, type table blocks, metadata, etc, but if streaming is in use, it will save its state and return as soon as a function subblock is encountered (rather than saving its location and skipping over it). Each subsequent time it is called, it bookmarks and skips one function block. Later, when a function needs to be materialized, if the function body has been seen already, then materialization is the same as before. Otherwise, Materialize will keep calling ParseModule (each time bookmarking and skipping one function body) until the requested function is found. The one other change required to make this work simply is that the bitcode writer writes function bodies as the last subblock (currently the attachment metadata and value symbol table are written after the function bodies).
> 
> The prototype patch is attached and can also be viewed online at http://codereview.chromium.org/8393017/ . Feedback is welcome, as well as guidance from the relevant code owners/reviewers regarding what the next step needs to be toward committing this.
> 
> Thanks,
> -Derek
> <bitcode_streaming_r144247.diff>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From clattner at apple.com  Tue Nov 15 18:40:19 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 15 Nov 2011 16:40:19 -0800
Subject: [llvm-commits] [llvm] r144580 - in /llvm/trunk:
 include/llvm/Analysis/CaptureTracking.h
 include/llvm/Analysis/MemoryDependenceAnalysis.h
 lib/Analysis/CaptureTracking.cpp lib/Analysis/MemoryDependenceAnalysis.cpp
 test/Transforms/GVN/rle.ll
In-Reply-To: <20111114224942.B52192A6C131@llvm.org>
References: <20111114224942.B52192A6C131@llvm.org>
Message-ID: <7DE51D28-D95B-4C50-89A0-C3A66C67C192@apple.com>


On Nov 14, 2011, at 2:49 PM, Nick Lewycky wrote:

> Author: nicholas
> Date: Mon Nov 14 16:49:42 2011
> New Revision: 144580
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=144580&view=rev
> Log:
> Refactor capture tracking (which already had a couple flags for whether returns
> and stores capture) to permit the caller to see each capture point and decide
> whether to continue looking.
> 
> Use this inside memdep to do an analysis that basicaa won't do. This lets us
> solve another devirtualization case, fixing PR8908!

Awesome, thanks for fixing this! but...
> +++ llvm/trunk/include/llvm/Analysis/CaptureTracking.h Mon Nov 14 16:49:42 2011
> @@ -14,9 +14,14 @@
> #ifndef LLVM_ANALYSIS_CAPTURETRACKING_H
> #define LLVM_ANALYSIS_CAPTURETRACKING_H
> 
> -namespace llvm {
> -  class Value;
> +#include "llvm/Constants.h"
> +#include "llvm/Instructions.h"
> +#include "llvm/Analysis/AliasAnalysis.h"
> +#include "llvm/ADT/SmallSet.h"
> +#include "llvm/ADT/SmallVector.h"
> +#include "llvm/Support/CallSite.h"

Eww, gross.  Why not make PointerMayBeCaptured a virtual interface instead of templatizing this like crazy?  This would also turn your giant comment block into actual code :) and allow the simple implementation to be used by default.

-Chris



From kcc at google.com  Tue Nov 15 18:45:37 2011
From: kcc at google.com (Kostya Serebryany)
Date: Tue, 15 Nov 2011 16:45:37 -0800
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <36A55DEE-6AB5-4975-820C-FA3774485E46@apple.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
	<1137D6EF-A4A8-4C7B-AAA7-831E5E36124F@apple.com>
	<CAN=P9pjg6r7r-csthwB0or1Y5h1GFXxdn4Tpj_jdtkn9SsDfcA@mail.gmail.com>
	<CAN=P9ph7ED02yrX_vvWu7AUgphRpU_4TcAPCmBoM9dQ1gVvGOA@mail.gmail.com>
	<CAN=P9piQT4=7vbGKfW+8zV7fff-7rjASxGH_AGDt=a3iLYrsmA@mail.gmail.com>
	<CAN=P9pjf5V0mO=rPzR3Xt2RbW1iTaui748WFr4fBUAKXiE93tw@mail.gmail.com>
	<36A55DEE-6AB5-4975-820C-FA3774485E46@apple.com>
Message-ID: <CAN=P9pjPO8x7L_H=4+615ksybjYPEtjcJLyWkFvNrJJhw_JogQ@mail.gmail.com>

On Tue, Nov 15, 2011 at 4:33 PM, Chris Lattner <clattner at apple.com> wrote:

>
> On Nov 15, 2011, at 4:31 PM, Kostya Serebryany wrote:
>
> Hello,
>
> Here is the fresh AddressSanitizer patch for your consideration.
> This is LLVM-only patch.
> If/when it is submitted, clang changes and the run-time library will
> follow.
> http://codereview.appspot.com/5393042/
>
>
> Hi Kostya,
>
> This can certainly be improved, but I think it is fine to check it into
> mainline.  Please do!
>

Thank you. What shall I do to get the LVVM commit access?

--kcc



>
> -Chris
>
>
> Thanks,
>
> --kcc
>
> On Thu, Sep 15, 2011 at 1:31 PM, Kostya Serebryany <kcc at google.com> wrote:
>
>> Hi,
>>
>> I haven't heard any more comments.
>> Eric Christopher confirmed that the only concern is having the
>> instrumentation pass w/o the run-time library.
>> I do want to contribute run-time as well.
>> How do we proceed?
>>
>> Let me describe the whole thing once more.
>>
>> AddressSanitizer finds
>>   - Out-of-bounds accesses to heap, stack and globals
>>   - Use-after-free (heap)
>> The slowdown is typically within 2x:
>> http://code.google.com/p/address-sanitizer/wiki/PerformanceNumbers
>> It also has an experimental feature to detect use-after-return (stack).
>>
>> The tool currently works on x86 Linux and Mac, both 32- and 64- bits.
>> The Linux port is absolutely stable (one can browse the web using
>> instrumented Chromium for hours).
>> The Mac port is slightly less stable (Chromium tests work, but the
>> browser hiccups infrequently).
>>
>> The tool consists of two parts: instrumentation pass (~1KLOC) and
>> run-time library (~3KLOC).
>>
>> The instrumentation pass being reviewed in this mail thread only supports
>> detection of heap bugs.
>> Other parts (~400 more LOC) will add stack, globals, and blacklisting.
>>
>> The run-time library replaces malloc/free/etc, intercepts other libc
>> functions (e.g. pthread_create) and does error reporting.
>> The library and test code uses google coding conventions.
>> The integration tests use gtest.
>>
>> I'd like to have the run-time available as part of LLVM, and I would
>> agree on any reasonable way of doing so in the following order of
>> preference:
>>   - use svn:externals to point to the existing repository at
>> http://code.google.com/p/address-sanitizer/source/checkout
>>   - copy the code to LLVM repository and periodically take the fresh
>> versions from c.g.c repository.
>>   - use the LLVM repository as the primary repository (here I am
>> concerned with the tool chain: we are too used to the features provided
>> by c.g.c.)
>> Please suggest what suits LLVM the most.
>>
>> Thanks,
>>
>> --kcc
>>
>>
>> On Mon, Sep 12, 2011 at 11:48 AM, Kostya Serebryany <kcc at google.com>wrote:
>>
>>> FYI
>>> I've added noreturn attribute to the __asan_report_error call. It
>>> doesn't cause compile problems in cpu2006 any more.
>>> The good news is that the slowdown (compared to assembly with ud2) on
>>> cpu2006 ranges between 1% and 8%.
>>> And we may recover from it if __asan_report_error does not cause stack
>>> frame to be created in leaf functions.
>>>
>>> --kcc
>>>
>>>
>>> On Fri, Sep 9, 2011 at 12:48 PM, Kostya Serebryany <kcc at google.com>wrote:
>>>
>>>>
>>>>
>>>> On Thu, Sep 8, 2011 at 5:38 PM, Eric Christopher <echristo at apple.com>wrote:
>>>>
>>>>>
>>>>> On Sep 8, 2011, at 5:14 PM, Kostya Serebryany wrote:
>>>>>
>>>>>
>>>>>
>>>>> On Thu, Sep 8, 2011 at 4:43 PM, Eric Christopher <echristo at apple.com>wrote:
>>>>>
>>>>>>
>>>>>> On Sep 8, 2011, at 4:35 PM, Chandler Carruth wrote:
>>>>>>
>>>>>> > FYI,
>>>>>> >
>>>>>> > I've looked again at this patch recently, and talked to several
>>>>>> others about it...
>>>>>> >
>>>>>> > I think there are some big issues with the implementation, bit I
>>>>>> think they could probably be addressed. The one that I see the most is the
>>>>>> x86 assembly just being dumped as a blob. I think that really needs to be
>>>>>> resolved before this can move forward.
>>>>>> >
>>>>>> > It seems like this should be do-able in some way with the llvm.trap
>>>>>> intrinsic. If anything, we might need another intrinsic or an extension of
>>>>>> llvm.trap that allows feeding the SIGILL signal handler the data arguments
>>>>>> it needs; I'd need to read up on exactly what is required for that to
>>>>>> figure out how best to represent that in IR, but it shouldn't be that hard.
>>>>>> >
>>>>>> > That said, maybe to improve the discussion of the patch and make
>>>>>> reviewing it easier, you could just switch to emitting the call to the
>>>>>> runtime library function in all cases? That should be a strictly simpler
>>>>>> patch, and then how to improve performance by avoiding the runtime call can
>>>>>> be a followup.
>>>>>> >
>>>>>>
>>>>>> This encompasses most of my concerns with the patch.
>>>>>>
>>>>>> > Maybe others could comment on other implementation issues? I'm
>>>>>> sadly not an expert at LLVM...
>>>>>>
>>>>>> In a glance I didn't see a lot, but the other bits were somewhat
>>>>>> hiding it. How about when we get a new patch we can take a bit more of a
>>>>>> look at it.
>>>>>>
>>>>>
>>>>> I dropped the assembly part and updated the patch at
>>>>> http://codereview.appspot.com/4867059/ (also in attachment).
>>>>> We can figure out how to make it more efficient later (something
>>>>> like llvm.trap intrinsic with a parameter).
>>>>>
>>>>> This patch is 570 LOC plus few lines of trivial changes and a test.
>>>>> It implements only basic functionality: detection of out-of-bounds and
>>>>> use-after-free in heap.
>>>>>
>>>>> The complete version of LLVM pass is ~1000 LOC (
>>>>> http://code.google.com/p/address-sanitizer/source/browse/trunk/llvm/AddressSanitizer.cpp
>>>>> ).
>>>>> It also handles out-of-bounds for stack and global objects and
>>>>> (recently added) stack use-after-return bugs.
>>>>>
>>>>>
>>>>> Some somewhat trivial issues:
>>>>>
>>>>> a) Please go ahead and hide the non-user visible flags.
>>>>>
>>>> done
>>>>
>>>>>
>>>>> b) Not a big fan of this style of avoid 80-col wrap:
>>>>>
>>>>> +Instruction *AddressSanitizer::generateCrashCode(
>>>>> +    IRBuilder<> &IRB, Value *Addr, int TelltaleValue) {
>>>>>
>>>> done
>>>>
>>>>>
>>>>> c) +  // which will be lowered to a cusom assembly.
>>>>>
>>>>> s/cusom/custom
>>>>>
>>>>> d)
>>>>>
>>>>> +  if (TypeSize != 8 && TypeSize != 16 &&
>>>>> +      TypeSize != 32 && TypeSize != 64 && TypeSize != 128) {
>>>>> +    // TODO(kcc): do something better.
>>>>> +    return;
>>>>> +  }
>>>>>
>>>>> What's the reason behind this?
>>>>>
>>>>
>>>> Changed the comment.
>>>>
>>>>
>>>>>
>>>>> Perhaps not so trivial:
>>>>>
>>>>> a) Where are the asan_* functions? Where are they supposed to live?
>>>>>
>>>>> I'll probably have more, but it's a start and the discussion on the
>>>>> library functions probably should happen sooner rather than later.
>>>>>
>>>>> -eric
>>>>>
>>>>
>>>>
>>>
>>
> <issue5393042_3001.diff>
>
>
>
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From clattner at apple.com  Tue Nov 15 18:46:30 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 15 Nov 2011 16:46:30 -0800
Subject: [llvm-commits] [llvm] r133106 - in /llvm/trunk:
 include/llvm/CodeGen/ValueTypes.h include/llvm/CodeGen/ValueTypes.td
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
 utils/TableGen/CodeGenTarget.cpp
In-Reply-To: <20110615233518.6051C2A6C12C@llvm.org>
References: <20110615233518.6051C2A6C12C@llvm.org>
Message-ID: <D9D8BB56-9A98-438C-BC58-A9BB1F3A6162@apple.com>


On Jun 15, 2011, at 4:35 PM, Owen Anderson wrote:

> Author: resistor
> Date: Wed Jun 15 18:35:18 2011
> New Revision: 133106
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133106&view=rev
> Log:
> Add a new MVT::untyped.  This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers).  We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.

Hi Owen,

I know this was a long time ago now, but please rename this to MVT::Untyped.  Things like Glue, Metadata, etc are capitalized.

-Chris

From eli.friedman at gmail.com  Tue Nov 15 18:49:40 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 15 Nov 2011 16:49:40 -0800
Subject: [llvm-commits] AddressSanitizer, first patch
In-Reply-To: <CAN=P9pjPO8x7L_H=4+615ksybjYPEtjcJLyWkFvNrJJhw_JogQ@mail.gmail.com>
References: <CAN=P9phLGUS8CoiTUffFQNi0RYgN2pJjqG-ATSWK6_uw4yZVMA@mail.gmail.com>
	<CAGCO0KjqBniz_1aANpjU9UT2CNejk9o4LNafvpB1n+pRwYUVZw@mail.gmail.com>
	<CAGCO0Kgufi8a424X6Y-2DruFK9itM96hgws81CV2dKcV41QDcQ@mail.gmail.com>
	<E73F051C-1513-49F4-AF0A-83E0CDFE22A6@apple.com>
	<CAN=P9piC1iL6q=UdmWXpKL6PKPnDpvrNBeoDEoBWf2MT5v6gyw@mail.gmail.com>
	<1137D6EF-A4A8-4C7B-AAA7-831E5E36124F@apple.com>
	<CAN=P9pjg6r7r-csthwB0or1Y5h1GFXxdn4Tpj_jdtkn9SsDfcA@mail.gmail.com>
	<CAN=P9ph7ED02yrX_vvWu7AUgphRpU_4TcAPCmBoM9dQ1gVvGOA@mail.gmail.com>
	<CAN=P9piQT4=7vbGKfW+8zV7fff-7rjASxGH_AGDt=a3iLYrsmA@mail.gmail.com>
	<CAN=P9pjf5V0mO=rPzR3Xt2RbW1iTaui748WFr4fBUAKXiE93tw@mail.gmail.com>
	<36A55DEE-6AB5-4975-820C-FA3774485E46@apple.com>
	<CAN=P9pjPO8x7L_H=4+615ksybjYPEtjcJLyWkFvNrJJhw_JogQ@mail.gmail.com>
Message-ID: <CAJdarcHRYZcEgtEVorQhPx2B8YUcJ3mUsv5oWSUWc7VRxy9Dgw@mail.gmail.com>

On Tue, Nov 15, 2011 at 4:45 PM, Kostya Serebryany <kcc at google.com> wrote:
>
>
> On Tue, Nov 15, 2011 at 4:33 PM, Chris Lattner <clattner at apple.com> wrote:
>>
>> On Nov 15, 2011, at 4:31 PM, Kostya Serebryany wrote:
>>
>> Hello,
>> Here is the fresh AddressSanitizer patch for your consideration.
>> This is LLVM-only patch.
>> If/when it is submitted, clang changes and the run-time library will
>> follow.
>> http://codereview.appspot.com/5393042/
>>
>> Hi Kostya,
>> This can certainly be improved, but I think it is fine to check it into
>> mainline. ?Please do!
>
> Thank you. What shall I do to get the LVVM commit access?
> --kcc

http://llvm.org/docs/DeveloperPolicy.html#commitaccess

-Eli


From atrick at apple.com  Tue Nov 15 18:52:40 2011
From: atrick at apple.com (Andrew Trick)
Date: Wed, 16 Nov 2011 00:52:40 -0000
Subject: [llvm-commits] [llvm] r144746 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp
 test/Transforms/IndVarSimplify/2011-11-15-multiexit.ll
 test/Transforms/IndVarSimplify/loop_evaluate10.ll
 test/Transforms/IndVarSimplify/loop_evaluate9.ll
Message-ID: <20111116005240.4A19B2A6C132@llvm.org>

Author: atrick
Date: Tue Nov 15 18:52:40 2011
New Revision: 144746

URL: http://llvm.org/viewvc/llvm-project?rev=144746&view=rev
Log:
Fix SCEV overly optimistic back edge taken count for multi-exit loops.

Fixes PR11375: Different results for 'clang++ huh.cpp'...

Added:
    llvm/trunk/test/Transforms/IndVarSimplify/2011-11-15-multiexit.ll
Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate10.ll
    llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate9.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=144746&r1=144745&r2=144746&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Nov 15 18:52:40 2011
@@ -4153,13 +4153,19 @@
 }
 
 /// getExact - Get the exact loop backedge taken count considering all loop
-/// exits. If all exits are computable, this is the minimum computed count.
+/// exits. A computable result can only be return for loops with a single exit.
+/// Returning the minimum taken count among all exits is incorrect because one
+/// of the loop's exit limit's may have been skipped. HowFarToZero assumes that
+/// the limit of each loop test is never skipped. This is a valid assumption as
+/// long as the loop exits via that test. For precise results, it is the
+/// caller's responsibility to specify the relevant loop exit using
+/// getExact(ExitingBlock, SE).
 const SCEV *
 ScalarEvolution::BackedgeTakenInfo::getExact(ScalarEvolution *SE) const {
   // If any exits were not computable, the loop is not computable.
   if (!ExitNotTaken.isCompleteList()) return SE->getCouldNotCompute();
 
-  // We need at least one computable exit.
+  // We need exactly one computable exit.
   if (!ExitNotTaken.ExitingBlock) return SE->getCouldNotCompute();
   assert(ExitNotTaken.ExactNotTaken && "uninitialized not-taken info");
 
@@ -4171,8 +4177,8 @@
 
     if (!BECount)
       BECount = ENT->ExactNotTaken;
-    else
-      BECount = SE->getUMinFromMismatchedTypes(BECount, ENT->ExactNotTaken);
+    else if (BECount != ENT->ExactNotTaken)
+      return SE->getCouldNotCompute();
   }
   assert(BECount && "Invalid not taken count for loop exit");
   return BECount;
@@ -4253,8 +4259,15 @@
 
     if (MaxBECount == getCouldNotCompute())
       MaxBECount = EL.Max;
-    else if (EL.Max != getCouldNotCompute())
-      MaxBECount = getUMinFromMismatchedTypes(MaxBECount, EL.Max);
+    else if (EL.Max != getCouldNotCompute()) {
+      // We cannot take the "min" MaxBECount, because non-unit stride loops may
+      // skip some loop tests. Taking the max over the exits is sufficiently
+      // conservative.  TODO: We could do better taking into consideration
+      // that (1) the loop has unit stride (2) the last loop test is
+      // less-than/greater-than (3) any loop test is less-than/greater-than AND
+      // falls-through some constant times less then the other tests.
+      MaxBECount = getUMaxFromMismatchedTypes(MaxBECount, EL.Max);
+    }
   }
 
   return BackedgeTakenInfo(ExitCounts, CouldComputeBECount, MaxBECount);
@@ -4920,7 +4933,7 @@
   // the loop symbolically to determine when the condition gets a value of
   // "ExitWhen".
 
-  unsigned MaxIterations = MaxBruteForceIterations;   // Limit analysis.  
+  unsigned MaxIterations = MaxBruteForceIterations;   // Limit analysis.
   for (unsigned IterationNum = 0; IterationNum != MaxIterations;++IterationNum){
     ConstantInt *CondVal =
       dyn_cast_or_null<ConstantInt>(EvaluateExpression(Cond, L,
@@ -5507,10 +5520,10 @@
   // behavior. Loops must exhibit defined behavior until a wrapped value is
   // actually used. So the trip count computed by udiv could be smaller than the
   // number of well-defined iterations.
-  if (AddRec->getNoWrapFlags(SCEV::FlagNW))
+  if (AddRec->getNoWrapFlags(SCEV::FlagNW)) {
     // FIXME: We really want an "isexact" bit for udiv.
     return getUDivExpr(Distance, CountDown ? getNegativeSCEV(Step) : Step);
-
+  }
   // Then, try to solve the above equation provided that Start is constant.
   if (const SCEVConstant *StartC = dyn_cast<SCEVConstant>(Start))
     return SolveLinEquationWithOverflow(StepC->getValue()->getValue(),

Added: llvm/trunk/test/Transforms/IndVarSimplify/2011-11-15-multiexit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2011-11-15-multiexit.ll?rev=144746&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/2011-11-15-multiexit.ll (added)
+++ llvm/trunk/test/Transforms/IndVarSimplify/2011-11-15-multiexit.ll Tue Nov 15 18:52:40 2011
@@ -0,0 +1,40 @@
+; RUN: opt < %s -indvars -S | FileCheck %s
+;
+; Prior to the fix for PR11375, indvars would replace %firstIV with a
+; loop-invariant gep computed in the preheader. This was incorrect
+; because it was based on the minimum "ExitNotTaken" count. If the
+; final loop test is skipped (odd number of elements) then the early
+; exit would be taken and the loop invariant value would be incorrect.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-darwin"
+
+; CHECK: if.end:
+; CHECK: phi i32* [ %first.lcssa, %early.exit ]
+define i32 @test(i32* %first, i32* %last) uwtable ssp {
+entry:
+  br i1 undef, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  br i1 undef, label %if.end, label %do.body
+
+do.body:                                          ; preds = %if.else, %if.then
+  %firstIV = phi i32* [ %incdec.ptr2, %if.else ], [ %first, %if.then ]
+  %incdec.ptr1 = getelementptr inbounds i32* %firstIV, i64 1
+  %cmp1 = icmp eq i32* %incdec.ptr1, %last
+  br i1 %cmp1, label %early.exit, label %if.else
+
+if.else:                                        ; preds = %do.body
+  %incdec.ptr2 = getelementptr inbounds i32* %firstIV, i64 2
+  %cmp2 = icmp eq i32* %incdec.ptr2, %last
+  br i1 %cmp2, label %if.end, label %do.body
+
+early.exit:
+  %first.lcssa = phi i32* [ %firstIV, %do.body ]
+  br label %if.end
+
+if.end:
+  %tmp = phi i32* [ %first.lcssa, %early.exit ], [ %first, %if.then ], [ %first, %entry ], [ undef, %if.else ]
+  %val = load i32* %tmp
+  ret i32 %val
+}

Modified: llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate10.ll?rev=144746&r1=144745&r2=144746&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate10.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate10.ll Tue Nov 15 18:52:40 2011
@@ -1,8 +1,14 @@
 ; RUN: opt < %s -indvars -S \
 ; RUN:   | grep {%b.1 = phi i32 \\\[ 2, %bb \\\], \\\[ 1, %bb2 \\\]}
-
+;
 ; This loop has multiple exits, and the value of %b1 depends on which
 ; exit is taken. Indvars should correctly compute the exit values.
+;
+; XFAIL: *
+; Indvars does not currently replace loop invariant values unless all
+; loop exits have the same exit value. We could handle some cases,
+; such as this, by making getSCEVAtScope() sensitive to a particular
+; loop exit.  See PR11388.
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-pc-linux-gnu"

Modified: llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate9.ll?rev=144746&r1=144745&r2=144746&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate9.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate9.ll Tue Nov 15 18:52:40 2011
@@ -2,8 +2,13 @@
 ; RUN: grep {\[%\]tmp7 = icmp eq i8 -28, -28} %t
 ; RUN: grep {\[%\]tmp8 = icmp eq i8 63, 63} %t
 ; PR4477
-
 ; Indvars should compute the exit values in loop.
+;
+; XFAIL: *
+; Indvars does not currently replace loop invariant values unless all
+; loop exits have the same exit value. We could handle some cases,
+; such as this, by making getSCEVAtScope() sensitive to a particular
+; loop exit.  See PR11388.
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
 target triple = "i386-pc-linux-gnu"



From resistor at mac.com  Tue Nov 15 19:02:57 2011
From: resistor at mac.com (Owen Anderson)
Date: Wed, 16 Nov 2011 01:02:57 -0000
Subject: [llvm-commits] [llvm] r144747 - in /llvm/trunk:
 include/llvm/CodeGen/ValueTypes.h lib/CodeGen/MachineLICM.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp lib/VMCore/ValueTypes.cpp
 utils/TableGen/CodeGenTarget.cpp
Message-ID: <20111116010257.824872A6C133@llvm.org>

Author: resistor
Date: Tue Nov 15 19:02:57 2011
New Revision: 144747

URL: http://llvm.org/viewvc/llvm-project?rev=144747&view=rev
Log:
Rename MVT::untyped to MVT::Untyped to match similar nomenclature.

Modified:
    llvm/trunk/include/llvm/CodeGen/ValueTypes.h
    llvm/trunk/lib/CodeGen/MachineLICM.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/VMCore/ValueTypes.cpp
    llvm/trunk/utils/TableGen/CodeGenTarget.cpp

Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=144747&r1=144746&r2=144747&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Tue Nov 15 19:02:57 2011
@@ -83,7 +83,7 @@
 
       isVoid         =  35,   // This has no value
 
-      untyped        =  36,   // This value takes a register, but has
+      Untyped        =  36,   // This value takes a register, but has
                               // unspecified type.  The register class
                               // will be determined by the opcode.
 

Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=144747&r1=144746&r2=144747&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Tue Nov 15 19:02:57 2011
@@ -670,7 +670,7 @@
                                        unsigned &RCId, unsigned &RCCost) const {
   const TargetRegisterClass *RC = MRI->getRegClass(Reg);
   EVT VT = *RC->vt_begin();
-  if (VT == MVT::untyped) {
+  if (VT == MVT::Untyped) {
     RCId = RC->getID();
     RCCost = 1;
   } else {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=144747&r1=144746&r2=144747&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Nov 15 19:02:57 2011
@@ -267,7 +267,7 @@
 
 /// GetCostForDef - Looks up the register class and cost for a given definition.
 /// Typically this just means looking up the representative register class,
-/// but for untyped values (MVT::untyped) it means inspecting the node's
+/// but for untyped values (MVT::Untyped) it means inspecting the node's
 /// opcode to determine what register class is being generated.
 static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
                           const TargetLowering *TLI,
@@ -278,7 +278,7 @@
 
   // Special handling for untyped values.  These values can only come from
   // the expansion of custom DAG-to-DAG patterns.
-  if (VT == MVT::untyped) {
+  if (VT == MVT::Untyped) {
     const SDNode *Node = RegDefPos.GetNode();
     unsigned Opcode = Node->getMachineOpcode();
 

Modified: llvm/trunk/lib/VMCore/ValueTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ValueTypes.cpp?rev=144747&r1=144746&r2=144747&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ValueTypes.cpp (original)
+++ llvm/trunk/lib/VMCore/ValueTypes.cpp Tue Nov 15 19:02:57 2011
@@ -139,7 +139,7 @@
   case MVT::v2f64:   return "v2f64";
   case MVT::v4f64:   return "v4f64";
   case MVT::Metadata:return "Metadata";
-  case MVT::untyped: return "untyped";
+  case MVT::Untyped: return "Untyped";
   }
 }
 

Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=144747&r1=144746&r2=144747&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Tue Nov 15 19:02:57 2011
@@ -90,7 +90,7 @@
   case MVT::Metadata: return "MVT::Metadata";
   case MVT::iPTR:     return "MVT::iPTR";
   case MVT::iPTRAny:  return "MVT::iPTRAny";
-  case MVT::untyped:  return "MVT::untyped";
+  case MVT::Untyped:  return "MVT::Untyped";
   default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
   }
 }



From kcc at google.com  Tue Nov 15 19:14:38 2011
From: kcc at google.com (Kostya Serebryany)
Date: Wed, 16 Nov 2011 01:14:38 -0000
Subject: [llvm-commits] [llvm] r144748 -
	/llvm/trunk/lib/Transforms/Utils/ModuleUtils.cpp
Message-ID: <20111116011438.721102A6C133@llvm.org>

Author: kcc
Date: Tue Nov 15 19:14:38 2011
New Revision: 144748

URL: http://llvm.org/viewvc/llvm-project?rev=144748&view=rev
Log:
test commit to verify that commit access works (added blank line)

Modified:
    llvm/trunk/lib/Transforms/Utils/ModuleUtils.cpp

Modified: llvm/trunk/lib/Transforms/Utils/ModuleUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/ModuleUtils.cpp?rev=144748&r1=144747&r2=144748&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/ModuleUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/ModuleUtils.cpp Tue Nov 15 19:14:38 2011
@@ -16,6 +16,7 @@
 #include "llvm/Function.h"
 #include "llvm/Module.h"
 #include "llvm/Support/IRBuilder.h"
+
 using namespace llvm;
 
 void llvm::appendToGlobalCtors(Module &M, Function *F, int Priority) {



From daniel at zuster.org  Tue Nov 15 19:19:12 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 01:19:12 -0000
Subject: [llvm-commits] [compiler-rt] r144749 -
	/compiler-rt/trunk/lib/int_lib.h
Message-ID: <20111116011912.3C6592A6C133@llvm.org>

Author: ddunbar
Date: Tue Nov 15 19:19:12 2011
New Revision: 144749

URL: http://llvm.org/viewvc/llvm-project?rev=144749&view=rev
Log:
lib: Remove math.h from int_lib.h, which doesn't appear to be required.

Modified:
    compiler-rt/trunk/lib/int_lib.h

Modified: compiler-rt/trunk/lib/int_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_lib.h?rev=144749&r1=144748&r2=144749&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_lib.h (original)
+++ compiler-rt/trunk/lib/int_lib.h Tue Nov 15 19:19:12 2011
@@ -37,9 +37,6 @@
 #include <stdbool.h>
 #include <float.h>
 
-/* Include the system math.h, which we use in a number of places. */
-#include <math.h>
-
 /* If compiling for kernel use, call panic() instead of abort(). */
 #ifdef KERNEL_USE
 extern void panic (const char *, ...);



From daniel at zuster.org  Tue Nov 15 19:19:16 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 01:19:16 -0000
Subject: [llvm-commits] [compiler-rt] r144750 - in /compiler-rt/trunk/lib:
 ppc/DD.h ppc/fixtfdi.c ppc/fixunstfdi.c ppc/floatditf.c ppc/floatunditf.c
 x86_64/floatdidf.c x86_64/floatdisf.c x86_64/floatdixf.c
Message-ID: <20111116011916.819E02A6C133@llvm.org>

Author: ddunbar
Date: Tue Nov 15 19:19:16 2011
New Revision: 144750

URL: http://llvm.org/viewvc/llvm-project?rev=144750&view=rev
Log:
lib/{ppc,x86_64}: Fixup a number of files to include int_lib.h instead of
directly including system headers.

Modified:
    compiler-rt/trunk/lib/ppc/DD.h
    compiler-rt/trunk/lib/ppc/fixtfdi.c
    compiler-rt/trunk/lib/ppc/fixunstfdi.c
    compiler-rt/trunk/lib/ppc/floatditf.c
    compiler-rt/trunk/lib/ppc/floatunditf.c
    compiler-rt/trunk/lib/x86_64/floatdidf.c
    compiler-rt/trunk/lib/x86_64/floatdisf.c
    compiler-rt/trunk/lib/x86_64/floatdixf.c

Modified: compiler-rt/trunk/lib/ppc/DD.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ppc/DD.h?rev=144750&r1=144749&r2=144750&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ppc/DD.h (original)
+++ compiler-rt/trunk/lib/ppc/DD.h Tue Nov 15 19:19:16 2011
@@ -1,7 +1,7 @@
 #ifndef __DD_HEADER
 #define __DD_HEADER
 
-#include <stdint.h>
+#include "../int_lib.h"
 
 typedef union {
 	long double ld;

Modified: compiler-rt/trunk/lib/ppc/fixtfdi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ppc/fixtfdi.c?rev=144750&r1=144749&r2=144750&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ppc/fixtfdi.c (original)
+++ compiler-rt/trunk/lib/ppc/fixtfdi.c Tue Nov 15 19:19:16 2011
@@ -7,7 +7,6 @@
  */
 
 #include "DD.h"
-#include <stdint.h>
 
 uint64_t __fixtfdi(long double input)
 {

Modified: compiler-rt/trunk/lib/ppc/fixunstfdi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ppc/fixunstfdi.c?rev=144750&r1=144749&r2=144750&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ppc/fixunstfdi.c (original)
+++ compiler-rt/trunk/lib/ppc/fixunstfdi.c Tue Nov 15 19:19:16 2011
@@ -6,7 +6,6 @@
 /* This file implements the PowerPC 128-bit double-double -> uint64_t conversion */
 
 #include "DD.h"
-#include <stdint.h>
 
 uint64_t __fixunstfdi(long double input)
 {

Modified: compiler-rt/trunk/lib/ppc/floatditf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ppc/floatditf.c?rev=144750&r1=144749&r2=144750&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ppc/floatditf.c (original)
+++ compiler-rt/trunk/lib/ppc/floatditf.c Tue Nov 15 19:19:16 2011
@@ -6,7 +6,6 @@
 /* This file implements the PowerPC long long -> long double conversion */
 
 #include "DD.h"
-#include <stdint.h>
 
 long double __floatditf(int64_t a) {
 	

Modified: compiler-rt/trunk/lib/ppc/floatunditf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ppc/floatunditf.c?rev=144750&r1=144749&r2=144750&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ppc/floatunditf.c (original)
+++ compiler-rt/trunk/lib/ppc/floatunditf.c Tue Nov 15 19:19:16 2011
@@ -6,7 +6,6 @@
 /* This file implements the PowerPC unsigned long long -> long double conversion */
 
 #include "DD.h"
-#include <stdint.h>
 
 long double __floatunditf(uint64_t a) {
 	

Modified: compiler-rt/trunk/lib/x86_64/floatdidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/x86_64/floatdidf.c?rev=144750&r1=144749&r2=144750&view=diff
==============================================================================
--- compiler-rt/trunk/lib/x86_64/floatdidf.c (original)
+++ compiler-rt/trunk/lib/x86_64/floatdidf.c Tue Nov 15 19:19:16 2011
@@ -6,7 +6,7 @@
 
 #ifdef __x86_64__
 
-#include <stdint.h>
+#include "../int_lib.h"
 
 double __floatdidf(int64_t a)
 {

Modified: compiler-rt/trunk/lib/x86_64/floatdisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/x86_64/floatdisf.c?rev=144750&r1=144749&r2=144750&view=diff
==============================================================================
--- compiler-rt/trunk/lib/x86_64/floatdisf.c (original)
+++ compiler-rt/trunk/lib/x86_64/floatdisf.c Tue Nov 15 19:19:16 2011
@@ -4,7 +4,7 @@
 
 #ifdef __x86_64__
 
-#include <stdint.h>
+#include "../int_lib.h"
 
 float __floatdisf(int64_t a)
 {

Modified: compiler-rt/trunk/lib/x86_64/floatdixf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/x86_64/floatdixf.c?rev=144750&r1=144749&r2=144750&view=diff
==============================================================================
--- compiler-rt/trunk/lib/x86_64/floatdixf.c (original)
+++ compiler-rt/trunk/lib/x86_64/floatdixf.c Tue Nov 15 19:19:16 2011
@@ -6,7 +6,7 @@
 
 #ifdef __x86_64__
 
-#include <stdint.h>
+#include "../int_lib.h"
 
 long double __floatdixf(int64_t a)
 {



From daniel at zuster.org  Tue Nov 15 19:19:20 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 01:19:20 -0000
Subject: [llvm-commits] [compiler-rt] r144751 - in /compiler-rt/trunk:
 Makefile lib/int_lib.h lib/int_util.c lib/int_util.h make/config.mk
Message-ID: <20111116011920.45B142A6C133@llvm.org>

Author: ddunbar
Date: Tue Nov 15 19:19:19 2011
New Revision: 144751

URL: http://llvm.org/viewvc/llvm-project?rev=144751&view=rev
Log:
lib: Add support for library wide utility functions, and make compilerrt_abort()
a real boy.
 - The utility module needs to be included into every produced library, because
   we don't have enough dependency tracking to know exactly which other modules
   might require the utilities.

Added:
    compiler-rt/trunk/lib/int_util.c
    compiler-rt/trunk/lib/int_util.h
Modified:
    compiler-rt/trunk/Makefile
    compiler-rt/trunk/lib/int_lib.h
    compiler-rt/trunk/make/config.mk

Modified: compiler-rt/trunk/Makefile
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/Makefile?rev=144751&r1=144750&r2=144751&view=diff
==============================================================================
--- compiler-rt/trunk/Makefile (original)
+++ compiler-rt/trunk/Makefile Tue Nov 15 19:19:19 2011
@@ -164,6 +164,7 @@
 $(call Set,Tmp.Arch,$(1))
 $(call Set,Tmp.ObjPath,$(ProjObjRoot)/$(Tmp.Name)/$(Tmp.Config)/$(Tmp.Arch))
 $(call Set,Tmp.Functions,$(strip \
+  $(AlwaysRequiredModules) \
   $(call GetCNAVar,FUNCTIONS,$(Tmp.Key),$(Tmp.Config),$(Tmp.Arch))))
 $(call Set,Tmp.Optimized,$(strip \
   $(call GetCNAVar,OPTIMIZED,$(Tmp.Key),$(Tmp.Config),$(Tmp.Arch))))

Modified: compiler-rt/trunk/lib/int_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_lib.h?rev=144751&r1=144750&r2=144751&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_lib.h (original)
+++ compiler-rt/trunk/lib/int_lib.h Tue Nov 15 19:19:19 2011
@@ -37,15 +37,6 @@
 #include <stdbool.h>
 #include <float.h>
 
-/* If compiling for kernel use, call panic() instead of abort(). */
-#ifdef KERNEL_USE
-extern void panic (const char *, ...);
-#define compilerrt_abort() \
-  panic("%s:%d: abort in %s", __FILE__, __LINE__, __FUNCTION__)
-#else
-#define compilerrt_abort() abort()
-#endif
-
 #if !defined(INFINITY) && defined(HUGE_VAL)
 #define INFINITY HUGE_VAL
 #endif /* INFINITY */
@@ -53,4 +44,7 @@
 /* Include the commonly used internal type definitions. */
 #include "int_types.h"
 
+/* Include internal utility function declarations. */
+#include "int_util.h"
+
 #endif /* INT_LIB_H */

Added: compiler-rt/trunk/lib/int_util.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_util.c?rev=144751&view=auto
==============================================================================
--- compiler-rt/trunk/lib/int_util.c (added)
+++ compiler-rt/trunk/lib/int_util.c Tue Nov 15 19:19:19 2011
@@ -0,0 +1,32 @@
+/* ===-- int_util.c - Implement internal utilities --------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===----------------------------------------------------------------------===
+ */
+
+#include "int_util.h"
+#include "int_lib.h"
+
+#ifdef KERNEL_USE
+
+extern void panic(const char *, ...) __attribute__((noreturn));
+__attribute__((visibility("hidden")))
+void compilerrt_abort_impl(const char *file, int line, const char *function) {
+  panic("%s:%d: abort in %s", file, line, function);
+}
+
+#else
+
+/* Get the system definition of abort() */
+#include <stdlib.h>
+
+__attribute__((visibility("hidden")))
+void compilerrt_abort_impl(const char *file, int line, const char *function) {
+  abort();
+}
+
+#endif

Added: compiler-rt/trunk/lib/int_util.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_util.h?rev=144751&view=auto
==============================================================================
--- compiler-rt/trunk/lib/int_util.h (added)
+++ compiler-rt/trunk/lib/int_util.h Tue Nov 15 19:19:19 2011
@@ -0,0 +1,29 @@
+/* ===-- int_util.h - internal utility functions ----------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This file is not part of the interface of this library.
+ *
+ * This file defines non-inline utilities which are available for use in the
+ * library. The function definitions themselves are all contained in int_util.c
+ * which will always be compiled into any compiler-rt library.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef INT_UTIL_H
+#define INT_UTIL_H
+
+/** \brief Trigger a program abort (or panic for kernel code). */
+#define compilerrt_abort() compilerrt_abort_impl(__FILE__, __LINE__, \
+                                                 __FUNCTION__)
+void compilerrt_abort_impl(const char *file, int line,
+                           const char *function)
+  __attribute__((noreturn)) __attribute__((visibility("hidden")));
+
+#endif /* INT_UTIL_H */

Modified: compiler-rt/trunk/make/config.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/config.mk?rev=144751&r1=144750&r2=144751&view=diff
==============================================================================
--- compiler-rt/trunk/make/config.mk (original)
+++ compiler-rt/trunk/make/config.mk Tue Nov 15 19:19:19 2011
@@ -8,6 +8,11 @@
 ProjSrcRoot := $(shell pwd)
 ProjObjRoot := $(ProjSrcRoot)
 
+# The list of modules which are required to be built into every library. This
+# should only be used for internal utilities which could be used in any other
+# module. Any other cases the platform should be allowed to opt-in to.
+AlwaysRequiredModules := int_util
+
 ###
 # Tool configuration variables.
 



From daniel at zuster.org  Tue Nov 15 19:19:26 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 01:19:26 -0000
Subject: [llvm-commits] [compiler-rt] r144752 - in /compiler-rt/trunk/lib:
 absvdi2.c absvsi2.c absvti2.c addvdi3.c addvsi3.c addvti3.c clear_cache.c
 eprintf.c gcc_personality_v0.c mulodi4.c mulosi4.c muloti4.c mulvdi3.c
 mulvsi3.c mulvti3.c negvdi2.c negvsi2.c negvti2.c subvdi3.c subvsi3.c
 subvti3.c trampoline_setup.c
Message-ID: <20111116011926.ACEE02A6C133@llvm.org>

Author: ddunbar
Date: Tue Nov 15 19:19:26 2011
New Revision: 144752

URL: http://llvm.org/viewvc/llvm-project?rev=144752&view=rev
Log:
lib: Eliminate direct include of stdlib.h from files that used to (potentially)
need it for compilerrt_abort().

Modified:
    compiler-rt/trunk/lib/absvdi2.c
    compiler-rt/trunk/lib/absvsi2.c
    compiler-rt/trunk/lib/absvti2.c
    compiler-rt/trunk/lib/addvdi3.c
    compiler-rt/trunk/lib/addvsi3.c
    compiler-rt/trunk/lib/addvti3.c
    compiler-rt/trunk/lib/clear_cache.c
    compiler-rt/trunk/lib/eprintf.c
    compiler-rt/trunk/lib/gcc_personality_v0.c
    compiler-rt/trunk/lib/mulodi4.c
    compiler-rt/trunk/lib/mulosi4.c
    compiler-rt/trunk/lib/muloti4.c
    compiler-rt/trunk/lib/mulvdi3.c
    compiler-rt/trunk/lib/mulvsi3.c
    compiler-rt/trunk/lib/mulvti3.c
    compiler-rt/trunk/lib/negvdi2.c
    compiler-rt/trunk/lib/negvsi2.c
    compiler-rt/trunk/lib/negvti2.c
    compiler-rt/trunk/lib/subvdi3.c
    compiler-rt/trunk/lib/subvsi3.c
    compiler-rt/trunk/lib/subvti3.c
    compiler-rt/trunk/lib/trampoline_setup.c

Modified: compiler-rt/trunk/lib/absvdi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/absvdi2.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/absvdi2.c (original)
+++ compiler-rt/trunk/lib/absvdi2.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: absolute value */
 

Modified: compiler-rt/trunk/lib/absvsi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/absvsi2.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/absvsi2.c (original)
+++ compiler-rt/trunk/lib/absvsi2.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: absolute value */
 

Modified: compiler-rt/trunk/lib/absvti2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/absvti2.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/absvti2.c (original)
+++ compiler-rt/trunk/lib/absvti2.c Tue Nov 15 19:19:26 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: absolute value */
 

Modified: compiler-rt/trunk/lib/addvdi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/addvdi3.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/addvdi3.c (original)
+++ compiler-rt/trunk/lib/addvdi3.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a + b */
 

Modified: compiler-rt/trunk/lib/addvsi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/addvsi3.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/addvsi3.c (original)
+++ compiler-rt/trunk/lib/addvsi3.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a + b */
 

Modified: compiler-rt/trunk/lib/addvti3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/addvti3.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/addvti3.c (original)
+++ compiler-rt/trunk/lib/addvti3.c Tue Nov 15 19:19:26 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a + b */
 

Modified: compiler-rt/trunk/lib/clear_cache.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/clear_cache.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/clear_cache.c (original)
+++ compiler-rt/trunk/lib/clear_cache.c Tue Nov 15 19:19:26 2011
@@ -8,8 +8,6 @@
  * ===----------------------------------------------------------------------===
  */
 
-#include <stdlib.h>
-
 #if __APPLE__
   #include <libkern/OSCacheControl.h>
 #endif

Modified: compiler-rt/trunk/lib/eprintf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/eprintf.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/eprintf.c (original)
+++ compiler-rt/trunk/lib/eprintf.c Tue Nov 15 19:19:26 2011
@@ -12,7 +12,6 @@
 
 #include "int_lib.h"
 #include <stdio.h>
-#include <stdlib.h>
 
 
 /*

Modified: compiler-rt/trunk/lib/gcc_personality_v0.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/gcc_personality_v0.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/gcc_personality_v0.c (original)
+++ compiler-rt/trunk/lib/gcc_personality_v0.c Tue Nov 15 19:19:26 2011
@@ -10,7 +10,6 @@
  */
 
 #include <stdio.h>
-#include <stdlib.h>
 
 #include "int_lib.h"
 

Modified: compiler-rt/trunk/lib/mulodi4.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulodi4.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulodi4.c (original)
+++ compiler-rt/trunk/lib/mulodi4.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a * b */
 

Modified: compiler-rt/trunk/lib/mulosi4.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulosi4.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulosi4.c (original)
+++ compiler-rt/trunk/lib/mulosi4.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a * b */
 

Modified: compiler-rt/trunk/lib/muloti4.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/muloti4.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/muloti4.c (original)
+++ compiler-rt/trunk/lib/muloti4.c Tue Nov 15 19:19:26 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a * b */
 

Modified: compiler-rt/trunk/lib/mulvdi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulvdi3.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulvdi3.c (original)
+++ compiler-rt/trunk/lib/mulvdi3.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a * b */
 

Modified: compiler-rt/trunk/lib/mulvsi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulvsi3.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulvsi3.c (original)
+++ compiler-rt/trunk/lib/mulvsi3.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a * b */
 

Modified: compiler-rt/trunk/lib/mulvti3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulvti3.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulvti3.c (original)
+++ compiler-rt/trunk/lib/mulvti3.c Tue Nov 15 19:19:26 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a * b */
 

Modified: compiler-rt/trunk/lib/negvdi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negvdi2.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/negvdi2.c (original)
+++ compiler-rt/trunk/lib/negvdi2.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: -a */
 

Modified: compiler-rt/trunk/lib/negvsi2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negvsi2.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/negvsi2.c (original)
+++ compiler-rt/trunk/lib/negvsi2.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: -a */
 

Modified: compiler-rt/trunk/lib/negvti2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negvti2.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/negvti2.c (original)
+++ compiler-rt/trunk/lib/negvti2.c Tue Nov 15 19:19:26 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: -a */
 

Modified: compiler-rt/trunk/lib/subvdi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/subvdi3.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/subvdi3.c (original)
+++ compiler-rt/trunk/lib/subvdi3.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a - b */
 

Modified: compiler-rt/trunk/lib/subvsi3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/subvsi3.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/subvsi3.c (original)
+++ compiler-rt/trunk/lib/subvsi3.c Tue Nov 15 19:19:26 2011
@@ -13,7 +13,6 @@
  */
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a - b */
 

Modified: compiler-rt/trunk/lib/subvti3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/subvti3.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/subvti3.c (original)
+++ compiler-rt/trunk/lib/subvti3.c Tue Nov 15 19:19:26 2011
@@ -15,7 +15,6 @@
 #if __x86_64
 
 #include "int_lib.h"
-#include <stdlib.h>
 
 /* Returns: a - b */
 

Modified: compiler-rt/trunk/lib/trampoline_setup.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/trampoline_setup.c?rev=144752&r1=144751&r2=144752&view=diff
==============================================================================
--- compiler-rt/trunk/lib/trampoline_setup.c (original)
+++ compiler-rt/trunk/lib/trampoline_setup.c Tue Nov 15 19:19:26 2011
@@ -8,8 +8,6 @@
  * ===----------------------------------------------------------------------===
  */
 
-#include <stdlib.h>
-
 #include "int_lib.h"
 
 extern void __clear_cache(void* start, void* end);



From daniel at zuster.org  Tue Nov 15 19:19:29 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 01:19:29 -0000
Subject: [llvm-commits] [compiler-rt] r144753 -
	/compiler-rt/trunk/lib/gcc_personality_v0.c
Message-ID: <20111116011929.73BFE2A6C133@llvm.org>

Author: ddunbar
Date: Tue Nov 15 19:19:29 2011
New Revision: 144753

URL: http://llvm.org/viewvc/llvm-project?rev=144753&view=rev
Log:
lib/gcc_personality_v0: Remove an unnecessary include.

Modified:
    compiler-rt/trunk/lib/gcc_personality_v0.c

Modified: compiler-rt/trunk/lib/gcc_personality_v0.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/gcc_personality_v0.c?rev=144753&r1=144752&r2=144753&view=diff
==============================================================================
--- compiler-rt/trunk/lib/gcc_personality_v0.c (original)
+++ compiler-rt/trunk/lib/gcc_personality_v0.c Tue Nov 15 19:19:29 2011
@@ -9,8 +9,6 @@
  *
  */
 
-#include <stdio.h>
-
 #include "int_lib.h"
 
 /*
@@ -200,7 +198,7 @@
         
     /* There is nothing to do if there is no LSDA for this frame. */
     const uint8_t* lsda = _Unwind_GetLanguageSpecificData(context);
-    if ( lsda == NULL )
+    if ( lsda == (uint8_t*) 0 )
         return _URC_CONTINUE_UNWIND;
 
     uintptr_t pc = _Unwind_GetIP(context)-1;



From daniel at zuster.org  Tue Nov 15 19:19:32 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 01:19:32 -0000
Subject: [llvm-commits] [compiler-rt] r144754 - in /compiler-rt/trunk/lib:
 divdc3.c divsc3.c divxc3.c muldc3.c mulsc3.c mulxc3.c
Message-ID: <20111116011933.101D82A6C133@llvm.org>

Author: ddunbar
Date: Tue Nov 15 19:19:32 2011
New Revision: 144754

URL: http://llvm.org/viewvc/llvm-project?rev=144754&view=rev
Log:
lib: Remove uses of complex.h which does not appear to be required.

Modified:
    compiler-rt/trunk/lib/divdc3.c
    compiler-rt/trunk/lib/divsc3.c
    compiler-rt/trunk/lib/divxc3.c
    compiler-rt/trunk/lib/muldc3.c
    compiler-rt/trunk/lib/mulsc3.c
    compiler-rt/trunk/lib/mulxc3.c

Modified: compiler-rt/trunk/lib/divdc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divdc3.c?rev=144754&r1=144753&r2=144754&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divdc3.c (original)
+++ compiler-rt/trunk/lib/divdc3.c Tue Nov 15 19:19:32 2011
@@ -14,7 +14,6 @@
 
 #include "int_lib.h"
 #include <math.h>
-#include <complex.h>
 
 /* Returns: the quotient of (a + ib) / (c + id) */
 

Modified: compiler-rt/trunk/lib/divsc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divsc3.c?rev=144754&r1=144753&r2=144754&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divsc3.c (original)
+++ compiler-rt/trunk/lib/divsc3.c Tue Nov 15 19:19:32 2011
@@ -14,7 +14,6 @@
 
 #include "int_lib.h"
 #include <math.h>
-#include <complex.h>
 
 /* Returns: the quotient of (a + ib) / (c + id) */
 

Modified: compiler-rt/trunk/lib/divxc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divxc3.c?rev=144754&r1=144753&r2=144754&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divxc3.c (original)
+++ compiler-rt/trunk/lib/divxc3.c Tue Nov 15 19:19:32 2011
@@ -15,7 +15,6 @@
 
 #include "int_lib.h"
 #include <math.h>
-#include <complex.h>
 
 /* Returns: the quotient of (a + ib) / (c + id) */
 

Modified: compiler-rt/trunk/lib/muldc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/muldc3.c?rev=144754&r1=144753&r2=144754&view=diff
==============================================================================
--- compiler-rt/trunk/lib/muldc3.c (original)
+++ compiler-rt/trunk/lib/muldc3.c Tue Nov 15 19:19:32 2011
@@ -14,7 +14,6 @@
 
 #include "int_lib.h"
 #include <math.h>
-#include <complex.h>
 
 /* Returns: the product of a + ib and c + id */
 

Modified: compiler-rt/trunk/lib/mulsc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulsc3.c?rev=144754&r1=144753&r2=144754&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulsc3.c (original)
+++ compiler-rt/trunk/lib/mulsc3.c Tue Nov 15 19:19:32 2011
@@ -14,7 +14,6 @@
 
 #include "int_lib.h"
 #include <math.h>
-#include <complex.h>
 
 /* Returns: the product of a + ib and c + id */
 

Modified: compiler-rt/trunk/lib/mulxc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulxc3.c?rev=144754&r1=144753&r2=144754&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulxc3.c (original)
+++ compiler-rt/trunk/lib/mulxc3.c Tue Nov 15 19:19:32 2011
@@ -16,7 +16,6 @@
 
 #include "int_lib.h"
 #include <math.h>
-#include <complex.h>
 
 /* Returns: the product of a + ib and c + id */
 



From bigcheesegs at gmail.com  Tue Nov 15 19:24:41 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Wed, 16 Nov 2011 01:24:41 -0000
Subject: [llvm-commits] [llvm] r144755 -
	/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
Message-ID: <20111116012441.5C4F22A6C133@llvm.org>

Author: mspencer
Date: Tue Nov 15 19:24:41 2011
New Revision: 144755

URL: http://llvm.org/viewvc/llvm-project?rev=144755&view=rev
Log:
llvm-objdump: Ignore non-objects in archives.

Modified:
    llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp

Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=144755&r1=144754&r2=144755&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Tue Nov 15 19:24:41 2011
@@ -556,8 +556,10 @@
                                e = a->end_children(); i != e; ++i) {
     OwningPtr<Binary> child;
     if (error_code ec = i->getAsBinary(child)) {
-      errs() << ToolName << ": '" << a->getFileName() << "': " << ec.message()
-             << ".\n";
+      // Ignore non-object files.
+      if (ec != object_error::invalid_file_type)
+        errs() << ToolName << ": '" << a->getFileName() << "': " << ec.message()
+               << ".\n";
       continue;
     }
     if (ObjectFile *o = dyn_cast<ObjectFile>(child.get()))



From bigcheesegs at gmail.com  Tue Nov 15 19:24:57 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Wed, 16 Nov 2011 01:24:57 -0000
Subject: [llvm-commits] [llvm] r144756 -
	/llvm/trunk/include/llvm/Support/COFF.h
Message-ID: <20111116012457.BD3F92A6C133@llvm.org>

Author: mspencer
Date: Tue Nov 15 19:24:57 2011
New Revision: 144756

URL: http://llvm.org/viewvc/llvm-project?rev=144756&view=rev
Log:
Support/COFF: Add structs and enums from the standard for image files.

Modified:
    llvm/trunk/include/llvm/Support/COFF.h

Modified: llvm/trunk/include/llvm/Support/COFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/COFF.h?rev=144756&r1=144755&r2=144756&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/COFF.h (original)
+++ llvm/trunk/include/llvm/Support/COFF.h Tue Nov 15 19:24:57 2011
@@ -24,6 +24,7 @@
 #define LLVM_SUPPORT_WIN_COFF_H
 
 #include "llvm/Support/DataTypes.h"
+#include <cassert>
 #include <cstring>
 
 namespace llvm {
@@ -49,8 +50,65 @@
   };
 
   enum MachineTypes {
-    IMAGE_FILE_MACHINE_I386 = 0x14C,
-    IMAGE_FILE_MACHINE_AMD64 = 0x8664
+    IMAGE_FILE_MACHINE_UNKNOWN   = 0x0,
+    IMAGE_FILE_MACHINE_AM33      = 0x13,
+    IMAGE_FILE_MACHINE_AMD64     = 0x8664,
+    IMAGE_FILE_MACHINE_ARM       = 0x1C0,
+    IMAGE_FILE_MACHINE_ARMV7     = 0x1C4,
+    IMAGE_FILE_MACHINE_EBC       = 0xEBC,
+    IMAGE_FILE_MACHINE_I386      = 0x14C,
+    IMAGE_FILE_MACHINE_IA64      = 0x200,
+    IMAGE_FILE_MACHINE_M32R      = 0x9041,
+    IMAGE_FILE_MACHINE_MIPS16    = 0x266,
+    IMAGE_FILE_MACHINE_MIPSFPU   = 0x366,
+    IMAGE_FILE_MACHINE_MIPSFPU16 = 0x466,
+    IMAGE_FILE_MACHINE_POWERPC   = 0x1F0,
+    IMAGE_FILE_MACHINE_POWERPCFP = 0x1F1,
+    IMAGE_FILE_MACHINE_R4000     = 0x166,
+    IMAGE_FILE_MACHINE_SH3       = 0x1A2,
+    IMAGE_FILE_MACHINE_SH3DSP    = 0x1A3,
+    IMAGE_FILE_MACHINE_SH4       = 0x1A6,
+    IMAGE_FILE_MACHINE_SH5       = 0x1A8,
+    IMAGE_FILE_MACHINE_THUMB     = 0x1C2,
+    IMAGE_FILE_MACHINE_WCEMIPSV2 = 0x169
+  };
+
+  enum Characteristics {
+    /// The file does not contain base relocations and must be loaded at its
+    /// preferred base. If this cannot be done, the loader will error.
+    IMAGE_FILE_RELOCS_STRIPPED         = 0x0001,
+    /// The file is valid and can be run.
+    IMAGE_FILE_EXECUTABLE_IMAGE        = 0x0002,
+    /// COFF line numbers have been stripped. This is deprecated and should be
+    /// 0.
+    IMAGE_FILE_LINE_NUMS_STRIPPED      = 0x0004,
+    /// COFF symbol table entries for local symbols have been removed. This is
+    /// deprecated and should be 0.
+    IMAGE_FILE_LOCAL_SYMS_STRIPPED     = 0x0008,
+    /// Aggressively trim working set. This is deprecated and must be 0.
+    IMAGE_FILE_AGGRESSIVE_WS_TRIM      = 0x0010,
+    /// Image can handle > 2GiB addresses.
+    IMAGE_FILE_LARGE_ADDRESS_AWARE     = 0x0020,
+    /// Little endian: the LSB precedes the MSB in memory. This is deprecated
+    /// and should be 0.
+    IMAGE_FILE_BYTES_REVERSED_LO       = 0x0080,
+    /// Machine is based on a 32bit word architecture.
+    IMAGE_FILE_32BIT_MACHINE           = 0x0100,
+    /// Debugging info has been removed.
+    IMAGE_FILE_DEBUG_STRIPPED          = 0x0200,
+    /// If the image is on removable media, fully load it and copy it to swap.
+    IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP = 0x0400,
+    /// If the image is on network media, fully load it and copy it to swap.
+    IMAGE_FILE_NET_RUN_FROM_SWAP       = 0x0800,
+    /// The image file is a system file, not a user program.
+    IMAGE_FILE_SYSTEM                  = 0x1000,
+    /// The image file is a DLL.
+    IMAGE_FILE_DLL                     = 0x2000,
+    /// This file should only be run on a uniprocessor machine.
+    IMAGE_FILE_UP_SYSTEM_ONLY          = 0x4000,
+    /// Big endian: the MSB precedes the LSB in memory. This is deprecated
+    /// and should be 0.
+    IMAGE_FILE_BYTES_REVERSED_HI       = 0x8000
   };
 
   struct symbol {
@@ -231,6 +289,24 @@
     IMAGE_REL_AMD64_SSPAN32   = 0x0010
   };
 
+  enum RelocationTypesARM {
+    IMAGE_REL_ARM_ABSOLUTE  = 0x0000,
+    IMAGE_REL_ARM_ADDR32    = 0x0001,
+    IMAGE_REL_ARM_ADDR32NB  = 0x0002,
+    IMAGE_REL_ARM_BRANCH24  = 0x0003,
+    IMAGE_REL_ARM_BRANCH11  = 0x0004,
+    IMAGE_REL_ARM_TOKEN     = 0x0005,
+    IMAGE_REL_ARM_BLX24     = 0x0008,
+    IMAGE_REL_ARM_BLX11     = 0x0009,
+    IMAGE_REL_ARM_SECTION   = 0x000E,
+    IMAGE_REL_ARM_SECREL    = 0x000F,
+    IMAGE_REL_ARM_MOV32A    = 0x0010,
+    IMAGE_REL_ARM_MOV32T    = 0x0011,
+    IMAGE_REL_ARM_BRANCH20T = 0x0012,
+    IMAGE_REL_ARM_BRANCH24T = 0x0014,
+    IMAGE_REL_ARM_BLX23T    = 0x0015
+  };
+
   enum COMDATType {
     IMAGE_COMDAT_SELECT_NODUPLICATES = 1,
     IMAGE_COMDAT_SELECT_ANY,
@@ -292,7 +368,219 @@
     AuxiliarySectionDefinition  SectionDefinition;
   };
 
-} // End namespace llvm.
+  /// @brief The Import Directory Table.
+  ///
+  /// There is a single array of these and one entry per imported DLL.
+  struct ImportDirectoryTableEntry {
+    uint32_t ImportLookupTableRVA;
+    uint32_t TimeDateStamp;
+    uint32_t ForwarderChain;
+    uint32_t NameRVA;
+    uint32_t ImportAddressTableRVA;
+  };
+
+  /// @brief The PE32 Import Lookup Table.
+  ///
+  /// There is an array of these for each imported DLL. It represents either
+  /// the ordinal to import from the target DLL, or a name to lookup and import
+  /// from the target DLL.
+  ///
+  /// This also happens to be the same format used by the Import Address Table
+  /// when it is initially written out to the image.
+  struct ImportLookupTableEntry32 {
+    uint32_t data;
+
+    /// @brief Is this entry specified by ordinal, or name?
+    bool isOrdinal() const { return data & 0x80000000; }
+
+    /// @brief Get the ordinal value of this entry. isOrdinal must be true.
+    uint16_t getOrdinal() const {
+      assert(isOrdinal() && "ILT entry is not an ordinal!");
+      return data & 0xFFFF;
+    }
+
+    /// @brief Set the ordinal value and set isOrdinal to true.
+    void setOrdinal(uint16_t o) {
+      data = o;
+      data |= 0x80000000;
+    }
+
+    /// @brief Get the Hint/Name entry RVA. isOrdinal must be false.
+    uint32_t getHintNameRVA() const {
+      assert(!isOrdinal() && "ILT entry is not a Hint/Name RVA!");
+      return data;
+    }
+
+    /// @brief Set the Hint/Name entry RVA and set isOrdinal to false.
+    void setHintNameRVA(uint32_t rva) { data = rva; }
+  };
+
+  /// @brief The DOS compatible header at the front of all PEs.
+  struct DOSHeader {
+    uint16_t Magic;
+    uint16_t UsedBytesInTheLastPage;
+    uint16_t FileSizeInPages;
+    uint16_t NumberOfRelocationItems;
+    uint16_t HeaderSizeInParagraphs;
+    uint16_t MinimumExtraParagraphs;
+    uint16_t MaximumExtraParagraphs;
+    uint16_t InitialRelativeSS;
+    uint16_t InitialSP;
+    uint16_t Checksum;
+    uint16_t InitialIP;
+    uint16_t InitialRelativeCS;
+    uint16_t AddressOfRelocationTable;
+    uint16_t OverlayNumber;
+    uint16_t Reserved[4];
+    uint16_t OEMid;
+    uint16_t OEMinfo;
+    uint16_t Reserved2[10];
+    uint32_t AddressOfNewExeHeader;
+  };
+
+  struct PEHeader {
+    uint32_t Signature;
+    header COFFHeader;
+    uint16_t Magic;
+    uint8_t  MajorLinkerVersion;
+    uint8_t  MinorLinkerVersion;
+    uint32_t SizeOfCode;
+    uint32_t SizeOfInitializedData;
+    uint32_t SizeOfUninitializedData;
+    uint32_t AddressOfEntryPoint; // RVA
+    uint32_t BaseOfCode; // RVA
+    uint32_t BaseOfData; // RVA
+    uint64_t ImageBase;
+    uint32_t SectionAlignment;
+    uint32_t FileAlignment;
+    uint16_t MajorOperatingSystemVersion;
+    uint16_t MinorOperatingSystemVersion;
+    uint16_t MajorImageVersion;
+    uint16_t MinorImageVersion;
+    uint16_t MajorSubsystemVersion;
+    uint16_t MinorSubsystemVersion;
+    uint32_t Win32VersionValue;
+    uint32_t SizeOfImage;
+    uint32_t SizeOfHeaders;
+    uint32_t CheckSum;
+    uint16_t Subsystem;
+    uint16_t DLLCharacteristics;
+    uint64_t SizeOfStackReserve;
+    uint64_t SizeOfStackCommit;
+    uint64_t SizeOfHeapReserve;
+    uint64_t SizeOfHeapCommit;
+    uint32_t LoaderFlags;
+    uint32_t NumberOfRvaAndSize;
+  };
+
+  struct DataDirectory {
+    uint32_t RelativeVirtualAddress;
+    uint32_t Size;
+  };
+
+  enum WindowsSubsystem {
+    IMAGE_SUBSYSTEM_UNKNOWN = 0, ///< An unknown subsystem.
+    IMAGE_SUBSYSTEM_NATIVE = 1, ///< Device drivers and native Windows processes
+    IMAGE_SUBSYSTEM_WINDOWS_GUI = 2, ///< The Windows GUI subsystem.
+    IMAGE_SUBSYSTEM_WINDOWS_CUI = 3, ///< The Windows character subsystem.
+    IMAGE_SUBSYSTEM_POSIX_CUI = 7, ///< The POSIX character subsystem.
+    IMAGE_SUBSYSTEM_WINDOWS_CE_GUI = 9, ///< Windows CE.
+    IMAGE_SUBSYSTEM_EFI_APPLICATION = 10, ///< An EFI application.
+    IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER = 11, ///< An EFI driver with boot
+                                                  ///  services.
+    IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER = 12, ///< An EFI driver with run-time
+                                             ///  services.
+    IMAGE_SUBSYSTEM_EFI_ROM = 13, ///< An EFI ROM image.
+    IMAGE_SUBSYSTEM_XBOX = 14 ///< XBOX.
+  };
+
+  enum DLLCharacteristics {
+    /// DLL can be relocated at load time.
+    IMAGE_DLL_CHARACTERISTICS_DYNAMIC_BASE = 0x0040,
+    /// Code integrity checks are enforced.
+    IMAGE_DLL_CHARACTERISTICS_FORCE_INTEGRITY = 0x0080,
+    IMAGE_DLL_CHARACTERISTICS_NX_COMPAT = 0x0100, ///< Image is NX compatible.
+    /// Isolation aware, but do not isolate the image.
+    IMAGE_DLL_CHARACTERISTICS_NO_ISOLATION = 0x0200,
+    /// Does not use structured exception handling (SEH). No SEH handler may be
+    /// called in this image.
+    IMAGE_DLL_CHARACTERISTICS_NO_SEH = 0x0400,
+    /// Do not bind the image.
+    IMAGE_DLL_CHARACTERISTICS_NO_BIND = 0x0800,
+    IMAGE_DLL_CHARACTERISTICS_WDM_DRIVER = 0x2000, ///< A WDM driver.
+    /// Terminal Server aware.
+    IMAGE_DLL_CHARACTERISTICS_TERMINAL_SERVER_AWARE = 0x8000
+  };
+
+  enum DebugType {
+    IMAGE_DEBUG_TYPE_UNKNOWN       = 0,
+    IMAGE_DEBUG_TYPE_COFF          = 1,
+    IMAGE_DEBUG_TYPE_CODEVIEW      = 2,
+    IMAGE_DEBUG_TYPE_FPO           = 3,
+    IMAGE_DEBUG_TYPE_MISC          = 4,
+    IMAGE_DEBUG_TYPE_EXCEPTION     = 5,
+    IMAGE_DEBUG_TYPE_FIXUP         = 6,
+    IMAGE_DEBUG_TYPE_OMAP_TO_SRC   = 7,
+    IMAGE_DEBUG_TYPE_OMAP_FROM_SRC = 8,
+    IMAGE_DEBUG_TYPE_BORLAND       = 9,
+    IMAGE_DEBUG_TYPE_CLSID         = 11
+  };
+
+  enum BaseRelocationType {
+    IMAGE_REL_BASED_ABSOLUTE       = 0,
+    IMAGE_REL_BASED_HIGH           = 1,
+    IMAGE_REL_BASED_LOW            = 2,
+    IMAGE_REL_BASED_HIGHLOW        = 3,
+    IMAGE_REL_BASED_HIGHADJ        = 4,
+    IMAGE_REL_BASED_MIPS_JMPADDR   = 5,
+    IMAGE_REL_BASED_ARM_MOV32A     = 5,
+    IMAGE_REL_BASED_ARM_MOV32T     = 7,
+    IMAGE_REL_BASED_MIPS_JMPADDR16 = 9,
+    IMAGE_REL_BASED_DIR64          = 10
+  };
+
+  enum ImportType {
+    IMPORT_CODE  = 0,
+    IMPORT_DATA  = 1,
+    IMPORT_CONST = 2
+  };
+
+  enum ImportNameType {
+    /// Import is by ordinal. This indicates that the value in the Ordinal/Hint
+    /// field of the import header is the import's ordinal. If this constant is
+    /// not specified, then the Ordinal/Hint field should always be interpreted
+    /// as the import's hint.
+    IMPORT_ORDINAL         = 0,
+    /// The import name is identical to the public symbol name
+    IMPORT_NAME            = 1,
+    /// The import name is the public symbol name, but skipping the leading ?,
+    /// @, or optionally _.
+    IMPORT_NAME_NOPREFIX   = 2,
+    /// The import name is the public symbol name, but skipping the leading ?,
+    /// @, or optionally _, and truncating at the first @.
+    IMPORT_NAME_UNDECORATE = 3,
+  };
+
+  struct ImportHeader {
+    uint16_t Sig1; ///< Must be IMAGE_FILE_MACHINE_UNKNOWN (0).
+    uint16_t Sig2; ///< Must be 0xFFFF.
+    uint16_t Version;
+    uint16_t Machine;
+    uint32_t TimeDateStamp;
+    uint32_t SizeOfData;
+    uint16_t OrdinalHint;
+    uint16_t TypeInfo;
+
+    ImportType getType() const {
+      return static_cast<ImportType>(TypeInfo & 0x3);
+    }
+
+    ImportNameType getNameType() const {
+      return static_cast<ImportNameType>((TypeInfo & 0x1C) >> 3);
+    }
+  };
+
 } // End namespace COFF.
+} // End namespace llvm.
 
 #endif



From bigcheesegs at gmail.com  Tue Nov 15 19:25:13 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Wed, 16 Nov 2011 01:25:13 -0000
Subject: [llvm-commits] [llvm] r144757 -
	/llvm/trunk/include/llvm/Object/Archive.h
Message-ID: <20111116012513.673D32A6C133@llvm.org>

Author: mspencer
Date: Tue Nov 15 19:25:13 2011
New Revision: 144757

URL: http://llvm.org/viewvc/llvm-project?rev=144757&view=rev
Log:
Object/Archive: Give Child a operator < for map.

Modified:
    llvm/trunk/include/llvm/Object/Archive.h

Modified: llvm/trunk/include/llvm/Object/Archive.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/Archive.h?rev=144757&r1=144756&r2=144757&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/Archive.h (original)
+++ llvm/trunk/include/llvm/Object/Archive.h Tue Nov 15 19:25:13 2011
@@ -34,6 +34,10 @@
       return (Parent == other.Parent) && (Data.begin() == other.Data.begin());
     }
 
+    bool operator <(const Child &other) const {
+      return Data.begin() < other.Data.begin();
+    }
+
     Child getNext() const;
     error_code getName(StringRef &Result) const;
     int getLastModified() const;
@@ -64,6 +68,10 @@
       return !(*this == other);
     }
 
+    bool operator <(const child_iterator &other) const {
+      return child < other.child;
+    }
+
     child_iterator& operator++() {  // Preincrement
       child = child.getNext();
       return *this;



From kcc at google.com  Tue Nov 15 19:35:23 2011
From: kcc at google.com (Kostya Serebryany)
Date: Wed, 16 Nov 2011 01:35:23 -0000
Subject: [llvm-commits] [llvm] r144758 - in /llvm/trunk:
 include/llvm/InitializePasses.h include/llvm/Transforms/Instrumentation.h
 lib/Transforms/Instrumentation/AddressSanitizer.cpp
 lib/Transforms/Instrumentation/CMakeLists.txt
 lib/Transforms/Instrumentation/Instrumentation.cpp test/Instrumentation/
 test/Instrumentation/AddressSanitizer/
 test/Instrumentation/AddressSanitizer/dg.exp
 test/Instrumentation/AddressSanitizer/test64.ll
Message-ID: <20111116013523.E81E22A6C133@llvm.org>

Author: kcc
Date: Tue Nov 15 19:35:23 2011
New Revision: 144758

URL: http://llvm.org/viewvc/llvm-project?rev=144758&view=rev
Log:
AddressSanitizer, first commit (compiler module only)

Added:
    llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
    llvm/trunk/test/Instrumentation/
    llvm/trunk/test/Instrumentation/AddressSanitizer/
    llvm/trunk/test/Instrumentation/AddressSanitizer/dg.exp
    llvm/trunk/test/Instrumentation/AddressSanitizer/test64.ll
Modified:
    llvm/trunk/include/llvm/InitializePasses.h
    llvm/trunk/include/llvm/Transforms/Instrumentation.h
    llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt
    llvm/trunk/lib/Transforms/Instrumentation/Instrumentation.cpp

Modified: llvm/trunk/include/llvm/InitializePasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=144758&r1=144757&r2=144758&view=diff
==============================================================================
--- llvm/trunk/include/llvm/InitializePasses.h (original)
+++ llvm/trunk/include/llvm/InitializePasses.h Tue Nov 15 19:35:23 2011
@@ -96,6 +96,7 @@
 void initializeEdgeProfilerPass(PassRegistry&);
 void initializePathProfilerPass(PassRegistry&);
 void initializeGCOVProfilerPass(PassRegistry&);
+void initializeAddressSanitizerPass(PassRegistry&);
 void initializeEarlyCSEPass(PassRegistry&);
 void initializeExpandISelPseudosPass(PassRegistry&);
 void initializeFindUsedTypesPass(PassRegistry&);

Modified: llvm/trunk/include/llvm/Transforms/Instrumentation.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Instrumentation.h?rev=144758&r1=144757&r2=144758&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Instrumentation.h (original)
+++ llvm/trunk/include/llvm/Transforms/Instrumentation.h Tue Nov 15 19:35:23 2011
@@ -31,6 +31,9 @@
 ModulePass *createGCOVProfilerPass(bool EmitNotes = true, bool EmitData = true,
                                    bool Use402Format = false);
 
+// Insert AddressSanitizer (address sanity checking) instrumentation
+ModulePass *createAddressSanitizerPass();
+
 } // End llvm namespace
 
 #endif

Added: llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp?rev=144758&view=auto
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp (added)
+++ llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Tue Nov 15 19:35:23 2011
@@ -0,0 +1,965 @@
+//===-- AddressSanitizer.cpp - memory error detector ------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is a part of AddressSanitizer, an address sanity checker.
+// Details of the algorithm:
+//  http://code.google.com/p/address-sanitizer/wiki/AddressSanitizerAlgorithm
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "asan"
+
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/OwningPtr.h"
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/Function.h"
+#include "llvm/InlineAsm.h"
+#include "llvm/IntrinsicInst.h"
+#include "llvm/LLVMContext.h"
+#include "llvm/Module.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/DataTypes.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/IRBuilder.h"
+#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/Regex.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/system_error.h"
+#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Transforms/Instrumentation.h"
+#include "llvm/Transforms/Utils/BasicBlockUtils.h"
+#include "llvm/Transforms/Utils/ModuleUtils.h"
+#include "llvm/Type.h"
+
+#include <string>
+#include <algorithm>
+
+using namespace llvm;
+
+static const uint64_t kDefaultShadowScale = 3;
+static const uint64_t kDefaultShadowOffset32 = 1ULL << 29;
+static const uint64_t kDefaultShadowOffset64 = 1ULL << 44;
+
+static const size_t kMaxStackMallocSize = 1 << 16;  // 64K
+static const uintptr_t kCurrentStackFrameMagic = 0x41B58AB3;
+static const uintptr_t kRetiredStackFrameMagic = 0x45E0360E;
+
+static const char *kAsanModuleCtorName = "asan.module_ctor";
+static const char *kAsanReportErrorTemplate = "__asan_report_";
+static const char *kAsanRegisterGlobalsName = "__asan_register_globals";
+static const char *kAsanInitName = "__asan_init";
+static const char *kAsanMappingOffsetName = "__asan_mapping_offset";
+static const char *kAsanMappingScaleName = "__asan_mapping_scale";
+static const char *kAsanStackMallocName = "__asan_stack_malloc";
+static const char *kAsanStackFreeName = "__asan_stack_free";
+
+static const int kAsanStackLeftRedzoneMagic = 0xf1;
+static const int kAsanStackMidRedzoneMagic = 0xf2;
+static const int kAsanStackRightRedzoneMagic = 0xf3;
+static const int kAsanStackPartialRedzoneMagic = 0xf4;
+
+// Command-line flags.
+
+// This flag may need to be replaced with -f[no-]asan-reads.
+static cl::opt<bool> ClInstrumentReads("asan-instrument-reads",
+       cl::desc("instrument read instructions"), cl::Hidden, cl::init(true));
+static cl::opt<bool> ClInstrumentWrites("asan-instrument-writes",
+       cl::desc("instrument write instructions"), cl::Hidden, cl::init(true));
+// This flag may need to be replaced with -f[no]asan-stack.
+static cl::opt<bool> ClStack("asan-stack",
+       cl::desc("Handle stack memory"), cl::Hidden, cl::init(true));
+// This flag may need to be replaced with -f[no]asan-use-after-return.
+static cl::opt<bool> ClUseAfterReturn("asan-use-after-return",
+       cl::desc("Check return-after-free"), cl::Hidden, cl::init(false));
+// This flag may need to be replaced with -f[no]asan-globals.
+static cl::opt<bool> ClGlobals("asan-globals",
+       cl::desc("Handle global objects"), cl::Hidden, cl::init(true));
+static cl::opt<bool> ClMemIntrin("asan-memintrin",
+       cl::desc("Handle memset/memcpy/memmove"), cl::Hidden, cl::init(true));
+// This flag may need to be replaced with -fasan-blacklist.
+static cl::opt<std::string>  ClBlackListFile("asan-blacklist",
+       cl::desc("File containing the list of functions to ignore "
+                "during instrumentation"), cl::Hidden);
+static cl::opt<bool> ClUseCall("asan-use-call",
+       cl::desc("Use function call to generate a crash"), cl::Hidden,
+       cl::init(true));
+
+// These flags allow to change the shadow mapping.
+// The shadow mapping looks like
+//    Shadow = (Mem >> scale) + (1 << offset_log)
+static cl::opt<int> ClMappingScale("asan-mapping-scale",
+       cl::desc("scale of asan shadow mapping"), cl::Hidden, cl::init(0));
+static cl::opt<int> ClMappingOffsetLog("asan-mapping-offset-log",
+       cl::desc("offset of asan shadow mapping"), cl::Hidden, cl::init(-1));
+
+// Optimization flags. Not user visible, used mostly for testing
+// and benchmarking the tool.
+static cl::opt<bool> ClOpt("asan-opt",
+       cl::desc("Optimize instrumentation"), cl::Hidden, cl::init(true));
+static cl::opt<bool> ClOptSameTemp("asan-opt-same-temp",
+       cl::desc("Instrument the same temp just once"), cl::Hidden,
+       cl::init(true));
+static cl::opt<bool> ClOptGlobals("asan-opt-globals",
+       cl::desc("Don't instrument scalar globals"), cl::Hidden, cl::init(true));
+
+// Debug flags.
+static cl::opt<int> ClDebug("asan-debug", cl::desc("debug"), cl::Hidden,
+                            cl::init(0));
+static cl::opt<int> ClDebugStack("asan-debug-stack", cl::desc("debug stack"),
+                                 cl::Hidden, cl::init(0));
+static cl::opt<std::string> ClDebugFunc("asan-debug-func",
+                                        cl::Hidden, cl::desc("Debug func"));
+static cl::opt<int> ClDebugMin("asan-debug-min", cl::desc("Debug min inst"),
+                               cl::Hidden, cl::init(-1));
+static cl::opt<int> ClDebugMax("asan-debug-max", cl::desc("Debug man inst"),
+                               cl::Hidden, cl::init(-1));
+
+namespace {
+
+// Blacklisted functions are not instrumented.
+// The blacklist file contains one or more lines like this:
+// ---
+// fun:FunctionWildCard
+// ---
+// This is similar to the "ignore" feature of ThreadSanitizer.
+// http://code.google.com/p/data-race-test/wiki/ThreadSanitizerIgnores
+class BlackList {
+ public:
+  BlackList(const std::string &Path);
+  bool isIn(const Function &F);
+ private:
+  Regex *Functions;
+};
+
+/// AddressSanitizer: instrument the code in module to find memory bugs.
+struct AddressSanitizer : public ModulePass {
+  AddressSanitizer();
+  void instrumentMop(Instruction *I);
+  void instrumentAddress(Instruction *OrigIns, IRBuilder<> &IRB,
+                         Value *Addr, uint32_t TypeSize, bool IsWrite);
+  Instruction *generateCrashCode(IRBuilder<> &IRB, Value *Addr,
+                                 bool IsWrite, uint32_t TypeSize);
+  bool instrumentMemIntrinsic(MemIntrinsic *MI);
+  void instrumentMemIntrinsicParam(Instruction *OrigIns, Value *Addr,
+                                  Value *Size,
+                                   Instruction *InsertBefore, bool IsWrite);
+  Value *memToShadow(Value *Shadow, IRBuilder<> &IRB);
+  bool handleFunction(Module &M, Function &F);
+  bool poisonStackInFunction(Module &M, Function &F);
+  virtual bool runOnModule(Module &M);
+  bool insertGlobalRedzones(Module &M);
+  BranchInst *splitBlockAndInsertIfThen(Instruction *SplitBefore, Value *Cmp);
+  static char ID;  // Pass identification, replacement for typeid
+
+ private:
+
+  uint64_t getAllocaSizeInBytes(AllocaInst *AI) {
+    Type *Ty = AI->getAllocatedType();
+    uint64_t SizeInBytes = TD->getTypeStoreSizeInBits(Ty) / 8;
+    return SizeInBytes;
+  }
+  uint64_t getAlignedSize(uint64_t SizeInBytes) {
+    return ((SizeInBytes + RedzoneSize - 1)
+            / RedzoneSize) * RedzoneSize;
+  }
+  uint64_t getAlignedAllocaSize(AllocaInst *AI) {
+    uint64_t SizeInBytes = getAllocaSizeInBytes(AI);
+    return getAlignedSize(SizeInBytes);
+  }
+
+  void PoisonStack(const ArrayRef<AllocaInst*> &AllocaVec, IRBuilder<> IRB,
+                   Value *ShadowBase, bool DoPoison);
+
+  Module      *CurrentModule;
+  LLVMContext *C;
+  TargetData *TD;
+  uint64_t MappingOffset;
+  int MappingScale;
+  size_t RedzoneSize;
+  int LongSize;
+  Type *IntptrTy;
+  Type *IntptrPtrTy;
+  Function *AsanCtorFunction;
+  Function *AsanInitFunction;
+  Instruction *CtorInsertBefore;
+  OwningPtr<BlackList> BL;
+};
+}  // namespace
+
+char AddressSanitizer::ID = 0;
+INITIALIZE_PASS(AddressSanitizer, "asan",
+    "AddressSanitizer: detects use-after-free and out-of-bounds bugs.",
+    false, false)
+AddressSanitizer::AddressSanitizer() : ModulePass(ID) { }
+ModulePass *llvm::createAddressSanitizerPass() {
+  return new AddressSanitizer();
+}
+
+// Create a constant for Str so that we can pass it to the run-time lib.
+static GlobalVariable *createPrivateGlobalForString(Module &M, StringRef Str) {
+  Constant *StrConst = ConstantArray::get(M.getContext(), Str);
+  return new GlobalVariable(M, StrConst->getType(), true,
+                            GlobalValue::PrivateLinkage, StrConst, "");
+}
+
+// Split the basic block and insert an if-then code.
+// Before:
+//   Head
+//   SplitBefore
+//   Tail
+// After:
+//   Head
+//   if (Cmp)
+//     NewBasicBlock
+//   SplitBefore
+//   Tail
+//
+// Returns the NewBasicBlock's terminator.
+BranchInst *AddressSanitizer::splitBlockAndInsertIfThen(
+    Instruction *SplitBefore, Value *Cmp) {
+  BasicBlock *Head = SplitBefore->getParent();
+  BasicBlock *Tail = Head->splitBasicBlock(SplitBefore);
+  TerminatorInst *HeadOldTerm = Head->getTerminator();
+  BasicBlock *NewBasicBlock =
+      BasicBlock::Create(*C, "", Head->getParent());
+  BranchInst *HeadNewTerm = BranchInst::Create(/*ifTrue*/NewBasicBlock,
+                                               /*ifFalse*/Tail,
+                                               Cmp);
+  ReplaceInstWithInst(HeadOldTerm, HeadNewTerm);
+
+  BranchInst *CheckTerm = BranchInst::Create(Tail, NewBasicBlock);
+  return CheckTerm;
+}
+
+Value *AddressSanitizer::memToShadow(Value *Shadow, IRBuilder<> &IRB) {
+  // Shadow >> scale
+  Shadow = IRB.CreateLShr(Shadow, MappingScale);
+  if (MappingOffset == 0)
+    return Shadow;
+  // (Shadow >> scale) | offset
+  return IRB.CreateOr(Shadow, ConstantInt::get(IntptrTy,
+                                               MappingOffset));
+}
+
+void AddressSanitizer::instrumentMemIntrinsicParam(Instruction *OrigIns,
+    Value *Addr, Value *Size, Instruction *InsertBefore, bool IsWrite) {
+  // Check the first byte.
+  {
+    IRBuilder<> IRB(InsertBefore);
+    instrumentAddress(OrigIns, IRB, Addr, 8, IsWrite);
+  }
+  // Check the last byte.
+  {
+    IRBuilder<> IRB(InsertBefore);
+    Value *SizeMinusOne = IRB.CreateSub(
+        Size, ConstantInt::get(Size->getType(), 1));
+    SizeMinusOne = IRB.CreateIntCast(SizeMinusOne, IntptrTy, false);
+    Value *AddrLong = IRB.CreatePointerCast(Addr, IntptrTy);
+    Value *AddrPlusSizeMinisOne = IRB.CreateAdd(AddrLong, SizeMinusOne);
+    instrumentAddress(OrigIns, IRB, AddrPlusSizeMinisOne, 8, IsWrite);
+  }
+}
+
+// Instrument memset/memmove/memcpy
+bool AddressSanitizer::instrumentMemIntrinsic(MemIntrinsic *MI) {
+  Value *Dst = MI->getDest();
+  MemTransferInst *MemTran = dyn_cast<MemTransferInst>(MI);
+  Value *Src = MemTran ? MemTran->getSource() : NULL;
+  Value *Length = MI->getLength();
+
+  Constant *ConstLength = dyn_cast<Constant>(Length);
+  Instruction *InsertBefore = MI;
+  if (ConstLength) {
+    if (ConstLength->isNullValue()) return false;
+  } else {
+    // The size is not a constant so it could be zero -- check at run-time.
+    IRBuilder<> IRB(InsertBefore);
+
+    Value *Cmp = IRB.CreateICmpNE(Length,
+                                   Constant::getNullValue(Length->getType()));
+    InsertBefore = splitBlockAndInsertIfThen(InsertBefore, Cmp);
+  }
+
+  instrumentMemIntrinsicParam(MI, Dst, Length, InsertBefore, true);
+  if (Src)
+    instrumentMemIntrinsicParam(MI, Src, Length, InsertBefore, false);
+  return true;
+}
+
+static Value *getLDSTOperand(Instruction *I) {
+  if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
+    return LI->getPointerOperand();
+  }
+  return cast<StoreInst>(*I).getPointerOperand();
+}
+
+void AddressSanitizer::instrumentMop(Instruction *I) {
+  int IsWrite = isa<StoreInst>(*I);
+  Value *Addr = getLDSTOperand(I);
+  if (ClOpt && ClOptGlobals && isa<GlobalVariable>(Addr)) {
+    // We are accessing a global scalar variable. Nothing to catch here.
+    return;
+  }
+  Type *OrigPtrTy = Addr->getType();
+  Type *OrigTy = cast<PointerType>(OrigPtrTy)->getElementType();
+
+  assert(OrigTy->isSized());
+  uint32_t TypeSize = TD->getTypeStoreSizeInBits(OrigTy);
+
+  if (TypeSize != 8  && TypeSize != 16 &&
+      TypeSize != 32 && TypeSize != 64 && TypeSize != 128) {
+    // Ignore all unusual sizes.
+    return;
+  }
+
+  IRBuilder<> IRB(I);
+  instrumentAddress(I, IRB, Addr, TypeSize, IsWrite);
+}
+
+Instruction *AddressSanitizer::generateCrashCode(
+    IRBuilder<> &IRB, Value *Addr, bool IsWrite, uint32_t TypeSize) {
+
+  if (ClUseCall) {
+    // Here we use a call instead of arch-specific asm to report an error.
+    // This is almost always slower (because the codegen needs to generate
+    // prologue/epilogue for otherwise leaf functions) and generates more code.
+    // This mode could be useful if we can not use SIGILL for some reason.
+    //
+    // IsWrite and TypeSize are encoded in the function name.
+    std::string FunctionName = std::string(kAsanReportErrorTemplate) +
+        (IsWrite ? "store" : "load") + itostr(TypeSize / 8);
+    Value *ReportWarningFunc = CurrentModule->getOrInsertFunction(
+        FunctionName, IRB.getVoidTy(), IntptrTy, NULL);
+    CallInst *Call = IRB.CreateCall(ReportWarningFunc, Addr);
+    Call->setDoesNotReturn();
+    return Call;
+  }
+
+  uint32_t LogOfSizeInBytes = CountTrailingZeros_32(TypeSize / 8);
+  assert(8U * (1 << LogOfSizeInBytes) == TypeSize);
+  uint8_t TelltaleValue = IsWrite * 8 + LogOfSizeInBytes;
+  assert(TelltaleValue < 16);
+
+  // Move the failing address to %rax/%eax
+  FunctionType *Fn1Ty = FunctionType::get(
+      IRB.getVoidTy(), ArrayRef<Type*>(IntptrTy), false);
+  const char *MovStr = LongSize == 32
+      ? "mov $0, %eax" : "mov $0, %rax";
+  Value *AsmMov = InlineAsm::get(
+      Fn1Ty, StringRef(MovStr), StringRef("r"), true);
+  IRB.CreateCall(AsmMov, Addr);
+
+  // crash with ud2; could use int3, but it is less friendly to gdb.
+  // after ud2 put a 1-byte instruction that encodes the access type and size.
+
+  const char *TelltaleInsns[16] = {
+    "push   %eax",  // 0x50
+    "push   %ecx",  // 0x51
+    "push   %edx",  // 0x52
+    "push   %ebx",  // 0x53
+    "push   %esp",  // 0x54
+    "push   %ebp",  // 0x55
+    "push   %esi",  // 0x56
+    "push   %edi",  // 0x57
+    "pop    %eax",  // 0x58
+    "pop    %ecx",  // 0x59
+    "pop    %edx",  // 0x5a
+    "pop    %ebx",  // 0x5b
+    "pop    %esp",  // 0x5c
+    "pop    %ebp",  // 0x5d
+    "pop    %esi",  // 0x5e
+    "pop    %edi"   // 0x5f
+  };
+
+  std::string AsmStr = "ud2;";
+  AsmStr += TelltaleInsns[TelltaleValue];
+  Value *MyAsm = InlineAsm::get(FunctionType::get(Type::getVoidTy(*C), false),
+                                StringRef(AsmStr), StringRef(""), true);
+  CallInst *AsmCall = IRB.CreateCall(MyAsm);
+
+  // This saves us one jump, but triggers a bug in RA (or somewhere else):
+  // while building 483.xalancbmk the compiler goes into infinite loop in
+  // llvm::SpillPlacement::iterate() / RAGreedy::growRegion
+  // AsmCall->setDoesNotReturn();
+  return AsmCall;
+}
+
+void AddressSanitizer::instrumentAddress(Instruction *OrigIns,
+                                         IRBuilder<> &IRB, Value *Addr,
+                                         uint32_t TypeSize, bool IsWrite) {
+  Value *AddrLong = IRB.CreatePointerCast(Addr, IntptrTy);
+
+  Type *ShadowTy  = IntegerType::get(
+      *C, std::max(8U, TypeSize >> MappingScale));
+  Type *ShadowPtrTy = PointerType::get(ShadowTy, 0);
+  Value *ShadowPtr = memToShadow(AddrLong, IRB);
+  Value *CmpVal = Constant::getNullValue(ShadowTy);
+  Value *ShadowValue = IRB.CreateLoad(
+      IRB.CreateIntToPtr(ShadowPtr, ShadowPtrTy));
+
+  Value *Cmp = IRB.CreateICmpNE(ShadowValue, CmpVal);
+
+  Instruction *CheckTerm = splitBlockAndInsertIfThen(
+      cast<Instruction>(Cmp)->getNextNode(), Cmp);
+  IRBuilder<> IRB2(CheckTerm);
+
+  size_t Granularity = 1 << MappingScale;
+  if (TypeSize < 8 * Granularity) {
+    // Addr & (Granularity - 1)
+    Value *Lower3Bits = IRB2.CreateAnd(
+        AddrLong, ConstantInt::get(IntptrTy, Granularity - 1));
+    // (Addr & (Granularity - 1)) + size - 1
+    Value *LastAccessedByte = IRB2.CreateAdd(
+        Lower3Bits, ConstantInt::get(IntptrTy, TypeSize / 8 - 1));
+    // (uint8_t) ((Addr & (Granularity-1)) + size - 1)
+    LastAccessedByte = IRB2.CreateIntCast(
+        LastAccessedByte, IRB.getInt8Ty(), false);
+    // ((uint8_t) ((Addr & (Granularity-1)) + size - 1)) >= ShadowValue
+    Value *Cmp2 = IRB2.CreateICmpSGE(LastAccessedByte, ShadowValue);
+
+    CheckTerm = splitBlockAndInsertIfThen(CheckTerm, Cmp2);
+  }
+
+  IRBuilder<> IRB1(CheckTerm);
+  Instruction *Crash = generateCrashCode(IRB1, AddrLong, IsWrite, TypeSize);
+  Crash->setDebugLoc(OrigIns->getDebugLoc());
+}
+
+// This function replaces all global variables with new variables that have
+// trailing redzones. It also creates a function that poisons
+// redzones and inserts this function into llvm.global_ctors.
+bool AddressSanitizer::insertGlobalRedzones(Module &M) {
+  SmallVector<GlobalVariable *, 16> GlobalsToChange;
+
+  for (Module::GlobalListType::iterator G = M.getGlobalList().begin(),
+       E = M.getGlobalList().end(); G != E; ++G) {
+    Type *Ty = cast<PointerType>(G->getType())->getElementType();
+    DEBUG(dbgs() << "GLOBAL: " << *G);
+
+    if (!Ty->isSized()) continue;
+    if (!G->hasInitializer()) continue;
+    if (GlobalVariable::mayBeOverridden(G->getLinkage()) ||
+        G->getLinkage() == GlobalVariable::AppendingLinkage)
+      continue;
+    // For now, just ignore this Alloca if the alignment is large.
+    if (G->getAlignment() > RedzoneSize) continue;
+
+    // Ignore all the globals with the names starting with "\01L_OBJC_".
+    // Many of those are put into the .cstring section. The linker compresses
+    // that section by removing the spare \0s after the string terminator, so
+    // our redzones get broken.
+    if ((G->getName().find("\01L_OBJC_") == 0) ||
+        (G->getName().find("\01l_OBJC_") == 0)) {
+      DEBUG(dbgs() << "Ignoring \\01L_OBJC_* global: " << *G);
+      continue;
+    }
+
+    // Ignore the globals from the __OBJC section. The ObjC runtime assumes
+    // those conform to /usr/lib/objc/runtime.h, so we can't add redzones to
+    // them.
+    if (G->hasSection()) {
+      StringRef Section(G->getSection());
+      if ((Section.find("__OBJC,") == 0) ||
+          (Section.find("__DATA, __objc_") == 0)) {
+        DEBUG(dbgs() << "Ignoring ObjC runtime global: " << *G);
+        continue;
+      }
+    }
+
+    GlobalsToChange.push_back(G);
+  }
+
+  size_t n = GlobalsToChange.size();
+  if (n == 0) return false;
+
+  // A global is described by a structure
+  //   size_t beg;
+  //   size_t size;
+  //   size_t size_with_redzone;
+  //   const char *name;
+  // We initialize an array of such structures and pass it to a run-time call.
+  StructType *GlobalStructTy = StructType::get(IntptrTy, IntptrTy,
+                                               IntptrTy, IntptrTy, NULL);
+  SmallVector<Constant *, 16> Initializers(n);
+
+  IRBuilder<> IRB(CtorInsertBefore);
+
+  for (size_t i = 0; i < n; i++) {
+    GlobalVariable *G = GlobalsToChange[i];
+    PointerType *PtrTy = cast<PointerType>(G->getType());
+    Type *Ty = PtrTy->getElementType();
+    uint64_t SizeInBytes = TD->getTypeStoreSizeInBits(Ty) / 8;
+    uint64_t RightRedzoneSize = RedzoneSize +
+        (RedzoneSize - (SizeInBytes % RedzoneSize));
+    Type *RightRedZoneTy = ArrayType::get(IRB.getInt8Ty(), RightRedzoneSize);
+
+    StructType *NewTy = StructType::get(Ty, RightRedZoneTy, NULL);
+    Constant *NewInitializer = ConstantStruct::get(
+        NewTy, G->getInitializer(),
+        Constant::getNullValue(RightRedZoneTy), NULL);
+
+    GlobalVariable *Name = createPrivateGlobalForString(M, G->getName());
+
+    // Create a new global variable with enough space for a redzone.
+    GlobalVariable *NewGlobal = new GlobalVariable(
+        M, NewTy, G->isConstant(), G->getLinkage(),
+        NewInitializer, "", G, G->isThreadLocal());
+    NewGlobal->copyAttributesFrom(G);
+    NewGlobal->setAlignment(RedzoneSize);
+
+    Value *Indices2[2];
+    Indices2[0] = IRB.getInt32(0);
+    Indices2[1] = IRB.getInt32(0);
+
+    G->replaceAllUsesWith(
+        ConstantExpr::getGetElementPtr(NewGlobal, Indices2, 2));
+    NewGlobal->takeName(G);
+    G->eraseFromParent();
+
+    Initializers[i] = ConstantStruct::get(
+        GlobalStructTy,
+        ConstantExpr::getPointerCast(NewGlobal, IntptrTy),
+        ConstantInt::get(IntptrTy, SizeInBytes),
+        ConstantInt::get(IntptrTy, SizeInBytes + RightRedzoneSize),
+        ConstantExpr::getPointerCast(Name, IntptrTy),
+        NULL);
+    DEBUG(dbgs() << "NEW GLOBAL:\n" << *NewGlobal);
+  }
+
+  ArrayType *ArrayOfGlobalStructTy = ArrayType::get(GlobalStructTy, n);
+  GlobalVariable *AllGlobals = new GlobalVariable(
+      M, ArrayOfGlobalStructTy, false, GlobalVariable::PrivateLinkage,
+      ConstantArray::get(ArrayOfGlobalStructTy, Initializers), "");
+
+  Function *AsanRegisterGlobals = cast<Function>(M.getOrInsertFunction(
+      kAsanRegisterGlobalsName, IRB.getVoidTy(), IntptrTy, IntptrTy, NULL));
+  AsanRegisterGlobals->setLinkage(Function::ExternalLinkage);
+
+  IRB.CreateCall2(AsanRegisterGlobals,
+                  IRB.CreatePointerCast(AllGlobals, IntptrTy),
+                  ConstantInt::get(IntptrTy, n));
+
+  DEBUG(dbgs() << M);
+  return true;
+}
+
+// virtual
+bool AddressSanitizer::runOnModule(Module &M) {
+  // Initialize the private fields. No one has accessed them before.
+  TD = getAnalysisIfAvailable<TargetData>();
+  if (!TD)
+    return false;
+  BL.reset(new BlackList(ClBlackListFile));
+
+  CurrentModule = &M;
+  C = &(M.getContext());
+  LongSize = TD->getPointerSizeInBits();
+  IntptrTy = Type::getIntNTy(*C, LongSize);
+  IntptrPtrTy = PointerType::get(IntptrTy, 0);
+
+  AsanCtorFunction = Function::Create(
+      FunctionType::get(Type::getVoidTy(*C), false),
+      GlobalValue::InternalLinkage, kAsanModuleCtorName, &M);
+  BasicBlock *AsanCtorBB = BasicBlock::Create(*C, "", AsanCtorFunction);
+  CtorInsertBefore = ReturnInst::Create(*C, AsanCtorBB);
+
+  // call __asan_init in the module ctor.
+  IRBuilder<> IRB(CtorInsertBefore);
+  AsanInitFunction = cast<Function>(
+      M.getOrInsertFunction(kAsanInitName, IRB.getVoidTy(), NULL));
+  AsanInitFunction->setLinkage(Function::ExternalLinkage);
+  IRB.CreateCall(AsanInitFunction);
+
+  MappingOffset = LongSize == 32
+      ? kDefaultShadowOffset32 : kDefaultShadowOffset64;
+  if (ClMappingOffsetLog >= 0) {
+    if (ClMappingOffsetLog == 0) {
+      // special case
+      MappingOffset = 0;
+    } else {
+      MappingOffset = 1ULL << ClMappingOffsetLog;
+    }
+  }
+  MappingScale = kDefaultShadowScale;
+  if (ClMappingScale) {
+    MappingScale = ClMappingScale;
+  }
+  // Redzone used for stack and globals is at least 32 bytes.
+  // For scales 6 and 7, the redzone has to be 64 and 128 bytes respectively.
+  RedzoneSize = std::max(32, (int)(1 << MappingScale));
+
+  bool Res = false;
+
+  if (ClGlobals)
+    Res |= insertGlobalRedzones(M);
+
+  // Tell the run-time the current values of mapping offset and scale.
+  GlobalValue *asan_mapping_offset =
+      new GlobalVariable(M, IntptrTy, true, GlobalValue::LinkOnceODRLinkage,
+                     ConstantInt::get(IntptrTy, MappingOffset),
+                     kAsanMappingOffsetName);
+  GlobalValue *asan_mapping_scale =
+      new GlobalVariable(M, IntptrTy, true, GlobalValue::LinkOnceODRLinkage,
+                         ConstantInt::get(IntptrTy, MappingScale),
+                         kAsanMappingScaleName);
+  // Read these globals, otherwise they may be optimized away.
+  IRB.CreateLoad(asan_mapping_scale, true);
+  IRB.CreateLoad(asan_mapping_offset, true);
+
+
+  for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
+    if (F->isDeclaration()) continue;
+    Res |= handleFunction(M, *F);
+  }
+
+  appendToGlobalCtors(M, AsanCtorFunction, 1 /*high priority*/);
+
+  return Res;
+}
+
+bool AddressSanitizer::handleFunction(Module &M, Function &F) {
+  if (BL->isIn(F)) return false;
+  if (&F == AsanCtorFunction) return false;
+
+  if (!ClDebugFunc.empty() && ClDebugFunc != F.getName())
+    return false;
+  // We want to instrument every address only once per basic block
+  // (unless there are calls between uses).
+  SmallSet<Value*, 16> TempsToInstrument;
+  SmallVector<Instruction*, 16> ToInstrument;
+
+  // Fill the set of memory operations to instrument.
+  for (Function::iterator FI = F.begin(), FE = F.end();
+       FI != FE; ++FI) {
+    TempsToInstrument.clear();
+    for (BasicBlock::iterator BI = FI->begin(), BE = FI->end();
+         BI != BE; ++BI) {
+      if ((isa<LoadInst>(BI) && ClInstrumentReads) ||
+          (isa<StoreInst>(BI) && ClInstrumentWrites)) {
+        Value *Addr = getLDSTOperand(BI);
+        if (ClOpt && ClOptSameTemp) {
+          if (!TempsToInstrument.insert(Addr))
+            continue;  // We've seen this temp in the current BB.
+        }
+      } else if (isa<MemIntrinsic>(BI) && ClMemIntrin) {
+        // ok, take it.
+      } else {
+        if (isa<CallInst>(BI)) {
+          // A call inside BB.
+          TempsToInstrument.clear();
+        }
+        continue;
+      }
+      ToInstrument.push_back(BI);
+    }
+  }
+
+  // Instrument.
+  int NumInstrumented = 0;
+  for (size_t i = 0, n = ToInstrument.size(); i != n; i++) {
+    Instruction *Inst = ToInstrument[i];
+    if (ClDebugMin < 0 || ClDebugMax < 0 ||
+        (NumInstrumented >= ClDebugMin && NumInstrumented <= ClDebugMax)) {
+      if (isa<StoreInst>(Inst) || isa<LoadInst>(Inst))
+        instrumentMop(Inst);
+      else
+        instrumentMemIntrinsic(cast<MemIntrinsic>(Inst));
+    }
+    NumInstrumented++;
+  }
+
+  DEBUG(dbgs() << F);
+
+  bool ChangedStack = poisonStackInFunction(M, F);
+
+  // For each NSObject descendant having a +load method, this method is invoked
+  // by the ObjC runtime before any of the static constructors is called.
+  // Therefore we need to instrument such methods with a call to __asan_init
+  // at the beginning in order to initialize our runtime before any access to
+  // the shadow memory.
+  // We cannot just ignore these methods, because they may call other
+  // instrumented functions.
+  if (F.getName().find(" load]") != std::string::npos) {
+    IRBuilder<> IRB(F.begin()->begin());
+    IRB.CreateCall(AsanInitFunction);
+  }
+
+  return NumInstrumented > 0 || ChangedStack;
+}
+
+static uint64_t ValueForPoison(uint64_t PoisonByte, size_t ShadowRedzoneSize) {
+  if (ShadowRedzoneSize == 1) return PoisonByte;
+  if (ShadowRedzoneSize == 2) return (PoisonByte << 8) + PoisonByte;
+  if (ShadowRedzoneSize == 4)
+    return (PoisonByte << 24) + (PoisonByte << 16) +
+        (PoisonByte << 8) + (PoisonByte);
+  assert(0 && "ShadowRedzoneSize is either 1, 2 or 4");
+  return 0;
+}
+
+static void PoisonShadowPartialRightRedzone(uint8_t *Shadow,
+                                            size_t Size,
+                                            size_t RedzoneSize,
+                                            size_t ShadowGranularity,
+                                            uint8_t Magic) {
+  for (size_t i = 0; i < RedzoneSize;
+       i+= ShadowGranularity, Shadow++) {
+    if (i + ShadowGranularity <= Size) {
+      *Shadow = 0;  // fully addressable
+    } else if (i >= Size) {
+      *Shadow = Magic;  // unaddressable
+    } else {
+      *Shadow = Size - i;  // first Size-i bytes are addressable
+    }
+  }
+}
+
+void AddressSanitizer::PoisonStack(const ArrayRef<AllocaInst*> &AllocaVec,
+                                   IRBuilder<> IRB,
+                                   Value *ShadowBase, bool DoPoison) {
+  size_t ShadowRZSize = RedzoneSize >> MappingScale;
+  assert(ShadowRZSize >= 1 && ShadowRZSize <= 4);
+  Type *RZTy = Type::getIntNTy(*C, ShadowRZSize * 8);
+  Type *RZPtrTy = PointerType::get(RZTy, 0);
+
+  Value *PoisonLeft  = ConstantInt::get(RZTy,
+    ValueForPoison(DoPoison ? kAsanStackLeftRedzoneMagic : 0LL, ShadowRZSize));
+  Value *PoisonMid   = ConstantInt::get(RZTy,
+    ValueForPoison(DoPoison ? kAsanStackMidRedzoneMagic : 0LL, ShadowRZSize));
+  Value *PoisonRight = ConstantInt::get(RZTy,
+    ValueForPoison(DoPoison ? kAsanStackRightRedzoneMagic : 0LL, ShadowRZSize));
+
+  // poison the first red zone.
+  IRB.CreateStore(PoisonLeft, IRB.CreateIntToPtr(ShadowBase, RZPtrTy));
+
+  // poison all other red zones.
+  uint64_t Pos = RedzoneSize;
+  for (size_t i = 0, n = AllocaVec.size(); i < n; i++) {
+    AllocaInst *AI = AllocaVec[i];
+    uint64_t SizeInBytes = getAllocaSizeInBytes(AI);
+    uint64_t AlignedSize = getAlignedAllocaSize(AI);
+    assert(AlignedSize - SizeInBytes < RedzoneSize);
+    Value *Ptr = NULL;
+
+    Pos += AlignedSize;
+
+    assert(ShadowBase->getType() == IntptrTy);
+    if (SizeInBytes < AlignedSize) {
+      // Poison the partial redzone at right
+      Ptr = IRB.CreateAdd(
+          ShadowBase, ConstantInt::get(IntptrTy,
+                                       (Pos >> MappingScale) - ShadowRZSize));
+      size_t AddressableBytes = RedzoneSize - (AlignedSize - SizeInBytes);
+      uint32_t Poison = 0;
+      if (DoPoison) {
+        PoisonShadowPartialRightRedzone((uint8_t*)&Poison, AddressableBytes,
+                                        RedzoneSize,
+                                        1ULL << MappingScale,
+                                        kAsanStackPartialRedzoneMagic);
+      }
+      Value *PartialPoison = ConstantInt::get(RZTy, Poison);
+      IRB.CreateStore(PartialPoison, IRB.CreateIntToPtr(Ptr, RZPtrTy));
+    }
+
+    // Poison the full redzone at right.
+    Ptr = IRB.CreateAdd(ShadowBase,
+                        ConstantInt::get(IntptrTy, Pos >> MappingScale));
+    Value *Poison = i == AllocaVec.size() - 1 ? PoisonRight : PoisonMid;
+    IRB.CreateStore(Poison, IRB.CreateIntToPtr(Ptr, RZPtrTy));
+
+    Pos += RedzoneSize;
+  }
+}
+
+// Find all static Alloca instructions and put
+// poisoned red zones around all of them.
+// Then unpoison everything back before the function returns.
+//
+// Stack poisoning does not play well with exception handling.
+// When an exception is thrown, we essentially bypass the code
+// that unpoisones the stack. This is why the run-time library has
+// to intercept __cxa_throw (as well as longjmp, etc) and unpoison the entire
+// stack in the interceptor. This however does not work inside the
+// actual function which catches the exception. Most likely because the
+// compiler hoists the load of the shadow value somewhere too high.
+// This causes asan to report a non-existing bug on 453.povray.
+// It sounds like an LLVM bug.
+bool AddressSanitizer::poisonStackInFunction(Module &M, Function &F) {
+  if (!ClStack) return false;
+  SmallVector<AllocaInst*, 16> AllocaVec;
+  SmallVector<Instruction*, 8> RetVec;
+  uint64_t TotalSize = 0;
+
+  // Filter out Alloca instructions we want (and can) handle.
+  // Collect Ret instructions.
+  for (Function::iterator FI = F.begin(), FE = F.end();
+       FI != FE; ++FI) {
+    BasicBlock &BB = *FI;
+    for (BasicBlock::iterator BI = BB.begin(), BE = BB.end();
+         BI != BE; ++BI) {
+      if (isa<ReturnInst>(BI)) {
+          RetVec.push_back(BI);
+          continue;
+      }
+
+      AllocaInst *AI = dyn_cast<AllocaInst>(BI);
+      if (!AI) continue;
+      if (AI->isArrayAllocation()) continue;
+      if (!AI->isStaticAlloca()) continue;
+      if (!AI->getAllocatedType()->isSized()) continue;
+      if (AI->getAlignment() > RedzoneSize) continue;
+      AllocaVec.push_back(AI);
+      uint64_t AlignedSize =  getAlignedAllocaSize(AI);
+      TotalSize += AlignedSize;
+    }
+  }
+
+  if (AllocaVec.empty()) return false;
+
+  uint64_t LocalStackSize = TotalSize + (AllocaVec.size() + 1) * RedzoneSize;
+
+  bool DoStackMalloc = ClUseAfterReturn
+      && LocalStackSize <= kMaxStackMallocSize;
+
+  Instruction *InsBefore = AllocaVec[0];
+  IRBuilder<> IRB(InsBefore);
+
+
+  Type *ByteArrayTy = ArrayType::get(IRB.getInt8Ty(), LocalStackSize);
+  AllocaInst *MyAlloca =
+      new AllocaInst(ByteArrayTy, "MyAlloca", InsBefore);
+  MyAlloca->setAlignment(RedzoneSize);
+  assert(MyAlloca->isStaticAlloca());
+  Value *OrigStackBase = IRB.CreatePointerCast(MyAlloca, IntptrTy);
+  Value *LocalStackBase = OrigStackBase;
+
+  if (DoStackMalloc) {
+    Value *AsanStackMallocFunc = M.getOrInsertFunction(
+        kAsanStackMallocName, IntptrTy, IntptrTy, IntptrTy, NULL);
+    LocalStackBase = IRB.CreateCall2(AsanStackMallocFunc,
+        ConstantInt::get(IntptrTy, LocalStackSize), OrigStackBase);
+  }
+
+  // This string will be parsed by the run-time (DescribeStackAddress).
+  SmallString<2048> StackDescriptionStorage;
+  raw_svector_ostream StackDescription(StackDescriptionStorage);
+  StackDescription << F.getName() << " " << AllocaVec.size() << " ";
+
+  uint64_t Pos = RedzoneSize;
+  // Replace Alloca instructions with base+offset.
+  for (size_t i = 0, n = AllocaVec.size(); i < n; i++) {
+    AllocaInst *AI = AllocaVec[i];
+    uint64_t SizeInBytes = getAllocaSizeInBytes(AI);
+    StringRef Name = AI->getName();
+    StackDescription << Pos << " " << SizeInBytes << " "
+                     << Name.size() << " " << Name << " ";
+    uint64_t AlignedSize = getAlignedAllocaSize(AI);
+    assert((AlignedSize % RedzoneSize) == 0);
+    AI->replaceAllUsesWith(
+        IRB.CreateIntToPtr(
+            IRB.CreateAdd(LocalStackBase, ConstantInt::get(IntptrTy, Pos)),
+            AI->getType()));
+    Pos += AlignedSize + RedzoneSize;
+  }
+  assert(Pos == LocalStackSize);
+
+  // Write the Magic value and the frame description constant to the redzone.
+  Value *BasePlus0 = IRB.CreateIntToPtr(LocalStackBase, IntptrPtrTy);
+  IRB.CreateStore(ConstantInt::get(IntptrTy, kCurrentStackFrameMagic),
+                  BasePlus0);
+  Value *BasePlus1 = IRB.CreateAdd(LocalStackBase,
+                                   ConstantInt::get(IntptrTy, LongSize/8));
+  BasePlus1 = IRB.CreateIntToPtr(BasePlus1, IntptrPtrTy);
+  Value *Description = IRB.CreatePointerCast(
+      createPrivateGlobalForString(M, StackDescription.str()),
+      IntptrTy);
+  IRB.CreateStore(Description, BasePlus1);
+
+  // Poison the stack redzones at the entry.
+  Value *ShadowBase = memToShadow(LocalStackBase, IRB);
+  PoisonStack(ArrayRef<AllocaInst*>(AllocaVec), IRB, ShadowBase, true);
+
+  Value *AsanStackFreeFunc = NULL;
+  if (DoStackMalloc) {
+    AsanStackFreeFunc = M.getOrInsertFunction(
+        kAsanStackFreeName, IRB.getVoidTy(),
+        IntptrTy, IntptrTy, IntptrTy, NULL);
+  }
+
+  // Unpoison the stack before all ret instructions.
+  for (size_t i = 0, n = RetVec.size(); i < n; i++) {
+    Instruction *Ret = RetVec[i];
+    IRBuilder<> IRBRet(Ret);
+
+    // Mark the current frame as retired.
+    IRBRet.CreateStore(ConstantInt::get(IntptrTy, kRetiredStackFrameMagic),
+                       BasePlus0);
+    // Unpoison the stack.
+    PoisonStack(ArrayRef<AllocaInst*>(AllocaVec), IRBRet, ShadowBase, false);
+
+    if (DoStackMalloc) {
+      IRBRet.CreateCall3(AsanStackFreeFunc, LocalStackBase,
+                         ConstantInt::get(IntptrTy, LocalStackSize),
+                         OrigStackBase);
+    }
+  }
+
+  if (ClDebugStack) {
+    DEBUG(dbgs() << F);
+  }
+
+  return true;
+}
+
+BlackList::BlackList(const std::string &Path) {
+  Functions = NULL;
+  const char *kFunPrefix = "fun:";
+  if (!ClBlackListFile.size()) return;
+  std::string Fun;
+
+  OwningPtr<MemoryBuffer> File;
+  if (error_code EC = MemoryBuffer::getFile(ClBlackListFile.c_str(), File)) {
+    errs() << EC.message();
+    exit(1);
+  }
+  MemoryBuffer *Buff = File.take();
+  const char *Data = Buff->getBufferStart();
+  size_t DataLen = Buff->getBufferSize();
+  SmallVector<StringRef, 16> Lines;
+  SplitString(StringRef(Data, DataLen), Lines, "\n\r");
+  for (size_t i = 0, numLines = Lines.size(); i < numLines; i++) {
+    if (Lines[i].startswith(kFunPrefix)) {
+      std::string ThisFunc = Lines[i].substr(strlen(kFunPrefix));
+      if (Fun.size()) {
+        Fun += "|";
+      }
+      // add ThisFunc replacing * with .*
+      for (size_t j = 0, n = ThisFunc.size(); j < n; j++) {
+        if (ThisFunc[j] == '*')
+          Fun += '.';
+        Fun += ThisFunc[j];
+      }
+    }
+  }
+  if (Fun.size()) {
+    Functions = new Regex(Fun);
+  }
+}
+
+bool BlackList::isIn(const Function &F) {
+  if (Functions) {
+    bool Res = Functions->match(F.getName());
+    return Res;
+  }
+  return false;
+}

Modified: llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt?rev=144758&r1=144757&r2=144758&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt Tue Nov 15 19:35:23 2011
@@ -1,4 +1,5 @@
 add_llvm_library(LLVMInstrumentation
+  AddressSanitizer.cpp
   EdgeProfiling.cpp
   GCOVProfiling.cpp
   Instrumentation.cpp

Modified: llvm/trunk/lib/Transforms/Instrumentation/Instrumentation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/Instrumentation.cpp?rev=144758&r1=144757&r2=144758&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/Instrumentation.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/Instrumentation.cpp Tue Nov 15 19:35:23 2011
@@ -24,6 +24,7 @@
   initializeOptimalEdgeProfilerPass(Registry);
   initializePathProfilerPass(Registry);
   initializeGCOVProfilerPass(Registry);
+  initializeAddressSanitizerPass(Registry);
 }
 
 /// LLVMInitializeInstrumentation - C binding for

Added: llvm/trunk/test/Instrumentation/AddressSanitizer/dg.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Instrumentation/AddressSanitizer/dg.exp?rev=144758&view=auto
==============================================================================
--- llvm/trunk/test/Instrumentation/AddressSanitizer/dg.exp (added)
+++ llvm/trunk/test/Instrumentation/AddressSanitizer/dg.exp Tue Nov 15 19:35:23 2011
@@ -0,0 +1,3 @@
+load_lib llvm.exp
+
+RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]

Added: llvm/trunk/test/Instrumentation/AddressSanitizer/test64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Instrumentation/AddressSanitizer/test64.ll?rev=144758&view=auto
==============================================================================
--- llvm/trunk/test/Instrumentation/AddressSanitizer/test64.ll (added)
+++ llvm/trunk/test/Instrumentation/AddressSanitizer/test64.ll Tue Nov 15 19:35:23 2011
@@ -0,0 +1,14 @@
+; RUN: opt < %s -asan -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+define i32 @read_4_bytes(i32* %a) {
+entry:
+  %tmp1 = load i32* %a, align 4
+  ret i32 %tmp1
+}
+; CHECK: @read_4_bytes
+; CHECK-NOT: ret
+; CHECK: lshr {{.*}} 3
+; Check for ASAN's Offset for 64-bit (2^44)
+; CHECK-NEXT: 17592186044416
+; CHECK: ret



From bigcheesegs at gmail.com  Tue Nov 15 19:36:51 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Wed, 16 Nov 2011 01:36:51 -0000
Subject: [llvm-commits] [llvm] r144759 -
	/llvm/trunk/include/llvm/Support/COFF.h
Message-ID: <20111116013651.25B062A6C133@llvm.org>

Author: mspencer
Date: Tue Nov 15 19:36:50 2011
New Revision: 144759

URL: http://llvm.org/viewvc/llvm-project?rev=144759&view=rev
Log:
Remove extra ,.

Modified:
    llvm/trunk/include/llvm/Support/COFF.h

Modified: llvm/trunk/include/llvm/Support/COFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/COFF.h?rev=144759&r1=144758&r2=144759&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/COFF.h (original)
+++ llvm/trunk/include/llvm/Support/COFF.h Tue Nov 15 19:36:50 2011
@@ -558,7 +558,7 @@
     IMPORT_NAME_NOPREFIX   = 2,
     /// The import name is the public symbol name, but skipping the leading ?,
     /// @, or optionally _, and truncating at the first @.
-    IMPORT_NAME_UNDECORATE = 3,
+    IMPORT_NAME_UNDECORATE = 3
   };
 
   struct ImportHeader {



From eli.friedman at gmail.com  Tue Nov 15 20:43:16 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 16 Nov 2011 02:43:16 -0000
Subject: [llvm-commits] [llvm] r144767 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Message-ID: <20111116024316.13B182A6C133@llvm.org>

Author: efriedma
Date: Tue Nov 15 20:43:15 2011
New Revision: 144767

URL: http://llvm.org/viewvc/llvm-project?rev=144767&view=rev
Log:
Add a couple asserts so it will be easier to debug if we accidentally pass indexed loads/stores to the legalizer.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=144767&r1=144766&r2=144767&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Nov 15 20:43:15 2011
@@ -293,6 +293,8 @@
 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
                                  const TargetLowering &TLI,
                                  SelectionDAGLegalize *DAGLegalize) {
+  assert(ST->getAddressingMode() == ISD::UNINDEXED &&
+         "unaligned indexed stores not implemented!");
   SDValue Chain = ST->getChain();
   SDValue Ptr = ST->getBasePtr();
   SDValue Val = ST->getValue();
@@ -413,6 +415,8 @@
 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
                     const TargetLowering &TLI,
                     SDValue &ValResult, SDValue &ChainResult) {
+  assert(LD->getAddressingMode() == ISD::UNINDEXED &&
+         "unaligned indexed loads not implemented!");
   SDValue Chain = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
   EVT VT = LD->getValueType(0);



From eli.friedman at gmail.com  Tue Nov 15 20:52:39 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 16 Nov 2011 02:52:39 -0000
Subject: [llvm-commits] [llvm] r144768 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
 test/CodeGen/X86/widen_shuffle-1.ll
Message-ID: <20111116025239.AD4972A6C133@llvm.org>

Author: efriedma
Date: Tue Nov 15 20:52:39 2011
New Revision: 144768

URL: http://llvm.org/viewvc/llvm-project?rev=144768&view=rev
Log:
CONCAT_VECTORS can have more than two operands.  PR11389.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=144768&r1=144767&r2=144768&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Nov 15 20:52:39 2011
@@ -2926,38 +2926,28 @@
 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
   DebugLoc dl = N->getDebugLoc();
 
-  SDValue Op0 = N->getOperand(0);
-  SDValue Op1 = N->getOperand(1);
-  assert(Op0.getValueType() == Op1.getValueType() &&
-         "Invalid input vector types");
-
   EVT OutVT = N->getValueType(0);
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
   assert(NOutVT.isVector() && "This type must be promoted to a vector type");
 
+  EVT InElemTy = OutVT.getVectorElementType();
   EVT OutElemTy = NOutVT.getVectorElementType();
 
-  unsigned NumElem0 = Op0.getValueType().getVectorNumElements();
-  unsigned NumElem1 = Op1.getValueType().getVectorNumElements();
+  unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
   unsigned NumOutElem = NOutVT.getVectorNumElements();
-  assert(NumElem0 + NumElem1 == NumOutElem &&
-         "Invalid number of incoming elements");
+  unsigned NumOperands = N->getNumOperands();
+  assert(NumElem * NumOperands == NumOutElem &&
+         "Unexpected number of elements");
 
   // Take the elements from the first vector.
   SmallVector<SDValue, 8> Ops(NumOutElem);
-  for (unsigned i = 0; i < NumElem0; ++i) {
-    SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
-                              Op0.getValueType().getScalarType(), Op0,
-                              DAG.getIntPtrConstant(i));
-    Ops[i] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
-  }
-
-  // Take the elements from the second vector
-  for (unsigned i = 0; i < NumElem1; ++i) {
-    SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
-                              Op1.getValueType().getScalarType(), Op1,
-                              DAG.getIntPtrConstant(i));
-    Ops[i + NumElem0] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
+  for (unsigned i = 0; i < NumOperands; ++i) {
+    SDValue Op = N->getOperand(i);
+    for (unsigned j = 0; j < NumElem; ++j) {
+      SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+                                InElemTy, Op, DAG.getIntPtrConstant(j));
+      Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
+    }
   }
 
   return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());

Modified: llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll?rev=144768&r1=144767&r2=144768&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll Tue Nov 15 20:52:39 2011
@@ -54,3 +54,12 @@
   %vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i8> %vshuf
 }
+
+; PR11389: another CONCAT_VECTORS case
+define void @shuf5(<8 x i8>* %p) nounwind {
+; CHECK: shuf5:
+; CHECK-NOT: punpcklwd
+  %v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  store <8 x i8> %v, <8 x i8>* %p, align 8
+  ret void
+}



From eli.friedman at gmail.com  Tue Nov 15 21:03:52 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 16 Nov 2011 03:03:52 -0000
Subject: [llvm-commits] [llvm] r144769 -
	/llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll
Message-ID: <20111116030352.464E52A6C133@llvm.org>

Author: efriedma
Date: Tue Nov 15 21:03:52 2011
New Revision: 144769

URL: http://llvm.org/viewvc/llvm-project?rev=144769&view=rev
Log:
Fix testcase.


Modified:
    llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll

Modified: llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll?rev=144769&r1=144768&r2=144769&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll Tue Nov 15 21:03:52 2011
@@ -58,7 +58,6 @@
 ; PR11389: another CONCAT_VECTORS case
 define void @shuf5(<8 x i8>* %p) nounwind {
 ; CHECK: shuf5:
-; CHECK-NOT: punpcklwd
   %v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   store <8 x i8> %v, <8 x i8>* %p, align 8
   ret void



From evan.cheng at apple.com  Tue Nov 15 21:05:12 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 16 Nov 2011 03:05:12 -0000
Subject: [llvm-commits] [llvm] r144770 -
	/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
Message-ID: <20111116030512.A6F692A6C133@llvm.org>

Author: evancheng
Date: Tue Nov 15 21:05:12 2011
New Revision: 144770

URL: http://llvm.org/viewvc/llvm-project?rev=144770&view=rev
Log:
Process all uses first before defs to accurately capture register liveness. rdar://10449480

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=144770&r1=144769&r2=144770&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Nov 15 21:05:12 2011
@@ -1115,6 +1115,7 @@
         MCID.isTerminator())
       // Don't move pass calls, etc.
       return false;
+    SmallVector<unsigned, 2> OtherDefs;
     for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
       const MachineOperand &MO = OtherMI->getOperand(i);
       if (!MO.isReg())
@@ -1131,15 +1132,20 @@
           // Don't want to extend other live ranges and update kills.
           return false;
       } else {
-        if (Uses.count(MOReg))
-          return false;
-        if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
-            LiveDefs.count(MOReg))
-          return false;
-        // Physical register def is seen.
-        Defs.erase(MOReg);
+        OtherDefs.push_back(MOReg);
       }
     }
+
+    for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
+      unsigned MOReg = OtherDefs[i];
+      if (Uses.count(MOReg))
+        return false;
+      if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
+          LiveDefs.count(MOReg))
+        return false;
+      // Physical register def is seen.
+      Defs.erase(MOReg);
+    }
   }
 
   // Move the old kill above MI, don't forget to move debug info as well.



From evan.cheng at apple.com  Tue Nov 15 21:33:08 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 16 Nov 2011 03:33:08 -0000
Subject: [llvm-commits] [llvm] r144771 -
	/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
Message-ID: <20111116033308.A065D2A6C133@llvm.org>

Author: evancheng
Date: Tue Nov 15 21:33:08 2011
New Revision: 144771

URL: http://llvm.org/viewvc/llvm-project?rev=144771&view=rev
Log:
RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE instructions. rdar://10451185

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=144771&r1=144770&r2=144771&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Nov 15 21:33:08 2011
@@ -1158,7 +1158,7 @@
     --From;
   MBB->splice(InsertPos, MBB, From, To);
 
-  nmi = llvm::prior(mi); // Backtrack so we process the moved instruction.
+  nmi = llvm::prior(InsertPos); // Backtrack so we process the moved instr.
   DistanceMap.erase(DI);
 
   if (LV) {



From evan.cheng at apple.com  Tue Nov 15 21:47:42 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 16 Nov 2011 03:47:42 -0000
Subject: [llvm-commits] [llvm] r144772 -
	/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
Message-ID: <20111116034742.A85DB2A6C133@llvm.org>

Author: evancheng
Date: Tue Nov 15 21:47:42 2011
New Revision: 144772

URL: http://llvm.org/viewvc/llvm-project?rev=144772&view=rev
Log:
If the 2addr instruction has other kills, don't move it below any other uses since we don't want to extend other live ranges.

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=144772&r1=144771&r2=144772&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Nov 15 21:47:42 2011
@@ -933,6 +933,7 @@
     return false;
 
   SmallSet<unsigned, 2> Uses;
+  SmallSet<unsigned, 2> Kills;
   SmallSet<unsigned, 2> Defs;
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
@@ -943,8 +944,11 @@
       continue;
     if (MO.isDef())
       Defs.insert(MOReg);
-    else
+    else {
       Uses.insert(MOReg);
+      if (MO.isKill() && MOReg != Reg)
+        Kills.insert(MOReg);
+    }
   }
 
   // Move the copies connected to MI down as well.
@@ -991,7 +995,8 @@
       } else {
         if (Defs.count(MOReg))
           return false;
-        if (MOReg != Reg && MO.isKill() && Uses.count(MOReg))
+        if (MOReg != Reg &&
+            ((MO.isKill() && Uses.count(MOReg)) || Kills.count(MOReg)))
           // Don't want to extend other live ranges and update kills.
           return false;
       }



From nicholas at mxc.ca  Tue Nov 15 21:49:48 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 16 Nov 2011 03:49:48 -0000
Subject: [llvm-commits] [llvm] r144773 - in /llvm/trunk:
 lib/Transforms/Scalar/DeadStoreElimination.cpp
 test/Transforms/DeadStoreElimination/pr11390.ll
Message-ID: <20111116034948.D68E02A6C133@llvm.org>

Author: nicholas
Date: Tue Nov 15 21:49:48 2011
New Revision: 144773

URL: http://llvm.org/viewvc/llvm-project?rev=144773&view=rev
Log:
Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it when
looking at the size of the pointee. Fixes PR11390!

Added:
    llvm/trunk/test/Transforms/DeadStoreElimination/pr11390.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=144773&r1=144772&r2=144773&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Tue Nov 15 21:49:48 2011
@@ -274,43 +274,35 @@
   }
 }
 
-static uint64_t getPointerSize(Value *V, AliasAnalysis &AA) {
+static uint64_t getPointerSize(const Value *V, AliasAnalysis &AA) {
   const TargetData *TD = AA.getTargetData();
 
-  if (CallInst *CI = dyn_cast<CallInst>(V)) {
-    assert(isMalloc(CI) && "Expected Malloc call!");
-    if (ConstantInt *C = dyn_cast<ConstantInt>(CI->getArgOperand(0)))
+  if (const CallInst *CI = extractMallocCall(V)) {
+    if (const ConstantInt *C = dyn_cast<ConstantInt>(CI->getArgOperand(0)))
       return C->getZExtValue();
-    return AliasAnalysis::UnknownSize;
   }
 
   if (TD == 0)
     return AliasAnalysis::UnknownSize;
 
-  if (AllocaInst *A = dyn_cast<AllocaInst>(V)) {
+  if (const AllocaInst *A = dyn_cast<AllocaInst>(V)) {
     // Get size information for the alloca
-    if (ConstantInt *C = dyn_cast<ConstantInt>(A->getArraySize()))
+    if (const ConstantInt *C = dyn_cast<ConstantInt>(A->getArraySize()))
       return C->getZExtValue() * TD->getTypeAllocSize(A->getAllocatedType());
-    return AliasAnalysis::UnknownSize;
   }
 
-  assert(isa<Argument>(V) && "Expected AllocaInst, malloc call or Argument!");
-  PointerType *PT = cast<PointerType>(V->getType());
-  return TD->getTypeAllocSize(PT->getElementType());
-}
+  if (const Argument *A = dyn_cast<Argument>(V)) {
+    if (A->hasByValAttr())
+      if (PointerType *PT = dyn_cast<PointerType>(A->getType()))
+        return TD->getTypeAllocSize(PT->getElementType());
+  }
 
-/// isObjectPointerWithTrustworthySize - Return true if the specified Value* is
-/// pointing to an object with a pointer size we can trust.
-static bool isObjectPointerWithTrustworthySize(const Value *V) {
-  if (const AllocaInst *AI = dyn_cast<AllocaInst>(V))
-    return !AI->isArrayAllocation();
-  if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(V))
-    return !GV->mayBeOverridden();
-  if (const Argument *A = dyn_cast<Argument>(V))
-    return A->hasByValAttr();
-  if (isMalloc(V))
-    return true;
-  return false;
+  if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(V)) {
+    if (!GV->mayBeOverridden())
+      return TD->getTypeAllocSize(GV->getType()->getElementType());
+  }
+
+  return AliasAnalysis::UnknownSize;
 }
 
 namespace {
@@ -329,8 +321,8 @@
 static OverwriteResult isOverwrite(const AliasAnalysis::Location &Later,
                                    const AliasAnalysis::Location &Earlier,
                                    AliasAnalysis &AA,
-                                   int64_t& EarlierOff,
-                                   int64_t& LaterOff) {
+                                   int64_t &EarlierOff,
+                                   int64_t &LaterOff) {
   const Value *P1 = Earlier.Ptr->stripPointerCasts();
   const Value *P2 = Later.Ptr->stripPointerCasts();
 
@@ -377,12 +369,10 @@
     return OverwriteUnknown;
 
   // If the "Later" store is to a recognizable object, get its size.
-  if (isObjectPointerWithTrustworthySize(UO2)) {
-    uint64_t ObjectSize =
-      TD.getTypeAllocSize(cast<PointerType>(UO2->getType())->getElementType());
+  uint64_t ObjectSize = getPointerSize(UO2, AA);
+  if (ObjectSize != AliasAnalysis::UnknownSize)
     if (ObjectSize == Later.Size && ObjectSize >= Earlier.Size)
       return OverwriteComplete;
-  }
 
   // Okay, we have stores to two completely different pointers.  Try to
   // decompose the pointer into a "base + constant_offset" form.  If the base

Added: llvm/trunk/test/Transforms/DeadStoreElimination/pr11390.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/DeadStoreElimination/pr11390.ll?rev=144773&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/DeadStoreElimination/pr11390.ll (added)
+++ llvm/trunk/test/Transforms/DeadStoreElimination/pr11390.ll Tue Nov 15 21:49:48 2011
@@ -0,0 +1,38 @@
+; RUN: opt -basicaa -dse -S -o - | FileCheck %s
+; PR11390
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define fastcc void @cat_domain(i8* nocapture %name, i8* nocapture %domain, i8** 
+nocapture %s) nounwind uwtable {
+entry:
+  %call = tail call i64 @strlen(i8* %name) nounwind readonly
+  %call1 = tail call i64 @strlen(i8* %domain) nounwind readonly
+  %add = add i64 %call, 1
+  %add2 = add i64 %add, %call1
+  %add3 = add i64 %add2, 1
+  %call4 = tail call noalias i8* @malloc(i64 %add3) nounwind
+  store i8* %call4, i8** %s, align 8
+  %tobool = icmp eq i8* %call4, null
+  br i1 %tobool, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %call4, i8* %name, i64 %call, i32 1, i1 false)
+  %arrayidx = getelementptr inbounds i8* %call4, i64 %call
+  store i8 46, i8* %arrayidx, align 1
+; CHECK: store i8 46
+  %add.ptr5 = getelementptr inbounds i8* %call4, i64 %add
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %add.ptr5, i8* %domain, i64 %call1, i32 1, i1 false)
+  %arrayidx8 = getelementptr inbounds i8* %call4, i64 %add2
+  store i8 0, i8* %arrayidx8, align 1
+  br label %return
+
+return:                                           ; preds = %if.end, %entry
+  ret void
+}
+
+declare i64 @strlen(i8* nocapture) nounwind readonly
+
+declare noalias i8* @malloc(i64) nounwind
+
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind



From nicholas at mxc.ca  Tue Nov 15 21:56:39 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 16 Nov 2011 03:56:39 -0000
Subject: [llvm-commits] [llvm] r144774 -
	/llvm/trunk/test/Transforms/DeadStoreElimination/pr11390.ll
Message-ID: <20111116035639.0B9FA2A6C133@llvm.org>

Author: nicholas
Date: Tue Nov 15 21:56:38 2011
New Revision: 144774

URL: http://llvm.org/viewvc/llvm-project?rev=144774&view=rev
Log:
Fix typo in test.

Modified:
    llvm/trunk/test/Transforms/DeadStoreElimination/pr11390.ll

Modified: llvm/trunk/test/Transforms/DeadStoreElimination/pr11390.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/DeadStoreElimination/pr11390.ll?rev=144774&r1=144773&r2=144774&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/DeadStoreElimination/pr11390.ll (original)
+++ llvm/trunk/test/Transforms/DeadStoreElimination/pr11390.ll Tue Nov 15 21:56:38 2011
@@ -1,4 +1,4 @@
-; RUN: opt -basicaa -dse -S -o - | FileCheck %s
+; RUN: opt -basicaa -dse -S -o - %s | FileCheck %s
 ; PR11390
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"



From spop at codeaurora.org  Tue Nov 15 22:38:37 2011
From: spop at codeaurora.org (Sebastian Pop)
Date: Tue, 15 Nov 2011 22:38:37 -0600
Subject: [llvm-commits] [polly] r143576 -
	/polly/trunk/lib/Analysis/ScopDetection.cpp
In-Reply-To: <20111102214008.8D8D72A6C12C@llvm.org>
References: <20111102214008.8D8D72A6C12C@llvm.org>
Message-ID: <CAE5reQ+gmwvkcismTBhv7jqOZQWYhFMD7p_LP9RRHhaZenfKnw@mail.gmail.com>

On Wed, Nov 2, 2011 at 4:40 PM, Tobias Grosser
<grosser at fim.uni-passau.de> wrote:
> Author: grosser
> Date: Wed Nov  2 16:40:08 2011
> New Revision: 143576
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143576&view=rev
> Log:
> ScopDetection: Add new SCEV Validator
>
> The SCEV Validator is used to check if the bound of a loop can be translated
> into a polyhedral constraint. The new validator is more general as the check
> used previously and e.g. allows bounds like 'smax 1, %a'. At the moment, we
> only allow signed comparisons. Also, the new validator is only used to verify
> loop bounds. Memory accesses are still handled by the old validator.
>
> Modified:
>    polly/trunk/lib/Analysis/ScopDetection.cpp
>
> Modified: polly/trunk/lib/Analysis/ScopDetection.cpp
> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=143576&r1=143575&r2=143576&view=diff
> ==============================================================================
> --- polly/trunk/lib/Analysis/ScopDetection.cpp (original)
> +++ polly/trunk/lib/Analysis/ScopDetection.cpp Wed Nov  2 16:40:08 2011
> @@ -109,6 +109,162 @@
>  //===----------------------------------------------------------------------===//
>  // ScopDetection.
>
> +namespace SCEVType {
> +  enum TYPE {INT, PARAM, IV, INVALID};
> +}
> +
> +/// Check if a SCEV is valid in a SCoP.
> +struct SCEVValidator : public SCEVVisitor<SCEVValidator, SCEVType::TYPE> {
> +private:
> +  const Region *R;
> +  ScalarEvolution &SE;
> +  const Value **BaseAddress;
> +
> +public:
> +  static bool isValid(const Region *R, const SCEV *Scev,
> +                      ScalarEvolution &SE,
> +                      const Value **BaseAddress = NULL) {
> +    if (isa<SCEVCouldNotCompute>(Scev))
> +      return false;
> +
> +    SCEVValidator Validator(R, SE, BaseAddress);
> +    return Validator.visit(Scev) != SCEVType::INVALID;
> +  }
> +
> +  SCEVValidator(const Region *R, ScalarEvolution &SE,
> +                const Value **BaseAddress) : R(R), SE(SE),
> +    BaseAddress(BaseAddress) {};
> +
> +  SCEVType::TYPE visitConstant(const SCEVConstant *Constant) {
> +    return SCEVType::INT;
> +  }
> +
> +  SCEVType::TYPE visitTruncateExpr(const SCEVTruncateExpr* Expr) {

Please use a single way to place the *, i.e., SCEVTruncateExpr *Expr
also occurs below, several times in several inconsistent ways.

> +    SCEVType::TYPE Op = visit(Expr->getOperand());
> +
> +    // We cannot represent this as a affine expression yet. If it is constant

s/a affine/an affine/

> +    // during Scop execution treat this as a parameter, otherwise bail out.
> +    if (Op == SCEVType::INT || Op == SCEVType::PARAM)
> +      return SCEVType::PARAM;
> +
> +    return SCEVType::INVALID;
> +  }
> +
> +  SCEVType::TYPE visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) {
> +    SCEVType::TYPE Op = visit(Expr->getOperand());
> +
> +    // We cannot represent this as a affine expression yet. If it is constant

s/a affine/an affine/

> +    // during Scop execution treat this as a parameter, otherwise bail out.
> +    if (Op == SCEVType::INT || Op == SCEVType::PARAM)
> +      return SCEVType::PARAM;
> +
> +    return SCEVType::INVALID;
> +  }
> +
> +  SCEVType::TYPE visitSignExtendExpr(const SCEVSignExtendExpr* Expr) {
> +    // Assuming the value is signed, a sign extension is basically a noop.
> +    // TODO: Reconsider this as soon as we support unsigned values.
> +    return visit(Expr->getOperand());
> +  }
> +
> +  SCEVType::TYPE visitAddExpr(const SCEVAddExpr* Expr) {
> +    SCEVType::TYPE Return = SCEVType::INT;
> +
> +    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> +      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
> +      Return = std::max(Return, OpType);
> +    }
> +
> +    // TODO: Check for NSW and NUW.
> +    return Return;
> +  }
> +
> +  SCEVType::TYPE visitMulExpr(const SCEVMulExpr* Expr) {
> +    SCEVType::TYPE Return = SCEVType::INT;
> +
> +    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> +      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
> +
> +      if (OpType == SCEVType::INVALID)
> +        return SCEVType::INVALID;
> +
> +      if (OpType == SCEVType::IV) {
> +        if (Return == SCEVType::PARAM || Return == SCEVType::IV)
> +          return SCEVType::INVALID;
> +
> +        Return = OpType;
> +        continue;
> +      }
> +
> +      if (OpType == SCEVType::PARAM) {
> +        if (Return == SCEVType::PARAM)
> +          return SCEVType::INVALID;
> +
> +        Return = SCEVType::PARAM;
> +        continue;
> +      }
> +
> +      // OpType == SCEVType::INT, no need to change anything.
> +    }
> +
> +    // TODO: Check for NSW and NUW.
> +    return Return;
> +  }
> +
> +  SCEVType::TYPE visitUDivExpr(const SCEVUDivExpr* Expr) {
> +    // We do not yet support unsigned operations.
> +    return SCEVType::INVALID;
> +  }
> +
> +  SCEVType::TYPE visitAddRecExpr(const SCEVAddRecExpr* Expr) {
> +    if (!Expr->isAffine())
> +      return SCEVType::INVALID;
> +
> +    SCEVType::TYPE Start = visit(Expr->getStart());
> +
> +    if (Start == SCEVType::INVALID)
> +      return Start;
> +
> +    SCEVType::TYPE Recurrence = visit(Expr->getStepRecurrence(SE));

In the following code, why not doing this instead?


   if (Recurrence == SCEVType::INT)
     return SCEVType::IV;

   return SCEVType::INVALID;

> +    if (Recurrence != SCEVType::INT)
> +      return SCEVType::INVALID;
> +
> +    return SCEVType::PARAM;

I don't see why you would return a PARAM for an addrec with a constant step.
I would return SCEVType::IV.

> +  }
> +
> +  SCEVType::TYPE visitSMaxExpr(const SCEVSMaxExpr* Expr) {
> +    SCEVType::TYPE Return = SCEVType::INT;
> +
> +    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> +      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
> +
> +      if (OpType == SCEVType::INVALID)
> +        return SCEVType::INVALID;
> +      if (OpType == SCEVType::PARAM)
> +        Return = SCEVType::PARAM;
> +    }
> +
> +    return Return;
> +  }
> +
> +  SCEVType::TYPE visitUMaxExpr(const SCEVUMaxExpr* Expr) {
> +    // We do not yet support unsigned operations. If 'Expr' is constant
> +    // during Scop execution treat this as a parameter, otherwise bail out.
> +    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> +      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
> +
> +      if (OpType != SCEVType::INT && OpType != SCEVType::PARAM)
> +        return SCEVType::PARAM;

Probably this first return should have been SCEVType::INVALID?

> +    }
> +
> +    return SCEVType::PARAM;
> +  }

You should check the logic in this function, as I see that you always
return SCEVType::PARAM.


> +
> +  SCEVType::TYPE visitUnknown(const SCEVUnknown* Expr) {
> +    return SCEVType::PARAM;
> +  }

Really?  I would have returned INVALID instead of PARAM for an unknown SCEV.

> +};
> +
>  bool ScopDetection::isMaxRegionInScop(const Region &R) const {
>   // The Region is valid only if it could be found in the set.
>   return ValidRegions.count(&R);
> @@ -401,7 +557,7 @@
>
>   // Is the loop count affine?
>   const SCEV *LoopCount = SE->getBackedgeTakenCount(L);
> -  if (!isValidAffineFunction(LoopCount, Context.CurRegion))
> +  if (!SCEVValidator::isValid(&Context.CurRegion, LoopCount, *SE))
>     INVALID(LoopBound, "Non affine loop bound '" << *LoopCount << "' in loop: "
>                        << L->getHeader()->getNameStr());
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Sebastian Pop
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

From spop at codeaurora.org  Tue Nov 15 22:55:05 2011
From: spop at codeaurora.org (Sebastian Pop)
Date: Tue, 15 Nov 2011 22:55:05 -0600
Subject: [llvm-commits] [polly] r143692 -
	/polly/trunk/lib/Analysis/ScopDetection.cpp
In-Reply-To: <20111104100808.A50192A6C12D@llvm.org>
References: <20111104100808.A50192A6C12D@llvm.org>
Message-ID: <CAE5reQJ1mFsVtQxU_m85WAP149dSe-cTbUGNsYbRbWRs2TSdiw@mail.gmail.com>

On Fri, Nov 4, 2011 at 5:08 AM, Tobias Grosser
<grosser at fim.uni-passau.de> wrote:
> Author: grosser
> Date: Fri Nov  4 05:08:08 2011
> New Revision: 143692
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143692&view=rev
> Log:
> ScopDetection: Small fixes and improvements for the SCEVValidator
>
> These fixes were part of a code audit of the SCEVValidator.
>
> Modified:
>    polly/trunk/lib/Analysis/ScopDetection.cpp
>
> Modified: polly/trunk/lib/Analysis/ScopDetection.cpp
> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=143692&r1=143691&r2=143692&view=diff
> ==============================================================================
> --- polly/trunk/lib/Analysis/ScopDetection.cpp (original)
> +++ polly/trunk/lib/Analysis/ScopDetection.cpp Fri Nov  4 05:08:08 2011
> @@ -145,8 +145,9 @@
>   SCEVType::TYPE visitTruncateExpr(const SCEVTruncateExpr* Expr) {
>     SCEVType::TYPE Op = visit(Expr->getOperand());
>
> -    // We cannot represent this as a affine expression yet. If it is constant
> -    // during Scop execution treat this as a parameter, otherwise bail out.
> +    // We currently do not represent a truncate expression as an affine
> +    // expression. If it is constant during Scop execution, we treat it as a
> +    // parameter, otherwise we bail out.
>     if (Op == SCEVType::INT || Op == SCEVType::PARAM)
>       return SCEVType::PARAM;
>
> @@ -156,8 +157,9 @@
>   SCEVType::TYPE visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) {
>     SCEVType::TYPE Op = visit(Expr->getOperand());
>
> -    // We cannot represent this as a affine expression yet. If it is constant
> -    // during Scop execution treat this as a parameter, otherwise bail out.
> +    // We currently do not represent a zero extend expression as an affine
> +    // expression. If it is constant during Scop execution, we treat it as a
> +    // parameter, otherwise we bail out.
>     if (Op == SCEVType::INT || Op == SCEVType::PARAM)
>       return SCEVType::PARAM;
>
> @@ -165,8 +167,10 @@
>   }
>
>   SCEVType::TYPE visitSignExtendExpr(const SCEVSignExtendExpr* Expr) {
> -    // Assuming the value is signed, a sign extension is basically a noop.
> -    // TODO: Reconsider this as soon as we support unsigned values.
> +    // We currently allow only signed SCEV expressions. In the case of a
> +    // signed value, a sign extend is a noop.
> +    //
> +    // TODO: Reconsider this when we add support for unsigned values.
>     return visit(Expr->getOperand());
>   }
>
> @@ -175,6 +179,10 @@
>
>     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
>       SCEVType::TYPE OpType = visit(Expr->getOperand(i));
> +
> +      if (OpType == SCEVType::INVALID)
> +        return SCEVType::INVALID;
> +
>       Return = std::max(Return, OpType);
>     }
>
> @@ -188,26 +196,13 @@
>     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
>       SCEVType::TYPE OpType = visit(Expr->getOperand(i));
>
> -      if (OpType == SCEVType::INVALID)
> -        return SCEVType::INVALID;
> -
> -      if (OpType == SCEVType::IV) {
> -        if (Return == SCEVType::PARAM || Return == SCEVType::IV)
> -          return SCEVType::INVALID;
> -
> -        Return = OpType;
> +      if (OpType == SCEVType::INT)
>         continue;
> -      }
> -
> -      if (OpType == SCEVType::PARAM) {
> -        if (Return == SCEVType::PARAM)
> -          return SCEVType::INVALID;
>
> -        Return = SCEVType::PARAM;
> -        continue;
> -      }
> +      if (OpType == SCEVType::INVALID || Return != SCEVType::INT)
> +        return SCEVType::INVALID;
>
> -      // OpType == SCEVType::INT, no need to change anything.
> +      Return = OpType;
>     }
>
>     // TODO: Check for NSW and NUW.
> @@ -215,7 +210,16 @@
>   }
>
>   SCEVType::TYPE visitUDivExpr(const SCEVUDivExpr* Expr) {
> -    // We do not yet support unsigned operations.
> +    SCEVType::TYPE LHS = visit(Expr->getLHS());
> +    SCEVType::TYPE RHS = visit(Expr->getRHS());
> +
> +    // We currently do not represent a unsigned devision as an affine

s/a unsigned/an unsigned/

> +    // expression. If the division is constant during Scop execution we treat it
> +    // as a parameter, otherwise we bail out.
> +    if (LHS == SCEVType::INT || LHS == SCEVType::PARAM ||
> +        RHS == SCEVType::INT || RHS == SCEVType::PARAM)
> +      return SCEVType::PARAM;
> +
>     return SCEVType::INVALID;
>   }
>
> @@ -224,15 +228,24 @@
>       return SCEVType::INVALID;
>
>     SCEVType::TYPE Start = visit(Expr->getStart());
> +    SCEVType::TYPE Recurrence = visit(Expr->getStepRecurrence(SE));
>
> -    if (Start == SCEVType::INVALID)
> -      return Start;
> +    if (Start == SCEVType::INVALID ||
> +        Recurrence == SCEVType::INVALID ||
> +        Recurrence == SCEVType::IV)
> +      return SCEVType::INVALID;
> +
> +    if (!R->contains(Expr->getLoop())) {
> +      if (Start == SCEVType::IV)
> +        return SCEVType::INVALID;
> +      else
> +        return SCEVType::PARAM;
> +    }
>
> -    SCEVType::TYPE Recurrence = visit(Expr->getStepRecurrence(SE));
>     if (Recurrence != SCEVType::INT)
>       return SCEVType::INVALID;
>
> -    return SCEVType::PARAM;
> +    return SCEVType::IV;

Good!
I see that you got this one corrected.

>   }
>
>   SCEVType::TYPE visitSMaxExpr(const SCEVSMaxExpr* Expr) {
> @@ -243,32 +256,31 @@
>
>       if (OpType == SCEVType::INVALID)
>         return SCEVType::INVALID;
> -      if (OpType == SCEVType::PARAM)
> -        Return = SCEVType::PARAM;
> +
> +      Return = std::max(Return, OpType);
>     }
>
>     return Return;
>   }
>
>   SCEVType::TYPE visitUMaxExpr(const SCEVUMaxExpr* Expr) {
> -    // We do not yet support unsigned operations. If 'Expr' is constant
> -    // during Scop execution treat this as a parameter, otherwise bail out.
> +    // We do not support unsigned operations. If 'Expr' is constant during Scop
> +    // execution we treat this as a parameter, otherwise we bail out.
>     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
>       SCEVType::TYPE OpType = visit(Expr->getOperand(i));
>
>       if (OpType != SCEVType::INT && OpType != SCEVType::PARAM)
> -        return SCEVType::PARAM;
> +        return SCEVType::INVALID;

And this one as well looks good after this change.

>     }
>
>     return SCEVType::PARAM;
>   }
>
>   SCEVType::TYPE visitUnknown(const SCEVUnknown* Expr) {
> -
>     Value *V = Expr->getValue();
>
>     if (isa<UndefValue>(V))
> -        return SCEVType::INVALID;
> +      return SCEVType::INVALID;
>
>     if (BaseAddress) {
>       if (*BaseAddress)
> @@ -280,6 +292,7 @@
>     if (Instruction *I = dyn_cast<Instruction>(Expr->getValue()))
>       if (R->contains(I))
>         return SCEVType::INVALID;
> +
>     return SCEVType::PARAM;
>   }
>  };
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Sebastian Pop
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

From evan.cheng at apple.com  Tue Nov 15 22:55:02 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 16 Nov 2011 04:55:02 -0000
Subject: [llvm-commits] [llvm] r144776 -
	/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
Message-ID: <20111116045502.295662A6C133@llvm.org>

Author: evancheng
Date: Tue Nov 15 22:55:01 2011
New Revision: 144776

URL: http://llvm.org/viewvc/llvm-project?rev=144776&view=rev
Log:
Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=144776&r1=144775&r2=144776&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Nov 15 22:55:01 2011
@@ -502,8 +502,7 @@
       continue;
     if (!UI.getOperand().isKill())
       return 0;
-    if (KillMI)
-      return 0;  // -O0 kill markers cannot be trusted?
+    assert(!KillMI && "More than one local kills?");
     KillMI = UseMI;
   }
 



From craig.topper at gmail.com  Tue Nov 15 23:02:04 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Wed, 16 Nov 2011 05:02:04 -0000
Subject: [llvm-commits] [llvm] r144777 -
	/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
Message-ID: <20111116050204.DA1BA2A6C133@llvm.org>

Author: ctopper
Date: Tue Nov 15 23:02:04 2011
New Revision: 144777

URL: http://llvm.org/viewvc/llvm-project?rev=144777&view=rev
Log:
Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636.

Modified:
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=144777&r1=144776&r2=144777&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Tue Nov 15 23:02:04 2011
@@ -135,15 +135,9 @@
 bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
                                       CodeGenOpt::Level OptLevel) {
   bool ShouldPrint = false;
-  if (OptLevel != CodeGenOpt::None) {
-    if (Subtarget.hasXMMInt()) {
-      PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
-      ShouldPrint = true;
-    }
-    if (Subtarget.hasAVX()) {
-      PM.add(createExecutionDependencyFixPass(&X86::VR256RegClass));
-      ShouldPrint = true;
-    }
+  if (OptLevel != CodeGenOpt::None && Subtarget.hasXMMInt()) {
+    PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
+    ShouldPrint = true;
   }
 
   if (Subtarget.hasAVX() && UseVZeroUpper) {



From spop at codeaurora.org  Tue Nov 15 23:04:59 2011
From: spop at codeaurora.org (Sebastian Pop)
Date: Tue, 15 Nov 2011 23:04:59 -0600
Subject: [llvm-commits] [polly] r143958 -
	/polly/trunk/lib/Analysis/ScopDetection.cpp
In-Reply-To: <20111107125842.302162A6C12C@llvm.org>
References: <20111107125842.302162A6C12C@llvm.org>
Message-ID: <CAE5reQJKwC0rn33Wo2Y-XArBxTmU4fKb=W-HGByF26CkpD6qPg@mail.gmail.com>

On Mon, Nov 7, 2011 at 6:58 AM, Tobias Grosser
<grosser at fim.uni-passau.de> wrote:
> Author: grosser
> Date: Mon Nov  7 06:58:41 2011
> New Revision: 143958
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143958&view=rev
> Log:
> ScopDetection: Add ValidatorResult class
>
> Modified:
>    polly/trunk/lib/Analysis/ScopDetection.cpp
>
> Modified: polly/trunk/lib/Analysis/ScopDetection.cpp
> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=143958&r1=143957&r2=143958&view=diff
> ==============================================================================
> --- polly/trunk/lib/Analysis/ScopDetection.cpp (original)
> +++ polly/trunk/lib/Analysis/ScopDetection.cpp Mon Nov  7 06:58:41 2011
> @@ -113,8 +113,22 @@
>   enum TYPE {INT, PARAM, IV, INVALID};
>  }
>
> +struct ValidatorResult {
> +  SCEVType::TYPE type;
> +
> +  ValidatorResult() : type(SCEVType::INVALID) {};
> +
> +  ValidatorResult(const ValidatorResult &vres) {
> +    type = vres.type;
> +  };
> +
> +  ValidatorResult(SCEVType::TYPE type) : type(type) {};
> +
> +};
> +
>  /// Check if a SCEV is valid in a SCoP.
> -struct SCEVValidator : public SCEVVisitor<SCEVValidator, SCEVType::TYPE> {
> +struct SCEVValidator
> +  : public SCEVVisitor<SCEVValidator, struct ValidatorResult> {
>  private:
>   const Region *R;
>   ScalarEvolution &SE;
> @@ -131,42 +145,44 @@
>       *BaseAddress = NULL;
>
>     SCEVValidator Validator(R, SE, BaseAddress);
> -    return Validator.visit(Scev) != SCEVType::INVALID;
> +    ValidatorResult Result = Validator.visit(Scev);
> +
> +    return Result.type != SCEVType::INVALID;
>   }
>
>   SCEVValidator(const Region *R, ScalarEvolution &SE,
>                 Value **BaseAddress) : R(R), SE(SE),
>     BaseAddress(BaseAddress) {};
>
> -  SCEVType::TYPE visitConstant(const SCEVConstant *Constant) {
> -    return SCEVType::INT;
> +  struct ValidatorResult visitConstant(const SCEVConstant *Constant) {
> +    return ValidatorResult(SCEVType::INT);
>   }
>
> -  SCEVType::TYPE visitTruncateExpr(const SCEVTruncateExpr* Expr) {
> -    SCEVType::TYPE Op = visit(Expr->getOperand());
> +  struct ValidatorResult visitTruncateExpr(const SCEVTruncateExpr* Expr) {
> +    ValidatorResult Op = visit(Expr->getOperand());
>
>     // We currently do not represent a truncate expression as an affine
>     // expression. If it is constant during Scop execution, we treat it as a
>     // parameter, otherwise we bail out.
> -    if (Op == SCEVType::INT || Op == SCEVType::PARAM)
> -      return SCEVType::PARAM;
> +    if (Op.type == SCEVType::INT || Op.type == SCEVType::PARAM)
> +      return ValidatorResult(SCEVType::PARAM);
>
> -    return SCEVType::INVALID;
> +    return ValidatorResult (SCEVType::INVALID);
>   }
>
> -  SCEVType::TYPE visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) {
> -    SCEVType::TYPE Op = visit(Expr->getOperand());
> +  struct ValidatorResult visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) {
> +    ValidatorResult Op = visit(Expr->getOperand());
>
>     // We currently do not represent a zero extend expression as an affine
>     // expression. If it is constant during Scop execution, we treat it as a
>     // parameter, otherwise we bail out.
> -    if (Op == SCEVType::INT || Op == SCEVType::PARAM)
> -      return SCEVType::PARAM;
> +    if (Op.type == SCEVType::INT || Op.type == SCEVType::PARAM)
> +      return ValidatorResult (SCEVType::PARAM);
>
> -    return SCEVType::INVALID;
> +    return ValidatorResult(SCEVType::INVALID);
>   }
>
> -  SCEVType::TYPE visitSignExtendExpr(const SCEVSignExtendExpr* Expr) {
> +  struct ValidatorResult visitSignExtendExpr(const SCEVSignExtendExpr* Expr) {
>     // We currently allow only signed SCEV expressions. In the case of a
>     // signed value, a sign extend is a noop.
>     //
> @@ -174,126 +190,130 @@
>     return visit(Expr->getOperand());
>   }
>
> -  SCEVType::TYPE visitAddExpr(const SCEVAddExpr* Expr) {
> -    SCEVType::TYPE Return = SCEVType::INT;
> +  struct ValidatorResult visitAddExpr(const SCEVAddExpr* Expr) {
> +    ValidatorResult Return(SCEVType::INT);
>
>     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> -      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
> +      ValidatorResult Op = visit(Expr->getOperand(i));
>
> -      if (OpType == SCEVType::INVALID)
> -        return SCEVType::INVALID;
> +      if (Op.type == SCEVType::INVALID)
> +        return ValidatorResult(SCEVType::INVALID);
>
> -      Return = std::max(Return, OpType);
> +      Return.type = std::max(Return.type, Op.type);
>     }
>
>     // TODO: Check for NSW and NUW.
>     return Return;
>   }
>
> -  SCEVType::TYPE visitMulExpr(const SCEVMulExpr* Expr) {
> -    SCEVType::TYPE Return = SCEVType::INT;
> +  struct ValidatorResult visitMulExpr(const SCEVMulExpr* Expr) {
> +    ValidatorResult Return(SCEVType::INT);
>
>     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> -      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
> +      ValidatorResult Op = visit(Expr->getOperand(i));
>
> -      if (OpType == SCEVType::INT)
> +      if (Op.type == SCEVType::INT)
>         continue;
>
> -      if (OpType == SCEVType::INVALID || Return != SCEVType::INT)
> -        return SCEVType::INVALID;
> +      if (Op.type == SCEVType::INVALID || Return.type != SCEVType::INT)
> +        return ValidatorResult(SCEVType::INVALID);
>
> -      Return = OpType;
> +      Return.type = Op.type;
>     }
>
>     // TODO: Check for NSW and NUW.
>     return Return;
>   }
>
> -  SCEVType::TYPE visitUDivExpr(const SCEVUDivExpr* Expr) {
> -    SCEVType::TYPE LHS = visit(Expr->getLHS());
> -    SCEVType::TYPE RHS = visit(Expr->getRHS());
> +  struct ValidatorResult visitUDivExpr(const SCEVUDivExpr* Expr) {
> +    ValidatorResult LHS = visit(Expr->getLHS());
> +    ValidatorResult RHS = visit(Expr->getRHS());
>
>     // We currently do not represent a unsigned devision as an affine
>     // expression. If the division is constant during Scop execution we treat it
>     // as a parameter, otherwise we bail out.
> -    if (LHS == SCEVType::INT || LHS == SCEVType::PARAM ||
> -        RHS == SCEVType::INT || RHS == SCEVType::PARAM)
> -      return SCEVType::PARAM;
> +    if (LHS.type == SCEVType::INT || LHS.type == SCEVType::PARAM ||
> +        RHS.type == SCEVType::INT || RHS.type == SCEVType::PARAM)
> +      return ValidatorResult(SCEVType::PARAM);
>
> -    return SCEVType::INVALID;
> +    return ValidatorResult(SCEVType::INVALID);
>   }
>
> -  SCEVType::TYPE visitAddRecExpr(const SCEVAddRecExpr* Expr) {
> +  struct ValidatorResult visitAddRecExpr(const SCEVAddRecExpr* Expr) {
>     if (!Expr->isAffine())
> -      return SCEVType::INVALID;
> +      return ValidatorResult(SCEVType::INVALID);
>
> -    SCEVType::TYPE Start = visit(Expr->getStart());
> -    SCEVType::TYPE Recurrence = visit(Expr->getStepRecurrence(SE));
> +    ValidatorResult Start = visit(Expr->getStart());
> +    ValidatorResult Recurrence = visit(Expr->getStepRecurrence(SE));
> +
> +    if (Start.type == SCEVType::INVALID ||
> +        Recurrence.type == SCEVType::INVALID ||
> +        Recurrence.type == SCEVType::IV)
> +      return ValidatorResult(SCEVType::INVALID);
>
> -    if (Start == SCEVType::INVALID ||
> -        Recurrence == SCEVType::INVALID ||
> -        Recurrence == SCEVType::IV)
> -      return SCEVType::INVALID;
>
>     if (!R->contains(Expr->getLoop())) {
> -      if (Start == SCEVType::IV)
> -        return SCEVType::INVALID;
> +      if (Start.type == SCEVType::IV)
> +        return ValidatorResult(SCEVType::INVALID);
>       else
> -        return SCEVType::PARAM;
> +        return ValidatorResult(SCEVType::PARAM);
>     }
>
> -    if (Recurrence != SCEVType::INT)
> -      return SCEVType::INVALID;
> +    if (Recurrence.type != SCEVType::INT)
> +      return ValidatorResult(SCEVType::INVALID);
>
> -    return SCEVType::IV;
> +    return ValidatorResult(SCEVType::IV);
>   }
>
> -  SCEVType::TYPE visitSMaxExpr(const SCEVSMaxExpr* Expr) {
> -    SCEVType::TYPE Return = SCEVType::INT;
> +  struct ValidatorResult visitSMaxExpr(const SCEVSMaxExpr* Expr) {
> +    ValidatorResult Return(SCEVType::INT);
>
>     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> -      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
> +      ValidatorResult Op = visit(Expr->getOperand(i));
>
> -      if (OpType == SCEVType::INVALID)
> -        return SCEVType::INVALID;
> +      if (Op.type == SCEVType::INVALID)
> +        return ValidatorResult(SCEVType::INVALID);
>
> -      Return = std::max(Return, OpType);
> +      Return.type = std::max(Return.type, Op.type);
>     }
>
>     return Return;
>   }
>
> -  SCEVType::TYPE visitUMaxExpr(const SCEVUMaxExpr* Expr) {
> +  struct ValidatorResult visitUMaxExpr(const SCEVUMaxExpr* Expr) {
>     // We do not support unsigned operations. If 'Expr' is constant during Scop
>     // execution we treat this as a parameter, otherwise we bail out.
>     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> -      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
> +      ValidatorResult Op = visit(Expr->getOperand(i));
>
> -      if (OpType != SCEVType::INT && OpType != SCEVType::PARAM)
> -        return SCEVType::INVALID;
> +      if (Op.type != SCEVType::INT && Op.type != SCEVType::PARAM)
> +        return ValidatorResult(SCEVType::INVALID);
>     }
>
> -    return SCEVType::PARAM;
> +    return ValidatorResult(SCEVType::PARAM);
>   }
>
> -  SCEVType::TYPE visitUnknown(const SCEVUnknown* Expr) {
> +  ValidatorResult visitUnknown(const SCEVUnknown* Expr) {
>     Value *V = Expr->getValue();
>
>     if (isa<UndefValue>(V))
> -      return SCEVType::INVALID;
> +      return ValidatorResult(SCEVType::INVALID);
>
>     if (BaseAddress) {
>       if (*BaseAddress)
> -        return SCEVType::INVALID;
> +        return ValidatorResult(SCEVType::INVALID);
>       else
>         *BaseAddress = V;
>     }
>
>     if (Instruction *I = dyn_cast<Instruction>(Expr->getValue()))
>       if (R->contains(I))
> -        return SCEVType::INVALID;
> +        return ValidatorResult(SCEVType::INVALID);
>
> -    return SCEVType::PARAM;
> +    if (BaseAddress)
> +      return ValidatorResult(SCEVType::PARAM);
> +    else
> +      return ValidatorResult(SCEVType::PARAM);

This change looks strange: why are you returning the same thing in
both branches?

>   }
>  };
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Sebastian Pop
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

From spop at codeaurora.org  Tue Nov 15 23:14:57 2011
From: spop at codeaurora.org (Sebastian Pop)
Date: Tue, 15 Nov 2011 23:14:57 -0600
Subject: [llvm-commits] [polly] r143960 - in /polly/trunk:
 include/polly/Support/SCEVValidator.h lib/Analysis/ScopDetection.cpp
 lib/Support/CMakeLists.txt lib/Support/SCEVValidator.cpp
In-Reply-To: <20111107125854.552013524001@llvm.org>
References: <20111107125854.552013524001@llvm.org>
Message-ID: <CAE5reQKfvzQZ7Mjr5gAmJawiVO9AP5Q+qA4G48PB3kMCifpK4g@mail.gmail.com>

On Mon, Nov 7, 2011 at 6:58 AM, Tobias Grosser
<grosser at fim.uni-passau.de> wrote:
> Author: grosser
> Date: Mon Nov  7 06:58:54 2011
> New Revision: 143960
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143960&view=rev
> Log:
> SCEVValidator: Move into own file
>
> Added:
>    polly/trunk/include/polly/Support/SCEVValidator.h   (with props)
>    polly/trunk/lib/Support/SCEVValidator.cpp
> Modified:
>    polly/trunk/lib/Analysis/ScopDetection.cpp
>    polly/trunk/lib/Support/CMakeLists.txt
>
> Added: polly/trunk/include/polly/Support/SCEVValidator.h
> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/Support/SCEVValidator.h?rev=143960&view=auto
> ==============================================================================
> --- polly/trunk/include/polly/Support/SCEVValidator.h (added)
> +++ polly/trunk/include/polly/Support/SCEVValidator.h Mon Nov  7 06:58:54 2011
> @@ -0,0 +1,27 @@
> +//===--- SCEVValidator.h - Detect Scops -------------------------*- C++ -*-===//
> +//
> +//                     The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +// Checks if a SCEV expression represents a valid affine expression.
> +//===----------------------------------------------------------------------===//
> +
> +#ifndef POLLY_SCEV_VALIDATOR_H
> +#define POLLY_SCEV_VALIDATOR_H
> +
> +namespace llvm {
> +  class Region;
> +  class SCEV;
> +  class ScalarEvolution;
> +  class Value;
> +}
> +
> +namespace polly {
> +  bool isAffineExpr(const llvm::Region *R, const llvm::SCEV *Expression,
> +                    llvm::ScalarEvolution &SE, llvm::Value **BaseAddress = 0);
> +}
> +
> +#endif
>
> Propchange: polly/trunk/include/polly/Support/SCEVValidator.h
> ------------------------------------------------------------------------------
>    svn:executable = *
>
> Modified: polly/trunk/lib/Analysis/ScopDetection.cpp
> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=143960&r1=143959&r2=143960&view=diff
> ==============================================================================
> --- polly/trunk/lib/Analysis/ScopDetection.cpp (original)
> +++ polly/trunk/lib/Analysis/ScopDetection.cpp Mon Nov  7 06:58:54 2011
> @@ -48,6 +48,7 @@
>
>  #include "polly/LinkAllPasses.h"
>  #include "polly/Support/ScopHelper.h"
> +#include "polly/Support/SCEVValidator.h"
>  #include "polly/Support/AffineSCEVIterator.h"
>
>  #include "llvm/LLVMContext.h"
> @@ -108,227 +109,6 @@
>
>  //===----------------------------------------------------------------------===//
>  // ScopDetection.
> -
> -namespace SCEVType {
> -  enum TYPE {INT, PARAM, IV, INVALID};
> -}
> -
> -struct ValidatorResult {
> -  SCEVType::TYPE type;
> -
> -  ValidatorResult() : type(SCEVType::INVALID) {};
> -
> -  ValidatorResult(const ValidatorResult &vres) {
> -    type = vres.type;
> -  };
> -
> -  ValidatorResult(SCEVType::TYPE type) : type(type) {};
> -
> -  bool isConstant() {
> -    return type == SCEVType::INT || type == SCEVType::PARAM;
> -  }
> -
> -  bool isValid() {
> -    return type != SCEVType::INVALID;
> -  }
> -
> -  bool isIV() {
> -    return type == SCEVType::IV;
> -  }
> -
> -  bool isINT() {
> -    return type == SCEVType::INT;
> -  }
> -};
> -
> -/// Check if a SCEV is valid in a SCoP.
> -struct SCEVValidator
> -  : public SCEVVisitor<SCEVValidator, struct ValidatorResult> {
> -private:
> -  const Region *R;
> -  ScalarEvolution &SE;
> -  Value **BaseAddress;
> -
> -public:
> -  static bool isValid(const Region *R, const SCEV *Scev,
> -                      ScalarEvolution &SE,
> -                      Value **BaseAddress = NULL) {
> -    if (isa<SCEVCouldNotCompute>(Scev))
> -      return false;
> -
> -    if (BaseAddress)
> -      *BaseAddress = NULL;
> -
> -    SCEVValidator Validator(R, SE, BaseAddress);
> -    ValidatorResult Result = Validator.visit(Scev);
> -
> -    return Result.isValid();
> -  }
> -
> -  SCEVValidator(const Region *R, ScalarEvolution &SE,
> -                Value **BaseAddress) : R(R), SE(SE),
> -    BaseAddress(BaseAddress) {};
> -
> -  struct ValidatorResult visitConstant(const SCEVConstant *Constant) {
> -    return ValidatorResult(SCEVType::INT);
> -  }
> -
> -  struct ValidatorResult visitTruncateExpr(const SCEVTruncateExpr* Expr) {
> -    ValidatorResult Op = visit(Expr->getOperand());
> -
> -    // We currently do not represent a truncate expression as an affine
> -    // expression. If it is constant during Scop execution, we treat it as a
> -    // parameter, otherwise we bail out.
> -    if (Op.isConstant())
> -      return ValidatorResult(SCEVType::PARAM);
> -
> -    return ValidatorResult (SCEVType::INVALID);
> -  }
> -
> -  struct ValidatorResult visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) {
> -    ValidatorResult Op = visit(Expr->getOperand());
> -
> -    // We currently do not represent a zero extend expression as an affine
> -    // expression. If it is constant during Scop execution, we treat it as a
> -    // parameter, otherwise we bail out.
> -    if (Op.isConstant())
> -      return ValidatorResult (SCEVType::PARAM);
> -
> -    return ValidatorResult(SCEVType::INVALID);
> -  }
> -
> -  struct ValidatorResult visitSignExtendExpr(const SCEVSignExtendExpr* Expr) {
> -    // We currently allow only signed SCEV expressions. In the case of a
> -    // signed value, a sign extend is a noop.
> -    //
> -    // TODO: Reconsider this when we add support for unsigned values.
> -    return visit(Expr->getOperand());
> -  }
> -
> -  struct ValidatorResult visitAddExpr(const SCEVAddExpr* Expr) {
> -    ValidatorResult Return(SCEVType::INT);
> -
> -    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> -      ValidatorResult Op = visit(Expr->getOperand(i));
> -
> -      if (!Op.isValid())
> -        return ValidatorResult(SCEVType::INVALID);
> -
> -      Return.type = std::max(Return.type, Op.type);
> -    }
> -
> -    // TODO: Check for NSW and NUW.
> -    return Return;
> -  }
> -
> -  struct ValidatorResult visitMulExpr(const SCEVMulExpr* Expr) {
> -    ValidatorResult Return(SCEVType::INT);
> -
> -    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> -      ValidatorResult Op = visit(Expr->getOperand(i));
> -
> -      if (Op.type == SCEVType::INT)
> -        continue;
> -
> -      if (Op.type == SCEVType::INVALID || Return.type != SCEVType::INT)
> -        return ValidatorResult(SCEVType::INVALID);
> -
> -      Return.type = Op.type;
> -    }
> -
> -    // TODO: Check for NSW and NUW.
> -    return Return;
> -  }
> -
> -  struct ValidatorResult visitUDivExpr(const SCEVUDivExpr* Expr) {
> -    ValidatorResult LHS = visit(Expr->getLHS());
> -    ValidatorResult RHS = visit(Expr->getRHS());
> -
> -    // We currently do not represent a unsigned devision as an affine
> -    // expression. If the division is constant during Scop execution we treat it
> -    // as a parameter, otherwise we bail out.
> -    if (LHS.isConstant() && RHS.isConstant())
> -      return ValidatorResult(SCEVType::PARAM);
> -
> -    return ValidatorResult(SCEVType::INVALID);
> -  }
> -
> -  struct ValidatorResult visitAddRecExpr(const SCEVAddRecExpr* Expr) {
> -    if (!Expr->isAffine())
> -      return ValidatorResult(SCEVType::INVALID);
> -
> -    ValidatorResult Start = visit(Expr->getStart());
> -    ValidatorResult Recurrence = visit(Expr->getStepRecurrence(SE));
> -
> -    if (!Start.isValid() || !Recurrence.isValid() || Recurrence.isIV())
> -      return ValidatorResult(SCEVType::INVALID);
> -
> -
> -    if (!R->contains(Expr->getLoop())) {
> -      if (Start.isIV())
> -        return ValidatorResult(SCEVType::INVALID);
> -      else
> -        return ValidatorResult(SCEVType::PARAM);
> -    }
> -
> -    if (!Recurrence.isINT())
> -      return ValidatorResult(SCEVType::INVALID);
> -
> -    return ValidatorResult(SCEVType::IV);
> -  }
> -
> -  struct ValidatorResult visitSMaxExpr(const SCEVSMaxExpr* Expr) {
> -    ValidatorResult Return(SCEVType::INT);
> -
> -    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> -      ValidatorResult Op = visit(Expr->getOperand(i));
> -
> -      if (!Op.isValid())
> -        return ValidatorResult(SCEVType::INVALID);
> -
> -      Return.type = std::max(Return.type, Op.type);
> -    }
> -
> -    return Return;
> -  }
> -
> -  struct ValidatorResult visitUMaxExpr(const SCEVUMaxExpr* Expr) {
> -    // We do not support unsigned operations. If 'Expr' is constant during Scop
> -    // execution we treat this as a parameter, otherwise we bail out.
> -    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> -      ValidatorResult Op = visit(Expr->getOperand(i));
> -
> -      if (!Op.isConstant())
> -        return ValidatorResult(SCEVType::INVALID);
> -    }
> -
> -    return ValidatorResult(SCEVType::PARAM);
> -  }
> -
> -  ValidatorResult visitUnknown(const SCEVUnknown* Expr) {
> -    Value *V = Expr->getValue();
> -
> -    if (isa<UndefValue>(V))
> -      return ValidatorResult(SCEVType::INVALID);
> -
> -    if (BaseAddress) {
> -      if (*BaseAddress)
> -        return ValidatorResult(SCEVType::INVALID);
> -      else
> -        *BaseAddress = V;
> -    }
> -
> -    if (Instruction *I = dyn_cast<Instruction>(Expr->getValue()))
> -      if (R->contains(I))
> -        return ValidatorResult(SCEVType::INVALID);
> -
> -    if (BaseAddress)
> -      return ValidatorResult(SCEVType::PARAM);
> -    else
> -      return ValidatorResult(SCEVType::PARAM);
> -  }
> -};
> -
>  bool ScopDetection::isMaxRegionInScop(const Region &R) const {
>   // The Region is valid only if it could be found in the set.
>   return ValidRegions.count(&R);
> @@ -457,8 +237,8 @@
>     const SCEV *ScevLHS = SE->getSCEV(ICmp->getOperand(0));
>     const SCEV *ScevRHS = SE->getSCEV(ICmp->getOperand(1));
>
> -    bool affineLHS = SCEVValidator::isValid(&Context.CurRegion, ScevLHS, *SE);
> -    bool affineRHS = SCEVValidator::isValid(&Context.CurRegion, ScevRHS, *SE);
> +    bool affineLHS = isAffineExpr(&Context.CurRegion, ScevLHS, *SE);
> +    bool affineRHS = isAffineExpr(&Context.CurRegion, ScevRHS, *SE);
>
>     if (!affineLHS || !affineRHS)
>       INVALID(AffFunc, "Non affine branch in BB: " + BB.getNameStr());
> @@ -499,8 +279,7 @@
>   Value *Ptr = getPointerOperand(Inst), *BasePtr;
>   const SCEV *AccessFunction = SE->getSCEV(Ptr);
>
> -  if (!SCEVValidator::isValid(&Context.CurRegion, AccessFunction, *SE,
> -                                 &BasePtr))
> +  if (!isAffineExpr(&Context.CurRegion, AccessFunction, *SE, &BasePtr))
>     INVALID(AffFunc, "Bad memory address " << *AccessFunction);
>
>   // FIXME: Also check with isValidAffineFunction, as for the moment it is
> @@ -628,7 +407,7 @@
>
>   // Is the loop count affine?
>   const SCEV *LoopCount = SE->getBackedgeTakenCount(L);
> -  if (!SCEVValidator::isValid(&Context.CurRegion, LoopCount, *SE))
> +  if (!isAffineExpr(&Context.CurRegion, LoopCount, *SE))
>     INVALID(LoopBound, "Non affine loop bound '" << *LoopCount << "' in loop: "
>                        << L->getHeader()->getNameStr());
>
>
> Modified: polly/trunk/lib/Support/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/CMakeLists.txt?rev=143960&r1=143959&r2=143960&view=diff
> ==============================================================================
> --- polly/trunk/lib/Support/CMakeLists.txt (original)
> +++ polly/trunk/lib/Support/CMakeLists.txt Mon Nov  7 06:58:54 2011
> @@ -1,5 +1,6 @@
>  add_polly_library(PollySupport
>   AffSCEVItTester.cpp
>   GICHelper.cpp
> +  SCEVValidator.cpp
>   ScopHelper.cpp
>   )
>
> Added: polly/trunk/lib/Support/SCEVValidator.cpp
> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/SCEVValidator.cpp?rev=143960&view=auto
> ==============================================================================
> --- polly/trunk/lib/Support/SCEVValidator.cpp (added)
> +++ polly/trunk/lib/Support/SCEVValidator.cpp Mon Nov  7 06:58:54 2011
> @@ -0,0 +1,231 @@
> +
> +#include "polly/Support/SCEVValidator.h"
> +
> +#include "llvm/Analysis/ScalarEvolution.h"
> +#include "llvm/Analysis/ScalarEvolutionExpressions.h"
> +#include "llvm/Analysis/RegionInfo.h"
> +
> +using namespace llvm;
> +
> +namespace SCEVType {
> +  enum TYPE {INT, PARAM, IV, INVALID};

You should probably document what each stands for, and also document
the fact that the order in which the elements of the enum are arranged is
important as we call max on their value.

> +}
> +
> +struct ValidatorResult {
> +  SCEVType::TYPE type;
> +
> +  ValidatorResult() : type(SCEVType::INVALID) {};
> +
> +  ValidatorResult(const ValidatorResult &vres) {
> +    type = vres.type;
> +  };
> +
> +  ValidatorResult(SCEVType::TYPE type) : type(type) {};
> +
> +  bool isConstant() {
> +    return type == SCEVType::INT || type == SCEVType::PARAM;
> +  }
> +
> +  bool isValid() {
> +    return type != SCEVType::INVALID;
> +  }
> +
> +  bool isIV() {
> +    return type == SCEVType::IV;
> +  }
> +
> +  bool isINT() {
> +    return type == SCEVType::INT;
> +  }
> +};
> +
> +/// Check if a SCEV is valid in a SCoP.
> +struct SCEVValidator
> +  : public SCEVVisitor<SCEVValidator, struct ValidatorResult> {
> +private:
> +  const Region *R;
> +  ScalarEvolution &SE;
> +  Value **BaseAddress;
> +
> +public:
> +  SCEVValidator(const Region *R, ScalarEvolution &SE,
> +                Value **BaseAddress) : R(R), SE(SE),
> +    BaseAddress(BaseAddress) {};
> +
> +  struct ValidatorResult visitConstant(const SCEVConstant *Constant) {
> +    return ValidatorResult(SCEVType::INT);
> +  }
> +
> +  struct ValidatorResult visitTruncateExpr(const SCEVTruncateExpr* Expr) {
> +    ValidatorResult Op = visit(Expr->getOperand());
> +
> +    // We currently do not represent a truncate expression as an affine
> +    // expression. If it is constant during Scop execution, we treat it as a
> +    // parameter, otherwise we bail out.
> +    if (Op.isConstant())
> +      return ValidatorResult(SCEVType::PARAM);
> +
> +    return ValidatorResult (SCEVType::INVALID);
> +  }
> +
> +  struct ValidatorResult visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) {
> +    ValidatorResult Op = visit(Expr->getOperand());
> +
> +    // We currently do not represent a zero extend expression as an affine
> +    // expression. If it is constant during Scop execution, we treat it as a
> +    // parameter, otherwise we bail out.
> +    if (Op.isConstant())
> +      return ValidatorResult (SCEVType::PARAM);
> +
> +    return ValidatorResult(SCEVType::INVALID);
> +  }
> +
> +  struct ValidatorResult visitSignExtendExpr(const SCEVSignExtendExpr* Expr) {
> +    // We currently allow only signed SCEV expressions. In the case of a
> +    // signed value, a sign extend is a noop.
> +    //
> +    // TODO: Reconsider this when we add support for unsigned values.
> +    return visit(Expr->getOperand());
> +  }
> +
> +  struct ValidatorResult visitAddExpr(const SCEVAddExpr* Expr) {
> +    ValidatorResult Return(SCEVType::INT);
> +
> +    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> +      ValidatorResult Op = visit(Expr->getOperand(i));
> +
> +      if (!Op.isValid())
> +        return ValidatorResult(SCEVType::INVALID);
> +
> +      Return.type = std::max(Return.type, Op.type);
> +    }
> +
> +    // TODO: Check for NSW and NUW.
> +    return Return;
> +  }
> +
> +  struct ValidatorResult visitMulExpr(const SCEVMulExpr* Expr) {
> +    ValidatorResult Return(SCEVType::INT);
> +
> +    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> +      ValidatorResult Op = visit(Expr->getOperand(i));
> +
> +      if (Op.type == SCEVType::INT)
> +        continue;
> +
> +      if (Op.type == SCEVType::INVALID || Return.type != SCEVType::INT)
> +        return ValidatorResult(SCEVType::INVALID);
> +
> +      Return.type = Op.type;
> +    }
> +
> +    // TODO: Check for NSW and NUW.
> +    return Return;
> +  }
> +
> +  struct ValidatorResult visitUDivExpr(const SCEVUDivExpr* Expr) {
> +    ValidatorResult LHS = visit(Expr->getLHS());
> +    ValidatorResult RHS = visit(Expr->getRHS());
> +
> +    // We currently do not represent a unsigned devision as an affine
> +    // expression. If the division is constant during Scop execution we treat it
> +    // as a parameter, otherwise we bail out.
> +    if (LHS.isConstant() && RHS.isConstant())
> +      return ValidatorResult(SCEVType::PARAM);
> +
> +    return ValidatorResult(SCEVType::INVALID);
> +  }
> +
> +  struct ValidatorResult visitAddRecExpr(const SCEVAddRecExpr* Expr) {
> +    if (!Expr->isAffine())
> +      return ValidatorResult(SCEVType::INVALID);
> +
> +    ValidatorResult Start = visit(Expr->getStart());
> +    ValidatorResult Recurrence = visit(Expr->getStepRecurrence(SE));
> +
> +    if (!Start.isValid() || !Recurrence.isValid() || Recurrence.isIV())
> +      return ValidatorResult(SCEVType::INVALID);
> +
> +
> +    if (!R->contains(Expr->getLoop())) {
> +      if (Start.isIV())
> +        return ValidatorResult(SCEVType::INVALID);
> +      else
> +        return ValidatorResult(SCEVType::PARAM);
> +    }
> +
> +    if (!Recurrence.isINT())
> +      return ValidatorResult(SCEVType::INVALID);
> +
> +    return ValidatorResult(SCEVType::IV);
> +  }
> +
> +  struct ValidatorResult visitSMaxExpr(const SCEVSMaxExpr* Expr) {
> +    ValidatorResult Return(SCEVType::INT);
> +
> +    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> +      ValidatorResult Op = visit(Expr->getOperand(i));
> +
> +      if (!Op.isValid())
> +        return ValidatorResult(SCEVType::INVALID);
> +
> +      Return.type = std::max(Return.type, Op.type);
> +    }
> +
> +    return Return;
> +  }
> +
> +  struct ValidatorResult visitUMaxExpr(const SCEVUMaxExpr* Expr) {
> +    // We do not support unsigned operations. If 'Expr' is constant during Scop
> +    // execution we treat this as a parameter, otherwise we bail out.
> +    for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
> +      ValidatorResult Op = visit(Expr->getOperand(i));
> +
> +      if (!Op.isConstant())
> +        return ValidatorResult(SCEVType::INVALID);
> +    }
> +
> +    return ValidatorResult(SCEVType::PARAM);
> +  }
> +
> +  ValidatorResult visitUnknown(const SCEVUnknown* Expr) {
> +    Value *V = Expr->getValue();
> +
> +    if (isa<UndefValue>(V))
> +      return ValidatorResult(SCEVType::INVALID);
> +
> +    if (BaseAddress) {
> +      if (*BaseAddress)
> +        return ValidatorResult(SCEVType::INVALID);
> +      else
> +        *BaseAddress = V;
> +    }
> +
> +    if (Instruction *I = dyn_cast<Instruction>(Expr->getValue()))
> +      if (R->contains(I))
> +        return ValidatorResult(SCEVType::INVALID);
> +
> +    if (BaseAddress)
> +      return ValidatorResult(SCEVType::PARAM);
> +    else
> +      return ValidatorResult(SCEVType::PARAM);
> +  }
> +};
> +
> +namespace polly {
> +  bool isAffineExpr(const Region *R, const SCEV *Expr, ScalarEvolution &SE,
> +                    Value **BaseAddress) {
> +    if (isa<SCEVCouldNotCompute>(Expr))
> +      return false;
> +
> +    if (BaseAddress)
> +      *BaseAddress = NULL;
> +
> +    SCEVValidator Validator(R, SE, BaseAddress);
> +    ValidatorResult Result = Validator.visit(Expr);
> +
> +    return Result.isValid();
> +  }
> +}
> +
> +
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Sebastian Pop
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

From evan.cheng at apple.com  Tue Nov 15 23:42:30 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 15 Nov 2011 21:42:30 -0800
Subject: [llvm-commits] [llvm] r144705 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp
 test/CodeGen/X86/dec-eflags-lower.ll
In-Reply-To: <20111115215753.791CE2A6C131@llvm.org>
References: <20111115215753.791CE2A6C131@llvm.org>
Message-ID: <E77F49AA-94E0-418F-9DED-C435D069F19A@apple.com>

Hi Pete,

Comments below.

On Nov 15, 2011, at 1:57 PM, Pete Cooper wrote:

> Author: pete
> Date: Tue Nov 15 15:57:53 2011
> New Revision: 144705
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=144705&view=rev
> Log:
> Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
> by later instructions.
> 
> Only done for DEC64m right now.
> 
> Fixes <rdar://problem/6172640>
> 
> Added:
>    llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=144705&r1=144704&r2=144705&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Nov 15 15:57:53 2011
> @@ -948,6 +948,11 @@
>     if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
>       return NULL;
> 
> +    // unfolding an x86 DEC64m operation results in store, dec, load which
> +    // can't be handled here so quit
> +    if (NewNodes.size() == 3)
> +      return NULL;

I don't think this is the right way. Can't you detect it's folding both a load and a store before doing a bunch of work?


> +
>     DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n");
>     assert(NewNodes.size() == 2 && "Expected a load folding node!");
> 
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=144705&r1=144704&r2=144705&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Nov 15 15:57:53 2011
> @@ -2216,6 +2216,63 @@
>     }
>     break;
>   }
> +  case ISD::STORE: {

Please add comments to show why we need c++ code to isel this. Preferably with a example of what the isel pattern *should* look like when we get around to adding the tablegen syntax.

Thanks,

Evan

> +    StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
> +    SDValue Chain = StoreNode->getOperand(0);
> +    SDValue StoredVal = StoreNode->getOperand(1);
> +    SDValue Address = StoreNode->getOperand(2);
> +    SDValue Undef = StoreNode->getOperand(3);
> +
> +    if (StoreNode->getMemOperand()->getSize() != 8 ||
> +        Undef->getOpcode() != ISD::UNDEF ||
> +        Chain->getOpcode() != ISD::LOAD ||
> +        StoredVal->getOpcode() != X86ISD::DEC ||
> +        StoredVal.getResNo() != 0 ||
> +        StoredVal->getOperand(0).getNode() != Chain.getNode())
> +      break;
> +
> +    //OPC_CheckPredicate, 1, // Predicate_nontemporalstore
> +    if (StoreNode->isNonTemporal())
> +      break;
> +
> +    LoadSDNode *LoadNode = cast<LoadSDNode>(Chain.getNode());
> +    if (LoadNode->getOperand(1) != Address ||
> +        LoadNode->getOperand(2) != Undef)
> +      break;
> +
> +    if (!ISD::isNormalLoad(LoadNode))
> +      break;
> +
> +    if (!ISD::isNormalStore(StoreNode))
> +      break;
> +
> +    // check load chain has only one use (from the store)
> +    if (!Chain.hasOneUse())
> +      break;
> +
> +    // Merge the input chains if they are not intra-pattern references.
> +    SDValue InputChain = LoadNode->getOperand(0);
> +
> +    SDValue Base, Scale, Index, Disp, Segment;
> +    if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
> +                    Base, Scale, Index, Disp, Segment))
> +      break;
> +
> +    MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
> +    MemOp[0] = StoreNode->getMemOperand();
> +    MemOp[1] = LoadNode->getMemOperand();
> +    const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
> +    MachineSDNode *Result = CurDAG->getMachineNode(X86::DEC64m,
> +                                                   Node->getDebugLoc(),
> +                                                   MVT::i32, MVT::Other, Ops,
> +                                                   array_lengthof(Ops));
> +    Result->setMemRefs(MemOp, MemOp + 2);
> +
> +    ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
> +    ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
> +
> +    return Result;
> +  }
>   }
> 
>   SDNode *ResNode = SelectCode(Node);
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144705&r1=144704&r2=144705&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Nov 15 15:57:53 2011
> @@ -8263,8 +8263,10 @@
>     // climbing the DAG back to the root, and it doesn't seem to be worth the
>     // effort.
>     for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
> -           UE = Op.getNode()->use_end(); UI != UE; ++UI)
> -      if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
> +         UE = Op.getNode()->use_end(); UI != UE; ++UI)
> +      if (UI->getOpcode() != ISD::CopyToReg &&
> +          UI->getOpcode() != ISD::SETCC &&
> +          UI->getOpcode() != ISD::STORE)
>         goto default_case;
> 
>     if (ConstantSDNode *C =
> 
> Added: llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll?rev=144705&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll Tue Nov 15 15:57:53 2011
> @@ -0,0 +1,29 @@
> +; RUN: llc < %s -march=x86-64 | FileCheck %s
> +
> +%struct.obj = type { i64 }
> +
> +define void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
> +entry:
> +; CHECK: decq	(%rdi)
> +; CHECK-NEXT: je
> +  %refcnt = getelementptr inbounds %struct.obj* %o, i64 0, i32 0
> +  %0 = load i64* %refcnt, align 8, !tbaa !0
> +  %dec = add i64 %0, -1
> +  store i64 %dec, i64* %refcnt, align 8, !tbaa !0
> +  %tobool = icmp eq i64 %dec, 0
> +  br i1 %tobool, label %if.end, label %return
> +
> +if.end:                                           ; preds = %entry
> +  %1 = bitcast %struct.obj* %o to i8*
> +  tail call void @free(i8* %1)
> +  br label %return
> +
> +return:                                           ; preds = %entry, %if.end
> +  ret void
> +}
> +
> +declare void @free(i8* nocapture) nounwind
> +
> +!0 = metadata !{metadata !"long", metadata !1}
> +!1 = metadata !{metadata !"omnipotent char", metadata !2}
> +!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From atrick at apple.com  Tue Nov 15 23:58:58 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 15 Nov 2011 21:58:58 -0800
Subject: [llvm-commits] [PATCH] Loop unrolling for run-time trip counts
In-Reply-To: <024501cc9f30$c8edb550$5ac91ff0$@org>
References: <01a401cc9cda$fa184580$ee48d080$@org>
	<F9878BB1-70EF-4589-B93F-FB08EB369E29@apple.com>
	<024501cc9f30$c8edb550$5ac91ff0$@org>
Message-ID: <A401A377-F48E-4577-929E-2D0DE2812AA0@apple.com>

On Nov 9, 2011, at 2:41 PM, Brendon Cahoon wrote:
> Hi Andy,
>  
> Thanks for the reply.  Much appreciated.
>  
> I agree that the optimization may not help every target, and can cause some performance problems.  Target specific information would be a huge help.  Since our target is a VLIW, we have found the pass to be useful on several SPEC2K and EEMBC benchmarks.  We also see some improvements on ARM for some of the programs in those benchmark suites.  But, we have seen some performance regressions especially on ARM due to an increase in register spills, which we?re investigating.   I haven?t done any significant performance analysis for x86 with the patch though.
>  
> I *think* I?m updating the preserved info correctly.  I believe the dominator information gets recomputed by the existing loop unrolling code.  I will run tests with the ?verify-dom-info and ?verify-loop-info flags though.  I hadn?t tried that.  I?ll also try your suggestions about disabling the normal unrolling code for compile-time loops, and I can run some more tests when changing loop count.
>  
> Thanks again,
> -- Brendon
>  
> --
> Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
>  
> From: Andrew Trick [mailto:atrick at apple.com] 
> Sent: Wednesday, November 09, 2011 12:36 PM
> To: Brendon Cahoon
> Subject: Re: [llvm-commits] [PATCH] Loop unrolling for run-time trip counts
>  
> On Nov 6, 2011, at 3:22 PM, Brendon Cahoon wrote:
> Hi,
>  
> This patch contains code to unroll loops that contain a run-time trip count.  It extends the existing code, in the LoopUnroll and LoopUnrollPass classes, that unrolls loops with compile-time trip counts.
>  
> The ability to unroll loops with run-time trip counts using this patch is turned off by default.  To enable the transformation, I added an option, ?unroll-runtime.  It?s probably best to keep it disabled for now since some programs may degrade in performance with the option enabled.  We?re hoping that some more tuning will help minimize any performance regressions.  Of course, we do see performance improvements as well.
>  
> I tested llvm with the patch and it passes ?make check-all? and there are no regressions in test-suite when using the ?simple? test target.  I have also enabled the option and tested using test-suite, and there are no regressions with the option enabled.    With the option enabled, there will be some errors with the tests when running ?make check-all? for two reasons.  The existing tests assume that there is no loop unrolling for run-time trip counts, and my implementation requires that loop simplify is run afterward (I am planning on fixing this issue).  I?ve also tested the code on a different test suite for ARM and our soon to be added backend.
>  
> This implementation works by using the existing loop unrolling code to actually unroll the loop by some unroll factor (the default is 8 iterations).   This patch generates code prior to the loop to compute the number of extra iterations to execute before entering the unrolled loop.  The number of extra iterations is the run-time trip count modulo the unroll factor.  We generate code to check the number of extra iterations and branch to the extra copies of the loop body that  execute the extra iterations before entering the unrolled loop.  We generate an if-then-else sequence, which may get converted to a switch statement by LLVM.  The patch generates ?unroll factor ? 1? copies of the loop body prior to the loop to execute these extra iterations. 
>  
> This implementation only allow unroll factors that are a power to 2 to reduce the cost of computing the number of extra iterations.  There are other limitations in implementation including only allowing loops with a single exit that occurs in the latch block.  There is certainly some room for improving the code, but it works and improves performance on some actual benchmarks.
>  
> The patch includes changes to the following files:
>    lib/Transforms/Scalar/LoopUnrollPass.cpp
>    lib/Transfoms/Utils/LoopUnroll.cpp
>    include/llvm/Transforms/Utils/UnrollLoop.h
>  
> And new files in the test directory: test/Transforms/LoopUnroll/runtime-loop[1-3].ll
>  
> I appreciate any comments, questions, etc. on the code.
>  
> Thanks,
> -- Brendon Cahoon
> --
> Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
>  
>  
> Brendon,
>  
> Thanks for the patch. I see no problem adding this as an experimental framework given the testing you've done and unit tests you've provided. I suspect the optimization will be useful on some targets if branch profiles are available, logic is added to detect optimizations that can be exploited by unrolling, and/or target-specific heuristics can be queried to determine which loops may benefit.
>  
> Before I dig into code review, let me ask a high level question. Creating pre/post loops complicates the CFG. Are you sure you're updating the preserved passes properly, including DominatorTree and LoopInfo. Please run the test suite with forced runtime unrolling plus -verify-dom-info and -verify-loop-info. To further stress your framework, make sure constant trip unrolling is disabled in your runs, so your unroller processes these too. I would also try with a small unroll (e.g. 2) count to stress the loop body and a large count to stress prolog/epilog.

For the purpose of code review, I'll ignore the issue of
unroll-runtime profitability, which is obviously left for later. I
will say that this is only half the framework because to achieve
data-alignment we would need to emit an epilog as well. Also, I
misread your original message, and assumed you were adding a prolog
*loop*. That would be nice for targets that care about code
size. There are cases when unrolling the main loop can be done without
increasing the size of the loop body. Your design would not always be
well suited for those cases. On the other hand, your design is a much
simpler CFG transform. We have less SSA/LoopInfo updating to worry
about this way.

Never mind my earlier comment about DominatorTree. I forgot we always
recompute it. You're welcome to fix that :)

It does seem like your transform should preserve LoopSimplify. I'm
guessing you just need a unique loop exit block--just split the
exit. Can you please do that?

In general, your implementation looks quite nice.

I am concerned that you're doubling the size of LoopUnroll.cpp for a
feature that most people won't need to look at. I'd be ok with you
creating a new .cpp file. Or at least make it blatantly obvious that
all the new code is specific to runtime-unroll. For example, you can
add function-level comments like "Support for -runtime-unroll", and
code sections like:
//===----------------------------------------------------------------------===//
// Implementation of -runtime-unroll.
//===----------------------------------------------------------------------===//
<your code>
//===----------------------------------------------------------------------===//
// Driver for loop unrolling transformations.
//===----------------------------------------------------------------------===//
...

Formatting: You have two 80-col violations, but otherwise looks great.

Typo:
+ // ... loop
+ // loop prologue

---
In EmitRuntimePrologueFixup:

+///    extraiters = tripcount % loopfactor
+///    if (extraiters == 0) jump Loop:
+///    if (extraiters == loopfactor) jump L1
+///    if (extraiters == loopfactor-1) jump L2

You may want to comment that you expect a later pass to convert this
to a switch.

Before you erase PH->terminator, maybe you should assert that it has one
successor pointing to PEnd.

+ std::vector<BasicBlock*> NewBlocks(LoopBlocks.size());

No need to initialize the vector, then immediately clear it. You can use
NewBlocks.reserve(LoopBlocks.size()).

+  for (unsigned i = Count-1; i > 0; --i) {

This is a large, complex loop. To be more self-documenting, use a
meaningful variable like "leftOverIters". Then it will be clear why
you're counting down, and the nested loop won't hide the variable.

+    if (i != Count-1) {

My personal preference, I'd like to see the i == Count-1 case first
since that's what happens first.

---
In CloneLoopBlocks:

+    LPM->cloneBasicBlockSimpleAnalysis(LoopBlocks[j], NewBB, L);

I'm not sure this makes sense given that the new block is in the
parent loop. It may happen to work for the only user, LICM. Since
you're not doing anything to enforce safety in the API, I would add
comments in your code, in the API declaration, and in LICM that 'L' is
the "From" block's loop, not necessarily the "To" block's loop.

+       if (InsertTop != 0) {

Why isn't InsertTop set to PH for the first copy?

+    // Update our running map of newest clones
+    for (ValueToValueMapTy::iterator VI = VMap.begin(), VE = VMap.end();

If possible, avoid copying the map. For example, call LVMap.swap(VMap)
later, after you're done with the current loop iteration, before
RemapInstrucion. You might need more explicit handling of header phis
and latch terminators, but it's probably worth it both in efficiency
and code clarity. I realize the current unroller does this, but it
think the copying wasn't removed only because it does membership
checks on LastValueMap, which you don't need.

In runtime-loop3.ll please use FileCheck instead of grep. We're trying
to minimize dependence on external tools in the unit tests.

-Andy
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From geek4civic at gmail.com  Wed Nov 16 01:05:58 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Wed, 16 Nov 2011 16:05:58 +0900
Subject: [llvm-commits] [llvm] r141907 -
	/llvm/trunk/lib/Support/Windows/RWMutex.inc
In-Reply-To: <20111013231057.0E72C312800A@llvm.org>
References: <20111013231057.0E72C312800A@llvm.org>
Message-ID: <CADiQthN5Dv0XJRrVcUmAFaipLAyzLb4TcHixCrCWTM3p9LcBNA@mail.gmail.com>

Bill please revert it on release_30, if we should resolve compile
error on Visual Studio 2005.

It is not needed to revert on ToT. IMO, we have to introduce NT6
header checking in future.

...Takumi

2011/10/14 Michael J. Spencer <bigcheesegs at gmail.com>:
> Author: mspencer
> Date: Thu Oct 13 18:10:56 2011
> New Revision: 141907
>
> URL: http://llvm.org/viewvc/llvm-project?rev=141907&view=rev
> Log:
> Support/Windows: Add efficent RW mutex on Windows. Patch by Aaron Ballman!
>
> Modified:
> ? ?llvm/trunk/lib/Support/Windows/RWMutex.inc
>
> Modified: llvm/trunk/lib/Support/Windows/RWMutex.inc
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/RWMutex.inc?rev=141907&r1=141906&r2=141907&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Support/Windows/RWMutex.inc (original)
> +++ llvm/trunk/lib/Support/Windows/RWMutex.inc Thu Oct 13 18:10:56 2011
> @@ -18,39 +18,115 @@
>
> ?#include "Windows.h"
>
> -// FIXME: Windows does not have reader-writer locks pre-Vista. ?If you want
> -// real reader-writer locks, you a threads implementation for Windows.
> -
> ?namespace llvm {
> ?using namespace sys;
>
> +// Windows has slim read-writer lock support on Vista and higher, so we
> +// will attempt to load the APIs. ?If they exist, we will use them, and
> +// if not, we will fall back on critical sections. ?When we drop support
> +// for XP, we can stop lazy-loading these APIs and just use them directly.
> +#if defined(__MINGW32__)
> + ?// Taken from WinNT.h
> + ?typedef struct _RTL_SRWLOCK {
> + ? ?PVOID Ptr;
> + ?} RTL_SRWLOCK, *PRTL_SRWLOCK;
> +
> + ?// Taken from WinBase.h
> + ?typedef RTL_SRWLOCK SRWLOCK, *PSRWLOCK;
> +#endif
> +
> +static VOID (WINAPI *fpInitializeSRWLock)(PSRWLOCK lock) = NULL;
> +static VOID (WINAPI *fpAcquireSRWLockExclusive)(PSRWLOCK lock) = NULL;
> +static VOID (WINAPI *fpAcquireSRWLockShared)(PSRWLOCK lock) = NULL;
> +static VOID (WINAPI *fpReleaseSRWLockExclusive)(PSRWLOCK lock) = NULL;
> +static VOID (WINAPI *fpReleaseSRWLockShared)(PSRWLOCK lock) = NULL;
> +
> +static bool sHasSRW = false;
> +
> +static bool loadSRW() {
> + ?static bool sChecked = false;
> + ?if (!sChecked) {
> + ? ?sChecked = true;
> +
> + ? ?HMODULE hLib = ::LoadLibrary(TEXT("Kernel32"));
> + ? ?if (hLib) {
> + ? ? ?fpInitializeSRWLock =
> + ? ? ? ?(VOID (WINAPI *)(PSRWLOCK))::GetProcAddress(hLib,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "InitializeSRWLock");
> + ? ? ?fpAcquireSRWLockExclusive =
> + ? ? ? ?(VOID (WINAPI *)(PSRWLOCK))::GetProcAddress(hLib,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "AcquireSRWLockExclusive");
> + ? ? ?fpAcquireSRWLockShared =
> + ? ? ? ?(VOID (WINAPI *)(PSRWLOCK))::GetProcAddress(hLib,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "AcquireSRWLockShared");
> + ? ? ?fpReleaseSRWLockExclusive =
> + ? ? ? ?(VOID (WINAPI *)(PSRWLOCK))::GetProcAddress(hLib,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "ReleaseSRWLockExclusive");
> + ? ? ?fpReleaseSRWLockShared =
> + ? ? ? ?(VOID (WINAPI *)(PSRWLOCK))::GetProcAddress(hLib,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "ReleaseSRWLockShared");
> + ? ? ?::FreeLibrary(hLib);
> +
> + ? ? ? ? if (fpInitializeSRWLock != NULL) {
> + ? ? ? ? ? sHasSRW = true;
> + ? ? ? ? }
> + ? ?}
> + ?}
> + ?return sHasSRW;
> +}
> +
> ?RWMutexImpl::RWMutexImpl() {
> - ?data_ = calloc(1, sizeof(CRITICAL_SECTION));
> - ?InitializeCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> + ?if (loadSRW()) {
> + ? ?data_ = calloc(1, sizeof(SRWLOCK));
> + ? ?fpInitializeSRWLock(static_cast<PSRWLOCK>(data_));
> + ?} else {
> + ? ?data_ = calloc(1, sizeof(CRITICAL_SECTION));
> + ? ?InitializeCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> + ?}
> ?}
>
> ?RWMutexImpl::~RWMutexImpl() {
> - ?DeleteCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> - ?free(data_);
> + ?if (sHasSRW) {
> + ? ?// Nothing to do in the case of slim reader/writers
> + ?} else {
> + ? ?DeleteCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> + ? ?free(data_);
> + ?}
> ?}
>
> ?bool RWMutexImpl::reader_acquire() {
> - ?EnterCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> + ?if (sHasSRW) {
> + ? ?fpAcquireSRWLockShared(static_cast<PSRWLOCK>(data_));
> + ?} else {
> + ? ?EnterCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> + ?}
> ? return true;
> ?}
>
> ?bool RWMutexImpl::reader_release() {
> - ?LeaveCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> + ?if (sHasSRW) {
> + ? ?fpReleaseSRWLockShared(static_cast<PSRWLOCK>(data_));
> + ?} else {
> + ? ?LeaveCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> + ?}
> ? return true;
> ?}
>
> ?bool RWMutexImpl::writer_acquire() {
> - ?EnterCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> + ?if (sHasSRW) {
> + ? ?fpAcquireSRWLockExclusive(static_cast<PSRWLOCK>(data_));
> + ?} else {
> + ? ?EnterCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> + ?}
> ? return true;
> ?}
>
> ?bool RWMutexImpl::writer_release() {
> - ?LeaveCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> + ?if (sHasSRW) {
> + ? ?fpReleaseSRWLockExclusive(static_cast<PSRWLOCK>(data_));
> + ?} else {
> + ? ?LeaveCriticalSection(static_cast<LPCRITICAL_SECTION>(data_));
> + ?}
> ? return true;
> ?}
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From geek4civic at gmail.com  Wed Nov 16 01:09:07 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Wed, 16 Nov 2011 16:09:07 +0900
Subject: [llvm-commits] [llvm] r143876 -
	/llvm/trunk/lib/Support/Windows/Program.inc
In-Reply-To: <20111106164546.AC31E2A6C12C@llvm.org>
References: <20111106164546.AC31E2A6C12C@llvm.org>
Message-ID: <CADiQthNwgkDtJBQaK9uwXd3014vHcnPHZLZ=OuN2WhvQzs6S8Q@mail.gmail.com>

Bill, I am happier if you picked it up into release_30.
It resolves a few test failures.

I think it is trivial. :)

...Takumi

2011/11/7 Peter Collingbourne <peter at pcc.me.uk>:
> Author: pcc
> Date: Sun Nov ?6 10:45:46 2011
> New Revision: 143876
>
> URL: http://llvm.org/viewvc/llvm-project?rev=143876&view=rev
> Log:
> Return only the least significant 8 bits of the exit status from
> Process::Wait on Windows (mimicing POSIX behaviour).
>
> Modified:
> ? ?llvm/trunk/lib/Support/Windows/Program.inc
>
> Modified: llvm/trunk/lib/Support/Windows/Program.inc
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/Program.inc?rev=143876&r1=143875&r2=143876&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Support/Windows/Program.inc (original)
> +++ llvm/trunk/lib/Support/Windows/Program.inc Sun Nov ?6 10:45:46 2011
> @@ -367,7 +367,7 @@
> ? ? return -2;
> ? }
>
> - ?return status;
> + ?return status & 0377;
> ?}
>
> ?bool
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From dschuff at google.com  Tue Nov 15 19:26:02 2011
From: dschuff at google.com (Derek Schuff)
Date: Tue, 15 Nov 2011 17:26:02 -0800
Subject: [llvm-commits] Proposal/patch: Enable bitcode streaming
In-Reply-To: <7A6CF9E2-C5B7-45D4-AE10-185BA8EC3BD7@apple.com>
References: <CAAEAhvci4uJmsT4b1ibkG57qmzAesDdPQejmhAVLEmFd_FzyOg@mail.gmail.com>
	<7A6CF9E2-C5B7-45D4-AE10-185BA8EC3BD7@apple.com>
Message-ID: <CAAEAhvc69xQGByGH4KGUrMTrDmN3cqRc3fm2_cmeJGVX=d1NHw@mail.gmail.com>

There's a small difference, about 2.5%

Here's a 45MB bitcode file:
time bin/llvm-dis -disable-output
/ulg/naclgit/native_client/toolchain/hg-build-newlib/llvm-sb-universal-srpc/Release+Asserts/bin/llc---linked.pre_opt.pexe

real    0m3.055s
user    0m2.750s
sys     0m0.290s

new:
time bin/llvm-dis -disable-output
/ulg/naclgit/native_client/toolchain/hg-build-newlib/llvm-sb-universal-srpc/Release+Asserts/bin/llc---linked.pre_opt.pexe

real    0m3.126s
user    0m2.860s
sys     0m0.260s



On Tue, Nov 15, 2011 at 4:37 PM, Chris Lattner <clattner at apple.com> wrote:

> Hi Derek,
>
> Have you measured the performance impact of this patch on the
> non-streaming case?  How much slower does "llvm-dis -disable-output foo.bc"
> go (with a release build)?
>
> -Chris
>
> On Nov 9, 2011, at 4:57 PM, Derek Schuff wrote:
>
> Hello all,
> The following is a proposal (and a prototype patch) to enable bitcode
> streaming. The overall goal is to be able to overlap bitcode
> reading/download with compilation, a functionality useful obviously for
> pnacl and renderscript but also potentially for any situation where the
> interface between the frontend and backend is something other than a file.
>
> In the current state of the world, at a high level, there are 2 things
> keeping this from happening. The first is that BitcodeReader construction
> takes a MemoryBuffer which it expects to be filled with bitcode, and inside
> BitcodeReader, the BitstreamCursor (which is the primary interface to the
> bitcode itself) gets pointers to the bitcode in memory, and does all of its
> magic with pointer arithmetic. The second issue is that in
> BitcodeReader::ParseModule (which is run when right after the Module and
> BitcodeReader objects are created), the reader makes a pass over the entire
> bitcode file. This step does everything except read the function bodies,
> but it records the bit locations of each function for future
> materialization.
>
> High-level change description:
> This patch creates a class called BitcodeStream, which is a very simple
> interface with one method (GetBytes), which fetches the requested number of
> bytes from the stream, and writes them into the requested destination. This
> method may block the calling thread if there are not yet enough bytes
> available in the stream buffer (similarly to a stdin or socket read).
>
> The first issue above is addressed by introducing the BitstreamVector, an
> abstraction that wraps the bitcode in memory. Instead of using pointers,
> the BitstreamCursor uses indices and gets bitcode bytes by indexing (i.e.
> operator[] ) the BitstreamVector. When streaming is not used, the
> BitstreamVector itself keeps pointers to the start and end of the backing
> MemoryBuffer and the indexing operator is just a pointer dereference. For
> streaming use, the BitstreamVector has a BitcodeStream object. If a byte is
> requested that has not yet been fetched, it calls GetBytes to get more,
> until it has enough to return the requested byte.
> This model of allowing any byte to be requested and blocking the caller
> has the advantage that there is no structural/architectural change required
> at this lowest level, nor at the high level (A FunctionPassManager is used
> to iterate over all the functions and compile each one).
>
> The second issue is solved by 2 simple changes. The first is in
> ParseModule. Instead of a single pass over all the bitcode, ParseModule
> becomes resumable.  ParseModule will do its normal handling for top-level
> records, type table blocks, metadata, etc, but if streaming is in use, it
> will save its state and return as soon as a function subblock is
> encountered (rather than saving its location and skipping over it). Each
> subsequent time it is called, it bookmarks and skips one function block.
> Later, when a function needs to be materialized, if the function body has
> been seen already, then materialization is the same as before. Otherwise,
> Materialize will keep calling ParseModule (each time bookmarking and
> skipping one function body) until the requested function is found. The one
> other change required to make this work simply is that the bitcode writer
> writes function bodies as the last subblock (currently the attachment
> metadata and value symbol table are written after the function bodies).
>
> The prototype patch is attached and can also be viewed online at
> http://codereview.chromium.org/8393017/ . Feedback is welcome, as well as
> guidance from the relevant code owners/reviewers regarding what the next
> step needs to be toward committing this.
>
> Thanks,
> -Derek
> <bitcode_streaming_r144247.diff>
> _______________________________________________
>
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
>
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From bob.wilson at apple.com  Wed Nov 16 01:12:01 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 16 Nov 2011 07:12:01 -0000
Subject: [llvm-commits] [llvm] r144782 -
	/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
Message-ID: <20111116071201.120912A6C134@llvm.org>

Author: bwilson
Date: Wed Nov 16 01:12:00 2011
New Revision: 144782

URL: http://llvm.org/viewvc/llvm-project?rev=144782&view=rev
Log:
Update the SP in the SjLj jmpbuf whenever it changes.  <rdar://problem/10444602>

This same basic code was in the older version of the SjLj exception handling,
but it was removed in the recent revisions to that code.  It needs to be there.

Modified:
    llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=144782&r1=144781&r2=144782&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Wed Nov 16 01:12:00 2011
@@ -48,10 +48,10 @@
     Constant *BuiltinSetjmpFn;
     Constant *FrameAddrFn;
     Constant *StackAddrFn;
+    Constant *StackRestoreFn;
     Constant *LSDAAddrFn;
     Value *PersonalityFn;
     Constant *CallSiteFn;
-    Constant *DispatchSetupFn;
     Constant *FuncCtxFn;
     Value *CallSite;
   public:
@@ -107,11 +107,10 @@
                           (Type *)0);
   FrameAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::frameaddress);
   StackAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::stacksave);
+  StackRestoreFn = Intrinsic::getDeclaration(&M, Intrinsic::stackrestore);
   BuiltinSetjmpFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_setjmp);
   LSDAAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_lsda);
   CallSiteFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_callsite);
-  DispatchSetupFn
-    = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_dispatch_setup);
   FuncCtxFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_functioncontext);
   PersonalityFn = 0;
 
@@ -460,6 +459,25 @@
                                         EntryBB->getTerminator());
   Register->setDoesNotThrow();
 
+  // Following any allocas not in the entry block, update the saved SP in the
+  // jmpbuf to the new value.
+  for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
+    if (BB == F.begin())
+      continue;
+    for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
+      if (CallInst *CI = dyn_cast<CallInst>(I)) {
+        if (CI->getCalledFunction() != StackRestoreFn)
+          continue;
+      } else if (!isa<AllocaInst>(I)) {
+        continue;
+      }
+      Instruction *StackAddr = CallInst::Create(StackAddrFn, "sp");
+      StackAddr->insertAfter(I);
+      Instruction *StoreStackAddr = new StoreInst(StackAddr, StackPtr, true);
+      StoreStackAddr->insertAfter(StackAddr);
+    }
+  }
+
   // Finally, for any returns from this function, if this function contains an
   // invoke, add a call to unregister the function context.
   for (unsigned I = 0, E = Returns.size(); I != E; ++I)



From bob.wilson at apple.com  Wed Nov 16 01:11:58 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 16 Nov 2011 07:11:58 -0000
Subject: [llvm-commits] [llvm] r144781 - in /llvm/trunk/lib/Target/ARM:
 ARMExpandPseudoInsts.cpp ARMISelLowering.cpp ARMISelLowering.h
 ARMInstrInfo.td
Message-ID: <20111116071158.4D9B12A6C133@llvm.org>

Author: bwilson
Date: Wed Nov 16 01:11:57 2011
New Revision: 144781

URL: http://llvm.org/viewvc/llvm-project?rev=144781&view=rev
Log:
Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>

The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal.  The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block.  The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op.  The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.

Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic.  Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.

Modified:
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.h
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=144781&r1=144780&r2=144781&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed Nov 16 01:11:57 2011
@@ -824,7 +824,7 @@
       MI.eraseFromParent();
       return true;
     }
-    case ARM::Int_eh_sjlj_dispatchsetup: {
+    case ARM::eh_sjlj_dispatchsetup: {
       MachineFunction &MF = *MI.getParent()->getParent();
       const ARMBaseInstrInfo *AII =
         static_cast<const ARMBaseInstrInfo*>(TII);

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=144781&r1=144780&r2=144781&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Nov 16 01:11:57 2011
@@ -686,7 +686,6 @@
   if (Subtarget->isTargetDarwin()) {
     setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
     setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
-    setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
     setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
   }
 
@@ -863,7 +862,6 @@
 
   case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
   case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
-  case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
 
   case ARMISD::TC_RETURN:     return "ARMISD::TC_RETURN";
 
@@ -2212,14 +2210,6 @@
 }
 
 SDValue
-ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
-  const {
-  DebugLoc dl = Op.getDebugLoc();
-  return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
-                     Op.getOperand(0), Op.getOperand(1));
-}
-
-SDValue
 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
   DebugLoc dl = Op.getDebugLoc();
   SDValue Val = DAG.getConstant(0, MVT::i32);
@@ -5024,7 +5014,6 @@
   case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
   case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
   case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
-  case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
                                                                Subtarget);
   case ISD::BITCAST:       return ExpandBITCAST(Op.getNode(), DAG);
@@ -5566,52 +5555,6 @@
   return BB;
 }
 
-/// EmitBasePointerRecalculation - For functions using a base pointer, we
-/// rematerialize it (via the frame pointer).
-void ARMTargetLowering::
-EmitBasePointerRecalculation(MachineInstr *MI, MachineBasicBlock *MBB,
-                             MachineBasicBlock *DispatchBB) const {
-  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
-  const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
-  MachineFunction &MF = *MI->getParent()->getParent();
-  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
-  const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
-
-  if (!RI.hasBasePointer(MF)) return;
-
-  MachineBasicBlock::iterator MBBI = MI;
-
-  int32_t NumBytes = AFI->getFramePtrSpillOffset();
-  unsigned FramePtr = RI.getFrameRegister(MF);
-  assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
-         "Base pointer without frame pointer?");
-
-  if (AFI->isThumb2Function())
-    llvm::emitT2RegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6,
-                                 FramePtr, -NumBytes, ARMCC::AL, 0, *AII);
-  else if (AFI->isThumbFunction())
-    llvm::emitThumbRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6,
-                                    FramePtr, -NumBytes, *AII, RI);
-  else
-    llvm::emitARMRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6,
-                                  FramePtr, -NumBytes, ARMCC::AL, 0, *AII);
-
-  if (!RI.needsStackRealignment(MF)) return;
-
-  // If there's dynamic realignment, adjust for it.
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  unsigned MaxAlign = MFI->getMaxAlignment();
-  assert(!AFI->isThumb1OnlyFunction());
-
-  // Emit bic r6, r6, MaxAlign
-  unsigned bicOpc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri;
-  AddDefaultCC(
-    AddDefaultPred(
-      BuildMI(*MBB, MBBI, MI->getDebugLoc(), TII->get(bicOpc), ARM::R6)
-      .addReg(ARM::R6, RegState::Kill)
-      .addImm(MaxAlign - 1)));
-}
-
 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
 /// registers the function context.
 void ARMTargetLowering::
@@ -5646,8 +5589,6 @@
     MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
                              MachineMemOperand::MOStore, 4, 4);
 
-  EmitBasePointerRecalculation(MI, MBB, DispatchBB);
-
   // Load the address of the dispatch MBB into the jump buffer.
   if (isThumb2) {
     // Incoming value: jbuf
@@ -5821,6 +5762,8 @@
                              MachineMemOperand::MOLoad |
                              MachineMemOperand::MOVolatile, 4, 4);
 
+  BuildMI(DispatchBB, dl, TII->get(ARM::eh_sjlj_dispatchsetup));
+
   unsigned NumLPads = LPadList.size();
   if (Subtarget->isThumb2()) {
     unsigned NewVReg1 = MRI->createVirtualRegister(TRC);

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=144781&r1=144780&r2=144781&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Nov 16 01:11:57 2011
@@ -81,7 +81,6 @@
 
       EH_SJLJ_SETJMP,         // SjLj exception handling setjmp.
       EH_SJLJ_LONGJMP,        // SjLj exception handling longjmp.
-      EH_SJLJ_DISPATCHSETUP,  // SjLj exception handling dispatch setup.
 
       TC_RETURN,    // Tail call return pseudo.
 
@@ -410,7 +409,6 @@
                              ISD::ArgFlagsTy Flags) const;
     SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
                                     const ARMSubtarget *Subtarget) const;
     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
@@ -520,9 +518,6 @@
                                                bool signExtend,
                                                ARMCC::CondCodes Cond) const;
 
-    void EmitBasePointerRecalculation(MachineInstr *MI, MachineBasicBlock *MBB,
-                                      MachineBasicBlock *DispatchBB) const;
-
     void SetupEntryBlockForSjLj(MachineInstr *MI,
                                 MachineBasicBlock *MBB,
                                 MachineBasicBlock *DispatchBB, int FI) const;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=144781&r1=144780&r2=144781&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 16 01:11:57 2011
@@ -58,8 +58,6 @@
                                                  SDTCisInt<2>]>;
 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
 
-def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
-
 def SDT_ARMMEMBARRIER     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
@@ -143,9 +141,6 @@
                                SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
                                SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
-def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
-                               SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
-
 
 def ARMMemBarrier     : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
                                [SDNPHasChain]>;
@@ -4674,10 +4669,7 @@
 // handled when the pseudo is expanded (which happens before any passes
 // that need the instruction size).
 let isBarrier = 1, hasSideEffects = 1 in
-def Int_eh_sjlj_dispatchsetup :
- PseudoInst<(outs), (ins GPR:$src), NoItinerary,
-            [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
-              Requires<[IsDarwin]>;
+def eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns



From craig.topper at gmail.com  Wed Nov 16 01:30:47 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Wed, 16 Nov 2011 07:30:47 -0000
Subject: [llvm-commits] [llvm] r144784 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20111116073047.2FBB32A6C133@llvm.org>

Author: ctopper
Date: Wed Nov 16 01:30:46 2011
New Revision: 144784

URL: http://llvm.org/viewvc/llvm-project?rev=144784&view=rev
Log:
Fix the execution domain on a bunch of SSE/AVX instructions.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144784&r1=144783&r2=144784&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Nov 16 01:30:46 2011
@@ -5052,21 +5052,25 @@
        [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
 }
 
-let Predicates = [HasAVX],
-  ExeDomain = SSEPackedDouble in {
-  defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
-                               f128mem, 0>, TB, XD, VEX_4V;
-  defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
-                               f128mem, 0>, TB, OpSize, VEX_4V;
-  defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
-                               f256mem, 0>, TB, XD, VEX_4V;
-  defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
-                               f256mem, 0>, TB, OpSize, VEX_4V;
+let Predicates = [HasAVX] in {
+  let ExeDomain = SSEPackedSingle in {
+    defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
+                                 f128mem, 0>, TB, XD, VEX_4V;
+    defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
+                                 f256mem, 0>, TB, XD, VEX_4V;
+  }
+  let ExeDomain = SSEPackedDouble in {
+    defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
+                                 f128mem, 0>, TB, OpSize, VEX_4V;
+    defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
+                                 f256mem, 0>, TB, OpSize, VEX_4V;
+  }
 }
-let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
-    ExeDomain = SSEPackedDouble in {
+let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
+  let ExeDomain = SSEPackedSingle in
   defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
                               f128mem>, TB, XD;
+  let ExeDomain = SSEPackedDouble in
   defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
                               f128mem>, TB, OpSize;
 }
@@ -5106,29 +5110,37 @@
 }
 
 let Predicates = [HasAVX] in {
-  defm VHADDPS  : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
-                          X86fhadd, 0>, VEX_4V;
-  defm VHADDPD  : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
-                          X86fhadd, 0>, VEX_4V;
-  defm VHSUBPS  : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
-                          X86fhsub, 0>, VEX_4V;
-  defm VHSUBPD  : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
-                          X86fhsub, 0>, VEX_4V;
-  defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
-                          X86fhadd, 0>, VEX_4V;
-  defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
-                          X86fhadd, 0>, VEX_4V;
-  defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
-                          X86fhsub, 0>, VEX_4V;
-  defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
-                          X86fhsub, 0>, VEX_4V;
+  let ExeDomain = SSEPackedSingle in {
+    defm VHADDPS  : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
+                            X86fhadd, 0>, VEX_4V;
+    defm VHSUBPS  : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
+                            X86fhsub, 0>, VEX_4V;
+    defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
+                            X86fhadd, 0>, VEX_4V;
+    defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
+                            X86fhsub, 0>, VEX_4V;
+  }
+  let ExeDomain = SSEPackedDouble in {
+    defm VHADDPD  : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
+                            X86fhadd, 0>, VEX_4V;
+    defm VHSUBPD  : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
+                            X86fhsub, 0>, VEX_4V;
+    defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
+                            X86fhadd, 0>, VEX_4V;
+    defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
+                            X86fhsub, 0>, VEX_4V;
+  }
 }
 
 let Constraints = "$src1 = $dst" in {
-  defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
-  defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
-  defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
-  defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
+  let ExeDomain = SSEPackedSingle in {
+    defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
+    defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
+  }
+  let ExeDomain = SSEPackedDouble in {
+    defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
+    defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
+  }
 }
 
 //===---------------------------------------------------------------------===//
@@ -5837,14 +5849,16 @@
                           addr:$dst)]>, OpSize;
 }
 
-let Predicates = [HasAVX] in {
-  defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
-  def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
-                  (ins VR128:$src1, i32i8imm:$src2),
-                  "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                  []>, OpSize, VEX;
+let ExeDomain = SSEPackedSingle in {
+  let Predicates = [HasAVX] in {
+    defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
+    def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
+                    (ins VR128:$src1, i32i8imm:$src2),
+                    "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                    []>, OpSize, VEX;
+  }
+  defm EXTRACTPS   : SS41I_extractf32<0x17, "extractps">;
 }
-defm EXTRACTPS   : SS41I_extractf32<0x17, "extractps">;
 
 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
@@ -5965,10 +5979,12 @@
                     imm:$src3))]>, OpSize;
 }
 
-let Constraints = "$src1 = $dst" in
-  defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
-let Predicates = [HasAVX] in
-  defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
+let ExeDomain = SSEPackedSingle in {
+  let Constraints = "$src1 = $dst" in
+    defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
+  let Predicates = [HasAVX] in
+    defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
+}
 
 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
           (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
@@ -5985,6 +6001,7 @@
                             X86MemOperand x86memop, RegisterClass RC,
                             PatFrag mem_frag32, PatFrag mem_frag64,
                             Intrinsic V4F32Int, Intrinsic V2F64Int> {
+let ExeDomain = SSEPackedSingle in {
   // Intrinsic operation, reg.
   // Vector intrinsic operation, reg
   def PSr : SS4AIi8<opcps, MRMSrcReg,
@@ -6001,9 +6018,10 @@
                     "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
                     [(set RC:$dst,
                           (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
-                    TA, OpSize,
-                Requires<[HasSSE41]>;
+                    TA, OpSize, Requires<[HasSSE41]>;
+} // ExeDomain = SSEPackedSingle
 
+let ExeDomain = SSEPackedDouble in {
   // Vector intrinsic operation, reg
   def PDr : SS4AIi8<opcpd, MRMSrcReg,
                     (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
@@ -6020,10 +6038,12 @@
                     [(set RC:$dst,
                           (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
                     OpSize;
+} // ExeDomain = SSEPackedDouble
 }
 
 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
                    RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
+let ExeDomain = SSEPackedSingle in {
   // Intrinsic operation, reg.
   // Vector intrinsic operation, reg
   def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
@@ -6038,7 +6058,9 @@
                     !strconcat(OpcodeStr,
                     "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
                     []>, TA, OpSize, Requires<[HasSSE41]>;
+} // ExeDomain = SSEPackedSingle
 
+let ExeDomain = SSEPackedDouble in {
   // Vector intrinsic operation, reg
   def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
                     (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
@@ -6052,12 +6074,14 @@
                     !strconcat(OpcodeStr,
                     "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
                     []>, OpSize;
+} // ExeDomain = SSEPackedDouble
 }
 
 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
                             string OpcodeStr,
                             Intrinsic F32Int,
                             Intrinsic F64Int, bit Is2Addr = 1> {
+let ExeDomain = GenericDomain in {
   // Intrinsic operation, reg.
   def SSr : SS4AIi8<opcss, MRMSrcReg,
         (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
@@ -6103,10 +6127,12 @@
         [(set VR128:$dst,
               (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
         OpSize;
+} // ExeDomain = GenericDomain
 }
 
 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
                                    string OpcodeStr> {
+let ExeDomain = GenericDomain in {
   // Intrinsic operation, reg.
   def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
         (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
@@ -6134,6 +6160,7 @@
             !strconcat(OpcodeStr,
                 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
         []>, OpSize;
+} // ExeDomain = GenericDomain
 }
 
 // FP round - roundss, roundps, roundsd, roundpd
@@ -6216,11 +6243,15 @@
 }
 
 let Defs = [EFLAGS], Predicates = [HasAVX] in {
+let ExeDomain = SSEPackedSingle in {
 defm VTESTPS  : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
+}
+let ExeDomain = SSEPackedDouble in {
 defm VTESTPD  : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
 }
+}
 
 //===----------------------------------------------------------------------===//
 // SSE4.1 - Misc Instructions
@@ -6391,10 +6422,12 @@
   defm PMULDQ   : SS41I_binop_rm_int<0x28, "pmuldq",   int_x86_sse41_pmuldq>;
 }
 
-def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
-          (PCMPEQQrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
-          (PCMPEQQrm VR128:$src1, addr:$src2)>;
+let Predicates = [HasSSE41] in {
+  def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
+            (PCMPEQQrr VR128:$src1, VR128:$src2)>;
+  def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
+            (PCMPEQQrm VR128:$src1, addr:$src2)>;
+}
 
 /// SS48I_binop_rm - Simple SSE41 binary operator.
 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
@@ -6470,23 +6503,30 @@
 
 let Predicates = [HasAVX] in {
   let isCommutable = 0 in {
-  defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
-                                      VR128, memopv16i8, i128mem, 0>, VEX_4V;
-  defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
-                                      VR128, memopv16i8, i128mem, 0>, VEX_4V;
-  defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
-            int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
-  defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
-            int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
+    let ExeDomain = SSEPackedSingle in {
+    defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
+                                        VR128, memopv16i8, i128mem, 0>, VEX_4V;
+    defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
+              int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
+    }
+    let ExeDomain = SSEPackedDouble in {
+    defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
+                                        VR128, memopv16i8, i128mem, 0>, VEX_4V;
+    defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
+              int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
+    }
   defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
                                       VR128, memopv16i8, i128mem, 0>, VEX_4V;
   defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
                                       VR128, memopv16i8, i128mem, 0>, VEX_4V;
   }
+  let ExeDomain = SSEPackedSingle in
   defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
                                    VR128, memopv16i8, i128mem, 0>, VEX_4V;
+  let ExeDomain = SSEPackedDouble in
   defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
                                    VR128, memopv16i8, i128mem, 0>, VEX_4V;
+  let ExeDomain = SSEPackedSingle in
   defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
                                    VR256, memopv32i8, i256mem, 0>, VEX_4V;
 }
@@ -6502,8 +6542,10 @@
 
 let Constraints = "$src1 = $dst" in {
   let isCommutable = 0 in {
+  let ExeDomain = SSEPackedSingle in
   defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
                                      VR128, memopv16i8, i128mem>;
+  let ExeDomain = SSEPackedDouble in
   defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
                                      VR128, memopv16i8, i128mem>;
   defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
@@ -6511,8 +6553,10 @@
   defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
                                      VR128, memopv16i8, i128mem>;
   }
+  let ExeDomain = SSEPackedSingle in
   defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
                                   VR128, memopv16i8, i128mem>;
+  let ExeDomain = SSEPackedDouble in
   defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
                                   VR128, memopv16i8, i128mem>;
 }
@@ -6539,16 +6583,20 @@
 }
 
 let Predicates = [HasAVX] in {
+let ExeDomain = SSEPackedDouble in {
 defm VBLENDVPD  : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
                                            memopv16i8, int_x86_sse41_blendvpd>;
-defm VBLENDVPS  : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
-                                           memopv16i8, int_x86_sse41_blendvps>;
-defm VPBLENDVB  : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
-                                           memopv16i8, int_x86_sse41_pblendvb>;
 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
                                          memopv32i8, int_x86_avx_blendv_pd_256>;
+} // ExeDomain = SSEPackedDouble
+let ExeDomain = SSEPackedSingle in {
+defm VBLENDVPS  : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
+                                           memopv16i8, int_x86_sse41_blendvps>;
 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
                                          memopv32i8, int_x86_avx_blendv_ps_256>;
+} // ExeDomain = SSEPackedSingle
+defm VPBLENDVB  : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
+                                           memopv16i8, int_x86_sse41_pblendvb>;
 }
 
 let Predicates = [HasAVX2] in {
@@ -6612,7 +6660,9 @@
   }
 }
 
+let ExeDomain = SSEPackedDouble in
 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
+let ExeDomain = SSEPackedSingle in
 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
 
@@ -6712,10 +6762,12 @@
 let Constraints = "$src1 = $dst" in
   defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
 
-def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
-          (PCMPGTQrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
-          (PCMPGTQrm VR128:$src1, addr:$src2)>;
+let Predicates = [HasSSE42] in {
+  def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
+            (PCMPGTQrr VR128:$src1, VR128:$src2)>;
+  def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
+            (PCMPGTQrm VR128:$src1, addr:$src2)>;
+}
 
 //===----------------------------------------------------------------------===//
 // SSE4.2 - String/text Processing Instructions
@@ -7164,21 +7216,27 @@
          !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
          [(set RC:$dst, (Int VR128:$src))]>, VEX;
 
-def VBROADCASTSSrm  : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
-                                    int_x86_avx_vbroadcast_ss>;
-def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
-                                    int_x86_avx_vbroadcast_ss_256>;
+let ExeDomain = SSEPackedSingle in {
+  def VBROADCASTSSrm  : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
+                                      int_x86_avx_vbroadcast_ss>;
+  def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
+                                      int_x86_avx_vbroadcast_ss_256>;
+}
+let ExeDomain = SSEPackedDouble in
 def VBROADCASTSDrm  : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
                                     int_x86_avx_vbroadcast_sd_256>;
 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
                                    int_x86_avx_vbroadcastf128_pd_256>;
 
-def VBROADCASTSSrr  : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
-                                        int_x86_avx2_vbroadcast_ss_ps>;
-def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
-                                        int_x86_avx2_vbroadcast_ss_ps_256>;
+let ExeDomain = SSEPackedSingle in {
+  def VBROADCASTSSrr  : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
+                                           int_x86_avx2_vbroadcast_ss_ps>;
+  def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
+                                           int_x86_avx2_vbroadcast_ss_ps_256>;
+}
+let ExeDomain = SSEPackedDouble in
 def VBROADCASTSDrr  : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
-                                        int_x86_avx2_vbroadcast_sd_pd_256>;
+                                         int_x86_avx2_vbroadcast_sd_pd_256>;
 
 let Predicates = [HasAVX2] in
 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
@@ -7322,12 +7380,14 @@
              [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
 }
 
+let ExeDomain = SSEPackedSingle in
 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
                                  int_x86_avx_maskload_ps,
                                  int_x86_avx_maskload_ps_256,
                                  int_x86_avx_maskstore_ps,
                                  int_x86_avx_maskstore_ps_256,
                                  memopv4f32, memopv8f32>;
+let ExeDomain = SSEPackedDouble in
 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
                                  int_x86_avx_maskload_pd,
                                  int_x86_avx_maskload_pd_256,
@@ -7361,22 +7421,26 @@
              [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
 }
 
-defm VPERMILPS  : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
-                             memopv4f32, memopv4i32,
-                             int_x86_avx_vpermilvar_ps,
-                             int_x86_avx_vpermil_ps>;
-defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
-                             memopv8f32, memopv8i32,
-                             int_x86_avx_vpermilvar_ps_256,
-                             int_x86_avx_vpermil_ps_256>;
-defm VPERMILPD  : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
-                             memopv2f64, memopv2i64,
-                             int_x86_avx_vpermilvar_pd,
-                             int_x86_avx_vpermil_pd>;
-defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
-                             memopv4f64, memopv4i64,
-                             int_x86_avx_vpermilvar_pd_256,
-                             int_x86_avx_vpermil_pd_256>;
+let ExeDomain = SSEPackedSingle in {
+  defm VPERMILPS  : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
+                               memopv4f32, memopv4i32,
+                               int_x86_avx_vpermilvar_ps,
+                               int_x86_avx_vpermil_ps>;
+  defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
+                               memopv8f32, memopv8i32,
+                               int_x86_avx_vpermilvar_ps_256,
+                               int_x86_avx_vpermil_ps_256>;
+}
+let ExeDomain = SSEPackedDouble in {
+  defm VPERMILPD  : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
+                               memopv2f64, memopv2i64,
+                               int_x86_avx_vpermilvar_pd,
+                               int_x86_avx_vpermil_pd>;
+  defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
+                               memopv4f64, memopv4i64,
+                               int_x86_avx_vpermilvar_pd_256,
+                               int_x86_avx_vpermil_pd_256>;
+}
 
 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
           (VPERMILPSYri VR256:$src1, imm:$imm)>;
@@ -7569,6 +7633,7 @@
 }
 
 defm VPERMD : avx2_perm<0x36, "vpermd", memopv8i32, int_x86_avx2_permd>;
+let ExeDomain = SSEPackedSingle in
 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, int_x86_avx2_permps>;
 
 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
@@ -7588,6 +7653,7 @@
 
 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, int_x86_avx2_permq>,
                             VEX_W;
+let ExeDomain = SSEPackedDouble in
 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, int_x86_avx2_permpd>,
                              VEX_W;
 



From daniel at zuster.org  Wed Nov 16 01:33:00 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 07:33:00 -0000
Subject: [llvm-commits] [compiler-rt] r144785 - in /compiler-rt/trunk/lib:
 divdc3.c divsc3.c divxc3.c int_math.h muldc3.c mulsc3.c mulxc3.c
 ppc/divtc3.c ppc/multc3.c
Message-ID: <20111116073301.0839E2A6C133@llvm.org>

Author: ddunbar
Date: Wed Nov 16 01:33:00 2011
New Revision: 144785

URL: http://llvm.org/viewvc/llvm-project?rev=144785&view=rev
Log:
lib: Starting thinning out the dependency on math.h by using compiler builtins
where available.

Added:
    compiler-rt/trunk/lib/int_math.h
Modified:
    compiler-rt/trunk/lib/divdc3.c
    compiler-rt/trunk/lib/divsc3.c
    compiler-rt/trunk/lib/divxc3.c
    compiler-rt/trunk/lib/muldc3.c
    compiler-rt/trunk/lib/mulsc3.c
    compiler-rt/trunk/lib/mulxc3.c
    compiler-rt/trunk/lib/ppc/divtc3.c
    compiler-rt/trunk/lib/ppc/multc3.c

Modified: compiler-rt/trunk/lib/divdc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divdc3.c?rev=144785&r1=144784&r2=144785&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divdc3.c (original)
+++ compiler-rt/trunk/lib/divdc3.c Wed Nov 16 01:33:00 2011
@@ -13,6 +13,7 @@
  */
 
 #include "int_lib.h"
+#include "int_math.h"
 #include <math.h>
 
 /* Returns: the quotient of (a + ib) / (c + id) */
@@ -22,7 +23,7 @@
 {
     int __ilogbw = 0;
     double __logbw = logb(fmax(fabs(__c), fabs(__d)));
-    if (isfinite(__logbw))
+    if (crt_isfinite(__logbw))
     {
         __ilogbw = (int)__logbw;
         __c = scalbn(__c, -__ilogbw);
@@ -32,24 +33,26 @@
     double _Complex z;
     __real__ z = scalbn((__a * __c + __b * __d) / __denom, -__ilogbw);
     __imag__ z = scalbn((__b * __c - __a * __d) / __denom, -__ilogbw);
-    if (isnan(__real__ z) && isnan(__imag__ z))
+    if (crt_isnan(__real__ z) && crt_isnan(__imag__ z))
     {
-        if ((__denom == 0.0) && (!isnan(__a) || !isnan(__b)))
+        if ((__denom == 0.0) && (!crt_isnan(__a) || !crt_isnan(__b)))
         {
             __real__ z = copysign(INFINITY, __c) * __a;
             __imag__ z = copysign(INFINITY, __c) * __b;
         }
-        else if ((isinf(__a) || isinf(__b)) && isfinite(__c) && isfinite(__d))
+        else if ((crt_isinf(__a) || crt_isinf(__b)) &&
+                 crt_isfinite(__c) && crt_isfinite(__d))
         {
-            __a = copysign(isinf(__a) ? 1.0 : 0.0, __a);
-            __b = copysign(isinf(__b) ? 1.0 : 0.0, __b);
+            __a = copysign(crt_isinf(__a) ? 1.0 : 0.0, __a);
+            __b = copysign(crt_isinf(__b) ? 1.0 : 0.0, __b);
             __real__ z = INFINITY * (__a * __c + __b * __d);
             __imag__ z = INFINITY * (__b * __c - __a * __d);
         }
-        else if (isinf(__logbw) && __logbw > 0.0 && isfinite(__a) && isfinite(__b))
+        else if (crt_isinf(__logbw) && __logbw > 0.0 &&
+                 crt_isfinite(__a) && crt_isfinite(__b))
         {
-            __c = copysign(isinf(__c) ? 1.0 : 0.0, __c);
-            __d = copysign(isinf(__d) ? 1.0 : 0.0, __d);
+            __c = copysign(crt_isinf(__c) ? 1.0 : 0.0, __c);
+            __d = copysign(crt_isinf(__d) ? 1.0 : 0.0, __d);
             __real__ z = 0.0 * (__a * __c + __b * __d);
             __imag__ z = 0.0 * (__b * __c - __a * __d);
         }

Modified: compiler-rt/trunk/lib/divsc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divsc3.c?rev=144785&r1=144784&r2=144785&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divsc3.c (original)
+++ compiler-rt/trunk/lib/divsc3.c Wed Nov 16 01:33:00 2011
@@ -13,6 +13,7 @@
  */
 
 #include "int_lib.h"
+#include "int_math.h"
 #include <math.h>
 
 /* Returns: the quotient of (a + ib) / (c + id) */
@@ -22,7 +23,7 @@
 {
     int __ilogbw = 0;
     float __logbw = logbf(fmaxf(fabsf(__c), fabsf(__d)));
-    if (isfinite(__logbw))
+    if (crt_isfinite(__logbw))
     {
         __ilogbw = (int)__logbw;
         __c = scalbnf(__c, -__ilogbw);
@@ -32,24 +33,26 @@
     float _Complex z;
     __real__ z = scalbnf((__a * __c + __b * __d) / __denom, -__ilogbw);
     __imag__ z = scalbnf((__b * __c - __a * __d) / __denom, -__ilogbw);
-    if (isnan(__real__ z) && isnan(__imag__ z))
+    if (crt_isnan(__real__ z) && crt_isnan(__imag__ z))
     {
-        if ((__denom == 0) && (!isnan(__a) || !isnan(__b)))
+        if ((__denom == 0) && (!crt_isnan(__a) || !crt_isnan(__b)))
         {
             __real__ z = copysignf(INFINITY, __c) * __a;
             __imag__ z = copysignf(INFINITY, __c) * __b;
         }
-        else if ((isinf(__a) || isinf(__b)) && isfinite(__c) && isfinite(__d))
+        else if ((crt_isinf(__a) || crt_isinf(__b)) &&
+                 crt_isfinite(__c) && crt_isfinite(__d))
         {
-            __a = copysignf(isinf(__a) ? 1 : 0, __a);
-            __b = copysignf(isinf(__b) ? 1 : 0, __b);
+            __a = copysignf(crt_isinf(__a) ? 1 : 0, __a);
+            __b = copysignf(crt_isinf(__b) ? 1 : 0, __b);
             __real__ z = INFINITY * (__a * __c + __b * __d);
             __imag__ z = INFINITY * (__b * __c - __a * __d);
         }
-        else if (isinf(__logbw) && __logbw > 0 && isfinite(__a) && isfinite(__b))
+        else if (crt_isinf(__logbw) && __logbw > 0 &&
+                 crt_isfinite(__a) && crt_isfinite(__b))
         {
-            __c = copysignf(isinf(__c) ? 1 : 0, __c);
-            __d = copysignf(isinf(__d) ? 1 : 0, __d);
+            __c = copysignf(crt_isinf(__c) ? 1 : 0, __c);
+            __d = copysignf(crt_isinf(__d) ? 1 : 0, __d);
             __real__ z = 0 * (__a * __c + __b * __d);
             __imag__ z = 0 * (__b * __c - __a * __d);
         }

Modified: compiler-rt/trunk/lib/divxc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divxc3.c?rev=144785&r1=144784&r2=144785&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divxc3.c (original)
+++ compiler-rt/trunk/lib/divxc3.c Wed Nov 16 01:33:00 2011
@@ -14,6 +14,7 @@
 #if !_ARCH_PPC
 
 #include "int_lib.h"
+#include "int_math.h"
 #include <math.h>
 
 /* Returns: the quotient of (a + ib) / (c + id) */
@@ -23,7 +24,7 @@
 {
     int __ilogbw = 0;
     long double __logbw = logbl(fmaxl(fabsl(__c), fabsl(__d)));
-    if (isfinite(__logbw))
+    if (crt_isfinite(__logbw))
     {
         __ilogbw = (int)__logbw;
         __c = scalbnl(__c, -__ilogbw);
@@ -33,24 +34,26 @@
     long double _Complex z;
     __real__ z = scalbnl((__a * __c + __b * __d) / __denom, -__ilogbw);
     __imag__ z = scalbnl((__b * __c - __a * __d) / __denom, -__ilogbw);
-    if (isnan(__real__ z) && isnan(__imag__ z))
+    if (crt_isnan(__real__ z) && crt_isnan(__imag__ z))
     {
-        if ((__denom == 0) && (!isnan(__a) || !isnan(__b)))
+        if ((__denom == 0) && (!crt_isnan(__a) || !crt_isnan(__b)))
         {
             __real__ z = copysignl(INFINITY, __c) * __a;
             __imag__ z = copysignl(INFINITY, __c) * __b;
         }
-        else if ((isinf(__a) || isinf(__b)) && isfinite(__c) && isfinite(__d))
+        else if ((crt_isinf(__a) || crt_isinf(__b)) &&
+                 crt_isfinite(__c) && crt_isfinite(__d))
         {
-            __a = copysignl(isinf(__a) ? 1 : 0, __a);
-            __b = copysignl(isinf(__b) ? 1 : 0, __b);
+            __a = copysignl(crt_isinf(__a) ? 1 : 0, __a);
+            __b = copysignl(crt_isinf(__b) ? 1 : 0, __b);
             __real__ z = INFINITY * (__a * __c + __b * __d);
             __imag__ z = INFINITY * (__b * __c - __a * __d);
         }
-        else if (isinf(__logbw) && __logbw > 0 && isfinite(__a) && isfinite(__b))
+        else if (crt_isinf(__logbw) && __logbw > 0 &&
+                 crt_isfinite(__a) && crt_isfinite(__b))
         {
-            __c = copysignl(isinf(__c) ? 1 : 0, __c);
-            __d = copysignl(isinf(__d) ? 1 : 0, __d);
+            __c = copysignl(crt_isinf(__c) ? 1 : 0, __c);
+            __d = copysignl(crt_isinf(__d) ? 1 : 0, __d);
             __real__ z = 0 * (__a * __c + __b * __d);
             __imag__ z = 0 * (__b * __c - __a * __d);
         }

Added: compiler-rt/trunk/lib/int_math.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_math.h?rev=144785&view=auto
==============================================================================
--- compiler-rt/trunk/lib/int_math.h (added)
+++ compiler-rt/trunk/lib/int_math.h Wed Nov 16 01:33:00 2011
@@ -0,0 +1,28 @@
+/* ===-- int_math.h - internal math inlines ---------------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This file is not part of the interface of this library.
+ *
+ * This file defines substitutes for the libm functions used in some of the
+ * compiler-rt implementations, defined in such a way that there is not a direct
+ * dependency on libm or math.h. Instead, we use the compiler builtin versions
+ * where available. This reduces our dependencies on the system SDK by foisting
+ * the responsibility onto the compiler.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef INT_MATH_H
+#define INT_MATH_H
+
+#define crt_isfinite(x) __builtin_isfinite((x))
+#define crt_isinf(x) __builtin_isinf((x))
+#define crt_isnan(x) __builtin_isnan((x))
+
+#endif /* INT_MATH_H */

Modified: compiler-rt/trunk/lib/muldc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/muldc3.c?rev=144785&r1=144784&r2=144785&view=diff
==============================================================================
--- compiler-rt/trunk/lib/muldc3.c (original)
+++ compiler-rt/trunk/lib/muldc3.c Wed Nov 16 01:33:00 2011
@@ -13,6 +13,7 @@
  */
 
 #include "int_lib.h"
+#include "int_math.h"
 #include <math.h>
 
 /* Returns: the product of a + ib and c + id */
@@ -27,39 +28,39 @@
     double _Complex z;
     __real__ z = __ac - __bd;
     __imag__ z = __ad + __bc;
-    if (isnan(__real__ z) && isnan(__imag__ z))
+    if (crt_isnan(__real__ z) && crt_isnan(__imag__ z))
     {
         int __recalc = 0;
-        if (isinf(__a) || isinf(__b))
+        if (crt_isinf(__a) || crt_isinf(__b))
         {
-            __a = copysign(isinf(__a) ? 1 : 0, __a);
-            __b = copysign(isinf(__b) ? 1 : 0, __b);
-            if (isnan(__c))
+            __a = copysign(crt_isinf(__a) ? 1 : 0, __a);
+            __b = copysign(crt_isinf(__b) ? 1 : 0, __b);
+            if (crt_isnan(__c))
                 __c = copysign(0, __c);
-            if (isnan(__d))
+            if (crt_isnan(__d))
                 __d = copysign(0, __d);
             __recalc = 1;
         }
-        if (isinf(__c) || isinf(__d))
+        if (crt_isinf(__c) || crt_isinf(__d))
         {
-            __c = copysign(isinf(__c) ? 1 : 0, __c);
-            __d = copysign(isinf(__d) ? 1 : 0, __d);
-            if (isnan(__a))
+            __c = copysign(crt_isinf(__c) ? 1 : 0, __c);
+            __d = copysign(crt_isinf(__d) ? 1 : 0, __d);
+            if (crt_isnan(__a))
                 __a = copysign(0, __a);
-            if (isnan(__b))
+            if (crt_isnan(__b))
                 __b = copysign(0, __b);
             __recalc = 1;
         }
-        if (!__recalc && (isinf(__ac) || isinf(__bd) ||
-                          isinf(__ad) || isinf(__bc)))
+        if (!__recalc && (crt_isinf(__ac) || crt_isinf(__bd) ||
+                          crt_isinf(__ad) || crt_isinf(__bc)))
         {
-            if (isnan(__a))
+            if (crt_isnan(__a))
                 __a = copysign(0, __a);
-            if (isnan(__b))
+            if (crt_isnan(__b))
                 __b = copysign(0, __b);
-            if (isnan(__c))
+            if (crt_isnan(__c))
                 __c = copysign(0, __c);
-            if (isnan(__d))
+            if (crt_isnan(__d))
                 __d = copysign(0, __d);
             __recalc = 1;
         }

Modified: compiler-rt/trunk/lib/mulsc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulsc3.c?rev=144785&r1=144784&r2=144785&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulsc3.c (original)
+++ compiler-rt/trunk/lib/mulsc3.c Wed Nov 16 01:33:00 2011
@@ -13,6 +13,7 @@
  */
 
 #include "int_lib.h"
+#include "int_math.h"
 #include <math.h>
 
 /* Returns: the product of a + ib and c + id */
@@ -27,39 +28,39 @@
     float _Complex z;
     __real__ z = __ac - __bd;
     __imag__ z = __ad + __bc;
-    if (isnan(__real__ z) && isnan(__imag__ z))
+    if (crt_isnan(__real__ z) && crt_isnan(__imag__ z))
     {
         int __recalc = 0;
-        if (isinf(__a) || isinf(__b))
+        if (crt_isinf(__a) || crt_isinf(__b))
         {
-            __a = copysignf(isinf(__a) ? 1 : 0, __a);
-            __b = copysignf(isinf(__b) ? 1 : 0, __b);
-            if (isnan(__c))
+            __a = copysignf(crt_isinf(__a) ? 1 : 0, __a);
+            __b = copysignf(crt_isinf(__b) ? 1 : 0, __b);
+            if (crt_isnan(__c))
                 __c = copysignf(0, __c);
-            if (isnan(__d))
+            if (crt_isnan(__d))
                 __d = copysignf(0, __d);
             __recalc = 1;
         }
-        if (isinf(__c) || isinf(__d))
+        if (crt_isinf(__c) || crt_isinf(__d))
         {
-            __c = copysignf(isinf(__c) ? 1 : 0, __c);
-            __d = copysignf(isinf(__d) ? 1 : 0, __d);
-            if (isnan(__a))
+            __c = copysignf(crt_isinf(__c) ? 1 : 0, __c);
+            __d = copysignf(crt_isinf(__d) ? 1 : 0, __d);
+            if (crt_isnan(__a))
                 __a = copysignf(0, __a);
-            if (isnan(__b))
+            if (crt_isnan(__b))
                 __b = copysignf(0, __b);
             __recalc = 1;
         }
-        if (!__recalc && (isinf(__ac) || isinf(__bd) ||
-                          isinf(__ad) || isinf(__bc)))
+        if (!__recalc && (crt_isinf(__ac) || crt_isinf(__bd) ||
+                          crt_isinf(__ad) || crt_isinf(__bc)))
         {
-            if (isnan(__a))
+            if (crt_isnan(__a))
                 __a = copysignf(0, __a);
-            if (isnan(__b))
+            if (crt_isnan(__b))
                 __b = copysignf(0, __b);
-            if (isnan(__c))
+            if (crt_isnan(__c))
                 __c = copysignf(0, __c);
-            if (isnan(__d))
+            if (crt_isnan(__d))
                 __d = copysignf(0, __d);
             __recalc = 1;
         }

Modified: compiler-rt/trunk/lib/mulxc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulxc3.c?rev=144785&r1=144784&r2=144785&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulxc3.c (original)
+++ compiler-rt/trunk/lib/mulxc3.c Wed Nov 16 01:33:00 2011
@@ -15,6 +15,7 @@
 #if !_ARCH_PPC
 
 #include "int_lib.h"
+#include "int_math.h"
 #include <math.h>
 
 /* Returns: the product of a + ib and c + id */
@@ -29,39 +30,39 @@
     long double _Complex z;
     __real__ z = __ac - __bd;
     __imag__ z = __ad + __bc;
-    if (isnan(__real__ z) && isnan(__imag__ z))
+    if (crt_isnan(__real__ z) && crt_isnan(__imag__ z))
     {
         int __recalc = 0;
-        if (isinf(__a) || isinf(__b))
+        if (crt_isinf(__a) || crt_isinf(__b))
         {
-            __a = copysignl(isinf(__a) ? 1 : 0, __a);
-            __b = copysignl(isinf(__b) ? 1 : 0, __b);
-            if (isnan(__c))
+            __a = copysignl(crt_isinf(__a) ? 1 : 0, __a);
+            __b = copysignl(crt_isinf(__b) ? 1 : 0, __b);
+            if (crt_isnan(__c))
                 __c = copysignl(0, __c);
-            if (isnan(__d))
+            if (crt_isnan(__d))
                 __d = copysignl(0, __d);
             __recalc = 1;
         }
-        if (isinf(__c) || isinf(__d))
+        if (crt_isinf(__c) || crt_isinf(__d))
         {
-            __c = copysignl(isinf(__c) ? 1 : 0, __c);
-            __d = copysignl(isinf(__d) ? 1 : 0, __d);
-            if (isnan(__a))
+            __c = copysignl(crt_isinf(__c) ? 1 : 0, __c);
+            __d = copysignl(crt_isinf(__d) ? 1 : 0, __d);
+            if (crt_isnan(__a))
                 __a = copysignl(0, __a);
-            if (isnan(__b))
+            if (crt_isnan(__b))
                 __b = copysignl(0, __b);
             __recalc = 1;
         }
-        if (!__recalc && (isinf(__ac) || isinf(__bd) ||
-                          isinf(__ad) || isinf(__bc)))
+        if (!__recalc && (crt_isinf(__ac) || crt_isinf(__bd) ||
+                          crt_isinf(__ad) || crt_isinf(__bc)))
         {
-            if (isnan(__a))
+            if (crt_isnan(__a))
                 __a = copysignl(0, __a);
-            if (isnan(__b))
+            if (crt_isnan(__b))
                 __b = copysignl(0, __b);
-            if (isnan(__c))
+            if (crt_isnan(__c))
                 __c = copysignl(0, __c);
-            if (isnan(__d))
+            if (crt_isnan(__d))
                 __d = copysignl(0, __d);
             __recalc = 1;
         }

Modified: compiler-rt/trunk/lib/ppc/divtc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ppc/divtc3.c?rev=144785&r1=144784&r2=144785&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ppc/divtc3.c (original)
+++ compiler-rt/trunk/lib/ppc/divtc3.c Wed Nov 16 01:33:00 2011
@@ -3,16 +3,17 @@
  */
 
 #include "DD.h"
+#include "../int_math.h"
 #include <math.h>
 
 #if !defined(INFINITY) && defined(HUGE_VAL)
 #define INFINITY HUGE_VAL
 #endif /* INFINITY */
 
-#define makeFinite(x)	{ \
-							(x).s.hi = __builtin_copysign(isinf((x).s.hi) ? 1.0 : 0.0, (x).s.hi); \
-							(x).s.lo = 0.0; \
-						}
+#define makeFinite(x) { \
+    (x).s.hi = __builtin_copysign(crt_isinf((x).s.hi) ? 1.0 : 0.0, (x).s.hi); \
+    (x).s.lo = 0.0;                                                     \
+  }
 
 long double __gcc_qadd(long double, long double);
 long double __gcc_qsub(long double, long double);
@@ -28,7 +29,7 @@
 	int ilogbw = 0;
 	const double logbw = logb(__builtin_fmax( __builtin_fabs(cDD.s.hi), __builtin_fabs(dDD.s.hi) ));
 	
-	if (isfinite(logbw))
+	if (crt_isfinite(logbw))
 	{
 		ilogbw = (int)logbw;
 		
@@ -50,13 +51,14 @@
 	imag.s.hi = scalbn(imag.s.hi, -ilogbw);
 	imag.s.lo = scalbn(imag.s.lo, -ilogbw);
 	
-	if (isnan(real.s.hi) && isnan(imag.s.hi))
+	if (crt_isnan(real.s.hi) && crt_isnan(imag.s.hi))
 	{
 		DD aDD = { .ld = a };
 		DD bDD = { .ld = b };
 		DD rDD = { .ld = denom };
 		
-		if ((rDD.s.hi == 0.0) && (!isnan(aDD.s.hi) || !isnan(bDD.s.hi)))
+		if ((rDD.s.hi == 0.0) && (!crt_isnan(aDD.s.hi) ||
+                                          !crt_isnan(bDD.s.hi)))
 		{
 			real.s.hi = __builtin_copysign(INFINITY,cDD.s.hi) * aDD.s.hi;
 			real.s.lo = 0.0;
@@ -64,7 +66,8 @@
 			imag.s.lo = 0.0;
 		}
 		
-		else if ((isinf(aDD.s.hi) || isinf(bDD.s.hi)) && isfinite(cDD.s.hi) && isfinite(dDD.s.hi))
+		else if ((crt_isinf(aDD.s.hi) || crt_isinf(bDD.s.hi)) &&
+                         crt_isfinite(cDD.s.hi) && crt_isfinite(dDD.s.hi))
 		{
 			makeFinite(aDD);
 			makeFinite(bDD);
@@ -74,7 +77,8 @@
 			imag.s.lo = 0.0;
 		}
 		
-		else if ((isinf(cDD.s.hi) || isinf(dDD.s.hi)) && isfinite(aDD.s.hi) && isfinite(bDD.s.hi))
+		else if ((crt_isinf(cDD.s.hi) || crt_isinf(dDD.s.hi)) &&
+                         crt_isfinite(aDD.s.hi) && crt_isfinite(bDD.s.hi))
 		{
 			makeFinite(cDD);
 			makeFinite(dDD);

Modified: compiler-rt/trunk/lib/ppc/multc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ppc/multc3.c?rev=144785&r1=144784&r2=144785&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ppc/multc3.c (original)
+++ compiler-rt/trunk/lib/ppc/multc3.c Wed Nov 16 01:33:00 2011
@@ -3,23 +3,24 @@
  */
 
 #include "DD.h"
+#include "../int_math.h"
 #include <math.h>
 
 #if !defined(INFINITY) && defined(HUGE_VAL)
 #define INFINITY HUGE_VAL
 #endif /* INFINITY */
 
-#define makeFinite(x)	{ \
-							(x).s.hi = __builtin_copysign(isinf((x).s.hi) ? 1.0 : 0.0, (x).s.hi); \
-							(x).s.lo = 0.0; \
-						}
-
-#define zeroNaN(x)		{ \
-							if (isnan((x).s.hi)) { \
-								(x).s.hi = __builtin_copysign(0.0, (x).s.hi); \
-								(x).s.lo = 0.0; \
-							} \
-						}
+#define makeFinite(x) { \
+    (x).s.hi = __builtin_copysign(crt_isinf((x).s.hi) ? 1.0 : 0.0, (x).s.hi); \
+    (x).s.lo = 0.0;                                                     \
+  }
+
+#define zeroNaN() { \
+    if (crt_isnan((x).s.hi)) {                                          \
+      (x).s.hi = __builtin_copysign(0.0, (x).s.hi);                     \
+      (x).s.lo = 0.0;                                                   \
+    }                                                                   \
+  }
 
 long double __gcc_qadd(long double, long double);
 long double __gcc_qsub(long double, long double);
@@ -36,7 +37,7 @@
 	DD real = { .ld = __gcc_qsub(ac,bd) };
 	DD imag = { .ld = __gcc_qadd(ad,bc) };
 	
-	if (isnan(real.s.hi) && isnan(imag.s.hi))
+	if (crt_isnan(real.s.hi) && crt_isnan(imag.s.hi))
 	{
 		int recalc = 0;
 		
@@ -45,7 +46,7 @@
 		DD cDD = { .ld = c };
 		DD dDD = { .ld = d };
 		
-		if (isinf(aDD.s.hi) || isinf(bDD.s.hi))
+		if (crt_isinf(aDD.s.hi) || crt_isinf(bDD.s.hi))
 		{
 			makeFinite(aDD);
 			makeFinite(bDD);
@@ -54,7 +55,7 @@
 			recalc = 1;
 		}
 		
-		if (isinf(cDD.s.hi) || isinf(dDD.s.hi))
+		if (crt_isinf(cDD.s.hi) || crt_isinf(dDD.s.hi))
 		{
 			makeFinite(cDD);
 			makeFinite(dDD);
@@ -70,7 +71,8 @@
 			DD adDD = { .ld = ad };
 			DD bcDD = { .ld = bc };
 			
-			if (isinf(acDD.s.hi) || isinf(bdDD.s.hi) || isinf(adDD.s.hi) || isinf(bcDD.s.hi))
+			if (crt_isinf(acDD.s.hi) || crt_isinf(bdDD.s.hi) ||
+                            crt_isinf(adDD.s.hi) || crt_isinf(bcDD.s.hi))
 			{
 				zeroNaN(aDD);
 				zeroNaN(bDD);



From daniel at zuster.org  Wed Nov 16 01:33:06 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 07:33:06 -0000
Subject: [llvm-commits] [compiler-rt] r144786 - in /compiler-rt/trunk:
 lib/divdc3.c lib/divsc3.c lib/divxc3.c lib/int_lib.h lib/int_math.h
 lib/muldc3.c lib/mulsc3.c lib/mulxc3.c lib/ppc/divtc3.c lib/ppc/fixtfdi.c
 lib/ppc/multc3.c make/platform/clang_darwin_test_input.c
Message-ID: <20111116073306.7FAA12A6C133@llvm.org>

Author: ddunbar
Date: Wed Nov 16 01:33:06 2011
New Revision: 144786

URL: http://llvm.org/viewvc/llvm-project?rev=144786&view=rev
Log:
lib: Finish int_math.h definitions using compiler builtins and eliminate
implementation use of <math.h>.

Modified:
    compiler-rt/trunk/lib/divdc3.c
    compiler-rt/trunk/lib/divsc3.c
    compiler-rt/trunk/lib/divxc3.c
    compiler-rt/trunk/lib/int_lib.h
    compiler-rt/trunk/lib/int_math.h
    compiler-rt/trunk/lib/muldc3.c
    compiler-rt/trunk/lib/mulsc3.c
    compiler-rt/trunk/lib/mulxc3.c
    compiler-rt/trunk/lib/ppc/divtc3.c
    compiler-rt/trunk/lib/ppc/fixtfdi.c
    compiler-rt/trunk/lib/ppc/multc3.c
    compiler-rt/trunk/make/platform/clang_darwin_test_input.c

Modified: compiler-rt/trunk/lib/divdc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divdc3.c?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divdc3.c (original)
+++ compiler-rt/trunk/lib/divdc3.c Wed Nov 16 01:33:06 2011
@@ -14,7 +14,6 @@
 
 #include "int_lib.h"
 #include "int_math.h"
-#include <math.h>
 
 /* Returns: the quotient of (a + ib) / (c + id) */
 
@@ -22,37 +21,37 @@
 __divdc3(double __a, double __b, double __c, double __d)
 {
     int __ilogbw = 0;
-    double __logbw = logb(fmax(fabs(__c), fabs(__d)));
+    double __logbw = crt_logb(crt_fmax(crt_fabs(__c), crt_fabs(__d)));
     if (crt_isfinite(__logbw))
     {
         __ilogbw = (int)__logbw;
-        __c = scalbn(__c, -__ilogbw);
-        __d = scalbn(__d, -__ilogbw);
+        __c = crt_scalbn(__c, -__ilogbw);
+        __d = crt_scalbn(__d, -__ilogbw);
     }
     double __denom = __c * __c + __d * __d;
     double _Complex z;
-    __real__ z = scalbn((__a * __c + __b * __d) / __denom, -__ilogbw);
-    __imag__ z = scalbn((__b * __c - __a * __d) / __denom, -__ilogbw);
+    __real__ z = crt_scalbn((__a * __c + __b * __d) / __denom, -__ilogbw);
+    __imag__ z = crt_scalbn((__b * __c - __a * __d) / __denom, -__ilogbw);
     if (crt_isnan(__real__ z) && crt_isnan(__imag__ z))
     {
         if ((__denom == 0.0) && (!crt_isnan(__a) || !crt_isnan(__b)))
         {
-            __real__ z = copysign(INFINITY, __c) * __a;
-            __imag__ z = copysign(INFINITY, __c) * __b;
+            __real__ z = crt_copysign(CRT_INFINITY, __c) * __a;
+            __imag__ z = crt_copysign(CRT_INFINITY, __c) * __b;
         }
         else if ((crt_isinf(__a) || crt_isinf(__b)) &&
                  crt_isfinite(__c) && crt_isfinite(__d))
         {
-            __a = copysign(crt_isinf(__a) ? 1.0 : 0.0, __a);
-            __b = copysign(crt_isinf(__b) ? 1.0 : 0.0, __b);
-            __real__ z = INFINITY * (__a * __c + __b * __d);
-            __imag__ z = INFINITY * (__b * __c - __a * __d);
+            __a = crt_copysign(crt_isinf(__a) ? 1.0 : 0.0, __a);
+            __b = crt_copysign(crt_isinf(__b) ? 1.0 : 0.0, __b);
+            __real__ z = CRT_INFINITY * (__a * __c + __b * __d);
+            __imag__ z = CRT_INFINITY * (__b * __c - __a * __d);
         }
         else if (crt_isinf(__logbw) && __logbw > 0.0 &&
                  crt_isfinite(__a) && crt_isfinite(__b))
         {
-            __c = copysign(crt_isinf(__c) ? 1.0 : 0.0, __c);
-            __d = copysign(crt_isinf(__d) ? 1.0 : 0.0, __d);
+            __c = crt_copysign(crt_isinf(__c) ? 1.0 : 0.0, __c);
+            __d = crt_copysign(crt_isinf(__d) ? 1.0 : 0.0, __d);
             __real__ z = 0.0 * (__a * __c + __b * __d);
             __imag__ z = 0.0 * (__b * __c - __a * __d);
         }

Modified: compiler-rt/trunk/lib/divsc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divsc3.c?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divsc3.c (original)
+++ compiler-rt/trunk/lib/divsc3.c Wed Nov 16 01:33:06 2011
@@ -14,7 +14,6 @@
 
 #include "int_lib.h"
 #include "int_math.h"
-#include <math.h>
 
 /* Returns: the quotient of (a + ib) / (c + id) */
 
@@ -22,37 +21,37 @@
 __divsc3(float __a, float __b, float __c, float __d)
 {
     int __ilogbw = 0;
-    float __logbw = logbf(fmaxf(fabsf(__c), fabsf(__d)));
+    float __logbw = crt_logbf(crt_fmaxf(crt_fabsf(__c), crt_fabsf(__d)));
     if (crt_isfinite(__logbw))
     {
         __ilogbw = (int)__logbw;
-        __c = scalbnf(__c, -__ilogbw);
-        __d = scalbnf(__d, -__ilogbw);
+        __c = crt_scalbnf(__c, -__ilogbw);
+        __d = crt_scalbnf(__d, -__ilogbw);
     }
     float __denom = __c * __c + __d * __d;
     float _Complex z;
-    __real__ z = scalbnf((__a * __c + __b * __d) / __denom, -__ilogbw);
-    __imag__ z = scalbnf((__b * __c - __a * __d) / __denom, -__ilogbw);
+    __real__ z = crt_scalbnf((__a * __c + __b * __d) / __denom, -__ilogbw);
+    __imag__ z = crt_scalbnf((__b * __c - __a * __d) / __denom, -__ilogbw);
     if (crt_isnan(__real__ z) && crt_isnan(__imag__ z))
     {
         if ((__denom == 0) && (!crt_isnan(__a) || !crt_isnan(__b)))
         {
-            __real__ z = copysignf(INFINITY, __c) * __a;
-            __imag__ z = copysignf(INFINITY, __c) * __b;
+            __real__ z = crt_copysignf(CRT_INFINITY, __c) * __a;
+            __imag__ z = crt_copysignf(CRT_INFINITY, __c) * __b;
         }
         else if ((crt_isinf(__a) || crt_isinf(__b)) &&
                  crt_isfinite(__c) && crt_isfinite(__d))
         {
-            __a = copysignf(crt_isinf(__a) ? 1 : 0, __a);
-            __b = copysignf(crt_isinf(__b) ? 1 : 0, __b);
-            __real__ z = INFINITY * (__a * __c + __b * __d);
-            __imag__ z = INFINITY * (__b * __c - __a * __d);
+            __a = crt_copysignf(crt_isinf(__a) ? 1 : 0, __a);
+            __b = crt_copysignf(crt_isinf(__b) ? 1 : 0, __b);
+            __real__ z = CRT_INFINITY * (__a * __c + __b * __d);
+            __imag__ z = CRT_INFINITY * (__b * __c - __a * __d);
         }
         else if (crt_isinf(__logbw) && __logbw > 0 &&
                  crt_isfinite(__a) && crt_isfinite(__b))
         {
-            __c = copysignf(crt_isinf(__c) ? 1 : 0, __c);
-            __d = copysignf(crt_isinf(__d) ? 1 : 0, __d);
+            __c = crt_copysignf(crt_isinf(__c) ? 1 : 0, __c);
+            __d = crt_copysignf(crt_isinf(__d) ? 1 : 0, __d);
             __real__ z = 0 * (__a * __c + __b * __d);
             __imag__ z = 0 * (__b * __c - __a * __d);
         }

Modified: compiler-rt/trunk/lib/divxc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divxc3.c?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divxc3.c (original)
+++ compiler-rt/trunk/lib/divxc3.c Wed Nov 16 01:33:06 2011
@@ -15,7 +15,6 @@
 
 #include "int_lib.h"
 #include "int_math.h"
-#include <math.h>
 
 /* Returns: the quotient of (a + ib) / (c + id) */
 
@@ -23,37 +22,37 @@
 __divxc3(long double __a, long double __b, long double __c, long double __d)
 {
     int __ilogbw = 0;
-    long double __logbw = logbl(fmaxl(fabsl(__c), fabsl(__d)));
+    long double __logbw = crt_logbl(crt_fmaxl(crt_fabsl(__c), crt_fabsl(__d)));
     if (crt_isfinite(__logbw))
     {
         __ilogbw = (int)__logbw;
-        __c = scalbnl(__c, -__ilogbw);
-        __d = scalbnl(__d, -__ilogbw);
+        __c = crt_scalbnl(__c, -__ilogbw);
+        __d = crt_scalbnl(__d, -__ilogbw);
     }
     long double __denom = __c * __c + __d * __d;
     long double _Complex z;
-    __real__ z = scalbnl((__a * __c + __b * __d) / __denom, -__ilogbw);
-    __imag__ z = scalbnl((__b * __c - __a * __d) / __denom, -__ilogbw);
+    __real__ z = crt_scalbnl((__a * __c + __b * __d) / __denom, -__ilogbw);
+    __imag__ z = crt_scalbnl((__b * __c - __a * __d) / __denom, -__ilogbw);
     if (crt_isnan(__real__ z) && crt_isnan(__imag__ z))
     {
         if ((__denom == 0) && (!crt_isnan(__a) || !crt_isnan(__b)))
         {
-            __real__ z = copysignl(INFINITY, __c) * __a;
-            __imag__ z = copysignl(INFINITY, __c) * __b;
+            __real__ z = crt_copysignl(CRT_INFINITY, __c) * __a;
+            __imag__ z = crt_copysignl(CRT_INFINITY, __c) * __b;
         }
         else if ((crt_isinf(__a) || crt_isinf(__b)) &&
                  crt_isfinite(__c) && crt_isfinite(__d))
         {
-            __a = copysignl(crt_isinf(__a) ? 1 : 0, __a);
-            __b = copysignl(crt_isinf(__b) ? 1 : 0, __b);
-            __real__ z = INFINITY * (__a * __c + __b * __d);
-            __imag__ z = INFINITY * (__b * __c - __a * __d);
+            __a = crt_copysignl(crt_isinf(__a) ? 1 : 0, __a);
+            __b = crt_copysignl(crt_isinf(__b) ? 1 : 0, __b);
+            __real__ z = CRT_INFINITY * (__a * __c + __b * __d);
+            __imag__ z = CRT_INFINITY * (__b * __c - __a * __d);
         }
         else if (crt_isinf(__logbw) && __logbw > 0 &&
                  crt_isfinite(__a) && crt_isfinite(__b))
         {
-            __c = copysignl(crt_isinf(__c) ? 1 : 0, __c);
-            __d = copysignl(crt_isinf(__d) ? 1 : 0, __d);
+            __c = crt_copysignl(crt_isinf(__c) ? 1 : 0, __c);
+            __d = crt_copysignl(crt_isinf(__d) ? 1 : 0, __d);
             __real__ z = 0 * (__a * __c + __b * __d);
             __imag__ z = 0 * (__b * __c - __a * __d);
         }

Modified: compiler-rt/trunk/lib/int_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_lib.h?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_lib.h (original)
+++ compiler-rt/trunk/lib/int_lib.h Wed Nov 16 01:33:06 2011
@@ -37,10 +37,6 @@
 #include <stdbool.h>
 #include <float.h>
 
-#if !defined(INFINITY) && defined(HUGE_VAL)
-#define INFINITY HUGE_VAL
-#endif /* INFINITY */
-
 /* Include the commonly used internal type definitions. */
 #include "int_types.h"
 

Modified: compiler-rt/trunk/lib/int_math.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_math.h?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_math.h (original)
+++ compiler-rt/trunk/lib/int_math.h Wed Nov 16 01:33:06 2011
@@ -21,8 +21,30 @@
 #ifndef INT_MATH_H
 #define INT_MATH_H
 
+#define CRT_INFINITY __builtin_huge_valf()
+
 #define crt_isfinite(x) __builtin_isfinite((x))
 #define crt_isinf(x) __builtin_isinf((x))
 #define crt_isnan(x) __builtin_isnan((x))
 
+#define crt_copysign(x, y) __builtin_copysign((x), (y))
+#define crt_copysignf(x, y) __builtin_copysignf((x), (y))
+#define crt_copysignl(x, y) __builtin_copysignl((x), (y))
+
+#define crt_fabs(x) __builtin_fabs((x))
+#define crt_fabsf(x) __builtin_fabsf((x))
+#define crt_fabsl(x) __builtin_fabsl((x))
+
+#define crt_fmax(x, y) __builtin_fmax((x), (y))
+#define crt_fmaxf(x, y) __builtin_fmaxf((x), (y))
+#define crt_fmaxl(x, y) __builtin_fmaxl((x), (y))
+
+#define crt_logb(x) __builtin_logb((x))
+#define crt_logbf(x) __builtin_logbf((x))
+#define crt_logbl(x) __builtin_logbl((x))
+
+#define crt_scalbn(x, y) __builtin_scalbn((x), (y))
+#define crt_scalbnf(x, y) __builtin_scalbnf((x), (y))
+#define crt_scalbnl(x, y) __builtin_scalbnl((x), (y))
+
 #endif /* INT_MATH_H */

Modified: compiler-rt/trunk/lib/muldc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/muldc3.c?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/lib/muldc3.c (original)
+++ compiler-rt/trunk/lib/muldc3.c Wed Nov 16 01:33:06 2011
@@ -14,7 +14,6 @@
 
 #include "int_lib.h"
 #include "int_math.h"
-#include <math.h>
 
 /* Returns: the product of a + ib and c + id */
 
@@ -33,41 +32,41 @@
         int __recalc = 0;
         if (crt_isinf(__a) || crt_isinf(__b))
         {
-            __a = copysign(crt_isinf(__a) ? 1 : 0, __a);
-            __b = copysign(crt_isinf(__b) ? 1 : 0, __b);
+            __a = crt_copysign(crt_isinf(__a) ? 1 : 0, __a);
+            __b = crt_copysign(crt_isinf(__b) ? 1 : 0, __b);
             if (crt_isnan(__c))
-                __c = copysign(0, __c);
+                __c = crt_copysign(0, __c);
             if (crt_isnan(__d))
-                __d = copysign(0, __d);
+                __d = crt_copysign(0, __d);
             __recalc = 1;
         }
         if (crt_isinf(__c) || crt_isinf(__d))
         {
-            __c = copysign(crt_isinf(__c) ? 1 : 0, __c);
-            __d = copysign(crt_isinf(__d) ? 1 : 0, __d);
+            __c = crt_copysign(crt_isinf(__c) ? 1 : 0, __c);
+            __d = crt_copysign(crt_isinf(__d) ? 1 : 0, __d);
             if (crt_isnan(__a))
-                __a = copysign(0, __a);
+                __a = crt_copysign(0, __a);
             if (crt_isnan(__b))
-                __b = copysign(0, __b);
+                __b = crt_copysign(0, __b);
             __recalc = 1;
         }
         if (!__recalc && (crt_isinf(__ac) || crt_isinf(__bd) ||
                           crt_isinf(__ad) || crt_isinf(__bc)))
         {
             if (crt_isnan(__a))
-                __a = copysign(0, __a);
+                __a = crt_copysign(0, __a);
             if (crt_isnan(__b))
-                __b = copysign(0, __b);
+                __b = crt_copysign(0, __b);
             if (crt_isnan(__c))
-                __c = copysign(0, __c);
+                __c = crt_copysign(0, __c);
             if (crt_isnan(__d))
-                __d = copysign(0, __d);
+                __d = crt_copysign(0, __d);
             __recalc = 1;
         }
         if (__recalc)
         {
-            __real__ z = INFINITY * (__a * __c - __b * __d);
-            __imag__ z = INFINITY * (__a * __d + __b * __c);
+            __real__ z = CRT_INFINITY * (__a * __c - __b * __d);
+            __imag__ z = CRT_INFINITY * (__a * __d + __b * __c);
         }
     }
     return z;

Modified: compiler-rt/trunk/lib/mulsc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulsc3.c?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulsc3.c (original)
+++ compiler-rt/trunk/lib/mulsc3.c Wed Nov 16 01:33:06 2011
@@ -14,7 +14,6 @@
 
 #include "int_lib.h"
 #include "int_math.h"
-#include <math.h>
 
 /* Returns: the product of a + ib and c + id */
 
@@ -33,41 +32,41 @@
         int __recalc = 0;
         if (crt_isinf(__a) || crt_isinf(__b))
         {
-            __a = copysignf(crt_isinf(__a) ? 1 : 0, __a);
-            __b = copysignf(crt_isinf(__b) ? 1 : 0, __b);
+            __a = crt_copysignf(crt_isinf(__a) ? 1 : 0, __a);
+            __b = crt_copysignf(crt_isinf(__b) ? 1 : 0, __b);
             if (crt_isnan(__c))
-                __c = copysignf(0, __c);
+                __c = crt_copysignf(0, __c);
             if (crt_isnan(__d))
-                __d = copysignf(0, __d);
+                __d = crt_copysignf(0, __d);
             __recalc = 1;
         }
         if (crt_isinf(__c) || crt_isinf(__d))
         {
-            __c = copysignf(crt_isinf(__c) ? 1 : 0, __c);
-            __d = copysignf(crt_isinf(__d) ? 1 : 0, __d);
+            __c = crt_copysignf(crt_isinf(__c) ? 1 : 0, __c);
+            __d = crt_copysignf(crt_isinf(__d) ? 1 : 0, __d);
             if (crt_isnan(__a))
-                __a = copysignf(0, __a);
+                __a = crt_copysignf(0, __a);
             if (crt_isnan(__b))
-                __b = copysignf(0, __b);
+                __b = crt_copysignf(0, __b);
             __recalc = 1;
         }
         if (!__recalc && (crt_isinf(__ac) || crt_isinf(__bd) ||
                           crt_isinf(__ad) || crt_isinf(__bc)))
         {
             if (crt_isnan(__a))
-                __a = copysignf(0, __a);
+                __a = crt_copysignf(0, __a);
             if (crt_isnan(__b))
-                __b = copysignf(0, __b);
+                __b = crt_copysignf(0, __b);
             if (crt_isnan(__c))
-                __c = copysignf(0, __c);
+                __c = crt_copysignf(0, __c);
             if (crt_isnan(__d))
-                __d = copysignf(0, __d);
+                __d = crt_copysignf(0, __d);
             __recalc = 1;
         }
         if (__recalc)
         {
-            __real__ z = INFINITY * (__a * __c - __b * __d);
-            __imag__ z = INFINITY * (__a * __d + __b * __c);
+            __real__ z = CRT_INFINITY * (__a * __c - __b * __d);
+            __imag__ z = CRT_INFINITY * (__a * __d + __b * __c);
         }
     }
     return z;

Modified: compiler-rt/trunk/lib/mulxc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulxc3.c?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulxc3.c (original)
+++ compiler-rt/trunk/lib/mulxc3.c Wed Nov 16 01:33:06 2011
@@ -16,7 +16,6 @@
 
 #include "int_lib.h"
 #include "int_math.h"
-#include <math.h>
 
 /* Returns: the product of a + ib and c + id */
 
@@ -35,41 +34,41 @@
         int __recalc = 0;
         if (crt_isinf(__a) || crt_isinf(__b))
         {
-            __a = copysignl(crt_isinf(__a) ? 1 : 0, __a);
-            __b = copysignl(crt_isinf(__b) ? 1 : 0, __b);
+            __a = crt_copysignl(crt_isinf(__a) ? 1 : 0, __a);
+            __b = crt_copysignl(crt_isinf(__b) ? 1 : 0, __b);
             if (crt_isnan(__c))
-                __c = copysignl(0, __c);
+                __c = crt_copysignl(0, __c);
             if (crt_isnan(__d))
-                __d = copysignl(0, __d);
+                __d = crt_copysignl(0, __d);
             __recalc = 1;
         }
         if (crt_isinf(__c) || crt_isinf(__d))
         {
-            __c = copysignl(crt_isinf(__c) ? 1 : 0, __c);
-            __d = copysignl(crt_isinf(__d) ? 1 : 0, __d);
+            __c = crt_copysignl(crt_isinf(__c) ? 1 : 0, __c);
+            __d = crt_copysignl(crt_isinf(__d) ? 1 : 0, __d);
             if (crt_isnan(__a))
-                __a = copysignl(0, __a);
+                __a = crt_copysignl(0, __a);
             if (crt_isnan(__b))
-                __b = copysignl(0, __b);
+                __b = crt_copysignl(0, __b);
             __recalc = 1;
         }
         if (!__recalc && (crt_isinf(__ac) || crt_isinf(__bd) ||
                           crt_isinf(__ad) || crt_isinf(__bc)))
         {
             if (crt_isnan(__a))
-                __a = copysignl(0, __a);
+                __a = crt_copysignl(0, __a);
             if (crt_isnan(__b))
-                __b = copysignl(0, __b);
+                __b = crt_copysignl(0, __b);
             if (crt_isnan(__c))
-                __c = copysignl(0, __c);
+                __c = crt_copysignl(0, __c);
             if (crt_isnan(__d))
-                __d = copysignl(0, __d);
+                __d = crt_copysignl(0, __d);
             __recalc = 1;
         }
         if (__recalc)
         {
-            __real__ z = INFINITY * (__a * __c - __b * __d);
-            __imag__ z = INFINITY * (__a * __d + __b * __c);
+            __real__ z = CRT_INFINITY * (__a * __c - __b * __d);
+            __imag__ z = CRT_INFINITY * (__a * __d + __b * __c);
         }
     }
     return z;

Modified: compiler-rt/trunk/lib/ppc/divtc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ppc/divtc3.c?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ppc/divtc3.c (original)
+++ compiler-rt/trunk/lib/ppc/divtc3.c Wed Nov 16 01:33:06 2011
@@ -4,14 +4,13 @@
 
 #include "DD.h"
 #include "../int_math.h"
-#include <math.h>
 
-#if !defined(INFINITY) && defined(HUGE_VAL)
-#define INFINITY HUGE_VAL
-#endif /* INFINITY */
+#if !defined(CRT_INFINITY) && defined(HUGE_VAL)
+#define CRT_INFINITY HUGE_VAL
+#endif /* CRT_INFINITY */
 
 #define makeFinite(x) { \
-    (x).s.hi = __builtin_copysign(crt_isinf((x).s.hi) ? 1.0 : 0.0, (x).s.hi); \
+    (x).s.hi = crt_copysign(crt_isinf((x).s.hi) ? 1.0 : 0.0, (x).s.hi); \
     (x).s.lo = 0.0;                                                     \
   }
 
@@ -27,16 +26,16 @@
 	DD dDD = { .ld = d };
 	
 	int ilogbw = 0;
-	const double logbw = logb(__builtin_fmax( __builtin_fabs(cDD.s.hi), __builtin_fabs(dDD.s.hi) ));
+	const double logbw = crt_logb(crt_fmax(crt_fabs(cDD.s.hi), crt_fabs(dDD.s.hi) ));
 	
 	if (crt_isfinite(logbw))
 	{
 		ilogbw = (int)logbw;
 		
-		cDD.s.hi = scalbn(cDD.s.hi, -ilogbw);
-		cDD.s.lo = scalbn(cDD.s.lo, -ilogbw);
-		dDD.s.hi = scalbn(dDD.s.hi, -ilogbw);
-		dDD.s.lo = scalbn(dDD.s.lo, -ilogbw);
+		cDD.s.hi = crt_scalbn(cDD.s.hi, -ilogbw);
+		cDD.s.lo = crt_scalbn(cDD.s.lo, -ilogbw);
+		dDD.s.hi = crt_scalbn(dDD.s.hi, -ilogbw);
+		dDD.s.lo = crt_scalbn(dDD.s.lo, -ilogbw);
 	}
 	
 	const long double denom = __gcc_qadd(__gcc_qmul(cDD.ld, cDD.ld), __gcc_qmul(dDD.ld, dDD.ld));
@@ -46,10 +45,10 @@
 	DD real = { .ld = __gcc_qdiv(realNumerator, denom) };
 	DD imag = { .ld = __gcc_qdiv(imagNumerator, denom) };
 	
-	real.s.hi = scalbn(real.s.hi, -ilogbw);
-	real.s.lo = scalbn(real.s.lo, -ilogbw);
-	imag.s.hi = scalbn(imag.s.hi, -ilogbw);
-	imag.s.lo = scalbn(imag.s.lo, -ilogbw);
+	real.s.hi = crt_scalbn(real.s.hi, -ilogbw);
+	real.s.lo = crt_scalbn(real.s.lo, -ilogbw);
+	imag.s.hi = crt_scalbn(imag.s.hi, -ilogbw);
+	imag.s.lo = crt_scalbn(imag.s.lo, -ilogbw);
 	
 	if (crt_isnan(real.s.hi) && crt_isnan(imag.s.hi))
 	{
@@ -60,9 +59,9 @@
 		if ((rDD.s.hi == 0.0) && (!crt_isnan(aDD.s.hi) ||
                                           !crt_isnan(bDD.s.hi)))
 		{
-			real.s.hi = __builtin_copysign(INFINITY,cDD.s.hi) * aDD.s.hi;
+			real.s.hi = crt_copysign(CRT_INFINITY,cDD.s.hi) * aDD.s.hi;
 			real.s.lo = 0.0;
-			imag.s.hi = __builtin_copysign(INFINITY,cDD.s.hi) * bDD.s.hi;
+			imag.s.hi = crt_copysign(CRT_INFINITY,cDD.s.hi) * bDD.s.hi;
 			imag.s.lo = 0.0;
 		}
 		
@@ -71,9 +70,9 @@
 		{
 			makeFinite(aDD);
 			makeFinite(bDD);
-			real.s.hi = INFINITY * (aDD.s.hi*cDD.s.hi + bDD.s.hi*dDD.s.hi);
+			real.s.hi = CRT_INFINITY * (aDD.s.hi*cDD.s.hi + bDD.s.hi*dDD.s.hi);
 			real.s.lo = 0.0;
-			imag.s.hi = INFINITY * (bDD.s.hi*cDD.s.hi - aDD.s.hi*dDD.s.hi);
+			imag.s.hi = CRT_INFINITY * (bDD.s.hi*cDD.s.hi - aDD.s.hi*dDD.s.hi);
 			imag.s.lo = 0.0;
 		}
 		
@@ -82,9 +81,9 @@
 		{
 			makeFinite(cDD);
 			makeFinite(dDD);
-			real.s.hi = __builtin_copysign(0.0,(aDD.s.hi*cDD.s.hi + bDD.s.hi*dDD.s.hi));
+			real.s.hi = crt_copysign(0.0,(aDD.s.hi*cDD.s.hi + bDD.s.hi*dDD.s.hi));
 			real.s.lo = 0.0;
-			imag.s.hi = __builtin_copysign(0.0,(bDD.s.hi*cDD.s.hi - aDD.s.hi*dDD.s.hi));
+			imag.s.hi = crt_copysign(0.0,(bDD.s.hi*cDD.s.hi - aDD.s.hi*dDD.s.hi));
 			imag.s.lo = 0.0;
 		}
 	}

Modified: compiler-rt/trunk/lib/ppc/fixtfdi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ppc/fixtfdi.c?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ppc/fixtfdi.c (original)
+++ compiler-rt/trunk/lib/ppc/fixtfdi.c Wed Nov 16 01:33:06 2011
@@ -7,6 +7,7 @@
  */
 
 #include "DD.h"
+#include "../int_math.h"
 
 uint64_t __fixtfdi(long double input)
 {
@@ -64,7 +65,7 @@
 	/* Edge cases handled here: */
 	
 	/* |x| < 1, result is zero. */
-	if (1.0 > __builtin_fabs(x.s.hi))
+	if (1.0 > crt_fabs(x.s.hi))
 		return INT64_C(0);
 	
 	/* x very close to INT64_MIN, care must be taken to see which side we are on. */

Modified: compiler-rt/trunk/lib/ppc/multc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ppc/multc3.c?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ppc/multc3.c (original)
+++ compiler-rt/trunk/lib/ppc/multc3.c Wed Nov 16 01:33:06 2011
@@ -4,20 +4,15 @@
 
 #include "DD.h"
 #include "../int_math.h"
-#include <math.h>
-
-#if !defined(INFINITY) && defined(HUGE_VAL)
-#define INFINITY HUGE_VAL
-#endif /* INFINITY */
 
 #define makeFinite(x) { \
-    (x).s.hi = __builtin_copysign(crt_isinf((x).s.hi) ? 1.0 : 0.0, (x).s.hi); \
+    (x).s.hi = crt_copysign(crt_isinf((x).s.hi) ? 1.0 : 0.0, (x).s.hi); \
     (x).s.lo = 0.0;                                                     \
   }
 
 #define zeroNaN() { \
     if (crt_isnan((x).s.hi)) {                                          \
-      (x).s.hi = __builtin_copysign(0.0, (x).s.hi);                     \
+      (x).s.hi = crt_copysign(0.0, (x).s.hi);                     \
       (x).s.lo = 0.0;                                                   \
     }                                                                   \
   }
@@ -84,9 +79,9 @@
 		
 		if (recalc)
 		{
-			real.s.hi = INFINITY * (aDD.s.hi*cDD.s.hi - bDD.s.hi*dDD.s.hi);
+			real.s.hi = CRT_INFINITY * (aDD.s.hi*cDD.s.hi - bDD.s.hi*dDD.s.hi);
 			real.s.lo = 0.0;
-			imag.s.hi = INFINITY * (aDD.s.hi*dDD.s.hi + bDD.s.hi*cDD.s.hi);
+			imag.s.hi = CRT_INFINITY * (aDD.s.hi*dDD.s.hi + bDD.s.hi*cDD.s.hi);
 			imag.s.lo = 0.0;
 		}
 	}

Modified: compiler-rt/trunk/make/platform/clang_darwin_test_input.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin_test_input.c?rev=144786&r1=144785&r2=144786&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin_test_input.c (original)
+++ compiler-rt/trunk/make/platform/clang_darwin_test_input.c Wed Nov 16 01:33:06 2011
@@ -2,4 +2,5 @@
 
 #include <limits.h>
 #include <stdint.h>
-#include <math.h>
+#include <stdlib.h>
+#include <stdio.h>



From bob.wilson at apple.com  Wed Nov 16 01:57:21 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 16 Nov 2011 07:57:21 -0000
Subject: [llvm-commits] [llvm] r144787 -
	/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
Message-ID: <20111116075721.7A97C2A6C133@llvm.org>

Author: bwilson
Date: Wed Nov 16 01:57:21 2011
New Revision: 144787

URL: http://llvm.org/viewvc/llvm-project?rev=144787&view=rev
Log:
Record landing pads with a SmallSetVector to avoid multiple entries.

There may be many invokes that share one landing pad, and the previous code
would record the landing pad once for each invoke.  Besides the wasted
effort, a pair of volatile loads gets inserted every time the landing pad is
processed.  The rest of the code can get optimized away when a landing pad
is processed repeatedly, but the volatile loads remain, resulting in code like:

LBB35_18:
Ltmp483:
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r4, [r7, #-72]
        ldr     r2, [r7, #-68]

Modified:
    llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=144787&r1=144786&r2=144787&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Wed Nov 16 01:57:21 2011
@@ -30,6 +30,7 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/IRBuilder.h"
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
@@ -364,13 +365,13 @@
 bool SjLjEHPass::setupEntryBlockAndCallSites(Function &F) {
   SmallVector<ReturnInst*,     16> Returns;
   SmallVector<InvokeInst*,     16> Invokes;
-  SmallVector<LandingPadInst*, 16> LPads;
+  SmallSetVector<LandingPadInst*, 16> LPads;
 
   // Look through the terminators of the basic blocks to find invokes.
   for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
     if (InvokeInst *II = dyn_cast<InvokeInst>(BB->getTerminator())) {
       Invokes.push_back(II);
-      LPads.push_back(II->getUnwindDest()->getLandingPadInst());
+      LPads.insert(II->getUnwindDest()->getLandingPadInst());
     } else if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator())) {
       Returns.push_back(RI);
     }
@@ -382,7 +383,8 @@
   lowerIncomingArguments(F);
   lowerAcrossUnwindEdges(F, Invokes);
 
-  Value *FuncCtx = setupFunctionContext(F, LPads);
+  Value *FuncCtx =
+    setupFunctionContext(F, makeArrayRef(LPads.begin(), LPads.end()));
   BasicBlock *EntryBB = F.begin();
   Type *Int32Ty = Type::getInt32Ty(F.getContext());
 



From evan.cheng at apple.com  Wed Nov 16 02:38:27 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 16 Nov 2011 08:38:27 -0000
Subject: [llvm-commits] [llvm] r144788 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Support/
 include/llvm/Target/ lib/CodeGen/ lib/ExecutionEngine/MCJIT/ lib/MC/
 lib/Target/ lib/Target/ARM/ lib/Target/ARM/MCTargetDesc/
 lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CellSPU/MCTargetDesc/
 lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MBlaze/MCTargetDesc/
 lib/Target/MSP430/ lib/Target/MSP430/MCTargetDesc/ lib/Target/Mips/
 lib/Target/Mips/MCTargetDesc/ lib/Target/PTX/
 lib/Target/PTX/MCTargetDesc...
Message-ID: <20111116083828.7A3D21BE001@llvm.org>

Author: evancheng
Date: Wed Nov 16 02:38:26 2011
New Revision: 144788

URL: http://llvm.org/viewvc/llvm-project?rev=144788&view=rev
Log:
Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h
    llvm/trunk/include/llvm/MC/MCCodeGenInfo.h
    llvm/trunk/include/llvm/Support/CodeGen.h
    llvm/trunk/include/llvm/Support/TargetRegistry.h
    llvm/trunk/include/llvm/Target/TargetMachine.h
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
    llvm/trunk/lib/CodeGen/MachineFunctionAnalysis.cpp
    llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp
    llvm/trunk/lib/MC/MCCodeGenInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
    llvm/trunk/lib/Target/CBackend/CBackend.cpp
    llvm/trunk/lib/Target/CBackend/CTargetMachine.h
    llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp
    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
    llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
    llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h
    llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp
    llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
    llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp
    llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
    llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
    llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp
    llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp
    llvm/trunk/lib/Target/PTX/PTXTargetMachine.h
    llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
    llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
    llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
    llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
    llvm/trunk/lib/Target/TargetMachine.cpp
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.h
    llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
    llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
    llvm/trunk/tools/llc/llc.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunctionAnalysis.h Wed Nov 16 02:38:26 2011
@@ -26,17 +26,14 @@
 struct MachineFunctionAnalysis : public FunctionPass {
 private:
   const TargetMachine &TM;
-  CodeGenOpt::Level OptLevel;
   MachineFunction *MF;
   unsigned NextFnNum;
 public:
   static char ID;
-  explicit MachineFunctionAnalysis(const TargetMachine &tm,
-                                   CodeGenOpt::Level OL = CodeGenOpt::Default);
+  explicit MachineFunctionAnalysis(const TargetMachine &tm);
   ~MachineFunctionAnalysis();
 
   MachineFunction &getMF() const { return *MF; }
-  CodeGenOpt::Level getOptLevel() const { return OptLevel; }
   
   virtual const char* getPassName() const {
     return "Machine Function Analysis";

Modified: llvm/trunk/include/llvm/MC/MCCodeGenInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCCodeGenInfo.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCCodeGenInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCCodeGenInfo.h Wed Nov 16 02:38:26 2011
@@ -28,13 +28,20 @@
     ///
     CodeModel::Model CMModel;
 
+    /// OptLevel - Optimization level.
+    ///
+    CodeGenOpt::Level OptLevel;
+
   public:
     void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,
-                           CodeModel::Model CM = CodeModel::Default);
+                           CodeModel::Model CM = CodeModel::Default,
+                           CodeGenOpt::Level OL = CodeGenOpt::Default);
 
     Reloc::Model getRelocationModel() const { return RelocationModel; }
 
     CodeModel::Model getCodeModel() const { return CMModel; }
+
+    CodeGenOpt::Level getOptLevel() const { return OptLevel; }
   };
 } // namespace llvm
 

Modified: llvm/trunk/include/llvm/Support/CodeGen.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CodeGen.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CodeGen.h (original)
+++ llvm/trunk/include/llvm/Support/CodeGen.h Wed Nov 16 02:38:26 2011
@@ -27,6 +27,16 @@
     enum Model { Default, JITDefault, Small, Kernel, Medium, Large };
   }
 
+  // Code generation optimization level.
+  namespace CodeGenOpt {
+    enum Level {
+      None,        // -O0
+      Less,        // -O1
+      Default,     // -O2, -Os
+      Aggressive   // -O3
+    };
+  }
+
 }  // end llvm namespace
 
 #endif

Modified: llvm/trunk/include/llvm/Support/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetRegistry.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetRegistry.h (original)
+++ llvm/trunk/include/llvm/Support/TargetRegistry.h Wed Nov 16 02:38:26 2011
@@ -74,7 +74,8 @@
                                             StringRef TT);
     typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,
                                                     Reloc::Model RM,
-                                                    CodeModel::Model CM);
+                                                    CodeModel::Model CM,
+                                                    CodeGenOpt::Level OL);
     typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
     typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo*Info);
     typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
@@ -86,7 +87,8 @@
                                                   StringRef CPU,
                                                   StringRef Features,
                                                   Reloc::Model RM,
-                                                  CodeModel::Model CM);
+                                                  CodeModel::Model CM,
+                                                  CodeGenOpt::Level OL);
     typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
                                             MCStreamer &Streamer);
     typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, StringRef TT);
@@ -145,8 +147,8 @@
     /// registered.
     MCAsmInfoCtorFnTy MCAsmInfoCtorFn;
 
-    /// MCCodeGenInfoCtorFn - Constructor function for this target's MCCodeGenInfo,
-    /// if registered.
+    /// MCCodeGenInfoCtorFn - Constructor function for this target's
+    /// MCCodeGenInfo, if registered.
     MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn;
 
     /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo,
@@ -277,10 +279,11 @@
     /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
     ///
     MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM,
-                                       CodeModel::Model CM) const {
+                                       CodeModel::Model CM,
+                                       CodeGenOpt::Level OL) const {
       if (!MCCodeGenInfoCtorFn)
         return 0;
-      return MCCodeGenInfoCtorFn(Triple, RM, CM);
+      return MCCodeGenInfoCtorFn(Triple, RM, CM, OL);
     }
 
     /// createMCInstrInfo - Create a MCInstrInfo implementation.
@@ -331,12 +334,13 @@
     /// either the target triple from the module, or the target triple of the
     /// host if that does not exist.
     TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,
-                               StringRef Features,
-                               Reloc::Model RM = Reloc::Default,
-                               CodeModel::Model CM = CodeModel::Default) const {
+                             StringRef Features,
+                             Reloc::Model RM = Reloc::Default,
+                             CodeModel::Model CM = CodeModel::Default,
+                             CodeGenOpt::Level OL = CodeGenOpt::Default) const {
       if (!TargetMachineCtorFn)
         return 0;
-      return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM);
+      return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM, OL);
     }
 
     /// createMCAsmBackend - Create a target specific assembly parser.
@@ -843,8 +847,8 @@
       TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);
     }
   private:
-    static MCCodeGenInfo *Allocator(StringRef TT,
-                                    Reloc::Model RM, CodeModel::Model CM) {
+    static MCCodeGenInfo *Allocator(StringRef TT, Reloc::Model RM,
+                                    CodeModel::Model CM, CodeGenOpt::Level OL) {
       return new MCCodeGenInfoImpl();
     }
   };
@@ -1014,8 +1018,9 @@
     static TargetMachine *Allocator(const Target &T, StringRef TT,
                                     StringRef CPU, StringRef FS,
                                     Reloc::Model RM,
-                                    CodeModel::Model CM) {
-      return new TargetMachineImpl(T, TT, CPU, FS, RM, CM);
+                                    CodeModel::Model CM,
+                                    CodeGenOpt::Level OL) {
+      return new TargetMachineImpl(T, TT, CPU, FS, RM, CM, OL);
     }
   };
 

Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Wed Nov 16 02:38:26 2011
@@ -43,16 +43,6 @@
 class formatted_raw_ostream;
 class raw_ostream;
 
-// Code generation optimization level.
-namespace CodeGenOpt {
-  enum Level {
-    None,        // -O0
-    Less,        // -O1
-    Default,     // -O2, -Os
-    Aggressive   // -O3
-  };
-}
-
 namespace Sched {
   enum Preference {
     None,             // No preference
@@ -212,6 +202,10 @@
   /// medium, large, and target default.
   CodeModel::Model getCodeModel() const;
 
+  /// getOptLevel - Returns the optimization level: None, Less,
+  /// Default, or Aggressive.
+  CodeGenOpt::Level getOptLevel() const;
+
   /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
   ///
   static bool getAsmVerbosityDefault();
@@ -255,7 +249,6 @@
   virtual bool addPassesToEmitFile(PassManagerBase &,
                                    formatted_raw_ostream &,
                                    CodeGenFileType,
-                                   CodeGenOpt::Level,
                                    bool = true) {
     return true;
   }
@@ -268,7 +261,6 @@
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &,
                                           JITCodeEmitter &,
-                                          CodeGenOpt::Level,
                                           bool = true) {
     return true;
   }
@@ -281,7 +273,6 @@
   virtual bool addPassesToEmitMC(PassManagerBase &,
                                  MCContext *&,
                                  raw_ostream &,
-                                 CodeGenOpt::Level,
                                  bool = true) {
     return true;
   }
@@ -294,24 +285,23 @@
 protected: // Can only create subclasses.
   LLVMTargetMachine(const Target &T, StringRef TargetTriple,
                     StringRef CPU, StringRef FS,
-                    Reloc::Model RM, CodeModel::Model CM);
+                    Reloc::Model RM, CodeModel::Model CM,
+                    CodeGenOpt::Level OL);
 
 private:
   /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
   /// both emitting to assembly files or machine code output.
   ///
-  bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
+  bool addCommonCodeGenPasses(PassManagerBase &,
                               bool DisableVerify, MCContext *&OutCtx);
 
 public:
   /// addPassesToEmitFile - Add passes to the specified pass manager to get the
   /// specified file emitted.  Typically this will involve several steps of code
-  /// generation.  If OptLevel is None, the code generator should emit code as
-  /// fast as possible, though the generated code may be less efficient.
+  /// generation.
   virtual bool addPassesToEmitFile(PassManagerBase &PM,
                                    formatted_raw_ostream &Out,
                                    CodeGenFileType FileType,
-                                   CodeGenOpt::Level,
                                    bool DisableVerify = true);
 
   /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
@@ -322,7 +312,6 @@
   ///
   virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
                                           JITCodeEmitter &MCE,
-                                          CodeGenOpt::Level,
                                           bool DisableVerify = true);
 
   /// addPassesToEmitMC - Add passes to the specified pass manager to get
@@ -333,27 +322,26 @@
   virtual bool addPassesToEmitMC(PassManagerBase &PM,
                                  MCContext *&Ctx,
                                  raw_ostream &OS,
-                                 CodeGenOpt::Level OptLevel,
                                  bool DisableVerify = true);
 
   /// Target-Independent Code Generator Pass Configuration Options.
 
   /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
   /// passes (which are run just before instruction selector).
-  virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
+  virtual bool addPreISel(PassManagerBase &) {
     return true;
   }
 
   /// addInstSelector - This method should install an instruction selector pass,
   /// which converts from LLVM code to machine instructions.
-  virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
+  virtual bool addInstSelector(PassManagerBase &) {
     return true;
   }
 
   /// addPreRegAlloc - This method may be implemented by targets that want to
   /// run passes immediately before register allocation. This should return
   /// true if -print-machineinstrs should print after these passes.
-  virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
+  virtual bool addPreRegAlloc(PassManagerBase &) {
     return false;
   }
 
@@ -361,7 +349,7 @@
   /// to run passes after register allocation but before prolog-epilog
   /// insertion.  This should return true if -print-machineinstrs should print
   /// after these passes.
-  virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
+  virtual bool addPostRegAlloc(PassManagerBase &) {
     return false;
   }
 
@@ -369,14 +357,14 @@
   /// run passes after prolog-epilog insertion and before the second instruction
   /// scheduling pass.  This should return true if -print-machineinstrs should
   /// print after these passes.
-  virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
+  virtual bool addPreSched2(PassManagerBase &) {
     return false;
   }
 
   /// addPreEmitPass - This pass may be implemented by targets that want to run
   /// passes immediately before machine code is emitted.  This should return
   /// true if -print-machineinstrs should print out the code after the passes.
-  virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
+  virtual bool addPreEmitPass(PassManagerBase &) {
     return false;
   }
 
@@ -384,7 +372,7 @@
   /// addCodeEmitter - This pass should be overridden by the target to add a
   /// code emitter, if supported.  If this is not supported, 'true' should be
   /// returned.
-  virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
+  virtual bool addCodeEmitter(PassManagerBase &,
                               JITCodeEmitter &) {
     return true;
   }

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -114,9 +114,10 @@
 
 LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
                                      StringRef CPU, StringRef FS,
-                                     Reloc::Model RM, CodeModel::Model CM)
+                                     Reloc::Model RM, CodeModel::Model CM,
+                                     CodeGenOpt::Level OL)
   : TargetMachine(T, Triple, CPU, FS) {
-  CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM);
+  CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
   AsmInfo = T.createMCAsmInfo(Triple);
   // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
   // and if the old one gets included then MCAsmInfo will be NULL and
@@ -130,11 +131,10 @@
 bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                             formatted_raw_ostream &Out,
                                             CodeGenFileType FileType,
-                                            CodeGenOpt::Level OptLevel,
                                             bool DisableVerify) {
   // Add common CodeGen passes.
   MCContext *Context = 0;
-  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
+  if (addCommonCodeGenPasses(PM, DisableVerify, Context))
     return true;
   assert(Context != 0 && "Failed to get MCContext");
 
@@ -219,14 +219,13 @@
 ///
 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
                                                    JITCodeEmitter &JCE,
-                                                   CodeGenOpt::Level OptLevel,
                                                    bool DisableVerify) {
   // Add common CodeGen passes.
   MCContext *Ctx = 0;
-  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
+  if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
     return true;
 
-  addCodeEmitter(PM, OptLevel, JCE);
+  addCodeEmitter(PM, JCE);
   PM.add(createGCInfoDeleter());
 
   return false; // success!
@@ -240,10 +239,9 @@
 bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
                                           MCContext *&Ctx,
                                           raw_ostream &Out,
-                                          CodeGenOpt::Level OptLevel,
                                           bool DisableVerify) {
   // Add common CodeGen passes.
-  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
+  if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
     return true;
 
   if (hasMCSaveTempLabels())
@@ -295,7 +293,6 @@
 /// emitting to assembly files or machine code output.
 ///
 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
-                                               CodeGenOpt::Level OptLevel,
                                                bool DisableVerify,
                                                MCContext *&OutContext) {
   // Standard LLVM-Level Passes.
@@ -313,7 +310,7 @@
     PM.add(createVerifierPass());
 
   // Run loop strength reduction before anything else.
-  if (OptLevel != CodeGenOpt::None && !DisableLSR) {
+  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
@@ -349,12 +346,12 @@
     break;
   }
 
-  if (OptLevel != CodeGenOpt::None && !DisableCGP)
+  if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   PM.add(createStackProtectorPass(getTargetLowering()));
 
-  addPreISel(PM, OptLevel);
+  addPreISel(PM);
 
   if (PrintISelInput)
     PM.add(createPrintFunctionPass("\n\n"
@@ -377,15 +374,16 @@
   OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
 
   // Set up a MachineFunction for the rest of CodeGen to work on.
-  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
+  PM.add(new MachineFunctionAnalysis(*this));
 
   // Enable FastISel with -fast, but allow that to be overridden.
   if (EnableFastISelOption == cl::BOU_TRUE ||
-      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
+      (getOptLevel() == CodeGenOpt::None &&
+       EnableFastISelOption != cl::BOU_FALSE))
     EnableFastISel = true;
 
   // Ask the target for an isel.
-  if (addInstSelector(PM, OptLevel))
+  if (addInstSelector(PM))
     return true;
 
   // Print the instruction selected machine code...
@@ -395,21 +393,21 @@
   PM.add(createExpandISelPseudosPass());
 
   // Pre-ra tail duplication.
-  if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
+  if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
     PM.add(createTailDuplicatePass(true));
     printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
   }
 
   // Optimize PHIs before DCE: removing dead PHI cycles may make more
   // instructions dead.
-  if (OptLevel != CodeGenOpt::None)
+  if (getOptLevel() != CodeGenOpt::None)
     PM.add(createOptimizePHIsPass());
 
   // If the target requests it, assign local variables to stack slots relative
   // to one another and simplify frame index references where possible.
   PM.add(createLocalStackSlotAllocationPass());
 
-  if (OptLevel != CodeGenOpt::None) {
+  if (getOptLevel() != CodeGenOpt::None) {
     // With optimization, dead code should already be eliminated. However
     // there is one known exception: lowered code for arguments that are only
     // used by tail calls, where the tail calls reuse the incoming stack
@@ -431,15 +429,15 @@
   }
 
   // Run pre-ra passes.
-  if (addPreRegAlloc(PM, OptLevel))
+  if (addPreRegAlloc(PM))
     printAndVerify(PM, "After PreRegAlloc passes");
 
   // Perform register allocation.
-  PM.add(createRegisterAllocator(OptLevel));
+  PM.add(createRegisterAllocator(getOptLevel()));
   printAndVerify(PM, "After Register Allocation");
 
   // Perform stack slot coloring and post-ra machine LICM.
-  if (OptLevel != CodeGenOpt::None) {
+  if (getOptLevel() != CodeGenOpt::None) {
     // FIXME: Re-enable coloring with register when it's capable of adding
     // kill markers.
     if (!DisableSSC)
@@ -453,7 +451,7 @@
   }
 
   // Run post-ra passes.
-  if (addPostRegAlloc(PM, OptLevel))
+  if (addPostRegAlloc(PM))
     printAndVerify(PM, "After PostRegAlloc passes");
 
   PM.add(createExpandPostRAPseudosPass());
@@ -464,23 +462,23 @@
   printAndVerify(PM, "After PrologEpilogCodeInserter");
 
   // Run pre-sched2 passes.
-  if (addPreSched2(PM, OptLevel))
+  if (addPreSched2(PM))
     printAndVerify(PM, "After PreSched2 passes");
 
   // Second pass scheduler.
-  if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
-    PM.add(createPostRAScheduler(OptLevel));
+  if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
+    PM.add(createPostRAScheduler(getOptLevel()));
     printAndVerify(PM, "After PostRAScheduler");
   }
 
   // Branch folding must be run after regalloc and prolog/epilog insertion.
-  if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
+  if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
     printNoVerify(PM, "After BranchFolding");
   }
 
   // Tail duplication.
-  if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
+  if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
     PM.add(createTailDuplicatePass(false));
     printNoVerify(PM, "After TailDuplicate");
   }
@@ -490,7 +488,7 @@
   if (PrintGCInfo)
     PM.add(createGCInfoPrinter(dbgs()));
 
-  if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
+  if (getOptLevel() != CodeGenOpt::None && !DisableCodePlace) {
     if (EnableBlockPlacement) {
       // MachineBlockPlacement is an experimental pass which is disabled by
       // default currently. Eventually it should subsume CodePlacementOpt, so
@@ -509,7 +507,7 @@
     }
   }
 
-  if (addPreEmitPass(PM, OptLevel))
+  if (addPreEmitPass(PM))
     printNoVerify(PM, "After PreEmit passes");
 
   return false;

Modified: llvm/trunk/lib/CodeGen/MachineFunctionAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunctionAnalysis.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunctionAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunctionAnalysis.cpp Wed Nov 16 02:38:26 2011
@@ -19,9 +19,8 @@
 
 char MachineFunctionAnalysis::ID = 0;
 
-MachineFunctionAnalysis::MachineFunctionAnalysis(const TargetMachine &tm,
-                                                 CodeGenOpt::Level OL) :
-  FunctionPass(ID), TM(tm), OptLevel(OL), MF(0) {
+MachineFunctionAnalysis::MachineFunctionAnalysis(const TargetMachine &tm) :
+  FunctionPass(ID), TM(tm), MF(0) {
   initializeMachineModuleInfoPass(*PassRegistry::getPassRegistry());
 }
 

Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Wed Nov 16 02:38:26 2011
@@ -64,7 +64,7 @@
 
   // Turn the machine code intermediate representation into bytes in memory
   // that may be executed.
-  if (TM->addPassesToEmitMC(PM, Ctx, OS, CodeGenOpt::Default, false)) {
+  if (TM->addPassesToEmitMC(PM, Ctx, OS, false)) {
     report_fatal_error("Target does not support MC emission!");
   }
 

Modified: llvm/trunk/lib/MC/MCCodeGenInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCCodeGenInfo.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCCodeGenInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCCodeGenInfo.cpp Wed Nov 16 02:38:26 2011
@@ -15,7 +15,9 @@
 #include "llvm/MC/MCCodeGenInfo.h"
 using namespace llvm;
 
-void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM) {
+void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM,
+                                      CodeGenOpt::Level OL) {
   RelocationModel = RM;
   CMModel = CM;
+  OptLevel = OL;
 }

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -38,8 +38,9 @@
 ///
 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
                                            StringRef CPU, StringRef FS,
-                                           Reloc::Model RM, CodeModel::Model CM)
-  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+                                           Reloc::Model RM, CodeModel::Model CM,
+                                           CodeGenOpt::Level OL)
+  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
     Subtarget(TT, CPU, FS),
     JITInfo(),
     InstrItins(Subtarget.getInstrItineraryData()) {
@@ -50,8 +51,9 @@
 
 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
                                    StringRef CPU, StringRef FS,
-                                   Reloc::Model RM, CodeModel::Model CM)
-  : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget),
+                                   Reloc::Model RM, CodeModel::Model CM,
+                                   CodeGenOpt::Level OL)
+  : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM, OL), InstrInfo(Subtarget),
     DataLayout(Subtarget.isAPCS_ABI() ?
                std::string("e-p:32:32-f64:32:64-i64:32:64-"
                            "v128:32:128-v64:32:64-n32-S32") :
@@ -71,8 +73,9 @@
 
 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
-                                       Reloc::Model RM, CodeModel::Model CM)
-  : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM),
+                                       Reloc::Model RM, CodeModel::Model CM,
+                                       CodeGenOpt::Level OL)
+  : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM, OL),
     InstrInfo(Subtarget.hasThumb2()
               ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
               : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
@@ -95,34 +98,30 @@
               : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
 }
 
-bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
-                                      CodeGenOpt::Level OptLevel) {
-  if (OptLevel != CodeGenOpt::None && EnableGlobalMerge)
+bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM) {
+  if (getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
     PM.add(createGlobalMergePass(getTargetLowering()));
 
   return false;
 }
 
-bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
-                                           CodeGenOpt::Level OptLevel) {
-  PM.add(createARMISelDag(*this, OptLevel));
+bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM) {
+  PM.add(createARMISelDag(*this, getOptLevel()));
   return false;
 }
 
-bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
-                                          CodeGenOpt::Level OptLevel) {
+bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
-  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
+  if (getOptLevel() != CodeGenOpt::None && !Subtarget.isThumb1Only())
     PM.add(createARMLoadStoreOptimizationPass(true));
-  if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
+  if (getOptLevel() != CodeGenOpt::None && Subtarget.isCortexA9())
     PM.add(createMLxExpansionPass());
   return true;
 }
 
-bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
-                                        CodeGenOpt::Level OptLevel) {
+bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
-  if (OptLevel != CodeGenOpt::None) {
+  if (getOptLevel() != CodeGenOpt::None) {
     if (!Subtarget.isThumb1Only())
       PM.add(createARMLoadStoreOptimizationPass());
     if (Subtarget.hasNEON())
@@ -133,7 +132,7 @@
   // proper scheduling.
   PM.add(createARMExpandPseudoPass());
 
-  if (OptLevel != CodeGenOpt::None) {
+  if (getOptLevel() != CodeGenOpt::None) {
     if (!Subtarget.isThumb1Only())
       PM.add(createIfConverterPass());
   }
@@ -143,8 +142,7 @@
   return true;
 }
 
-bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
-                                          CodeGenOpt::Level OptLevel) {
+bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM) {
   if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
     PM.add(createThumb2SizeReductionPass());
 
@@ -153,7 +151,6 @@
 }
 
 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
-                                          CodeGenOpt::Level OptLevel,
                                           JITCodeEmitter &JCE) {
   // Machine code emitter pass for ARM.
   PM.add(createARMJITCodeEmitterPass(*this, JCE));

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Wed Nov 16 02:38:26 2011
@@ -41,7 +41,8 @@
 public:
   ARMBaseTargetMachine(const Target &T, StringRef TT,
                        StringRef CPU, StringRef FS,
-                       Reloc::Model RM, CodeModel::Model CM);
+                       Reloc::Model RM, CodeModel::Model CM,
+                       CodeGenOpt::Level OL);
 
   virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
   virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
@@ -50,13 +51,12 @@
   }
 
   // Pass Pipeline Configuration
-  virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
-                              JITCodeEmitter &MCE);
+  virtual bool addPreISel(PassManagerBase &PM);
+  virtual bool addInstSelector(PassManagerBase &PM);
+  virtual bool addPreRegAlloc(PassManagerBase &PM);
+  virtual bool addPreSched2(PassManagerBase &PM);
+  virtual bool addPreEmitPass(PassManagerBase &PM);
+  virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
 };
 
 /// ARMTargetMachine - ARM target machine.
@@ -71,7 +71,8 @@
  public:
   ARMTargetMachine(const Target &T, StringRef TT,
                    StringRef CPU, StringRef FS,
-                   Reloc::Model RM, CodeModel::Model CM);
+                   Reloc::Model RM, CodeModel::Model CM,
+                   CodeGenOpt::Level OL);
 
   virtual const ARMRegisterInfo  *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
@@ -111,7 +112,8 @@
 public:
   ThumbTargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS,
-                     Reloc::Model RM, CodeModel::Model CM);
+                     Reloc::Model RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL);
 
   /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
   virtual const ARMBaseRegisterInfo *getRegisterInfo() const {

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Nov 16 02:38:26 2011
@@ -129,14 +129,15 @@
 }
 
 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                             CodeModel::Model CM) {
+                                             CodeModel::Model CM,
+                                             CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (RM == Reloc::Default) {
     Triple TheTriple(TT);
     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
   }
-  X->InitMCCodeGenInfo(RM, CM);
+  X->InitMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 

Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
+++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Nov 16 02:38:26 2011
@@ -3604,7 +3604,6 @@
 bool CTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                          formatted_raw_ostream &o,
                                          CodeGenFileType FileType,
-                                         CodeGenOpt::Level OptLevel,
                                          bool DisableVerify) {
   if (FileType != TargetMachine::CGFT_AssemblyFile) return true;
 

Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Wed Nov 16 02:38:26 2011
@@ -22,13 +22,13 @@
 struct CTargetMachine : public TargetMachine {
   CTargetMachine(const Target &T, StringRef TT,
                  StringRef CPU, StringRef FS,
-                 Reloc::Model RM, CodeModel::Model CM)
+                 Reloc::Model RM, CodeModel::Model CM,
+                 CodeGenOpt::Level OL)
     : TargetMachine(T, TT, CPU, FS) {}
 
   virtual bool addPassesToEmitFile(PassManagerBase &PM,
                                    formatted_raw_ostream &Out,
                                    CodeGenFileType FileType,
-                                   CodeGenOpt::Level OptLevel,
                                    bool DisableVerify);
   
   virtual const TargetData *getTargetData() const { return 0; }

Modified: llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp Wed Nov 16 02:38:26 2011
@@ -62,11 +62,12 @@
 }
 
 static MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                      CodeModel::Model CM) {
+                                             CodeModel::Model CM,
+                                             CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   // For the time being, use static relocations, since there's really no
   // support for PIC yet.
-  X->InitMCCodeGenInfo(Reloc::Static, CM);
+  X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
   return X;
 }
 

Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -34,8 +34,9 @@
 
 SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT,
                                    StringRef CPU, StringRef FS,
-                                   Reloc::Model RM, CodeModel::Model CM)
-  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+                                   Reloc::Model RM, CodeModel::Model CM,
+                                   CodeGenOpt::Level OL)
+  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
     Subtarget(TT, CPU, FS),
     DataLayout(Subtarget.getTargetDataString()),
     InstrInfo(*this),
@@ -49,8 +50,7 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool SPUTargetMachine::addInstSelector(PassManagerBase &PM,
-                                       CodeGenOpt::Level OptLevel) {
+bool SPUTargetMachine::addInstSelector(PassManagerBase &PM) {
   // Install an instruction selector.
   PM.add(createSPUISelDag(*this));
   return false;
@@ -58,7 +58,7 @@
 
 // passes to run just before printing the assembly
 bool SPUTargetMachine::
-addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
+addPreEmitPass(PassManagerBase &PM) {
   // load the TCE instruction scheduler, if available via
   // loaded plugins
   typedef llvm::FunctionPass* (*BuilderFunc)(const char*);

Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Wed Nov 16 02:38:26 2011
@@ -40,7 +40,8 @@
 public:
   SPUTargetMachine(const Target &T, StringRef TT,
                    StringRef CPU, StringRef FS,
-                   Reloc::Model RM, CodeModel::Model CM);
+                   Reloc::Model RM, CodeModel::Model CM,
+                   CodeGenOpt::Level OL);
 
   /// Return the subtarget implementation object
   virtual const SPUSubtarget     *getSubtargetImpl() const {
@@ -81,9 +82,8 @@
   }
   
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM,
-                               CodeGenOpt::Level OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level);	
+  virtual bool addInstSelector(PassManagerBase &PM);
+  virtual bool addPreEmitPass(PassManagerBase &);	
 };
 
 } // end namespace llvm

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Wed Nov 16 02:38:26 2011
@@ -2065,7 +2065,6 @@
 bool CPPTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                            formatted_raw_ostream &o,
                                            CodeGenFileType FileType,
-                                           CodeGenOpt::Level OptLevel,
                                            bool DisableVerify) {
   if (FileType != TargetMachine::CGFT_AssemblyFile) return true;
   PM.add(new CppWriter(o));

Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Wed Nov 16 02:38:26 2011
@@ -24,13 +24,13 @@
 struct CPPTargetMachine : public TargetMachine {
   CPPTargetMachine(const Target &T, StringRef TT,
                    StringRef CPU, StringRef FS,
-                   Reloc::Model RM, CodeModel::Model CM)
+                   Reloc::Model RM, CodeModel::Model CM,
+                   CodeGenOpt::Level OL)
     : TargetMachine(T, TT, CPU, FS) {}
 
   virtual bool addPassesToEmitFile(PassManagerBase &PM,
                                    formatted_raw_ostream &Out,
                                    CodeGenFileType FileType,
-                                   CodeGenOpt::Level OptLevel,
                                    bool DisableVerify);
 
   virtual const TargetData *getTargetData() const { return 0; }

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -34,8 +34,9 @@
 MBlazeTargetMachine::
 MBlazeTargetMachine(const Target &T, StringRef TT,
                     StringRef CPU, StringRef FS,
-                    Reloc::Model RM, CodeModel::Model CM):
-  LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+                    Reloc::Model RM, CodeModel::Model CM,
+                    CodeGenOpt::Level OL):
+  LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
   Subtarget(TT, CPU, FS),
   DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
   InstrInfo(*this),
@@ -46,8 +47,7 @@
 
 // Install an instruction selector pass using
 // the ISelDag to gen MBlaze code.
-bool MBlazeTargetMachine::addInstSelector(PassManagerBase &PM,
-                                          CodeGenOpt::Level OptLevel) {
+bool MBlazeTargetMachine::addInstSelector(PassManagerBase &PM) {
   PM.add(createMBlazeISelDag(*this));
   return false;
 }
@@ -55,8 +55,7 @@
 // Implemented by targets that want to run passes immediately before
 // machine code is emitted. return true if -print-machineinstrs should
 // print out the code after the passes.
-bool MBlazeTargetMachine::addPreEmitPass(PassManagerBase &PM,
-                                         CodeGenOpt::Level OptLevel) {
+bool MBlazeTargetMachine::addPreEmitPass(PassManagerBase &PM) {
   PM.add(createMBlazeDelaySlotFillerPass(*this));
   return true;
 }

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h Wed Nov 16 02:38:26 2011
@@ -43,7 +43,8 @@
   public:
     MBlazeTargetMachine(const Target &T, StringRef TT,
                         StringRef CPU, StringRef FS,
-                        Reloc::Model RM, CodeModel::Model CM);
+                        Reloc::Model RM, CodeModel::Model CM,
+                        CodeGenOpt::Level OL);
 
     virtual const MBlazeInstrInfo *getInstrInfo() const
     { return &InstrInfo; }
@@ -77,8 +78,8 @@
     }
 
     // Pass Pipeline Configuration
-    virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level Opt);
-    virtual bool addPreEmitPass(PassManagerBase &PM,CodeGenOpt::Level Opt);
+    virtual bool addInstSelector(PassManagerBase &PM);
+    virtual bool addPreEmitPass(PassManagerBase &PM);
   };
 } // End llvm namespace
 

Modified: llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Wed Nov 16 02:38:26 2011
@@ -62,13 +62,14 @@
 }
 
 static MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                                CodeModel::Model CM) {
+                                                CodeModel::Model CM,
+                                                CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (RM == Reloc::Default)
     RM = Reloc::Static;
   if (CM == CodeModel::Default)
     CM = CodeModel::Small;
-  X->InitMCCodeGenInfo(RM, CM);
+  X->InitMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 

Modified: llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp Wed Nov 16 02:38:26 2011
@@ -51,9 +51,10 @@
 }
 
 static MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                                CodeModel::Model CM) {
+                                                CodeModel::Model CM,
+                                                CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
-  X->InitMCCodeGenInfo(RM, CM);
+  X->InitMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 

Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -28,8 +28,9 @@
                                          StringRef TT,
                                          StringRef CPU,
                                          StringRef FS,
-                                         Reloc::Model RM, CodeModel::Model CM)
-  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+                                         Reloc::Model RM, CodeModel::Model CM,
+                                         CodeGenOpt::Level OL)
+  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
     Subtarget(TT, CPU, FS),
     // FIXME: Check TargetData string.
     DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
@@ -37,15 +38,13 @@
     FrameLowering(Subtarget) { }
 
 
-bool MSP430TargetMachine::addInstSelector(PassManagerBase &PM,
-                                          CodeGenOpt::Level OptLevel) {
+bool MSP430TargetMachine::addInstSelector(PassManagerBase &PM) {
   // Install an instruction selector.
-  PM.add(createMSP430ISelDag(*this, OptLevel));
+  PM.add(createMSP430ISelDag(*this, getOptLevel()));
   return false;
 }
 
-bool MSP430TargetMachine::addPreEmitPass(PassManagerBase &PM,
-                                         CodeGenOpt::Level OptLevel) {
+bool MSP430TargetMachine::addPreEmitPass(PassManagerBase &PM) {
   // Must run branch selection immediately preceding the asm printer.
   PM.add(createMSP430BranchSelectionPass());
   return false;

Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h Wed Nov 16 02:38:26 2011
@@ -40,7 +40,8 @@
 public:
   MSP430TargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS,
-                      Reloc::Model RM, CodeModel::Model CM);
+                      Reloc::Model RM, CodeModel::Model CM,
+                      CodeGenOpt::Level OL);
 
   virtual const TargetFrameLowering *getFrameLowering() const {
     return &FrameLowering;
@@ -61,8 +62,8 @@
     return &TSInfo;
   }
 
-  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addInstSelector(PassManagerBase &PM);
+  virtual bool addPreEmitPass(PassManagerBase &PM);
 }; // MSP430TargetMachine.
 
 } // end namespace llvm

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Wed Nov 16 02:38:26 2011
@@ -63,11 +63,12 @@
 }
 
 static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                              CodeModel::Model CM) {
+                                              CodeModel::Model CM,
+                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
   if (RM == Reloc::Default)
     RM = Reloc::PIC_;
-  X->InitMCCodeGenInfo(RM, CM);
+  X->InitMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -36,8 +36,9 @@
 MipsTargetMachine(const Target &T, StringRef TT,
                   StringRef CPU, StringRef FS,
                   Reloc::Model RM, CodeModel::Model CM,
+                  CodeGenOpt::Level OL,
                   bool isLittle):
-  LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+  LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
   Subtarget(TT, CPU, FS, isLittle),
   DataLayout(isLittle ?
              (Subtarget.isABI_N64() ?
@@ -54,31 +55,35 @@
 MipsebTargetMachine::
 MipsebTargetMachine(const Target &T, StringRef TT,
                     StringRef CPU, StringRef FS,
-                    Reloc::Model RM, CodeModel::Model CM) :
-  MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {}
+                    Reloc::Model RM, CodeModel::Model CM,
+                    CodeGenOpt::Level OL) :
+  MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {}
 
 MipselTargetMachine::
 MipselTargetMachine(const Target &T, StringRef TT,
                     StringRef CPU, StringRef FS,
-                    Reloc::Model RM, CodeModel::Model CM) :
-  MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
+                    Reloc::Model RM, CodeModel::Model CM,
+                    CodeGenOpt::Level OL) :
+  MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {}
 
 Mips64ebTargetMachine::
 Mips64ebTargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS,
-                      Reloc::Model RM, CodeModel::Model CM) :
-  MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {}
+                      Reloc::Model RM, CodeModel::Model CM,
+                      CodeGenOpt::Level OL) :
+  MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {}
 
 Mips64elTargetMachine::
 Mips64elTargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS,
-                      Reloc::Model RM, CodeModel::Model CM) :
-  MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
+                      Reloc::Model RM, CodeModel::Model CM,
+                      CodeGenOpt::Level OL) :
+  MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {}
 
 // Install an instruction selector pass using
 // the ISelDag to gen Mips code.
 bool MipsTargetMachine::
-addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
+addInstSelector(PassManagerBase &PM)
 {
   PM.add(createMipsISelDag(*this));
   return false;
@@ -88,14 +93,14 @@
 // machine code is emitted. return true if -print-machineinstrs should
 // print out the code after the passes.
 bool MipsTargetMachine::
-addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
+addPreEmitPass(PassManagerBase &PM)
 {
   PM.add(createMipsDelaySlotFillerPass(*this));
   return true;
 }
 
 bool MipsTargetMachine::
-addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
+addPreRegAlloc(PassManagerBase &PM) {
   // Do not restore $gp if target is Mips64.
   // In N32/64, $gp is a callee-saved register.
   if (!Subtarget.hasMips64())
@@ -104,14 +109,13 @@
 }
 
 bool MipsTargetMachine::
-addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
+addPostRegAlloc(PassManagerBase &PM) {
   PM.add(createMipsExpandPseudoPass(*this));
   return true;
 }
 
 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
-                                          CodeGenOpt::Level OptLevel,
-                                          JITCodeEmitter &JCE) {
+                                       JITCodeEmitter &JCE) {
   // Machine code emitter pass for Mips.
   PM.add(createMipsJITCodeEmitterPass(*this, JCE));
   return false;

Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Wed Nov 16 02:38:26 2011
@@ -40,6 +40,7 @@
     MipsTargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS,
                       Reloc::Model RM, CodeModel::Model CM,
+                      CodeGenOpt::Level OL,
                       bool isLittle);
 
     virtual const MipsInstrInfo   *getInstrInfo()     const
@@ -67,15 +68,11 @@
     }
 
     // Pass Pipeline Configuration
-    virtual bool addInstSelector(PassManagerBase &PM,
-                                 CodeGenOpt::Level OptLevel);
-    virtual bool addPreEmitPass(PassManagerBase &PM,
-                                CodeGenOpt::Level OptLevel);
-    virtual bool addPreRegAlloc(PassManagerBase &PM,
-                                CodeGenOpt::Level OptLevel);
-    virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level);
+    virtual bool addInstSelector(PassManagerBase &PM);
+    virtual bool addPreEmitPass(PassManagerBase &PM);
+    virtual bool addPreRegAlloc(PassManagerBase &PM);
+    virtual bool addPostRegAlloc(PassManagerBase &);
     virtual bool addCodeEmitter(PassManagerBase &PM,
-				 CodeGenOpt::Level OptLevel,
 				 JITCodeEmitter &JCE);
 
   };
@@ -86,7 +83,8 @@
 public:
   MipsebTargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS,
-                      Reloc::Model RM, CodeModel::Model CM);
+                      Reloc::Model RM, CodeModel::Model CM,
+                      CodeGenOpt::Level OL);
 };
 
 /// MipselTargetMachine - Mips32 little endian target machine.
@@ -95,7 +93,8 @@
 public:
   MipselTargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS,
-                      Reloc::Model RM, CodeModel::Model CM);
+                      Reloc::Model RM, CodeModel::Model CM,
+                      CodeGenOpt::Level OL);
 };
 
 /// Mips64ebTargetMachine - Mips64 big endian target machine.
@@ -104,7 +103,8 @@
 public:
   Mips64ebTargetMachine(const Target &T, StringRef TT,
                         StringRef CPU, StringRef FS,
-                        Reloc::Model RM, CodeModel::Model CM);
+                        Reloc::Model RM, CodeModel::Model CM,
+                        CodeGenOpt::Level OL);
 };
 
 /// Mips64elTargetMachine - Mips64 little endian target machine.
@@ -113,7 +113,8 @@
 public:
   Mips64elTargetMachine(const Target &T, StringRef TT,
                         StringRef CPU, StringRef FS,
-                        Reloc::Model RM, CodeModel::Model CM);
+                        Reloc::Model RM, CodeModel::Model CM,
+                        CodeGenOpt::Level OL);
 };
 } // End llvm namespace
 

Modified: llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp Wed Nov 16 02:38:26 2011
@@ -52,9 +52,10 @@
 }
 
 static MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                             CodeModel::Model CM) {
+                                             CodeModel::Model CM,
+                                             CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
-  X->InitMCCodeGenInfo(RM, CM);
+  X->InitMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 

Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -88,8 +88,9 @@
 PTXTargetMachine::PTXTargetMachine(const Target &T,
                                    StringRef TT, StringRef CPU, StringRef FS,
                                    Reloc::Model RM, CodeModel::Model CM,
+                                   CodeGenOpt::Level OL,
                                    bool is64Bit)
-  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
     DataLayout(is64Bit ? DataLayout64 : DataLayout32),
     Subtarget(TT, CPU, FS, is64Bit),
     FrameLowering(Subtarget),
@@ -100,39 +101,38 @@
 
 PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
-                                       Reloc::Model RM, CodeModel::Model CM)
-  : PTXTargetMachine(T, TT, CPU, FS, RM, CM, false) {
+                                       Reloc::Model RM, CodeModel::Model CM,
+                                       CodeGenOpt::Level OL)
+  : PTXTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
 }
 
 PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
-                                       Reloc::Model RM, CodeModel::Model CM)
-  : PTXTargetMachine(T, TT, CPU, FS, RM, CM, true) {
+                                       Reloc::Model RM, CodeModel::Model CM,
+                                       CodeGenOpt::Level OL)
+  : PTXTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
 }
 
-bool PTXTargetMachine::addInstSelector(PassManagerBase &PM,
-                                       CodeGenOpt::Level OptLevel) {
-  PM.add(createPTXISelDag(*this, OptLevel));
+bool PTXTargetMachine::addInstSelector(PassManagerBase &PM) {
+  PM.add(createPTXISelDag(*this, getOptLevel()));
   return false;
 }
 
-bool PTXTargetMachine::addPostRegAlloc(PassManagerBase &PM,
-                                       CodeGenOpt::Level OptLevel) {
+bool PTXTargetMachine::addPostRegAlloc(PassManagerBase &PM) {
   // PTXMFInfoExtract must after register allocation!
-  //PM.add(createPTXMFInfoExtract(*this, OptLevel));
+  //PM.add(createPTXMFInfoExtract(*this));
   return false;
 }
 
 bool PTXTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                            formatted_raw_ostream &Out,
                                            CodeGenFileType FileType,
-                                           CodeGenOpt::Level OptLevel,
                                            bool DisableVerify) {
   // This is mostly based on LLVMTargetMachine::addPassesToEmitFile
 
   // Add common CodeGen passes.
   MCContext *Context = 0;
-  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
+  if (addCommonCodeGenPasses(PM, DisableVerify, Context))
     return true;
   assert(Context != 0 && "Failed to get MCContext");
 
@@ -192,7 +192,6 @@
 }
 
 bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
-                                              CodeGenOpt::Level OptLevel,
                                               bool DisableVerify,
                                               MCContext *&OutContext) {
   // Add standard LLVM codegen passes.
@@ -214,7 +213,7 @@
     PM.add(createVerifierPass());
 
   // Run loop strength reduction before anything else.
-  if (OptLevel != CodeGenOpt::None) {
+  if (getOptLevel() != CodeGenOpt::None) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     //PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
   }
@@ -228,12 +227,12 @@
   // The lower invoke pass may create unreachable code. Remove it.
   PM.add(createUnreachableBlockEliminationPass());
 
-  if (OptLevel != CodeGenOpt::None)
+  if (getOptLevel() != CodeGenOpt::None)
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   PM.add(createStackProtectorPass(getTargetLowering()));
 
-  addPreISel(PM, OptLevel);
+  addPreISel(PM);
 
   //PM.add(createPrintFunctionPass("\n\n"
   //                               "*** Final LLVM Code input to ISel ***\n",
@@ -255,10 +254,10 @@
   OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
 
   // Set up a MachineFunction for the rest of CodeGen to work on.
-  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
+  PM.add(new MachineFunctionAnalysis(*this));
 
   // Ask the target for an isel.
-  if (addInstSelector(PM, OptLevel))
+  if (addInstSelector(PM))
     return true;
 
   // Print the instruction selected machine code...
@@ -268,21 +267,21 @@
   PM.add(createExpandISelPseudosPass());
 
   // Pre-ra tail duplication.
-  if (OptLevel != CodeGenOpt::None) {
+  if (getOptLevel() != CodeGenOpt::None) {
     PM.add(createTailDuplicatePass(true));
     printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
   }
 
   // Optimize PHIs before DCE: removing dead PHI cycles may make more
   // instructions dead.
-  if (OptLevel != CodeGenOpt::None)
+  if (getOptLevel() != CodeGenOpt::None)
     PM.add(createOptimizePHIsPass());
 
   // If the target requests it, assign local variables to stack slots relative
   // to one another and simplify frame index references where possible.
   PM.add(createLocalStackSlotAllocationPass());
 
-  if (OptLevel != CodeGenOpt::None) {
+  if (getOptLevel() != CodeGenOpt::None) {
     // With optimization, dead code should already be eliminated. However
     // there is one known exception: lowered code for arguments that are only
     // used by tail calls, where the tail calls reuse the incoming stack
@@ -300,7 +299,7 @@
   }
 
   // Run pre-ra passes.
-  if (addPreRegAlloc(PM, OptLevel))
+  if (addPreRegAlloc(PM))
     printAndVerify(PM, "After PreRegAlloc passes");
 
   // Perform register allocation.
@@ -308,7 +307,7 @@
   printAndVerify(PM, "After Register Allocation");
 
   // Perform stack slot coloring and post-ra machine LICM.
-  if (OptLevel != CodeGenOpt::None) {
+  if (getOptLevel() != CodeGenOpt::None) {
     // FIXME: Re-enable coloring with register when it's capable of adding
     // kill markers.
     PM.add(createStackSlotColoringPass(false));
@@ -322,7 +321,7 @@
   }
 
   // Run post-ra passes.
-  if (addPostRegAlloc(PM, OptLevel))
+  if (addPostRegAlloc(PM))
     printAndVerify(PM, "After PostRegAlloc passes");
 
   PM.add(createExpandPostRAPseudosPass());
@@ -333,23 +332,23 @@
   printAndVerify(PM, "After PrologEpilogCodeInserter");
 
   // Run pre-sched2 passes.
-  if (addPreSched2(PM, OptLevel))
+  if (addPreSched2(PM))
     printAndVerify(PM, "After PreSched2 passes");
 
   // Second pass scheduler.
-  if (OptLevel != CodeGenOpt::None) {
-    PM.add(createPostRAScheduler(OptLevel));
+  if (getOptLevel() != CodeGenOpt::None) {
+    PM.add(createPostRAScheduler(getOptLevel()));
     printAndVerify(PM, "After PostRAScheduler");
   }
 
   // Branch folding must be run after regalloc and prolog/epilog insertion.
-  if (OptLevel != CodeGenOpt::None) {
+  if (getOptLevel() != CodeGenOpt::None) {
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
     printNoVerify(PM, "After BranchFolding");
   }
 
   // Tail duplication.
-  if (OptLevel != CodeGenOpt::None) {
+  if (getOptLevel() != CodeGenOpt::None) {
     PM.add(createTailDuplicatePass(false));
     printNoVerify(PM, "After TailDuplicate");
   }
@@ -359,16 +358,16 @@
   //if (PrintGCInfo)
   //  PM.add(createGCInfoPrinter(dbgs()));
 
-  if (OptLevel != CodeGenOpt::None) {
+  if (getOptLevel() != CodeGenOpt::None) {
     PM.add(createCodePlacementOptPass());
     printNoVerify(PM, "After CodePlacementOpt");
   }
 
-  if (addPreEmitPass(PM, OptLevel))
+  if (addPreEmitPass(PM))
     printNoVerify(PM, "After PreEmit passes");
 
-  PM.add(createPTXMFInfoExtract(*this, OptLevel));
-  PM.add(createPTXFPRoundingModePass(*this, OptLevel));
+  PM.add(createPTXMFInfoExtract(*this, getOptLevel()));
+  PM.add(createPTXFPRoundingModePass(*this, getOptLevel()));
 
   return false;
 }

Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXTargetMachine.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.h Wed Nov 16 02:38:26 2011
@@ -37,6 +37,7 @@
     PTXTargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS,
                      Reloc::Model RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL,
                      bool is64Bit);
 
     virtual const TargetData *getTargetData() const { return &DataLayout; }
@@ -58,22 +59,18 @@
 
     virtual const PTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
 
-    virtual bool addInstSelector(PassManagerBase &PM,
-                                 CodeGenOpt::Level OptLevel);
-    virtual bool addPostRegAlloc(PassManagerBase &PM,
-                                 CodeGenOpt::Level OptLevel);
+    virtual bool addInstSelector(PassManagerBase &PM);
+    virtual bool addPostRegAlloc(PassManagerBase &PM);
 
     // We override this method to supply our own set of codegen passes.
     virtual bool addPassesToEmitFile(PassManagerBase &,
                                      formatted_raw_ostream &,
                                      CodeGenFileType,
-                                     CodeGenOpt::Level,
                                      bool = true);
 
     // Emission of machine code through JITCodeEmitter is not supported.
     virtual bool addPassesToEmitMachineCode(PassManagerBase &,
                                             JITCodeEmitter &,
-                                            CodeGenOpt::Level,
                                             bool = true) {
       return true;
     }
@@ -82,14 +79,13 @@
     virtual bool addPassesToEmitMC(PassManagerBase &,
                                    MCContext *&,
                                    raw_ostream &,
-                                   CodeGenOpt::Level,
                                    bool = true) {
       return true;
     }
 
   private:
 
-    bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
+    bool addCommonCodeGenPasses(PassManagerBase &,
                                 bool DisableVerify, MCContext *&OutCtx);
 }; // class PTXTargetMachine
 
@@ -99,7 +95,8 @@
 
   PTX32TargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS,
-                     Reloc::Model RM, CodeModel::Model CM);
+                     Reloc::Model RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL);
 }; // class PTX32TargetMachine
 
 class PTX64TargetMachine : public PTXTargetMachine {
@@ -107,7 +104,8 @@
 
   PTX64TargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS,
-                     Reloc::Model RM, CodeModel::Model CM);
+                     Reloc::Model RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL);
 }; // class PTX32TargetMachine
 
 } // namespace llvm

Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Wed Nov 16 02:38:26 2011
@@ -76,7 +76,8 @@
 }
 
 static MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                             CodeModel::Model CM) {
+                                             CodeModel::Model CM,
+                                             CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   if (RM == Reloc::Default) {
@@ -86,7 +87,7 @@
     else
       RM = Reloc::Static;
   }
-  X->InitMCCodeGenInfo(RM, CM);
+  X->InitMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Nov 16 02:38:26 2011
@@ -18,7 +18,6 @@
 #include "MCTargetDesc/PPCPredicates.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFunctionAnalysis.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -29,8 +29,9 @@
 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
                                    StringRef CPU, StringRef FS,
                                    Reloc::Model RM, CodeModel::Model CM,
+                                   CodeGenOpt::Level OL,
                                    bool is64Bit)
-  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
     Subtarget(TT, CPU, FS, is64Bit),
     DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
     FrameLowering(Subtarget), JITInfo(*this, is64Bit),
@@ -44,15 +45,17 @@
 
 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, 
                                        StringRef CPU, StringRef FS,
-                                       Reloc::Model RM, CodeModel::Model CM) 
-  : PPCTargetMachine(T, TT, CPU, FS, RM, CM, false) {
+                                       Reloc::Model RM, CodeModel::Model CM,
+                                       CodeGenOpt::Level OL)
+  : PPCTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
 }
 
 
 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, 
                                        StringRef CPU,  StringRef FS,
-                                       Reloc::Model RM, CodeModel::Model CM)
-  : PPCTargetMachine(T, TT, CPU, FS, RM, CM, true) {
+                                       Reloc::Model RM, CodeModel::Model CM,
+                                       CodeGenOpt::Level OL)
+  : PPCTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
 }
 
 
@@ -60,22 +63,19 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
-                                       CodeGenOpt::Level OptLevel) {
+bool PPCTargetMachine::addInstSelector(PassManagerBase &PM) {
   // Install an instruction selector.
   PM.add(createPPCISelDag(*this));
   return false;
 }
 
-bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
-                                      CodeGenOpt::Level OptLevel) {
+bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM) {
   // Must run branch selection immediately preceding the asm printer.
   PM.add(createPPCBranchSelectionPass());
   return false;
 }
 
 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
-                                      CodeGenOpt::Level OptLevel,
                                       JITCodeEmitter &JCE) {
   // FIXME: This should be moved to TargetJITInfo!!
   if (Subtarget.isPPC64())

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Wed Nov 16 02:38:26 2011
@@ -42,7 +42,8 @@
 public:
   PPCTargetMachine(const Target &T, StringRef TT,
                    StringRef CPU, StringRef FS,
-                   Reloc::Model RM, CodeModel::Model CM, bool is64Bit);
+                   Reloc::Model RM, CodeModel::Model CM,
+                   CodeGenOpt::Level OL, bool is64Bit);
 
   virtual const PPCInstrInfo      *getInstrInfo() const { return &InstrInfo; }
   virtual const PPCFrameLowering  *getFrameLowering() const {
@@ -66,9 +67,9 @@
   }
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
+  virtual bool addInstSelector(PassManagerBase &PM);
+  virtual bool addPreEmitPass(PassManagerBase &PM);
+  virtual bool addCodeEmitter(PassManagerBase &PM,
                               JITCodeEmitter &JCE);
   virtual bool getEnableTailMergeDefault() const;
 };
@@ -79,7 +80,8 @@
 public:
   PPC32TargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS,
-                     Reloc::Model RM, CodeModel::Model CM);
+                     Reloc::Model RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL);
 };
 
 /// PPC64TargetMachine - PowerPC 64-bit target machine.
@@ -88,7 +90,8 @@
 public:
   PPC64TargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS,
-                     Reloc::Model RM, CodeModel::Model CM);
+                     Reloc::Model RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL);
 };
 
 } // end namespace llvm

Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp Wed Nov 16 02:38:26 2011
@@ -50,9 +50,10 @@
 }
 
 static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                               CodeModel::Model CM) {
+                                               CodeModel::Model CM,
+                                               CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
-  X->InitMCCodeGenInfo(RM, CM);
+  X->InitMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 

Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -27,16 +27,16 @@
 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, 
                                        StringRef CPU, StringRef FS,
                                        Reloc::Model RM, CodeModel::Model CM,
+                                       CodeGenOpt::Level OL,
                                        bool is64bit)
-  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
     Subtarget(TT, CPU, FS, is64bit),
     DataLayout(Subtarget.getDataLayout()),
     TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
     FrameLowering(Subtarget) {
 }
 
-bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         CodeGenOpt::Level OptLevel) {
+bool SparcTargetMachine::addInstSelector(PassManagerBase &PM) {
   PM.add(createSparcISelDag(*this));
   return false;
 }
@@ -44,8 +44,7 @@
 /// addPreEmitPass - This pass may be implemented by targets that want to run
 /// passes immediately before machine code is emitted.  This should return
 /// true if -print-machineinstrs should print out the code after the passes.
-bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
-                                        CodeGenOpt::Level OptLevel){
+bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM){
   PM.add(createSparcFPMoverPass(*this));
   PM.add(createSparcDelaySlotFillerPass(*this));
   return true;
@@ -54,13 +53,15 @@
 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
                                            StringRef TT, StringRef CPU,
                                            StringRef FS, Reloc::Model RM,
-                                           CodeModel::Model CM)
-  : SparcTargetMachine(T, TT, CPU, FS, RM, CM, false) {
+                                           CodeModel::Model CM,
+                                           CodeGenOpt::Level OL)
+  : SparcTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
 }
 
 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, 
                                            StringRef TT,  StringRef CPU,
                                            StringRef FS, Reloc::Model RM,
-                                           CodeModel::Model CM)
-  : SparcTargetMachine(T, TT, CPU, FS, RM, CM, true) {
+                                           CodeModel::Model CM,
+                                           CodeGenOpt::Level OL)
+  : SparcTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
 }

Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Wed Nov 16 02:38:26 2011
@@ -35,7 +35,8 @@
 public:
   SparcTargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS,
-                     Reloc::Model RM, CodeModel::Model CM, bool is64bit);
+                     Reloc::Model RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL,  bool is64bit);
 
   virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
   virtual const TargetFrameLowering  *getFrameLowering() const {
@@ -54,8 +55,8 @@
   virtual const TargetData       *getTargetData() const { return &DataLayout; }
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addInstSelector(PassManagerBase &PM);
+  virtual bool addPreEmitPass(PassManagerBase &PM);
 };
 
 /// SparcV8TargetMachine - Sparc 32-bit target machine
@@ -64,7 +65,8 @@
 public:
   SparcV8TargetMachine(const Target &T, StringRef TT,
                        StringRef CPU, StringRef FS,
-                       Reloc::Model RM, CodeModel::Model CM);
+                       Reloc::Model RM, CodeModel::Model CM,
+                       CodeGenOpt::Level OL);
 };
 
 /// SparcV9TargetMachine - Sparc 64-bit target machine
@@ -73,7 +75,8 @@
 public:
   SparcV9TargetMachine(const Target &T, StringRef TT,
                        StringRef CPU, StringRef FS,
-                       Reloc::Model RM, CodeModel::Model CM);
+                       Reloc::Model RM, CodeModel::Model CM,
+                       CodeGenOpt::Level OL);
 };
 
 } // end namespace llvm

Modified: llvm/trunk/lib/Target/TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/TargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -226,6 +226,14 @@
   return CodeGenInfo->getCodeModel();
 }
 
+/// getOptLevel - Returns the optimization level: None, Less,
+/// Default, or Aggressive.
+CodeGenOpt::Level TargetMachine::getOptLevel() const {
+  if (!CodeGenInfo)
+    return CodeGenOpt::Default;
+  return CodeGenInfo->getOptLevel();
+}
+
 bool TargetMachine::getAsmVerbosityDefault() {
   return AsmVerbosityDefault;
 }

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Wed Nov 16 02:38:26 2011
@@ -385,7 +385,8 @@
 }
 
 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                             CodeModel::Model CM) {
+                                             CodeModel::Model CM,
+                                             CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
 
   Triple T(TT);
@@ -429,7 +430,7 @@
     // 64-bit JIT places everything in the same buffer except external funcs.
     CM = is64Bit ? CodeModel::Large : CodeModel::Small;
 
-  X->InitMCCodeGenInfo(RM, CM);
+  X->InitMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -31,8 +31,9 @@
 
 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
                                          StringRef CPU, StringRef FS,
-                                         Reloc::Model RM, CodeModel::Model CM)
-  : X86TargetMachine(T, TT, CPU, FS, RM, CM, false),
+                                         Reloc::Model RM, CodeModel::Model CM,
+                                         CodeGenOpt::Level OL)
+  : X86TargetMachine(T, TT, CPU, FS, RM, CM, OL, false),
     DataLayout(getSubtargetImpl()->isTargetDarwin() ?
                "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
                "n8:16:32-S128" :
@@ -51,8 +52,9 @@
 
 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
                                          StringRef CPU, StringRef FS,
-                                         Reloc::Model RM, CodeModel::Model CM)
-  : X86TargetMachine(T, TT, CPU, FS, RM, CM, true),
+                                         Reloc::Model RM, CodeModel::Model CM,
+                                         CodeGenOpt::Level OL)
+  : X86TargetMachine(T, TT, CPU, FS, RM, CM, OL, true),
     DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
                "n8:16:32:64-S128"),
     InstrInfo(*this),
@@ -66,8 +68,9 @@
 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
                                    StringRef CPU, StringRef FS,
                                    Reloc::Model RM, CodeModel::Model CM,
+                                   CodeGenOpt::Level OL,
                                    bool is64Bit)
-  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
     Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
     FrameLowering(*this, Subtarget),
     ELFWriterInfo(is64Bit, true) {
@@ -108,10 +111,9 @@
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
-bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
-                                       CodeGenOpt::Level OptLevel) {
+bool X86TargetMachine::addInstSelector(PassManagerBase &PM) {
   // Install an instruction selector.
-  PM.add(createX86ISelDag(*this, OptLevel));
+  PM.add(createX86ISelDag(*this, getOptLevel()));
 
   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
   if (!Subtarget.is64Bit())
@@ -120,22 +122,19 @@
   return false;
 }
 
-bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
-                                      CodeGenOpt::Level OptLevel) {
+bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM) {
   PM.add(createX86MaxStackAlignmentHeuristicPass());
   return false;  // -print-machineinstr shouldn't print after this.
 }
 
-bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
-                                       CodeGenOpt::Level OptLevel) {
+bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM) {
   PM.add(createX86FloatingPointStackifierPass());
   return true;  // -print-machineinstr should print after this.
 }
 
-bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
-                                      CodeGenOpt::Level OptLevel) {
+bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM) {
   bool ShouldPrint = false;
-  if (OptLevel != CodeGenOpt::None && Subtarget.hasXMMInt()) {
+  if (getOptLevel() != CodeGenOpt::None && Subtarget.hasXMMInt()) {
     PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
     ShouldPrint = true;
   }
@@ -149,7 +148,6 @@
 }
 
 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
-                                      CodeGenOpt::Level OptLevel,
                                       JITCodeEmitter &JCE) {
   PM.add(createX86JITCodeEmitterPass(*this, JCE));
 

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Wed Nov 16 02:38:26 2011
@@ -40,6 +40,7 @@
   X86TargetMachine(const Target &T, StringRef TT, 
                    StringRef CPU, StringRef FS,
                    Reloc::Model RM, CodeModel::Model CM,
+                   CodeGenOpt::Level OL,
                    bool is64Bit);
 
   virtual const X86InstrInfo     *getInstrInfo() const {
@@ -66,11 +67,11 @@
   }
 
   // Set up the pass pipeline.
-  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
+  virtual bool addInstSelector(PassManagerBase &PM);
+  virtual bool addPreRegAlloc(PassManagerBase &PM);
+  virtual bool addPostRegAlloc(PassManagerBase &PM);
+  virtual bool addPreEmitPass(PassManagerBase &PM);
+  virtual bool addCodeEmitter(PassManagerBase &PM,
                               JITCodeEmitter &JCE);
 };
 
@@ -85,7 +86,8 @@
 public:
   X86_32TargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS,
-                      Reloc::Model RM, CodeModel::Model CM);
+                      Reloc::Model RM, CodeModel::Model CM,
+                      CodeGenOpt::Level OL);
   virtual const TargetData *getTargetData() const { return &DataLayout; }
   virtual const X86TargetLowering *getTargetLowering() const {
     return &TLInfo;
@@ -112,7 +114,8 @@
 public:
   X86_64TargetMachine(const Target &T, StringRef TT,
                       StringRef CPU, StringRef FS,
-                      Reloc::Model RM, CodeModel::Model CM);
+                      Reloc::Model RM, CodeModel::Model CM,
+                      CodeGenOpt::Level OL);
   virtual const TargetData *getTargetData() const { return &DataLayout; }
   virtual const X86TargetLowering *getTargetLowering() const {
     return &TLInfo;

Modified: llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp Wed Nov 16 02:38:26 2011
@@ -61,9 +61,10 @@
 }
 
 static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                               CodeModel::Model CM) {
+                                               CodeModel::Model CM,
+                                               CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
-  X->InitMCCodeGenInfo(RM, CM);
+  X->InitMCCodeGenInfo(RM, CM, OL);
   return X;
 }
 

Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Wed Nov 16 02:38:26 2011
@@ -21,8 +21,9 @@
 ///
 XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
-                                       Reloc::Model RM, CodeModel::Model CM)
-  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+                                       Reloc::Model RM, CodeModel::Model CM,
+                                       CodeGenOpt::Level OL)
+  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
     Subtarget(TT, CPU, FS),
     DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
                "i16:16:32-i32:32:32-i64:32:32-n32"),
@@ -32,8 +33,7 @@
     TSInfo(*this) {
 }
 
-bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         CodeGenOpt::Level OptLevel) {
+bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM) {
   PM.add(createXCoreISelDag(*this));
   return false;
 }

Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Wed Nov 16 02:38:26 2011
@@ -34,7 +34,8 @@
 public:
   XCoreTargetMachine(const Target &T, StringRef TT,
                      StringRef CPU, StringRef FS,
-                     Reloc::Model RM, CodeModel::Model CM);
+                     Reloc::Model RM, CodeModel::Model CM,
+                     CodeGenOpt::Level OL);
 
   virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; }
   virtual const XCoreFrameLowering *getFrameLowering() const {
@@ -55,7 +56,7 @@
   virtual const TargetData       *getTargetData() const { return &DataLayout; }
 
   // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addInstSelector(PassManagerBase &PM);
 };
 
 } // end namespace llvm

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=144788&r1=144787&r2=144788&view=diff
==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Wed Nov 16 02:38:26 2011
@@ -306,10 +306,22 @@
     FeaturesStr = Features.getString();
   }
 
+  CodeGenOpt::Level OLvl = CodeGenOpt::Default;
+  switch (OptLevel) {
+  default:
+    errs() << argv[0] << ": invalid optimization level.\n";
+    return 1;
+  case ' ': break;
+  case '0': OLvl = CodeGenOpt::None; break;
+  case '1': OLvl = CodeGenOpt::Less; break;
+  case '2': OLvl = CodeGenOpt::Default; break;
+  case '3': OLvl = CodeGenOpt::Aggressive; break;
+  }
+
   std::auto_ptr<TargetMachine>
     target(TheTarget->createTargetMachine(TheTriple.getTriple(),
                                           MCPU, FeaturesStr,
-                                          RelocModel, CMModel));
+                                          RelocModel, CMModel, OLvl));
   assert(target.get() && "Could not allocate target machine!");
   TargetMachine &Target = *target.get();
 
@@ -332,18 +344,6 @@
     (GetOutputStream(TheTarget->getName(), TheTriple.getOS(), argv[0]));
   if (!Out) return 1;
 
-  CodeGenOpt::Level OLvl = CodeGenOpt::Default;
-  switch (OptLevel) {
-  default:
-    errs() << argv[0] << ": invalid optimization level.\n";
-    return 1;
-  case ' ': break;
-  case '0': OLvl = CodeGenOpt::None; break;
-  case '1': OLvl = CodeGenOpt::Less; break;
-  case '2': OLvl = CodeGenOpt::Default; break;
-  case '3': OLvl = CodeGenOpt::Aggressive; break;
-  }
-
   // Build up all of the passes that we want to do to the module.
   PassManager PM;
 
@@ -368,7 +368,7 @@
     formatted_raw_ostream FOS(Out->os());
 
     // Ask the target to add backend passes as necessary.
-    if (Target.addPassesToEmitFile(PM, FOS, FileType, OLvl, NoVerify)) {
+    if (Target.addPassesToEmitFile(PM, FOS, FileType, NoVerify)) {
       errs() << argv[0] << ": target does not support generation of this"
              << " file type!\n";
       return 1;



From evan.cheng at apple.com  Wed Nov 16 02:39:32 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 16 Nov 2011 08:39:32 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r144790 -
	/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Message-ID: <20111116083933.067811BE001@llvm.org>

Author: evancheng
Date: Wed Nov 16 02:39:32 2011
New Revision: 144790

URL: http://llvm.org/viewvc/llvm-project?rev=144790&view=rev
Log:
Match LLVM API change.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=144790&r1=144789&r2=144790&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Nov 16 02:39:32 2011
@@ -413,6 +413,14 @@
   
   Reloc::Model RelocModel = Reloc::Default;
   CodeModel::Model CMModel = CodeModel::Default;
+  CodeGenOpt::Level OptLevel = CodeGenOpt::Default;  // -O2, -Os, and -Oz
+  if (optimize == 0)
+    OptLevel = CodeGenOpt::None;
+  else if (optimize == 1)
+    OptLevel = CodeGenOpt::Less;
+  else if (optimize == 3)
+    // -O3 and above.
+    OptLevel = CodeGenOpt::Aggressive;
 
   // Initialize LLVM options.
   std::vector<const char*> Args;
@@ -563,7 +571,7 @@
   FeatureStr = Features.getString();
 
   TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr,
-                                       RelocModel, CMModel);
+                                       RelocModel, CMModel, OptLevel);
   TheTarget->setMCUseLoc(false);
   TheTarget->setMCUseCFI(false);
   assert(TheTarget->getTargetData()->isBigEndian() == BYTES_BIG_ENDIAN);
@@ -767,7 +775,7 @@
     // Note, this also adds codegenerator level optimization passes.
     if (TheTarget->addPassesToEmitFile(*PM, *AsmOutRawStream,
                                        TargetMachine::CGFT_AssemblyFile,
-                                       OptLevel, DisableVerify)) {
+                                       DisableVerify)) {
       errs() << "Error interfacing to target machine!\n";
       exit(1);
     }
@@ -880,7 +888,7 @@
       // Note, this also adds codegenerator level optimization passes.
       if (TheTarget->addPassesToEmitFile(*PM, *AsmOutRawStream,
                                          TargetMachine::CGFT_AssemblyFile,
-                                         OptLevel, DisableVerify)) {
+                                         DisableVerify)) {
         errs() << "Error interfacing to target machine!\n";
         exit(1);
       }



From geek4civic at gmail.com  Wed Nov 16 03:18:29 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Wed, 16 Nov 2011 09:18:29 -0000
Subject: [llvm-commits] [llvm] r144794 -
	/llvm/trunk/lib/Target/ARM/CMakeLists.txt
Message-ID: <20111116091829.15AD22A6C133@llvm.org>

Author: chapuni
Date: Wed Nov 16 03:18:28 2011
New Revision: 144794

URL: http://llvm.org/viewvc/llvm-project?rev=144794&view=rev
Log:
lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.

Modified:
    llvm/trunk/lib/Target/ARM/CMakeLists.txt

Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=144794&r1=144793&r2=144794&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Wed Nov 16 03:18:28 2011
@@ -62,8 +62,8 @@
   LLVMTarget
   )
 
-# workaround for hanging compilation on MSVC10
-if( MSVC_VERSION EQUAL 1600 )
+# workaround for hanging compilation on MSVC9, 10
+if( MSVC_VERSION EQUAL 1600 OR MSVC_VERSION EQUAL 1500 )
 set_property(
   SOURCE ARMISelLowering.cpp
   PROPERTY COMPILE_FLAGS "/Od"



From geek4civic at gmail.com  Wed Nov 16 06:12:35 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Wed, 16 Nov 2011 21:12:35 +0900
Subject: [llvm-commits] [zorg] Don't use ClangTestCommand
Message-ID: <CADiQthNc-b=1vEF65b2pgX+X_QKY82txn88vdQY0WbXfvjO0_w@mail.gmail.com>

Good evening!

http://llvm.org/bugs/show_bug.cgi?id=11317

ClangTestCommand has a problem. Shall we migrate to LitTestCommand?

When ClangTestCommand would not be used in anywhere, we could mark
PR11317 as *WONTFIX*

Thank you, ...Takumi

From bcahoon at codeaurora.org  Wed Nov 16 09:22:51 2011
From: bcahoon at codeaurora.org (Brendon Cahoon)
Date: Wed, 16 Nov 2011 09:22:51 -0600
Subject: [llvm-commits] [PATCH] Loop unrolling for run-time trip counts
In-Reply-To: <A401A377-F48E-4577-929E-2D0DE2812AA0@apple.com>
References: <01a401cc9cda$fa184580$ee48d080$@org>
	<F9878BB1-70EF-4589-B93F-FB08EB369E29@apple.com>
	<024501cc9f30$c8edb550$5ac91ff0$@org>
	<A401A377-F48E-4577-929E-2D0DE2812AA0@apple.com>
Message-ID: <008101cca473$9baf1a00$d30d4e00$@org>

Hi Andy,

 

Thanks for reviewing the loop unrolling code.  I appreciate the feedback.  I
was just finishing up the testing that was suggested previously, and was
about to submit a new patch with some minor changes.  I'll hold off and
incorporate your suggestions below and then resubmit the patch.  It
shouldn't take long.

 

I'll plan adding your suggested changes below, including:

- Add code to preserve LoopSimplify.

- Create a new .cpp file for the code.  I think that's a code idea
especially if one wants to add new strategy for unrolling loops with
run-time trip counts.  For example, using prolog/epilog loops instead of the
if-then-else sequence.

 

Thanks,

Brendon

 

--

Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

 

From: Andrew Trick [mailto:atrick at apple.com] 
Sent: Tuesday, November 15, 2011 11:59 PM
To: Brendon Cahoon
Cc: llvm-commits at cs.uiuc.edu LLVM
Subject: Re: [llvm-commits] [PATCH] Loop unrolling for run-time trip counts

 

For the purpose of code review, I'll ignore the issue of

unroll-runtime profitability, which is obviously left for later. I

will say that this is only half the framework because to achieve

data-alignment we would need to emit an epilog as well. Also, I

misread your original message, and assumed you were adding a prolog

*loop*. That would be nice for targets that care about code

size. There are cases when unrolling the main loop can be done without

increasing the size of the loop body. Your design would not always be

well suited for those cases. On the other hand, your design is a much

simpler CFG transform. We have less SSA/LoopInfo updating to worry

about this way.

 

Never mind my earlier comment about DominatorTree. I forgot we always

recompute it. You're welcome to fix that :)

 

It does seem like your transform should preserve LoopSimplify. I'm

guessing you just need a unique loop exit block--just split the

exit. Can you please do that?

 

In general, your implementation looks quite nice.

 

I am concerned that you're doubling the size of LoopUnroll.cpp for a

feature that most people won't need to look at. I'd be ok with you

creating a new .cpp file. Or at least make it blatantly obvious that

all the new code is specific to runtime-unroll. For example, you can

add function-level comments like "Support for -runtime-unroll", and

code sections like:

//===----------------------------------------------------------------------=
==//

// Implementation of -runtime-unroll.

//===----------------------------------------------------------------------=
==//

<your code>

//===----------------------------------------------------------------------=
==//

// Driver for loop unrolling transformations.

//===----------------------------------------------------------------------=
==//

...

 

Formatting: You have two 80-col violations, but otherwise looks great.

 

Typo:

+ // ... loop

+ // loop prologue

 

---

In EmitRuntimePrologueFixup:

 

+///    extraiters = tripcount % loopfactor

+///    if (extraiters == 0) jump Loop:

+///    if (extraiters == loopfactor) jump L1

+///    if (extraiters == loopfactor-1) jump L2

 

You may want to comment that you expect a later pass to convert this

to a switch.

 

Before you erase PH->terminator, maybe you should assert that it has one

successor pointing to PEnd.

 

+ std::vector<BasicBlock*> NewBlocks(LoopBlocks.size());

 

No need to initialize the vector, then immediately clear it. You can use

NewBlocks.reserve(LoopBlocks.size()).

 

+  for (unsigned i = Count-1; i > 0; --i) {

 

This is a large, complex loop. To be more self-documenting, use a

meaningful variable like "leftOverIters". Then it will be clear why

you're counting down, and the nested loop won't hide the variable.

 

+    if (i != Count-1) {

 

My personal preference, I'd like to see the i == Count-1 case first

since that's what happens first.

 

---

In CloneLoopBlocks:

 

+    LPM->cloneBasicBlockSimpleAnalysis(LoopBlocks[j], NewBB, L);

 

I'm not sure this makes sense given that the new block is in the

parent loop. It may happen to work for the only user, LICM. Since

you're not doing anything to enforce safety in the API, I would add

comments in your code, in the API declaration, and in LICM that 'L' is

the "From" block's loop, not necessarily the "To" block's loop.

 

+       if (InsertTop != 0) {

 

Why isn't InsertTop set to PH for the first copy?

 

+    // Update our running map of newest clones

+    for (ValueToValueMapTy::iterator VI = VMap.begin(), VE = VMap.end();

 

If possible, avoid copying the map. For example, call LVMap.swap(VMap)

later, after you're done with the current loop iteration, before

RemapInstrucion. You might need more explicit handling of header phis

and latch terminators, but it's probably worth it both in efficiency

and code clarity. I realize the current unroller does this, but it

think the copying wasn't removed only because it does membership

checks on LastValueMap, which you don't need.

 

In runtime-loop3.ll please use FileCheck instead of grep. We're trying

to minimize dependence on external tools in the unit tests.

 

-Andy

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From matt.pharr at gmail.com  Wed Nov 16 10:13:18 2011
From: matt.pharr at gmail.com (Matt Pharr)
Date: Wed, 16 Nov 2011 08:13:18 -0800
Subject: [llvm-commits] pr11367
In-Reply-To: <34B7AD23-CF92-4485-B2BB-ED55C9C5F628@apple.com>
References: <CAG3jReJHN2jo=Mv97jR9Ep2jywLTbMPyvF03y6Q_ffU6m0S8wA@mail.gmail.com>
	<B1289D79-A496-43C2-A644-564033AF3EF2@nondot.org>
	<AEE31309-99DD-47C3-912A-2674D658E6A7@apple.com>
	<1CF650DE-6A87-445E-8F76-A3034E121D98@gmail.com>
	<34B7AD23-CF92-4485-B2BB-ED55C9C5F628@apple.com>
Message-ID: <C7BBDAE5-5DF4-4C96-922C-9AB96ABFE133@gmail.com>

On Nov 15, 2011, at 9:45 AM, Chris Lattner wrote:
> On Nov 14, 2011, at 11:24 AM, Matt Pharr wrote:
> 
>> It's not a completely theoretical use case: the ispc compiler depended on the old behavior from LinkModules() ("link everything in the provided modules together, and don't be clever about skipping stuff that seems to not be used"), and the lazy linking change broke that.
> 
> Why?  Can you explain the use case?

The basic context is that the front-end needs to emit code for things like "do a masked store of this value to this location with this mask", where the implementation of that thing is target-dependent.  e.g. for masked store, for a target like AVX, this can be a single instruction, whereas for SSE a more complex instruction sequence is needed.

Previously, this had been implemented by linking a number of precompiled target-specific modules together at compile time, based on the selected target, before compiling the user's code.  The compiler could then emit calls to those functions as needed.

All of those functions had been defined as internal/alwaysinline, so that by the time optimization was done, they'd be inlined and the original stand-alone definitions would go away in the final compiler output.  So the LinkModules() change broke this, since it didn't bring in all of those functions during the initial module linking step.

(I realize that I could just add declarations for those functions to the module before compiling the user's program and then link in the definitions at the end and things would just work--I'm just explaining how it was implemented.)

I ended up working around the LinkModules() change by removing the internal qualifiers and then adding a pass that has a list of these functions that then changes them to be internal after they've been linked in.  This is obviously clunky.

I hope this gives some useful context.

Thanks,
-matt



From peter at pcc.me.uk  Wed Nov 16 10:29:24 2011
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Wed, 16 Nov 2011 16:29:24 +0000
Subject: [llvm-commits] pr11367
In-Reply-To: <C7BBDAE5-5DF4-4C96-922C-9AB96ABFE133@gmail.com>
References: <CAG3jReJHN2jo=Mv97jR9Ep2jywLTbMPyvF03y6Q_ffU6m0S8wA@mail.gmail.com>
	<B1289D79-A496-43C2-A644-564033AF3EF2@nondot.org>
	<AEE31309-99DD-47C3-912A-2674D658E6A7@apple.com>
	<1CF650DE-6A87-445E-8F76-A3034E121D98@gmail.com>
	<34B7AD23-CF92-4485-B2BB-ED55C9C5F628@apple.com>
	<C7BBDAE5-5DF4-4C96-922C-9AB96ABFE133@gmail.com>
Message-ID: <20111116162924.GA26776@pcc.me.uk>

On Wed, Nov 16, 2011 at 08:13:18AM -0800, Matt Pharr wrote:
> On Nov 15, 2011, at 9:45 AM, Chris Lattner wrote:
> > On Nov 14, 2011, at 11:24 AM, Matt Pharr wrote:
> > 
> >> It's not a completely theoretical use case: the ispc compiler depended on the old behavior from LinkModules() ("link everything in the provided modules together, and don't be clever about skipping stuff that seems to not be used"), and the lazy linking change broke that.
> > 
> > Why?  Can you explain the use case?
> 
> The basic context is that the front-end needs to emit code for things like "do a masked store of this value to this location with this mask", where the implementation of that thing is target-dependent.  e.g. for masked store, for a target like AVX, this can be a single instruction, whereas for SSE a more complex instruction sequence is needed.
> 
> Previously, this had been implemented by linking a number of precompiled target-specific modules together at compile time, based on the selected target, before compiling the user's code.  The compiler could then emit calls to those functions as needed.
> 
> All of those functions had been defined as internal/alwaysinline, so that by the time optimization was done, they'd be inlined and the original stand-alone definitions would go away in the final compiler output.  So the LinkModules() change broke this, since it didn't bring in all of those functions during the initial module linking step.
> 
> (I realize that I could just add declarations for those functions to the module before compiling the user's program and then link in the definitions at the end and things would just work--I'm just explaining how it was implemented.)
> 
> I ended up working around the LinkModules() change by removing the internal qualifiers and then adding a pass that has a list of these functions that then changes them to be internal after they've been linked in.  This is obviously clunky.

I faced a similar issue when developing libclc.  I decided to use
the linkonce_odr linkage for the builtin functions, since that gave
me the linkage semantics I needed (and caused the inlined builtins
to be eliminated during globaldce, or simply not added at all thanks
to the lazy linking changes) without needing to modify the linker or
use any special passes.

Thanks,
-- 
Peter

From dmalyshev at accesssoftek.com  Wed Nov 16 10:34:04 2011
From: dmalyshev at accesssoftek.com (Danil Malyshev)
Date: Wed, 16 Nov 2011 08:34:04 -0800
Subject: [llvm-commits] ExecutionEngine move Intercept.cpp
In-Reply-To: <C6F23A75-DBC1-4212-8E74-7B80A2C2664F@apple.com>
References: <6AE1604EE3EC5F4296C096518C6B77EE18123D6E02@mail.accesssoftek.com>
	<C6F23A75-DBC1-4212-8E74-7B80A2C2664F@apple.com>
Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE189CCED7A1@mail.accesssoftek.com>

?????? ????,

? ????? ????? ???? ?? ???????, ????????? ?? ?????? ? ????????.
????? RuntimeDyLd ????? ????????, ?????, ??????? ???? ?????? ????.

? ?????, ???????? ?????, ?? ??????????? ????????? ? RelocationReslover ??? ? ????????? ?????? ?? ??????????, ???????? ??????? ??????? ???? ??????????????, ? ?????? ????? ??????????, ? ?????????? ? ??? ?????.
?????? ? ???? ??? ??? ????????:
??? ? ??????, ???????? ?????? ???? ? ????? RuntimeDyLdImpl.
??? ???????? ?????????? ????? ?? ??????? ????????? ? ??????? ??????? ? ??????, ????? ?????????? ????????? ? ??? ?????? ????????? ?????????? processRelocationRef(), ?????????? ???????? ??? ????? ? ???????: RuntimeDyLdMachO ? RuntimeDyLdELF.
??? ????????? ???????? ? ??, ??????? ????? ??? ????? ????????? - ???????????, ????????? ????????????? ?? ????? ???????? ???? ????????.

? ?????, ? RuntimeDyLdMachO ? RuntimeDyLdELF ??????????? ??????? processRelocationRef() ? resolveRelocation(), ? ??? ????????? ? ??????? ??????.



??????, ?? ??????.
???????? ?????.
? ExecutionEngine ???? ??? ??????????: JIT, MCJIT ? Interpreter.
? JIT ? MCJIT ???? ??????? getPointerToNamedFunction(), ?? ?? ??? ? Interpreter, ???????, ?????? ???????? ?? ??????????? ? ExecutionEngine ?? ?????????.
?????? ? ?? ????????? ? ???????, ????? ???????? ?????? ?? ???????????? ???????, ????? ??? printf.
?????? ? ????? ???: ??????? ? RuntimeDyLd ??????? SetExecutionEngine() ? ???? ??? ?????????? ? EE ??? ??????????, ?? ??? ?????? ??????? ????????? EE->getPointerToNamedFunction().
?? ??? ?? ??? ?? ????? ?????????? getPointerToNamedFunction ? ExecutionEngine, ?? ? ???? ???? ????????? ????????:

1. ???????? ? ExecutionEngine ??????????? getPointerToNamedFunction, ???????? ? Interpreter getPointerToNamedFunction ?????? ???????????? 0 ? ?????-?????? fixme ????????????.
2. ? RuntimeDyLd ?????? SetExecutionEngine ???????????? SetMCJIT
3. ? RuntimeDyLd ?????? SetExecutionEngine ???????? ???-?? ????? SetFunctionFinder, ? ????????? ?? ???????, ? ??? ???????? RuntimeDyLd ? MCJIT-? ???????? SetFunctionFinder ????????? ????????? ?? MCJIT->getPointerToNamedFunction. ? ???? ?????? RuntimeDyLd ?????? ?? ????? ???????? ?? ? ExecutionEngine, ?? ? MCJIT, ? ???-?? ??????, ??? ????? ?? ????????????, ????? ??????? ???? ?????????? ?????? ??????? ?? ?????.

? ???? ??? ???????? ?????? ?????? ???????, ?? ???-?? ?????? ????????? ? ????????.


? ?????????,
?????


-----Original Message-----
From: Jim Grosbach [mailto:grosbach at apple.com] 
Sent: Saturday, November 12, 2011 3:14 AM
To: Danil Malyshev
Cc: 'llvm-commits at cs.uiuc.edu'
Subject: Re: [llvm-commits] ExecutionEngine move Intercept.cpp

I don't think we want to do this yet. For now, the code is similar, but this will not be the case soon. The MCJIT will almost certainly do things differently. Consider the current code on that side as a placeholder. If, once we have a real solution in place for this part of the MCJIT, there's still lots of commonality, then we can look at combining them.

-Jim

On Nov 11, 2011, at 11:55 AM, Danil Malyshev wrote:

> ping
>  
> From: Danil Malyshev 
> Sent: Friday, November 04, 2011 1:51 AM
> To: 'llvm-commits at cs.uiuc.edu'
> Subject: ExecutionEngine move Intercept.cpp
>  
> Hello everyone,
>  
>  
> Please find attached the patch for review.
> We have 2 similar implementations of getPointerToNamedFunction in MCJIT/Intercept.cpp and in JIT/Intercept.cpp.
> I have re-factored this to move it to the ExecutionEngine so both MCJIT and JIT could use a single implementation.
> Besides, ExecutionEngine looks like a right place for this method.
>  
>  
> Regards,
> Danil
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From dmalyshev at accesssoftek.com  Wed Nov 16 10:45:39 2011
From: dmalyshev at accesssoftek.com (Danil Malyshev)
Date: Wed, 16 Nov 2011 08:45:39 -0800
Subject: [llvm-commits] ExecutionEngine move Intercept.cpp
References: <6AE1604EE3EC5F4296C096518C6B77EE18123D6E02@mail.accesssoftek.com>
	<C6F23A75-DBC1-4212-8E74-7B80A2C2664F@apple.com> 
Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE189CCED7A3@mail.accesssoftek.com>

I'm sorry, I accidentally sent a previous letter to the wrong address. If there is any option to remove it from the llvm-commits, it would be great.

Thank you for understanding.

Regards,
Danil



From bob.wilson at apple.com  Wed Nov 16 11:09:59 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Wed, 16 Nov 2011 17:09:59 -0000
Subject: [llvm-commits] [llvm] r144798 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20111116170959.E063E1BE001@llvm.org>

Author: bwilson
Date: Wed Nov 16 11:09:59 2011
New Revision: 144798

URL: http://llvm.org/viewvc/llvm-project?rev=144798&view=rev
Log:
Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=144798&r1=144797&r2=144798&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 16 11:09:59 2011
@@ -4668,7 +4668,7 @@
 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
 // handled when the pseudo is expanded (which happens before any passes
 // that need the instruction size).
-let isBarrier = 1, hasSideEffects = 1 in
+let isBarrier = 1 in
 def eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
 
 //===----------------------------------------------------------------------===//



From peter_cooper at apple.com  Wed Nov 16 11:30:44 2011
From: peter_cooper at apple.com (Peter Cooper)
Date: Wed, 16 Nov 2011 09:30:44 -0800
Subject: [llvm-commits] [llvm] r144705 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp
 test/CodeGen/X86/dec-eflags-lower.ll
In-Reply-To: <E77F49AA-94E0-418F-9DED-C435D069F19A@apple.com>
References: <20111115215753.791CE2A6C131@llvm.org>
	<E77F49AA-94E0-418F-9DED-C435D069F19A@apple.com>
Message-ID: <5220EB07-AA8C-4DDC-A9FA-EAD5DE1E20A4@apple.com>

Hi Evan

Thanks for the comments.  I'll add the changes you requested.

Pete

On Nov 15, 2011, at 9:42 PM, Evan Cheng wrote:

> Hi Pete,
> 
> Comments below.
> 
> On Nov 15, 2011, at 1:57 PM, Pete Cooper wrote:
> 
>> Author: pete
>> Date: Tue Nov 15 15:57:53 2011
>> New Revision: 144705
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=144705&view=rev
>> Log:
>> Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
>> by later instructions.
>> 
>> Only done for DEC64m right now.
>> 
>> Fixes <rdar://problem/6172640>
>> 
>> Added:
>>   llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll
>> Modified:
>>   llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>   llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>>   llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> 
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=144705&r1=144704&r2=144705&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Nov 15 15:57:53 2011
>> @@ -948,6 +948,11 @@
>>    if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
>>      return NULL;
>> 
>> +    // unfolding an x86 DEC64m operation results in store, dec, load which
>> +    // can't be handled here so quit
>> +    if (NewNodes.size() == 3)
>> +      return NULL;
> 
> I don't think this is the right way. Can't you detect it's folding both a load and a store before doing a bunch of work?
> 
> 
>> +
>>    DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n");
>>    assert(NewNodes.size() == 2 && "Expected a load folding node!");
>> 
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=144705&r1=144704&r2=144705&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Nov 15 15:57:53 2011
>> @@ -2216,6 +2216,63 @@
>>    }
>>    break;
>>  }
>> +  case ISD::STORE: {
> 
> Please add comments to show why we need c++ code to isel this. Preferably with a example of what the isel pattern *should* look like when we get around to adding the tablegen syntax.
> 
> Thanks,
> 
> Evan
> 
>> +    StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
>> +    SDValue Chain = StoreNode->getOperand(0);
>> +    SDValue StoredVal = StoreNode->getOperand(1);
>> +    SDValue Address = StoreNode->getOperand(2);
>> +    SDValue Undef = StoreNode->getOperand(3);
>> +
>> +    if (StoreNode->getMemOperand()->getSize() != 8 ||
>> +        Undef->getOpcode() != ISD::UNDEF ||
>> +        Chain->getOpcode() != ISD::LOAD ||
>> +        StoredVal->getOpcode() != X86ISD::DEC ||
>> +        StoredVal.getResNo() != 0 ||
>> +        StoredVal->getOperand(0).getNode() != Chain.getNode())
>> +      break;
>> +
>> +    //OPC_CheckPredicate, 1, // Predicate_nontemporalstore
>> +    if (StoreNode->isNonTemporal())
>> +      break;
>> +
>> +    LoadSDNode *LoadNode = cast<LoadSDNode>(Chain.getNode());
>> +    if (LoadNode->getOperand(1) != Address ||
>> +        LoadNode->getOperand(2) != Undef)
>> +      break;
>> +
>> +    if (!ISD::isNormalLoad(LoadNode))
>> +      break;
>> +
>> +    if (!ISD::isNormalStore(StoreNode))
>> +      break;
>> +
>> +    // check load chain has only one use (from the store)
>> +    if (!Chain.hasOneUse())
>> +      break;
>> +
>> +    // Merge the input chains if they are not intra-pattern references.
>> +    SDValue InputChain = LoadNode->getOperand(0);
>> +
>> +    SDValue Base, Scale, Index, Disp, Segment;
>> +    if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
>> +                    Base, Scale, Index, Disp, Segment))
>> +      break;
>> +
>> +    MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
>> +    MemOp[0] = StoreNode->getMemOperand();
>> +    MemOp[1] = LoadNode->getMemOperand();
>> +    const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
>> +    MachineSDNode *Result = CurDAG->getMachineNode(X86::DEC64m,
>> +                                                   Node->getDebugLoc(),
>> +                                                   MVT::i32, MVT::Other, Ops,
>> +                                                   array_lengthof(Ops));
>> +    Result->setMemRefs(MemOp, MemOp + 2);
>> +
>> +    ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
>> +    ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
>> +
>> +    return Result;
>> +  }
>>  }
>> 
>>  SDNode *ResNode = SelectCode(Node);
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144705&r1=144704&r2=144705&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Nov 15 15:57:53 2011
>> @@ -8263,8 +8263,10 @@
>>    // climbing the DAG back to the root, and it doesn't seem to be worth the
>>    // effort.
>>    for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
>> -           UE = Op.getNode()->use_end(); UI != UE; ++UI)
>> -      if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
>> +         UE = Op.getNode()->use_end(); UI != UE; ++UI)
>> +      if (UI->getOpcode() != ISD::CopyToReg &&
>> +          UI->getOpcode() != ISD::SETCC &&
>> +          UI->getOpcode() != ISD::STORE)
>>        goto default_case;
>> 
>>    if (ConstantSDNode *C =
>> 
>> Added: llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll?rev=144705&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll (added)
>> +++ llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll Tue Nov 15 15:57:53 2011
>> @@ -0,0 +1,29 @@
>> +; RUN: llc < %s -march=x86-64 | FileCheck %s
>> +
>> +%struct.obj = type { i64 }
>> +
>> +define void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
>> +entry:
>> +; CHECK: decq	(%rdi)
>> +; CHECK-NEXT: je
>> +  %refcnt = getelementptr inbounds %struct.obj* %o, i64 0, i32 0
>> +  %0 = load i64* %refcnt, align 8, !tbaa !0
>> +  %dec = add i64 %0, -1
>> +  store i64 %dec, i64* %refcnt, align 8, !tbaa !0
>> +  %tobool = icmp eq i64 %dec, 0
>> +  br i1 %tobool, label %if.end, label %return
>> +
>> +if.end:                                           ; preds = %entry
>> +  %1 = bitcast %struct.obj* %o to i8*
>> +  tail call void @free(i8* %1)
>> +  br label %return
>> +
>> +return:                                           ; preds = %entry, %if.end
>> +  ret void
>> +}
>> +
>> +declare void @free(i8* nocapture) nounwind
>> +
>> +!0 = metadata !{metadata !"long", metadata !1}
>> +!1 = metadata !{metadata !"omnipotent char", metadata !2}
>> +!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 


From dpatel at apple.com  Wed Nov 16 12:16:26 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 16 Nov 2011 10:16:26 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r144790 -
 /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
In-Reply-To: <20111116083933.067811BE001@llvm.org>
References: <20111116083933.067811BE001@llvm.org>
Message-ID: <2231B3D2-46B7-4489-B45F-1B1B211BBDA9@apple.com>

Someone will have to apply this (or similar patch) to dragon-egg also...

On Nov 16, 2011, at 12:39 AM, Evan Cheng wrote:

> Author: evancheng
> Date: Wed Nov 16 02:39:32 2011
> New Revision: 144790
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=144790&view=rev
> Log:
> Match LLVM API change.
> 
> Modified:
>    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
> 
> Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=144790&r1=144789&r2=144790&view=diff
> ==============================================================================
> --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
> +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Nov 16 02:39:32 2011
> @@ -413,6 +413,14 @@
> 
>   Reloc::Model RelocModel = Reloc::Default;
>   CodeModel::Model CMModel = CodeModel::Default;
> +  CodeGenOpt::Level OptLevel = CodeGenOpt::Default;  // -O2, -Os, and -Oz
> +  if (optimize == 0)
> +    OptLevel = CodeGenOpt::None;
> +  else if (optimize == 1)
> +    OptLevel = CodeGenOpt::Less;
> +  else if (optimize == 3)
> +    // -O3 and above.
> +    OptLevel = CodeGenOpt::Aggressive;
> 
>   // Initialize LLVM options.
>   std::vector<const char*> Args;
> @@ -563,7 +571,7 @@
>   FeatureStr = Features.getString();
> 
>   TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr,
> -                                       RelocModel, CMModel);
> +                                       RelocModel, CMModel, OptLevel);
>   TheTarget->setMCUseLoc(false);
>   TheTarget->setMCUseCFI(false);
>   assert(TheTarget->getTargetData()->isBigEndian() == BYTES_BIG_ENDIAN);
> @@ -767,7 +775,7 @@
>     // Note, this also adds codegenerator level optimization passes.
>     if (TheTarget->addPassesToEmitFile(*PM, *AsmOutRawStream,
>                                        TargetMachine::CGFT_AssemblyFile,
> -                                       OptLevel, DisableVerify)) {
> +                                       DisableVerify)) {
>       errs() << "Error interfacing to target machine!\n";
>       exit(1);
>     }
> @@ -880,7 +888,7 @@
>       // Note, this also adds codegenerator level optimization passes.
>       if (TheTarget->addPassesToEmitFile(*PM, *AsmOutRawStream,
>                                          TargetMachine::CGFT_AssemblyFile,
> -                                         OptLevel, DisableVerify)) {
> +                                         DisableVerify)) {
>         errs() << "Error interfacing to target machine!\n";
>         exit(1);
>       }
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From evan.cheng at apple.com  Wed Nov 16 12:32:14 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 16 Nov 2011 18:32:14 -0000
Subject: [llvm-commits] [llvm] r144804 -
	/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
Message-ID: <20111116183214.95BCF1BE002@llvm.org>

Author: evancheng
Date: Wed Nov 16 12:32:14 2011
New Revision: 144804

URL: http://llvm.org/viewvc/llvm-project?rev=144804&view=rev
Log:
Disable the assertion again. Looks like fastisel is still generating bad kill markers.

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=144804&r1=144803&r2=144804&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Wed Nov 16 12:32:14 2011
@@ -502,7 +502,8 @@
       continue;
     if (!UI.getOperand().isKill())
       return 0;
-    assert(!KillMI && "More than one local kills?");
+    if (KillMI)
+      return 0;  // -O0 kill markers cannot be trusted?
     KillMI = UseMI;
   }
 



From grosbach at apple.com  Wed Nov 16 12:31:46 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 16 Nov 2011 18:31:46 -0000
Subject: [llvm-commits] [llvm] r144803 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrInfo.td AsmParser/ARMAsmParser.cpp
Message-ID: <20111116183146.34F991BE001@llvm.org>

Author: grosbach
Date: Wed Nov 16 12:31:45 2011
New Revision: 144803

URL: http://llvm.org/viewvc/llvm-project?rev=144803&view=rev
Log:
ARM mode aliases for bitwise instructions w/ register operands.

rdar://9704684

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=144803&r1=144802&r2=144803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 16 12:31:45 2011
@@ -5015,6 +5015,18 @@
 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
                         (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
                              cc_out:$s)>;
+def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
+                        (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                             cc_out:$s)>;
+def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
+                        (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                             cc_out:$s)>;
+def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
+                        (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                             cc_out:$s)>;
+def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
+                        (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                             cc_out:$s)>;
 // shifter instructions also support a two-operand form.
 def : ARMInstAlias<"asr${s}${p} $Rm, $imm",
                    (ASRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144803&r1=144802&r2=144803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Nov 16 12:31:45 2011
@@ -4613,6 +4613,32 @@
                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   switch (Inst.getOpcode()) {
   // Handle the MOV complex aliases.
+  case ARM::ASRr:
+  case ARM::LSRr:
+  case ARM::LSLr:
+  case ARM::RORr: {
+    ARM_AM::ShiftOpc ShiftTy;
+    switch(Inst.getOpcode()) {
+    default: llvm_unreachable("unexpected opcode!");
+    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
+    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
+    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
+    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
+    }
+    // A shift by zero is a plain MOVr, not a MOVsi.
+    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
+    MCInst TmpInst;
+    TmpInst.setOpcode(ARM::MOVsr);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rd
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // Rm
+    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    TmpInst.addOperand(Inst.getOperand(4));
+    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
+    Inst = TmpInst;
+    return true;
+  }
   case ARM::ASRi:
   case ARM::LSRi:
   case ARM::LSLi:



From mcrosier at apple.com  Wed Nov 16 12:39:44 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 16 Nov 2011 18:39:44 -0000
Subject: [llvm-commits] [llvm] r144805 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20111116183944.7D3A01BE001@llvm.org>

Author: mcrosier
Date: Wed Nov 16 12:39:44 2011
New Revision: 144805

URL: http://llvm.org/viewvc/llvm-project?rev=144805&view=rev
Log:
Check to make sure we can select the instruction before trying to put the
operands into a register.  Otherwise, we may materialize dead code.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144805&r1=144804&r2=144805&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Nov 16 12:39:44 2011
@@ -1670,12 +1670,6 @@
   if (isFloat && !Subtarget->hasVFP2())
     return false;
 
-  unsigned Op1 = getRegForValue(I->getOperand(0));
-  if (Op1 == 0) return false;
-
-  unsigned Op2 = getRegForValue(I->getOperand(1));
-  if (Op2 == 0) return false;
-
   unsigned Opc;
   bool is64bit = VT == MVT::f64 || VT == MVT::i64;
   switch (ISDOpcode) {
@@ -1690,6 +1684,12 @@
       Opc = is64bit ? ARM::VMULD : ARM::VMULS;
       break;
   }
+  unsigned Op1 = getRegForValue(I->getOperand(0));
+  if (Op1 == 0) return false;
+
+  unsigned Op2 = getRegForValue(I->getOperand(1));
+  if (Op2 == 0) return false;
+
   unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                           TII.get(Opc), ResultReg)



From evan.cheng at apple.com  Wed Nov 16 12:44:48 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 16 Nov 2011 18:44:48 -0000
Subject: [llvm-commits] [llvm] r144806 - in /llvm/trunk:
 lib/CodeGen/TwoAddressInstructionPass.cpp test/CodeGen/X86/fast-isel-gep.ll
 test/CodeGen/X86/fast-isel-x86-64.ll
Message-ID: <20111116184448.666181BE001@llvm.org>

Author: evancheng
Date: Wed Nov 16 12:44:48 2011
New Revision: 144806

URL: http://llvm.org/viewvc/llvm-project?rev=144806&view=rev
Log:
Disable expensive two-address optimizations at -O0. rdar://10453055

Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll
    llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=144806&r1=144805&r2=144806&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Wed Nov 16 12:44:48 2011
@@ -68,6 +68,7 @@
     MachineRegisterInfo *MRI;
     LiveVariables *LV;
     AliasAnalysis *AA;
+    CodeGenOpt::Level OptLevel;
 
     // DistanceMap - Keep track the distance of a MI from the start of the
     // current basic block.
@@ -571,6 +572,9 @@
 TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC,
                                        MachineInstr *MI, MachineBasicBlock *MBB,
                                        unsigned Dist) {
+  if (OptLevel == CodeGenOpt::None)
+    return false;
+
   // Determine if it's profitable to commute this two address instruction. In
   // general, we want no uses between this instruction and the definition of
   // the two-address register.
@@ -1193,6 +1197,9 @@
                         MachineFunction::iterator &mbbi,
                         unsigned SrcIdx, unsigned DstIdx, unsigned Dist,
                         SmallPtrSet<MachineInstr*, 8> &Processed) {
+  if (OptLevel == CodeGenOpt::None)
+    return false;
+
   MachineInstr &MI = *mi;
   const MCInstrDesc &MCID = MI.getDesc();
   unsigned regA = MI.getOperand(DstIdx).getReg();
@@ -1388,6 +1395,7 @@
   InstrItins = TM.getInstrItineraryData();
   LV = getAnalysisIfAvailable<LiveVariables>();
   AA = &getAnalysis<AliasAnalysis>();
+  OptLevel = TM.getOptLevel();
 
   bool MadeChange = false;
 

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll?rev=144806&r1=144805&r2=144806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Wed Nov 16 12:44:48 2011
@@ -82,9 +82,8 @@
   ret i64 %v11
 ; X64: test5:
 ; X64: movslq	%e[[A1]], %rax
-; X64-NEXT: movq	(%r[[A0]],%rax), %rax
-; X64-NEXT: addq	%{{rdx|r8}}, %rax
-; X64-NEXT: ret
+; X64-NEXT: (%r[[A0]],%rax),
+; X64: ret
 }
 
 ; PR9500, rdar://9156159 - Don't do non-local address mode folding,

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll?rev=144806&r1=144805&r2=144806&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll Wed Nov 16 12:44:48 2011
@@ -82,7 +82,7 @@
   ret i64 %mul
 
 ; CHECK: test6:
-; CHECK: leaq	(,%rdi,8), %rax
+; CHECK: shlq	$3, %rdi
 }
 
 define i32 @test7(i32 %x) nounwind ssp {
@@ -90,7 +90,7 @@
   %mul = mul nsw i32 %x, 8
   ret i32 %mul
 ; CHECK: test7:
-; CHECK: leal	(,%rdi,8), %eax
+; CHECK: shll	$3, %edi
 }
 
 



From daniel at zuster.org  Wed Nov 16 12:56:53 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 18:56:53 -0000
Subject: [llvm-commits] [compiler-rt] r144809 -
	/compiler-rt/trunk/lib/ppc/multc3.c
Message-ID: <20111116185653.41F7D1BE001@llvm.org>

Author: ddunbar
Date: Wed Nov 16 12:56:53 2011
New Revision: 144809

URL: http://llvm.org/viewvc/llvm-project?rev=144809&view=rev
Log:
lib/ppc: Fix a refacto.

Modified:
    compiler-rt/trunk/lib/ppc/multc3.c

Modified: compiler-rt/trunk/lib/ppc/multc3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/ppc/multc3.c?rev=144809&r1=144808&r2=144809&view=diff
==============================================================================
--- compiler-rt/trunk/lib/ppc/multc3.c (original)
+++ compiler-rt/trunk/lib/ppc/multc3.c Wed Nov 16 12:56:53 2011
@@ -10,7 +10,7 @@
     (x).s.lo = 0.0;                                                     \
   }
 
-#define zeroNaN() { \
+#define zeroNaN(x) { \
     if (crt_isnan((x).s.hi)) {                                          \
       (x).s.hi = crt_copysign(0.0, (x).s.hi);                     \
       (x).s.lo = 0.0;                                                   \



From daniel at zuster.org  Wed Nov 16 12:56:55 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 18:56:55 -0000
Subject: [llvm-commits] [compiler-rt] r144810 -
	/compiler-rt/trunk/lib/int_math.h
Message-ID: <20111116185655.569D61BE001@llvm.org>

Author: ddunbar
Date: Wed Nov 16 12:56:55 2011
New Revision: 144810

URL: http://llvm.org/viewvc/llvm-project?rev=144810&view=rev
Log:
lib/int_math: Some versions of GCC don't provide __builtin_isfinite. Support
them.

Modified:
    compiler-rt/trunk/lib/int_math.h

Modified: compiler-rt/trunk/lib/int_math.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/int_math.h?rev=144810&r1=144809&r2=144810&view=diff
==============================================================================
--- compiler-rt/trunk/lib/int_math.h (original)
+++ compiler-rt/trunk/lib/int_math.h Wed Nov 16 12:56:55 2011
@@ -21,12 +21,29 @@
 #ifndef INT_MATH_H
 #define INT_MATH_H
 
+#ifndef __has_builtin
+#  define  __has_builtin(x) 0
+#endif
+
 #define CRT_INFINITY __builtin_huge_valf()
 
-#define crt_isfinite(x) __builtin_isfinite((x))
 #define crt_isinf(x) __builtin_isinf((x))
 #define crt_isnan(x) __builtin_isnan((x))
 
+/* Define crt_isfinite in terms of the builtin if available, otherwise provide
+ * an alternate version in terms of our other functions. This supports some
+ * versions of GCC which didn't have __builtin_isfinite.
+ */
+#if __has_builtin(__builtin_isfinite)
+#  define crt_isfinite(x) __builtin_isfinite((x))
+#else
+#  define crt_isfinite(x) \
+  __extension__(({ \
+      __typeof((x)) x_ = (x); \
+      !crt_isinf(x_) && !crt_isnan(x_); \
+    }))
+#endif
+
 #define crt_copysign(x, y) __builtin_copysign((x), (y))
 #define crt_copysignf(x, y) __builtin_copysignf((x), (y))
 #define crt_copysignl(x, y) __builtin_copysignl((x), (y))



From peter_cooper at apple.com  Wed Nov 16 13:03:24 2011
From: peter_cooper at apple.com (Pete Cooper)
Date: Wed, 16 Nov 2011 19:03:24 -0000
Subject: [llvm-commits] [llvm] r144811 -
	/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Message-ID: <20111116190324.2660C1BE001@llvm.org>

Author: pete
Date: Wed Nov 16 13:03:23 2011
New Revision: 144811

URL: http://llvm.org/viewvc/llvm-project?rev=144811&view=rev
Log:
Added missing comment about new custom lowering of DEC64

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=144811&r1=144810&r2=144811&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Nov 16 13:03:23 2011
@@ -2217,6 +2217,18 @@
     break;
   }
   case ISD::STORE: {
+    // The DEC64m tablegen pattern is currently not able to match the case where
+    // the EFLAGS on the original DEC are used.
+    // we'll need to improve tablegen to allow flags to be transferred from a
+    // node in the pattern to the result node.  probably with a new keyword
+    // for example, we have this
+    // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
+    //  [(store (add (loadi64 addr:$dst), -1), addr:$dst),
+    //   (implicit EFLAGS)]>;
+    // but maybe need something like this
+    // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
+    //  [(store (add (loadi64 addr:$dst), -1), addr:$dst),
+    //   (transferrable EFLAGS)]>;
     StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
     SDValue Chain = StoreNode->getOperand(0);
     SDValue StoredVal = StoreNode->getOperand(1);



From grosbach at apple.com  Wed Nov 16 13:05:59 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 16 Nov 2011 19:05:59 -0000
Subject: [llvm-commits] [llvm] r144812 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrInfo.td AsmParser/ARMAsmParser.cpp
Message-ID: <20111116190559.ED5931BE001@llvm.org>

Author: grosbach
Date: Wed Nov 16 13:05:59 2011
New Revision: 144812

URL: http://llvm.org/viewvc/llvm-project?rev=144812&view=rev
Log:
ARM assembly parsing for RRX mnemonic.

rdar://9704684

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=144812&r1=144811&r2=144812&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 16 13:05:59 2011
@@ -5015,6 +5015,8 @@
 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
                         (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
                              cc_out:$s)>;
+def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
+                        (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
                         (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
                              cc_out:$s)>;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144812&r1=144811&r2=144812&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Nov 16 13:05:59 2011
@@ -4644,7 +4644,6 @@
   case ARM::LSLi:
   case ARM::RORi: {
     ARM_AM::ShiftOpc ShiftTy;
-    unsigned Amt = Inst.getOperand(2).getImm();
     switch(Inst.getOpcode()) {
     default: llvm_unreachable("unexpected opcode!");
     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
@@ -4653,6 +4652,7 @@
     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
     }
     // A shift by zero is a plain MOVr, not a MOVsi.
+    unsigned Amt = Inst.getOperand(2).getImm();
     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
     MCInst TmpInst;
@@ -4667,6 +4667,19 @@
     Inst = TmpInst;
     return true;
   }
+  case ARM::RRXi: {
+    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
+    MCInst TmpInst;
+    TmpInst.setOpcode(ARM::MOVsi);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rd
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
+    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
+    TmpInst.addOperand(Inst.getOperand(3));
+    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
+    Inst = TmpInst;
+    return true;
+  }
   case ARM::t2LDMIA_UPD: {
     // If this is a load of a single register, then we should use
     // a post-indexed LDR instruction instead, per the ARM ARM.



From grosbach at apple.com  Wed Nov 16 13:12:24 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 16 Nov 2011 19:12:24 -0000
Subject: [llvm-commits] [llvm] r144814 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20111116191224.57A3C1BE001@llvm.org>

Author: grosbach
Date: Wed Nov 16 13:12:24 2011
New Revision: 144814

URL: http://llvm.org/viewvc/llvm-project?rev=144814&view=rev
Log:
ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=144814&r1=144813&r2=144814&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 16 13:12:24 2011
@@ -5038,6 +5038,18 @@
                    (LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
 def : ARMInstAlias<"ror${s}${p} $Rm, $imm",
                    (RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
+def : ARMInstAlias<"asr${s}${p} $Rn, $Rm",
+                   (ASRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                         cc_out:$s)>;
+def : ARMInstAlias<"lsr${s}${p} $Rn, $Rm",
+                   (LSRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                         cc_out:$s)>;
+def : ARMInstAlias<"lsl${s}${p} $Rn, $Rm",
+                   (LSLr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                         cc_out:$s)>;
+def : ARMInstAlias<"ror${s}${p} $Rn, $Rm",
+                   (RORr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                         cc_out:$s)>;
 
 
 // 'mul' instruction can be specified with only two operands.



From chandlerc at gmail.com  Wed Nov 16 13:52:13 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Wed, 16 Nov 2011 19:52:13 -0000
Subject: [llvm-commits] [llvm] r144818 - in /llvm/trunk/docs: CMake.html
 GettingStarted.html GettingStartedVS.html
Message-ID: <20111116195213.B60E71BE001@llvm.org>

Author: chandlerc
Date: Wed Nov 16 13:52:13 2011
New Revision: 144818

URL: http://llvm.org/viewvc/llvm-project?rev=144818&view=rev
Log:
There are already problems with building LLVM under VS2005, and it's
quite old now. Update the documentation to reflect this, and direct
people to use VS2008 or newer.

Modified:
    llvm/trunk/docs/CMake.html
    llvm/trunk/docs/GettingStarted.html
    llvm/trunk/docs/GettingStartedVS.html

Modified: llvm/trunk/docs/CMake.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CMake.html?rev=144818&r1=144817&r2=144818&view=diff
==============================================================================
--- llvm/trunk/docs/CMake.html (original)
+++ llvm/trunk/docs/CMake.html Wed Nov 16 13:52:13 2011
@@ -145,7 +145,7 @@
       text. Generator's names are case-sensitive. Example:</p>
 
     <div class="doc_code">
-      <p><tt>cmake -G "Visual Studio 8 2005" path/to/llvm/source/root</tt></p>
+      <p><tt>cmake -G "Visual Studio 9 2008" path/to/llvm/source/root</tt></p>
     </div>
 
     <p>For a given development platform there can be more than one

Modified: llvm/trunk/docs/GettingStarted.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=144818&r1=144817&r2=144818&view=diff
==============================================================================
--- llvm/trunk/docs/GettingStarted.html (original)
+++ llvm/trunk/docs/GettingStarted.html Wed Nov 16 13:52:13 2011
@@ -283,7 +283,7 @@
 <tr>
   <td>Windows</td>
   <td>x86<sup><a href="#pf_1">1</a></sup></td>
-  <td>Visual Studio 2005 SP1 or higher<sup><a href="#pf_4">4</a>,<a href="#pf_5">5</a></sup></td>
+  <td>Visual Studio 2008 or higher<sup><a href="#pf_4">4</a>,<a href="#pf_5">5</a></sup></td>
 <tr>
   <td>AIX<sup><a href="#pf_3">3</a>,<a href="#pf_4">4</a></sup></td>
   <td>PowerPC</td>

Modified: llvm/trunk/docs/GettingStartedVS.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStartedVS.html?rev=144818&r1=144817&r2=144818&view=diff
==============================================================================
--- llvm/trunk/docs/GettingStartedVS.html (original)
+++ llvm/trunk/docs/GettingStartedVS.html Wed Nov 16 13:52:13 2011
@@ -88,8 +88,8 @@
 
 <div>
 
-  <p>Any system that can adequately run Visual Studio .NET 2005 SP1 is fine.
-  The LLVM source tree and object files, libraries and executables will consume
+  <p>Any system that can adequately run Visual Studio 2008 is fine. The LLVM
+  source tree and object files, libraries and executables will consume
   approximately 3GB.</p>
 
 </div>
@@ -98,10 +98,9 @@
 <h3><a name="software"><b>Software</b></a></h3>
 <div>
 
-  <p>You will need Visual Studio .NET 2005 SP1 or higher.  The VS2005 SP1
-  beta and the normal VS2005 still have bugs that are not completely
-  compatible.  Earlier versions of Visual Studio do not support the C++ standard
-  well enough and will not work.</p>
+  <p>You will need Visual Studio 2008 or higher.  Earlier versions of Visual
+  Studio have bugs, are not completely compatible, or do not support the C++
+  standard well enough.</p>
 
   <p>You will also need the <a href="http://www.cmake.org/">CMake</a> build
   system since it generates the project files you will use to build with.</p>



From evan.cheng at apple.com  Wed Nov 16 14:48:56 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 16 Nov 2011 12:48:56 -0800
Subject: [llvm-commits] [llvm] r144705 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp
 test/CodeGen/X86/dec-eflags-lower.ll
In-Reply-To: <5220EB07-AA8C-4DDC-A9FA-EAD5DE1E20A4@apple.com>
References: <20111115215753.791CE2A6C131@llvm.org>
	<E77F49AA-94E0-418F-9DED-C435D069F19A@apple.com>
	<5220EB07-AA8C-4DDC-A9FA-EAD5DE1E20A4@apple.com>
Message-ID: <22AB1DB0-0A73-42CA-A19D-7F0FD7778103@apple.com>

Thanks. I think you can use getOpcodeAfterMemoryUnfold() to test if the instruction is folding both a load and a store.

Evan

On Nov 16, 2011, at 9:30 AM, Peter Cooper wrote:

> Hi Evan
> 
> Thanks for the comments.  I'll add the changes you requested.
> 
> Pete
> 
> On Nov 15, 2011, at 9:42 PM, Evan Cheng wrote:
> 
>> Hi Pete,
>> 
>> Comments below.
>> 
>> On Nov 15, 2011, at 1:57 PM, Pete Cooper wrote:
>> 
>>> Author: pete
>>> Date: Tue Nov 15 15:57:53 2011
>>> New Revision: 144705
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=144705&view=rev
>>> Log:
>>> Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
>>> by later instructions.
>>> 
>>> Only done for DEC64m right now.
>>> 
>>> Fixes <rdar://problem/6172640>
>>> 
>>> Added:
>>>  llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll
>>> Modified:
>>>  llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>>  llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>>>  llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>> 
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=144705&r1=144704&r2=144705&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Nov 15 15:57:53 2011
>>> @@ -948,6 +948,11 @@
>>>   if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
>>>     return NULL;
>>> 
>>> +    // unfolding an x86 DEC64m operation results in store, dec, load which
>>> +    // can't be handled here so quit
>>> +    if (NewNodes.size() == 3)
>>> +      return NULL;
>> 
>> I don't think this is the right way. Can't you detect it's folding both a load and a store before doing a bunch of work?
>> 
>> 
>>> +
>>>   DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n");
>>>   assert(NewNodes.size() == 2 && "Expected a load folding node!");
>>> 
>>> 
>>> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=144705&r1=144704&r2=144705&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
>>> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Nov 15 15:57:53 2011
>>> @@ -2216,6 +2216,63 @@
>>>   }
>>>   break;
>>> }
>>> +  case ISD::STORE: {
>> 
>> Please add comments to show why we need c++ code to isel this. Preferably with a example of what the isel pattern *should* look like when we get around to adding the tablegen syntax.
>> 
>> Thanks,
>> 
>> Evan
>> 
>>> +    StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
>>> +    SDValue Chain = StoreNode->getOperand(0);
>>> +    SDValue StoredVal = StoreNode->getOperand(1);
>>> +    SDValue Address = StoreNode->getOperand(2);
>>> +    SDValue Undef = StoreNode->getOperand(3);
>>> +
>>> +    if (StoreNode->getMemOperand()->getSize() != 8 ||
>>> +        Undef->getOpcode() != ISD::UNDEF ||
>>> +        Chain->getOpcode() != ISD::LOAD ||
>>> +        StoredVal->getOpcode() != X86ISD::DEC ||
>>> +        StoredVal.getResNo() != 0 ||
>>> +        StoredVal->getOperand(0).getNode() != Chain.getNode())
>>> +      break;
>>> +
>>> +    //OPC_CheckPredicate, 1, // Predicate_nontemporalstore
>>> +    if (StoreNode->isNonTemporal())
>>> +      break;
>>> +
>>> +    LoadSDNode *LoadNode = cast<LoadSDNode>(Chain.getNode());
>>> +    if (LoadNode->getOperand(1) != Address ||
>>> +        LoadNode->getOperand(2) != Undef)
>>> +      break;
>>> +
>>> +    if (!ISD::isNormalLoad(LoadNode))
>>> +      break;
>>> +
>>> +    if (!ISD::isNormalStore(StoreNode))
>>> +      break;
>>> +
>>> +    // check load chain has only one use (from the store)
>>> +    if (!Chain.hasOneUse())
>>> +      break;
>>> +
>>> +    // Merge the input chains if they are not intra-pattern references.
>>> +    SDValue InputChain = LoadNode->getOperand(0);
>>> +
>>> +    SDValue Base, Scale, Index, Disp, Segment;
>>> +    if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
>>> +                    Base, Scale, Index, Disp, Segment))
>>> +      break;
>>> +
>>> +    MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
>>> +    MemOp[0] = StoreNode->getMemOperand();
>>> +    MemOp[1] = LoadNode->getMemOperand();
>>> +    const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
>>> +    MachineSDNode *Result = CurDAG->getMachineNode(X86::DEC64m,
>>> +                                                   Node->getDebugLoc(),
>>> +                                                   MVT::i32, MVT::Other, Ops,
>>> +                                                   array_lengthof(Ops));
>>> +    Result->setMemRefs(MemOp, MemOp + 2);
>>> +
>>> +    ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
>>> +    ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
>>> +
>>> +    return Result;
>>> +  }
>>> }
>>> 
>>> SDNode *ResNode = SelectCode(Node);
>>> 
>>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144705&r1=144704&r2=144705&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Nov 15 15:57:53 2011
>>> @@ -8263,8 +8263,10 @@
>>>   // climbing the DAG back to the root, and it doesn't seem to be worth the
>>>   // effort.
>>>   for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
>>> -           UE = Op.getNode()->use_end(); UI != UE; ++UI)
>>> -      if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
>>> +         UE = Op.getNode()->use_end(); UI != UE; ++UI)
>>> +      if (UI->getOpcode() != ISD::CopyToReg &&
>>> +          UI->getOpcode() != ISD::SETCC &&
>>> +          UI->getOpcode() != ISD::STORE)
>>>       goto default_case;
>>> 
>>>   if (ConstantSDNode *C =
>>> 
>>> Added: llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll?rev=144705&view=auto
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll (added)
>>> +++ llvm/trunk/test/CodeGen/X86/dec-eflags-lower.ll Tue Nov 15 15:57:53 2011
>>> @@ -0,0 +1,29 @@
>>> +; RUN: llc < %s -march=x86-64 | FileCheck %s
>>> +
>>> +%struct.obj = type { i64 }
>>> +
>>> +define void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
>>> +entry:
>>> +; CHECK: decq	(%rdi)
>>> +; CHECK-NEXT: je
>>> +  %refcnt = getelementptr inbounds %struct.obj* %o, i64 0, i32 0
>>> +  %0 = load i64* %refcnt, align 8, !tbaa !0
>>> +  %dec = add i64 %0, -1
>>> +  store i64 %dec, i64* %refcnt, align 8, !tbaa !0
>>> +  %tobool = icmp eq i64 %dec, 0
>>> +  br i1 %tobool, label %if.end, label %return
>>> +
>>> +if.end:                                           ; preds = %entry
>>> +  %1 = bitcast %struct.obj* %o to i8*
>>> +  tail call void @free(i8* %1)
>>> +  br label %return
>>> +
>>> +return:                                           ; preds = %entry, %if.end
>>> +  ret void
>>> +}
>>> +
>>> +declare void @free(i8* nocapture) nounwind
>>> +
>>> +!0 = metadata !{metadata !"long", metadata !1}
>>> +!1 = metadata !{metadata !"omnipotent char", metadata !2}
>>> +!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
> 


From mcrosier at apple.com  Wed Nov 16 15:02:08 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 16 Nov 2011 21:02:08 -0000
Subject: [llvm-commits] [llvm] r144832 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <20111116210208.6DEEE1BE001@llvm.org>

Author: mcrosier
Date: Wed Nov 16 15:02:08 2011
New Revision: 144832

URL: http://llvm.org/viewvc/llvm-project?rev=144832&view=rev
Log:
Fix the stats collection for fast-isel.  The failed count was only accounting
for a single miss and not all predecessor instructions that get selected by
the selection DAG instruction selector.  This is still not exact (e.g., over
states misses when folded/dead instructions are present), but it is a step in
the right direction.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=144832&r1=144831&r2=144832&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Nov 16 15:02:08 2011
@@ -892,13 +892,16 @@
           FastIS->setLastLocalValue(0);
       }
 
+      unsigned NumFastIselRemaining = std::distance(Begin, End);
       // Do FastISel on as many instructions as possible.
       for (; BI != Begin; --BI) {
         const Instruction *Inst = llvm::prior(BI);
 
         // If we no longer require this instruction, skip it.
-        if (isFoldedOrDeadInstruction(Inst, FuncInfo))
+        if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
+          --NumFastIselRemaining;
           continue;
+        }
 
         // Bottom-up: reset the insert pos at the top, after any local-value
         // instructions.
@@ -906,6 +909,7 @@
 
         // Try to select the instruction with FastISel.
         if (FastIS->SelectInstruction(Inst)) {
+          --NumFastIselRemaining;
           ++NumFastIselSuccess;
           // If fast isel succeeded, skip over all the folded instructions, and
           // then see if there is a load right before the selected instructions.
@@ -918,15 +922,18 @@
           }
           if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
               BeforeInst->hasOneUse() &&
-              TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS))
+              TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
             // If we succeeded, don't re-select the load.
             BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
+            --NumFastIselRemaining;
+            ++NumFastIselSuccess;
+          }
           continue;
         }
 
         // Then handle certain instructions as single-LLVM-Instruction blocks.
         if (isa<CallInst>(Inst)) {
-          ++NumFastIselFailures;
+
           if (EnableFastISelVerbose || EnableFastISelAbort) {
             dbgs() << "FastISel missed call: ";
             Inst->dump();
@@ -941,24 +948,30 @@
           bool HadTailCall = false;
           SelectBasicBlock(Inst, BI, HadTailCall);
 
+          // Recompute NumFastIselRemaining as Selection DAG instruction
+          // selection may have handled the call, input args, etc.
+          unsigned RemainingNow = std::distance(Begin, BI);
+          NumFastIselFailures += NumFastIselRemaining - RemainingNow;
+
           // If the call was emitted as a tail call, we're done with the block.
           if (HadTailCall) {
             --BI;
             break;
           }
 
+          NumFastIselRemaining = RemainingNow;
           continue;
         }
 
         if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
           // Don't abort, and use a different message for terminator misses.
-          ++NumFastIselFailures;
+          NumFastIselFailures += NumFastIselRemaining;
           if (EnableFastISelVerbose || EnableFastISelAbort) {
             dbgs() << "FastISel missed terminator: ";
             Inst->dump();
           }
         } else {
-          ++NumFastIselFailures;
+          NumFastIselFailures += NumFastIselRemaining;
           if (EnableFastISelVerbose || EnableFastISelAbort) {
             dbgs() << "FastISel miss: ";
             Inst->dump();



From mcrosier at apple.com  Wed Nov 16 15:05:28 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 16 Nov 2011 21:05:28 -0000
Subject: [llvm-commits] [llvm] r144833 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
Message-ID: <20111116210528.F3BF21BE001@llvm.org>

Author: mcrosier
Date: Wed Nov 16 15:05:28 2011
New Revision: 144833

URL: http://llvm.org/viewvc/llvm-project?rev=144833&view=rev
Log:
Add fast-isel stats to determine who's doing all the work, the 
target-independent selector or the target-specific selector.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=144833&r1=144832&r2=144833&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Nov 16 15:05:28 2011
@@ -39,6 +39,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#define DEBUG_TYPE "isel"
 #include "llvm/Function.h"
 #include "llvm/GlobalVariable.h"
 #include "llvm/Instructions.h"
@@ -58,8 +59,12 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/ADT/Statistic.h"
 using namespace llvm;
 
+STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by target-independent selector");
+STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by target-specific selector");
+
 /// startNewBlock - Set the current block to which generated machine
 /// instructions will be appended, and clear the local CSE map.
 ///
@@ -765,12 +770,14 @@
 
   // First, try doing target-independent selection.
   if (SelectOperator(I, I->getOpcode())) {
+    ++NumFastIselSuccessIndependent;
     DL = DebugLoc();
     return true;
   }
 
   // Next, try calling the target to attempt to handle the instruction.
   if (TargetSelectInstruction(I)) {
+    ++NumFastIselSuccessTarget;
     DL = DebugLoc();
     return true;
   }



From krasin at chromium.org  Wed Nov 16 15:44:38 2011
From: krasin at chromium.org (Ivan Krasin)
Date: Wed, 16 Nov 2011 13:44:38 -0800
Subject: [llvm-commits] arm mc: fix relocation of an alias to an alias
In-Reply-To: <4E9F0948.9060808@gmail.com>
References: <CAOei5RcgpmebdoG-=msLNtH7ezDxcpJtEXywTSVxwThiknroDA@mail.gmail.com>
	<8AE16CFC-D9D4-431B-9716-C8493971AEF0@apple.com>
	<CAOei5RdiS-ZC11e+sQhtZavhAjTOTJg7TMXY+3sjnA3v-e0JBw@mail.gmail.com>
	<CADbEz-jynVkn26S7CHvLYrRSj+qup-fb=q0KXcBTC_U1dBWkkw@mail.gmail.com>
	<CAOei5ReBeh2NCwFL1gup8OEmDNODb8W04owatrCWjcBoMxjO+A@mail.gmail.com>
	<CA+Ov9+mBQ9hm2imKFg3PBP-B9LO8MpXkNvBs+s=Ju9PM=tPuXA@mail.gmail.com>
	<4E9F0948.9060808@gmail.com>
Message-ID: <CAOei5Rd1adR_iJ5rqZdA=T7k4HSG3OFnwXw9Mi6UV6Y=FCrm7A@mail.gmail.com>

Hm...
I have not touched this issue for a while (because I had other tasks), but
now it seems that it's fixed independently. The attached patch adds the
test to avoid regression. It passes with llvm tip-of-tree.
OK to commit?

krasin

On Wed, Oct 19, 2011 at 10:30 AM, Rafael ?vila de Esp?ndola <
rafael.espindola at gmail.com> wrote:

> > But you cannot! If alias is weak it can be overridden.
> >
>
> we have some tests for it in test/MC/ELF, but they are run only for i386
> or x86_64 at the moment. Having the equivalent ones for ARM would
> probably help (as would factoring the code to share more logic between
> ARM and X86).
>
> Cheers,
> Rafael
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From grosbach at apple.com  Wed Nov 16 15:46:51 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 16 Nov 2011 21:46:51 -0000
Subject: [llvm-commits] [llvm] r144836 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20111116214651.3031A1BE001@llvm.org>

Author: grosbach
Date: Wed Nov 16 15:46:50 2011
New Revision: 144836

URL: http://llvm.org/viewvc/llvm-project?rev=144836&view=rev
Log:
Clean up debug printing of ARM shifted operands.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144836&r1=144835&r2=144836&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Nov 16 15:46:50 2011
@@ -1946,18 +1946,15 @@
     break;
   case k_ShiftedRegister:
     OS << "<so_reg_reg "
-       << RegShiftedReg.SrcReg
-       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
-       << ", " << RegShiftedReg.ShiftReg << ", "
-       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
-       << ">";
+       << RegShiftedReg.SrcReg << " "
+       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
+       << " " << RegShiftedReg.ShiftReg << ">";
     break;
   case k_ShiftedImmediate:
     OS << "<so_reg_imm "
-       << RegShiftedImm.SrcReg
-       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
-       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
-       << ">";
+       << RegShiftedImm.SrcReg << " "
+       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
+       << " #" << RegShiftedImm.ShiftImm << ">";
     break;
   case k_RotateImmediate:
     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";



From grosbach at apple.com  Wed Nov 16 15:50:05 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 16 Nov 2011 21:50:05 -0000
Subject: [llvm-commits] [llvm] r144837 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20111116215005.C5D4F1BE001@llvm.org>

Author: grosbach
Date: Wed Nov 16 15:50:05 2011
New Revision: 144837

URL: http://llvm.org/viewvc/llvm-project?rev=144837&view=rev
Log:
ARM assembly parsing for shifted register operands for MOV instruction.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=144837&r1=144836&r2=144837&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 16 15:50:05 2011
@@ -470,6 +470,7 @@
   let EncoderMethod = "getSORegRegOpValue";
   let PrintMethod = "printSORegRegOperand";
   let DecoderMethod = "DecodeSORegRegOperand";
+  let ParserMatchClass = ShiftedRegAsmOperand;
   let MIOperandInfo = (ops GPR, GPR, i32imm);
 }
 
@@ -480,6 +481,7 @@
   let EncoderMethod = "getSORegImmOpValue";
   let PrintMethod = "printSORegImmOperand";
   let DecoderMethod = "DecodeSORegImmOperand";
+  let ParserMatchClass = ShiftedImmAsmOperand;
   let MIOperandInfo = (ops GPR, i32imm);
 }
 



From evan.cheng at apple.com  Wed Nov 16 16:24:44 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 16 Nov 2011 22:24:44 -0000
Subject: [llvm-commits] [llvm] r144839 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_shuffle-39.ll
Message-ID: <20111116222444.878FC1BE001@llvm.org>

Author: evancheng
Date: Wed Nov 16 16:24:44 2011
New Revision: 144839

URL: http://llvm.org/viewvc/llvm-project?rev=144839&view=rev
Log:
Another missing X86ISD::MOVLPD pattern. rdar://10450317

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144839&r1=144838&r2=144839&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Nov 16 16:24:44 2011
@@ -522,6 +522,8 @@
   // fold opportunity reappears.
   def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
             (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
+  def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
+            (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
   def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
             (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
   def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll?rev=144839&r1=144838&r2=144839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-39.ll Wed Nov 16 16:24:44 2011
@@ -67,3 +67,20 @@
   %tmp7 = shufflevector <2 x double> %tmp5, <2 x double> %tmp6, <2 x i32> <i32 2, i32 1>
   ret <2 x double> %tmp7
 }
+
+; rdar://10450317
+define <2 x i64> @t4() nounwind readonly {
+bb:
+; CHECK: t4:
+; CHECK: punpcklqdq %xmm0, %xmm1
+; CHECK: movq (%rax), %xmm0
+; CHECK: movsd %xmm1, %xmm0
+  %tmp0 = load i128* null, align 1
+  %tmp1 = load <2 x i32>* undef, align 8
+  %tmp2 = bitcast i128 %tmp0 to <16 x i8>
+  %tmp3 = bitcast <2 x i32> %tmp1 to i64
+  %tmp4 = insertelement <2 x i64> undef, i64 %tmp3, i32 0
+  %tmp5 = bitcast <16 x i8> %tmp2 to <2 x i64>
+  %tmp6 = shufflevector <2 x i64> %tmp4, <2 x i64> %tmp5, <2 x i32> <i32 2, i32 1>
+  ret <2 x i64> %tmp6
+}



From ahatanaka at mips.com  Wed Nov 16 16:36:01 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 16 Nov 2011 22:36:01 -0000
Subject: [llvm-commits] [llvm] r144840 - in /llvm/trunk/lib/Target/Mips:
 Mips64InstrInfo.td MipsInstrInfo.td
Message-ID: <20111116223601.66D5B1BE001@llvm.org>

Author: ahatanak
Date: Wed Nov 16 16:36:01 2011
New Revision: 144840

URL: http://llvm.org/viewvc/llvm-project?rev=144840&view=rev
Log:
64-bit jump register instruction.

Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=144840&r1=144839&r2=144840&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Nov 16 16:36:01 2011
@@ -175,6 +175,7 @@
 def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]>;
 
 /// Jump and Branch Instructions
+def JR64   : JumpFR<0x00, 0x08, "jr", CPU64Regs>;
 def JAL64  : JumpLink64<0x03, "jal">;
 def JALR64 : JumpLinkReg64<0x00, 0x09, "jalr">;
 def BEQ64  : CBranch<0x04, "beq", seteq, CPU64Regs>;

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=144840&r1=144839&r2=144840&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Nov 16 16:36:01 2011
@@ -458,10 +458,11 @@
   FJ<op, (outs), (ins jmptarget:$target),
      !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
 
-let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
-class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
-  FR<op, func, (outs), (ins CPURegs:$rs),
-     !strconcat(instr_asm, "\t$rs"), [(brind CPURegs:$rs)], IIBranch> {
+let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,
+    isIndirectBranch = 1 in
+class JumpFR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
+  FR<op, func, (outs), (ins RC:$rs),
+     !strconcat(instr_asm, "\t$rs"), [(brind RC:$rs)], IIBranch> {
   let rt = 0;
   let rd = 0;
   let shamt = 0;
@@ -779,8 +780,7 @@
 
 /// Jump and Branch Instructions
 def J       : JumpFJ<0x02, "j">;
-let isIndirectBranch = 1 in
-  def JR      : JumpFR<0x00, 0x08, "jr">;
+def JR      : JumpFR<0x00, 0x08, "jr", CPURegs>;
 def JAL     : JumpLink<0x03, "jal">;
 def JALR    : JumpLinkReg<0x00, 0x09, "jalr">;
 def BEQ     : CBranch<0x04, "beq", seteq, CPURegs>;



From ahatanaka at mips.com  Wed Nov 16 16:39:56 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 16 Nov 2011 22:39:56 -0000
Subject: [llvm-commits] [llvm] r144841 - in /llvm/trunk/lib/Target/Mips:
 Mips64InstrInfo.td MipsInstrInfo.td
Message-ID: <20111116223956.D555A1BE001@llvm.org>

Author: ahatanak
Date: Wed Nov 16 16:39:56 2011
New Revision: 144841

URL: http://llvm.org/viewvc/llvm-project?rev=144841&view=rev
Log:
Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
nodes.

Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=144841&r1=144840&r2=144841&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Nov 16 16:39:56 2011
@@ -232,7 +232,24 @@
 }
 
 // hi/lo relocs
-def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>;
+def : Pat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
+def : Pat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
+def : Pat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
+def : Pat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
+
+def : Pat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
+def : Pat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
+def : Pat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
+def : Pat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
+
+def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
+          (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
+def : Pat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
+          (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
+def : Pat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
+          (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
+def : Pat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
+          (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
 
 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
                   ZERO_64>;

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=144841&r1=144840&r2=144841&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Nov 16 16:39:56 2011
@@ -898,20 +898,20 @@
 // hi/lo relocs
 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
+def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
+def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
+
 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
+def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
+def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
+
 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
           (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
           (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
-
-def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
-def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
           (ADDiu CPURegs:$hi, tjumptable:$lo)>;
-
-def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
-def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
           (ADDiu CPURegs:$hi, tconstpool:$lo)>;
 



From grosbach at apple.com  Wed Nov 16 16:40:25 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 16 Nov 2011 22:40:25 -0000
Subject: [llvm-commits] [llvm] r144842 -
	/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
Message-ID: <20111116224025.7D88B1BE001@llvm.org>

Author: grosbach
Date: Wed Nov 16 16:40:25 2011
New Revision: 144842

URL: http://llvm.org/viewvc/llvm-project?rev=144842&view=rev
Log:
Fix encoding of NOP used for padding in ARM mode .align.

Modified:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=144842&r1=144841&r2=144842&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed Nov 16 16:40:25 2011
@@ -138,7 +138,7 @@
   const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
   const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
   const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
-  const uint32_t ARMv6T2_NopEncoding = 0xe3207800; // NOP
+  const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
   if (isThumb()) {
     const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
                                           : Thumb1_16bitNopEncoding;



From daniel at zuster.org  Wed Nov 16 16:41:00 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 22:41:00 -0000
Subject: [llvm-commits] [compiler-rt] r144844 -
	/compiler-rt/trunk/make/platform/clang_darwin.mk
Message-ID: <20111116224100.D5BFF1BE002@llvm.org>

Author: ddunbar
Date: Wed Nov 16 16:41:00 2011
New Revision: 144844

URL: http://llvm.org/viewvc/llvm-project?rev=144844&view=rev
Log:
platform/clang_darwin: Tweak deployment arg variable names.

Modified:
    compiler-rt/trunk/make/platform/clang_darwin.mk

Modified: compiler-rt/trunk/make/platform/clang_darwin.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=144844&r1=144843&r2=144844&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin.mk (original)
+++ compiler-rt/trunk/make/platform/clang_darwin.mk Wed Nov 16 16:41:00 2011
@@ -79,28 +79,28 @@
 # never depend on the environmental overrides. We simply set them to minimum
 # supported deployment target -- nothing in the compiler-rt libraries should
 # actually depend on the deployment target.
-X86_DEPLOYMENT_ARGS := -mmacosx-version-min=10.4
-ARM_DEPLOYMENT_ARGS := -miphoneos-version-min=1.0
+OSX_DEPLOYMENT_ARGS := -mmacosx-version-min=10.4
+IOS_DEPLOYMENT_ARGS := -miphoneos-version-min=1.0
+IOSSIM_DEPLOYMENT_ARGS := -miphoneos-version-min=1.0
 
 # If an explicit ARM_SDK build variable is set, use that as the isysroot.
 ifneq ($(ARM_SDK),)
-ARM_DEPLOYMENT_ARGS += -isysroot $(ARM_SDK)
+IOS_DEPLOYMENT_ARGS += -isysroot $(ARM_SDK)
+IOSSIM_DEPLOYMENT_ARGS += -isysroot $(ARM_SDK)
 endif
 
-CFLAGS.eprintf		:= $(CFLAGS) $(X86_DEPLOYMENT_ARGS)
-CFLAGS.10.4		:= $(CFLAGS) $(X86_DEPLOYMENT_ARGS)
-CFLAGS.ios.i386		:= $(CFLAGS) $(X86_DEPLOYMENT_ARGS)
-CFLAGS.ios.x86_64	:= $(CFLAGS) $(X86_DEPLOYMENT_ARGS)
-CFLAGS.ios.armv6	:= $(CFLAGS) $(ARM_DEPLOYMENT_ARGS)
-CFLAGS.ios.armv7	:= $(CFLAGS) $(ARM_DEPLOYMENT_ARGS)
-CFLAGS.osx.i386         := $(CFLAGS) $(X86_DEPLOYMENT_ARGS)
-CFLAGS.osx.x86_64       := $(CFLAGS) $(X86_DEPLOYMENT_ARGS)
-CFLAGS.osx.armv6        := $(CFLAGS) $(ARM_DEPLOYMENT_ARGS)
-CFLAGS.osx.armv7        := $(CFLAGS) $(ARM_DEPLOYMENT_ARGS)
-CFLAGS.cc_kext.i386	:= $(CFLAGS) $(X86_DEPLOYMENT_ARGS)
-CFLAGS.cc_kext.x86_64	:= $(CFLAGS) $(X86_DEPLOYMENT_ARGS)
-CFLAGS.cc_kext.armv6	:= $(CFLAGS) $(ARM_DEPLOYMENT_ARGS) -mthumb
-CFLAGS.cc_kext.armv7	:= $(CFLAGS) $(ARM_DEPLOYMENT_ARGS)
+CFLAGS.eprintf		:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
+CFLAGS.10.4		:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
+CFLAGS.ios.i386		:= $(CFLAGS) $(IOSSIM_DEPLOYMENT_ARGS)
+CFLAGS.ios.x86_64	:= $(CFLAGS) $(IOSSIM_DEPLOYMENT_ARGS)
+CFLAGS.ios.armv6	:= $(CFLAGS) $(IOS_DEPLOYMENT_ARGS)
+CFLAGS.ios.armv7	:= $(CFLAGS) $(IOS_DEPLOYMENT_ARGS)
+CFLAGS.osx.i386		:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
+CFLAGS.osx.x86_64	:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
+CFLAGS.cc_kext.i386	:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
+CFLAGS.cc_kext.x86_64	:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
+CFLAGS.cc_kext.armv6	:= $(CFLAGS) $(IOS_DEPLOYMENT_ARGS) -mthumb
+CFLAGS.cc_kext.armv7	:= $(CFLAGS) $(IOS_DEPLOYMENT_ARGS)
 
 FUNCTIONS.eprintf := eprintf
 FUNCTIONS.10.4 := eprintf floatundidf floatundisf floatundixf



From daniel at zuster.org  Wed Nov 16 16:40:58 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 22:40:58 -0000
Subject: [llvm-commits] [compiler-rt] r144843 - in /compiler-rt/trunk/SDKs:
 ./ README.txt darwin/ darwin/README.txt darwin/usr/ darwin/usr/include/
 darwin/usr/include/limits.h darwin/usr/include/stdio.h
 darwin/usr/include/stdlib.h darwin/usr/include/string.h
 darwin/usr/include/sys/ darwin/usr/include/sys/stat.h
 darwin/usr/include/sys/types.h
Message-ID: <20111116224058.47D571BE001@llvm.org>

Author: ddunbar
Date: Wed Nov 16 16:40:57 2011
New Revision: 144843

URL: http://llvm.org/viewvc/llvm-project?rev=144843&view=rev
Log:
build/SDKs: Sketch a minimal stub SDK for Darwin.
 - Motivation is explained in the README, but basically it is convenient to be
   able to build compiler-rt free standing. Since our external dependencies are
   so small, we can achieve this relatively easily by just stubbing out the
   declarations of the external dependencies.
 - This is in no way, shape, or form intended to be complete, it is just the
   minimal stubs necessary to support the stuff we use.

Added:
    compiler-rt/trunk/SDKs/
    compiler-rt/trunk/SDKs/README.txt
    compiler-rt/trunk/SDKs/darwin/
    compiler-rt/trunk/SDKs/darwin/README.txt
    compiler-rt/trunk/SDKs/darwin/usr/
    compiler-rt/trunk/SDKs/darwin/usr/include/
    compiler-rt/trunk/SDKs/darwin/usr/include/limits.h
    compiler-rt/trunk/SDKs/darwin/usr/include/stdio.h
    compiler-rt/trunk/SDKs/darwin/usr/include/stdlib.h
    compiler-rt/trunk/SDKs/darwin/usr/include/string.h
    compiler-rt/trunk/SDKs/darwin/usr/include/sys/
    compiler-rt/trunk/SDKs/darwin/usr/include/sys/stat.h
    compiler-rt/trunk/SDKs/darwin/usr/include/sys/types.h

Added: compiler-rt/trunk/SDKs/README.txt
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/README.txt?rev=144843&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/README.txt (added)
+++ compiler-rt/trunk/SDKs/README.txt Wed Nov 16 16:40:57 2011
@@ -0,0 +1,9 @@
+It is often convenient to be able to build compiler-rt libraries for a certain
+platform without having a full SDK or development environment installed.
+
+This makes it easy for users to build a compiler which can target a number of
+different platforms, without having to actively maintain full development
+environments for those platforms.
+
+Since compiler-rt's libraries typically have minimal interaction with the
+system, we achieve this by stubbing out the SDKs of certain platforms.

Added: compiler-rt/trunk/SDKs/darwin/README.txt
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/darwin/README.txt?rev=144843&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/darwin/README.txt (added)
+++ compiler-rt/trunk/SDKs/darwin/README.txt Wed Nov 16 16:40:57 2011
@@ -0,0 +1,3 @@
+The Darwin platforms are all similar enough we roll them into one SDK, and use
+preprocessor tricks to get the right definitions for the few things which
+diverge between OS X and iOS.

Added: compiler-rt/trunk/SDKs/darwin/usr/include/limits.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/darwin/usr/include/limits.h?rev=144843&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/darwin/usr/include/limits.h (added)
+++ compiler-rt/trunk/SDKs/darwin/usr/include/limits.h Wed Nov 16 16:40:57 2011
@@ -0,0 +1,23 @@
+/* ===-- limits.h - stub SDK header for compiler-rt -------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __LIMITS_H__
+#define __LIMITS_H__
+
+/* This is only here as a landing pad for the include_next from the compiler's
+   built-in limits.h. */
+
+#endif /* __LIMITS_H__ */

Added: compiler-rt/trunk/SDKs/darwin/usr/include/stdio.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/darwin/usr/include/stdio.h?rev=144843&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/darwin/usr/include/stdio.h (added)
+++ compiler-rt/trunk/SDKs/darwin/usr/include/stdio.h Wed Nov 16 16:40:57 2011
@@ -0,0 +1,61 @@
+/* ===-- stdio.h - stub SDK header for compiler-rt --------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __STDIO_H__
+#define __STDIO_H__
+
+typedef struct __sFILE FILE;
+typedef __SIZE_TYPE__ size_t;
+
+/* Determine the appropriate fopen() and fwrite() functions. */
+#if defined(__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__)
+#  if defined(__i386)
+#    define __FOPEN_NAME "_fopen$UNIX2003"
+#    define __FWRITE_NAME "_fwrite$UNIX2003"
+#  elif defined(__x86_64__)
+#    define __FOPEN_NAME "_fopen"
+#    define __FWRITE_NAME "_fwrite"
+#  elif defined(__arm)
+#    define __FOPEN_NAME "_fopen"
+#    define __FWRITE_NAME "_fwrite"
+#  else
+#    error "unrecognized architecture for targetting OS X"
+#  endif
+#elif defined(__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__)
+#  if defined(__i386) || defined (__x86_64)
+#    define __FOPEN_NAME "_fopen"
+#    define __FWRITE_NAME "_fwrite"
+#  elif defined(__arm)
+#    define __FOPEN_NAME "_fopen"
+#    define __FWRITE_NAME "_fwrite"
+#  else
+#    error "unrecognized architecture for targetting iOS"
+#  endif
+#else
+#  error "unrecognized architecture for targetting Darwin"
+#endif
+
+#    define stderr __stderrp
+extern FILE *__stderrp;
+
+int fclose(FILE *);
+int fflush(FILE *);
+FILE *fopen(const char * restrict, const char * restrict) __asm(__FOPEN_NAME);
+int fprintf(FILE * restrict, const char * restrict, ...);
+size_t fwrite(const void * restrict, size_t, size_t, FILE * restrict)
+  __asm(__FWRITE_NAME);
+
+#endif /* __STDIO_H__ */

Added: compiler-rt/trunk/SDKs/darwin/usr/include/stdlib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/darwin/usr/include/stdlib.h?rev=144843&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/darwin/usr/include/stdlib.h (added)
+++ compiler-rt/trunk/SDKs/darwin/usr/include/stdlib.h Wed Nov 16 16:40:57 2011
@@ -0,0 +1,29 @@
+/* ===-- stdlib.h - stub SDK header for compiler-rt -------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __STDLIB_H__
+#define __STDLIB_H__
+
+#define NULL ((void *)0)
+
+typedef __SIZE_TYPE__ size_t;
+
+void abort(void) __attribute__((__noreturn__));
+void free(void *);
+char *getenv(const char *);
+void *malloc(size_t);
+
+#endif /* __STDLIB_H__ */

Added: compiler-rt/trunk/SDKs/darwin/usr/include/string.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/darwin/usr/include/string.h?rev=144843&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/darwin/usr/include/string.h (added)
+++ compiler-rt/trunk/SDKs/darwin/usr/include/string.h Wed Nov 16 16:40:57 2011
@@ -0,0 +1,28 @@
+/* ===-- string.h - stub SDK header for compiler-rt -------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __STRING_H__
+#define __STRING_H__
+
+typedef __SIZE_TYPE__ size_t;
+
+char *strcat(char *, const char *);
+char *strcpy(char *, const char *);
+char *strdup(const char *);
+size_t strlen(const char *);
+char *strncpy(char *, const char *, size_t);
+
+#endif /* __STRING_H__ */

Added: compiler-rt/trunk/SDKs/darwin/usr/include/sys/stat.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/darwin/usr/include/sys/stat.h?rev=144843&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/darwin/usr/include/sys/stat.h (added)
+++ compiler-rt/trunk/SDKs/darwin/usr/include/sys/stat.h Wed Nov 16 16:40:57 2011
@@ -0,0 +1,25 @@
+/* ===-- stat.h - stub SDK header for compiler-rt ---------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __SYS_STAT_H__
+#define __SYS_STAT_H__
+
+typedef unsigned short uint16_t;
+typedef uint16_t mode_t;
+
+int mkdir(const char *, mode_t);
+
+#endif /* __SYS_STAT_H__ */

Added: compiler-rt/trunk/SDKs/darwin/usr/include/sys/types.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/SDKs/darwin/usr/include/sys/types.h?rev=144843&view=auto
==============================================================================
--- compiler-rt/trunk/SDKs/darwin/usr/include/sys/types.h (added)
+++ compiler-rt/trunk/SDKs/darwin/usr/include/sys/types.h Wed Nov 16 16:40:57 2011
@@ -0,0 +1,20 @@
+/* ===-- types.h - stub SDK header for compiler-rt --------------------------===
+ *
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ===-----------------------------------------------------------------------===
+ *
+ * This is a stub SDK header file. This file is not part of the interface of
+ * this library nor an official version of the appropriate SDK header. It is
+ * intended only to stub the features of this header required by compiler-rt.
+ *
+ * ===-----------------------------------------------------------------------===
+ */
+
+#ifndef __SYS_TYPES_H__
+#define __SYS_TYPES_H__
+
+#endif /* __SYS_TYPES_H__ */



From daniel at zuster.org  Wed Nov 16 16:41:03 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 22:41:03 -0000
Subject: [llvm-commits] [compiler-rt] r144845 -
	/compiler-rt/trunk/make/platform/clang_darwin.mk
Message-ID: <20111116224103.596B51BE002@llvm.org>

Author: ddunbar
Date: Wed Nov 16 16:41:03 2011
New Revision: 144845

URL: http://llvm.org/viewvc/llvm-project?rev=144845&view=rev
Log:
platform/clang_darwin: Switch over to use stub Darwin SDK.

Modified:
    compiler-rt/trunk/make/platform/clang_darwin.mk

Modified: compiler-rt/trunk/make/platform/clang_darwin.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=144845&r1=144844&r2=144845&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin.mk (original)
+++ compiler-rt/trunk/make/platform/clang_darwin.mk Wed Nov 16 16:41:03 2011
@@ -84,10 +84,9 @@
 IOSSIM_DEPLOYMENT_ARGS := -miphoneos-version-min=1.0
 
 # If an explicit ARM_SDK build variable is set, use that as the isysroot.
-ifneq ($(ARM_SDK),)
-IOS_DEPLOYMENT_ARGS += -isysroot $(ARM_SDK)
-IOSSIM_DEPLOYMENT_ARGS += -isysroot $(ARM_SDK)
-endif
+X86_OSX_DEPLOYMENT_ARGS += -isysroot $(ProjSrcRoot)/SDKs/darwin
+ARM_IOS_DEPLOYMENT_ARGS += -isysroot $(ProjSrcRoot)/SDKs/darwin
+X86_IOS_DEPLOYMENT_ARGS += -isysroot $(ProjSrcRoot)/SDKs/darwin
 
 CFLAGS.eprintf		:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
 CFLAGS.10.4		:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)



From ahatanaka at mips.com  Wed Nov 16 16:42:10 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 16 Nov 2011 22:42:10 -0000
Subject: [llvm-commits] [llvm] r144847 -
	/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
Message-ID: <20111116224210.F31101BE001@llvm.org>

Author: ahatanak
Date: Wed Nov 16 16:42:10 2011
New Revision: 144847

URL: http://llvm.org/viewvc/llvm-project?rev=144847&view=rev
Log:
Lower 64-bit block address.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=144847&r1=144846&r2=144847&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Nov 16 16:42:10 2011
@@ -127,6 +127,7 @@
   setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
   setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
   setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
+  setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
   setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
   setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
   setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
@@ -1506,7 +1507,7 @@
   // FIXME there isn't actually debug info here
   DebugLoc dl = Op.getDebugLoc();
 
-  if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
+  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
     // %hi/%lo relocation
     SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
                                        MipsII::MO_ABS_HI);
@@ -1517,16 +1518,17 @@
     return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
   }
 
-  SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
-                                            MipsII::MO_GOT);
-  BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset);
-  SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
-                                           MipsII::MO_ABS_LO);
-  SDValue Load = DAG.getLoad(MVT::i32, dl,
+  EVT ValTy = Op.getValueType();
+  unsigned GOTFlag = IsN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
+  unsigned OFSTFlag = IsN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
+  SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag);
+  BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, ValTy, BAGOTOffset);
+  SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag);
+  SDValue Load = DAG.getLoad(ValTy, dl,
                              DAG.getEntryNode(), BAGOTOffset,
                              MachinePointerInfo(), false, false, false, 0);
-  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
-  return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
+  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
+  return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
 }
 
 SDValue MipsTargetLowering::



From ahatanaka at mips.com  Wed Nov 16 16:44:38 2011
From: ahatanaka at mips.com (Akira Hatanaka)
Date: Wed, 16 Nov 2011 22:44:38 -0000
Subject: [llvm-commits] [llvm] r144849 -
	/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
Message-ID: <20111116224438.6F7CD1BE001@llvm.org>

Author: ahatanak
Date: Wed Nov 16 16:44:38 2011
New Revision: 144849

URL: http://llvm.org/viewvc/llvm-project?rev=144849&view=rev
Log:
Lower 64-bit constant pool node.


Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=144849&r1=144848&r2=144849&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Nov 16 16:44:38 2011
@@ -131,6 +131,7 @@
   setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
   setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
   setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
+  setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
   setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
   setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
   setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
@@ -1651,16 +1652,19 @@
     SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
     ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
   } else {
-    SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
-                                           N->getOffset(), MipsII::MO_GOT);
-    CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP);
-    SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
+    EVT ValTy = Op.getValueType();
+    unsigned GOTFlag = IsN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
+    unsigned OFSTFlag = IsN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
+    SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
+                                           N->getOffset(), GOTFlag);
+    CP = DAG.getNode(MipsISD::WrapperPIC, dl, ValTy, CP);
+    SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(),
                                CP, MachinePointerInfo::getConstantPool(),
                                false, false, false, 0);
-    SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
-                                             N->getOffset(), MipsII::MO_ABS_LO);
-    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
-    ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
+    SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
+                                             N->getOffset(), OFSTFlag);
+    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
+    ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
   }
 
   return ResNode;



From grosbach at apple.com  Wed Nov 16 16:46:27 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 16 Nov 2011 22:46:27 -0000
Subject: [llvm-commits] [llvm] r144851 -
	/llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s
Message-ID: <20111116224627.D328E1BE001@llvm.org>

Author: grosbach
Date: Wed Nov 16 16:46:27 2011
New Revision: 144851

URL: http://llvm.org/viewvc/llvm-project?rev=144851&view=rev
Log:
Update test for r144842.

Modified:
    llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s

Modified: llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s?rev=144851&r1=144850&r2=144851&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s (original)
+++ llvm/trunk/test/MC/ARM/nop-armv6t2-padding.s Wed Nov 16 16:46:27 2011
@@ -7,4 +7,4 @@
       .align 4
       add r0, r1, r2
 
-@ CHECK: ('_section_data', '020081e0 007820e3 007820e3 007820e3 020081e0')
+@ CHECK: ('_section_data', '020081e0 00f020e3 00f020e3 00f020e3 020081e0')



From grosbach at apple.com  Wed Nov 16 16:48:37 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 16 Nov 2011 22:48:37 -0000
Subject: [llvm-commits] [llvm] r144852 - in /llvm/trunk:
 lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
 test/MC/ARM/basic-arm-instructions.s
Message-ID: <20111116224837.B9C081BE001@llvm.org>

Author: grosbach
Date: Wed Nov 16 16:48:37 2011
New Revision: 144852

URL: http://llvm.org/viewvc/llvm-project?rev=144852&view=rev
Log:
Generalize the fixup info for ARM mode.

We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

Modified:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
    llvm/trunk/test/MC/ARM/basic-arm-instructions.s

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=144852&r1=144851&r2=144852&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed Nov 16 16:48:37 2011
@@ -60,7 +60,7 @@
 // ARMFixupKinds.h.
 //
 // Name                      Offset (bits) Size (bits)     Flags
-{ "fixup_arm_ldst_pcrel_12", 1,            24,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_ldst_pcrel_12", 0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_ldst_pcrel_12",  0,            32,  MCFixupKindInfo::FKF_IsPCRel |
                                    MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
 { "fixup_arm_pcrel_10",      0,            32,  MCFixupKindInfo::FKF_IsPCRel },
@@ -68,7 +68,7 @@
                                    MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
 { "fixup_thumb_adr_pcrel_10",0,            8,   MCFixupKindInfo::FKF_IsPCRel |
                                    MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
-{ "fixup_arm_adr_pcrel_12",  1,            24,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_adr_pcrel_12",  0,            32,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_t2_adr_pcrel_12",   0,            32,  MCFixupKindInfo::FKF_IsPCRel |
                                    MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
 { "fixup_arm_condbranch",    0,            24,  MCFixupKindInfo::FKF_IsPCRel },

Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=144852&r1=144851&r2=144852&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Wed Nov 16 16:48:37 2011
@@ -133,9 +133,9 @@
         adr	r2, #-3
 
 @ CHECK: Lback:
-@ CHECK: adr	r2, Lback    @ encoding: [0bAAAAAAA0,0x20'A',0x0f'A',0b1110001A]
+@ CHECK: adr	r2, Lback    @ encoding: [A,0x20'A',0x0f'A',0xe2'A']
 @ CHECK:  @   fixup A - offset: 0, value: Lback, kind: fixup_arm_adr_pcrel_12
-@ CHECK: adr	r3, Lforward @ encoding: [0bAAAAAAA0,0x30'A',0x0f'A',0b1110001A]
+@ CHECK: adr	r3, Lforward @ encoding: [A,0x30'A',0x0f'A',0xe2'A']
 @ CHECK:  @   fixup A - offset: 0, value: Lforward, kind: fixup_arm_adr_pcrel_12
 @ CHECK: Lforward:
 @ CHECK: adr	r2, #3                  @ encoding: [0x03,0x20,0x8f,0xe2]



From grosbach at apple.com  Wed Nov 16 16:50:38 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 16 Nov 2011 22:50:38 -0000
Subject: [llvm-commits] [llvm] r144853 - /llvm/trunk/test/MC/ARM/prefetch.ll
Message-ID: <20111116225038.BFBE61BE001@llvm.org>

Author: grosbach
Date: Wed Nov 16 16:50:38 2011
New Revision: 144853

URL: http://llvm.org/viewvc/llvm-project?rev=144853&view=rev
Log:
Remove obsolete test.

The PLD encoding is checked via the .s file now.

Removed:
    llvm/trunk/test/MC/ARM/prefetch.ll

Removed: llvm/trunk/test/MC/ARM/prefetch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/prefetch.ll?rev=144852&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/prefetch.ll (original)
+++ llvm/trunk/test/MC/ARM/prefetch.ll (removed)
@@ -1,58 +0,0 @@
-; RUN: llc < %s -mtriple=armv7-apple-darwin   -mattr=+v7,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7     -show-mc-encoding | FileCheck %s -check-prefix=T2
-; rdar://8924681
-
-define void @t1(i8* %ptr) nounwind  {
-entry:
-; ARM: t1:
-; ARM: pldw [r0]                        @ encoding: [0x00,0xf0,0x90,0xf5]
-; ARM: pld [r0]                         @ encoding: [0x00,0xf0,0xd0,0xf5]
-
-; T2: t1:
-; T2: pld [r0]                      @ encoding: [0x90,0xf8,0x00,0xf0]
-  tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3 )
-  tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
-  ret void
-}
-
-define void @t2(i8* %ptr) nounwind  {
-entry:
-; ARM: t2:
-; ARM: pld [r0, #1023]                  @ encoding: [0xff,0xf3,0xd0,0xf5]
-
-; T2: t2:
-; T2: pld [r0, #1023]               @ encoding: [0x90,0xf8,0xff,0xf3]
-  %tmp = getelementptr i8* %ptr, i32 1023
-  tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3 )
-  ret void
-}
-
-define void @t3(i32 %base, i32 %offset) nounwind  {
-entry:
-; ARM: t3:
-; ARM: pld [r0, r1, lsr #2]             @ encoding: [0x21,0xf1,0xd0,0xf7]
-
-; T2: t3:
-; T2: pld [r0, r1]                  @ encoding: [0x10,0xf8,0x01,0xf0]
-  %tmp1 = lshr i32 %offset, 2
-  %tmp2 = add i32 %base, %tmp1
-  %tmp3 = inttoptr i32 %tmp2 to i8*
-  tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
-  ret void
-}
-
-define void @t4(i32 %base, i32 %offset) nounwind  {
-entry:
-; ARM: t4:
-; ARM: pld [r0, r1, lsl #2]             @ encoding: [0x01,0xf1,0xd0,0xf7]
-
-; T2: t4:
-; T2: pld [r0, r1, lsl #2]          @ encoding: [0x10,0xf8,0x21,0xf0]
-  %tmp1 = shl i32 %offset, 2
-  %tmp2 = add i32 %base, %tmp1
-  %tmp3 = inttoptr i32 %tmp2 to i8*
-  tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
-  ret void
-}
-
-declare void @llvm.prefetch(i8*, i32, i32) nounwind 



From bigcheesegs at gmail.com  Wed Nov 16 17:36:12 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Wed, 16 Nov 2011 23:36:12 -0000
Subject: [llvm-commits] [llvm] r144861 -
	/llvm/trunk/lib/Object/COFFObjectFile.cpp
Message-ID: <20111116233612.889F91BE001@llvm.org>

Author: mspencer
Date: Wed Nov 16 17:36:12 2011
New Revision: 144861

URL: http://llvm.org/viewvc/llvm-project?rev=144861&view=rev
Log:
Object/COFF: Support common symbols.

Modified:
    llvm/trunk/lib/Object/COFFObjectFile.cpp

Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=144861&r1=144860&r2=144861&view=diff
==============================================================================
--- llvm/trunk/lib/Object/COFFObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/COFFObjectFile.cpp Wed Nov 16 17:36:12 2011
@@ -226,7 +226,9 @@
     if (symb->StorageClass == COFF::IMAGE_SYM_CLASS_WEAK_EXTERNAL) {
       Result = 'w';
       return object_error::success; // Don't do ::toupper.
-    } else
+    } else if (symb->Value != 0) // Check for common symbols.
+      ret = 'c';
+    else
       ret = 'u';
     break;
   case COFF::IMAGE_SYM_ABSOLUTE:



From hfinkel at anl.gov  Wed Nov 16 17:38:59 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Wed, 16 Nov 2011 17:38:59 -0600
Subject: [llvm-commits] [LLVMdev] [PATCH] BasicBlock Autovectorization
 Pass
In-Reply-To: <1321400339.19359.782.camel@sapling>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
	<1319919418.23036.881.camel@sapling>
	<1319928991.23036.957.camel@sapling>
	<1320108633.23036.1266.camel@sapling>
	<1320172356.23036.1298.camel@sapling>
	<4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling>
	<1320191694.23036.1497.camel@sapling>
	<1320749109.19359.76.camel@sapling>
	<4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling>
	<4EB98207.2070807@grosser.es> <1320791390.19359.262.camel@sapling>
	<4EBC4B0F.6010609@grosser.es> <1321050998.19359.539.camel@sapling>
	<4EBDA7F9.9080709@grosser.es> <1321053083.19359.550.camel@sapling>
	<4EBDB1BF.7090006@grosser.es>  <1321400339.19359.782.camel@sapling>
Message-ID: <1321486739.19359.1067.camel@sapling>

Tobias, et al.,

Attached is the my autovectorization pass. I've fixed a bug that appears
when using -bb-vectorize-aligned-only, fixed some 80-col violations,
etc., and at least on x86_64, all test cases pass except for a few; and
all of these failures look like instruction-selection bugs. For example:

MultiSource/Applications/ClamAV - fails to compile shared_sha256.c with
an error: error in backend: Cannot select: 0x4fbcb40: v2i64 =
X86ISD::MOVLPD 0x4149e00, 0x418d930 [ID=596]
SingleSource/Benchmarks/BenchmarkGame/n-body - crashes; incorrectly
generates an aligned vector load for an unaligned load (so passing
-bb-vectorize-aligned-only will make it work for now)

 -Hal

On Tue, 2011-11-15 at 17:38 -0600, Hal Finkel wrote:
> Tobias,
> 
> I've attached the latest version of my autovectorization patch. I was
> able to add support for using the ScalarEvolution analysis for
> load/store pairing (thanks for your help!). This led to a modest
> performance increase and a modest compile-time increase. This version
> also has a cutoff as you suggested (although the default value is set
> high (4000 instructions between pairs) because setting it lower led to
> performance regressions in both run time and compile time).
> 
> At this point there seem to be no unexpected test-suite compile
> failures. Some of the tests, however, do seem to compute the wrong
> output. I've yet to determine whether this is due to bad instruction
> fusing or some error in a later stage. I'll try running the failing
> tests in the interpreter and/or on another platform.
> 
> Thanks again,
> Hal
> 
> On Sat, 2011-11-12 at 00:37 +0100, Tobias Grosser wrote:
> > On 11/12/2011 12:11 AM, Hal Finkel wrote:
> > > On Fri, 2011-11-11 at 23:55 +0100, Tobias Grosser wrote:
> > >> On 11/11/2011 11:36 PM, Hal Finkel wrote:
> > >>> On Thu, 2011-11-10 at 23:07 +0100, Tobias Grosser wrote:
> > >>>> On 11/08/2011 11:29 PM, Hal Finkel wrote: Talking about this I
> > >>>> looked again into ScalarEvolution.
> > >>>>
> > >>>> To analyze a load, you would do:
> > >>>>
> > >>>> LoadInst *Load = ... Value *Pointer = Load->getPointer(); const
> > >>>> SCEV *PointerSCEV = SE->getSCEV(Pointer); const SCEVUnknown
> > >>>> *PointerBase =
> > >>>> dyn_cast<SCEVUnknown>(SE->getPointerBase(PointerSCEV));
> > >>>>
> > >>>> if (!PointerBase) return 'Analysis failed'
> > >>>>
> > >>>> const Value *BaseValue = PointerBase->getValue();
> > >>>>
> > >>>> You get the offset between two load addresses with
> > >>>> SE->getMinusSCEV(). The size of an element is
> > >>>> SE->getSizeOfExpr().
> > >>>>
> > >>>
> > >>> The AliasAnalysis class has a set of interfaces that can be used
> > >>> to preserve the analysis even when some things are changed. Does
> > >>> ScalarEvolution have a similar capability?
> > >>
> > >> You can state that your pass preserves ScalarEvolution. In this
> > >> case all analysis results are by default preserved and it is your
> > >> job to invalidate the scalar evolution for the loops/values where
> > >> it needs to be recalculated.
> > >>
> > >> The relevant functions are
> > >>
> > >> ScalarEvolution::forgetValue(Value *)
> > >
> > > Since the vectorization pass is currently just a basic-block pass, I
> > > think that I should need only forgetValue, right? I suppose that I
> > > would call that on all of the values that are fused.
> > 
> > You call it on all the values/instructions that are removed and for
> > those where the result calculated has changed.
> > 
> > > Also, using getPointerBase to get the base pointer seems simple
> > > enough, but how should I use getMinusSCEV to get the offset.
> > 
> > This should give you the offset from the base pointer:
> > 
> > LoadInst *Load = ...
> > Value *Pointer = Load->getPointer();
> > const SCEV *PointerSCEV = SE->getSCEV(Pointer);
> > const SCEVUnknown *PointerBase =
> > 	dyn_cast<SCEVUnknown>(SE->getPointerBase(PointerSCEV));
> > 
> > if (!PointerBase)
> >    return 'Analysis failed'
> > 
> > const SCEV *OffsetFromBase = SE->getMinusSCEV(Pointer, PointerBase);
> > 
> > > Should I call it on each load pointer and its base pointer, or
> > > between the two load pointers once I know that they share the same
> > > base.
> > That depends what you want.
> > 
> > > And once I do that, how do I get the offset (if known). I see the
> > > get[Uns|S]ignedRange functions, but if there is a way to directly get
> > > a constant value, then that would be more straightforward.
> > 
> > I assume you want to know if two load addresses are either identical, 
> > have stride one (have a offset of +1) or some other more complicated stuff.
> > 
> > What might work is the following (entirely untested):
> > 
> > LoadInst *LoadOne = ...
> > LoadInst *LoadTwo = ...
> > 
> > Value *PointerOne = LoadOne->getPointer();
> > Value *PointerTwo = LoadTwo->getPointer();
> > 
> > const SCEV *PointerOneSCEV = SE->getSCEV(PointerOne);
> > const SCEV *PointerTwoSCEV = SE->getSCEV(PointerTwo);
> > 
> > // If this is a trivial offset we get something like 1*sizeof(long)
> > const SCEV *Offset = SE->getMinusSCEV(PointerOneSCEV, PointerTwoSCEV);
> > 
> > // Now we devide it by the element size
> > Type *AllocTy = LoadOne->getType()->getAllocTy();
> > const SCEV *TypeOfSCEV = SE->getSizeOfExpr(AllocTy);
> > const SCEV *OffsetInElements = SE->getUDivExpr(Offset, TypeOfSCEV);
> > 
> > if (const SCEVConstant *IntOffsetSCEV
> > 	= dyn_cast<SCEVConstant>(OffsetInElements)) {
> >    ConstantInt *IntOffset = IntOffsetSCEV->getValue()
> >    return IntOffset;
> > } else {
> >    return "This seems to be a complicated offset";
> > }
> > 
> > const SCEV *OffsetInElements = SE->getUDivExpr(Offset, TypeOfSCEV);
> > 
> > Let me know if this or something similar worked.
> > Tobi
> > 
> > 
> > 
> > 
> > 
> > 
> > 
> > 
> 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory
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From hfinkel at anl.gov  Wed Nov 16 17:50:23 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Wed, 16 Nov 2011 17:50:23 -0600
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <1321486739.19359.1067.camel@sapling>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
	<1319919418.23036.881.camel@sapling>
	<1319928991.23036.957.camel@sapling>
	<1320108633.23036.1266.camel@sapling>
	<1320172356.23036.1298.camel@sapling>
	<4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling>
	<1320191694.23036.1497.camel@sapling>
	<1320749109.19359.76.camel@sapling>
	<4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling>
	<4EB98207.2070807@grosser.es> <1320791390.19359.262.camel@sapling>
	<4EBC4B0F.6010609@grosser.es> <1321050998.19359.539.camel@sapling>
	<4EBDA7F9.9080709@grosser.es> <1321053083.19359.550.camel@sapling>
	<4EBDB1BF.7090006@grosser.es>  <1321400339.19359.782.camel@sapling>
	<1321486739.19359.1067.camel@sapling>
Message-ID: <1321487423.19359.1078.camel@sapling>

Please review this patch (attached to previous e-mail) and let me know
if there is any objection to me committing it at this point.

Thanks again,
Hal

On Wed, 2011-11-16 at 17:39 -0600, Hal Finkel wrote:
> Tobias, et al.,
> 
> Attached is the my autovectorization pass. I've fixed a bug that appears
> when using -bb-vectorize-aligned-only, fixed some 80-col violations,
> etc., and at least on x86_64, all test cases pass except for a few; and
> all of these failures look like instruction-selection bugs. For example:
> 
> MultiSource/Applications/ClamAV - fails to compile shared_sha256.c with
> an error: error in backend: Cannot select: 0x4fbcb40: v2i64 =
> X86ISD::MOVLPD 0x4149e00, 0x418d930 [ID=596]
> SingleSource/Benchmarks/BenchmarkGame/n-body - crashes; incorrectly
> generates an aligned vector load for an unaligned load (so passing
> -bb-vectorize-aligned-only will make it work for now)
> 
>  -Hal
> 
> On Tue, 2011-11-15 at 17:38 -0600, Hal Finkel wrote:
> > Tobias,
> > 
> > I've attached the latest version of my autovectorization patch. I was
> > able to add support for using the ScalarEvolution analysis for
> > load/store pairing (thanks for your help!). This led to a modest
> > performance increase and a modest compile-time increase. This version
> > also has a cutoff as you suggested (although the default value is set
> > high (4000 instructions between pairs) because setting it lower led to
> > performance regressions in both run time and compile time).
> > 
> > At this point there seem to be no unexpected test-suite compile
> > failures. Some of the tests, however, do seem to compute the wrong
> > output. I've yet to determine whether this is due to bad instruction
> > fusing or some error in a later stage. I'll try running the failing
> > tests in the interpreter and/or on another platform.
> > 
> > Thanks again,
> > Hal
> > 
> > On Sat, 2011-11-12 at 00:37 +0100, Tobias Grosser wrote:
> > > On 11/12/2011 12:11 AM, Hal Finkel wrote:
> > > > On Fri, 2011-11-11 at 23:55 +0100, Tobias Grosser wrote:
> > > >> On 11/11/2011 11:36 PM, Hal Finkel wrote:
> > > >>> On Thu, 2011-11-10 at 23:07 +0100, Tobias Grosser wrote:
> > > >>>> On 11/08/2011 11:29 PM, Hal Finkel wrote: Talking about this I
> > > >>>> looked again into ScalarEvolution.
> > > >>>>
> > > >>>> To analyze a load, you would do:
> > > >>>>
> > > >>>> LoadInst *Load = ... Value *Pointer = Load->getPointer(); const
> > > >>>> SCEV *PointerSCEV = SE->getSCEV(Pointer); const SCEVUnknown
> > > >>>> *PointerBase =
> > > >>>> dyn_cast<SCEVUnknown>(SE->getPointerBase(PointerSCEV));
> > > >>>>
> > > >>>> if (!PointerBase) return 'Analysis failed'
> > > >>>>
> > > >>>> const Value *BaseValue = PointerBase->getValue();
> > > >>>>
> > > >>>> You get the offset between two load addresses with
> > > >>>> SE->getMinusSCEV(). The size of an element is
> > > >>>> SE->getSizeOfExpr().
> > > >>>>
> > > >>>
> > > >>> The AliasAnalysis class has a set of interfaces that can be used
> > > >>> to preserve the analysis even when some things are changed. Does
> > > >>> ScalarEvolution have a similar capability?
> > > >>
> > > >> You can state that your pass preserves ScalarEvolution. In this
> > > >> case all analysis results are by default preserved and it is your
> > > >> job to invalidate the scalar evolution for the loops/values where
> > > >> it needs to be recalculated.
> > > >>
> > > >> The relevant functions are
> > > >>
> > > >> ScalarEvolution::forgetValue(Value *)
> > > >
> > > > Since the vectorization pass is currently just a basic-block pass, I
> > > > think that I should need only forgetValue, right? I suppose that I
> > > > would call that on all of the values that are fused.
> > > 
> > > You call it on all the values/instructions that are removed and for
> > > those where the result calculated has changed.
> > > 
> > > > Also, using getPointerBase to get the base pointer seems simple
> > > > enough, but how should I use getMinusSCEV to get the offset.
> > > 
> > > This should give you the offset from the base pointer:
> > > 
> > > LoadInst *Load = ...
> > > Value *Pointer = Load->getPointer();
> > > const SCEV *PointerSCEV = SE->getSCEV(Pointer);
> > > const SCEVUnknown *PointerBase =
> > > 	dyn_cast<SCEVUnknown>(SE->getPointerBase(PointerSCEV));
> > > 
> > > if (!PointerBase)
> > >    return 'Analysis failed'
> > > 
> > > const SCEV *OffsetFromBase = SE->getMinusSCEV(Pointer, PointerBase);
> > > 
> > > > Should I call it on each load pointer and its base pointer, or
> > > > between the two load pointers once I know that they share the same
> > > > base.
> > > That depends what you want.
> > > 
> > > > And once I do that, how do I get the offset (if known). I see the
> > > > get[Uns|S]ignedRange functions, but if there is a way to directly get
> > > > a constant value, then that would be more straightforward.
> > > 
> > > I assume you want to know if two load addresses are either identical, 
> > > have stride one (have a offset of +1) or some other more complicated stuff.
> > > 
> > > What might work is the following (entirely untested):
> > > 
> > > LoadInst *LoadOne = ...
> > > LoadInst *LoadTwo = ...
> > > 
> > > Value *PointerOne = LoadOne->getPointer();
> > > Value *PointerTwo = LoadTwo->getPointer();
> > > 
> > > const SCEV *PointerOneSCEV = SE->getSCEV(PointerOne);
> > > const SCEV *PointerTwoSCEV = SE->getSCEV(PointerTwo);
> > > 
> > > // If this is a trivial offset we get something like 1*sizeof(long)
> > > const SCEV *Offset = SE->getMinusSCEV(PointerOneSCEV, PointerTwoSCEV);
> > > 
> > > // Now we devide it by the element size
> > > Type *AllocTy = LoadOne->getType()->getAllocTy();
> > > const SCEV *TypeOfSCEV = SE->getSizeOfExpr(AllocTy);
> > > const SCEV *OffsetInElements = SE->getUDivExpr(Offset, TypeOfSCEV);
> > > 
> > > if (const SCEVConstant *IntOffsetSCEV
> > > 	= dyn_cast<SCEVConstant>(OffsetInElements)) {
> > >    ConstantInt *IntOffset = IntOffsetSCEV->getValue()
> > >    return IntOffset;
> > > } else {
> > >    return "This seems to be a complicated offset";
> > > }
> > > 
> > > const SCEV *OffsetInElements = SE->getUDivExpr(Offset, TypeOfSCEV);
> > > 
> > > Let me know if this or something similar worked.
> > > Tobi
> > > 
> > > 
> > > 
> > > 
> > > 
> > > 
> > > 
> > > 
> > 
> > _______________________________________________
> > LLVM Developers mailing list
> > LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From eli.friedman at gmail.com  Wed Nov 16 17:50:23 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 16 Nov 2011 23:50:23 -0000
Subject: [llvm-commits] [llvm] r144863 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 test/CodeGen/X86/vec_extract-sse4.ll
Message-ID: <20111116235023.1D6F21BE001@llvm.org>

Author: efriedma
Date: Wed Nov 16 17:50:22 2011
New Revision: 144863

URL: http://llvm.org/viewvc/llvm-project?rev=144863&view=rev
Log:
Make sure to replace the chain properly when DAGCombining a LOAD+EXTRACT_VECTOR_ELT into a single LOAD.  Fixes PR10747/PR11393.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/vec_extract-sse4.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=144863&r1=144862&r2=144863&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Nov 16 17:50:22 2011
@@ -6936,10 +6936,23 @@
                            DAG.getConstant(PtrOff, PtrType));
     }
 
-    return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
-                       LN0->getPointerInfo().getWithOffset(PtrOff),
-                       LN0->isVolatile(), LN0->isNonTemporal(), 
-                       LN0->isInvariant(), Align);
+    // The replacement we need to do here is a little tricky: we need to
+    // replace an extractelement of a load with a load.
+    // Use ReplaceAllUsesOfValuesWith to do the replacement.
+    SDValue Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
+                               LN0->getPointerInfo().getWithOffset(PtrOff),
+                               LN0->isVolatile(), LN0->isNonTemporal(), 
+                               LN0->isInvariant(), Align);
+    WorkListRemover DeadNodes(*this);
+    SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
+    SDValue To[] = { Load.getValue(0), Load.getValue(1) };
+    DAG.ReplaceAllUsesOfValuesWith(From, To, 2, &DeadNodes);
+    // Since we're explcitly calling ReplaceAllUses, add the new node to the
+    // worklist explicitly as well.
+    AddToWorkList(Load.getNode());
+    // Make sure to revisit this node to clean it up; it will usually be dead.
+    AddToWorkList(N);
+    return SDValue(N, 0);
   }
 
   return SDValue();

Modified: llvm/trunk/test/CodeGen/X86/vec_extract-sse4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_extract-sse4.ll?rev=144863&r1=144862&r2=144863&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_extract-sse4.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_extract-sse4.ll Wed Nov 16 17:50:22 2011
@@ -2,7 +2,7 @@
 ; RUN: not grep extractps   %t
 ; RUN: not grep pextrd      %t
 ; RUN: not grep pshufd  %t
-; RUN: grep movss   %t | count 2
+; RUN: not grep movss   %t
 
 define void @t1(float* %R, <4 x float>* %P1) nounwind {
 	%X = load <4 x float>* %P1



From daniel at zuster.org  Wed Nov 16 17:56:03 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 16 Nov 2011 23:56:03 -0000
Subject: [llvm-commits] [llvm] r144864 - /llvm/trunk/test/Makefile
Message-ID: <20111116235603.ACED81BE001@llvm.org>

Author: ddunbar
Date: Wed Nov 16 17:56:03 2011
New Revision: 144864

URL: http://llvm.org/viewvc/llvm-project?rev=144864&view=rev
Log:
build/make/test: Get rid of unused BUGPOINT_TOPTS variable.

Modified:
    llvm/trunk/test/Makefile

Modified: llvm/trunk/test/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=144864&r1=144863&r2=144864&view=diff
==============================================================================
--- llvm/trunk/test/Makefile (original)
+++ llvm/trunk/test/Makefile Wed Nov 16 17:56:03 2011
@@ -121,11 +121,6 @@
 else
 DSYMUTIL=true
 endif
-ifdef TargetCommonOpts
-BUGPOINT_TOPTS="-gcc-tool-args $(TargetCommonOpts)"
-else
-BUGPOINT_TOPTS=""
-endif
 
 ifneq ($(OCAMLOPT),)
 CC_FOR_OCAMLOPT := $(shell $(OCAMLOPT) -config | grep native_c_compiler | sed -e 's/native_c_compiler: //')



From anton at korobeynikov.info  Wed Nov 16 18:08:03 2011
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Thu, 17 Nov 2011 04:08:03 +0400
Subject: [llvm-commits] [LLVMdev] [PATCH] BasicBlock Autovectorization
	Pass
In-Reply-To: <1321486739.19359.1067.camel@sapling>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
	<1319919418.23036.881.camel@sapling>
	<1319928991.23036.957.camel@sapling>
	<1320108633.23036.1266.camel@sapling>
	<1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es>
	<1320184739.23036.1334.camel@sapling>
	<1320191694.23036.1497.camel@sapling>
	<1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es>
	<1320762963.19359.117.camel@sapling> <4EB98207.2070807@grosser.es>
	<1320791390.19359.262.camel@sapling> <4EBC4B0F.6010609@grosser.es>
	<1321050998.19359.539.camel@sapling> <4EBDA7F9.9080709@grosser.es>
	<1321053083.19359.550.camel@sapling> <4EBDB1BF.7090006@grosser.es>
	<1321400339.19359.782.camel@sapling>
	<1321486739.19359.1067.camel@sapling>
Message-ID: <CA+Ov9+=CZEpKMu0ZbmzjLfqi0emGbDd3UYE5bQvN2VfwXD9_6g@mail.gmail.com>

Hello Hal,

> MultiSource/Applications/ClamAV - fails to compile shared_sha256.c with
> an error: error in backend: Cannot select: 0x4fbcb40: v2i64 =
> X86ISD::MOVLPD 0x4149e00, 0x418d930 [ID=596]
Please report this as a PR regardless of the pass. Bugs in the backend
should be fixed.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

From daniel at zuster.org  Wed Nov 16 18:12:10 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 17 Nov 2011 00:12:10 -0000
Subject: [llvm-commits] [compiler-rt] r144865 - in /compiler-rt/trunk/lib:
 Makefile.mk profile/ profile/GCDAProfiling.c profile/Makefile.mk
Message-ID: <20111117001210.998431BE001@llvm.org>

Author: ddunbar
Date: Wed Nov 16 18:12:10 2011
New Revision: 144865

URL: http://llvm.org/viewvc/llvm-project?rev=144865&view=rev
Log:
lib: Import GCDA profiling support from LLVM.
 - I'm in the process of moving this here but it will live in both places until
   the ancilliary support is ready.
 - Currently unused.

Added:
    compiler-rt/trunk/lib/profile/
    compiler-rt/trunk/lib/profile/GCDAProfiling.c
    compiler-rt/trunk/lib/profile/Makefile.mk
      - copied, changed from r144845, compiler-rt/trunk/lib/Makefile.mk
Modified:
    compiler-rt/trunk/lib/Makefile.mk

Modified: compiler-rt/trunk/lib/Makefile.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/Makefile.mk?rev=144865&r1=144864&r2=144865&view=diff
==============================================================================
--- compiler-rt/trunk/lib/Makefile.mk (original)
+++ compiler-rt/trunk/lib/Makefile.mk Wed Nov 16 18:12:10 2011
@@ -7,8 +7,15 @@
 #
 #===------------------------------------------------------------------------===#
 
-SubDirs := i386 ppc x86_64 arm
+SubDirs :=
 
+# Add arch specific optimized implementations.
+SubDirs += i386 ppc x86_64 arm
+
+# Add other submodules.
+SubDirs += profile
+
+# Define the variables for this specific directory.
 Sources := $(foreach file,$(wildcard $(Dir)/*.c),$(notdir $(file)))
 ObjNames := $(Sources:%.c=%.o)
 Implementation := Generic

Added: compiler-rt/trunk/lib/profile/GCDAProfiling.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/profile/GCDAProfiling.c?rev=144865&view=auto
==============================================================================
--- compiler-rt/trunk/lib/profile/GCDAProfiling.c (added)
+++ compiler-rt/trunk/lib/profile/GCDAProfiling.c Wed Nov 16 18:12:10 2011
@@ -0,0 +1,200 @@
+/*===- GCDAProfiling.c - Support library for GCDA file emission -----------===*\
+|*
+|*                     The LLVM Compiler Infrastructure
+|*
+|* This file is distributed under the University of Illinois Open Source
+|* License. See LICENSE.TXT for details.
+|* 
+|*===----------------------------------------------------------------------===*|
+|* 
+|* This file implements the call back routines for the gcov profiling
+|* instrumentation pass. Link against this library when running code through
+|* the -insert-gcov-profiling LLVM pass.
+|*
+|* We emit files in a corrupt version of GCOV's "gcda" file format. These files
+|* are only close enough that LCOV will happily parse them. Anything that lcov
+|* ignores is missing.
+|*
+|* TODO: gcov is multi-process safe by having each exit open the existing file
+|* and append to it. We'd like to achieve that and be thread-safe too.
+|*
+\*===----------------------------------------------------------------------===*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#ifdef _WIN32
+#include <direct.h>
+#endif
+
+#ifndef _MSC_VER
+#include <stdint.h>
+#else
+typedef unsigned int uint32_t;
+typedef unsigned int uint64_t;
+#endif
+
+/* #define DEBUG_GCDAPROFILING */
+
+/*
+ * --- GCOV file format I/O primitives ---
+ */
+
+static FILE *output_file = NULL;
+
+static void write_int32(uint32_t i) {
+  fwrite(&i, 4, 1, output_file);
+}
+
+static void write_int64(uint64_t i) {
+  uint32_t lo, hi;
+  lo = i >>  0;
+  hi = i >> 32;
+
+  write_int32(lo);
+  write_int32(hi);
+}
+
+static uint32_t length_of_string(const char *s) {
+  return (strlen(s) / 4) + 1;
+}
+
+static void write_string(const char *s) {
+  uint32_t len = length_of_string(s);
+  write_int32(len);
+  fwrite(s, strlen(s), 1, output_file);
+  fwrite("\0\0\0\0", 4 - (strlen(s) % 4), 1, output_file);
+}
+
+static char *mangle_filename(const char *orig_filename) {
+  /* TODO: handle GCOV_PREFIX_STRIP */
+  const char *prefix;
+  char *filename = 0;
+
+  prefix = getenv("GCOV_PREFIX");
+
+  if (!prefix)
+    return strdup(orig_filename);
+
+  filename = malloc(strlen(prefix) + 1 + strlen(orig_filename) + 1);
+  strcpy(filename, prefix);
+  strcat(filename, "/");
+  strcat(filename, orig_filename);
+
+  return filename;
+}
+
+static void recursive_mkdir(const char *filename) {
+  char *pathname;
+  int i, e;
+
+  for (i = 1, e = strlen(filename); i != e; ++i) {
+    if (filename[i] == '/') {
+      pathname = malloc(i + 1);
+      strncpy(pathname, filename, i);
+      pathname[i] = '\0';
+#ifdef _WIN32
+      _mkdir(pathname);
+#else
+      mkdir(pathname, 0750);  /* some of these will fail, ignore it. */
+#endif
+      free(pathname);
+    }
+  }
+}
+
+/*
+ * --- LLVM line counter API ---
+ */
+
+/* A file in this case is a translation unit. Each .o file built with line
+ * profiling enabled will emit to a different file. Only one file may be
+ * started at a time.
+ */
+void llvm_gcda_start_file(const char *orig_filename) {
+  char *filename;
+  filename = mangle_filename(orig_filename);
+  recursive_mkdir(filename);
+  output_file = fopen(filename, "wb");
+
+  /* gcda file, version 404*, stamp LLVM. */
+#ifdef __APPLE__
+  fwrite("adcg*204MVLL", 12, 1, output_file);
+#else
+  fwrite("adcg*404MVLL", 12, 1, output_file);
+#endif
+
+#ifdef DEBUG_GCDAPROFILING
+  printf("llvmgcda: [%s]\n", orig_filename);
+#endif
+
+  free(filename);
+}
+
+/* Given an array of pointers to counters (counters), increment the n-th one,
+ * where we're also given a pointer to n (predecessor).
+ */
+void llvm_gcda_increment_indirect_counter(uint32_t *predecessor,
+                                          uint64_t **counters) {
+  uint64_t *counter;
+  uint32_t pred;
+
+  pred = *predecessor;
+  if (pred == 0xffffffff)
+    return;
+  counter = counters[pred];
+
+  /* Don't crash if the pred# is out of sync. This can happen due to threads,
+     or because of a TODO in GCOVProfiling.cpp buildEdgeLookupTable(). */
+  if (counter)
+    ++*counter;
+#ifdef DEBUG_GCDAPROFILING
+  else
+    printf("llvmgcda: increment_indirect_counter counters=%x, pred=%u\n",
+           state_table_row, *predecessor);
+#endif
+}
+
+void llvm_gcda_emit_function(uint32_t ident, const char *function_name) {
+#ifdef DEBUG_GCDAPROFILING
+  printf("llvmgcda: function id=%x\n", ident);
+#endif
+
+  /* function tag */  
+  fwrite("\0\0\0\1", 4, 1, output_file);
+  write_int32(3 + 1 + length_of_string(function_name));
+  write_int32(ident);
+  write_int32(0);
+  write_int32(0);
+  write_string(function_name);
+}
+
+void llvm_gcda_emit_arcs(uint32_t num_counters, uint64_t *counters) {
+  uint32_t i;
+  /* counter #1 (arcs) tag */
+  fwrite("\0\0\xa1\1", 4, 1, output_file);
+  write_int32(num_counters * 2);
+  for (i = 0; i < num_counters; ++i) {
+    write_int64(counters[i]);
+  }
+
+#ifdef DEBUG_GCDAPROFILING
+  printf("llvmgcda:   %u arcs\n", num_counters);
+  for (i = 0; i < num_counters; ++i) {
+    printf("llvmgcda:   %llu\n", (unsigned long long)counters[i]);
+  }
+#endif
+}
+
+void llvm_gcda_end_file() {
+  /* Write out EOF record. */
+  fwrite("\0\0\0\0\0\0\0\0", 8, 1, output_file);
+  fclose(output_file);
+  output_file = NULL;
+
+#ifdef DEBUG_GCDAPROFILING
+  printf("llvmgcda: -----\n");
+#endif
+}

Copied: compiler-rt/trunk/lib/profile/Makefile.mk (from r144845, compiler-rt/trunk/lib/Makefile.mk)
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/profile/Makefile.mk?p2=compiler-rt/trunk/lib/profile/Makefile.mk&p1=compiler-rt/trunk/lib/Makefile.mk&r1=144845&r2=144865&rev=144865&view=diff
==============================================================================
--- compiler-rt/trunk/lib/Makefile.mk (original)
+++ compiler-rt/trunk/lib/profile/Makefile.mk Wed Nov 16 18:12:10 2011
@@ -1,4 +1,4 @@
-#===- lib/Makefile.mk --------------------------------------*- Makefile -*--===#
+#===- lib/profile/Makefile.mk ------------------------------*- Makefile -*--===#
 #
 #                     The LLVM Compiler Infrastructure
 #
@@ -7,7 +7,7 @@
 #
 #===------------------------------------------------------------------------===#
 
-SubDirs := i386 ppc x86_64 arm
+SubDirs :=
 
 Sources := $(foreach file,$(wildcard $(Dir)/*.c),$(notdir $(file)))
 ObjNames := $(Sources:%.c=%.o)



From daniel at zuster.org  Wed Nov 16 18:12:12 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 17 Nov 2011 00:12:12 -0000
Subject: [llvm-commits] [compiler-rt] r144866 -
	/compiler-rt/trunk/make/platform/clang_darwin.mk
Message-ID: <20111117001212.E3FC71BE001@llvm.org>

Author: ddunbar
Date: Wed Nov 16 18:12:12 2011
New Revision: 144866

URL: http://llvm.org/viewvc/llvm-project?rev=144866&view=rev
Log:
platform/clang_darwin: Add configs for profiling support.

Modified:
    compiler-rt/trunk/make/platform/clang_darwin.mk

Modified: compiler-rt/trunk/make/platform/clang_darwin.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=144866&r1=144865&r2=144866&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin.mk (original)
+++ compiler-rt/trunk/make/platform/clang_darwin.mk Wed Nov 16 18:12:12 2011
@@ -54,6 +54,12 @@
 Configs += cc_kext
 UniversalArchs.cc_kext := $(call CheckArches,armv6 armv7 i386 x86_64)
 
+# Configurations which define the profiling support functions.
+Configs += profile_osx
+UniversalArchs.profile_osx := $(call CheckArches,i386 x86_64)
+Configs += profile_ios
+UniversalArchs.profile_ios := $(call CheckArches,i386 x86_64 armv6 armv7)
+
 # If RC_SUPPORTED_ARCHS is defined, treat it as a list of the architectures we
 # are intended to support and limit what we try to build to that.
 #
@@ -100,6 +106,12 @@
 CFLAGS.cc_kext.x86_64	:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
 CFLAGS.cc_kext.armv6	:= $(CFLAGS) $(IOS_DEPLOYMENT_ARGS) -mthumb
 CFLAGS.cc_kext.armv7	:= $(CFLAGS) $(IOS_DEPLOYMENT_ARGS)
+CFLAGS.profile_osx.i386   := $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
+CFLAGS.profile_osx.x86_64 := $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
+CFLAGS.profile_ios.i386   := $(CFLAGS) $(IOSSIM_DEPLOYMENT_ARGS)
+CFLAGS.profile_ios.x86_64 := $(CFLAGS) $(IOSSIM_DEPLOYMENT_ARGS)
+CFLAGS.profile_ios.armv6  := $(CFLAGS) $(IOS_DEPLOYMENT_ARGS)
+CFLAGS.profile_ios.armv7  := $(CFLAGS) $(IOS_DEPLOYMENT_ARGS)
 
 FUNCTIONS.eprintf := eprintf
 FUNCTIONS.10.4 := eprintf floatundidf floatundisf floatundixf
@@ -117,6 +129,9 @@
 
 FUNCTIONS.osx	:= mulosi4 mulodi4 muloti4
 
+FUNCTIONS.profile_osx := GCDAProfiling
+FUNCTIONS.profile_ios := GCDAProfiling
+
 CCKEXT_COMMON_FUNCTIONS := \
 	absvdi2 \
 	absvsi2 \



From eli.friedman at gmail.com  Wed Nov 16 18:21:52 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 17 Nov 2011 00:21:52 -0000
Subject: [llvm-commits] [llvm] r144867 -
	/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
Message-ID: <20111117002152.613641BE001@llvm.org>

Author: efriedma
Date: Wed Nov 16 18:21:52 2011
New Revision: 144867

URL: http://llvm.org/viewvc/llvm-project?rev=144867&view=rev
Log:
Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing.


Modified:
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=144867&r1=144866&r2=144867&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Wed Nov 16 18:21:52 2011
@@ -105,7 +105,7 @@
 static cl::opt<bool>
 UseVZeroUpper("x86-use-vzeroupper",
   cl::desc("Minimize AVX to SSE transition penalty"),
-  cl::init(false));
+  cl::init(true));
 
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration



From eli.friedman at gmail.com  Wed Nov 16 18:48:12 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 16 Nov 2011 16:48:12 -0800
Subject: [llvm-commits] Patch: new backend for Hexagon processor
In-Reply-To: <4EC2F380.7010509@codeaurora.org>
References: <4EC17287.3090708@codeaurora.org>
	<CAJdarcFKL91HwSttsQTcd8FkSaoT7Tz8Jxw1JBmESLo=kjOrpQ@mail.gmail.com>
	<4EC2F380.7010509@codeaurora.org>
Message-ID: <CAJdarcEQwn6oKgp-ZMtg03uR6YpJp=jBUUmAFaTwKTO0dw7p7Q@mail.gmail.com>

On Tue, Nov 15, 2011 at 3:19 PM, Tony Linthicum <tlinth at codeaurora.org> wrote:
> On 11/14/2011 2:54 PM, Eli Friedman wrote:
>
>>
>> --- a/include/llvm/InitializePasses.h
>> +++ b/include/llvm/InitializePasses.h
>> @@ -233,6 +233,7 @@ void initializeVerifierPass(PassRegistry&);
>> ?void initializeVirtRegMapPass(PassRegistry&);
>> ?void initializeInstSimplifierPass(PassRegistry&);
>>
>> +void initializeHexagonHardwareLoopsPass(PassRegistry&);
>> ?}
>>
>> ?#endif
>>
>> This change shouldn't be necessary; only target-independent passes
>> need to be listed here, IIRC.
>>
>
> We are in the process of fixing this and will update with a new patch in a
> day or two.
>
>> Your changes to add Data128bitsDirective etc. seem a bit confused...
>> ".uleb128" is not a 128-bit integer in the sense you're using it.
>
> Sorry about that. ?It's a hack to fix an exception handling issue and we
> didn't intend to send it out. ?I've removed it in the attached patches. ?We
> will submit a proper fix at a later date.
>
>> Also, please separate out the MC changes into a separate patch;
>> they're interesting changes mixed into a bunch of mechanical changes,
>> and it would be nice to have more eyes on them.
>
> Done. ?Please let me know if you'd like any further breakdown of the
> patches.

The split should be fine as-is now.

It would be nice to see some more documentation in
docs/CodeGenerator.html for Hexagon-specific target information; it
looks like there are some interesting target-specific passes, and
other information might be useful.

I don't see any issues with the rest of the patch; I haven't looked at
the lib/Target/Hexagon/* bits in much detail, though.

-Eli


From mcrosier at apple.com  Wed Nov 16 19:16:53 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Thu, 17 Nov 2011 01:16:53 -0000
Subject: [llvm-commits] [llvm] r144872 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20111117011653.6F9ED1BE001@llvm.org>

Author: mcrosier
Date: Wed Nov 16 19:16:53 2011
New Revision: 144872

URL: http://llvm.org/viewvc/llvm-project?rev=144872&view=rev
Log:
Don't unconditionally set the kill flag.
rdar://10456186

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144872&r1=144871&r2=144872&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Nov 16 19:16:53 2011
@@ -1114,7 +1114,7 @@
   // Create the base instruction, then add the operands.
   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                                     TII.get(StrOpc))
-                            .addReg(SrcReg, getKillRegState(true));
+                            .addReg(SrcReg);
   AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
   return true;
 }



From daniel at zuster.org  Wed Nov 16 19:19:54 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 17 Nov 2011 01:19:54 -0000
Subject: [llvm-commits] [llvm] r144873 -
	/llvm/trunk/utils/llvm-build/llvmbuild/main.py
Message-ID: <20111117011954.336721BE001@llvm.org>

Author: ddunbar
Date: Wed Nov 16 19:19:53 2011
New Revision: 144873

URL: http://llvm.org/viewvc/llvm-project?rev=144873&view=rev
Log:
llvm-build: Attempt to work around a CMake Makefile generator bug that doesn't
properly quote strings when writing the CMakeFiles/Makefile.cmake output file
(which lists the dependencies). This shows up when using CMake + MSYS Makefile
generator.

Modified:
    llvm/trunk/utils/llvm-build/llvmbuild/main.py

Modified: llvm/trunk/utils/llvm-build/llvmbuild/main.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm-build/llvmbuild/main.py?rev=144873&r1=144872&r2=144873&view=diff
==============================================================================
--- llvm/trunk/utils/llvm-build/llvmbuild/main.py (original)
+++ llvm/trunk/utils/llvm-build/llvmbuild/main.py Wed Nov 16 19:19:53 2011
@@ -21,6 +21,21 @@
 
     return value
 
+def cmake_quote_path(value):
+    """
+    cmake_quote_path(value) -> str
+
+    Return a quoted form of the given value that is suitable for use in CMake
+    language files.
+    """
+
+    # CMake has a bug in it's Makefile generator that doesn't properly quote
+    # strings it generates. So instead of using proper quoting, we just use "/"
+    # style paths.  Currently, we only handle escaping backslashes.
+    value = value.replace("\\", "/")
+
+    return value
+
 def mk_quote_string_for_target(value):
     """
     mk_quote_string_for_target(target_name) -> str
@@ -430,7 +445,7 @@
             print >>f, """\
 configure_file(\"%s\"
                ${CMAKE_CURRENT_BINARY_DIR}/DummyConfigureOutput)""" % (
-                cmake_quote_string(dep),)
+                cmake_quote_path(dep),)
 
         f.close()
 



From eli.friedman at gmail.com  Wed Nov 16 19:27:36 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 17 Nov 2011 01:27:36 -0000
Subject: [llvm-commits] [llvm] r144876 - in /llvm/trunk:
 include/llvm/Target/TargetLibraryInfo.h
 include/llvm/Transforms/Utils/BuildLibCalls.h
 lib/Target/TargetLibraryInfo.cpp lib/Transforms/Scalar/SimplifyLibCalls.cpp
 lib/Transforms/Utils/BuildLibCalls.cpp
 test/Transforms/SimplifyLibCalls/osx-names.ll
Message-ID: <20111117012737.1719A1BE001@llvm.org>

Author: efriedma
Date: Wed Nov 16 19:27:36 2011
New Revision: 144876

URL: http://llvm.org/viewvc/llvm-project?rev=144876&view=rev
Log:
Add support for custom names for library functions in TargetLibraryInfo.  Add a custom name for fwrite and fputs on x86-32 OSX.  Make SimplifyLibCalls honor the custom
names for fwrite and fputs.

Fixes <rdar://problem/9815881>.


Added:
    llvm/trunk/test/Transforms/SimplifyLibCalls/osx-names.ll
Modified:
    llvm/trunk/include/llvm/Target/TargetLibraryInfo.h
    llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h
    llvm/trunk/lib/Target/TargetLibraryInfo.cpp
    llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
    llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp

Modified: llvm/trunk/include/llvm/Target/TargetLibraryInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLibraryInfo.h?rev=144876&r1=144875&r2=144876&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLibraryInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLibraryInfo.h Wed Nov 16 19:27:36 2011
@@ -11,6 +11,7 @@
 #define LLVM_TARGET_TARGETLIBRARYINFO_H
 
 #include "llvm/Pass.h"
+#include "llvm/ADT/DenseMap.h"
 
 namespace llvm {
   class Triple;
@@ -37,7 +38,14 @@
       
       /// int fiprintf(FILE *stream, const char *format, ...);
       fiprintf,
-      
+
+      // size_t fwrite(const void *ptr, size_t size, size_t nitems,
+      //               FILE *stream);
+      fwrite,
+
+      // int fputs(const char *s, FILE *stream);
+      fputs,
+
       NumLibFuncs
     };
   }
@@ -46,7 +54,23 @@
 /// library functions are available for the current target, and allows a
 /// frontend to disable optimizations through -fno-builtin etc.
 class TargetLibraryInfo : public ImmutablePass {
-  unsigned char AvailableArray[(LibFunc::NumLibFuncs+7)/8];
+  unsigned char AvailableArray[(LibFunc::NumLibFuncs+3)/4];
+  llvm::DenseMap<unsigned, std::string> CustomNames;
+  static const char* StandardNames[LibFunc::NumLibFuncs];
+
+  enum AvailabilityState {
+    StandardName = 3, // (memset to all ones)
+    CustomName = 1,
+    Unavailable = 0  // (memset to all zeros)
+  };
+  void setState(LibFunc::Func F, AvailabilityState State) {
+    AvailableArray[F/4] &= ~(3 << 2*(F&3));
+    AvailableArray[F/4] |= State << 2*(F&3);
+  }
+  AvailabilityState getState(LibFunc::Func F) const {
+    return static_cast<AvailabilityState>((AvailableArray[F/4] >> 2*(F&3)) & 3);
+  }
+
 public:
   static char ID;
   TargetLibraryInfo();
@@ -56,19 +80,39 @@
   /// has - This function is used by optimizations that want to match on or form
   /// a given library function.
   bool has(LibFunc::Func F) const {
-    return (AvailableArray[F/8] & (1 << (F&7))) != 0;
+    return getState(F) != Unavailable;
+  }
+
+  StringRef getName(LibFunc::Func F) const {
+    AvailabilityState State = getState(F);
+    if (State == Unavailable)
+      return StringRef();
+    if (State == StandardName)
+      return StandardNames[F];
+    assert(State == CustomName);
+    return CustomNames.find(F)->second;
   }
 
   /// setUnavailable - this can be used by whatever sets up TargetLibraryInfo to
   /// ban use of specific library functions.
   void setUnavailable(LibFunc::Func F) {
-    AvailableArray[F/8] &= ~(1 << (F&7));
+    setState(F, Unavailable);
   }
 
   void setAvailable(LibFunc::Func F) {
-    AvailableArray[F/8] |= 1 << (F&7);
+    setState(F, StandardName);
   }
-  
+
+  void setAvailableWithName(LibFunc::Func F, StringRef Name) {
+    if (StandardNames[F] != Name) {
+      setState(F, CustomName);
+      CustomNames[F] = Name;
+      assert(CustomNames.find(F) != CustomNames.end());
+    } else {
+      setState(F, StandardName);
+    }
+  }
+
   /// disableAllFunctions - This disables all builtins, which is used for
   /// options like -fno-builtin.
   void disableAllFunctions();

Modified: llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h?rev=144876&r1=144875&r2=144876&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h (original)
+++ llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h Wed Nov 16 19:27:36 2011
@@ -20,6 +20,7 @@
 namespace llvm {
   class Value;
   class TargetData;
+  class TargetLibraryInfo;
   
   /// CastToCStr - Return V if it is an i8*, otherwise cast it to i8*.
   Value *CastToCStr(Value *V, IRBuilder<> &B);
@@ -86,12 +87,13 @@
 
   /// EmitFPutS - Emit a call to the puts function.  Str is required to be a
   /// pointer and File is a pointer to FILE.
-  void EmitFPutS(Value *Str, Value *File, IRBuilder<> &B, const TargetData *TD);
+  void EmitFPutS(Value *Str, Value *File, IRBuilder<> &B, const TargetData *TD,
+                 const TargetLibraryInfo *TLI);
 
   /// EmitFWrite - Emit a call to the fwrite function.  This assumes that Ptr is
   /// a pointer, Size is an 'intptr_t', and File is a pointer to FILE.
   void EmitFWrite(Value *Ptr, Value *Size, Value *File, IRBuilder<> &B,
-                  const TargetData *TD);
+                  const TargetData *TD, const TargetLibraryInfo *TLI);
 
   /// SimplifyFortifiedLibCalls - Helper class for folding checked library
   /// calls (e.g. __strcpy_chk) into their unchecked counterparts.

Modified: llvm/trunk/lib/Target/TargetLibraryInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLibraryInfo.cpp?rev=144876&r1=144875&r2=144876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetLibraryInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetLibraryInfo.cpp Wed Nov 16 19:27:36 2011
@@ -20,6 +20,19 @@
                 "Target Library Information", false, true)
 char TargetLibraryInfo::ID = 0;
 
+const char* TargetLibraryInfo::StandardNames[LibFunc::NumLibFuncs] =
+  {
+    "memset",
+    "memcpy",
+    "memmove",
+    "memset_pattern16",
+    "iprintf",
+    "siprintf",
+    "fiprintf",
+    "fwrite",
+    "fputs"
+  };
+
 /// initialize - Initialize the set of available library functions based on the
 /// specified target triple.  This should be carefully written so that a missing
 /// target triple gets a sane set of defaults.
@@ -38,6 +51,17 @@
     TLI.setUnavailable(LibFunc::memset_pattern16);
   }
 
+  if (T.isMacOSX() && T.getArch() == Triple::x86 &&
+      !T.isMacOSXVersionLT(10, 7)) {
+    // x86-32 OSX has a scheme where fwrite and fputs (and some other functions
+    // we don't care about) have two versions; on recent OSX, the one we want
+    // has a $UNIX2003 suffix. The two implementations are identical except
+    // for the return value in some edge cases.  However, we don't want to
+    // generate code that depends on the old symbols.
+    TLI.setAvailableWithName(LibFunc::fwrite, "fwrite$UNIX2003");
+    TLI.setAvailableWithName(LibFunc::fputs, "fputs$UNIX2003");
+  }
+
   // iprintf and friends are only available on XCore and TCE.
   if (T.getArch() != Triple::xcore && T.getArch() != Triple::tce) {
     TLI.setUnavailable(LibFunc::iprintf);
@@ -64,6 +88,7 @@
 TargetLibraryInfo::TargetLibraryInfo(const TargetLibraryInfo &TLI)
   : ImmutablePass(ID) {
   memcpy(AvailableArray, TLI.AvailableArray, sizeof(AvailableArray));
+  CustomNames = TLI.CustomNames;
 }
 
 

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=144876&r1=144875&r2=144876&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Wed Nov 16 19:27:36 2011
@@ -1323,7 +1323,7 @@
     if (!Len) return 0;
     EmitFWrite(CI->getArgOperand(0),
                ConstantInt::get(TD->getIntPtrType(*Context), Len-1),
-               CI->getArgOperand(1), B, TD);
+               CI->getArgOperand(1), B, TD, TLI);
     return CI;  // Known to have no uses (see above).
   }
 };
@@ -1351,7 +1351,7 @@
       EmitFWrite(CI->getArgOperand(1),
                  ConstantInt::get(TD->getIntPtrType(*Context),
                                   FormatStr.size()),
-                 CI->getArgOperand(0), B, TD);
+                 CI->getArgOperand(0), B, TD, TLI);
       return ConstantInt::get(CI->getType(), FormatStr.size());
     }
 
@@ -1373,7 +1373,7 @@
       // fprintf(F, "%s", str) --> fputs(str, F)
       if (!CI->getArgOperand(2)->getType()->isPointerTy() || !CI->use_empty())
         return 0;
-      EmitFPutS(CI->getArgOperand(2), CI->getArgOperand(0), B, TD);
+      EmitFPutS(CI->getArgOperand(2), CI->getArgOperand(0), B, TD, TLI);
       return CI;
     }
     return 0;
@@ -1469,6 +1469,7 @@
     SimplifyLibCalls() : FunctionPass(ID), StrCpy(false), StrCpyChk(true) {
       initializeSimplifyLibCallsPass(*PassRegistry::getPassRegistry());
     }
+    void AddOpt(LibFunc::Func F, LibCallOptimization* Opt);
     void InitOptimizations();
     bool runOnFunction(Function &F);
 
@@ -1499,6 +1500,11 @@
   return new SimplifyLibCalls();
 }
 
+void SimplifyLibCalls::AddOpt(LibFunc::Func F, LibCallOptimization* Opt) {
+  if (TLI->has(F))
+    Optimizations[TLI->getName(F)] = Opt;
+}
+
 /// Optimizations - Populate the Optimizations map with all the optimizations
 /// we know.
 void SimplifyLibCalls::InitOptimizations() {
@@ -1524,9 +1530,9 @@
   Optimizations["strcspn"] = &StrCSpn;
   Optimizations["strstr"] = &StrStr;
   Optimizations["memcmp"] = &MemCmp;
-  if (TLI->has(LibFunc::memcpy)) Optimizations["memcpy"] = &MemCpy;
+  AddOpt(LibFunc::memcpy, &MemCpy);
   Optimizations["memmove"] = &MemMove;
-  if (TLI->has(LibFunc::memset)) Optimizations["memset"] = &MemSet;
+  AddOpt(LibFunc::memset, &MemSet);
 
   // _chk variants of String and Memory LibCall Optimizations.
   Optimizations["__strcpy_chk"] = &StrCpyChk;
@@ -1579,8 +1585,8 @@
   // Formatting and IO Optimizations
   Optimizations["sprintf"] = &SPrintF;
   Optimizations["printf"] = &PrintF;
-  Optimizations["fwrite"] = &FWrite;
-  Optimizations["fputs"] = &FPuts;
+  AddOpt(LibFunc::fwrite, &FWrite);
+  AddOpt(LibFunc::fputs, &FPuts);
   Optimizations["fprintf"] = &FPrintF;
   Optimizations["puts"] = &Puts;
 }

Modified: llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp?rev=144876&r1=144875&r2=144876&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp Wed Nov 16 19:27:36 2011
@@ -20,6 +20,9 @@
 #include "llvm/Module.h"
 #include "llvm/Support/IRBuilder.h"
 #include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetLibraryInfo.h"
+#include "llvm/LLVMContext.h"
+#include "llvm/Intrinsics.h"
 #include "llvm/ADT/SmallString.h"
 
 using namespace llvm;
@@ -297,20 +300,21 @@
 /// EmitFPutS - Emit a call to the puts function.  Str is required to be a
 /// pointer and File is a pointer to FILE.
 void llvm::EmitFPutS(Value *Str, Value *File, IRBuilder<> &B,
-                     const TargetData *TD) {
+                     const TargetData *TD, const TargetLibraryInfo *TLI) {
   Module *M = B.GetInsertBlock()->getParent()->getParent();
   AttributeWithIndex AWI[3];
   AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
   AWI[1] = AttributeWithIndex::get(2, Attribute::NoCapture);
   AWI[2] = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
+  StringRef FPutsName = TLI->getName(LibFunc::fputs);
   Constant *F;
   if (File->getType()->isPointerTy())
-    F = M->getOrInsertFunction("fputs", AttrListPtr::get(AWI, 3),
+    F = M->getOrInsertFunction(FPutsName, AttrListPtr::get(AWI, 3),
                                B.getInt32Ty(),
                                B.getInt8PtrTy(),
                                File->getType(), NULL);
   else
-    F = M->getOrInsertFunction("fputs", B.getInt32Ty(),
+    F = M->getOrInsertFunction(FPutsName, B.getInt32Ty(),
                                B.getInt8PtrTy(),
                                File->getType(), NULL);
   CallInst *CI = B.CreateCall2(F, CastToCStr(Str, B), File, "fputs");
@@ -322,23 +326,25 @@
 /// EmitFWrite - Emit a call to the fwrite function.  This assumes that Ptr is
 /// a pointer, Size is an 'intptr_t', and File is a pointer to FILE.
 void llvm::EmitFWrite(Value *Ptr, Value *Size, Value *File,
-                      IRBuilder<> &B, const TargetData *TD) {
+                      IRBuilder<> &B, const TargetData *TD,
+                      const TargetLibraryInfo *TLI) {
   Module *M = B.GetInsertBlock()->getParent()->getParent();
   AttributeWithIndex AWI[3];
   AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
   AWI[1] = AttributeWithIndex::get(4, Attribute::NoCapture);
   AWI[2] = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
   LLVMContext &Context = B.GetInsertBlock()->getContext();
+  StringRef FWriteName = TLI->getName(LibFunc::fwrite);
   Constant *F;
   if (File->getType()->isPointerTy())
-    F = M->getOrInsertFunction("fwrite", AttrListPtr::get(AWI, 3),
+    F = M->getOrInsertFunction(FWriteName, AttrListPtr::get(AWI, 3),
                                TD->getIntPtrType(Context),
                                B.getInt8PtrTy(),
                                TD->getIntPtrType(Context),
                                TD->getIntPtrType(Context),
                                File->getType(), NULL);
   else
-    F = M->getOrInsertFunction("fwrite", TD->getIntPtrType(Context),
+    F = M->getOrInsertFunction(FWriteName, TD->getIntPtrType(Context),
                                B.getInt8PtrTy(),
                                TD->getIntPtrType(Context),
                                TD->getIntPtrType(Context),

Added: llvm/trunk/test/Transforms/SimplifyLibCalls/osx-names.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/osx-names.ll?rev=144876&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyLibCalls/osx-names.ll (added)
+++ llvm/trunk/test/Transforms/SimplifyLibCalls/osx-names.ll Wed Nov 16 19:27:36 2011
@@ -0,0 +1,30 @@
+; RUN: opt < %s -simplify-libcalls -S | FileCheck %s
+; <rdar://problem/9815881>
+; On OSX x86-32, fwrite and fputs aren't called fwrite and fputs.
+; Make sure we use the correct names.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
+target triple = "i386-apple-macosx10.7.2"
+
+%struct.__sFILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+%struct.__sbuf = type { i8*, i32 }
+%struct.__sFILEX = type opaque
+
+ at .str = private unnamed_addr constant [13 x i8] c"Hello world\0A\00", align 1
+ at .str2 = private unnamed_addr constant [3 x i8] c"%s\00", align 1
+
+define void @test1(%struct.__sFILE* %stream) nounwind {
+; CHECK: define void @test1
+; CHECK: call i32 @"fwrite$UNIX2003"
+  %call = tail call i32 (%struct.__sFILE*, i8*, ...)* @fprintf(%struct.__sFILE* %stream, i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) nounwind
+  ret void
+}
+
+define void @test2(%struct.__sFILE* %stream, i8* %str) nounwind ssp {
+; CHECK: define void @test2
+; CHECK: call i32 @"fputs$UNIX2003"
+  %call = tail call i32 (%struct.__sFILE*, i8*, ...)* @fprintf(%struct.__sFILE* %stream, i8* getelementptr inbounds ([3 x i8]* @.str2, i32 0, i32 0), i8* %str) nounwind
+  ret void
+}
+
+declare i32 @fprintf(%struct.__sFILE*, i8*, ...) nounwind



From sabre at nondot.org  Wed Nov 16 19:42:23 2011
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 17 Nov 2011 01:42:23 -0000
Subject: [llvm-commits] [llvm] r144878 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20111117014223.67AF91BE001@llvm.org>

Author: lattner
Date: Wed Nov 16 19:42:23 2011
New Revision: 144878

URL: http://llvm.org/viewvc/llvm-project?rev=144878&view=rev
Log:
x86/windows issues fixed.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=144878&r1=144877&r2=144878&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Wed Nov 16 19:42:23 2011
@@ -1268,24 +1268,9 @@
 <div>
 
 <ul>
-
-  <li>The X86-64 backend does not yet support the LLVM IR instruction
-      <tt>va_arg</tt>. Currently, front-ends support variadic argument
-      constructs on X86-64 by lowering them manually.</li>
-
-  <li>Windows x64 (aka Win64) code generator has a few issues.
-    <ul>
-      <li>On mingw-w64, you will see unresolved symbol <tt>__chkstk</tt> due
-          to <a href="http://llvm.org/bugs/show_bug.cgi?id=8919">Bug 8919</a>.
-          It is fixed
-          in <a href="http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110321/118499.html">r128206</a>.</li>
-
-      <li>Miss-aligned MOVDQA might crash your program. It is due to
-          <a href="http://llvm.org/bugs/show_bug.cgi?id=9483">Bug 9483</a>, lack
-          of handling aligned internal globals.</li>
-      </ul>
-  </li>
-
+  <li>The X86-64 backend <a href="http://llvm.org/PR1740">does not yet support
+      the <tt>va_arg</tt> LLVM IR instruction</a>. Currently, front-ends support
+      variadic argument constructs on X86-64 by lowering them manually.</li>
 </ul>
 
 </div>



From hfinkel at anl.gov  Wed Nov 16 21:09:18 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Wed, 16 Nov 2011 21:09:18 -0600
Subject: [llvm-commits] [LLVMdev] [PATCH] BasicBlock Autovectorization
 Pass
In-Reply-To: <CA+Ov9+=CZEpKMu0ZbmzjLfqi0emGbDd3UYE5bQvN2VfwXD9_6g@mail.gmail.com>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
	<1319919418.23036.881.camel@sapling>
	<1319928991.23036.957.camel@sapling>
	<1320108633.23036.1266.camel@sapling>
	<1320172356.23036.1298.camel@sapling>
	<4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling>
	<1320191694.23036.1497.camel@sapling>
	<1320749109.19359.76.camel@sapling>
	<4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling>
	<4EB98207.2070807@grosser.es> <1320791390.19359.262.camel@sapling>
	<4EBC4B0F.6010609@grosser.es> <1321050998.19359.539.camel@sapling>
	<4EBDA7F9.9080709@grosser.es> <1321053083.19359.550.camel@sapling>
	<4EBDB1BF.7090006@grosser.es> <1321400339.19359.782.camel@sapling>
	<1321486739.19359.1067.camel@sapling>
	<CA+Ov9+=CZEpKMu0ZbmzjLfqi0emGbDd3UYE5bQvN2VfwXD9_6g@mail.gmail.com>
Message-ID: <1321499358.19359.1083.camel@sapling>

On Thu, 2011-11-17 at 04:08 +0400, Anton Korobeynikov wrote:
> Hello Hal,
> 
> > MultiSource/Applications/ClamAV - fails to compile shared_sha256.c with
> > an error: error in backend: Cannot select: 0x4fbcb40: v2i64 =
> > X86ISD::MOVLPD 0x4149e00, 0x418d930 [ID=596]
> Please report this as a PR regardless of the pass. Bugs in the backend
> should be fixed.

Certainly will do; x86_64 seems to have a few of these, and 32-bit looks
like it may have more. I'll extract the .ll files and start opening PRs
shortly.

 -Hal

> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From craig.topper at gmail.com  Thu Nov 17 01:04:00 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Thu, 17 Nov 2011 07:04:00 -0000
Subject: [llvm-commits] [llvm] r144885 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20111117070400.8DB481BE001@llvm.org>

Author: ctopper
Date: Thu Nov 17 01:04:00 2011
New Revision: 144885

URL: http://llvm.org/viewvc/llvm-project?rev=144885&view=rev
Log:
Remove seemingly unnecessary duplicate VROUND definitions.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144885&r1=144884&r2=144885&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Nov 17 01:04:00 2011
@@ -6014,13 +6014,13 @@
                     OpSize;
 
   // Vector intrinsic operation, mem
-  def PSm : Ii8<opcps, MRMSrcMem,
+  def PSm : SS4AIi8<opcps, MRMSrcMem,
                     (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
                     !strconcat(OpcodeStr,
                     "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
                     [(set RC:$dst,
                           (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
-                    TA, OpSize, Requires<[HasSSE41]>;
+                    OpSize;
 } // ExeDomain = SSEPackedSingle
 
 let ExeDomain = SSEPackedDouble in {
@@ -6043,42 +6043,6 @@
 } // ExeDomain = SSEPackedDouble
 }
 
-multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
-                   RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
-let ExeDomain = SSEPackedSingle in {
-  // Intrinsic operation, reg.
-  // Vector intrinsic operation, reg
-  def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
-                    (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
-                    !strconcat(OpcodeStr,
-                    "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                    []>, OpSize;
-
-  // Vector intrinsic operation, mem
-  def PSm_AVX : Ii8<opcps, MRMSrcMem,
-                    (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
-                    !strconcat(OpcodeStr,
-                    "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                    []>, TA, OpSize, Requires<[HasSSE41]>;
-} // ExeDomain = SSEPackedSingle
-
-let ExeDomain = SSEPackedDouble in {
-  // Vector intrinsic operation, reg
-  def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
-                    (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
-                    !strconcat(OpcodeStr,
-                    "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                    []>, OpSize;
-
-  // Vector intrinsic operation, mem
-  def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
-                    (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
-                    !strconcat(OpcodeStr,
-                    "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-                    []>, OpSize;
-} // ExeDomain = SSEPackedDouble
-}
-
 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
                             string OpcodeStr,
                             Intrinsic F32Int,
@@ -6132,39 +6096,6 @@
 } // ExeDomain = GenericDomain
 }
 
-multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
-                                   string OpcodeStr> {
-let ExeDomain = GenericDomain in {
-  // Intrinsic operation, reg.
-  def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
-        (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
-        !strconcat(OpcodeStr,
-                "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
-        []>, OpSize;
-
-  // Intrinsic operation, mem.
-  def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
-        (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
-        !strconcat(OpcodeStr,
-                "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
-        []>, OpSize;
-
-  // Intrinsic operation, reg.
-  def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
-        (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
-            !strconcat(OpcodeStr,
-                "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
-        []>, OpSize;
-
-  // Intrinsic operation, mem.
-  def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
-        (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
-            !strconcat(OpcodeStr,
-                "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
-        []>, OpSize;
-} // ExeDomain = GenericDomain
-}
-
 // FP round - roundss, roundps, roundsd, roundpd
 let Predicates = [HasAVX] in {
   // Intrinsic form
@@ -6179,13 +6110,6 @@
   defm VROUND  : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
                                   int_x86_sse41_round_ss,
                                   int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
-
-  // Instructions for the assembler
-  defm VROUND  : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
-                                        VEX;
-  defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
-                                        VEX;
-  defm VROUND  : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V, VEX_LIG;
 }
 
 defm ROUND  : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
@@ -6223,11 +6147,11 @@
 
 let Defs = [EFLAGS] in {
 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
-              "ptest \t{$src2, $src1|$src1, $src2}",
+              "ptest\t{$src2, $src1|$src1, $src2}",
               [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
               OpSize;
 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
-              "ptest \t{$src2, $src1|$src1, $src2}",
+              "ptest\t{$src2, $src1|$src1, $src2}",
               [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
               OpSize;
 }



From mcrosier at apple.com  Thu Nov 17 01:15:58 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Thu, 17 Nov 2011 07:15:58 -0000
Subject: [llvm-commits] [llvm] r144886 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/FastISel.cpp
 test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
Message-ID: <20111117071558.D88371BE001@llvm.org>

Author: mcrosier
Date: Thu Nov 17 01:15:58 2011
New Revision: 144886

URL: http://llvm.org/viewvc/llvm-project?rev=144886&view=rev
Log:
When fast iseling a GEP, accumulate the offset rather than emitting a series of
ADDs.  MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs
being: (1) If we can't materialize the large constant then we'll cause fast-isel
to bail. (2) Too large of an offset can't be directly encoded in the ADD
resulting in a MOV+ADD.  Generally not a bad thing because otherwise we would
have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix
for that. (3) Conversely, too low of a threshold we'll miss opportunities to 
coalesce ADDs.
rdar://10412592


Added:
    llvm/trunk/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=144886&r1=144885&r2=144886&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Nov 17 01:15:58 2011
@@ -437,6 +437,11 @@
 
   bool NIsKill = hasTrivialKill(I->getOperand(0));
 
+  // Keep a running tab of the total offset to coalesce multiple N = N + Offset
+  // into a single N = N + TotalOffset.
+  uint64_t TotalOffs = 0;
+  // FIXME: What's a good SWAG number for MaxOffs?
+  uint64_t MaxOffs = 2048;
   Type *Ty = I->getOperand(0)->getType();
   MVT VT = TLI.getPointerTy();
   for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1,
@@ -446,14 +451,15 @@
       unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
       if (Field) {
         // N = N + Offset
-        uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
-        // FIXME: This can be optimized by combining the add with a
-        // subsequent one.
-        N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT);
-        if (N == 0)
-          // Unhandled operand. Halt "fast" selection and bail.
-          return false;
-        NIsKill = true;
+        TotalOffs += TD.getStructLayout(StTy)->getElementOffset(Field);
+        if (TotalOffs >= MaxOffs) {
+          N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
+          if (N == 0)
+            // Unhandled operand. Halt "fast" selection and bail.
+            return false;
+          NIsKill = true;
+          TotalOffs = 0;
+        }
       }
       Ty = StTy->getElementType(Field);
     } else {
@@ -462,14 +468,26 @@
       // If this is a constant subscript, handle it quickly.
       if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
         if (CI->isZero()) continue;
-        uint64_t Offs =
+        // N = N + Offset
+        TotalOffs += 
           TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
-        N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT);
+        if (TotalOffs >= MaxOffs) {
+          N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
+          if (N == 0)
+            // Unhandled operand. Halt "fast" selection and bail.
+            return false;
+          NIsKill = true;
+          TotalOffs = 0;
+        }
+        continue;
+      }
+      if (TotalOffs) {
+        N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
         if (N == 0)
           // Unhandled operand. Halt "fast" selection and bail.
           return false;
         NIsKill = true;
-        continue;
+        TotalOffs = 0;
       }
 
       // N = N + Idx * ElementSize;
@@ -494,6 +512,12 @@
         return false;
     }
   }
+  if (TotalOffs) {
+    N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
+    if (N == 0)
+      // Unhandled operand. Halt "fast" selection and bail.
+      return false;
+  }
 
   // We successfully emitted code for the given LLVM Instruction.
   UpdateValueMap(I, N);

Added: llvm/trunk/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll?rev=144886&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll Thu Nov 17 01:15:58 2011
@@ -0,0 +1,65 @@
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
+
+%struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
+%struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] }
+
+ at arr = common global [2 x [2 x [2 x [2 x [2 x i32]]]]] zeroinitializer, align 4
+ at A = common global [3 x [3 x %struct.A]] zeroinitializer, align 4
+ at B = common global [2 x [2 x [2 x %struct.B]]] zeroinitializer, align 4
+
+define i32* @t1() nounwind {
+entry:
+; ARM: t1
+; THUMB: t1
+  %addr = alloca i32*, align 4
+  store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4
+; ARM: add r0, r0, #124
+; THUMB: adds r0, #124
+  %0 = load i32** %addr, align 4
+  ret i32* %0
+}
+
+define i32* @t2() nounwind {
+entry:
+; ARM: t2
+; THUMB: t2
+  %addr = alloca i32*, align 4
+  store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
+; ARM: movw r1, #1148
+; ARM: add r0, r0, r1
+; THUMB: addw r0, r0, #1148
+  %0 = load i32** %addr, align 4
+  ret i32* %0
+}
+
+define i32* @t3() nounwind {
+entry:
+; ARM: t3
+; THUMB: t3
+  %addr = alloca i32*, align 4
+  store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4
+; ARM: add r0, r0, #140
+; THUMB: adds r0, #140
+  %0 = load i32** %addr, align 4
+  ret i32* %0
+}
+
+define i32* @t4() nounwind {
+entry:
+; ARM: t4
+; THUMB: t4
+  %addr = alloca i32*, align 4
+  store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4
+; ARM-NOT: movw r{{[0-9]}}, #1060
+; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #4
+; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #132
+; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #24
+; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #36
+; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #24
+; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #4
+; ARM: movw r{{[0-9]}}, #1284
+; THUMB: addw r{{[0-9]}}, r{{[0-9]}}, #1284
+  %0 = load i32** %addr, align 4
+  ret i32* %0
+}



From mcrosier at apple.com  Thu Nov 17 01:24:50 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Thu, 17 Nov 2011 07:24:50 -0000
Subject: [llvm-commits] [llvm] r144888 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20111117072450.29DA31BE001@llvm.org>

Author: mcrosier
Date: Thu Nov 17 01:24:49 2011
New Revision: 144888

URL: http://llvm.org/viewvc/llvm-project?rev=144888&view=rev
Log:
Dead code.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144888&r1=144887&r2=144888&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Nov 17 01:24:49 2011
@@ -196,8 +196,6 @@
 
     // Call handling routines.
   private:
-    bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
-                        unsigned &ResultReg);
     CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
     bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
                          SmallVectorImpl<unsigned> &ArgRegs,
@@ -1700,18 +1698,6 @@
 
 // Call Handling Code
 
-bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
-                                 EVT SrcVT, unsigned &ResultReg) {
-  unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
-                           Src, /*TODO: Kill=*/false);
-
-  if (RR != 0) {
-    ResultReg = RR;
-    return true;
-  } else
-    return false;
-}
-
 // This is largely taken directly from CCAssignFnForNode - we don't support
 // varargs in FastISel so that part has been removed.
 // TODO: We may not support all of this.



From tonic at nondot.org  Thu Nov 17 01:29:06 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Thu, 17 Nov 2011 07:29:06 -0000
Subject: [llvm-commits] [compiler-rt] r144890 -
	/compiler-rt/tags/RELEASE_30/rc4/
Message-ID: <20111117072906.1C15C1BE001@llvm.org>

Author: tbrethou
Date: Thu Nov 17 01:29:05 2011
New Revision: 144890

URL: http://llvm.org/viewvc/llvm-project?rev=144890&view=rev
Log:
Creating release candidate 4 from release_30 branch

Added:
    compiler-rt/tags/RELEASE_30/rc4/
      - copied from r144889, compiler-rt/branches/release_30/


From tonic at nondot.org  Thu Nov 17 01:32:10 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Thu, 17 Nov 2011 07:32:10 -0000
Subject: [llvm-commits] [test-suite] r144893 -
	/test-suite/tags/RELEASE_30/rc4/
Message-ID: <20111117073211.004FE1BE001@llvm.org>

Author: tbrethou
Date: Thu Nov 17 01:32:10 2011
New Revision: 144893

URL: http://llvm.org/viewvc/llvm-project?rev=144893&view=rev
Log:
Creating release candidate 4 from release_30 branch

Added:
    test-suite/tags/RELEASE_30/rc4/   (props changed)
      - copied from r144892, test-suite/branches/release_30/

Propchange: test-suite/tags/RELEASE_30/rc4/
------------------------------------------------------------------------------
--- svn:ignore (added)
+++ svn:ignore Thu Nov 17 01:32:10 2011
@@ -0,0 +1,4 @@
+Makefile.config
+config.log
+config.status
+mklib

Propchange: test-suite/tags/RELEASE_30/rc4/
------------------------------------------------------------------------------
    svn:mergeinfo = /test-suite/trunk:142659,143460



From craig.topper at gmail.com  Thu Nov 17 01:49:38 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Thu, 17 Nov 2011 07:49:38 -0000
Subject: [llvm-commits] [llvm] r144896 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20111117074938.BB6DD1BE001@llvm.org>

Author: ctopper
Date: Thu Nov 17 01:49:38 2011
New Revision: 144896

URL: http://llvm.org/viewvc/llvm-project?rev=144896&view=rev
Log:
Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144896&r1=144895&r2=144896&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Nov 17 01:49:38 2011
@@ -3891,28 +3891,34 @@
 
   def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
             (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
+                    (bc_v16i8 (memopv2i64 addr:$src2)))),
             (VPCMPEQBrm VR128:$src1, addr:$src2)>;
   def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
             (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
+                    (bc_v8i16 (memopv2i64 addr:$src2)))),
             (VPCMPEQWrm VR128:$src1, addr:$src2)>;
   def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
             (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
+                    (bc_v4i32 (memopv2i64 addr:$src2)))),
             (VPCMPEQDrm VR128:$src1, addr:$src2)>;
 
   def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
             (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
+                    (bc_v16i8 (memopv2i64 addr:$src2)))),
             (VPCMPGTBrm VR128:$src1, addr:$src2)>;
   def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
             (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
+                    (bc_v8i16 (memopv2i64 addr:$src2)))),
             (VPCMPGTWrm VR128:$src1, addr:$src2)>;
   def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
             (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
+                    (bc_v4i32 (memopv2i64 addr:$src2)))),
             (VPCMPGTDrm VR128:$src1, addr:$src2)>;
 }
 
@@ -3932,28 +3938,34 @@
 
   def : Pat<(v32i8 (X86pcmpeqb VR256:$src1, VR256:$src2)),
             (VPCMPEQBYrr VR256:$src1, VR256:$src2)>;
-  def : Pat<(v32i8 (X86pcmpeqb VR256:$src1, (memop addr:$src2))),
+  def : Pat<(v32i8 (X86pcmpeqb VR256:$src1,
+                    (bc_v32i8 (memopv4i64 addr:$src2)))),
             (VPCMPEQBYrm VR256:$src1, addr:$src2)>;
   def : Pat<(v16i16 (X86pcmpeqw VR256:$src1, VR256:$src2)),
             (VPCMPEQWYrr VR256:$src1, VR256:$src2)>;
-  def : Pat<(v16i16 (X86pcmpeqw VR256:$src1, (memop addr:$src2))),
+  def : Pat<(v16i16 (X86pcmpeqw VR256:$src1,
+                     (bc_v16i16 (memopv4i64 addr:$src2)))),
             (VPCMPEQWYrm VR256:$src1, addr:$src2)>;
   def : Pat<(v8i32 (X86pcmpeqd VR256:$src1, VR256:$src2)),
             (VPCMPEQDYrr VR256:$src1, VR256:$src2)>;
-  def : Pat<(v8i32 (X86pcmpeqd VR256:$src1, (memop addr:$src2))),
+  def : Pat<(v8i32 (X86pcmpeqd VR256:$src1,
+                    (bc_v8i32 (memopv4i64 addr:$src2)))),
             (VPCMPEQDYrm VR256:$src1, addr:$src2)>;
 
   def : Pat<(v32i8 (X86pcmpgtb VR256:$src1, VR256:$src2)),
             (VPCMPGTBYrr VR256:$src1, VR256:$src2)>;
-  def : Pat<(v32i8 (X86pcmpgtb VR256:$src1, (memop addr:$src2))),
+  def : Pat<(v32i8 (X86pcmpgtb VR256:$src1,
+                    (bc_v32i8 (memopv4i64 addr:$src2)))),
             (VPCMPGTBYrm VR256:$src1, addr:$src2)>;
   def : Pat<(v16i16 (X86pcmpgtw VR256:$src1, VR256:$src2)),
             (VPCMPGTWYrr VR256:$src1, VR256:$src2)>;
-  def : Pat<(v16i16 (X86pcmpgtw VR256:$src1, (memop addr:$src2))),
+  def : Pat<(v16i16 (X86pcmpgtw VR256:$src1,
+                     (bc_v16i16 (memopv4i64 addr:$src2)))),
             (VPCMPGTWYrm VR256:$src1, addr:$src2)>;
   def : Pat<(v8i32 (X86pcmpgtd VR256:$src1, VR256:$src2)),
             (VPCMPGTDYrr VR256:$src1, VR256:$src2)>;
-  def : Pat<(v8i32 (X86pcmpgtd VR256:$src1, (memop addr:$src2))),
+  def : Pat<(v8i32 (X86pcmpgtd VR256:$src1,
+                    (bc_v8i32 (memopv4i64 addr:$src2)))),
             (VPCMPGTDYrm VR256:$src1, addr:$src2)>;
 }
 
@@ -3975,28 +3987,34 @@
 let Predicates = [HasSSE2] in {
   def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
             (PCMPEQBrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
+                    (bc_v16i8 (memopv2i64 addr:$src2)))),
             (PCMPEQBrm VR128:$src1, addr:$src2)>;
   def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
             (PCMPEQWrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
+                    (bc_v8i16 (memopv2i64 addr:$src2)))),
             (PCMPEQWrm VR128:$src1, addr:$src2)>;
   def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
             (PCMPEQDrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
+                    (bc_v4i32 (memopv2i64 addr:$src2)))),
             (PCMPEQDrm VR128:$src1, addr:$src2)>;
 
   def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
             (PCMPGTBrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
+             (bc_v16i8 (memopv2i64 addr:$src2)))),
             (PCMPGTBrm VR128:$src1, addr:$src2)>;
   def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
             (PCMPGTWrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
+                    (bc_v8i16 (memopv2i64 addr:$src2)))),
             (PCMPGTWrm VR128:$src1, addr:$src2)>;
   def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
             (PCMPGTDrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
+  def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
+                    (bc_v4i32 (memopv2i64 addr:$src2)))),
             (PCMPGTDrm VR128:$src1, addr:$src2)>;
 }
 
@@ -7754,29 +7772,29 @@
             (VPSRAVDYrr VR256:$src1, VR256:$src2)>;
 
   def : Pat<(v4i32 (shl (v4i32 VR128:$src1),
-                    (v4i32 (bitconvert (memopv2i64 addr:$src2))))),
+                    (bc_v4i32 (memopv2i64 addr:$src2)))),
             (VPSLLVDrm VR128:$src1,  addr:$src2)>;
   def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))),
             (VPSLLVQrm VR128:$src1,  addr:$src2)>;
   def : Pat<(v4i32 (srl (v4i32 VR128:$src1),
-                    (v4i32 (bitconvert (memopv2i64 addr:$src2))))),
+                    (bc_v4i32 (memopv2i64 addr:$src2)))),
             (VPSRLVDrm VR128:$src1,  addr:$src2)>;
   def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))),
             (VPSRLVQrm VR128:$src1,  addr:$src2)>;
   def : Pat<(v4i32 (sra (v4i32 VR128:$src1),
-                    (v4i32 (bitconvert (memopv2i64 addr:$src2))))),
+                    (bc_v4i32 (memopv2i64 addr:$src2)))),
             (VPSRAVDrm VR128:$src1,  addr:$src2)>;
   def : Pat<(v8i32 (shl (v8i32 VR256:$src1),
-                    (v8i32 (bitconvert (memopv4i64 addr:$src2))))),
+                    (bc_v8i32 (memopv4i64 addr:$src2)))),
             (VPSLLVDYrm VR256:$src1, addr:$src2)>;
   def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))),
             (VPSLLVQYrm VR256:$src1, addr:$src2)>;
   def : Pat<(v8i32 (srl (v8i32 VR256:$src1),
-                    (v8i32 (bitconvert (memopv4i64 addr:$src2))))),
+                    (bc_v8i32 (memopv4i64 addr:$src2)))),
             (VPSRLVDYrm VR256:$src1, addr:$src2)>;
   def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))),
             (VPSRLVQYrm VR256:$src1, addr:$src2)>;
   def : Pat<(v8i32 (sra (v8i32 VR256:$src1),
-                    (v8i32 (bitconvert (memopv4i64 addr:$src2))))),
+                    (bc_v8i32 (memopv4i64 addr:$src2)))),
             (VPSRAVDYrm VR256:$src1, addr:$src2)>;
 }



From tobias at grosser.es  Thu Nov 17 06:57:25 2011
From: tobias at grosser.es (Tobias Grosser)
Date: Thu, 17 Nov 2011 13:57:25 +0100
Subject: [llvm-commits] [LLVMdev] [PATCH] BasicBlock Autovectorization
 Pass
In-Reply-To: <1321486739.19359.1067.camel@sapling>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
	<1319919418.23036.881.camel@sapling>
	<1319928991.23036.957.camel@sapling>
	<1320108633.23036.1266.camel@sapling>
	<1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es>
	<1320184739.23036.1334.camel@sapling>
	<1320191694.23036.1497.camel@sapling>
	<1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es>
	<1320762963.19359.117.camel@sapling> <4EB98207.2070807@grosser.es>
	<1320791390.19359.262.camel@sapling> <4EBC4B0F.6010609@grosser.es>
	<1321050998.19359.539.camel@sapling> <4EBDA7F9.9080709@grosser.es>
	<1321053083.19359.550.camel@sapling> <4EBDB1BF.7090006@grosser.es>
	<1321400339.19359.782.camel@sapling>
	<1321486739.19359.1067.camel@sapling>
Message-ID: <4EC504B5.2020408@grosser.es>

On 11/17/2011 12:38 AM, Hal Finkel wrote:
> Tobias, et al.,
>
> Attached is the my autovectorization pass.

Very nice. Will you be at the developer summit? Maybe we could discuss 
the integration there?

Here a first review of the source code.


> diff --git a/docs/Passes.html b/docs/Passes.html
> index 5c42f3f..076effa 100644
> --- a/docs/Passes.html
> +++ b/docs/Passes.html
> @@ -126,6 +126,7 @@ perl -e '$/ = undef; for (split(/\n/,<>)) { s:^ *///? ?::; print "<p>\n" if !
>   <tr><td><a href="#adce">-adce</a></td><td>Aggressive Dead Code Elimination</td></tr>
>   <tr><td><a href="#always-inline">-always-inline</a></td><td>Inliner for always_inline functions</td></tr>
>   <tr><td><a href="#argpromotion">-argpromotion</a></td><td>Promote 'by reference' arguments to scalars</td></tr>
> +<tr><td><a href="#bb-vectorize">-bb-vectorize</a></td><td>Combine instructions to vectorize within basic blocks</td></tr>

Maybe 'Combine instructions to vector instructions within basic blocks'

> diff --git a/include/llvm-c/Transforms/Vectorize.h b/include/llvm-c/Transforms/Vectorize.h
> new file mode 100644
> index 0000000..497518a
> --- /dev/null
> +++ b/include/llvm-c/Transforms/Vectorize.h
> @@ -0,0 +1,36 @@
> +/*===---------------------------Vectorize.h ------------------- -*- C++ -*-===*\
> +|*===----------- Vectorization Transformation Library C Interface ---------===*|
> +|*                                                                            *|
> +|*                     The LLVM Compiler Infrastructure                       *|
> +|*                                                                            *|
> +|* This file is distributed under the University of Illinois Open Source      *|
> +|* License. See LICENSE.TXT for details.                                      *|
> +|*                                                                            *|
> +|*===----------------------------------------------------------------------===*|
> +|*                                                                            *|
> +|* This header declares the C interface to libLLVMScalarOpts.a, which         *|
> +|* implements various scalar transformations of the LLVM IR.                  *|
> +|*                                                                            *|
> +|* Many exotic languages can interoperate with C code but have a harder time  *|
> +|* with C++ due to name mangling. So in addition to C, this interface enables *|
> +|* tools written in such languages.                                           *|
> +|*                                                                            *|
> +\*===----------------------------------------------------------------------===*/

This comment does not match the content of the file.

>
> +static cl::opt<bool>
> +RunVectorization("vectorize", cl::desc("Run vectorization passes"));
> +
>   PassManagerBuilder::PassManagerBuilder() {
>       OptLevel = 2;
>       SizeLevel = 0;
> @@ -38,6 +43,7 @@ PassManagerBuilder::PassManagerBuilder() {
>       DisableSimplifyLibCalls = false;
>       DisableUnitAtATime = false;
>       DisableUnrollLoops = false;
> +    Vectorize = RunVectorization;

Integrating vectorization like this seems to work for now. However, it 
does not seem to be 100% clean. I wonder if we could follow the other 
flags here and set Vectorize = false in the constructor and add the 
flags which enable this to the tools that use the PassManagerBuilder. 
You may even had this or something similar before, because I remember 
for your earlier patches -mllvm did not work for you in clang. If we 
require the tools to explicitly set Vectorizer, we would neeed to add a 
clang specific flag that could drive the vectorizer. I am not sure if we 
want to do this at this stage or even at all.

For now I would keep it like this. I don't have a better solution, but 
wanted to write down my thoughts.


>   }
>
>   PassManagerBuilder::~PassManagerBuilder() {
> @@ -170,6 +176,14 @@ void PassManagerBuilder::populateModulePassManager(PassManagerBase&MPM) {
>
>     addExtensionsToPM(EP_ScalarOptimizerLate, MPM);
>
> +  if (Vectorize) {
> +    MPM.add(createBBVectorizePass());
> +    if (OptLevel>  1) {
> +      MPM.add(createInstructionCombiningPass());
> +      MPM.add(createGVNPass());                 // Remove redundancies
> +    }
> +  }
> +

What is the reason you will not enable this at -O1. LLVM runs even at 
-O1 a number of instcombine and GVN passes. I don't see a strong reason 
why we would not want to do this after vectorization (In case it is 
known to be useful in general).


> +++ b/lib/Transforms/Vectorize/BBVectorize.cpp
> @@ -0,0 +1,1338 @@

> +    typedef std::pair<Value *, Value *>  value_pair;
> +    typedef std::pair<value_pair, value_pair>  vp_pair;
> +    typedef std::pair<std::multimap<Value *, Value *>::iterator,
> +              std::multimap<Value *, Value *>::iterator>  vp_iterator_pair;
> +    typedef std::pair<std::multimap<value_pair, value_pair>::iterator,
> +              std::multimap<value_pair, value_pair>::iterator>
> +                vpp_iterator_pair;

http://llvm.org/docs/CodingStandards.html#ll_naming

"Type names (including classes, structs, enums, typedefs, etc) should be 
nouns and start with an upper-case letter (e.g. TextFileReader)."


> +    void getCandPairs(unsigned vBits, BasicBlock&BB,
> +                       std::multimap<Value *, Value *>  &candPairs,
> +                       std::vector<Value *>  &pairableInsts);

"Variable names should be nouns (as they represent state). The name 
should be camel case, and start with an upper case letter (e.g. Leader 
or Boats)."

This happens at several places. Can you check your code for this.

> +    void replValues(BasicBlock&BB,
> +                     std::vector<Value *>  &pairableInsts,
> +                     DenseMap<Value *, Value *>&  chosenPairs);
'repl' is no obvious abbreviation for me. Can you use the full word or 
equivalent shorter one?

> +
> +    virtual bool runOnBasicBlock(BasicBlock&BB) {
> +      // const TargetData *TD = getAnalysisIfAvailable<TargetData>();
> +
> +      bool changed = false;
> +      // Iterate a sufficient number of times to merge types of
> +      // size 1, then 2, then 4, etc. up to half of the
> +      // target vector width of the target vector register.
Any reason you don't use the 80 columns?

Also, why are you iterating here?


> +      for (unsigned vBits = 2, n = 1; vBits<= VectorBits&&
> +             (!MaxIter || n<= MaxIter); vBits *= 2, ++n) {
> +        DEBUG(dbgs()<<  "BBV: fusing loop #"<<  n<<  "...\n");
> +        if (vectorizePairs(VectorBits, BB)) {
> +          changed = true;
> +        }
> +        else {
> +          break;
> +        }

In general you should use '} else {'. Here braces are not needed at all.

> +    static inline VectorType *getVecType(Type *iType) {
> +      if (iType->isVectorTy()) {
> +        unsigned numElem = cast<VectorType>(iType)->getNumElements();
> +        return VectorType::get(iType->getScalarType(), numElem*2);
> +      }
> +      else {
> +        return VectorType::get(iType, 2);
> +      }
> +    }
> +
> +    // Note: when this function returns 0, the
> +    // resulting instructions are not actually fused.

Use all 80 columns. What is a depth factor? Can you explain in the
comment what this function calculates and not what happens when it is
used. If you want to keep the use case, just put is an example.

> +    static inline size_t depthFactor(Value *v) {
> +      if (isa<InsertElementInst>(v) || isa<ExtractElementInst>(v)) {
> +        return 0;
> +      }
No '{}' needed.

> +
> +      return 1;
> +    }
> +
> +    // Returns 1 if J accesses the memory directly after I; -1 if I accesses
> +    // the memory directly after J; and 0 otherwise.
> +    int getPairPtrInfo(Instruction *I, Instruction *J, const TargetData&TD,
> +        Value *&Iptr, Value *&Jptr, unsigned&Ialign, unsigned&Jalign) {

Also getPairPtrInfo() does not sound like a very descriptive name. What
about getOffset().

I am not sure about returning 0 for the remaining cases. I think
an offset of 0 is actually a very useful case, which can be implemented
as a scalar load plus a splat. What about returning the offset as a
reference value and return a boolean if it was successfully computed.
The other alternative I see is to use an enum that specifies the known
offsets and also includes an UNKNOWN value.

> +      if (isa<LoadInst>(I)) {
> +        Iptr = cast<LoadInst>(I)->getPointerOperand();
> +        Jptr = cast<LoadInst>(J)->getPointerOperand();
> +        Ialign = cast<LoadInst>(I)->getAlignment();
> +        Jalign = cast<LoadInst>(J)->getAlignment();
> +      }
> +      else {
> +        Iptr = cast<StoreInst>(I)->getPointerOperand();
> +        Jptr = cast<StoreInst>(J)->getPointerOperand();
> +        Ialign = cast<StoreInst>(I)->getAlignment();
> +        Jalign = cast<StoreInst>(J)->getAlignment();
> +      }

Use '} else {'. Also you are just checking just the type of one
instruction. You may want to check both and add a call to
llvm_unreachable in case the types do not match.

> +      ScalarEvolution&SE = getAnalysis<ScalarEvolution>();
> +      const SCEV *IptrSCEV = SE.getSCEV(Iptr);
> +      const SCEV *JptrSCEV = SE.getSCEV(Jptr);
> +
> +      // If this is a trivial offset, then we'll get something
> +      // like 1*sizeof(type). With target data, which we need
> +      // anyway, this will get constant folded into a number.
Why don't you use the full 80 columns?


> +      const SCEV *RelOffSCEV = SE.getMinusSCEV(JptrSCEV, IptrSCEV);

What about just alling this 'Offset'. Those appreviations are hard to
read.

> +      if (const SCEVConstant *ConstOffSCEV =
> +            dyn_cast<SCEVConstant>(RelOffSCEV)) {
> +        ConstantInt *IntOff = ConstOffSCEV->getValue();
> +        int64_t off = IntOff->getSExtValue();
> +
> +        Type *VTy = cast<PointerType>(Iptr->getType())->getElementType();

You should assert that the types of both pointers are indentical.
Also you should document that this function only works for vector types.
I actually expected it to just work for scalar types. Vector types look
a little bit wired here and I am actually not even sure if it is correct
for vector types.

> +        int64_t VTy_tss = (int64_t) TD.getTypeStoreSize(VTy);
> +
> +        if (off == VTy_tss) {
> +          return 1;
> +        } else if (-off == VTy_tss) {
> +          return -1;
> +        }
Braces not needed.

> +      }
Did you think of using SE.getSizeOfExpr()?

const SCEV *ElementSize = SE.getSizeofExpr(Iprt->getAllocType())
const SCEV *ElementOffset = SE.getUDivExpr(RelOffSCEV, ElementSize);

if (const SCEVConstant *ConstOffset =
       dyn_cast<SCEVConstant>(ElementOffset))
   return ConstOffset->getValue();

else
   return "Unknown offset"

> +  bool BBVectorize::vectorizePairs(unsigned vBits, BasicBlock&BB) {
> +    std::vector<Value *>  pairableInsts;
> +    std::multimap<Value *, Value *>  candPairs;

Variables should start with Uppercase letters.

> +    getCandPairs(vBits, BB, candPairs, pairableInsts);
> +    if (!pairableInsts.size()) return false;
> +
> +    // Now we have a map of all of the pairable instructions and we need to
> +    // select the best possible pairing. A good pairing is one such that the
> +    // users of the pair are also paired. This defines a (directed) forest
> +    // over the pairs such that two pairs are connected iff the second pair
> +    // uses the first.
> +
> +    // Note that it only matters that both members of the second pair use some
> +    // element of the first pair (to allow for splatting).
> +
> +    std::multimap<value_pair, value_pair>  connPairs;
> +    computeConnPairs(candPairs, pairableInsts, connPairs);
> +    if (!connPairs.size()) return false;
> +
> +    // Build the pairable-instruction dependency map
> +    DenseSet<value_pair>  pairableInstUsers;
> +    buildDepMap(BB, candPairs, pairableInsts, pairableInstUsers);
> +
> +    // There is now a graph of the connected pairs. For each variable, pick the
> +    // pairing with the largest tree meeting the depth requirement on at least
> +    // one branch. Then select all pairings that are part of that tree and
> +    // remove them from the list of available parings and pairable variables.
> +
> +    DenseMap<Value *, Value *>  chosenPairs;
> +    choosePairs(candPairs, pairableInsts, connPairs,
> +      pairableInstUsers, chosenPairs);
> +
> +    if (!chosenPairs.size()) return false;
> +    NumFusedOps += chosenPairs.size();
> +
> +    // A set of chosen pairs has now been selected. It is now necessary to
> +    // replace the paired functions with vector functions. For this procedure
                              instructions with vector instructions.

> +    // each argument much be replaced with a vector argument. This vector
                         must

> +    // is formed by using build_vector on the old arguments. The replaced
> +    // values are then replaced with a vector_extract on the result.
> +    // Subsequent optimization passes should coalesce the build/extract
> +    // combinations.
> +
> +    replValues(BB, pairableInsts, chosenPairs);
> +
> +    return true;
> +  }
> +
> +  void BBVectorize::getCandPairs(unsigned vBits, BasicBlock&BB,
> +                       std::multimap<Value *, Value *>  &candPairs,
> +                       std::vector<Value *>  &pairableInsts) {
This function is too big. It does not even fit on my large screen. Can
you extract sub functons. E.g. isValidInst()

> +    AliasAnalysis&AA = getAnalysis<AliasAnalysis>();
> +    BasicBlock::iterator E = BB.end();
> +    for (BasicBlock::iterator I = BB.getFirstInsertionPt(); I != E; ++I) {

The common pattern is:

for (BasicBlock::iterator I = BB.getFirstInsertionPt(), E.BB.end(); I != E;
      ++I) {

BTW, why don't you start at BB.begin()?

> +      bool isGoodIntr = false;
> +      if (isa<CallInst>(I)) {
> +        if (Function *F = cast<CallInst>(I)->getCalledFunction()) {

if (CallInst *CallInst = dyn_cast<CallInst>(I)) {
   if (Function *F = CallInst->getCalledFunction()) {

> +          if (unsigned IID = F->getIntrinsicID()) {
> +            switch(IID) {
> +            case Intrinsic::sqrt:
> +            case Intrinsic::powi:
> +            case Intrinsic::sin:
> +            case Intrinsic::cos:
> +            case Intrinsic::log:
> +            case Intrinsic::log2:
> +            case Intrinsic::log10:
> +            case Intrinsic::exp:
> +            case Intrinsic::exp2:
> +            case Intrinsic::pow:
> +              isGoodIntr = !NoMath;
Is the fallthrough intended here?

> +            case Intrinsic::fma:
> +              isGoodIntr = !NoFMA;
I would also put a break here.

What happends in the default case or do you cover all intrinsics.?
> +            }
> +          }
> +        }
Most of these '{}' are not needed.

> +      }
> +
> +      // Vectorize simple loads and stores if possbile:
> +      bool isLdStr = false;

IsSimpleLoad?

> +      if (isa<LoadInst>(I)) {
> +        isLdStr = cast<LoadInst>(I)->isSimple();
> +      } else if (isa<StoreInst>(I)) {
> +        isLdStr = cast<StoreInst>(I)->isSimple();
> +      }

if (LoadInst *Load = dyn_cast<LoadInst>(I)) {
   isLdStr = Load->isSimple();
} else if (StoreInst *Store = dyn_cast<StoreInst>(I)) {
   isLdStr = Store->isSimple();
}

> +
> +      // We can vectorize casts, but not casts of pointer types, etc.
> +      bool isCast = false;
> +      if (I->isCast()) {
> +        isCast = true;
> +        if (!cast<CastInst>(I)->getSrcTy()->isSingleValueType()) {
> +          isCast = false;
> +        } else if (!cast<CastInst>(I)->getDestTy()->isSingleValueType()) {
> +          isCast = false;
> +        } else if (cast<CastInst>(I)->getSrcTy()->isPointerTy()) {
> +          isCast = false;
> +        } else if (cast<CastInst>(I)->getDestTy()->isPointerTy()) {
> +          isCast = false;
> +        }
> +      }
> +
> +      if (!(I->isBinaryOp() || isa<ShuffleVectorInst>(I) ||
> +              isa<ExtractElementInst>(I) || isa<InsertElementInst>(I) ||
> +              (!NoCasts&&  isCast) || isGoodIntr ||
> +              (!NoMemOps&&  isLdStr))) {
> +        continue;
> +      }
> +
> +      // We can't vectorize memory operations without target data
> +      if (AA.getTargetData() == 0&&  isLdStr) {
> +        continue;
> +      }
> +
> +      Type *T1, *T2;
> +      if (isa<StoreInst>(I)) {
> +        // For stores, it is the value type, not the pointer type that matters
> +        // because the value is what will come from a vector register.
> +
> +        Value *Ival = cast<StoreInst>(I)->getValueOperand();
> +        T1 = Ival->getType();
> +      }
> +      else {
> +        T1 = I->getType();
> +      }
> +
> +      if (I->isCast()) {
> +        T2 = cast<CastInst>(I)->getSrcTy();
> +      }
> +      else {
> +        T2 = T1;
> +      }
> +
> +      // Not every type can be vectorized...
> +      if (!(VectorType::isValidElementType(T1) || T1->isVectorTy()) ||
> +          !(VectorType::isValidElementType(T2) || T2->isVectorTy())) {
> +        continue;
> +      }
> +
> +      if (NoInts&&  (T1->isIntOrIntVectorTy() || T2->isIntOrIntVectorTy())) {
> +        continue;
> +      }
> +
> +      if (NoFloats&&  (T1->isFPOrFPVectorTy() || T2->isFPOrFPVectorTy())) {
> +        continue;
> +      }
> +
> +      if (T1->getPrimitiveSizeInBits()>  vBits/2 ||
> +          T2->getPrimitiveSizeInBits()>  vBits/2) {
> +        continue;
> +      }
> +
> +      // Look for an instruction with which to pair instruction *I...
This could be a separate function, no?

> +      DenseSet<Value *>  users;
> +      AliasSetTracker writes(AA);
> +      BasicBlock::iterator J = I; ++J;
> +      for (unsigned ss = 0; J != E&&  ss<= SearchLimit; ++J, ++ss) {
> +        // Determine if J uses I, if so, exit the loop.

This loop is way to big. You can extract here also a couple of
subfunctions. I will review this after this in etail more readable.
> +        bool usesI = false;
> +        for (User::op_iterator i = J->op_begin(), e = J->op_end();
> +               i != e; ++i) {
> +          Value *v = *i;
> +          if (I == v ||
> +               (!FastDep&&  users.count(v))) {

Why a newline here? It should not break the 80 col limit.

> +            usesI = true; break;
One instruction per line, please.

> +          }
> +        }
> +        if (!usesI&&  J->mayReadFromMemory()) {
> +          for (AliasSetTracker::iterator i = writes.begin(), e = writes.end();
> +                i != e; ++i) {
> +            for (AliasSet::iterator j = i->begin(), e2 = i->end();
> +                   j != e2; ++j) {
> +              AliasAnalysis::Location ptrLoc(j->getValue(), j->getSize(),
> +                j->getTBAAInfo());
> +              if (AA.getModRefInfo(J, ptrLoc) != AliasAnalysis::NoModRef) {
> +                usesI = true; break;
One instruction per line.

> +              }
> +            }
> +            if (usesI) break;
> +          }
> +        }
Many of these braces are not necessarily needed. In case this function
would be smaller they would also not be required for readability.

> +        if (FastDep) {
> +          // Note: For this heuristic to be effective, independent operations
> +          // must tend to be intermixed. This is likely to be true from some
> +          // kinds of loop unrolling (but not the generic LLVM pass),
> +          // but otherwise may require some kind of reordering pass.

What does it mean that independent operations must be intermixed? Can
you give an example?

> +
> +          // When using fast dependency analysis,
> +          // stop searching after first use:
> +          if (usesI) break;
> +        }
> +        else {
> +          if (usesI) {

} else if (usesI) {

> +            if (J->mayWriteToMemory()) writes.add(J);
> +            users.insert(J);
> +            continue;
> +          }
> +        }
> +
> +        // J does not use I, and comes before the first use of I, so it can be
> +        // merged with I if the instructions are compatible.
> +        bool isCompat = J->isSameOperationAs(I);
> +        // FIXME: handle addsub-type operations!
> +
> +        // Only merge two shuffles if they're both constant
> +        // or both not constant.
> +        if (isCompat&&  isa<ShuffleVectorInst>(I)) {
> +          isCompat = isa<Constant>(I->getOperand(2))&&
> +                     isa<Constant>(J->getOperand(2));
> +          // FIXME: We may want to vectorize non-constant shuffles also.
> +        }
> +
> +        // Loads and stores can be merged if they have different alignments,
> +        // but are otherwise the same.
> +        if (!isCompat&&  isa<LoadInst>(I)&&  isa<LoadInst>(J)) {
> +          if (I->getType() == J->getType()) {
> +            if (cast<LoadInst>(I)->getPointerOperand()->getType() ==
> +                  cast<LoadInst>(J)->getPointerOperand()->getType()&&
> +                cast<LoadInst>(I)->isVolatile() ==
> +                  cast<LoadInst>(J)->isVolatile()&&
> +                cast<LoadInst>(I)->getOrdering() ==
> +                  cast<LoadInst>(J)->getOrdering()&&
> +                cast<LoadInst>(I)->getSynchScope() ==
> +                  cast<LoadInst>(J)->getSynchScope()
> +               ) {
> +                 isCompat = true;
> +             }
> +          }
> +        } else if (!isCompat&&  isa<StoreInst>(I)&&  isa<StoreInst>(J)) {
> +          if (cast<StoreInst>(I)->getValueOperand()->getType() ==
> +                cast<StoreInst>(J)->getValueOperand()->getType()&&
> +              cast<StoreInst>(I)->getPointerOperand()->getType() ==
> +                cast<StoreInst>(J)->getPointerOperand()->getType()&&
> +              cast<StoreInst>(I)->isVolatile() ==
> +                cast<StoreInst>(J)->isVolatile()&&
> +              cast<StoreInst>(I)->getOrdering() ==
> +                cast<StoreInst>(J)->getOrdering()&&
> +              cast<StoreInst>(I)->getSynchScope() ==
> +                cast<StoreInst>(J)->getSynchScope()
> +             ) {
> +               isCompat = true;
> +           }
> +        }
> +
> +        if (isCompat&&  isLdStr) {
> +          const TargetData&TD = *AA.getTargetData();
> +
> +          Value *Iptr, *Jptr;
> +          unsigned Ialign, Jalign;
> +          int rel = getPairPtrInfo(I, J, TD, Iptr, Jptr, Ialign, Jalign);

Use uppercase letters. What does 'rel' mean? Can you use a more
descriptive name?

> +
> +          if (rel != 0) {
> +            if (AlignedOnly) {
> +              Type *aType = isa<StoreInst>(I) ?
> +                cast<StoreInst>(I)->getValueOperand()->getType() : I->getType();
> +              // An aligned load or store is possible only if the instruction
> +              // with the lower offset has an alignment suitable for the
> +              // vector type.
> +
> +              unsigned balign = Ialign;

Uppercase letter.

> +              if (rel<  0) balign = Jalign;
> +
> +              Type *vType = getVecType(aType);
> +              unsigned vecalign = TD.getPrefTypeAlignment(vType);

Uppercase.

> +              if (balign<  vecalign) {
> +                isCompat = false;

This could just be a continue (or a return false if extracted to a
separate function. Also no braces needed.

> +              }
> +            }
> +          }
> +          else {

} else {

> +            isCompat = false;
This could just be a continue (or a return false if extracted to a
separate function.


> +          }
> +        }
> +
> +        if (!isCompat) continue;
> +
> +        // J is a candidate for merging with I.
> +        if (!pairableInsts.size() ||
> +             pairableInsts[pairableInsts.size()-1] != I) {
> +          pairableInsts.push_back(I);
> +        }

No braces needed.

> +        candPairs.insert(value_pair(I, J));
> +        DEBUG(dbgs()<<  "BBV: candidate pair "<<  *I<<
> +                     "<->  "<<  *J<<  "\n");
> +      }
> +    }
> +
> +    DEBUG(dbgs()<<  "BBV: found "<<  pairableInsts.size()
> +<<  " instructions with candidate pairs\n");
> +  }
> +
> +  void BBVectorize::computeConnPairs(
> +                      std::multimap<Value *, Value *>  &candPairs,
> +                      std::vector<Value *>  &pairableInsts,
> +                      std::multimap<value_pair, value_pair>  &connPairs) {
Uppercase names for arguments. Also, the function is way too long. Can
you extract smaller helper functions. I will review this then.

> +
> +    for (std::vector<Value *>::iterator i = pairableInsts.begin(),
> +           e = pairableInsts.end(); i != e; ++i) {
> +      vp_iterator_pair choiceRange = candPairs.equal_range(*i);
> +
> +      for (std::multimap<Value *, Value *>::iterator j = choiceRange.first;
> +           j != choiceRange.second; ++j) {
> +
> +        // For each possible pairing for this variable, look at the uses of
> +        // the first value...
> +        for (Value::use_iterator I = j->first->use_begin(),
> +             E = j->first->use_end(); I != E; ++I) {
> +          vp_iterator_pair iPairRange = candPairs.equal_range(*I);
> +
> +          // For each use of the first variable, look for uses of the second
> +          // variable...
> +          for (Value::use_iterator J = j->second->use_begin(),
> +               E2 = j->second->use_end(); J != E2; ++J) {
> +            vp_iterator_pair jPairRange = candPairs.equal_range(*J);
> +
> +            // Look for<I, J>:
> +            for (std::multimap<Value *, Value *>::iterator k = iPairRange.first;
> +                 k != iPairRange.second; ++k) {
> +              if (k->second == *J) {
> +                connPairs.insert(vp_pair(*j, value_pair(*I, *J)));
> +                break;
> +              }
> +            }
> +            // Look for<J, I>:
> +            for (std::multimap<Value *, Value *>::iterator k = jPairRange.first;
> +                 k != jPairRange.second; ++k) {
> +              if (k->second == *I) {
> +                connPairs.insert(vp_pair(*j, value_pair(*J, *I)));
> +                break;
> +              }
> +            }
> +          }
> +
> +          // Look for cases where just the first value in the pair is used by
> +          // both members of another pair (splatting).
> +          Value::use_iterator J = j->first->use_begin();
> +          if (!SplatBreaksChain) for (; J != E; ++J) {
> +            for (std::multimap<Value *, Value *>::iterator k = iPairRange.first;
> +                 k != iPairRange.second; ++k) {
> +              if (k->second == *J) {
> +                connPairs.insert(vp_pair(*j, value_pair(*I, *J)));
> +                break;
> +              }
> +            }
> +          }
> +        }
> +
> +        // Look for cases where just the second value in the pair is used by
> +        // both members of another pair (splatting).
> +        if (!SplatBreaksChain)
> +          for (Value::use_iterator I = j->second->use_begin(),
> +             E = j->second->use_end(); I != E; ++I) {
> +          vp_iterator_pair iPairRange = candPairs.equal_range(*I);
> +
> +          Value::use_iterator J = j->second->use_begin();
> +          for (; J != E; ++J) {
> +            for (std::multimap<Value *, Value *>::iterator k = iPairRange.first;
> +                 k != iPairRange.second; ++k) {
> +              if (k->second == *J) {
> +                connPairs.insert(vp_pair(*j, value_pair(*I, *J)));
> +                break;
> +              }
> +            }
> +          }
> +        }
> +      }
> +    }
> +
> +    DEBUG(dbgs()<<  "BBV: found "<<  connPairs.size()
> +<<  " pair connections.\n");
> +  }


> +  void BBVectorize::buildDepMap(
> +                      BasicBlock&BB,
> +                      std::multimap<Value *, Value *>  &candPairs,
> +                      std::vector<Value *>  &pairableInsts,
> +                      DenseSet<value_pair>  &pairableInstUsers) {
Uppercase variable names.

> +    DenseSet<Value *>  isInPair;
> +    for (std::multimap<Value *, Value *>::iterator i = candPairs.begin(),
> +           e = candPairs.end(); i != e; ++i) {

Uppercase letters are used in LLVM for iterators.

> +      isInPair.insert(i->first); isInPair.insert(i->second);
> +    }

No braces needed.

> +
> +    // Iterate through the basic block, recording all users of each
> +    // pairable instruction.
> +
> +    AliasAnalysis&AA = getAnalysis<AliasAnalysis>();
> +    BasicBlock::iterator E = BB.end();
> +    for (BasicBlock::iterator I = BB.getFirstInsertionPt(); I != E; ++I) {
> +      if (isInPair.find(I) == isInPair.end()) continue;
> +
> +      DenseSet<Value *>  users;
> +      AliasSetTracker writes(AA);
> +      BasicBlock::iterator J = I; ++J;
> +      for (; J != E; ++J) {
> +        // Determine if J uses I, if so, exit the loop.
Just extract this into a small helper function. No need to keep it here.

> +        bool usesI = false;
> +        for (User::op_iterator i = J->op_begin(), e = J->op_end();
> +               i != e; ++i) {
> +          Value *v = *i;
> +          if (I == v || users.count(v)) {
> +            usesI = true; break;
> +          }
> +        }
> +        if (!usesI&&  J->mayReadFromMemory()) {

And this one as well
> +          for (AliasSetTracker::iterator i = writes.begin(), e = writes.end();
> +                i != e; ++i) {
> +            for (AliasSet::iterator j = i->begin(), e2 = i->end();
> +                   j != e2; ++j) {
> +              AliasAnalysis::Location ptrLoc(j->getValue(), j->getSize(),
> +                j->getTBAAInfo());
> +              if (AA.getModRefInfo(J, ptrLoc) != AliasAnalysis::NoModRef) {
> +                usesI = true; break;
> +              }
> +            }
> +            if (usesI) break;
> +          }
> +        }
> +        if (usesI) {
> +          if (J->mayWriteToMemory()) writes.add(J);
> +          users.insert(J);
> +        }

> +      }
The resulting loop should be very simple.
	
> +
> +      for (DenseSet<Value *>::iterator i = users.begin(), e = users.end();
> +             i != e; ++i) {
> +        pairableInstUsers.insert(value_pair(I, *i));
> +      }
> +    }
> +  }
> +

What does it mean pairs are in conflict? What about adding a comment
about what this actually means.

> +  bool BBVectorize::pairsConflict(value_pair i, value_pair j,
> +                      DenseSet<value_pair>  &pairableInstUsers) {
> +    // Two pairs are in conflict if they are mutual users of eachother.
> +    bool jui = pairableInstUsers.count(value_pair(i.first, j.first)) ||
> +               pairableInstUsers.count(value_pair(i.first, j.second)) ||
> +               pairableInstUsers.count(value_pair(i.second, j.first)) ||
> +               pairableInstUsers.count(value_pair(i.second, j.second));
> +    bool iuj = pairableInstUsers.count(value_pair(j.first, i.first)) ||
> +               pairableInstUsers.count(value_pair(j.first, i.second)) ||
> +               pairableInstUsers.count(value_pair(j.second, i.first)) ||
> +               pairableInstUsers.count(value_pair(j.second, i.second));
> +    return (jui&&  iuj);
> +  }
> +
> +  void BBVectorize::choosePairs(
> +                      std::multimap<Value *, Value *>  &candPairs,
> +                      std::vector<Value *>  &pairableInsts,
> +                      std::multimap<value_pair, value_pair>  &connPairs,
> +                      DenseSet<value_pair>  &pairableInstUsers,
> +                      DenseMap<Value *, Value *>&  chosenPairs) {

This one is again way to large. Can you please extract subfunctions.

I need to stop here, as I run out of time for today. I hope you already
get an impression what kind of improvements I suggest. If you agree,
please go ahead and integrate them. Especially the use of smaller
subfunctions will help me a lot when reviewing this again. Most probably
many of your inline comments, could become the descriptions of some of
those extracted functions.

Cheers
Tobi


From grosser at fim.uni-passau.de  Thu Nov 17 06:56:00 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 12:56:00 -0000
Subject: [llvm-commits] [polly] r144898 -
	/polly/trunk/lib/ScheduleOptimizer.cpp
Message-ID: <20111117125601.070EB2A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 06:56:00 2011
New Revision: 144898

URL: http://llvm.org/viewvc/llvm-project?rev=144898&view=rev
Log:
ScheduleOptimizer: Use early exit

Style fix, noted by Sebastian Pop.

Modified:
    polly/trunk/lib/ScheduleOptimizer.cpp

Modified: polly/trunk/lib/ScheduleOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=144898&r1=144897&r2=144898&view=diff
==============================================================================
--- polly/trunk/lib/ScheduleOptimizer.cpp (original)
+++ polly/trunk/lib/ScheduleOptimizer.cpp Thu Nov 17 06:56:00 2011
@@ -207,18 +207,17 @@
 
   partialSchedule = isl_band_get_partial_schedule(band);
 
-  if (!DisableTiling) {
-    ctx = isl_union_map_get_ctx(partialSchedule);
-    Space= isl_union_map_get_space(partialSchedule);
-    scheduleDimensions = isl_band_n_member(band);
-
-    tileMap = getTileMap(ctx, scheduleDimensions, Space);
-    tileUnionMap = isl_union_map_from_map(isl_map_from_basic_map(tileMap));
-    tileUnionMap = isl_union_map_align_params(tileUnionMap, Space);
-    partialSchedule = isl_union_map_apply_range(partialSchedule, tileUnionMap);
-  }
+  if (DisableTiling)
+    return partialSchedule;
 
-  return partialSchedule;
+  ctx = isl_union_map_get_ctx(partialSchedule);
+  Space = isl_union_map_get_space(partialSchedule);
+  scheduleDimensions = isl_band_n_member(band);
+
+  tileMap = getTileMap(ctx, scheduleDimensions, Space);
+  tileUnionMap = isl_union_map_from_map(isl_map_from_basic_map(tileMap));
+  tileUnionMap = isl_union_map_align_params(tileUnionMap, Space);
+  return isl_union_map_apply_range(partialSchedule, tileUnionMap);
 }
 
 static isl_map *getPrevectorMap(isl_ctx *ctx, int vectorDimension,



From grosser at fim.uni-passau.de  Thu Nov 17 06:56:03 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 12:56:03 -0000
Subject: [llvm-commits] [polly] r144899 -
	/polly/trunk/lib/ScheduleOptimizer.cpp
Message-ID: <20111117125603.40AB52A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 06:56:03 2011
New Revision: 144899

URL: http://llvm.org/viewvc/llvm-project?rev=144899&view=rev
Log:
ScheduleOptimizer: Some style changes

- Use uppercase letters according to the LLVM coding style
- Rename functions to not include 'tiledSchedule', but just Schedule. This
  is more correct as tiling might be disabled.

Modified:
    polly/trunk/lib/ScheduleOptimizer.cpp

Modified: polly/trunk/lib/ScheduleOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=144899&r1=144898&r2=144899&view=diff
==============================================================================
--- polly/trunk/lib/ScheduleOptimizer.cpp (original)
+++ polly/trunk/lib/ScheduleOptimizer.cpp Thu Nov 17 06:56:03 2011
@@ -197,27 +197,30 @@
   return tileMap;
 }
 
-isl_union_map *getTiledPartialSchedule(isl_band *band) {
-  isl_union_map *partialSchedule;
-  int scheduleDimensions;
+// getScheduleForBand - Get the schedule for this band.
+//
+// In case tiling is enabled, the schedule of the band is tiled.
+isl_union_map *getScheduleForBand(isl_band *Band) {
+  isl_union_map *PartialSchedule;
+  int Dimensions;
   isl_ctx *ctx;
   isl_space *Space;
-  isl_basic_map *tileMap;
-  isl_union_map *tileUnionMap;
+  isl_basic_map *TileMap;
+  isl_union_map *TileUMap;
 
-  partialSchedule = isl_band_get_partial_schedule(band);
+  PartialSchedule = isl_band_get_partial_schedule(Band);
 
   if (DisableTiling)
-    return partialSchedule;
+    return PartialSchedule;
 
-  ctx = isl_union_map_get_ctx(partialSchedule);
-  Space = isl_union_map_get_space(partialSchedule);
-  scheduleDimensions = isl_band_n_member(band);
-
-  tileMap = getTileMap(ctx, scheduleDimensions, Space);
-  tileUnionMap = isl_union_map_from_map(isl_map_from_basic_map(tileMap));
-  tileUnionMap = isl_union_map_align_params(tileUnionMap, Space);
-  return isl_union_map_apply_range(partialSchedule, tileUnionMap);
+  ctx = isl_union_map_get_ctx(PartialSchedule);
+  Space = isl_union_map_get_space(PartialSchedule);
+  Dimensions = isl_band_n_member(Band);
+
+  TileMap = getTileMap(ctx, Dimensions, Space);
+  TileUMap = isl_union_map_from_map(isl_map_from_basic_map(TileMap));
+  TileUMap = isl_union_map_align_params(TileUMap, Space);
+  return isl_union_map_apply_range(PartialSchedule, TileUMap);
 }
 
 static isl_map *getPrevectorMap(isl_ctx *ctx, int vectorDimension,
@@ -284,67 +287,75 @@
   return isl_map_from_basic_map(tilingMap);
 }
 
-// tileBandList - Tile all bands contained in a band forest.
+// getScheduleForBandList - Get the scheduling map for a list of bands.
 //
-// Recursively walk the band forest and tile all bands in the forest. Return
-// a schedule that describes the tiled scattering.
-static isl_union_map *tileBandList(isl_band_list *blist) {
-  int numBands = isl_band_list_n_band(blist);
-
-  isl_union_map *finalSchedule = 0;
-
-  for (int i = 0; i < numBands; i++) {
-    isl_band *band;
-    isl_union_map *partialSchedule;
-    band = isl_band_list_get_band(blist, i);
-    partialSchedule = getTiledPartialSchedule(band);
-    int scheduleDimensions = isl_band_n_member(band);
-    isl_space *Space = isl_union_map_get_space(partialSchedule);
-
-
-    if (isl_band_has_children(band)) {
-      isl_band_list *children = isl_band_get_children(band);
-      isl_union_map *suffixSchedule = tileBandList(children);
-      partialSchedule = isl_union_map_flat_range_product(partialSchedule,
-							 suffixSchedule);
-      isl_band_list_free(children);
+// We walk recursively the forest of bands to combine the schedules of the
+// individual bands to the overall schedule. In case tiling is requested,
+// the individual bands are tiled.
+static isl_union_map *getScheduleForBandList(isl_band_list *BandList) {
+  int NumBands;
+  isl_union_map *Schedule;
+  isl_ctx *ctx;
+
+  ctx = isl_band_list_get_ctx(BandList);
+  NumBands = isl_band_list_n_band(BandList);
+  Schedule = 0;
+
+  for (int i = 0; i < NumBands; i++) {
+    isl_band *Band;
+    isl_union_map *PartialSchedule;
+    int ScheduleDimensions;
+    isl_space *Space;
+
+    Band = isl_band_list_get_band(BandList, i);
+    PartialSchedule = getScheduleForBand(Band);
+    ScheduleDimensions = isl_band_n_member(Band);
+    Space = isl_union_map_get_space(PartialSchedule);
+
+    if (isl_band_has_children(Band)) {
+      isl_band_list *Children;
+      isl_union_map *SuffixSchedule;
+
+      Children = isl_band_get_children(Band);
+      SuffixSchedule = getScheduleForBandList(Children);
+      PartialSchedule = isl_union_map_flat_range_product(PartialSchedule,
+							 SuffixSchedule);
+      isl_band_list_free(Children);
     } else if (EnablePollyVector) {
-      isl_map *tileMap;
-      isl_union_map *tileUnionMap;
-      isl_ctx *ctx;
-
-      ctx = isl_union_map_get_ctx(partialSchedule);
-      for (int i = scheduleDimensions - 1 ;  i >= 0 ; i--) {
-	if (isl_band_member_is_zero_distance(band, i)) {
-	  tileMap = getPrevectorMap(ctx, scheduleDimensions + i,
-				    scheduleDimensions * 2, 0);
-	  tileUnionMap = isl_union_map_from_map(tileMap);
-          tileUnionMap = isl_union_map_align_params(tileUnionMap,
-                                                    isl_space_copy(Space));
-	  partialSchedule = isl_union_map_apply_range(partialSchedule,
-						      tileUnionMap);
+      for (int i = ScheduleDimensions - 1 ;  i >= 0 ; i--) {
+	if (isl_band_member_is_zero_distance(Band, i)) {
+          isl_map *TileMap;
+          isl_union_map *TileUMap;
+
+	  TileMap = getPrevectorMap(ctx, ScheduleDimensions + i,
+				    ScheduleDimensions * 2, 0);
+	  TileUMap = isl_union_map_from_map(TileMap);
+          TileUMap = isl_union_map_align_params(TileUMap,
+                                                isl_space_copy(Space));
+	  PartialSchedule = isl_union_map_apply_range(PartialSchedule,
+						      TileUMap);
 	  break;
 	}
       }
     }
 
-    if (finalSchedule)
-      finalSchedule = isl_union_map_union(finalSchedule, partialSchedule);
+    if (Schedule)
+      Schedule = isl_union_map_union(Schedule, PartialSchedule);
     else
-      finalSchedule = partialSchedule;
+      Schedule = PartialSchedule;
 
-    isl_band_free(band);
+    isl_band_free(Band);
     isl_space_free(Space);
   }
 
-  return finalSchedule;
+  return Schedule;
 }
 
-static isl_union_map *tileSchedule(isl_schedule *schedule) {
-  isl_band_list *blist = isl_schedule_get_band_forest(schedule);
-  isl_union_map *tiledSchedule = tileBandList(blist);
-  isl_band_list_free(blist);
-  return tiledSchedule;
+static isl_union_map *getScheduleMap(isl_schedule *Schedule) {
+  isl_band_list *BandList = isl_schedule_get_band_forest(Schedule);
+  isl_union_map *ScheduleMap = getScheduleForBandList(BandList);
+  isl_band_list_free(BandList);
+  return ScheduleMap;
 }
 
 bool IslScheduleOptimizer::runOnScop(Scop &S) {
@@ -386,7 +397,7 @@
   DEBUG(dbgs() << stringFromIslObj(schedule));
   DEBUG(dbgs() << "Individual bands: ");
 
-  isl_union_map *tiledSchedule = tileSchedule(schedule);
+  isl_union_map *ScheduleMap = getScheduleMap(schedule);
 
   for (Scop::iterator SI = S.begin(), SE = S.end(); SI != SE; ++SI) {
     ScopStmt *stmt = *SI;
@@ -396,7 +407,7 @@
 
     isl_set *domain = stmt->getDomain();
     isl_union_map *stmtBand;
-    stmtBand = isl_union_map_intersect_domain(isl_union_map_copy(tiledSchedule),
+    stmtBand = isl_union_map_intersect_domain(isl_union_map_copy(ScheduleMap),
 					      isl_union_set_from_set(domain));
     isl_map *stmtSchedule;
     isl_union_map_foreach_map(stmtBand, getSingleMap, &stmtSchedule);
@@ -404,7 +415,7 @@
     isl_union_map_free(stmtBand);
   }
 
-  isl_union_map_free(tiledSchedule);
+  isl_union_map_free(ScheduleMap);
   isl_schedule_free(schedule);
 
   unsigned maxScatDims = 0;



From grosser at fim.uni-passau.de  Thu Nov 17 06:56:05 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 12:56:05 -0000
Subject: [llvm-commits] [polly] r144900 -
	/polly/trunk/lib/ScheduleOptimizer.cpp
Message-ID: <20111117125605.45BCF2A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 06:56:04 2011
New Revision: 144900

URL: http://llvm.org/viewvc/llvm-project?rev=144900&view=rev
Log:
ScheduleOptimizer: Start with an empty union_map and add elements

Modified:
    polly/trunk/lib/ScheduleOptimizer.cpp

Modified: polly/trunk/lib/ScheduleOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=144900&r1=144899&r2=144900&view=diff
==============================================================================
--- polly/trunk/lib/ScheduleOptimizer.cpp (original)
+++ polly/trunk/lib/ScheduleOptimizer.cpp Thu Nov 17 06:56:04 2011
@@ -299,7 +299,7 @@
 
   ctx = isl_band_list_get_ctx(BandList);
   NumBands = isl_band_list_n_band(BandList);
-  Schedule = 0;
+  Schedule = isl_union_map_empty(isl_space_params_alloc(ctx, 0));
 
   for (int i = 0; i < NumBands; i++) {
     isl_band *Band;
@@ -339,10 +339,7 @@
       }
     }
 
-    if (Schedule)
-      Schedule = isl_union_map_union(Schedule, PartialSchedule);
-    else
-      Schedule = PartialSchedule;
+    Schedule = isl_union_map_union(Schedule, PartialSchedule);
 
     isl_band_free(Band);
     isl_space_free(Space);



From grosser at fim.uni-passau.de  Thu Nov 17 06:56:07 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 12:56:07 -0000
Subject: [llvm-commits] [polly] r144901 - /polly/trunk/lib/RegisterPasses.cpp
Message-ID: <20111117125607.0FC472A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 06:56:06 2011
New Revision: 144901

URL: http://llvm.org/viewvc/llvm-project?rev=144901&view=rev
Log:
RegisterPasses: Avoid double negation

Fix suggested by Sebastian Pop.

Modified:
    polly/trunk/lib/RegisterPasses.cpp

Modified: polly/trunk/lib/RegisterPasses.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/RegisterPasses.cpp?rev=144901&r1=144900&r2=144901&view=diff
==============================================================================
--- polly/trunk/lib/RegisterPasses.cpp (original)
+++ polly/trunk/lib/RegisterPasses.cpp Thu Nov 17 06:56:06 2011
@@ -104,6 +104,9 @@
 
 static void registerPollyPasses(const llvm::PassManagerBuilder &Builder,
                                 llvm::PassManagerBase &PM) {
+  bool RunScheduler = !DisableScheduler;
+  bool RunCodegen = !DisableCodegen;
+
   // Polly is only enabled at -O3
   if (Builder.OptLevel != 3)
     return;
@@ -150,10 +153,8 @@
   if (ImportJScop)
     PM.add(polly::createJSONImporterPass());
 
-  if (!DisableScheduler) {
-    if (!UsePocc)
-      PM.add(polly::createIslScheduleOptimizerPass());
-    else {
+  if (RunScheduler) {
+    if (UsePocc) {
 #ifdef SCOPLIB_FOUND
       PM.add(polly::createPoccPass());
 #else
@@ -162,14 +163,15 @@
              << "back to the isl optimizer.\n";
       PM.add(polly::createIslScheduleOptimizerPass());
 #endif
+    } else {
+      PM.add(polly::createIslScheduleOptimizerPass());
     }
   }
 
   if (ExportJScop)
     PM.add(polly::createJSONExporterPass());
 
-
-  if (!DisableCodegen)
+  if (RunCodegen)
     PM.add(polly::createCodeGenerationPass());
 }
 



From grosser at fim.uni-passau.de  Thu Nov 17 06:56:10 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 12:56:10 -0000
Subject: [llvm-commits] [polly] r144902 - in /polly/trunk/lib:
 Analysis/Dependences.cpp Analysis/ScopGraphPrinter.cpp
 Analysis/ScopInfo.cpp Cloog.cpp CodeGeneration.cpp
 Exchange/OpenScopExporter.cpp IndependentBlocks.cpp
 Support/SCEVValidator.cpp Support/ScopHelper.cpp
Message-ID: <20111117125610.E6E922A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 06:56:10 2011
New Revision: 144902

URL: http://llvm.org/viewvc/llvm-project?rev=144902&view=rev
Log:
Fix placement of the '*' that marks a pointer

Suggested by Sebastian Pop.

Modified:
    polly/trunk/lib/Analysis/Dependences.cpp
    polly/trunk/lib/Analysis/ScopGraphPrinter.cpp
    polly/trunk/lib/Analysis/ScopInfo.cpp
    polly/trunk/lib/Cloog.cpp
    polly/trunk/lib/CodeGeneration.cpp
    polly/trunk/lib/Exchange/OpenScopExporter.cpp
    polly/trunk/lib/IndependentBlocks.cpp
    polly/trunk/lib/Support/SCEVValidator.cpp
    polly/trunk/lib/Support/ScopHelper.cpp

Modified: polly/trunk/lib/Analysis/Dependences.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/Dependences.cpp?rev=144902&r1=144901&r2=144902&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/Dependences.cpp (original)
+++ polly/trunk/lib/Analysis/Dependences.cpp Thu Nov 17 06:56:10 2011
@@ -235,7 +235,7 @@
   return isValid;
 }
 
-isl_union_map* getCombinedScheduleForSpace(Scop *scop, unsigned dimLevel) {
+isl_union_map *getCombinedScheduleForSpace(Scop *scop, unsigned dimLevel) {
   isl_space *Space = scop->getParamSpace();
   isl_union_map *schedule = isl_union_map_empty(Space);
 
@@ -454,6 +454,6 @@
 INITIALIZE_PASS_END(Dependences, "polly-dependences",
                     "Polly - Calculate dependences", false, false)
 
-Pass* polly::createDependencesPass() {
+Pass *polly::createDependencesPass() {
   return new Dependences();
 }

Modified: polly/trunk/lib/Analysis/ScopGraphPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopGraphPrinter.cpp?rev=144902&r1=144901&r2=144902&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopGraphPrinter.cpp (original)
+++ polly/trunk/lib/Analysis/ScopGraphPrinter.cpp Thu Nov 17 06:56:10 2011
@@ -31,7 +31,7 @@
     static NodeType *getEntryNode(ScopDetection *SD) {
       return GraphTraits<RegionInfo*>::getEntryNode(SD->getRI());
     }
-    static nodes_iterator nodes_begin(ScopDetection* SD) {
+    static nodes_iterator nodes_begin(ScopDetection *SD) {
       return nodes_iterator::begin(getEntryNode(SD));
     }
     static nodes_iterator nodes_end(ScopDetection *SD) {
@@ -144,7 +144,7 @@
 
     O.indent(2 * depth) << "}\n";
   }
-  static void addCustomGraphFeatures(const ScopDetection* SD,
+  static void addCustomGraphFeatures(const ScopDetection *SD,
                                      GraphWriter<ScopDetection*> &GW) {
     raw_ostream &O = GW.getOStream();
     O << "\tcolorscheme = \"paired12\"\n";
@@ -199,18 +199,18 @@
 N("dot-scops-only",
   "Polly - Print Scops of function (with no function bodies)");
 
-Pass* polly::createDOTViewerPass() {
+Pass *polly::createDOTViewerPass() {
   return new ScopViewer();
 }
 
-Pass* polly::createDOTOnlyViewerPass() {
+Pass *polly::createDOTOnlyViewerPass() {
   return new ScopOnlyViewer();
 }
 
-Pass* polly::createDOTPrinterPass() {
+Pass *polly::createDOTPrinterPass() {
   return new ScopPrinter();
 }
 
-Pass* polly::createDOTOnlyPrinterPass() {
+Pass *polly::createDOTOnlyPrinterPass() {
   return new ScopOnlyPrinter();
 }

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144902&r1=144901&r2=144902&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Thu Nov 17 06:56:10 2011
@@ -140,21 +140,21 @@
     return isl_pw_aff_alloc(Domain, Affine);
   }
 
-  __isl_give isl_pw_aff *visitTruncateExpr(const SCEVTruncateExpr* Expr) {
+  __isl_give isl_pw_aff *visitTruncateExpr(const SCEVTruncateExpr *Expr) {
     assert(0 && "Not yet supported");
   }
 
-  __isl_give isl_pw_aff *visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) {
+  __isl_give isl_pw_aff *visitZeroExtendExpr(const SCEVZeroExtendExpr *Expr) {
     assert(0 && "Not yet supported");
   }
 
-  __isl_give isl_pw_aff *visitSignExtendExpr(const SCEVSignExtendExpr* Expr) {
+  __isl_give isl_pw_aff *visitSignExtendExpr(const SCEVSignExtendExpr *Expr) {
     // Assuming the value is signed, a sign extension is basically a noop.
     // TODO: Reconsider this as soon as we support unsigned values.
     return visit(Expr->getOperand());
   }
 
-  __isl_give isl_pw_aff *visitAddExpr(const SCEVAddExpr* Expr) {
+  __isl_give isl_pw_aff *visitAddExpr(const SCEVAddExpr *Expr) {
     isl_pw_aff *Sum = visit(Expr->getOperand(0));
 
     for (int i = 1, e = Expr->getNumOperands(); i < e; ++i) {
@@ -167,7 +167,7 @@
     return Sum;
   }
 
-  __isl_give isl_pw_aff *visitMulExpr(const SCEVMulExpr* Expr) {
+  __isl_give isl_pw_aff *visitMulExpr(const SCEVMulExpr *Expr) {
     isl_pw_aff *Product = visit(Expr->getOperand(0));
 
     for (int i = 1, e = Expr->getNumOperands(); i < e; ++i) {
@@ -186,7 +186,7 @@
     return Product;
   }
 
-  __isl_give isl_pw_aff *visitUDivExpr(const SCEVUDivExpr* Expr) {
+  __isl_give isl_pw_aff *visitUDivExpr(const SCEVUDivExpr *Expr) {
     assert(0 && "Not yet supported");
   }
 
@@ -197,7 +197,7 @@
     return L->getLoopDepth() - outerLoop->getLoopDepth();
   }
 
-  __isl_give isl_pw_aff *visitAddRecExpr(const SCEVAddRecExpr* Expr) {
+  __isl_give isl_pw_aff *visitAddRecExpr(const SCEVAddRecExpr *Expr) {
     assert(Expr->isAffine() && "Only affine AddRecurrences allowed");
     assert(scop->getRegion().contains(Expr->getLoop())
            && "Scop does not contain the loop referenced in this AddRec");
@@ -217,7 +217,7 @@
     return isl_pw_aff_add(Start, isl_pw_aff_mul(Step, LPwAff));
   }
 
-  __isl_give isl_pw_aff *visitSMaxExpr(const SCEVSMaxExpr* Expr) {
+  __isl_give isl_pw_aff *visitSMaxExpr(const SCEVSMaxExpr *Expr) {
     isl_pw_aff *Max = visit(Expr->getOperand(0));
 
     for (int i = 1, e = Expr->getNumOperands(); i < e; ++i) {
@@ -228,11 +228,11 @@
     return Max;
   }
 
-  __isl_give isl_pw_aff *visitUMaxExpr(const SCEVUMaxExpr* Expr) {
+  __isl_give isl_pw_aff *visitUMaxExpr(const SCEVUMaxExpr *Expr) {
     assert(0 && "Not yet supported");
   }
 
-  __isl_give isl_pw_aff *visitUnknown(const SCEVUnknown* Expr) {
+  __isl_give isl_pw_aff *visitUnknown(const SCEVUnknown *Expr) {
     Value *Value = Expr->getValue();
 
     isl_space *Space;
@@ -843,7 +843,7 @@
 //===----------------------------------------------------------------------===//
 /// Scop class implement
 
-void Scop::setContext(__isl_take isl_set* NewContext) {
+void Scop::setContext(__isl_take isl_set *NewContext) {
   NewContext = isl_set_align_params(NewContext, isl_set_get_space(Context));
   isl_set_free(Context);
   Context = NewContext;

Modified: polly/trunk/lib/Cloog.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Cloog.cpp?rev=144902&r1=144901&r2=144902&view=diff
==============================================================================
--- polly/trunk/lib/Cloog.cpp (original)
+++ polly/trunk/lib/Cloog.cpp Thu Nov 17 06:56:10 2011
@@ -260,7 +260,7 @@
                                     " (Writes a .cloog file for each Scop)"
                                     );
 
-llvm::Pass* polly::createCloogExporterPass() {
+llvm::Pass *polly::createCloogExporterPass() {
   return new CloogExporter();
 }
 
@@ -323,6 +323,6 @@
 INITIALIZE_PASS_END(CloogInfo, "polly-cloog",
                     "Execute Cloog code generation", false, false)
 
-Pass* polly::createCloogInfoPass() {
+Pass *polly::createCloogInfoPass() {
   return new CloogInfo();
 }

Modified: polly/trunk/lib/CodeGeneration.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/CodeGeneration.cpp?rev=144902&r1=144901&r2=144902&view=diff
==============================================================================
--- polly/trunk/lib/CodeGeneration.cpp (original)
+++ polly/trunk/lib/CodeGeneration.cpp Thu Nov 17 06:56:10 2011
@@ -158,7 +158,7 @@
     return S.getRegion();
   }
 
-  Value* makeVectorOperand(Value *operand, int vectorWidth) {
+  Value *makeVectorOperand(Value *operand, int vectorWidth) {
     if (operand->getType()->isVectorTy())
       return operand;
 
@@ -176,7 +176,7 @@
     return Builder.CreateShuffleVector(vector, vector, splatVector);
   }
 
-  Value* getOperand(const Value *oldOperand, ValueMapT &BBMap,
+  Value *getOperand(const Value *oldOperand, ValueMapT &BBMap,
                     ValueMapT *VectorMap = 0) {
     const Instruction *OpInst = dyn_cast<Instruction>(oldOperand);
 
@@ -912,7 +912,7 @@
   }
 
   /// @brief Add a new definition of an openmp subfunction.
-  Function* addOpenMPSubfunction(Module *M) {
+  Function *addOpenMPSubfunction(Module *M) {
     Function *F = Builder.GetInsertBlock()->getParent();
     const std::string &Name = F->getNameStr() + ".omp_subfn";
 
@@ -1608,6 +1608,6 @@
 INITIALIZE_PASS_END(CodeGeneration, "polly-codegen",
                       "Polly - Create LLVM-IR form SCoPs", false, false)
 
-Pass* polly::createCodeGenerationPass() {
+Pass *polly::createCodeGenerationPass() {
   return new CodeGeneration();
 }

Modified: polly/trunk/lib/Exchange/OpenScopExporter.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/OpenScopExporter.cpp?rev=144902&r1=144901&r2=144902&view=diff
==============================================================================
--- polly/trunk/lib/Exchange/OpenScopExporter.cpp (original)
+++ polly/trunk/lib/Exchange/OpenScopExporter.cpp Thu Nov 17 06:56:10 2011
@@ -153,7 +153,7 @@
 
 
   // Statement name
-  const char* entryName = stmt->getBaseName();
+  const char *entryName = stmt->getBaseName();
   Stmt->body = (char*)malloc(sizeof(char) * (strlen(entryName) + 1));
   strcpy(Stmt->body, entryName);
 

Modified: polly/trunk/lib/IndependentBlocks.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/IndependentBlocks.cpp?rev=144902&r1=144901&r2=144902&view=diff
==============================================================================
--- polly/trunk/lib/IndependentBlocks.cpp (original)
+++ polly/trunk/lib/IndependentBlocks.cpp Thu Nov 17 06:56:10 2011
@@ -550,6 +550,6 @@
 INITIALIZE_PASS_END(IndependentBlocks, "polly-independent",
                     "Polly - Create independent blocks", false, false)
 
-Pass* polly::createIndependentBlocksPass() {
+Pass *polly::createIndependentBlocksPass() {
   return new IndependentBlocks();
 }

Modified: polly/trunk/lib/Support/SCEVValidator.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/SCEVValidator.cpp?rev=144902&r1=144901&r2=144902&view=diff
==============================================================================
--- polly/trunk/lib/Support/SCEVValidator.cpp (original)
+++ polly/trunk/lib/Support/SCEVValidator.cpp Thu Nov 17 06:56:10 2011
@@ -25,7 +25,7 @@
   };
 
   ValidatorResult(SCEVType::TYPE type) : type(type) {};
-  ValidatorResult(SCEVType::TYPE type, const SCEV* Expr) : type(type) {
+  ValidatorResult(SCEVType::TYPE type, const SCEV *Expr) : type(type) {
     Parameters.push_back(Expr);
   };
 
@@ -68,7 +68,7 @@
     return ValidatorResult(SCEVType::INT);
   }
 
-  struct ValidatorResult visitTruncateExpr(const SCEVTruncateExpr* Expr) {
+  struct ValidatorResult visitTruncateExpr(const SCEVTruncateExpr *Expr) {
     ValidatorResult Op = visit(Expr->getOperand());
 
     // We currently do not represent a truncate expression as an affine
@@ -80,7 +80,7 @@
     return ValidatorResult (SCEVType::INVALID);
   }
 
-  struct ValidatorResult visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) {
+  struct ValidatorResult visitZeroExtendExpr(const SCEVZeroExtendExpr *Expr) {
     ValidatorResult Op = visit(Expr->getOperand());
 
     // We currently do not represent a zero extend expression as an affine
@@ -92,7 +92,7 @@
     return ValidatorResult(SCEVType::INVALID);
   }
 
-  struct ValidatorResult visitSignExtendExpr(const SCEVSignExtendExpr* Expr) {
+  struct ValidatorResult visitSignExtendExpr(const SCEVSignExtendExpr *Expr) {
     // We currently allow only signed SCEV expressions. In the case of a
     // signed value, a sign extend is a noop.
     //
@@ -100,7 +100,7 @@
     return visit(Expr->getOperand());
   }
 
-  struct ValidatorResult visitAddExpr(const SCEVAddExpr* Expr) {
+  struct ValidatorResult visitAddExpr(const SCEVAddExpr *Expr) {
     ValidatorResult Return(SCEVType::INT);
 
     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
@@ -117,7 +117,7 @@
     return Return;
   }
 
-  struct ValidatorResult visitMulExpr(const SCEVMulExpr* Expr) {
+  struct ValidatorResult visitMulExpr(const SCEVMulExpr *Expr) {
     ValidatorResult Return(SCEVType::INT);
 
     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
@@ -137,7 +137,7 @@
     return Return;
   }
 
-  struct ValidatorResult visitUDivExpr(const SCEVUDivExpr* Expr) {
+  struct ValidatorResult visitUDivExpr(const SCEVUDivExpr *Expr) {
     ValidatorResult LHS = visit(Expr->getLHS());
     ValidatorResult RHS = visit(Expr->getRHS());
 
@@ -150,7 +150,7 @@
     return ValidatorResult(SCEVType::INVALID);
   }
 
-  struct ValidatorResult visitAddRecExpr(const SCEVAddRecExpr* Expr) {
+  struct ValidatorResult visitAddRecExpr(const SCEVAddRecExpr *Expr) {
     if (!Expr->isAffine())
       return ValidatorResult(SCEVType::INVALID);
 
@@ -176,7 +176,7 @@
     return Result;
   }
 
-  struct ValidatorResult visitSMaxExpr(const SCEVSMaxExpr* Expr) {
+  struct ValidatorResult visitSMaxExpr(const SCEVSMaxExpr *Expr) {
     ValidatorResult Return(SCEVType::INT);
 
     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
@@ -192,7 +192,7 @@
     return Return;
   }
 
-  struct ValidatorResult visitUMaxExpr(const SCEVUMaxExpr* Expr) {
+  struct ValidatorResult visitUMaxExpr(const SCEVUMaxExpr *Expr) {
     ValidatorResult Return(SCEVType::PARAM);
 
     // We do not support unsigned operations. If 'Expr' is constant during Scop
@@ -209,7 +209,7 @@
     return Return;
   }
 
-  ValidatorResult visitUnknown(const SCEVUnknown* Expr) {
+  ValidatorResult visitUnknown(const SCEVUnknown *Expr) {
     Value *V = Expr->getValue();
 
     if (isa<UndefValue>(V))

Modified: polly/trunk/lib/Support/ScopHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/ScopHelper.cpp?rev=144902&r1=144901&r2=144902&view=diff
==============================================================================
--- polly/trunk/lib/Support/ScopHelper.cpp (original)
+++ polly/trunk/lib/Support/ScopHelper.cpp Thu Nov 17 06:56:10 2011
@@ -37,7 +37,7 @@
     return true;
   }
 
-  bool visitUnknown(const SCEVUnknown* S) {
+  bool visitUnknown(const SCEVUnknown *S) {
     Value *V = S->getValue();
 
     // An Instruction defined outside the region is invariant.
@@ -57,7 +57,7 @@
     return true;
   }
 
-  bool visitMulExpr(const SCEVMulExpr* S) {
+  bool visitMulExpr(const SCEVMulExpr *S) {
     return visitNAryExpr(S);
   }
 



From grosser at fim.uni-passau.de  Thu Nov 17 06:56:13 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 12:56:13 -0000
Subject: [llvm-commits] [polly] r144903 -
	/polly/trunk/lib/Support/SCEVValidator.cpp
Message-ID: <20111117125613.0FB8E2A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 06:56:12 2011
New Revision: 144903

URL: http://llvm.org/viewvc/llvm-project?rev=144903&view=rev
Log:
SCEVValidator: Fix typo

Modified:
    polly/trunk/lib/Support/SCEVValidator.cpp

Modified: polly/trunk/lib/Support/SCEVValidator.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/SCEVValidator.cpp?rev=144903&r1=144902&r2=144903&view=diff
==============================================================================
--- polly/trunk/lib/Support/SCEVValidator.cpp (original)
+++ polly/trunk/lib/Support/SCEVValidator.cpp Thu Nov 17 06:56:12 2011
@@ -141,7 +141,7 @@
     ValidatorResult LHS = visit(Expr->getLHS());
     ValidatorResult RHS = visit(Expr->getRHS());
 
-    // We currently do not represent a unsigned devision as an affine
+    // We currently do not represent an unsigned devision as an affine
     // expression. If the division is constant during Scop execution we treat it
     // as a parameter, otherwise we bail out.
     if (LHS.isConstant() && RHS.isConstant())



From grosser at fim.uni-passau.de  Thu Nov 17 06:56:15 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 12:56:15 -0000
Subject: [llvm-commits] [polly] r144904 -
	/polly/trunk/lib/Support/SCEVValidator.cpp
Message-ID: <20111117125615.5270E2A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 06:56:14 2011
New Revision: 144904

URL: http://llvm.org/viewvc/llvm-project?rev=144904&view=rev
Log:
SCEVValidator: Restructure the logic of visitAddRecExpr

Suggested by Sebastian Pop.

Modified:
    polly/trunk/lib/Support/SCEVValidator.cpp

Modified: polly/trunk/lib/Support/SCEVValidator.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/SCEVValidator.cpp?rev=144904&r1=144903&r2=144904&view=diff
==============================================================================
--- polly/trunk/lib/Support/SCEVValidator.cpp (original)
+++ polly/trunk/lib/Support/SCEVValidator.cpp Thu Nov 17 06:56:14 2011
@@ -157,23 +157,23 @@
     ValidatorResult Start = visit(Expr->getStart());
     ValidatorResult Recurrence = visit(Expr->getStepRecurrence(SE));
 
-    if (!Start.isValid() || !Recurrence.isValid() || Recurrence.isIV())
+    if (!Start.isValid() || !Recurrence.isConstant())
       return ValidatorResult(SCEVType::INVALID);
 
+    if (R->contains(Expr->getLoop())) {
+      if (Recurrence.isINT()) {
+        ValidatorResult Result(SCEVType::IV);
+        Result.addParamsFrom(Start);
+        return Result;
+      }
 
-    if (!R->contains(Expr->getLoop())) {
-      if (Start.isIV())
-        return ValidatorResult(SCEVType::INVALID);
-      else
-        return ValidatorResult(SCEVType::PARAM, Expr);
+      return ValidatorResult(SCEVType::INVALID);
     }
 
-    if (!Recurrence.isINT())
-      return ValidatorResult(SCEVType::INVALID);
+    if (Start.isConstant())
+      return ValidatorResult(SCEVType::PARAM, Expr);
 
-    ValidatorResult Result(SCEVType::IV);
-    Result.addParamsFrom(Start);
-    return Result;
+    return ValidatorResult(SCEVType::INVALID);
   }
 
   struct ValidatorResult visitSMaxExpr(const SCEVSMaxExpr *Expr) {



From grosser at fim.uni-passau.de  Thu Nov 17 06:56:17 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 12:56:17 -0000
Subject: [llvm-commits] [polly] r144905 -
	/polly/trunk/lib/Support/SCEVValidator.cpp
Message-ID: <20111117125617.5EBB32A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 06:56:17 2011
New Revision: 144905

URL: http://llvm.org/viewvc/llvm-project?rev=144905&view=rev
Log:
SCEVValidator: Document SCEVType and ValidatorResult

Suggested by Sebastian Pop.

Modified:
    polly/trunk/lib/Support/SCEVValidator.cpp

Modified: polly/trunk/lib/Support/SCEVValidator.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/SCEVValidator.cpp?rev=144905&r1=144904&r2=144905&view=diff
==============================================================================
--- polly/trunk/lib/Support/SCEVValidator.cpp (original)
+++ polly/trunk/lib/Support/SCEVValidator.cpp Thu Nov 17 06:56:17 2011
@@ -10,43 +10,77 @@
 using namespace llvm;
 
 namespace SCEVType {
-  enum TYPE {INT, PARAM, IV, INVALID};
+  /// @brief The type of a SCEV
+  ///
+  /// To check for the validity of a SCEV we assign to each SCEV a type. The
+  /// possible types are INT, PARAM, IV and INVALID. The order of the types is
+  /// important. The subexpressions of SCEV with a type X can only have a type
+  /// that is smaller or equal than X.
+  enum TYPE {
+             // An integer value.
+             INT,
+
+             // An expression that is constant during the execution of the Scop,
+             // but that may depend on parameters unknown at compile time.
+             PARAM,
+
+             // An expression that may change during the execution of the SCoP.
+             IV,
+
+             // An invalid expression.
+             INVALID
+  };
 }
 
+/// @brief The result the validator returns for a SCEV expression.
 struct ValidatorResult {
+  /// @brief The type of the expression
   SCEVType::TYPE type;
+
+  /// @brief The set of Parameters in the expression.
   std::vector<const SCEV*> Parameters;
 
+  /// @brief Create an invalid result.
   ValidatorResult() : type(SCEVType::INVALID) {};
 
+  /// @brief The copy constructor
   ValidatorResult(const ValidatorResult &vres) {
     type = vres.type;
     Parameters = vres.Parameters;
   };
 
+  /// @brief Construct a result with a certain type and no parameters.
   ValidatorResult(SCEVType::TYPE type) : type(type) {};
+
+  /// @brief Construct a result with a certain type and a single parameter.
   ValidatorResult(SCEVType::TYPE type, const SCEV *Expr) : type(type) {
     Parameters.push_back(Expr);
   };
 
+  /// @brief Is the analyzed SCEV constant during the execution of the SCoP.
   bool isConstant() {
     return type == SCEVType::INT || type == SCEVType::PARAM;
   }
 
+  /// @brief Is the analyzed SCEV valid.
   bool isValid() {
     return type != SCEVType::INVALID;
   }
 
+  /// @brief Is the analyzed SCEV of type IV.
   bool isIV() {
     return type == SCEVType::IV;
   }
 
+  /// @brief Is the analyzed SCEV of type INT.
   bool isINT() {
     return type == SCEVType::INT;
   }
 
+  /// @brief Add the parameters of Source to this result.
   void addParamsFrom(struct ValidatorResult &Source) {
-    Parameters.insert(Parameters.end(), Source.Parameters.begin(),
+    Parameters.insert(Parameters.end(),
+                      Source.Parameters.begin(),
                       Source.Parameters.end());
   }
 };



From grosser at fim.uni-passau.de  Thu Nov 17 06:56:19 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 12:56:19 -0000
Subject: [llvm-commits] [polly] r144906 -
	/polly/trunk/lib/Support/SCEVValidator.cpp
Message-ID: <20111117125619.A1E7F2A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 06:56:19 2011
New Revision: 144906

URL: http://llvm.org/viewvc/llvm-project?rev=144906&view=rev
Log:
SCEVValidator: Make ValidatorResult a class and enforce the use of wproper accessors

Modified:
    polly/trunk/lib/Support/SCEVValidator.cpp

Modified: polly/trunk/lib/Support/SCEVValidator.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/SCEVValidator.cpp?rev=144906&r1=144905&r2=144906&view=diff
==============================================================================
--- polly/trunk/lib/Support/SCEVValidator.cpp (original)
+++ polly/trunk/lib/Support/SCEVValidator.cpp Thu Nov 17 06:56:19 2011
@@ -33,13 +33,15 @@
 }
 
 /// @brief The result the validator returns for a SCEV expression.
-struct ValidatorResult {
+class ValidatorResult {
   /// @brief The type of the expression
   SCEVType::TYPE type;
 
   /// @brief The set of Parameters in the expression.
   std::vector<const SCEV*> Parameters;
 
+public:
+
   /// @brief Create an invalid result.
   ValidatorResult() : type(SCEVType::INVALID) {};
 
@@ -77,17 +79,32 @@
     return type == SCEVType::INT;
   }
 
+  /// @brief Get the parameters of this validator result.
+  std::vector<const SCEV*> getParameters() {
+    return Parameters;
+  }
+
   /// @brief Add the parameters of Source to this result.
-  void addParamsFrom(struct ValidatorResult &Source) {
+  void addParamsFrom(class ValidatorResult &Source) {
     Parameters.insert(Parameters.end(),
                       Source.Parameters.begin(),
                       Source.Parameters.end());
   }
+
+  /// @brief Merge a result.
+  ///
+  /// This means to merge the parameters and to set the type to the most
+  /// specific type that matches both.
+  void merge(class ValidatorResult &ToMerge) {
+    type = std::max(type, ToMerge.type);
+    addParamsFrom(ToMerge);
+  }
+
 };
 
 /// Check if a SCEV is valid in a SCoP.
 struct SCEVValidator
-  : public SCEVVisitor<SCEVValidator, struct ValidatorResult> {
+  : public SCEVVisitor<SCEVValidator, class ValidatorResult> {
 private:
   const Region *R;
   ScalarEvolution &SE;
@@ -98,11 +115,11 @@
                 const Value *BaseAddress) : R(R), SE(SE),
     BaseAddress(BaseAddress) {};
 
-  struct ValidatorResult visitConstant(const SCEVConstant *Constant) {
+  class ValidatorResult visitConstant(const SCEVConstant *Constant) {
     return ValidatorResult(SCEVType::INT);
   }
 
-  struct ValidatorResult visitTruncateExpr(const SCEVTruncateExpr *Expr) {
+  class ValidatorResult visitTruncateExpr(const SCEVTruncateExpr *Expr) {
     ValidatorResult Op = visit(Expr->getOperand());
 
     // We currently do not represent a truncate expression as an affine
@@ -111,22 +128,22 @@
     if (Op.isConstant())
       return ValidatorResult(SCEVType::PARAM, Expr);
 
-    return ValidatorResult (SCEVType::INVALID);
+    return ValidatorResult(SCEVType::INVALID);
   }
 
-  struct ValidatorResult visitZeroExtendExpr(const SCEVZeroExtendExpr *Expr) {
+  class ValidatorResult visitZeroExtendExpr(const SCEVZeroExtendExpr *Expr) {
     ValidatorResult Op = visit(Expr->getOperand());
 
     // We currently do not represent a zero extend expression as an affine
     // expression. If it is constant during Scop execution, we treat it as a
     // parameter, otherwise we bail out.
     if (Op.isConstant())
-      return ValidatorResult (SCEVType::PARAM, Expr);
+      return ValidatorResult(SCEVType::PARAM, Expr);
 
     return ValidatorResult(SCEVType::INVALID);
   }
 
-  struct ValidatorResult visitSignExtendExpr(const SCEVSignExtendExpr *Expr) {
+  class ValidatorResult visitSignExtendExpr(const SCEVSignExtendExpr *Expr) {
     // We currently allow only signed SCEV expressions. In the case of a
     // signed value, a sign extend is a noop.
     //
@@ -134,7 +151,7 @@
     return visit(Expr->getOperand());
   }
 
-  struct ValidatorResult visitAddExpr(const SCEVAddExpr *Expr) {
+  class ValidatorResult visitAddExpr(const SCEVAddExpr *Expr) {
     ValidatorResult Return(SCEVType::INT);
 
     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
@@ -143,35 +160,33 @@
       if (!Op.isValid())
         return ValidatorResult(SCEVType::INVALID);
 
-      Return.type = std::max(Return.type, Op.type);
-      Return.addParamsFrom(Op);
+      Return.merge(Op);
     }
 
     // TODO: Check for NSW and NUW.
     return Return;
   }
 
-  struct ValidatorResult visitMulExpr(const SCEVMulExpr *Expr) {
+  class ValidatorResult visitMulExpr(const SCEVMulExpr *Expr) {
     ValidatorResult Return(SCEVType::INT);
 
     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
       ValidatorResult Op = visit(Expr->getOperand(i));
 
-      if (Op.type == SCEVType::INT)
+      if (Op.isINT())
         continue;
 
-      if (Op.type == SCEVType::INVALID || Return.type != SCEVType::INT)
+      if (!Op.isValid() || !Return.isINT())
         return ValidatorResult(SCEVType::INVALID);
 
-      Return.type = Op.type;
-      Return.addParamsFrom(Op);
+      Return.merge(Op);
     }
 
     // TODO: Check for NSW and NUW.
     return Return;
   }
 
-  struct ValidatorResult visitUDivExpr(const SCEVUDivExpr *Expr) {
+  class ValidatorResult visitUDivExpr(const SCEVUDivExpr *Expr) {
     ValidatorResult LHS = visit(Expr->getLHS());
     ValidatorResult RHS = visit(Expr->getRHS());
 
@@ -184,7 +199,7 @@
     return ValidatorResult(SCEVType::INVALID);
   }
 
-  struct ValidatorResult visitAddRecExpr(const SCEVAddRecExpr *Expr) {
+  class ValidatorResult visitAddRecExpr(const SCEVAddRecExpr *Expr) {
     if (!Expr->isAffine())
       return ValidatorResult(SCEVType::INVALID);
 
@@ -210,7 +225,7 @@
     return ValidatorResult(SCEVType::INVALID);
   }
 
-  struct ValidatorResult visitSMaxExpr(const SCEVSMaxExpr *Expr) {
+  class ValidatorResult visitSMaxExpr(const SCEVSMaxExpr *Expr) {
     ValidatorResult Return(SCEVType::INT);
 
     for (int i = 0, e = Expr->getNumOperands(); i < e; ++i) {
@@ -219,14 +234,13 @@
       if (!Op.isValid())
         return ValidatorResult(SCEVType::INVALID);
 
-      Return.type = std::max(Return.type, Op.type);
-      Return.addParamsFrom(Op);
+      Return.merge(Op);
     }
 
     return Return;
   }
 
-  struct ValidatorResult visitUMaxExpr(const SCEVUMaxExpr *Expr) {
+  class ValidatorResult visitUMaxExpr(const SCEVUMaxExpr *Expr) {
     ValidatorResult Return(SCEVType::PARAM);
 
     // We do not support unsigned operations. If 'Expr' is constant during Scop
@@ -237,7 +251,7 @@
       if (!Op.isConstant())
         return ValidatorResult(SCEVType::INVALID);
 
-      Return.addParamsFrom(Op);
+      Return.merge(Op);
     }
 
     return Return;
@@ -282,7 +296,7 @@
     SCEVValidator Validator(R, SE, BaseAddress);
     ValidatorResult Result = Validator.visit(Expr);
 
-    return Result.Parameters;
+    return Result.getParameters();
   }
 }
 



From grosser at fim.uni-passau.de  Thu Nov 17 06:56:21 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 12:56:21 -0000
Subject: [llvm-commits] [polly] r144907 -
	/polly/trunk/lib/Support/SCEVValidator.cpp
Message-ID: <20111117125621.A8D872A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 06:56:21 2011
New Revision: 144907

URL: http://llvm.org/viewvc/llvm-project?rev=144907&view=rev
Log:
SCEVValidator: Fix coding standards in ValidatorResult

Modified:
    polly/trunk/lib/Support/SCEVValidator.cpp

Modified: polly/trunk/lib/Support/SCEVValidator.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/SCEVValidator.cpp?rev=144907&r1=144906&r2=144907&view=diff
==============================================================================
--- polly/trunk/lib/Support/SCEVValidator.cpp (original)
+++ polly/trunk/lib/Support/SCEVValidator.cpp Thu Nov 17 06:56:21 2011
@@ -35,7 +35,7 @@
 /// @brief The result the validator returns for a SCEV expression.
 class ValidatorResult {
   /// @brief The type of the expression
-  SCEVType::TYPE type;
+  SCEVType::TYPE Type;
 
   /// @brief The set of Parameters in the expression.
   std::vector<const SCEV*> Parameters;
@@ -43,40 +43,40 @@
 public:
 
   /// @brief Create an invalid result.
-  ValidatorResult() : type(SCEVType::INVALID) {};
+  ValidatorResult() : Type(SCEVType::INVALID) {};
 
   /// @brief The copy constructor
-  ValidatorResult(const ValidatorResult &vres) {
-    type = vres.type;
-    Parameters = vres.Parameters;
+  ValidatorResult(const ValidatorResult &Source) {
+    Type = Source.Type;
+    Parameters = Source.Parameters;
   };
 
   /// @brief Construct a result with a certain type and no parameters.
-  ValidatorResult(SCEVType::TYPE type) : type(type) {};
+  ValidatorResult(SCEVType::TYPE Type) : Type(Type) {};
 
   /// @brief Construct a result with a certain type and a single parameter.
-  ValidatorResult(SCEVType::TYPE type, const SCEV *Expr) : type(type) {
+  ValidatorResult(SCEVType::TYPE Type, const SCEV *Expr) : Type(Type) {
     Parameters.push_back(Expr);
   };
 
   /// @brief Is the analyzed SCEV constant during the execution of the SCoP.
   bool isConstant() {
-    return type == SCEVType::INT || type == SCEVType::PARAM;
+    return Type == SCEVType::INT || Type == SCEVType::PARAM;
   }
 
   /// @brief Is the analyzed SCEV valid.
   bool isValid() {
-    return type != SCEVType::INVALID;
+    return Type != SCEVType::INVALID;
   }
 
-  /// @brief Is the analyzed SCEV of type IV.
+  /// @brief Is the analyzed SCEV of Type IV.
   bool isIV() {
-    return type == SCEVType::IV;
+    return Type == SCEVType::IV;
   }
 
-  /// @brief Is the analyzed SCEV of type INT.
+  /// @brief Is the analyzed SCEV of Type INT.
   bool isINT() {
-    return type == SCEVType::INT;
+    return Type == SCEVType::INT;
   }
 
   /// @brief Get the parameters of this validator result.
@@ -93,13 +93,12 @@
 
   /// @brief Merge a result.
   ///
-  /// This means to merge the parameters and to set the type to the most
-  /// specific type that matches both.
+  /// This means to merge the parameters and to set the Type to the most
+  /// specific Type that matches both.
   void merge(class ValidatorResult &ToMerge) {
-    type = std::max(type, ToMerge.type);
+    Type = std::max(Type, ToMerge.Type);
     addParamsFrom(ToMerge);
   }
-
 };
 
 /// Check if a SCEV is valid in a SCoP.



From grosser at fim.uni-passau.de  Thu Nov 17 06:56:23 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 12:56:23 -0000
Subject: [llvm-commits] [polly] r144908 - /polly/trunk/lib/Analysis/Makefile
Message-ID: <20111117125623.CA3672A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 06:56:23 2011
New Revision: 144908

URL: http://llvm.org/viewvc/llvm-project?rev=144908&view=rev
Log:
autoconf: Specify that pollyanalysis depends on pollysupport

Modified:
    polly/trunk/lib/Analysis/Makefile

Modified: polly/trunk/lib/Analysis/Makefile
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/Makefile?rev=144908&r1=144907&r2=144908&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/Makefile (original)
+++ polly/trunk/lib/Analysis/Makefile Thu Nov 17 06:56:23 2011
@@ -6,6 +6,7 @@
 LEVEL=../..
 
 LIBRARYNAME=pollyanalysis
+USEDLIBS = pollysupport.a
 BUILD_ARCHIVE = 1
 
 CPP.Flags += $(POLLY_INC)



From grosser at fim.uni-passau.de  Wed Nov 16 05:14:06 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 16 Nov 2011 12:14:06 +0100
Subject: [llvm-commits] [polly] r142770 -
	/polly/trunk/lib/ScheduleOptimizer.cpp
In-Reply-To: <CAE5reQ+UF36qOyoP_fCEqaMmnneskrFtTHzApucqEBS=x6Amqg@mail.gmail.com>
References: <20111023205926.E87883524006@llvm.org>
	<CAE5reQ+UF36qOyoP_fCEqaMmnneskrFtTHzApucqEBS=x6Amqg@mail.gmail.com>
Message-ID: <4EC39AFE.40604@fim.uni-passau.de>

On 11/15/2011 10:24 PM, Sebastian Pop wrote:
> On Sun, Oct 23, 2011 at 3:59 PM, Tobias Grosser
> <grosser at fim.uni-passau.de>  wrote:
>> Author: grosser
>> Date: Sun Oct 23 15:59:26 2011
>> New Revision: 142770
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=142770&view=rev
>> Log:
>> ScheduleOptimizer: Allow to disable tiling
>>
>> Modified:
>>     polly/trunk/lib/ScheduleOptimizer.cpp
>>
>> Modified: polly/trunk/lib/ScheduleOptimizer.cpp
>> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=142770&r1=142769&r2=142770&view=diff
>> ==============================================================================
>> --- polly/trunk/lib/ScheduleOptimizer.cpp (original)
>> +++ polly/trunk/lib/ScheduleOptimizer.cpp Sun Oct 23 15:59:26 2011
>> @@ -38,6 +38,11 @@
>>   using namespace polly;
>>
>>   static cl::opt<bool>
>> +DisableTiling("polly-no-tiling",
>> +         cl::desc("Disable tiling in the isl scheduler"), cl::Hidden,
>> +         cl::init(false));
>> +
>> +static cl::opt<bool>
>>   Prevector("enable-schedule-prevector",
>>           cl::desc("Enable the prevectorization in the scheduler"), cl::Hidden,
>>           cl::value_desc("Prevectorization enabled"),
>> @@ -202,14 +207,17 @@
>>    isl_union_map *tileUnionMap;
>>
>>    partialSchedule = isl_band_get_partial_schedule(band);
>> -  ctx = isl_union_map_get_ctx(partialSchedule);
>> -  Space= isl_union_map_get_space(partialSchedule);
>> -  scheduleDimensions = isl_band_n_member(band);
>> -
>> -  tileMap = getTileMap(ctx, scheduleDimensions, Space);
>> -  tileUnionMap = isl_union_map_from_map(isl_map_from_basic_map(tileMap));
>> -  tileUnionMap = isl_union_map_align_params(tileUnionMap, Space);
>> -  partialSchedule = isl_union_map_apply_range(partialSchedule, tileUnionMap);
>
> Could you please rewrite this with an early return like this?
>
> if (DisableTiling)
>    return partialSchedule;
>
> See http://llvm.org/docs/CodingStandards.html#hl_earlyexit

True.

Changed in commit: "ScheduleOptimizer: Use early exit"

Tobias


From grosser at fim.uni-passau.de  Wed Nov 16 05:28:12 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 16 Nov 2011 12:28:12 +0100
Subject: [llvm-commits] [polly] r142773 - in /polly/trunk:
 lib/RegisterPasses.cpp www/example_load_Polly_into_clang.html
In-Reply-To: <CAE5reQJWZXMetPsxqtyLuK7Y_PZAFCmduBDNZ0syoMs+8h5z3w@mail.gmail.com>
References: <20111023205935.E768C3524009@llvm.org>
	<CAE5reQJWZXMetPsxqtyLuK7Y_PZAFCmduBDNZ0syoMs+8h5z3w@mail.gmail.com>
Message-ID: <4EC39E4C.9020508@fim.uni-passau.de>

On 11/15/2011 10:42 PM, Sebastian Pop wrote:
> On Sun, Oct 23, 2011 at 3:59 PM, Tobias Grosser
> <grosser at fim.uni-passau.de>  wrote:
>> Author: grosser
>> Date: Sun Oct 23 15:59:35 2011
>> New Revision: 142773
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=142773&view=rev
>> Log:
>> Add an option to run the PoCC optimizer
>>
>> Modified:
>>     polly/trunk/lib/RegisterPasses.cpp
>>     polly/trunk/www/example_load_Polly_into_clang.html
>>
>> Modified: polly/trunk/lib/RegisterPasses.cpp
>> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/RegisterPasses.cpp?rev=142773&r1=142772&r2=142773&view=diff
>> ==============================================================================
>> --- polly/trunk/lib/RegisterPasses.cpp (original)
>> +++ polly/trunk/lib/RegisterPasses.cpp Sun Oct 23 15:59:35 2011
>> @@ -37,6 +37,10 @@
>>         cl::desc("Disable Polly Code Generation"), cl::Hidden,
>>         cl::init(false));
>>   static cl::opt<bool>
>> +UsePocc("polly-use-pocc",
>> +       cl::desc("Use the PoCC optimizer instead of the one in isl"), cl::Hidden,
>> +       cl::init(false));
>> +static cl::opt<bool>
>>   PollyViewer("polly-show",
>>         cl::desc("Enable the Polly DOT viewer in -O3"), cl::Hidden,
>>         cl::value_desc("Run the Polly DOT viewer at -O3"),
>> @@ -124,8 +128,21 @@
>>    if (PollyOnlyPrinter)
>>      PM.add(polly::createDOTOnlyPrinterPass());
>>
>> -  if (!DisableScheduler)
>> -    PM.add(polly::createIslScheduleOptimizerPass());
>> +  if (!DisableScheduler) {
>
> Could you please avoid double negation: what about declaring
> a bool EnableScheduler and then use that?
>
>> +    if (!UsePocc)
>> +      PM.add(polly::createIslScheduleOptimizerPass());
>> +    else {
>
> Also here, please use the positive condition to avoid the negation:
>
> if (UsePocc) {
>    #ifdef SCOPLIB_FOUND
>    etc.
> } else {
>    PM.add(polly::createIslScheduleOptimizerPass());
> }
>
>> +#ifdef SCOPLIB_FOUND
>> +      PM.add(polly::createPoccPass());
>> +#else
>> +      errs()<<  "Polly is compiled without scoplib support. As scoplib is"
>> +<<  "required to run PoCC, PoCC is also not available. Falling"
>> +<<  "back to the isl optimizer.\n";
>> +      PM.add(polly::createIslScheduleOptimizerPass());
>> +#endif
>> +    }
>> +
>> +  }
>>
>>    if (!DisableCodegen)
>>      PM.add(polly::createCodeGenerationPass());

All fixed in "RegisterPasses: Avoid double negation"

Thanks for this pointer

Tobi

From grosser at fim.uni-passau.de  Wed Nov 16 06:09:09 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 16 Nov 2011 13:09:09 +0100
Subject: [llvm-commits] [polly] r143576 -
	/polly/trunk/lib/Analysis/ScopDetection.cpp
In-Reply-To: <CAE5reQ+gmwvkcismTBhv7jqOZQWYhFMD7p_LP9RRHhaZenfKnw@mail.gmail.com>
References: <20111102214008.8D8D72A6C12C@llvm.org>
	<CAE5reQ+gmwvkcismTBhv7jqOZQWYhFMD7p_LP9RRHhaZenfKnw@mail.gmail.com>
Message-ID: <4EC3A7E5.3080606@fim.uni-passau.de>

On 11/16/2011 05:38 AM, Sebastian Pop wrote:
> On Wed, Nov 2, 2011 at 4:40 PM, Tobias Grosser
> <grosser at fim.uni-passau.de>  wrote:
>> Author: grosser
>> Date: Wed Nov  2 16:40:08 2011
>> New Revision: 143576
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=143576&view=rev
>> Log:
>> ScopDetection: Add new SCEV Validator
>>
>> The SCEV Validator is used to check if the bound of a loop can be translated
>> into a polyhedral constraint. The new validator is more general as the check
>> used previously and e.g. allows bounds like 'smax 1, %a'. At the moment, we
>> only allow signed comparisons. Also, the new validator is only used to verify
>> loop bounds. Memory accesses are still handled by the old validator.
>>
>> Modified:
>>     polly/trunk/lib/Analysis/ScopDetection.cpp
>>
>> Modified: polly/trunk/lib/Analysis/ScopDetection.cpp
>> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=143576&r1=143575&r2=143576&view=diff
>> ==============================================================================
>> --- polly/trunk/lib/Analysis/ScopDetection.cpp (original)
>> +++ polly/trunk/lib/Analysis/ScopDetection.cpp Wed Nov  2 16:40:08 2011
>> @@ -109,6 +109,162 @@
>>   //===----------------------------------------------------------------------===//
>>   // ScopDetection.
>>
>> +namespace SCEVType {
>> +  enum TYPE {INT, PARAM, IV, INVALID};
>> +}
>> +
>> +/// Check if a SCEV is valid in a SCoP.
>> +struct SCEVValidator : public SCEVVisitor<SCEVValidator, SCEVType::TYPE>  {
>> +private:
>> +  const Region *R;
>> +  ScalarEvolution&SE;
>> +  const Value **BaseAddress;
>> +
>> +public:
>> +  static bool isValid(const Region *R, const SCEV *Scev,
>> +                      ScalarEvolution&SE,
>> +                      const Value **BaseAddress = NULL) {
>> +    if (isa<SCEVCouldNotCompute>(Scev))
>> +      return false;
>> +
>> +    SCEVValidator Validator(R, SE, BaseAddress);
>> +    return Validator.visit(Scev) != SCEVType::INVALID;
>> +  }
>> +
>> +  SCEVValidator(const Region *R, ScalarEvolution&SE,
>> +                const Value **BaseAddress) : R(R), SE(SE),
>> +    BaseAddress(BaseAddress) {};
>> +
>> +  SCEVType::TYPE visitConstant(const SCEVConstant *Constant) {
>> +    return SCEVType::INT;
>> +  }
>> +
>> +  SCEVType::TYPE visitTruncateExpr(const SCEVTruncateExpr* Expr) {
>
> Please use a single way to place the *, i.e., SCEVTruncateExpr *Expr
> also occurs below, several times in several inconsistent ways.

Fixed in "Fix placement of the '*' that marks a pointer"


>> +    SCEVType::TYPE Op = visit(Expr->getOperand());
>> +
>> +    // We cannot represent this as a affine expression yet. If it is constant
>
> s/a affine/an affine/
>
>> +    // during Scop execution treat this as a parameter, otherwise bail out.
>> +    if (Op == SCEVType::INT || Op == SCEVType::PARAM)
>> +      return SCEVType::PARAM;
>> +
>> +    return SCEVType::INVALID;
>> +  }
>> +
>> +  SCEVType::TYPE visitZeroExtendExpr(const SCEVZeroExtendExpr * Expr) {
>> +    SCEVType::TYPE Op = visit(Expr->getOperand());
>> +
>> +    // We cannot represent this as a affine expression yet. If it is constant
>
> s/a affine/an affine/

This was already fixed in a later commit.

>> +    // during Scop execution treat this as a parameter, otherwise bail out.
>> +    if (Op == SCEVType::INT || Op == SCEVType::PARAM)
>> +      return SCEVType::PARAM;
>> +
>> +    return SCEVType::INVALID;
>> +  }
>> +
>> +  SCEVType::TYPE visitSignExtendExpr(const SCEVSignExtendExpr* Expr) {
>> +    // Assuming the value is signed, a sign extension is basically a noop.
>> +    // TODO: Reconsider this as soon as we support unsigned values.
>> +    return visit(Expr->getOperand());
>> +  }
>> +
>> +  SCEVType::TYPE visitAddExpr(const SCEVAddExpr* Expr) {
>> +    SCEVType::TYPE Return = SCEVType::INT;
>> +
>> +    for (int i = 0, e = Expr->getNumOperands(); i<  e; ++i) {
>> +      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
>> +      Return = std::max(Return, OpType);
>> +    }
>> +
>> +    // TODO: Check for NSW and NUW.
>> +    return Return;
>> +  }
>> +
>> +  SCEVType::TYPE visitMulExpr(const SCEVMulExpr* Expr) {
>> +    SCEVType::TYPE Return = SCEVType::INT;
>> +
>> +    for (int i = 0, e = Expr->getNumOperands(); i<  e; ++i) {
>> +      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
>> +
>> +      if (OpType == SCEVType::INVALID)
>> +        return SCEVType::INVALID;
>> +
>> +      if (OpType == SCEVType::IV) {
>> +        if (Return == SCEVType::PARAM || Return == SCEVType::IV)
>> +          return SCEVType::INVALID;
>> +
>> +        Return = OpType;
>> +        continue;
>> +      }
>> +
>> +      if (OpType == SCEVType::PARAM) {
>> +        if (Return == SCEVType::PARAM)
>> +          return SCEVType::INVALID;
>> +
>> +        Return = SCEVType::PARAM;
>> +        continue;
>> +      }
>> +
>> +      // OpType == SCEVType::INT, no need to change anything.
>> +    }
>> +
>> +    // TODO: Check for NSW and NUW.
>> +    return Return;
>> +  }
>> +
>> +  SCEVType::TYPE visitUDivExpr(const SCEVUDivExpr* Expr) {
>> +    // We do not yet support unsigned operations.
>> +    return SCEVType::INVALID;
>> +  }
>> +
>> +  SCEVType::TYPE visitAddRecExpr(const SCEVAddRecExpr* Expr) {
>> +    if (!Expr->isAffine())
>> +      return SCEVType::INVALID;
>> +
>> +    SCEVType::TYPE Start = visit(Expr->getStart());
>> +
>> +    if (Start == SCEVType::INVALID)
>> +      return Start;
>> +
>> +    SCEVType::TYPE Recurrence = visit(Expr->getStepRecurrence(SE));
>
> In the following code, why not doing this instead?
>
>
>     if (Recurrence == SCEVType::INT)
>       return SCEVType::IV;
>
>     return SCEVType::INVALID;

I used the chance to reorganize the structure of the whole function.
I hope it is now better to understand:

Committed in "SCEVValidator: Restructure the logic of visitAddRecExpr"

>> +    if (Recurrence != SCEVType::INT)
>> +      return SCEVType::INVALID;
>> +
>> +    return SCEVType::PARAM;
>
> I don't see why you would return a PARAM for an addrec with a constant step.
> I would return SCEVType::IV.

This one is already fixed in trunk.
>
>> +  }
>> +
>> +  SCEVType::TYPE visitSMaxExpr(const SCEVSMaxExpr* Expr) {
>> +    SCEVType::TYPE Return = SCEVType::INT;
>> +
>> +    for (int i = 0, e = Expr->getNumOperands(); i<  e; ++i) {
>> +      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
>> +
>> +      if (OpType == SCEVType::INVALID)
>> +        return SCEVType::INVALID;
>> +      if (OpType == SCEVType::PARAM)
>> +        Return = SCEVType::PARAM;
>> +    }
>> +
>> +    return Return;
>> +  }
>> +
>> +  SCEVType::TYPE visitUMaxExpr(const SCEVUMaxExpr* Expr) {
>> +    // We do not yet support unsigned operations. If 'Expr' is constant
>> +    // during Scop execution treat this as a parameter, otherwise bail out.
>> +    for (int i = 0, e = Expr->getNumOperands(); i<  e; ++i) {
>> +      SCEVType::TYPE OpType = visit(Expr->getOperand(i));
>> +
>> +      if (OpType != SCEVType::INT&&  OpType != SCEVType::PARAM)
>> +        return SCEVType::PARAM;
>
> Probably this first return should have been SCEVType::INVALID?
Yes, already fixed in trunk.

>
>> +    }
>> +
>> +    return SCEVType::PARAM;
>> +  }
>
> You should check the logic in this function, as I see that you always
> return SCEVType::PARAM.

Already fixed in trunk.

>> +
>> +  SCEVType::TYPE visitUnknown(const SCEVUnknown* Expr) {
>> +    return SCEVType::PARAM;
>> +  }
>
> Really?  I would have returned INVALID instead of PARAM for an unknown SCEV.

;-)

Unknown is the name SCEV uses for valid variables where the actual value
is unknown. This means SCEVUnknowns are references to llvm::Value* and 
represent e.g. variables like '%a'. So yes, an SCEVUnknown is definitely 
a parameter.

Thanks for the review
Tobi

From grosser at fim.uni-passau.de  Wed Nov 16 07:15:57 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 16 Nov 2011 14:15:57 +0100
Subject: [llvm-commits] [polly] r143692 -
	/polly/trunk/lib/Analysis/ScopDetection.cpp
In-Reply-To: <CAE5reQJ1mFsVtQxU_m85WAP149dSe-cTbUGNsYbRbWRs2TSdiw@mail.gmail.com>
References: <20111104100808.A50192A6C12D@llvm.org>
	<CAE5reQJ1mFsVtQxU_m85WAP149dSe-cTbUGNsYbRbWRs2TSdiw@mail.gmail.com>
Message-ID: <4EC3B78D.8080500@fim.uni-passau.de>

On 11/16/2011 05:55 AM, Sebastian Pop wrote:
> On Fri, Nov 4, 2011 at 5:08 AM, Tobias Grosser
> <grosser at fim.uni-passau.de>  wrote:
>> Author: grosser
>> Date: Fri Nov  4 05:08:08 2011
>> New Revision: 143692
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=143692&view=rev
>> Log:
>> ScopDetection: Small fixes and improvements for the SCEVValidator
>>
>> These fixes were part of a code audit of the SCEVValidator.
>>
>> Modified:
>>     polly/trunk/lib/Analysis/ScopDetection.cpp
>>
>> Modified: polly/trunk/lib/Analysis/ScopDetection.cpp
>> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=143692&r1=143691&r2=143692&view=diff
>> ==============================================================================
>> --- polly/trunk/lib/Analysis/ScopDetection.cpp (original)
>> +++ polly/trunk/lib/Analysis/ScopDetection.cpp Fri Nov  4 05:08:08 2011
>>    SCEVType::TYPE visitUDivExpr(const SCEVUDivExpr* Expr) {
>> -    // We do not yet support unsigned operations.
>> +    SCEVType::TYPE LHS = visit(Expr->getLHS());
>> +    SCEVType::TYPE RHS = visit(Expr->getRHS());
>> +
>> +    // We currently do not represent a unsigned devision as an affine
>
> s/a unsigned/an unsigned/

Fixed in current.

>> -    if (Start == SCEVType::INVALID)
>> -      return Start;
>> +    if (Start == SCEVType::INVALID ||
>> +        Recurrence == SCEVType::INVALID ||
>> +        Recurrence == SCEVType::IV)
>> +      return SCEVType::INVALID;
>> +
>> +    if (!R->contains(Expr->getLoop())) {
>> +      if (Start == SCEVType::IV)
>> +        return SCEVType::INVALID;
>> +      else
>> +        return SCEVType::PARAM;
>> +    }
>>
>> -    SCEVType::TYPE Recurrence = visit(Expr->getStepRecurrence(SE));
>>      if (Recurrence != SCEVType::INT)
>>        return SCEVType::INVALID;
>>
>> -    return SCEVType::PARAM;
>> +    return SCEVType::IV;
>
> Good!
> I see that you got this one corrected.
>
>>    }
>>    SCEVType::TYPE visitUMaxExpr(const SCEVUMaxExpr* Expr) {
>> -    // We do not yet support unsigned operations. If 'Expr' is constant
>> -    // during Scop execution treat this as a parameter, otherwise bail out.
>> +    // We do not support unsigned operations. If 'Expr' is constant during Scop
>> +    // execution we treat this as a parameter, otherwise we bail out.
>>      for (int i = 0, e = Expr->getNumOperands(); i<  e; ++i) {
>>        SCEVType::TYPE OpType = visit(Expr->getOperand(i));
>>
>>        if (OpType != SCEVType::INT&&  OpType != SCEVType::PARAM)
>> -        return SCEVType::PARAM;
>> +        return SCEVType::INVALID;
>
> And this one as well looks good after this change.

I should do the review before committing. Sorry committing incomplete stuff.

Tobi

From grosser at fim.uni-passau.de  Wed Nov 16 07:22:09 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 16 Nov 2011 14:22:09 +0100
Subject: [llvm-commits] [polly] r143958 -
	/polly/trunk/lib/Analysis/ScopDetection.cpp
In-Reply-To: <CAE5reQJKwC0rn33Wo2Y-XArBxTmU4fKb=W-HGByF26CkpD6qPg@mail.gmail.com>
References: <20111107125842.302162A6C12C@llvm.org>
	<CAE5reQJKwC0rn33Wo2Y-XArBxTmU4fKb=W-HGByF26CkpD6qPg@mail.gmail.com>
Message-ID: <4EC3B901.5090409@fim.uni-passau.de>

On 11/16/2011 06:04 AM, Sebastian Pop wrote:
> On Mon, Nov 7, 2011 at 6:58 AM, Tobias Grosser
> <grosser at fim.uni-passau.de>  wrote:
>> Author: grosser
>> Date: Mon Nov  7 06:58:41 2011
>> New Revision: 143958
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=143958&view=rev
>> Log:
>> ScopDetection: Add ValidatorResult class
>> -    return SCEVType::PARAM;
>> +    if (BaseAddress)
>> +      return ValidatorResult(SCEVType::PARAM);
>> +    else
>> +      return ValidatorResult(SCEVType::PARAM);
>
> This change looks strange: why are you returning the same thing in
> both branches?

It is strange and was probablly buggy. The reason for the ugly code here 
is that we extracted the base address during the validation of the SCEV. 
This approach was problematic in several ways and had the limitation 
that we did not support parameters in access functions.

Now we extract the base address before validating the SCEV, such that 
any special handling for the base address in the SCEV validator can be 
removed. The only one left is a check that the base address is really 
removed from the SCEV.

Cheers
Tobi

From grosser at fim.uni-passau.de  Wed Nov 16 07:39:16 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Wed, 16 Nov 2011 14:39:16 +0100
Subject: [llvm-commits] [polly] r143960 - in /polly/trunk:
 include/polly/Support/SCEVValidator.h lib/Analysis/ScopDetection.cpp
 lib/Support/CMakeLists.txt lib/Support/SCEVValidator.cpp
In-Reply-To: <CAE5reQKfvzQZ7Mjr5gAmJawiVO9AP5Q+qA4G48PB3kMCifpK4g@mail.gmail.com>
References: <20111107125854.552013524001@llvm.org>
	<CAE5reQKfvzQZ7Mjr5gAmJawiVO9AP5Q+qA4G48PB3kMCifpK4g@mail.gmail.com>
Message-ID: <4EC3BD04.5060101@fim.uni-passau.de>

On 11/16/2011 06:14 AM, Sebastian Pop wrote:
> On Mon, Nov 7, 2011 at 6:58 AM, Tobias Grosser
> <grosser at fim.uni-passau.de>  wrote:
>> Author: grosser
>> Date: Mon Nov  7 06:58:54 2011
>> New Revision: 143960
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=143960&view=rev
>> Log:
>> SCEVValidator: Move into own file
>> Added: polly/trunk/lib/Support/SCEVValidator.cpp
>> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/SCEVValidator.cpp?rev=143960&view=auto
>> ==============================================================================
>> --- polly/trunk/lib/Support/SCEVValidator.cpp (added)
>> +++ polly/trunk/lib/Support/SCEVValidator.cpp Mon Nov  7 06:58:54 2011
>> @@ -0,0 +1,231 @@

[...]

>> +using namespace llvm;
>> +
>> +namespace SCEVType {
>> +  enum TYPE {INT, PARAM, IV, INVALID};
>
> You should probably document what each stands for, and also document
> the fact that the order in which the elements of the enum are arranged is
> important as we call max on their value.

You are right.

Documentation added in

"SCEVValidator: Document SCEVType and ValidatorResult"

Tobi

From grosser at fim.uni-passau.de  Thu Nov 17 08:52:36 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 14:52:36 -0000
Subject: [llvm-commits] [polly] r144909 - in /polly/trunk/lib:
 Analysis/ScopDetection.cpp Analysis/ScopInfo.cpp Cloog.cpp
 CodeGeneration.cpp Exchange/JSONExporter.cpp Exchange/ScopLib.cpp
 Exchange/ScopLibExporter.cpp Exchange/ScopLibImporter.cpp
 RegionSimplify.cpp
Message-ID: <20111117145237.1209B2A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 08:52:36 2011
New Revision: 144909

URL: http://llvm.org/viewvc/llvm-project?rev=144909&view=rev
Log:
Do not use getNameStr() anymore.

Instead we switch to the recommended getName(). This fixes compilation with
recent versions of LLVM.

Modified:
    polly/trunk/lib/Analysis/ScopDetection.cpp
    polly/trunk/lib/Analysis/ScopInfo.cpp
    polly/trunk/lib/Cloog.cpp
    polly/trunk/lib/CodeGeneration.cpp
    polly/trunk/lib/Exchange/JSONExporter.cpp
    polly/trunk/lib/Exchange/ScopLib.cpp
    polly/trunk/lib/Exchange/ScopLibExporter.cpp
    polly/trunk/lib/Exchange/ScopLibImporter.cpp
    polly/trunk/lib/RegionSimplify.cpp

Modified: polly/trunk/lib/Analysis/ScopDetection.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopDetection.cpp?rev=144909&r1=144908&r2=144909&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopDetection.cpp (original)
+++ polly/trunk/lib/Analysis/ScopDetection.cpp Thu Nov 17 08:52:36 2011
@@ -154,7 +154,7 @@
   BranchInst *Br = dyn_cast<BranchInst>(TI);
 
   if (!Br)
-    INVALID(CFG, "Non branch instruction terminates BB: " + BB.getNameStr());
+    INVALID(CFG, "Non branch instruction terminates BB: " + BB.getName());
 
   if (Br->isUnconditional()) return true;
 
@@ -163,11 +163,11 @@
   // UndefValue is not allowed as condition.
   if (isa<UndefValue>(Condition))
     INVALID(AffFunc, "Condition based on 'undef' value in BB: "
-                     + BB.getNameStr());
+                     + BB.getName());
 
   // Only Constant and ICmpInst are allowed as condition.
   if (!(isa<Constant>(Condition) || isa<ICmpInst>(Condition)))
-    INVALID(AffFunc, "Condition in BB '" + BB.getNameStr() + "' neither "
+    INVALID(AffFunc, "Condition in BB '" + BB.getName() + "' neither "
                      "constant nor an icmp instruction");
 
   // Allow perfectly nested conditions.
@@ -185,14 +185,14 @@
     // Are both operands of the ICmp affine?
     if (isa<UndefValue>(ICmp->getOperand(0))
         || isa<UndefValue>(ICmp->getOperand(1)))
-      INVALID(AffFunc, "undef operand in branch at BB: " + BB.getNameStr());
+      INVALID(AffFunc, "undef operand in branch at BB: " + BB.getName());
 
     const SCEV *LHS = SE->getSCEV(ICmp->getOperand(0));
     const SCEV *RHS = SE->getSCEV(ICmp->getOperand(1));
 
     if (!isAffineExpr(&Context.CurRegion, LHS, *SE) ||
         !isAffineExpr(&Context.CurRegion, RHS, *SE))
-      INVALID(AffFunc, "Non affine branch in BB '" << BB.getNameStr()
+      INVALID(AffFunc, "Non affine branch in BB '" << BB.getName()
                         << "' with LHS: " << *LHS << " and RHS: " << *RHS);
   }
 
@@ -204,7 +204,7 @@
   // Allow perfectly nested conditions.
   Region *R = RI->getRegionFor(&BB);
   if (R->getEntry() != &BB)
-    INVALID(CFG, "Not well structured condition at BB: " + BB.getNameStr());
+    INVALID(CFG, "Not well structured condition at BB: " + BB.getName());
 
   return true;
 }
@@ -358,13 +358,13 @@
   // No canonical induction variable.
   if (!IndVar)
     INVALID(IndVar, "No canonical IV at loop header: "
-                    << L->getHeader()->getNameStr());
+                    << L->getHeader()->getName());
 
   // Is the loop count affine?
   const SCEV *LoopCount = SE->getBackedgeTakenCount(L);
   if (!isAffineExpr(&Context.CurRegion, LoopCount, *SE))
     INVALID(LoopBound, "Non affine loop bound '" << *LoopCount << "' in loop: "
-                       << L->getHeader()->getNameStr());
+                       << L->getHeader()->getName());
 
   return true;
 }
@@ -525,7 +525,7 @@
 
   releaseMemory();
 
-  if (OnlyFunction != "" && F.getNameStr() != OnlyFunction)
+  if (OnlyFunction != "" && F.getName() != OnlyFunction)
     return false;
 
   if(!isValidFunction(F))

Modified: polly/trunk/lib/Analysis/ScopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Analysis/ScopInfo.cpp?rev=144909&r1=144908&r2=144909&view=diff
==============================================================================
--- polly/trunk/lib/Analysis/ScopInfo.cpp (original)
+++ polly/trunk/lib/Analysis/ScopInfo.cpp Thu Nov 17 08:52:36 2011
@@ -237,7 +237,8 @@
 
     isl_space *Space;
 
-    isl_id *ID = isl_id_alloc(ctx, Value->getNameStr().c_str(), Value);
+    std::string ValueName = Value->getName();
+    isl_id *ID = isl_id_alloc(ctx, ValueName.c_str(), Value);
     Space = isl_space_set_alloc(ctx, 1, NbLoopSpaces);
     Space = isl_space_set_dim_id(Space, isl_dim_param, 0, ID);
 
@@ -874,7 +875,7 @@
 
   if (const SCEVUnknown *ValueParameter = dyn_cast<SCEVUnknown>(Parameter)) {
     Value *Val = ValueParameter->getValue();
-    ParameterName = Val->getNameStr();
+    ParameterName = Val->getName();
   }
 
   if (ParameterName == "" || ParameterName.substr(0, 2) == "p_")

Modified: polly/trunk/lib/Cloog.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Cloog.cpp?rev=144909&r1=144908&r2=144909&view=diff
==============================================================================
--- polly/trunk/lib/Cloog.cpp (original)
+++ polly/trunk/lib/Cloog.cpp Thu Nov 17 08:52:36 2011
@@ -210,7 +210,7 @@
 
 }
 std::string CloogExporter::getFileName(Region *R) const {
-  std::string FunctionName = R->getEntry()->getParent()->getNameStr();
+  std::string FunctionName = R->getEntry()->getParent()->getName();
   std::string ExitName, EntryName;
 
   raw_string_ostream ExitStr(ExitName);
@@ -236,7 +236,7 @@
   Region &R = S.getRegion();
   CloogInfo &C = getAnalysis<CloogInfo>();
 
-  std::string FunctionName = R.getEntry()->getParent()->getNameStr();
+  std::string FunctionName = R.getEntry()->getParent()->getName();
   std::string Filename = getFileName(&R);
 
   errs() << "Writing Scop '" << R.getNameStr() << "' in function '"
@@ -296,7 +296,7 @@
 
   Function *F = S.getRegion().getEntry()->getParent();
 
-  DEBUG(dbgs() << ":: " << F->getNameStr());
+  DEBUG(dbgs() << ":: " << F->getName());
   DEBUG(dbgs() << " : " << S.getRegion().getNameStr() << "\n");;
   DEBUG(C->pprint(dbgs()));
 
@@ -306,7 +306,7 @@
 void CloogInfo::printScop(raw_ostream &OS) const {
   Function *function = scop->getRegion().getEntry()->getParent();
 
-  OS << function->getNameStr() << "():\n";
+  OS << function->getName() << "():\n";
 
   C->pprint(OS);
 }

Modified: polly/trunk/lib/CodeGeneration.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/CodeGeneration.cpp?rev=144909&r1=144908&r2=144909&view=diff
==============================================================================
--- polly/trunk/lib/CodeGeneration.cpp (original)
+++ polly/trunk/lib/CodeGeneration.cpp Thu Nov 17 08:52:36 2011
@@ -239,8 +239,7 @@
     Value *VectorPtr = Builder.CreateBitCast(newPointer, vectorPtrType,
                                              "vector_ptr");
     LoadInst *VecLoad = Builder.CreateLoad(VectorPtr,
-                                        load->getNameStr()
-                                        + "_p_vec_full");
+                                           load->getName() + "_p_vec_full");
     if (!Aligned)
       VecLoad->setAlignment(8);
 
@@ -263,9 +262,9 @@
     Type *vectorPtrType = getVectorPtrTy(pointer, 1);
     Value *newPointer = getOperand(pointer, BBMap);
     Value *vectorPtr = Builder.CreateBitCast(newPointer, vectorPtrType,
-                                             load->getNameStr() + "_p_vec_p");
+                                             load->getName() + "_p_vec_p");
     LoadInst *scalarLoad= Builder.CreateLoad(vectorPtr,
-                                          load->getNameStr() + "_p_splat_one");
+                                             load->getName() + "_p_splat_one");
 
     if (!Aligned)
       scalarLoad->setAlignment(8);
@@ -279,7 +278,7 @@
 
     Value *vectorLoad = Builder.CreateShuffleVector(scalarLoad, scalarLoad,
                                                     splatVector,
-                                                    load->getNameStr()
+                                                    load->getName()
                                                     + "_p_splat");
     return vectorLoad;
   }
@@ -307,10 +306,10 @@
     for (int i = 0; i < size; i++) {
       Value *newPointer = getOperand(pointer, scalarMaps[i]);
       Value *scalarLoad = Builder.CreateLoad(newPointer,
-                                             load->getNameStr() + "_p_scalar_");
+                                             load->getName() + "_p_scalar_");
       vector = Builder.CreateInsertElement(vector, scalarLoad,
                                            Builder.getInt32(i),
-                                           load->getNameStr() + "_p_vec_");
+                                           load->getName() + "_p_vec_");
     }
 
     return vector;
@@ -387,7 +386,7 @@
     const Instruction *Inst = dyn_cast<Instruction>(load);
     Value *newPointer = generateLocationAccessed(Inst, pointer, BBMap);
     Value *scalarLoad = Builder.CreateLoad(newPointer,
-                                           load->getNameStr() + "_p_scalar_");
+                                           load->getName() + "_p_scalar_");
     return scalarLoad;
   }
 
@@ -444,7 +443,7 @@
 
     Value *newInst = Builder.CreateBinOp(Inst->getOpcode(), newOpZero,
                                          newOpOne,
-                                         Inst->getNameStr() + "p_vec");
+                                         Inst->getName() + "p_vec");
     vectorMap[Inst] = newInst;
 
     return;
@@ -580,8 +579,7 @@
     Function *F = Builder.GetInsertBlock()->getParent();
     LLVMContext &Context = F->getContext();
     BasicBlock *CopyBB = BasicBlock::Create(Context,
-                                            "polly." + BB->getNameStr()
-                                            + ".stmt",
+                                            "polly." + BB->getName() + ".stmt",
                                             F);
     Builder.CreateBr(CopyBB);
     DT->addNewBlock(CopyBB, Builder.GetInsertBlock());
@@ -914,11 +912,10 @@
   /// @brief Add a new definition of an openmp subfunction.
   Function *addOpenMPSubfunction(Module *M) {
     Function *F = Builder.GetInsertBlock()->getParent();
-    const std::string &Name = F->getNameStr() + ".omp_subfn";
-
     std::vector<Type*> Arguments(1, Builder.getInt8PtrTy());
     FunctionType *FT = FunctionType::get(Builder.getVoidTy(), Arguments, false);
-    Function *FN = Function::Create(FT, Function::InternalLinkage, Name, M);
+    Function *FN = Function::Create(FT, Function::InternalLinkage,
+                                    F->getName() + ".omp_subfn", M);
     // Do not run any polly pass on the new function.
     SD->markFunctionAsInvalid(FN);
 

Modified: polly/trunk/lib/Exchange/JSONExporter.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/JSONExporter.cpp?rev=144909&r1=144908&r2=144909&view=diff
==============================================================================
--- polly/trunk/lib/Exchange/JSONExporter.cpp (original)
+++ polly/trunk/lib/Exchange/JSONExporter.cpp Thu Nov 17 08:52:36 2011
@@ -83,7 +83,7 @@
 char JSONExporter::ID = 0;
 std::string JSONExporter::getFileName(Scop *S) const {
   std::string FunctionName =
-    S->getRegion().getEntry()->getParent()->getNameStr();
+    S->getRegion().getEntry()->getParent()->getName();
   std::string FileName = FunctionName + "___" + S->getNameStr() + ".jscop";
   return FileName;
 }
@@ -142,7 +142,7 @@
   std::string ErrInfo;
   tool_output_file F(FileName.c_str(), ErrInfo);
 
-  std::string FunctionName = R.getEntry()->getParent()->getNameStr();
+  std::string FunctionName = R.getEntry()->getParent()->getName();
   errs() << "Writing JScop '" << R.getNameStr() << "' in function '"
     << FunctionName << "' to '" << FileName << "'.\n";
 
@@ -182,7 +182,7 @@
 char JSONImporter::ID = 0;
 std::string JSONImporter::getFileName(Scop *S) const {
   std::string FunctionName =
-    S->getRegion().getEntry()->getParent()->getNameStr();
+    S->getRegion().getEntry()->getParent()->getName();
   std::string FileName = FunctionName + "___" + S->getNameStr() + ".jscop";
 
   if (ImportPostfix != "")
@@ -207,7 +207,7 @@
 
   std::string FileName = ImportDir + "/" + getFileName(S);
 
-  std::string FunctionName = R.getEntry()->getParent()->getNameStr();
+  std::string FunctionName = R.getEntry()->getParent()->getName();
   errs() << "Reading JScop '" << R.getNameStr() << "' in function '"
     << FunctionName << "' from '" << FileName << "'.\n";
   OwningPtr<MemoryBuffer> result;

Modified: polly/trunk/lib/Exchange/ScopLib.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/ScopLib.cpp?rev=144909&r1=144908&r2=144909&view=diff
==============================================================================
--- polly/trunk/lib/Exchange/ScopLib.cpp (original)
+++ polly/trunk/lib/Exchange/ScopLib.cpp Thu Nov 17 08:52:36 2011
@@ -76,7 +76,7 @@
          VE = ArrayMap.end(); VI != VE; ++VI)
       if ((*VI).second == i) {
         const Value *V = (*VI).first;
-        std::string name = V->getNameStr();
+        std::string name = V->getName();
         scoplib->arrays[i] = (char*) malloc(sizeof(char*) * (name.size() + 1));
         strcpy(scoplib->arrays[i], name.c_str());
       }

Modified: polly/trunk/lib/Exchange/ScopLibExporter.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/ScopLibExporter.cpp?rev=144909&r1=144908&r2=144909&view=diff
==============================================================================
--- polly/trunk/lib/Exchange/ScopLibExporter.cpp (original)
+++ polly/trunk/lib/Exchange/ScopLibExporter.cpp Thu Nov 17 08:52:36 2011
@@ -54,7 +54,7 @@
 
 std::string ScopLibExporter::getFileName(Scop *S) const {
   std::string FunctionName =
-    S->getRegion().getEntry()->getParent()->getNameStr();
+    S->getRegion().getEntry()->getParent()->getName();
   std::string FileName = FunctionName + "___" + S->getNameStr() + ".scoplib";
   return FileName;
 }
@@ -76,7 +76,7 @@
   scoplib.print(F);
   fclose(F);
 
-  std::string FunctionName = R->getEntry()->getParent()->getNameStr();
+  std::string FunctionName = R->getEntry()->getParent()->getName();
   errs() << "Writing Scop '" << R->getNameStr() << "' in function '"
     << FunctionName << "' to '" << FileName << "'.\n";
 

Modified: polly/trunk/lib/Exchange/ScopLibImporter.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Exchange/ScopLibImporter.cpp?rev=144909&r1=144908&r2=144909&view=diff
==============================================================================
--- polly/trunk/lib/Exchange/ScopLibImporter.cpp (original)
+++ polly/trunk/lib/Exchange/ScopLibImporter.cpp Thu Nov 17 08:52:36 2011
@@ -62,7 +62,7 @@
 namespace {
 std::string ScopLibImporter::getFileName(Scop *S) const {
   std::string FunctionName =
-    S->getRegion().getEntry()->getParent()->getNameStr();
+    S->getRegion().getEntry()->getParent()->getName();
   std::string FileName = FunctionName + "___" + S->getNameStr() + ".scoplib";
   return FileName;
 }
@@ -85,7 +85,7 @@
     return false;
   }
 
-  std::string FunctionName = R->getEntry()->getParent()->getNameStr();
+  std::string FunctionName = R->getEntry()->getParent()->getName();
   errs() << "Reading Scop '" << R->getNameStr() << "' in function '"
     << FunctionName << "' from '" << FileName << "'.\n";
 

Modified: polly/trunk/lib/RegionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/RegionSimplify.cpp?rev=144909&r1=144908&r2=144909&view=diff
==============================================================================
--- polly/trunk/lib/RegionSimplify.cpp (original)
+++ polly/trunk/lib/RegionSimplify.cpp Thu Nov 17 08:52:36 2011
@@ -73,11 +73,11 @@
   O << "Region: " << r->getNameStr() << " Edges:\t";
 
   if (enteringBlock)
-    O << "Entering: [" << enteringBlock->getNameStr() << " -> "
+    O << "Entering: [" << enteringBlock->getName() << " -> "
       << r->getEntry()->getName() << "], ";
 
   if (exitingBlock) {
-    O << "Exiting: [" << exitingBlock->getNameStr() << " -> ";
+    O << "Exiting: [" << exitingBlock->getName() << " -> ";
     if (r->getExit())
       O << r->getExit()->getName();
     else



From daniel at zuster.org  Thu Nov 17 11:47:23 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 17 Nov 2011 17:47:23 -0000
Subject: [llvm-commits] [compiler-rt] r144913 -
	/compiler-rt/trunk/make/platform/clang_darwin.mk
Message-ID: <20111117174723.1F82F2A6C133@llvm.org>

Author: ddunbar
Date: Thu Nov 17 11:47:22 2011
New Revision: 144913

URL: http://llvm.org/viewvc/llvm-project?rev=144913&view=rev
Log:
platform/clang_darwin: Fix a refacto and commento.

Modified:
    compiler-rt/trunk/make/platform/clang_darwin.mk

Modified: compiler-rt/trunk/make/platform/clang_darwin.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=144913&r1=144912&r2=144913&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/clang_darwin.mk (original)
+++ compiler-rt/trunk/make/platform/clang_darwin.mk Thu Nov 17 11:47:22 2011
@@ -89,10 +89,10 @@
 IOS_DEPLOYMENT_ARGS := -miphoneos-version-min=1.0
 IOSSIM_DEPLOYMENT_ARGS := -miphoneos-version-min=1.0
 
-# If an explicit ARM_SDK build variable is set, use that as the isysroot.
-X86_OSX_DEPLOYMENT_ARGS += -isysroot $(ProjSrcRoot)/SDKs/darwin
-ARM_IOS_DEPLOYMENT_ARGS += -isysroot $(ProjSrcRoot)/SDKs/darwin
-X86_IOS_DEPLOYMENT_ARGS += -isysroot $(ProjSrcRoot)/SDKs/darwin
+# Use our stub SDK as the sysroot to support more portable building.
+OSX_DEPLOYMENT_ARGS += -isysroot $(ProjSrcRoot)/SDKs/darwin
+IOS_DEPLOYMENT_ARGS += -isysroot $(ProjSrcRoot)/SDKs/darwin
+IOSSIM_DEPLOYMENT_ARGS += -isysroot $(ProjSrcRoot)/SDKs/darwin
 
 CFLAGS.eprintf		:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)
 CFLAGS.10.4		:= $(CFLAGS) $(OSX_DEPLOYMENT_ARGS)



From tonic at nondot.org  Thu Nov 17 11:54:20 2011
From: tonic at nondot.org (Tanya Lattner)
Date: Thu, 17 Nov 2011 17:54:20 -0000
Subject: [llvm-commits] [dragonegg] r144914 - /dragonegg/tags/RELEASE_30/rc4/
Message-ID: <20111117175420.2FB362A6C133@llvm.org>

Author: tbrethou
Date: Thu Nov 17 11:54:19 2011
New Revision: 144914

URL: http://llvm.org/viewvc/llvm-project?rev=144914&view=rev
Log:
Creating release candidate 4 from release_30 branch

Added:
    dragonegg/tags/RELEASE_30/rc4/   (props changed)
      - copied from r144913, dragonegg/branches/release_30/

Propchange: dragonegg/tags/RELEASE_30/rc4/
------------------------------------------------------------------------------
--- svn:ignore (added)
+++ svn:ignore Thu Nov 17 11:54:19 2011
@@ -0,0 +1,2 @@
+*.d
+target

Propchange: dragonegg/tags/RELEASE_30/rc4/
------------------------------------------------------------------------------
    svn:mergeinfo = /dragonegg/trunk:142351,142575,142651,143357



From hfinkel at anl.gov  Thu Nov 17 12:01:30 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Thu, 17 Nov 2011 12:01:30 -0600
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <4EC504B5.2020408@grosser.es>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
	<1319919418.23036.881.camel@sapling>
	<1319928991.23036.957.camel@sapling>
	<1320108633.23036.1266.camel@sapling>
	<1320172356.23036.1298.camel@sapling>
	<4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling>
	<1320191694.23036.1497.camel@sapling>
	<1320749109.19359.76.camel@sapling>
	<4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling>
	<4EB98207.2070807@grosser.es> <1320791390.19359.262.camel@sapling>
	<4EBC4B0F.6010609@grosser.es> <1321050998.19359.539.camel@sapling>
	<4EBDA7F9.9080709@grosser.es> <1321053083.19359.550.camel@sapling>
	<4EBDB1BF.7090006@grosser.es>  <1321400339.19359.782.camel@sapling>
	<1321486739.19359.1067.camel@sapling>  <4EC504B5.2020408@grosser.es>
Message-ID: <1321552890.19359.1327.camel@sapling>

On Thu, 2011-11-17 at 13:57 +0100, Tobias Grosser wrote:
> On 11/17/2011 12:38 AM, Hal Finkel wrote:
> > Tobias, et al.,
> >
> > Attached is the my autovectorization pass.
> 
> Very nice. Will you be at the developer summit? Maybe we could discuss 
> the integration there?

Unfortunately, not this year.

> 
> Here a first review of the source code.

Thanks! This is great! There are a few inline comments; but for the most
part I'll makes the changes as suggested.

> 
> 
> > diff --git a/docs/Passes.html b/docs/Passes.html
> > index 5c42f3f..076effa 100644
> > --- a/docs/Passes.html
> > +++ b/docs/Passes.html
> > @@ -126,6 +126,7 @@ perl -e '$/ = undef; for (split(/\n/,<>)) { s:^ *///? ?::; print "<p>\n" if !
> >   <tr><td><a href="#adce">-adce</a></td><td>Aggressive Dead Code Elimination</td></tr>
> >   <tr><td><a href="#always-inline">-always-inline</a></td><td>Inliner for always_inline functions</td></tr>
> >   <tr><td><a href="#argpromotion">-argpromotion</a></td><td>Promote 'by reference' arguments to scalars</td></tr>
> > +<tr><td><a href="#bb-vectorize">-bb-vectorize</a></td><td>Combine instructions to vectorize within basic blocks</td></tr>
> 
> Maybe 'Combine instructions to vector instructions within basic blocks'
> 
> > diff --git a/include/llvm-c/Transforms/Vectorize.h b/include/llvm-c/Transforms/Vectorize.h
> > new file mode 100644
> > index 0000000..497518a
> > --- /dev/null
> > +++ b/include/llvm-c/Transforms/Vectorize.h
> > @@ -0,0 +1,36 @@
> > +/*===---------------------------Vectorize.h ------------------- -*- C++ -*-===*\
> > +|*===----------- Vectorization Transformation Library C Interface ---------===*|
> > +|*                                                                            *|
> > +|*                     The LLVM Compiler Infrastructure                       *|
> > +|*                                                                            *|
> > +|* This file is distributed under the University of Illinois Open Source      *|
> > +|* License. See LICENSE.TXT for details.                                      *|
> > +|*                                                                            *|
> > +|*===----------------------------------------------------------------------===*|
> > +|*                                                                            *|
> > +|* This header declares the C interface to libLLVMScalarOpts.a, which         *|
> > +|* implements various scalar transformations of the LLVM IR.                  *|
> > +|*                                                                            *|
> > +|* Many exotic languages can interoperate with C code but have a harder time  *|
> > +|* with C++ due to name mangling. So in addition to C, this interface enables *|
> > +|* tools written in such languages.                                           *|
> > +|*                                                                            *|
> > +\*===----------------------------------------------------------------------===*/
> 
> This comment does not match the content of the file.
> 
> >
> > +static cl::opt<bool>
> > +RunVectorization("vectorize", cl::desc("Run vectorization passes"));
> > +
> >   PassManagerBuilder::PassManagerBuilder() {
> >       OptLevel = 2;
> >       SizeLevel = 0;
> > @@ -38,6 +43,7 @@ PassManagerBuilder::PassManagerBuilder() {
> >       DisableSimplifyLibCalls = false;
> >       DisableUnitAtATime = false;
> >       DisableUnrollLoops = false;
> > +    Vectorize = RunVectorization;
> 
> Integrating vectorization like this seems to work for now. However, it 
> does not seem to be 100% clean. I wonder if we could follow the other 
> flags here and set Vectorize = false in the constructor and add the 
> flags which enable this to the tools that use the PassManagerBuilder. 
> You may even had this or something similar before, because I remember 
> for your earlier patches -mllvm did not work for you in clang. If we 
> require the tools to explicitly set Vectorizer, we would neeed to add a 
> clang specific flag that could drive the vectorizer. I am not sure if we 
> want to do this at this stage or even at all.
> 
> For now I would keep it like this. I don't have a better solution, but 
> wanted to write down my thoughts.
> 
> 
> >   }
> >
> >   PassManagerBuilder::~PassManagerBuilder() {
> > @@ -170,6 +176,14 @@ void PassManagerBuilder::populateModulePassManager(PassManagerBase&MPM) {
> >
> >     addExtensionsToPM(EP_ScalarOptimizerLate, MPM);
> >
> > +  if (Vectorize) {
> > +    MPM.add(createBBVectorizePass());
> > +    if (OptLevel>  1) {
> > +      MPM.add(createInstructionCombiningPass());
> > +      MPM.add(createGVNPass());                 // Remove redundancies
> > +    }
> > +  }
> > +
> 
> What is the reason you will not enable this at -O1. LLVM runs even at 
> -O1 a number of instcombine and GVN passes. I don't see a strong reason 
> why we would not want to do this after vectorization (In case it is 
> known to be useful in general).

Fair enough. I had essentially just copied the O1 guard from the
previous invocation of those passes. You're right, however, that they're
really needed after vectorization and, if you're doing vectorization
anyway, then you'll want them.

> 
> 
> > +++ b/lib/Transforms/Vectorize/BBVectorize.cpp
> > @@ -0,0 +1,1338 @@
> 
> > +    typedef std::pair<Value *, Value *>  value_pair;
> > +    typedef std::pair<value_pair, value_pair>  vp_pair;
> > +    typedef std::pair<std::multimap<Value *, Value *>::iterator,
> > +              std::multimap<Value *, Value *>::iterator>  vp_iterator_pair;
> > +    typedef std::pair<std::multimap<value_pair, value_pair>::iterator,
> > +              std::multimap<value_pair, value_pair>::iterator>
> > +                vpp_iterator_pair;
> 
> http://llvm.org/docs/CodingStandards.html#ll_naming
> 
> "Type names (including classes, structs, enums, typedefs, etc) should be 
> nouns and start with an upper-case letter (e.g. TextFileReader)."
> 
> 
> > +    void getCandPairs(unsigned vBits, BasicBlock&BB,
> > +                       std::multimap<Value *, Value *>  &candPairs,
> > +                       std::vector<Value *>  &pairableInsts);
> 
> "Variable names should be nouns (as they represent state). The name 
> should be camel case, and start with an upper case letter (e.g. Leader 
> or Boats)."
> 
> This happens at several places. Can you check your code for this.
> 
> > +    void replValues(BasicBlock&BB,
> > +                     std::vector<Value *>  &pairableInsts,
> > +                     DenseMap<Value *, Value *>&  chosenPairs);
> 'repl' is no obvious abbreviation for me. Can you use the full word or 
> equivalent shorter one?

Replace. [I'll change it].

> 
> > +
> > +    virtual bool runOnBasicBlock(BasicBlock&BB) {
> > +      // const TargetData *TD = getAnalysisIfAvailable<TargetData>();
> > +
> > +      bool changed = false;
> > +      // Iterate a sufficient number of times to merge types of
> > +      // size 1, then 2, then 4, etc. up to half of the
> > +      // target vector width of the target vector register.
> Any reason you don't use the 80 columns?
> 
> Also, why are you iterating here?

I'll add a comment; it is iterating to vectorize pairs. The first
iteration may combine float ops into <2 x float> ops. The next iteration
may combine those into <4 x float> ops (which is probably what you want
for floats anyway).

> 
> 
> > +      for (unsigned vBits = 2, n = 1; vBits<= VectorBits&&
> > +             (!MaxIter || n<= MaxIter); vBits *= 2, ++n) {
> > +        DEBUG(dbgs()<<  "BBV: fusing loop #"<<  n<<  "...\n");
> > +        if (vectorizePairs(VectorBits, BB)) {
> > +          changed = true;
> > +        }
> > +        else {
> > +          break;
> > +        }
> 
> In general you should use '} else {'. Here braces are not needed at all.
> 
> > +    static inline VectorType *getVecType(Type *iType) {
> > +      if (iType->isVectorTy()) {
> > +        unsigned numElem = cast<VectorType>(iType)->getNumElements();
> > +        return VectorType::get(iType->getScalarType(), numElem*2);
> > +      }
> > +      else {
> > +        return VectorType::get(iType, 2);
> > +      }
> > +    }
> > +
> > +    // Note: when this function returns 0, the
> > +    // resulting instructions are not actually fused.
> 
> Use all 80 columns. What is a depth factor? Can you explain in the
> comment what this function calculates and not what happens when it is
> used. If you want to keep the use case, just put is an example.
> 
> > +    static inline size_t depthFactor(Value *v) {
> > +      if (isa<InsertElementInst>(v) || isa<ExtractElementInst>(v)) {
> > +        return 0;
> > +      }
> No '{}' needed.
> 
> > +
> > +      return 1;
> > +    }
> > +
> > +    // Returns 1 if J accesses the memory directly after I; -1 if I accesses
> > +    // the memory directly after J; and 0 otherwise.
> > +    int getPairPtrInfo(Instruction *I, Instruction *J, const TargetData&TD,
> > +        Value *&Iptr, Value *&Jptr, unsigned&Ialign, unsigned&Jalign) {
> 
> Also getPairPtrInfo() does not sound like a very descriptive name. What
> about getOffset().
> 
> I am not sure about returning 0 for the remaining cases. I think
> an offset of 0 is actually a very useful case, which can be implemented
> as a scalar load plus a splat. What about returning the offset as a
> reference value and return a boolean if it was successfully computed.
> The other alternative I see is to use an enum that specifies the known
> offsets and also includes an UNKNOWN value.

True, but a load/splat is not a fused load, and if the result of such a
load is fused, then the splat will automatically be generated by the
later fusion. If some architecture supported a single-instruction
load/splat, then that should be caught by instruction selection.

You are correct, however, an enum would be cleaner in the current
implementation. I am under the impression that some instruction sets now
have masked loads and stores, and if we support them in the future (via
an IR extension of some kind), then we'll want an integer here. Thus, I
change it to a bool-returning function with an integer-reference
argument.

> 
> > +      if (isa<LoadInst>(I)) {
> > +        Iptr = cast<LoadInst>(I)->getPointerOperand();
> > +        Jptr = cast<LoadInst>(J)->getPointerOperand();
> > +        Ialign = cast<LoadInst>(I)->getAlignment();
> > +        Jalign = cast<LoadInst>(J)->getAlignment();
> > +      }
> > +      else {
> > +        Iptr = cast<StoreInst>(I)->getPointerOperand();
> > +        Jptr = cast<StoreInst>(J)->getPointerOperand();
> > +        Ialign = cast<StoreInst>(I)->getAlignment();
> > +        Jalign = cast<StoreInst>(J)->getAlignment();
> > +      }
> 
> Use '} else {'. Also you are just checking just the type of one
> instruction. You may want to check both and add a call to
> llvm_unreachable in case the types do not match.
> 
> > +      ScalarEvolution&SE = getAnalysis<ScalarEvolution>();
> > +      const SCEV *IptrSCEV = SE.getSCEV(Iptr);
> > +      const SCEV *JptrSCEV = SE.getSCEV(Jptr);
> > +
> > +      // If this is a trivial offset, then we'll get something
> > +      // like 1*sizeof(type). With target data, which we need
> > +      // anyway, this will get constant folded into a number.
> Why don't you use the full 80 columns?
> 
> 
> > +      const SCEV *RelOffSCEV = SE.getMinusSCEV(JptrSCEV, IptrSCEV);
> 
> What about just alling this 'Offset'. Those appreviations are hard to
> read.
> 
> > +      if (const SCEVConstant *ConstOffSCEV =
> > +            dyn_cast<SCEVConstant>(RelOffSCEV)) {
> > +        ConstantInt *IntOff = ConstOffSCEV->getValue();
> > +        int64_t off = IntOff->getSExtValue();
> > +
> > +        Type *VTy = cast<PointerType>(Iptr->getType())->getElementType();
> 
> You should assert that the types of both pointers are indentical.

This is done implicitly in all calling code. This, however, should be
documented as a precondition of the function.

> Also you should document that this function only works for vector types.
> I actually expected it to just work for scalar types. Vector types look
> a little bit wired here and I am actually not even sure if it is correct
> for vector types.

What do you mean by working only for vector types? I don't think that's
true. As I recall, it seemed to work find for both loads and stores
using both scalar pointers and vector pointers.

> 
> > +        int64_t VTy_tss = (int64_t) TD.getTypeStoreSize(VTy);
> > +
> > +        if (off == VTy_tss) {
> > +          return 1;
> > +        } else if (-off == VTy_tss) {
> > +          return -1;
> > +        }
> Braces not needed.
> 
> > +      }
> Did you think of using SE.getSizeOfExpr()?

Yes. ;)

I did not for two reasons. First, if we have target data, which we need
for load/store vectorization anyway, then it is unnecessary because the
sizeof gets constant folded. Thus, that division is just an integer
division in the relevant cases anyway.

Second, correct me if I'm wrong, but I would need a signed division, not
an unsigned division.

> 
> const SCEV *ElementSize = SE.getSizeofExpr(Iprt->getAllocType())
> const SCEV *ElementOffset = SE.getUDivExpr(RelOffSCEV, ElementSize);
> 
> if (const SCEVConstant *ConstOffset =
>        dyn_cast<SCEVConstant>(ElementOffset))
>    return ConstOffset->getValue();
> 
> else
>    return "Unknown offset"
> 
> > +  bool BBVectorize::vectorizePairs(unsigned vBits, BasicBlock&BB) {
> > +    std::vector<Value *>  pairableInsts;
> > +    std::multimap<Value *, Value *>  candPairs;
> 
> Variables should start with Uppercase letters.
> 
> > +    getCandPairs(vBits, BB, candPairs, pairableInsts);
> > +    if (!pairableInsts.size()) return false;
> > +
> > +    // Now we have a map of all of the pairable instructions and we need to
> > +    // select the best possible pairing. A good pairing is one such that the
> > +    // users of the pair are also paired. This defines a (directed) forest
> > +    // over the pairs such that two pairs are connected iff the second pair
> > +    // uses the first.
> > +
> > +    // Note that it only matters that both members of the second pair use some
> > +    // element of the first pair (to allow for splatting).
> > +
> > +    std::multimap<value_pair, value_pair>  connPairs;
> > +    computeConnPairs(candPairs, pairableInsts, connPairs);
> > +    if (!connPairs.size()) return false;
> > +
> > +    // Build the pairable-instruction dependency map
> > +    DenseSet<value_pair>  pairableInstUsers;
> > +    buildDepMap(BB, candPairs, pairableInsts, pairableInstUsers);
> > +
> > +    // There is now a graph of the connected pairs. For each variable, pick the
> > +    // pairing with the largest tree meeting the depth requirement on at least
> > +    // one branch. Then select all pairings that are part of that tree and
> > +    // remove them from the list of available parings and pairable variables.
> > +
> > +    DenseMap<Value *, Value *>  chosenPairs;
> > +    choosePairs(candPairs, pairableInsts, connPairs,
> > +      pairableInstUsers, chosenPairs);
> > +
> > +    if (!chosenPairs.size()) return false;
> > +    NumFusedOps += chosenPairs.size();
> > +
> > +    // A set of chosen pairs has now been selected. It is now necessary to
> > +    // replace the paired functions with vector functions. For this procedure
>                               instructions with vector instructions.
> 
> > +    // each argument much be replaced with a vector argument. This vector
>                          must
> 
> > +    // is formed by using build_vector on the old arguments. The replaced
> > +    // values are then replaced with a vector_extract on the result.
> > +    // Subsequent optimization passes should coalesce the build/extract
> > +    // combinations.
> > +
> > +    replValues(BB, pairableInsts, chosenPairs);
> > +
> > +    return true;
> > +  }
> > +
> > +  void BBVectorize::getCandPairs(unsigned vBits, BasicBlock&BB,
> > +                       std::multimap<Value *, Value *>  &candPairs,
> > +                       std::vector<Value *>  &pairableInsts) {
> This function is too big. It does not even fit on my large screen. Can
> you extract sub functons. E.g. isValidInst()
> 
> > +    AliasAnalysis&AA = getAnalysis<AliasAnalysis>();
> > +    BasicBlock::iterator E = BB.end();
> > +    for (BasicBlock::iterator I = BB.getFirstInsertionPt(); I != E; ++I) {
> 
> The common pattern is:
> 
> for (BasicBlock::iterator I = BB.getFirstInsertionPt(), E.BB.end(); I != E;
>       ++I) {
> 
> BTW, why don't you start at BB.begin()?
> 
> > +      bool isGoodIntr = false;
> > +      if (isa<CallInst>(I)) {
> > +        if (Function *F = cast<CallInst>(I)->getCalledFunction()) {
> 
> if (CallInst *CallInst = dyn_cast<CallInst>(I)) {
>    if (Function *F = CallInst->getCalledFunction()) {
> 
> > +          if (unsigned IID = F->getIntrinsicID()) {
> > +            switch(IID) {
> > +            case Intrinsic::sqrt:
> > +            case Intrinsic::powi:
> > +            case Intrinsic::sin:
> > +            case Intrinsic::cos:
> > +            case Intrinsic::log:
> > +            case Intrinsic::log2:
> > +            case Intrinsic::log10:
> > +            case Intrinsic::exp:
> > +            case Intrinsic::exp2:
> > +            case Intrinsic::pow:
> > +              isGoodIntr = !NoMath;
> Is the fallthrough intended here?

No, thanks!

> 
> > +            case Intrinsic::fma:
> > +              isGoodIntr = !NoFMA;
> I would also put a break here.
> 
> What happends in the default case or do you cover all intrinsics.?

In the default case the intrinsic is not considered for vectorization.
This will be clearer when I put this into a separate function as you're
suggested.

> > +            }
> > +          }
> > +        }
> Most of these '{}' are not needed.
> 
> > +      }
> > +
> > +      // Vectorize simple loads and stores if possbile:
> > +      bool isLdStr = false;
> 
> IsSimpleLoad?

That would be a better name.

> 
> > +      if (isa<LoadInst>(I)) {
> > +        isLdStr = cast<LoadInst>(I)->isSimple();
> > +      } else if (isa<StoreInst>(I)) {
> > +        isLdStr = cast<StoreInst>(I)->isSimple();
> > +      }
> 
> if (LoadInst *Load = dyn_cast<LoadInst>(I)) {
>    isLdStr = Load->isSimple();
> } else if (StoreInst *Store = dyn_cast<StoreInst>(I)) {
>    isLdStr = Store->isSimple();
> }
> 
> > +
> > +      // We can vectorize casts, but not casts of pointer types, etc.
> > +      bool isCast = false;
> > +      if (I->isCast()) {
> > +        isCast = true;
> > +        if (!cast<CastInst>(I)->getSrcTy()->isSingleValueType()) {
> > +          isCast = false;
> > +        } else if (!cast<CastInst>(I)->getDestTy()->isSingleValueType()) {
> > +          isCast = false;
> > +        } else if (cast<CastInst>(I)->getSrcTy()->isPointerTy()) {
> > +          isCast = false;
> > +        } else if (cast<CastInst>(I)->getDestTy()->isPointerTy()) {
> > +          isCast = false;
> > +        }
> > +      }
> > +
> > +      if (!(I->isBinaryOp() || isa<ShuffleVectorInst>(I) ||
> > +              isa<ExtractElementInst>(I) || isa<InsertElementInst>(I) ||
> > +              (!NoCasts&&  isCast) || isGoodIntr ||
> > +              (!NoMemOps&&  isLdStr))) {
> > +        continue;
> > +      }
> > +
> > +      // We can't vectorize memory operations without target data
> > +      if (AA.getTargetData() == 0&&  isLdStr) {
> > +        continue;
> > +      }
> > +
> > +      Type *T1, *T2;
> > +      if (isa<StoreInst>(I)) {
> > +        // For stores, it is the value type, not the pointer type that matters
> > +        // because the value is what will come from a vector register.
> > +
> > +        Value *Ival = cast<StoreInst>(I)->getValueOperand();
> > +        T1 = Ival->getType();
> > +      }
> > +      else {
> > +        T1 = I->getType();
> > +      }
> > +
> > +      if (I->isCast()) {
> > +        T2 = cast<CastInst>(I)->getSrcTy();
> > +      }
> > +      else {
> > +        T2 = T1;
> > +      }
> > +
> > +      // Not every type can be vectorized...
> > +      if (!(VectorType::isValidElementType(T1) || T1->isVectorTy()) ||
> > +          !(VectorType::isValidElementType(T2) || T2->isVectorTy())) {
> > +        continue;
> > +      }
> > +
> > +      if (NoInts&&  (T1->isIntOrIntVectorTy() || T2->isIntOrIntVectorTy())) {
> > +        continue;
> > +      }
> > +
> > +      if (NoFloats&&  (T1->isFPOrFPVectorTy() || T2->isFPOrFPVectorTy())) {
> > +        continue;
> > +      }
> > +
> > +      if (T1->getPrimitiveSizeInBits()>  vBits/2 ||
> > +          T2->getPrimitiveSizeInBits()>  vBits/2) {
> > +        continue;
> > +      }
> > +
> > +      // Look for an instruction with which to pair instruction *I...
> This could be a separate function, no?
> 
> > +      DenseSet<Value *>  users;
> > +      AliasSetTracker writes(AA);
> > +      BasicBlock::iterator J = I; ++J;
> > +      for (unsigned ss = 0; J != E&&  ss<= SearchLimit; ++J, ++ss) {
> > +        // Determine if J uses I, if so, exit the loop.
> 
> This loop is way to big. You can extract here also a couple of
> subfunctions. I will review this after this in etail more readable.
> > +        bool usesI = false;
> > +        for (User::op_iterator i = J->op_begin(), e = J->op_end();
> > +               i != e; ++i) {
> > +          Value *v = *i;
> > +          if (I == v ||
> > +               (!FastDep&&  users.count(v))) {
> 
> Why a newline here? It should not break the 80 col limit.
> 
> > +            usesI = true; break;
> One instruction per line, please.
> 
> > +          }
> > +        }
> > +        if (!usesI&&  J->mayReadFromMemory()) {
> > +          for (AliasSetTracker::iterator i = writes.begin(), e = writes.end();
> > +                i != e; ++i) {
> > +            for (AliasSet::iterator j = i->begin(), e2 = i->end();
> > +                   j != e2; ++j) {
> > +              AliasAnalysis::Location ptrLoc(j->getValue(), j->getSize(),
> > +                j->getTBAAInfo());
> > +              if (AA.getModRefInfo(J, ptrLoc) != AliasAnalysis::NoModRef) {
> > +                usesI = true; break;
> One instruction per line.
> 
> > +              }
> > +            }
> > +            if (usesI) break;
> > +          }
> > +        }
> Many of these braces are not necessarily needed. In case this function
> would be smaller they would also not be required for readability.
> 
> > +        if (FastDep) {
> > +          // Note: For this heuristic to be effective, independent operations
> > +          // must tend to be intermixed. This is likely to be true from some
> > +          // kinds of loop unrolling (but not the generic LLVM pass),
> > +          // but otherwise may require some kind of reordering pass.
> 
> What does it mean that independent operations must be intermixed? Can
> you give an example?

It means that if you group variables into independent groups, say A and
B, such that things in B don't use results from A and vice-verse, and
then have: A B A B A B A B... then FastDep will be able to, if the
instruction are otherwise compatible, vectorize to make <A B> <A B>...
On the other hand, if you have A A A A B B B B, then you need a full
search and dependency analysis to determine that you can move some of
the Bs ahead of the preceding As in order to vectorize them.

> 
> > +
> > +          // When using fast dependency analysis,
> > +          // stop searching after first use:
> > +          if (usesI) break;
> > +        }
> > +        else {
> > +          if (usesI) {
> 
> } else if (usesI) {
> 
> > +            if (J->mayWriteToMemory()) writes.add(J);
> > +            users.insert(J);
> > +            continue;
> > +          }
> > +        }
> > +
> > +        // J does not use I, and comes before the first use of I, so it can be
> > +        // merged with I if the instructions are compatible.
> > +        bool isCompat = J->isSameOperationAs(I);
> > +        // FIXME: handle addsub-type operations!
> > +
> > +        // Only merge two shuffles if they're both constant
> > +        // or both not constant.
> > +        if (isCompat&&  isa<ShuffleVectorInst>(I)) {
> > +          isCompat = isa<Constant>(I->getOperand(2))&&
> > +                     isa<Constant>(J->getOperand(2));
> > +          // FIXME: We may want to vectorize non-constant shuffles also.
> > +        }
> > +
> > +        // Loads and stores can be merged if they have different alignments,
> > +        // but are otherwise the same.
> > +        if (!isCompat&&  isa<LoadInst>(I)&&  isa<LoadInst>(J)) {
> > +          if (I->getType() == J->getType()) {
> > +            if (cast<LoadInst>(I)->getPointerOperand()->getType() ==
> > +                  cast<LoadInst>(J)->getPointerOperand()->getType()&&
> > +                cast<LoadInst>(I)->isVolatile() ==
> > +                  cast<LoadInst>(J)->isVolatile()&&
> > +                cast<LoadInst>(I)->getOrdering() ==
> > +                  cast<LoadInst>(J)->getOrdering()&&
> > +                cast<LoadInst>(I)->getSynchScope() ==
> > +                  cast<LoadInst>(J)->getSynchScope()
> > +               ) {
> > +                 isCompat = true;
> > +             }
> > +          }
> > +        } else if (!isCompat&&  isa<StoreInst>(I)&&  isa<StoreInst>(J)) {
> > +          if (cast<StoreInst>(I)->getValueOperand()->getType() ==
> > +                cast<StoreInst>(J)->getValueOperand()->getType()&&
> > +              cast<StoreInst>(I)->getPointerOperand()->getType() ==
> > +                cast<StoreInst>(J)->getPointerOperand()->getType()&&
> > +              cast<StoreInst>(I)->isVolatile() ==
> > +                cast<StoreInst>(J)->isVolatile()&&
> > +              cast<StoreInst>(I)->getOrdering() ==
> > +                cast<StoreInst>(J)->getOrdering()&&
> > +              cast<StoreInst>(I)->getSynchScope() ==
> > +                cast<StoreInst>(J)->getSynchScope()
> > +             ) {
> > +               isCompat = true;
> > +           }
> > +        }
> > +
> > +        if (isCompat&&  isLdStr) {
> > +          const TargetData&TD = *AA.getTargetData();
> > +
> > +          Value *Iptr, *Jptr;
> > +          unsigned Ialign, Jalign;
> > +          int rel = getPairPtrInfo(I, J, TD, Iptr, Jptr, Ialign, Jalign);
> 
> Use uppercase letters. What does 'rel' mean? Can you use a more
> descriptive name?

Relationship.

> 
> > +
> > +          if (rel != 0) {
> > +            if (AlignedOnly) {
> > +              Type *aType = isa<StoreInst>(I) ?
> > +                cast<StoreInst>(I)->getValueOperand()->getType() : I->getType();
> > +              // An aligned load or store is possible only if the instruction
> > +              // with the lower offset has an alignment suitable for the
> > +              // vector type.
> > +
> > +              unsigned balign = Ialign;
> 
> Uppercase letter.
> 
> > +              if (rel<  0) balign = Jalign;
> > +
> > +              Type *vType = getVecType(aType);
> > +              unsigned vecalign = TD.getPrefTypeAlignment(vType);
> 
> Uppercase.
> 
> > +              if (balign<  vecalign) {
> > +                isCompat = false;
> 
> This could just be a continue (or a return false if extracted to a
> separate function. Also no braces needed.
> 
> > +              }
> > +            }
> > +          }
> > +          else {
> 
> } else {
> 
> > +            isCompat = false;
> This could just be a continue (or a return false if extracted to a
> separate function.
> 
> 
> > +          }
> > +        }
> > +
> > +        if (!isCompat) continue;
> > +
> > +        // J is a candidate for merging with I.
> > +        if (!pairableInsts.size() ||
> > +             pairableInsts[pairableInsts.size()-1] != I) {
> > +          pairableInsts.push_back(I);
> > +        }
> 
> No braces needed.
> 
> > +        candPairs.insert(value_pair(I, J));
> > +        DEBUG(dbgs()<<  "BBV: candidate pair "<<  *I<<
> > +                     "<->  "<<  *J<<  "\n");
> > +      }
> > +    }
> > +
> > +    DEBUG(dbgs()<<  "BBV: found "<<  pairableInsts.size()
> > +<<  " instructions with candidate pairs\n");
> > +  }
> > +
> > +  void BBVectorize::computeConnPairs(
> > +                      std::multimap<Value *, Value *>  &candPairs,
> > +                      std::vector<Value *>  &pairableInsts,
> > +                      std::multimap<value_pair, value_pair>  &connPairs) {
> Uppercase names for arguments. Also, the function is way too long. Can
> you extract smaller helper functions. I will review this then.
> 
> > +
> > +    for (std::vector<Value *>::iterator i = pairableInsts.begin(),
> > +           e = pairableInsts.end(); i != e; ++i) {
> > +      vp_iterator_pair choiceRange = candPairs.equal_range(*i);
> > +
> > +      for (std::multimap<Value *, Value *>::iterator j = choiceRange.first;
> > +           j != choiceRange.second; ++j) {
> > +
> > +        // For each possible pairing for this variable, look at the uses of
> > +        // the first value...
> > +        for (Value::use_iterator I = j->first->use_begin(),
> > +             E = j->first->use_end(); I != E; ++I) {
> > +          vp_iterator_pair iPairRange = candPairs.equal_range(*I);
> > +
> > +          // For each use of the first variable, look for uses of the second
> > +          // variable...
> > +          for (Value::use_iterator J = j->second->use_begin(),
> > +               E2 = j->second->use_end(); J != E2; ++J) {
> > +            vp_iterator_pair jPairRange = candPairs.equal_range(*J);
> > +
> > +            // Look for<I, J>:
> > +            for (std::multimap<Value *, Value *>::iterator k = iPairRange.first;
> > +                 k != iPairRange.second; ++k) {
> > +              if (k->second == *J) {
> > +                connPairs.insert(vp_pair(*j, value_pair(*I, *J)));
> > +                break;
> > +              }
> > +            }
> > +            // Look for<J, I>:
> > +            for (std::multimap<Value *, Value *>::iterator k = jPairRange.first;
> > +                 k != jPairRange.second; ++k) {
> > +              if (k->second == *I) {
> > +                connPairs.insert(vp_pair(*j, value_pair(*J, *I)));
> > +                break;
> > +              }
> > +            }
> > +          }
> > +
> > +          // Look for cases where just the first value in the pair is used by
> > +          // both members of another pair (splatting).
> > +          Value::use_iterator J = j->first->use_begin();
> > +          if (!SplatBreaksChain) for (; J != E; ++J) {
> > +            for (std::multimap<Value *, Value *>::iterator k = iPairRange.first;
> > +                 k != iPairRange.second; ++k) {
> > +              if (k->second == *J) {
> > +                connPairs.insert(vp_pair(*j, value_pair(*I, *J)));
> > +                break;
> > +              }
> > +            }
> > +          }
> > +        }
> > +
> > +        // Look for cases where just the second value in the pair is used by
> > +        // both members of another pair (splatting).
> > +        if (!SplatBreaksChain)
> > +          for (Value::use_iterator I = j->second->use_begin(),
> > +             E = j->second->use_end(); I != E; ++I) {
> > +          vp_iterator_pair iPairRange = candPairs.equal_range(*I);
> > +
> > +          Value::use_iterator J = j->second->use_begin();
> > +          for (; J != E; ++J) {
> > +            for (std::multimap<Value *, Value *>::iterator k = iPairRange.first;
> > +                 k != iPairRange.second; ++k) {
> > +              if (k->second == *J) {
> > +                connPairs.insert(vp_pair(*j, value_pair(*I, *J)));
> > +                break;
> > +              }
> > +            }
> > +          }
> > +        }
> > +      }
> > +    }
> > +
> > +    DEBUG(dbgs()<<  "BBV: found "<<  connPairs.size()
> > +<<  " pair connections.\n");
> > +  }
> 
> 
> > +  void BBVectorize::buildDepMap(
> > +                      BasicBlock&BB,
> > +                      std::multimap<Value *, Value *>  &candPairs,
> > +                      std::vector<Value *>  &pairableInsts,
> > +                      DenseSet<value_pair>  &pairableInstUsers) {
> Uppercase variable names.
> 
> > +    DenseSet<Value *>  isInPair;
> > +    for (std::multimap<Value *, Value *>::iterator i = candPairs.begin(),
> > +           e = candPairs.end(); i != e; ++i) {
> 
> Uppercase letters are used in LLVM for iterators.
> 
> > +      isInPair.insert(i->first); isInPair.insert(i->second);
> > +    }
> 
> No braces needed.
> 
> > +
> > +    // Iterate through the basic block, recording all users of each
> > +    // pairable instruction.
> > +
> > +    AliasAnalysis&AA = getAnalysis<AliasAnalysis>();
> > +    BasicBlock::iterator E = BB.end();
> > +    for (BasicBlock::iterator I = BB.getFirstInsertionPt(); I != E; ++I) {
> > +      if (isInPair.find(I) == isInPair.end()) continue;
> > +
> > +      DenseSet<Value *>  users;
> > +      AliasSetTracker writes(AA);
> > +      BasicBlock::iterator J = I; ++J;
> > +      for (; J != E; ++J) {
> > +        // Determine if J uses I, if so, exit the loop.
> Just extract this into a small helper function. No need to keep it here.
> 
> > +        bool usesI = false;
> > +        for (User::op_iterator i = J->op_begin(), e = J->op_end();
> > +               i != e; ++i) {
> > +          Value *v = *i;
> > +          if (I == v || users.count(v)) {
> > +            usesI = true; break;
> > +          }
> > +        }
> > +        if (!usesI&&  J->mayReadFromMemory()) {
> 
> And this one as well
> > +          for (AliasSetTracker::iterator i = writes.begin(), e = writes.end();
> > +                i != e; ++i) {
> > +            for (AliasSet::iterator j = i->begin(), e2 = i->end();
> > +                   j != e2; ++j) {
> > +              AliasAnalysis::Location ptrLoc(j->getValue(), j->getSize(),
> > +                j->getTBAAInfo());
> > +              if (AA.getModRefInfo(J, ptrLoc) != AliasAnalysis::NoModRef) {
> > +                usesI = true; break;
> > +              }
> > +            }
> > +            if (usesI) break;
> > +          }
> > +        }
> > +        if (usesI) {
> > +          if (J->mayWriteToMemory()) writes.add(J);
> > +          users.insert(J);
> > +        }
> 
> > +      }
> The resulting loop should be very simple.
> 	
> > +
> > +      for (DenseSet<Value *>::iterator i = users.begin(), e = users.end();
> > +             i != e; ++i) {
> > +        pairableInstUsers.insert(value_pair(I, *i));
> > +      }
> > +    }
> > +  }
> > +
> 
> What does it mean pairs are in conflict? What about adding a comment
> about what this actually means.

There is a comment about this near the calling location. I'll move it.

> 
> > +  bool BBVectorize::pairsConflict(value_pair i, value_pair j,
> > +                      DenseSet<value_pair>  &pairableInstUsers) {
> > +    // Two pairs are in conflict if they are mutual users of eachother.
> > +    bool jui = pairableInstUsers.count(value_pair(i.first, j.first)) ||
> > +               pairableInstUsers.count(value_pair(i.first, j.second)) ||
> > +               pairableInstUsers.count(value_pair(i.second, j.first)) ||
> > +               pairableInstUsers.count(value_pair(i.second, j.second));
> > +    bool iuj = pairableInstUsers.count(value_pair(j.first, i.first)) ||
> > +               pairableInstUsers.count(value_pair(j.first, i.second)) ||
> > +               pairableInstUsers.count(value_pair(j.second, i.first)) ||
> > +               pairableInstUsers.count(value_pair(j.second, i.second));
> > +    return (jui&&  iuj);
> > +  }
> > +
> > +  void BBVectorize::choosePairs(
> > +                      std::multimap<Value *, Value *>  &candPairs,
> > +                      std::vector<Value *>  &pairableInsts,
> > +                      std::multimap<value_pair, value_pair>  &connPairs,
> > +                      DenseSet<value_pair>  &pairableInstUsers,
> > +                      DenseMap<Value *, Value *>&  chosenPairs) {
> 
> This one is again way to large. Can you please extract subfunctions.
> 
> I need to stop here, as I run out of time for today. I hope you already
> get an impression what kind of improvements I suggest. If you agree,
> please go ahead and integrate them. Especially the use of smaller
> subfunctions will help me a lot when reviewing this again. Most probably
> many of your inline comments, could become the descriptions of some of
> those extracted functions.

Will do, and thanks again. I'll send an updated patch soon.

 -Hal

> 
> Cheers
> Tobi
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From tobias at grosser.es  Thu Nov 17 13:11:46 2011
From: tobias at grosser.es (Tobias Grosser)
Date: Thu, 17 Nov 2011 11:11:46 -0800
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <1321552890.19359.1327.camel@sapling>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
	<1319919418.23036.881.camel@sapling>
	<1319928991.23036.957.camel@sapling>
	<1320108633.23036.1266.camel@sapling>
	<1320172356.23036.1298.camel@sapling> <4EB0462C.5010209@grosser.es>
	<1320184739.23036.1334.camel@sapling>
	<1320191694.23036.1497.camel@sapling>
	<1320749109.19359.76.camel@sapling> <4EB90E98.4010805@grosser.es>
	<1320762963.19359.117.camel@sapling> <4EB98207.2070807@grosser.es>
	<1320791390.19359.262.camel@sapling> <4EBC4B0F.6010609@grosser.es>
	<1321050998.19359.539.camel@sapling> <4EBDA7F9.9080709@grosser.es>
	<1321053083.19359.550.camel@sapling> <4EBDB1BF.7090006@grosser.es>
	<1321400339.19359.782.camel@sapling>
	<1321486739.19359.1067.camel@sapling> <4EC504B5.2020408@grosser.es>
	<1321552890.19359.1327.camel@sapling>
Message-ID: <4EC55C72.8020001@grosser.es>

On 11/17/2011 10:01 AM, Hal Finkel wrote:
> On Thu, 2011-11-17 at 13:57 +0100, Tobias Grosser wrote:
>> On 11/17/2011 12:38 AM, Hal Finkel wrote:
>>> Tobias, et al.,
>>>
>>> Attached is the my autovectorization pass.
>>
>> Very nice. Will you be at the developer summit? Maybe we could discuss
>> the integration there?
>
> Unfortunately, not this year.
>
>>
>> Here a first review of the source code.
>
> Thanks! This is great! There are a few inline comments; but for the most
> part I'll makes the changes as suggested.

>>> +      if (const SCEVConstant *ConstOffSCEV =
>>> +            dyn_cast<SCEVConstant>(RelOffSCEV)) {
>>> +        ConstantInt *IntOff = ConstOffSCEV->getValue();
>>> +        int64_t off = IntOff->getSExtValue();
>>> +
>>> +        Type *VTy = cast<PointerType>(Iptr->getType())->getElementType();
>>
>> You should assert that the types of both pointers are indentical.
>
> This is done implicitly in all calling code. This, however, should be
> documented as a precondition of the function.

Yes. And just put an assert in the function that checks this. This does 
not cost a lot and may save someone who did not read the comment.

>> Also you should document that this function only works for vector types.
>> I actually expected it to just work for scalar types. Vector types look
>> a little bit wired here and I am actually not even sure if it is correct
>> for vector types.
>
> What do you mean by working only for vector types? I don't think that's
> true. As I recall, it seemed to work find for both loads and stores
> using both scalar pointers and vector pointers.

Oh sorry. I thought getElementType() returns the element of a vector. 
However, it returns the type pointed to by the pointer.

>>> +        int64_t VTy_tss = (int64_t) TD.getTypeStoreSize(VTy);
>>> +
>>> +        if (off == VTy_tss) {
>>> +          return 1;
>>> +        } else if (-off == VTy_tss) {
>>> +          return -1;
>>> +        }
>> Braces not needed.
>>
>>> +      }
>> Did you think of using SE.getSizeOfExpr()?
>
> Yes. ;)
>
> I did not for two reasons. First, if we have target data, which we need
> for load/store vectorization anyway, then it is unnecessary because the
> sizeof gets constant folded. Thus, that division is just an integer
> division in the relevant cases anyway.
True.

>
> Second, correct me if I'm wrong, but I would need a signed division, not
> an unsigned division.

At least I cannot convince myself that UDiv is always correct. Just 
leave it like this now.

>>> +        if (FastDep) {
>>> +          // Note: For this heuristic to be effective, independent operations
>>> +          // must tend to be intermixed. This is likely to be true from some
>>> +          // kinds of loop unrolling (but not the generic LLVM pass),
>>> +          // but otherwise may require some kind of reordering pass.
>>
>> What does it mean that independent operations must be intermixed? Can
>> you give an example?
>
> It means that if you group variables into independent groups, say A and
> B, such that things in B don't use results from A and vice-verse, and
> then have: A B A B A B A B... then FastDep will be able to, if the
> instruction are otherwise compatible, vectorize to make<A B>  <A B>...
> On the other hand, if you have A A A A B B B B, then you need a full
> search and dependency analysis to determine that you can move some of
> the Bs ahead of the preceding As in order to vectorize them.

Basically this means FastDep would be sufficient, if you do grouped 
unrolling?

> Will do, and thanks again. I'll send an updated patch soon.

Great!

Tobi

From grosser at fim.uni-passau.de  Thu Nov 17 13:10:48 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 17 Nov 2011 19:10:48 -0000
Subject: [llvm-commits] [polly] r144917 - in /polly/trunk:
 lib/RegisterPasses.cpp www/example_load_Polly_into_clang.html
Message-ID: <20111117191048.AFE522A6C133@llvm.org>

Author: grosser
Date: Thu Nov 17 13:10:48 2011
New Revision: 144917

URL: http://llvm.org/viewvc/llvm-project?rev=144917&view=rev
Log:
RegisterPass: Disable Polly by default

We disable Polly by default and add a new option '-polly' that enables Polly.
This allows us to create an the alias

$ alias clang clang -Xclang -load -Xclang LLVMPolly.so

which loads Polly always into clang. It can now be enabled by running:

$ clang -O3 -mllvm -polly file.c

To enable it by default an alias pollycc can be create

$ alias pollycc clang -O3 -mllvm -polly

Modified:
    polly/trunk/lib/RegisterPasses.cpp
    polly/trunk/www/example_load_Polly_into_clang.html

Modified: polly/trunk/lib/RegisterPasses.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/RegisterPasses.cpp?rev=144917&r1=144916&r2=144917&view=diff
==============================================================================
--- polly/trunk/lib/RegisterPasses.cpp (original)
+++ polly/trunk/lib/RegisterPasses.cpp Thu Nov 17 13:10:48 2011
@@ -29,6 +29,10 @@
 using namespace llvm;
 
 static cl::opt<bool>
+PollyEnabled("polly", cl::desc("Enable the default passes of Polly in -O3"),
+             cl::init(false));
+
+static cl::opt<bool>
 DisableScheduler("polly-no-optimizer",
                  cl::desc("Disable Polly Scheduling Optimizer"), cl::Hidden,
                  cl::init(false));
@@ -104,12 +108,37 @@
 
 static void registerPollyPasses(const llvm::PassManagerBuilder &Builder,
                                 llvm::PassManagerBase &PM) {
-  bool RunScheduler = !DisableScheduler;
-  bool RunCodegen = !DisableCodegen;
+  if (PollyOnlyPrinter || PollyPrinter || PollyOnlyViewer || PollyViewer ||
+      ExportJScop || ImportJScop)
+    PollyEnabled = true;
+
+  if (!PollyEnabled) {
+    if (UsePocc)
+      errs() << "The option -polly-use-pocc has no effect. "
+                "Polly was not enabled\n";
+
+    if (DisableCodegen)
+      errs() << "The option -polly-no-codegen has no effect. "
+                "Polly was not enabled\n";
+
+    if (DisableScheduler)
+      errs() << "The option -polly-no-optimizer has no effect. "
+                "Polly was not enabled\n";
+
+    return;
+  }
 
   // Polly is only enabled at -O3
-  if (Builder.OptLevel != 3)
+  if (Builder.OptLevel != 3) {
+    errs() << "Polly should only be run with -O3. Disabling Polly.\n";
     return;
+  }
+
+  bool RunScheduler = !DisableScheduler;
+  bool RunCodegen = !DisableCodegen;
+
+
+
 
   // A standard set of optimization passes partially taken/copied from the
   // set of default optimization passes. It is used to bring the code into

Modified: polly/trunk/www/example_load_Polly_into_clang.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/example_load_Polly_into_clang.html?rev=144917&r1=144916&r2=144917&view=diff
==============================================================================
--- polly/trunk/www/example_load_Polly_into_clang.html (original)
+++ polly/trunk/www/example_load_Polly_into_clang.html Thu Nov 17 13:10:48 2011
@@ -15,37 +15,49 @@
 <h1>Load Polly into clang and automatically run it at -O3</h1>
 <!--=====================================================================-->
 
-<p>Warning: This example makes it very easy to use Polly. Still, please be aware
-that Polly is a young research project. It is expected to crash, produce
-invalid code or to hang in complex calculations even for simple examples. In
-case you see such a problem, please check the <a href="bugs.html">Bug
-database</a> and consider reporting the bug.
-<h2>Compiling code with Polly</h2>
-
-To compile code with Polly you only need to add <b>-Xclang -load -Xclang
-${POLLY_BUILD_DIR}/lib/LLVMPolly.so</b> to your command line or your CFLAGS and
-Polly is automatically executed at -O3.
-
+<p><b>Warning:</b> Even though this example makes it very easy to use Polly,
+you should be aware that Polly is a young research project. It is expected
+to crash, produce invalid code or to hang in complex calculations even for
+simple examples. In case you see such a problem, please check the <a
+href="bugs.html">Bug database</a> and consider reporting a bug.
 <p>
-<b>WARNING: clang/LLVM/Polly need to be in sync. This means
+<b>Warning II:</b> clang/LLVM/Polly need to be in sync. This means
             you need to compile them yourself from a recent svn/git checkout</b>
-            </p>
+<h2>Load Polly into clang</h2>
+
+By loading Polly into clang (or opt) the Polly options become automatically
+available. You can load Polly either by adding the relevant commands to
+the CPPFLAGS or by creating an alias.
+
+<pre class="code">
+$ export CPPFLAGS="-Xclang -load -Xclang ${POLLY_BUILD_DIR}/lib/LLVMPolly.so"
+</pre>
+
+or
+<pre class="code">
+$ alias pollycc clang -Xclang -load -Xclang ${POLLY_BUILD_DIR}/lib/LLVMPolly.so
+</pre>
+
+<h2>Optimizing with Polly</h2>
+
+Optimizing with Polly is as easy as ading <b>-O3 -polly</b> to your compiler
+flags (Polly is only available at -O3).
 
-<pre class="code">clang -Xclang -load -Xclang ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 file.c</pre>
+<pre class="code">pollycc -O3 -polly file.c</pre>
 
 <h2>Automatic OpenMP code generation</h2>
 
 To automatically detect parallel loops and generate OpenMP code for them you
 also need to add <b>-mllvm -enable-polly-openmp -lgomp</b> to your CFLAGS.
 
-<pre class="code">clang -Xclang -load -Xclang ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 -mllvm -enable-polly-openmp -lgomp file.c</pre>
+<pre class="code">pollycc -O3 -mllvm -enable-polly-openmp -lgomp file.c</pre>
 
 <h2>Automatic Vector code generation</h2>
 
 Automatic vector code generation can be enabled by adding <b>-mllvm
 -enable-polly-vector</b> to your CFLAGS.
 
-<pre class="code">clang -Xclang -load -Xclang ${POLLY_BUILD_DIR}/lib/LLVMPolly.so -O3 -mllvm -enable-polly-vector file.c</pre>
+<pre class="code">pollycc -O3 -mllvm -enable-polly-vector file.c</pre>
 
 <h2>Further options</h2>
 



From hfinkel at anl.gov  Thu Nov 17 13:30:35 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Thu, 17 Nov 2011 13:30:35 -0600
Subject: [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
In-Reply-To: <4EC55C72.8020001@grosser.es>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
	<1319919418.23036.881.camel@sapling>
	<1319928991.23036.957.camel@sapling>
	<1320108633.23036.1266.camel@sapling>
	<1320172356.23036.1298.camel@sapling>
	<4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling>
	<1320191694.23036.1497.camel@sapling>
	<1320749109.19359.76.camel@sapling>
	<4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling>
	<4EB98207.2070807@grosser.es> <1320791390.19359.262.camel@sapling>
	<4EBC4B0F.6010609@grosser.es> <1321050998.19359.539.camel@sapling>
	<4EBDA7F9.9080709@grosser.es> <1321053083.19359.550.camel@sapling>
	<4EBDB1BF.7090006@grosser.es>  <1321400339.19359.782.camel@sapling>
	<1321486739.19359.1067.camel@sapling>  <4EC504B5.2020408@grosser.es>
	<1321552890.19359.1327.camel@sapling>  <4EC55C72.8020001@grosser.es>
Message-ID: <1321558235.19359.1339.camel@sapling>

On Thu, 2011-11-17 at 11:11 -0800, Tobias Grosser wrote:
> On 11/17/2011 10:01 AM, Hal Finkel wrote:
> > On Thu, 2011-11-17 at 13:57 +0100, Tobias Grosser wrote:
> >> On 11/17/2011 12:38 AM, Hal Finkel wrote:
> >>> Tobias, et al.,
> >>>
> >>> Attached is the my autovectorization pass.
> >>
> >> Very nice. Will you be at the developer summit? Maybe we could discuss
> >> the integration there?
> >
> > Unfortunately, not this year.
> >
> >>
> >> Here a first review of the source code.
> >
> > Thanks! This is great! There are a few inline comments; but for the most
> > part I'll makes the changes as suggested.
> 
> >>> +      if (const SCEVConstant *ConstOffSCEV =
> >>> +            dyn_cast<SCEVConstant>(RelOffSCEV)) {
> >>> +        ConstantInt *IntOff = ConstOffSCEV->getValue();
> >>> +        int64_t off = IntOff->getSExtValue();
> >>> +
> >>> +        Type *VTy = cast<PointerType>(Iptr->getType())->getElementType();
> >>
> >> You should assert that the types of both pointers are indentical.
> >
> > This is done implicitly in all calling code. This, however, should be
> > documented as a precondition of the function.
> 
> Yes. And just put an assert in the function that checks this. This does 
> not cost a lot and may save someone who did not read the comment.

Good suggestion.

> 
> >> Also you should document that this function only works for vector types.
> >> I actually expected it to just work for scalar types. Vector types look
> >> a little bit wired here and I am actually not even sure if it is correct
> >> for vector types.
> >
> > What do you mean by working only for vector types? I don't think that's
> > true. As I recall, it seemed to work find for both loads and stores
> > using both scalar pointers and vector pointers.
> 
> Oh sorry. I thought getElementType() returns the element of a vector. 
> However, it returns the type pointed to by the pointer.
> 
> >>> +        int64_t VTy_tss = (int64_t) TD.getTypeStoreSize(VTy);
> >>> +
> >>> +        if (off == VTy_tss) {
> >>> +          return 1;
> >>> +        } else if (-off == VTy_tss) {
> >>> +          return -1;
> >>> +        }
> >> Braces not needed.
> >>
> >>> +      }
> >> Did you think of using SE.getSizeOfExpr()?
> >
> > Yes. ;)
> >
> > I did not for two reasons. First, if we have target data, which we need
> > for load/store vectorization anyway, then it is unnecessary because the
> > sizeof gets constant folded. Thus, that division is just an integer
> > division in the relevant cases anyway.
> True.
> 
> >
> > Second, correct me if I'm wrong, but I would need a signed division, not
> > an unsigned division.
> 
> At least I cannot convince myself that UDiv is always correct. Just 
> leave it like this now.
> 
> >>> +        if (FastDep) {
> >>> +          // Note: For this heuristic to be effective, independent operations
> >>> +          // must tend to be intermixed. This is likely to be true from some
> >>> +          // kinds of loop unrolling (but not the generic LLVM pass),
> >>> +          // but otherwise may require some kind of reordering pass.
> >>
> >> What does it mean that independent operations must be intermixed? Can
> >> you give an example?
> >
> > It means that if you group variables into independent groups, say A and
> > B, such that things in B don't use results from A and vice-verse, and
> > then have: A B A B A B A B... then FastDep will be able to, if the
> > instruction are otherwise compatible, vectorize to make<A B>  <A B>...
> > On the other hand, if you have A A A A B B B B, then you need a full
> > search and dependency analysis to determine that you can move some of
> > the Bs ahead of the preceding As in order to vectorize them.
> 
> Basically this means FastDep would be sufficient, if you do grouped 
> unrolling?

Yes, I believe this is correct.

 -Hal

> 
> > Will do, and thanks again. I'll send an updated patch soon.
> 
> Great!
> 
> Tobi

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From mcrosier at apple.com  Thu Nov 17 15:46:13 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Thu, 17 Nov 2011 21:46:13 -0000
Subject: [llvm-commits] [llvm] r144920 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20111117214613.41D592A6C133@llvm.org>

Author: mcrosier
Date: Thu Nov 17 15:46:13 2011
New Revision: 144920

URL: http://llvm.org/viewvc/llvm-project?rev=144920&view=rev
Log:
Add TODO comment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144920&r1=144919&r2=144920&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Nov 17 15:46:13 2011
@@ -684,6 +684,8 @@
   return 0;
 }
 
+// TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
+
 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
   // Don't handle dynamic allocas.
   if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;



From kremenek at apple.com  Thu Nov 17 17:02:14 2011
From: kremenek at apple.com (Ted Kremenek)
Date: Thu, 17 Nov 2011 23:02:14 -0000
Subject: [llvm-commits] [llvm] r144931 -
	/llvm/trunk/include/llvm/ADT/IntrusiveRefCntPtr.h
Message-ID: <20111117230214.EB5BC2A6C133@llvm.org>

Author: kremenek
Date: Thu Nov 17 17:02:14 2011
New Revision: 144931

URL: http://llvm.org/viewvc/llvm-project?rev=144931&view=rev
Log:
Fix bug in RefCountedBase/RefCountedBaseVPTR where the reference count was accidentally copied as part of the copy constructor.  This could result in objects getting leaked because there reference count was too high.

Modified:
    llvm/trunk/include/llvm/ADT/IntrusiveRefCntPtr.h

Modified: llvm/trunk/include/llvm/ADT/IntrusiveRefCntPtr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/IntrusiveRefCntPtr.h?rev=144931&r1=144930&r2=144931&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/IntrusiveRefCntPtr.h (original)
+++ llvm/trunk/include/llvm/ADT/IntrusiveRefCntPtr.h Thu Nov 17 17:02:14 2011
@@ -46,6 +46,7 @@
 
   public:
     RefCountedBase() : ref_cnt(0) {}
+    RefCountedBase(const RefCountedBase &) : ref_cnt(0) {}
 
     void Retain() const { ++ref_cnt; }
     void Release() const {
@@ -67,6 +68,8 @@
 
   protected:
     RefCountedBaseVPTR() : ref_cnt(0) {}
+    RefCountedBaseVPTR(const RefCountedBaseVPTR &) : ref_cnt(0) {}
+
     virtual ~RefCountedBaseVPTR() {}
 
     void Retain() const { ++ref_cnt; }



From kcc at google.com  Thu Nov 17 17:15:00 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 17 Nov 2011 23:15:00 -0000
Subject: [llvm-commits] [llvm] r144933 - in /llvm/trunk:
 lib/Transforms/Instrumentation/AddressSanitizer.cpp
 test/Instrumentation/AddressSanitizer/do-not-touch-odr-global.ll
Message-ID: <20111117231500.0BD8C2A6C133@llvm.org>

Author: kcc
Date: Thu Nov 17 17:14:59 2011
New Revision: 144933

URL: http://llvm.org/viewvc/llvm-project?rev=144933&view=rev
Log:
fall back to explicit list of allowed linkages when instrumenting globals in asan; add a test check that asan does not touch linkonce_odr

Added:
    llvm/trunk/test/Instrumentation/AddressSanitizer/do-not-touch-odr-global.ll
Modified:
    llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Modified: llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp?rev=144933&r1=144932&r2=144933&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Thu Nov 17 17:14:59 2011
@@ -448,8 +448,11 @@
 
     if (!Ty->isSized()) continue;
     if (!G->hasInitializer()) continue;
-    if (GlobalVariable::mayBeOverridden(G->getLinkage()) ||
-        G->getLinkage() == GlobalVariable::AppendingLinkage)
+    // Touch only those globals that will not be defined in other modules.
+    // Don't handle ODR type linkages since other modules may be built w/o asan.
+    if (G->getLinkage() != GlobalVariable::GlobalVariable::ExternalLinkage &&
+        G->getLinkage() != GlobalVariable::GlobalVariable::PrivateLinkage &&
+        G->getLinkage() != GlobalVariable::GlobalVariable::InternalLinkage)
       continue;
     // For now, just ignore this Alloca if the alignment is large.
     if (G->getAlignment() > RedzoneSize) continue;

Added: llvm/trunk/test/Instrumentation/AddressSanitizer/do-not-touch-odr-global.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Instrumentation/AddressSanitizer/do-not-touch-odr-global.ll?rev=144933&view=auto
==============================================================================
--- llvm/trunk/test/Instrumentation/AddressSanitizer/do-not-touch-odr-global.ll (added)
+++ llvm/trunk/test/Instrumentation/AddressSanitizer/do-not-touch-odr-global.ll Thu Nov 17 17:14:59 2011
@@ -0,0 +1,6 @@
+; RUN: opt < %s -asan -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+; no action should be taken for these globals
+ at v1 = linkonce_odr constant i8 1
+; CHECK-NOT: __asan_register_globals



From geek4civic at gmail.com  Thu Nov 17 17:36:12 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Fri, 18 Nov 2011 08:36:12 +0900
Subject: [llvm-commits] [llvm] r144933 - in /llvm/trunk:
 lib/Transforms/Instrumentation/AddressSanitizer.cpp
 test/Instrumentation/AddressSanitizer/do-not-touch-odr-global.ll
In-Reply-To: <20111117231500.0BD8C2A6C133@llvm.org>
References: <20111117231500.0BD8C2A6C133@llvm.org>
Message-ID: <CADiQthMnj5yKEGYT0Vg3MHKE5OozNEso15pr1GHFsAMCNUOVNA@mail.gmail.com>

Kostya,

> --- llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp (original)
> +++ llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Thu Nov 17 17:14:59 2011
> @@ -448,8 +448,11 @@
>
> ? ? if (!Ty->isSized()) continue;
> ? ? if (!G->hasInitializer()) continue;
> - ? ?if (GlobalVariable::mayBeOverridden(G->getLinkage()) ||
> - ? ? ? ?G->getLinkage() == GlobalVariable::AppendingLinkage)
> + ? ?// Touch only those globals that will not be defined in other modules.
> + ? ?// Don't handle ODR type linkages since other modules may be built w/o asan.
> + ? ?if (G->getLinkage() != GlobalVariable::GlobalVariable::ExternalLinkage &&
> + ? ? ? ?G->getLinkage() != GlobalVariable::GlobalVariable::PrivateLinkage &&
> + ? ? ? ?G->getLinkage() != GlobalVariable::GlobalVariable::InternalLinkage)
> ? ? ? continue;
> ? ? // For now, just ignore this Alloca if the alignment is large.
> ? ? if (G->getAlignment() > RedzoneSize) continue;

What is "GlobalVariable::GlobalVariable::"?
FYI, MSVC does not accept them.

...Takumi


From pichet2000 at gmail.com  Thu Nov 17 17:36:58 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Thu, 17 Nov 2011 18:36:58 -0500
Subject: [llvm-commits] [llvm] r144933 - in /llvm/trunk:
 lib/Transforms/Instrumentation/AddressSanitizer.cpp
 test/Instrumentation/AddressSanitizer/do-not-touch-odr-global.ll
In-Reply-To: <20111117231500.0BD8C2A6C133@llvm.org>
References: <20111117231500.0BD8C2A6C133@llvm.org>
Message-ID: <CAH_MvcXB+H0FMwTacM6HLdBCJt0OvPZMYUQ_mzF0XNLAHL94DA@mail.gmail.com>

On Thu, Nov 17, 2011 at 6:15 PM, Kostya Serebryany <kcc at google.com> wrote:
> Author: kcc
> Date: Thu Nov 17 17:14:59 2011
> New Revision: 144933
>
> URL: http://llvm.org/viewvc/llvm-project?rev=144933&view=rev
> Log:
> fall back to explicit list of allowed linkages when instrumenting globals in asan; add a test check that asan does not touch linkonce_odr
>
> Added:
> ? ?llvm/trunk/test/Instrumentation/AddressSanitizer/do-not-touch-odr-global.ll
> Modified:
> ? ?llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
>
> Modified: llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp?rev=144933&r1=144932&r2=144933&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp (original)
> +++ llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Thu Nov 17 17:14:59 2011
> @@ -448,8 +448,11 @@
>
> ? ? if (!Ty->isSized()) continue;
> ? ? if (!G->hasInitializer()) continue;
> - ? ?if (GlobalVariable::mayBeOverridden(G->getLinkage()) ||
> - ? ? ? ?G->getLinkage() == GlobalVariable::AppendingLinkage)
> + ? ?// Touch only those globals that will not be defined in other modules.
> + ? ?// Don't handle ODR type linkages since other modules may be built w/o asan.
> + ? ?if (G->getLinkage() != GlobalVariable::GlobalVariable::ExternalLinkage &&
> + ? ? ? ?G->getLinkage() != GlobalVariable::GlobalVariable::PrivateLinkage &&
> + ? ? ? ?G->getLinkage() != GlobalVariable::GlobalVariable::InternalLinkage)

GlobalVariable::GlobalVariable?
I don't know if that's valid but MSVC doesn't like it.


From kcc at google.com  Thu Nov 17 17:37:40 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 17 Nov 2011 15:37:40 -0800
Subject: [llvm-commits] [llvm] r144933 - in /llvm/trunk:
 lib/Transforms/Instrumentation/AddressSanitizer.cpp
 test/Instrumentation/AddressSanitizer/do-not-touch-odr-global.ll
In-Reply-To: <CADiQthMnj5yKEGYT0Vg3MHKE5OozNEso15pr1GHFsAMCNUOVNA@mail.gmail.com>
References: <20111117231500.0BD8C2A6C133@llvm.org>
	<CADiQthMnj5yKEGYT0Vg3MHKE5OozNEso15pr1GHFsAMCNUOVNA@mail.gmail.com>
Message-ID: <CAN=P9phu7oip2CY1gyvEw5FodQZjxPV3Ct3YEhLrSS74V_pNYQ@mail.gmail.com>

On Thu, Nov 17, 2011 at 3:36 PM, NAKAMURA Takumi <geek4civic at gmail.com>wrote:

> Kostya,
>
> > --- llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
> (original)
> > +++ llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Thu
> Nov 17 17:14:59 2011
> > @@ -448,8 +448,11 @@
> >
> >     if (!Ty->isSized()) continue;
> >     if (!G->hasInitializer()) continue;
> > -    if (GlobalVariable::mayBeOverridden(G->getLinkage()) ||
> > -        G->getLinkage() == GlobalVariable::AppendingLinkage)
> > +    // Touch only those globals that will not be defined in other
> modules.
> > +    // Don't handle ODR type linkages since other modules may be built
> w/o asan.
> > +    if (G->getLinkage() !=
> GlobalVariable::GlobalVariable::ExternalLinkage &&
> > +        G->getLinkage() !=
> GlobalVariable::GlobalVariable::PrivateLinkage &&
> > +        G->getLinkage() !=
> GlobalVariable::GlobalVariable::InternalLinkage)
> >       continue;
> >     // For now, just ignore this Alloca if the alignment is large.
> >     if (G->getAlignment() > RedzoneSize) continue;
>
> What is "GlobalVariable::GlobalVariable::"?
>
Ouch! Thanks for the post review! Will fix shortly.

--kcc

> FYI, MSVC does not accept them.
>
> ...Takumi
>
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From atrick at apple.com  Thu Nov 17 17:36:35 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 17 Nov 2011 23:36:35 -0000
Subject: [llvm-commits] [llvm] r144935 - in /llvm/trunk:
 lib/Transforms/Utils/SimplifyIndVar.cpp
 test/Transforms/IndVarSimplify/2011-11-17-selfphi.ll
Message-ID: <20111117233636.050452A6C133@llvm.org>

Author: atrick
Date: Thu Nov 17 17:36:35 2011
New Revision: 144935

URL: http://llvm.org/viewvc/llvm-project?rev=144935&view=rev
Log:
Fix an overly general check in SimplifyIndvar to handle useless phi cycles.

The right way to check for a binary operation is
cast<BinaryOperator>. The original check: cast<Instruction> &&
numOperands() == 2 would match phi "instructions", leading to an
infinite loop in extreme corner case: a useless phi with operands
[self, constant] that prior optimization passes failed to remove,
being used in the loop by another useless phi, in turn being used by an
lshr or udiv.

Fixes PR11350: runaway iteration assertion.

Added:
    llvm/trunk/test/Transforms/IndVarSimplify/2011-11-17-selfphi.ll
Modified:
    llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp?rev=144935&r1=144934&r2=144935&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyIndVar.cpp Thu Nov 17 17:36:35 2011
@@ -107,8 +107,8 @@
 
     // Attempt to fold a binary operator with constant operand.
     // e.g. ((I + 1) >> 2) => I >> 2
-    if (IVOperand->getNumOperands() != 2 ||
-        !isa<ConstantInt>(IVOperand->getOperand(1)))
+    if (!isa<BinaryOperator>(IVOperand)
+        || !isa<ConstantInt>(IVOperand->getOperand(1)))
       return 0;
 
     IVSrc = IVOperand->getOperand(0);

Added: llvm/trunk/test/Transforms/IndVarSimplify/2011-11-17-selfphi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2011-11-17-selfphi.ll?rev=144935&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/2011-11-17-selfphi.ll (added)
+++ llvm/trunk/test/Transforms/IndVarSimplify/2011-11-17-selfphi.ll Thu Nov 17 17:36:35 2011
@@ -0,0 +1,29 @@
+; RUN: opt < %s -indvars -S | FileCheck %s
+; PR11350: Check that SimplifyIndvar handles a cycle of useless self-phis.
+
+; CHECK: @test
+; CHECK-NOT: lcssa = phi
+define void @test() nounwind {
+entry:
+  br label %for.cond.preheader
+
+for.cond.preheader:                               ; preds = %entry
+  br label %for.cond.outer
+
+for.cond.outer:                                   ; preds = %for.cond.preheader, %for.end
+  %p_41.addr.0.ph = phi i32 [ %p_41.addr.1.lcssa, %for.end ], [ 1, %for.cond.preheader ]
+  br label %for.cond
+
+for.cond:
+  br i1 true, label %for.end, label %for.ph
+
+for.ph:                                   ; preds = %for.cond4.preheader
+  br label %for.end
+
+for.end:
+  %p_41.addr.1.lcssa = phi i32 [ undef, %for.ph ], [ %p_41.addr.0.ph, %for.cond ]
+  %p_68.lobit.i = lshr i32 %p_41.addr.1.lcssa, 31
+  %cmp7 = icmp eq i32 %p_41.addr.1.lcssa, 0
+  %conv8 = zext i1 %cmp7 to i32
+  br label %for.cond.outer
+}



From kcc at google.com  Thu Nov 17 17:37:54 2011
From: kcc at google.com (Kostya Serebryany)
Date: Thu, 17 Nov 2011 23:37:54 -0000
Subject: [llvm-commits] [llvm] r144936 -
 /llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
Message-ID: <20111117233754.2095C2A6C133@llvm.org>

Author: kcc
Date: Thu Nov 17 17:37:53 2011
New Revision: 144936

URL: http://llvm.org/viewvc/llvm-project?rev=144936&view=rev
Log:
quick fix: remove GlobalVariable::GlobalVariable mistakenly commited at r144933. For some reason this compiles on linux 

Modified:
    llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Modified: llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp?rev=144936&r1=144935&r2=144936&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Thu Nov 17 17:37:53 2011
@@ -450,9 +450,9 @@
     if (!G->hasInitializer()) continue;
     // Touch only those globals that will not be defined in other modules.
     // Don't handle ODR type linkages since other modules may be built w/o asan.
-    if (G->getLinkage() != GlobalVariable::GlobalVariable::ExternalLinkage &&
-        G->getLinkage() != GlobalVariable::GlobalVariable::PrivateLinkage &&
-        G->getLinkage() != GlobalVariable::GlobalVariable::InternalLinkage)
+    if (G->getLinkage() != GlobalVariable::ExternalLinkage &&
+        G->getLinkage() != GlobalVariable::PrivateLinkage &&
+        G->getLinkage() != GlobalVariable::InternalLinkage)
       continue;
     // For now, just ignore this Alloca if the alignment is large.
     if (G->getAlignment() > RedzoneSize) continue;



From dpatel at apple.com  Thu Nov 17 17:43:16 2011
From: dpatel at apple.com (Devang Patel)
Date: Thu, 17 Nov 2011 23:43:16 -0000
Subject: [llvm-commits] [llvm] r144937 - in /llvm/trunk:
 include/llvm/Analysis/DebugInfo.h
 lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
 test/CodeGen/X86/dbg-subrange.ll
Message-ID: <20111117234316.4E6F22A6C133@llvm.org>

Author: dpatel
Date: Thu Nov 17 17:43:15 2011
New Revision: 144937

URL: http://llvm.org/viewvc/llvm-project?rev=144937&view=rev
Log:
DISubrange supports unsigned lower/upper array bounds, so let's not fake it in the end while emitting DWARF. If a FE needs to encode signed lower/upper array bounds then we need to extend DISubrange or ad DISignedSubrange. 

Added:
    llvm/trunk/test/CodeGen/X86/dbg-subrange.ll
Modified:
    llvm/trunk/include/llvm/Analysis/DebugInfo.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp

Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=144937&r1=144936&r2=144937&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Thu Nov 17 17:43:15 2011
@@ -135,8 +135,8 @@
   public:
     explicit DISubrange(const MDNode *N = 0) : DIDescriptor(N) {}
 
-    int64_t getLo() const { return (int64_t)getUInt64Field(1); }
-    int64_t getHi() const { return (int64_t)getUInt64Field(2); }
+    uint64_t getLo() const { return getUInt64Field(1); }
+    uint64_t getHi() const { return getUInt64Field(2); }
   };
 
   /// DIArray - This descriptor holds an array of descriptors.

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=144937&r1=144936&r2=144937&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Thu Nov 17 17:43:15 2011
@@ -1154,8 +1154,8 @@
 void CompileUnit::constructSubrangeDIE(DIE &Buffer, DISubrange SR, DIE *IndexTy){
   DIE *DW_Subrange = new DIE(dwarf::DW_TAG_subrange_type);
   addDIEEntry(DW_Subrange, dwarf::DW_AT_type, dwarf::DW_FORM_ref4, IndexTy);
-  int64_t L = SR.getLo();
-  int64_t H = SR.getHi();
+  uint64_t L = SR.getLo();
+  uint64_t H = SR.getHi();
 
   // The L value defines the lower bounds which is typically zero for C/C++. The
   // H value is the upper bounds.  Values are 64 bit.  H - L + 1 is the size
@@ -1168,8 +1168,8 @@
     return;
   }
   if (L)
-    addSInt(DW_Subrange, dwarf::DW_AT_lower_bound, 0, L);
-  addSInt(DW_Subrange, dwarf::DW_AT_upper_bound, 0, H);
+    addUInt(DW_Subrange, dwarf::DW_AT_lower_bound, 0, L);
+  addUInt(DW_Subrange, dwarf::DW_AT_upper_bound, 0, H);
   Buffer.addChild(DW_Subrange);
 }
 

Added: llvm/trunk/test/CodeGen/X86/dbg-subrange.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-subrange.ll?rev=144937&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-subrange.ll (added)
+++ llvm/trunk/test/CodeGen/X86/dbg-subrange.ll Thu Nov 17 17:43:15 2011
@@ -0,0 +1,37 @@
+; RUN: llc -O0 < %s | FileCheck %s
+; Radar 10464995
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.7.2"
+
+ at s = common global [4294967296 x i8] zeroinitializer, align 16
+;CHECK: .long	4294967295
+
+define void @bar() nounwind uwtable ssp {
+entry:
+  store i8 97, i8* getelementptr inbounds ([4294967296 x i8]* @s, i32 0, i64 0), align 1, !dbg !18
+  ret void, !dbg !20
+}
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"small.c", metadata !"/private/tmp", metadata !"clang version 3.1 (trunk 144833)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !11} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{metadata !2}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{metadata !5}
+!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @bar, null, null, metadata !9} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !"small.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!8 = metadata !{null}
+!9 = metadata !{metadata !10}
+!10 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
+!11 = metadata !{metadata !12}
+!12 = metadata !{metadata !13}
+!13 = metadata !{i32 720948, i32 0, null, metadata !"s", metadata !"s", metadata !"", metadata !6, i32 2, metadata !14, i32 0, i32 1, [4294967296 x i8]* @s} ; [ DW_TAG_variable ]
+!14 = metadata !{i32 720897, null, metadata !"", null, i32 0, i64 34359738368, i64 8, i32 0, i32 0, metadata !15, metadata !16, i32 0, i32 0} ; [ DW_TAG_array_type ]
+!15 = metadata !{i32 720932, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!16 = metadata !{metadata !17}
+!17 = metadata !{i32 720929, i64 0, i64 4294967295} ; [ DW_TAG_subrange_type ]
+!18 = metadata !{i32 5, i32 3, metadata !19, null}
+!19 = metadata !{i32 720907, metadata !5, i32 4, i32 1, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!20 = metadata !{i32 6, i32 1, metadata !19, null}



From mcrosier at apple.com  Thu Nov 17 19:17:34 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Fri, 18 Nov 2011 01:17:34 -0000
Subject: [llvm-commits] [llvm] r144959 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20111118011734.56FA32A6C133@llvm.org>

Author: mcrosier
Date: Thu Nov 17 19:17:34 2011
New Revision: 144959

URL: http://llvm.org/viewvc/llvm-project?rev=144959&view=rev
Log:
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=144959&r1=144958&r2=144959&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Nov 17 19:17:34 2011
@@ -2108,9 +2108,6 @@
     if (IntrMemName && e-i <= 2)
       break;
 
-    unsigned Arg = getRegForValue(*i);
-    if (Arg == 0)
-      return false;
     ISD::ArgFlagsTy Flags;
     unsigned AttrInd = i - CS.arg_begin() + 1;
     if (CS.paramHasAttr(AttrInd, Attribute::SExt))
@@ -2130,6 +2127,11 @@
     if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
         ArgVT != MVT::i1)
       return false;
+
+    unsigned Arg = getRegForValue(*i);
+    if (Arg == 0)
+      return false;
+
     unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
     Flags.setOrigAlign(OriginalAlignment);
 



From kcc at google.com  Thu Nov 17 19:41:06 2011
From: kcc at google.com (Kostya Serebryany)
Date: Fri, 18 Nov 2011 01:41:06 -0000
Subject: [llvm-commits] [llvm] r144962 - in /llvm/trunk:
 lib/Transforms/Instrumentation/AddressSanitizer.cpp
 test/Instrumentation/AddressSanitizer/bug_11395.ll
Message-ID: <20111118014106.C0C0E2A6C133@llvm.org>

Author: kcc
Date: Thu Nov 17 19:41:06 2011
New Revision: 144962

URL: http://llvm.org/viewvc/llvm-project?rev=144962&view=rev
Log:
[asan] workaround for reg alloc bug 11395: don't instrument functions with large chunks of inline assembler

Added:
    llvm/trunk/test/Instrumentation/AddressSanitizer/bug_11395.ll
Modified:
    llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Modified: llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp?rev=144962&r1=144961&r2=144962&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Thu Nov 17 19:41:06 2011
@@ -179,6 +179,7 @@
 
   void PoisonStack(const ArrayRef<AllocaInst*> &AllocaVec, IRBuilder<> IRB,
                    Value *ShadowBase, bool DoPoison);
+  bool LooksLikeCodeInBug11395(Instruction *I);
 
   Module      *CurrentModule;
   LLVMContext *C;
@@ -784,6 +785,17 @@
   }
 }
 
+// Workaround for bug 11395: we don't want to instrument stack in functions
+// with large assembly blobs (32-bit only), otherwise reg alloc may crash.
+bool AddressSanitizer::LooksLikeCodeInBug11395(Instruction *I) {
+  if (LongSize != 32) return false;
+  CallInst *CI = dyn_cast<CallInst>(I);
+  if (!CI || !CI->isInlineAsm()) return false;
+  if (CI->getNumArgOperands() <= 5) return false;
+  // We have inline assembly with quite a few arguments.
+  return true;
+}
+
 // Find all static Alloca instructions and put
 // poisoned red zones around all of them.
 // Then unpoison everything back before the function returns.
@@ -810,6 +822,7 @@
     BasicBlock &BB = *FI;
     for (BasicBlock::iterator BI = BB.begin(), BE = BB.end();
          BI != BE; ++BI) {
+      if (LooksLikeCodeInBug11395(BI)) return false;
       if (isa<ReturnInst>(BI)) {
           RetVec.push_back(BI);
           continue;

Added: llvm/trunk/test/Instrumentation/AddressSanitizer/bug_11395.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Instrumentation/AddressSanitizer/bug_11395.ll?rev=144962&view=auto
==============================================================================
--- llvm/trunk/test/Instrumentation/AddressSanitizer/bug_11395.ll (added)
+++ llvm/trunk/test/Instrumentation/AddressSanitizer/bug_11395.ll Thu Nov 17 19:41:06 2011
@@ -0,0 +1,71 @@
+; RUN: opt < %s -asan -S | llc -o /dev/null
+; The bug manifests as a reg alloc failure:
+; error: ran out of registers during register allocation
+; ModuleID = 'z.o'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128"
+target triple = "i386-unknown-linux-gnu"
+
+%struct.DSPContext = type { void (i16*, i8*, i32)*, void (i16*, i8*, i8*, i32)*, void (i16*, i8*, i32)*, void (i16*, i8*, i32)*, void (i16*, i8*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, i32 (i16*)*, void (i8*, i8*, i32, i32, i32, i32, i32)*, void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, void (i16*)*, void (i16*)*, i32 (i8*, i32)*, i32 (i8*, i32)*, [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8
 *, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], i32 (i8*, i16*, i32)*, [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [2 x void (i8*, i8*, i8*, i32, i32)*], [11 x void (i8*, i8*, i32, i32, i32)*], [11 x void (i8*, i8*, i32, i32, i32)*], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [8 x void (i8*, i8*, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [10 x void (i8*, i32, i32,
  i32, i32)*], [10 x void (i8*, i8*, i32, i32, i32, i32, i32)*], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i16*, i32)*, [2 x [4 x i32 (i8*, i8*, i8*, i32, i32)*]], void (i8*, i8*, i32)*, void (i8*, i8*, i8*, i32)*, void (i8*, i8*, i8*, i32)*, void (i8*, i8*, i8*, i32, i32*, i32*)*, void (i8*, i8*, i8*, i32, i32*, i32*)*, i32 (i8*, i8*, i32, i32)*, void (i8*, i8*, i32, i32*, i32*, i32*)*, void (i8*, i8*, i8*, i32, i32)*, void (i32*, i32*, i32)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32)*, void (i8*, i32, i32, i32)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32)*, void (i8*, i32, i32, i32)*, void ([4 x [4 x i16]]*, i8*, [40 x i8]*, [40 x [2 x i16]]*, i32, i32, i32, i32, i32,
  i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32*)*, void (i8*, i32, i32*)*, void (i8*, i8*, i32, i16*, i16*)*, void (float*, float*, i32)*, void ([256 x float]*, [2 x float]*, i32, i32, i32)*, void (i32*, i32, i32, double*)*, void (float*, float*, i32)*, void (float*, float*, float*, i32)*, void (float*, float*, float*, float*, i32)*, void (float*, float*, float*, float*, float, i32)*, void (float*, i32*, float, i32)*, void (float*, float*, float, float, i32)*, void (float*, float*, float, i32)*, [2 x void (float*, float*, float**, float, i32)*], [2 x void (float*, float**, float, i32)*], float (float*, float*, i32)*, void (float*, float*, i32)*, void (i16*, float*, i32)*, void (i16*, float**, i32, i32)*, void (i16*)*, void (i16*)*, void (i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, [64 x i8], i32, i32 (i16*, i16*, i16*, i32)*, void (i16*, i16*, i32)*, void (i8*, i32, i32, i3
 2, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void ([4 x i16]*)*, void (i8*, i32*, i16*, i32, i8*)*, void (i8*, i32*, i16*, i32, i8*)*, void (i8**, i32*, i16*, i32, i8*)*, void (i8*, i32*, i16*, i32, i8*)*, void (i16*, i16*, i16*, i16*, i16*, i16*, i32)*, void (i16*, i32)*, void (i8*, i32, i8**, i32, i32, i32, i32, i32, %struct.slice_buffer_s*, i32, i8*)*, void (i8*, i32, i32)*, [4 x void (i8*, i32, i8*, i32, i32, i32)*], void (i32*, i32*, i32, i32, i32, i32, i32, i32*)*, void (i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32)*, void (i8*, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, [16 x void (i8*, i8*, i32, i32)*], [16 x void (i8*, i8*, i32, i32)*], [12 x void (i8*, i8*, i32)
 *], void (i8*, i8*, i32, i32*, i32*, i32)*, void (i16*, i16*, i32)*, void (i16*, i16*, i32)*, i32 (i16*, i16*, i32, i32)*, [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*] }
+%struct.slice_buffer_s = type opaque
+%struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32, i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, %struct.AVCodec*, i8*, i32, void (%struct.AVCodecContext*, i8*, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, void (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*, float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, 
 i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*)*, i8*, i32*, i32, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i32, float, i64, i32, i64, i64, float, float, %struct.AVHWAccel*, i32, i8*, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*, i32, i32)*, i8*, i32*, i32)*, i32, i32, i32, i32, i32, i32, i8*, float, float, float, float, i32, i32, i32, float, float, float, i32, i32, i32, i32, [4 x i32], i8*, i32, i32, i32, i32 }
+%struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* }
+%struct.AVOption = type opaque
+%struct.AVRational = type { i32, i32 }
+%struct.AVFrame = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*], i64, i8* }
+%struct.AVPanScan = type { i32, i32, i32, [3 x [2 x i16]] }
+%struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, %struct.AVPacket*)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32*, i8*, i32*, i32*, i64* }
+%struct.AVPacket = type { i64, i64, i8*, i32, i32, i32, i32, void (%struct.AVPacket*)*, i8*, i64, i64 }
+%struct.RcOverride = type { i32, i32, i32, float }
+%struct.AVPaletteControl = type { i32, [256 x i32] }
+%struct.AVHWAccel = type { i8*, i32, i32, i32, i32, %struct.AVHWAccel*, i32 (%struct.AVCodecContext*, i8*, i32)*, i32 (%struct.AVCodecContext*, i8*, i32)*, i32 (%struct.AVCodecContext*)*, i32 }
+
+ at firtable = internal unnamed_addr constant [9 x i8*] [i8* @ff_mlp_firorder_0, i8* @ff_mlp_firorder_1, i8* @ff_mlp_firorder_2, i8* @ff_mlp_firorder_3, i8* @ff_mlp_firorder_4, i8* @ff_mlp_firorder_5, i8* @ff_mlp_firorder_6, i8* @ff_mlp_firorder_7, i8* @ff_mlp_firorder_8], align 4
+ at iirtable = internal unnamed_addr constant [5 x i8*] [i8* @ff_mlp_iirorder_0, i8* @ff_mlp_iirorder_1, i8* @ff_mlp_iirorder_2, i8* @ff_mlp_iirorder_3, i8* @ff_mlp_iirorder_4], align 4
+ at ff_mlp_iirorder_0 = external global i8
+ at ff_mlp_iirorder_1 = external global i8
+ at ff_mlp_iirorder_2 = external global i8
+ at ff_mlp_iirorder_3 = external global i8
+ at ff_mlp_iirorder_4 = external global i8
+ at ff_mlp_firorder_0 = external global i8
+ at ff_mlp_firorder_1 = external global i8
+ at ff_mlp_firorder_2 = external global i8
+ at ff_mlp_firorder_3 = external global i8
+ at ff_mlp_firorder_4 = external global i8
+ at ff_mlp_firorder_5 = external global i8
+ at ff_mlp_firorder_6 = external global i8
+ at ff_mlp_firorder_7 = external global i8
+ at ff_mlp_firorder_8 = external global i8
+
+define void @ff_mlp_init_x86(%struct.DSPContext* nocapture %c, %struct.AVCodecContext* nocapture %avctx) nounwind {
+entry:
+  %mlp_filter_channel = getelementptr inbounds %struct.DSPContext* %c, i32 0, i32 131
+  store void (i32*, i32*, i32, i32, i32, i32, i32, i32*)* @mlp_filter_channel_x86, void (i32*, i32*, i32, i32, i32, i32, i32, i32*)** %mlp_filter_channel, align 4, !tbaa !0
+  ret void
+}
+
+define internal void @mlp_filter_channel_x86(i32* %state, i32* %coeff, i32 %firorder, i32 %iirorder, i32 %filter_shift, i32 %mask, i32 %blocksize, i32* %sample_buffer) nounwind {
+entry:
+  %filter_shift.addr = alloca i32, align 4
+  %mask.addr = alloca i32, align 4
+  %blocksize.addr = alloca i32, align 4
+  %firjump = alloca i8*, align 4
+  %iirjump = alloca i8*, align 4
+  store i32 %filter_shift, i32* %filter_shift.addr, align 4, !tbaa !3
+  store i32 %mask, i32* %mask.addr, align 4, !tbaa !3
+  %arrayidx = getelementptr inbounds [9 x i8*]* @firtable, i32 0, i32 %firorder
+  %0 = load i8** %arrayidx, align 4, !tbaa !0
+  store i8* %0, i8** %firjump, align 4, !tbaa !0
+  %arrayidx1 = getelementptr inbounds [5 x i8*]* @iirtable, i32 0, i32 %iirorder
+  %1 = load i8** %arrayidx1, align 4, !tbaa !0
+  store i8* %1, i8** %iirjump, align 4, !tbaa !0
+  %sub = sub nsw i32 0, %blocksize
+  store i32 %sub, i32* %blocksize.addr, align 4, !tbaa !3
+  %2 = call { i32*, i32*, i32* } asm sideeffect "1:                           \0A\09xor           %esi, %esi\0A\09xor           %ecx, %ecx\0A\09jmp  *$5                     \0A\09ff_mlp_firorder_8:            \0A\09mov   0x1c+0($0), %eax\0A\09imull 0x1c+0($1)       \0A\09add                %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_firorder_7:            \0A\09mov   0x18+0($0), %eax\0A\09imull 0x18+0($1)       \0A\09add                %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_firorder_6:            \0A\09mov   0x14+0($0), %eax\0A\09imull 0x14+0($1)       \0A\09add                %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_firorder_5:            \0A\09mov   0x10+0($0), %eax\0A\09imull 0x10+0($1)       \0A\09add                %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_firorder_4:            \0A\09mov   0x0c+0($0), %eax\0A\09imull 0x0c+0($1)       \0A\09add                %eax , %esi\0A\09adc                %e
 dx , %ecx\0A\09ff_mlp_firorder_3:            \0A\09mov   0x08+0($0), %eax\0A\09imull 0x08+0($1)       \0A\09add                %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_firorder_2:            \0A\09mov   0x04+0($0), %eax\0A\09imull 0x04+0($1)       \0A\09add                %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_firorder_1:            \0A\09mov   0x00+0($0), %eax\0A\09imull 0x00+0($1)       \0A\09add                %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_firorder_0:\0A\09jmp  *$6                     \0A\09ff_mlp_iirorder_4:            \0A\09mov   0x0c+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x0c+4* 8($1)       \0A\09add                %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_iirorder_3:            \0A\09mov   0x08+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x08+4* 8($1)       \0A\09add                %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_iirorder_2:            \0A\09mov   0x04+4*(8 + 
 (40 * 4))($0), %eax\0A\09imull 0x04+4* 8($1)       \0A\09add                %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_iirorder_1:            \0A\09mov   0x00+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x00+4* 8($1)       \0A\09add                %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_iirorder_0:\0A\09mov           %ecx, %edx\0A\09mov           %esi, %eax\0A\09movzbl        $7   , %ecx\0A\09shrd    %cl, %edx, %eax\0A\09mov  %eax  ,%edx      \0A\09add  ($2)      ,%eax     \0A\09and   $4       ,%eax     \0A\09sub   $$4       ,  $0         \0A\09mov  %eax, ($0)        \0A\09mov  %eax, ($2)        \0A\09add $$4* 8    ,  $2         \0A\09sub  %edx   ,%eax     \0A\09mov  %eax,4*(8 + (40 * 4))($0)  \0A\09incl              $3         \0A\09js 1b                        \0A\09", "=r,=r,=r,=*m,*m,*m,*m,*m,0,1,2,*m,~{eax},~{edx},~{esi},~{ecx},~{dirflag},~{fpsr},~{flags}"(i32* %blocksize.addr, i32* %mask.addr, i8** %firjump, i8** %iirjump, i32* %filter_sh
 ift.addr, i32* %state, i32* %coeff, i32* %sample_buffer, i32* %blocksize.addr) nounwind, !srcloc !4
+  ret void
+}
+
+!0 = metadata !{metadata !"any pointer", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
+!3 = metadata !{metadata !"int", metadata !1}
+!4 = metadata !{i32 156132, i32 156164, i32 156205, i32 156238, i32 156282, i32 156332, i32 156370, i32 156408, i32 156447, i32 156486, i32 156536, i32 156574, i32 156612, i32 156651, i32 156690, i32 156740, i32 156778, i32 156816, i32 156855, i32 156894, i32 156944, i32 156982, i32 157020, i32 157059, i32 157098, i32 157148, i32 157186, i32 157224, i32 157263, i32 157302, i32 157352, i32 157390, i32 157428, i32 157467, i32 157506, i32 157556, i32 157594, i32 157632, i32 157671, i32 157710, i32 157760, i32 157798, i32 157836, i32 157875, i32 157914, i32 157952, i32 157996, i32 158046, i32 158099, i32 158140, i32 158179, i32 158218, i32 158268, i32 158321, i32 158362, i32 158401, i32 158440, i32 158490, i32 158543, i32 158584, i32 158623, i32 158662, i32 158712, i32 158765, i32 158806, i32 158845, i32 158884, i32 158922, i32 158963, i32 158996, i32 159029, i32 159062, i32 159109, i32 159154, i32 159199, i32 159243, i32 159286, i32 159329, i32 159375, i32 159422, i32 159478, i
 32 159522, i32 159566}



From chandlerc at google.com  Thu Nov 17 19:53:16 2011
From: chandlerc at google.com (Chandler Carruth)
Date: Thu, 17 Nov 2011 17:53:16 -0800
Subject: [llvm-commits] [llvm] r144962 - in /llvm/trunk:
 lib/Transforms/Instrumentation/AddressSanitizer.cpp
 test/Instrumentation/AddressSanitizer/bug_11395.ll
In-Reply-To: <20111118014106.C0C0E2A6C133@llvm.org>
References: <20111118014106.C0C0E2A6C133@llvm.org>
Message-ID: <CAGCO0KhB9g3PbFJu4d_JPYH5c30ootbP=U_y1x9u51Ax49RXtQ@mail.gmail.com>

You probably want to add FIXME comments so that we rip this out once the
bug is fixed... I'm a bit dubious on checking in workarounds like this --
we really need to fix the underlying bug.

On Thu, Nov 17, 2011 at 5:41 PM, Kostya Serebryany <kcc at google.com> wrote:

> Author: kcc
> Date: Thu Nov 17 19:41:06 2011
> New Revision: 144962
>
> URL: http://llvm.org/viewvc/llvm-project?rev=144962&view=rev
> Log:
> [asan] workaround for reg alloc bug 11395: don't instrument functions with
> large chunks of inline assembler
>
> Added:
>    llvm/trunk/test/Instrumentation/AddressSanitizer/bug_11395.ll
> Modified:
>    llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
>
> Modified: llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp?rev=144962&r1=144961&r2=144962&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp
> (original)
> +++ llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp Thu Nov
> 17 19:41:06 2011
> @@ -179,6 +179,7 @@
>
>   void PoisonStack(const ArrayRef<AllocaInst*> &AllocaVec, IRBuilder<> IRB,
>                    Value *ShadowBase, bool DoPoison);
> +  bool LooksLikeCodeInBug11395(Instruction *I);
>
>   Module      *CurrentModule;
>   LLVMContext *C;
> @@ -784,6 +785,17 @@
>   }
>  }
>
> +// Workaround for bug 11395: we don't want to instrument stack in
> functions
> +// with large assembly blobs (32-bit only), otherwise reg alloc may crash.
> +bool AddressSanitizer::LooksLikeCodeInBug11395(Instruction *I) {
> +  if (LongSize != 32) return false;
> +  CallInst *CI = dyn_cast<CallInst>(I);
> +  if (!CI || !CI->isInlineAsm()) return false;
> +  if (CI->getNumArgOperands() <= 5) return false;
> +  // We have inline assembly with quite a few arguments.
> +  return true;
> +}
> +
>  // Find all static Alloca instructions and put
>  // poisoned red zones around all of them.
>  // Then unpoison everything back before the function returns.
> @@ -810,6 +822,7 @@
>     BasicBlock &BB = *FI;
>     for (BasicBlock::iterator BI = BB.begin(), BE = BB.end();
>          BI != BE; ++BI) {
> +      if (LooksLikeCodeInBug11395(BI)) return false;
>       if (isa<ReturnInst>(BI)) {
>           RetVec.push_back(BI);
>           continue;
>
> Added: llvm/trunk/test/Instrumentation/AddressSanitizer/bug_11395.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Instrumentation/AddressSanitizer/bug_11395.ll?rev=144962&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/Instrumentation/AddressSanitizer/bug_11395.ll (added)
> +++ llvm/trunk/test/Instrumentation/AddressSanitizer/bug_11395.ll Thu Nov
> 17 19:41:06 2011
>

This testcase is monstrous and horrible. Can't you reduce it into something
smaller?

Also, something much more readable so that folks in the future understand
what it's trying to test?

In particular, the giant struct types don't seem at all relevant to the
bug, and I suspect you could greatly simplify the contents of the inline
asm. You could also format the inline asm in a readable way. =]

In general, it's better to not check in raw delta-reduced test cases, but
to massage them into a cleaner form.


> @@ -0,0 +1,71 @@
> +; RUN: opt < %s -asan -S | llc -o /dev/null
>

Add a FIXME to start using FileCheck to ensure the instrumentation makes it
into such challenging functions once the bug gets fixed?


> +; The bug manifests as a reg alloc failure:
> +; error: ran out of registers during register allocation
> +; ModuleID = 'z.o'
> +target datalayout =
> "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128"
> +target triple = "i386-unknown-linux-gnu"
> +
> +%struct.DSPContext = type { void (i16*, i8*, i32)*, void (i16*, i8*, i8*,
> i32)*, void (i16*, i8*, i32)*, void (i16*, i8*, i32)*, void (i16*, i8*,
> i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, i32 (i16*)*, void
> (i8*, i8*, i32, i32, i32, i32, i32)*, void (i8*, i8*, i32, i32, i32, i32,
> i32, i32, i32, i32, i32, i32, i32, i32)*, void (i16*)*, void (i16*)*, i32
> (i8*, i32)*, i32 (i8*, i32)*, [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x
> i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x
> i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x
> i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x
> i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x
> i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x
> i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x
> i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x
> i32 (i8*, i8*, i8
>  *, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*,
> i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*,
> i8*, i32, i32)*], i32 (i8*, i16*, i32)*, [4 x [4 x void (i8*, i8*, i32,
> i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*,
> i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [2 x void (i8*, i8*,
> i8*, i32, i32)*], [11 x void (i8*, i8*, i32, i32, i32)*], [11 x void (i8*,
> i8*, i32, i32, i32)*], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void
> (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void
> (i8*, i8*, i32)*]], [8 x void (i8*, i8*, i32)*], [3 x void (i8*, i8*, i32,
> i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void
> (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32,
> i32)*], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*,
> i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*,
> i32)*]], [10 x void (i8*, i32, i32,
>  i32, i32)*], [10 x void (i8*, i8*, i32, i32, i32, i32, i32)*], [2 x [16 x
> void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], void (i8*,
> i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*,
> void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32,
> i32, i32)*, void (i8*, i16*, i32)*, [2 x [4 x i32 (i8*, i8*, i8*, i32,
> i32)*]], void (i8*, i8*, i32)*, void (i8*, i8*, i8*, i32)*, void (i8*, i8*,
> i8*, i32)*, void (i8*, i8*, i8*, i32, i32*, i32*)*, void (i8*, i8*, i8*,
> i32, i32*, i32*)*, i32 (i8*, i8*, i32, i32)*, void (i8*, i8*, i32, i32*,
> i32*, i32*)*, void (i8*, i8*, i8*, i32, i32)*, void (i32*, i32*, i32)*,
> void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void
> (i8*, i32, i32, i32)*, void (i8*, i32, i32, i32)*, void (i8*, i32, i32,
> i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32)*,
> void (i8*, i32, i32, i32)*, void ([4 x [4 x i16]]*, i8*, [40 x i8]*, [40 x
> [2 x i16]]*, i32, i32, i32, i32, i32,
>  i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32)*,
> void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32*)*, void
> (i8*, i32, i32*)*, void (i8*, i8*, i32, i16*, i16*)*, void (float*, float*,
> i32)*, void ([256 x float]*, [2 x float]*, i32, i32, i32)*, void (i32*,
> i32, i32, double*)*, void (float*, float*, i32)*, void (float*, float*,
> float*, i32)*, void (float*, float*, float*, float*, i32)*, void (float*,
> float*, float*, float*, float, i32)*, void (float*, i32*, float, i32)*,
> void (float*, float*, float, float, i32)*, void (float*, float*, float,
> i32)*, [2 x void (float*, float*, float**, float, i32)*], [2 x void
> (float*, float**, float, i32)*], float (float*, float*, i32)*, void
> (float*, float*, i32)*, void (i16*, float*, i32)*, void (i16*, float**,
> i32, i32)*, void (i16*)*, void (i16*)*, void (i16*)*, void (i8*, i32,
> i16*)*, void (i8*, i32, i16*)*, [64 x i8], i32, i32 (i16*, i16*, i16*,
> i32)*, void (i16*, i16*, i32)*, void (i8*, i32, i32, i3
>  2, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*,
> i16*, i32)*, void (i8*, i16*, i32)*, void ([4 x i16]*)*, void (i8*, i32*,
> i16*, i32, i8*)*, void (i8*, i32*, i16*, i32, i8*)*, void (i8**, i32*,
> i16*, i32, i8*)*, void (i8*, i32*, i16*, i32, i8*)*, void (i16*, i16*,
> i16*, i16*, i16*, i16*, i32)*, void (i16*, i32)*, void (i8*, i32, i8**,
> i32, i32, i32, i32, i32, %struct.slice_buffer_s*, i32, i8*)*, void (i8*,
> i32, i32)*, [4 x void (i8*, i32, i8*, i32, i32, i32)*], void (i32*, i32*,
> i32, i32, i32, i32, i32, i32*)*, void (i16*)*, void (i8*, i32, i16*)*, void
> (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void
> (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void
> (i8*, i32)*, void (i8*, i32)*, void (i8*, i32, i32)*, void (i8*, i32,
> i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*,
> void (i8*, i32, i32)*, [16 x void (i8*, i8*, i32, i32)*], [16 x void (i8*,
> i8*, i32, i32)*], [12 x void (i8*, i8*, i32)
>  *], void (i8*, i8*, i32, i32*, i32*, i32)*, void (i16*, i16*, i32)*, void
> (i16*, i16*, i32)*, i32 (i16*, i16*, i32, i32)*, [4 x [16 x void (i8*, i8*,
> i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*,
> i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [3 x void (i8*, i8*, i32, i32,
> i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*] }
> +%struct.slice_buffer_s = type opaque
> +%struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32,
> i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void
> (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32,
> i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32,
> i32, i32, %struct.AVCodec*, i8*, i32, void (%struct.AVCodecContext*, i8*,
> i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8],
> i32, i32, i32, i32, i32, i32, i32, float, i32, i32
> (%struct.AVCodecContext*, %struct.AVFrame*)*, void
> (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*,
> float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float,
> float, float, float, i32, float, float, float, float, float, i32, i32,
> i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32,
> [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32
> (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32,
> i32, i32, i32,
>  i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32,
> i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32,
> i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*,
> i8*)*, i8*, i32*, i32, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32,
> i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32,
> i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32,
> i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i32,
> float, i64, i32, i64, i64, float, float, %struct.AVHWAccel*, i32, i8*, i32,
> i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32
> (%struct.AVCodecContext*, i8*, i32, i32)*, i8*, i32*, i32)*, i32, i32, i32,
> i32, i32, i32, i8*, float, float, float, float, i32, i32, i32, float,
> float, float, i32, i32, i32, i32, [4 x i32], i8*, i32, i32, i32, i32 }
> +%struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* }
> +%struct.AVOption = type opaque
> +%struct.AVRational = type { i32, i32 }
> +%struct.AVFrame = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64,
> i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4
> x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x
> i8*], i64, i8* }
> +%struct.AVPanScan = type { i32, i32, i32, [3 x [2 x i16]] }
> +%struct.AVCodec = type { i8*, i32, i32, i32, i32
> (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*,
> i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*,
> %struct.AVPacket*)*, i32, %struct.AVCodec*, void
> (%struct.AVCodecContext*)*, %struct.AVRational*, i32*, i8*, i32*, i32*,
> i64* }
> +%struct.AVPacket = type { i64, i64, i8*, i32, i32, i32, i32, void
> (%struct.AVPacket*)*, i8*, i64, i64 }
> +%struct.RcOverride = type { i32, i32, i32, float }
> +%struct.AVPaletteControl = type { i32, [256 x i32] }
> +%struct.AVHWAccel = type { i8*, i32, i32, i32, i32, %struct.AVHWAccel*,
> i32 (%struct.AVCodecContext*, i8*, i32)*, i32 (%struct.AVCodecContext*,
> i8*, i32)*, i32 (%struct.AVCodecContext*)*, i32 }
> +
> + at firtable = internal unnamed_addr constant [9 x i8*] [i8*
> @ff_mlp_firorder_0, i8* @ff_mlp_firorder_1, i8* @ff_mlp_firorder_2, i8*
> @ff_mlp_firorder_3, i8* @ff_mlp_firorder_4, i8* @ff_mlp_firorder_5, i8*
> @ff_mlp_firorder_6, i8* @ff_mlp_firorder_7, i8* @ff_mlp_firorder_8], align 4
> + at iirtable = internal unnamed_addr constant [5 x i8*] [i8*
> @ff_mlp_iirorder_0, i8* @ff_mlp_iirorder_1, i8* @ff_mlp_iirorder_2, i8*
> @ff_mlp_iirorder_3, i8* @ff_mlp_iirorder_4], align 4
> + at ff_mlp_iirorder_0 = external global i8
> + at ff_mlp_iirorder_1 = external global i8
> + at ff_mlp_iirorder_2 = external global i8
> + at ff_mlp_iirorder_3 = external global i8
> + at ff_mlp_iirorder_4 = external global i8
> + at ff_mlp_firorder_0 = external global i8
> + at ff_mlp_firorder_1 = external global i8
> + at ff_mlp_firorder_2 = external global i8
> + at ff_mlp_firorder_3 = external global i8
> + at ff_mlp_firorder_4 = external global i8
> + at ff_mlp_firorder_5 = external global i8
> + at ff_mlp_firorder_6 = external global i8
> + at ff_mlp_firorder_7 = external global i8
> + at ff_mlp_firorder_8 = external global i8
> +
> +define void @ff_mlp_init_x86(%struct.DSPContext* nocapture %c,
> %struct.AVCodecContext* nocapture %avctx) nounwind {
> +entry:
> +  %mlp_filter_channel = getelementptr inbounds %struct.DSPContext* %c,
> i32 0, i32 131
> +  store void (i32*, i32*, i32, i32, i32, i32, i32, i32*)*
> @mlp_filter_channel_x86, void (i32*, i32*, i32, i32, i32, i32, i32, i32*)**
> %mlp_filter_channel, align 4, !tbaa !0
> +  ret void
> +}
> +
> +define internal void @mlp_filter_channel_x86(i32* %state, i32* %coeff,
> i32 %firorder, i32 %iirorder, i32 %filter_shift, i32 %mask, i32 %blocksize,
> i32* %sample_buffer) nounwind {
> +entry:
> +  %filter_shift.addr = alloca i32, align 4
> +  %mask.addr = alloca i32, align 4
> +  %blocksize.addr = alloca i32, align 4
> +  %firjump = alloca i8*, align 4
> +  %iirjump = alloca i8*, align 4
> +  store i32 %filter_shift, i32* %filter_shift.addr, align 4, !tbaa !3
> +  store i32 %mask, i32* %mask.addr, align 4, !tbaa !3
> +  %arrayidx = getelementptr inbounds [9 x i8*]* @firtable, i32 0, i32
> %firorder
> +  %0 = load i8** %arrayidx, align 4, !tbaa !0
> +  store i8* %0, i8** %firjump, align 4, !tbaa !0
> +  %arrayidx1 = getelementptr inbounds [5 x i8*]* @iirtable, i32 0, i32
> %iirorder
> +  %1 = load i8** %arrayidx1, align 4, !tbaa !0
> +  store i8* %1, i8** %iirjump, align 4, !tbaa !0
> +  %sub = sub nsw i32 0, %blocksize
> +  store i32 %sub, i32* %blocksize.addr, align 4, !tbaa !3
> +  %2 = call { i32*, i32*, i32* } asm sideeffect "1:
>     \0A\09xor           %esi, %esi\0A\09xor           %ecx, %ecx\0A\09jmp
>  *$5                     \0A\09ff_mlp_firorder_8:            \0A\09mov
> 0x1c+0($0), %eax\0A\09imull 0x1c+0($1)       \0A\09add                %eax
> , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_firorder_7:
>    \0A\09mov   0x18+0($0), %eax\0A\09imull 0x18+0($1)       \0A\09add
>          %eax , %esi\0A\09adc                %edx ,
> %ecx\0A\09ff_mlp_firorder_6:            \0A\09mov   0x14+0($0),
> %eax\0A\09imull 0x14+0($1)       \0A\09add                %eax ,
> %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_firorder_5:
>  \0A\09mov   0x10+0($0), %eax\0A\09imull 0x10+0($1)       \0A\09add
>        %eax , %esi\0A\09adc                %edx ,
> %ecx\0A\09ff_mlp_firorder_4:            \0A\09mov   0x0c+0($0),
> %eax\0A\09imull 0x0c+0($1)       \0A\09add                %eax ,
> %esi\0A\09adc                %e
>  dx , %ecx\0A\09ff_mlp_firorder_3:            \0A\09mov   0x08+0($0),
> %eax\0A\09imull 0x08+0($1)       \0A\09add                %eax ,
> %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_firorder_2:
>  \0A\09mov   0x04+0($0), %eax\0A\09imull 0x04+0($1)       \0A\09add
>        %eax , %esi\0A\09adc                %edx ,
> %ecx\0A\09ff_mlp_firorder_1:            \0A\09mov   0x00+0($0),
> %eax\0A\09imull 0x00+0($1)       \0A\09add                %eax ,
> %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_firorder_0:\0A\09jmp
>  *$6                     \0A\09ff_mlp_iirorder_4:            \0A\09mov
> 0x0c+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x0c+4* 8($1)       \0A\09add
>              %eax , %esi\0A\09adc                %edx ,
> %ecx\0A\09ff_mlp_iirorder_3:            \0A\09mov   0x08+4*(8 + (40 *
> 4))($0), %eax\0A\09imull 0x08+4* 8($1)       \0A\09add                %eax
> , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_iirorder_2:
>    \0A\09mov   0x04+4*(8 +
>  (40 * 4))($0), %eax\0A\09imull 0x04+4* 8($1)       \0A\09add
>    %eax , %esi\0A\09adc                %edx , %ecx\0A\09ff_mlp_iirorder_1:
>            \0A\09mov   0x00+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x00+4*
> 8($1)       \0A\09add                %eax , %esi\0A\09adc
>  %edx , %ecx\0A\09ff_mlp_iirorder_0:\0A\09mov           %ecx, %edx\0A\09mov
>           %esi, %eax\0A\09movzbl        $7   , %ecx\0A\09shrd    %cl, %edx,
> %eax\0A\09mov  %eax  ,%edx      \0A\09add  ($2)      ,%eax     \0A\09and
> $4       ,%eax     \0A\09sub   $$4       ,  $0         \0A\09mov  %eax,
> ($0)        \0A\09mov  %eax, ($2)        \0A\09add $$4* 8    ,  $2
> \0A\09sub  %edx   ,%eax     \0A\09mov  %eax,4*(8 + (40 * 4))($0)
>  \0A\09incl              $3         \0A\09js 1b
>  \0A\09",
> "=r,=r,=r,=*m,*m,*m,*m,*m,0,1,2,*m,~{eax},~{edx},~{esi},~{ecx},~{dirflag},~{fpsr},~{flags}"(i32*
> %blocksize.addr, i32* %mask.addr, i8** %firjump, i8** %iirjump, i32*
> %filter_sh
>  ift.addr, i32* %state, i32* %coeff, i32* %sample_buffer, i32*
> %blocksize.addr) nounwind, !srcloc !4
> +  ret void
> +}
> +
> +!0 = metadata !{metadata !"any pointer", metadata !1}
> +!1 = metadata !{metadata !"omnipotent char", metadata !2}
> +!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
> +!3 = metadata !{metadata !"int", metadata !1}
> +!4 = metadata !{i32 156132, i32 156164, i32 156205, i32 156238, i32
> 156282, i32 156332, i32 156370, i32 156408, i32 156447, i32 156486, i32
> 156536, i32 156574, i32 156612, i32 156651, i32 156690, i32 156740, i32
> 156778, i32 156816, i32 156855, i32 156894, i32 156944, i32 156982, i32
> 157020, i32 157059, i32 157098, i32 157148, i32 157186, i32 157224, i32
> 157263, i32 157302, i32 157352, i32 157390, i32 157428, i32 157467, i32
> 157506, i32 157556, i32 157594, i32 157632, i32 157671, i32 157710, i32
> 157760, i32 157798, i32 157836, i32 157875, i32 157914, i32 157952, i32
> 157996, i32 158046, i32 158099, i32 158140, i32 158179, i32 158218, i32
> 158268, i32 158321, i32 158362, i32 158401, i32 158440, i32 158490, i32
> 158543, i32 158584, i32 158623, i32 158662, i32 158712, i32 158765, i32
> 158806, i32 158845, i32 158884, i32 158922, i32 158963, i32 158996, i32
> 159029, i32 159062, i32 159109, i32 159154, i32 159199, i32 159243, i32
> 159286, i32 159329, i32 159375, i32 159422, i32 159478, i
>  32 159522, i32 159566}
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From nadav.rotem at intel.com  Thu Nov 17 20:49:55 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Fri, 18 Nov 2011 02:49:55 -0000
Subject: [llvm-commits] [llvm] r144967 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td
 test/CodeGen/X86/avx2-vbroadcast.ll
Message-ID: <20111118024955.B2B562A6C133@llvm.org>

Author: nadav
Date: Thu Nov 17 20:49:55 2011
New Revision: 144967

URL: http://llvm.org/viewvc/llvm-project?rev=144967&view=rev
Log:
Add AVX2 vpbroadcast support

Added:
    llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144967&r1=144966&r2=144967&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Nov 17 20:49:55 2011
@@ -5115,9 +5115,9 @@
 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
 /// a scalar load.
-/// The scalar load node is returned when a pattern is found, 
-/// or SDValue() otherwise. 
-static SDValue isVectorBroadcast(SDValue &Op) {
+/// The scalar load node is returned when a pattern is found,
+/// or SDValue() otherwise.
+static SDValue isVectorBroadcast(SDValue &Op, bool hasAVX2) {
   EVT VT = Op.getValueType();
   SDValue V = Op;
 
@@ -5134,16 +5134,16 @@
 
     case ISD::BUILD_VECTOR: {
       // The BUILD_VECTOR node must be a splat.
-      if (!isSplatVector(V.getNode())) 
+      if (!isSplatVector(V.getNode()))
         return SDValue();
 
       Ld = V.getOperand(0);
-    
-      // The suspected load node has several users. Make sure that all 
+
+      // The suspected load node has several users. Make sure that all
       // of its users are from the BUILD_VECTOR node.
-      if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 
+      if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
         return SDValue();
-      break; 
+      break;
     }
 
     case ISD::VECTOR_SHUFFLE: {
@@ -5151,11 +5151,11 @@
 
       // Shuffles must have a splat mask where the first element is
       // broadcasted.
-      if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 
+      if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
         return SDValue();
 
       SDValue Sc = Op.getOperand(0);
-      if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 
+      if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
         return SDValue();
 
       Ld = Sc.getOperand(0);
@@ -5167,15 +5167,27 @@
       break;
     }
   }
-  
+
   // The scalar source must be a normal load.
-  if (!ISD::isNormalLoad(Ld.getNode())) 
+  if (!ISD::isNormalLoad(Ld.getNode()))
     return SDValue();
-  
+
   bool Is256 = VT.getSizeInBits() == 256;
   bool Is128 = VT.getSizeInBits() == 128;
   unsigned ScalarSize = Ld.getValueType().getSizeInBits();
 
+  if (hasAVX2) {
+    // VBroadcast to YMM
+    if (Is256 && (ScalarSize == 8  || ScalarSize == 16 ||
+                  ScalarSize == 32 || ScalarSize == 64 ))
+      return Ld;
+
+    // VBroadcast to XMM
+    if (Is128 && (ScalarSize ==  8 || ScalarSize == 32 ||
+                  ScalarSize == 16 || ScalarSize == 64 ))
+      return Ld;
+  }
+
   // VBroadcast to YMM
   if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
     return Ld;
@@ -5184,6 +5196,7 @@
   if (Is128 && (ScalarSize == 32))
     return Ld;
 
+
   // Unsupported broadcast.
   return SDValue();
 }
@@ -5216,7 +5229,7 @@
     return getOnesVector(Op.getValueType(), DAG, dl);
   }
 
-  SDValue LD = isVectorBroadcast(Op);
+  SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
   if (Subtarget->hasAVX() && LD.getNode())
       return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
 
@@ -6613,7 +6626,7 @@
       return Op;
 
     // Use vbroadcast whenever the splat comes from a foldable load
-    SDValue LD = isVectorBroadcast(Op);
+    SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
     if (Subtarget->hasAVX() && LD.getNode())
       return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
 

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144967&r1=144966&r2=144967&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Nov 17 20:49:55 2011
@@ -7189,19 +7189,6 @@
 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
           (VBROADCASTF128 addr:$src)>;
 
-def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
-          (VBROADCASTSSYrm addr:$src)>;
-def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
-          (VBROADCASTSDrm addr:$src)>;
-def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
-          (VBROADCASTSSYrm addr:$src)>;
-def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
-          (VBROADCASTSDrm addr:$src)>;
-
-def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
-          (VBROADCASTSSrm addr:$src)>;
-def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
-          (VBROADCASTSSrm addr:$src)>;
 
 //===----------------------------------------------------------------------===//
 // VINSERTF128 - Insert packed floating-point values
@@ -7557,6 +7544,40 @@
                                     int_x86_avx2_pbroadcastq_128,
                                     int_x86_avx2_pbroadcastq_256>;
 
+let Predicates = [HasAVX2] in {
+  def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
+          (VPBROADCASTBrm addr:$src)>;
+  def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
+          (VPBROADCASTBYrm addr:$src)>;
+  def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
+          (VPBROADCASTWrm addr:$src)>;
+  def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
+          (VPBROADCASTWYrm addr:$src)>;
+  def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
+          (VPBROADCASTDrm addr:$src)>;
+  def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
+          (VPBROADCASTDYrm addr:$src)>;
+  def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
+          (VPBROADCASTQrm addr:$src)>;
+  def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
+          (VPBROADCASTQYrm addr:$src)>;
+}
+
+// AVX1 broadcast patterns
+def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
+          (VBROADCASTSSYrm addr:$src)>;
+def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
+          (VBROADCASTSDrm addr:$src)>;
+def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
+          (VBROADCASTSSYrm addr:$src)>;
+def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
+          (VBROADCASTSDrm addr:$src)>;
+
+def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
+          (VBROADCASTSSrm addr:$src)>;
+def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
+          (VBROADCASTSSrm addr:$src)>;
+
 //===----------------------------------------------------------------------===//
 // VPERM - Permute instructions
 //

Added: llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll?rev=144967&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll (added)
+++ llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll Thu Nov 17 20:49:55 2011
@@ -0,0 +1,142 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
+
+; CHECK: vpbroadcastb (%
+define <16 x i8> @BB16(i8* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i8* %ptr, align 4
+  %q0 = insertelement <16 x i8> undef, i8 %q, i32 0
+  %q1 = insertelement <16 x i8> %q0, i8 %q, i32 1
+  %q2 = insertelement <16 x i8> %q1, i8 %q, i32 2
+  %q3 = insertelement <16 x i8> %q2, i8 %q, i32 3
+  %q4 = insertelement <16 x i8> %q3, i8 %q, i32 4
+  %q5 = insertelement <16 x i8> %q4, i8 %q, i32 5
+  %q6 = insertelement <16 x i8> %q5, i8 %q, i32 6
+  %q7 = insertelement <16 x i8> %q6, i8 %q, i32 7
+  %q8 = insertelement <16 x i8> %q7, i8 %q, i32 8
+  %q9 = insertelement <16 x i8> %q8, i8 %q, i32 9
+  %qa = insertelement <16 x i8> %q9, i8 %q, i32 10
+  %qb = insertelement <16 x i8> %qa, i8 %q, i32 11
+  %qc = insertelement <16 x i8> %qb, i8 %q, i32 12
+  %qd = insertelement <16 x i8> %qc, i8 %q, i32 13
+  %qe = insertelement <16 x i8> %qd, i8 %q, i32 14
+  %qf = insertelement <16 x i8> %qe, i8 %q, i32 15
+  ret <16 x i8> %qf
+}
+; CHECK: vpbroadcastb (%
+define <32 x i8> @BB32(i8* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i8* %ptr, align 4
+  %q0 = insertelement <32 x i8> undef, i8 %q, i32 0
+  %q1 = insertelement <32 x i8> %q0, i8 %q, i32 1
+  %q2 = insertelement <32 x i8> %q1, i8 %q, i32 2
+  %q3 = insertelement <32 x i8> %q2, i8 %q, i32 3
+  %q4 = insertelement <32 x i8> %q3, i8 %q, i32 4
+  %q5 = insertelement <32 x i8> %q4, i8 %q, i32 5
+  %q6 = insertelement <32 x i8> %q5, i8 %q, i32 6
+  %q7 = insertelement <32 x i8> %q6, i8 %q, i32 7
+  %q8 = insertelement <32 x i8> %q7, i8 %q, i32 8
+  %q9 = insertelement <32 x i8> %q8, i8 %q, i32 9
+  %qa = insertelement <32 x i8> %q9, i8 %q, i32 10
+  %qb = insertelement <32 x i8> %qa, i8 %q, i32 11
+  %qc = insertelement <32 x i8> %qb, i8 %q, i32 12
+  %qd = insertelement <32 x i8> %qc, i8 %q, i32 13
+  %qe = insertelement <32 x i8> %qd, i8 %q, i32 14
+  %qf = insertelement <32 x i8> %qe, i8 %q, i32 15
+
+  %q20 = insertelement <32 x i8> %qf, i8 %q,  i32 16
+  %q21 = insertelement <32 x i8> %q20, i8 %q, i32 17
+  %q22 = insertelement <32 x i8> %q21, i8 %q, i32 18
+  %q23 = insertelement <32 x i8> %q22, i8 %q, i32 19
+  %q24 = insertelement <32 x i8> %q23, i8 %q, i32 20
+  %q25 = insertelement <32 x i8> %q24, i8 %q, i32 21
+  %q26 = insertelement <32 x i8> %q25, i8 %q, i32 22
+  %q27 = insertelement <32 x i8> %q26, i8 %q, i32 23
+  %q28 = insertelement <32 x i8> %q27, i8 %q, i32 24
+  %q29 = insertelement <32 x i8> %q28, i8 %q, i32 25
+  %q2a = insertelement <32 x i8> %q29, i8 %q, i32 26
+  %q2b = insertelement <32 x i8> %q2a, i8 %q, i32 27
+  %q2c = insertelement <32 x i8> %q2b, i8 %q, i32 28
+  %q2d = insertelement <32 x i8> %q2c, i8 %q, i32 29
+  %q2e = insertelement <32 x i8> %q2d, i8 %q, i32 30
+  %q2f = insertelement <32 x i8> %q2e, i8 %q, i32 31
+  ret <32 x i8> %q2f
+}
+; CHECK: vpbroadcastw (%
+
+define <8 x i16> @W16(i16* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i16* %ptr, align 4
+  %q0 = insertelement <8 x i16> undef, i16 %q, i32 0
+  %q1 = insertelement <8 x i16> %q0, i16 %q, i32 1
+  %q2 = insertelement <8 x i16> %q1, i16 %q, i32 2
+  %q3 = insertelement <8 x i16> %q2, i16 %q, i32 3
+  %q4 = insertelement <8 x i16> %q3, i16 %q, i32 4
+  %q5 = insertelement <8 x i16> %q4, i16 %q, i32 5
+  %q6 = insertelement <8 x i16> %q5, i16 %q, i32 6
+  %q7 = insertelement <8 x i16> %q6, i16 %q, i32 7
+  ret <8 x i16> %q7
+}
+; CHECK: vpbroadcastw (%
+define <16 x i16> @WW16(i16* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i16* %ptr, align 4
+  %q0 = insertelement <16 x i16> undef, i16 %q, i32 0
+  %q1 = insertelement <16 x i16> %q0, i16 %q, i32 1
+  %q2 = insertelement <16 x i16> %q1, i16 %q, i32 2
+  %q3 = insertelement <16 x i16> %q2, i16 %q, i32 3
+  %q4 = insertelement <16 x i16> %q3, i16 %q, i32 4
+  %q5 = insertelement <16 x i16> %q4, i16 %q, i32 5
+  %q6 = insertelement <16 x i16> %q5, i16 %q, i32 6
+  %q7 = insertelement <16 x i16> %q6, i16 %q, i32 7
+  %q8 = insertelement <16 x i16> %q7, i16 %q, i32 8
+  %q9 = insertelement <16 x i16> %q8, i16 %q, i32 9
+  %qa = insertelement <16 x i16> %q9, i16 %q, i32 10
+  %qb = insertelement <16 x i16> %qa, i16 %q, i32 11
+  %qc = insertelement <16 x i16> %qb, i16 %q, i32 12
+  %qd = insertelement <16 x i16> %qc, i16 %q, i32 13
+  %qe = insertelement <16 x i16> %qd, i16 %q, i32 14
+  %qf = insertelement <16 x i16> %qe, i16 %q, i32 15
+  ret <16 x i16> %qf
+}
+; CHECK: vpbroadcastd (%
+define <4 x i32> @D32(i32* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i32* %ptr, align 4
+  %q0 = insertelement <4 x i32> undef, i32 %q, i32 0
+  %q1 = insertelement <4 x i32> %q0, i32 %q, i32 1
+  %q2 = insertelement <4 x i32> %q1, i32 %q, i32 2
+  %q3 = insertelement <4 x i32> %q2, i32 %q, i32 3
+  ret <4 x i32> %q3
+}
+; CHECK: vpbroadcastd (%
+define <8 x i32> @DD32(i32* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i32* %ptr, align 4
+  %q0 = insertelement <8 x i32> undef, i32 %q, i32 0
+  %q1 = insertelement <8 x i32> %q0, i32 %q, i32 1
+  %q2 = insertelement <8 x i32> %q1, i32 %q, i32 2
+  %q3 = insertelement <8 x i32> %q2, i32 %q, i32 3
+  %q4 = insertelement <8 x i32> %q3, i32 %q, i32 4
+  %q5 = insertelement <8 x i32> %q4, i32 %q, i32 5
+  %q6 = insertelement <8 x i32> %q5, i32 %q, i32 6
+  %q7 = insertelement <8 x i32> %q6, i32 %q, i32 7
+  ret <8 x i32> %q7
+}
+; CHECK: vpbroadcastq (%
+define <2 x i64> @Q64(i64* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i64* %ptr, align 4
+  %q0 = insertelement <2 x i64> undef, i64 %q, i32 0
+  %q1 = insertelement <2 x i64> %q0, i64 %q, i32 1
+  ret <2 x i64> %q1
+}
+; CHECK: vpbroadcastq (%
+define <4 x i64> @QQ64(i64* %ptr) nounwind uwtable readnone ssp {
+entry:
+  %q = load i64* %ptr, align 4
+  %q0 = insertelement <4 x i64> undef, i64 %q, i32 0
+  %q1 = insertelement <4 x i64> %q0, i64 %q, i32 1
+  %q2 = insertelement <4 x i64> %q1, i64 %q, i32 2
+  %q3 = insertelement <4 x i64> %q2, i64 %q, i32 3
+  ret <4 x i64> %q3
+}



From atrick at apple.com  Thu Nov 17 21:42:41 2011
From: atrick at apple.com (Andrew Trick)
Date: Fri, 18 Nov 2011 03:42:41 -0000
Subject: [llvm-commits] [llvm] r144970 - in /llvm/trunk:
 lib/Analysis/LoopInfo.cpp test/Transforms/LoopUnroll/unloop.ll
Message-ID: <20111118034241.D289E2A6C133@llvm.org>

Author: atrick
Date: Thu Nov 17 21:42:41 2011
New Revision: 144970

URL: http://llvm.org/viewvc/llvm-project?rev=144970&view=rev
Log:
Fix a corner case in updating LoopInfo after fully unrolling an outer loop.

The loop tree's inclusive block lists are painful and expensive to
update. (I have no idea why they're inclusive). The design was
supposed to handle this case but the implementation missed it and my
unit tests weren't thorough enough.

Fixes PR11335: loop unroll update.

Modified:
    llvm/trunk/lib/Analysis/LoopInfo.cpp
    llvm/trunk/test/Transforms/LoopUnroll/unloop.ll

Modified: llvm/trunk/lib/Analysis/LoopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopInfo.cpp?rev=144970&r1=144969&r2=144970&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/LoopInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/LoopInfo.cpp Thu Nov 17 21:42:41 2011
@@ -477,21 +477,19 @@
 /// removeBlocksFromAncestors - Remove unloop's blocks from all ancestors below
 /// their new parents.
 void UnloopUpdater::removeBlocksFromAncestors() {
-  // Remove unloop's blocks from all ancestors below their new parents.
+  // Remove all unloop's blocks (including those in nested subloops) from
+  // ancestors below the new parent loop.
   for (Loop::block_iterator BI = Unloop->block_begin(),
          BE = Unloop->block_end(); BI != BE; ++BI) {
-    Loop *NewParent = LI->getLoopFor(*BI);
-    // If this block is an immediate subloop, remove all blocks (including
-    // nested subloops) from ancestors below the new parent loop.
-    // Otherwise, if this block is in a nested subloop, skip it.
-    if (SubloopParents.count(NewParent))
-      NewParent = SubloopParents[NewParent];
-    else if (Unloop->contains(NewParent))
-      continue;
-
+    Loop *OuterParent = LI->getLoopFor(*BI);
+    if (Unloop->contains(OuterParent)) {
+      while (OuterParent->getParentLoop() != Unloop)
+        OuterParent = OuterParent->getParentLoop();
+      OuterParent = SubloopParents[OuterParent];
+    }
     // Remove blocks from former Ancestors except Unloop itself which will be
     // deleted.
-    for (Loop *OldParent = Unloop->getParentLoop(); OldParent != NewParent;
+    for (Loop *OldParent = Unloop->getParentLoop(); OldParent != OuterParent;
          OldParent = OldParent->getParentLoop()) {
       assert(OldParent && "new loop is not an ancestor of the original");
       OldParent->removeBlockFromLoop(*BI);

Modified: llvm/trunk/test/Transforms/LoopUnroll/unloop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnroll/unloop.ll?rev=144970&r1=144969&r2=144970&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/LoopUnroll/unloop.ll (original)
+++ llvm/trunk/test/Transforms/LoopUnroll/unloop.ll Thu Nov 17 21:42:41 2011
@@ -427,3 +427,44 @@
 return:                                           ; preds = %sw.bb304
   ret void
 }
+
+; PR11335: the most deeply nested block should be removed from the outer loop.
+; CHECK: @removeSubloopBlocks2
+; CHECK: for.cond3:
+; CHECK-NOT: br
+; CHECK: ret void
+define void @removeSubloopBlocks2() nounwind {
+entry:
+  %tobool.i = icmp ne i32 undef, 0
+  br label %lbl_616
+
+lbl_616.loopexit:                                 ; preds = %for.cond
+  br label %lbl_616
+
+lbl_616:                                          ; preds = %lbl_616.loopexit, %entry
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.cond3, %lbl_616
+  br i1 false, label %for.cond1.preheader, label %lbl_616.loopexit
+
+for.cond1.preheader:                              ; preds = %for.cond
+  br label %for.cond1
+
+for.cond1.loopexit:                               ; preds = %for.cond.i
+  br label %for.cond1
+
+for.cond1:                                        ; preds = %for.cond1.loopexit, %for.cond1.preheader
+  br i1 false, label %for.body2, label %for.cond3
+
+for.body2:                                        ; preds = %for.cond1
+  br label %for.cond.i
+
+for.cond.i:                                       ; preds = %for.cond.i, %for.body2
+  br i1 %tobool.i, label %for.cond.i, label %for.cond1.loopexit
+
+for.cond3:                                        ; preds = %for.cond1
+  br i1 false, label %for.cond, label %if.end
+
+if.end:                                           ; preds = %for.cond3
+  ret void
+}



From hfinkel at anl.gov  Thu Nov 17 21:59:18 2011
From: hfinkel at anl.gov (Hal Finkel)
Date: Thu, 17 Nov 2011 21:59:18 -0600
Subject: [llvm-commits] [LLVMdev] [PATCH] BasicBlock Autovectorization
 Pass
In-Reply-To: <CA+Ov9+=CZEpKMu0ZbmzjLfqi0emGbDd3UYE5bQvN2VfwXD9_6g@mail.gmail.com>
References: <fc2548c6-7c0c-4dc9-b7ac-3c4cdd628d1a@com>
	<1319909412.23036.851.camel@sapling>
	<1319914924.23036.852.camel@sapling>
	<1319919418.23036.881.camel@sapling>
	<1319928991.23036.957.camel@sapling>
	<1320108633.23036.1266.camel@sapling>
	<1320172356.23036.1298.camel@sapling>
	<4EB0462C.5010209@grosser.es> <1320184739.23036.1334.camel@sapling>
	<1320191694.23036.1497.camel@sapling>
	<1320749109.19359.76.camel@sapling>
	<4EB90E98.4010805@grosser.es> <1320762963.19359.117.camel@sapling>
	<4EB98207.2070807@grosser.es> <1320791390.19359.262.camel@sapling>
	<4EBC4B0F.6010609@grosser.es> <1321050998.19359.539.camel@sapling>
	<4EBDA7F9.9080709@grosser.es> <1321053083.19359.550.camel@sapling>
	<4EBDB1BF.7090006@grosser.es> <1321400339.19359.782.camel@sapling>
	<1321486739.19359.1067.camel@sapling>
	<CA+Ov9+=CZEpKMu0ZbmzjLfqi0emGbDd3UYE5bQvN2VfwXD9_6g@mail.gmail.com>
Message-ID: <1321588758.19359.1464.camel@sapling>

On Thu, 2011-11-17 at 04:08 +0400, Anton Korobeynikov wrote:
> Hello Hal,
> 
> > MultiSource/Applications/ClamAV - fails to compile shared_sha256.c with
> > an error: error in backend: Cannot select: 0x4fbcb40: v2i64 =
> > X86ISD::MOVLPD 0x4149e00, 0x418d930 [ID=596]
> Please report this as a PR regardless of the pass. Bugs in the backend
> should be fixed.
> 

For the curious, the two problems that I had mentioned specifically are:
PR 11397
PR 11398

 -Hal

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory


From tlinth at codeaurora.org  Thu Nov 17 23:00:29 2011
From: tlinth at codeaurora.org (Tony Linthicum)
Date: Thu, 17 Nov 2011 23:00:29 -0600
Subject: [llvm-commits] Patch: new backend for Hexagon processor
In-Reply-To: <CAJdarcEQwn6oKgp-ZMtg03uR6YpJp=jBUUmAFaTwKTO0dw7p7Q@mail.gmail.com>
References: <4EC17287.3090708@codeaurora.org>
	<CAJdarcFKL91HwSttsQTcd8FkSaoT7Tz8Jxw1JBmESLo=kjOrpQ@mail.gmail.com>
	<4EC2F380.7010509@codeaurora.org>
	<CAJdarcEQwn6oKgp-ZMtg03uR6YpJp=jBUUmAFaTwKTO0dw7p7Q@mail.gmail.com>
Message-ID: <4EC5E66D.8080303@codeaurora.org>

On 11/16/2011 6:48 PM, Eli Friedman wrote:
> On Tue, Nov 15, 2011 at 3:19 PM, Tony Linthicum<tlinth at codeaurora.org>  wrote:
>> On 11/14/2011 2:54 PM, Eli Friedman wrote:
>>
>>>
>>> --- a/include/llvm/InitializePasses.h
>>> +++ b/include/llvm/InitializePasses.h
>>> @@ -233,6 +233,7 @@ void initializeVerifierPass(PassRegistry&);
>>>   void initializeVirtRegMapPass(PassRegistry&);
>>>   void initializeInstSimplifierPass(PassRegistry&);
>>>
>>> +void initializeHexagonHardwareLoopsPass(PassRegistry&);
>>>   }
>>>
>>>   #endif
>>>
>>> This change shouldn't be necessary; only target-independent passes
>>> need to be listed here, IIRC.
>>>
>>
>> We are in the process of fixing this and will update with a new patch in a
>> day or two.
>>

Done.


>
> It would be nice to see some more documentation in
> docs/CodeGenerator.html for Hexagon-specific target information; it
> looks like there are some interesting target-specific passes, and
> other information might be useful.
>

Not a problem.  We will add some documentation.

> I don't see any issues with the rest of the patch; I haven't looked at
> the lib/Target/Hexagon/* bits in much detail, though.
>

Thanks.

Tony


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
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From gkistanova at gmail.com  Fri Nov 18 13:49:26 2011
From: gkistanova at gmail.com (Galina Kistanova)
Date: Fri, 18 Nov 2011 19:49:26 -0000
Subject: [llvm-commits] [zorg] r144978 -
	/zorg/trunk/buildbot/osuosl/master/config/builders.py
Message-ID: <20111118194926.463132A6C133@llvm.org>

Author: gkistanova
Date: Fri Nov 18 13:49:26 2011
New Revision: 144978

URL: http://llvm.org/viewvc/llvm-project?rev=144978&view=rev
Log:
Change configure for builder clang-native-arm-cortex-a9.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=144978&r1=144977&r2=144978&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Nov 18 13:49:26 2011
@@ -200,14 +200,14 @@
          'slavenames':["kistanova6"],
          'builddir':"clang-native-arm-cortex-a9",
          'factory' : ClangBuilder.getClangBuildFactory(
+                     stage1_config='Release+Asserts',
                      extra_configure_args=['--build=armv7l-unknown-linux-gnueabi',
                                            '--host=armv7l-unknown-linux-gnueabi',
                                            '--target=armv7l-unknown-linux-gnueabi',
                                            '--with-cpu=cortex-a9',
                                            '--with-fpu=neon', '--with-abi=aapcs',
                                            '--with-float=hard',
-                                           '--enable-targets=arm,cbe',
-                                           '--enable-optimized'])},
+                                           '--enable-targets=arm,cbe'])},
 
         {'name': "clang-X86_64-freebsd",
          'slavenames':["kistanova7"],



From baldrick at free.fr  Fri Nov 18 16:11:26 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 18 Nov 2011 22:11:26 -0000
Subject: [llvm-commits] [dragonegg] r144979 -
	/dragonegg/trunk/src/Backend.cpp
Message-ID: <20111118221126.134F02A6C133@llvm.org>

Author: baldrick
Date: Fri Nov 18 16:11:25 2011
New Revision: 144979

URL: http://llvm.org/viewvc/llvm-project?rev=144979&view=rev
Log:
Port commit 144790 (evancheng) from llvm-gcc, fixing the dragonegg
buildbots.  Original commit message:
Match LLVM API change.

Modified:
    dragonegg/trunk/src/Backend.cpp

Modified: dragonegg/trunk/src/Backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=144979&r1=144978&r2=144979&view=diff
==============================================================================
--- dragonegg/trunk/src/Backend.cpp (original)
+++ dragonegg/trunk/src/Backend.cpp Fri Nov 18 16:11:25 2011
@@ -434,7 +434,7 @@
 #endif
 
   TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr,
-                                       RelocModel, CMModel);
+                                       RelocModel, CMModel, CodeGenOptLevel());
   assert(TheTarget->getTargetData()->isBigEndian() == BYTES_BIG_ENDIAN);
   TheTarget->setMCUseCFI(flag_dwarf2_cfi_asm);
   // Binutils does not yet support the use of file directives with an explicit
@@ -610,7 +610,7 @@
     InitializeOutputStreams(false);
     if (TheTarget->addPassesToEmitFile(*PM, FormattedOutStream,
                                        TargetMachine::CGFT_AssemblyFile,
-                                       CodeGenOptLevel(), DisableVerify))
+                                       DisableVerify))
       DieAbjectly("Error interfacing to target machine!");
   }
 
@@ -693,7 +693,7 @@
       InitializeOutputStreams(false);
       if (TheTarget->addPassesToEmitFile(*PM, FormattedOutStream,
                                          TargetMachine::CGFT_AssemblyFile,
-                                         CodeGenOptLevel(), DisableVerify))
+                                         DisableVerify))
         DieAbjectly("Error interfacing to target machine!");
     }
   }



From craig.topper at gmail.com  Fri Nov 18 22:49:22 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sat, 19 Nov 2011 04:49:22 -0000
Subject: [llvm-commits] [llvm] r144985 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20111119044922.4E6002A6C133@llvm.org>

Author: ctopper
Date: Fri Nov 18 22:49:22 2011
New Revision: 144985

URL: http://llvm.org/viewvc/llvm-project?rev=144985&view=rev
Log:
Remove unused parameters from the AVX maskmov classes.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144985&r1=144984&r2=144985&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Nov 18 22:49:22 2011
@@ -7289,8 +7289,7 @@
 //
 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
                           Intrinsic IntLd, Intrinsic IntLd256,
-                          Intrinsic IntSt, Intrinsic IntSt256,
-                          PatFrag pf128, PatFrag pf256> {
+                          Intrinsic IntSt, Intrinsic IntSt256> {
   def rm  : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
              (ins VR128:$src1, f128mem:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
@@ -7316,15 +7315,13 @@
                                  int_x86_avx_maskload_ps,
                                  int_x86_avx_maskload_ps_256,
                                  int_x86_avx_maskstore_ps,
-                                 int_x86_avx_maskstore_ps_256,
-                                 memopv4f32, memopv8f32>;
+                                 int_x86_avx_maskstore_ps_256>;
 let ExeDomain = SSEPackedDouble in
 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
                                  int_x86_avx_maskload_pd,
                                  int_x86_avx_maskload_pd_256,
                                  int_x86_avx_maskstore_pd,
-                                 int_x86_avx_maskstore_pd_256,
-                                 memopv2f64, memopv4f64>;
+                                 int_x86_avx_maskstore_pd_256>;
 
 //===----------------------------------------------------------------------===//
 // VPERMIL - Permute Single and Double Floating-Point Values
@@ -7674,8 +7671,7 @@
 //
 multiclass avx2_pmovmask<string OpcodeStr,
                          Intrinsic IntLd128, Intrinsic IntLd256,
-                         Intrinsic IntSt128, Intrinsic IntSt256,
-                         PatFrag pf128, PatFrag pf256> {
+                         Intrinsic IntSt128, Intrinsic IntSt256> {
   def rm  : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
              (ins VR128:$src1, i128mem:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
@@ -7698,14 +7694,12 @@
                                 int_x86_avx2_maskload_d,
                                 int_x86_avx2_maskload_d_256,
                                 int_x86_avx2_maskstore_d,
-                                int_x86_avx2_maskstore_d_256,
-                                memopv4i32, memopv8i32>;
+                                int_x86_avx2_maskstore_d_256>;
 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
                                 int_x86_avx2_maskload_q,
                                 int_x86_avx2_maskload_q_256,
                                 int_x86_avx2_maskstore_q,
-                                int_x86_avx2_maskstore_q_256,
-                                memopv2i64, memopv4i64>, VEX_W;
+                                int_x86_avx2_maskstore_q_256>, VEX_W;
 
 
 //===----------------------------------------------------------------------===//



From craig.topper at gmail.com  Fri Nov 18 23:48:20 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sat, 19 Nov 2011 05:48:20 -0000
Subject: [llvm-commits] [llvm] r144986 -
	/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
Message-ID: <20111119054820.6B4842A6C133@llvm.org>

Author: ctopper
Date: Fri Nov 18 23:48:20 2011
New Revision: 144986

URL: http://llvm.org/viewvc/llvm-project?rev=144986&view=rev
Log:
Remove some unnecessary filtering checks from X86 disassembler table build.

Modified:
    llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp

Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=144986&r1=144985&r2=144986&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Fri Nov 18 23:48:20 2011
@@ -392,18 +392,11 @@
     
   // Filter out artificial instructions
     
-  if (Name.find("TAILJMP") != Name.npos    ||
-      Name.find("_Int") != Name.npos       ||
-      Name.find("_int") != Name.npos       ||
+  if (Name.find("_Int") != Name.npos       ||
       Name.find("Int_") != Name.npos       ||
       Name.find("_NOREX") != Name.npos     ||
-      Name.find("_TC") != Name.npos        ||
-      Name.find("EH_RETURN") != Name.npos  ||
-      Name.find("V_SET") != Name.npos      ||
-      Name.find("LOCK_") != Name.npos      ||
-      Name.find("WIN") != Name.npos        ||
-      Name.find("_AVX") != Name.npos       ||
-      Name.find("2SDL") != Name.npos)
+      Name.find("2SDL") != Name.npos       ||
+      Name == "LOCK_PREFIX")
     return FILTER_STRONG;
 
   // Filter out instructions with segment override prefixes.
@@ -440,12 +433,6 @@
       Name.find("Xrr") != Name.npos ||
       Name.find("rr64") != Name.npos)
     return FILTER_WEAK;
-    
-  if (Name == "VMASKMOVDQU64"  ||
-      Name == "VEXTRACTPSrr64" ||
-      Name == "VMOVQd64rr"     ||
-      Name == "VMOVQs64rr")
-    return FILTER_WEAK;
 
   // Special cases.
 
@@ -460,29 +447,15 @@
     return FILTER_WEAK;
   if (Name.find("Fs") != Name.npos)
     return FILTER_WEAK;
-  if (Name == "MOVLPDrr"          ||
-      Name == "MOVLPSrr"          ||
-      Name == "PUSHFQ"            ||
-      Name == "BSF16rr"           ||
-      Name == "BSF16rm"           ||
-      Name == "BSR16rr"           ||
-      Name == "BSR16rm"           ||
-      Name == "MOVSX16rm8"        ||
-      Name == "MOVSX16rr8"        ||
-      Name == "MOVZX16rm8"        ||
-      Name == "MOVZX16rr8"        ||
-      Name == "PUSH32i16"         ||
-      Name == "PUSH64i16"         ||
+  if (Name == "PUSH64i16"         ||
       Name == "MOVPQI2QImr"       ||
       Name == "VMOVPQI2QImr"      ||
-      Name == "MOVSDmr"           ||
-      Name == "MOVSDrm"           ||
-      Name == "MOVSSmr"           ||
-      Name == "MOVSSrm"           ||
       Name == "MMX_MOVD64rrv164"  ||
-      Name == "CRC32m16"          ||
       Name == "MOV64ri64i32"      ||
-      Name == "CRC32r16")
+      Name == "VMASKMOVDQU64"     ||
+      Name == "VEXTRACTPSrr64"    ||
+      Name == "VMOVQd64rr"        ||
+      Name == "VMOVQs64rr")
     return FILTER_WEAK;
 
   if (HasFROperands && Name.find("MOV") != Name.npos &&



From craig.topper at gmail.com  Sat Nov 19 01:07:26 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sat, 19 Nov 2011 07:07:26 -0000
Subject: [llvm-commits] [llvm] r144987 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFragmentsSIMD.td
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx2-logic.ll
Message-ID: <20111119070726.ED24B2A6C133@llvm.org>

Author: ctopper
Date: Sat Nov 19 01:07:26 2011
New Revision: 144987

URL: http://llvm.org/viewvc/llvm-project?rev=144987&view=rev
Log:
Extend VPBLENDVB and VPSIGN lowering to work for AVX2.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/avx2-logic.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144987&r1=144986&r2=144987&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 19 01:07:26 2011
@@ -13859,98 +13859,105 @@
     return R;
 
   EVT VT = N->getValueType(0);
-  if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
-    return SDValue();
 
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
 
   // look for psign/blend
-  if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) {
-    if (VT == MVT::v2i64) {
-      // Canonicalize pandn to RHS
-      if (N0.getOpcode() == X86ISD::ANDNP)
-        std::swap(N0, N1);
-      // or (and (m, x), (pandn m, y))
-      if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
-        SDValue Mask = N1.getOperand(0);
-        SDValue X    = N1.getOperand(1);
-        SDValue Y;
-        if (N0.getOperand(0) == Mask)
-          Y = N0.getOperand(1);
-        if (N0.getOperand(1) == Mask)
-          Y = N0.getOperand(0);
-
-        // Check to see if the mask appeared in both the AND and ANDNP and
-        if (!Y.getNode())
-          return SDValue();
-
-        // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
-        if (Mask.getOpcode() != ISD::BITCAST ||
-            X.getOpcode() != ISD::BITCAST ||
-            Y.getOpcode() != ISD::BITCAST)
-          return SDValue();
-
-        // Look through mask bitcast.
-        Mask = Mask.getOperand(0);
-        EVT MaskVT = Mask.getValueType();
-
-        // Validate that the Mask operand is a vector sra node.  The sra node
-        // will be an intrinsic.
-        if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
-          return SDValue();
-
-        // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
-        // there is no psrai.b
-        switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
-        case Intrinsic::x86_sse2_psrai_w:
-        case Intrinsic::x86_sse2_psrai_d:
-          break;
-        default: return SDValue();
-        }
+  if (VT == MVT::v2i64 || VT == MVT::v4i64) {
+    if (!(Subtarget->hasSSSE3() || Subtarget->hasAVX()) ||
+        (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
+      return SDValue();
 
-        // Check that the SRA is all signbits.
-        SDValue SraC = Mask.getOperand(2);
-        unsigned SraAmt  = cast<ConstantSDNode>(SraC)->getZExtValue();
-        unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
-        if ((SraAmt + 1) != EltBits)
-          return SDValue();
-
-        DebugLoc DL = N->getDebugLoc();
-
-        // Now we know we at least have a plendvb with the mask val.  See if
-        // we can form a psignb/w/d.
-        // psign = x.type == y.type == mask.type && y = sub(0, x);
-        X = X.getOperand(0);
-        Y = Y.getOperand(0);
-        if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
-            ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
-            X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
-          unsigned Opc = 0;
-          switch (EltBits) {
-          case 8: Opc = X86ISD::PSIGNB; break;
-          case 16: Opc = X86ISD::PSIGNW; break;
-          case 32: Opc = X86ISD::PSIGND; break;
-          default: break;
-          }
-          if (Opc) {
-            SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
-            return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
-          }
+    // Canonicalize pandn to RHS
+    if (N0.getOpcode() == X86ISD::ANDNP)
+      std::swap(N0, N1);
+    // or (and (m, x), (pandn m, y))
+    if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
+      SDValue Mask = N1.getOperand(0);
+      SDValue X    = N1.getOperand(1);
+      SDValue Y;
+      if (N0.getOperand(0) == Mask)
+        Y = N0.getOperand(1);
+      if (N0.getOperand(1) == Mask)
+        Y = N0.getOperand(0);
+
+      // Check to see if the mask appeared in both the AND and ANDNP and
+      if (!Y.getNode())
+        return SDValue();
+
+      // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
+      if (Mask.getOpcode() != ISD::BITCAST ||
+          X.getOpcode() != ISD::BITCAST ||
+          Y.getOpcode() != ISD::BITCAST)
+        return SDValue();
+
+      // Look through mask bitcast.
+      Mask = Mask.getOperand(0);
+      EVT MaskVT = Mask.getValueType();
+
+      // Validate that the Mask operand is a vector sra node.  The sra node
+      // will be an intrinsic.
+      if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
+        return SDValue();
+
+      // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
+      // there is no psrai.b
+      switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
+      case Intrinsic::x86_sse2_psrai_w:
+      case Intrinsic::x86_sse2_psrai_d:
+      case Intrinsic::x86_avx2_psrai_w:
+      case Intrinsic::x86_avx2_psrai_d:
+        break;
+      default: return SDValue();
+      }
+
+      // Check that the SRA is all signbits.
+      SDValue SraC = Mask.getOperand(2);
+      unsigned SraAmt  = cast<ConstantSDNode>(SraC)->getZExtValue();
+      unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
+      if ((SraAmt + 1) != EltBits)
+        return SDValue();
+
+      DebugLoc DL = N->getDebugLoc();
+
+      // Now we know we at least have a plendvb with the mask val.  See if
+      // we can form a psignb/w/d.
+      // psign = x.type == y.type == mask.type && y = sub(0, x);
+      X = X.getOperand(0);
+      Y = Y.getOperand(0);
+      if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
+          ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
+          X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
+        unsigned Opc = 0;
+        switch (EltBits) {
+        case 8: Opc = X86ISD::PSIGNB; break;
+        case 16: Opc = X86ISD::PSIGNW; break;
+        case 32: Opc = X86ISD::PSIGND; break;
+        default: break;
+        }
+        if (Opc) {
+          SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
+          return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
         }
-        // PBLENDVB only available on SSE 4.1
-        if (!(Subtarget->hasSSE41() || Subtarget->hasAVX()))
-          return SDValue();
-
-        X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
-        Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
-        Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
-        Mask = DAG.getNode(ISD::VSELECT, DL, MVT::v16i8, Mask, X, Y);
-        return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
       }
+      // PBLENDVB only available on SSE 4.1
+      if (!(Subtarget->hasSSE41() || Subtarget->hasAVX()))
+        return SDValue();
+
+      EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
+
+      X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
+      Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
+      Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
+      Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, X, Y);
+      return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
     }
   }
 
+  if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
+    return SDValue();
+
   // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
   if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
     std::swap(N0, N1);

Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=144987&r1=144986&r2=144987&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Sat Nov 19 01:07:26 2011
@@ -52,13 +52,13 @@
                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>]>>;
 def X86psignb  : SDNode<"X86ISD::PSIGNB",
-                 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
+                 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>]>>;
 def X86psignw  : SDNode<"X86ISD::PSIGNW",
-                 SDTypeProfile<1, 2, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
+                 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>]>>;
 def X86psignd  : SDNode<"X86ISD::PSIGND",
-                 SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
+                 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>]>>;
 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144987&r1=144986&r2=144987&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 01:07:26 2011
@@ -3824,51 +3824,51 @@
 
 let Predicates = [HasAVX] in {
   def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
-            (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
+            (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
   def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
-            (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
+            (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
   def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
-            (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
+            (VPSLLDQri VR128:$src1, imm:$src2)>;
   def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
-            (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
+            (VPSRLDQri VR128:$src1, imm:$src2)>;
   def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
-            (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
+            (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
 
   // Shift up / down and insert zero's.
   def : Pat<(v2i64 (X86vshl  VR128:$src, (i8 imm:$amt))),
-            (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
+            (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
   def : Pat<(v2i64 (X86vshr  VR128:$src, (i8 imm:$amt))),
-            (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
+            (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
 }
 
 let Predicates = [HasAVX2] in {
   def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
-            (v4i64 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2)))>;
+            (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
   def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
-            (v4i64 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2)))>;
+            (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
   def : Pat<(int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2),
-            (v4i64 (VPSLLDQYri VR256:$src1, imm:$src2))>;
+            (VPSLLDQYri VR256:$src1, imm:$src2)>;
   def : Pat<(int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2),
-            (v4i64 (VPSRLDQYri VR256:$src1, imm:$src2))>;
+            (VPSRLDQYri VR256:$src1, imm:$src2)>;
 }
 
 let Predicates = [HasSSE2] in {
   def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
-            (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
+            (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
   def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
-            (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
+            (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
   def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
-            (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
+            (PSLLDQri VR128:$src1, imm:$src2)>;
   def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
-            (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
+            (PSRLDQri VR128:$src1, imm:$src2)>;
   def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
-            (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
+            (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
 
   // Shift up / down and insert zero's.
   def : Pat<(v2i64 (X86vshl  VR128:$src, (i8 imm:$amt))),
-            (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
+            (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
   def : Pat<(v2i64 (X86vshr  VR128:$src, (i8 imm:$amt))),
-            (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
+            (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
 }
 
 //===---------------------------------------------------------------------===//
@@ -5316,11 +5316,11 @@
                                         int_x86_avx2_pmadd_ub_sw>, VEX_4V;
   defm VPSHUFB    : SS3I_binop_rm_int_y<0x00, "vpshufb", memopv32i8,
                                         int_x86_avx2_pshuf_b>, VEX_4V;
-  defm VPSIGNB    : SS3I_binop_rm_int_y<0x08, "vpsignb", memopv16i8,
+  defm VPSIGNB    : SS3I_binop_rm_int_y<0x08, "vpsignb", memopv32i8,
                                         int_x86_avx2_psign_b>, VEX_4V;
-  defm VPSIGNW    : SS3I_binop_rm_int_y<0x09, "vpsignw", memopv8i16,
+  defm VPSIGNW    : SS3I_binop_rm_int_y<0x09, "vpsignw", memopv16i16,
                                         int_x86_avx2_psign_w>, VEX_4V;
-  defm VPSIGND    : SS3I_binop_rm_int_y<0x0A, "vpsignd", memopv4i32,
+  defm VPSIGND    : SS3I_binop_rm_int_y<0x0A, "vpsignd", memopv8i32,
                                         int_x86_avx2_psign_d>, VEX_4V;
 }
 defm VPMULHRSW    : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw", memopv16i16,
@@ -5363,11 +5363,11 @@
   def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
             (PSHUFBrm128 VR128:$src, addr:$mask)>;
 
-  def : Pat<(X86psignb VR128:$src1, VR128:$src2),
+  def : Pat<(v16i8 (X86psignb VR128:$src1, VR128:$src2)),
             (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
-  def : Pat<(X86psignw VR128:$src1, VR128:$src2),
+  def : Pat<(v8i16 (X86psignw VR128:$src1, VR128:$src2)),
             (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
-  def : Pat<(X86psignd VR128:$src1, VR128:$src2),
+  def : Pat<(v4i32 (X86psignd VR128:$src1, VR128:$src2)),
             (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
 }
 
@@ -5377,14 +5377,23 @@
   def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
             (VPSHUFBrm128 VR128:$src, addr:$mask)>;
 
-  def : Pat<(X86psignb VR128:$src1, VR128:$src2),
+  def : Pat<(v16i8 (X86psignb VR128:$src1, VR128:$src2)),
             (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
-  def : Pat<(X86psignw VR128:$src1, VR128:$src2),
+  def : Pat<(v8i16 (X86psignw VR128:$src1, VR128:$src2)),
             (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
-  def : Pat<(X86psignd VR128:$src1, VR128:$src2),
+  def : Pat<(v4i32 (X86psignd VR128:$src1, VR128:$src2)),
             (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
 }
 
+let Predicates = [HasAVX2] in {
+  def : Pat<(v32i8 (X86psignb VR256:$src1, VR256:$src2)),
+            (VPSIGNBrr256 VR256:$src1, VR256:$src2)>;
+  def : Pat<(v16i16 (X86psignw VR256:$src1, VR256:$src2)),
+            (VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
+  def : Pat<(v8i32 (X86psignd VR256:$src1, VR256:$src2)),
+            (VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
+}
+
 //===---------------------------------------------------------------------===//
 // SSSE3 - Packed Align Instruction Patterns
 //===---------------------------------------------------------------------===//

Modified: llvm/trunk/test/CodeGen/X86/avx2-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-logic.ll?rev=144987&r1=144986&r2=144987&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-logic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-logic.ll Sat Nov 19 01:07:26 2011
@@ -53,3 +53,32 @@
   %min = select <32 x i1> %min_is_x, <32 x i8> %x, <32 x i8> %y
   ret <32 x i8> %min
 }
+
+define <8 x i32> @signd(<8 x i32> %a, <8 x i32> %b) nounwind {
+entry:
+; CHECK: signd:
+; CHECK: psignd
+; CHECK-NOT: sub
+; CHECK: ret
+  %b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
+  %sub = sub nsw <8 x i32> zeroinitializer, %a
+  %0 = xor <8 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+  %1 = and <8 x i32> %a, %0
+  %2 = and <8 x i32> %b.lobit, %sub
+  %cond = or <8 x i32> %1, %2
+  ret <8 x i32> %cond
+}
+
+define <8 x i32> @blendvb(<8 x i32> %b, <8 x i32> %a, <8 x i32> %c) nounwind {
+entry:
+; CHECK: blendvb:
+; CHECK: pblendvb
+; CHECK: ret
+  %b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
+  %sub = sub nsw <8 x i32> zeroinitializer, %a
+  %0 = xor <8 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+  %1 = and <8 x i32> %c, %0
+  %2 = and <8 x i32> %a, %b.lobit
+  %cond = or <8 x i32> %1, %2
+  ret <8 x i32> %cond
+}



From craig.topper at gmail.com  Sat Nov 19 01:33:10 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sat, 19 Nov 2011 07:33:10 -0000
Subject: [llvm-commits] [llvm] r144988 - in /llvm/trunk/lib/Target/X86:
 X86ISelLowering.cpp X86ISelLowering.h X86InstrFragmentsSIMD.td
 X86InstrSSE.td
Message-ID: <20111119073310.687D02A6C133@llvm.org>

Author: ctopper
Date: Sat Nov 19 01:33:10 2011
New Revision: 144988

URL: http://llvm.org/viewvc/llvm-project?rev=144988&view=rev
Log:
Collapse X86 PSIGNB/PSIGNW/PSIGND node types.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144988&r1=144987&r2=144988&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 19 01:33:10 2011
@@ -11084,9 +11084,7 @@
   case X86ISD::PINSRW:             return "X86ISD::PINSRW";
   case X86ISD::PSHUFB:             return "X86ISD::PSHUFB";
   case X86ISD::ANDNP:              return "X86ISD::ANDNP";
-  case X86ISD::PSIGNB:             return "X86ISD::PSIGNB";
-  case X86ISD::PSIGNW:             return "X86ISD::PSIGNW";
-  case X86ISD::PSIGND:             return "X86ISD::PSIGND";
+  case X86ISD::PSIGN:              return "X86ISD::PSIGN";
   case X86ISD::BLENDV:             return "X86ISD::BLENDV";
   case X86ISD::FHADD:              return "X86ISD::FHADD";
   case X86ISD::FHSUB:              return "X86ISD::FHSUB";
@@ -13928,18 +13926,11 @@
       Y = Y.getOperand(0);
       if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
           ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
-          X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
-        unsigned Opc = 0;
-        switch (EltBits) {
-        case 8: Opc = X86ISD::PSIGNB; break;
-        case 16: Opc = X86ISD::PSIGNW; break;
-        case 32: Opc = X86ISD::PSIGND; break;
-        default: break;
-        }
-        if (Opc) {
-          SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
-          return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
-        }
+          X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() &&
+          (EltBits == 8 || EltBits == 16 || EltBits == 32)) {
+        SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X,
+                                   Mask.getOperand(1));
+        return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
       }
       // PBLENDVB only available on SSE 4.1
       if (!(Subtarget->hasSSE41() || Subtarget->hasAVX()))

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=144988&r1=144987&r2=144988&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sat Nov 19 01:33:10 2011
@@ -172,8 +172,8 @@
       /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
       ANDNP,
 
-      /// PSIGNB/W/D - Copy integer sign.
-      PSIGNB, PSIGNW, PSIGND,
+      /// PSIGN - Copy integer sign.
+      PSIGN,
 
       /// BLEND family of opcodes
       BLENDV,

Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=144988&r1=144987&r2=144988&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Sat Nov 19 01:33:10 2011
@@ -51,13 +51,7 @@
 def X86andnp   : SDNode<"X86ISD::ANDNP",
                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>]>>;
-def X86psignb  : SDNode<"X86ISD::PSIGNB",
-                 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
-                                      SDTCisSameAs<0,2>]>>;
-def X86psignw  : SDNode<"X86ISD::PSIGNW",
-                 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
-                                      SDTCisSameAs<0,2>]>>;
-def X86psignd  : SDNode<"X86ISD::PSIGND",
+def X86psign   : SDNode<"X86ISD::PSIGN",
                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>]>>;
 def X86pextrb  : SDNode<"X86ISD::PEXTRB",

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144988&r1=144987&r2=144988&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 01:33:10 2011
@@ -5363,11 +5363,11 @@
   def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
             (PSHUFBrm128 VR128:$src, addr:$mask)>;
 
-  def : Pat<(v16i8 (X86psignb VR128:$src1, VR128:$src2)),
+  def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
             (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v8i16 (X86psignw VR128:$src1, VR128:$src2)),
+  def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
             (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4i32 (X86psignd VR128:$src1, VR128:$src2)),
+  def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
             (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
 }
 
@@ -5377,20 +5377,20 @@
   def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
             (VPSHUFBrm128 VR128:$src, addr:$mask)>;
 
-  def : Pat<(v16i8 (X86psignb VR128:$src1, VR128:$src2)),
+  def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
             (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v8i16 (X86psignw VR128:$src1, VR128:$src2)),
+  def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
             (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4i32 (X86psignd VR128:$src1, VR128:$src2)),
+  def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
             (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
 }
 
 let Predicates = [HasAVX2] in {
-  def : Pat<(v32i8 (X86psignb VR256:$src1, VR256:$src2)),
+  def : Pat<(v32i8 (X86psign VR256:$src1, VR256:$src2)),
             (VPSIGNBrr256 VR256:$src1, VR256:$src2)>;
-  def : Pat<(v16i16 (X86psignw VR256:$src1, VR256:$src2)),
+  def : Pat<(v16i16 (X86psign VR256:$src1, VR256:$src2)),
             (VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
-  def : Pat<(v8i32 (X86psignd VR256:$src1, VR256:$src2)),
+  def : Pat<(v8i32 (X86psign VR256:$src1, VR256:$src2)),
             (VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
 }
 



From craig.topper at gmail.com  Sat Nov 19 03:02:41 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sat, 19 Nov 2011 09:02:41 -0000
Subject: [llvm-commits] [llvm] r144989 - in /llvm/trunk/lib/Target/X86:
 X86ISelLowering.cpp X86ISelLowering.h X86InstrFragmentsSIMD.td
 X86InstrSSE.td
Message-ID: <20111119090241.2748F2A6C133@llvm.org>

Author: ctopper
Date: Sat Nov 19 03:02:40 2011
New Revision: 144989

URL: http://llvm.org/viewvc/llvm-project?rev=144989&view=rev
Log:
Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144989&r1=144988&r2=144989&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 19 03:02:40 2011
@@ -14670,7 +14670,24 @@
                      DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
 }
 
-static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
+/// PerformADDCombine - Do target-specific dag combines on integer adds.
+static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
+                                 const X86Subtarget *Subtarget) {
+  EVT VT = N->getValueType(0);
+  SDValue Op0 = N->getOperand(0);
+  SDValue Op1 = N->getOperand(1);
+
+  // Try to synthesize horizontal adds from adds of shuffles.
+  if ((Subtarget->hasSSSE3() || Subtarget->hasAVX()) &&
+      (VT == MVT::v8i16 || VT == MVT::v4i32) &&
+      isHorizontalBinOp(Op0, Op1, true))
+    return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
+
+  return OptimizeConditionalInDecrement(N, DAG);
+}
+
+static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
+                                 const X86Subtarget *Subtarget) {
   SDValue Op0 = N->getOperand(0);
   SDValue Op1 = N->getOperand(1);
 
@@ -14692,6 +14709,13 @@
     }
   }
 
+  // Try to synthesize horizontal adds from adds of shuffles.
+  EVT VT = N->getValueType(0);
+  if ((Subtarget->hasSSSE3() || Subtarget->hasAVX()) &&
+      (VT == MVT::v8i16 || VT == MVT::v4i32) &&
+      isHorizontalBinOp(Op0, Op1, false))
+    return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
+
   return OptimizeConditionalInDecrement(N, DAG);
 }
 
@@ -14705,8 +14729,8 @@
   case ISD::VSELECT:
   case ISD::SELECT:         return PerformSELECTCombine(N, DAG, Subtarget);
   case X86ISD::CMOV:        return PerformCMOVCombine(N, DAG, DCI);
-  case ISD::ADD:            return OptimizeConditionalInDecrement(N, DAG);
-  case ISD::SUB:            return PerformSubCombine(N, DAG);
+  case ISD::ADD:            return PerformAddCombine(N, DAG, Subtarget);
+  case ISD::SUB:            return PerformSubCombine(N, DAG, Subtarget);
   case X86ISD::ADC:         return PerformADCCombine(N, DAG, DCI);
   case ISD::MUL:            return PerformMulCombine(N, DAG, DCI);
   case ISD::SHL:

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=144989&r1=144988&r2=144989&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sat Nov 19 03:02:40 2011
@@ -178,6 +178,12 @@
       /// BLEND family of opcodes
       BLENDV,
 
+      /// HADD - Integer horizontal add.
+      HADD,
+
+      /// HSUB - Integer horizontal sub.
+      HSUB,
+
       /// FHADD - Floating point horizontal add.
       FHADD,
 

Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=144989&r1=144988&r2=144989&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Sat Nov 19 03:02:40 2011
@@ -41,6 +41,8 @@
 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
 def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
 def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
+def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
+def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
 def X86cmpss   : SDNode<"X86ISD::FSETCCss",    SDTX86Cmpss>;

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144989&r1=144988&r2=144989&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 03:02:40 2011
@@ -5369,6 +5369,15 @@
             (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
   def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
             (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
+
+  def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
+            (PHADDWrr128 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
+            (PHADDDrr128 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
+            (PHSUBWrr128 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
+            (PHSUBDrr128 VR128:$src1, VR128:$src2)>;
 }
 
 let Predicates = [HasAVX] in {
@@ -5383,6 +5392,15 @@
             (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
   def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
             (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
+
+  def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
+            (VPHADDWrr128 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
+            (VPHADDDrr128 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
+            (VPHSUBWrr128 VR128:$src1, VR128:$src2)>;
+  def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
+            (VPHSUBDrr128 VR128:$src1, VR128:$src2)>;
 }
 
 let Predicates = [HasAVX2] in {
@@ -5392,6 +5410,15 @@
             (VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
   def : Pat<(v8i32 (X86psign VR256:$src1, VR256:$src2)),
             (VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
+
+  def : Pat<(v16i16 (X86hadd VR256:$src1, VR256:$src2)),
+            (VPHADDWrr256 VR256:$src1, VR256:$src2)>;
+  def : Pat<(v8i32 (X86hadd VR256:$src1, VR256:$src2)),
+            (VPHADDDrr256 VR256:$src1, VR256:$src2)>;
+  def : Pat<(v16i16 (X86hsub VR256:$src1, VR256:$src2)),
+            (VPHSUBWrr256 VR256:$src1, VR256:$src2)>;
+  def : Pat<(v8i32 (X86hsub VR256:$src1, VR256:$src2)),
+            (VPHSUBDrr256 VR256:$src1, VR256:$src2)>;
 }
 
 //===---------------------------------------------------------------------===//



From craig.topper at gmail.com  Sat Nov 19 03:03:33 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sat, 19 Nov 2011 09:03:33 -0000
Subject: [llvm-commits] [llvm] r144990 -
	/llvm/trunk/test/CodeGen/X86/phaddsub.ll
Message-ID: <20111119090333.93CF42A6C134@llvm.org>

Author: ctopper
Date: Sat Nov 19 03:03:33 2011
New Revision: 144990

URL: http://llvm.org/viewvc/llvm-project?rev=144990&view=rev
Log:
Test cases for SSSE3/AVX integer horizontal add/sub.

Added:
    llvm/trunk/test/CodeGen/X86/phaddsub.ll

Added: llvm/trunk/test/CodeGen/X86/phaddsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/phaddsub.ll?rev=144990&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/phaddsub.ll (added)
+++ llvm/trunk/test/CodeGen/X86/phaddsub.ll Sat Nov 19 03:03:33 2011
@@ -0,0 +1,170 @@
+; RUN: llc < %s -march=x86-64 -mattr=+ssse3,-avx | FileCheck %s -check-prefix=SSSE3
+; RUN: llc < %s -march=x86-64 -mattr=-ssse3,+avx | FileCheck %s -check-prefix=AVX
+
+; SSSE3: phaddw1:
+; SSSE3-NOT: vphaddw
+; SSSE3: phaddw
+; AVX: phaddw1:
+; AVX: vphaddw
+define <8 x i16> @phaddw1(<8 x i16> %x, <8 x i16> %y) {
+  %a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+  %b = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+  %r = add <8 x i16> %a, %b
+  ret <8 x i16> %r
+}
+
+; SSSE3: phaddw2:
+; SSSE3-NOT: vphaddw
+; SSSE3: phaddw
+; AVX: phaddw2:
+; AVX: vphaddw
+define <8 x i16> @phaddw2(<8 x i16> %x, <8 x i16> %y) {
+  %a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 2, i32 5, i32 6, i32 9, i32 10, i32 13, i32 14>
+  %b = shufflevector <8 x i16> %y, <8 x i16> %x, <8 x i32> <i32 8, i32 11, i32 12, i32 15, i32 0, i32 3, i32 4, i32 7>
+  %r = add <8 x i16> %a, %b
+  ret <8 x i16> %r
+}
+
+; SSSE3: phaddd1:
+; SSSE3-NOT: vphaddd
+; SSSE3: phaddd
+; AVX: phaddd1:
+; AVX: vphaddd
+define <4 x i32> @phaddd1(<4 x i32> %x, <4 x i32> %y) {
+  %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+  %b = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %r = add <4 x i32> %a, %b
+  ret <4 x i32> %r
+}
+
+; SSSE3: phaddd2:
+; SSSE3-NOT: vphaddd
+; SSSE3: phaddd
+; AVX: phaddd2:
+; AVX: vphaddd
+define <4 x i32> @phaddd2(<4 x i32> %x, <4 x i32> %y) {
+  %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
+  %b = shufflevector <4 x i32> %y, <4 x i32> %x, <4 x i32> <i32 4, i32 7, i32 0, i32 3>
+  %r = add <4 x i32> %a, %b
+  ret <4 x i32> %r
+}
+
+; SSSE3: phaddd3:
+; SSSE3-NOT: vphaddd
+; SSSE3: phaddd
+; AVX: phaddd3:
+; AVX: vphaddd
+define <4 x i32> @phaddd3(<4 x i32> %x) {
+  %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
+  %b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
+  %r = add <4 x i32> %a, %b
+  ret <4 x i32> %r
+}
+
+; SSSE3: phaddd4:
+; SSSE3-NOT: vphaddd
+; SSSE3: phaddd
+; AVX: phaddd4:
+; AVX: vphaddd
+define <4 x i32> @phaddd4(<4 x i32> %x) {
+  %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
+  %b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
+  %r = add <4 x i32> %a, %b
+  ret <4 x i32> %r
+}
+
+; SSSE3: phaddd5:
+; SSSE3-NOT: vphaddd
+; SSSE3: phaddd
+; AVX: phaddd5:
+; AVX: vphaddd
+define <4 x i32> @phaddd5(<4 x i32> %x) {
+  %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
+  %b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 undef, i32 undef>
+  %r = add <4 x i32> %a, %b
+  ret <4 x i32> %r
+}
+
+; SSSE3: phaddd6:
+; SSSE3-NOT: vphaddd
+; SSSE3: phaddd
+; AVX: phaddd6:
+; AVX: vphaddd
+define <4 x i32> @phaddd6(<4 x i32> %x) {
+  %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+  %b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+  %r = add <4 x i32> %a, %b
+  ret <4 x i32> %r
+}
+
+; SSSE3: phaddd7:
+; SSSE3-NOT: vphaddd
+; SSSE3: phaddd
+; AVX: phaddd7:
+; AVX: vphaddd
+define <4 x i32> @phaddd7(<4 x i32> %x) {
+  %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
+  %b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
+  %r = add <4 x i32> %a, %b
+  ret <4 x i32> %r
+}
+
+; SSSE3: phsubw1:
+; SSSE3-NOT: vphsubw
+; SSSE3: phsubw
+; AVX: phsubw1:
+; AVX: vphsubw
+define <8 x i16> @phsubw1(<8 x i16> %x, <8 x i16> %y) {
+  %a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+  %b = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+  %r = sub <8 x i16> %a, %b
+  ret <8 x i16> %r
+}
+
+; SSSE3: phsubd1:
+; SSSE3-NOT: vphsubd
+; SSSE3: phsubd
+; AVX: phsubd1:
+; AVX: vphsubd
+define <4 x i32> @phsubd1(<4 x i32> %x, <4 x i32> %y) {
+  %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+  %b = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %r = sub <4 x i32> %a, %b
+  ret <4 x i32> %r
+}
+
+; SSSE3: phsubd2:
+; SSSE3-NOT: vphsubd
+; SSSE3: phsubd
+; AVX: phsubd2:
+; AVX: vphsubd
+define <4 x i32> @phsubd2(<4 x i32> %x) {
+  %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
+  %b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
+  %r = sub <4 x i32> %a, %b
+  ret <4 x i32> %r
+}
+
+; SSSE3: phsubd3:
+; SSSE3-NOT: vphsubd
+; SSSE3: phsubd
+; AVX: phsubd3:
+; AVX: vphsubd
+define <4 x i32> @phsubd3(<4 x i32> %x) {
+  %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
+  %b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
+  %r = sub <4 x i32> %a, %b
+  ret <4 x i32> %r
+}
+
+; SSSE3: phsubd4:
+; SSSE3-NOT: vphsubd
+; SSSE3: phsubd
+; AVX: phsubd4:
+; AVX: vphsubd
+define <4 x i32> @phsubd4(<4 x i32> %x) {
+  %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+  %b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+  %r = sub <4 x i32> %a, %b
+  ret <4 x i32> %r
+}



From chandlerc at gmail.com  Sat Nov 19 04:26:02 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Sat, 19 Nov 2011 10:26:02 -0000
Subject: [llvm-commits] [llvm] r144994 - in /llvm/trunk:
 lib/CodeGen/MachineBlockPlacement.cpp test/CodeGen/X86/block-placement.ll
Message-ID: <20111119102602.9E3EE2A6C134@llvm.org>

Author: chandlerc
Date: Sat Nov 19 04:26:02 2011
New Revision: 144994

URL: http://llvm.org/viewvc/llvm-project?rev=144994&view=rev
Log:
Move the handling of unanalyzable branches out of the loop-driven chain
formation phase and into the initial walk of the basic blocks. We
essentially pre-merge all blocks where unanalyzable fallthrough exists,
as we won't be able to update the terminators effectively after any
reorderings. This is quite a bit more principled as there may be CFGs
where the second half of the unanalyzable pair has some analyzable
predecessor that gets placed first. Then it may get placed next,
implicitly breaking the unanalyzable branch even though we never even
looked at the part that isn't analyzable. I've included a test case that
triggers this (thanks Benjamin yet again!), and I'm hoping to synthesize
some more general ones as I dig into related issues.

Also, to make this new scheme work we have to be able to handle branches
into the middle of a chain, so add this check. We always fallback on the
incoming ordering.

Finally, this starts to really underscore a known limitation of the
current implementation -- we don't consider broken predecessors when
merging successors. This can caused major missed opportunities, and is
something I'm planning on looking at next (modulo more bug reports).

Modified:
    llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
    llvm/trunk/test/CodeGen/X86/block-placement.ll

Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=144994&r1=144993&r2=144994&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Sat Nov 19 04:26:02 2011
@@ -355,6 +355,10 @@
       DEBUG(dbgs() << "    " << getBlockName(*SI) << " -> Already merged!\n");
       continue;
     }
+    if (*SI != *SuccChain.begin()) {
+      DEBUG(dbgs() << "    " << getBlockName(*SI) << " -> Mid chain!\n");
+      continue;
+    }
 
     uint32_t SuccWeight = MBPI->getEdgeWeight(BB, *SI);
     BranchProbability SuccProb(SuccWeight / WeightScale, SumWeight);
@@ -472,7 +476,6 @@
   assert(BB);
   assert(BlockToChain[BB] == &Chain);
   assert(*Chain.begin() == BB);
-  SmallVector<MachineOperand, 4> Cond; // For AnalyzeBranch.
   MachineFunction &F = *BB->getParent();
   MachineFunction::iterator PrevUnplacedBlockIt = F.begin();
 
@@ -485,26 +488,9 @@
     assert(*llvm::prior(Chain.end()) == BB);
     MachineBasicBlock *BestSucc = 0;
 
-    // Check for unreasonable branches, and forcibly merge the existing layout
-    // successor for them. We can handle cases that AnalyzeBranch can't: jump
-    // tables etc are fine. The case we want to handle specially is when there
-    // is potential fallthrough, but the branch cannot be analyzed. This
-    // includes blocks without terminators as well as other cases.
-    Cond.clear();
-    MachineBasicBlock *TBB = 0, *FBB = 0; // For AnalyzeBranch.
-    if (TII->AnalyzeBranch(*BB, TBB, FBB, Cond) && BB->canFallThrough()) {
-      MachineFunction::iterator I(BB), NextI(llvm::next(I));
-      // Ensure that the layout successor is a viable block, as we know that
-      // fallthrough is a possibility. Note that this may not be a valid block
-      // in the loop, but we allow that to cope with degenerate situations.
-      assert(NextI != BB->getParent()->end());
-      BestSucc = NextI;
-    }
-
-    // Otherwise, look for the best viable successor if there is one to place
-    // immediately after this block.
-    if (!BestSucc)
-      BestSucc = selectBestSuccessor(BB, Chain, BlockFilter);
+    // Look for the best viable successor if there is one to place immediately
+    // after this block.
+    BestSucc = selectBestSuccessor(BB, Chain, BlockFilter);
 
     // If an immediate successor isn't available, look for the best viable
     // block among those we've identified as not violating the loop's CFG at
@@ -624,9 +610,32 @@
 void MachineBlockPlacement::buildCFGChains(MachineFunction &F) {
   // Ensure that every BB in the function has an associated chain to simplify
   // the assumptions of the remaining algorithm.
-  for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
-    BlockToChain[&*FI] =
-      new (ChainAllocator.Allocate()) BlockChain(BlockToChain, &*FI);
+  SmallVector<MachineOperand, 4> Cond; // For AnalyzeBranch.
+  for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) {
+    MachineBasicBlock *BB = FI;
+    BlockChain *&Chain = BlockToChain[BB];
+    Chain = new (ChainAllocator.Allocate()) BlockChain(BlockToChain, BB);
+    // Also, merge any blocks which we cannot reason about and must preserve
+    // the exact fallthrough behavior for.
+    for (;;) {
+      Cond.clear();
+      MachineBasicBlock *TBB = 0, *FBB = 0; // For AnalyzeBranch.
+      if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond) || !FI->canFallThrough())
+        break;
+
+      MachineFunction::iterator NextFI(llvm::next(FI));
+      MachineBasicBlock *NextBB = NextFI;
+      // Ensure that the layout successor is a viable block, as we know that
+      // fallthrough is a possibility.
+      assert(NextFI != FE && "Can't fallthrough past the last block.");
+      DEBUG(dbgs() << "Pre-merging due to unanalyzable fallthrough: "
+                   << getBlockName(BB) << " -> " << getBlockName(NextBB)
+                   << "\n");
+      Chain->merge(NextBB, 0);
+      FI = NextFI;
+      BB = NextBB;
+    }
+  }
 
   // Build any loop-based chains.
   for (MachineLoopInfo::iterator LI = MLI->begin(), LE = MLI->end(); LI != LE;
@@ -692,7 +701,6 @@
 
   // Splice the blocks into place.
   MachineFunction::iterator InsertPos = F.begin();
-  SmallVector<MachineOperand, 4> Cond; // For AnalyzeBranch.
   for (BlockChain::iterator BI = FunctionChain.begin(),
                             BE = FunctionChain.end();
        BI != BE; ++BI) {

Modified: llvm/trunk/test/CodeGen/X86/block-placement.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=144994&r1=144993&r2=144994&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/block-placement.ll (original)
+++ llvm/trunk/test/CodeGen/X86/block-placement.ll Sat Nov 19 04:26:02 2011
@@ -393,3 +393,28 @@
   %merge = phi i32 [ 3, %step ], [ 6, %entry ]
   ret i32 %merge
 }
+
+define void @fpcmp_unanalyzable_branch(i1 %cond) {
+entry:
+  br i1 %cond, label %entry.if.then_crit_edge, label %lor.lhs.false
+
+entry.if.then_crit_edge:
+  %.pre14 = load i8* undef, align 1, !tbaa !0
+  br label %if.then
+
+lor.lhs.false:
+  br i1 undef, label %if.end, label %exit
+
+exit:
+  %cmp.i = fcmp une double 0.000000e+00, undef
+  br i1 %cmp.i, label %if.then, label %if.end
+
+if.then:
+  %0 = phi i8 [ %.pre14, %entry.if.then_crit_edge ], [ undef, %exit ]
+  %1 = and i8 %0, 1
+  store i8 %1, i8* undef, align 4, !tbaa !0
+  br label %if.end
+
+if.end:
+  ret void
+}



From baldrick at free.fr  Sat Nov 19 07:39:59 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sat, 19 Nov 2011 13:39:59 -0000
Subject: [llvm-commits] [dragonegg] r144996 - in /dragonegg/trunk/src:
 Backend.cpp Constants.cpp Convert.cpp Debug.cpp Types.cpp
Message-ID: <20111119133959.25CA42A6C134@llvm.org>

Author: baldrick
Date: Sat Nov 19 07:39:58 2011
New Revision: 144996

URL: http://llvm.org/viewvc/llvm-project?rev=144996&view=rev
Log:
Header file trimming.

Modified:
    dragonegg/trunk/src/Backend.cpp
    dragonegg/trunk/src/Constants.cpp
    dragonegg/trunk/src/Convert.cpp
    dragonegg/trunk/src/Debug.cpp
    dragonegg/trunk/src/Types.cpp

Modified: dragonegg/trunk/src/Backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=144996&r1=144995&r2=144996&view=diff
==============================================================================
--- dragonegg/trunk/src/Backend.cpp (original)
+++ dragonegg/trunk/src/Backend.cpp Sat Nov 19 07:39:58 2011
@@ -35,11 +35,9 @@
 #include "llvm/Module.h"
 #include "llvm/PassManager.h"
 #include "llvm/ADT/StringExtras.h"
-#include "llvm/Analysis/Verifier.h"
 #include "llvm/Assembly/PrintModulePass.h"
 #include "llvm/Bitcode/ReaderWriter.h"
 #include "llvm/CodeGen/RegAllocRegistry.h"
-#include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/TargetRegistry.h"

Modified: dragonegg/trunk/src/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Constants.cpp?rev=144996&r1=144995&r2=144996&view=diff
==============================================================================
--- dragonegg/trunk/src/Constants.cpp (original)
+++ dragonegg/trunk/src/Constants.cpp Sat Nov 19 07:39:58 2011
@@ -32,7 +32,6 @@
 #include "llvm/GlobalVariable.h"
 #include "llvm/LLVMContext.h"
 #include "llvm/Support/Host.h"
-#include "llvm/Support/TargetFolder.h"
 #include "llvm/Target/TargetData.h"
 
 // System headers

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=144996&r1=144995&r2=144996&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Sat Nov 19 07:39:58 2011
@@ -31,7 +31,6 @@
 #include "llvm/Module.h"
 #include "llvm/Support/CFG.h"
 #include "llvm/Support/Debug.h"
-#include "llvm/Support/Host.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/StringExtras.h"

Modified: dragonegg/trunk/src/Debug.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Debug.cpp?rev=144996&r1=144995&r2=144996&view=diff
==============================================================================
--- dragonegg/trunk/src/Debug.cpp (original)
+++ dragonegg/trunk/src/Debug.cpp Sat Nov 19 07:39:58 2011
@@ -26,7 +26,6 @@
 
 // LLVM headers
 #include "llvm/Module.h"
-#include "llvm/ADT/STLExtras.h"
 
 // System headers
 #include <gmp.h>

Modified: dragonegg/trunk/src/Types.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Types.cpp?rev=144996&r1=144995&r2=144996&view=diff
==============================================================================
--- dragonegg/trunk/src/Types.cpp (original)
+++ dragonegg/trunk/src/Types.cpp Sat Nov 19 07:39:58 2011
@@ -29,13 +29,7 @@
 #include "dragonegg/ADT/Range.h"
 
 // LLVM headers
-#include "llvm/Module.h"
-#include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/SCCIterator.h"
-#include "llvm/Assembly/Writer.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetMachine.h"
 
 // System headers
 #include <gmp.h>



From baldrick at free.fr  Sat Nov 19 07:47:57 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sat, 19 Nov 2011 14:47:57 +0100
Subject: [llvm-commits] [llvm] r144989 - in /llvm/trunk/lib/Target/X86:
 X86ISelLowering.cpp X86ISelLowering.h X86InstrFragmentsSIMD.td
 X86InstrSSE.td
In-Reply-To: <20111119090241.2748F2A6C133@llvm.org>
References: <20111119090241.2748F2A6C133@llvm.org>
Message-ID: <4EC7B38D.6090706@free.fr>

Hi Craig,

> Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors.

testcase?

Ciao, Duncan.

>
> Modified:
>      llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>      llvm/trunk/lib/Target/X86/X86ISelLowering.h
>      llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
>      llvm/trunk/lib/Target/X86/X86InstrSSE.td
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144989&r1=144988&r2=144989&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 19 03:02:40 2011
> @@ -14670,7 +14670,24 @@
>                        DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
>   }
>
> -static SDValue PerformSubCombine(SDNode *N, SelectionDAG&DAG) {
> +/// PerformADDCombine - Do target-specific dag combines on integer adds.
> +static SDValue PerformAddCombine(SDNode *N, SelectionDAG&DAG,
> +                                 const X86Subtarget *Subtarget) {
> +  EVT VT = N->getValueType(0);
> +  SDValue Op0 = N->getOperand(0);
> +  SDValue Op1 = N->getOperand(1);
> +
> +  // Try to synthesize horizontal adds from adds of shuffles.
> +  if ((Subtarget->hasSSSE3() || Subtarget->hasAVX())&&
> +      (VT == MVT::v8i16 || VT == MVT::v4i32)&&
> +      isHorizontalBinOp(Op0, Op1, true))
> +    return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
> +
> +  return OptimizeConditionalInDecrement(N, DAG);
> +}
> +
> +static SDValue PerformSubCombine(SDNode *N, SelectionDAG&DAG,
> +                                 const X86Subtarget *Subtarget) {
>     SDValue Op0 = N->getOperand(0);
>     SDValue Op1 = N->getOperand(1);
>
> @@ -14692,6 +14709,13 @@
>       }
>     }
>
> +  // Try to synthesize horizontal adds from adds of shuffles.
> +  EVT VT = N->getValueType(0);
> +  if ((Subtarget->hasSSSE3() || Subtarget->hasAVX())&&
> +      (VT == MVT::v8i16 || VT == MVT::v4i32)&&
> +      isHorizontalBinOp(Op0, Op1, false))
> +    return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
> +
>     return OptimizeConditionalInDecrement(N, DAG);
>   }
>
> @@ -14705,8 +14729,8 @@
>     case ISD::VSELECT:
>     case ISD::SELECT:         return PerformSELECTCombine(N, DAG, Subtarget);
>     case X86ISD::CMOV:        return PerformCMOVCombine(N, DAG, DCI);
> -  case ISD::ADD:            return OptimizeConditionalInDecrement(N, DAG);
> -  case ISD::SUB:            return PerformSubCombine(N, DAG);
> +  case ISD::ADD:            return PerformAddCombine(N, DAG, Subtarget);
> +  case ISD::SUB:            return PerformSubCombine(N, DAG, Subtarget);
>     case X86ISD::ADC:         return PerformADCCombine(N, DAG, DCI);
>     case ISD::MUL:            return PerformMulCombine(N, DAG, DCI);
>     case ISD::SHL:
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=144989&r1=144988&r2=144989&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sat Nov 19 03:02:40 2011
> @@ -178,6 +178,12 @@
>         /// BLEND family of opcodes
>         BLENDV,
>
> +      /// HADD - Integer horizontal add.
> +      HADD,
> +
> +      /// HSUB - Integer horizontal sub.
> +      HSUB,
> +
>         /// FHADD - Floating point horizontal add.
>         FHADD,
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=144989&r1=144988&r2=144989&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Sat Nov 19 03:02:40 2011
> @@ -41,6 +41,8 @@
>   def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
>   def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
>   def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
> +def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
> +def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
>   def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
>   def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
>   def X86cmpss   : SDNode<"X86ISD::FSETCCss",    SDTX86Cmpss>;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144989&r1=144988&r2=144989&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 03:02:40 2011
> @@ -5369,6 +5369,15 @@
>               (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
>     def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
>               (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
> +
> +  def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
> +            (PHADDWrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
> +            (PHADDDrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
> +            (PHSUBWrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
> +            (PHSUBDrr128 VR128:$src1, VR128:$src2)>;
>   }
>
>   let Predicates = [HasAVX] in {
> @@ -5383,6 +5392,15 @@
>               (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
>     def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
>               (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
> +
> +  def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
> +            (VPHADDWrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
> +            (VPHADDDrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
> +            (VPHSUBWrr128 VR128:$src1, VR128:$src2)>;
> +  def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
> +            (VPHSUBDrr128 VR128:$src1, VR128:$src2)>;
>   }
>
>   let Predicates = [HasAVX2] in {
> @@ -5392,6 +5410,15 @@
>               (VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
>     def : Pat<(v8i32 (X86psign VR256:$src1, VR256:$src2)),
>               (VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
> +
> +  def : Pat<(v16i16 (X86hadd VR256:$src1, VR256:$src2)),
> +            (VPHADDWrr256 VR256:$src1, VR256:$src2)>;
> +  def : Pat<(v8i32 (X86hadd VR256:$src1, VR256:$src2)),
> +            (VPHADDDrr256 VR256:$src1, VR256:$src2)>;
> +  def : Pat<(v16i16 (X86hsub VR256:$src1, VR256:$src2)),
> +            (VPHSUBWrr256 VR256:$src1, VR256:$src2)>;
> +  def : Pat<(v8i32 (X86hsub VR256:$src1, VR256:$src2)),
> +            (VPHSUBDrr256 VR256:$src1, VR256:$src2)>;
>   }
>
>   //===---------------------------------------------------------------------===//
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From baldrick at free.fr  Sat Nov 19 08:06:53 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sat, 19 Nov 2011 14:06:53 -0000
Subject: [llvm-commits] [dragonegg] r144997 - in /dragonegg/trunk/src:
	Convert.cpp Debug.cpp
Message-ID: <20111119140653.F40912A6C134@llvm.org>

Author: baldrick
Date: Sat Nov 19 08:06:53 2011
New Revision: 144997

URL: http://llvm.org/viewvc/llvm-project?rev=144997&view=rev
Log:
No need to use c_str here anymore.

Modified:
    dragonegg/trunk/src/Convert.cpp
    dragonegg/trunk/src/Debug.cpp

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=144997&r1=144996&r2=144997&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Sat Nov 19 08:06:53 2011
@@ -386,15 +386,14 @@
         } else if (ArgVal->getType()->isDoubleTy()) {
           // If this is a K&R float parameter, it got promoted to double. Insert
           // the truncation to float now.
-          ArgVal = Builder.CreateFPTrunc(ArgVal, LLVMTy,
-                                         NameStack.back().c_str());
+          ArgVal = Builder.CreateFPTrunc(ArgVal, LLVMTy, NameStack.back());
         } else {
           // If this is just a mismatch between integer types, this is due
           // to K&R prototypes, where the forward proto defines the arg as int
           // and the actual impls is a short or char.
           assert(ArgVal->getType()->isIntegerTy(32) && LLVMTy->isIntegerTy() &&
                  "Lowerings don't match?");
-          ArgVal = Builder.CreateTrunc(ArgVal, LLVMTy,NameStack.back().c_str());
+          ArgVal = Builder.CreateTrunc(ArgVal, LLVMTy,NameStack.back());
         }
       }
       assert(!LocStack.empty());

Modified: dragonegg/trunk/src/Debug.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Debug.cpp?rev=144997&r1=144996&r2=144997&view=diff
==============================================================================
--- dragonegg/trunk/src/Debug.cpp (original)
+++ dragonegg/trunk/src/Debug.cpp Sat Nov 19 08:06:53 2011
@@ -1133,8 +1133,7 @@
   unsigned ObjcRunTimeVer = 0;
 //  if (flag_objc_abi != 0 && flag_objc_abi != -1)
 //    ObjcRunTimeVer = flag_objc_abi;
-  return DebugFactory.CreateCompileUnit(LangTag, FileName.c_str(),
-                                        Directory.c_str(),
+  return DebugFactory.CreateCompileUnit(LangTag, FileName, Directory,
                                         version_string, isMain,
                                         optimize, Flags,
                                         ObjcRunTimeVer);



From baldrick at free.fr  Sat Nov 19 08:46:05 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sat, 19 Nov 2011 14:46:05 -0000
Subject: [llvm-commits] [dragonegg] r144998 -
	/dragonegg/trunk/src/Backend.cpp
Message-ID: <20111119144605.1A44A2A6C134@llvm.org>

Author: baldrick
Date: Sat Nov 19 08:46:04 2011
New Revision: 144998

URL: http://llvm.org/viewvc/llvm-project?rev=144998&view=rev
Log:
Add back a header file that is only used if GCC was built
with checking enabled.  Change things so that it is used
if LLVM was built with checking enabled.

Modified:
    dragonegg/trunk/src/Backend.cpp

Modified: dragonegg/trunk/src/Backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=144998&r1=144997&r2=144998&view=diff
==============================================================================
--- dragonegg/trunk/src/Backend.cpp (original)
+++ dragonegg/trunk/src/Backend.cpp Sat Nov 19 08:46:04 2011
@@ -35,6 +35,7 @@
 #include "llvm/Module.h"
 #include "llvm/PassManager.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/Analysis/Verifier.h"
 #include "llvm/Assembly/PrintModulePass.h"
 #include "llvm/Bitcode/ReaderWriter.h"
 #include "llvm/CodeGen/RegAllocRegistry.h"
@@ -579,7 +580,7 @@
   PerFunctionPasses = new FunctionPassManager(TheModule);
   PerFunctionPasses->add(new TargetData(TheModule));
 
-#ifdef ENABLE_CHECKING
+#ifndef NDEBUG
   PerFunctionPasses->add(createVerifierPass());
 #endif
 
@@ -1032,7 +1033,7 @@
   if (Value *V = get_decl_llvm(decl))
     return V;
 
-#ifdef ENABLE_CHECKING
+#ifndef NDEBUG
   // Check that we are not being given an automatic variable or a type or label.
   // A weak alias has TREE_PUBLIC set but not the other bits.
   if (TREE_CODE(decl) == PARM_DECL || TREE_CODE(decl) == RESULT_DECL ||



From craig.topper at gmail.com  Sat Nov 19 10:33:28 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sat, 19 Nov 2011 08:33:28 -0800
Subject: [llvm-commits] [llvm] r144989 - in /llvm/trunk/lib/Target/X86:
 X86ISelLowering.cpp X86ISelLowering.h X86InstrFragmentsSIMD.td
 X86InstrSSE.td
In-Reply-To: <4EC7B38D.6090706@free.fr>
References: <20111119090241.2748F2A6C133@llvm.org> <4EC7B38D.6090706@free.fr>
Message-ID: <CAF7ks-M0zpfSpS4nOU_vk6jwA451shF+Q=w72+nS4nvsM75OUA@mail.gmail.com>

Test case is in r144990. I forgot to add the file in the first commit.

~Craig

On Sat, Nov 19, 2011 at 5:47 AM, Duncan Sands <baldrick at free.fr> wrote:

> Hi Craig,
>
> > Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions
> from add/sub of appropriate shuffle vectors.
>
> testcase?
>
> Ciao, Duncan.
>
> >
> > Modified:
> >      llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> >      llvm/trunk/lib/Target/X86/X86ISelLowering.h
> >      llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> >      llvm/trunk/lib/Target/X86/X86InstrSSE.td
> >
> > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144989&r1=144988&r2=144989&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 19 03:02:40
> 2011
> > @@ -14670,7 +14670,24 @@
> >                        DAG.getConstant(0, OtherVal.getValueType()),
> NewCmp);
> >   }
> >
> > -static SDValue PerformSubCombine(SDNode *N, SelectionDAG&DAG) {
> > +/// PerformADDCombine - Do target-specific dag combines on integer adds.
> > +static SDValue PerformAddCombine(SDNode *N, SelectionDAG&DAG,
> > +                                 const X86Subtarget *Subtarget) {
> > +  EVT VT = N->getValueType(0);
> > +  SDValue Op0 = N->getOperand(0);
> > +  SDValue Op1 = N->getOperand(1);
> > +
> > +  // Try to synthesize horizontal adds from adds of shuffles.
> > +  if ((Subtarget->hasSSSE3() || Subtarget->hasAVX())&&
> > +      (VT == MVT::v8i16 || VT == MVT::v4i32)&&
> > +      isHorizontalBinOp(Op0, Op1, true))
> > +    return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
> > +
> > +  return OptimizeConditionalInDecrement(N, DAG);
> > +}
> > +
> > +static SDValue PerformSubCombine(SDNode *N, SelectionDAG&DAG,
> > +                                 const X86Subtarget *Subtarget) {
> >     SDValue Op0 = N->getOperand(0);
> >     SDValue Op1 = N->getOperand(1);
> >
> > @@ -14692,6 +14709,13 @@
> >       }
> >     }
> >
> > +  // Try to synthesize horizontal adds from adds of shuffles.
> > +  EVT VT = N->getValueType(0);
> > +  if ((Subtarget->hasSSSE3() || Subtarget->hasAVX())&&
> > +      (VT == MVT::v8i16 || VT == MVT::v4i32)&&
> > +      isHorizontalBinOp(Op0, Op1, false))
> > +    return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
> > +
> >     return OptimizeConditionalInDecrement(N, DAG);
> >   }
> >
> > @@ -14705,8 +14729,8 @@
> >     case ISD::VSELECT:
> >     case ISD::SELECT:         return PerformSELECTCombine(N, DAG,
> Subtarget);
> >     case X86ISD::CMOV:        return PerformCMOVCombine(N, DAG, DCI);
> > -  case ISD::ADD:            return OptimizeConditionalInDecrement(N,
> DAG);
> > -  case ISD::SUB:            return PerformSubCombine(N, DAG);
> > +  case ISD::ADD:            return PerformAddCombine(N, DAG, Subtarget);
> > +  case ISD::SUB:            return PerformSubCombine(N, DAG, Subtarget);
> >     case X86ISD::ADC:         return PerformADCCombine(N, DAG, DCI);
> >     case ISD::MUL:            return PerformMulCombine(N, DAG, DCI);
> >     case ISD::SHL:
> >
> > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=144989&r1=144988&r2=144989&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sat Nov 19 03:02:40 2011
> > @@ -178,6 +178,12 @@
> >         /// BLEND family of opcodes
> >         BLENDV,
> >
> > +      /// HADD - Integer horizontal add.
> > +      HADD,
> > +
> > +      /// HSUB - Integer horizontal sub.
> > +      HSUB,
> > +
> >         /// FHADD - Floating point horizontal add.
> >         FHADD,
> >
> >
> > Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=144989&r1=144988&r2=144989&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
> > +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Sat Nov 19
> 03:02:40 2011
> > @@ -41,6 +41,8 @@
> >   def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
> >   def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
> >   def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
> > +def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
> > +def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
> >   def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
> >   def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
> >   def X86cmpss   : SDNode<"X86ISD::FSETCCss",    SDTX86Cmpss>;
> >
> > Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144989&r1=144988&r2=144989&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> > +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 03:02:40 2011
> > @@ -5369,6 +5369,15 @@
> >               (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
> >     def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
> >               (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
> > +
> > +  def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
> > +            (PHADDWrr128 VR128:$src1, VR128:$src2)>;
> > +  def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
> > +            (PHADDDrr128 VR128:$src1, VR128:$src2)>;
> > +  def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
> > +            (PHSUBWrr128 VR128:$src1, VR128:$src2)>;
> > +  def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
> > +            (PHSUBDrr128 VR128:$src1, VR128:$src2)>;
> >   }
> >
> >   let Predicates = [HasAVX] in {
> > @@ -5383,6 +5392,15 @@
> >               (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
> >     def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
> >               (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
> > +
> > +  def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
> > +            (VPHADDWrr128 VR128:$src1, VR128:$src2)>;
> > +  def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
> > +            (VPHADDDrr128 VR128:$src1, VR128:$src2)>;
> > +  def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
> > +            (VPHSUBWrr128 VR128:$src1, VR128:$src2)>;
> > +  def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
> > +            (VPHSUBDrr128 VR128:$src1, VR128:$src2)>;
> >   }
> >
> >   let Predicates = [HasAVX2] in {
> > @@ -5392,6 +5410,15 @@
> >               (VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
> >     def : Pat<(v8i32 (X86psign VR256:$src1, VR256:$src2)),
> >               (VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
> > +
> > +  def : Pat<(v16i16 (X86hadd VR256:$src1, VR256:$src2)),
> > +            (VPHADDWrr256 VR256:$src1, VR256:$src2)>;
> > +  def : Pat<(v8i32 (X86hadd VR256:$src1, VR256:$src2)),
> > +            (VPHADDDrr256 VR256:$src1, VR256:$src2)>;
> > +  def : Pat<(v16i16 (X86hsub VR256:$src1, VR256:$src2)),
> > +            (VPHSUBWrr256 VR256:$src1, VR256:$src2)>;
> > +  def : Pat<(v8i32 (X86hsub VR256:$src1, VR256:$src2)),
> > +            (VPHSUBDrr256 VR256:$src1, VR256:$src2)>;
> >   }
> >
> >
> //===---------------------------------------------------------------------===//
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
~Craig
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From craig.topper at gmail.com  Sat Nov 19 11:46:46 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sat, 19 Nov 2011 17:46:46 -0000
Subject: [llvm-commits] [llvm] r144999 - in /llvm/trunk/lib/Target/X86:
 X86ISelLowering.cpp X86InstrSSE.td
Message-ID: <20111119174646.C54202A6C134@llvm.org>

Author: ctopper
Date: Sat Nov 19 11:46:46 2011
New Revision: 144999

URL: http://llvm.org/viewvc/llvm-project?rev=144999&view=rev
Log:
Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=144999&r1=144998&r2=144999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 19 11:46:46 2011
@@ -9515,6 +9515,23 @@
   case Intrinsic::x86_avx_hsub_pd_256:
     return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
                        Op.getOperand(1), Op.getOperand(2));
+  case Intrinsic::x86_avx2_psllv_d:
+  case Intrinsic::x86_avx2_psllv_q:
+  case Intrinsic::x86_avx2_psllv_d_256:
+  case Intrinsic::x86_avx2_psllv_q_256:
+    return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
+                      Op.getOperand(1), Op.getOperand(2));
+  case Intrinsic::x86_avx2_psrlv_d:
+  case Intrinsic::x86_avx2_psrlv_q:
+  case Intrinsic::x86_avx2_psrlv_d_256:
+  case Intrinsic::x86_avx2_psrlv_q_256:
+    return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
+                      Op.getOperand(1), Op.getOperand(2));
+  case Intrinsic::x86_avx2_psrav_d:
+  case Intrinsic::x86_avx2_psrav_d_256:
+    return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
+                      Op.getOperand(1), Op.getOperand(2));
+
   // ptest and testp intrinsics. The intrinsic these come from are designed to
   // return an integer value, not just an instruction so lower it to the ptest
   // or testp pattern and a setcc for the result.

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=144999&r1=144998&r2=144999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 11:46:46 2011
@@ -7741,111 +7741,62 @@
 //===----------------------------------------------------------------------===//
 // Variable Bit Shifts
 //
-multiclass avx2_var_shift<bits<8> opc, string OpcodeStr,
-                          Intrinsic Int128, Intrinsic Int256> {
+multiclass avx2_var_shift_i32<bits<8> opc, string OpcodeStr, SDNode OpNode> {
   def rr  : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
              (ins VR128:$src1, VR128:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2))]>, VEX_4V;
+             [(set VR128:$dst,
+               (v4i32 (OpNode VR128:$src1, (v4i32 VR128:$src2))))]>,
+             VEX_4V;
   def rm  : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
              (ins VR128:$src1, i128mem:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
              [(set VR128:$dst,
-              (Int128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>,
-             VEX_4V;
+               (v4i32 (OpNode VR128:$src1,
+                       (bc_v4i32 (memopv2i64 addr:$src2)))))]>, VEX_4V;
   def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
              (ins VR256:$src1, VR256:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2))]>, VEX_4V;
+             [(set VR256:$dst,
+               (v8i32 (OpNode VR256:$src1, (v8i32 VR256:$src2))))]>,
+             VEX_4V;
   def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
              (ins VR256:$src1, i256mem:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
              [(set VR256:$dst,
-               (Int256 VR256:$src1, (bitconvert (memopv4i64 addr:$src2))))]>,
-             VEX_4V;
+               (v8i32 (OpNode VR256:$src1,
+                       (bc_v8i32 (memopv4i64 addr:$src2)))))]>, VEX_4V;
 }
 
-multiclass avx2_var_shift_i64<bits<8> opc, string OpcodeStr,
-                              Intrinsic Int128, Intrinsic Int256> {
+multiclass avx2_var_shift_i64<bits<8> opc, string OpcodeStr, SDNode OpNode> {
   def rr  : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
              (ins VR128:$src1, VR128:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2))]>, VEX_4V;
+             [(set VR128:$dst,
+               (v2i64 (OpNode VR128:$src1, (v2i64 VR128:$src2))))]>,
+             VEX_4V;
   def rm  : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
              (ins VR128:$src1, i128mem:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
              [(set VR128:$dst,
-              (Int128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
+               (v2i64 (OpNode VR128:$src1, (memopv2i64 addr:$src2))))]>,
              VEX_4V;
   def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
              (ins VR256:$src1, VR256:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2))]>, VEX_4V;
+             [(set VR256:$dst,
+               (v4i64 (OpNode VR256:$src1, (v4i64 VR256:$src2))))]>,
+             VEX_4V;
   def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
              (ins VR256:$src1, i256mem:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
              [(set VR256:$dst,
-               (Int256 VR256:$src1, (memopv4i64 addr:$src2)))]>,
+               (v4i64 (OpNode VR256:$src1, (memopv4i64 addr:$src2))))]>,
              VEX_4V;
 }
 
-defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", int_x86_avx2_psllv_d,
-                              int_x86_avx2_psllv_d_256>;
-defm VPSLLVQ : avx2_var_shift_i64<0x47, "vpsllvq", int_x86_avx2_psllv_q,
-                                  int_x86_avx2_psllv_q_256>, VEX_W;
-defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", int_x86_avx2_psrlv_d,
-                              int_x86_avx2_psrlv_d_256>;
-defm VPSRLVQ : avx2_var_shift_i64<0x45, "vpsrlvq", int_x86_avx2_psrlv_q,
-                                  int_x86_avx2_psrlv_q_256>, VEX_W;
-defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", int_x86_avx2_psrav_d,
-                              int_x86_avx2_psrav_d_256>;
-
-let Predicates = [HasAVX2] in {
-  def : Pat<(v4i32 (shl (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
-            (VPSLLVDrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (v2i64 VR128:$src2))),
-            (VPSLLVQrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4i32 (srl (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
-            (VPSRLVDrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (v2i64 VR128:$src2))),
-            (VPSRLVQrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4i32 (sra (v4i32 VR128:$src1), (v4i32 VR128:$src2))),
-            (VPSRAVDrr VR128:$src1, VR128:$src2)>;
-  def : Pat<(v8i32 (shl (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
-            (VPSLLVDYrr VR256:$src1, VR256:$src2)>;
-  def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (v4i64 VR256:$src2))),
-            (VPSLLVQYrr VR256:$src1, VR256:$src2)>;
-  def : Pat<(v8i32 (srl (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
-            (VPSRLVDYrr VR256:$src1, VR256:$src2)>;
-  def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (v4i64 VR256:$src2))),
-            (VPSRLVQYrr VR256:$src1, VR256:$src2)>;
-  def : Pat<(v8i32 (sra (v8i32 VR256:$src1), (v8i32 VR256:$src2))),
-            (VPSRAVDYrr VR256:$src1, VR256:$src2)>;
-
-  def : Pat<(v4i32 (shl (v4i32 VR128:$src1),
-                    (bc_v4i32 (memopv2i64 addr:$src2)))),
-            (VPSLLVDrm VR128:$src1,  addr:$src2)>;
-  def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))),
-            (VPSLLVQrm VR128:$src1,  addr:$src2)>;
-  def : Pat<(v4i32 (srl (v4i32 VR128:$src1),
-                    (bc_v4i32 (memopv2i64 addr:$src2)))),
-            (VPSRLVDrm VR128:$src1,  addr:$src2)>;
-  def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))),
-            (VPSRLVQrm VR128:$src1,  addr:$src2)>;
-  def : Pat<(v4i32 (sra (v4i32 VR128:$src1),
-                    (bc_v4i32 (memopv2i64 addr:$src2)))),
-            (VPSRAVDrm VR128:$src1,  addr:$src2)>;
-  def : Pat<(v8i32 (shl (v8i32 VR256:$src1),
-                    (bc_v8i32 (memopv4i64 addr:$src2)))),
-            (VPSLLVDYrm VR256:$src1, addr:$src2)>;
-  def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))),
-            (VPSLLVQYrm VR256:$src1, addr:$src2)>;
-  def : Pat<(v8i32 (srl (v8i32 VR256:$src1),
-                    (bc_v8i32 (memopv4i64 addr:$src2)))),
-            (VPSRLVDYrm VR256:$src1, addr:$src2)>;
-  def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))),
-            (VPSRLVQYrm VR256:$src1, addr:$src2)>;
-  def : Pat<(v8i32 (sra (v8i32 VR256:$src1),
-                    (bc_v8i32 (memopv4i64 addr:$src2)))),
-            (VPSRAVDYrm VR256:$src1, addr:$src2)>;
-}
+defm VPSLLVD : avx2_var_shift_i32<0x47, "vpsllvd", shl>;
+defm VPSLLVQ : avx2_var_shift_i64<0x47, "vpsllvq", shl>, VEX_W;
+defm VPSRLVD : avx2_var_shift_i32<0x45, "vpsrlvd", srl>;
+defm VPSRLVQ : avx2_var_shift_i64<0x45, "vpsrlvq", srl>, VEX_W;
+defm VPSRAVD : avx2_var_shift_i32<0x46, "vpsravd", sra>;



From rafael.espindola at gmail.com  Sat Nov 19 13:46:35 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Sat, 19 Nov 2011 11:46:35 -0800
Subject: [llvm-commits] arm mc: fix relocation of an alias to an alias
In-Reply-To: <CAOei5Rd1adR_iJ5rqZdA=T7k4HSG3OFnwXw9Mi6UV6Y=FCrm7A@mail.gmail.com>
References: <CAOei5RcgpmebdoG-=msLNtH7ezDxcpJtEXywTSVxwThiknroDA@mail.gmail.com>
	<8AE16CFC-D9D4-431B-9716-C8493971AEF0@apple.com>
	<CAOei5RdiS-ZC11e+sQhtZavhAjTOTJg7TMXY+3sjnA3v-e0JBw@mail.gmail.com>
	<CADbEz-jynVkn26S7CHvLYrRSj+qup-fb=q0KXcBTC_U1dBWkkw@mail.gmail.com>
	<CAOei5ReBeh2NCwFL1gup8OEmDNODb8W04owatrCWjcBoMxjO+A@mail.gmail.com>
	<CA+Ov9+mBQ9hm2imKFg3PBP-B9LO8MpXkNvBs+s=Ju9PM=tPuXA@mail.gmail.com>
	<4E9F0948.9060808@gmail.com>
	<CAOei5Rd1adR_iJ5rqZdA=T7k4HSG3OFnwXw9Mi6UV6Y=FCrm7A@mail.gmail.com>
Message-ID: <4EC8079B.6050405@gmail.com>

On 11-11-16 1:44 PM, Ivan Krasin wrote:
> Hm...
> I have not touched this issue for a while (because I had other tasks),
> but now it seems that it's fixed independently. The attached patch adds
> the test to avoid regression. It passes with llvm tip-of-tree.
> OK to commit?

If the bug was in MC, the test should go from a .s to a .o, no?

> krasin

Cheers,
Rafael


From krasin at google.com  Sat Nov 19 14:53:32 2011
From: krasin at google.com (Ivan Krasin)
Date: Sat, 19 Nov 2011 12:53:32 -0800
Subject: [llvm-commits] arm mc: fix relocation of an alias to an alias
In-Reply-To: <4EC8079B.6050405@gmail.com>
References: <CAOei5RcgpmebdoG-=msLNtH7ezDxcpJtEXywTSVxwThiknroDA@mail.gmail.com>
	<8AE16CFC-D9D4-431B-9716-C8493971AEF0@apple.com>
	<CAOei5RdiS-ZC11e+sQhtZavhAjTOTJg7TMXY+3sjnA3v-e0JBw@mail.gmail.com>
	<CADbEz-jynVkn26S7CHvLYrRSj+qup-fb=q0KXcBTC_U1dBWkkw@mail.gmail.com>
	<CAOei5ReBeh2NCwFL1gup8OEmDNODb8W04owatrCWjcBoMxjO+A@mail.gmail.com>
	<CA+Ov9+mBQ9hm2imKFg3PBP-B9LO8MpXkNvBs+s=Ju9PM=tPuXA@mail.gmail.com>
	<4E9F0948.9060808@gmail.com>
	<CAOei5Rd1adR_iJ5rqZdA=T7k4HSG3OFnwXw9Mi6UV6Y=FCrm7A@mail.gmail.com>
	<4EC8079B.6050405@gmail.com>
Message-ID: <CAOei5RcbLqguTEteerWtnZ67op9CewP0rxsxnJEGC--jg_mW2g@mail.gmail.com>

On Sat, Nov 19, 2011 at 11:46 AM, Rafael ?vila de Esp?ndola <
rafael.espindola at gmail.com> wrote:

> On 11-11-16 1:44 PM, Ivan Krasin wrote:
>
>> Hm...
>> I have not touched this issue for a while (because I had other tasks),
>> but now it seems that it's fixed independently. The attached patch adds
>> the test to avoid regression. It passes with llvm tip-of-tree.
>> OK to commit?
>>
>
> If the bug was in MC, the test should go from a .s to a .o, no?
>
The bug was the crasher. This test at least checks that llc does not crash.

I'm fine to write .s -> .o test if you can point me to such a test case in
the tree (I didn't see them yet, sorry)

>
>  krasin
>>
>
> Cheers,
> Rafael
>
>
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From adasgupt at codeaurora.org  Fri Nov 18 22:51:30 2011
From: adasgupt at codeaurora.org (Anshuman Dasgupta)
Date: Fri, 18 Nov 2011 20:51:30 -0800
Subject: [llvm-commits] Deterministic finite automaton based packetizer for
	VLIW architectures
Message-ID: <4EC735D2.4040801@codeaurora.org>

Hi,

I'm attaching a patch that adds support for a deterministic finite 
automaton (DFA) based packetizer for VLIW architectures. Specifically, 
it automatically generates a DFA from a VLIW target's Schedule.td file. 
In a VLIW machine, an instruction can typically be dispatched to one or 
many function units. The DFA determines whether there exists a legal 
mapping of instructions to functional unit assignments in a packet. This 
DFA can then be queried by a backend packetization pass to determine 
which instructions can be grouped into a VLIW packet.

This patch contains the machine-independent code that adds a component 
to TableGen. The component autogenerates the DFA and implements the API 
that can be used to query the DFA during packetization. This can be used 
by any VLIW target to packetize its instructions. After the Hexagon 
backend is committed, I will post another Hexagon-specific patch that 
uses this mechanism to construct packets in the Hexagon backend. I ran 
the llvm test suite and this patch did not cause any regressions.

I would appreciate reviews and comments.

Thanks
-Anshu

--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

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From craig.topper at gmail.com  Sat Nov 19 15:01:55 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sat, 19 Nov 2011 21:01:55 -0000
Subject: [llvm-commits] [llvm] r145003 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20111119210155.3F0A62A6C134@llvm.org>

Author: ctopper
Date: Sat Nov 19 15:01:54 2011
New Revision: 145003

URL: http://llvm.org/viewvc/llvm-project?rev=145003&view=rev
Log:
Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=145003&r1=145002&r2=145003&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 15:01:54 2011
@@ -3423,47 +3423,6 @@
        [(set RC:$dst, (OpVT (OpNode RC:$src1,
                                      (bitconvert (memop_frag addr:$src2)))))]>;
 }
-
-/// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
-///
-/// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
-/// to collapse (bitconvert VT to VT) into its operand.
-///
-multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
-                              bit IsCommutable = 0, bit Is2Addr = 1> {
-  let isCommutable = IsCommutable in
-  def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
-       (ins VR128:$src1, VR128:$src2),
-       !if(Is2Addr,
-           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
-       [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
-  def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
-       (ins VR128:$src1, i128mem:$src2),
-       !if(Is2Addr,
-           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
-       [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
-}
-
-/// PDI_binop_rm_v4i64 - Simple AVX2 binary operator whose type is v4i64.
-///
-/// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
-/// to collapse (bitconvert VT to VT) into its operand.
-///
-multiclass PDI_binop_rm_v4i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
-                              bit IsCommutable = 0> {
-  let isCommutable = IsCommutable in
-  def rr : PDI<opc, MRMSrcReg, (outs VR256:$dst),
-       (ins VR256:$src1, VR256:$src2),
-       !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-       [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))]>;
-  def rm : PDI<opc, MRMSrcMem, (outs VR256:$dst),
-       (ins VR256:$src1, i256mem:$src2),
-       !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-       [(set VR256:$dst, (OpNode VR256:$src1, (memopv4i64 addr:$src2)))]>;
-}
-
 } // ExeDomain = SSEPackedInt
 
 // 128-bit Integer Arithmetic
@@ -3475,7 +3434,8 @@
                             i128mem, 1, 0>, VEX_4V;
 defm VPADDD  : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
                             i128mem, 1, 0>, VEX_4V;
-defm VPADDQ  : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
+defm VPADDQ  : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
+                            i128mem, 1, 0>, VEX_4V;
 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
                             i128mem, 1, 0>, VEX_4V;
 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
@@ -3484,7 +3444,8 @@
                             i128mem, 0, 0>, VEX_4V;
 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
                             i128mem, 0, 0>, VEX_4V;
-defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
+defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
+                            i128mem, 0, 0>, VEX_4V;
 
 // Intrinsic forms
 defm VPSUBSB  : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
@@ -3529,21 +3490,23 @@
 
 let Predicates = [HasAVX2] in {
 defm VPADDBY  : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
-                            i256mem, 1, 0>, VEX_4V;
+                             i256mem, 1, 0>, VEX_4V;
 defm VPADDWY  : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
-                            i256mem, 1, 0>, VEX_4V;
+                             i256mem, 1, 0>, VEX_4V;
 defm VPADDDY  : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
-                            i256mem, 1, 0>, VEX_4V;
-defm VPADDQY  : PDI_binop_rm_v4i64<0xD4, "vpaddq", add, 1>, VEX_4V;
+                             i256mem, 1, 0>, VEX_4V;
+defm VPADDQY  : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
+                             i256mem, 1, 0>, VEX_4V;
 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
-                            i256mem, 1, 0>, VEX_4V;
+                             i256mem, 1, 0>, VEX_4V;
 defm VPSUBBY  : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
-                            i256mem, 0, 0>, VEX_4V;
+                             i256mem, 0, 0>, VEX_4V;
 defm VPSUBWY  : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
-                            i256mem,  0, 0>, VEX_4V;
+                             i256mem, 0, 0>, VEX_4V;
 defm VPSUBDY  : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
-                            i256mem, 0, 0>, VEX_4V;
-defm VPSUBQY  : PDI_binop_rm_v4i64<0xFB, "vpsubq", sub, 0>, VEX_4V;
+                             i256mem, 0, 0>, VEX_4V;
+defm VPSUBQY  : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
+                             i256mem, 0, 0>, VEX_4V;
 
 // Intrinsic forms
 defm VPSUBSBY  : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
@@ -3593,7 +3556,8 @@
                            i128mem, 1>;
 defm PADDD  : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
                            i128mem, 1>;
-defm PADDQ  : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
+defm PADDQ  : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
+                           i128mem, 1>;
 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
                            i128mem, 1>;
 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
@@ -3602,7 +3566,8 @@
                           i128mem>;
 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
                           i128mem>;
-defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
+defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
+                          i128mem>;
 
 // Intrinsic forms
 defm PSUBSB  : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
@@ -3678,9 +3643,12 @@
                                 int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
                                 VR128, 0>, VEX_4V;
 
-defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
-defm VPOR  : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
-defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
+defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
+                          i128mem, 1, 0>, VEX_4V;
+defm VPOR  : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
+                          i128mem, 1, 0>, VEX_4V;
+defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
+                          i128mem, 1, 0>, VEX_4V;
 
 let ExeDomain = SSEPackedInt in {
   let neverHasSideEffects = 1 in {
@@ -3737,9 +3705,12 @@
                                  int_x86_avx2_psra_d, int_x86_avx2_psrai_d,
                                  VR256, 0>, VEX_4V;
 
-defm VPANDY : PDI_binop_rm_v4i64<0xDB, "vpand", and, 1>, VEX_4V;
-defm VPORY  : PDI_binop_rm_v4i64<0xEB, "vpor" , or, 1>, VEX_4V;
-defm VPXORY : PDI_binop_rm_v4i64<0xEF, "vpxor", xor, 1>, VEX_4V;
+defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
+                           i256mem, 1, 0>, VEX_4V;
+defm VPORY  : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
+                           i256mem, 1, 0>, VEX_4V;
+defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
+                           i256mem, 1, 0>, VEX_4V;
 
 let ExeDomain = SSEPackedInt in {
   let neverHasSideEffects = 1 in {
@@ -3796,9 +3767,12 @@
                                int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
                                VR128>;
 
-defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
-defm POR  : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
-defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
+defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
+                         i128mem, 1>;
+defm POR  : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
+                         i128mem, 1>;
+defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
+                         i128mem, 1>;
 
 let ExeDomain = SSEPackedInt in {
   let neverHasSideEffects = 1 in {
@@ -7741,62 +7715,38 @@
 //===----------------------------------------------------------------------===//
 // Variable Bit Shifts
 //
-multiclass avx2_var_shift_i32<bits<8> opc, string OpcodeStr, SDNode OpNode> {
-  def rr  : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
-             (ins VR128:$src1, VR128:$src2),
-             !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             [(set VR128:$dst,
-               (v4i32 (OpNode VR128:$src1, (v4i32 VR128:$src2))))]>,
-             VEX_4V;
-  def rm  : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
-             (ins VR128:$src1, i128mem:$src2),
-             !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             [(set VR128:$dst,
-               (v4i32 (OpNode VR128:$src1,
-                       (bc_v4i32 (memopv2i64 addr:$src2)))))]>, VEX_4V;
-  def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
-             (ins VR256:$src1, VR256:$src2),
-             !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             [(set VR256:$dst,
-               (v8i32 (OpNode VR256:$src1, (v8i32 VR256:$src2))))]>,
-             VEX_4V;
-  def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
-             (ins VR256:$src1, i256mem:$src2),
-             !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
-             [(set VR256:$dst,
-               (v8i32 (OpNode VR256:$src1,
-                       (bc_v8i32 (memopv4i64 addr:$src2)))))]>, VEX_4V;
-}
-
-multiclass avx2_var_shift_i64<bits<8> opc, string OpcodeStr, SDNode OpNode> {
+multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
+                          ValueType vt128, ValueType vt256> {
   def rr  : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
              (ins VR128:$src1, VR128:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
              [(set VR128:$dst,
-               (v2i64 (OpNode VR128:$src1, (v2i64 VR128:$src2))))]>,
+               (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
              VEX_4V;
   def rm  : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
              (ins VR128:$src1, i128mem:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
              [(set VR128:$dst,
-               (v2i64 (OpNode VR128:$src1, (memopv2i64 addr:$src2))))]>,
+               (vt128 (OpNode VR128:$src1,
+                       (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
              VEX_4V;
   def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
              (ins VR256:$src1, VR256:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
              [(set VR256:$dst,
-               (v4i64 (OpNode VR256:$src1, (v4i64 VR256:$src2))))]>,
+               (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
              VEX_4V;
   def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
              (ins VR256:$src1, i256mem:$src2),
              !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
              [(set VR256:$dst,
-               (v4i64 (OpNode VR256:$src1, (memopv4i64 addr:$src2))))]>,
+               (vt256 (OpNode VR256:$src1,
+                       (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
              VEX_4V;
 }
 
-defm VPSLLVD : avx2_var_shift_i32<0x47, "vpsllvd", shl>;
-defm VPSLLVQ : avx2_var_shift_i64<0x47, "vpsllvq", shl>, VEX_W;
-defm VPSRLVD : avx2_var_shift_i32<0x45, "vpsrlvd", srl>;
-defm VPSRLVQ : avx2_var_shift_i64<0x45, "vpsrlvq", srl>, VEX_W;
-defm VPSRAVD : avx2_var_shift_i32<0x46, "vpsravd", sra>;
+defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
+defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
+defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
+defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
+defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;



From craig.topper at gmail.com  Sat Nov 19 16:34:59 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sat, 19 Nov 2011 22:34:59 -0000
Subject: [llvm-commits] [llvm] r145004 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrInfo.cpp
 lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86MCInstLower.cpp
 test/CodeGen/X86/avx2-logic.ll
Message-ID: <20111119223459.CA1C02A6C134@llvm.org>

Author: ctopper
Date: Sat Nov 19 16:34:59 2011
New Revision: 145004

URL: http://llvm.org/viewvc/llvm-project?rev=145004&view=rev
Log:
Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
    llvm/trunk/test/CodeGen/X86/avx2-logic.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145004&r1=145003&r2=145004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 19 16:34:59 2011
@@ -4387,23 +4387,30 @@
 }
 
 /// getOnesVector - Returns a vector of specified type with all bits set.
-/// Always build ones vectors as <4 x i32>. For 256-bit types, use two
-/// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
-/// original type, ensuring they get CSE'd.
-static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
+/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
+/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
+/// Then bitcast to their original type, ensuring they get CSE'd.
+static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
+                             DebugLoc dl) {
   assert(VT.isVector() && "Expected a vector type");
   assert((VT.is128BitVector() || VT.is256BitVector())
          && "Expected a 128-bit or 256-bit vector type");
 
   SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
-  SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
-                            Cst, Cst, Cst, Cst);
-
-  if (VT.is256BitVector()) {
-    SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
-                              Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
-    Vec = Insert128BitVector(InsV, Vec,
-                  DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
+  SDValue Vec;
+  if (VT.getSizeInBits() == 256) {
+    if (HasAVX2) { // AVX2
+      SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
+      Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
+    } else { // AVX
+      Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
+      SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
+                                Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
+      Vec = Insert128BitVector(InsV, Vec,
+                    DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
+    }
+  } else {
+    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
   }
 
   return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
@@ -5221,12 +5228,14 @@
   }
 
   // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
-  // vectors or broken into v4i32 operations on 256-bit vectors.
+  // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
+  // vpcmpeqd on 256-bit vectors.
   if (ISD::isBuildVectorAllOnes(Op.getNode())) {
-    if (Op.getValueType() == MVT::v4i32)
+    if (Op.getValueType() == MVT::v4i32 ||
+        (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2()))
       return Op;
 
-    return getOnesVector(Op.getValueType(), DAG, dl);
+    return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl);
   }
 
   SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=145004&r1=145003&r2=145004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Nov 19 16:34:59 2011
@@ -2902,6 +2902,7 @@
     switch (LoadMI->getOpcode()) {
     case X86::AVX_SET0PSY:
     case X86::AVX_SET0PDY:
+    case X86::AVX2_SETALLONES:
       Alignment = 32;
       break;
     case X86::V_SET0:
@@ -2947,6 +2948,7 @@
   case X86::AVX_SET0PSY:
   case X86::AVX_SET0PDY:
   case X86::AVX_SETALLONES:
+  case X86::AVX2_SETALLONES:
   case X86::FsFLD0SD:
   case X86::FsFLD0SS:
   case X86::VFsFLD0SD:
@@ -2985,7 +2987,8 @@
     else
       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
 
-    bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES);
+    bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES ||
+                      Opc == X86::AVX2_SETALLONES);
     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
                                     Constant::getNullValue(Ty);
     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=145004&r1=145003&r2=145004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 16:34:59 2011
@@ -318,6 +318,10 @@
     isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
   def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
                          [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
+let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
+    isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX2] in
+  def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
+                          [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
 
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=145004&r1=145003&r2=145004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Sat Nov 19 16:34:59 2011
@@ -376,6 +376,7 @@
   case X86::AVX_SET0PSY:   LowerUnaryToTwoAddr(OutMI, X86::VXORPSYrr); break;
   case X86::AVX_SET0PDY:   LowerUnaryToTwoAddr(OutMI, X86::VXORPDYrr); break;
   case X86::AVX_SETALLONES:  LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDrr); break;
+  case X86::AVX2_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDYrr);break;
 
   case X86::MOV16r0:
     LowerSubReg32_Op0(OutMI, X86::MOV32r0);   // MOV16r0 -> MOV32r0

Modified: llvm/trunk/test/CodeGen/X86/avx2-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-logic.ll?rev=145004&r1=145003&r2=145004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-logic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-logic.ll Sat Nov 19 16:34:59 2011
@@ -82,3 +82,15 @@
   %cond = or <8 x i32> %1, %2
   ret <8 x i32> %cond
 }
+
+define <8 x i32> @allOnes() nounwind {
+; CHECK: vpcmpeqd
+; CHECK-NOT: vinsert
+        ret <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+}
+
+define <16 x i16> @allOnes2() nounwind {
+; CHECK: vpcmpeqd
+; CHECK-NOT: vinsert
+        ret <16 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+}



From craig.topper at gmail.com  Sat Nov 19 18:12:06 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sun, 20 Nov 2011 00:12:06 -0000
Subject: [llvm-commits] [llvm] r145005 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td
 test/CodeGen/X86/avx2-shift.ll
Message-ID: <20111120001206.35BB12A6C134@llvm.org>

Author: ctopper
Date: Sat Nov 19 18:12:05 2011
New Revision: 145005

URL: http://llvm.org/viewvc/llvm-project?rev=145005&view=rev
Log:
Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/avx2-shift.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145005&r1=145004&r2=145005&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 19 18:12:05 2011
@@ -10338,47 +10338,48 @@
         return Res;
       }
 
-      if (Subtarget->hasAVX2()) {
-        if (VT == MVT::v4i64 && Op.getOpcode() == ISD::SHL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SHL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SHL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v4i64 && Op.getOpcode() == ISD::SRL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SRL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SRL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SRA)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SRA)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
+      if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
+        if (Op.getOpcode() == ISD::SHL) {
+          // Make a large shift.
+          SDValue SHL =
+            DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+                        DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
+                        R, DAG.getConstant(ShiftAmt, MVT::i32));
+          // Zero out the rightmost bits.
+          SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt),
+                                                         MVT::i8));
+          return DAG.getNode(ISD::AND, dl, VT, SHL,
+                             DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
         }
+        if (Op.getOpcode() == ISD::SRL) {
+          // Make a large shift.
+          SDValue SRL =
+            DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+                        DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
+                        R, DAG.getConstant(ShiftAmt, MVT::i32));
+          // Zero out the leftmost bits.
+          SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
+                                                         MVT::i8));
+          return DAG.getNode(ISD::AND, dl, VT, SRL,
+                             DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
+        }
+        if (Op.getOpcode() == ISD::SRA) {
+          if (ShiftAmt == 7) {
+            // R s>> 7  ===  R s< 0
+            SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
+            return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
+          }
+
+          // R s>> a === ((R u>> a) ^ m) - m
+          SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
+          SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
+                                                         MVT::i8));
+          SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
+          Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
+          Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
+          return Res;
+        }
+      }
     }
   }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=145005&r1=145004&r2=145005&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 18:12:05 2011
@@ -311,17 +311,16 @@
 // JIT implementation, it does not expand the instructions below like
 // X86MCInstLower does.
 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
-    isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
+    isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
   def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
                          [(set VR128:$dst, (v4i32 immAllOnesV))]>;
-let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
-    isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
+  let Predicates = [HasAVX] in
   def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
                          [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
-let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
-    isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX2] in
+  let Predicates = [HasAVX2] in
   def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
                           [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
+}
 
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/test/CodeGen/X86/avx2-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-shift.ll?rev=145005&r1=145004&r2=145005&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-shift.ll Sat Nov 19 18:12:05 2011
@@ -58,14 +58,14 @@
 }
 
 ; CHECK: variable_sra0
-; CHECK: psravd
+; CHECK: vpsravd
 ; CHECK: ret
 define <4 x i32> @variable_sra0(<4 x i32> %x, <4 x i32> %y) {
   %k = ashr <4 x i32> %x, %y
   ret <4 x i32> %k
 }
 ; CHECK: variable_sra1
-; CHECK: psravd
+; CHECK: vpsravd
 ; CHECK: ret
 define <8 x i32> @variable_sra1(<8 x i32> %x, <8 x i32> %y) {
   %k = ashr <8 x i32> %x, %y
@@ -127,7 +127,7 @@
 }
 
 ; CHECK: variable_sra0_load
-; CHECK: psravd (%
+; CHECK: vpsravd (%
 ; CHECK: ret
 define <4 x i32> @variable_sra0_load(<4 x i32> %x, <4 x i32>* %y) {
   %y1 = load <4 x i32>* %y
@@ -136,7 +136,7 @@
 }
 
 ; CHECK: variable_sra1_load
-; CHECK: psravd (%
+; CHECK: vpsravd (%
 ; CHECK: ret
 define <8 x i32> @variable_sra1_load(<8 x i32> %x, <8 x i32>* %y) {
   %y1 = load <8 x i32>* %y
@@ -145,7 +145,7 @@
 }
 
 ; CHECK: variable_shl0_load
-; CHECK: psllvd (%
+; CHECK: vpsllvd (%
 ; CHECK: ret
 define <4 x i32> @variable_shl0_load(<4 x i32> %x, <4 x i32>* %y) {
   %y1 = load <4 x i32>* %y
@@ -153,7 +153,7 @@
   ret <4 x i32> %k
 }
 ; CHECK: variable_shl1_load
-; CHECK: psllvd (%
+; CHECK: vpsllvd (%
 ; CHECK: ret
 define <8 x i32> @variable_shl1_load(<8 x i32> %x, <8 x i32>* %y) {
   %y1 = load <8 x i32>* %y
@@ -161,7 +161,7 @@
   ret <8 x i32> %k
 }
 ; CHECK: variable_shl2_load
-; CHECK: psllvq (%
+; CHECK: vpsllvq (%
 ; CHECK: ret
 define <2 x i64> @variable_shl2_load(<2 x i64> %x, <2 x i64>* %y) {
   %y1 = load <2 x i64>* %y
@@ -169,7 +169,7 @@
   ret <2 x i64> %k
 }
 ; CHECK: variable_shl3_load
-; CHECK: psllvq (%
+; CHECK: vpsllvq (%
 ; CHECK: ret
 define <4 x i64> @variable_shl3_load(<4 x i64> %x, <4 x i64>* %y) {
   %y1 = load <4 x i64>* %y
@@ -177,7 +177,7 @@
   ret <4 x i64> %k
 }
 ; CHECK: variable_srl0_load
-; CHECK: psrlvd (%
+; CHECK: vpsrlvd (%
 ; CHECK: ret
 define <4 x i32> @variable_srl0_load(<4 x i32> %x, <4 x i32>* %y) {
   %y1 = load <4 x i32>* %y
@@ -185,7 +185,7 @@
   ret <4 x i32> %k
 }
 ; CHECK: variable_srl1_load
-; CHECK: psrlvd (%
+; CHECK: vpsrlvd (%
 ; CHECK: ret
 define <8 x i32> @variable_srl1_load(<8 x i32> %x, <8 x i32>* %y) {
   %y1 = load <8 x i32>* %y
@@ -193,7 +193,7 @@
   ret <8 x i32> %k
 }
 ; CHECK: variable_srl2_load
-; CHECK: psrlvq (%
+; CHECK: vpsrlvq (%
 ; CHECK: ret
 define <2 x i64> @variable_srl2_load(<2 x i64> %x, <2 x i64>* %y) {
   %y1 = load <2 x i64>* %y
@@ -201,10 +201,48 @@
   ret <2 x i64> %k
 }
 ; CHECK: variable_srl3_load
-; CHECK: psrlvq (%
+; CHECK: vpsrlvq (%
 ; CHECK: ret
 define <4 x i64> @variable_srl3_load(<4 x i64> %x, <4 x i64>* %y) {
   %y1 = load <4 x i64>* %y
   %k = lshr <4 x i64> %x, %y1
   ret <4 x i64> %k
 }
+
+define <32 x i8> @shl9(<32 x i8> %A) nounwind {
+  %B = shl <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <32 x i8> %B
+; CHECK: shl9:
+; CHECK: vpsllw $3
+; CHECK: vpand
+; CHECK: ret
+}
+
+define <32 x i8> @shr9(<32 x i8> %A) nounwind {
+  %B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <32 x i8> %B
+; CHECK: shr9:
+; CHECK: vpsrlw $3
+; CHECK: vpand
+; CHECK: ret
+}
+
+define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
+  %B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  ret <32 x i8> %B
+; CHECK: sra_v32i8_7:
+; CHECK: vxorps
+; CHECK: vpcmpgtb
+; CHECK: ret
+}
+
+define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
+  %B = ashr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <32 x i8> %B
+; CHECK: sra_v32i8:
+; CHECK: vpsrlw $3
+; CHECK: vpand
+; CHECK: vpxor
+; CHECK: vpsubb
+; CHECK: ret
+}



From nadav.rotem at intel.com  Sat Nov 19 19:44:41 2011
From: nadav.rotem at intel.com (Rotem, Nadav)
Date: Sun, 20 Nov 2011 03:44:41 +0200
Subject: [llvm-commits] [llvm] r145005 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td
 test/CodeGen/X86/avx2-shift.ll
In-Reply-To: <20111120001206.35BB12A6C134@llvm.org>
References: <20111120001206.35BB12A6C134@llvm.org>
Message-ID: <6594DDFF12B03D4E89690887C248699402A6891C83@hasmsx504.ger.corp.intel.com>

Craig, 

The code for handling splat-shift in the legalizer is there for a reason.  In some cases vector SIGN_EXTEND_INREG is legalized using shifts. During this process the shift amount is also legalized to a constant-pool load. It is too late to handle this case in the DAG combiner because it can't handle constant-pool loads. 

Nadav

-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Craig Topper
Sent: Saturday, November 19, 2011 19:12
To: llvm-commits at cs.uiuc.edu
Subject: [llvm-commits] [llvm] r145005 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx2-shift.ll

Author: ctopper
Date: Sat Nov 19 18:12:05 2011
New Revision: 145005

URL: http://llvm.org/viewvc/llvm-project?rev=145005&view=rev
Log:
Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/avx2-shift.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145005&r1=145004&r2=145005&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 19 18:12:05 2011
@@ -10338,47 +10338,48 @@
         return Res;
       }
 
-      if (Subtarget->hasAVX2()) {
-        if (VT == MVT::v4i64 && Op.getOpcode() == ISD::SHL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SHL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SHL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v4i64 && Op.getOpcode() == ISD::SRL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SRL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SRL)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SRA)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
-
-        if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SRA)
-         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
-                       DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32),
-                       R, DAG.getConstant(ShiftAmt, MVT::i32));
+      if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
+        if (Op.getOpcode() == ISD::SHL) {
+          // Make a large shift.
+          SDValue SHL =
+            DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+                        DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
+                        R, DAG.getConstant(ShiftAmt, MVT::i32));
+          // Zero out the rightmost bits.
+          SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt),
+                                                         MVT::i8));
+          return DAG.getNode(ISD::AND, dl, VT, SHL,
+                             DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
         }
+        if (Op.getOpcode() == ISD::SRL) {
+          // Make a large shift.
+          SDValue SRL =
+            DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+                        DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
+                        R, DAG.getConstant(ShiftAmt, MVT::i32));
+          // Zero out the leftmost bits.
+          SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
+                                                         MVT::i8));
+          return DAG.getNode(ISD::AND, dl, VT, SRL,
+                             DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
+        }
+        if (Op.getOpcode() == ISD::SRA) {
+          if (ShiftAmt == 7) {
+            // R s>> 7  ===  R s< 0
+            SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
+            return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
+          }
+
+          // R s>> a === ((R u>> a) ^ m) - m
+          SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
+          SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
+                                                         MVT::i8));
+          SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
+          Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
+          Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
+          return Res;
+        }
+      }
     }
   }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=145005&r1=145004&r2=145005&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 18:12:05 2011
@@ -311,17 +311,16 @@
 // JIT implementation, it does not expand the instructions below like
 // X86MCInstLower does.
 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
-    isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
+    isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
   def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
                          [(set VR128:$dst, (v4i32 immAllOnesV))]>;
-let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
-    isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
+  let Predicates = [HasAVX] in
   def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
                          [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
-let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
-    isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX2] in
+  let Predicates = [HasAVX2] in
   def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
                           [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
+}
 
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/test/CodeGen/X86/avx2-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-shift.ll?rev=145005&r1=145004&r2=145005&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-shift.ll Sat Nov 19 18:12:05 2011
@@ -58,14 +58,14 @@
 }
 
 ; CHECK: variable_sra0
-; CHECK: psravd
+; CHECK: vpsravd
 ; CHECK: ret
 define <4 x i32> @variable_sra0(<4 x i32> %x, <4 x i32> %y) {
   %k = ashr <4 x i32> %x, %y
   ret <4 x i32> %k
 }
 ; CHECK: variable_sra1
-; CHECK: psravd
+; CHECK: vpsravd
 ; CHECK: ret
 define <8 x i32> @variable_sra1(<8 x i32> %x, <8 x i32> %y) {
   %k = ashr <8 x i32> %x, %y
@@ -127,7 +127,7 @@
 }
 
 ; CHECK: variable_sra0_load
-; CHECK: psravd (%
+; CHECK: vpsravd (%
 ; CHECK: ret
 define <4 x i32> @variable_sra0_load(<4 x i32> %x, <4 x i32>* %y) {
   %y1 = load <4 x i32>* %y
@@ -136,7 +136,7 @@
 }
 
 ; CHECK: variable_sra1_load
-; CHECK: psravd (%
+; CHECK: vpsravd (%
 ; CHECK: ret
 define <8 x i32> @variable_sra1_load(<8 x i32> %x, <8 x i32>* %y) {
   %y1 = load <8 x i32>* %y
@@ -145,7 +145,7 @@
 }
 
 ; CHECK: variable_shl0_load
-; CHECK: psllvd (%
+; CHECK: vpsllvd (%
 ; CHECK: ret
 define <4 x i32> @variable_shl0_load(<4 x i32> %x, <4 x i32>* %y) {
   %y1 = load <4 x i32>* %y
@@ -153,7 +153,7 @@
   ret <4 x i32> %k
 }
 ; CHECK: variable_shl1_load
-; CHECK: psllvd (%
+; CHECK: vpsllvd (%
 ; CHECK: ret
 define <8 x i32> @variable_shl1_load(<8 x i32> %x, <8 x i32>* %y) {
   %y1 = load <8 x i32>* %y
@@ -161,7 +161,7 @@
   ret <8 x i32> %k
 }
 ; CHECK: variable_shl2_load
-; CHECK: psllvq (%
+; CHECK: vpsllvq (%
 ; CHECK: ret
 define <2 x i64> @variable_shl2_load(<2 x i64> %x, <2 x i64>* %y) {
   %y1 = load <2 x i64>* %y
@@ -169,7 +169,7 @@
   ret <2 x i64> %k
 }
 ; CHECK: variable_shl3_load
-; CHECK: psllvq (%
+; CHECK: vpsllvq (%
 ; CHECK: ret
 define <4 x i64> @variable_shl3_load(<4 x i64> %x, <4 x i64>* %y) {
   %y1 = load <4 x i64>* %y
@@ -177,7 +177,7 @@
   ret <4 x i64> %k
 }
 ; CHECK: variable_srl0_load
-; CHECK: psrlvd (%
+; CHECK: vpsrlvd (%
 ; CHECK: ret
 define <4 x i32> @variable_srl0_load(<4 x i32> %x, <4 x i32>* %y) {
   %y1 = load <4 x i32>* %y
@@ -185,7 +185,7 @@
   ret <4 x i32> %k
 }
 ; CHECK: variable_srl1_load
-; CHECK: psrlvd (%
+; CHECK: vpsrlvd (%
 ; CHECK: ret
 define <8 x i32> @variable_srl1_load(<8 x i32> %x, <8 x i32>* %y) {
   %y1 = load <8 x i32>* %y
@@ -193,7 +193,7 @@
   ret <8 x i32> %k
 }
 ; CHECK: variable_srl2_load
-; CHECK: psrlvq (%
+; CHECK: vpsrlvq (%
 ; CHECK: ret
 define <2 x i64> @variable_srl2_load(<2 x i64> %x, <2 x i64>* %y) {
   %y1 = load <2 x i64>* %y
@@ -201,10 +201,48 @@
   ret <2 x i64> %k
 }
 ; CHECK: variable_srl3_load
-; CHECK: psrlvq (%
+; CHECK: vpsrlvq (%
 ; CHECK: ret
 define <4 x i64> @variable_srl3_load(<4 x i64> %x, <4 x i64>* %y) {
   %y1 = load <4 x i64>* %y
   %k = lshr <4 x i64> %x, %y1
   ret <4 x i64> %k
 }
+
+define <32 x i8> @shl9(<32 x i8> %A) nounwind {
+  %B = shl <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <32 x i8> %B
+; CHECK: shl9:
+; CHECK: vpsllw $3
+; CHECK: vpand
+; CHECK: ret
+}
+
+define <32 x i8> @shr9(<32 x i8> %A) nounwind {
+  %B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <32 x i8> %B
+; CHECK: shr9:
+; CHECK: vpsrlw $3
+; CHECK: vpand
+; CHECK: ret
+}
+
+define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
+  %B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  ret <32 x i8> %B
+; CHECK: sra_v32i8_7:
+; CHECK: vxorps
+; CHECK: vpcmpgtb
+; CHECK: ret
+}
+
+define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
+  %B = ashr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <32 x i8> %B
+; CHECK: sra_v32i8:
+; CHECK: vpsrlw $3
+; CHECK: vpand
+; CHECK: vpxor
+; CHECK: vpsubb
+; CHECK: ret
+}


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From craig.topper at gmail.com  Sun Nov 20 00:04:05 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Sat, 19 Nov 2011 22:04:05 -0800
Subject: [llvm-commits] [llvm] r145005 - in /llvm/trunk:
	lib/Target/X86/X86ISelLowering.cpp
	lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx2-shift.ll
In-Reply-To: <6594DDFF12B03D4E89690887C248699402A6891C83@hasmsx504.ger.corp.intel.com>
References: <20111120001206.35BB12A6C134@llvm.org>
	<6594DDFF12B03D4E89690887C248699402A6891C83@hasmsx504.ger.corp.intel.com>
Message-ID: <28616E33-7B41-4ADD-915D-9A54D0AA4985@gmail.com>

Ok thanks. I'll restore the code. Can you tell me how to write a test case?

Sent from my iPhone

On Nov 19, 2011, at 5:44 PM, "Rotem, Nadav" <nadav.rotem at intel.com> wrote:

> Craig, 
> 
> The code for handling splat-shift in the legalizer is there for a reason.  In some cases vector SIGN_EXTEND_INREG is legalized using shifts. During this process the shift amount is also legalized to a constant-pool load. It is too late to handle this case in the DAG combiner because it can't handle constant-pool loads. 
> 
> Nadav
> 
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Craig Topper
> Sent: Saturday, November 19, 2011 19:12
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm-commits] [llvm] r145005 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx2-shift.ll
> 
> Author: ctopper
> Date: Sat Nov 19 18:12:05 2011
> New Revision: 145005
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=145005&view=rev
> Log:
> Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine.
> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>    llvm/trunk/lib/Target/X86/X86InstrSSE.td
>    llvm/trunk/test/CodeGen/X86/avx2-shift.ll
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145005&r1=145004&r2=145005&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 19 18:12:05 2011
> @@ -10338,47 +10338,48 @@
>         return Res;
>       }
> 
> -      if (Subtarget->hasAVX2()) {
> -        if (VT == MVT::v4i64 && Op.getOpcode() == ISD::SHL)
> -         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> -                       DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
> -                       R, DAG.getConstant(ShiftAmt, MVT::i32));
> -
> -        if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SHL)
> -         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> -                       DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32),
> -                       R, DAG.getConstant(ShiftAmt, MVT::i32));
> -
> -        if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SHL)
> -         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> -                       DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
> -                       R, DAG.getConstant(ShiftAmt, MVT::i32));
> -
> -        if (VT == MVT::v4i64 && Op.getOpcode() == ISD::SRL)
> -         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> -                       DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
> -                       R, DAG.getConstant(ShiftAmt, MVT::i32));
> -
> -        if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SRL)
> -         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> -                       DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32),
> -                       R, DAG.getConstant(ShiftAmt, MVT::i32));
> -
> -        if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SRL)
> -         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> -                       DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
> -                       R, DAG.getConstant(ShiftAmt, MVT::i32));
> -
> -        if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SRA)
> -         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> -                       DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32),
> -                       R, DAG.getConstant(ShiftAmt, MVT::i32));
> -
> -        if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SRA)
> -         return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> -                       DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32),
> -                       R, DAG.getConstant(ShiftAmt, MVT::i32));
> +      if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
> +        if (Op.getOpcode() == ISD::SHL) {
> +          // Make a large shift.
> +          SDValue SHL =
> +            DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> +                        DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
> +                        R, DAG.getConstant(ShiftAmt, MVT::i32));
> +          // Zero out the rightmost bits.
> +          SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt),
> +                                                         MVT::i8));
> +          return DAG.getNode(ISD::AND, dl, VT, SHL,
> +                             DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
>         }
> +        if (Op.getOpcode() == ISD::SRL) {
> +          // Make a large shift.
> +          SDValue SRL =
> +            DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
> +                        DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
> +                        R, DAG.getConstant(ShiftAmt, MVT::i32));
> +          // Zero out the leftmost bits.
> +          SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
> +                                                         MVT::i8));
> +          return DAG.getNode(ISD::AND, dl, VT, SRL,
> +                             DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
> +        }
> +        if (Op.getOpcode() == ISD::SRA) {
> +          if (ShiftAmt == 7) {
> +            // R s>> 7  ===  R s< 0
> +            SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
> +            return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
> +          }
> +
> +          // R s>> a === ((R u>> a) ^ m) - m
> +          SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
> +          SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
> +                                                         MVT::i8));
> +          SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
> +          Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
> +          Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
> +          return Res;
> +        }
> +      }
>     }
>   }
> 
> 
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=145005&r1=145004&r2=145005&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Nov 19 18:12:05 2011
> @@ -311,17 +311,16 @@
> // JIT implementation, it does not expand the instructions below like
> // X86MCInstLower does.
> let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
> -    isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
> +    isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
>   def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
>                          [(set VR128:$dst, (v4i32 immAllOnesV))]>;
> -let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
> -    isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
> +  let Predicates = [HasAVX] in
>   def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
>                          [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
> -let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
> -    isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX2] in
> +  let Predicates = [HasAVX2] in
>   def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
>                           [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
> +}
> 
> 
> //===----------------------------------------------------------------------===//
> 
> Modified: llvm/trunk/test/CodeGen/X86/avx2-shift.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-shift.ll?rev=145005&r1=145004&r2=145005&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/avx2-shift.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/avx2-shift.ll Sat Nov 19 18:12:05 2011
> @@ -58,14 +58,14 @@
> }
> 
> ; CHECK: variable_sra0
> -; CHECK: psravd
> +; CHECK: vpsravd
> ; CHECK: ret
> define <4 x i32> @variable_sra0(<4 x i32> %x, <4 x i32> %y) {
>   %k = ashr <4 x i32> %x, %y
>   ret <4 x i32> %k
> }
> ; CHECK: variable_sra1
> -; CHECK: psravd
> +; CHECK: vpsravd
> ; CHECK: ret
> define <8 x i32> @variable_sra1(<8 x i32> %x, <8 x i32> %y) {
>   %k = ashr <8 x i32> %x, %y
> @@ -127,7 +127,7 @@
> }
> 
> ; CHECK: variable_sra0_load
> -; CHECK: psravd (%
> +; CHECK: vpsravd (%
> ; CHECK: ret
> define <4 x i32> @variable_sra0_load(<4 x i32> %x, <4 x i32>* %y) {
>   %y1 = load <4 x i32>* %y
> @@ -136,7 +136,7 @@
> }
> 
> ; CHECK: variable_sra1_load
> -; CHECK: psravd (%
> +; CHECK: vpsravd (%
> ; CHECK: ret
> define <8 x i32> @variable_sra1_load(<8 x i32> %x, <8 x i32>* %y) {
>   %y1 = load <8 x i32>* %y
> @@ -145,7 +145,7 @@
> }
> 
> ; CHECK: variable_shl0_load
> -; CHECK: psllvd (%
> +; CHECK: vpsllvd (%
> ; CHECK: ret
> define <4 x i32> @variable_shl0_load(<4 x i32> %x, <4 x i32>* %y) {
>   %y1 = load <4 x i32>* %y
> @@ -153,7 +153,7 @@
>   ret <4 x i32> %k
> }
> ; CHECK: variable_shl1_load
> -; CHECK: psllvd (%
> +; CHECK: vpsllvd (%
> ; CHECK: ret
> define <8 x i32> @variable_shl1_load(<8 x i32> %x, <8 x i32>* %y) {
>   %y1 = load <8 x i32>* %y
> @@ -161,7 +161,7 @@
>   ret <8 x i32> %k
> }
> ; CHECK: variable_shl2_load
> -; CHECK: psllvq (%
> +; CHECK: vpsllvq (%
> ; CHECK: ret
> define <2 x i64> @variable_shl2_load(<2 x i64> %x, <2 x i64>* %y) {
>   %y1 = load <2 x i64>* %y
> @@ -169,7 +169,7 @@
>   ret <2 x i64> %k
> }
> ; CHECK: variable_shl3_load
> -; CHECK: psllvq (%
> +; CHECK: vpsllvq (%
> ; CHECK: ret
> define <4 x i64> @variable_shl3_load(<4 x i64> %x, <4 x i64>* %y) {
>   %y1 = load <4 x i64>* %y
> @@ -177,7 +177,7 @@
>   ret <4 x i64> %k
> }
> ; CHECK: variable_srl0_load
> -; CHECK: psrlvd (%
> +; CHECK: vpsrlvd (%
> ; CHECK: ret
> define <4 x i32> @variable_srl0_load(<4 x i32> %x, <4 x i32>* %y) {
>   %y1 = load <4 x i32>* %y
> @@ -185,7 +185,7 @@
>   ret <4 x i32> %k
> }
> ; CHECK: variable_srl1_load
> -; CHECK: psrlvd (%
> +; CHECK: vpsrlvd (%
> ; CHECK: ret
> define <8 x i32> @variable_srl1_load(<8 x i32> %x, <8 x i32>* %y) {
>   %y1 = load <8 x i32>* %y
> @@ -193,7 +193,7 @@
>   ret <8 x i32> %k
> }
> ; CHECK: variable_srl2_load
> -; CHECK: psrlvq (%
> +; CHECK: vpsrlvq (%
> ; CHECK: ret
> define <2 x i64> @variable_srl2_load(<2 x i64> %x, <2 x i64>* %y) {
>   %y1 = load <2 x i64>* %y
> @@ -201,10 +201,48 @@
>   ret <2 x i64> %k
> }
> ; CHECK: variable_srl3_load
> -; CHECK: psrlvq (%
> +; CHECK: vpsrlvq (%
> ; CHECK: ret
> define <4 x i64> @variable_srl3_load(<4 x i64> %x, <4 x i64>* %y) {
>   %y1 = load <4 x i64>* %y
>   %k = lshr <4 x i64> %x, %y1
>   ret <4 x i64> %k
> }
> +
> +define <32 x i8> @shl9(<32 x i8> %A) nounwind {
> +  %B = shl <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
> +  ret <32 x i8> %B
> +; CHECK: shl9:
> +; CHECK: vpsllw $3
> +; CHECK: vpand
> +; CHECK: ret
> +}
> +
> +define <32 x i8> @shr9(<32 x i8> %A) nounwind {
> +  %B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
> +  ret <32 x i8> %B
> +; CHECK: shr9:
> +; CHECK: vpsrlw $3
> +; CHECK: vpand
> +; CHECK: ret
> +}
> +
> +define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
> +  %B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
> +  ret <32 x i8> %B
> +; CHECK: sra_v32i8_7:
> +; CHECK: vxorps
> +; CHECK: vpcmpgtb
> +; CHECK: ret
> +}
> +
> +define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
> +  %B = ashr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
> +  ret <32 x i8> %B
> +; CHECK: sra_v32i8:
> +; CHECK: vpsrlw $3
> +; CHECK: vpand
> +; CHECK: vpxor
> +; CHECK: vpsubb
> +; CHECK: ret
> +}
> 
> 
> _______________________________________________
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> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
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> 


From chandlerc at gmail.com  Sun Nov 20 03:30:41 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Sun, 20 Nov 2011 09:30:41 -0000
Subject: [llvm-commits] [llvm] r145006 -
	/llvm/trunk/test/CodeGen/X86/block-placement.ll
Message-ID: <20111120093041.379932A6C134@llvm.org>

Author: chandlerc
Date: Sun Nov 20 03:30:40 2011
New Revision: 145006

URL: http://llvm.org/viewvc/llvm-project?rev=145006&view=rev
Log:
Add some comments to the latest test case I added here to document what
is actually being tested. Also add some FileCheck goodness to much more
carefully ensure that the result is the desired result. Before this test
would only have failed through an assert failure if the underlying fix
were reverted.

Also, add some weight metadata and a comment explaining exactly what is
going on to a trick section of the test case. Originally, we were
getting very unlucky and trying to form a block chain that isn't
actually profitable. I'm working on a fix to avoid forming these
unprofitable chains, and that would also have masked any failure from
this test case. The easy solution is to add some metadata that makes it
*really* profitable to form the bad chain here.

Modified:
    llvm/trunk/test/CodeGen/X86/block-placement.ll

Modified: llvm/trunk/test/CodeGen/X86/block-placement.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=145006&r1=145005&r2=145006&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/block-placement.ll (original)
+++ llvm/trunk/test/CodeGen/X86/block-placement.ll Sun Nov 20 03:30:40 2011
@@ -395,8 +395,27 @@
 }
 
 define void @fpcmp_unanalyzable_branch(i1 %cond) {
+; This function's CFG contains an unanalyzable branch that is likely to be
+; split due to having a different high-probability predecessor.
+; CHECK: fpcmp_unanalyzable_branch
+; CHECK: %entry
+; CHECK: %exit
+; CHECK-NOT: %if.then
+; CHECK-NOT: %if.end
+; CHECK-NOT: jne
+; CHECK-NOT: jnp
+; CHECK: jne
+; CHECK-NEXT: jnp
+; CHECK-NEXT: %if.then
+
 entry:
-  br i1 %cond, label %entry.if.then_crit_edge, label %lor.lhs.false
+; Note that this branch must be strongly biased toward
+; 'entry.if.then_crit_edge' to ensure that we would try to form a chain for
+; 'entry' -> 'entry.if.then_crit_edge' -> 'if.then'. It is the last edge in that
+; chain which would violate the unanalyzable branch in 'exit', but we won't even
+; try this trick unless 'if.then' is believed to almost always be reached from
+; 'entry.if.then_crit_edge'.
+  br i1 %cond, label %entry.if.then_crit_edge, label %lor.lhs.false, !prof !1
 
 entry.if.then_crit_edge:
   %.pre14 = load i8* undef, align 1, !tbaa !0
@@ -418,3 +437,5 @@
 if.end:
   ret void
 }
+
+!1 = metadata !{metadata !"branch_weights", i32 1000, i32 1}



From benny.kra at googlemail.com  Sun Nov 20 04:24:36 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Sun, 20 Nov 2011 10:24:36 -0000
Subject: [llvm-commits] [llvm] r145007 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20111120102436.80A652A6C134@llvm.org>

Author: d0k
Date: Sun Nov 20 04:24:36 2011
New Revision: 145007

URL: http://llvm.org/viewvc/llvm-project?rev=145007&view=rev
Log:
SCEV: Actually set overflow flags on add expressions.

setFlags doesn't modify its arguments.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=145007&r1=145006&r2=145007&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Sun Nov 20 04:24:36 2011
@@ -3601,9 +3601,9 @@
     SCEV::NoWrapFlags Flags = SCEV::FlagAnyWrap;
     OverflowingBinaryOperator *OBO = cast<OverflowingBinaryOperator>(V);
     if (OBO->hasNoSignedWrap())
-      setFlags(Flags, SCEV::FlagNSW);
+      Flags = setFlags(Flags, SCEV::FlagNSW);
     if (OBO->hasNoUnsignedWrap())
-      setFlags(Flags, SCEV::FlagNUW);
+      Flags = setFlags(Flags, SCEV::FlagNUW);
     return getAddExpr(AddOps, Flags);
   }
   case Instruction::Mul: {



From benny.kra at googlemail.com  Sun Nov 20 05:10:03 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Sun, 20 Nov 2011 11:10:03 -0000
Subject: [llvm-commits] [llvm] r145008 -
 /llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll
Message-ID: <20111120111003.BE3822A6C134@llvm.org>

Author: d0k
Date: Sun Nov 20 05:10:03 2011
New Revision: 145008

URL: http://llvm.org/viewvc/llvm-project?rev=145008&view=rev
Log:
XFAIL this test until I figure out what indvars is doing here (or find someone who does)

Modified:
    llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll

Modified: llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll?rev=145008&r1=145007&r2=145008&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/2011-09-10-widen-nsw.ll Sun Nov 20 05:10:03 2011
@@ -3,6 +3,9 @@
 ; add219 should be extended to i64 because it is nsw, even though its
 ; sext cannot be hoisted outside the loop.
 
+; FIXME: GetExtendedOperandRecurrence has problems with the nsw bit on add exprs
+; XFAIL: *
+
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 
 define void @test() nounwind {



From chandlerc at gmail.com  Sun Nov 20 05:22:03 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Sun, 20 Nov 2011 11:22:03 -0000
Subject: [llvm-commits] [llvm] r145009 -
	/llvm/trunk/include/llvm/Support/BranchProbability.h
Message-ID: <20111120112203.C7C022A6C134@llvm.org>

Author: chandlerc
Date: Sun Nov 20 05:22:03 2011
New Revision: 145009

URL: http://llvm.org/viewvc/llvm-project?rev=145009&view=rev
Log:
Make an obviously const interface actually be marked as const.

Modified:
    llvm/trunk/include/llvm/Support/BranchProbability.h

Modified: llvm/trunk/include/llvm/Support/BranchProbability.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/BranchProbability.h?rev=145009&r1=145008&r2=145009&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/BranchProbability.h (original)
+++ llvm/trunk/include/llvm/Support/BranchProbability.h Sun Nov 20 05:22:03 2011
@@ -42,7 +42,7 @@
   uint32_t getDenominator() const { return D; }
 
   // Return (1 - Probability).
-  BranchProbability getCompl() {
+  BranchProbability getCompl() const {
     return BranchProbability(D - N, D);
   }
 



From chandlerc at gmail.com  Sun Nov 20 05:22:06 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Sun, 20 Nov 2011 11:22:06 -0000
Subject: [llvm-commits] [llvm] r145010 - in /llvm/trunk:
 lib/CodeGen/MachineBlockPlacement.cpp test/CodeGen/X86/block-placement.ll
Message-ID: <20111120112206.BE6392A6C134@llvm.org>

Author: chandlerc
Date: Sun Nov 20 05:22:06 2011
New Revision: 145010

URL: http://llvm.org/viewvc/llvm-project?rev=145010&view=rev
Log:
The logic for breaking the CFG in the presence of hot successors didn't
properly account for the *global* probability of the edge being taken.
This manifested as a very large number of unconditional branches to
blocks being merged against the CFG even though they weren't
particularly hot within the CFG.

The fix is to check whether the edge being merged is both locally hot
relative to other successors for the source block, and globally hot
compared to other (unmerged) predecessors of the destination block.

This introduces a new crasher on GCC single-source, but it's currently
behind a flag, and Ben has offered to work on the reduction. =]

Modified:
    llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
    llvm/trunk/test/CodeGen/X86/block-placement.ll

Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=145010&r1=145009&r2=145010&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Sun Nov 20 05:22:06 2011
@@ -365,9 +365,35 @@
 
     // Only consider successors which are either "hot", or wouldn't violate
     // any CFG constraints.
-    if (SuccChain.LoopPredecessors != 0 && SuccProb < HotProb) {
-      DEBUG(dbgs() << "    " << getBlockName(*SI) << " -> CFG conflict\n");
-      continue;
+    if (SuccChain.LoopPredecessors != 0) {
+      if (SuccProb < HotProb) {
+        DEBUG(dbgs() << "    " << getBlockName(*SI) << " -> CFG conflict\n");
+        continue;
+      }
+
+      // Make sure that a hot successor doesn't have a globally more important
+      // predecessor.
+      BlockFrequency CandidateEdgeFreq
+        = MBFI->getBlockFreq(BB) * SuccProb * HotProb.getCompl();
+      bool BadCFGConflict = false;
+      for (MachineBasicBlock::pred_iterator PI = (*SI)->pred_begin(),
+                                            PE = (*SI)->pred_end();
+           PI != PE; ++PI) {
+        if (*PI == *SI || (BlockFilter && !BlockFilter->count(*PI)) ||
+            BlockToChain[*PI] == &Chain)
+          continue;
+        BlockFrequency PredEdgeFreq
+          = MBFI->getBlockFreq(*PI) * MBPI->getEdgeProbability(*PI, *SI);
+        if (PredEdgeFreq >= CandidateEdgeFreq) {
+          BadCFGConflict = true;
+          break;
+        }
+      }
+      if (BadCFGConflict) {
+        DEBUG(dbgs() << "    " << getBlockName(*SI)
+                               << " -> non-cold CFG conflict\n");
+        continue;
+      }
     }
 
     DEBUG(dbgs() << "    " << getBlockName(*SI) << " -> " << SuccProb

Modified: llvm/trunk/test/CodeGen/X86/block-placement.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=145010&r1=145009&r2=145010&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/block-placement.ll (original)
+++ llvm/trunk/test/CodeGen/X86/block-placement.ll Sun Nov 20 05:22:06 2011
@@ -439,3 +439,39 @@
 }
 
 !1 = metadata !{metadata !"branch_weights", i32 1000, i32 1}
+
+declare i32 @f()
+declare i32 @g()
+declare i32 @h(i32 %x)
+
+define i32 @test_global_cfg_break_profitability() {
+; Check that our metrics for the profitability of a CFG break are global rather
+; than local. A successor may be very hot, but if the current block isn't, it
+; doesn't matter. Within this test the 'then' block is slightly warmer than the
+; 'else' block, but not nearly enough to merit merging it with the exit block
+; even though the probability of 'then' branching to the 'exit' block is very
+; high.
+; CHECK: test_global_cfg_break_profitability
+; CHECK: calll f
+; CHECK: calll g
+; CHECK: calll h
+; CHECK: ret
+
+entry:
+  br i1 undef, label %then, label %else, !prof !2
+
+then:
+  %then.result = call i32 @f()
+  br label %exit
+
+else:
+  %else.result = call i32 @g()
+  br label %exit
+
+exit:
+  %result = phi i32 [ %then.result, %then ], [ %else.result, %else ]
+  %result2 = call i32 @h(i32 %result)
+  ret i32 %result
+}
+
+!2 = metadata !{metadata !"branch_weights", i32 3, i32 1}



From geek4civic at gmail.com  Sun Nov 20 06:49:45 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Sun, 20 Nov 2011 12:49:45 -0000
Subject: [llvm-commits] [llvm] r145011 -
	/llvm/trunk/test/CodeGen/X86/block-placement.ll
Message-ID: <20111120124945.772972A6C134@llvm.org>

Author: chapuni
Date: Sun Nov 20 06:49:45 2011
New Revision: 145011

URL: http://llvm.org/viewvc/llvm-project?rev=145011&view=rev
Log:
test/CodeGen/X86/block-placement.ll: Relax expressions for Win32.

Modified:
    llvm/trunk/test/CodeGen/X86/block-placement.ll

Modified: llvm/trunk/test/CodeGen/X86/block-placement.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.ll?rev=145011&r1=145010&r2=145011&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/block-placement.ll (original)
+++ llvm/trunk/test/CodeGen/X86/block-placement.ll Sun Nov 20 06:49:45 2011
@@ -452,9 +452,9 @@
 ; even though the probability of 'then' branching to the 'exit' block is very
 ; high.
 ; CHECK: test_global_cfg_break_profitability
-; CHECK: calll f
-; CHECK: calll g
-; CHECK: calll h
+; CHECK: calll {{_?}}f
+; CHECK: calll {{_?}}g
+; CHECK: calll {{_?}}h
 ; CHECK: ret
 
 entry:



From nicholas at mxc.ca  Sun Nov 20 13:09:04 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Sun, 20 Nov 2011 19:09:04 -0000
Subject: [llvm-commits] [llvm] r145013 - in /llvm/trunk:
 include/llvm/Analysis/CaptureTracking.h include/llvm/Support/CallSite.h
 lib/Analysis/BasicAliasAnalysis.cpp
 lib/Analysis/MemoryDependenceAnalysis.cpp
 lib/Transforms/InstCombine/InstCombineCalls.cpp
 lib/Transforms/Scalar/MemCpyOptimizer.cpp
 lib/Transforms/Scalar/ScalarReplAggregates.cpp
 lib/Transforms/Utils/InlineFunction.cpp
Message-ID: <20111120190905.054912A6C134@llvm.org>

Author: nicholas
Date: Sun Nov 20 13:09:04 2011
New Revision: 145013

URL: http://llvm.org/viewvc/llvm-project?rev=145013&view=rev
Log:
Refactor code to use new attribute getters on CallSite for NoCapture and ByVal.
Suggested in code review by Eli.

That code in InstCombine looks kinda suspicious.

Modified:
    llvm/trunk/include/llvm/Analysis/CaptureTracking.h
    llvm/trunk/include/llvm/Support/CallSite.h
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
    llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
    llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
    llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp
    llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
    llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp

Modified: llvm/trunk/include/llvm/Analysis/CaptureTracking.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CaptureTracking.h?rev=145013&r1=145012&r2=145013&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/CaptureTracking.h (original)
+++ llvm/trunk/include/llvm/Analysis/CaptureTracking.h Sun Nov 20 13:09:04 2011
@@ -104,7 +104,7 @@
       // (think of self-referential objects).
       CallSite::arg_iterator B = CS.arg_begin(), E = CS.arg_end();
       for (CallSite::arg_iterator A = B; A != E; ++A)
-        if (A->get() == V && !CS.paramHasAttr(A - B + 1, Attribute::NoCapture))
+        if (A->get() == V && !CS.doesNotCapture(A - B))
           // The parameter is not marked 'nocapture' - captured.
           if (Tracker.captured(I))
             return;

Modified: llvm/trunk/include/llvm/Support/CallSite.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=145013&r1=145012&r2=145013&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CallSite.h (original)
+++ llvm/trunk/include/llvm/Support/CallSite.h Sun Nov 20 13:09:04 2011
@@ -237,6 +237,16 @@
 #undef CALLSITE_DELEGATE_GETTER
 #undef CALLSITE_DELEGATE_SETTER
 
+  /// @brief Determine whether this argument is not captured.
+  bool doesNotCapture(unsigned ArgNo) const {
+    return paramHasAttr(ArgNo + 1, Attribute::NoCapture);
+  }
+
+  /// @brief Determine whether this argument is passed by value.
+  bool isByValArgument(unsigned ArgNo) const {
+    return paramHasAttr(ArgNo + 1, Attribute::ByVal);
+  }
+
   /// hasArgument - Returns true if this CallSite passes the given Value* as an
   /// argument to the called function.
   bool hasArgument(const Value *Arg) const {

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=145013&r1=145012&r2=145013&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sun Nov 20 13:09:04 2011
@@ -706,8 +706,7 @@
       // pointer were passed to arguments that were neither of these, then it
       // couldn't be no-capture.
       if (!(*CI)->getType()->isPointerTy() ||
-          (!CS.paramHasAttr(ArgNo+1, Attribute::NoCapture) &&
-           !CS.paramHasAttr(ArgNo+1, Attribute::ByVal)))
+          (!CS.doesNotCapture(ArgNo) && !CS.isByValArgument(ArgNo)))
         continue;
       
       // If this is a no-capture pointer argument, see if we can tell that it

Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=145013&r1=145012&r2=145013&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Sun Nov 20 13:09:04 2011
@@ -393,8 +393,7 @@
     // pointer were passed to arguments that were neither of these, then it
     // couldn't be no-capture.
     if (!(*CI)->getType()->isPointerTy() ||
-        (!CS.paramHasAttr(ArgNo+1, Attribute::NoCapture) &&
-         !CS.paramHasAttr(ArgNo+1, Attribute::ByVal)))
+        (!CS.doesNotCapture(ArgNo) && !CS.isByValArgument(ArgNo)))
       continue;
 
     // If this is a no-capture pointer argument, see if we can tell that it

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=145013&r1=145012&r2=145013&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Sun Nov 20 13:09:04 2011
@@ -760,7 +760,7 @@
   // The size of ByVal arguments is derived from the type, so we
   // can't change to a type with a different size.  If the size were
   // passed explicitly we could avoid this check.
-  if (!CS.paramHasAttr(ix, Attribute::ByVal))
+  if (!CS.isByValArgument(ix))
     return true;
 
   Type* SrcTy = 
@@ -960,7 +960,7 @@
   PointerType *PTy = cast<PointerType>(Callee->getType());
   FunctionType *FTy = cast<FunctionType>(PTy->getElementType());
   if (FTy->isVarArg()) {
-    int ix = FTy->getNumParams() + (isa<InvokeInst>(Callee) ? 3 : 1);
+    int ix = FTy->getNumParams() + (isa<InvokeInst>(Callee) ? 2 : 0);
     // See if we can optimize any arguments passed through the varargs area of
     // the call.
     for (CallSite::arg_iterator I = CS.arg_begin()+FTy->getNumParams(),

Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=145013&r1=145012&r2=145013&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Sun Nov 20 13:09:04 2011
@@ -950,7 +950,7 @@
         RepeatInstruction = processMemMove(M);
       else if (CallSite CS = (Value*)I) {
         for (unsigned i = 0, e = CS.arg_size(); i != e; ++i)
-          if (CS.paramHasAttr(i+1, Attribute::ByVal))
+          if (CS.isByValArgument(i))
             MadeChange |= processByValArgument(CS, i);
       }
 

Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=145013&r1=145012&r2=145013&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Sun Nov 20 13:09:04 2011
@@ -2534,13 +2534,12 @@
       // ignore it if we know that the value isn't captured.
       unsigned ArgNo = CS.getArgumentNo(UI);
       if (CS.onlyReadsMemory() &&
-          (CS.getInstruction()->use_empty() ||
-           CS.paramHasAttr(ArgNo+1, Attribute::NoCapture)))
+          (CS.getInstruction()->use_empty() || CS.doesNotCapture(ArgNo)))
         continue;
 
       // If this is being passed as a byval argument, the caller is making a
       // copy, so it is only a read of the alloca.
-      if (CS.paramHasAttr(ArgNo+1, Attribute::ByVal))
+      if (CS.isByValArgument(ArgNo))
         continue;
     }
 

Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=145013&r1=145012&r2=145013&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Sun Nov 20 13:09:04 2011
@@ -987,7 +987,7 @@
       // by them explicit.  However, we don't do this if the callee is readonly
       // or readnone, because the copy would be unneeded: the callee doesn't
       // modify the struct.
-      if (CalledFunc->paramHasAttr(ArgNo+1, Attribute::ByVal)) {
+      if (CS.isByValArgument(ArgNo)) {
         ActualArg = HandleByValArgument(ActualArg, TheCall, CalledFunc, IFI,
                                         CalledFunc->getParamAlignment(ArgNo+1));
  



From nicholas at mxc.ca  Sun Nov 20 13:37:06 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Sun, 20 Nov 2011 19:37:06 -0000
Subject: [llvm-commits] [llvm] r145014 - in /llvm/trunk:
 include/llvm/Analysis/CaptureTracking.h lib/Analysis/CaptureTracking.cpp
 lib/Analysis/MemoryDependenceAnalysis.cpp
Message-ID: <20111120193706.64D342A6C134@llvm.org>

Author: nicholas
Date: Sun Nov 20 13:37:06 2011
New Revision: 145014

URL: http://llvm.org/viewvc/llvm-project?rev=145014&view=rev
Log:
Less template, more virtual! Refactoring suggested by Chris in code review.

Modified:
    llvm/trunk/include/llvm/Analysis/CaptureTracking.h
    llvm/trunk/lib/Analysis/CaptureTracking.cpp
    llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp

Modified: llvm/trunk/include/llvm/Analysis/CaptureTracking.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CaptureTracking.h?rev=145014&r1=145013&r2=145014&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/CaptureTracking.h (original)
+++ llvm/trunk/include/llvm/Analysis/CaptureTracking.h Sun Nov 20 13:37:06 2011
@@ -33,132 +33,31 @@
                             bool ReturnCaptures,
                             bool StoreCaptures);
 
+  /// This callback is used in conjunction with PointerMayBeCaptured. In
+  /// addition to the interface here, you'll need to provide your own getters
+  /// to see whether anything was captured.
+  struct CaptureTracker {
+    /// tooManyUses - The depth of traversal has breached a limit. There may be
+    /// capturing instructions that will not be passed into captured().
+    virtual void tooManyUses() = 0;
+
+    /// shouldExplore - This is the use of a value derived from the pointer.
+    /// To prune the search (ie., assume that none of its users could possibly
+    /// capture) return false. To search it, return true.
+    ///
+    /// U->getUser() is always an Instruction.
+    virtual bool shouldExplore(Use *U) = 0;
+
+    /// captured - The instruction I captured the pointer. Return true to
+    /// stop the traversal or false to continue looking for more capturing
+    /// instructions.
+    virtual bool captured(Instruction *I) = 0;
+  };
+
   /// PointerMayBeCaptured - Visit the value and the values derived from it and
   /// find values which appear to be capturing the pointer value. This feeds
-  /// results into and is controlled by the templated CaptureTracker object:
-  ///
-  /// struct YourCaptureTracker {
-  ///   /// tooManyUses - The depth of traversal has breached a limit.
-  ///   /// The tracker should conservatively assume that the value is captured.
-  ///   void tooManyUses();
-  ///
-  ///   /// shouldExplore - This is the use of a value derived from the pointer.
-  ///   /// Return false to prune the search (ie., assume that none of its users
-  ///   /// could possibly capture) return false. To search it, return true.
-  ///   ///
-  ///   /// Also, U->getUser() is guaranteed to be an Instruction.
-  ///   bool shouldExplore(Use *U);
-  ///
-  ///   /// captured - The instruction I captured the pointer. Return true to
-  ///   /// stop the traversal or false to continue looking for more capturing
-  ///   /// instructions.
-  ///   bool captured(Instruction *I);
-  ///
-  ///   /// Provide your own getters for the state.
-  /// };
-  template<typename CaptureTracker>
-  void PointerMayBeCaptured(const Value *V, CaptureTracker &Tracker);
+  /// results into and is controlled by the CaptureTracker object.
+  void PointerMayBeCaptured(const Value *V, CaptureTracker *Tracker);
 } // end namespace llvm
 
-template<typename CaptureTracker>
-void llvm::PointerMayBeCaptured(const llvm::Value *V, CaptureTracker &Tracker) {
-  assert(V->getType()->isPointerTy() && "Capture is for pointers only!");
-  SmallVector<Use*, 20> Worklist;
-  SmallSet<Use*, 20> Visited;
-  int Count = 0;
-
-  for (Value::const_use_iterator UI = V->use_begin(), UE = V->use_end();
-       UI != UE; ++UI) {
-    // If there are lots of uses, conservatively say that the value
-    // is captured to avoid taking too much compile time.
-    if (Count++ >= 20)
-      return Tracker.tooManyUses();
-
-    Use *U = &UI.getUse();
-    if (!Tracker.shouldExplore(U)) continue;
-    Visited.insert(U);
-    Worklist.push_back(U);
-  }
-
-  while (!Worklist.empty()) {
-    Use *U = Worklist.pop_back_val();
-    Instruction *I = cast<Instruction>(U->getUser());
-    V = U->get();
-
-    switch (I->getOpcode()) {
-    case Instruction::Call:
-    case Instruction::Invoke: {
-      CallSite CS(I);
-      // Not captured if the callee is readonly, doesn't return a copy through
-      // its return value and doesn't unwind (a readonly function can leak bits
-      // by throwing an exception or not depending on the input value).
-      if (CS.onlyReadsMemory() && CS.doesNotThrow() && I->getType()->isVoidTy())
-        break;
-
-      // Not captured if only passed via 'nocapture' arguments.  Note that
-      // calling a function pointer does not in itself cause the pointer to
-      // be captured.  This is a subtle point considering that (for example)
-      // the callee might return its own address.  It is analogous to saying
-      // that loading a value from a pointer does not cause the pointer to be
-      // captured, even though the loaded value might be the pointer itself
-      // (think of self-referential objects).
-      CallSite::arg_iterator B = CS.arg_begin(), E = CS.arg_end();
-      for (CallSite::arg_iterator A = B; A != E; ++A)
-        if (A->get() == V && !CS.doesNotCapture(A - B))
-          // The parameter is not marked 'nocapture' - captured.
-          if (Tracker.captured(I))
-            return;
-      break;
-    }
-    case Instruction::Load:
-      // Loading from a pointer does not cause it to be captured.
-      break;
-    case Instruction::VAArg:
-      // "va-arg" from a pointer does not cause it to be captured.
-      break;
-    case Instruction::Store:
-      if (V == I->getOperand(0))
-        // Stored the pointer - conservatively assume it may be captured.
-        if (Tracker.captured(I))
-          return;
-      // Storing to the pointee does not cause the pointer to be captured.
-      break;
-    case Instruction::BitCast:
-    case Instruction::GetElementPtr:
-    case Instruction::PHI:
-    case Instruction::Select:
-      // The original value is not captured via this if the new value isn't.
-      for (Instruction::use_iterator UI = I->use_begin(), UE = I->use_end();
-           UI != UE; ++UI) {
-        Use *U = &UI.getUse();
-        if (Visited.insert(U))
-          if (Tracker.shouldExplore(U))
-            Worklist.push_back(U);
-      }
-      break;
-    case Instruction::ICmp:
-      // Don't count comparisons of a no-alias return value against null as
-      // captures. This allows us to ignore comparisons of malloc results
-      // with null, for example.
-      if (isNoAliasCall(V->stripPointerCasts()))
-        if (ConstantPointerNull *CPN =
-              dyn_cast<ConstantPointerNull>(I->getOperand(1)))
-          if (CPN->getType()->getAddressSpace() == 0)
-            break;
-      // Otherwise, be conservative. There are crazy ways to capture pointers
-      // using comparisons.
-      if (Tracker.captured(I))
-        return;
-      break;
-    default:
-      // Something else - be conservative and say it is captured.
-      if (Tracker.captured(I))
-        return;
-      break;
-    }
-  }
-
-  // All uses examined.
-}
-
 #endif

Modified: llvm/trunk/lib/Analysis/CaptureTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CaptureTracking.cpp?rev=145014&r1=145013&r2=145014&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/CaptureTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/CaptureTracking.cpp Sun Nov 20 13:37:06 2011
@@ -20,7 +20,7 @@
 using namespace llvm;
 
 namespace {
-  struct SimpleCaptureTracker {
+  struct SimpleCaptureTracker : public CaptureTracker {
     explicit SimpleCaptureTracker(bool ReturnCaptures)
       : ReturnCaptures(ReturnCaptures), Captured(false) {}
 
@@ -58,6 +58,111 @@
   (void)StoreCaptures;
 
   SimpleCaptureTracker SCT(ReturnCaptures);
-  PointerMayBeCaptured(V, SCT);
+  PointerMayBeCaptured(V, &SCT);
   return SCT.Captured;
 }
+
+/// TODO: Write a new FunctionPass AliasAnalysis so that it can keep
+/// a cache. Then we can move the code from BasicAliasAnalysis into
+/// that path, and remove this threshold.
+static int const Threshold = 20;
+
+void llvm::PointerMayBeCaptured(const Value *V, CaptureTracker *Tracker) {
+  assert(V->getType()->isPointerTy() && "Capture is for pointers only!");
+  SmallVector<Use*, Threshold> Worklist;
+  SmallSet<Use*, Threshold> Visited;
+  int Count = 0;
+
+  for (Value::const_use_iterator UI = V->use_begin(), UE = V->use_end();
+       UI != UE; ++UI) {
+    // If there are lots of uses, conservatively say that the value
+    // is captured to avoid taking too much compile time.
+    if (Count++ >= Threshold)
+      return Tracker->tooManyUses();
+
+    Use *U = &UI.getUse();
+    if (!Tracker->shouldExplore(U)) continue;
+    Visited.insert(U);
+    Worklist.push_back(U);
+  }
+
+  while (!Worklist.empty()) {
+    Use *U = Worklist.pop_back_val();
+    Instruction *I = cast<Instruction>(U->getUser());
+    V = U->get();
+
+    switch (I->getOpcode()) {
+    case Instruction::Call:
+    case Instruction::Invoke: {
+      CallSite CS(I);
+      // Not captured if the callee is readonly, doesn't return a copy through
+      // its return value and doesn't unwind (a readonly function can leak bits
+      // by throwing an exception or not depending on the input value).
+      if (CS.onlyReadsMemory() && CS.doesNotThrow() && I->getType()->isVoidTy())
+        break;
+
+      // Not captured if only passed via 'nocapture' arguments.  Note that
+      // calling a function pointer does not in itself cause the pointer to
+      // be captured.  This is a subtle point considering that (for example)
+      // the callee might return its own address.  It is analogous to saying
+      // that loading a value from a pointer does not cause the pointer to be
+      // captured, even though the loaded value might be the pointer itself
+      // (think of self-referential objects).
+      CallSite::arg_iterator B = CS.arg_begin(), E = CS.arg_end();
+      for (CallSite::arg_iterator A = B; A != E; ++A)
+        if (A->get() == V && !CS.doesNotCapture(A - B))
+          // The parameter is not marked 'nocapture' - captured.
+          if (Tracker->captured(I))
+            return;
+      break;
+    }
+    case Instruction::Load:
+      // Loading from a pointer does not cause it to be captured.
+      break;
+    case Instruction::VAArg:
+      // "va-arg" from a pointer does not cause it to be captured.
+      break;
+    case Instruction::Store:
+      if (V == I->getOperand(0))
+        // Stored the pointer - conservatively assume it may be captured.
+        if (Tracker->captured(I))
+          return;
+      // Storing to the pointee does not cause the pointer to be captured.
+      break;
+    case Instruction::BitCast:
+    case Instruction::GetElementPtr:
+    case Instruction::PHI:
+    case Instruction::Select:
+      // The original value is not captured via this if the new value isn't.
+      for (Instruction::use_iterator UI = I->use_begin(), UE = I->use_end();
+           UI != UE; ++UI) {
+        Use *U = &UI.getUse();
+        if (Visited.insert(U))
+          if (Tracker->shouldExplore(U))
+            Worklist.push_back(U);
+      }
+      break;
+    case Instruction::ICmp:
+      // Don't count comparisons of a no-alias return value against null as
+      // captures. This allows us to ignore comparisons of malloc results
+      // with null, for example.
+      if (isNoAliasCall(V->stripPointerCasts()))
+        if (ConstantPointerNull *CPN =
+              dyn_cast<ConstantPointerNull>(I->getOperand(1)))
+          if (CPN->getType()->getAddressSpace() == 0)
+            break;
+      // Otherwise, be conservative. There are crazy ways to capture pointers
+      // using comparisons.
+      if (Tracker->captured(I))
+        return;
+      break;
+    default:
+      // Something else - be conservative and say it is captured.
+      if (Tracker->captured(I))
+        return;
+      break;
+    }
+  }
+
+  // All uses examined.
+}

Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=145014&r1=145013&r2=145014&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Sun Nov 20 13:37:06 2011
@@ -336,7 +336,7 @@
 namespace {
   /// Only find pointer captures which happen before the given instruction. Uses
   /// the dominator tree to determine whether one instruction is before another.
-  struct CapturesBefore {
+  struct CapturesBefore : public CaptureTracker {
     CapturesBefore(const Instruction *I, DominatorTree *DT)
       : BeforeHere(I), DT(DT), Captured(false) {}
 
@@ -381,7 +381,7 @@
   if (!CS.getInstruction()) return AliasAnalysis::ModRef;
 
   CapturesBefore CB(Inst, DT);
-  llvm::PointerMayBeCaptured(Object, CB);
+  llvm::PointerMayBeCaptured(Object, &CB);
 
   if (isa<Constant>(Object) || CS.getInstruction() == Object || CB.Captured)
     return AliasAnalysis::ModRef;



From craig.topper at gmail.com  Sun Nov 20 19:12:36 2011
From: craig.topper at gmail.com (Craig Topper)
Date: Mon, 21 Nov 2011 01:12:36 -0000
Subject: [llvm-commits] [llvm] r145022 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-shift.ll
 test/CodeGen/X86/avx2-shift.ll
Message-ID: <20111121011236.762A62A6C134@llvm.org>

Author: ctopper
Date: Sun Nov 20 19:12:36 2011
New Revision: 145022

URL: http://llvm.org/viewvc/llvm-project?rev=145022&view=rev
Log:
Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/avx-shift.ll
    llvm/trunk/test/CodeGen/X86/avx2-shift.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=145022&r1=145021&r2=145022&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Nov 20 19:12:36 2011
@@ -10571,9 +10571,9 @@
 
 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
   DebugLoc dl = Op.getDebugLoc();
-  SDNode* Node = Op.getNode();
-  EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
-  EVT VT = Node->getValueType(0);
+  EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+  EVT VT = Op.getValueType();
+
   if (Subtarget->hasXMMInt() && VT.isVector()) {
     unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
                         ExtraVT.getScalarType().getSizeInBits();
@@ -10584,21 +10584,55 @@
     switch (VT.getSimpleVT().SimpleTy) {
       default:
         return SDValue();
-      case MVT::v4i32: {
+      case MVT::v4i32:
         SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
         SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
         break;
-      }
-      case MVT::v8i16: {
+      case MVT::v8i16:
         SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
         SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
         break;
-      }
+      case MVT::v8i32:
+      case MVT::v16i16:
+        if (!Subtarget->hasAVX())
+          return SDValue();
+        if (!Subtarget->hasAVX2()) {
+          // needs to be split
+          int NumElems = VT.getVectorNumElements();
+          SDValue Idx0 = DAG.getConstant(0, MVT::i32);
+          SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
+
+          // Extract the LHS vectors
+          SDValue LHS = Op.getOperand(0);
+          SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
+          SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
+
+          MVT EltVT = VT.getVectorElementType().getSimpleVT();
+          EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
+
+          EVT ExtraEltVT = ExtraVT.getVectorElementType();
+          int ExtraNumElems = ExtraVT.getVectorNumElements();
+          ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
+                                     ExtraNumElems/2);
+          SDValue Extra = DAG.getValueType(ExtraVT);
+
+          LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
+          LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
+
+          return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
+        }
+        if (VT == MVT::v8i32) {
+          SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d;
+          SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d;
+        } else {
+          SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w;
+          SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w;
+        }
     }
 
     SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
                          DAG.getConstant(SHLIntrinsicsID, MVT::i32),
-                         Node->getOperand(0), ShAmt);
+                         Op.getOperand(0), ShAmt);
 
     return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
                        DAG.getConstant(SRAIntrinsicsID, MVT::i32),

Modified: llvm/trunk/test/CodeGen/X86/avx-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-shift.ll?rev=145022&r1=145021&r2=145022&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-shift.ll Sun Nov 20 19:12:36 2011
@@ -112,3 +112,27 @@
   ret <8 x i32> %bitop
 }
 
+;;; Uses shifts for sign extension
+; CHECK: _sext_v16i16
+; CHECK: vpsllw
+; CHECK: vpsraw
+; CHECK: vpsllw
+; CHECK: vpsraw
+; CHECK: vinsertf128
+define <16 x i16> @sext_v16i16(<16 x i16> %a) nounwind {
+  %b = trunc <16 x i16> %a to <16 x i8>
+  %c = sext <16 x i8> %b to <16 x i16>
+  ret <16 x i16> %c
+}
+
+; CHECK: _sext_v8i32
+; CHECK: vpslld
+; CHECK: vpsrad
+; CHECK: vpslld
+; CHECK: vpsrad
+; CHECK: vinsertf128
+define <8 x i32> @sext_v8i32(<8 x i32> %a) nounwind {
+  %b = trunc <8 x i32> %a to <8 x i16>
+  %c = sext <8 x i16> %b to <8 x i32>
+  ret <8 x i32> %c
+}

Modified: llvm/trunk/test/CodeGen/X86/avx2-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-shift.ll?rev=145022&r1=145021&r2=145022&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-shift.ll Sun Nov 20 19:12:36 2011
@@ -246,3 +246,23 @@
 ; CHECK: vpsubb
 ; CHECK: ret
 }
+
+; CHECK: _sext_v16i16
+; CHECK: vpsllw
+; CHECK: vpsraw
+; CHECK-NOT: vinsertf128
+define <16 x i16> @sext_v16i16(<16 x i16> %a) nounwind {
+  %b = trunc <16 x i16> %a to <16 x i8>
+  %c = sext <16 x i8> %b to <16 x i16>
+  ret <16 x i16> %c
+}
+
+; CHECK: _sext_v8i32
+; CHECK: vpslld
+; CHECK: vpsrad
+; CHECK-NOT: vinsertf128
+define <8 x i32> @sext_v8i32(<8 x i32> %a) nounwind {
+  %b = trunc <8 x i32> %a to <8 x i16>
+  %c = sext <8 x i16> %b to <8 x i32>
+  ret <8 x i32> %c
+}



From jabbey at arxan.com  Sun Nov 20 22:42:21 2011
From: jabbey at arxan.com (Joe Abbey)
Date: Mon, 21 Nov 2011 04:42:21 -0000
Subject: [llvm-commits] [llvm] r145025 - /llvm/trunk/lib/VMCore/Pass.cpp
Message-ID: <20111121044221.ACD0C2A6C134@llvm.org>

Author: jabbey
Date: Sun Nov 20 22:42:21 2011
New Revision: 145025

URL: http://llvm.org/viewvc/llvm-project?rev=145025&view=rev
Log:
Fixing a comment


Modified:
    llvm/trunk/lib/VMCore/Pass.cpp

Modified: llvm/trunk/lib/VMCore/Pass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Pass.cpp?rev=145025&r1=145024&r2=145025&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Pass.cpp (original)
+++ llvm/trunk/lib/VMCore/Pass.cpp Sun Nov 20 22:42:21 2011
@@ -48,7 +48,7 @@
   return Resolver->getAnalysisIfAvailable(&AID, true) != 0;
 }
 
-// dumpPassStructure - Implement the -debug-passes=Structure option
+// dumpPassStructure - Implement the -debug-pass=Structure option
 void Pass::dumpPassStructure(unsigned Offset) {
   dbgs().indent(Offset*2) << getPassName() << "\n";
 }